]>
Commit | Line | Data |
---|---|---|
996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
d24652ee GK |
2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | ;; 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. | |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 | 5 | |
5de601cf | 6 | ;; This file is part of GCC. |
1fd4e8c1 | 7 | |
5de601cf NC |
8 | ;; GCC is free software; you can redistribute it and/or modify it |
9 | ;; under the terms of the GNU General Public License as published | |
10 | ;; by the Free Software Foundation; either version 2, or (at your | |
11 | ;; option) any later version. | |
1fd4e8c1 | 12 | |
5de601cf NC |
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | ;; License for more details. | |
1fd4e8c1 RK |
17 | |
18 | ;; You should have received a copy of the GNU General Public License | |
5de601cf NC |
19 | ;; along with GCC; see the file COPYING. If not, write to the |
20 | ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | ;; MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d | 24 | |
615158e2 JJ |
25 | ;; |
26 | ;; UNSPEC usage | |
27 | ;; | |
28 | ||
29 | (define_constants | |
30 | [(UNSPEC_FRSP 0) ; frsp for POWER machines | |
31 | (UNSPEC_TIE 5) ; tie stack contents and stack pointer | |
32 | (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC | |
33 | (UNSPEC_TOC 7) ; address of the TOC (more-or-less) | |
34 | (UNSPEC_MOVSI_GOT 8) | |
35 | (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit | |
36 | (UNSPEC_FCTIWZ 10) | |
37 | (UNSPEC_LD_MPIC 15) ; load_macho_picbase | |
38 | (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic | |
39 | (UNSPEC_TLSGD 17) | |
40 | (UNSPEC_TLSLD 18) | |
41 | (UNSPEC_MOVESI_FROM_CR 19) | |
42 | (UNSPEC_MOVESI_TO_CR 20) | |
43 | (UNSPEC_TLSDTPREL 21) | |
44 | (UNSPEC_TLSDTPRELHA 22) | |
45 | (UNSPEC_TLSDTPRELLO 23) | |
46 | (UNSPEC_TLSGOTDTPREL 24) | |
47 | (UNSPEC_TLSTPREL 25) | |
48 | (UNSPEC_TLSTPRELHA 26) | |
49 | (UNSPEC_TLSTPRELLO 27) | |
50 | (UNSPEC_TLSGOTTPREL 28) | |
51 | (UNSPEC_TLSTLS 29) | |
52 | ]) | |
53 | ||
54 | ;; | |
55 | ;; UNSPEC_VOLATILE usage | |
56 | ;; | |
57 | ||
58 | (define_constants | |
59 | [(UNSPECV_BLOCK 0) | |
60 | (UNSPECV_EH_RR 9) ; eh_reg_restore | |
61 | ]) | |
1fd4e8c1 RK |
62 | \f |
63 | ;; Define an insn type attribute. This is used in function unit delay | |
64 | ;; computations. | |
9259f3b0 | 65 | (define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mtcr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv" |
1fd4e8c1 RK |
66 | (const_string "integer")) |
67 | ||
b19003d8 | 68 | ;; Length (in bytes). |
6cbadf36 GK |
69 | ; '(pc)' in the following doesn't include the instruction itself; it is |
70 | ; calculated as if the instruction had zero size. | |
b19003d8 RK |
71 | (define_attr "length" "" |
72 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 73 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 74 | (const_int -32768)) |
6cbadf36 GK |
75 | (lt (minus (match_dup 0) (pc)) |
76 | (const_int 32764))) | |
39a10a29 GK |
77 | (const_int 4) |
78 | (const_int 8)) | |
b19003d8 RK |
79 | (const_int 4))) |
80 | ||
cfb557c4 RK |
81 | ;; Processor type -- this attribute must exactly match the processor_type |
82 | ;; enumeration in rs6000.h. | |
83 | ||
b54cf83a | 84 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4" |
cfb557c4 RK |
85 | (const (symbol_ref "rs6000_cpu_attr"))) |
86 | ||
b54cf83a DE |
87 | (automata_option "ndfa") |
88 | ||
89 | (include "rios1.md") | |
90 | (include "rios2.md") | |
91 | (include "rs64.md") | |
92 | (include "mpc.md") | |
93 | (include "40x.md") | |
94 | (include "603.md") | |
95 | (include "6xx.md") | |
96 | (include "7xx.md") | |
97 | (include "7450.md") | |
5e8006fa | 98 | (include "8540.md") |
b54cf83a | 99 | (include "power4.md") |
309323c2 | 100 | |
1fd4e8c1 RK |
101 | \f |
102 | ;; Start with fixed-point load and store insns. Here we put only the more | |
103 | ;; complex forms. Basic data transfer is done later. | |
104 | ||
51b8fc2c RK |
105 | (define_expand "zero_extendqidi2" |
106 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
107 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
108 | "TARGET_POWERPC64" | |
109 | "") | |
110 | ||
111 | (define_insn "" | |
112 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
113 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
114 | "TARGET_POWERPC64" | |
115 | "@ | |
116 | lbz%U1%X1 %0,%1 | |
4371f8af | 117 | rldicl %0,%1,0,56" |
51b8fc2c RK |
118 | [(set_attr "type" "load,*")]) |
119 | ||
120 | (define_insn "" | |
9ebbca7d GK |
121 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
122 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 123 | (const_int 0))) |
9ebbca7d | 124 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 125 | "TARGET_POWERPC64" |
9ebbca7d GK |
126 | "@ |
127 | rldicl. %2,%1,0,56 | |
128 | #" | |
129 | [(set_attr "type" "compare") | |
130 | (set_attr "length" "4,8")]) | |
131 | ||
132 | (define_split | |
133 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
134 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
135 | (const_int 0))) | |
136 | (clobber (match_scratch:DI 2 ""))] | |
137 | "TARGET_POWERPC64 && reload_completed" | |
138 | [(set (match_dup 2) | |
139 | (zero_extend:DI (match_dup 1))) | |
140 | (set (match_dup 0) | |
141 | (compare:CC (match_dup 2) | |
142 | (const_int 0)))] | |
143 | "") | |
51b8fc2c RK |
144 | |
145 | (define_insn "" | |
9ebbca7d GK |
146 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
147 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 148 | (const_int 0))) |
9ebbca7d | 149 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 150 | (zero_extend:DI (match_dup 1)))] |
58e09803 | 151 | "TARGET_POWERPC64" |
9ebbca7d GK |
152 | "@ |
153 | rldicl. %0,%1,0,56 | |
154 | #" | |
155 | [(set_attr "type" "compare") | |
156 | (set_attr "length" "4,8")]) | |
157 | ||
158 | (define_split | |
159 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
160 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
161 | (const_int 0))) | |
162 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
163 | (zero_extend:DI (match_dup 1)))] | |
164 | "TARGET_POWERPC64 && reload_completed" | |
165 | [(set (match_dup 0) | |
166 | (zero_extend:DI (match_dup 1))) | |
167 | (set (match_dup 2) | |
168 | (compare:CC (match_dup 0) | |
169 | (const_int 0)))] | |
170 | "") | |
51b8fc2c | 171 | |
2bee0449 RK |
172 | (define_insn "extendqidi2" |
173 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
174 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 175 | "TARGET_POWERPC64" |
2bee0449 | 176 | "extsb %0,%1") |
51b8fc2c RK |
177 | |
178 | (define_insn "" | |
9ebbca7d GK |
179 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
180 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 181 | (const_int 0))) |
9ebbca7d | 182 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 183 | "TARGET_POWERPC64" |
9ebbca7d GK |
184 | "@ |
185 | extsb. %2,%1 | |
186 | #" | |
187 | [(set_attr "type" "compare") | |
188 | (set_attr "length" "4,8")]) | |
189 | ||
190 | (define_split | |
191 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
192 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
193 | (const_int 0))) | |
194 | (clobber (match_scratch:DI 2 ""))] | |
195 | "TARGET_POWERPC64 && reload_completed" | |
196 | [(set (match_dup 2) | |
197 | (sign_extend:DI (match_dup 1))) | |
198 | (set (match_dup 0) | |
199 | (compare:CC (match_dup 2) | |
200 | (const_int 0)))] | |
201 | "") | |
51b8fc2c RK |
202 | |
203 | (define_insn "" | |
9ebbca7d GK |
204 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
205 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 206 | (const_int 0))) |
9ebbca7d | 207 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
208 | (sign_extend:DI (match_dup 1)))] |
209 | "TARGET_POWERPC64" | |
9ebbca7d GK |
210 | "@ |
211 | extsb. %0,%1 | |
212 | #" | |
213 | [(set_attr "type" "compare") | |
214 | (set_attr "length" "4,8")]) | |
215 | ||
216 | (define_split | |
217 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
218 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
219 | (const_int 0))) | |
220 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
221 | (sign_extend:DI (match_dup 1)))] | |
222 | "TARGET_POWERPC64 && reload_completed" | |
223 | [(set (match_dup 0) | |
224 | (sign_extend:DI (match_dup 1))) | |
225 | (set (match_dup 2) | |
226 | (compare:CC (match_dup 0) | |
227 | (const_int 0)))] | |
228 | "") | |
51b8fc2c RK |
229 | |
230 | (define_expand "zero_extendhidi2" | |
231 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
232 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
233 | "TARGET_POWERPC64" | |
234 | "") | |
235 | ||
236 | (define_insn "" | |
237 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
238 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
239 | "TARGET_POWERPC64" | |
240 | "@ | |
241 | lhz%U1%X1 %0,%1 | |
4371f8af | 242 | rldicl %0,%1,0,48" |
51b8fc2c RK |
243 | [(set_attr "type" "load,*")]) |
244 | ||
245 | (define_insn "" | |
9ebbca7d GK |
246 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
247 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 248 | (const_int 0))) |
9ebbca7d | 249 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 250 | "TARGET_POWERPC64" |
9ebbca7d GK |
251 | "@ |
252 | rldicl. %2,%1,0,48 | |
253 | #" | |
254 | [(set_attr "type" "compare") | |
255 | (set_attr "length" "4,8")]) | |
256 | ||
257 | (define_split | |
258 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
259 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
260 | (const_int 0))) | |
261 | (clobber (match_scratch:DI 2 ""))] | |
262 | "TARGET_POWERPC64 && reload_completed" | |
263 | [(set (match_dup 2) | |
264 | (zero_extend:DI (match_dup 1))) | |
265 | (set (match_dup 0) | |
266 | (compare:CC (match_dup 2) | |
267 | (const_int 0)))] | |
268 | "") | |
51b8fc2c RK |
269 | |
270 | (define_insn "" | |
9ebbca7d GK |
271 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
272 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 273 | (const_int 0))) |
9ebbca7d | 274 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
275 | (zero_extend:DI (match_dup 1)))] |
276 | "TARGET_POWERPC64" | |
9ebbca7d GK |
277 | "@ |
278 | rldicl. %0,%1,0,48 | |
279 | #" | |
280 | [(set_attr "type" "compare") | |
281 | (set_attr "length" "4,8")]) | |
282 | ||
283 | (define_split | |
284 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
285 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
286 | (const_int 0))) | |
287 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
288 | (zero_extend:DI (match_dup 1)))] | |
289 | "TARGET_POWERPC64 && reload_completed" | |
290 | [(set (match_dup 0) | |
291 | (zero_extend:DI (match_dup 1))) | |
292 | (set (match_dup 2) | |
293 | (compare:CC (match_dup 0) | |
294 | (const_int 0)))] | |
295 | "") | |
51b8fc2c RK |
296 | |
297 | (define_expand "extendhidi2" | |
298 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
299 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
300 | "TARGET_POWERPC64" | |
301 | "") | |
302 | ||
303 | (define_insn "" | |
304 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
305 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
306 | "TARGET_POWERPC64" | |
307 | "@ | |
308 | lha%U1%X1 %0,%1 | |
309 | extsh %0,%1" | |
b54cf83a | 310 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
311 | |
312 | (define_insn "" | |
9ebbca7d GK |
313 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
314 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 315 | (const_int 0))) |
9ebbca7d | 316 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 317 | "TARGET_POWERPC64" |
9ebbca7d GK |
318 | "@ |
319 | extsh. %2,%1 | |
320 | #" | |
321 | [(set_attr "type" "compare") | |
322 | (set_attr "length" "4,8")]) | |
323 | ||
324 | (define_split | |
325 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
326 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
327 | (const_int 0))) | |
328 | (clobber (match_scratch:DI 2 ""))] | |
329 | "TARGET_POWERPC64 && reload_completed" | |
330 | [(set (match_dup 2) | |
331 | (sign_extend:DI (match_dup 1))) | |
332 | (set (match_dup 0) | |
333 | (compare:CC (match_dup 2) | |
334 | (const_int 0)))] | |
335 | "") | |
51b8fc2c RK |
336 | |
337 | (define_insn "" | |
9ebbca7d GK |
338 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
339 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 340 | (const_int 0))) |
9ebbca7d | 341 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
342 | (sign_extend:DI (match_dup 1)))] |
343 | "TARGET_POWERPC64" | |
9ebbca7d GK |
344 | "@ |
345 | extsh. %0,%1 | |
346 | #" | |
347 | [(set_attr "type" "compare") | |
348 | (set_attr "length" "4,8")]) | |
349 | ||
350 | (define_split | |
351 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
352 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
353 | (const_int 0))) | |
354 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
355 | (sign_extend:DI (match_dup 1)))] | |
356 | "TARGET_POWERPC64 && reload_completed" | |
357 | [(set (match_dup 0) | |
358 | (sign_extend:DI (match_dup 1))) | |
359 | (set (match_dup 2) | |
360 | (compare:CC (match_dup 0) | |
361 | (const_int 0)))] | |
362 | "") | |
51b8fc2c RK |
363 | |
364 | (define_expand "zero_extendsidi2" | |
365 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
366 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
367 | "TARGET_POWERPC64" | |
368 | "") | |
369 | ||
370 | (define_insn "" | |
371 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
372 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
373 | "TARGET_POWERPC64" | |
374 | "@ | |
375 | lwz%U1%X1 %0,%1 | |
376 | rldicl %0,%1,0,32" | |
377 | [(set_attr "type" "load,*")]) | |
378 | ||
379 | (define_insn "" | |
9ebbca7d GK |
380 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
381 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 382 | (const_int 0))) |
9ebbca7d | 383 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 384 | "TARGET_POWERPC64" |
9ebbca7d GK |
385 | "@ |
386 | rldicl. %2,%1,0,32 | |
387 | #" | |
388 | [(set_attr "type" "compare") | |
389 | (set_attr "length" "4,8")]) | |
390 | ||
391 | (define_split | |
392 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
393 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
394 | (const_int 0))) | |
395 | (clobber (match_scratch:DI 2 ""))] | |
396 | "TARGET_POWERPC64 && reload_completed" | |
397 | [(set (match_dup 2) | |
398 | (zero_extend:DI (match_dup 1))) | |
399 | (set (match_dup 0) | |
400 | (compare:CC (match_dup 2) | |
401 | (const_int 0)))] | |
402 | "") | |
51b8fc2c RK |
403 | |
404 | (define_insn "" | |
9ebbca7d GK |
405 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
406 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 407 | (const_int 0))) |
9ebbca7d | 408 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
409 | (zero_extend:DI (match_dup 1)))] |
410 | "TARGET_POWERPC64" | |
9ebbca7d GK |
411 | "@ |
412 | rldicl. %0,%1,0,32 | |
413 | #" | |
414 | [(set_attr "type" "compare") | |
415 | (set_attr "length" "4,8")]) | |
416 | ||
417 | (define_split | |
418 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
419 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
420 | (const_int 0))) | |
421 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
422 | (zero_extend:DI (match_dup 1)))] | |
423 | "TARGET_POWERPC64 && reload_completed" | |
424 | [(set (match_dup 0) | |
425 | (zero_extend:DI (match_dup 1))) | |
426 | (set (match_dup 2) | |
427 | (compare:CC (match_dup 0) | |
428 | (const_int 0)))] | |
429 | "") | |
51b8fc2c RK |
430 | |
431 | (define_expand "extendsidi2" | |
432 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
433 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
434 | "TARGET_POWERPC64" | |
435 | "") | |
436 | ||
437 | (define_insn "" | |
438 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 439 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
440 | "TARGET_POWERPC64" |
441 | "@ | |
442 | lwa%U1%X1 %0,%1 | |
443 | extsw %0,%1" | |
b54cf83a | 444 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
445 | |
446 | (define_insn "" | |
9ebbca7d GK |
447 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
448 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 449 | (const_int 0))) |
9ebbca7d | 450 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 451 | "TARGET_POWERPC64" |
9ebbca7d GK |
452 | "@ |
453 | extsw. %2,%1 | |
454 | #" | |
455 | [(set_attr "type" "compare") | |
456 | (set_attr "length" "4,8")]) | |
457 | ||
458 | (define_split | |
459 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
460 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
461 | (const_int 0))) | |
462 | (clobber (match_scratch:DI 2 ""))] | |
463 | "TARGET_POWERPC64 && reload_completed" | |
464 | [(set (match_dup 2) | |
465 | (sign_extend:DI (match_dup 1))) | |
466 | (set (match_dup 0) | |
467 | (compare:CC (match_dup 2) | |
468 | (const_int 0)))] | |
469 | "") | |
51b8fc2c RK |
470 | |
471 | (define_insn "" | |
9ebbca7d GK |
472 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
473 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 474 | (const_int 0))) |
9ebbca7d | 475 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
476 | (sign_extend:DI (match_dup 1)))] |
477 | "TARGET_POWERPC64" | |
9ebbca7d GK |
478 | "@ |
479 | extsw. %0,%1 | |
480 | #" | |
481 | [(set_attr "type" "compare") | |
482 | (set_attr "length" "4,8")]) | |
483 | ||
484 | (define_split | |
485 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
486 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
487 | (const_int 0))) | |
488 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
489 | (sign_extend:DI (match_dup 1)))] | |
490 | "TARGET_POWERPC64 && reload_completed" | |
491 | [(set (match_dup 0) | |
492 | (sign_extend:DI (match_dup 1))) | |
493 | (set (match_dup 2) | |
494 | (compare:CC (match_dup 0) | |
495 | (const_int 0)))] | |
496 | "") | |
51b8fc2c | 497 | |
1fd4e8c1 | 498 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
499 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
500 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
501 | "" |
502 | "") | |
503 | ||
504 | (define_insn "" | |
cd2b37d9 | 505 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
506 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
507 | "" | |
508 | "@ | |
509 | lbz%U1%X1 %0,%1 | |
005a35b9 | 510 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
511 | [(set_attr "type" "load,*")]) |
512 | ||
513 | (define_insn "" | |
9ebbca7d GK |
514 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
515 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 516 | (const_int 0))) |
9ebbca7d | 517 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 518 | "" |
9ebbca7d GK |
519 | "@ |
520 | {andil.|andi.} %2,%1,0xff | |
521 | #" | |
522 | [(set_attr "type" "compare") | |
523 | (set_attr "length" "4,8")]) | |
524 | ||
525 | (define_split | |
526 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
527 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
528 | (const_int 0))) | |
529 | (clobber (match_scratch:SI 2 ""))] | |
530 | "reload_completed" | |
531 | [(set (match_dup 2) | |
532 | (zero_extend:SI (match_dup 1))) | |
533 | (set (match_dup 0) | |
534 | (compare:CC (match_dup 2) | |
535 | (const_int 0)))] | |
536 | "") | |
1fd4e8c1 RK |
537 | |
538 | (define_insn "" | |
9ebbca7d GK |
539 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
540 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 541 | (const_int 0))) |
9ebbca7d | 542 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
543 | (zero_extend:SI (match_dup 1)))] |
544 | "" | |
9ebbca7d GK |
545 | "@ |
546 | {andil.|andi.} %0,%1,0xff | |
547 | #" | |
548 | [(set_attr "type" "compare") | |
549 | (set_attr "length" "4,8")]) | |
550 | ||
551 | (define_split | |
552 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
553 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
554 | (const_int 0))) | |
555 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
556 | (zero_extend:SI (match_dup 1)))] | |
557 | "reload_completed" | |
558 | [(set (match_dup 0) | |
559 | (zero_extend:SI (match_dup 1))) | |
560 | (set (match_dup 2) | |
561 | (compare:CC (match_dup 0) | |
562 | (const_int 0)))] | |
563 | "") | |
1fd4e8c1 | 564 | |
51b8fc2c RK |
565 | (define_expand "extendqisi2" |
566 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
567 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
568 | "" | |
569 | " | |
570 | { | |
571 | if (TARGET_POWERPC) | |
572 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
573 | else if (TARGET_POWER) | |
574 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
575 | else | |
576 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
577 | DONE; | |
578 | }") | |
579 | ||
580 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
581 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
582 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 583 | "TARGET_POWERPC" |
2bee0449 | 584 | "extsb %0,%1") |
51b8fc2c RK |
585 | |
586 | (define_insn "" | |
9ebbca7d GK |
587 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
588 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 589 | (const_int 0))) |
9ebbca7d | 590 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 591 | "TARGET_POWERPC" |
9ebbca7d GK |
592 | "@ |
593 | extsb. %2,%1 | |
594 | #" | |
595 | [(set_attr "type" "compare") | |
596 | (set_attr "length" "4,8")]) | |
597 | ||
598 | (define_split | |
599 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
600 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
601 | (const_int 0))) | |
602 | (clobber (match_scratch:SI 2 ""))] | |
603 | "TARGET_POWERPC && reload_completed" | |
604 | [(set (match_dup 2) | |
605 | (sign_extend:SI (match_dup 1))) | |
606 | (set (match_dup 0) | |
607 | (compare:CC (match_dup 2) | |
608 | (const_int 0)))] | |
609 | "") | |
51b8fc2c RK |
610 | |
611 | (define_insn "" | |
9ebbca7d GK |
612 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
613 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 614 | (const_int 0))) |
9ebbca7d | 615 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
616 | (sign_extend:SI (match_dup 1)))] |
617 | "TARGET_POWERPC" | |
9ebbca7d GK |
618 | "@ |
619 | extsb. %0,%1 | |
620 | #" | |
621 | [(set_attr "type" "compare") | |
622 | (set_attr "length" "4,8")]) | |
623 | ||
624 | (define_split | |
625 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
626 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
627 | (const_int 0))) | |
628 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
629 | (sign_extend:SI (match_dup 1)))] | |
630 | "TARGET_POWERPC && reload_completed" | |
631 | [(set (match_dup 0) | |
632 | (sign_extend:SI (match_dup 1))) | |
633 | (set (match_dup 2) | |
634 | (compare:CC (match_dup 0) | |
635 | (const_int 0)))] | |
636 | "") | |
51b8fc2c RK |
637 | |
638 | (define_expand "extendqisi2_power" | |
639 | [(parallel [(set (match_dup 2) | |
640 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
641 | (const_int 24))) | |
642 | (clobber (scratch:SI))]) | |
643 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
644 | (ashiftrt:SI (match_dup 2) | |
645 | (const_int 24))) | |
646 | (clobber (scratch:SI))])] | |
647 | "TARGET_POWER" | |
648 | " | |
649 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
650 | operands[2] = gen_reg_rtx (SImode); }") | |
651 | ||
652 | (define_expand "extendqisi2_no_power" | |
653 | [(set (match_dup 2) | |
654 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
655 | (const_int 24))) | |
656 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
657 | (ashiftrt:SI (match_dup 2) | |
658 | (const_int 24)))] | |
659 | "! TARGET_POWER && ! TARGET_POWERPC" | |
660 | " | |
661 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
662 | operands[2] = gen_reg_rtx (SImode); }") | |
663 | ||
1fd4e8c1 | 664 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
665 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
666 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
667 | "" |
668 | "") | |
669 | ||
670 | (define_insn "" | |
cd2b37d9 | 671 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
672 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
673 | "" | |
674 | "@ | |
675 | lbz%U1%X1 %0,%1 | |
005a35b9 | 676 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
677 | [(set_attr "type" "load,*")]) |
678 | ||
679 | (define_insn "" | |
9ebbca7d GK |
680 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
681 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 682 | (const_int 0))) |
9ebbca7d | 683 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 684 | "" |
9ebbca7d GK |
685 | "@ |
686 | {andil.|andi.} %2,%1,0xff | |
687 | #" | |
688 | [(set_attr "type" "compare") | |
689 | (set_attr "length" "4,8")]) | |
690 | ||
691 | (define_split | |
692 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
693 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
694 | (const_int 0))) | |
695 | (clobber (match_scratch:HI 2 ""))] | |
696 | "reload_completed" | |
697 | [(set (match_dup 2) | |
698 | (zero_extend:HI (match_dup 1))) | |
699 | (set (match_dup 0) | |
700 | (compare:CC (match_dup 2) | |
701 | (const_int 0)))] | |
702 | "") | |
1fd4e8c1 | 703 | |
51b8fc2c | 704 | (define_insn "" |
9ebbca7d GK |
705 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
706 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 707 | (const_int 0))) |
9ebbca7d | 708 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
709 | (zero_extend:HI (match_dup 1)))] |
710 | "" | |
9ebbca7d GK |
711 | "@ |
712 | {andil.|andi.} %0,%1,0xff | |
713 | #" | |
714 | [(set_attr "type" "compare") | |
715 | (set_attr "length" "4,8")]) | |
716 | ||
717 | (define_split | |
718 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
719 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
720 | (const_int 0))) | |
721 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
722 | (zero_extend:HI (match_dup 1)))] | |
723 | "reload_completed" | |
724 | [(set (match_dup 0) | |
725 | (zero_extend:HI (match_dup 1))) | |
726 | (set (match_dup 2) | |
727 | (compare:CC (match_dup 0) | |
728 | (const_int 0)))] | |
729 | "") | |
815cdc52 MM |
730 | |
731 | (define_expand "extendqihi2" | |
732 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
733 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
734 | "" | |
735 | " | |
736 | { | |
737 | if (TARGET_POWERPC) | |
738 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
739 | else if (TARGET_POWER) | |
740 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
741 | else | |
742 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
743 | DONE; | |
744 | }") | |
745 | ||
746 | (define_insn "extendqihi2_ppc" | |
747 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
748 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
749 | "TARGET_POWERPC" | |
750 | "extsb %0,%1") | |
751 | ||
752 | (define_insn "" | |
9ebbca7d GK |
753 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
754 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 755 | (const_int 0))) |
9ebbca7d | 756 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 757 | "TARGET_POWERPC" |
9ebbca7d GK |
758 | "@ |
759 | extsb. %2,%1 | |
760 | #" | |
761 | [(set_attr "type" "compare") | |
762 | (set_attr "length" "4,8")]) | |
763 | ||
764 | (define_split | |
765 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
766 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
767 | (const_int 0))) | |
768 | (clobber (match_scratch:HI 2 ""))] | |
769 | "TARGET_POWERPC && reload_completed" | |
770 | [(set (match_dup 2) | |
771 | (sign_extend:HI (match_dup 1))) | |
772 | (set (match_dup 0) | |
773 | (compare:CC (match_dup 2) | |
774 | (const_int 0)))] | |
775 | "") | |
815cdc52 MM |
776 | |
777 | (define_insn "" | |
9ebbca7d GK |
778 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
779 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 780 | (const_int 0))) |
9ebbca7d | 781 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
782 | (sign_extend:HI (match_dup 1)))] |
783 | "TARGET_POWERPC" | |
9ebbca7d GK |
784 | "@ |
785 | extsb. %0,%1 | |
786 | #" | |
787 | [(set_attr "type" "compare") | |
788 | (set_attr "length" "4,8")]) | |
789 | ||
790 | (define_split | |
791 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
792 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
793 | (const_int 0))) | |
794 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
795 | (sign_extend:HI (match_dup 1)))] | |
796 | "TARGET_POWERPC && reload_completed" | |
797 | [(set (match_dup 0) | |
798 | (sign_extend:HI (match_dup 1))) | |
799 | (set (match_dup 2) | |
800 | (compare:CC (match_dup 0) | |
801 | (const_int 0)))] | |
802 | "") | |
51b8fc2c RK |
803 | |
804 | (define_expand "extendqihi2_power" | |
805 | [(parallel [(set (match_dup 2) | |
806 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
807 | (const_int 24))) | |
808 | (clobber (scratch:SI))]) | |
809 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
810 | (ashiftrt:SI (match_dup 2) | |
811 | (const_int 24))) | |
812 | (clobber (scratch:SI))])] | |
813 | "TARGET_POWER" | |
814 | " | |
815 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
816 | operands[1] = gen_lowpart (SImode, operands[1]); | |
817 | operands[2] = gen_reg_rtx (SImode); }") | |
818 | ||
819 | (define_expand "extendqihi2_no_power" | |
820 | [(set (match_dup 2) | |
821 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
822 | (const_int 24))) | |
823 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
824 | (ashiftrt:SI (match_dup 2) | |
825 | (const_int 24)))] | |
826 | "! TARGET_POWER && ! TARGET_POWERPC" | |
827 | " | |
828 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
829 | operands[1] = gen_lowpart (SImode, operands[1]); | |
830 | operands[2] = gen_reg_rtx (SImode); }") | |
831 | ||
1fd4e8c1 | 832 | (define_expand "zero_extendhisi2" |
5f243543 | 833 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 834 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
835 | "" |
836 | "") | |
837 | ||
838 | (define_insn "" | |
cd2b37d9 | 839 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
840 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
841 | "" | |
842 | "@ | |
843 | lhz%U1%X1 %0,%1 | |
005a35b9 | 844 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
845 | [(set_attr "type" "load,*")]) |
846 | ||
847 | (define_insn "" | |
9ebbca7d GK |
848 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
849 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 850 | (const_int 0))) |
9ebbca7d | 851 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 852 | "" |
9ebbca7d GK |
853 | "@ |
854 | {andil.|andi.} %2,%1,0xffff | |
855 | #" | |
856 | [(set_attr "type" "compare") | |
857 | (set_attr "length" "4,8")]) | |
858 | ||
859 | (define_split | |
860 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
861 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
862 | (const_int 0))) | |
863 | (clobber (match_scratch:SI 2 ""))] | |
864 | "reload_completed" | |
865 | [(set (match_dup 2) | |
866 | (zero_extend:SI (match_dup 1))) | |
867 | (set (match_dup 0) | |
868 | (compare:CC (match_dup 2) | |
869 | (const_int 0)))] | |
870 | "") | |
1fd4e8c1 RK |
871 | |
872 | (define_insn "" | |
9ebbca7d GK |
873 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
874 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 875 | (const_int 0))) |
9ebbca7d | 876 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
877 | (zero_extend:SI (match_dup 1)))] |
878 | "" | |
9ebbca7d GK |
879 | "@ |
880 | {andil.|andi.} %0,%1,0xffff | |
881 | #" | |
882 | [(set_attr "type" "compare") | |
883 | (set_attr "length" "4,8")]) | |
884 | ||
885 | (define_split | |
886 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
887 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
888 | (const_int 0))) | |
889 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
890 | (zero_extend:SI (match_dup 1)))] | |
891 | "reload_completed" | |
892 | [(set (match_dup 0) | |
893 | (zero_extend:SI (match_dup 1))) | |
894 | (set (match_dup 2) | |
895 | (compare:CC (match_dup 0) | |
896 | (const_int 0)))] | |
897 | "") | |
1fd4e8c1 RK |
898 | |
899 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
900 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
901 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
902 | "" |
903 | "") | |
904 | ||
905 | (define_insn "" | |
cd2b37d9 | 906 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
907 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
908 | "" | |
909 | "@ | |
910 | lha%U1%X1 %0,%1 | |
ca7f5001 | 911 | {exts|extsh} %0,%1" |
b54cf83a | 912 | [(set_attr "type" "load_ext,*")]) |
1fd4e8c1 RK |
913 | |
914 | (define_insn "" | |
9ebbca7d GK |
915 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
916 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 917 | (const_int 0))) |
9ebbca7d | 918 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 919 | "" |
9ebbca7d GK |
920 | "@ |
921 | {exts.|extsh.} %2,%1 | |
922 | #" | |
923 | [(set_attr "type" "compare") | |
924 | (set_attr "length" "4,8")]) | |
925 | ||
926 | (define_split | |
927 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
928 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
929 | (const_int 0))) | |
930 | (clobber (match_scratch:SI 2 ""))] | |
931 | "reload_completed" | |
932 | [(set (match_dup 2) | |
933 | (sign_extend:SI (match_dup 1))) | |
934 | (set (match_dup 0) | |
935 | (compare:CC (match_dup 2) | |
936 | (const_int 0)))] | |
937 | "") | |
1fd4e8c1 RK |
938 | |
939 | (define_insn "" | |
9ebbca7d GK |
940 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
941 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 942 | (const_int 0))) |
9ebbca7d | 943 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
944 | (sign_extend:SI (match_dup 1)))] |
945 | "" | |
9ebbca7d GK |
946 | "@ |
947 | {exts.|extsh.} %0,%1 | |
948 | #" | |
949 | [(set_attr "type" "compare") | |
950 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 951 | \f |
9ebbca7d GK |
952 | (define_split |
953 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
954 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
955 | (const_int 0))) | |
956 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
957 | (sign_extend:SI (match_dup 1)))] | |
958 | "reload_completed" | |
959 | [(set (match_dup 0) | |
960 | (sign_extend:SI (match_dup 1))) | |
961 | (set (match_dup 2) | |
962 | (compare:CC (match_dup 0) | |
963 | (const_int 0)))] | |
964 | "") | |
965 | ||
1fd4e8c1 | 966 | ;; Fixed-point arithmetic insns. |
deb9225a RK |
967 | |
968 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
969 | ;; allowing register zero as source. | |
7cd5235b MM |
970 | (define_expand "addsi3" |
971 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
972 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 973 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
7cd5235b MM |
974 | "" |
975 | " | |
976 | { | |
677a9668 DE |
977 | if (GET_CODE (operands[2]) == CONST_INT |
978 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 979 | { |
677a9668 | 980 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
981 | ? operands[0] : gen_reg_rtx (SImode)); |
982 | ||
2bfcf297 | 983 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 984 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 985 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
7cd5235b | 986 | |
9ebbca7d GK |
987 | /* The ordering here is important for the prolog expander. |
988 | When space is allocated from the stack, adding 'low' first may | |
989 | produce a temporary deallocation (which would be bad). */ | |
2bfcf297 | 990 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest))); |
7cd5235b MM |
991 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); |
992 | DONE; | |
993 | } | |
994 | }") | |
995 | ||
996 | (define_insn "*addsi3_internal1" | |
997 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
998 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 999 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1000 | "" |
1001 | "@ | |
deb9225a RK |
1002 | {cax|add} %0,%1,%2 |
1003 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1004 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1005 | {cau|addis} %0,%1,%v2" |
1006 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1007 | |
ee890fe2 SS |
1008 | (define_insn "addsi3_high" |
1009 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1010 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1011 | (high:SI (match_operand 2 "" ""))))] | |
1012 | "TARGET_MACHO && !TARGET_64BIT" | |
1013 | "{cau|addis} %0,%1,ha16(%2)" | |
1014 | [(set_attr "length" "4")]) | |
1015 | ||
7cd5235b | 1016 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1017 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1018 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1019 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1020 | (const_int 0))) |
cb8cc086 | 1021 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
0ad91047 | 1022 | "! TARGET_POWERPC64" |
deb9225a RK |
1023 | "@ |
1024 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1025 | {ai.|addic.} %3,%1,%2 |
1026 | # | |
1027 | #" | |
a62bfff2 | 1028 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1029 | (set_attr "length" "4,4,8,8")]) |
1030 | ||
1031 | (define_split | |
1032 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1033 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1034 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1035 | (const_int 0))) | |
1036 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1037 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1038 | [(set (match_dup 3) |
1039 | (plus:SI (match_dup 1) | |
1040 | (match_dup 2))) | |
1041 | (set (match_dup 0) | |
1042 | (compare:CC (match_dup 3) | |
1043 | (const_int 0)))] | |
1044 | "") | |
7e69e155 | 1045 | |
7cd5235b | 1046 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1047 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1048 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1049 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1050 | (const_int 0))) |
cb8cc086 MM |
1051 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1052 | (plus:SI (match_dup 1) | |
1053 | (match_dup 2)))] | |
0ad91047 | 1054 | "! TARGET_POWERPC64" |
deb9225a RK |
1055 | "@ |
1056 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1057 | {ai.|addic.} %0,%1,%2 |
1058 | # | |
1059 | #" | |
a62bfff2 | 1060 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1061 | (set_attr "length" "4,4,8,8")]) |
1062 | ||
1063 | (define_split | |
1064 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1065 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1066 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1067 | (const_int 0))) | |
1068 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1069 | (plus:SI (match_dup 1) (match_dup 2)))] | |
0ad91047 | 1070 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1071 | [(set (match_dup 0) |
1072 | (plus:SI (match_dup 1) | |
1073 | (match_dup 2))) | |
1074 | (set (match_dup 3) | |
1075 | (compare:CC (match_dup 0) | |
1076 | (const_int 0)))] | |
1077 | "") | |
7e69e155 | 1078 | |
f357808b RK |
1079 | ;; Split an add that we can't do in one insn into two insns, each of which |
1080 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1081 | ;; add should be last in case the result gets used in an address. | |
1082 | ||
1083 | (define_split | |
cd2b37d9 RK |
1084 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1085 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1086 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1087 | "" |
f357808b RK |
1088 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1089 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1090 | " | |
1fd4e8c1 | 1091 | { |
2bfcf297 | 1092 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1093 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 1094 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
1fd4e8c1 | 1095 | |
2bfcf297 | 1096 | operands[3] = GEN_INT (rest); |
e6ca2c17 | 1097 | operands[4] = GEN_INT (low); |
1fd4e8c1 RK |
1098 | }") |
1099 | ||
8de2a197 | 1100 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1101 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1102 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1103 | "" |
ca7f5001 RK |
1104 | "nor %0,%1,%1") |
1105 | ||
1106 | (define_insn "" | |
52d3af72 DE |
1107 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1108 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1109 | (const_int 0))) |
52d3af72 | 1110 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1111 | "! TARGET_POWERPC64" |
52d3af72 DE |
1112 | "@ |
1113 | nor. %2,%1,%1 | |
1114 | #" | |
1115 | [(set_attr "type" "compare") | |
1116 | (set_attr "length" "4,8")]) | |
1117 | ||
1118 | (define_split | |
1119 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1120 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1121 | (const_int 0))) | |
1122 | (clobber (match_scratch:SI 2 ""))] | |
0ad91047 | 1123 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1124 | [(set (match_dup 2) |
1125 | (not:SI (match_dup 1))) | |
1126 | (set (match_dup 0) | |
1127 | (compare:CC (match_dup 2) | |
1128 | (const_int 0)))] | |
1129 | "") | |
ca7f5001 RK |
1130 | |
1131 | (define_insn "" | |
52d3af72 DE |
1132 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1133 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1134 | (const_int 0))) |
52d3af72 | 1135 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1136 | (not:SI (match_dup 1)))] |
0ad91047 | 1137 | "! TARGET_POWERPC64" |
52d3af72 DE |
1138 | "@ |
1139 | nor. %0,%1,%1 | |
1140 | #" | |
1141 | [(set_attr "type" "compare") | |
1142 | (set_attr "length" "4,8")]) | |
1143 | ||
1144 | (define_split | |
1145 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1146 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1147 | (const_int 0))) | |
1cb18e3c | 1148 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
52d3af72 | 1149 | (not:SI (match_dup 1)))] |
0ad91047 | 1150 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1151 | [(set (match_dup 0) |
1152 | (not:SI (match_dup 1))) | |
1153 | (set (match_dup 2) | |
1154 | (compare:CC (match_dup 0) | |
1155 | (const_int 0)))] | |
1156 | "") | |
1fd4e8c1 RK |
1157 | |
1158 | (define_insn "" | |
3d91674b RK |
1159 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1160 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1161 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1162 | "! TARGET_POWERPC" |
ca7f5001 | 1163 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1164 | |
deb9225a RK |
1165 | (define_insn "" |
1166 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1167 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1168 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1169 | "TARGET_POWERPC" | |
1170 | "@ | |
1171 | subf %0,%2,%1 | |
1172 | subfic %0,%2,%1") | |
1173 | ||
1fd4e8c1 | 1174 | (define_insn "" |
cb8cc086 MM |
1175 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1176 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1177 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1178 | (const_int 0))) |
cb8cc086 | 1179 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1180 | "! TARGET_POWERPC" |
cb8cc086 MM |
1181 | "@ |
1182 | {sf.|subfc.} %3,%2,%1 | |
1183 | #" | |
1184 | [(set_attr "type" "compare") | |
1185 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1186 | |
deb9225a | 1187 | (define_insn "" |
cb8cc086 MM |
1188 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1189 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1190 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1191 | (const_int 0))) |
cb8cc086 | 1192 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 1193 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
cb8cc086 MM |
1194 | "@ |
1195 | subf. %3,%2,%1 | |
1196 | #" | |
a62bfff2 | 1197 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1198 | (set_attr "length" "4,8")]) |
1199 | ||
1200 | (define_split | |
1201 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1202 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1203 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1204 | (const_int 0))) | |
1205 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1206 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1207 | [(set (match_dup 3) |
1208 | (minus:SI (match_dup 1) | |
1209 | (match_dup 2))) | |
1210 | (set (match_dup 0) | |
1211 | (compare:CC (match_dup 3) | |
1212 | (const_int 0)))] | |
1213 | "") | |
deb9225a | 1214 | |
1fd4e8c1 | 1215 | (define_insn "" |
cb8cc086 MM |
1216 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1217 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1218 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1219 | (const_int 0))) |
cb8cc086 | 1220 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1221 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1222 | "! TARGET_POWERPC" |
cb8cc086 MM |
1223 | "@ |
1224 | {sf.|subfc.} %0,%2,%1 | |
1225 | #" | |
1226 | [(set_attr "type" "compare") | |
1227 | (set_attr "length" "4,8")]) | |
815cdc52 | 1228 | |
29ae5b89 | 1229 | (define_insn "" |
cb8cc086 MM |
1230 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1231 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1232 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1233 | (const_int 0))) |
cb8cc086 MM |
1234 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1235 | (minus:SI (match_dup 1) | |
1236 | (match_dup 2)))] | |
0ad91047 | 1237 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
90612787 DE |
1238 | "@ |
1239 | subf. %0,%2,%1 | |
1240 | #" | |
a62bfff2 | 1241 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1242 | (set_attr "length" "4,8")]) |
1243 | ||
1244 | (define_split | |
1245 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1246 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1247 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1248 | (const_int 0))) | |
1249 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1250 | (minus:SI (match_dup 1) | |
1251 | (match_dup 2)))] | |
0ad91047 | 1252 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1253 | [(set (match_dup 0) |
1254 | (minus:SI (match_dup 1) | |
1255 | (match_dup 2))) | |
1256 | (set (match_dup 3) | |
1257 | (compare:CC (match_dup 0) | |
1258 | (const_int 0)))] | |
1259 | "") | |
deb9225a | 1260 | |
1fd4e8c1 | 1261 | (define_expand "subsi3" |
cd2b37d9 | 1262 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1263 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
f6bf7de2 | 1264 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
1fd4e8c1 | 1265 | "" |
a0044fb1 RK |
1266 | " |
1267 | { | |
1268 | if (GET_CODE (operands[2]) == CONST_INT) | |
1269 | { | |
1270 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1271 | negate_rtx (SImode, operands[2]))); | |
1272 | DONE; | |
1273 | } | |
1274 | }") | |
1fd4e8c1 RK |
1275 | |
1276 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1277 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1278 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1279 | ;; combine. | |
1fd4e8c1 RK |
1280 | |
1281 | (define_expand "sminsi3" | |
1282 | [(set (match_dup 3) | |
cd2b37d9 | 1283 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1284 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1285 | (const_int 0) | |
1286 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1287 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1288 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1289 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1290 | " |
a3170dc6 AH |
1291 | { |
1292 | if (TARGET_ISEL) | |
1293 | { | |
1294 | operands[2] = force_reg (SImode, operands[2]); | |
1295 | rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); | |
1296 | DONE; | |
1297 | } | |
1298 | ||
1299 | operands[3] = gen_reg_rtx (SImode); | |
1300 | }") | |
1fd4e8c1 | 1301 | |
95ac8e67 RK |
1302 | (define_split |
1303 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1304 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1305 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1306 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1307 | "TARGET_POWER" |
95ac8e67 RK |
1308 | [(set (match_dup 3) |
1309 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1310 | (const_int 0) | |
1311 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1312 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1313 | "") | |
1314 | ||
1fd4e8c1 RK |
1315 | (define_expand "smaxsi3" |
1316 | [(set (match_dup 3) | |
cd2b37d9 | 1317 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1318 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1319 | (const_int 0) | |
1320 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1321 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1322 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1323 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1324 | " |
a3170dc6 AH |
1325 | { |
1326 | if (TARGET_ISEL) | |
1327 | { | |
1328 | operands[2] = force_reg (SImode, operands[2]); | |
1329 | rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); | |
1330 | DONE; | |
1331 | } | |
1332 | operands[3] = gen_reg_rtx (SImode); | |
1333 | }") | |
1fd4e8c1 | 1334 | |
95ac8e67 RK |
1335 | (define_split |
1336 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1337 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1338 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1339 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1340 | "TARGET_POWER" |
95ac8e67 RK |
1341 | [(set (match_dup 3) |
1342 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1343 | (const_int 0) | |
1344 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1345 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1346 | "") | |
1347 | ||
1fd4e8c1 | 1348 | (define_expand "uminsi3" |
cd2b37d9 | 1349 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1350 | (match_dup 5))) |
cd2b37d9 | 1351 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1352 | (match_dup 5))) |
1fd4e8c1 RK |
1353 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1354 | (const_int 0) | |
1355 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1356 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1357 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1358 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1359 | " |
bb68ff55 | 1360 | { |
a3170dc6 AH |
1361 | if (TARGET_ISEL) |
1362 | { | |
1363 | rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]); | |
1364 | DONE; | |
1365 | } | |
bb68ff55 MM |
1366 | operands[3] = gen_reg_rtx (SImode); |
1367 | operands[4] = gen_reg_rtx (SImode); | |
1368 | operands[5] = GEN_INT (-2147483647 - 1); | |
1369 | }") | |
1fd4e8c1 RK |
1370 | |
1371 | (define_expand "umaxsi3" | |
cd2b37d9 | 1372 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1373 | (match_dup 5))) |
cd2b37d9 | 1374 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1375 | (match_dup 5))) |
1fd4e8c1 RK |
1376 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1377 | (const_int 0) | |
1378 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1379 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1380 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1381 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1382 | " |
bb68ff55 | 1383 | { |
a3170dc6 AH |
1384 | if (TARGET_ISEL) |
1385 | { | |
1386 | rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]); | |
1387 | DONE; | |
1388 | } | |
bb68ff55 MM |
1389 | operands[3] = gen_reg_rtx (SImode); |
1390 | operands[4] = gen_reg_rtx (SImode); | |
1391 | operands[5] = GEN_INT (-2147483647 - 1); | |
1392 | }") | |
1fd4e8c1 RK |
1393 | |
1394 | (define_insn "" | |
cd2b37d9 RK |
1395 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1396 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1397 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1398 | (const_int 0) |
1399 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1400 | "TARGET_POWER" |
1fd4e8c1 RK |
1401 | "doz%I2 %0,%1,%2") |
1402 | ||
1403 | (define_insn "" | |
9ebbca7d | 1404 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1405 | (compare:CC |
9ebbca7d GK |
1406 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1407 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1408 | (const_int 0) |
1409 | (minus:SI (match_dup 2) (match_dup 1))) | |
1410 | (const_int 0))) | |
9ebbca7d | 1411 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 1412 | "TARGET_POWER" |
9ebbca7d GK |
1413 | "@ |
1414 | doz%I2. %3,%1,%2 | |
1415 | #" | |
1416 | [(set_attr "type" "delayed_compare") | |
1417 | (set_attr "length" "4,8")]) | |
1418 | ||
1419 | (define_split | |
1420 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1421 | (compare:CC | |
1422 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1423 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1424 | (const_int 0) | |
1425 | (minus:SI (match_dup 2) (match_dup 1))) | |
1426 | (const_int 0))) | |
1427 | (clobber (match_scratch:SI 3 ""))] | |
1428 | "TARGET_POWER && reload_completed" | |
1429 | [(set (match_dup 3) | |
1430 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1431 | (const_int 0) | |
1432 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1433 | (set (match_dup 0) | |
1434 | (compare:CC (match_dup 3) | |
1435 | (const_int 0)))] | |
1436 | "") | |
1fd4e8c1 RK |
1437 | |
1438 | (define_insn "" | |
9ebbca7d | 1439 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1440 | (compare:CC |
9ebbca7d GK |
1441 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1442 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1443 | (const_int 0) |
1444 | (minus:SI (match_dup 2) (match_dup 1))) | |
1445 | (const_int 0))) | |
9ebbca7d | 1446 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1447 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1448 | (const_int 0) | |
1449 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1450 | "TARGET_POWER" |
9ebbca7d GK |
1451 | "@ |
1452 | doz%I2. %0,%1,%2 | |
1453 | #" | |
1454 | [(set_attr "type" "delayed_compare") | |
1455 | (set_attr "length" "4,8")]) | |
1456 | ||
1457 | (define_split | |
1458 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1459 | (compare:CC | |
1460 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1461 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1462 | (const_int 0) | |
1463 | (minus:SI (match_dup 2) (match_dup 1))) | |
1464 | (const_int 0))) | |
1465 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1466 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1467 | (const_int 0) | |
1468 | (minus:SI (match_dup 2) (match_dup 1))))] | |
1469 | "TARGET_POWER && reload_completed" | |
1470 | [(set (match_dup 0) | |
1471 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1472 | (const_int 0) | |
1473 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1474 | (set (match_dup 3) | |
1475 | (compare:CC (match_dup 0) | |
1476 | (const_int 0)))] | |
1477 | "") | |
1fd4e8c1 RK |
1478 | |
1479 | ;; We don't need abs with condition code because such comparisons should | |
1480 | ;; never be done. | |
ea9be077 MM |
1481 | (define_expand "abssi2" |
1482 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1483 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1484 | "" | |
1485 | " | |
1486 | { | |
a3170dc6 AH |
1487 | if (TARGET_ISEL) |
1488 | { | |
1489 | emit_insn (gen_abssi2_isel (operands[0], operands[1])); | |
1490 | DONE; | |
1491 | } | |
1492 | else if (! TARGET_POWER) | |
ea9be077 MM |
1493 | { |
1494 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1495 | DONE; | |
1496 | } | |
1497 | }") | |
1498 | ||
ea112fc4 | 1499 | (define_insn "*abssi2_power" |
cd2b37d9 RK |
1500 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1501 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1502 | "TARGET_POWER" |
1fd4e8c1 RK |
1503 | "abs %0,%1") |
1504 | ||
a3170dc6 AH |
1505 | (define_insn_and_split "abssi2_isel" |
1506 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1507 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
1508 | (clobber (match_scratch:SI 2 "=b")) | |
1509 | (clobber (match_scratch:CC 3 "=y"))] | |
1510 | "TARGET_ISEL" | |
1511 | "#" | |
1512 | "&& reload_completed" | |
1513 | [(set (match_dup 2) (neg:SI (match_dup 1))) | |
1514 | (set (match_dup 3) | |
1515 | (compare:CC (match_dup 1) | |
1516 | (const_int 0))) | |
1517 | (set (match_dup 0) | |
1518 | (if_then_else:SI (ge (match_dup 3) | |
1519 | (const_int 0)) | |
1520 | (match_dup 1) | |
1521 | (match_dup 2)))] | |
1522 | "") | |
1523 | ||
ea112fc4 | 1524 | (define_insn_and_split "abssi2_nopower" |
ea9be077 | 1525 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1526 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) |
ea9be077 | 1527 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
a3170dc6 | 1528 | "! TARGET_POWER && ! TARGET_ISEL" |
ea112fc4 DE |
1529 | "#" |
1530 | "&& reload_completed" | |
ea9be077 MM |
1531 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1532 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1533 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1534 | "") |
1535 | ||
463b558b | 1536 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1537 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1538 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1539 | "TARGET_POWER" |
1fd4e8c1 RK |
1540 | "nabs %0,%1") |
1541 | ||
ea112fc4 | 1542 | (define_insn_and_split "*nabs_nopower" |
ea9be077 | 1543 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1544 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) |
ea9be077 | 1545 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
0ad91047 | 1546 | "! TARGET_POWER" |
ea112fc4 DE |
1547 | "#" |
1548 | "&& reload_completed" | |
ea9be077 MM |
1549 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1550 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1551 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1552 | "") |
1553 | ||
1fd4e8c1 | 1554 | (define_insn "negsi2" |
cd2b37d9 RK |
1555 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1556 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1557 | "" |
1558 | "neg %0,%1") | |
1559 | ||
1560 | (define_insn "" | |
9ebbca7d GK |
1561 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1562 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1563 | (const_int 0))) |
9ebbca7d | 1564 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1565 | "! TARGET_POWERPC64" |
9ebbca7d GK |
1566 | "@ |
1567 | neg. %2,%1 | |
1568 | #" | |
a62bfff2 | 1569 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1570 | (set_attr "length" "4,8")]) |
1571 | ||
1572 | (define_split | |
1573 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1574 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1575 | (const_int 0))) | |
1576 | (clobber (match_scratch:SI 2 ""))] | |
1577 | "! TARGET_POWERPC64 && reload_completed" | |
1578 | [(set (match_dup 2) | |
1579 | (neg:SI (match_dup 1))) | |
1580 | (set (match_dup 0) | |
1581 | (compare:CC (match_dup 2) | |
1582 | (const_int 0)))] | |
1583 | "") | |
1fd4e8c1 RK |
1584 | |
1585 | (define_insn "" | |
9ebbca7d GK |
1586 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1587 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1588 | (const_int 0))) |
9ebbca7d | 1589 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1590 | (neg:SI (match_dup 1)))] |
0ad91047 | 1591 | "! TARGET_POWERPC64" |
9ebbca7d GK |
1592 | "@ |
1593 | neg. %0,%1 | |
1594 | #" | |
a62bfff2 | 1595 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1596 | (set_attr "length" "4,8")]) |
1597 | ||
1598 | (define_split | |
1599 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1600 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1601 | (const_int 0))) | |
1602 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1603 | (neg:SI (match_dup 1)))] | |
1604 | "! TARGET_POWERPC64 && reload_completed" | |
1605 | [(set (match_dup 0) | |
1606 | (neg:SI (match_dup 1))) | |
1607 | (set (match_dup 2) | |
1608 | (compare:CC (match_dup 0) | |
1609 | (const_int 0)))] | |
1610 | "") | |
1fd4e8c1 | 1611 | |
1b1edcfa DE |
1612 | (define_insn "clzsi2" |
1613 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1614 | (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1615 | "" | |
1616 | "{cntlz|cntlzw} %0,%1") | |
1617 | ||
1618 | (define_expand "ctzsi2" | |
4977bab6 | 1619 | [(set (match_dup 2) |
1b1edcfa | 1620 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
4977bab6 | 1621 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) |
1b1edcfa DE |
1622 | (match_dup 2))) |
1623 | (clobber (scratch:CC))]) | |
d865b122 | 1624 | (set (match_dup 4) (clz:SI (match_dup 3))) |
4977bab6 | 1625 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 1626 | (minus:SI (const_int 31) (match_dup 4)))] |
1fd4e8c1 | 1627 | "" |
4977bab6 ZW |
1628 | { |
1629 | operands[2] = gen_reg_rtx (SImode); | |
1630 | operands[3] = gen_reg_rtx (SImode); | |
1631 | operands[4] = gen_reg_rtx (SImode); | |
1632 | }) | |
1633 | ||
1b1edcfa DE |
1634 | (define_expand "ffssi2" |
1635 | [(set (match_dup 2) | |
1636 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
1637 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) | |
1638 | (match_dup 2))) | |
1639 | (clobber (scratch:CC))]) | |
1640 | (set (match_dup 4) (clz:SI (match_dup 3))) | |
1641 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1642 | (minus:SI (const_int 32) (match_dup 4)))] | |
4977bab6 | 1643 | "" |
1b1edcfa DE |
1644 | { |
1645 | operands[2] = gen_reg_rtx (SImode); | |
1646 | operands[3] = gen_reg_rtx (SImode); | |
1647 | operands[4] = gen_reg_rtx (SImode); | |
1648 | }) | |
1649 | ||
ca7f5001 RK |
1650 | (define_expand "mulsi3" |
1651 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1652 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
1653 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
1654 | "" | |
1655 | " | |
1656 | { | |
1657 | if (TARGET_POWER) | |
68b40e7e | 1658 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 1659 | else |
68b40e7e | 1660 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
1661 | DONE; |
1662 | }") | |
1663 | ||
68b40e7e | 1664 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
1665 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1666 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
1667 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
1668 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
1669 | "TARGET_POWER" |
1670 | "@ | |
1671 | {muls|mullw} %0,%1,%2 | |
1672 | {muli|mulli} %0,%1,%2" | |
c859cda6 DJ |
1673 | [(set (attr "type") |
1674 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") | |
1675 | (const_string "imul3") | |
1676 | (match_operand:SI 2 "short_cint_operand" "") | |
1677 | (const_string "imul2")] | |
1678 | (const_string "imul")))]) | |
ca7f5001 | 1679 | |
68b40e7e | 1680 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
1681 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1682 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1683 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 1684 | "! TARGET_POWER" |
1fd4e8c1 | 1685 | "@ |
d904e9ed RK |
1686 | {muls|mullw} %0,%1,%2 |
1687 | {muli|mulli} %0,%1,%2" | |
c859cda6 DJ |
1688 | [(set (attr "type") |
1689 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") | |
1690 | (const_string "imul3") | |
1691 | (match_operand:SI 2 "short_cint_operand" "") | |
1692 | (const_string "imul2")] | |
1693 | (const_string "imul")))]) | |
1fd4e8c1 | 1694 | |
9259f3b0 | 1695 | (define_insn "*mulsi3_mq_internal1" |
9ebbca7d GK |
1696 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1697 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1698 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1699 | (const_int 0))) |
9ebbca7d GK |
1700 | (clobber (match_scratch:SI 3 "=r,r")) |
1701 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 1702 | "TARGET_POWER" |
9ebbca7d GK |
1703 | "@ |
1704 | {muls.|mullw.} %3,%1,%2 | |
1705 | #" | |
9259f3b0 | 1706 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1707 | (set_attr "length" "4,8")]) |
1708 | ||
1709 | (define_split | |
1710 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1711 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1712 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1713 | (const_int 0))) | |
1714 | (clobber (match_scratch:SI 3 "")) | |
1715 | (clobber (match_scratch:SI 4 ""))] | |
1716 | "TARGET_POWER && reload_completed" | |
1717 | [(parallel [(set (match_dup 3) | |
1718 | (mult:SI (match_dup 1) (match_dup 2))) | |
1719 | (clobber (match_dup 4))]) | |
1720 | (set (match_dup 0) | |
1721 | (compare:CC (match_dup 3) | |
1722 | (const_int 0)))] | |
1723 | "") | |
ca7f5001 | 1724 | |
9259f3b0 | 1725 | (define_insn "*mulsi3_no_mq_internal1" |
9ebbca7d GK |
1726 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1727 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1728 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1729 | (const_int 0))) |
9ebbca7d | 1730 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 1731 | "! TARGET_POWER" |
9ebbca7d GK |
1732 | "@ |
1733 | {muls.|mullw.} %3,%1,%2 | |
1734 | #" | |
9259f3b0 | 1735 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1736 | (set_attr "length" "4,8")]) |
1737 | ||
1738 | (define_split | |
1739 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1740 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1741 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1742 | (const_int 0))) | |
1743 | (clobber (match_scratch:SI 3 ""))] | |
1744 | "! TARGET_POWER && reload_completed" | |
1745 | [(set (match_dup 3) | |
1746 | (mult:SI (match_dup 1) (match_dup 2))) | |
1747 | (set (match_dup 0) | |
1748 | (compare:CC (match_dup 3) | |
1749 | (const_int 0)))] | |
1750 | "") | |
1fd4e8c1 | 1751 | |
9259f3b0 | 1752 | (define_insn "*mulsi3_mq_internal2" |
9ebbca7d GK |
1753 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1754 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1755 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1756 | (const_int 0))) |
9ebbca7d | 1757 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 1758 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 1759 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 1760 | "TARGET_POWER" |
9ebbca7d GK |
1761 | "@ |
1762 | {muls.|mullw.} %0,%1,%2 | |
1763 | #" | |
9259f3b0 | 1764 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1765 | (set_attr "length" "4,8")]) |
1766 | ||
1767 | (define_split | |
1768 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1769 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1770 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1771 | (const_int 0))) | |
1772 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1773 | (mult:SI (match_dup 1) (match_dup 2))) | |
1774 | (clobber (match_scratch:SI 4 ""))] | |
1775 | "TARGET_POWER && reload_completed" | |
1776 | [(parallel [(set (match_dup 0) | |
1777 | (mult:SI (match_dup 1) (match_dup 2))) | |
1778 | (clobber (match_dup 4))]) | |
1779 | (set (match_dup 3) | |
1780 | (compare:CC (match_dup 0) | |
1781 | (const_int 0)))] | |
1782 | "") | |
ca7f5001 | 1783 | |
9259f3b0 | 1784 | (define_insn "*mulsi3_no_mq_internal2" |
9ebbca7d GK |
1785 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1786 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1787 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1788 | (const_int 0))) |
9ebbca7d | 1789 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 1790 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 1791 | "! TARGET_POWER" |
9ebbca7d GK |
1792 | "@ |
1793 | {muls.|mullw.} %0,%1,%2 | |
1794 | #" | |
9259f3b0 | 1795 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1796 | (set_attr "length" "4,8")]) |
1797 | ||
1798 | (define_split | |
1799 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1800 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1801 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1802 | (const_int 0))) | |
1803 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1804 | (mult:SI (match_dup 1) (match_dup 2)))] | |
1805 | "! TARGET_POWER && reload_completed" | |
1806 | [(set (match_dup 0) | |
1807 | (mult:SI (match_dup 1) (match_dup 2))) | |
1808 | (set (match_dup 3) | |
1809 | (compare:CC (match_dup 0) | |
1810 | (const_int 0)))] | |
1811 | "") | |
1fd4e8c1 RK |
1812 | |
1813 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
1814 | ;; 0 and remainder to operand 3. | |
1815 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
1816 | ||
8ffd9c51 RK |
1817 | (define_expand "divmodsi4" |
1818 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1819 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1820 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
bb157ff4 | 1821 | (set (match_operand:SI 3 "register_operand" "") |
8ffd9c51 RK |
1822 | (mod:SI (match_dup 1) (match_dup 2)))])] |
1823 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1824 | " | |
1825 | { | |
1826 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1827 | { | |
39403d82 DE |
1828 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1829 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1830 | emit_insn (gen_divss_call ()); |
39403d82 DE |
1831 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1832 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
1833 | DONE; |
1834 | } | |
1835 | }") | |
deb9225a | 1836 | |
bb157ff4 | 1837 | (define_insn "*divmodsi4_internal" |
cd2b37d9 RK |
1838 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1839 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1840 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
bb157ff4 | 1841 | (set (match_operand:SI 3 "register_operand" "=q") |
1fd4e8c1 | 1842 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 1843 | "TARGET_POWER" |
cfb557c4 RK |
1844 | "divs %0,%1,%2" |
1845 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 1846 | |
8ffd9c51 RK |
1847 | (define_expand "udivsi3" |
1848 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1849 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1850 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
1851 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1852 | " | |
1853 | { | |
1854 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1855 | { | |
39403d82 DE |
1856 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1857 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1858 | emit_insn (gen_quous_call ()); |
39403d82 | 1859 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1860 | DONE; |
1861 | } | |
f192bf8b DE |
1862 | else if (TARGET_POWER) |
1863 | { | |
1864 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
1865 | DONE; | |
1866 | } | |
8ffd9c51 | 1867 | }") |
deb9225a | 1868 | |
f192bf8b DE |
1869 | (define_insn "udivsi3_mq" |
1870 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1871 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1872 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1873 | (clobber (match_scratch:SI 3 "=q"))] | |
1874 | "TARGET_POWERPC && TARGET_POWER" | |
1875 | "divwu %0,%1,%2" | |
1876 | [(set_attr "type" "idiv")]) | |
1877 | ||
1878 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
1879 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1880 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1881 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 1882 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 1883 | "divwu %0,%1,%2" |
ca7f5001 RK |
1884 | [(set_attr "type" "idiv")]) |
1885 | ||
1fd4e8c1 | 1886 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 1887 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
1888 | ;; used; for PowerPC, force operands into register and do a normal divide; |
1889 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 1890 | (define_expand "divsi3" |
cd2b37d9 RK |
1891 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1892 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
1893 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
1894 | "" | |
1895 | " | |
1896 | { | |
ca7f5001 | 1897 | if (GET_CODE (operands[2]) == CONST_INT |
2bfcf297 | 1898 | && INTVAL (operands[2]) > 0 |
ca7f5001 RK |
1899 | && exact_log2 (INTVAL (operands[2])) >= 0) |
1900 | ; | |
b6c9286a | 1901 | else if (TARGET_POWERPC) |
f192bf8b DE |
1902 | { |
1903 | operands[2] = force_reg (SImode, operands[2]); | |
1904 | if (TARGET_POWER) | |
1905 | { | |
1906 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
1907 | DONE; | |
1908 | } | |
1909 | } | |
b6c9286a | 1910 | else if (TARGET_POWER) |
1fd4e8c1 | 1911 | FAIL; |
405c5495 | 1912 | else |
8ffd9c51 | 1913 | { |
39403d82 DE |
1914 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1915 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1916 | emit_insn (gen_quoss_call ()); |
39403d82 | 1917 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1918 | DONE; |
1919 | } | |
1fd4e8c1 RK |
1920 | }") |
1921 | ||
f192bf8b DE |
1922 | (define_insn "divsi3_mq" |
1923 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1924 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1925 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1926 | (clobber (match_scratch:SI 3 "=q"))] | |
1927 | "TARGET_POWERPC && TARGET_POWER" | |
1928 | "divw %0,%1,%2" | |
1929 | [(set_attr "type" "idiv")]) | |
1930 | ||
1931 | (define_insn "*divsi3_no_mq" | |
1932 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1933 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1934 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1935 | "TARGET_POWERPC && ! TARGET_POWER" | |
1936 | "divw %0,%1,%2" | |
1937 | [(set_attr "type" "idiv")]) | |
1938 | ||
1fd4e8c1 | 1939 | (define_expand "modsi3" |
85644414 RK |
1940 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
1941 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 1942 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 1943 | "" |
1fd4e8c1 RK |
1944 | " |
1945 | { | |
481c7efa | 1946 | int i; |
39b52ba2 RK |
1947 | rtx temp1; |
1948 | rtx temp2; | |
1949 | ||
2bfcf297 | 1950 | if (GET_CODE (operands[2]) != CONST_INT |
a65c591c | 1951 | || INTVAL (operands[2]) <= 0 |
2bfcf297 | 1952 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) |
39b52ba2 RK |
1953 | FAIL; |
1954 | ||
1955 | temp1 = gen_reg_rtx (SImode); | |
1956 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 1957 | |
85644414 | 1958 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 1959 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
1960 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
1961 | DONE; | |
1fd4e8c1 RK |
1962 | }") |
1963 | ||
1964 | (define_insn "" | |
cd2b37d9 RK |
1965 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1966 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
1967 | (match_operand:SI 2 "exact_log2_cint_operand" "N")))] |
1968 | "" | |
ca7f5001 | 1969 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 1970 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
1971 | |
1972 | (define_insn "" | |
9ebbca7d GK |
1973 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1974 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 1975 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 1976 | (const_int 0))) |
9ebbca7d | 1977 | (clobber (match_scratch:SI 3 "=r,r"))] |
2bfcf297 | 1978 | "" |
9ebbca7d GK |
1979 | "@ |
1980 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
1981 | #" | |
b19003d8 | 1982 | [(set_attr "type" "compare") |
9ebbca7d GK |
1983 | (set_attr "length" "8,12")]) |
1984 | ||
1985 | (define_split | |
1986 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1987 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 1988 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
1989 | (const_int 0))) |
1990 | (clobber (match_scratch:SI 3 ""))] | |
2bfcf297 | 1991 | "reload_completed" |
9ebbca7d GK |
1992 | [(set (match_dup 3) |
1993 | (div:SI (match_dup 1) (match_dup 2))) | |
1994 | (set (match_dup 0) | |
1995 | (compare:CC (match_dup 3) | |
1996 | (const_int 0)))] | |
1997 | "") | |
1fd4e8c1 RK |
1998 | |
1999 | (define_insn "" | |
9ebbca7d GK |
2000 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2001 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2002 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2003 | (const_int 0))) |
9ebbca7d | 2004 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2005 | (div:SI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 2006 | "" |
9ebbca7d GK |
2007 | "@ |
2008 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2009 | #" | |
b19003d8 | 2010 | [(set_attr "type" "compare") |
9ebbca7d GK |
2011 | (set_attr "length" "8,12")]) |
2012 | ||
2013 | (define_split | |
2014 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2015 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2016 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2017 | (const_int 0))) |
2018 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2019 | (div:SI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2020 | "reload_completed" |
9ebbca7d GK |
2021 | [(set (match_dup 0) |
2022 | (div:SI (match_dup 1) (match_dup 2))) | |
2023 | (set (match_dup 3) | |
2024 | (compare:CC (match_dup 0) | |
2025 | (const_int 0)))] | |
2026 | "") | |
1fd4e8c1 RK |
2027 | |
2028 | (define_insn "" | |
cd2b37d9 | 2029 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2030 | (udiv:SI |
996a5f59 | 2031 | (plus:DI (ashift:DI |
cd2b37d9 | 2032 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2033 | (const_int 32)) |
23a900dc | 2034 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2035 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2036 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2037 | (umod:SI |
996a5f59 | 2038 | (plus:DI (ashift:DI |
1fd4e8c1 | 2039 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2040 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2041 | (match_dup 3)))] |
ca7f5001 | 2042 | "TARGET_POWER" |
cfb557c4 RK |
2043 | "div %0,%1,%3" |
2044 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2045 | |
2046 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2047 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2048 | ;; have to worry about the branches. So make a few subroutines here. | |
2049 | ;; | |
2050 | ;; First comes the normal case. | |
2051 | (define_expand "udivmodsi4_normal" | |
2052 | [(set (match_dup 4) (const_int 0)) | |
2053 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2054 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2055 | (const_int 32)) |
2056 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2057 | (match_operand:SI 2 "" ""))) | |
2058 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2059 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2060 | (const_int 32)) |
2061 | (zero_extend:DI (match_dup 1))) | |
2062 | (match_dup 2)))])] | |
ca7f5001 | 2063 | "TARGET_POWER" |
1fd4e8c1 RK |
2064 | " |
2065 | { operands[4] = gen_reg_rtx (SImode); }") | |
2066 | ||
2067 | ;; This handles the branches. | |
2068 | (define_expand "udivmodsi4_tests" | |
2069 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2070 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2071 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2072 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2073 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2074 | (set (match_dup 0) (const_int 1)) | |
2075 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2076 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2077 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2078 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2079 | "TARGET_POWER" |
1fd4e8c1 RK |
2080 | " |
2081 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2082 | operands[6] = gen_reg_rtx (CCmode); | |
2083 | }") | |
2084 | ||
2085 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2086 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2087 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2088 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2089 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2090 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2091 | "" |
1fd4e8c1 RK |
2092 | " |
2093 | { | |
2094 | rtx label = 0; | |
2095 | ||
8ffd9c51 | 2096 | if (! TARGET_POWER) |
c4d38ccb MM |
2097 | { |
2098 | if (! TARGET_POWERPC) | |
2099 | { | |
39403d82 DE |
2100 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2101 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2102 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2103 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2104 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2105 | DONE; |
2106 | } | |
2107 | else | |
2108 | FAIL; | |
2109 | } | |
0081a354 | 2110 | |
1fd4e8c1 RK |
2111 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2112 | { | |
2113 | operands[2] = force_reg (SImode, operands[2]); | |
2114 | label = gen_label_rtx (); | |
2115 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2116 | operands[3], label)); | |
2117 | } | |
2118 | else | |
2119 | operands[2] = force_reg (SImode, operands[2]); | |
2120 | ||
2121 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2122 | operands[3])); | |
2123 | if (label) | |
2124 | emit_label (label); | |
2125 | ||
2126 | DONE; | |
2127 | }") | |
0081a354 | 2128 | |
fada905b MM |
2129 | ;; AIX architecture-independent common-mode multiply (DImode), |
2130 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2131 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2132 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2133 | ;; assumed unused if generating common-mode, so ignore. | |
2134 | (define_insn "mulh_call" | |
2135 | [(set (reg:SI 3) | |
2136 | (truncate:SI | |
2137 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2138 | (sign_extend:DI (reg:SI 4))) | |
2139 | (const_int 32)))) | |
cf27b467 | 2140 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2141 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2142 | "bla __mulh" |
2143 | [(set_attr "type" "imul")]) | |
fada905b MM |
2144 | |
2145 | (define_insn "mull_call" | |
2146 | [(set (reg:DI 3) | |
2147 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2148 | (sign_extend:DI (reg:SI 4)))) | |
2149 | (clobber (match_scratch:SI 0 "=l")) | |
2150 | (clobber (reg:SI 0))] | |
2151 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2152 | "bla __mull" |
2153 | [(set_attr "type" "imul")]) | |
fada905b MM |
2154 | |
2155 | (define_insn "divss_call" | |
2156 | [(set (reg:SI 3) | |
2157 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2158 | (set (reg:SI 4) | |
2159 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2160 | (clobber (match_scratch:SI 0 "=l")) | |
2161 | (clobber (reg:SI 0))] | |
2162 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2163 | "bla __divss" |
2164 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2165 | |
2166 | (define_insn "divus_call" | |
8ffd9c51 RK |
2167 | [(set (reg:SI 3) |
2168 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2169 | (set (reg:SI 4) | |
2170 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2171 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2172 | (clobber (reg:SI 0)) |
2173 | (clobber (match_scratch:CC 1 "=x")) | |
2174 | (clobber (reg:CC 69))] | |
2175 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2176 | "bla __divus" |
2177 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2178 | |
2179 | (define_insn "quoss_call" | |
2180 | [(set (reg:SI 3) | |
2181 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2182 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2183 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2184 | "bla __quoss" |
2185 | [(set_attr "type" "idiv")]) | |
0081a354 | 2186 | |
fada905b MM |
2187 | (define_insn "quous_call" |
2188 | [(set (reg:SI 3) | |
2189 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2190 | (clobber (match_scratch:SI 0 "=l")) | |
2191 | (clobber (reg:SI 0)) | |
2192 | (clobber (match_scratch:CC 1 "=x")) | |
2193 | (clobber (reg:CC 69))] | |
2194 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2195 | "bla __quous" |
2196 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2197 | \f |
bb21487f | 2198 | ;; Logical instructions |
dfbdccdb GK |
2199 | ;; The logical instructions are mostly combined by using match_operator, |
2200 | ;; but the plain AND insns are somewhat different because there is no | |
2201 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2202 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2203 | ||
29ae5b89 JL |
2204 | (define_insn "andsi3" |
2205 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2206 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2207 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2208 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2209 | "" |
2210 | "@ | |
2211 | and %0,%1,%2 | |
ca7f5001 RK |
2212 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2213 | {andil.|andi.} %0,%1,%b2 | |
9ebbca7d | 2214 | {andiu.|andis.} %0,%1,%u2") |
52d3af72 DE |
2215 | |
2216 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
0ba1b2ff | 2217 | ;; the test again -- this avoids a mfcr which on the higher end |
52d3af72 | 2218 | ;; machines causes an execution serialization |
1fd4e8c1 | 2219 | |
7cd5235b | 2220 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2221 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2222 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2223 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2224 | (const_int 0))) |
52d3af72 DE |
2225 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2226 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2227 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2228 | "@ |
2229 | and. %3,%1,%2 | |
ca7f5001 RK |
2230 | {andil.|andi.} %3,%1,%b2 |
2231 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2232 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2233 | # | |
2234 | # | |
2235 | # | |
2236 | #" | |
2237 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2238 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2239 | |
0ba1b2ff AM |
2240 | (define_insn "*andsi3_internal3" |
2241 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2242 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2243 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2244 | (const_int 0))) | |
2245 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) | |
2246 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
2247 | "TARGET_POWERPC64" | |
2248 | "@ | |
2249 | # | |
2250 | {andil.|andi.} %3,%1,%b2 | |
2251 | {andiu.|andis.} %3,%1,%u2 | |
2252 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 | |
2253 | # | |
2254 | # | |
2255 | # | |
2256 | #" | |
2257 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2258 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2259 | ||
52d3af72 DE |
2260 | (define_split |
2261 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2262 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2263 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 2264 | (const_int 0))) |
52d3af72 DE |
2265 | (clobber (match_scratch:SI 3 "")) |
2266 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2267 | "reload_completed" |
52d3af72 DE |
2268 | [(parallel [(set (match_dup 3) |
2269 | (and:SI (match_dup 1) | |
2270 | (match_dup 2))) | |
2271 | (clobber (match_dup 4))]) | |
2272 | (set (match_dup 0) | |
2273 | (compare:CC (match_dup 3) | |
2274 | (const_int 0)))] | |
2275 | "") | |
2276 | ||
0ba1b2ff AM |
2277 | ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the |
2278 | ;; whole 64 bit reg, and we don't know what is in the high 32 bits. | |
2279 | ||
2280 | (define_split | |
2281 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
2282 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2283 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2284 | (const_int 0))) | |
2285 | (clobber (match_scratch:SI 3 "")) | |
2286 | (clobber (match_scratch:CC 4 ""))] | |
2287 | "TARGET_POWERPC64 && reload_completed" | |
2288 | [(parallel [(set (match_dup 3) | |
2289 | (and:SI (match_dup 1) | |
2290 | (match_dup 2))) | |
2291 | (clobber (match_dup 4))]) | |
2292 | (set (match_dup 0) | |
2293 | (compare:CC (match_dup 3) | |
2294 | (const_int 0)))] | |
2295 | "") | |
2296 | ||
2297 | (define_insn "*andsi3_internal4" | |
52d3af72 DE |
2298 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2299 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2300 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2301 | (const_int 0))) |
2302 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2303 | (and:SI (match_dup 1) | |
2304 | (match_dup 2))) | |
2305 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2306 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2307 | "@ |
2308 | and. %0,%1,%2 | |
ca7f5001 RK |
2309 | {andil.|andi.} %0,%1,%b2 |
2310 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2311 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2312 | # | |
2313 | # | |
2314 | # | |
2315 | #" | |
2316 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2317 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2318 | ||
0ba1b2ff AM |
2319 | (define_insn "*andsi3_internal5" |
2320 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2321 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2322 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2323 | (const_int 0))) | |
2324 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2325 | (and:SI (match_dup 1) | |
2326 | (match_dup 2))) | |
2327 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
2328 | "TARGET_POWERPC64" | |
2329 | "@ | |
2330 | # | |
2331 | {andil.|andi.} %0,%1,%b2 | |
2332 | {andiu.|andis.} %0,%1,%u2 | |
2333 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 | |
2334 | # | |
2335 | # | |
2336 | # | |
2337 | #" | |
2338 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2339 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2340 | ||
52d3af72 DE |
2341 | (define_split |
2342 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2343 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2344 | (match_operand:SI 2 "and_operand" "")) | |
2345 | (const_int 0))) | |
2346 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2347 | (and:SI (match_dup 1) | |
2348 | (match_dup 2))) | |
2349 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2350 | "reload_completed" |
52d3af72 DE |
2351 | [(parallel [(set (match_dup 0) |
2352 | (and:SI (match_dup 1) | |
2353 | (match_dup 2))) | |
2354 | (clobber (match_dup 4))]) | |
2355 | (set (match_dup 3) | |
2356 | (compare:CC (match_dup 0) | |
2357 | (const_int 0)))] | |
2358 | "") | |
1fd4e8c1 | 2359 | |
0ba1b2ff AM |
2360 | (define_split |
2361 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
2362 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2363 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2364 | (const_int 0))) | |
2365 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2366 | (and:SI (match_dup 1) | |
2367 | (match_dup 2))) | |
2368 | (clobber (match_scratch:CC 4 ""))] | |
2369 | "TARGET_POWERPC64 && reload_completed" | |
2370 | [(parallel [(set (match_dup 0) | |
2371 | (and:SI (match_dup 1) | |
2372 | (match_dup 2))) | |
2373 | (clobber (match_dup 4))]) | |
2374 | (set (match_dup 3) | |
2375 | (compare:CC (match_dup 0) | |
2376 | (const_int 0)))] | |
2377 | "") | |
2378 | ||
2379 | ;; Handle the PowerPC64 rlwinm corner case | |
2380 | ||
2381 | (define_insn_and_split "*andsi3_internal6" | |
2382 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2383 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2384 | (match_operand:SI 2 "mask_operand_wrap" "i")))] | |
2385 | "TARGET_POWERPC64" | |
2386 | "#" | |
2387 | "TARGET_POWERPC64" | |
2388 | [(set (match_dup 0) | |
2389 | (and:SI (rotate:SI (match_dup 1) (match_dup 3)) | |
2390 | (match_dup 4))) | |
2391 | (set (match_dup 0) | |
2392 | (rotate:SI (match_dup 0) (match_dup 5)))] | |
2393 | " | |
2394 | { | |
2395 | int mb = extract_MB (operands[2]); | |
2396 | int me = extract_ME (operands[2]); | |
2397 | operands[3] = GEN_INT (me + 1); | |
2398 | operands[5] = GEN_INT (32 - (me + 1)); | |
2399 | operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2400 | }" | |
2401 | [(set_attr "length" "8")]) | |
2402 | ||
2403 | (define_insn_and_split "*andsi3_internal7" | |
2404 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") | |
2405 | (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r") | |
2406 | (match_operand:SI 1 "mask_operand_wrap" "i,i")) | |
2407 | (const_int 0))) | |
2408 | (clobber (match_scratch:SI 3 "=r,r"))] | |
2409 | "TARGET_POWERPC64" | |
2410 | "#" | |
2411 | "TARGET_POWERPC64" | |
2412 | [(parallel [(set (match_dup 2) | |
2413 | (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4)) | |
2414 | (match_dup 5)) | |
2415 | (const_int 0))) | |
2416 | (clobber (match_dup 3))])] | |
2417 | " | |
2418 | { | |
2419 | int mb = extract_MB (operands[1]); | |
2420 | int me = extract_ME (operands[1]); | |
2421 | operands[4] = GEN_INT (me + 1); | |
2422 | operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2423 | }" | |
2424 | [(set_attr "type" "delayed_compare,compare") | |
2425 | (set_attr "length" "4,8")]) | |
2426 | ||
2427 | (define_insn_and_split "*andsi3_internal8" | |
2428 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y") | |
2429 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2430 | (match_operand:SI 2 "mask_operand_wrap" "i,i")) | |
2431 | (const_int 0))) | |
2432 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
2433 | (and:SI (match_dup 1) | |
2434 | (match_dup 2)))] | |
2435 | "TARGET_POWERPC64" | |
2436 | "#" | |
2437 | "TARGET_POWERPC64" | |
2438 | [(parallel [(set (match_dup 3) | |
2439 | (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4)) | |
2440 | (match_dup 5)) | |
2441 | (const_int 0))) | |
2442 | (set (match_dup 0) | |
2443 | (and:SI (rotate:SI (match_dup 1) (match_dup 4)) | |
2444 | (match_dup 5)))]) | |
2445 | (set (match_dup 0) | |
2446 | (rotate:SI (match_dup 0) (match_dup 6)))] | |
2447 | " | |
2448 | { | |
2449 | int mb = extract_MB (operands[2]); | |
2450 | int me = extract_ME (operands[2]); | |
2451 | operands[4] = GEN_INT (me + 1); | |
2452 | operands[6] = GEN_INT (32 - (me + 1)); | |
2453 | operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2454 | }" | |
2455 | [(set_attr "type" "delayed_compare,compare") | |
2456 | (set_attr "length" "8,12")]) | |
2457 | ||
7cd5235b | 2458 | (define_expand "iorsi3" |
cd2b37d9 | 2459 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2460 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2461 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 2462 | "" |
f357808b RK |
2463 | " |
2464 | { | |
7cd5235b | 2465 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2466 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2467 | { |
2468 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2469 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2470 | ? operands[0] : gen_reg_rtx (SImode)); |
2471 | ||
a260abc9 DE |
2472 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2473 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2474 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2475 | DONE; |
2476 | } | |
f357808b RK |
2477 | }") |
2478 | ||
7cd5235b | 2479 | (define_expand "xorsi3" |
cd2b37d9 | 2480 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2481 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2482 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 2483 | "" |
7cd5235b | 2484 | " |
1fd4e8c1 | 2485 | { |
7cd5235b | 2486 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2487 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2488 | { |
2489 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2490 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2491 | ? operands[0] : gen_reg_rtx (SImode)); |
2492 | ||
a260abc9 DE |
2493 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2494 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2495 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2496 | DONE; |
2497 | } | |
1fd4e8c1 RK |
2498 | }") |
2499 | ||
dfbdccdb | 2500 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2501 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 2502 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2503 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
2504 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2505 | "" |
2506 | "@ | |
dfbdccdb GK |
2507 | %q3 %0,%1,%2 |
2508 | {%q3il|%q3i} %0,%1,%b2 | |
2509 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2510 | |
dfbdccdb | 2511 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2512 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 2513 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
2514 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
2515 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2516 | (const_int 0))) | |
52d3af72 | 2517 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2518 | "! TARGET_POWERPC64" |
52d3af72 | 2519 | "@ |
dfbdccdb | 2520 | %q4. %3,%1,%2 |
52d3af72 DE |
2521 | #" |
2522 | [(set_attr "type" "compare") | |
2523 | (set_attr "length" "4,8")]) | |
2524 | ||
2525 | (define_split | |
2526 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2527 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2528 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2529 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2530 | (const_int 0))) |
52d3af72 | 2531 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2532 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2533 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2534 | (set (match_dup 0) |
2535 | (compare:CC (match_dup 3) | |
2536 | (const_int 0)))] | |
2537 | "") | |
815cdc52 | 2538 | |
dfbdccdb | 2539 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2540 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2541 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2542 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2543 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2544 | (const_int 0))) | |
52d3af72 | 2545 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2546 | (match_dup 4))] |
0ad91047 | 2547 | "! TARGET_POWERPC64" |
52d3af72 | 2548 | "@ |
dfbdccdb | 2549 | %q4. %0,%1,%2 |
52d3af72 DE |
2550 | #" |
2551 | [(set_attr "type" "compare") | |
2552 | (set_attr "length" "4,8")]) | |
2553 | ||
2554 | (define_split | |
e72247f4 | 2555 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2556 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2557 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2558 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2559 | (const_int 0))) |
75540af0 | 2560 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2561 | (match_dup 4))] |
0ad91047 | 2562 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2563 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2564 | (set (match_dup 3) |
2565 | (compare:CC (match_dup 0) | |
2566 | (const_int 0)))] | |
2567 | "") | |
1fd4e8c1 | 2568 | |
5bdc5878 | 2569 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 2570 | ;; each of which does one 16-bit part. This is used by combine. |
a260abc9 DE |
2571 | |
2572 | (define_split | |
2573 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 2574 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2575 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2576 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 2577 | "" |
dfbdccdb GK |
2578 | [(set (match_dup 0) (match_dup 4)) |
2579 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
2580 | " |
2581 | { | |
dfbdccdb GK |
2582 | rtx i; |
2583 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
2584 | operands[4] = gen_rtx (GET_CODE (operands[3]), SImode, | |
2585 | operands[1], i); | |
2586 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
2587 | operands[5] = gen_rtx (GET_CODE (operands[3]), SImode, | |
2588 | operands[0], i); | |
a260abc9 DE |
2589 | }") |
2590 | ||
dfbdccdb | 2591 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 2592 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2593 | (match_operator:SI 3 "boolean_operator" |
2594 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2595 | (match_operand:SI 2 "gpc_reg_operand" "r")]))] |
1fd4e8c1 | 2596 | "" |
dfbdccdb | 2597 | "%q3 %0,%2,%1") |
1fd4e8c1 | 2598 | |
dfbdccdb | 2599 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 2600 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2601 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2602 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2603 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2604 | (const_int 0))) | |
52d3af72 | 2605 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2606 | "! TARGET_POWERPC64" |
52d3af72 | 2607 | "@ |
dfbdccdb | 2608 | %q4. %3,%2,%1 |
52d3af72 DE |
2609 | #" |
2610 | [(set_attr "type" "compare") | |
2611 | (set_attr "length" "4,8")]) | |
2612 | ||
2613 | (define_split | |
2614 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2615 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2616 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2617 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2618 | (const_int 0))) |
52d3af72 | 2619 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2620 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2621 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2622 | (set (match_dup 0) |
2623 | (compare:CC (match_dup 3) | |
2624 | (const_int 0)))] | |
2625 | "") | |
1fd4e8c1 | 2626 | |
dfbdccdb | 2627 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 2628 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2629 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2630 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2631 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2632 | (const_int 0))) | |
52d3af72 | 2633 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2634 | (match_dup 4))] |
0ad91047 | 2635 | "! TARGET_POWERPC64" |
52d3af72 | 2636 | "@ |
dfbdccdb | 2637 | %q4. %0,%2,%1 |
52d3af72 DE |
2638 | #" |
2639 | [(set_attr "type" "compare") | |
2640 | (set_attr "length" "4,8")]) | |
2641 | ||
2642 | (define_split | |
e72247f4 | 2643 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2644 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2645 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2646 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2647 | (const_int 0))) |
75540af0 | 2648 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2649 | (match_dup 4))] |
0ad91047 | 2650 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2651 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2652 | (set (match_dup 3) |
2653 | (compare:CC (match_dup 0) | |
2654 | (const_int 0)))] | |
2655 | "") | |
2656 | ||
dfbdccdb | 2657 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 2658 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2659 | (match_operator:SI 3 "boolean_operator" |
2660 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2661 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] |
1fd4e8c1 | 2662 | "" |
dfbdccdb | 2663 | "%q3 %0,%1,%2") |
1fd4e8c1 | 2664 | |
dfbdccdb | 2665 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 2666 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2667 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2668 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2669 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2670 | (const_int 0))) | |
52d3af72 | 2671 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2672 | "! TARGET_POWERPC64" |
52d3af72 | 2673 | "@ |
dfbdccdb | 2674 | %q4. %3,%1,%2 |
52d3af72 DE |
2675 | #" |
2676 | [(set_attr "type" "compare") | |
2677 | (set_attr "length" "4,8")]) | |
2678 | ||
2679 | (define_split | |
2680 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2681 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2682 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2683 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2684 | (const_int 0))) |
52d3af72 | 2685 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2686 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2687 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2688 | (set (match_dup 0) |
2689 | (compare:CC (match_dup 3) | |
2690 | (const_int 0)))] | |
2691 | "") | |
1fd4e8c1 | 2692 | |
dfbdccdb | 2693 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 2694 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2695 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2696 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2697 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2698 | (const_int 0))) | |
52d3af72 | 2699 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2700 | (match_dup 4))] |
0ad91047 | 2701 | "! TARGET_POWERPC64" |
52d3af72 | 2702 | "@ |
dfbdccdb | 2703 | %q4. %0,%1,%2 |
52d3af72 DE |
2704 | #" |
2705 | [(set_attr "type" "compare") | |
2706 | (set_attr "length" "4,8")]) | |
2707 | ||
2708 | (define_split | |
e72247f4 | 2709 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2710 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2711 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2712 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2713 | (const_int 0))) |
75540af0 | 2714 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2715 | (match_dup 4))] |
0ad91047 | 2716 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2717 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2718 | (set (match_dup 3) |
2719 | (compare:CC (match_dup 0) | |
2720 | (const_int 0)))] | |
2721 | "") | |
1fd4e8c1 RK |
2722 | |
2723 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2724 | ;; orders. Don't define forms that only set CR fields because these | |
2725 | ;; would modify an input register. | |
2726 | ||
7cd5235b | 2727 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2728 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2729 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2730 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2731 | (and:SI (match_dup 2) | |
cd2b37d9 | 2732 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2733 | "TARGET_POWER" |
01def764 | 2734 | "maskir %0,%3,%2") |
1fd4e8c1 | 2735 | |
7cd5235b | 2736 | (define_insn "*maskir_internal2" |
242e8072 | 2737 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2738 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2739 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2740 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2741 | (match_dup 2))))] |
ca7f5001 | 2742 | "TARGET_POWER" |
01def764 | 2743 | "maskir %0,%3,%2") |
1fd4e8c1 | 2744 | |
7cd5235b | 2745 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2746 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2747 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2748 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2749 | (and:SI (not:SI (match_dup 2)) |
2750 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2751 | "TARGET_POWER" |
01def764 | 2752 | "maskir %0,%3,%2") |
1fd4e8c1 | 2753 | |
7cd5235b | 2754 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2755 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2756 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2757 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2758 | (and:SI (not:SI (match_dup 2)) | |
2759 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2760 | "TARGET_POWER" |
01def764 | 2761 | "maskir %0,%3,%2") |
1fd4e8c1 | 2762 | |
7cd5235b | 2763 | (define_insn "*maskir_internal5" |
9ebbca7d | 2764 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2765 | (compare:CC |
9ebbca7d GK |
2766 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2767 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 2768 | (and:SI (match_dup 2) |
9ebbca7d | 2769 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 2770 | (const_int 0))) |
9ebbca7d | 2771 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2772 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2773 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2774 | "TARGET_POWER" |
9ebbca7d GK |
2775 | "@ |
2776 | maskir. %0,%3,%2 | |
2777 | #" | |
2778 | [(set_attr "type" "compare") | |
2779 | (set_attr "length" "4,8")]) | |
2780 | ||
2781 | (define_split | |
2782 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2783 | (compare:CC | |
2784 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2785 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2786 | (and:SI (match_dup 2) | |
2787 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
2788 | (const_int 0))) | |
2789 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2790 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2791 | (and:SI (match_dup 2) (match_dup 3))))] | |
2792 | "TARGET_POWER && reload_completed" | |
2793 | [(set (match_dup 0) | |
2794 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2795 | (and:SI (match_dup 2) (match_dup 3)))) | |
2796 | (set (match_dup 4) | |
2797 | (compare:CC (match_dup 0) | |
2798 | (const_int 0)))] | |
2799 | "") | |
1fd4e8c1 | 2800 | |
7cd5235b | 2801 | (define_insn "*maskir_internal6" |
9ebbca7d | 2802 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2803 | (compare:CC |
9ebbca7d GK |
2804 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2805 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
2806 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 2807 | (match_dup 2))) |
1fd4e8c1 | 2808 | (const_int 0))) |
9ebbca7d | 2809 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2810 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2811 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 2812 | "TARGET_POWER" |
9ebbca7d GK |
2813 | "@ |
2814 | maskir. %0,%3,%2 | |
2815 | #" | |
2816 | [(set_attr "type" "compare") | |
2817 | (set_attr "length" "4,8")]) | |
2818 | ||
2819 | (define_split | |
2820 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2821 | (compare:CC | |
2822 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2823 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2824 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2825 | (match_dup 2))) | |
2826 | (const_int 0))) | |
2827 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2828 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2829 | (and:SI (match_dup 3) (match_dup 2))))] | |
2830 | "TARGET_POWER && reload_completed" | |
2831 | [(set (match_dup 0) | |
2832 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2833 | (and:SI (match_dup 3) (match_dup 2)))) | |
2834 | (set (match_dup 4) | |
2835 | (compare:CC (match_dup 0) | |
2836 | (const_int 0)))] | |
2837 | "") | |
1fd4e8c1 | 2838 | |
7cd5235b | 2839 | (define_insn "*maskir_internal7" |
9ebbca7d | 2840 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 2841 | (compare:CC |
9ebbca7d GK |
2842 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
2843 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2844 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2845 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 2846 | (const_int 0))) |
9ebbca7d | 2847 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
2848 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
2849 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2850 | "TARGET_POWER" | |
9ebbca7d GK |
2851 | "@ |
2852 | maskir. %0,%3,%2 | |
2853 | #" | |
2854 | [(set_attr "type" "compare") | |
2855 | (set_attr "length" "4,8")]) | |
2856 | ||
2857 | (define_split | |
2858 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2859 | (compare:CC | |
2860 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
2861 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
2862 | (and:SI (not:SI (match_dup 2)) | |
2863 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2864 | (const_int 0))) | |
2865 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2866 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2867 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2868 | "TARGET_POWER && reload_completed" | |
2869 | [(set (match_dup 0) | |
2870 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2871 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2872 | (set (match_dup 4) | |
2873 | (compare:CC (match_dup 0) | |
2874 | (const_int 0)))] | |
2875 | "") | |
1fd4e8c1 | 2876 | |
7cd5235b | 2877 | (define_insn "*maskir_internal8" |
9ebbca7d | 2878 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2879 | (compare:CC |
9ebbca7d GK |
2880 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
2881 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 2882 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2883 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 2884 | (const_int 0))) |
9ebbca7d | 2885 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2886 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
2887 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 2888 | "TARGET_POWER" |
9ebbca7d GK |
2889 | "@ |
2890 | maskir. %0,%3,%2 | |
2891 | #" | |
2892 | [(set_attr "type" "compare") | |
2893 | (set_attr "length" "4,8")]) | |
fcce224d | 2894 | |
9ebbca7d GK |
2895 | (define_split |
2896 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2897 | (compare:CC | |
2898 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2899 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2900 | (and:SI (not:SI (match_dup 2)) | |
2901 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2902 | (const_int 0))) | |
2903 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2904 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2905 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2906 | "TARGET_POWER && reload_completed" | |
2907 | [(set (match_dup 0) | |
2908 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2909 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2910 | (set (match_dup 4) | |
2911 | (compare:CC (match_dup 0) | |
2912 | (const_int 0)))] | |
2913 | "") | |
fcce224d | 2914 | \f |
1fd4e8c1 RK |
2915 | ;; Rotate and shift insns, in all their variants. These support shifts, |
2916 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 2917 | (define_expand "insv" |
0ad91047 DE |
2918 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
2919 | (match_operand:SI 1 "const_int_operand" "") | |
2920 | (match_operand:SI 2 "const_int_operand" "")) | |
2921 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
2922 | "" |
2923 | " | |
2924 | { | |
2925 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2926 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2927 | compiler if the address of the structure is taken later. */ | |
2928 | if (GET_CODE (operands[0]) == SUBREG | |
2929 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2930 | FAIL; | |
a78e33fc DE |
2931 | |
2932 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
2933 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
2934 | else | |
2935 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
2936 | DONE; | |
034c1be0 MM |
2937 | }") |
2938 | ||
a78e33fc | 2939 | (define_insn "insvsi" |
cd2b37d9 | 2940 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
2941 | (match_operand:SI 1 "const_int_operand" "i") |
2942 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 2943 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
2944 | "" |
2945 | "* | |
2946 | { | |
2947 | int start = INTVAL (operands[2]) & 31; | |
2948 | int size = INTVAL (operands[1]) & 31; | |
2949 | ||
89e9f3a8 MM |
2950 | operands[4] = GEN_INT (32 - start - size); |
2951 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2952 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
1fd4e8c1 RK |
2953 | }") |
2954 | ||
a78e33fc | 2955 | (define_insn "*insvsi_internal1" |
d56d506a RK |
2956 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2957 | (match_operand:SI 1 "const_int_operand" "i") | |
2958 | (match_operand:SI 2 "const_int_operand" "i")) | |
2959 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2960 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2961 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2962 | "* |
2963 | { | |
2964 | int shift = INTVAL (operands[4]) & 31; | |
2965 | int start = INTVAL (operands[2]) & 31; | |
2966 | int size = INTVAL (operands[1]) & 31; | |
2967 | ||
89e9f3a8 MM |
2968 | operands[4] = GEN_INT (shift - start - size); |
2969 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2970 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
2971 | }") |
2972 | ||
a78e33fc | 2973 | (define_insn "*insvsi_internal2" |
d56d506a RK |
2974 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2975 | (match_operand:SI 1 "const_int_operand" "i") | |
2976 | (match_operand:SI 2 "const_int_operand" "i")) | |
2977 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2978 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2979 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2980 | "* |
2981 | { | |
2982 | int shift = INTVAL (operands[4]) & 31; | |
2983 | int start = INTVAL (operands[2]) & 31; | |
2984 | int size = INTVAL (operands[1]) & 31; | |
2985 | ||
89e9f3a8 MM |
2986 | operands[4] = GEN_INT (32 - shift - start - size); |
2987 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2988 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
2989 | }") |
2990 | ||
a78e33fc | 2991 | (define_insn "*insvsi_internal3" |
d56d506a RK |
2992 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2993 | (match_operand:SI 1 "const_int_operand" "i") | |
2994 | (match_operand:SI 2 "const_int_operand" "i")) | |
2995 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2996 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 2997 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2998 | "* |
2999 | { | |
3000 | int shift = INTVAL (operands[4]) & 31; | |
3001 | int start = INTVAL (operands[2]) & 31; | |
3002 | int size = INTVAL (operands[1]) & 31; | |
3003 | ||
89e9f3a8 MM |
3004 | operands[4] = GEN_INT (32 - shift - start - size); |
3005 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3006 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3007 | }") |
3008 | ||
a78e33fc | 3009 | (define_insn "*insvsi_internal4" |
d56d506a RK |
3010 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3011 | (match_operand:SI 1 "const_int_operand" "i") | |
3012 | (match_operand:SI 2 "const_int_operand" "i")) | |
3013 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3014 | (match_operand:SI 4 "const_int_operand" "i") | |
3015 | (match_operand:SI 5 "const_int_operand" "i")))] | |
3016 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
3017 | "* | |
3018 | { | |
3019 | int extract_start = INTVAL (operands[5]) & 31; | |
3020 | int extract_size = INTVAL (operands[4]) & 31; | |
3021 | int insert_start = INTVAL (operands[2]) & 31; | |
3022 | int insert_size = INTVAL (operands[1]) & 31; | |
3023 | ||
3024 | /* Align extract field with insert field */ | |
3a598fbe | 3025 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 3026 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 3027 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
d56d506a RK |
3028 | }") |
3029 | ||
a78e33fc | 3030 | (define_insn "insvdi" |
685f3906 | 3031 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3032 | (match_operand:SI 1 "const_int_operand" "i") |
3033 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3034 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3035 | "TARGET_POWERPC64" | |
3036 | "* | |
3037 | { | |
3038 | int start = INTVAL (operands[2]) & 63; | |
3039 | int size = INTVAL (operands[1]) & 63; | |
3040 | ||
a78e33fc DE |
3041 | operands[1] = GEN_INT (64 - start - size); |
3042 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3043 | }") |
3044 | ||
034c1be0 | 3045 | (define_expand "extzv" |
0ad91047 DE |
3046 | [(set (match_operand 0 "gpc_reg_operand" "") |
3047 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3048 | (match_operand:SI 2 "const_int_operand" "") | |
3049 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3050 | "" |
3051 | " | |
3052 | { | |
3053 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3054 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3055 | compiler if the address of the structure is taken later. */ | |
3056 | if (GET_CODE (operands[0]) == SUBREG | |
3057 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3058 | FAIL; | |
a78e33fc DE |
3059 | |
3060 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3061 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3062 | else | |
3063 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3064 | DONE; | |
034c1be0 MM |
3065 | }") |
3066 | ||
a78e33fc | 3067 | (define_insn "extzvsi" |
cd2b37d9 RK |
3068 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3069 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3070 | (match_operand:SI 2 "const_int_operand" "i") |
3071 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3072 | "" | |
3073 | "* | |
3074 | { | |
3075 | int start = INTVAL (operands[3]) & 31; | |
3076 | int size = INTVAL (operands[2]) & 31; | |
3077 | ||
3078 | if (start + size >= 32) | |
3079 | operands[3] = const0_rtx; | |
3080 | else | |
89e9f3a8 | 3081 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3082 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3083 | }") |
3084 | ||
a78e33fc | 3085 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3086 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3087 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3088 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3089 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3090 | (const_int 0))) |
9ebbca7d | 3091 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3092 | "" |
1fd4e8c1 RK |
3093 | "* |
3094 | { | |
3095 | int start = INTVAL (operands[3]) & 31; | |
3096 | int size = INTVAL (operands[2]) & 31; | |
3097 | ||
9ebbca7d GK |
3098 | /* Force split for non-cc0 compare. */ |
3099 | if (which_alternative == 1) | |
3100 | return \"#\"; | |
3101 | ||
43a88a8c | 3102 | /* If the bit-field being tested fits in the upper or lower half of a |
a7a975e1 RK |
3103 | word, it is possible to use andiu. or andil. to test it. This is |
3104 | useful because the condition register set-use delay is smaller for | |
3105 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3106 | position is 0 because the LT and GT bits may be set wrong. */ | |
3107 | ||
3108 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3109 | { |
3a598fbe | 3110 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3111 | - (1 << (16 - (start & 15) - size)))); |
3112 | if (start < 16) | |
ca7f5001 | 3113 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3114 | else |
ca7f5001 | 3115 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3116 | } |
7e69e155 | 3117 | |
1fd4e8c1 RK |
3118 | if (start + size >= 32) |
3119 | operands[3] = const0_rtx; | |
3120 | else | |
89e9f3a8 | 3121 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3122 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3123 | }" |
9ebbca7d GK |
3124 | [(set_attr "type" "compare") |
3125 | (set_attr "length" "4,8")]) | |
3126 | ||
3127 | (define_split | |
3128 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3129 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3130 | (match_operand:SI 2 "const_int_operand" "") | |
3131 | (match_operand:SI 3 "const_int_operand" "")) | |
3132 | (const_int 0))) | |
3133 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3134 | "reload_completed" |
9ebbca7d GK |
3135 | [(set (match_dup 4) |
3136 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3137 | (match_dup 3))) | |
3138 | (set (match_dup 0) | |
3139 | (compare:CC (match_dup 4) | |
3140 | (const_int 0)))] | |
3141 | "") | |
1fd4e8c1 | 3142 | |
a78e33fc | 3143 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3144 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3145 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3146 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3147 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3148 | (const_int 0))) |
9ebbca7d | 3149 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3150 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
ce71f754 | 3151 | "" |
1fd4e8c1 RK |
3152 | "* |
3153 | { | |
3154 | int start = INTVAL (operands[3]) & 31; | |
3155 | int size = INTVAL (operands[2]) & 31; | |
3156 | ||
9ebbca7d GK |
3157 | /* Force split for non-cc0 compare. */ |
3158 | if (which_alternative == 1) | |
3159 | return \"#\"; | |
3160 | ||
bc401279 | 3161 | /* Since we are using the output value, we can't ignore any need for |
43a88a8c | 3162 | a shift. The bit-field must end at the LSB. */ |
bc401279 | 3163 | if (start >= 16 && start + size == 32) |
df031c43 | 3164 | { |
bc401279 AM |
3165 | operands[3] = GEN_INT ((1 << size) - 1); |
3166 | return \"{andil.|andi.} %0,%1,%3\"; | |
df031c43 | 3167 | } |
7e69e155 | 3168 | |
1fd4e8c1 RK |
3169 | if (start + size >= 32) |
3170 | operands[3] = const0_rtx; | |
3171 | else | |
89e9f3a8 | 3172 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3173 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3174 | }" |
ce71f754 | 3175 | [(set_attr "type" "compare") |
9ebbca7d GK |
3176 | (set_attr "length" "4,8")]) |
3177 | ||
3178 | (define_split | |
3179 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3180 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3181 | (match_operand:SI 2 "const_int_operand" "") | |
3182 | (match_operand:SI 3 "const_int_operand" "")) | |
3183 | (const_int 0))) | |
3184 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3185 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
ce71f754 | 3186 | "reload_completed" |
9ebbca7d GK |
3187 | [(set (match_dup 0) |
3188 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3189 | (set (match_dup 4) | |
3190 | (compare:CC (match_dup 0) | |
3191 | (const_int 0)))] | |
3192 | "") | |
1fd4e8c1 | 3193 | |
a78e33fc | 3194 | (define_insn "extzvdi" |
685f3906 DE |
3195 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3196 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3197 | (match_operand:SI 2 "const_int_operand" "i") |
3198 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3199 | "TARGET_POWERPC64" |
3200 | "* | |
3201 | { | |
3202 | int start = INTVAL (operands[3]) & 63; | |
3203 | int size = INTVAL (operands[2]) & 63; | |
3204 | ||
3205 | if (start + size >= 64) | |
3206 | operands[3] = const0_rtx; | |
3207 | else | |
89e9f3a8 MM |
3208 | operands[3] = GEN_INT (start + size); |
3209 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3210 | return \"rldicl %0,%1,%3,%2\"; |
3211 | }") | |
3212 | ||
a78e33fc | 3213 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3214 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3215 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3216 | (match_operand:SI 2 "const_int_operand" "i") |
3217 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3218 | (const_int 0))) |
29ae5b89 | 3219 | (clobber (match_scratch:DI 4 "=r"))] |
685f3906 DE |
3220 | "TARGET_POWERPC64" |
3221 | "* | |
3222 | { | |
3223 | int start = INTVAL (operands[3]) & 63; | |
3224 | int size = INTVAL (operands[2]) & 63; | |
3225 | ||
3226 | if (start + size >= 64) | |
3227 | operands[3] = const0_rtx; | |
3228 | else | |
89e9f3a8 MM |
3229 | operands[3] = GEN_INT (start + size); |
3230 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3231 | return \"rldicl. %4,%1,%3,%2\"; |
3232 | }") | |
3233 | ||
a78e33fc | 3234 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3235 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3236 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3237 | (match_operand:SI 2 "const_int_operand" "i") |
3238 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3239 | (const_int 0))) |
29ae5b89 | 3240 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 DE |
3241 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
3242 | "TARGET_POWERPC64" | |
3243 | "* | |
3244 | { | |
3245 | int start = INTVAL (operands[3]) & 63; | |
3246 | int size = INTVAL (operands[2]) & 63; | |
3247 | ||
3248 | if (start + size >= 64) | |
3249 | operands[3] = const0_rtx; | |
3250 | else | |
89e9f3a8 MM |
3251 | operands[3] = GEN_INT (start + size); |
3252 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3253 | return \"rldicl. %0,%1,%3,%2\"; |
3254 | }") | |
3255 | ||
1fd4e8c1 | 3256 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3257 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3258 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3259 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3260 | "" | |
ca7f5001 | 3261 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3262 | |
a260abc9 | 3263 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3264 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3265 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3266 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3267 | (const_int 0))) |
9ebbca7d | 3268 | (clobber (match_scratch:SI 3 "=r,r"))] |
ce71f754 | 3269 | "" |
9ebbca7d GK |
3270 | "@ |
3271 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3272 | #" | |
3273 | [(set_attr "type" "delayed_compare") | |
3274 | (set_attr "length" "4,8")]) | |
3275 | ||
3276 | (define_split | |
3277 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3278 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3279 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3280 | (const_int 0))) | |
3281 | (clobber (match_scratch:SI 3 ""))] | |
ce71f754 | 3282 | "reload_completed" |
9ebbca7d GK |
3283 | [(set (match_dup 3) |
3284 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3285 | (set (match_dup 0) | |
3286 | (compare:CC (match_dup 3) | |
3287 | (const_int 0)))] | |
3288 | "") | |
1fd4e8c1 | 3289 | |
a260abc9 | 3290 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3291 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3292 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3293 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3294 | (const_int 0))) |
9ebbca7d | 3295 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3296 | (rotate:SI (match_dup 1) (match_dup 2)))] |
ce71f754 | 3297 | "" |
9ebbca7d GK |
3298 | "@ |
3299 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3300 | #" | |
3301 | [(set_attr "type" "delayed_compare") | |
3302 | (set_attr "length" "4,8")]) | |
3303 | ||
3304 | (define_split | |
3305 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3306 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3307 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3308 | (const_int 0))) | |
3309 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3310 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
ce71f754 | 3311 | "reload_completed" |
9ebbca7d GK |
3312 | [(set (match_dup 0) |
3313 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3314 | (set (match_dup 3) | |
3315 | (compare:CC (match_dup 0) | |
3316 | (const_int 0)))] | |
3317 | "") | |
1fd4e8c1 | 3318 | |
a260abc9 | 3319 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3320 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3321 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3322 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
ce71f754 | 3323 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3324 | "" |
ca7f5001 | 3325 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3326 | |
a260abc9 | 3327 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3328 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3329 | (compare:CC (and:SI |
9ebbca7d GK |
3330 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3331 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3332 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3333 | (const_int 0))) |
9ebbca7d | 3334 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3335 | "" |
9ebbca7d GK |
3336 | "@ |
3337 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3338 | #" | |
3339 | [(set_attr "type" "delayed_compare") | |
3340 | (set_attr "length" "4,8")]) | |
3341 | ||
3342 | (define_split | |
3343 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3344 | (compare:CC (and:SI | |
3345 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3346 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3347 | (match_operand:SI 3 "mask_operand" "")) | |
3348 | (const_int 0))) | |
3349 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3350 | "reload_completed" |
9ebbca7d GK |
3351 | [(set (match_dup 4) |
3352 | (and:SI (rotate:SI (match_dup 1) | |
3353 | (match_dup 2)) | |
3354 | (match_dup 3))) | |
3355 | (set (match_dup 0) | |
3356 | (compare:CC (match_dup 4) | |
3357 | (const_int 0)))] | |
3358 | "") | |
1fd4e8c1 | 3359 | |
a260abc9 | 3360 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3361 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3362 | (compare:CC (and:SI |
9ebbca7d GK |
3363 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3364 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3365 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3366 | (const_int 0))) |
9ebbca7d | 3367 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3368 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3369 | "" |
9ebbca7d GK |
3370 | "@ |
3371 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3372 | #" | |
3373 | [(set_attr "type" "delayed_compare") | |
3374 | (set_attr "length" "4,8")]) | |
3375 | ||
3376 | (define_split | |
3377 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3378 | (compare:CC (and:SI | |
3379 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3380 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3381 | (match_operand:SI 3 "mask_operand" "")) | |
3382 | (const_int 0))) | |
3383 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3384 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3385 | "reload_completed" |
9ebbca7d GK |
3386 | [(set (match_dup 0) |
3387 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3388 | (set (match_dup 4) | |
3389 | (compare:CC (match_dup 0) | |
3390 | (const_int 0)))] | |
3391 | "") | |
1fd4e8c1 | 3392 | |
a260abc9 | 3393 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3394 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3395 | (zero_extend:SI |
3396 | (subreg:QI | |
cd2b37d9 | 3397 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3398 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3399 | "" | |
ca7f5001 | 3400 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3401 | |
a260abc9 | 3402 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3403 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3404 | (compare:CC (zero_extend:SI |
3405 | (subreg:QI | |
9ebbca7d GK |
3406 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3407 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3408 | (const_int 0))) |
9ebbca7d | 3409 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3410 | "" |
9ebbca7d GK |
3411 | "@ |
3412 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3413 | #" | |
3414 | [(set_attr "type" "delayed_compare") | |
3415 | (set_attr "length" "4,8")]) | |
3416 | ||
3417 | (define_split | |
3418 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3419 | (compare:CC (zero_extend:SI | |
3420 | (subreg:QI | |
3421 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3422 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3423 | (const_int 0))) | |
3424 | (clobber (match_scratch:SI 3 ""))] | |
3425 | "reload_completed" | |
3426 | [(set (match_dup 3) | |
3427 | (zero_extend:SI (subreg:QI | |
3428 | (rotate:SI (match_dup 1) | |
3429 | (match_dup 2)) 0))) | |
3430 | (set (match_dup 0) | |
3431 | (compare:CC (match_dup 3) | |
3432 | (const_int 0)))] | |
3433 | "") | |
1fd4e8c1 | 3434 | |
a260abc9 | 3435 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3436 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3437 | (compare:CC (zero_extend:SI |
3438 | (subreg:QI | |
9ebbca7d GK |
3439 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3440 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3441 | (const_int 0))) |
9ebbca7d | 3442 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3443 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3444 | "" | |
9ebbca7d GK |
3445 | "@ |
3446 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3447 | #" | |
3448 | [(set_attr "type" "delayed_compare") | |
3449 | (set_attr "length" "4,8")]) | |
3450 | ||
3451 | (define_split | |
3452 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3453 | (compare:CC (zero_extend:SI | |
3454 | (subreg:QI | |
3455 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3456 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3457 | (const_int 0))) | |
3458 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3459 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3460 | "reload_completed" | |
3461 | [(set (match_dup 0) | |
3462 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3463 | (set (match_dup 3) | |
3464 | (compare:CC (match_dup 0) | |
3465 | (const_int 0)))] | |
3466 | "") | |
1fd4e8c1 | 3467 | |
a260abc9 | 3468 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3469 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3470 | (zero_extend:SI |
3471 | (subreg:HI | |
cd2b37d9 | 3472 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3473 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3474 | "" | |
ca7f5001 | 3475 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3476 | |
a260abc9 | 3477 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3478 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3479 | (compare:CC (zero_extend:SI |
3480 | (subreg:HI | |
9ebbca7d GK |
3481 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3482 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3483 | (const_int 0))) |
9ebbca7d | 3484 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3485 | "" |
9ebbca7d GK |
3486 | "@ |
3487 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3488 | #" | |
3489 | [(set_attr "type" "delayed_compare") | |
3490 | (set_attr "length" "4,8")]) | |
3491 | ||
3492 | (define_split | |
3493 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3494 | (compare:CC (zero_extend:SI | |
3495 | (subreg:HI | |
3496 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3497 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3498 | (const_int 0))) | |
3499 | (clobber (match_scratch:SI 3 ""))] | |
3500 | "reload_completed" | |
3501 | [(set (match_dup 3) | |
3502 | (zero_extend:SI (subreg:HI | |
3503 | (rotate:SI (match_dup 1) | |
3504 | (match_dup 2)) 0))) | |
3505 | (set (match_dup 0) | |
3506 | (compare:CC (match_dup 3) | |
3507 | (const_int 0)))] | |
3508 | "") | |
1fd4e8c1 | 3509 | |
a260abc9 | 3510 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3511 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3512 | (compare:CC (zero_extend:SI |
3513 | (subreg:HI | |
9ebbca7d GK |
3514 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3515 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3516 | (const_int 0))) |
9ebbca7d | 3517 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3518 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3519 | "" | |
9ebbca7d GK |
3520 | "@ |
3521 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3522 | #" | |
3523 | [(set_attr "type" "delayed_compare") | |
3524 | (set_attr "length" "4,8")]) | |
3525 | ||
3526 | (define_split | |
3527 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3528 | (compare:CC (zero_extend:SI | |
3529 | (subreg:HI | |
3530 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3531 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3532 | (const_int 0))) | |
3533 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3534 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3535 | "reload_completed" | |
3536 | [(set (match_dup 0) | |
3537 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3538 | (set (match_dup 3) | |
3539 | (compare:CC (match_dup 0) | |
3540 | (const_int 0)))] | |
3541 | "") | |
1fd4e8c1 RK |
3542 | |
3543 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3544 | ;; SHIFT_COUNT_TRUNCATED. | |
3545 | ||
ca7f5001 RK |
3546 | (define_expand "ashlsi3" |
3547 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3548 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3549 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3550 | "" | |
3551 | " | |
3552 | { | |
3553 | if (TARGET_POWER) | |
3554 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3555 | else | |
25c341fa | 3556 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3557 | DONE; |
3558 | }") | |
3559 | ||
3560 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3561 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3562 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3563 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3564 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3565 | "TARGET_POWER" |
1fd4e8c1 RK |
3566 | "@ |
3567 | sle %0,%1,%2 | |
9ebbca7d | 3568 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3569 | |
25c341fa | 3570 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3571 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3572 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3573 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3574 | "! TARGET_POWER" |
9ebbca7d | 3575 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3576 | |
3577 | (define_insn "" | |
9ebbca7d GK |
3578 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3579 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3580 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3581 | (const_int 0))) |
9ebbca7d GK |
3582 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
3583 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 3584 | "TARGET_POWER" |
1fd4e8c1 RK |
3585 | "@ |
3586 | sle. %3,%1,%2 | |
9ebbca7d GK |
3587 | {sli.|slwi.} %3,%1,%h2 |
3588 | # | |
3589 | #" | |
3590 | [(set_attr "type" "delayed_compare") | |
3591 | (set_attr "length" "4,4,8,8")]) | |
3592 | ||
3593 | (define_split | |
3594 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3595 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3596 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3597 | (const_int 0))) | |
3598 | (clobber (match_scratch:SI 3 "")) | |
3599 | (clobber (match_scratch:SI 4 ""))] | |
3600 | "TARGET_POWER && reload_completed" | |
3601 | [(parallel [(set (match_dup 3) | |
3602 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3603 | (clobber (match_dup 4))]) | |
3604 | (set (match_dup 0) | |
3605 | (compare:CC (match_dup 3) | |
3606 | (const_int 0)))] | |
3607 | "") | |
25c341fa | 3608 | |
ca7f5001 | 3609 | (define_insn "" |
9ebbca7d GK |
3610 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3611 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3612 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3613 | (const_int 0))) |
9ebbca7d | 3614 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3615 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
3616 | "@ |
3617 | {sl|slw}%I2. %3,%1,%h2 | |
3618 | #" | |
3619 | [(set_attr "type" "delayed_compare") | |
3620 | (set_attr "length" "4,8")]) | |
3621 | ||
3622 | (define_split | |
3623 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3624 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3625 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3626 | (const_int 0))) | |
3627 | (clobber (match_scratch:SI 3 ""))] | |
3628 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3629 | [(set (match_dup 3) | |
3630 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3631 | (set (match_dup 0) | |
3632 | (compare:CC (match_dup 3) | |
3633 | (const_int 0)))] | |
3634 | "") | |
1fd4e8c1 RK |
3635 | |
3636 | (define_insn "" | |
9ebbca7d GK |
3637 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3638 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3639 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3640 | (const_int 0))) |
9ebbca7d | 3641 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 3642 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3643 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 3644 | "TARGET_POWER" |
1fd4e8c1 RK |
3645 | "@ |
3646 | sle. %0,%1,%2 | |
9ebbca7d GK |
3647 | {sli.|slwi.} %0,%1,%h2 |
3648 | # | |
3649 | #" | |
3650 | [(set_attr "type" "delayed_compare") | |
3651 | (set_attr "length" "4,4,8,8")]) | |
3652 | ||
3653 | (define_split | |
3654 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3655 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3656 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3657 | (const_int 0))) | |
3658 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3659 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3660 | (clobber (match_scratch:SI 4 ""))] | |
3661 | "TARGET_POWER && reload_completed" | |
3662 | [(parallel [(set (match_dup 0) | |
3663 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3664 | (clobber (match_dup 4))]) | |
3665 | (set (match_dup 3) | |
3666 | (compare:CC (match_dup 0) | |
3667 | (const_int 0)))] | |
3668 | "") | |
25c341fa | 3669 | |
ca7f5001 | 3670 | (define_insn "" |
9ebbca7d GK |
3671 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3672 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3673 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3674 | (const_int 0))) |
9ebbca7d | 3675 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 3676 | (ashift:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3677 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
3678 | "@ |
3679 | {sl|slw}%I2. %0,%1,%h2 | |
3680 | #" | |
3681 | [(set_attr "type" "delayed_compare") | |
3682 | (set_attr "length" "4,8")]) | |
3683 | ||
3684 | (define_split | |
3685 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3686 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3687 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3688 | (const_int 0))) | |
3689 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3690 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
3691 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3692 | [(set (match_dup 0) | |
3693 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3694 | (set (match_dup 3) | |
3695 | (compare:CC (match_dup 0) | |
3696 | (const_int 0)))] | |
3697 | "") | |
1fd4e8c1 RK |
3698 | |
3699 | (define_insn "" | |
cd2b37d9 RK |
3700 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3701 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3702 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3703 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3704 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 3705 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3706 | |
3707 | (define_insn "" | |
9ebbca7d | 3708 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3709 | (compare:CC |
9ebbca7d GK |
3710 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3711 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3712 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3713 | (const_int 0))) |
9ebbca7d | 3714 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3715 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3716 | "@ |
3717 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
3718 | #" | |
3719 | [(set_attr "type" "delayed_compare") | |
3720 | (set_attr "length" "4,8")]) | |
3721 | ||
3722 | (define_split | |
3723 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3724 | (compare:CC | |
3725 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3726 | (match_operand:SI 2 "const_int_operand" "")) | |
3727 | (match_operand:SI 3 "mask_operand" "")) | |
3728 | (const_int 0))) | |
3729 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3730 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3731 | [(set (match_dup 4) |
3732 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
3733 | (match_dup 3))) | |
3734 | (set (match_dup 0) | |
3735 | (compare:CC (match_dup 4) | |
3736 | (const_int 0)))] | |
3737 | "") | |
1fd4e8c1 RK |
3738 | |
3739 | (define_insn "" | |
9ebbca7d | 3740 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3741 | (compare:CC |
9ebbca7d GK |
3742 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3743 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3744 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3745 | (const_int 0))) |
9ebbca7d | 3746 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3747 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3748 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3749 | "@ |
3750 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
3751 | #" | |
3752 | [(set_attr "type" "delayed_compare") | |
3753 | (set_attr "length" "4,8")]) | |
3754 | ||
3755 | (define_split | |
3756 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3757 | (compare:CC | |
3758 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3759 | (match_operand:SI 2 "const_int_operand" "")) | |
3760 | (match_operand:SI 3 "mask_operand" "")) | |
3761 | (const_int 0))) | |
3762 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3763 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3764 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3765 | [(set (match_dup 0) |
3766 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3767 | (set (match_dup 4) | |
3768 | (compare:CC (match_dup 0) | |
3769 | (const_int 0)))] | |
3770 | "") | |
1fd4e8c1 | 3771 | |
ca7f5001 | 3772 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3773 | ;; "sli x,x,0". |
ca7f5001 RK |
3774 | (define_expand "lshrsi3" |
3775 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3776 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3777 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3778 | "" | |
3779 | " | |
3780 | { | |
3781 | if (TARGET_POWER) | |
3782 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
3783 | else | |
25c341fa | 3784 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3785 | DONE; |
3786 | }") | |
3787 | ||
3788 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
3789 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
3790 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3791 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
3792 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 3793 | "TARGET_POWER" |
1fd4e8c1 RK |
3794 | "@ |
3795 | sre %0,%1,%2 | |
bdf423cb | 3796 | mr %0,%1 |
ca7f5001 RK |
3797 | {s%A2i|s%A2wi} %0,%1,%h2") |
3798 | ||
25c341fa | 3799 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
3800 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3801 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3802 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 3803 | "! TARGET_POWER" |
bdf423cb MM |
3804 | "@ |
3805 | mr %0,%1 | |
3806 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
3807 | |
3808 | (define_insn "" | |
9ebbca7d GK |
3809 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
3810 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3811 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3812 | (const_int 0))) |
9ebbca7d GK |
3813 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
3814 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 3815 | "TARGET_POWER" |
1fd4e8c1 | 3816 | "@ |
29ae5b89 JL |
3817 | sre. %3,%1,%2 |
3818 | mr. %1,%1 | |
9ebbca7d GK |
3819 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
3820 | # | |
3821 | # | |
3822 | #" | |
3823 | [(set_attr "type" "delayed_compare") | |
3824 | (set_attr "length" "4,4,4,8,8,8")]) | |
3825 | ||
3826 | (define_split | |
3827 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3828 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3829 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3830 | (const_int 0))) | |
3831 | (clobber (match_scratch:SI 3 "")) | |
3832 | (clobber (match_scratch:SI 4 ""))] | |
3833 | "TARGET_POWER && reload_completed" | |
3834 | [(parallel [(set (match_dup 3) | |
3835 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3836 | (clobber (match_dup 4))]) | |
3837 | (set (match_dup 0) | |
3838 | (compare:CC (match_dup 3) | |
3839 | (const_int 0)))] | |
3840 | "") | |
ca7f5001 RK |
3841 | |
3842 | (define_insn "" | |
9ebbca7d GK |
3843 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3844 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3845 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 3846 | (const_int 0))) |
9ebbca7d | 3847 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
0ad91047 | 3848 | "! TARGET_POWER && ! TARGET_POWERPC64" |
bdf423cb MM |
3849 | "@ |
3850 | mr. %1,%1 | |
9ebbca7d GK |
3851 | {sr|srw}%I2. %3,%1,%h2 |
3852 | # | |
3853 | #" | |
3854 | [(set_attr "type" "delayed_compare") | |
3855 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 3856 | |
9ebbca7d GK |
3857 | (define_split |
3858 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3859 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3860 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3861 | (const_int 0))) | |
3862 | (clobber (match_scratch:SI 3 ""))] | |
3863 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3864 | [(set (match_dup 3) | |
3865 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3866 | (set (match_dup 0) | |
3867 | (compare:CC (match_dup 3) | |
3868 | (const_int 0)))] | |
3869 | "") | |
3870 | ||
3871 | (define_insn "" | |
3872 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
3873 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3874 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3875 | (const_int 0))) |
9ebbca7d | 3876 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 3877 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3878 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 3879 | "TARGET_POWER" |
1fd4e8c1 | 3880 | "@ |
29ae5b89 JL |
3881 | sre. %0,%1,%2 |
3882 | mr. %0,%1 | |
9ebbca7d GK |
3883 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
3884 | # | |
3885 | # | |
3886 | #" | |
3887 | [(set_attr "type" "delayed_compare") | |
3888 | (set_attr "length" "4,4,4,8,8,8")]) | |
3889 | ||
3890 | (define_split | |
3891 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3892 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3893 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3894 | (const_int 0))) | |
3895 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3896 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3897 | (clobber (match_scratch:SI 4 ""))] | |
3898 | "TARGET_POWER && reload_completed" | |
3899 | [(parallel [(set (match_dup 0) | |
3900 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3901 | (clobber (match_dup 4))]) | |
3902 | (set (match_dup 3) | |
3903 | (compare:CC (match_dup 0) | |
3904 | (const_int 0)))] | |
3905 | "") | |
ca7f5001 RK |
3906 | |
3907 | (define_insn "" | |
9ebbca7d GK |
3908 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3909 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3910 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 3911 | (const_int 0))) |
9ebbca7d | 3912 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 3913 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3914 | "! TARGET_POWER && ! TARGET_POWERPC64" |
29ae5b89 JL |
3915 | "@ |
3916 | mr. %0,%1 | |
9ebbca7d GK |
3917 | {sr|srw}%I2. %0,%1,%h2 |
3918 | # | |
3919 | #" | |
3920 | [(set_attr "type" "delayed_compare") | |
3921 | (set_attr "length" "4,4,8,8")]) | |
3922 | ||
3923 | (define_split | |
3924 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3925 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3926 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3927 | (const_int 0))) | |
3928 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3929 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
3930 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3931 | [(set (match_dup 0) | |
3932 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3933 | (set (match_dup 3) | |
3934 | (compare:CC (match_dup 0) | |
3935 | (const_int 0)))] | |
3936 | "") | |
1fd4e8c1 RK |
3937 | |
3938 | (define_insn "" | |
cd2b37d9 RK |
3939 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3940 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3941 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3942 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3943 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 3944 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
3945 | |
3946 | (define_insn "" | |
9ebbca7d | 3947 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3948 | (compare:CC |
9ebbca7d GK |
3949 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3950 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3951 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3952 | (const_int 0))) |
9ebbca7d | 3953 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3954 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3955 | "@ |
3956 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
3957 | #" | |
3958 | [(set_attr "type" "delayed_compare") | |
3959 | (set_attr "length" "4,8")]) | |
3960 | ||
3961 | (define_split | |
3962 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3963 | (compare:CC | |
3964 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3965 | (match_operand:SI 2 "const_int_operand" "")) | |
3966 | (match_operand:SI 3 "mask_operand" "")) | |
3967 | (const_int 0))) | |
3968 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3969 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3970 | [(set (match_dup 4) |
3971 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
3972 | (match_dup 3))) | |
3973 | (set (match_dup 0) | |
3974 | (compare:CC (match_dup 4) | |
3975 | (const_int 0)))] | |
3976 | "") | |
1fd4e8c1 RK |
3977 | |
3978 | (define_insn "" | |
9ebbca7d | 3979 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3980 | (compare:CC |
9ebbca7d GK |
3981 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3982 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3983 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3984 | (const_int 0))) |
9ebbca7d | 3985 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3986 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3987 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3988 | "@ |
3989 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
3990 | #" | |
3991 | [(set_attr "type" "delayed_compare") | |
3992 | (set_attr "length" "4,8")]) | |
3993 | ||
3994 | (define_split | |
3995 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3996 | (compare:CC | |
3997 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3998 | (match_operand:SI 2 "const_int_operand" "")) | |
3999 | (match_operand:SI 3 "mask_operand" "")) | |
4000 | (const_int 0))) | |
4001 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4002 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 4003 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4004 | [(set (match_dup 0) |
4005 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4006 | (set (match_dup 4) | |
4007 | (compare:CC (match_dup 0) | |
4008 | (const_int 0)))] | |
4009 | "") | |
1fd4e8c1 RK |
4010 | |
4011 | (define_insn "" | |
cd2b37d9 | 4012 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4013 | (zero_extend:SI |
4014 | (subreg:QI | |
cd2b37d9 | 4015 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4016 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4017 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4018 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4019 | |
4020 | (define_insn "" | |
9ebbca7d | 4021 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4022 | (compare:CC |
4023 | (zero_extend:SI | |
4024 | (subreg:QI | |
9ebbca7d GK |
4025 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4026 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4027 | (const_int 0))) |
9ebbca7d | 4028 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4029 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4030 | "@ |
4031 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4032 | #" | |
4033 | [(set_attr "type" "delayed_compare") | |
4034 | (set_attr "length" "4,8")]) | |
4035 | ||
4036 | (define_split | |
4037 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4038 | (compare:CC | |
4039 | (zero_extend:SI | |
4040 | (subreg:QI | |
4041 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4042 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4043 | (const_int 0))) | |
4044 | (clobber (match_scratch:SI 3 ""))] | |
4045 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4046 | [(set (match_dup 3) | |
4047 | (zero_extend:SI (subreg:QI | |
4048 | (lshiftrt:SI (match_dup 1) | |
4049 | (match_dup 2)) 0))) | |
4050 | (set (match_dup 0) | |
4051 | (compare:CC (match_dup 3) | |
4052 | (const_int 0)))] | |
4053 | "") | |
1fd4e8c1 RK |
4054 | |
4055 | (define_insn "" | |
9ebbca7d | 4056 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4057 | (compare:CC |
4058 | (zero_extend:SI | |
4059 | (subreg:QI | |
9ebbca7d GK |
4060 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4061 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4062 | (const_int 0))) |
9ebbca7d | 4063 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4064 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4065 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4066 | "@ |
4067 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4068 | #" | |
4069 | [(set_attr "type" "delayed_compare") | |
4070 | (set_attr "length" "4,8")]) | |
4071 | ||
4072 | (define_split | |
4073 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4074 | (compare:CC | |
4075 | (zero_extend:SI | |
4076 | (subreg:QI | |
4077 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4078 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4079 | (const_int 0))) | |
4080 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4081 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4082 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4083 | [(set (match_dup 0) | |
4084 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4085 | (set (match_dup 3) | |
4086 | (compare:CC (match_dup 0) | |
4087 | (const_int 0)))] | |
4088 | "") | |
1fd4e8c1 RK |
4089 | |
4090 | (define_insn "" | |
cd2b37d9 | 4091 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4092 | (zero_extend:SI |
4093 | (subreg:HI | |
cd2b37d9 | 4094 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4095 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4096 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4097 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4098 | |
4099 | (define_insn "" | |
9ebbca7d | 4100 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4101 | (compare:CC |
4102 | (zero_extend:SI | |
4103 | (subreg:HI | |
9ebbca7d GK |
4104 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4105 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4106 | (const_int 0))) |
9ebbca7d | 4107 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4108 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4109 | "@ |
4110 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4111 | #" | |
4112 | [(set_attr "type" "delayed_compare") | |
4113 | (set_attr "length" "4,8")]) | |
4114 | ||
4115 | (define_split | |
4116 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4117 | (compare:CC | |
4118 | (zero_extend:SI | |
4119 | (subreg:HI | |
4120 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4121 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4122 | (const_int 0))) | |
4123 | (clobber (match_scratch:SI 3 ""))] | |
4124 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4125 | [(set (match_dup 3) | |
4126 | (zero_extend:SI (subreg:HI | |
4127 | (lshiftrt:SI (match_dup 1) | |
4128 | (match_dup 2)) 0))) | |
4129 | (set (match_dup 0) | |
4130 | (compare:CC (match_dup 3) | |
4131 | (const_int 0)))] | |
4132 | "") | |
1fd4e8c1 RK |
4133 | |
4134 | (define_insn "" | |
9ebbca7d | 4135 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4136 | (compare:CC |
4137 | (zero_extend:SI | |
4138 | (subreg:HI | |
9ebbca7d GK |
4139 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4140 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4141 | (const_int 0))) |
9ebbca7d | 4142 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4143 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4144 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4145 | "@ |
4146 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4147 | #" | |
4148 | [(set_attr "type" "delayed_compare") | |
4149 | (set_attr "length" "4,8")]) | |
4150 | ||
4151 | (define_split | |
4152 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4153 | (compare:CC | |
4154 | (zero_extend:SI | |
4155 | (subreg:HI | |
4156 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4157 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4158 | (const_int 0))) | |
4159 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4160 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4161 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4162 | [(set (match_dup 0) | |
4163 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4164 | (set (match_dup 3) | |
4165 | (compare:CC (match_dup 0) | |
4166 | (const_int 0)))] | |
4167 | "") | |
1fd4e8c1 RK |
4168 | |
4169 | (define_insn "" | |
cd2b37d9 | 4170 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4171 | (const_int 1) |
cd2b37d9 RK |
4172 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4173 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4174 | (const_int 31)))] |
ca7f5001 | 4175 | "TARGET_POWER" |
1fd4e8c1 RK |
4176 | "rrib %0,%1,%2") |
4177 | ||
4178 | (define_insn "" | |
cd2b37d9 | 4179 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4180 | (const_int 1) |
cd2b37d9 RK |
4181 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4182 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4183 | (const_int 31)))] |
ca7f5001 | 4184 | "TARGET_POWER" |
1fd4e8c1 RK |
4185 | "rrib %0,%1,%2") |
4186 | ||
4187 | (define_insn "" | |
cd2b37d9 | 4188 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4189 | (const_int 1) |
cd2b37d9 RK |
4190 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4191 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4192 | (const_int 1) |
4193 | (const_int 0)))] | |
ca7f5001 | 4194 | "TARGET_POWER" |
1fd4e8c1 RK |
4195 | "rrib %0,%1,%2") |
4196 | ||
ca7f5001 RK |
4197 | (define_expand "ashrsi3" |
4198 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4199 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4200 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4201 | "" | |
4202 | " | |
4203 | { | |
4204 | if (TARGET_POWER) | |
4205 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4206 | else | |
25c341fa | 4207 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4208 | DONE; |
4209 | }") | |
4210 | ||
4211 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4212 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4213 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4214 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4215 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4216 | "TARGET_POWER" |
1fd4e8c1 RK |
4217 | "@ |
4218 | srea %0,%1,%2 | |
ca7f5001 RK |
4219 | {srai|srawi} %0,%1,%h2") |
4220 | ||
25c341fa | 4221 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4222 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4223 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4224 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4225 | "! TARGET_POWER" |
d904e9ed | 4226 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4227 | |
4228 | (define_insn "" | |
9ebbca7d GK |
4229 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4230 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4231 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4232 | (const_int 0))) |
9ebbca7d GK |
4233 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4234 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4235 | "TARGET_POWER" |
1fd4e8c1 RK |
4236 | "@ |
4237 | srea. %3,%1,%2 | |
9ebbca7d GK |
4238 | {srai.|srawi.} %3,%1,%h2 |
4239 | # | |
4240 | #" | |
4241 | [(set_attr "type" "delayed_compare") | |
4242 | (set_attr "length" "4,4,8,8")]) | |
4243 | ||
4244 | (define_split | |
4245 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4246 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4247 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4248 | (const_int 0))) | |
4249 | (clobber (match_scratch:SI 3 "")) | |
4250 | (clobber (match_scratch:SI 4 ""))] | |
4251 | "TARGET_POWER && reload_completed" | |
4252 | [(parallel [(set (match_dup 3) | |
4253 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4254 | (clobber (match_dup 4))]) | |
4255 | (set (match_dup 0) | |
4256 | (compare:CC (match_dup 3) | |
4257 | (const_int 0)))] | |
4258 | "") | |
ca7f5001 RK |
4259 | |
4260 | (define_insn "" | |
9ebbca7d GK |
4261 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4262 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4263 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4264 | (const_int 0))) |
9ebbca7d | 4265 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4266 | "! TARGET_POWER" |
9ebbca7d GK |
4267 | "@ |
4268 | {sra|sraw}%I2. %3,%1,%h2 | |
4269 | #" | |
4270 | [(set_attr "type" "delayed_compare") | |
4271 | (set_attr "length" "4,8")]) | |
4272 | ||
4273 | (define_split | |
4274 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4275 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4276 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4277 | (const_int 0))) | |
4278 | (clobber (match_scratch:SI 3 ""))] | |
4279 | "! TARGET_POWER && reload_completed" | |
4280 | [(set (match_dup 3) | |
4281 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4282 | (set (match_dup 0) | |
4283 | (compare:CC (match_dup 3) | |
4284 | (const_int 0)))] | |
4285 | "") | |
1fd4e8c1 RK |
4286 | |
4287 | (define_insn "" | |
9ebbca7d GK |
4288 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4289 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4290 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4291 | (const_int 0))) |
9ebbca7d | 4292 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4293 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4294 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4295 | "TARGET_POWER" |
1fd4e8c1 RK |
4296 | "@ |
4297 | srea. %0,%1,%2 | |
9ebbca7d GK |
4298 | {srai.|srawi.} %0,%1,%h2 |
4299 | # | |
4300 | #" | |
4301 | [(set_attr "type" "delayed_compare") | |
4302 | (set_attr "length" "4,4,8,8")]) | |
4303 | ||
4304 | (define_split | |
4305 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4306 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4307 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4308 | (const_int 0))) | |
4309 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4310 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4311 | (clobber (match_scratch:SI 4 ""))] | |
4312 | "TARGET_POWER && reload_completed" | |
4313 | [(parallel [(set (match_dup 0) | |
4314 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4315 | (clobber (match_dup 4))]) | |
4316 | (set (match_dup 3) | |
4317 | (compare:CC (match_dup 0) | |
4318 | (const_int 0)))] | |
4319 | "") | |
1fd4e8c1 | 4320 | |
ca7f5001 | 4321 | (define_insn "" |
9ebbca7d GK |
4322 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4323 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4324 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4325 | (const_int 0))) |
9ebbca7d | 4326 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4327 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4328 | "! TARGET_POWER" |
9ebbca7d GK |
4329 | "@ |
4330 | {sra|sraw}%I2. %0,%1,%h2 | |
4331 | #" | |
4332 | [(set_attr "type" "delayed_compare") | |
4333 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4334 | \f |
9ebbca7d GK |
4335 | (define_split |
4336 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4337 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4338 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4339 | (const_int 0))) | |
4340 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4341 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4342 | "! TARGET_POWER && reload_completed" | |
4343 | [(set (match_dup 0) | |
4344 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4345 | (set (match_dup 3) | |
4346 | (compare:CC (match_dup 0) | |
4347 | (const_int 0)))] | |
4348 | "") | |
4349 | ||
1fd4e8c1 RK |
4350 | ;; Floating-point insns, excluding normal data motion. |
4351 | ;; | |
ca7f5001 RK |
4352 | ;; PowerPC has a full set of single-precision floating point instructions. |
4353 | ;; | |
4354 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4355 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4356 | ;; The only conversions we will do will be when storing to memory. In that | |
4357 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4358 | ;; |
4359 | ;; Note that when we store into a single-precision memory location, we need to | |
4360 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4361 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4362 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4363 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4364 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4365 | ||
e8112008 | 4366 | (define_insn "extendsfdf2" |
cd2b37d9 | 4367 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
e8112008 | 4368 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] |
a3170dc6 | 4369 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
e8112008 | 4370 | "* |
5c30aff8 | 4371 | { |
e8112008 RK |
4372 | if (REGNO (operands[0]) == REGNO (operands[1])) |
4373 | return \"\"; | |
4374 | else | |
4375 | return \"fmr %0,%1\"; | |
4376 | }" | |
4377 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4378 | |
4379 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
4380 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4381 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4382 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
dcac138d | 4383 | "frsp %0,%1" |
1fd4e8c1 RK |
4384 | [(set_attr "type" "fp")]) |
4385 | ||
455350f4 RK |
4386 | (define_insn "aux_truncdfsf2" |
4387 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
615158e2 | 4388 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))] |
a3170dc6 | 4389 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
455350f4 RK |
4390 | "frsp %0,%1" |
4391 | [(set_attr "type" "fp")]) | |
4392 | ||
a3170dc6 AH |
4393 | (define_expand "negsf2" |
4394 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4395 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4396 | "TARGET_HARD_FLOAT" | |
4397 | "") | |
4398 | ||
4399 | (define_insn "*negsf2" | |
cd2b37d9 RK |
4400 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4401 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4402 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4403 | "fneg %0,%1" |
4404 | [(set_attr "type" "fp")]) | |
4405 | ||
a3170dc6 AH |
4406 | (define_expand "abssf2" |
4407 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4408 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4409 | "TARGET_HARD_FLOAT" | |
4410 | "") | |
4411 | ||
4412 | (define_insn "*abssf2" | |
cd2b37d9 RK |
4413 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4414 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4415 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4416 | "fabs %0,%1" |
4417 | [(set_attr "type" "fp")]) | |
4418 | ||
4419 | (define_insn "" | |
cd2b37d9 RK |
4420 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4421 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4422 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4423 | "fnabs %0,%1" |
4424 | [(set_attr "type" "fp")]) | |
4425 | ||
ca7f5001 RK |
4426 | (define_expand "addsf3" |
4427 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4428 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4429 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4430 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4431 | "") |
4432 | ||
4433 | (define_insn "" | |
cd2b37d9 RK |
4434 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4435 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4436 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4437 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4438 | "fadds %0,%1,%2" |
ca7f5001 RK |
4439 | [(set_attr "type" "fp")]) |
4440 | ||
4441 | (define_insn "" | |
4442 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4443 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4444 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4445 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4446 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4447 | [(set_attr "type" "fp")]) |
4448 | ||
4449 | (define_expand "subsf3" | |
4450 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4451 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4452 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4453 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4454 | "") |
4455 | ||
4456 | (define_insn "" | |
4457 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4458 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4459 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4460 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4461 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4462 | [(set_attr "type" "fp")]) |
4463 | ||
ca7f5001 | 4464 | (define_insn "" |
cd2b37d9 RK |
4465 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4466 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4467 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4468 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4469 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4470 | [(set_attr "type" "fp")]) |
4471 | ||
4472 | (define_expand "mulsf3" | |
4473 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4474 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4475 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4476 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4477 | "") |
4478 | ||
4479 | (define_insn "" | |
4480 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4481 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4482 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4483 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4484 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4485 | [(set_attr "type" "fp")]) |
4486 | ||
ca7f5001 | 4487 | (define_insn "" |
cd2b37d9 RK |
4488 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4489 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4490 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4491 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4492 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4493 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4494 | |
ca7f5001 RK |
4495 | (define_expand "divsf3" |
4496 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4497 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4498 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4499 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4500 | "") |
4501 | ||
4502 | (define_insn "" | |
cd2b37d9 RK |
4503 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4504 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4505 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4506 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4507 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4508 | [(set_attr "type" "sdiv")]) |
4509 | ||
4510 | (define_insn "" | |
4511 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4512 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4513 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4514 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4515 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4516 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4517 | |
4518 | (define_insn "" | |
cd2b37d9 RK |
4519 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4520 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4521 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4522 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4523 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4524 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4525 | [(set_attr "type" "fp")]) |
4526 | ||
4527 | (define_insn "" | |
4528 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4529 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4530 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4531 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4532 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4533 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4534 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4535 | |
4536 | (define_insn "" | |
cd2b37d9 RK |
4537 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4538 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4539 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4540 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4541 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4542 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4543 | [(set_attr "type" "fp")]) |
4544 | ||
4545 | (define_insn "" | |
4546 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4547 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4548 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4549 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4550 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4551 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4552 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4553 | |
4554 | (define_insn "" | |
cd2b37d9 RK |
4555 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4556 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4557 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4558 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4559 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4560 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4561 | "fnmadds %0,%1,%2,%3" | |
4562 | [(set_attr "type" "fp")]) | |
4563 | ||
4564 | (define_insn "" | |
4565 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4566 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4567 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4568 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4569 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4570 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4571 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4572 | [(set_attr "type" "fp")]) |
4573 | ||
4574 | (define_insn "" | |
4575 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4576 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4577 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4578 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4579 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4580 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4581 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4582 | |
16823694 GK |
4583 | (define_insn "" |
4584 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4585 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4586 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4587 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4588 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4589 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4590 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4591 | [(set_attr "type" "dmul")]) | |
4592 | ||
1fd4e8c1 | 4593 | (define_insn "" |
cd2b37d9 RK |
4594 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4595 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4596 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4597 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4598 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4599 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4600 | "fnmsubs %0,%1,%2,%3" | |
4601 | [(set_attr "type" "fp")]) | |
4602 | ||
4603 | (define_insn "" | |
4604 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4605 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4606 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4607 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4608 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4609 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4610 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4611 | [(set_attr "type" "fp")]) |
4612 | ||
4613 | (define_insn "" | |
4614 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4615 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4616 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4617 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4618 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4619 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 4620 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4621 | |
16823694 GK |
4622 | (define_insn "" |
4623 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4624 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4625 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4626 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4627 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4628 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4629 | "{fnms|fnmsub} %0,%1,%2,%3" | |
4630 | [(set_attr "type" "fp")]) | |
4631 | ||
ca7f5001 RK |
4632 | (define_expand "sqrtsf2" |
4633 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4634 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 4635 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4636 | "") |
4637 | ||
4638 | (define_insn "" | |
4639 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4640 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4641 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4642 | "fsqrts %0,%1" |
4643 | [(set_attr "type" "ssqrt")]) | |
4644 | ||
4645 | (define_insn "" | |
4646 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4647 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4648 | "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4649 | "fsqrt %0,%1" |
4650 | [(set_attr "type" "dsqrt")]) | |
4651 | ||
94d7001a RK |
4652 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4653 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4654 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
4655 | ;; combine. |
4656 | (define_expand "maxsf3" | |
8e871c05 | 4657 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4658 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
4659 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4660 | (match_dup 1) |
4661 | (match_dup 2)))] | |
a3170dc6 | 4662 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 4663 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
2f607b94 | 4664 | |
8e871c05 | 4665 | (define_expand "minsf3" |
50a0b056 GK |
4666 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
4667 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
4668 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
4669 | (match_dup 2) | |
4670 | (match_dup 1)))] | |
a3170dc6 | 4671 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 4672 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 4673 | |
8e871c05 RK |
4674 | (define_split |
4675 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4676 | (match_operator:SF 3 "min_max_operator" |
4677 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
4678 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
a3170dc6 | 4679 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 GK |
4680 | [(const_int 0)] |
4681 | " | |
4682 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
4683 | operands[1], operands[2]); | |
4684 | DONE; | |
4685 | }") | |
2f607b94 | 4686 | |
a3170dc6 AH |
4687 | (define_expand "movsicc" |
4688 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4689 | (if_then_else:SI (match_operand 1 "comparison_operator" "") | |
4690 | (match_operand:SI 2 "gpc_reg_operand" "") | |
4691 | (match_operand:SI 3 "gpc_reg_operand" "")))] | |
4692 | "TARGET_ISEL" | |
4693 | " | |
4694 | { | |
4695 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) | |
4696 | DONE; | |
4697 | else | |
4698 | FAIL; | |
4699 | }") | |
4700 | ||
4701 | ;; We use the BASE_REGS for the isel input operands because, if rA is | |
4702 | ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB | |
4703 | ;; because we may switch the operands and rB may end up being rA. | |
4704 | ;; | |
4705 | ;; We need 2 patterns: an unsigned and a signed pattern. We could | |
4706 | ;; leave out the mode in operand 4 and use one pattern, but reload can | |
4707 | ;; change the mode underneath our feet and then gets confused trying | |
4708 | ;; to reload the value. | |
4709 | (define_insn "isel_signed" | |
4710 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4711 | (if_then_else:SI | |
4712 | (match_operator 1 "comparison_operator" | |
4713 | [(match_operand:CC 4 "cc_reg_operand" "y") | |
4714 | (const_int 0)]) | |
4715 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4716 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4717 | "TARGET_ISEL" | |
4718 | "* | |
4719 | { return output_isel (operands); }" | |
4720 | [(set_attr "length" "4")]) | |
4721 | ||
4722 | (define_insn "isel_unsigned" | |
4723 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4724 | (if_then_else:SI | |
4725 | (match_operator 1 "comparison_operator" | |
4726 | [(match_operand:CCUNS 4 "cc_reg_operand" "y") | |
4727 | (const_int 0)]) | |
4728 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4729 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4730 | "TARGET_ISEL" | |
4731 | "* | |
4732 | { return output_isel (operands); }" | |
4733 | [(set_attr "length" "4")]) | |
4734 | ||
94d7001a | 4735 | (define_expand "movsfcc" |
0ad91047 | 4736 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 4737 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4738 | (match_operand:SF 2 "gpc_reg_operand" "") |
4739 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 4740 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4741 | " |
4742 | { | |
50a0b056 GK |
4743 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4744 | DONE; | |
94d7001a | 4745 | else |
50a0b056 | 4746 | FAIL; |
94d7001a | 4747 | }") |
d56d506a | 4748 | |
50a0b056 | 4749 | (define_insn "*fselsfsf4" |
8e871c05 RK |
4750 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4751 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4752 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4753 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4754 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4755 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
4756 | "fsel %0,%1,%2,%3" |
4757 | [(set_attr "type" "fp")]) | |
2f607b94 | 4758 | |
50a0b056 | 4759 | (define_insn "*fseldfsf4" |
94d7001a RK |
4760 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4761 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 4762 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4763 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4764 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4765 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4766 | "fsel %0,%1,%2,%3" |
4767 | [(set_attr "type" "fp")]) | |
d56d506a | 4768 | |
1fd4e8c1 | 4769 | (define_insn "negdf2" |
cd2b37d9 RK |
4770 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4771 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4772 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4773 | "fneg %0,%1" |
4774 | [(set_attr "type" "fp")]) | |
4775 | ||
4776 | (define_insn "absdf2" | |
cd2b37d9 RK |
4777 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4778 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4779 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4780 | "fabs %0,%1" |
4781 | [(set_attr "type" "fp")]) | |
4782 | ||
4783 | (define_insn "" | |
cd2b37d9 RK |
4784 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4785 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4786 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4787 | "fnabs %0,%1" |
4788 | [(set_attr "type" "fp")]) | |
4789 | ||
4790 | (define_insn "adddf3" | |
cd2b37d9 RK |
4791 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4792 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4793 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4794 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4795 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
4796 | [(set_attr "type" "fp")]) |
4797 | ||
4798 | (define_insn "subdf3" | |
cd2b37d9 RK |
4799 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4800 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4801 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4802 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4803 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
4804 | [(set_attr "type" "fp")]) |
4805 | ||
4806 | (define_insn "muldf3" | |
cd2b37d9 RK |
4807 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4808 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4809 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4810 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4811 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 4812 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4813 | |
4814 | (define_insn "divdf3" | |
cd2b37d9 RK |
4815 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4816 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4817 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4818 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4819 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 4820 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4821 | |
4822 | (define_insn "" | |
cd2b37d9 RK |
4823 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4824 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4825 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4826 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4827 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4828 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 4829 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4830 | |
4831 | (define_insn "" | |
cd2b37d9 RK |
4832 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4833 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4834 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4835 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4836 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4837 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 4838 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4839 | |
4840 | (define_insn "" | |
cd2b37d9 RK |
4841 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4842 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4843 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4844 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4845 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4846 | && HONOR_SIGNED_ZEROS (DFmode)" | |
4847 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4848 | [(set_attr "type" "dmul")]) | |
4849 | ||
4850 | (define_insn "" | |
4851 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4852 | (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) | |
4853 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4854 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
4855 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4856 | && ! HONOR_SIGNED_ZEROS (DFmode)" | |
ca7f5001 | 4857 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 4858 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4859 | |
4860 | (define_insn "" | |
cd2b37d9 RK |
4861 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4862 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4863 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4864 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4865 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4866 | && HONOR_SIGNED_ZEROS (DFmode)" | |
4867 | "{fnms|fnmsub} %0,%1,%2,%3" | |
4868 | [(set_attr "type" "dmul")]) | |
4869 | ||
4870 | (define_insn "" | |
4871 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4872 | (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") | |
4873 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4874 | (match_operand:DF 2 "gpc_reg_operand" "f"))))] | |
4875 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4876 | && ! HONOR_SIGNED_ZEROS (DFmode)" | |
ca7f5001 | 4877 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 4878 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
4879 | |
4880 | (define_insn "sqrtdf2" | |
4881 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4882 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4883 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4884 | "fsqrt %0,%1" |
4885 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 4886 | |
50a0b056 GK |
4887 | ;; The conditional move instructions allow us to perform max and min |
4888 | ;; operations even when | |
b77dfefc | 4889 | |
8e871c05 | 4890 | (define_expand "maxdf3" |
8e871c05 | 4891 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4892 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
4893 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4894 | (match_dup 1) |
4895 | (match_dup 2)))] | |
a3170dc6 | 4896 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 4897 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
b77dfefc | 4898 | |
8e871c05 | 4899 | (define_expand "mindf3" |
50a0b056 GK |
4900 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
4901 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
4902 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
4903 | (match_dup 2) | |
4904 | (match_dup 1)))] | |
a3170dc6 | 4905 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 4906 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 4907 | |
8e871c05 RK |
4908 | (define_split |
4909 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4910 | (match_operator:DF 3 "min_max_operator" |
4911 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
4912 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
a3170dc6 | 4913 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 GK |
4914 | [(const_int 0)] |
4915 | " | |
4916 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
4917 | operands[1], operands[2]); | |
4918 | DONE; | |
4919 | }") | |
b77dfefc | 4920 | |
94d7001a | 4921 | (define_expand "movdfcc" |
0ad91047 | 4922 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 4923 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4924 | (match_operand:DF 2 "gpc_reg_operand" "") |
4925 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 4926 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4927 | " |
4928 | { | |
50a0b056 GK |
4929 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4930 | DONE; | |
94d7001a | 4931 | else |
50a0b056 | 4932 | FAIL; |
94d7001a | 4933 | }") |
d56d506a | 4934 | |
50a0b056 | 4935 | (define_insn "*fseldfdf4" |
8e871c05 RK |
4936 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4937 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4938 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4939 | (match_operand:DF 2 "gpc_reg_operand" "f") |
4940 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4941 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
4942 | "fsel %0,%1,%2,%3" |
4943 | [(set_attr "type" "fp")]) | |
d56d506a | 4944 | |
50a0b056 | 4945 | (define_insn "*fselsfdf4" |
94d7001a RK |
4946 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4947 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4948 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4949 | (match_operand:DF 2 "gpc_reg_operand" "f") |
4950 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
4951 | "TARGET_PPC_GFXOPT" | |
4952 | "fsel %0,%1,%2,%3" | |
4953 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4954 | \f |
4955 | ;; Conversions to and from floating-point. | |
802a0058 | 4956 | |
a3170dc6 AH |
4957 | (define_expand "fixunssfsi2" |
4958 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4959 | (unsigned_fix:SI (fix:SF (match_operand:SF 1 "gpc_reg_operand" ""))))] | |
4960 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
4961 | "") | |
4962 | ||
4963 | (define_expand "fix_truncsfsi2" | |
4964 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4965 | (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4966 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
4967 | "") | |
4968 | ||
9ebbca7d GK |
4969 | ; For each of these conversions, there is a define_expand, a define_insn |
4970 | ; with a '#' template, and a define_split (with C code). The idea is | |
4971 | ; to allow constant folding with the template of the define_insn, | |
4972 | ; then to have the insns split later (between sched1 and final). | |
4973 | ||
1fd4e8c1 | 4974 | (define_expand "floatsidf2" |
802a0058 MM |
4975 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
4976 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
4977 | (use (match_dup 2)) | |
4978 | (use (match_dup 3)) | |
208c89ce | 4979 | (clobber (match_dup 4)) |
a7df97e6 | 4980 | (clobber (match_dup 5)) |
9ebbca7d | 4981 | (clobber (match_dup 6))])] |
a3170dc6 | 4982 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4983 | " |
4984 | { | |
05d49501 AM |
4985 | if (TARGET_POWERPC64) |
4986 | { | |
4987 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
4988 | rtx t1 = gen_reg_rtx (DImode); | |
4989 | rtx t2 = gen_reg_rtx (DImode); | |
4990 | emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); | |
4991 | DONE; | |
4992 | } | |
4993 | ||
802a0058 | 4994 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 4995 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); |
9ebbca7d GK |
4996 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
4997 | operands[5] = gen_reg_rtx (DFmode); | |
4998 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
4999 | }") |
5000 | ||
802a0058 MM |
5001 | (define_insn "*floatsidf2_internal" |
5002 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5003 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5004 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5005 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5006 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 DJ |
5007 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) |
5008 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] | |
a3170dc6 | 5009 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5010 | "#" |
a7df97e6 | 5011 | [(set_attr "length" "24")]) |
802a0058 MM |
5012 | |
5013 | (define_split | |
dbe3df29 | 5014 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
5015 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
5016 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5017 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5018 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5019 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5020 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
a3170dc6 | 5021 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5022 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5023 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5024 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5025 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5026 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5027 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5028 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
208c89ce MM |
5029 | " |
5030 | { | |
9ebbca7d GK |
5031 | rtx lowword, highword; |
5032 | if (GET_CODE (operands[4]) != MEM) | |
5033 | abort(); | |
5034 | highword = XEXP (operands[4], 0); | |
5035 | lowword = plus_constant (highword, 4); | |
5036 | if (! WORDS_BIG_ENDIAN) | |
5037 | { | |
5038 | rtx tmp; | |
5039 | tmp = highword; highword = lowword; lowword = tmp; | |
5040 | } | |
5041 | ||
5042 | emit_insn (gen_xorsi3 (operands[6], operands[1], | |
5043 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); | |
5044 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); | |
5045 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5046 | emit_move_insn (operands[5], operands[4]); | |
5047 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5048 | DONE; | |
208c89ce | 5049 | }") |
802a0058 | 5050 | |
a3170dc6 AH |
5051 | (define_expand "floatunssisf2" |
5052 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5053 | (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5054 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5055 | "") | |
5056 | ||
802a0058 MM |
5057 | (define_expand "floatunssidf2" |
5058 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5059 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5060 | (use (match_dup 2)) | |
5061 | (use (match_dup 3)) | |
a7df97e6 | 5062 | (clobber (match_dup 4)) |
9ebbca7d | 5063 | (clobber (match_dup 5))])] |
a3170dc6 | 5064 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5065 | " |
5066 | { | |
05d49501 AM |
5067 | if (TARGET_POWERPC64) |
5068 | { | |
5069 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5070 | rtx t1 = gen_reg_rtx (DImode); | |
5071 | rtx t2 = gen_reg_rtx (DImode); | |
5072 | emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, | |
5073 | t1, t2)); | |
5074 | DONE; | |
5075 | } | |
5076 | ||
802a0058 | 5077 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5078 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); |
9ebbca7d GK |
5079 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5080 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5081 | }") |
5082 | ||
802a0058 MM |
5083 | (define_insn "*floatunssidf2_internal" |
5084 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5085 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5086 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5087 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5088 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 | 5089 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] |
a3170dc6 | 5090 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5091 | "#" |
a7df97e6 | 5092 | [(set_attr "length" "20")]) |
802a0058 MM |
5093 | |
5094 | (define_split | |
5095 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5096 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5097 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5098 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5099 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5100 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
a3170dc6 | 5101 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5102 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5103 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5104 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5105 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5106 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5107 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
5108 | " | |
802a0058 | 5109 | { |
9ebbca7d GK |
5110 | rtx lowword, highword; |
5111 | if (GET_CODE (operands[4]) != MEM) | |
5112 | abort(); | |
5113 | highword = XEXP (operands[4], 0); | |
5114 | lowword = plus_constant (highword, 4); | |
5115 | if (! WORDS_BIG_ENDIAN) | |
f6968f59 | 5116 | { |
9ebbca7d GK |
5117 | rtx tmp; |
5118 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5119 | } |
802a0058 | 5120 | |
9ebbca7d GK |
5121 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); |
5122 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5123 | emit_move_insn (operands[5], operands[4]); | |
5124 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5125 | DONE; | |
5126 | }") | |
1fd4e8c1 | 5127 | |
1fd4e8c1 | 5128 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
5129 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5130 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5131 | (clobber (match_dup 2)) | |
9ebbca7d | 5132 | (clobber (match_dup 3))])] |
a3170dc6 | 5133 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5134 | " |
5135 | { | |
802a0058 | 5136 | operands[2] = gen_reg_rtx (DImode); |
9ebbca7d | 5137 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5138 | }") |
5139 | ||
802a0058 MM |
5140 | (define_insn "*fix_truncdfsi2_internal" |
5141 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5142 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
e3485bbc | 5143 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) |
9ebbca7d | 5144 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
a3170dc6 | 5145 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5146 | "#" |
9ebbca7d | 5147 | [(set_attr "length" "16")]) |
802a0058 MM |
5148 | |
5149 | (define_split | |
5150 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
75540af0 | 5151 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
802a0058 | 5152 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
9ebbca7d | 5153 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] |
a3170dc6 | 5154 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d | 5155 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
75540af0 | 5156 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
9ebbca7d GK |
5157 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
5158 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] | |
5159 | " | |
802a0058 | 5160 | { |
9ebbca7d GK |
5161 | rtx lowword; |
5162 | if (GET_CODE (operands[3]) != MEM) | |
5163 | abort(); | |
5164 | lowword = XEXP (operands[3], 0); | |
5165 | if (WORDS_BIG_ENDIAN) | |
5166 | lowword = plus_constant (lowword, 4); | |
802a0058 | 5167 | |
9ebbca7d GK |
5168 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5169 | emit_move_insn (operands[3], operands[2]); | |
5170 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
5171 | DONE; | |
5172 | }") | |
802a0058 | 5173 | |
615158e2 | 5174 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) |
9ebbca7d GK |
5175 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) |
5176 | ; because the first makes it clear that operand 0 is not live | |
5177 | ; before the instruction. | |
5178 | (define_insn "fctiwz" | |
61c07d3c | 5179 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
615158e2 JJ |
5180 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] |
5181 | UNSPEC_FCTIWZ))] | |
a3170dc6 | 5182 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
a260abc9 DE |
5183 | "{fcirz|fctiwz} %0,%1" |
5184 | [(set_attr "type" "fp")]) | |
5185 | ||
a3170dc6 AH |
5186 | (define_expand "floatsisf2" |
5187 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5188 | (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5189 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5190 | "") | |
5191 | ||
a473029f RK |
5192 | (define_insn "floatdidf2" |
5193 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 5194 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] |
a3170dc6 | 5195 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5196 | "fcfid %0,%1" |
5197 | [(set_attr "type" "fp")]) | |
5198 | ||
05d49501 AM |
5199 | (define_insn_and_split "floatsidf_ppc64" |
5200 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5201 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5202 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5203 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5204 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5205 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 AM |
5206 | "#" |
5207 | "" | |
5208 | [(set (match_dup 3) (sign_extend:DI (match_dup 1))) | |
5209 | (set (match_dup 2) (match_dup 3)) | |
5210 | (set (match_dup 4) (match_dup 2)) | |
5211 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5212 | "") | |
5213 | ||
5214 | (define_insn_and_split "floatunssidf_ppc64" | |
5215 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5216 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5217 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5218 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5219 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5220 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 AM |
5221 | "#" |
5222 | "" | |
5223 | [(set (match_dup 3) (zero_extend:DI (match_dup 1))) | |
5224 | (set (match_dup 2) (match_dup 3)) | |
5225 | (set (match_dup 4) (match_dup 2)) | |
5226 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5227 | "") | |
5228 | ||
a473029f | 5229 | (define_insn "fix_truncdfdi2" |
61c07d3c | 5230 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
a473029f | 5231 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] |
a3170dc6 | 5232 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5233 | "fctidz %0,%1" |
5234 | [(set_attr "type" "fp")]) | |
ea112fc4 | 5235 | |
678b7733 AM |
5236 | (define_expand "floatdisf2" |
5237 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5238 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] | |
5239 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" | |
5240 | " | |
5241 | { | |
5242 | if (!flag_unsafe_math_optimizations) | |
5243 | { | |
5244 | rtx label = gen_label_rtx (); | |
5245 | emit_insn (gen_floatdisf2_internal2 (operands[1], label)); | |
5246 | emit_label (label); | |
5247 | } | |
5248 | emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1])); | |
5249 | DONE; | |
5250 | }") | |
5251 | ||
5252 | ;; This is not IEEE compliant if rounding mode is "round to nearest". | |
5253 | ;; If the DI->DF conversion is inexact, then it's possible to suffer | |
5254 | ;; from double rounding. | |
5255 | (define_insn_and_split "floatdisf2_internal1" | |
ea112fc4 | 5256 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
61c07d3c | 5257 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 | 5258 | (clobber (match_scratch:DF 2 "=f"))] |
678b7733 | 5259 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ea112fc4 DE |
5260 | "#" |
5261 | "&& reload_completed" | |
5262 | [(set (match_dup 2) | |
5263 | (float:DF (match_dup 1))) | |
5264 | (set (match_dup 0) | |
5265 | (float_truncate:SF (match_dup 2)))] | |
5266 | "") | |
678b7733 AM |
5267 | |
5268 | ;; Twiddles bits to avoid double rounding. | |
b6d08ca1 | 5269 | ;; Bits that might be truncated when converting to DFmode are replaced |
678b7733 AM |
5270 | ;; by a bit that won't be lost at that stage, but is below the SFmode |
5271 | ;; rounding position. | |
5272 | (define_expand "floatdisf2_internal2" | |
42a6388c AM |
5273 | [(parallel [(set (match_dup 4) |
5274 | (compare:CC (and:DI (match_operand:DI 0 "" "") | |
5275 | (const_int 2047)) | |
5276 | (const_int 0))) | |
5277 | (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047))) | |
5278 | (clobber (match_scratch:CC 7 ""))]) | |
678b7733 AM |
5279 | (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53))) |
5280 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1))) | |
5281 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
5282 | (label_ref (match_operand:DI 1 "" "")) | |
5283 | (pc))) | |
5284 | (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2))) | |
5285 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
5286 | (label_ref (match_dup 1)) | |
5287 | (pc))) | |
5288 | (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2))) | |
5289 | (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))] | |
5290 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" | |
5291 | " | |
5292 | { | |
5293 | operands[2] = gen_reg_rtx (DImode); | |
5294 | operands[3] = gen_reg_rtx (DImode); | |
5295 | operands[4] = gen_reg_rtx (CCmode); | |
5296 | operands[5] = gen_reg_rtx (CCUNSmode); | |
5297 | }") | |
1fd4e8c1 RK |
5298 | \f |
5299 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5300 | ;; of instructions. The & constraints are to prevent the register |
5301 | ;; allocator from allocating registers that overlap with the inputs | |
5302 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5303 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5304 | |
266eb58a | 5305 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5306 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5307 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5308 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5309 | "! TARGET_POWERPC64" |
0f645302 MM |
5310 | "* |
5311 | { | |
5312 | if (WORDS_BIG_ENDIAN) | |
5313 | return (GET_CODE (operands[2])) != CONST_INT | |
5314 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5315 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5316 | else | |
5317 | return (GET_CODE (operands[2])) != CONST_INT | |
5318 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5319 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5320 | }" | |
b19003d8 | 5321 | [(set_attr "length" "8")]) |
1fd4e8c1 | 5322 | |
266eb58a | 5323 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5324 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5325 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5326 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5327 | "! TARGET_POWERPC64" |
5502823b RK |
5328 | "* |
5329 | { | |
0f645302 MM |
5330 | if (WORDS_BIG_ENDIAN) |
5331 | return (GET_CODE (operands[1]) != CONST_INT) | |
5332 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5333 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5334 | else | |
5335 | return (GET_CODE (operands[1]) != CONST_INT) | |
5336 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5337 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5338 | }" |
ca7f5001 RK |
5339 | [(set_attr "length" "8")]) |
5340 | ||
266eb58a | 5341 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5342 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5343 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5344 | "! TARGET_POWERPC64" |
5502823b RK |
5345 | "* |
5346 | { | |
5347 | return (WORDS_BIG_ENDIAN) | |
5348 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5349 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5350 | }" | |
ca7f5001 RK |
5351 | [(set_attr "length" "8")]) |
5352 | ||
8ffd9c51 RK |
5353 | (define_expand "mulsidi3" |
5354 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5355 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5356 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5357 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5358 | " |
5359 | { | |
5360 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5361 | { | |
39403d82 DE |
5362 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5363 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5364 | emit_insn (gen_mull_call ()); |
cf27b467 | 5365 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5366 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5367 | else |
5368 | { | |
5369 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5370 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5371 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5372 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5373 | } |
8ffd9c51 RK |
5374 | DONE; |
5375 | } | |
5376 | else if (TARGET_POWER) | |
5377 | { | |
5378 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5379 | DONE; | |
5380 | } | |
5381 | }") | |
deb9225a | 5382 | |
8ffd9c51 | 5383 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5384 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5385 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5386 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5387 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5388 | "TARGET_POWER" |
b19003d8 | 5389 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5390 | [(set_attr "type" "imul") |
5391 | (set_attr "length" "8")]) | |
deb9225a | 5392 | |
f192bf8b | 5393 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5394 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5395 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5396 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5397 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5398 | "* |
5399 | { | |
5400 | return (WORDS_BIG_ENDIAN) | |
5401 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5402 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5403 | }" | |
8ffd9c51 RK |
5404 | [(set_attr "type" "imul") |
5405 | (set_attr "length" "8")]) | |
deb9225a | 5406 | |
ebedb4dd MM |
5407 | (define_split |
5408 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5409 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5410 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5411 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5412 | [(set (match_dup 3) |
5413 | (truncate:SI | |
5414 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5415 | (sign_extend:DI (match_dup 2))) | |
5416 | (const_int 32)))) | |
5417 | (set (match_dup 4) | |
5418 | (mult:SI (match_dup 1) | |
5419 | (match_dup 2)))] | |
5420 | " | |
5421 | { | |
5422 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5423 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5424 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5425 | }") | |
5426 | ||
f192bf8b DE |
5427 | (define_expand "umulsidi3" |
5428 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5429 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5430 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5431 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5432 | " | |
5433 | { | |
5434 | if (TARGET_POWER) | |
5435 | { | |
5436 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5437 | DONE; | |
5438 | } | |
5439 | }") | |
5440 | ||
5441 | (define_insn "umulsidi3_mq" | |
5442 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5443 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5444 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5445 | (clobber (match_scratch:SI 3 "=q"))] | |
5446 | "TARGET_POWERPC && TARGET_POWER" | |
5447 | "* | |
5448 | { | |
5449 | return (WORDS_BIG_ENDIAN) | |
5450 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5451 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5452 | }" | |
5453 | [(set_attr "type" "imul") | |
5454 | (set_attr "length" "8")]) | |
5455 | ||
5456 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5457 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5458 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5459 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5460 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5461 | "* |
5462 | { | |
5463 | return (WORDS_BIG_ENDIAN) | |
5464 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5465 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5466 | }" | |
5467 | [(set_attr "type" "imul") | |
5468 | (set_attr "length" "8")]) | |
5469 | ||
ebedb4dd MM |
5470 | (define_split |
5471 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5472 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5473 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5474 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5475 | [(set (match_dup 3) |
5476 | (truncate:SI | |
5477 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5478 | (zero_extend:DI (match_dup 2))) | |
5479 | (const_int 32)))) | |
5480 | (set (match_dup 4) | |
5481 | (mult:SI (match_dup 1) | |
5482 | (match_dup 2)))] | |
5483 | " | |
5484 | { | |
5485 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5486 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5487 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5488 | }") | |
5489 | ||
8ffd9c51 RK |
5490 | (define_expand "smulsi3_highpart" |
5491 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5492 | (truncate:SI | |
5493 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5494 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5495 | (sign_extend:DI | |
5496 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5497 | (const_int 32))))] | |
5498 | "" | |
5499 | " | |
5500 | { | |
5501 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5502 | { | |
39403d82 DE |
5503 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5504 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5505 | emit_insn (gen_mulh_call ()); |
39403d82 | 5506 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5507 | DONE; |
5508 | } | |
5509 | else if (TARGET_POWER) | |
5510 | { | |
5511 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5512 | DONE; | |
5513 | } | |
5514 | }") | |
deb9225a | 5515 | |
8ffd9c51 RK |
5516 | (define_insn "smulsi3_highpart_mq" |
5517 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5518 | (truncate:SI | |
fada905b MM |
5519 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5520 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5521 | (sign_extend:DI | |
5522 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5523 | (const_int 32)))) |
5524 | (clobber (match_scratch:SI 3 "=q"))] | |
5525 | "TARGET_POWER" | |
5526 | "mul %0,%1,%2" | |
5527 | [(set_attr "type" "imul")]) | |
deb9225a | 5528 | |
f192bf8b | 5529 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5530 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5531 | (truncate:SI | |
fada905b MM |
5532 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5533 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5534 | (sign_extend:DI | |
5535 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5536 | (const_int 32))))] |
f192bf8b | 5537 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5538 | "mulhw %0,%1,%2" |
5539 | [(set_attr "type" "imul")]) | |
deb9225a | 5540 | |
f192bf8b DE |
5541 | (define_expand "umulsi3_highpart" |
5542 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5543 | (truncate:SI | |
5544 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5545 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5546 | (zero_extend:DI | |
5547 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5548 | (const_int 32))))] | |
5549 | "TARGET_POWERPC" | |
5550 | " | |
5551 | { | |
5552 | if (TARGET_POWER) | |
5553 | { | |
5554 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5555 | DONE; | |
5556 | } | |
5557 | }") | |
5558 | ||
5559 | (define_insn "umulsi3_highpart_mq" | |
5560 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5561 | (truncate:SI | |
5562 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5563 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5564 | (zero_extend:DI | |
5565 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5566 | (const_int 32)))) | |
5567 | (clobber (match_scratch:SI 3 "=q"))] | |
5568 | "TARGET_POWERPC && TARGET_POWER" | |
5569 | "mulhwu %0,%1,%2" | |
5570 | [(set_attr "type" "imul")]) | |
5571 | ||
5572 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5573 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5574 | (truncate:SI | |
5575 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5576 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5577 | (zero_extend:DI | |
5578 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5579 | (const_int 32))))] | |
f192bf8b | 5580 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5581 | "mulhwu %0,%1,%2" |
5582 | [(set_attr "type" "imul")]) | |
5583 | ||
5584 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5585 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5586 | ;; why we have the strange constraints below. | |
5587 | (define_insn "ashldi3_power" | |
5588 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5589 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5590 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5591 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5592 | "TARGET_POWER" | |
5593 | "@ | |
5594 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5595 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5596 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5597 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5598 | [(set_attr "length" "8")]) | |
5599 | ||
5600 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5601 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5602 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5603 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5604 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5605 | "TARGET_POWER" | |
5606 | "@ | |
47ad8c61 | 5607 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5608 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5609 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5610 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5611 | [(set_attr "length" "8")]) | |
5612 | ||
5613 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5614 | ;; just handle shifts by constants. | |
5615 | (define_insn "ashrdi3_power" | |
7093ddee | 5616 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5617 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5618 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5619 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5620 | "TARGET_POWER" | |
5621 | "@ | |
5622 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5623 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5624 | [(set_attr "length" "8")]) | |
4aa74a4f FS |
5625 | |
5626 | (define_insn "ashrdi3_no_power" | |
5627 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") | |
5628 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5629 | (match_operand:SI 2 "const_int_operand" "M,i")))] | |
5630 | "TARGET_32BIT && !TARGET_POWER" | |
5631 | "@ | |
5632 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5633 | {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" | |
5634 | [(set_attr "length" "8,12")]) | |
266eb58a DE |
5635 | \f |
5636 | ;; PowerPC64 DImode operations. | |
5637 | ||
5638 | (define_expand "adddi3" | |
5639 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5640 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 5641 | (match_operand:DI 2 "reg_or_add_cint64_operand" "")))] |
266eb58a DE |
5642 | "" |
5643 | " | |
5644 | { | |
a260abc9 DE |
5645 | if (! TARGET_POWERPC64) |
5646 | { | |
5647 | if (non_short_cint_operand (operands[2], DImode)) | |
5648 | FAIL; | |
5649 | } | |
5650 | else | |
5651 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 5652 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 5653 | { |
677a9668 | 5654 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
5655 | ? operands[0] : gen_reg_rtx (DImode)); |
5656 | ||
2bfcf297 | 5657 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5658 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5659 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
a260abc9 | 5660 | |
2bfcf297 DB |
5661 | if (!CONST_OK_FOR_LETTER_P (rest, 'L')) |
5662 | FAIL; | |
a260abc9 | 5663 | |
2bfcf297 DB |
5664 | /* The ordering here is important for the prolog expander. |
5665 | When space is allocated from the stack, adding 'low' first may | |
5666 | produce a temporary deallocation (which would be bad). */ | |
5667 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest))); | |
a260abc9 DE |
5668 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); |
5669 | DONE; | |
5670 | } | |
266eb58a DE |
5671 | }") |
5672 | ||
5673 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
5674 | ;; allowing register zero as source. | |
5675 | ||
a260abc9 | 5676 | (define_insn "*adddi3_internal1" |
266eb58a DE |
5677 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
5678 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 5679 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
5680 | "TARGET_POWERPC64" |
5681 | "@ | |
5682 | add %0,%1,%2 | |
5683 | addi %0,%1,%2 | |
5684 | addic %0,%1,%2 | |
802a0058 | 5685 | addis %0,%1,%v2") |
266eb58a | 5686 | |
a260abc9 | 5687 | (define_insn "*adddi3_internal2" |
9ebbca7d GK |
5688 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
5689 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5690 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5691 | (const_int 0))) |
9ebbca7d | 5692 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
266eb58a DE |
5693 | "TARGET_POWERPC64" |
5694 | "@ | |
5695 | add. %3,%1,%2 | |
9ebbca7d GK |
5696 | addic. %3,%1,%2 |
5697 | # | |
5698 | #" | |
a62bfff2 | 5699 | [(set_attr "type" "fast_compare,compare,compare,compare") |
9ebbca7d GK |
5700 | (set_attr "length" "4,4,8,8")]) |
5701 | ||
5702 | (define_split | |
5703 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5704 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5705 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5706 | (const_int 0))) | |
5707 | (clobber (match_scratch:DI 3 ""))] | |
5708 | "TARGET_POWERPC64 && reload_completed" | |
5709 | [(set (match_dup 3) | |
5710 | (plus:DI (match_dup 1) (match_dup 2))) | |
5711 | (set (match_dup 0) | |
5712 | (compare:CC (match_dup 3) | |
5713 | (const_int 0)))] | |
5714 | "") | |
266eb58a | 5715 | |
a260abc9 | 5716 | (define_insn "*adddi3_internal3" |
9ebbca7d GK |
5717 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
5718 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5719 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5720 | (const_int 0))) |
9ebbca7d | 5721 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
266eb58a DE |
5722 | (plus:DI (match_dup 1) (match_dup 2)))] |
5723 | "TARGET_POWERPC64" | |
5724 | "@ | |
5725 | add. %0,%1,%2 | |
9ebbca7d GK |
5726 | addic. %0,%1,%2 |
5727 | # | |
5728 | #" | |
a62bfff2 | 5729 | [(set_attr "type" "fast_compare,compare,compare,compare") |
9ebbca7d GK |
5730 | (set_attr "length" "4,4,8,8")]) |
5731 | ||
5732 | (define_split | |
5733 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5734 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5735 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5736 | (const_int 0))) | |
5737 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5738 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5739 | "TARGET_POWERPC64 && reload_completed" | |
5740 | [(set (match_dup 0) | |
5741 | (plus:DI (match_dup 1) (match_dup 2))) | |
5742 | (set (match_dup 3) | |
5743 | (compare:CC (match_dup 0) | |
5744 | (const_int 0)))] | |
5745 | "") | |
266eb58a DE |
5746 | |
5747 | ;; Split an add that we can't do in one insn into two insns, each of which | |
5748 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
5749 | ;; add should be last in case the result gets used in an address. | |
5750 | ||
5751 | (define_split | |
5752 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5753 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5754 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
5755 | "TARGET_POWERPC64" | |
5756 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
5757 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
5758 | " | |
5759 | { | |
2bfcf297 | 5760 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5761 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5762 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
266eb58a | 5763 | |
2bfcf297 DB |
5764 | operands[4] = GEN_INT (low); |
5765 | if (CONST_OK_FOR_LETTER_P (rest, 'L')) | |
5766 | operands[3] = GEN_INT (rest); | |
5767 | else if (! no_new_pseudos) | |
38886f37 | 5768 | { |
2bfcf297 DB |
5769 | operands[3] = gen_reg_rtx (DImode); |
5770 | emit_move_insn (operands[3], operands[2]); | |
5771 | emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); | |
5772 | DONE; | |
38886f37 | 5773 | } |
2bfcf297 DB |
5774 | else |
5775 | FAIL; | |
266eb58a DE |
5776 | }") |
5777 | ||
5778 | (define_insn "one_cmpldi2" | |
5779 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5780 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5781 | "TARGET_POWERPC64" | |
5782 | "nor %0,%1,%1") | |
5783 | ||
5784 | (define_insn "" | |
9ebbca7d GK |
5785 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5786 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5787 | (const_int 0))) |
9ebbca7d | 5788 | (clobber (match_scratch:DI 2 "=r,r"))] |
266eb58a | 5789 | "TARGET_POWERPC64" |
9ebbca7d GK |
5790 | "@ |
5791 | nor. %2,%1,%1 | |
5792 | #" | |
5793 | [(set_attr "type" "compare") | |
5794 | (set_attr "length" "4,8")]) | |
5795 | ||
5796 | (define_split | |
5797 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5798 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5799 | (const_int 0))) | |
5800 | (clobber (match_scratch:DI 2 ""))] | |
5801 | "TARGET_POWERPC64 && reload_completed" | |
5802 | [(set (match_dup 2) | |
5803 | (not:DI (match_dup 1))) | |
5804 | (set (match_dup 0) | |
5805 | (compare:CC (match_dup 2) | |
5806 | (const_int 0)))] | |
5807 | "") | |
266eb58a DE |
5808 | |
5809 | (define_insn "" | |
9ebbca7d GK |
5810 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5811 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5812 | (const_int 0))) |
9ebbca7d | 5813 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
5814 | (not:DI (match_dup 1)))] |
5815 | "TARGET_POWERPC64" | |
9ebbca7d GK |
5816 | "@ |
5817 | nor. %0,%1,%1 | |
5818 | #" | |
5819 | [(set_attr "type" "compare") | |
5820 | (set_attr "length" "4,8")]) | |
5821 | ||
5822 | (define_split | |
5823 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5824 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5825 | (const_int 0))) | |
5826 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5827 | (not:DI (match_dup 1)))] | |
5828 | "TARGET_POWERPC64 && reload_completed" | |
5829 | [(set (match_dup 0) | |
5830 | (not:DI (match_dup 1))) | |
5831 | (set (match_dup 2) | |
5832 | (compare:CC (match_dup 0) | |
5833 | (const_int 0)))] | |
5834 | "") | |
266eb58a DE |
5835 | |
5836 | (define_insn "" | |
5837 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5838 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
5839 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
5840 | "TARGET_POWERPC64" | |
5841 | "@ | |
5842 | subf %0,%2,%1 | |
5843 | subfic %0,%2,%1") | |
5844 | ||
5845 | (define_insn "" | |
9ebbca7d GK |
5846 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5847 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5848 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5849 | (const_int 0))) |
9ebbca7d | 5850 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 5851 | "TARGET_POWERPC64" |
9ebbca7d GK |
5852 | "@ |
5853 | subf. %3,%2,%1 | |
5854 | #" | |
a62bfff2 | 5855 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
5856 | (set_attr "length" "4,8")]) |
5857 | ||
5858 | (define_split | |
5859 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5860 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5861 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5862 | (const_int 0))) | |
5863 | (clobber (match_scratch:DI 3 ""))] | |
5864 | "TARGET_POWERPC64 && reload_completed" | |
5865 | [(set (match_dup 3) | |
5866 | (minus:DI (match_dup 1) (match_dup 2))) | |
5867 | (set (match_dup 0) | |
5868 | (compare:CC (match_dup 3) | |
5869 | (const_int 0)))] | |
5870 | "") | |
266eb58a DE |
5871 | |
5872 | (define_insn "" | |
9ebbca7d GK |
5873 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
5874 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5875 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5876 | (const_int 0))) |
9ebbca7d | 5877 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
5878 | (minus:DI (match_dup 1) (match_dup 2)))] |
5879 | "TARGET_POWERPC64" | |
9ebbca7d GK |
5880 | "@ |
5881 | subf. %0,%2,%1 | |
5882 | #" | |
a62bfff2 | 5883 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
5884 | (set_attr "length" "4,8")]) |
5885 | ||
5886 | (define_split | |
5887 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5888 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5889 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5890 | (const_int 0))) | |
5891 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5892 | (minus:DI (match_dup 1) (match_dup 2)))] | |
5893 | "TARGET_POWERPC64 && reload_completed" | |
5894 | [(set (match_dup 0) | |
5895 | (minus:DI (match_dup 1) (match_dup 2))) | |
5896 | (set (match_dup 3) | |
5897 | (compare:CC (match_dup 0) | |
5898 | (const_int 0)))] | |
5899 | "") | |
266eb58a DE |
5900 | |
5901 | (define_expand "subdi3" | |
5902 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5903 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
2bfcf297 | 5904 | (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))] |
266eb58a DE |
5905 | "" |
5906 | " | |
5907 | { | |
5908 | if (GET_CODE (operands[2]) == CONST_INT) | |
5909 | { | |
5910 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
5911 | negate_rtx (DImode, operands[2]))); | |
5912 | DONE; | |
5913 | } | |
5914 | }") | |
5915 | ||
ea112fc4 | 5916 | (define_insn_and_split "absdi2" |
266eb58a | 5917 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 5918 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) |
266eb58a DE |
5919 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
5920 | "TARGET_POWERPC64" | |
ea112fc4 DE |
5921 | "#" |
5922 | "&& reload_completed" | |
a260abc9 | 5923 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5924 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 5925 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
5926 | "") |
5927 | ||
ea112fc4 | 5928 | (define_insn_and_split "*nabsdi2" |
266eb58a | 5929 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 5930 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) |
266eb58a DE |
5931 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
5932 | "TARGET_POWERPC64" | |
ea112fc4 DE |
5933 | "#" |
5934 | "&& reload_completed" | |
a260abc9 | 5935 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5936 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 5937 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
5938 | "") |
5939 | ||
5940 | (define_expand "negdi2" | |
5941 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5942 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
5943 | "" | |
5944 | "") | |
5945 | ||
5946 | (define_insn "" | |
5947 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5948 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5949 | "TARGET_POWERPC64" | |
5950 | "neg %0,%1") | |
5951 | ||
5952 | (define_insn "" | |
9ebbca7d GK |
5953 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5954 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5955 | (const_int 0))) |
9ebbca7d | 5956 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 5957 | "TARGET_POWERPC64" |
9ebbca7d GK |
5958 | "@ |
5959 | neg. %2,%1 | |
5960 | #" | |
a62bfff2 | 5961 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
5962 | (set_attr "length" "4,8")]) |
5963 | ||
5964 | (define_split | |
5965 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5966 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5967 | (const_int 0))) | |
5968 | (clobber (match_scratch:DI 2 ""))] | |
5969 | "TARGET_POWERPC64 && reload_completed" | |
5970 | [(set (match_dup 2) | |
5971 | (neg:DI (match_dup 1))) | |
5972 | (set (match_dup 0) | |
5973 | (compare:CC (match_dup 2) | |
5974 | (const_int 0)))] | |
5975 | "") | |
815cdc52 | 5976 | |
29ae5b89 | 5977 | (define_insn "" |
9ebbca7d GK |
5978 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5979 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 5980 | (const_int 0))) |
9ebbca7d | 5981 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 5982 | (neg:DI (match_dup 1)))] |
29ae5b89 | 5983 | "TARGET_POWERPC64" |
9ebbca7d GK |
5984 | "@ |
5985 | neg. %0,%1 | |
5986 | #" | |
a62bfff2 | 5987 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
5988 | (set_attr "length" "4,8")]) |
5989 | ||
5990 | (define_split | |
5991 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5992 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5993 | (const_int 0))) | |
5994 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5995 | (neg:DI (match_dup 1)))] | |
5996 | "TARGET_POWERPC64 && reload_completed" | |
5997 | [(set (match_dup 0) | |
5998 | (neg:DI (match_dup 1))) | |
5999 | (set (match_dup 2) | |
6000 | (compare:CC (match_dup 0) | |
6001 | (const_int 0)))] | |
6002 | "") | |
266eb58a | 6003 | |
1b1edcfa DE |
6004 | (define_insn "clzdi2" |
6005 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6006 | (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6007 | "TARGET_POWERPC64" | |
6008 | "cntlzd %0,%1") | |
6009 | ||
6010 | (define_expand "ctzdi2" | |
4977bab6 | 6011 | [(set (match_dup 2) |
1b1edcfa | 6012 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) |
4977bab6 | 6013 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) |
1b1edcfa DE |
6014 | (match_dup 2))) |
6015 | (clobber (scratch:CC))]) | |
d865b122 | 6016 | (set (match_dup 4) (clz:DI (match_dup 3))) |
4977bab6 | 6017 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 6018 | (minus:DI (const_int 63) (match_dup 4)))] |
266eb58a | 6019 | "TARGET_POWERPC64" |
4977bab6 ZW |
6020 | { |
6021 | operands[2] = gen_reg_rtx (DImode); | |
6022 | operands[3] = gen_reg_rtx (DImode); | |
6023 | operands[4] = gen_reg_rtx (DImode); | |
6024 | }) | |
6025 | ||
1b1edcfa DE |
6026 | (define_expand "ffsdi2" |
6027 | [(set (match_dup 2) | |
6028 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
6029 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) | |
6030 | (match_dup 2))) | |
6031 | (clobber (scratch:CC))]) | |
6032 | (set (match_dup 4) (clz:DI (match_dup 3))) | |
6033 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6034 | (minus:DI (const_int 64) (match_dup 4)))] | |
4977bab6 | 6035 | "TARGET_POWERPC64" |
1b1edcfa DE |
6036 | { |
6037 | operands[2] = gen_reg_rtx (DImode); | |
6038 | operands[3] = gen_reg_rtx (DImode); | |
6039 | operands[4] = gen_reg_rtx (DImode); | |
6040 | }) | |
266eb58a DE |
6041 | |
6042 | (define_insn "muldi3" | |
6043 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6044 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
6045 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6046 | "TARGET_POWERPC64" | |
6047 | "mulld %0,%1,%2" | |
3cb999d8 | 6048 | [(set_attr "type" "lmul")]) |
266eb58a | 6049 | |
9259f3b0 DE |
6050 | (define_insn "*muldi3_internal1" |
6051 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6052 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6053 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
6054 | (const_int 0))) | |
6055 | (clobber (match_scratch:DI 3 "=r,r"))] | |
6056 | "TARGET_POWERPC64" | |
6057 | "@ | |
6058 | mulld. %3,%1,%2 | |
6059 | #" | |
6060 | [(set_attr "type" "lmul_compare") | |
6061 | (set_attr "length" "4,8")]) | |
6062 | ||
6063 | (define_split | |
6064 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6065 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6066 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6067 | (const_int 0))) | |
6068 | (clobber (match_scratch:DI 3 ""))] | |
6069 | "TARGET_POWERPC64 && reload_completed" | |
6070 | [(set (match_dup 3) | |
6071 | (mult:DI (match_dup 1) (match_dup 2))) | |
6072 | (set (match_dup 0) | |
6073 | (compare:CC (match_dup 3) | |
6074 | (const_int 0)))] | |
6075 | "") | |
6076 | ||
6077 | (define_insn "*muldi3_internal2" | |
6078 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") | |
6079 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6080 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
6081 | (const_int 0))) | |
6082 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6083 | (mult:DI (match_dup 1) (match_dup 2)))] | |
6084 | "TARGET_POWERPC64" | |
6085 | "@ | |
6086 | mulld. %0,%1,%2 | |
6087 | #" | |
6088 | [(set_attr "type" "lmul_compare") | |
6089 | (set_attr "length" "4,8")]) | |
6090 | ||
6091 | (define_split | |
6092 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6093 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6094 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6095 | (const_int 0))) | |
6096 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6097 | (mult:DI (match_dup 1) (match_dup 2)))] | |
6098 | "TARGET_POWERPC64 && reload_completed" | |
6099 | [(set (match_dup 0) | |
6100 | (mult:DI (match_dup 1) (match_dup 2))) | |
6101 | (set (match_dup 3) | |
6102 | (compare:CC (match_dup 0) | |
6103 | (const_int 0)))] | |
6104 | "") | |
6105 | ||
266eb58a DE |
6106 | (define_insn "smuldi3_highpart" |
6107 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6108 | (truncate:DI | |
6109 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
6110 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6111 | (sign_extend:TI | |
6112 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6113 | (const_int 64))))] | |
6114 | "TARGET_POWERPC64" | |
6115 | "mulhd %0,%1,%2" | |
3cb999d8 | 6116 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6117 | |
6118 | (define_insn "umuldi3_highpart" | |
6119 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6120 | (truncate:DI | |
6121 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
6122 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6123 | (zero_extend:TI | |
6124 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6125 | (const_int 64))))] | |
6126 | "TARGET_POWERPC64" | |
6127 | "mulhdu %0,%1,%2" | |
3cb999d8 | 6128 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6129 | |
6130 | (define_expand "divdi3" | |
6131 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6132 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6133 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6134 | "TARGET_POWERPC64" | |
6135 | " | |
6136 | { | |
6137 | if (GET_CODE (operands[2]) == CONST_INT | |
2bfcf297 | 6138 | && INTVAL (operands[2]) > 0 |
266eb58a DE |
6139 | && exact_log2 (INTVAL (operands[2])) >= 0) |
6140 | ; | |
6141 | else | |
6142 | operands[2] = force_reg (DImode, operands[2]); | |
6143 | }") | |
6144 | ||
6145 | (define_expand "moddi3" | |
6146 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6147 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6148 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6149 | "TARGET_POWERPC64" | |
6150 | " | |
6151 | { | |
2bfcf297 | 6152 | int i; |
266eb58a DE |
6153 | rtx temp1; |
6154 | rtx temp2; | |
6155 | ||
2bfcf297 DB |
6156 | if (GET_CODE (operands[2]) != CONST_INT |
6157 | || INTVAL (operands[2]) <= 0 | |
6158 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) | |
266eb58a DE |
6159 | FAIL; |
6160 | ||
6161 | temp1 = gen_reg_rtx (DImode); | |
6162 | temp2 = gen_reg_rtx (DImode); | |
6163 | ||
6164 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6165 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6166 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6167 | DONE; | |
6168 | }") | |
6169 | ||
6170 | (define_insn "" | |
6171 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6172 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
6173 | (match_operand:DI 2 "exact_log2_cint_operand" "N")))] |
6174 | "TARGET_POWERPC64" | |
266eb58a DE |
6175 | "sradi %0,%1,%p2\;addze %0,%0" |
6176 | [(set_attr "length" "8")]) | |
6177 | ||
6178 | (define_insn "" | |
9ebbca7d GK |
6179 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6180 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6181 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6182 | (const_int 0))) |
9ebbca7d | 6183 | (clobber (match_scratch:DI 3 "=r,r"))] |
2bfcf297 | 6184 | "TARGET_POWERPC64" |
9ebbca7d GK |
6185 | "@ |
6186 | sradi %3,%1,%p2\;addze. %3,%3 | |
6187 | #" | |
266eb58a | 6188 | [(set_attr "type" "compare") |
9ebbca7d GK |
6189 | (set_attr "length" "8,12")]) |
6190 | ||
6191 | (define_split | |
6192 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6193 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6194 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6195 | (const_int 0))) |
6196 | (clobber (match_scratch:DI 3 ""))] | |
2bfcf297 | 6197 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6198 | [(set (match_dup 3) |
6199 | (div:DI (match_dup 1) (match_dup 2))) | |
6200 | (set (match_dup 0) | |
6201 | (compare:CC (match_dup 3) | |
6202 | (const_int 0)))] | |
6203 | "") | |
266eb58a DE |
6204 | |
6205 | (define_insn "" | |
9ebbca7d GK |
6206 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6207 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6208 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6209 | (const_int 0))) |
9ebbca7d | 6210 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6211 | (div:DI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 6212 | "TARGET_POWERPC64" |
9ebbca7d GK |
6213 | "@ |
6214 | sradi %0,%1,%p2\;addze. %0,%0 | |
6215 | #" | |
266eb58a | 6216 | [(set_attr "type" "compare") |
9ebbca7d | 6217 | (set_attr "length" "8,12")]) |
266eb58a | 6218 | |
9ebbca7d GK |
6219 | (define_split |
6220 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6221 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6222 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6223 | (const_int 0))) |
6224 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6225 | (div:DI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 6226 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6227 | [(set (match_dup 0) |
6228 | (div:DI (match_dup 1) (match_dup 2))) | |
6229 | (set (match_dup 3) | |
6230 | (compare:CC (match_dup 0) | |
6231 | (const_int 0)))] | |
6232 | "") | |
6233 | ||
6234 | (define_insn "" | |
6235 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6236 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6237 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6238 | "TARGET_POWERPC64" |
6239 | "divd %0,%1,%2" | |
3cb999d8 | 6240 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6241 | |
6242 | (define_insn "udivdi3" | |
6243 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6244 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6245 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6246 | "TARGET_POWERPC64" | |
6247 | "divdu %0,%1,%2" | |
3cb999d8 | 6248 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6249 | |
6250 | (define_insn "rotldi3" | |
6251 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6252 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6253 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6254 | "TARGET_POWERPC64" | |
a66078ee | 6255 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6256 | |
a260abc9 | 6257 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6258 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6259 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6260 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6261 | (const_int 0))) |
9ebbca7d | 6262 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6263 | "TARGET_POWERPC64" |
9ebbca7d GK |
6264 | "@ |
6265 | rld%I2cl. %3,%1,%H2,0 | |
6266 | #" | |
6267 | [(set_attr "type" "delayed_compare") | |
6268 | (set_attr "length" "4,8")]) | |
6269 | ||
6270 | (define_split | |
6271 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6272 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6273 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6274 | (const_int 0))) | |
6275 | (clobber (match_scratch:DI 3 ""))] | |
6276 | "TARGET_POWERPC64 && reload_completed" | |
6277 | [(set (match_dup 3) | |
6278 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6279 | (set (match_dup 0) | |
6280 | (compare:CC (match_dup 3) | |
6281 | (const_int 0)))] | |
6282 | "") | |
266eb58a | 6283 | |
a260abc9 | 6284 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6285 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6286 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6287 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6288 | (const_int 0))) |
9ebbca7d | 6289 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6290 | (rotate:DI (match_dup 1) (match_dup 2)))] |
6291 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6292 | "@ |
6293 | rld%I2cl. %0,%1,%H2,0 | |
6294 | #" | |
6295 | [(set_attr "type" "delayed_compare") | |
6296 | (set_attr "length" "4,8")]) | |
6297 | ||
6298 | (define_split | |
6299 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6300 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6301 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6302 | (const_int 0))) | |
6303 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6304 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6305 | "TARGET_POWERPC64 && reload_completed" | |
6306 | [(set (match_dup 0) | |
6307 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6308 | (set (match_dup 3) | |
6309 | (compare:CC (match_dup 0) | |
6310 | (const_int 0)))] | |
6311 | "") | |
266eb58a | 6312 | |
a260abc9 DE |
6313 | (define_insn "*rotldi3_internal4" |
6314 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6315 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6316 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
ce71f754 | 6317 | (match_operand:DI 3 "mask64_operand" "n")))] |
a260abc9 DE |
6318 | "TARGET_POWERPC64" |
6319 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6320 | ||
6321 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6322 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6323 | (compare:CC (and:DI |
9ebbca7d GK |
6324 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6325 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6326 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6327 | (const_int 0))) |
9ebbca7d | 6328 | (clobber (match_scratch:DI 4 "=r,r"))] |
a260abc9 | 6329 | "TARGET_POWERPC64" |
9ebbca7d GK |
6330 | "@ |
6331 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6332 | #" | |
6333 | [(set_attr "type" "delayed_compare") | |
6334 | (set_attr "length" "4,8")]) | |
6335 | ||
6336 | (define_split | |
6337 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6338 | (compare:CC (and:DI | |
6339 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6340 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6341 | (match_operand:DI 3 "mask64_operand" "")) | |
6342 | (const_int 0))) | |
6343 | (clobber (match_scratch:DI 4 ""))] | |
6344 | "TARGET_POWERPC64 && reload_completed" | |
6345 | [(set (match_dup 4) | |
6346 | (and:DI (rotate:DI (match_dup 1) | |
6347 | (match_dup 2)) | |
6348 | (match_dup 3))) | |
6349 | (set (match_dup 0) | |
6350 | (compare:CC (match_dup 4) | |
6351 | (const_int 0)))] | |
6352 | "") | |
a260abc9 DE |
6353 | |
6354 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6355 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6356 | (compare:CC (and:DI |
9ebbca7d GK |
6357 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6358 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6359 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6360 | (const_int 0))) |
9ebbca7d | 6361 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6362 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
6363 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6364 | "@ |
6365 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6366 | #" | |
6367 | [(set_attr "type" "delayed_compare") | |
6368 | (set_attr "length" "4,8")]) | |
6369 | ||
6370 | (define_split | |
6371 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6372 | (compare:CC (and:DI | |
6373 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6374 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6375 | (match_operand:DI 3 "mask64_operand" "")) | |
6376 | (const_int 0))) | |
6377 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6378 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6379 | "TARGET_POWERPC64 && reload_completed" | |
6380 | [(set (match_dup 0) | |
6381 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6382 | (set (match_dup 4) | |
6383 | (compare:CC (match_dup 0) | |
6384 | (const_int 0)))] | |
6385 | "") | |
a260abc9 DE |
6386 | |
6387 | (define_insn "*rotldi3_internal7" | |
6388 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6389 | (zero_extend:DI | |
6390 | (subreg:QI | |
6391 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6392 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6393 | "TARGET_POWERPC64" | |
6394 | "rld%I2cl %0,%1,%H2,56") | |
6395 | ||
6396 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6397 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6398 | (compare:CC (zero_extend:DI |
6399 | (subreg:QI | |
9ebbca7d GK |
6400 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6401 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6402 | (const_int 0))) |
9ebbca7d | 6403 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6404 | "TARGET_POWERPC64" |
9ebbca7d GK |
6405 | "@ |
6406 | rld%I2cl. %3,%1,%H2,56 | |
6407 | #" | |
6408 | [(set_attr "type" "delayed_compare") | |
6409 | (set_attr "length" "4,8")]) | |
6410 | ||
6411 | (define_split | |
6412 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6413 | (compare:CC (zero_extend:DI | |
6414 | (subreg:QI | |
6415 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6416 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6417 | (const_int 0))) | |
6418 | (clobber (match_scratch:DI 3 ""))] | |
6419 | "TARGET_POWERPC64 && reload_completed" | |
6420 | [(set (match_dup 3) | |
6421 | (zero_extend:DI (subreg:QI | |
6422 | (rotate:DI (match_dup 1) | |
6423 | (match_dup 2)) 0))) | |
6424 | (set (match_dup 0) | |
6425 | (compare:CC (match_dup 3) | |
6426 | (const_int 0)))] | |
6427 | "") | |
a260abc9 DE |
6428 | |
6429 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6430 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6431 | (compare:CC (zero_extend:DI |
6432 | (subreg:QI | |
9ebbca7d GK |
6433 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6434 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6435 | (const_int 0))) |
9ebbca7d | 6436 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6437 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6438 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6439 | "@ |
6440 | rld%I2cl. %0,%1,%H2,56 | |
6441 | #" | |
6442 | [(set_attr "type" "delayed_compare") | |
6443 | (set_attr "length" "4,8")]) | |
6444 | ||
6445 | (define_split | |
6446 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6447 | (compare:CC (zero_extend:DI | |
6448 | (subreg:QI | |
6449 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6450 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6451 | (const_int 0))) | |
6452 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6453 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6454 | "TARGET_POWERPC64 && reload_completed" | |
6455 | [(set (match_dup 0) | |
6456 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6457 | (set (match_dup 3) | |
6458 | (compare:CC (match_dup 0) | |
6459 | (const_int 0)))] | |
6460 | "") | |
a260abc9 DE |
6461 | |
6462 | (define_insn "*rotldi3_internal10" | |
6463 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6464 | (zero_extend:DI | |
6465 | (subreg:HI | |
6466 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6467 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6468 | "TARGET_POWERPC64" | |
6469 | "rld%I2cl %0,%1,%H2,48") | |
6470 | ||
6471 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6472 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6473 | (compare:CC (zero_extend:DI |
6474 | (subreg:HI | |
9ebbca7d GK |
6475 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6476 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6477 | (const_int 0))) |
9ebbca7d | 6478 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6479 | "TARGET_POWERPC64" |
9ebbca7d GK |
6480 | "@ |
6481 | rld%I2cl. %3,%1,%H2,48 | |
6482 | #" | |
6483 | [(set_attr "type" "delayed_compare") | |
6484 | (set_attr "length" "4,8")]) | |
6485 | ||
6486 | (define_split | |
6487 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6488 | (compare:CC (zero_extend:DI | |
6489 | (subreg:HI | |
6490 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6491 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6492 | (const_int 0))) | |
6493 | (clobber (match_scratch:DI 3 ""))] | |
6494 | "TARGET_POWERPC64 && reload_completed" | |
6495 | [(set (match_dup 3) | |
6496 | (zero_extend:DI (subreg:HI | |
6497 | (rotate:DI (match_dup 1) | |
6498 | (match_dup 2)) 0))) | |
6499 | (set (match_dup 0) | |
6500 | (compare:CC (match_dup 3) | |
6501 | (const_int 0)))] | |
6502 | "") | |
a260abc9 DE |
6503 | |
6504 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6505 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6506 | (compare:CC (zero_extend:DI |
6507 | (subreg:HI | |
9ebbca7d GK |
6508 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6509 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6510 | (const_int 0))) |
9ebbca7d | 6511 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6512 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6513 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6514 | "@ |
6515 | rld%I2cl. %0,%1,%H2,48 | |
6516 | #" | |
6517 | [(set_attr "type" "delayed_compare") | |
6518 | (set_attr "length" "4,8")]) | |
6519 | ||
6520 | (define_split | |
6521 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6522 | (compare:CC (zero_extend:DI | |
6523 | (subreg:HI | |
6524 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6525 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6526 | (const_int 0))) | |
6527 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6528 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6529 | "TARGET_POWERPC64 && reload_completed" | |
6530 | [(set (match_dup 0) | |
6531 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6532 | (set (match_dup 3) | |
6533 | (compare:CC (match_dup 0) | |
6534 | (const_int 0)))] | |
6535 | "") | |
a260abc9 DE |
6536 | |
6537 | (define_insn "*rotldi3_internal13" | |
6538 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6539 | (zero_extend:DI | |
6540 | (subreg:SI | |
6541 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6542 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6543 | "TARGET_POWERPC64" | |
6544 | "rld%I2cl %0,%1,%H2,32") | |
6545 | ||
6546 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6547 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6548 | (compare:CC (zero_extend:DI |
6549 | (subreg:SI | |
9ebbca7d GK |
6550 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6551 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6552 | (const_int 0))) |
9ebbca7d | 6553 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6554 | "TARGET_POWERPC64" |
9ebbca7d GK |
6555 | "@ |
6556 | rld%I2cl. %3,%1,%H2,32 | |
6557 | #" | |
6558 | [(set_attr "type" "delayed_compare") | |
6559 | (set_attr "length" "4,8")]) | |
6560 | ||
6561 | (define_split | |
6562 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6563 | (compare:CC (zero_extend:DI | |
6564 | (subreg:SI | |
6565 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6566 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6567 | (const_int 0))) | |
6568 | (clobber (match_scratch:DI 3 ""))] | |
6569 | "TARGET_POWERPC64 && reload_completed" | |
6570 | [(set (match_dup 3) | |
6571 | (zero_extend:DI (subreg:SI | |
6572 | (rotate:DI (match_dup 1) | |
6573 | (match_dup 2)) 0))) | |
6574 | (set (match_dup 0) | |
6575 | (compare:CC (match_dup 3) | |
6576 | (const_int 0)))] | |
6577 | "") | |
a260abc9 DE |
6578 | |
6579 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6580 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6581 | (compare:CC (zero_extend:DI |
6582 | (subreg:SI | |
9ebbca7d GK |
6583 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6584 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6585 | (const_int 0))) |
9ebbca7d | 6586 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6587 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6588 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6589 | "@ |
6590 | rld%I2cl. %0,%1,%H2,32 | |
6591 | #" | |
6592 | [(set_attr "type" "delayed_compare") | |
6593 | (set_attr "length" "4,8")]) | |
6594 | ||
6595 | (define_split | |
6596 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6597 | (compare:CC (zero_extend:DI | |
6598 | (subreg:SI | |
6599 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6600 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6601 | (const_int 0))) | |
6602 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6603 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6604 | "TARGET_POWERPC64 && reload_completed" | |
6605 | [(set (match_dup 0) | |
6606 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6607 | (set (match_dup 3) | |
6608 | (compare:CC (match_dup 0) | |
6609 | (const_int 0)))] | |
6610 | "") | |
a260abc9 | 6611 | |
266eb58a DE |
6612 | (define_expand "ashldi3" |
6613 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6614 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6615 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6616 | "TARGET_POWERPC64 || TARGET_POWER" | |
6617 | " | |
6618 | { | |
6619 | if (TARGET_POWERPC64) | |
6620 | ; | |
6621 | else if (TARGET_POWER) | |
6622 | { | |
6623 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6624 | DONE; | |
6625 | } | |
6626 | else | |
6627 | FAIL; | |
6628 | }") | |
6629 | ||
e2c953b6 | 6630 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
6631 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6632 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6633 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6634 | "TARGET_POWERPC64" | |
a66078ee | 6635 | "sld%I2 %0,%1,%H2" |
266eb58a DE |
6636 | [(set_attr "length" "8")]) |
6637 | ||
e2c953b6 | 6638 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
6639 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6640 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6641 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6642 | (const_int 0))) |
9ebbca7d | 6643 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6644 | "TARGET_POWERPC64" |
9ebbca7d GK |
6645 | "@ |
6646 | sld%I2. %3,%1,%H2 | |
6647 | #" | |
6648 | [(set_attr "type" "delayed_compare") | |
6649 | (set_attr "length" "4,8")]) | |
29ae5b89 | 6650 | |
9ebbca7d GK |
6651 | (define_split |
6652 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6653 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6654 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6655 | (const_int 0))) | |
6656 | (clobber (match_scratch:DI 3 ""))] | |
6657 | "TARGET_POWERPC64 && reload_completed" | |
6658 | [(set (match_dup 3) | |
6659 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6660 | (set (match_dup 0) | |
6661 | (compare:CC (match_dup 3) | |
6662 | (const_int 0)))] | |
6663 | "") | |
6664 | ||
e2c953b6 | 6665 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
6666 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6667 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6668 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6669 | (const_int 0))) |
9ebbca7d | 6670 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6671 | (ashift:DI (match_dup 1) (match_dup 2)))] |
6672 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6673 | "@ |
6674 | sld%I2. %0,%1,%H2 | |
6675 | #" | |
6676 | [(set_attr "type" "delayed_compare") | |
6677 | (set_attr "length" "4,8")]) | |
6678 | ||
6679 | (define_split | |
6680 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6681 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6682 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6683 | (const_int 0))) | |
6684 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6685 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6686 | "TARGET_POWERPC64 && reload_completed" | |
6687 | [(set (match_dup 0) | |
6688 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6689 | (set (match_dup 3) | |
6690 | (compare:CC (match_dup 0) | |
6691 | (const_int 0)))] | |
6692 | "") | |
266eb58a | 6693 | |
e2c953b6 | 6694 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
6695 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6696 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6697 | (match_operand:SI 2 "const_int_operand" "i")) | |
c5059423 AM |
6698 | (match_operand:DI 3 "const_int_operand" "n")))] |
6699 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" | |
e2c953b6 | 6700 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 6701 | |
e2c953b6 | 6702 | (define_insn "ashldi3_internal5" |
9ebbca7d | 6703 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6704 | (compare:CC |
9ebbca7d GK |
6705 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6706 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6707 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6708 | (const_int 0))) |
9ebbca7d | 6709 | (clobber (match_scratch:DI 4 "=r,r"))] |
c5059423 | 6710 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6711 | "@ |
e2c953b6 | 6712 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
6713 | #" |
6714 | [(set_attr "type" "delayed_compare") | |
6715 | (set_attr "length" "4,8")]) | |
6716 | ||
6717 | (define_split | |
6718 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6719 | (compare:CC | |
6720 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6721 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6722 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6723 | (const_int 0))) |
6724 | (clobber (match_scratch:DI 4 ""))] | |
c5059423 AM |
6725 | "TARGET_POWERPC64 && reload_completed |
6726 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
9ebbca7d GK |
6727 | [(set (match_dup 4) |
6728 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 6729 | (match_dup 3))) |
9ebbca7d GK |
6730 | (set (match_dup 0) |
6731 | (compare:CC (match_dup 4) | |
6732 | (const_int 0)))] | |
6733 | "") | |
3cb999d8 | 6734 | |
e2c953b6 | 6735 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 6736 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6737 | (compare:CC |
9ebbca7d GK |
6738 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6739 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6740 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6741 | (const_int 0))) |
9ebbca7d | 6742 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 6743 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
c5059423 | 6744 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6745 | "@ |
e2c953b6 | 6746 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
6747 | #" |
6748 | [(set_attr "type" "delayed_compare") | |
6749 | (set_attr "length" "4,8")]) | |
6750 | ||
6751 | (define_split | |
6752 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6753 | (compare:CC | |
6754 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6755 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6756 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6757 | (const_int 0))) |
6758 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6759 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
c5059423 AM |
6760 | "TARGET_POWERPC64 && reload_completed |
6761 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
6762 | [(set (match_dup 0) | |
6763 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6764 | (match_dup 3))) | |
6765 | (set (match_dup 4) | |
6766 | (compare:CC (match_dup 0) | |
6767 | (const_int 0)))] | |
6768 | "") | |
6769 | ||
6770 | (define_insn "*ashldi3_internal7" | |
6771 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6772 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6773 | (match_operand:SI 2 "const_int_operand" "i")) | |
ce71f754 | 6774 | (match_operand:DI 3 "mask64_operand" "n")))] |
c5059423 AM |
6775 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" |
6776 | "rldicr %0,%1,%H2,%S3") | |
6777 | ||
6778 | (define_insn "ashldi3_internal8" | |
6779 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6780 | (compare:CC | |
6781 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6782 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6783 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6784 | (const_int 0))) |
6785 | (clobber (match_scratch:DI 4 "=r,r"))] | |
6786 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6787 | "@ | |
6788 | rldicr. %4,%1,%H2,%S3 | |
6789 | #" | |
6790 | [(set_attr "type" "delayed_compare") | |
6791 | (set_attr "length" "4,8")]) | |
6792 | ||
6793 | (define_split | |
6794 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6795 | (compare:CC | |
6796 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6797 | (match_operand:SI 2 "const_int_operand" "")) | |
6798 | (match_operand:DI 3 "mask64_operand" "")) | |
6799 | (const_int 0))) | |
6800 | (clobber (match_scratch:DI 4 ""))] | |
6801 | "TARGET_POWERPC64 && reload_completed | |
6802 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6803 | [(set (match_dup 4) | |
6804 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6805 | (match_dup 3))) | |
6806 | (set (match_dup 0) | |
6807 | (compare:CC (match_dup 4) | |
6808 | (const_int 0)))] | |
6809 | "") | |
6810 | ||
6811 | (define_insn "*ashldi3_internal9" | |
6812 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
6813 | (compare:CC | |
6814 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6815 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6816 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6817 | (const_int 0))) |
6818 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6819 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6820 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6821 | "@ | |
6822 | rldicr. %0,%1,%H2,%S3 | |
6823 | #" | |
6824 | [(set_attr "type" "delayed_compare") | |
6825 | (set_attr "length" "4,8")]) | |
6826 | ||
6827 | (define_split | |
6828 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6829 | (compare:CC | |
6830 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6831 | (match_operand:SI 2 "const_int_operand" "")) | |
6832 | (match_operand:DI 3 "mask64_operand" "")) | |
6833 | (const_int 0))) | |
6834 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6835 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6836 | "TARGET_POWERPC64 && reload_completed | |
6837 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
9ebbca7d | 6838 | [(set (match_dup 0) |
e2c953b6 DE |
6839 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
6840 | (match_dup 3))) | |
9ebbca7d GK |
6841 | (set (match_dup 4) |
6842 | (compare:CC (match_dup 0) | |
6843 | (const_int 0)))] | |
6844 | "") | |
6845 | ||
6846 | (define_expand "lshrdi3" | |
266eb58a DE |
6847 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6848 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6849 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6850 | "TARGET_POWERPC64 || TARGET_POWER" | |
6851 | " | |
6852 | { | |
6853 | if (TARGET_POWERPC64) | |
6854 | ; | |
6855 | else if (TARGET_POWER) | |
6856 | { | |
6857 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
6858 | DONE; | |
6859 | } | |
6860 | else | |
6861 | FAIL; | |
6862 | }") | |
6863 | ||
e2c953b6 | 6864 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
6865 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6866 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6867 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6868 | "TARGET_POWERPC64" | |
a66078ee | 6869 | "srd%I2 %0,%1,%H2") |
266eb58a | 6870 | |
e2c953b6 | 6871 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
6872 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6873 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6874 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 6875 | (const_int 0))) |
9ebbca7d | 6876 | (clobber (match_scratch:DI 3 "=r,r"))] |
29ae5b89 | 6877 | "TARGET_POWERPC64" |
9ebbca7d GK |
6878 | "@ |
6879 | srd%I2. %3,%1,%H2 | |
6880 | #" | |
6881 | [(set_attr "type" "delayed_compare") | |
6882 | (set_attr "length" "4,8")]) | |
6883 | ||
6884 | (define_split | |
6885 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6886 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6887 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6888 | (const_int 0))) | |
6889 | (clobber (match_scratch:DI 3 ""))] | |
6890 | "TARGET_POWERPC64 && reload_completed" | |
6891 | [(set (match_dup 3) | |
6892 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6893 | (set (match_dup 0) | |
6894 | (compare:CC (match_dup 3) | |
6895 | (const_int 0)))] | |
6896 | "") | |
266eb58a | 6897 | |
e2c953b6 | 6898 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
6899 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6900 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6901 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6902 | (const_int 0))) |
9ebbca7d | 6903 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 JL |
6904 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
6905 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6906 | "@ |
6907 | srd%I2. %0,%1,%H2 | |
6908 | #" | |
6909 | [(set_attr "type" "delayed_compare") | |
6910 | (set_attr "length" "4,8")]) | |
6911 | ||
6912 | (define_split | |
6913 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6914 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6915 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6916 | (const_int 0))) | |
6917 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6918 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
6919 | "TARGET_POWERPC64 && reload_completed" | |
6920 | [(set (match_dup 0) | |
6921 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6922 | (set (match_dup 3) | |
6923 | (compare:CC (match_dup 0) | |
6924 | (const_int 0)))] | |
6925 | "") | |
266eb58a DE |
6926 | |
6927 | (define_expand "ashrdi3" | |
6928 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6929 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6930 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4aa74a4f | 6931 | "" |
266eb58a DE |
6932 | " |
6933 | { | |
6934 | if (TARGET_POWERPC64) | |
6935 | ; | |
6936 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
6937 | { | |
6938 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
6939 | DONE; | |
6940 | } | |
4aa74a4f FS |
6941 | else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT) |
6942 | { | |
6943 | emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); | |
6944 | DONE; | |
6945 | } | |
266eb58a DE |
6946 | else |
6947 | FAIL; | |
6948 | }") | |
6949 | ||
e2c953b6 | 6950 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
6951 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6952 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6953 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6954 | "TARGET_POWERPC64" | |
375490e0 | 6955 | "srad%I2 %0,%1,%H2") |
266eb58a | 6956 | |
e2c953b6 | 6957 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
6958 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6959 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6960 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6961 | (const_int 0))) |
9ebbca7d | 6962 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6963 | "TARGET_POWERPC64" |
9ebbca7d GK |
6964 | "@ |
6965 | srad%I2. %3,%1,%H2 | |
6966 | #" | |
6967 | [(set_attr "type" "delayed_compare") | |
6968 | (set_attr "length" "4,8")]) | |
6969 | ||
6970 | (define_split | |
6971 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6972 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6973 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6974 | (const_int 0))) | |
6975 | (clobber (match_scratch:DI 3 ""))] | |
6976 | "TARGET_POWERPC64 && reload_completed" | |
6977 | [(set (match_dup 3) | |
6978 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6979 | (set (match_dup 0) | |
6980 | (compare:CC (match_dup 3) | |
6981 | (const_int 0)))] | |
6982 | "") | |
266eb58a | 6983 | |
e2c953b6 | 6984 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
6985 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6986 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6987 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6988 | (const_int 0))) |
9ebbca7d | 6989 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6990 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6991 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6992 | "@ |
6993 | srad%I2. %0,%1,%H2 | |
6994 | #" | |
6995 | [(set_attr "type" "delayed_compare") | |
6996 | (set_attr "length" "4,8")]) | |
6997 | ||
6998 | (define_split | |
6999 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7000 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7001 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7002 | (const_int 0))) | |
7003 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7004 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
7005 | "TARGET_POWERPC64 && reload_completed" | |
7006 | [(set (match_dup 0) | |
7007 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7008 | (set (match_dup 3) | |
7009 | (compare:CC (match_dup 0) | |
7010 | (const_int 0)))] | |
7011 | "") | |
815cdc52 | 7012 | |
29ae5b89 | 7013 | (define_insn "anddi3" |
0ba1b2ff AM |
7014 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") |
7015 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
7016 | (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t"))) | |
7017 | (clobber (match_scratch:CC 3 "=X,X,x,x,X"))] | |
6ffc8580 | 7018 | "TARGET_POWERPC64" |
266eb58a DE |
7019 | "@ |
7020 | and %0,%1,%2 | |
29ae5b89 JL |
7021 | rldic%B2 %0,%1,0,%S2 |
7022 | andi. %0,%1,%b2 | |
0ba1b2ff AM |
7023 | andis. %0,%1,%u2 |
7024 | #" | |
7025 | [(set_attr "length" "4,4,4,4,8")]) | |
7026 | ||
7027 | (define_split | |
7028 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7029 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7030 | (match_operand:DI 2 "mask64_2_operand" ""))) | |
7031 | (clobber (match_scratch:CC 3 ""))] | |
7032 | "TARGET_POWERPC64 | |
7033 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7034 | && !mask64_operand (operands[2], DImode)" | |
7035 | [(set (match_dup 0) | |
7036 | (and:DI (rotate:DI (match_dup 1) | |
7037 | (match_dup 4)) | |
7038 | (match_dup 5))) | |
7039 | (set (match_dup 0) | |
7040 | (and:DI (rotate:DI (match_dup 0) | |
7041 | (match_dup 6)) | |
7042 | (match_dup 7)))] | |
7043 | " | |
7044 | { | |
7045 | build_mask64_2_operands (operands[2], &operands[4]); | |
7046 | }") | |
266eb58a | 7047 | |
a260abc9 | 7048 | (define_insn "*anddi3_internal2" |
0ba1b2ff AM |
7049 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7050 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7051 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7052 | (const_int 0))) |
0ba1b2ff AM |
7053 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r")) |
7054 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] | |
6ffc8580 | 7055 | "TARGET_POWERPC64" |
266eb58a DE |
7056 | "@ |
7057 | and. %3,%1,%2 | |
6c873122 | 7058 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
7059 | andi. %3,%1,%b2 |
7060 | andis. %3,%1,%u2 | |
9ebbca7d GK |
7061 | # |
7062 | # | |
7063 | # | |
0ba1b2ff AM |
7064 | # |
7065 | # | |
9ebbca7d | 7066 | #" |
0ba1b2ff AM |
7067 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7068 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7069 | |
7070 | (define_split | |
7071 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7072 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7073 | (match_operand:DI 2 "and64_operand" "")) | |
7074 | (const_int 0))) | |
7075 | (clobber (match_scratch:DI 3 "")) | |
7076 | (clobber (match_scratch:CC 4 ""))] | |
7077 | "TARGET_POWERPC64 && reload_completed" | |
7078 | [(parallel [(set (match_dup 3) | |
7079 | (and:DI (match_dup 1) | |
7080 | (match_dup 2))) | |
7081 | (clobber (match_dup 4))]) | |
7082 | (set (match_dup 0) | |
7083 | (compare:CC (match_dup 3) | |
7084 | (const_int 0)))] | |
7085 | "") | |
266eb58a | 7086 | |
0ba1b2ff AM |
7087 | (define_split |
7088 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
7089 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7090 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7091 | (const_int 0))) | |
7092 | (clobber (match_scratch:DI 3 "")) | |
7093 | (clobber (match_scratch:CC 4 ""))] | |
7094 | "TARGET_POWERPC64 && reload_completed | |
7095 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7096 | && !mask64_operand (operands[2], DImode)" | |
7097 | [(set (match_dup 3) | |
7098 | (and:DI (rotate:DI (match_dup 1) | |
7099 | (match_dup 5)) | |
7100 | (match_dup 6))) | |
7101 | (parallel [(set (match_dup 0) | |
7102 | (compare:CC (and:DI (rotate:DI (match_dup 3) | |
7103 | (match_dup 7)) | |
7104 | (match_dup 8)) | |
7105 | (const_int 0))) | |
7106 | (clobber (match_dup 3))])] | |
7107 | " | |
7108 | { | |
7109 | build_mask64_2_operands (operands[2], &operands[5]); | |
7110 | }") | |
7111 | ||
a260abc9 | 7112 | (define_insn "*anddi3_internal3" |
0ba1b2ff AM |
7113 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7114 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7115 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7116 | (const_int 0))) |
0ba1b2ff | 7117 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
9ebbca7d | 7118 | (and:DI (match_dup 1) (match_dup 2))) |
0ba1b2ff | 7119 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] |
6ffc8580 | 7120 | "TARGET_POWERPC64" |
266eb58a DE |
7121 | "@ |
7122 | and. %0,%1,%2 | |
6c873122 | 7123 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
7124 | andi. %0,%1,%b2 |
7125 | andis. %0,%1,%u2 | |
9ebbca7d GK |
7126 | # |
7127 | # | |
7128 | # | |
0ba1b2ff AM |
7129 | # |
7130 | # | |
9ebbca7d | 7131 | #" |
0ba1b2ff AM |
7132 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7133 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7134 | |
7135 | (define_split | |
7136 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7137 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7138 | (match_operand:DI 2 "and64_operand" "")) | |
7139 | (const_int 0))) | |
7140 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7141 | (and:DI (match_dup 1) (match_dup 2))) | |
7142 | (clobber (match_scratch:CC 4 ""))] | |
7143 | "TARGET_POWERPC64 && reload_completed" | |
7144 | [(parallel [(set (match_dup 0) | |
7145 | (and:DI (match_dup 1) (match_dup 2))) | |
7146 | (clobber (match_dup 4))]) | |
7147 | (set (match_dup 3) | |
7148 | (compare:CC (match_dup 0) | |
7149 | (const_int 0)))] | |
7150 | "") | |
266eb58a | 7151 | |
0ba1b2ff AM |
7152 | (define_split |
7153 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
7154 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7155 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7156 | (const_int 0))) | |
7157 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7158 | (and:DI (match_dup 1) (match_dup 2))) | |
7159 | (clobber (match_scratch:CC 4 ""))] | |
7160 | "TARGET_POWERPC64 && reload_completed | |
7161 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7162 | && !mask64_operand (operands[2], DImode)" | |
7163 | [(set (match_dup 0) | |
7164 | (and:DI (rotate:DI (match_dup 1) | |
7165 | (match_dup 5)) | |
7166 | (match_dup 6))) | |
7167 | (parallel [(set (match_dup 3) | |
7168 | (compare:CC (and:DI (rotate:DI (match_dup 0) | |
7169 | (match_dup 7)) | |
7170 | (match_dup 8)) | |
7171 | (const_int 0))) | |
7172 | (set (match_dup 0) | |
7173 | (and:DI (rotate:DI (match_dup 0) | |
7174 | (match_dup 7)) | |
7175 | (match_dup 8)))])] | |
7176 | " | |
7177 | { | |
7178 | build_mask64_2_operands (operands[2], &operands[5]); | |
7179 | }") | |
7180 | ||
a260abc9 | 7181 | (define_expand "iordi3" |
266eb58a | 7182 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 7183 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 7184 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 7185 | "TARGET_POWERPC64" |
266eb58a DE |
7186 | " |
7187 | { | |
dfbdccdb | 7188 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 7189 | { |
dfbdccdb | 7190 | HOST_WIDE_INT value; |
677a9668 | 7191 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 7192 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 7193 | |
dfbdccdb GK |
7194 | if (GET_CODE (operands[2]) == CONST_INT) |
7195 | { | |
7196 | value = INTVAL (operands[2]); | |
7197 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7198 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7199 | } | |
e2c953b6 | 7200 | else |
dfbdccdb GK |
7201 | { |
7202 | value = CONST_DOUBLE_LOW (operands[2]); | |
7203 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7204 | immed_double_const (value | |
7205 | & (~ (HOST_WIDE_INT) 0xffff), | |
7206 | 0, DImode))); | |
7207 | } | |
e2c953b6 | 7208 | |
9ebbca7d GK |
7209 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7210 | DONE; | |
7211 | } | |
266eb58a DE |
7212 | }") |
7213 | ||
a260abc9 DE |
7214 | (define_expand "xordi3" |
7215 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7216 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 7217 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
7218 | "TARGET_POWERPC64" |
7219 | " | |
7220 | { | |
dfbdccdb | 7221 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 7222 | { |
dfbdccdb | 7223 | HOST_WIDE_INT value; |
677a9668 | 7224 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
7225 | ? operands[0] : gen_reg_rtx (DImode)); |
7226 | ||
dfbdccdb GK |
7227 | if (GET_CODE (operands[2]) == CONST_INT) |
7228 | { | |
7229 | value = INTVAL (operands[2]); | |
7230 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7231 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7232 | } | |
e2c953b6 | 7233 | else |
dfbdccdb GK |
7234 | { |
7235 | value = CONST_DOUBLE_LOW (operands[2]); | |
7236 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7237 | immed_double_const (value | |
7238 | & (~ (HOST_WIDE_INT) 0xffff), | |
7239 | 0, DImode))); | |
7240 | } | |
e2c953b6 | 7241 | |
9ebbca7d GK |
7242 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7243 | DONE; | |
7244 | } | |
a260abc9 DE |
7245 | }") |
7246 | ||
dfbdccdb | 7247 | (define_insn "*booldi3_internal1" |
266eb58a | 7248 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 7249 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7250 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
7251 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 7252 | "TARGET_POWERPC64" |
1fd4e8c1 | 7253 | "@ |
dfbdccdb GK |
7254 | %q3 %0,%1,%2 |
7255 | %q3i %0,%1,%b2 | |
7256 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 7257 | |
dfbdccdb | 7258 | (define_insn "*booldi3_internal2" |
9ebbca7d | 7259 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 7260 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
7261 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
7262 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7263 | (const_int 0))) | |
9ebbca7d | 7264 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7265 | "TARGET_POWERPC64" |
9ebbca7d | 7266 | "@ |
dfbdccdb | 7267 | %q4. %3,%1,%2 |
9ebbca7d GK |
7268 | #" |
7269 | [(set_attr "type" "compare") | |
7270 | (set_attr "length" "4,8")]) | |
7271 | ||
7272 | (define_split | |
7273 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7274 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7275 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7276 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7277 | (const_int 0))) |
9ebbca7d GK |
7278 | (clobber (match_scratch:DI 3 ""))] |
7279 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7280 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7281 | (set (match_dup 0) |
7282 | (compare:CC (match_dup 3) | |
7283 | (const_int 0)))] | |
7284 | "") | |
1fd4e8c1 | 7285 | |
dfbdccdb | 7286 | (define_insn "*booldi3_internal3" |
9ebbca7d | 7287 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7288 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7289 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7290 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7291 | (const_int 0))) | |
9ebbca7d | 7292 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7293 | (match_dup 4))] |
266eb58a | 7294 | "TARGET_POWERPC64" |
9ebbca7d | 7295 | "@ |
dfbdccdb | 7296 | %q4. %0,%1,%2 |
9ebbca7d GK |
7297 | #" |
7298 | [(set_attr "type" "compare") | |
7299 | (set_attr "length" "4,8")]) | |
7300 | ||
7301 | (define_split | |
e72247f4 | 7302 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7303 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7304 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7305 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7306 | (const_int 0))) |
75540af0 | 7307 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7308 | (match_dup 4))] |
9ebbca7d | 7309 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7310 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7311 | (set (match_dup 3) |
7312 | (compare:CC (match_dup 0) | |
7313 | (const_int 0)))] | |
7314 | "") | |
1fd4e8c1 | 7315 | |
5bdc5878 | 7316 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 7317 | ;; each of which does one 16-bit part. This is used by combine. |
266eb58a DE |
7318 | |
7319 | (define_split | |
7320 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 7321 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7322 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7323 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7324 | "TARGET_POWERPC64" |
dfbdccdb GK |
7325 | [(set (match_dup 0) (match_dup 4)) |
7326 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7327 | " |
7328 | { | |
dfbdccdb GK |
7329 | rtx i3,i4; |
7330 | ||
9ebbca7d GK |
7331 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7332 | { | |
7333 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7334 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7335 | 0, DImode); |
dfbdccdb | 7336 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7337 | } |
7338 | else | |
7339 | { | |
dfbdccdb | 7340 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7341 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7342 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7343 | } |
dfbdccdb GK |
7344 | operands[4] = gen_rtx (GET_CODE (operands[3]), DImode, |
7345 | operands[1], i3); | |
7346 | operands[5] = gen_rtx (GET_CODE (operands[3]), DImode, | |
7347 | operands[0], i4); | |
1fd4e8c1 RK |
7348 | }") |
7349 | ||
dfbdccdb | 7350 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7351 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7352 | (match_operator:DI 3 "boolean_operator" |
7353 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7354 | (match_operand:DI 2 "gpc_reg_operand" "r")]))] |
a473029f | 7355 | "TARGET_POWERPC64" |
1d328b19 | 7356 | "%q3 %0,%2,%1") |
a473029f | 7357 | |
dfbdccdb | 7358 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7359 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7360 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7361 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7362 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7363 | (const_int 0))) | |
9ebbca7d | 7364 | (clobber (match_scratch:DI 3 "=r,r"))] |
a473029f | 7365 | "TARGET_POWERPC64" |
9ebbca7d | 7366 | "@ |
1d328b19 | 7367 | %q4. %3,%2,%1 |
9ebbca7d GK |
7368 | #" |
7369 | [(set_attr "type" "compare") | |
7370 | (set_attr "length" "4,8")]) | |
7371 | ||
7372 | (define_split | |
7373 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7374 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7375 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7376 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7377 | (const_int 0))) |
9ebbca7d GK |
7378 | (clobber (match_scratch:DI 3 ""))] |
7379 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7380 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7381 | (set (match_dup 0) |
7382 | (compare:CC (match_dup 3) | |
7383 | (const_int 0)))] | |
7384 | "") | |
a473029f | 7385 | |
dfbdccdb | 7386 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7387 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7388 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7389 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7390 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7391 | (const_int 0))) | |
9ebbca7d | 7392 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7393 | (match_dup 4))] |
a473029f | 7394 | "TARGET_POWERPC64" |
9ebbca7d | 7395 | "@ |
1d328b19 | 7396 | %q4. %0,%2,%1 |
9ebbca7d GK |
7397 | #" |
7398 | [(set_attr "type" "compare") | |
7399 | (set_attr "length" "4,8")]) | |
7400 | ||
7401 | (define_split | |
e72247f4 | 7402 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7403 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7404 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7405 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7406 | (const_int 0))) |
75540af0 | 7407 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7408 | (match_dup 4))] |
9ebbca7d | 7409 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7410 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7411 | (set (match_dup 3) |
7412 | (compare:CC (match_dup 0) | |
7413 | (const_int 0)))] | |
7414 | "") | |
266eb58a | 7415 | |
dfbdccdb | 7416 | (define_insn "*boolccdi3_internal1" |
a473029f | 7417 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7418 | (match_operator:DI 3 "boolean_operator" |
7419 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7420 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] |
a473029f | 7421 | "TARGET_POWERPC64" |
dfbdccdb | 7422 | "%q3 %0,%1,%2") |
a473029f | 7423 | |
dfbdccdb | 7424 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7425 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7426 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7427 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7428 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7429 | (const_int 0))) | |
9ebbca7d | 7430 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7431 | "TARGET_POWERPC64" |
9ebbca7d | 7432 | "@ |
dfbdccdb | 7433 | %q4. %3,%1,%2 |
9ebbca7d GK |
7434 | #" |
7435 | [(set_attr "type" "compare") | |
7436 | (set_attr "length" "4,8")]) | |
7437 | ||
7438 | (define_split | |
7439 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7440 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7441 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7442 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7443 | (const_int 0))) |
9ebbca7d GK |
7444 | (clobber (match_scratch:DI 3 ""))] |
7445 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7446 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7447 | (set (match_dup 0) |
7448 | (compare:CC (match_dup 3) | |
7449 | (const_int 0)))] | |
7450 | "") | |
266eb58a | 7451 | |
dfbdccdb | 7452 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7453 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7454 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7455 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7456 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7457 | (const_int 0))) | |
9ebbca7d | 7458 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7459 | (match_dup 4))] |
29ae5b89 | 7460 | "TARGET_POWERPC64" |
9ebbca7d | 7461 | "@ |
dfbdccdb | 7462 | %q4. %0,%1,%2 |
9ebbca7d GK |
7463 | #" |
7464 | [(set_attr "type" "compare") | |
7465 | (set_attr "length" "4,8")]) | |
7466 | ||
7467 | (define_split | |
e72247f4 | 7468 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7469 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7470 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7471 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7472 | (const_int 0))) |
75540af0 | 7473 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7474 | (match_dup 4))] |
9ebbca7d | 7475 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7476 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7477 | (set (match_dup 3) |
7478 | (compare:CC (match_dup 0) | |
7479 | (const_int 0)))] | |
7480 | "") | |
dfbdccdb | 7481 | \f |
1fd4e8c1 | 7482 | ;; Now define ways of moving data around. |
4697a36c MM |
7483 | |
7484 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
7485 | ;; The output of this could be r0, but we make a very strong |
7486 | ;; preference for a base register because it will usually | |
7487 | ;; be needed there. | |
4697a36c | 7488 | (define_insn "elf_high" |
9ebbca7d | 7489 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 7490 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 7491 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 7492 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
7493 | |
7494 | (define_insn "elf_low" | |
9ebbca7d GK |
7495 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
7496 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 7497 | (match_operand 2 "" "")))] |
0ad91047 | 7498 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
7499 | "@ |
7500 | {cal|la} %0,%2@l(%1) | |
81eace42 | 7501 | {ai|addic} %0,%1,%K2") |
4697a36c | 7502 | |
ee890fe2 SS |
7503 | ;; Mach-O PIC trickery. |
7504 | (define_insn "macho_high" | |
7505 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") | |
7506 | (high:SI (match_operand 1 "" "")))] | |
7507 | "TARGET_MACHO && ! TARGET_64BIT" | |
7508 | "{liu|lis} %0,ha16(%1)") | |
7509 | ||
7510 | (define_insn "macho_low" | |
7511 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
7512 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
7513 | (match_operand 2 "" "")))] | |
7514 | "TARGET_MACHO && ! TARGET_64BIT" | |
7515 | "@ | |
7516 | {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} | |
7517 | {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") | |
7518 | ||
766a866c MM |
7519 | ;; Set up a register with a value from the GOT table |
7520 | ||
7521 | (define_expand "movsi_got" | |
52d3af72 | 7522 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7523 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
615158e2 | 7524 | (match_dup 2)] UNSPEC_MOVSI_GOT))] |
f607bc57 | 7525 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7526 | " |
7527 | { | |
38c1f2d7 MM |
7528 | if (GET_CODE (operands[1]) == CONST) |
7529 | { | |
7530 | rtx offset = const0_rtx; | |
7531 | HOST_WIDE_INT value; | |
7532 | ||
7533 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7534 | value = INTVAL (offset); | |
7535 | if (value != 0) | |
7536 | { | |
677a9668 | 7537 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7538 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7539 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7540 | DONE; | |
7541 | } | |
7542 | } | |
7543 | ||
c4c40373 | 7544 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7545 | }") |
7546 | ||
84f414bc | 7547 | (define_insn "*movsi_got_internal" |
52d3af72 | 7548 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d | 7549 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7550 | (match_operand:SI 2 "gpc_reg_operand" "b")] |
7551 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7552 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7553 | "{l|lwz} %0,%a1@got(%2)" |
7554 | [(set_attr "type" "load")]) | |
7555 | ||
b22b9b3e JL |
7556 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7557 | ;; didn't get allocated to a hard register. | |
7558 | (define_split | |
75540af0 | 7559 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7560 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7561 | (match_operand:SI 2 "memory_operand" "")] |
7562 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7563 | "DEFAULT_ABI == ABI_V4 |
b22b9b3e JL |
7564 | && flag_pic == 1 |
7565 | && (reload_in_progress || reload_completed)" | |
7566 | [(set (match_dup 0) (match_dup 2)) | |
615158e2 JJ |
7567 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] |
7568 | UNSPEC_MOVSI_GOT))] | |
b22b9b3e JL |
7569 | "") |
7570 | ||
1fd4e8c1 RK |
7571 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7572 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7573 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7574 | ;; integers in the TOC. | |
7575 | (define_expand "movsi" | |
7576 | [(set (match_operand:SI 0 "general_operand" "") | |
7577 | (match_operand:SI 1 "any_operand" ""))] | |
7578 | "" | |
fb4d4348 | 7579 | "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") |
1fd4e8c1 | 7580 | |
ee890fe2 SS |
7581 | (define_insn "movsi_low" |
7582 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
f585a356 | 7583 | (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
ee890fe2 SS |
7584 | (match_operand 2 "" ""))))] |
7585 | "TARGET_MACHO && ! TARGET_64BIT" | |
7586 | "{l|lwz} %0,lo16(%2)(%1)" | |
7587 | [(set_attr "type" "load") | |
7588 | (set_attr "length" "4")]) | |
7589 | ||
c859cda6 | 7590 | (define_insn "movsi_low_st" |
f585a356 | 7591 | [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
c859cda6 DJ |
7592 | (match_operand 2 "" ""))) |
7593 | (match_operand:SI 0 "gpc_reg_operand" "r"))] | |
7594 | "TARGET_MACHO && ! TARGET_64BIT" | |
7595 | "{st|stw} %0,lo16(%2)(%1)" | |
7596 | [(set_attr "type" "store") | |
7597 | (set_attr "length" "4")]) | |
7598 | ||
7599 | (define_insn "movdf_low" | |
234e114c | 7600 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") |
f585a356 | 7601 | (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 7602 | (match_operand 2 "" ""))))] |
a3170dc6 | 7603 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
234e114c DJ |
7604 | "* |
7605 | { | |
7606 | switch (which_alternative) | |
7607 | { | |
7608 | case 0: | |
7609 | return \"lfd %0,lo16(%2)(%1)\"; | |
7610 | case 1: | |
7611 | { | |
7612 | rtx operands2[4]; | |
7613 | operands2[0] = operands[0]; | |
7614 | operands2[1] = operands[1]; | |
7615 | operands2[2] = operands[2]; | |
1db02437 | 7616 | operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
234e114c | 7617 | output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands); |
ab82a49f AP |
7618 | #if TARGET_MACHO |
7619 | if (MACHO_DYNAMIC_NO_PIC_P) | |
7620 | output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands); | |
7621 | else | |
234e114c DJ |
7622 | /* We cannot rely on ha16(low half)==ha16(high half), alas, |
7623 | although in practice it almost always is. */ | |
7624 | output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2); | |
ab82a49f | 7625 | #endif |
234e114c DJ |
7626 | return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\"); |
7627 | } | |
7628 | default: | |
7629 | abort(); | |
7630 | } | |
7631 | }" | |
c859cda6 | 7632 | [(set_attr "type" "load") |
234e114c | 7633 | (set_attr "length" "4,12")]) |
c859cda6 DJ |
7634 | |
7635 | (define_insn "movdf_low_st" | |
f585a356 | 7636 | [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
c859cda6 DJ |
7637 | (match_operand 2 "" ""))) |
7638 | (match_operand:DF 0 "gpc_reg_operand" "f"))] | |
a3170dc6 | 7639 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
c859cda6 DJ |
7640 | "stfd %0,lo16(%2)(%1)" |
7641 | [(set_attr "type" "store") | |
7642 | (set_attr "length" "4")]) | |
7643 | ||
7644 | (define_insn "movsf_low" | |
fd3b43f2 | 7645 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") |
f585a356 | 7646 | (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 7647 | (match_operand 2 "" ""))))] |
a3170dc6 | 7648 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
fd3b43f2 DJ |
7649 | "@ |
7650 | lfs %0,lo16(%2)(%1) | |
7651 | {l|lwz} %0,lo16(%2)(%1)" | |
c859cda6 DJ |
7652 | [(set_attr "type" "load") |
7653 | (set_attr "length" "4")]) | |
7654 | ||
7655 | (define_insn "movsf_low_st" | |
f585a356 | 7656 | [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 7657 | (match_operand 2 "" ""))) |
fd3b43f2 | 7658 | (match_operand:SF 0 "gpc_reg_operand" "f,!r"))] |
a3170dc6 | 7659 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
fd3b43f2 DJ |
7660 | "@ |
7661 | stfs %0,lo16(%2)(%1) | |
7662 | {st|stw} %0,lo16(%2)(%1)" | |
c859cda6 DJ |
7663 | [(set_attr "type" "store") |
7664 | (set_attr "length" "4")]) | |
7665 | ||
acad7ed3 | 7666 | (define_insn "*movsi_internal1" |
a004eb82 AH |
7667 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") |
7668 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] | |
19d5775a RK |
7669 | "gpc_reg_operand (operands[0], SImode) |
7670 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7671 | "@ |
deb9225a | 7672 | mr %0,%1 |
b9442c72 | 7673 | {cal|la} %0,%a1 |
ca7f5001 RK |
7674 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7675 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7676 | {lil|li} %0,%1 |
802a0058 | 7677 | {liu|lis} %0,%v1 |
beaec479 | 7678 | # |
aee86b38 | 7679 | {cal|la} %0,%a1 |
1fd4e8c1 | 7680 | mf%1 %0 |
5c23c401 | 7681 | mt%0 %1 |
e76e75bb | 7682 | mt%0 %1 |
a004eb82 | 7683 | mt%0 %1 |
e34eaae5 | 7684 | {cror 0,0,0|nop}" |
a004eb82 AH |
7685 | [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*,*") |
7686 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) | |
1fd4e8c1 | 7687 | |
77fa0940 RK |
7688 | ;; Split a load of a large constant into the appropriate two-insn |
7689 | ;; sequence. | |
7690 | ||
7691 | (define_split | |
7692 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7693 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7694 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7695 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7696 | [(set (match_dup 0) | |
7697 | (match_dup 2)) | |
7698 | (set (match_dup 0) | |
7699 | (ior:SI (match_dup 0) | |
7700 | (match_dup 3)))] | |
7701 | " | |
af8cb5c5 DE |
7702 | { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2); |
7703 | ||
7704 | if (tem == operands[0]) | |
7705 | DONE; | |
7706 | else | |
7707 | FAIL; | |
77fa0940 RK |
7708 | }") |
7709 | ||
acad7ed3 | 7710 | (define_insn "*movsi_internal2" |
9ebbca7d GK |
7711 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
7712 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 7713 | (const_int 0))) |
9ebbca7d | 7714 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
0ad91047 | 7715 | "! TARGET_POWERPC64" |
9ebbca7d GK |
7716 | "@ |
7717 | mr. %0,%1 | |
7718 | #" | |
7719 | [(set_attr "type" "compare") | |
7720 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 7721 | \f |
9ebbca7d GK |
7722 | (define_split |
7723 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
7724 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
7725 | (const_int 0))) | |
7726 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
7727 | "! TARGET_POWERPC64 && reload_completed" | |
7728 | [(set (match_dup 0) (match_dup 1)) | |
7729 | (set (match_dup 2) | |
7730 | (compare:CC (match_dup 0) | |
7731 | (const_int 0)))] | |
7732 | "") | |
7733 | ||
1fd4e8c1 RK |
7734 | (define_expand "movhi" |
7735 | [(set (match_operand:HI 0 "general_operand" "") | |
7736 | (match_operand:HI 1 "any_operand" ""))] | |
7737 | "" | |
fb4d4348 | 7738 | "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") |
1fd4e8c1 | 7739 | |
e34eaae5 | 7740 | (define_insn "*movhi_internal" |
fb81d7ce RK |
7741 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7742 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7743 | "gpc_reg_operand (operands[0], HImode) |
7744 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7745 | "@ |
deb9225a | 7746 | mr %0,%1 |
1fd4e8c1 RK |
7747 | lhz%U1%X1 %0,%1 |
7748 | sth%U0%X0 %1,%0 | |
19d5775a | 7749 | {lil|li} %0,%w1 |
1fd4e8c1 | 7750 | mf%1 %0 |
e76e75bb | 7751 | mt%0 %1 |
fb81d7ce | 7752 | mt%0 %1 |
e34eaae5 | 7753 | {cror 0,0,0|nop}" |
b7ff3d82 | 7754 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7755 | |
7756 | (define_expand "movqi" | |
7757 | [(set (match_operand:QI 0 "general_operand" "") | |
7758 | (match_operand:QI 1 "any_operand" ""))] | |
7759 | "" | |
fb4d4348 | 7760 | "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") |
1fd4e8c1 | 7761 | |
e34eaae5 | 7762 | (define_insn "*movqi_internal" |
fb81d7ce RK |
7763 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7764 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7765 | "gpc_reg_operand (operands[0], QImode) |
7766 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7767 | "@ |
deb9225a | 7768 | mr %0,%1 |
1fd4e8c1 RK |
7769 | lbz%U1%X1 %0,%1 |
7770 | stb%U0%X0 %1,%0 | |
19d5775a | 7771 | {lil|li} %0,%1 |
1fd4e8c1 | 7772 | mf%1 %0 |
e76e75bb | 7773 | mt%0 %1 |
fb81d7ce | 7774 | mt%0 %1 |
e34eaae5 | 7775 | {cror 0,0,0|nop}" |
b7ff3d82 | 7776 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7777 | \f |
7778 | ;; Here is how to move condition codes around. When we store CC data in | |
7779 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7780 | ;; This lets us not shift in the most common case of CR0. | |
7781 | (define_expand "movcc" | |
7782 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7783 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7784 | "" | |
7785 | "") | |
7786 | ||
a65c591c | 7787 | (define_insn "*movcc_internal1" |
b54cf83a DE |
7788 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m") |
7789 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))] | |
1fd4e8c1 RK |
7790 | "register_operand (operands[0], CCmode) |
7791 | || register_operand (operands[1], CCmode)" | |
7792 | "@ | |
7793 | mcrf %0,%1 | |
7794 | mtcrf 128,%1 | |
ca7f5001 | 7795 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
1fd4e8c1 | 7796 | mfcr %0 |
ca7f5001 | 7797 | mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 |
deb9225a | 7798 | mr %0,%1 |
b54cf83a | 7799 | mf%1 %0 |
b991a865 GK |
7800 | mt%0 %1 |
7801 | mt%0 %1 | |
ca7f5001 RK |
7802 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7803 | {st%U0%U1|stw%U0%U1} %1,%0" | |
b54cf83a | 7804 | [(set_attr "type" "cr_logical,mtcr,mtcr,mfcr,mfcr,*,*,*,mtjmpr,load,store") |
b991a865 | 7805 | (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7806 | \f |
e52e05ca MM |
7807 | ;; For floating-point, we normally deal with the floating-point registers |
7808 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7809 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7810 | ;; value is a simple constant or already in memory, we deal with this by | |
7811 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7812 | (define_expand "movsf" |
7813 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7814 | (match_operand:SF 1 "any_operand" ""))] | |
7815 | "" | |
fb4d4348 | 7816 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 7817 | |
1fd4e8c1 | 7818 | (define_split |
cd2b37d9 | 7819 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7820 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7821 | "reload_completed |
5ae4759c MM |
7822 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7823 | || (GET_CODE (operands[0]) == SUBREG | |
7824 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7825 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7826 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7827 | " |
7828 | { | |
7829 | long l; | |
7830 | REAL_VALUE_TYPE rv; | |
7831 | ||
7832 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7833 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7834 | |
f99f88e0 DE |
7835 | if (! TARGET_POWERPC64) |
7836 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7837 | else | |
7838 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7839 | |
2496c7bd | 7840 | operands[3] = gen_int_mode (l, SImode); |
a260abc9 DE |
7841 | }") |
7842 | ||
c4c40373 | 7843 | (define_insn "*movsf_hardfloat" |
b991a865 GK |
7844 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!r,!r") |
7845 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,G,Fn"))] | |
d14a6d05 | 7846 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7847 | || gpc_reg_operand (operands[1], SFmode)) |
7848 | && (TARGET_HARD_FLOAT && TARGET_FPRS)" | |
1fd4e8c1 | 7849 | "@ |
f99f88e0 DE |
7850 | mr %0,%1 |
7851 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7852 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7853 | fmr %0,%1 |
7854 | lfs%U1%X1 %0,%1 | |
c4c40373 | 7855 | stfs%U0%X0 %1,%0 |
b991a865 GK |
7856 | mt%0 %1 |
7857 | mt%0 %1 | |
7858 | mf%1 %0 | |
c4c40373 MM |
7859 | # |
7860 | #" | |
b991a865 GK |
7861 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*") |
7862 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7863 | |
c4c40373 | 7864 | (define_insn "*movsf_softfloat" |
dd0fbae2 MK |
7865 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h") |
7866 | (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))] | |
d14a6d05 | 7867 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7868 | || gpc_reg_operand (operands[1], SFmode)) |
7869 | && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" | |
d14a6d05 MM |
7870 | "@ |
7871 | mr %0,%1 | |
b991a865 GK |
7872 | mt%0 %1 |
7873 | mt%0 %1 | |
7874 | mf%1 %0 | |
d14a6d05 MM |
7875 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7876 | {st%U0%X0|stw%U0%X0} %1,%0 | |
7877 | {lil|li} %0,%1 | |
802a0058 | 7878 | {liu|lis} %0,%v1 |
aee86b38 | 7879 | {cal|la} %0,%a1 |
c4c40373 | 7880 | # |
dd0fbae2 MK |
7881 | # |
7882 | {cror 0,0,0|nop}" | |
7883 | [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*") | |
7884 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")]) | |
d14a6d05 | 7885 | |
1fd4e8c1 RK |
7886 | \f |
7887 | (define_expand "movdf" | |
7888 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
7889 | (match_operand:DF 1 "any_operand" ""))] | |
7890 | "" | |
fb4d4348 | 7891 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
7892 | |
7893 | (define_split | |
cd2b37d9 | 7894 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 7895 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 7896 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7897 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7898 | || (GET_CODE (operands[0]) == SUBREG | |
7899 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7900 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7901 | [(set (match_dup 2) (match_dup 4)) |
7902 | (set (match_dup 3) (match_dup 1))] | |
7903 | " | |
7904 | { | |
5ae4759c | 7905 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
7906 | HOST_WIDE_INT value = INTVAL (operands[1]); |
7907 | ||
5ae4759c MM |
7908 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7909 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
7910 | #if HOST_BITS_PER_WIDE_INT == 32 |
7911 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
7912 | #else | |
7913 | operands[4] = GEN_INT (value >> 32); | |
a65c591c | 7914 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
5f59ecb7 | 7915 | #endif |
c4c40373 MM |
7916 | }") |
7917 | ||
c4c40373 MM |
7918 | (define_split |
7919 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
7920 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 7921 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7922 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7923 | || (GET_CODE (operands[0]) == SUBREG | |
7924 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7925 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7926 | [(set (match_dup 2) (match_dup 4)) |
7927 | (set (match_dup 3) (match_dup 5))] | |
7928 | " | |
7929 | { | |
5ae4759c | 7930 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
7931 | long l[2]; |
7932 | REAL_VALUE_TYPE rv; | |
7933 | ||
7934 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7935 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7936 | ||
5ae4759c MM |
7937 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7938 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
2496c7bd LB |
7939 | operands[4] = gen_int_mode (l[endian], SImode); |
7940 | operands[5] = gen_int_mode (l[1 - endian], SImode); | |
c4c40373 MM |
7941 | }") |
7942 | ||
efc08378 DE |
7943 | (define_split |
7944 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 7945 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 7946 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7947 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7948 | || (GET_CODE (operands[0]) == SUBREG | |
7949 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7950 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 7951 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 7952 | " |
a260abc9 DE |
7953 | { |
7954 | int endian = (WORDS_BIG_ENDIAN == 0); | |
7955 | long l[2]; | |
7956 | REAL_VALUE_TYPE rv; | |
4977bab6 | 7957 | #if HOST_BITS_PER_WIDE_INT >= 64 |
5b029315 | 7958 | HOST_WIDE_INT val; |
4977bab6 | 7959 | #endif |
a260abc9 DE |
7960 | |
7961 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7962 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7963 | ||
7964 | operands[2] = gen_lowpart (DImode, operands[0]); | |
7965 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
5b029315 | 7966 | #if HOST_BITS_PER_WIDE_INT >= 64 |
a2419b96 DE |
7967 | val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 |
7968 | | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); | |
5b029315 | 7969 | |
f5264b52 | 7970 | operands[3] = gen_int_mode (val, DImode); |
5b029315 | 7971 | #else |
a260abc9 | 7972 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); |
5b029315 | 7973 | #endif |
a260abc9 | 7974 | }") |
efc08378 | 7975 | |
4eae5fe1 | 7976 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 7977 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
7978 | ;; a non-offsettable memref, but also it is less efficient than loading |
7979 | ;; the constant into an FP register, since it will probably be used there. | |
7980 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
7981 | ;; of handling these non-offsettable values. | |
c4c40373 | 7982 | (define_insn "*movdf_hardfloat32" |
914a7297 DE |
7983 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") |
7984 | (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] | |
a3170dc6 | 7985 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
7986 | && (gpc_reg_operand (operands[0], DFmode) |
7987 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
7988 | "* |
7989 | { | |
7990 | switch (which_alternative) | |
7991 | { | |
a260abc9 | 7992 | default: |
a6c2a102 | 7993 | abort (); |
e7113111 RK |
7994 | case 0: |
7995 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
7996 | the first register operand 0 is the same as the second register |
7997 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 7998 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 7999 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 8000 | else |
deb9225a | 8001 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 8002 | case 1: |
2b97222d DE |
8003 | if (offsettable_memref_p (operands[1]) |
8004 | || (GET_CODE (operands[1]) == MEM | |
69f51a21 DE |
8005 | && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM |
8006 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC | |
8007 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))) | |
000034eb DE |
8008 | { |
8009 | /* If the low-address word is used in the address, we must load | |
8010 | it last. Otherwise, load it first. Note that we cannot have | |
8011 | auto-increment in that case since the address register is | |
8012 | known to be dead. */ | |
8013 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8014 | operands[1], 0)) | |
8015 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
8016 | else | |
8017 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8018 | } | |
e7113111 | 8019 | else |
000034eb DE |
8020 | { |
8021 | rtx addreg; | |
8022 | ||
000034eb DE |
8023 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
8024 | if (refers_to_regno_p (REGNO (operands[0]), | |
8025 | REGNO (operands[0]) + 1, | |
8026 | operands[1], 0)) | |
8027 | { | |
8028 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 8029 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 8030 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 8031 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
8032 | } |
8033 | else | |
8034 | { | |
2b97222d | 8035 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 8036 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8037 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
8038 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8039 | return \"\"; | |
8040 | } | |
8041 | } | |
e7113111 | 8042 | case 2: |
2b97222d DE |
8043 | if (offsettable_memref_p (operands[0]) |
8044 | || (GET_CODE (operands[0]) == MEM | |
69f51a21 DE |
8045 | && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM |
8046 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC | |
8047 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))) | |
000034eb DE |
8048 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8049 | else | |
8050 | { | |
8051 | rtx addreg; | |
8052 | ||
000034eb | 8053 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 8054 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 8055 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8056 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
8057 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8058 | return \"\"; | |
8059 | } | |
e7113111 | 8060 | case 3: |
914a7297 | 8061 | return \"fmr %0,%1\"; |
e7113111 | 8062 | case 4: |
914a7297 | 8063 | return \"lfd%U1%X1 %0,%1\"; |
e7113111 | 8064 | case 5: |
914a7297 | 8065 | return \"stfd%U0%X0 %1,%0\"; |
e7113111 | 8066 | case 6: |
c4c40373 | 8067 | case 7: |
c4c40373 | 8068 | case 8: |
914a7297 | 8069 | return \"#\"; |
e7113111 RK |
8070 | } |
8071 | }" | |
914a7297 DE |
8072 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*") |
8073 | (set_attr "length" "8,16,16,4,4,4,8,12,16")]) | |
51b8fc2c | 8074 | |
c4c40373 | 8075 | (define_insn "*movdf_softfloat32" |
1427100a DE |
8076 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
8077 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
a3170dc6 | 8078 | "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
8079 | && (gpc_reg_operand (operands[0], DFmode) |
8080 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8081 | "* |
8082 | { | |
8083 | switch (which_alternative) | |
8084 | { | |
a260abc9 | 8085 | default: |
a6c2a102 | 8086 | abort (); |
dc4f83ca MM |
8087 | case 0: |
8088 | /* We normally copy the low-numbered register first. However, if | |
8089 | the first register operand 0 is the same as the second register of | |
8090 | operand 1, we must copy in the opposite order. */ | |
8091 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8092 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8093 | else | |
8094 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8095 | case 1: | |
3cb999d8 DE |
8096 | /* If the low-address word is used in the address, we must load |
8097 | it last. Otherwise, load it first. Note that we cannot have | |
8098 | auto-increment in that case since the address register is | |
8099 | known to be dead. */ | |
dc4f83ca | 8100 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 8101 | operands[1], 0)) |
dc4f83ca MM |
8102 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
8103 | else | |
8104 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8105 | case 2: | |
8106 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
8107 | case 3: | |
c4c40373 MM |
8108 | case 4: |
8109 | case 5: | |
dc4f83ca MM |
8110 | return \"#\"; |
8111 | } | |
8112 | }" | |
c4c40373 MM |
8113 | [(set_attr "type" "*,load,store,*,*,*") |
8114 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 8115 | |
c4c40373 | 8116 | (define_insn "*movdf_hardfloat64" |
914a7297 DE |
8117 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!cl,!r,!r,!r,!r") |
8118 | (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,r,h,G,H,F"))] | |
a3170dc6 | 8119 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
8120 | && (gpc_reg_operand (operands[0], DFmode) |
8121 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 8122 | "@ |
3d5570cb RK |
8123 | mr %0,%1 |
8124 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8125 | std%U0%X0 %1,%0 |
3d5570cb | 8126 | fmr %0,%1 |
f63184ac | 8127 | lfd%U1%X1 %0,%1 |
914a7297 DE |
8128 | stfd%U0%X0 %1,%0 |
8129 | mt%0 %1 | |
8130 | mf%1 %0 | |
8131 | # | |
8132 | # | |
8133 | #" | |
8134 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*") | |
8135 | (set_attr "length" "4,4,4,4,4,4,4,4,8,12,16")]) | |
dc4f83ca | 8136 | |
c4c40373 | 8137 | (define_insn "*movdf_softfloat64" |
914a7297 DE |
8138 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r") |
8139 | (match_operand:DF 1 "input_operand" "r,r,h,m,r,G,H,F"))] | |
a3170dc6 | 8140 | "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
8141 | && (gpc_reg_operand (operands[0], DFmode) |
8142 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8143 | "@ |
8144 | mr %0,%1 | |
914a7297 DE |
8145 | mt%0 %1 |
8146 | mf%1 %0 | |
dc4f83ca | 8147 | ld%U1%X1 %0,%1 |
96bb8ed3 | 8148 | std%U0%X0 %1,%0 |
c4c40373 MM |
8149 | # |
8150 | # | |
dc4f83ca | 8151 | #" |
914a7297 DE |
8152 | [(set_attr "type" "*,*,*,load,store,*,*,*") |
8153 | (set_attr "length" "4,4,4,4,4,8,12,16")]) | |
1fd4e8c1 | 8154 | \f |
06f4e019 DE |
8155 | (define_expand "movtf" |
8156 | [(set (match_operand:TF 0 "general_operand" "") | |
8157 | (match_operand:TF 1 "any_operand" ""))] | |
a3170dc6 AH |
8158 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8159 | && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8160 | "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") |
8161 | ||
8162 | (define_insn "*movtf_internal" | |
8163 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,m,!r,!r,!r") | |
8164 | (match_operand:TF 1 "input_operand" "f,m,f,G,H,F"))] | |
a3170dc6 AH |
8165 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8166 | && TARGET_LONG_DOUBLE_128 | |
06f4e019 DE |
8167 | && (gpc_reg_operand (operands[0], TFmode) |
8168 | || gpc_reg_operand (operands[1], TFmode))" | |
8169 | "* | |
8170 | { | |
8171 | switch (which_alternative) | |
8172 | { | |
8173 | default: | |
8174 | abort (); | |
8175 | case 0: | |
8176 | /* We normally copy the low-numbered register first. However, if | |
8177 | the first register operand 0 is the same as the second register of | |
8178 | operand 1, we must copy in the opposite order. */ | |
8179 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8180 | return \"fmr %L0,%L1\;fmr %0,%1\"; | |
8181 | else | |
8182 | return \"fmr %0,%1\;fmr %L0,%L1\"; | |
8183 | case 1: | |
f5264b52 | 8184 | return \"lfd %0,%1\;lfd %L0,%Y1\"; |
06f4e019 | 8185 | case 2: |
f5264b52 | 8186 | return \"stfd %1,%0\;stfd %L1,%Y0\"; |
06f4e019 DE |
8187 | case 3: |
8188 | case 4: | |
8189 | case 5: | |
8190 | return \"#\"; | |
8191 | } | |
8192 | }" | |
8193 | [(set_attr "type" "fp,fpload,fpstore,*,*,*") | |
8194 | (set_attr "length" "8,8,8,12,16,20")]) | |
8195 | ||
8196 | (define_split | |
8197 | [(set (match_operand:TF 0 "gpc_reg_operand" "") | |
f5264b52 | 8198 | (match_operand:TF 1 "easy_fp_constant" ""))] |
fcce224d DE |
8199 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8200 | && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_POWERPC64 | |
8201 | && TARGET_LONG_DOUBLE_128 && reload_completed | |
8202 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) | |
8203 | || (GET_CODE (operands[0]) == SUBREG | |
8204 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8205 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
8206 | [(set (match_dup 2) (match_dup 6)) | |
8207 | (set (match_dup 3) (match_dup 7)) | |
8208 | (set (match_dup 4) (match_dup 8)) | |
8209 | (set (match_dup 5) (match_dup 9))] | |
8210 | " | |
8211 | { | |
8212 | long l[4]; | |
8213 | REAL_VALUE_TYPE rv; | |
8214 | ||
8215 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8216 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l); | |
8217 | ||
8218 | operands[2] = operand_subword (operands[0], 0, 0, TFmode); | |
8219 | operands[3] = operand_subword (operands[0], 1, 0, TFmode); | |
8220 | operands[4] = operand_subword (operands[0], 2, 0, TFmode); | |
8221 | operands[5] = operand_subword (operands[0], 3, 0, TFmode); | |
8222 | operands[6] = gen_int_mode (l[0], SImode); | |
8223 | operands[7] = gen_int_mode (l[1], SImode); | |
8224 | operands[8] = gen_int_mode (l[2], SImode); | |
8225 | operands[9] = gen_int_mode (l[3], SImode); | |
8226 | }") | |
8227 | ||
8228 | (define_split | |
8229 | [(set (match_operand:TF 0 "gpc_reg_operand" "") | |
8230 | (match_operand:TF 1 "easy_fp_constant" ""))] | |
8231 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8232 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 | |
8233 | && TARGET_LONG_DOUBLE_128 && reload_completed | |
8234 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) | |
8235 | || (GET_CODE (operands[0]) == SUBREG | |
8236 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8237 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
8238 | [(set (match_dup 2) (match_dup 4)) | |
8239 | (set (match_dup 3) (match_dup 5))] | |
06f4e019 DE |
8240 | " |
8241 | { | |
fcce224d DE |
8242 | long l[4]; |
8243 | REAL_VALUE_TYPE rv; | |
d24652ee | 8244 | #if HOST_BITS_PER_WIDE_INT >= 64 |
f5264b52 | 8245 | HOST_WIDE_INT val; |
d24652ee | 8246 | #endif |
fcce224d DE |
8247 | |
8248 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8249 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l); | |
8250 | ||
f5264b52 DE |
8251 | operands[2] = gen_lowpart (DImode, operands[0]); |
8252 | operands[3] = gen_highpart (DImode, operands[0]); | |
8253 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
a2419b96 DE |
8254 | val = ((HOST_WIDE_INT)(unsigned long)l[0] << 32 |
8255 | | ((HOST_WIDE_INT)(unsigned long)l[1])); | |
f5264b52 DE |
8256 | operands[4] = gen_int_mode (val, DImode); |
8257 | ||
a2419b96 DE |
8258 | val = ((HOST_WIDE_INT)(unsigned long)l[2] << 32 |
8259 | | ((HOST_WIDE_INT)(unsigned long)l[3])); | |
f5264b52 DE |
8260 | operands[5] = gen_int_mode (val, DImode); |
8261 | #else | |
8262 | operands[4] = immed_double_const (l[1], l[0], DImode); | |
8263 | operands[5] = immed_double_const (l[3], l[2], DImode); | |
8264 | #endif | |
06f4e019 DE |
8265 | }") |
8266 | ||
a2419b96 | 8267 | (define_insn "extenddftf2" |
06f4e019 DE |
8268 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
8269 | (float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
8270 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8271 | && TARGET_LONG_DOUBLE_128" | |
a2419b96 | 8272 | "* |
06f4e019 | 8273 | { |
a2419b96 DE |
8274 | if (REGNO (operands[0]) == REGNO (operands[1])) |
8275 | return \"fsub %L0,%L0,%L0\"; | |
8276 | else | |
8277 | return \"fmr %0,%1\;fsub %L0,%L0,%L0\"; | |
8278 | }" | |
8279 | [(set_attr "type" "fp")]) | |
06f4e019 | 8280 | |
a2419b96 | 8281 | (define_insn "extendsftf2" |
06f4e019 DE |
8282 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
8283 | (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
8284 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8285 | && TARGET_LONG_DOUBLE_128" | |
a2419b96 | 8286 | "* |
06f4e019 | 8287 | { |
a2419b96 DE |
8288 | if (REGNO (operands[0]) == REGNO (operands[1])) |
8289 | return \"fsub %L0,%L0,%L0\"; | |
8290 | else | |
8291 | return \"fmr %0,%1\;fsub %L0,%L0,%L0\"; | |
8292 | }" | |
8293 | [(set_attr "type" "fp")]) | |
06f4e019 DE |
8294 | |
8295 | (define_insn "trunctfdf2" | |
8296 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8297 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
8298 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8299 | && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8300 | "fadd %0,%1,%L1" |
8301 | [(set_attr "type" "fp") | |
8302 | (set_attr "length" "8")]) | |
8303 | ||
8304 | (define_insn_and_split "trunctfsf2" | |
8305 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
ea112fc4 DE |
8306 | (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8307 | (clobber (match_scratch:DF 2 "=f"))] | |
a3170dc6 AH |
8308 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT |
8309 | && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8310 | "#" |
ea112fc4 | 8311 | "&& reload_completed" |
06f4e019 DE |
8312 | [(set (match_dup 2) |
8313 | (float_truncate:DF (match_dup 1))) | |
8314 | (set (match_dup 0) | |
8315 | (float_truncate:SF (match_dup 2)))] | |
ea112fc4 | 8316 | "") |
06f4e019 | 8317 | |
ea112fc4 DE |
8318 | (define_insn_and_split "floatditf2" |
8319 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 8320 | (float:TF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 DE |
8321 | (clobber (match_scratch:DF 2 "=f"))] |
8322 | "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 | |
a3170dc6 | 8323 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" |
ea112fc4 DE |
8324 | "#" |
8325 | "&& reload_completed" | |
06f4e019 | 8326 | [(set (match_dup 2) |
a2419b96 DE |
8327 | (float:DF (match_dup 1))) |
8328 | (set (match_dup 0) | |
06f4e019 | 8329 | (float_extend:TF (match_dup 2)))] |
ea112fc4 | 8330 | "") |
06f4e019 | 8331 | |
ea112fc4 DE |
8332 | (define_insn_and_split "floatsitf2" |
8333 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 8334 | (float:TF (match_operand:SI 1 "gpc_reg_operand" "r"))) |
ea112fc4 | 8335 | (clobber (match_scratch:DF 2 "=f"))] |
a3170dc6 AH |
8336 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8337 | && TARGET_LONG_DOUBLE_128" | |
ea112fc4 DE |
8338 | "#" |
8339 | "&& reload_completed" | |
06f4e019 | 8340 | [(set (match_dup 2) |
a2419b96 DE |
8341 | (float:DF (match_dup 1))) |
8342 | (set (match_dup 0) | |
06f4e019 | 8343 | (float_extend:TF (match_dup 2)))] |
ea112fc4 | 8344 | "") |
06f4e019 | 8345 | |
ea112fc4 | 8346 | (define_insn_and_split "fix_trunctfdi2" |
61c07d3c | 8347 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
a2419b96 DE |
8348 | (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8349 | (clobber (match_scratch:DF 2 "=f"))] | |
ea112fc4 | 8350 | "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 |
a3170dc6 | 8351 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" |
ea112fc4 DE |
8352 | "#" |
8353 | "&& reload_completed" | |
06f4e019 | 8354 | [(set (match_dup 2) |
a2419b96 DE |
8355 | (float_truncate:DF (match_dup 1))) |
8356 | (set (match_dup 0) | |
8357 | (fix:DI (match_dup 2)))] | |
ea112fc4 | 8358 | "") |
06f4e019 | 8359 | |
ea112fc4 | 8360 | (define_insn_and_split "fix_trunctfsi2" |
61c07d3c | 8361 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
a2419b96 DE |
8362 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8363 | (clobber (match_scratch:DF 2 "=f"))] | |
a3170dc6 AH |
8364 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8365 | && TARGET_LONG_DOUBLE_128" | |
ea112fc4 DE |
8366 | "#" |
8367 | "&& reload_completed" | |
06f4e019 | 8368 | [(set (match_dup 2) |
a2419b96 DE |
8369 | (float_truncate:DF (match_dup 1))) |
8370 | (set (match_dup 0) | |
06f4e019 | 8371 | (fix:SI (match_dup 2)))] |
ea112fc4 | 8372 | "") |
06f4e019 DE |
8373 | |
8374 | (define_insn "negtf2" | |
8375 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8376 | (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
8377 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8378 | && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8379 | "* |
8380 | { | |
8381 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8382 | return \"fneg %L0,%L1\;fneg %0,%1\"; | |
8383 | else | |
8384 | return \"fneg %0,%1\;fneg %L0,%L1\"; | |
8385 | }" | |
8386 | [(set_attr "type" "fp") | |
8387 | (set_attr "length" "8")]) | |
8388 | ||
8389 | (define_insn "abstf2" | |
8390 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8391 | (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
8392 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8393 | && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8394 | "* |
8395 | { | |
8396 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8397 | return \"fabs %L0,%L1\;fabs %0,%1\"; | |
8398 | else | |
8399 | return \"fabs %0,%1\;fabs %L0,%L1\"; | |
8400 | }" | |
8401 | [(set_attr "type" "fp") | |
8402 | (set_attr "length" "8")]) | |
8403 | ||
8404 | (define_insn "" | |
8405 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8406 | (neg:TF (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 AH |
8407 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8408 | && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8409 | "* |
8410 | { | |
8411 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8412 | return \"fnabs %L0,%L1\;fnabs %0,%1\"; | |
8413 | else | |
8414 | return \"fnabs %0,%1\;fnabs %L0,%L1\"; | |
8415 | }" | |
8416 | [(set_attr "type" "fp") | |
8417 | (set_attr "length" "8")]) | |
8418 | \f | |
1fd4e8c1 RK |
8419 | ;; Next come the multi-word integer load and store and the load and store |
8420 | ;; multiple insns. | |
8421 | (define_expand "movdi" | |
8422 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 8423 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 | 8424 | "" |
fb4d4348 | 8425 | "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") |
1fd4e8c1 | 8426 | |
acad7ed3 | 8427 | (define_insn "*movdi_internal32" |
4e74d8ec MM |
8428 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") |
8429 | (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] | |
a260abc9 | 8430 | "! TARGET_POWERPC64 |
4e74d8ec MM |
8431 | && (gpc_reg_operand (operands[0], DImode) |
8432 | || gpc_reg_operand (operands[1], DImode))" | |
1fd4e8c1 RK |
8433 | "* |
8434 | { | |
8435 | switch (which_alternative) | |
8436 | { | |
a260abc9 | 8437 | default: |
a6c2a102 | 8438 | abort (); |
1fd4e8c1 RK |
8439 | case 0: |
8440 | /* We normally copy the low-numbered register first. However, if | |
8441 | the first register operand 0 is the same as the second register of | |
8442 | operand 1, we must copy in the opposite order. */ | |
8443 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 8444 | return \"mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 8445 | else |
deb9225a | 8446 | return \"mr %0,%1\;mr %L0,%L1\"; |
1fd4e8c1 RK |
8447 | case 1: |
8448 | /* If the low-address word is used in the address, we must load it | |
8449 | last. Otherwise, load it first. Note that we cannot have | |
8450 | auto-increment in that case since the address register is known to be | |
8451 | dead. */ | |
8452 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 8453 | operands[1], 0)) |
ca7f5001 | 8454 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
1fd4e8c1 | 8455 | else |
ca7f5001 | 8456 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 | 8457 | case 2: |
ca7f5001 | 8458 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8ffd9c51 RK |
8459 | case 3: |
8460 | return \"fmr %0,%1\"; | |
8461 | case 4: | |
8462 | return \"lfd%U1%X1 %0,%1\"; | |
8463 | case 5: | |
8464 | return \"stfd%U0%X0 %1,%0\"; | |
4e74d8ec MM |
8465 | case 6: |
8466 | case 7: | |
8467 | case 8: | |
8468 | case 9: | |
8469 | case 10: | |
8470 | return \"#\"; | |
1fd4e8c1 RK |
8471 | } |
8472 | }" | |
4e74d8ec | 8473 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*") |
914a7297 | 8474 | (set_attr "length" "8,8,8,4,4,4,8,12,8,12,16")]) |
4e74d8ec MM |
8475 | |
8476 | (define_split | |
8477 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8478 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 8479 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8480 | [(set (match_dup 2) (match_dup 4)) |
8481 | (set (match_dup 3) (match_dup 1))] | |
8482 | " | |
8483 | { | |
5f59ecb7 | 8484 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
8485 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8486 | DImode); | |
8487 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8488 | DImode); | |
75d39459 | 8489 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 8490 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 8491 | #else |
5f59ecb7 | 8492 | operands[4] = GEN_INT (value >> 32); |
a65c591c | 8493 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
75d39459 | 8494 | #endif |
4e74d8ec MM |
8495 | }") |
8496 | ||
4e74d8ec MM |
8497 | (define_split |
8498 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8499 | (match_operand:DI 1 "const_double_operand" ""))] | |
75d39459 | 8500 | "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8501 | [(set (match_dup 2) (match_dup 4)) |
8502 | (set (match_dup 3) (match_dup 5))] | |
8503 | " | |
8504 | { | |
bdaa0181 GK |
8505 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8506 | DImode); | |
8507 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8508 | DImode); | |
f6968f59 MM |
8509 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
8510 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
4e74d8ec MM |
8511 | }") |
8512 | ||
6fc19dc9 AM |
8513 | (define_split |
8514 | [(set (match_operand:TI 0 "gpc_reg_operand" "") | |
8515 | (match_operand:TI 1 "const_double_operand" ""))] | |
8516 | "TARGET_POWERPC64" | |
8517 | [(set (match_dup 2) (match_dup 4)) | |
8518 | (set (match_dup 3) (match_dup 5))] | |
8519 | " | |
8520 | { | |
8521 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, | |
8522 | TImode); | |
8523 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8524 | TImode); | |
8525 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
8526 | { | |
8527 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
8528 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
8529 | } | |
8530 | else if (GET_CODE (operands[1]) == CONST_INT) | |
8531 | { | |
8532 | operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0)); | |
8533 | operands[5] = operands[1]; | |
8534 | } | |
8535 | else | |
8536 | FAIL; | |
8537 | }") | |
8538 | ||
acad7ed3 | 8539 | (define_insn "*movdi_internal64" |
5d7e6254 | 8540 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h") |
9615f239 | 8541 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 8542 | "TARGET_POWERPC64 |
4e74d8ec MM |
8543 | && (gpc_reg_operand (operands[0], DImode) |
8544 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 8545 | "@ |
3d5570cb RK |
8546 | mr %0,%1 |
8547 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8548 | std%U0%X0 %1,%0 |
3d5570cb | 8549 | li %0,%1 |
802a0058 | 8550 | lis %0,%v1 |
e6ca2c17 | 8551 | # |
aee86b38 | 8552 | {cal|la} %0,%a1 |
3d5570cb RK |
8553 | fmr %0,%1 |
8554 | lfd%U1%X1 %0,%1 | |
8555 | stfd%U0%X0 %1,%0 | |
8556 | mf%1 %0 | |
08075ead | 8557 | mt%0 %1 |
e34eaae5 | 8558 | {cror 0,0,0|nop}" |
b7ff3d82 | 8559 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*") |
e6ca2c17 DE |
8560 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
8561 | ||
5f59ecb7 | 8562 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
8563 | (define_insn "" |
8564 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8565 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
8566 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8567 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
8568 | && num_insns_constant (operands[1], DImode) == 1" |
8569 | "* | |
8570 | { | |
8571 | return ((unsigned HOST_WIDE_INT) | |
8572 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
8573 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
8574 | }") | |
8575 | ||
a260abc9 DE |
8576 | ;; Generate all one-bits and clear left or right. |
8577 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8578 | (define_split | |
8579 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8580 | (match_operand:DI 1 "mask64_operand" ""))] | |
8581 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8582 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8583 | (set (match_dup 0) |
a260abc9 DE |
8584 | (and:DI (rotate:DI (match_dup 0) |
8585 | (const_int 0)) | |
8586 | (match_dup 1)))] | |
8587 | "") | |
8588 | ||
8589 | ;; Split a load of a large constant into the appropriate five-instruction | |
8590 | ;; sequence. Handle anything in a constant number of insns. | |
8591 | ;; When non-easy constants can go in the TOC, this should use | |
8592 | ;; easy_fp_constant predicate. | |
8593 | (define_split | |
8594 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8595 | (match_operand:DI 1 "const_int_operand" ""))] |
8596 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8597 | [(set (match_dup 0) (match_dup 2)) | |
8598 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
e6ca2c17 | 8599 | " |
2bfcf297 DB |
8600 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8601 | ||
8602 | if (tem == operands[0]) | |
8603 | DONE; | |
e8d791dd | 8604 | else |
2bfcf297 | 8605 | FAIL; |
5f59ecb7 | 8606 | }") |
e6ca2c17 | 8607 | |
5f59ecb7 DE |
8608 | (define_split |
8609 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8610 | (match_operand:DI 1 "const_double_operand" ""))] |
8611 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8612 | [(set (match_dup 0) (match_dup 2)) | |
8613 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
5f59ecb7 | 8614 | " |
2bfcf297 DB |
8615 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8616 | ||
8617 | if (tem == operands[0]) | |
8618 | DONE; | |
8619 | else | |
8620 | FAIL; | |
e6ca2c17 | 8621 | }") |
08075ead | 8622 | |
2bfcf297 | 8623 | ;; Split a load of a large constant into the appropriate five-instruction |
acad7ed3 | 8624 | (define_insn "*movdi_internal2" |
9ebbca7d GK |
8625 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
8626 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
08075ead | 8627 | (const_int 0))) |
9ebbca7d | 8628 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
08075ead | 8629 | "TARGET_POWERPC64" |
9ebbca7d GK |
8630 | "@ |
8631 | mr. %0,%1 | |
8632 | #" | |
8633 | [(set_attr "type" "compare") | |
8634 | (set_attr "length" "4,8")]) | |
acad7ed3 | 8635 | |
9ebbca7d GK |
8636 | (define_split |
8637 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8638 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
8639 | (const_int 0))) | |
8640 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8641 | "TARGET_POWERPC64 && reload_completed" | |
8642 | [(set (match_dup 0) (match_dup 1)) | |
8643 | (set (match_dup 2) | |
8644 | (compare:CC (match_dup 0) | |
8645 | (const_int 0)))] | |
8646 | "") | |
acad7ed3 | 8647 | \f |
1fd4e8c1 RK |
8648 | ;; TImode is similar, except that we usually want to compute the address into |
8649 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8650 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8651 | (define_expand "movti" |
8652 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
8653 | (match_operand:TI 1 "general_operand" "")) | |
8654 | (clobber (scratch:SI))])] | |
7e69e155 | 8655 | "TARGET_STRING || TARGET_POWERPC64" |
fb4d4348 | 8656 | "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") |
1fd4e8c1 RK |
8657 | |
8658 | ;; We say that MQ is clobbered in the last alternative because the first | |
8659 | ;; alternative would never get used otherwise since it would need a reload | |
8660 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8661 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8662 | ;; giving the SCRATCH mq. | |
a260abc9 | 8663 | (define_insn "*movti_power" |
e1469d0d | 8664 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
8665 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
8666 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
7e69e155 | 8667 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8668 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8669 | "* |
8670 | { | |
8671 | switch (which_alternative) | |
8672 | { | |
dc4f83ca MM |
8673 | default: |
8674 | abort (); | |
8675 | ||
1fd4e8c1 | 8676 | case 0: |
ca7f5001 | 8677 | return \"{stsi|stswi} %1,%P0,16\"; |
1fd4e8c1 | 8678 | case 1: |
ca7f5001 | 8679 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
1fd4e8c1 RK |
8680 | case 2: |
8681 | /* Normally copy registers with lowest numbered register copied first. | |
8682 | But copy in the other order if the first register of the output | |
8683 | is the second, third, or fourth register in the input. */ | |
8684 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8685 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
deb9225a | 8686 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 8687 | else |
deb9225a | 8688 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; |
1fd4e8c1 RK |
8689 | case 3: |
8690 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8691 | fall through to generating four loads. */ | |
8692 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8693 | return \"{lsi|lswi} %0,%P1,16\"; |
82e41834 | 8694 | /* ... fall through ... */ |
1fd4e8c1 RK |
8695 | case 4: |
8696 | /* If the address register is the same as the register for the lowest- | |
8697 | addressed word, load it last. Similarly for the next two words. | |
8698 | Otherwise load lowest address to highest. */ | |
8699 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8700 | operands[1], 0)) | |
ca7f5001 | 8701 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; |
1fd4e8c1 RK |
8702 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, |
8703 | REGNO (operands[0]) + 2, operands[1], 0)) | |
ca7f5001 | 8704 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 RK |
8705 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, |
8706 | REGNO (operands[0]) + 3, operands[1], 0)) | |
ca7f5001 | 8707 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; |
1fd4e8c1 | 8708 | else |
ca7f5001 | 8709 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; |
1fd4e8c1 RK |
8710 | } |
8711 | }" | |
b7ff3d82 | 8712 | [(set_attr "type" "store,store,*,load,load") |
914a7297 | 8713 | (set_attr "length" "4,16,16,4,16")]) |
51b8fc2c | 8714 | |
a260abc9 | 8715 | (define_insn "*movti_string" |
cd1d3445 | 8716 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
27dc0551 | 8717 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))] |
0ad91047 | 8718 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8719 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8720 | "* | |
8721 | { | |
8722 | switch (which_alternative) | |
8723 | { | |
8724 | default: | |
8725 | abort (); | |
8726 | ||
8727 | case 0: | |
cd1d3445 | 8728 | return \"{stsi|stswi} %1,%P0,16\"; |
dc4f83ca | 8729 | case 1: |
cd1d3445 DE |
8730 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
8731 | case 2: | |
dc4f83ca MM |
8732 | /* Normally copy registers with lowest numbered register copied first. |
8733 | But copy in the other order if the first register of the output | |
8734 | is the second, third, or fourth register in the input. */ | |
8735 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8736 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
8737 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; | |
8738 | else | |
8739 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; | |
cd1d3445 DE |
8740 | case 3: |
8741 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8742 | fall through to generating four loads. */ | |
8743 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
8744 | return \"{lsi|lswi} %0,%P1,16\"; | |
8745 | /* ... fall through ... */ | |
8746 | case 4: | |
dc4f83ca MM |
8747 | /* If the address register is the same as the register for the lowest- |
8748 | addressed word, load it last. Similarly for the next two words. | |
8749 | Otherwise load lowest address to highest. */ | |
8750 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8751 | operands[1], 0)) | |
8752 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; | |
8753 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, | |
8754 | REGNO (operands[0]) + 2, operands[1], 0)) | |
8755 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; | |
8756 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, | |
8757 | REGNO (operands[0]) + 3, operands[1], 0)) | |
8758 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; | |
8759 | else | |
8760 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; | |
8761 | } | |
8762 | }" | |
cd1d3445 DE |
8763 | [(set_attr "type" "store,store,*,load,load") |
8764 | (set_attr "length" "4,16,16,4,16")]) | |
dc4f83ca | 8765 | |
a260abc9 | 8766 | (define_insn "*movti_ppc64" |
51b8fc2c RK |
8767 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") |
8768 | (match_operand:TI 1 "input_operand" "r,m,r"))] | |
8769 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) | |
8770 | || gpc_reg_operand (operands[1], TImode))" | |
8771 | "* | |
8772 | { | |
8773 | switch (which_alternative) | |
8774 | { | |
a260abc9 | 8775 | default: |
a6c2a102 | 8776 | abort (); |
51b8fc2c RK |
8777 | case 0: |
8778 | /* We normally copy the low-numbered register first. However, if | |
8779 | the first register operand 0 is the same as the second register of | |
8780 | operand 1, we must copy in the opposite order. */ | |
8781 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8782 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8783 | else | |
8784 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8785 | case 1: | |
8786 | /* If the low-address word is used in the address, we must load it | |
8787 | last. Otherwise, load it first. Note that we cannot have | |
8788 | auto-increment in that case since the address register is known to be | |
8789 | dead. */ | |
8790 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 8791 | operands[1], 0)) |
51b8fc2c RK |
8792 | return \"ld %L0,%L1\;ld %0,%1\"; |
8793 | else | |
8794 | return \"ld%U1 %0,%1\;ld %L0,%L1\"; | |
8795 | case 2: | |
8796 | return \"std%U0 %1,%0\;std %L1,%L0\"; | |
8797 | } | |
8798 | }" | |
b7ff3d82 | 8799 | [(set_attr "type" "*,load,store") |
51b8fc2c | 8800 | (set_attr "length" "8,8,8")]) |
1fd4e8c1 RK |
8801 | \f |
8802 | (define_expand "load_multiple" | |
2f622005 RK |
8803 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8804 | (match_operand:SI 1 "" "")) | |
8805 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8806 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8807 | " |
8808 | { | |
8809 | int regno; | |
8810 | int count; | |
792760b9 | 8811 | rtx op1; |
1fd4e8c1 RK |
8812 | int i; |
8813 | ||
8814 | /* Support only loading a constant number of fixed-point registers from | |
8815 | memory and only bother with this if more than two; the machine | |
8816 | doesn't support more than eight. */ | |
8817 | if (GET_CODE (operands[2]) != CONST_INT | |
8818 | || INTVAL (operands[2]) <= 2 | |
8819 | || INTVAL (operands[2]) > 8 | |
8820 | || GET_CODE (operands[1]) != MEM | |
8821 | || GET_CODE (operands[0]) != REG | |
8822 | || REGNO (operands[0]) >= 32) | |
8823 | FAIL; | |
8824 | ||
8825 | count = INTVAL (operands[2]); | |
8826 | regno = REGNO (operands[0]); | |
8827 | ||
39403d82 | 8828 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
8829 | op1 = replace_equiv_address (operands[1], |
8830 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
8831 | |
8832 | for (i = 0; i < count; i++) | |
8833 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8834 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
7ef788f0 | 8835 | adjust_address_nv (op1, SImode, i * 4)); |
1fd4e8c1 RK |
8836 | }") |
8837 | ||
9caa3eb2 | 8838 | (define_insn "*ldmsi8" |
1fd4e8c1 | 8839 | [(match_parallel 0 "load_multiple_operation" |
9caa3eb2 DE |
8840 | [(set (match_operand:SI 2 "gpc_reg_operand" "") |
8841 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8842 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8843 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8844 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8845 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8846 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8847 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8848 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8849 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8850 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8851 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8852 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8853 | (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
8854 | (set (match_operand:SI 9 "gpc_reg_operand" "") | |
8855 | (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] | |
8856 | "TARGET_STRING && XVECLEN (operands[0], 0) == 8" | |
1fd4e8c1 | 8857 | "* |
9caa3eb2 DE |
8858 | { return rs6000_output_load_multiple (operands); }" |
8859 | [(set_attr "type" "load") | |
8860 | (set_attr "length" "32")]) | |
1fd4e8c1 | 8861 | |
9caa3eb2 DE |
8862 | (define_insn "*ldmsi7" |
8863 | [(match_parallel 0 "load_multiple_operation" | |
8864 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8865 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8866 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8867 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8868 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8869 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8870 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8871 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8872 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8873 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8874 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8875 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8876 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8877 | (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] | |
8878 | "TARGET_STRING && XVECLEN (operands[0], 0) == 7" | |
8879 | "* | |
8880 | { return rs6000_output_load_multiple (operands); }" | |
8881 | [(set_attr "type" "load") | |
8882 | (set_attr "length" "32")]) | |
8883 | ||
8884 | (define_insn "*ldmsi6" | |
8885 | [(match_parallel 0 "load_multiple_operation" | |
8886 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8887 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8888 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8889 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8890 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8891 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8892 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8893 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8894 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8895 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8896 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8897 | (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] | |
8898 | "TARGET_STRING && XVECLEN (operands[0], 0) == 6" | |
8899 | "* | |
8900 | { return rs6000_output_load_multiple (operands); }" | |
8901 | [(set_attr "type" "load") | |
8902 | (set_attr "length" "32")]) | |
8903 | ||
8904 | (define_insn "*ldmsi5" | |
8905 | [(match_parallel 0 "load_multiple_operation" | |
8906 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8907 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8908 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8909 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8910 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8911 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8912 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8913 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8914 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8915 | (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] | |
8916 | "TARGET_STRING && XVECLEN (operands[0], 0) == 5" | |
8917 | "* | |
8918 | { return rs6000_output_load_multiple (operands); }" | |
8919 | [(set_attr "type" "load") | |
8920 | (set_attr "length" "32")]) | |
8921 | ||
8922 | (define_insn "*ldmsi4" | |
8923 | [(match_parallel 0 "load_multiple_operation" | |
8924 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8925 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8926 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8927 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8928 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8929 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8930 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8931 | (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] | |
8932 | "TARGET_STRING && XVECLEN (operands[0], 0) == 4" | |
8933 | "* | |
8934 | { return rs6000_output_load_multiple (operands); }" | |
8935 | [(set_attr "type" "load") | |
8936 | (set_attr "length" "32")]) | |
8937 | ||
8938 | (define_insn "*ldmsi3" | |
8939 | [(match_parallel 0 "load_multiple_operation" | |
8940 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8941 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8942 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8943 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8944 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8945 | (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] | |
8946 | "TARGET_STRING && XVECLEN (operands[0], 0) == 3" | |
8947 | "* | |
8948 | { return rs6000_output_load_multiple (operands); }" | |
b19003d8 | 8949 | [(set_attr "type" "load") |
e82ee4cc | 8950 | (set_attr "length" "32")]) |
b19003d8 | 8951 | |
1fd4e8c1 | 8952 | (define_expand "store_multiple" |
2f622005 RK |
8953 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8954 | (match_operand:SI 1 "" "")) | |
8955 | (clobber (scratch:SI)) | |
8956 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8957 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8958 | " |
8959 | { | |
8960 | int regno; | |
8961 | int count; | |
8962 | rtx to; | |
792760b9 | 8963 | rtx op0; |
1fd4e8c1 RK |
8964 | int i; |
8965 | ||
8966 | /* Support only storing a constant number of fixed-point registers to | |
8967 | memory and only bother with this if more than two; the machine | |
8968 | doesn't support more than eight. */ | |
8969 | if (GET_CODE (operands[2]) != CONST_INT | |
8970 | || INTVAL (operands[2]) <= 2 | |
8971 | || INTVAL (operands[2]) > 8 | |
8972 | || GET_CODE (operands[0]) != MEM | |
8973 | || GET_CODE (operands[1]) != REG | |
8974 | || REGNO (operands[1]) >= 32) | |
8975 | FAIL; | |
8976 | ||
8977 | count = INTVAL (operands[2]); | |
8978 | regno = REGNO (operands[1]); | |
8979 | ||
39403d82 | 8980 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 8981 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 8982 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
8983 | |
8984 | XVECEXP (operands[3], 0, 0) | |
7ef788f0 | 8985 | = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]); |
39403d82 | 8986 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8987 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8988 | |
8989 | for (i = 1; i < count; i++) | |
8990 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8991 | = gen_rtx_SET (VOIDmode, |
7ef788f0 | 8992 | adjust_address_nv (op0, SImode, i * 4), |
c5c76735 | 8993 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
8994 | }") |
8995 | ||
9caa3eb2 | 8996 | (define_insn "*store_multiple_power" |
1fd4e8c1 RK |
8997 | [(match_parallel 0 "store_multiple_operation" |
8998 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 8999 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9000 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 9001 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
9002 | "{stsi|stswi} %2,%P1,%O0" |
9003 | [(set_attr "type" "store")]) | |
d14a6d05 | 9004 | |
e46e3130 | 9005 | (define_insn "*stmsi8" |
d14a6d05 | 9006 | [(match_parallel 0 "store_multiple_operation" |
e46e3130 DJ |
9007 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
9008 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9009 | (clobber (match_scratch:SI 3 "X")) | |
9010 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9011 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9012 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9013 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9014 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9015 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9016 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9017 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9018 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9019 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
9020 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
9021 | (match_operand:SI 9 "gpc_reg_operand" "r")) | |
9022 | (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
9023 | (match_operand:SI 10 "gpc_reg_operand" "r"))])] | |
9024 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9" | |
9025 | "{stsi|stswi} %2,%1,%O0" | |
9026 | [(set_attr "type" "store")]) | |
9027 | ||
9028 | (define_insn "*stmsi7" | |
9029 | [(match_parallel 0 "store_multiple_operation" | |
9030 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9031 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9032 | (clobber (match_scratch:SI 3 "X")) | |
9033 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9034 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9035 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9036 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9037 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9038 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9039 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9040 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9041 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9042 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
9043 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
9044 | (match_operand:SI 9 "gpc_reg_operand" "r"))])] | |
9045 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8" | |
9046 | "{stsi|stswi} %2,%1,%O0" | |
9047 | [(set_attr "type" "store")]) | |
9048 | ||
9049 | (define_insn "*stmsi6" | |
9050 | [(match_parallel 0 "store_multiple_operation" | |
9051 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9052 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9053 | (clobber (match_scratch:SI 3 "X")) | |
9054 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9055 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9056 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9057 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9058 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9059 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9060 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9061 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9062 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9063 | (match_operand:SI 8 "gpc_reg_operand" "r"))])] | |
9064 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7" | |
9065 | "{stsi|stswi} %2,%1,%O0" | |
9066 | [(set_attr "type" "store")]) | |
9067 | ||
9068 | (define_insn "*stmsi5" | |
9069 | [(match_parallel 0 "store_multiple_operation" | |
9070 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9071 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9072 | (clobber (match_scratch:SI 3 "X")) | |
9073 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9074 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9075 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9076 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9077 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9078 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9079 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9080 | (match_operand:SI 7 "gpc_reg_operand" "r"))])] | |
9081 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6" | |
9082 | "{stsi|stswi} %2,%1,%O0" | |
9083 | [(set_attr "type" "store")]) | |
9084 | ||
9085 | (define_insn "*stmsi4" | |
9086 | [(match_parallel 0 "store_multiple_operation" | |
9087 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9088 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9089 | (clobber (match_scratch:SI 3 "X")) | |
9090 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9091 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9092 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9093 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9094 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9095 | (match_operand:SI 6 "gpc_reg_operand" "r"))])] | |
9096 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5" | |
b7ff3d82 DE |
9097 | "{stsi|stswi} %2,%1,%O0" |
9098 | [(set_attr "type" "store")]) | |
7e69e155 | 9099 | |
e46e3130 DJ |
9100 | (define_insn "*stmsi3" |
9101 | [(match_parallel 0 "store_multiple_operation" | |
9102 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9103 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9104 | (clobber (match_scratch:SI 3 "X")) | |
9105 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9106 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9107 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9108 | (match_operand:SI 5 "gpc_reg_operand" "r"))])] | |
9109 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4" | |
9110 | "{stsi|stswi} %2,%1,%O0" | |
9111 | [(set_attr "type" "store")]) | |
7e69e155 MM |
9112 | \f |
9113 | ;; String/block move insn. | |
9114 | ;; Argument 0 is the destination | |
9115 | ;; Argument 1 is the source | |
9116 | ;; Argument 2 is the length | |
9117 | ;; Argument 3 is the alignment | |
9118 | ||
9119 | (define_expand "movstrsi" | |
b6c9286a MM |
9120 | [(parallel [(set (match_operand:BLK 0 "" "") |
9121 | (match_operand:BLK 1 "" "")) | |
9122 | (use (match_operand:SI 2 "" "")) | |
9123 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
9124 | "" |
9125 | " | |
9126 | { | |
9127 | if (expand_block_move (operands)) | |
9128 | DONE; | |
9129 | else | |
9130 | FAIL; | |
9131 | }") | |
9132 | ||
9133 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
9134 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
9135 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9136 | (define_expand "movstrsi_8reg" |
b6c9286a MM |
9137 | [(parallel [(set (match_operand 0 "" "") |
9138 | (match_operand 1 "" "")) | |
9139 | (use (match_operand 2 "" "")) | |
9140 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
9141 | (clobber (reg:SI 5)) |
9142 | (clobber (reg:SI 6)) | |
9143 | (clobber (reg:SI 7)) | |
9144 | (clobber (reg:SI 8)) | |
9145 | (clobber (reg:SI 9)) | |
9146 | (clobber (reg:SI 10)) | |
9147 | (clobber (reg:SI 11)) | |
9148 | (clobber (reg:SI 12)) | |
3c67b673 | 9149 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9150 | "TARGET_STRING" |
9151 | "") | |
9152 | ||
9153 | (define_insn "" | |
52d3af72 DE |
9154 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9155 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9156 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9157 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9158 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9159 | (clobber (reg:SI 6)) |
9160 | (clobber (reg:SI 7)) | |
9161 | (clobber (reg:SI 8)) | |
9162 | (clobber (reg:SI 9)) | |
9163 | (clobber (reg:SI 10)) | |
9164 | (clobber (reg:SI 11)) | |
9165 | (clobber (reg:SI 12)) | |
3c67b673 | 9166 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 9167 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
9168 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9169 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9170 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9171 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9172 | && REGNO (operands[4]) == 5" |
9173 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9174 | [(set_attr "type" "load") |
9175 | (set_attr "length" "8")]) | |
7e69e155 MM |
9176 | |
9177 | (define_insn "" | |
52d3af72 DE |
9178 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9179 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9180 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9181 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9182 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9183 | (clobber (reg:SI 6)) |
9184 | (clobber (reg:SI 7)) | |
9185 | (clobber (reg:SI 8)) | |
9186 | (clobber (reg:SI 9)) | |
9187 | (clobber (reg:SI 10)) | |
9188 | (clobber (reg:SI 11)) | |
9189 | (clobber (reg:SI 12)) | |
3c67b673 | 9190 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9191 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
9192 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9193 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9194 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9195 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9196 | && REGNO (operands[4]) == 5" |
9197 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9198 | [(set_attr "type" "load") |
9199 | (set_attr "length" "8")]) | |
7e69e155 | 9200 | |
09a625f7 TR |
9201 | (define_insn "" |
9202 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9203 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9204 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9205 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9206 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9207 | (clobber (reg:SI 6)) | |
9208 | (clobber (reg:SI 7)) | |
9209 | (clobber (reg:SI 8)) | |
9210 | (clobber (reg:SI 9)) | |
9211 | (clobber (reg:SI 10)) | |
9212 | (clobber (reg:SI 11)) | |
9213 | (clobber (reg:SI 12)) | |
9214 | (clobber (match_scratch:SI 5 "X"))] | |
9215 | "TARGET_STRING && TARGET_POWERPC64 | |
9216 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) | |
9217 | || INTVAL (operands[2]) == 0) | |
9218 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
9219 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
9220 | && REGNO (operands[4]) == 5" | |
9221 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9222 | [(set_attr "type" "load") | |
9223 | (set_attr "length" "8")]) | |
9224 | ||
7e69e155 | 9225 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the |
f9562f27 DE |
9226 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
9227 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9228 | (define_expand "movstrsi_6reg" |
b6c9286a MM |
9229 | [(parallel [(set (match_operand 0 "" "") |
9230 | (match_operand 1 "" "")) | |
9231 | (use (match_operand 2 "" "")) | |
9232 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9233 | (clobber (reg:SI 5)) |
9234 | (clobber (reg:SI 6)) | |
7e69e155 MM |
9235 | (clobber (reg:SI 7)) |
9236 | (clobber (reg:SI 8)) | |
9237 | (clobber (reg:SI 9)) | |
9238 | (clobber (reg:SI 10)) | |
3c67b673 | 9239 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9240 | "TARGET_STRING" |
9241 | "") | |
9242 | ||
9243 | (define_insn "" | |
52d3af72 DE |
9244 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9245 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9246 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9247 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9248 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9249 | (clobber (reg:SI 6)) |
9250 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9251 | (clobber (reg:SI 8)) |
9252 | (clobber (reg:SI 9)) | |
9253 | (clobber (reg:SI 10)) | |
3c67b673 | 9254 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9255 | "TARGET_STRING && TARGET_POWER |
9256 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
9257 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9258 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9259 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9260 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9261 | [(set_attr "type" "load") |
9262 | (set_attr "length" "8")]) | |
7e69e155 MM |
9263 | |
9264 | (define_insn "" | |
52d3af72 DE |
9265 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9266 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9267 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9268 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9269 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9270 | (clobber (reg:SI 6)) |
9271 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9272 | (clobber (reg:SI 8)) |
9273 | (clobber (reg:SI 9)) | |
9274 | (clobber (reg:SI 10)) | |
3c67b673 | 9275 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9276 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9277 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
9278 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9279 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9280 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9281 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9282 | [(set_attr "type" "load") |
9283 | (set_attr "length" "8")]) | |
7e69e155 | 9284 | |
09a625f7 TR |
9285 | (define_insn "" |
9286 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9287 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9288 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9289 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9290 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9291 | (clobber (reg:SI 6)) | |
9292 | (clobber (reg:SI 7)) | |
9293 | (clobber (reg:SI 8)) | |
9294 | (clobber (reg:SI 9)) | |
9295 | (clobber (reg:SI 10)) | |
9296 | (clobber (match_scratch:SI 5 "X"))] | |
9297 | "TARGET_STRING && TARGET_POWERPC64 | |
9298 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 | |
9299 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) | |
9300 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9301 | && REGNO (operands[4]) == 5" | |
9302 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9303 | [(set_attr "type" "load") | |
9304 | (set_attr "length" "8")]) | |
9305 | ||
f9562f27 DE |
9306 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
9307 | ;; problems with TImode. | |
9308 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9309 | (define_expand "movstrsi_4reg" |
b6c9286a MM |
9310 | [(parallel [(set (match_operand 0 "" "") |
9311 | (match_operand 1 "" "")) | |
9312 | (use (match_operand 2 "" "")) | |
9313 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9314 | (clobber (reg:SI 5)) |
9315 | (clobber (reg:SI 6)) | |
9316 | (clobber (reg:SI 7)) | |
9317 | (clobber (reg:SI 8)) | |
3c67b673 | 9318 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9319 | "TARGET_STRING" |
9320 | "") | |
9321 | ||
9322 | (define_insn "" | |
52d3af72 DE |
9323 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9324 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9325 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9326 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9327 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9328 | (clobber (reg:SI 6)) |
9329 | (clobber (reg:SI 7)) | |
9330 | (clobber (reg:SI 8)) | |
3c67b673 | 9331 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9332 | "TARGET_STRING && TARGET_POWER |
9333 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
9334 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9335 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9336 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9337 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9338 | [(set_attr "type" "load") |
9339 | (set_attr "length" "8")]) | |
7e69e155 MM |
9340 | |
9341 | (define_insn "" | |
52d3af72 DE |
9342 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9343 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9344 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9345 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9346 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9347 | (clobber (reg:SI 6)) |
9348 | (clobber (reg:SI 7)) | |
9349 | (clobber (reg:SI 8)) | |
3c67b673 | 9350 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9351 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9352 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
9353 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9354 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9355 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9356 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9357 | [(set_attr "type" "load") |
9358 | (set_attr "length" "8")]) | |
7e69e155 | 9359 | |
09a625f7 TR |
9360 | (define_insn "" |
9361 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9362 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9363 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9364 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9365 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9366 | (clobber (reg:SI 6)) | |
9367 | (clobber (reg:SI 7)) | |
9368 | (clobber (reg:SI 8)) | |
9369 | (clobber (match_scratch:SI 5 "X"))] | |
9370 | "TARGET_STRING && TARGET_POWERPC64 | |
9371 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
9372 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) | |
9373 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9374 | && REGNO (operands[4]) == 5" | |
9375 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9376 | [(set_attr "type" "load") | |
9377 | (set_attr "length" "8")]) | |
9378 | ||
7e69e155 MM |
9379 | ;; Move up to 8 bytes at a time. |
9380 | (define_expand "movstrsi_2reg" | |
b6c9286a MM |
9381 | [(parallel [(set (match_operand 0 "" "") |
9382 | (match_operand 1 "" "")) | |
9383 | (use (match_operand 2 "" "")) | |
9384 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9385 | (clobber (match_scratch:DI 4 "")) |
9386 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 9387 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
9388 | "") |
9389 | ||
9390 | (define_insn "" | |
52d3af72 DE |
9391 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9392 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9393 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9394 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9395 | (clobber (match_scratch:DI 4 "=&r")) | |
9396 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 9397 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
9398 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
9399 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9400 | [(set_attr "type" "load") |
9401 | (set_attr "length" "8")]) | |
7e69e155 MM |
9402 | |
9403 | (define_insn "" | |
52d3af72 DE |
9404 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9405 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9406 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9407 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9408 | (clobber (match_scratch:DI 4 "=&r")) | |
9409 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 9410 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 9411 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 9412 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9413 | [(set_attr "type" "load") |
9414 | (set_attr "length" "8")]) | |
7e69e155 MM |
9415 | |
9416 | ;; Move up to 4 bytes at a time. | |
9417 | (define_expand "movstrsi_1reg" | |
b6c9286a MM |
9418 | [(parallel [(set (match_operand 0 "" "") |
9419 | (match_operand 1 "" "")) | |
9420 | (use (match_operand 2 "" "")) | |
9421 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9422 | (clobber (match_scratch:SI 4 "")) |
9423 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
9424 | "TARGET_STRING" |
9425 | "") | |
9426 | ||
9427 | (define_insn "" | |
52d3af72 DE |
9428 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9429 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9430 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9431 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9432 | (clobber (match_scratch:SI 4 "=&r")) | |
9433 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
9434 | "TARGET_STRING && TARGET_POWER |
9435 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9436 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9437 | [(set_attr "type" "load") |
9438 | (set_attr "length" "8")]) | |
7e69e155 MM |
9439 | |
9440 | (define_insn "" | |
52d3af72 DE |
9441 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9442 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9443 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9444 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9445 | (clobber (match_scratch:SI 4 "=&r")) | |
9446 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 9447 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9448 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
09a625f7 TR |
9449 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
9450 | [(set_attr "type" "load") | |
9451 | (set_attr "length" "8")]) | |
9452 | ||
9453 | (define_insn "" | |
9454 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9455 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9456 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9457 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9458 | (clobber (match_scratch:SI 4 "=&r")) | |
9459 | (clobber (match_scratch:SI 5 "X"))] | |
9460 | "TARGET_STRING && TARGET_POWERPC64 | |
9461 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9462 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9463 | [(set_attr "type" "load") |
9464 | (set_attr "length" "8")]) | |
7e69e155 | 9465 | |
1fd4e8c1 | 9466 | \f |
7e69e155 | 9467 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
9468 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
9469 | ;; do cases where the increment is not the size of the object. | |
9470 | ;; | |
9471 | ;; In all these cases, we use operands 0 and 1 for the register being | |
9472 | ;; incremented because those are the operands that local-alloc will | |
9473 | ;; tie and these are the pair most likely to be tieable (and the ones | |
9474 | ;; that will benefit the most). | |
9475 | ||
38c1f2d7 | 9476 | (define_insn "*movdi_update1" |
51b8fc2c | 9477 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 9478 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 9479 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) |
51b8fc2c RK |
9480 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") |
9481 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9482 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9483 | "@ |
9484 | ldux %3,%0,%2 | |
9485 | ldu %3,%2(%0)" | |
b54cf83a | 9486 | [(set_attr "type" "load_ux,load_u")]) |
287f13ff | 9487 | |
4697a36c | 9488 | (define_insn "movdi_update" |
51b8fc2c | 9489 | [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 9490 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))) |
51b8fc2c RK |
9491 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) |
9492 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
9493 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9494 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9495 | "@ |
9496 | stdux %3,%0,%2 | |
b7ff3d82 | 9497 | stdu %3,%2(%0)" |
b54cf83a | 9498 | [(set_attr "type" "store_ux,store_u")]) |
51b8fc2c | 9499 | |
38c1f2d7 | 9500 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
9501 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
9502 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9503 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9504 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9505 | (plus:SI (match_dup 1) (match_dup 2)))] |
f7b3ab8a | 9506 | "TARGET_UPDATE" |
1fd4e8c1 | 9507 | "@ |
ca7f5001 RK |
9508 | {lux|lwzux} %3,%0,%2 |
9509 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a DE |
9510 | [(set_attr "type" "load_ux,load_u")]) |
9511 | ||
9512 | (define_insn "*movsi_update2" | |
9513 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
9514 | (sign_extend:DI | |
9515 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
9516 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
9517 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
9518 | (plus:DI (match_dup 1) (match_dup 2)))] | |
9519 | "TARGET_POWERPC64" | |
9520 | "lwaux %3,%0,%2" | |
9521 | [(set_attr "type" "load_ext_ux")]) | |
1fd4e8c1 | 9522 | |
4697a36c | 9523 | (define_insn "movsi_update" |
cd2b37d9 | 9524 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9525 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9526 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
9527 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9528 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9529 | "TARGET_UPDATE" |
1fd4e8c1 | 9530 | "@ |
ca7f5001 | 9531 | {stux|stwux} %3,%0,%2 |
b7ff3d82 | 9532 | {stu|stwu} %3,%2(%0)" |
b54cf83a | 9533 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9534 | |
b54cf83a | 9535 | (define_insn "*movhi_update1" |
cd2b37d9 RK |
9536 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
9537 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9538 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9539 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9540 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9541 | "TARGET_UPDATE" |
1fd4e8c1 | 9542 | "@ |
5f243543 RK |
9543 | lhzux %3,%0,%2 |
9544 | lhzu %3,%2(%0)" | |
b54cf83a | 9545 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9546 | |
38c1f2d7 | 9547 | (define_insn "*movhi_update2" |
cd2b37d9 | 9548 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9549 | (zero_extend:SI |
cd2b37d9 | 9550 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9551 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9552 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9553 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9554 | "TARGET_UPDATE" |
1fd4e8c1 | 9555 | "@ |
5f243543 RK |
9556 | lhzux %3,%0,%2 |
9557 | lhzu %3,%2(%0)" | |
b54cf83a | 9558 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9559 | |
38c1f2d7 | 9560 | (define_insn "*movhi_update3" |
cd2b37d9 | 9561 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9562 | (sign_extend:SI |
cd2b37d9 | 9563 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9564 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9565 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9566 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9567 | "TARGET_UPDATE" |
1fd4e8c1 | 9568 | "@ |
5f243543 RK |
9569 | lhaux %3,%0,%2 |
9570 | lhau %3,%2(%0)" | |
b54cf83a | 9571 | [(set_attr "type" "load_ext_ux,load_ext_u")]) |
1fd4e8c1 | 9572 | |
38c1f2d7 | 9573 | (define_insn "*movhi_update4" |
cd2b37d9 | 9574 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9575 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9576 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
9577 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9578 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9579 | "TARGET_UPDATE" |
1fd4e8c1 | 9580 | "@ |
5f243543 | 9581 | sthux %3,%0,%2 |
b7ff3d82 | 9582 | sthu %3,%2(%0)" |
b54cf83a | 9583 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9584 | |
38c1f2d7 | 9585 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
9586 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
9587 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9588 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9589 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9590 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9591 | "TARGET_UPDATE" |
1fd4e8c1 | 9592 | "@ |
5f243543 RK |
9593 | lbzux %3,%0,%2 |
9594 | lbzu %3,%2(%0)" | |
b54cf83a | 9595 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9596 | |
38c1f2d7 | 9597 | (define_insn "*movqi_update2" |
cd2b37d9 | 9598 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9599 | (zero_extend:SI |
cd2b37d9 | 9600 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9601 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9602 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9603 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9604 | "TARGET_UPDATE" |
1fd4e8c1 | 9605 | "@ |
5f243543 RK |
9606 | lbzux %3,%0,%2 |
9607 | lbzu %3,%2(%0)" | |
b54cf83a | 9608 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9609 | |
38c1f2d7 | 9610 | (define_insn "*movqi_update3" |
cd2b37d9 | 9611 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9612 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9613 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
9614 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9615 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9616 | "TARGET_UPDATE" |
1fd4e8c1 | 9617 | "@ |
5f243543 | 9618 | stbux %3,%0,%2 |
b7ff3d82 | 9619 | stbu %3,%2(%0)" |
b54cf83a | 9620 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9621 | |
38c1f2d7 | 9622 | (define_insn "*movsf_update1" |
cd2b37d9 | 9623 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 9624 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9625 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9626 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9627 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9628 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9629 | "@ |
5f243543 RK |
9630 | lfsux %3,%0,%2 |
9631 | lfsu %3,%2(%0)" | |
b54cf83a | 9632 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9633 | |
38c1f2d7 | 9634 | (define_insn "*movsf_update2" |
cd2b37d9 | 9635 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9636 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9637 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
9638 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9639 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9640 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9641 | "@ |
85fff2f3 | 9642 | stfsux %3,%0,%2 |
b7ff3d82 | 9643 | stfsu %3,%2(%0)" |
b54cf83a | 9644 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
1fd4e8c1 | 9645 | |
38c1f2d7 MM |
9646 | (define_insn "*movsf_update3" |
9647 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
9648 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9649 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
9650 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9651 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9652 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9653 | "@ |
9654 | {lux|lwzux} %3,%0,%2 | |
9655 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a | 9656 | [(set_attr "type" "load_ux,load_u")]) |
38c1f2d7 MM |
9657 | |
9658 | (define_insn "*movsf_update4" | |
9659 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9660 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
9661 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
9662 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9663 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9664 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9665 | "@ |
9666 | {stux|stwux} %3,%0,%2 | |
9667 | {stu|stwu} %3,%2(%0)" | |
b54cf83a | 9668 | [(set_attr "type" "store_ux,store_u")]) |
38c1f2d7 MM |
9669 | |
9670 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
9671 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
9672 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9673 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9674 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9675 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9676 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9677 | "@ |
5f243543 RK |
9678 | lfdux %3,%0,%2 |
9679 | lfdu %3,%2(%0)" | |
b54cf83a | 9680 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9681 | |
38c1f2d7 | 9682 | (define_insn "*movdf_update2" |
cd2b37d9 | 9683 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9684 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9685 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
9686 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9687 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9688 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9689 | "@ |
5f243543 | 9690 | stfdux %3,%0,%2 |
b7ff3d82 | 9691 | stfdu %3,%2(%0)" |
b54cf83a | 9692 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
4c70a4f3 RK |
9693 | |
9694 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
9695 | ||
9696 | (define_peephole | |
9697 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
9698 | (match_operand:DF 1 "memory_operand" "")) | |
9699 | (set (match_operand:DF 2 "gpc_reg_operand" "=f") | |
9700 | (match_operand:DF 3 "memory_operand" ""))] | |
9701 | "TARGET_POWER2 | |
a3170dc6 | 9702 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 RK |
9703 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
9704 | && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) | |
9705 | && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" | |
9706 | "lfq%U1%X1 %0,%1") | |
9707 | ||
9708 | (define_peephole | |
9709 | [(set (match_operand:DF 0 "memory_operand" "") | |
9710 | (match_operand:DF 1 "gpc_reg_operand" "f")) | |
9711 | (set (match_operand:DF 2 "memory_operand" "") | |
9712 | (match_operand:DF 3 "gpc_reg_operand" "f"))] | |
9713 | "TARGET_POWER2 | |
a3170dc6 | 9714 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 RK |
9715 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
9716 | && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) | |
9717 | && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" | |
9718 | "stfq%U0%X0 %1,%0") | |
1fd4e8c1 RK |
9719 | \f |
9720 | ;; Next come insns related to the calling sequence. | |
9721 | ;; | |
9722 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 9723 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
9724 | |
9725 | (define_expand "allocate_stack" | |
52d3af72 | 9726 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9727 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
9728 | (set (reg 1) | |
9729 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
9730 | "" |
9731 | " | |
4697a36c | 9732 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 9733 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 9734 | rtx neg_op0; |
1fd4e8c1 RK |
9735 | |
9736 | emit_move_insn (chain, stack_bot); | |
4697a36c | 9737 | |
a157febd GK |
9738 | /* Check stack bounds if necessary. */ |
9739 | if (current_function_limit_stack) | |
9740 | { | |
9741 | rtx available; | |
9742 | available = expand_binop (Pmode, sub_optab, | |
9743 | stack_pointer_rtx, stack_limit_rtx, | |
9744 | NULL_RTX, 1, OPTAB_WIDEN); | |
9745 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
9746 | } | |
9747 | ||
e9a25f70 JL |
9748 | if (GET_CODE (operands[1]) != CONST_INT |
9749 | || INTVAL (operands[1]) < -32767 | |
9750 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
9751 | { |
9752 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 9753 | if (TARGET_32BIT) |
e9a25f70 | 9754 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 9755 | else |
e9a25f70 | 9756 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
9757 | } |
9758 | else | |
e9a25f70 | 9759 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 9760 | |
38c1f2d7 MM |
9761 | if (TARGET_UPDATE) |
9762 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) | |
9763 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); | |
4697a36c | 9764 | |
38c1f2d7 MM |
9765 | else |
9766 | { | |
9767 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
9768 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 9769 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 9770 | } |
e9a25f70 JL |
9771 | |
9772 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
9773 | DONE; |
9774 | }") | |
59257ff7 RK |
9775 | |
9776 | ;; These patterns say how to save and restore the stack pointer. We need not | |
9777 | ;; save the stack pointer at function level since we are careful to | |
9778 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9779 | ;; when we restore the stack pointer. | |
9780 | ;; | |
9781 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9782 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9783 | ;; save area is a memory location. | |
9784 | ||
9785 | (define_expand "save_stack_function" | |
ff381587 MM |
9786 | [(match_operand 0 "any_operand" "") |
9787 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9788 | "" |
ff381587 | 9789 | "DONE;") |
59257ff7 RK |
9790 | |
9791 | (define_expand "restore_stack_function" | |
ff381587 MM |
9792 | [(match_operand 0 "any_operand" "") |
9793 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9794 | "" |
ff381587 | 9795 | "DONE;") |
59257ff7 RK |
9796 | |
9797 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
9798 | [(use (match_operand 0 "register_operand" "")) |
9799 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 9800 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 9801 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
9802 | "" |
9803 | " | |
dfdfa60f DE |
9804 | { |
9805 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 9806 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 9807 | }") |
59257ff7 RK |
9808 | |
9809 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
9810 | [(match_operand 0 "memory_operand" "") |
9811 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
9812 | "" |
9813 | " | |
9814 | { | |
a260abc9 | 9815 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
9816 | |
9817 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 9818 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
c5c76735 JL |
9819 | emit_move_insn (operand_subword (operands[0], 0, 0, |
9820 | (TARGET_32BIT ? DImode : TImode)), | |
a260abc9 DE |
9821 | temp); |
9822 | emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)), | |
9823 | operands[1]); | |
59257ff7 RK |
9824 | DONE; |
9825 | }") | |
7e69e155 | 9826 | |
59257ff7 | 9827 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
9828 | [(match_operand 0 "register_operand" "") |
9829 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
9830 | "" |
9831 | " | |
9832 | { | |
a260abc9 | 9833 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
9834 | |
9835 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 DE |
9836 | emit_move_insn (temp, |
9837 | operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode))); | |
9838 | emit_move_insn (operands[0], | |
c5c76735 JL |
9839 | operand_subword (operands[1], 1, 0, |
9840 | (TARGET_32BIT ? DImode : TImode))); | |
39403d82 | 9841 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
9842 | DONE; |
9843 | }") | |
9ebbca7d GK |
9844 | \f |
9845 | ;; TOC register handling. | |
b6c9286a | 9846 | |
9ebbca7d | 9847 | ;; Code to initialize the TOC register... |
f0f6a223 | 9848 | |
9ebbca7d | 9849 | (define_insn "load_toc_aix_si" |
e72247f4 | 9850 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
615158e2 | 9851 | (unspec:SI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 9852 | (use (reg:SI 2))])] |
2bfcf297 | 9853 | "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" |
f0f6a223 RK |
9854 | "* |
9855 | { | |
9ebbca7d GK |
9856 | char buf[30]; |
9857 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 9858 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9859 | operands[2] = gen_rtx_REG (Pmode, 2); |
9860 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
9861 | }" |
9862 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
9863 | |
9864 | (define_insn "load_toc_aix_di" | |
e72247f4 | 9865 | [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
615158e2 | 9866 | (unspec:DI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 9867 | (use (reg:DI 2))])] |
2bfcf297 | 9868 | "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" |
9ebbca7d GK |
9869 | "* |
9870 | { | |
9871 | char buf[30]; | |
f585a356 DE |
9872 | #ifdef TARGET_RELOCATABLE |
9873 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", | |
9874 | !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); | |
9875 | #else | |
9ebbca7d | 9876 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); |
f585a356 | 9877 | #endif |
2bfcf297 DB |
9878 | if (TARGET_ELF) |
9879 | strcat (buf, \"@toc\"); | |
a8a05998 | 9880 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9881 | operands[2] = gen_rtx_REG (Pmode, 2); |
9882 | return \"ld %0,%1(%2)\"; | |
9883 | }" | |
9884 | [(set_attr "type" "load")]) | |
9885 | ||
9886 | (define_insn "load_toc_v4_pic_si" | |
9887 | [(set (match_operand:SI 0 "register_operand" "=l") | |
615158e2 | 9888 | (unspec:SI [(const_int 0)] UNSPEC_TOC))] |
f607bc57 | 9889 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" |
9ebbca7d GK |
9890 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
9891 | [(set_attr "type" "branch") | |
9892 | (set_attr "length" "4")]) | |
9893 | ||
9ebbca7d GK |
9894 | (define_insn "load_toc_v4_PIC_1" |
9895 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9896 | (match_operand:SI 1 "immediate_operand" "s")) | |
615158e2 | 9897 | (unspec [(match_dup 1)] UNSPEC_TOC)] |
20b71b17 | 9898 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
df7a8989 | 9899 | "bcl 20,31,%1\\n%1:" |
9ebbca7d GK |
9900 | [(set_attr "type" "branch") |
9901 | (set_attr "length" "4")]) | |
9902 | ||
9903 | (define_insn "load_toc_v4_PIC_1b" | |
9904 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9905 | (match_operand:SI 1 "immediate_operand" "s")) | |
615158e2 JJ |
9906 | (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] |
9907 | UNSPEC_TOCPTR)] | |
20b71b17 | 9908 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
df7a8989 | 9909 | "bcl 20,31,%1\\n\\t.long %2-%1+4\\n%1:" |
9ebbca7d GK |
9910 | [(set_attr "type" "branch") |
9911 | (set_attr "length" "8")]) | |
9912 | ||
9913 | (define_insn "load_toc_v4_PIC_2" | |
f585a356 | 9914 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
a2900460 | 9915 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
9ebbca7d GK |
9916 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") |
9917 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
20b71b17 | 9918 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
9ebbca7d GK |
9919 | "{l|lwz} %0,%2-%3(%1)" |
9920 | [(set_attr "type" "load")]) | |
9921 | ||
ee890fe2 SS |
9922 | (define_insn "load_macho_picbase" |
9923 | [(set (match_operand:SI 0 "register_operand" "=l") | |
615158e2 JJ |
9924 | (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] |
9925 | UNSPEC_LD_MPIC))] | |
ee890fe2 | 9926 | "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" |
f51eee6a | 9927 | "bcl 20,31,%1\\n%1:" |
ee890fe2 SS |
9928 | [(set_attr "type" "branch") |
9929 | (set_attr "length" "4")]) | |
9930 | ||
f51eee6a GK |
9931 | (define_insn "macho_correct_pic" |
9932 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
8291cc0e | 9933 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
f51eee6a GK |
9934 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "s") |
9935 | (match_operand:SI 3 "immediate_operand" "s")] | |
615158e2 | 9936 | UNSPEC_MPIC_CORRECT)))] |
f51eee6a | 9937 | "DEFAULT_ABI == ABI_DARWIN" |
8291cc0e | 9938 | "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)" |
f51eee6a GK |
9939 | [(set_attr "length" "8")]) |
9940 | ||
9ebbca7d GK |
9941 | ;; If the TOC is shared over a translation unit, as happens with all |
9942 | ;; the kinds of PIC that we support, we need to restore the TOC | |
9943 | ;; pointer only when jumping over units of translation. | |
f51eee6a | 9944 | ;; On Darwin, we need to reload the picbase. |
9ebbca7d GK |
9945 | |
9946 | (define_expand "builtin_setjmp_receiver" | |
9947 | [(use (label_ref (match_operand 0 "" "")))] | |
f607bc57 | 9948 | "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
f51eee6a GK |
9949 | || (TARGET_TOC && TARGET_MINIMAL_TOC) |
9950 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" | |
9ebbca7d GK |
9951 | " |
9952 | { | |
84d7dd4a | 9953 | #if TARGET_MACHO |
f51eee6a GK |
9954 | if (DEFAULT_ABI == ABI_DARWIN) |
9955 | { | |
d24652ee | 9956 | const char *picbase = machopic_function_base_name (); |
f51eee6a GK |
9957 | rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1)); |
9958 | rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); | |
9959 | rtx tmplabrtx; | |
9960 | char tmplab[20]; | |
9961 | ||
9962 | ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", | |
9963 | CODE_LABEL_NUMBER (operands[0])); | |
9964 | tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (tmplab, -1)); | |
9965 | ||
9966 | emit_insn (gen_load_macho_picbase (picreg, tmplabrtx)); | |
9967 | emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); | |
9968 | } | |
9969 | else | |
84d7dd4a | 9970 | #endif |
f51eee6a | 9971 | rs6000_emit_load_toc_table (FALSE); |
9ebbca7d GK |
9972 | DONE; |
9973 | }") | |
9974 | \f | |
9975 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
9976 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
9977 | ;; pointer to its TOC, and whose third word contains a value to place in the |
9978 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 9979 | ;; "trampoline" need not have any executable code. |
b6c9286a | 9980 | |
cccf3bdc DE |
9981 | (define_expand "call_indirect_aix32" |
9982 | [(set (match_dup 2) | |
9983 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
9984 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9985 | (reg:SI 2)) | |
9986 | (set (reg:SI 2) | |
9987 | (mem:SI (plus:SI (match_dup 0) | |
9988 | (const_int 4)))) | |
9989 | (set (reg:SI 11) | |
9990 | (mem:SI (plus:SI (match_dup 0) | |
9991 | (const_int 8)))) | |
9992 | (parallel [(call (mem:SI (match_dup 2)) | |
9993 | (match_operand 1 "" "")) | |
9994 | (use (reg:SI 2)) | |
9995 | (use (reg:SI 11)) | |
9996 | (set (reg:SI 2) | |
9997 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9998 | (clobber (scratch:SI))])] | |
9999 | "TARGET_32BIT" | |
10000 | " | |
10001 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10002 | |
cccf3bdc DE |
10003 | (define_expand "call_indirect_aix64" |
10004 | [(set (match_dup 2) | |
10005 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
10006 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10007 | (reg:DI 2)) | |
10008 | (set (reg:DI 2) | |
10009 | (mem:DI (plus:DI (match_dup 0) | |
10010 | (const_int 8)))) | |
10011 | (set (reg:DI 11) | |
10012 | (mem:DI (plus:DI (match_dup 0) | |
10013 | (const_int 16)))) | |
10014 | (parallel [(call (mem:SI (match_dup 2)) | |
10015 | (match_operand 1 "" "")) | |
10016 | (use (reg:DI 2)) | |
10017 | (use (reg:DI 11)) | |
10018 | (set (reg:DI 2) | |
10019 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10020 | (clobber (scratch:SI))])] | |
10021 | "TARGET_64BIT" | |
10022 | " | |
10023 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 10024 | |
cccf3bdc DE |
10025 | (define_expand "call_value_indirect_aix32" |
10026 | [(set (match_dup 3) | |
10027 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10028 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10029 | (reg:SI 2)) | |
10030 | (set (reg:SI 2) | |
10031 | (mem:SI (plus:SI (match_dup 1) | |
10032 | (const_int 4)))) | |
10033 | (set (reg:SI 11) | |
10034 | (mem:SI (plus:SI (match_dup 1) | |
10035 | (const_int 8)))) | |
10036 | (parallel [(set (match_operand 0 "" "") | |
10037 | (call (mem:SI (match_dup 3)) | |
10038 | (match_operand 2 "" ""))) | |
10039 | (use (reg:SI 2)) | |
10040 | (use (reg:SI 11)) | |
10041 | (set (reg:SI 2) | |
10042 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10043 | (clobber (scratch:SI))])] | |
10044 | "TARGET_32BIT" | |
10045 | " | |
10046 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10047 | |
cccf3bdc DE |
10048 | (define_expand "call_value_indirect_aix64" |
10049 | [(set (match_dup 3) | |
10050 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10051 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10052 | (reg:DI 2)) | |
10053 | (set (reg:DI 2) | |
10054 | (mem:DI (plus:DI (match_dup 1) | |
10055 | (const_int 8)))) | |
10056 | (set (reg:DI 11) | |
10057 | (mem:DI (plus:DI (match_dup 1) | |
10058 | (const_int 16)))) | |
10059 | (parallel [(set (match_operand 0 "" "") | |
10060 | (call (mem:SI (match_dup 3)) | |
10061 | (match_operand 2 "" ""))) | |
10062 | (use (reg:DI 2)) | |
10063 | (use (reg:DI 11)) | |
10064 | (set (reg:DI 2) | |
10065 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10066 | (clobber (scratch:SI))])] | |
10067 | "TARGET_64BIT" | |
10068 | " | |
10069 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 10070 | |
b6c9286a | 10071 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 10072 | (define_expand "call" |
a260abc9 | 10073 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 10074 | (match_operand 1 "" "")) |
4697a36c | 10075 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
10076 | (clobber (scratch:SI))])] |
10077 | "" | |
10078 | " | |
10079 | { | |
ee890fe2 | 10080 | #if TARGET_MACHO |
ab82a49f | 10081 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
10082 | operands[0] = machopic_indirect_call_target (operands[0]); |
10083 | #endif | |
10084 | ||
1fd4e8c1 RK |
10085 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) |
10086 | abort (); | |
10087 | ||
10088 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 10089 | |
6a4cee5f MM |
10090 | if (GET_CODE (operands[0]) != SYMBOL_REF |
10091 | || (INTVAL (operands[2]) & CALL_LONG) != 0) | |
1fd4e8c1 | 10092 | { |
6a4cee5f MM |
10093 | if (INTVAL (operands[2]) & CALL_LONG) |
10094 | operands[0] = rs6000_longcall_ref (operands[0]); | |
10095 | ||
cccf3bdc | 10096 | if (DEFAULT_ABI == ABI_V4 |
f607bc57 | 10097 | || DEFAULT_ABI == ABI_DARWIN) |
cccf3bdc | 10098 | operands[0] = force_reg (Pmode, operands[0]); |
1fd4e8c1 | 10099 | |
cccf3bdc DE |
10100 | else if (DEFAULT_ABI == ABI_AIX) |
10101 | { | |
10102 | /* AIX function pointers are really pointers to a three word | |
10103 | area. */ | |
10104 | emit_call_insn (TARGET_32BIT | |
10105 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
10106 | operands[0]), | |
10107 | operands[1]) | |
10108 | : gen_call_indirect_aix64 (force_reg (DImode, | |
10109 | operands[0]), | |
10110 | operands[1])); | |
10111 | DONE; | |
b6c9286a | 10112 | } |
cccf3bdc DE |
10113 | else |
10114 | abort (); | |
1fd4e8c1 RK |
10115 | } |
10116 | }") | |
10117 | ||
10118 | (define_expand "call_value" | |
10119 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 10120 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 10121 | (match_operand 2 "" ""))) |
4697a36c | 10122 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
10123 | (clobber (scratch:SI))])] |
10124 | "" | |
10125 | " | |
10126 | { | |
ee890fe2 | 10127 | #if TARGET_MACHO |
ab82a49f | 10128 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
10129 | operands[1] = machopic_indirect_call_target (operands[1]); |
10130 | #endif | |
10131 | ||
1fd4e8c1 RK |
10132 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) |
10133 | abort (); | |
10134 | ||
10135 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 10136 | |
6a4cee5f MM |
10137 | if (GET_CODE (operands[1]) != SYMBOL_REF |
10138 | || (INTVAL (operands[3]) & CALL_LONG) != 0) | |
1fd4e8c1 | 10139 | { |
6756293c | 10140 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
10141 | operands[1] = rs6000_longcall_ref (operands[1]); |
10142 | ||
cccf3bdc | 10143 | if (DEFAULT_ABI == ABI_V4 |
f607bc57 | 10144 | || DEFAULT_ABI == ABI_DARWIN) |
cccf3bdc | 10145 | operands[0] = force_reg (Pmode, operands[0]); |
1fd4e8c1 | 10146 | |
cccf3bdc DE |
10147 | else if (DEFAULT_ABI == ABI_AIX) |
10148 | { | |
10149 | /* AIX function pointers are really pointers to a three word | |
10150 | area. */ | |
10151 | emit_call_insn (TARGET_32BIT | |
10152 | ? gen_call_value_indirect_aix32 (operands[0], | |
10153 | force_reg (SImode, | |
10154 | operands[1]), | |
10155 | operands[2]) | |
10156 | : gen_call_value_indirect_aix64 (operands[0], | |
10157 | force_reg (DImode, | |
10158 | operands[1]), | |
10159 | operands[2])); | |
10160 | DONE; | |
b6c9286a | 10161 | } |
cccf3bdc DE |
10162 | else |
10163 | abort (); | |
1fd4e8c1 RK |
10164 | } |
10165 | }") | |
10166 | ||
04780ee7 | 10167 | ;; Call to function in current module. No TOC pointer reload needed. |
a0ab749a | 10168 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10169 | ;; either the function was not prototyped, or it was prototyped as a |
10170 | ;; variable argument function. It is > 0 if FP registers were passed | |
10171 | ;; and < 0 if they were not. | |
04780ee7 | 10172 | |
a260abc9 | 10173 | (define_insn "*call_local32" |
4697a36c MM |
10174 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
10175 | (match_operand 1 "" "g,g")) | |
10176 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10177 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 10178 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
10179 | "* |
10180 | { | |
6a4cee5f MM |
10181 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
10182 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10183 | ||
10184 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10185 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 10186 | |
a226df46 | 10187 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 10188 | }" |
b7ff3d82 DE |
10189 | [(set_attr "type" "branch") |
10190 | (set_attr "length" "4,8")]) | |
04780ee7 | 10191 | |
a260abc9 DE |
10192 | (define_insn "*call_local64" |
10193 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10194 | (match_operand 1 "" "g,g")) | |
10195 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10196 | (clobber (match_scratch:SI 3 "=l,l"))] | |
10197 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10198 | "* | |
10199 | { | |
10200 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10201 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10202 | ||
10203 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10204 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10205 | ||
10206 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
10207 | }" | |
10208 | [(set_attr "type" "branch") | |
10209 | (set_attr "length" "4,8")]) | |
10210 | ||
cccf3bdc | 10211 | (define_insn "*call_value_local32" |
d18dba68 | 10212 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10213 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) |
10214 | (match_operand 2 "" "g,g"))) | |
10215 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10216 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10217 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10218 | "* | |
10219 | { | |
10220 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10221 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10222 | ||
10223 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10224 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10225 | ||
10226 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10227 | }" | |
10228 | [(set_attr "type" "branch") | |
10229 | (set_attr "length" "4,8")]) | |
10230 | ||
10231 | ||
cccf3bdc | 10232 | (define_insn "*call_value_local64" |
d18dba68 | 10233 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10234 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) |
10235 | (match_operand 2 "" "g,g"))) | |
10236 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10237 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10238 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10239 | "* | |
10240 | { | |
10241 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10242 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10243 | ||
10244 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10245 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10246 | ||
10247 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10248 | }" | |
10249 | [(set_attr "type" "branch") | |
10250 | (set_attr "length" "4,8")]) | |
10251 | ||
04780ee7 | 10252 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 10253 | ;; pointer (r2) after the call unless this is System V. |
a0ab749a | 10254 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10255 | ;; either the function was not prototyped, or it was prototyped as a |
10256 | ;; variable argument function. It is > 0 if FP registers were passed | |
10257 | ;; and < 0 if they were not. | |
04780ee7 | 10258 | |
cccf3bdc DE |
10259 | (define_insn "*call_indirect_nonlocal_aix32" |
10260 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) | |
10261 | (match_operand 1 "" "g")) | |
10262 | (use (reg:SI 2)) | |
10263 | (use (reg:SI 11)) | |
10264 | (set (reg:SI 2) | |
10265 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
c77e04ae | 10266 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10267 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
10268 | "b%T0l\;{l|lwz} 2,20(1)" | |
10269 | [(set_attr "type" "jmpreg") | |
10270 | (set_attr "length" "8")]) | |
10271 | ||
a260abc9 | 10272 | (define_insn "*call_nonlocal_aix32" |
cc4d5fec | 10273 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10274 | (match_operand 1 "" "g")) |
10275 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10276 | (clobber (match_scratch:SI 3 "=l"))] | |
10277 | "TARGET_32BIT | |
10278 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10279 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10280 | "bl %z0\;%." |
b7ff3d82 | 10281 | [(set_attr "type" "branch") |
cccf3bdc DE |
10282 | (set_attr "length" "8")]) |
10283 | ||
10284 | (define_insn "*call_indirect_nonlocal_aix64" | |
10285 | [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) | |
10286 | (match_operand 1 "" "g")) | |
10287 | (use (reg:DI 2)) | |
10288 | (use (reg:DI 11)) | |
10289 | (set (reg:DI 2) | |
10290 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
c77e04ae | 10291 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10292 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
10293 | "b%T0l\;ld 2,40(1)" | |
10294 | [(set_attr "type" "jmpreg") | |
10295 | (set_attr "length" "8")]) | |
59313e4e | 10296 | |
a260abc9 | 10297 | (define_insn "*call_nonlocal_aix64" |
cc4d5fec | 10298 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10299 | (match_operand 1 "" "g")) |
10300 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10301 | (clobber (match_scratch:SI 3 "=l"))] | |
9ebbca7d GK |
10302 | "TARGET_64BIT |
10303 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10304 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10305 | "bl %z0\;%." |
a260abc9 | 10306 | [(set_attr "type" "branch") |
cccf3bdc | 10307 | (set_attr "length" "8")]) |
7509c759 | 10308 | |
cccf3bdc | 10309 | (define_insn "*call_value_indirect_nonlocal_aix32" |
d18dba68 | 10310 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10311 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) |
10312 | (match_operand 2 "" "g"))) | |
10313 | (use (reg:SI 2)) | |
10314 | (use (reg:SI 11)) | |
10315 | (set (reg:SI 2) | |
10316 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10317 | (clobber (match_scratch:SI 3 "=l"))] | |
10318 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" | |
10319 | "b%T1l\;{l|lwz} 2,20(1)" | |
10320 | [(set_attr "type" "jmpreg") | |
10321 | (set_attr "length" "8")]) | |
1fd4e8c1 | 10322 | |
cccf3bdc | 10323 | (define_insn "*call_value_nonlocal_aix32" |
d18dba68 | 10324 | [(set (match_operand 0 "" "") |
cc4d5fec | 10325 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10326 | (match_operand 2 "" "g"))) |
10327 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10328 | (clobber (match_scratch:SI 4 "=l"))] | |
10329 | "TARGET_32BIT | |
10330 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10331 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 10332 | "bl %z1\;%." |
b7ff3d82 | 10333 | [(set_attr "type" "branch") |
cccf3bdc | 10334 | (set_attr "length" "8")]) |
04780ee7 | 10335 | |
cccf3bdc | 10336 | (define_insn "*call_value_indirect_nonlocal_aix64" |
d18dba68 | 10337 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10338 | (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) |
10339 | (match_operand 2 "" "g"))) | |
10340 | (use (reg:DI 2)) | |
10341 | (use (reg:DI 11)) | |
10342 | (set (reg:DI 2) | |
10343 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10344 | (clobber (match_scratch:SI 3 "=l"))] | |
10345 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" | |
10346 | "b%T1l\;ld 2,40(1)" | |
10347 | [(set_attr "type" "jmpreg") | |
10348 | (set_attr "length" "8")]) | |
10349 | ||
10350 | (define_insn "*call_value_nonlocal_aix64" | |
d18dba68 | 10351 | [(set (match_operand 0 "" "") |
cc4d5fec | 10352 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10353 | (match_operand 2 "" "g"))) |
10354 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10355 | (clobber (match_scratch:SI 4 "=l"))] | |
9ebbca7d GK |
10356 | "TARGET_64BIT |
10357 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10358 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
10359 | "bl %z1\;%." |
10360 | [(set_attr "type" "branch") | |
10361 | (set_attr "length" "8")]) | |
10362 | ||
10363 | ;; A function pointer under System V is just a normal pointer | |
10364 | ;; operands[0] is the function pointer | |
10365 | ;; operands[1] is the stack size to clean up | |
10366 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
10367 | ;; which indicates how to set cr1 | |
10368 | ||
a5c76ee6 ZW |
10369 | (define_insn "*call_indirect_nonlocal_sysv" |
10370 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl")) | |
10371 | (match_operand 1 "" "g,g")) | |
10372 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10373 | (clobber (match_scratch:SI 3 "=l,l"))] | |
50d440bc | 10374 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10375 | || DEFAULT_ABI == ABI_DARWIN" |
911f679c | 10376 | { |
cccf3bdc | 10377 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10378 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f | 10379 | |
cccf3bdc | 10380 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
a5c76ee6 | 10381 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10382 | |
a5c76ee6 ZW |
10383 | return "b%T0l"; |
10384 | } | |
10385 | [(set_attr "type" "jmpreg,jmpreg") | |
10386 | (set_attr "length" "4,8")]) | |
cccf3bdc | 10387 | |
a5c76ee6 ZW |
10388 | (define_insn "*call_nonlocal_sysv" |
10389 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10390 | (match_operand 1 "" "g,g")) | |
10391 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10392 | (clobber (match_scratch:SI 3 "=l,l"))] | |
50d440bc | 10393 | "(DEFAULT_ABI == ABI_V4 |
a5c76ee6 ZW |
10394 | || DEFAULT_ABI == ABI_DARWIN) |
10395 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10396 | { | |
10397 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10398 | output_asm_insn ("crxor 6,6,6", operands); | |
10399 | ||
10400 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10401 | output_asm_insn ("creqv 6,6,6", operands); | |
10402 | ||
10403 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0"; | |
10404 | } | |
10405 | [(set_attr "type" "branch,branch") | |
10406 | (set_attr "length" "4,8")]) | |
10407 | ||
10408 | (define_insn "*call_value_indirect_nonlocal_sysv" | |
d18dba68 | 10409 | [(set (match_operand 0 "" "") |
a5c76ee6 ZW |
10410 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl")) |
10411 | (match_operand 2 "" "g,g"))) | |
10412 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10413 | (clobber (match_scratch:SI 4 "=l,l"))] | |
50d440bc | 10414 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10415 | || DEFAULT_ABI == ABI_DARWIN" |
b6c9286a | 10416 | { |
6a4cee5f | 10417 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10418 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f MM |
10419 | |
10420 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
a5c76ee6 | 10421 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10422 | |
a5c76ee6 ZW |
10423 | return "b%T1l"; |
10424 | } | |
10425 | [(set_attr "type" "jmpreg,jmpreg") | |
10426 | (set_attr "length" "4,8")]) | |
10427 | ||
10428 | (define_insn "*call_value_nonlocal_sysv" | |
10429 | [(set (match_operand 0 "" "") | |
10430 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10431 | (match_operand 2 "" "g,g"))) | |
10432 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10433 | (clobber (match_scratch:SI 4 "=l,l"))] | |
50d440bc | 10434 | "(DEFAULT_ABI == ABI_V4 |
a5c76ee6 ZW |
10435 | || DEFAULT_ABI == ABI_DARWIN) |
10436 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10437 | { | |
10438 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10439 | output_asm_insn ("crxor 6,6,6", operands); | |
10440 | ||
10441 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10442 | output_asm_insn ("creqv 6,6,6", operands); | |
10443 | ||
10444 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1"; | |
10445 | } | |
10446 | [(set_attr "type" "branch,branch") | |
10447 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
10448 | |
10449 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
10450 | (define_expand "untyped_call" |
10451 | [(parallel [(call (match_operand 0 "" "") | |
10452 | (const_int 0)) | |
10453 | (match_operand 1 "" "") | |
10454 | (match_operand 2 "" "")])] | |
10455 | "" | |
10456 | " | |
10457 | { | |
10458 | int i; | |
10459 | ||
7d70b8b2 | 10460 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
10461 | |
10462 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10463 | { | |
10464 | rtx set = XVECEXP (operands[2], 0, i); | |
10465 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10466 | } | |
10467 | ||
10468 | /* The optimizer does not know that the call sets the function value | |
10469 | registers we stored in the result block. We avoid problems by | |
10470 | claiming that all hard registers are used and clobbered at this | |
10471 | point. */ | |
10472 | emit_insn (gen_blockage ()); | |
10473 | ||
10474 | DONE; | |
10475 | }") | |
10476 | ||
5e1bf043 DJ |
10477 | ;; sibling call patterns |
10478 | (define_expand "sibcall" | |
10479 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) | |
10480 | (match_operand 1 "" "")) | |
10481 | (use (match_operand 2 "" "")) | |
fe352c29 | 10482 | (use (match_operand 3 "" "")) |
5e1bf043 DJ |
10483 | (return)])] |
10484 | "" | |
10485 | " | |
10486 | { | |
10487 | #if TARGET_MACHO | |
ab82a49f | 10488 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10489 | operands[0] = machopic_indirect_call_target (operands[0]); |
10490 | #endif | |
10491 | ||
10492 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) | |
10493 | abort (); | |
10494 | ||
10495 | operands[0] = XEXP (operands[0], 0); | |
fe352c29 | 10496 | operands[3] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10497 | |
10498 | }") | |
10499 | ||
10500 | ;; this and similar patterns must be marked as using LR, otherwise | |
10501 | ;; dataflow will try to delete the store into it. This is true | |
10502 | ;; even when the actual reg to jump to is in CTR, when LR was | |
10503 | ;; saved and restored around the PIC-setting BCL. | |
10504 | (define_insn "*sibcall_local32" | |
10505 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) | |
10506 | (match_operand 1 "" "g,g")) | |
10507 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10508 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10509 | (return)] |
10510 | "(INTVAL (operands[2]) & CALL_LONG) == 0" | |
10511 | "* | |
10512 | { | |
10513 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10514 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10515 | ||
10516 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10517 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10518 | ||
10519 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10520 | }" | |
10521 | [(set_attr "type" "branch") | |
10522 | (set_attr "length" "4,8")]) | |
10523 | ||
10524 | (define_insn "*sibcall_local64" | |
10525 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10526 | (match_operand 1 "" "g,g")) | |
10527 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10528 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10529 | (return)] |
10530 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10531 | "* | |
10532 | { | |
10533 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10534 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10535 | ||
10536 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10537 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10538 | ||
10539 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10540 | }" | |
10541 | [(set_attr "type" "branch") | |
10542 | (set_attr "length" "4,8")]) | |
10543 | ||
10544 | (define_insn "*sibcall_value_local32" | |
10545 | [(set (match_operand 0 "" "") | |
10546 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
10547 | (match_operand 2 "" "g,g"))) | |
10548 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10549 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10550 | (return)] |
10551 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10552 | "* | |
10553 | { | |
10554 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10555 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10556 | ||
10557 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10558 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10559 | ||
10560 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10561 | }" | |
10562 | [(set_attr "type" "branch") | |
10563 | (set_attr "length" "4,8")]) | |
10564 | ||
10565 | ||
10566 | (define_insn "*sibcall_value_local64" | |
10567 | [(set (match_operand 0 "" "") | |
10568 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
10569 | (match_operand 2 "" "g,g"))) | |
10570 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10571 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10572 | (return)] |
10573 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10574 | "* | |
10575 | { | |
10576 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10577 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10578 | ||
10579 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10580 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10581 | ||
10582 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10583 | }" | |
10584 | [(set_attr "type" "branch") | |
10585 | (set_attr "length" "4,8")]) | |
10586 | ||
10587 | (define_insn "*sibcall_nonlocal_aix32" | |
10588 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) | |
10589 | (match_operand 1 "" "g")) | |
10590 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10591 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 DJ |
10592 | (return)] |
10593 | "TARGET_32BIT | |
10594 | && DEFAULT_ABI == ABI_AIX | |
10595 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10596 | "b %z0" | |
10597 | [(set_attr "type" "branch") | |
10598 | (set_attr "length" "4")]) | |
10599 | ||
10600 | (define_insn "*sibcall_nonlocal_aix64" | |
10601 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) | |
10602 | (match_operand 1 "" "g")) | |
10603 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10604 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 DJ |
10605 | (return)] |
10606 | "TARGET_64BIT | |
10607 | && DEFAULT_ABI == ABI_AIX | |
10608 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10609 | "b %z0" | |
10610 | [(set_attr "type" "branch") | |
10611 | (set_attr "length" "4")]) | |
10612 | ||
10613 | (define_insn "*sibcall_value_nonlocal_aix32" | |
10614 | [(set (match_operand 0 "" "") | |
10615 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) | |
10616 | (match_operand 2 "" "g"))) | |
10617 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10618 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 DJ |
10619 | (return)] |
10620 | "TARGET_32BIT | |
10621 | && DEFAULT_ABI == ABI_AIX | |
10622 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10623 | "b %z1" | |
10624 | [(set_attr "type" "branch") | |
10625 | (set_attr "length" "4")]) | |
10626 | ||
10627 | (define_insn "*sibcall_value_nonlocal_aix64" | |
10628 | [(set (match_operand 0 "" "") | |
10629 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) | |
10630 | (match_operand 2 "" "g"))) | |
10631 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10632 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 DJ |
10633 | (return)] |
10634 | "TARGET_64BIT | |
10635 | && DEFAULT_ABI == ABI_AIX | |
10636 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10637 | "b %z1" | |
10638 | [(set_attr "type" "branch") | |
10639 | (set_attr "length" "4")]) | |
10640 | ||
10641 | (define_insn "*sibcall_nonlocal_sysv" | |
10642 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10643 | (match_operand 1 "" "")) | |
10644 | (use (match_operand 2 "immediate_operand" "O,n")) | |
fe352c29 | 10645 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10646 | (return)] |
10647 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10648 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10649 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
10650 | "* | |
10651 | { | |
10652 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10653 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10654 | ||
10655 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10656 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10657 | ||
10658 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\"; | |
10659 | }" | |
10660 | [(set_attr "type" "branch,branch") | |
10661 | (set_attr "length" "4,8")]) | |
10662 | ||
10663 | (define_expand "sibcall_value" | |
10664 | [(parallel [(set (match_operand 0 "register_operand" "") | |
10665 | (call (mem:SI (match_operand 1 "address_operand" "")) | |
10666 | (match_operand 2 "" ""))) | |
10667 | (use (match_operand 3 "" "")) | |
fe352c29 | 10668 | (use (match_operand 4 "" "")) |
5e1bf043 DJ |
10669 | (return)])] |
10670 | "" | |
10671 | " | |
10672 | { | |
10673 | #if TARGET_MACHO | |
ab82a49f | 10674 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10675 | operands[1] = machopic_indirect_call_target (operands[1]); |
10676 | #endif | |
10677 | ||
10678 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) | |
10679 | abort (); | |
10680 | ||
10681 | operands[1] = XEXP (operands[1], 0); | |
fe352c29 | 10682 | operands[4] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10683 | |
10684 | }") | |
10685 | ||
10686 | (define_insn "*sibcall_value_nonlocal_sysv" | |
10687 | [(set (match_operand 0 "" "") | |
10688 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10689 | (match_operand 2 "" ""))) | |
10690 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10691 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10692 | (return)] |
10693 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10694 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10695 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
10696 | "* | |
10697 | { | |
10698 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10699 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10700 | ||
10701 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10702 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10703 | ||
10704 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\"; | |
10705 | }" | |
10706 | [(set_attr "type" "branch,branch") | |
10707 | (set_attr "length" "4,8")]) | |
10708 | ||
10709 | (define_expand "sibcall_epilogue" | |
10710 | [(use (const_int 0))] | |
10711 | "TARGET_SCHED_PROLOG" | |
10712 | " | |
10713 | { | |
10714 | rs6000_emit_epilogue (TRUE); | |
10715 | DONE; | |
10716 | }") | |
10717 | ||
e6f948e3 RK |
10718 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and |
10719 | ;; all of memory. This blocks insns from being moved across this point. | |
10720 | ||
10721 | (define_insn "blockage" | |
615158e2 | 10722 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)] |
e6f948e3 RK |
10723 | "" |
10724 | "") | |
1fd4e8c1 RK |
10725 | \f |
10726 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 10727 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
10728 | ;; |
10729 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
10730 | ;; insns, and branches. We store the operands of compares until we see | |
10731 | ;; how it is used. | |
10732 | (define_expand "cmpsi" | |
10733 | [(set (cc0) | |
cd2b37d9 | 10734 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10735 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
10736 | "" | |
10737 | " | |
10738 | { | |
10739 | /* Take care of the possibility that operands[1] might be negative but | |
10740 | this might be a logical operation. That insn doesn't exist. */ | |
10741 | if (GET_CODE (operands[1]) == CONST_INT | |
10742 | && INTVAL (operands[1]) < 0) | |
10743 | operands[1] = force_reg (SImode, operands[1]); | |
10744 | ||
10745 | rs6000_compare_op0 = operands[0]; | |
10746 | rs6000_compare_op1 = operands[1]; | |
10747 | rs6000_compare_fp_p = 0; | |
10748 | DONE; | |
10749 | }") | |
10750 | ||
266eb58a DE |
10751 | (define_expand "cmpdi" |
10752 | [(set (cc0) | |
10753 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
10754 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
10755 | "TARGET_POWERPC64" | |
10756 | " | |
10757 | { | |
10758 | /* Take care of the possibility that operands[1] might be negative but | |
10759 | this might be a logical operation. That insn doesn't exist. */ | |
10760 | if (GET_CODE (operands[1]) == CONST_INT | |
10761 | && INTVAL (operands[1]) < 0) | |
10762 | operands[1] = force_reg (DImode, operands[1]); | |
10763 | ||
10764 | rs6000_compare_op0 = operands[0]; | |
10765 | rs6000_compare_op1 = operands[1]; | |
10766 | rs6000_compare_fp_p = 0; | |
10767 | DONE; | |
10768 | }") | |
10769 | ||
1fd4e8c1 | 10770 | (define_expand "cmpsf" |
cd2b37d9 RK |
10771 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
10772 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 10773 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10774 | " |
10775 | { | |
10776 | rs6000_compare_op0 = operands[0]; | |
10777 | rs6000_compare_op1 = operands[1]; | |
10778 | rs6000_compare_fp_p = 1; | |
10779 | DONE; | |
10780 | }") | |
10781 | ||
10782 | (define_expand "cmpdf" | |
cd2b37d9 RK |
10783 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
10784 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 10785 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
10786 | " |
10787 | { | |
10788 | rs6000_compare_op0 = operands[0]; | |
10789 | rs6000_compare_op1 = operands[1]; | |
10790 | rs6000_compare_fp_p = 1; | |
10791 | DONE; | |
10792 | }") | |
10793 | ||
d6f99ca4 | 10794 | (define_expand "cmptf" |
e7a4130e DE |
10795 | [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "") |
10796 | (match_operand:TF 1 "gpc_reg_operand" "")))] | |
a3170dc6 AH |
10797 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT |
10798 | && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
d6f99ca4 DE |
10799 | " |
10800 | { | |
10801 | rs6000_compare_op0 = operands[0]; | |
10802 | rs6000_compare_op1 = operands[1]; | |
10803 | rs6000_compare_fp_p = 1; | |
10804 | DONE; | |
10805 | }") | |
10806 | ||
1fd4e8c1 | 10807 | (define_expand "beq" |
39a10a29 | 10808 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10809 | "" |
39a10a29 | 10810 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10811 | |
10812 | (define_expand "bne" | |
39a10a29 | 10813 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10814 | "" |
39a10a29 | 10815 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 10816 | |
39a10a29 GK |
10817 | (define_expand "bge" |
10818 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10819 | "" |
39a10a29 | 10820 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
10821 | |
10822 | (define_expand "bgt" | |
39a10a29 | 10823 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10824 | "" |
39a10a29 | 10825 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
10826 | |
10827 | (define_expand "ble" | |
39a10a29 | 10828 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10829 | "" |
39a10a29 | 10830 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 10831 | |
39a10a29 GK |
10832 | (define_expand "blt" |
10833 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10834 | "" |
39a10a29 | 10835 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 10836 | |
39a10a29 GK |
10837 | (define_expand "bgeu" |
10838 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10839 | "" |
39a10a29 | 10840 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 10841 | |
39a10a29 GK |
10842 | (define_expand "bgtu" |
10843 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10844 | "" |
39a10a29 | 10845 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 10846 | |
39a10a29 GK |
10847 | (define_expand "bleu" |
10848 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10849 | "" |
39a10a29 | 10850 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 10851 | |
39a10a29 GK |
10852 | (define_expand "bltu" |
10853 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10854 | "" |
39a10a29 | 10855 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 10856 | |
1c882ea4 | 10857 | (define_expand "bunordered" |
39a10a29 | 10858 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10859 | "" |
39a10a29 | 10860 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
10861 | |
10862 | (define_expand "bordered" | |
39a10a29 | 10863 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10864 | "" |
39a10a29 | 10865 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
10866 | |
10867 | (define_expand "buneq" | |
39a10a29 | 10868 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10869 | "" |
39a10a29 | 10870 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
10871 | |
10872 | (define_expand "bunge" | |
39a10a29 | 10873 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10874 | "" |
39a10a29 | 10875 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
10876 | |
10877 | (define_expand "bungt" | |
39a10a29 | 10878 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10879 | "" |
39a10a29 | 10880 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
10881 | |
10882 | (define_expand "bunle" | |
39a10a29 | 10883 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10884 | "" |
39a10a29 | 10885 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
10886 | |
10887 | (define_expand "bunlt" | |
39a10a29 | 10888 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10889 | "" |
39a10a29 | 10890 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
10891 | |
10892 | (define_expand "bltgt" | |
39a10a29 | 10893 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10894 | "" |
39a10a29 | 10895 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 10896 | |
1fd4e8c1 RK |
10897 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
10898 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
10899 | ;; with an scc insns. However, due to the order that combine see the | |
10900 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
10901 | ;; the cases we don't want to handle. | |
10902 | (define_expand "seq" | |
39a10a29 | 10903 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10904 | "" |
39a10a29 | 10905 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10906 | |
10907 | (define_expand "sne" | |
39a10a29 | 10908 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10909 | "" |
10910 | " | |
39a10a29 GK |
10911 | { |
10912 | if (! rs6000_compare_fp_p) | |
1fd4e8c1 RK |
10913 | FAIL; |
10914 | ||
39a10a29 GK |
10915 | rs6000_emit_sCOND (NE, operands[0]); |
10916 | DONE; | |
1fd4e8c1 RK |
10917 | }") |
10918 | ||
10919 | ;; A > 0 is best done using the portable sequence, so fail in that case. | |
10920 | (define_expand "sgt" | |
39a10a29 | 10921 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10922 | "" |
10923 | " | |
5638268e DE |
10924 | { |
10925 | if (! rs6000_compare_fp_p | |
10926 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
10927 | FAIL; |
10928 | ||
39a10a29 GK |
10929 | rs6000_emit_sCOND (GT, operands[0]); |
10930 | DONE; | |
1fd4e8c1 RK |
10931 | }") |
10932 | ||
10933 | ;; A < 0 is best done in the portable way for A an integer. | |
10934 | (define_expand "slt" | |
39a10a29 | 10935 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10936 | "" |
10937 | " | |
5638268e DE |
10938 | { |
10939 | if (! rs6000_compare_fp_p | |
10940 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
10941 | FAIL; |
10942 | ||
39a10a29 GK |
10943 | rs6000_emit_sCOND (LT, operands[0]); |
10944 | DONE; | |
1fd4e8c1 RK |
10945 | }") |
10946 | ||
5638268e | 10947 | ;; A >= 0 is best done the portable way for A an integer. |
1fd4e8c1 | 10948 | (define_expand "sge" |
39a10a29 | 10949 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10950 | "" |
5638268e DE |
10951 | " |
10952 | { | |
10953 | if (! rs6000_compare_fp_p | |
10954 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
10955 | FAIL; | |
10956 | ||
10957 | rs6000_emit_sCOND (GE, operands[0]); | |
10958 | DONE; | |
10959 | }") | |
1fd4e8c1 RK |
10960 | |
10961 | ;; A <= 0 is best done the portable way for A an integer. | |
10962 | (define_expand "sle" | |
39a10a29 | 10963 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10964 | "" |
10965 | " | |
5638268e DE |
10966 | { |
10967 | if (! rs6000_compare_fp_p | |
10968 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
10969 | FAIL; |
10970 | ||
39a10a29 GK |
10971 | rs6000_emit_sCOND (LE, operands[0]); |
10972 | DONE; | |
1fd4e8c1 RK |
10973 | }") |
10974 | ||
10975 | (define_expand "sgtu" | |
39a10a29 | 10976 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10977 | "" |
39a10a29 | 10978 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10979 | |
10980 | (define_expand "sltu" | |
39a10a29 | 10981 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10982 | "" |
39a10a29 | 10983 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10984 | |
10985 | (define_expand "sgeu" | |
39a10a29 | 10986 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10987 | "" |
39a10a29 | 10988 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10989 | |
10990 | (define_expand "sleu" | |
39a10a29 | 10991 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10992 | "" |
39a10a29 | 10993 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10994 | \f |
10995 | ;; Here are the actual compare insns. | |
acad7ed3 | 10996 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 10997 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 10998 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
10999 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
11000 | "" | |
7f340546 | 11001 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
b54cf83a | 11002 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 11003 | |
acad7ed3 | 11004 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
11005 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
11006 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
11007 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
11008 | "TARGET_POWERPC64" | |
11009 | "cmpd%I2 %0,%1,%2" | |
b54cf83a | 11010 | [(set_attr "type" "cmp")]) |
266eb58a | 11011 | |
f357808b RK |
11012 | ;; If we are comparing a register for equality with a large constant, |
11013 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
11014 | ;; register for the result of the XOR. | |
11015 | ||
11016 | (define_split | |
11017 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 11018 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 11019 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 11020 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
11021 | "find_single_use (operands[0], insn, 0) |
11022 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
11023 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
11024 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
11025 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
11026 | " | |
11027 | { | |
11028 | /* Get the constant we are comparing against, C, and see what it looks like | |
11029 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
11030 | with C to get the sign-extended value. */ | |
11031 | ||
5f59ecb7 | 11032 | HOST_WIDE_INT c = INTVAL (operands[2]); |
a65c591c | 11033 | HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; |
5f59ecb7 | 11034 | HOST_WIDE_INT xorv = c ^ sextc; |
f357808b | 11035 | |
89e9f3a8 MM |
11036 | operands[4] = GEN_INT (xorv); |
11037 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
11038 | }") |
11039 | ||
acad7ed3 | 11040 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 11041 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 11042 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 11043 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 11044 | "" |
e2c953b6 | 11045 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
b54cf83a | 11046 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 11047 | |
acad7ed3 | 11048 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
11049 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
11050 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 11051 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 11052 | "" |
e2c953b6 | 11053 | "cmpld%I2 %0,%1,%b2" |
b54cf83a | 11054 | [(set_attr "type" "cmp")]) |
266eb58a | 11055 | |
1fd4e8c1 RK |
11056 | ;; The following two insns don't exist as single insns, but if we provide |
11057 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
11058 | ;; of the required delay between a compare and branch. We generate code for | |
11059 | ;; them by splitting. | |
11060 | ||
11061 | (define_insn "" | |
11062 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11063 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11064 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 11065 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11066 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11067 | "" | |
baf97f86 RK |
11068 | "#" |
11069 | [(set_attr "length" "8")]) | |
7e69e155 | 11070 | |
1fd4e8c1 RK |
11071 | (define_insn "" |
11072 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11073 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11074 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 11075 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11076 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11077 | "" | |
baf97f86 RK |
11078 | "#" |
11079 | [(set_attr "length" "8")]) | |
7e69e155 | 11080 | |
1fd4e8c1 RK |
11081 | (define_split |
11082 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 11083 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11084 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 11085 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11086 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11087 | "" | |
11088 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
11089 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11090 | ||
11091 | (define_split | |
11092 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 11093 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11094 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 11095 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11096 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11097 | "" | |
11098 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
11099 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11100 | ||
acad7ed3 | 11101 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 11102 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11103 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
11104 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11105 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11106 | "fcmpu %0,%1,%2" |
11107 | [(set_attr "type" "fpcompare")]) | |
11108 | ||
acad7ed3 | 11109 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 11110 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11111 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
11112 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11113 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11114 | "fcmpu %0,%1,%2" |
11115 | [(set_attr "type" "fpcompare")]) | |
d6f99ca4 DE |
11116 | |
11117 | ;; Only need to compare second words if first words equal | |
11118 | (define_insn "*cmptf_internal1" | |
11119 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
11120 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
11121 | (match_operand:TF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
11122 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
11123 | && TARGET_LONG_DOUBLE_128" | |
2e7d5318 | 11124 | "fcmpu %0,%1,%2\;bne %0,$+4\;fcmpu %0,%L1,%L2" |
d6f99ca4 DE |
11125 | [(set_attr "type" "fpcompare") |
11126 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
11127 | \f |
11128 | ;; Now we have the scc insns. We can do some combinations because of the | |
11129 | ;; way the machine works. | |
11130 | ;; | |
11131 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
11132 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
11133 | ;; cases the insns below which don't use an intermediate CR field will | |
11134 | ;; be used instead. | |
1fd4e8c1 | 11135 | (define_insn "" |
cd2b37d9 | 11136 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11137 | (match_operator:SI 1 "scc_comparison_operator" |
11138 | [(match_operand 2 "cc_reg_operand" "y") | |
11139 | (const_int 0)]))] | |
11140 | "" | |
ca7f5001 | 11141 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" |
b54cf83a | 11142 | [(set_attr "type" "mfcr") |
309323c2 | 11143 | (set_attr "length" "12")]) |
1fd4e8c1 | 11144 | |
a3170dc6 AH |
11145 | ;; Same as above, but get the OV/ORDERED bit. |
11146 | (define_insn "move_from_CR_ov_bit" | |
11147 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
615158e2 | 11148 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))] |
a3170dc6 AH |
11149 | "TARGET_ISEL" |
11150 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1" | |
b54cf83a DE |
11151 | [(set_attr "type" "mfcr") |
11152 | (set_attr "length" "12")]) | |
a3170dc6 | 11153 | |
1fd4e8c1 | 11154 | (define_insn "" |
9ebbca7d GK |
11155 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
11156 | (match_operator:DI 1 "scc_comparison_operator" | |
11157 | [(match_operand 2 "cc_reg_operand" "y") | |
11158 | (const_int 0)]))] | |
11159 | "TARGET_POWERPC64" | |
11160 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" | |
b54cf83a | 11161 | [(set_attr "type" "mfcr") |
309323c2 | 11162 | (set_attr "length" "12")]) |
9ebbca7d GK |
11163 | |
11164 | (define_insn "" | |
11165 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 11166 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 11167 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
11168 | (const_int 0)]) |
11169 | (const_int 0))) | |
9ebbca7d | 11170 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11171 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
0ad91047 | 11172 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11173 | "@ |
11174 | %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1 | |
11175 | #" | |
b19003d8 | 11176 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11177 | (set_attr "length" "12,16")]) |
11178 | ||
11179 | (define_split | |
11180 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11181 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
11182 | [(match_operand 2 "cc_reg_operand" "") | |
11183 | (const_int 0)]) | |
11184 | (const_int 0))) | |
11185 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
11186 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
11187 | "! TARGET_POWERPC64 && reload_completed" | |
11188 | [(set (match_dup 3) | |
11189 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
11190 | (set (match_dup 0) | |
11191 | (compare:CC (match_dup 3) | |
11192 | (const_int 0)))] | |
11193 | "") | |
1fd4e8c1 RK |
11194 | |
11195 | (define_insn "" | |
cd2b37d9 | 11196 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11197 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
11198 | [(match_operand 2 "cc_reg_operand" "y") | |
11199 | (const_int 0)]) | |
11200 | (match_operand:SI 3 "const_int_operand" "n")))] | |
11201 | "" | |
11202 | "* | |
11203 | { | |
11204 | int is_bit = ccr_bit (operands[1], 1); | |
11205 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11206 | int count; | |
11207 | ||
11208 | if (is_bit >= put_bit) | |
11209 | count = is_bit - put_bit; | |
11210 | else | |
11211 | count = 32 - (put_bit - is_bit); | |
11212 | ||
89e9f3a8 MM |
11213 | operands[4] = GEN_INT (count); |
11214 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 11215 | |
ca7f5001 | 11216 | return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 | 11217 | }" |
b54cf83a | 11218 | [(set_attr "type" "mfcr") |
309323c2 | 11219 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
11220 | |
11221 | (define_insn "" | |
9ebbca7d | 11222 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11223 | (compare:CC |
11224 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 11225 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 11226 | (const_int 0)]) |
9ebbca7d | 11227 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 11228 | (const_int 0))) |
9ebbca7d | 11229 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11230 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
11231 | (match_dup 3)))] | |
ce71f754 | 11232 | "" |
1fd4e8c1 RK |
11233 | "* |
11234 | { | |
11235 | int is_bit = ccr_bit (operands[1], 1); | |
11236 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11237 | int count; | |
11238 | ||
9ebbca7d GK |
11239 | /* Force split for non-cc0 compare. */ |
11240 | if (which_alternative == 1) | |
11241 | return \"#\"; | |
11242 | ||
1fd4e8c1 RK |
11243 | if (is_bit >= put_bit) |
11244 | count = is_bit - put_bit; | |
11245 | else | |
11246 | count = 32 - (put_bit - is_bit); | |
11247 | ||
89e9f3a8 MM |
11248 | operands[5] = GEN_INT (count); |
11249 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 11250 | |
ca7f5001 | 11251 | return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 11252 | }" |
b19003d8 | 11253 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11254 | (set_attr "length" "12,16")]) |
11255 | ||
11256 | (define_split | |
11257 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11258 | (compare:CC | |
11259 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
11260 | [(match_operand 2 "cc_reg_operand" "") | |
11261 | (const_int 0)]) | |
11262 | (match_operand:SI 3 "const_int_operand" "")) | |
11263 | (const_int 0))) | |
11264 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
11265 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11266 | (match_dup 3)))] | |
ce71f754 | 11267 | "reload_completed" |
9ebbca7d GK |
11268 | [(set (match_dup 4) |
11269 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11270 | (match_dup 3))) | |
11271 | (set (match_dup 0) | |
11272 | (compare:CC (match_dup 4) | |
11273 | (const_int 0)))] | |
11274 | "") | |
1fd4e8c1 | 11275 | |
c5defebb RK |
11276 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
11277 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
11278 | ||
11279 | (define_peephole | |
cd2b37d9 | 11280 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
11281 | (match_operator:SI 1 "scc_comparison_operator" |
11282 | [(match_operand 2 "cc_reg_operand" "y") | |
11283 | (const_int 0)])) | |
cd2b37d9 | 11284 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
11285 | (match_operator:SI 4 "scc_comparison_operator" |
11286 | [(match_operand 5 "cc_reg_operand" "y") | |
11287 | (const_int 0)]))] | |
309323c2 DE |
11288 | "REGNO (operands[2]) != REGNO (operands[5])" |
11289 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" | |
b54cf83a | 11290 | [(set_attr "type" "mfcr") |
309323c2 | 11291 | (set_attr "length" "20")]) |
c5defebb | 11292 | |
9ebbca7d GK |
11293 | (define_peephole |
11294 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11295 | (match_operator:DI 1 "scc_comparison_operator" | |
11296 | [(match_operand 2 "cc_reg_operand" "y") | |
11297 | (const_int 0)])) | |
11298 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
11299 | (match_operator:DI 4 "scc_comparison_operator" | |
11300 | [(match_operand 5 "cc_reg_operand" "y") | |
11301 | (const_int 0)]))] | |
309323c2 DE |
11302 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" |
11303 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" | |
b54cf83a | 11304 | [(set_attr "type" "mfcr") |
309323c2 | 11305 | (set_attr "length" "20")]) |
9ebbca7d | 11306 | |
1fd4e8c1 RK |
11307 | ;; There are some scc insns that can be done directly, without a compare. |
11308 | ;; These are faster because they don't involve the communications between | |
11309 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
11310 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
11311 | ;; | |
11312 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
11313 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
11314 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
11315 | ;; cases where it is no more expensive than (neg (scc ..)). | |
11316 | ||
11317 | ;; Have reload force a constant into a register for the simple insns that | |
11318 | ;; otherwise won't accept constants. We do this because it is faster than | |
11319 | ;; the cmp/mfcr sequence we would otherwise generate. | |
11320 | ||
11321 | (define_insn "" | |
cd2b37d9 RK |
11322 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
11323 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 11324 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 11325 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
f9562f27 | 11326 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11327 | "@ |
ca7f5001 | 11328 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 11329 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
11330 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
11331 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
11332 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 11333 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 11334 | |
a260abc9 DE |
11335 | (define_insn "" |
11336 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
11337 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
11338 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
11339 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
11340 | "TARGET_POWERPC64" | |
11341 | "@ | |
11342 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11343 | subfic %3,%1,0\;adde %0,%3,%1 | |
11344 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11345 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11346 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
11347 | [(set_attr "length" "12,8,12,12,12")]) | |
11348 | ||
1fd4e8c1 | 11349 | (define_insn "" |
9ebbca7d | 11350 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11351 | (compare:CC |
9ebbca7d GK |
11352 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11353 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 11354 | (const_int 0))) |
9ebbca7d | 11355 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 11356 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11357 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
f9562f27 | 11358 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11359 | "@ |
ca7f5001 RK |
11360 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11361 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
11362 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
11363 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
11364 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11365 | # | |
11366 | # | |
11367 | # | |
11368 | # | |
11369 | #" | |
b19003d8 | 11370 | [(set_attr "type" "compare") |
9ebbca7d GK |
11371 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11372 | ||
11373 | (define_split | |
11374 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11375 | (compare:CC | |
11376 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11377 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11378 | (const_int 0))) | |
11379 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11380 | (eq:SI (match_dup 1) (match_dup 2))) | |
11381 | (clobber (match_scratch:SI 3 ""))] | |
11382 | "! TARGET_POWERPC64 && reload_completed" | |
11383 | [(parallel [(set (match_dup 0) | |
11384 | (eq:SI (match_dup 1) (match_dup 2))) | |
11385 | (clobber (match_dup 3))]) | |
11386 | (set (match_dup 4) | |
11387 | (compare:CC (match_dup 0) | |
11388 | (const_int 0)))] | |
11389 | "") | |
b19003d8 | 11390 | |
a260abc9 | 11391 | (define_insn "" |
9ebbca7d | 11392 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 11393 | (compare:CC |
9ebbca7d GK |
11394 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11395 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 11396 | (const_int 0))) |
9ebbca7d | 11397 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 11398 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11399 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
a260abc9 DE |
11400 | "TARGET_POWERPC64" |
11401 | "@ | |
11402 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11403 | subfic %3,%1,0\;adde. %0,%3,%1 | |
11404 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11405 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
11406 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
11407 | # | |
11408 | # | |
11409 | # | |
11410 | # | |
11411 | #" | |
a260abc9 | 11412 | [(set_attr "type" "compare") |
9ebbca7d GK |
11413 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11414 | ||
11415 | (define_split | |
11416 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11417 | (compare:CC | |
11418 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11419 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
11420 | (const_int 0))) | |
11421 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11422 | (eq:DI (match_dup 1) (match_dup 2))) | |
11423 | (clobber (match_scratch:DI 3 ""))] | |
11424 | "TARGET_POWERPC64 && reload_completed" | |
11425 | [(parallel [(set (match_dup 0) | |
11426 | (eq:DI (match_dup 1) (match_dup 2))) | |
11427 | (clobber (match_dup 3))]) | |
11428 | (set (match_dup 4) | |
11429 | (compare:CC (match_dup 0) | |
11430 | (const_int 0)))] | |
11431 | "") | |
a260abc9 | 11432 | |
b19003d8 RK |
11433 | ;; We have insns of the form shown by the first define_insn below. If |
11434 | ;; there is something inside the comparison operation, we must split it. | |
11435 | (define_split | |
11436 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
11437 | (plus:SI (match_operator 1 "comparison_operator" | |
11438 | [(match_operand:SI 2 "" "") | |
11439 | (match_operand:SI 3 | |
11440 | "reg_or_cint_operand" "")]) | |
11441 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
11442 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
11443 | "! gpc_reg_operand (operands[2], SImode)" | |
11444 | [(set (match_dup 5) (match_dup 2)) | |
11445 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
11446 | (match_dup 4)))]) | |
1fd4e8c1 RK |
11447 | |
11448 | (define_insn "" | |
5276df18 | 11449 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") |
cd2b37d9 | 11450 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11451 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
5276df18 | 11452 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] |
f9562f27 | 11453 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11454 | "@ |
5276df18 DE |
11455 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11456 | {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 | |
11457 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11458 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11459 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" | |
b19003d8 | 11460 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
11461 | |
11462 | (define_insn "" | |
9ebbca7d | 11463 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11464 | (compare:CC |
1fd4e8c1 | 11465 | (plus:SI |
9ebbca7d GK |
11466 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11467 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11468 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11469 | (const_int 0))) |
9ebbca7d | 11470 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 11471 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11472 | "@ |
ca7f5001 | 11473 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 11474 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
11475 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11476 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
11477 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11478 | # | |
11479 | # | |
11480 | # | |
11481 | # | |
11482 | #" | |
b19003d8 | 11483 | [(set_attr "type" "compare") |
9ebbca7d GK |
11484 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11485 | ||
11486 | (define_split | |
11487 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11488 | (compare:CC | |
11489 | (plus:SI | |
11490 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11491 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11492 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11493 | (const_int 0))) | |
11494 | (clobber (match_scratch:SI 4 ""))] | |
11495 | "! TARGET_POWERPC64 && reload_completed" | |
11496 | [(set (match_dup 4) | |
11497 | (plus:SI (eq:SI (match_dup 1) | |
11498 | (match_dup 2)) | |
11499 | (match_dup 3))) | |
11500 | (set (match_dup 0) | |
11501 | (compare:CC (match_dup 4) | |
11502 | (const_int 0)))] | |
11503 | "") | |
1fd4e8c1 RK |
11504 | |
11505 | (define_insn "" | |
0387639b | 11506 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11507 | (compare:CC |
1fd4e8c1 | 11508 | (plus:SI |
9ebbca7d GK |
11509 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11510 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11511 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11512 | (const_int 0))) |
0387639b DE |
11513 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") |
11514 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 11515 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11516 | "@ |
0387639b DE |
11517 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11518 | {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 | |
11519 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11520 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11521 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11522 | # |
11523 | # | |
11524 | # | |
11525 | # | |
11526 | #" | |
11527 | [(set_attr "type" "compare") | |
11528 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
11529 | ||
11530 | (define_split | |
0387639b | 11531 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11532 | (compare:CC |
11533 | (plus:SI | |
11534 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11535 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11536 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11537 | (const_int 0))) | |
11538 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
0387639b | 11539 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 11540 | "! TARGET_POWERPC64 && reload_completed" |
0387639b | 11541 | [(set (match_dup 0) |
9ebbca7d | 11542 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
0387639b | 11543 | (set (match_dup 4) |
9ebbca7d GK |
11544 | (compare:CC (match_dup 0) |
11545 | (const_int 0)))] | |
11546 | "") | |
11547 | ||
1fd4e8c1 | 11548 | (define_insn "" |
cd2b37d9 | 11549 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 11550 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11551 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
f9562f27 | 11552 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11553 | "@ |
ca7f5001 RK |
11554 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11555 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
11556 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11557 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11558 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11559 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 11560 | |
ea9be077 MM |
11561 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
11562 | ;; since it nabs/sr is just as fast. | |
463b558b | 11563 | (define_insn "*ne0" |
b4e95693 | 11564 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
11565 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
11566 | (const_int 31))) | |
11567 | (clobber (match_scratch:SI 2 "=&r"))] | |
a3170dc6 | 11568 | "! TARGET_POWER && ! TARGET_POWERPC64 && !TARGET_ISEL" |
ea9be077 MM |
11569 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
11570 | [(set_attr "length" "8")]) | |
11571 | ||
a260abc9 DE |
11572 | (define_insn "" |
11573 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11574 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11575 | (const_int 63))) | |
11576 | (clobber (match_scratch:DI 2 "=&r"))] | |
11577 | "TARGET_POWERPC64" | |
11578 | "addic %2,%1,-1\;subfe %0,%2,%1" | |
11579 | [(set_attr "length" "8")]) | |
11580 | ||
1fd4e8c1 RK |
11581 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
11582 | (define_insn "" | |
cd2b37d9 | 11583 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 11584 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 11585 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11586 | (const_int 31)) |
cd2b37d9 | 11587 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11588 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 11589 | "! TARGET_POWERPC64" |
ca7f5001 | 11590 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 11591 | [(set_attr "length" "8")]) |
1fd4e8c1 | 11592 | |
a260abc9 DE |
11593 | (define_insn "" |
11594 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11595 | (plus:DI (lshiftrt:DI | |
11596 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11597 | (const_int 63)) | |
11598 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11599 | (clobber (match_scratch:DI 3 "=&r"))] | |
11600 | "TARGET_POWERPC64" | |
11601 | "addic %3,%1,-1\;addze %0,%2" | |
11602 | [(set_attr "length" "8")]) | |
11603 | ||
1fd4e8c1 | 11604 | (define_insn "" |
9ebbca7d | 11605 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11606 | (compare:CC |
11607 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11608 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11609 | (const_int 31)) |
9ebbca7d | 11610 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11611 | (const_int 0))) |
889b90a1 GK |
11612 | (clobber (match_scratch:SI 3 "=&r,&r")) |
11613 | (clobber (match_scratch:SI 4 "=X,&r"))] | |
f9562f27 | 11614 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11615 | "@ |
11616 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
11617 | #" | |
b19003d8 | 11618 | [(set_attr "type" "compare") |
9ebbca7d GK |
11619 | (set_attr "length" "8,12")]) |
11620 | ||
11621 | (define_split | |
11622 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11623 | (compare:CC | |
11624 | (plus:SI (lshiftrt:SI | |
11625 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11626 | (const_int 31)) | |
11627 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11628 | (const_int 0))) | |
889b90a1 GK |
11629 | (clobber (match_scratch:SI 3 "")) |
11630 | (clobber (match_scratch:SI 4 ""))] | |
9ebbca7d | 11631 | "! TARGET_POWERPC64 && reload_completed" |
889b90a1 | 11632 | [(parallel [(set (match_dup 3) |
ce71f754 AM |
11633 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) |
11634 | (const_int 31)) | |
11635 | (match_dup 2))) | |
889b90a1 | 11636 | (clobber (match_dup 4))]) |
9ebbca7d GK |
11637 | (set (match_dup 0) |
11638 | (compare:CC (match_dup 3) | |
11639 | (const_int 0)))] | |
11640 | "") | |
1fd4e8c1 | 11641 | |
a260abc9 | 11642 | (define_insn "" |
9ebbca7d | 11643 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11644 | (compare:CC |
11645 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11646 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11647 | (const_int 63)) |
9ebbca7d | 11648 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11649 | (const_int 0))) |
9ebbca7d | 11650 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 11651 | "TARGET_POWERPC64" |
9ebbca7d GK |
11652 | "@ |
11653 | addic %3,%1,-1\;addze. %3,%2 | |
11654 | #" | |
a260abc9 | 11655 | [(set_attr "type" "compare") |
9ebbca7d GK |
11656 | (set_attr "length" "8,12")]) |
11657 | ||
11658 | (define_split | |
11659 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11660 | (compare:CC | |
11661 | (plus:DI (lshiftrt:DI | |
11662 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11663 | (const_int 63)) | |
11664 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11665 | (const_int 0))) | |
11666 | (clobber (match_scratch:DI 3 ""))] | |
11667 | "TARGET_POWERPC64 && reload_completed" | |
11668 | [(set (match_dup 3) | |
11669 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
11670 | (const_int 63)) | |
11671 | (match_dup 2))) | |
11672 | (set (match_dup 0) | |
11673 | (compare:CC (match_dup 3) | |
11674 | (const_int 0)))] | |
11675 | "") | |
a260abc9 | 11676 | |
1fd4e8c1 | 11677 | (define_insn "" |
9ebbca7d | 11678 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11679 | (compare:CC |
11680 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11681 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11682 | (const_int 31)) |
9ebbca7d | 11683 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11684 | (const_int 0))) |
9ebbca7d | 11685 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11686 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
11687 | (match_dup 2))) | |
9ebbca7d | 11688 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 11689 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11690 | "@ |
11691 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
11692 | #" | |
b19003d8 | 11693 | [(set_attr "type" "compare") |
9ebbca7d GK |
11694 | (set_attr "length" "8,12")]) |
11695 | ||
11696 | (define_split | |
11697 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11698 | (compare:CC | |
11699 | (plus:SI (lshiftrt:SI | |
11700 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11701 | (const_int 31)) | |
11702 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11703 | (const_int 0))) | |
11704 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11705 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11706 | (match_dup 2))) | |
11707 | (clobber (match_scratch:SI 3 ""))] | |
11708 | "! TARGET_POWERPC64 && reload_completed" | |
11709 | [(parallel [(set (match_dup 0) | |
11710 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11711 | (match_dup 2))) | |
11712 | (clobber (match_dup 3))]) | |
11713 | (set (match_dup 4) | |
11714 | (compare:CC (match_dup 0) | |
11715 | (const_int 0)))] | |
11716 | "") | |
1fd4e8c1 | 11717 | |
a260abc9 | 11718 | (define_insn "" |
9ebbca7d | 11719 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11720 | (compare:CC |
11721 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11722 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11723 | (const_int 63)) |
9ebbca7d | 11724 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11725 | (const_int 0))) |
9ebbca7d | 11726 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
11727 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
11728 | (match_dup 2))) | |
9ebbca7d | 11729 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 11730 | "TARGET_POWERPC64" |
9ebbca7d GK |
11731 | "@ |
11732 | addic %3,%1,-1\;addze. %0,%2 | |
11733 | #" | |
a260abc9 | 11734 | [(set_attr "type" "compare") |
9ebbca7d GK |
11735 | (set_attr "length" "8,12")]) |
11736 | ||
11737 | (define_split | |
11738 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11739 | (compare:CC | |
11740 | (plus:DI (lshiftrt:DI | |
11741 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11742 | (const_int 63)) | |
11743 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11744 | (const_int 0))) | |
11745 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11746 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11747 | (match_dup 2))) | |
11748 | (clobber (match_scratch:DI 3 ""))] | |
11749 | "TARGET_POWERPC64 && reload_completed" | |
11750 | [(parallel [(set (match_dup 0) | |
11751 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11752 | (match_dup 2))) | |
11753 | (clobber (match_dup 3))]) | |
11754 | (set (match_dup 4) | |
11755 | (compare:CC (match_dup 0) | |
11756 | (const_int 0)))] | |
11757 | "") | |
a260abc9 | 11758 | |
1fd4e8c1 | 11759 | (define_insn "" |
cd2b37d9 RK |
11760 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11761 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
11762 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
11763 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 11764 | "TARGET_POWER" |
1fd4e8c1 | 11765 | "@ |
ca7f5001 | 11766 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 11767 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11768 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11769 | |
11770 | (define_insn "" | |
9ebbca7d | 11771 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11772 | (compare:CC |
9ebbca7d GK |
11773 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11774 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 11775 | (const_int 0))) |
9ebbca7d | 11776 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11777 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11778 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 11779 | "TARGET_POWER" |
1fd4e8c1 | 11780 | "@ |
ca7f5001 | 11781 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
11782 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
11783 | # | |
11784 | #" | |
11785 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
11786 | (set_attr "length" "12,12,16,16")]) | |
11787 | ||
11788 | (define_split | |
11789 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11790 | (compare:CC | |
11791 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11792 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11793 | (const_int 0))) | |
11794 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11795 | (le:SI (match_dup 1) (match_dup 2))) | |
11796 | (clobber (match_scratch:SI 3 ""))] | |
11797 | "TARGET_POWER && reload_completed" | |
11798 | [(parallel [(set (match_dup 0) | |
11799 | (le:SI (match_dup 1) (match_dup 2))) | |
11800 | (clobber (match_dup 3))]) | |
11801 | (set (match_dup 4) | |
11802 | (compare:CC (match_dup 0) | |
11803 | (const_int 0)))] | |
11804 | "") | |
1fd4e8c1 RK |
11805 | |
11806 | (define_insn "" | |
097657c3 | 11807 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 11808 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 11809 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
097657c3 | 11810 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
ca7f5001 | 11811 | "TARGET_POWER" |
1fd4e8c1 | 11812 | "@ |
097657c3 AM |
11813 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11814 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" | |
b19003d8 | 11815 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11816 | |
11817 | (define_insn "" | |
9ebbca7d | 11818 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11819 | (compare:CC |
9ebbca7d GK |
11820 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11821 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
11822 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11823 | (const_int 0))) |
9ebbca7d | 11824 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 11825 | "TARGET_POWER" |
1fd4e8c1 | 11826 | "@ |
ca7f5001 | 11827 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
11828 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
11829 | # | |
11830 | #" | |
b19003d8 | 11831 | [(set_attr "type" "compare") |
9ebbca7d GK |
11832 | (set_attr "length" "12,12,16,16")]) |
11833 | ||
11834 | (define_split | |
11835 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11836 | (compare:CC | |
11837 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11838 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11839 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11840 | (const_int 0))) | |
11841 | (clobber (match_scratch:SI 4 ""))] | |
11842 | "TARGET_POWER && reload_completed" | |
11843 | [(set (match_dup 4) | |
11844 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 11845 | (match_dup 3))) |
9ebbca7d GK |
11846 | (set (match_dup 0) |
11847 | (compare:CC (match_dup 4) | |
11848 | (const_int 0)))] | |
11849 | "") | |
1fd4e8c1 RK |
11850 | |
11851 | (define_insn "" | |
097657c3 | 11852 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11853 | (compare:CC |
9ebbca7d GK |
11854 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11855 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
11856 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11857 | (const_int 0))) |
097657c3 AM |
11858 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
11859 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 11860 | "TARGET_POWER" |
1fd4e8c1 | 11861 | "@ |
097657c3 AM |
11862 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11863 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11864 | # |
11865 | #" | |
b19003d8 | 11866 | [(set_attr "type" "compare") |
9ebbca7d GK |
11867 | (set_attr "length" "12,12,16,16")]) |
11868 | ||
11869 | (define_split | |
097657c3 | 11870 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11871 | (compare:CC |
11872 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11873 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11874 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11875 | (const_int 0))) | |
11876 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 11877 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 11878 | "TARGET_POWER && reload_completed" |
097657c3 | 11879 | [(set (match_dup 0) |
9ebbca7d | 11880 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 11881 | (set (match_dup 4) |
9ebbca7d GK |
11882 | (compare:CC (match_dup 0) |
11883 | (const_int 0)))] | |
11884 | "") | |
1fd4e8c1 RK |
11885 | |
11886 | (define_insn "" | |
cd2b37d9 RK |
11887 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11888 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11889 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 11890 | "TARGET_POWER" |
1fd4e8c1 | 11891 | "@ |
ca7f5001 RK |
11892 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11893 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 11894 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11895 | |
11896 | (define_insn "" | |
cd2b37d9 RK |
11897 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11898 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11899 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 11900 | "! TARGET_POWERPC64" |
ca7f5001 | 11901 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 11902 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11903 | |
f9562f27 DE |
11904 | (define_insn "" |
11905 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11906 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
11907 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
11908 | "TARGET_POWERPC64" | |
11909 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" | |
11910 | [(set_attr "length" "12")]) | |
11911 | ||
11912 | (define_insn "" | |
9ebbca7d | 11913 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 11914 | (compare:CC |
9ebbca7d GK |
11915 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
11916 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 11917 | (const_int 0))) |
9ebbca7d | 11918 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
11919 | (leu:DI (match_dup 1) (match_dup 2)))] |
11920 | "TARGET_POWERPC64" | |
9ebbca7d GK |
11921 | "@ |
11922 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
11923 | #" | |
f9562f27 | 11924 | [(set_attr "type" "compare") |
9ebbca7d GK |
11925 | (set_attr "length" "12,16")]) |
11926 | ||
11927 | (define_split | |
11928 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11929 | (compare:CC | |
11930 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11931 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
11932 | (const_int 0))) | |
11933 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11934 | (leu:DI (match_dup 1) (match_dup 2)))] | |
11935 | "TARGET_POWERPC64 && reload_completed" | |
11936 | [(set (match_dup 0) | |
11937 | (leu:DI (match_dup 1) (match_dup 2))) | |
11938 | (set (match_dup 3) | |
11939 | (compare:CC (match_dup 0) | |
11940 | (const_int 0)))] | |
11941 | "") | |
f9562f27 | 11942 | |
1fd4e8c1 | 11943 | (define_insn "" |
9ebbca7d | 11944 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11945 | (compare:CC |
9ebbca7d GK |
11946 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11947 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11948 | (const_int 0))) |
9ebbca7d | 11949 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11950 | (leu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11951 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11952 | "@ |
11953 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
11954 | #" | |
b19003d8 | 11955 | [(set_attr "type" "compare") |
9ebbca7d GK |
11956 | (set_attr "length" "12,16")]) |
11957 | ||
11958 | (define_split | |
11959 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11960 | (compare:CC | |
11961 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11962 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11963 | (const_int 0))) | |
11964 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11965 | (leu:SI (match_dup 1) (match_dup 2)))] | |
11966 | "! TARGET_POWERPC64 && reload_completed" | |
11967 | [(set (match_dup 0) | |
11968 | (leu:SI (match_dup 1) (match_dup 2))) | |
11969 | (set (match_dup 3) | |
11970 | (compare:CC (match_dup 0) | |
11971 | (const_int 0)))] | |
11972 | "") | |
1fd4e8c1 | 11973 | |
f9562f27 | 11974 | (define_insn "" |
9ebbca7d | 11975 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 11976 | (compare:CC |
9ebbca7d GK |
11977 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
11978 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 11979 | (const_int 0))) |
9ebbca7d | 11980 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
11981 | (leu:DI (match_dup 1) (match_dup 2)))] |
11982 | "TARGET_POWERPC64" | |
9ebbca7d GK |
11983 | "@ |
11984 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
11985 | #" | |
f9562f27 | 11986 | [(set_attr "type" "compare") |
9ebbca7d | 11987 | (set_attr "length" "12,16")]) |
f9562f27 | 11988 | |
1fd4e8c1 | 11989 | (define_insn "" |
80103f96 | 11990 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 11991 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11992 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
80103f96 | 11993 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
f9562f27 | 11994 | "! TARGET_POWERPC64" |
80103f96 | 11995 | "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 11996 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
11997 | |
11998 | (define_insn "" | |
9ebbca7d | 11999 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12000 | (compare:CC |
9ebbca7d GK |
12001 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12002 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12003 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12004 | (const_int 0))) |
9ebbca7d | 12005 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 12006 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12007 | "@ |
12008 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
12009 | #" | |
b19003d8 | 12010 | [(set_attr "type" "compare") |
9ebbca7d GK |
12011 | (set_attr "length" "8,12")]) |
12012 | ||
12013 | (define_split | |
12014 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12015 | (compare:CC | |
12016 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12017 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12018 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12019 | (const_int 0))) | |
12020 | (clobber (match_scratch:SI 4 ""))] | |
12021 | "! TARGET_POWERPC64 && reload_completed" | |
12022 | [(set (match_dup 4) | |
12023 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
12024 | (match_dup 3))) | |
12025 | (set (match_dup 0) | |
12026 | (compare:CC (match_dup 4) | |
12027 | (const_int 0)))] | |
12028 | "") | |
1fd4e8c1 RK |
12029 | |
12030 | (define_insn "" | |
097657c3 | 12031 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12032 | (compare:CC |
9ebbca7d GK |
12033 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12034 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12035 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12036 | (const_int 0))) |
097657c3 AM |
12037 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12038 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 12039 | "! TARGET_POWERPC64" |
9ebbca7d | 12040 | "@ |
097657c3 | 12041 | {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 |
9ebbca7d | 12042 | #" |
b19003d8 | 12043 | [(set_attr "type" "compare") |
9ebbca7d GK |
12044 | (set_attr "length" "8,12")]) |
12045 | ||
12046 | (define_split | |
097657c3 | 12047 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12048 | (compare:CC |
12049 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12050 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12051 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12052 | (const_int 0))) | |
12053 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12054 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12055 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 12056 | [(set (match_dup 0) |
9ebbca7d | 12057 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12058 | (set (match_dup 4) |
9ebbca7d GK |
12059 | (compare:CC (match_dup 0) |
12060 | (const_int 0)))] | |
12061 | "") | |
1fd4e8c1 RK |
12062 | |
12063 | (define_insn "" | |
cd2b37d9 RK |
12064 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12065 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12066 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 12067 | "! TARGET_POWERPC64" |
ca7f5001 | 12068 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 12069 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12070 | |
12071 | (define_insn "" | |
097657c3 | 12072 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
1fd4e8c1 | 12073 | (and:SI (neg:SI |
cd2b37d9 | 12074 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12075 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
097657c3 | 12076 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
f9562f27 | 12077 | "! TARGET_POWERPC64" |
097657c3 | 12078 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" |
b19003d8 | 12079 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12080 | |
12081 | (define_insn "" | |
9ebbca7d | 12082 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12083 | (compare:CC |
12084 | (and:SI (neg:SI | |
9ebbca7d GK |
12085 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12086 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12087 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12088 | (const_int 0))) |
9ebbca7d | 12089 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 12090 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12091 | "@ |
12092 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
12093 | #" | |
12094 | [(set_attr "type" "compare") | |
12095 | (set_attr "length" "12,16")]) | |
12096 | ||
12097 | (define_split | |
12098 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12099 | (compare:CC | |
12100 | (and:SI (neg:SI | |
12101 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12102 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12103 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12104 | (const_int 0))) | |
12105 | (clobber (match_scratch:SI 4 ""))] | |
12106 | "! TARGET_POWERPC64 && reload_completed" | |
12107 | [(set (match_dup 4) | |
097657c3 AM |
12108 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) |
12109 | (match_dup 3))) | |
9ebbca7d GK |
12110 | (set (match_dup 0) |
12111 | (compare:CC (match_dup 4) | |
12112 | (const_int 0)))] | |
12113 | "") | |
1fd4e8c1 RK |
12114 | |
12115 | (define_insn "" | |
097657c3 | 12116 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12117 | (compare:CC |
12118 | (and:SI (neg:SI | |
9ebbca7d GK |
12119 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12120 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12121 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12122 | (const_int 0))) |
097657c3 AM |
12123 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12124 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
f9562f27 | 12125 | "! TARGET_POWERPC64" |
9ebbca7d | 12126 | "@ |
097657c3 | 12127 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
9ebbca7d | 12128 | #" |
b19003d8 | 12129 | [(set_attr "type" "compare") |
9ebbca7d GK |
12130 | (set_attr "length" "12,16")]) |
12131 | ||
12132 | (define_split | |
097657c3 | 12133 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12134 | (compare:CC |
12135 | (and:SI (neg:SI | |
12136 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12137 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12138 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12139 | (const_int 0))) | |
12140 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12141 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
9ebbca7d | 12142 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 AM |
12143 | [(set (match_dup 0) |
12144 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) | |
12145 | (match_dup 3))) | |
12146 | (set (match_dup 4) | |
9ebbca7d GK |
12147 | (compare:CC (match_dup 0) |
12148 | (const_int 0)))] | |
12149 | "") | |
1fd4e8c1 RK |
12150 | |
12151 | (define_insn "" | |
cd2b37d9 RK |
12152 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12153 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12154 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 12155 | "TARGET_POWER" |
7f340546 | 12156 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12157 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12158 | |
12159 | (define_insn "" | |
9ebbca7d | 12160 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12161 | (compare:CC |
9ebbca7d GK |
12162 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12163 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12164 | (const_int 0))) |
9ebbca7d | 12165 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12166 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12167 | "TARGET_POWER" |
9ebbca7d GK |
12168 | "@ |
12169 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12170 | #" | |
29ae5b89 | 12171 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12172 | (set_attr "length" "12,16")]) |
12173 | ||
12174 | (define_split | |
12175 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12176 | (compare:CC | |
12177 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12178 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12179 | (const_int 0))) | |
12180 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12181 | (lt:SI (match_dup 1) (match_dup 2)))] | |
12182 | "TARGET_POWER && reload_completed" | |
12183 | [(set (match_dup 0) | |
12184 | (lt:SI (match_dup 1) (match_dup 2))) | |
12185 | (set (match_dup 3) | |
12186 | (compare:CC (match_dup 0) | |
12187 | (const_int 0)))] | |
12188 | "") | |
1fd4e8c1 RK |
12189 | |
12190 | (define_insn "" | |
097657c3 | 12191 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12192 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12193 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12194 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12195 | "TARGET_POWER" |
097657c3 | 12196 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 12197 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12198 | |
12199 | (define_insn "" | |
9ebbca7d | 12200 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12201 | (compare:CC |
9ebbca7d GK |
12202 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12203 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12204 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12205 | (const_int 0))) |
9ebbca7d | 12206 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12207 | "TARGET_POWER" |
9ebbca7d GK |
12208 | "@ |
12209 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12210 | #" | |
b19003d8 | 12211 | [(set_attr "type" "compare") |
9ebbca7d GK |
12212 | (set_attr "length" "12,16")]) |
12213 | ||
12214 | (define_split | |
12215 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12216 | (compare:CC | |
12217 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12218 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12219 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12220 | (const_int 0))) | |
12221 | (clobber (match_scratch:SI 4 ""))] | |
12222 | "TARGET_POWER && reload_completed" | |
12223 | [(set (match_dup 4) | |
12224 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12225 | (match_dup 3))) |
9ebbca7d GK |
12226 | (set (match_dup 0) |
12227 | (compare:CC (match_dup 4) | |
12228 | (const_int 0)))] | |
12229 | "") | |
1fd4e8c1 RK |
12230 | |
12231 | (define_insn "" | |
097657c3 | 12232 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12233 | (compare:CC |
9ebbca7d GK |
12234 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12235 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12236 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12237 | (const_int 0))) |
097657c3 AM |
12238 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12239 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12240 | "TARGET_POWER" |
9ebbca7d | 12241 | "@ |
097657c3 | 12242 | doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 12243 | #" |
b19003d8 | 12244 | [(set_attr "type" "compare") |
9ebbca7d GK |
12245 | (set_attr "length" "12,16")]) |
12246 | ||
12247 | (define_split | |
097657c3 | 12248 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12249 | (compare:CC |
12250 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12251 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12252 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12253 | (const_int 0))) | |
12254 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12255 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12256 | "TARGET_POWER && reload_completed" |
097657c3 | 12257 | [(set (match_dup 0) |
9ebbca7d | 12258 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12259 | (set (match_dup 4) |
9ebbca7d GK |
12260 | (compare:CC (match_dup 0) |
12261 | (const_int 0)))] | |
12262 | "") | |
1fd4e8c1 RK |
12263 | |
12264 | (define_insn "" | |
cd2b37d9 RK |
12265 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12266 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12267 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12268 | "TARGET_POWER" |
12269 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12270 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12271 | |
12272 | (define_insn "" | |
cd2b37d9 RK |
12273 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12274 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12275 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 12276 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12277 | "@ |
ca7f5001 RK |
12278 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
12279 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 12280 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12281 | |
12282 | (define_insn "" | |
9ebbca7d | 12283 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12284 | (compare:CC |
9ebbca7d GK |
12285 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12286 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12287 | (const_int 0))) |
9ebbca7d | 12288 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12289 | (ltu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 12290 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12291 | "@ |
ca7f5001 | 12292 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
12293 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
12294 | # | |
12295 | #" | |
b19003d8 | 12296 | [(set_attr "type" "compare") |
9ebbca7d GK |
12297 | (set_attr "length" "12,12,16,16")]) |
12298 | ||
12299 | (define_split | |
12300 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12301 | (compare:CC | |
12302 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12303 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12304 | (const_int 0))) | |
12305 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12306 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
12307 | "! TARGET_POWERPC64 && reload_completed" | |
12308 | [(set (match_dup 0) | |
12309 | (ltu:SI (match_dup 1) (match_dup 2))) | |
12310 | (set (match_dup 3) | |
12311 | (compare:CC (match_dup 0) | |
12312 | (const_int 0)))] | |
12313 | "") | |
1fd4e8c1 RK |
12314 | |
12315 | (define_insn "" | |
80103f96 | 12316 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
19378cf8 MM |
12317 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12318 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
80103f96 | 12319 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))] |
f9562f27 | 12320 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12321 | "@ |
80103f96 FS |
12322 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3 |
12323 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" | |
b19003d8 | 12324 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12325 | |
12326 | (define_insn "" | |
9ebbca7d | 12327 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12328 | (compare:CC |
9ebbca7d GK |
12329 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12330 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12331 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12332 | (const_int 0))) |
9ebbca7d | 12333 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12334 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12335 | "@ |
ca7f5001 | 12336 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
9ebbca7d GK |
12337 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
12338 | # | |
12339 | #" | |
b19003d8 | 12340 | [(set_attr "type" "compare") |
9ebbca7d GK |
12341 | (set_attr "length" "12,12,16,16")]) |
12342 | ||
12343 | (define_split | |
12344 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12345 | (compare:CC | |
12346 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12347 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12348 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12349 | (const_int 0))) | |
12350 | (clobber (match_scratch:SI 4 ""))] | |
12351 | "! TARGET_POWERPC64 && reload_completed" | |
12352 | [(set (match_dup 4) | |
12353 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12354 | (match_dup 3))) |
9ebbca7d GK |
12355 | (set (match_dup 0) |
12356 | (compare:CC (match_dup 4) | |
12357 | (const_int 0)))] | |
12358 | "") | |
1fd4e8c1 RK |
12359 | |
12360 | (define_insn "" | |
097657c3 | 12361 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12362 | (compare:CC |
9ebbca7d GK |
12363 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12364 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12365 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12366 | (const_int 0))) |
097657c3 AM |
12367 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12368 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 12369 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12370 | "@ |
097657c3 AM |
12371 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 |
12372 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 | |
9ebbca7d GK |
12373 | # |
12374 | #" | |
b19003d8 | 12375 | [(set_attr "type" "compare") |
9ebbca7d GK |
12376 | (set_attr "length" "12,12,16,16")]) |
12377 | ||
12378 | (define_split | |
097657c3 | 12379 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12380 | (compare:CC |
12381 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12382 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12383 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12384 | (const_int 0))) | |
12385 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12386 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12387 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 12388 | [(set (match_dup 0) |
9ebbca7d | 12389 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12390 | (set (match_dup 4) |
9ebbca7d GK |
12391 | (compare:CC (match_dup 0) |
12392 | (const_int 0)))] | |
12393 | "") | |
1fd4e8c1 RK |
12394 | |
12395 | (define_insn "" | |
cd2b37d9 RK |
12396 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12397 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12398 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
f9562f27 | 12399 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12400 | "@ |
ca7f5001 RK |
12401 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
12402 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12403 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12404 | |
12405 | (define_insn "" | |
cd2b37d9 RK |
12406 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12407 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
12408 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
12409 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
12410 | "TARGET_POWER" |
12411 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 12412 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12413 | |
9ebbca7d GK |
12414 | (define_insn "" |
12415 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 12416 | (compare:CC |
9ebbca7d GK |
12417 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12418 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12419 | (const_int 0))) |
9ebbca7d | 12420 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12421 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12422 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 12423 | "TARGET_POWER" |
9ebbca7d GK |
12424 | "@ |
12425 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
12426 | #" | |
12427 | [(set_attr "type" "compare") | |
12428 | (set_attr "length" "12,16")]) | |
12429 | ||
12430 | (define_split | |
12431 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12432 | (compare:CC | |
12433 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12434 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12435 | (const_int 0))) | |
12436 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12437 | (ge:SI (match_dup 1) (match_dup 2))) | |
12438 | (clobber (match_scratch:SI 3 ""))] | |
12439 | "TARGET_POWER && reload_completed" | |
12440 | [(parallel [(set (match_dup 0) | |
097657c3 AM |
12441 | (ge:SI (match_dup 1) (match_dup 2))) |
12442 | (clobber (match_dup 3))]) | |
9ebbca7d GK |
12443 | (set (match_dup 4) |
12444 | (compare:CC (match_dup 0) | |
12445 | (const_int 0)))] | |
12446 | "") | |
12447 | ||
1fd4e8c1 | 12448 | (define_insn "" |
097657c3 | 12449 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12450 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12451 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12452 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12453 | "TARGET_POWER" |
097657c3 | 12454 | "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" |
b19003d8 | 12455 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12456 | |
12457 | (define_insn "" | |
9ebbca7d | 12458 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12459 | (compare:CC |
9ebbca7d GK |
12460 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12461 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12462 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12463 | (const_int 0))) |
9ebbca7d | 12464 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12465 | "TARGET_POWER" |
9ebbca7d GK |
12466 | "@ |
12467 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
12468 | #" | |
b19003d8 | 12469 | [(set_attr "type" "compare") |
9ebbca7d GK |
12470 | (set_attr "length" "12,16")]) |
12471 | ||
12472 | (define_split | |
12473 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12474 | (compare:CC | |
12475 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12476 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12477 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12478 | (const_int 0))) | |
12479 | (clobber (match_scratch:SI 4 ""))] | |
12480 | "TARGET_POWER && reload_completed" | |
12481 | [(set (match_dup 4) | |
12482 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12483 | (match_dup 3))) |
9ebbca7d GK |
12484 | (set (match_dup 0) |
12485 | (compare:CC (match_dup 4) | |
12486 | (const_int 0)))] | |
12487 | "") | |
1fd4e8c1 RK |
12488 | |
12489 | (define_insn "" | |
097657c3 | 12490 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12491 | (compare:CC |
9ebbca7d GK |
12492 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12493 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12494 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12495 | (const_int 0))) |
097657c3 AM |
12496 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12497 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12498 | "TARGET_POWER" |
9ebbca7d | 12499 | "@ |
097657c3 | 12500 | doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
9ebbca7d | 12501 | #" |
b19003d8 | 12502 | [(set_attr "type" "compare") |
9ebbca7d GK |
12503 | (set_attr "length" "12,16")]) |
12504 | ||
12505 | (define_split | |
097657c3 | 12506 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12507 | (compare:CC |
12508 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12509 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12510 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12511 | (const_int 0))) | |
12512 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12513 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12514 | "TARGET_POWER && reload_completed" |
097657c3 | 12515 | [(set (match_dup 0) |
9ebbca7d | 12516 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12517 | (set (match_dup 4) |
9ebbca7d GK |
12518 | (compare:CC (match_dup 0) |
12519 | (const_int 0)))] | |
12520 | "") | |
1fd4e8c1 RK |
12521 | |
12522 | (define_insn "" | |
cd2b37d9 RK |
12523 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12524 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12525 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12526 | "TARGET_POWER" |
12527 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12528 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12529 | |
1fd4e8c1 | 12530 | (define_insn "" |
cd2b37d9 RK |
12531 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12532 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12533 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 12534 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12535 | "@ |
ca7f5001 RK |
12536 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
12537 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 12538 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12539 | |
f9562f27 DE |
12540 | (define_insn "" |
12541 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12542 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12543 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
12544 | "TARGET_POWERPC64" | |
12545 | "@ | |
12546 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
12547 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
12548 | [(set_attr "length" "12")]) | |
12549 | ||
1fd4e8c1 | 12550 | (define_insn "" |
9ebbca7d | 12551 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12552 | (compare:CC |
9ebbca7d GK |
12553 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12554 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12555 | (const_int 0))) |
9ebbca7d | 12556 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12557 | (geu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 12558 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12559 | "@ |
ca7f5001 | 12560 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
12561 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
12562 | # | |
12563 | #" | |
b19003d8 | 12564 | [(set_attr "type" "compare") |
9ebbca7d GK |
12565 | (set_attr "length" "12,12,16,16")]) |
12566 | ||
12567 | (define_split | |
12568 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12569 | (compare:CC | |
12570 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12571 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12572 | (const_int 0))) | |
12573 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12574 | (geu:SI (match_dup 1) (match_dup 2)))] | |
12575 | "! TARGET_POWERPC64 && reload_completed" | |
12576 | [(set (match_dup 0) | |
12577 | (geu:SI (match_dup 1) (match_dup 2))) | |
12578 | (set (match_dup 3) | |
12579 | (compare:CC (match_dup 0) | |
12580 | (const_int 0)))] | |
12581 | "") | |
1fd4e8c1 | 12582 | |
f9562f27 | 12583 | (define_insn "" |
9ebbca7d | 12584 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12585 | (compare:CC |
9ebbca7d GK |
12586 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12587 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 12588 | (const_int 0))) |
9ebbca7d | 12589 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 DE |
12590 | (geu:DI (match_dup 1) (match_dup 2)))] |
12591 | "TARGET_POWERPC64" | |
12592 | "@ | |
12593 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
12594 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
12595 | # | |
12596 | #" | |
f9562f27 | 12597 | [(set_attr "type" "compare") |
9ebbca7d GK |
12598 | (set_attr "length" "12,12,16,16")]) |
12599 | ||
12600 | (define_split | |
12601 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12602 | (compare:CC | |
12603 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12604 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
12605 | (const_int 0))) | |
12606 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12607 | (geu:DI (match_dup 1) (match_dup 2)))] | |
12608 | "TARGET_POWERPC64 && reload_completed" | |
12609 | [(set (match_dup 0) | |
12610 | (geu:DI (match_dup 1) (match_dup 2))) | |
12611 | (set (match_dup 3) | |
12612 | (compare:CC (match_dup 0) | |
12613 | (const_int 0)))] | |
12614 | "") | |
f9562f27 | 12615 | |
1fd4e8c1 | 12616 | (define_insn "" |
80103f96 | 12617 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 12618 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12619 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
80103f96 | 12620 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
f9562f27 | 12621 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12622 | "@ |
80103f96 FS |
12623 | {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 |
12624 | {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 12625 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12626 | |
12627 | (define_insn "" | |
9ebbca7d | 12628 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12629 | (compare:CC |
9ebbca7d GK |
12630 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12631 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12632 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12633 | (const_int 0))) |
9ebbca7d | 12634 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12635 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12636 | "@ |
ca7f5001 | 12637 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12638 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
12639 | # | |
12640 | #" | |
b19003d8 | 12641 | [(set_attr "type" "compare") |
9ebbca7d GK |
12642 | (set_attr "length" "8,8,12,12")]) |
12643 | ||
12644 | (define_split | |
12645 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12646 | (compare:CC | |
12647 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12648 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12649 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12650 | (const_int 0))) | |
12651 | (clobber (match_scratch:SI 4 ""))] | |
12652 | "! TARGET_POWERPC64 && reload_completed" | |
12653 | [(set (match_dup 4) | |
12654 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
12655 | (match_dup 3))) | |
12656 | (set (match_dup 0) | |
12657 | (compare:CC (match_dup 4) | |
12658 | (const_int 0)))] | |
12659 | "") | |
1fd4e8c1 RK |
12660 | |
12661 | (define_insn "" | |
097657c3 | 12662 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12663 | (compare:CC |
9ebbca7d GK |
12664 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12665 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12666 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12667 | (const_int 0))) |
097657c3 AM |
12668 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12669 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 12670 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12671 | "@ |
097657c3 AM |
12672 | {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 |
12673 | {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12674 | # |
12675 | #" | |
b19003d8 | 12676 | [(set_attr "type" "compare") |
9ebbca7d GK |
12677 | (set_attr "length" "8,8,12,12")]) |
12678 | ||
12679 | (define_split | |
097657c3 | 12680 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12681 | (compare:CC |
12682 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12683 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12684 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12685 | (const_int 0))) | |
12686 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12687 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12688 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 12689 | [(set (match_dup 0) |
9ebbca7d | 12690 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12691 | (set (match_dup 4) |
9ebbca7d GK |
12692 | (compare:CC (match_dup 0) |
12693 | (const_int 0)))] | |
12694 | "") | |
1fd4e8c1 RK |
12695 | |
12696 | (define_insn "" | |
cd2b37d9 RK |
12697 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12698 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12699 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
f9562f27 | 12700 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12701 | "@ |
ca7f5001 | 12702 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 12703 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 12704 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12705 | |
12706 | (define_insn "" | |
097657c3 | 12707 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
1fd4e8c1 | 12708 | (and:SI (neg:SI |
cd2b37d9 | 12709 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12710 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
097657c3 | 12711 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
f9562f27 | 12712 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12713 | "@ |
097657c3 AM |
12714 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 |
12715 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" | |
b19003d8 | 12716 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12717 | |
12718 | (define_insn "" | |
9ebbca7d | 12719 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12720 | (compare:CC |
12721 | (and:SI (neg:SI | |
9ebbca7d GK |
12722 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12723 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12724 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12725 | (const_int 0))) |
9ebbca7d | 12726 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12727 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12728 | "@ |
ca7f5001 | 12729 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
12730 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
12731 | # | |
12732 | #" | |
b19003d8 | 12733 | [(set_attr "type" "compare") |
9ebbca7d GK |
12734 | (set_attr "length" "12,12,16,16")]) |
12735 | ||
12736 | (define_split | |
12737 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12738 | (compare:CC | |
12739 | (and:SI (neg:SI | |
12740 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12741 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12742 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12743 | (const_int 0))) | |
12744 | (clobber (match_scratch:SI 4 ""))] | |
12745 | "! TARGET_POWERPC64 && reload_completed" | |
12746 | [(set (match_dup 4) | |
097657c3 AM |
12747 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) |
12748 | (match_dup 3))) | |
9ebbca7d GK |
12749 | (set (match_dup 0) |
12750 | (compare:CC (match_dup 4) | |
12751 | (const_int 0)))] | |
12752 | "") | |
1fd4e8c1 RK |
12753 | |
12754 | (define_insn "" | |
097657c3 | 12755 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12756 | (compare:CC |
12757 | (and:SI (neg:SI | |
9ebbca7d GK |
12758 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12759 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12760 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12761 | (const_int 0))) |
097657c3 AM |
12762 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12763 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
f9562f27 | 12764 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12765 | "@ |
097657c3 AM |
12766 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
12767 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 | |
9ebbca7d GK |
12768 | # |
12769 | #" | |
b19003d8 | 12770 | [(set_attr "type" "compare") |
9ebbca7d GK |
12771 | (set_attr "length" "12,12,16,16")]) |
12772 | ||
12773 | (define_split | |
097657c3 | 12774 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12775 | (compare:CC |
12776 | (and:SI (neg:SI | |
12777 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12778 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12779 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12780 | (const_int 0))) | |
12781 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12782 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
9ebbca7d | 12783 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 12784 | [(set (match_dup 0) |
9ebbca7d | 12785 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
097657c3 | 12786 | (set (match_dup 4) |
9ebbca7d GK |
12787 | (compare:CC (match_dup 0) |
12788 | (const_int 0)))] | |
12789 | "") | |
1fd4e8c1 RK |
12790 | |
12791 | (define_insn "" | |
cd2b37d9 RK |
12792 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12793 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12794 | (const_int 0)))] |
f9562f27 | 12795 | "! TARGET_POWERPC64" |
ca7f5001 | 12796 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12797 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12798 | |
f9562f27 DE |
12799 | (define_insn "" |
12800 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12801 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12802 | (const_int 0)))] | |
12803 | "TARGET_POWERPC64" | |
12804 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" | |
12805 | [(set_attr "length" "12")]) | |
12806 | ||
1fd4e8c1 | 12807 | (define_insn "" |
9ebbca7d | 12808 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12809 | (compare:CC |
9ebbca7d | 12810 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
12811 | (const_int 0)) |
12812 | (const_int 0))) | |
9ebbca7d | 12813 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12814 | (gt:SI (match_dup 1) (const_int 0)))] |
f9562f27 | 12815 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12816 | "@ |
12817 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
12818 | #" | |
29ae5b89 | 12819 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12820 | (set_attr "length" "12,16")]) |
12821 | ||
12822 | (define_split | |
12823 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
12824 | (compare:CC | |
12825 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12826 | (const_int 0)) | |
12827 | (const_int 0))) | |
12828 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12829 | (gt:SI (match_dup 1) (const_int 0)))] | |
12830 | "! TARGET_POWERPC64 && reload_completed" | |
12831 | [(set (match_dup 0) | |
12832 | (gt:SI (match_dup 1) (const_int 0))) | |
12833 | (set (match_dup 2) | |
12834 | (compare:CC (match_dup 0) | |
12835 | (const_int 0)))] | |
12836 | "") | |
1fd4e8c1 | 12837 | |
f9562f27 | 12838 | (define_insn "" |
9ebbca7d | 12839 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 12840 | (compare:CC |
9ebbca7d | 12841 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
12842 | (const_int 0)) |
12843 | (const_int 0))) | |
9ebbca7d | 12844 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
12845 | (gt:DI (match_dup 1) (const_int 0)))] |
12846 | "TARGET_POWERPC64" | |
9ebbca7d GK |
12847 | "@ |
12848 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
12849 | #" | |
f9562f27 | 12850 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12851 | (set_attr "length" "12,16")]) |
12852 | ||
12853 | (define_split | |
12854 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
12855 | (compare:CC | |
12856 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12857 | (const_int 0)) | |
12858 | (const_int 0))) | |
12859 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12860 | (gt:DI (match_dup 1) (const_int 0)))] | |
12861 | "TARGET_POWERPC64 && reload_completed" | |
12862 | [(set (match_dup 0) | |
12863 | (gt:DI (match_dup 1) (const_int 0))) | |
12864 | (set (match_dup 2) | |
12865 | (compare:CC (match_dup 0) | |
12866 | (const_int 0)))] | |
12867 | "") | |
f9562f27 | 12868 | |
1fd4e8c1 | 12869 | (define_insn "" |
cd2b37d9 RK |
12870 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12871 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12872 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
12873 | "TARGET_POWER" |
12874 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 12875 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12876 | |
12877 | (define_insn "" | |
9ebbca7d | 12878 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12879 | (compare:CC |
9ebbca7d GK |
12880 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12881 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 12882 | (const_int 0))) |
9ebbca7d | 12883 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12884 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12885 | "TARGET_POWER" |
9ebbca7d GK |
12886 | "@ |
12887 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12888 | #" | |
29ae5b89 | 12889 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12890 | (set_attr "length" "12,16")]) |
12891 | ||
12892 | (define_split | |
12893 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12894 | (compare:CC | |
12895 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12896 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12897 | (const_int 0))) | |
12898 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12899 | (gt:SI (match_dup 1) (match_dup 2)))] | |
12900 | "TARGET_POWER && reload_completed" | |
12901 | [(set (match_dup 0) | |
12902 | (gt:SI (match_dup 1) (match_dup 2))) | |
12903 | (set (match_dup 3) | |
12904 | (compare:CC (match_dup 0) | |
12905 | (const_int 0)))] | |
12906 | "") | |
1fd4e8c1 RK |
12907 | |
12908 | (define_insn "" | |
80103f96 | 12909 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12910 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12911 | (const_int 0)) |
80103f96 | 12912 | (match_operand:SI 2 "gpc_reg_operand" "r")))] |
f9562f27 | 12913 | "! TARGET_POWERPC64" |
80103f96 | 12914 | "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" |
b19003d8 | 12915 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12916 | |
f9562f27 | 12917 | (define_insn "" |
097657c3 | 12918 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
f9562f27 DE |
12919 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
12920 | (const_int 0)) | |
097657c3 | 12921 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
f9562f27 | 12922 | "TARGET_POWERPC64" |
097657c3 | 12923 | "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" |
f9562f27 DE |
12924 | [(set_attr "length" "12")]) |
12925 | ||
1fd4e8c1 | 12926 | (define_insn "" |
9ebbca7d | 12927 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12928 | (compare:CC |
9ebbca7d | 12929 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12930 | (const_int 0)) |
9ebbca7d | 12931 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 12932 | (const_int 0))) |
9ebbca7d | 12933 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 12934 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12935 | "@ |
12936 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
12937 | #" | |
b19003d8 | 12938 | [(set_attr "type" "compare") |
9ebbca7d GK |
12939 | (set_attr "length" "12,16")]) |
12940 | ||
12941 | (define_split | |
12942 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12943 | (compare:CC | |
12944 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12945 | (const_int 0)) | |
12946 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
12947 | (const_int 0))) | |
12948 | (clobber (match_scratch:SI 3 ""))] | |
12949 | "! TARGET_POWERPC64 && reload_completed" | |
12950 | [(set (match_dup 3) | |
12951 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
12952 | (match_dup 2))) | |
12953 | (set (match_dup 0) | |
12954 | (compare:CC (match_dup 3) | |
12955 | (const_int 0)))] | |
12956 | "") | |
1fd4e8c1 | 12957 | |
f9562f27 | 12958 | (define_insn "" |
9ebbca7d | 12959 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 12960 | (compare:CC |
9ebbca7d | 12961 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 12962 | (const_int 0)) |
9ebbca7d | 12963 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 12964 | (const_int 0))) |
9ebbca7d | 12965 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 12966 | "TARGET_POWERPC64" |
9ebbca7d GK |
12967 | "@ |
12968 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
12969 | #" | |
f9562f27 | 12970 | [(set_attr "type" "compare") |
9ebbca7d GK |
12971 | (set_attr "length" "12,16")]) |
12972 | ||
12973 | (define_split | |
12974 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12975 | (compare:CC | |
12976 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12977 | (const_int 0)) | |
12978 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12979 | (const_int 0))) | |
12980 | (clobber (match_scratch:DI 3 ""))] | |
12981 | "TARGET_POWERPC64 && reload_completed" | |
12982 | [(set (match_dup 3) | |
12983 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
097657c3 | 12984 | (match_dup 2))) |
9ebbca7d GK |
12985 | (set (match_dup 0) |
12986 | (compare:CC (match_dup 3) | |
12987 | (const_int 0)))] | |
12988 | "") | |
f9562f27 | 12989 | |
1fd4e8c1 | 12990 | (define_insn "" |
097657c3 | 12991 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
9ebbca7d GK |
12992 | (compare:CC |
12993 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12994 | (const_int 0)) | |
12995 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
12996 | (const_int 0))) | |
097657c3 AM |
12997 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12998 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
9ebbca7d GK |
12999 | "! TARGET_POWERPC64" |
13000 | "@ | |
097657c3 | 13001 | {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 |
9ebbca7d GK |
13002 | #" |
13003 | [(set_attr "type" "compare") | |
13004 | (set_attr "length" "12,16")]) | |
13005 | ||
13006 | (define_split | |
097657c3 | 13007 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
1fd4e8c1 | 13008 | (compare:CC |
9ebbca7d | 13009 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 13010 | (const_int 0)) |
9ebbca7d | 13011 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 13012 | (const_int 0))) |
9ebbca7d | 13013 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
097657c3 | 13014 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] |
9ebbca7d | 13015 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 13016 | [(set (match_dup 0) |
9ebbca7d | 13017 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13018 | (set (match_dup 3) |
9ebbca7d GK |
13019 | (compare:CC (match_dup 0) |
13020 | (const_int 0)))] | |
13021 | "") | |
1fd4e8c1 | 13022 | |
f9562f27 | 13023 | (define_insn "" |
097657c3 | 13024 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13025 | (compare:CC |
9ebbca7d | 13026 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13027 | (const_int 0)) |
9ebbca7d | 13028 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13029 | (const_int 0))) |
097657c3 AM |
13030 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
13031 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
f9562f27 | 13032 | "TARGET_POWERPC64" |
9ebbca7d | 13033 | "@ |
097657c3 | 13034 | addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 |
9ebbca7d | 13035 | #" |
f9562f27 | 13036 | [(set_attr "type" "compare") |
9ebbca7d GK |
13037 | (set_attr "length" "12,16")]) |
13038 | ||
13039 | (define_split | |
097657c3 | 13040 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13041 | (compare:CC |
13042 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13043 | (const_int 0)) | |
13044 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13045 | (const_int 0))) | |
13046 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13047 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] |
9ebbca7d | 13048 | "TARGET_POWERPC64 && reload_completed" |
097657c3 | 13049 | [(set (match_dup 0) |
9ebbca7d | 13050 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13051 | (set (match_dup 3) |
9ebbca7d GK |
13052 | (compare:CC (match_dup 0) |
13053 | (const_int 0)))] | |
13054 | "") | |
f9562f27 | 13055 | |
1fd4e8c1 | 13056 | (define_insn "" |
097657c3 | 13057 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13058 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13059 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
097657c3 | 13060 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 13061 | "TARGET_POWER" |
097657c3 | 13062 | "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 13063 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13064 | |
13065 | (define_insn "" | |
9ebbca7d | 13066 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13067 | (compare:CC |
9ebbca7d GK |
13068 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13069 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13070 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13071 | (const_int 0))) |
9ebbca7d | 13072 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 13073 | "TARGET_POWER" |
9ebbca7d GK |
13074 | "@ |
13075 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
13076 | #" | |
b19003d8 | 13077 | [(set_attr "type" "compare") |
9ebbca7d GK |
13078 | (set_attr "length" "12,16")]) |
13079 | ||
13080 | (define_split | |
13081 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13082 | (compare:CC | |
13083 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13084 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13085 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13086 | (const_int 0))) | |
13087 | (clobber (match_scratch:SI 4 ""))] | |
13088 | "TARGET_POWER && reload_completed" | |
13089 | [(set (match_dup 4) | |
097657c3 | 13090 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d GK |
13091 | (set (match_dup 0) |
13092 | (compare:CC (match_dup 4) | |
13093 | (const_int 0)))] | |
13094 | "") | |
1fd4e8c1 RK |
13095 | |
13096 | (define_insn "" | |
097657c3 | 13097 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13098 | (compare:CC |
9ebbca7d GK |
13099 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13100 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13101 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13102 | (const_int 0))) |
097657c3 AM |
13103 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13104 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 13105 | "TARGET_POWER" |
9ebbca7d | 13106 | "@ |
097657c3 | 13107 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 13108 | #" |
b19003d8 | 13109 | [(set_attr "type" "compare") |
9ebbca7d GK |
13110 | (set_attr "length" "12,16")]) |
13111 | ||
13112 | (define_split | |
097657c3 | 13113 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13114 | (compare:CC |
13115 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13116 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13117 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13118 | (const_int 0))) | |
13119 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13120 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13121 | "TARGET_POWER && reload_completed" |
097657c3 | 13122 | [(set (match_dup 0) |
9ebbca7d | 13123 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13124 | (set (match_dup 4) |
9ebbca7d GK |
13125 | (compare:CC (match_dup 0) |
13126 | (const_int 0)))] | |
13127 | "") | |
1fd4e8c1 RK |
13128 | |
13129 | (define_insn "" | |
cd2b37d9 RK |
13130 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13131 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13132 | (const_int 0))))] |
f9562f27 | 13133 | "! TARGET_POWERPC64" |
ca7f5001 | 13134 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 13135 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13136 | |
f9562f27 DE |
13137 | (define_insn "" |
13138 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13139 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13140 | (const_int 0))))] | |
13141 | "TARGET_POWERPC64" | |
8377288b | 13142 | "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63" |
f9562f27 DE |
13143 | [(set_attr "length" "12")]) |
13144 | ||
1fd4e8c1 | 13145 | (define_insn "" |
cd2b37d9 RK |
13146 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13147 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13148 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
13149 | "TARGET_POWER" |
13150 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 13151 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13152 | |
13153 | (define_insn "" | |
cd2b37d9 RK |
13154 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13155 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13156 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 13157 | "! TARGET_POWERPC64" |
ca7f5001 | 13158 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 13159 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13160 | |
f9562f27 DE |
13161 | (define_insn "" |
13162 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13163 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13164 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
13165 | "TARGET_POWERPC64" | |
13166 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0" | |
13167 | [(set_attr "length" "12")]) | |
13168 | ||
1fd4e8c1 | 13169 | (define_insn "" |
9ebbca7d | 13170 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13171 | (compare:CC |
9ebbca7d GK |
13172 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13173 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 13174 | (const_int 0))) |
9ebbca7d | 13175 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13176 | (gtu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 13177 | "! TARGET_POWERPC64" |
9ebbca7d GK |
13178 | "@ |
13179 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
13180 | #" | |
b19003d8 | 13181 | [(set_attr "type" "compare") |
9ebbca7d GK |
13182 | (set_attr "length" "12,16")]) |
13183 | ||
13184 | (define_split | |
13185 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13186 | (compare:CC | |
13187 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13188 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13189 | (const_int 0))) | |
13190 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13191 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
13192 | "! TARGET_POWERPC64 && reload_completed" | |
13193 | [(set (match_dup 0) | |
13194 | (gtu:SI (match_dup 1) (match_dup 2))) | |
13195 | (set (match_dup 3) | |
13196 | (compare:CC (match_dup 0) | |
13197 | (const_int 0)))] | |
13198 | "") | |
1fd4e8c1 | 13199 | |
f9562f27 | 13200 | (define_insn "" |
9ebbca7d | 13201 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13202 | (compare:CC |
9ebbca7d GK |
13203 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13204 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 13205 | (const_int 0))) |
9ebbca7d | 13206 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
13207 | (gtu:DI (match_dup 1) (match_dup 2)))] |
13208 | "TARGET_POWERPC64" | |
9ebbca7d GK |
13209 | "@ |
13210 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
13211 | #" | |
f9562f27 | 13212 | [(set_attr "type" "compare") |
9ebbca7d GK |
13213 | (set_attr "length" "12,16")]) |
13214 | ||
13215 | (define_split | |
13216 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13217 | (compare:CC | |
13218 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13219 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13220 | (const_int 0))) | |
13221 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13222 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
13223 | "TARGET_POWERPC64 && reload_completed" | |
13224 | [(set (match_dup 0) | |
13225 | (gtu:DI (match_dup 1) (match_dup 2))) | |
13226 | (set (match_dup 3) | |
13227 | (compare:CC (match_dup 0) | |
13228 | (const_int 0)))] | |
13229 | "") | |
f9562f27 | 13230 | |
1fd4e8c1 | 13231 | (define_insn "" |
80103f96 | 13232 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
19378cf8 MM |
13233 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13234 | (match_operand:SI 2 "reg_or_short_operand" "I,rI")) | |
80103f96 | 13235 | (match_operand:SI 3 "reg_or_short_operand" "r,rI")))] |
f9562f27 | 13236 | "! TARGET_POWERPC64" |
00751805 | 13237 | "@ |
80103f96 FS |
13238 | {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3 |
13239 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" | |
19378cf8 | 13240 | [(set_attr "length" "8,12")]) |
1fd4e8c1 | 13241 | |
f9562f27 | 13242 | (define_insn "" |
097657c3 | 13243 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
f9562f27 DE |
13244 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13245 | (match_operand:DI 2 "reg_or_short_operand" "I,rI")) | |
097657c3 | 13246 | (match_operand:DI 3 "reg_or_short_operand" "r,rI")))] |
f9562f27 DE |
13247 | "TARGET_POWERPC64" |
13248 | "@ | |
097657c3 AM |
13249 | addic %0,%1,%k2\;addze %0,%3 |
13250 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3" | |
f9562f27 DE |
13251 | [(set_attr "length" "8,12")]) |
13252 | ||
1fd4e8c1 | 13253 | (define_insn "" |
9ebbca7d | 13254 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13255 | (compare:CC |
9ebbca7d GK |
13256 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13257 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13258 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13259 | (const_int 0))) |
9ebbca7d | 13260 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 13261 | "! TARGET_POWERPC64" |
00751805 | 13262 | "@ |
19378cf8 | 13263 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
13264 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
13265 | # | |
13266 | #" | |
b19003d8 | 13267 | [(set_attr "type" "compare") |
9ebbca7d GK |
13268 | (set_attr "length" "8,12,12,16")]) |
13269 | ||
13270 | (define_split | |
13271 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13272 | (compare:CC | |
13273 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13274 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13275 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13276 | (const_int 0))) | |
13277 | (clobber (match_scratch:SI 4 ""))] | |
13278 | "! TARGET_POWERPC64 && reload_completed" | |
13279 | [(set (match_dup 4) | |
13280 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 13281 | (match_dup 3))) |
9ebbca7d GK |
13282 | (set (match_dup 0) |
13283 | (compare:CC (match_dup 4) | |
13284 | (const_int 0)))] | |
13285 | "") | |
1fd4e8c1 | 13286 | |
f9562f27 | 13287 | (define_insn "" |
9ebbca7d | 13288 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13289 | (compare:CC |
9ebbca7d GK |
13290 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13291 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13292 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13293 | (const_int 0))) |
9ebbca7d | 13294 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
13295 | "TARGET_POWERPC64" |
13296 | "@ | |
13297 | addic %4,%1,%k2\;addze. %4,%3 | |
9ebbca7d GK |
13298 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3 |
13299 | # | |
13300 | #" | |
f9562f27 | 13301 | [(set_attr "type" "compare") |
9ebbca7d GK |
13302 | (set_attr "length" "8,12,12,16")]) |
13303 | ||
13304 | (define_split | |
13305 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13306 | (compare:CC | |
13307 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13308 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13309 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13310 | (const_int 0))) | |
13311 | (clobber (match_scratch:DI 4 ""))] | |
13312 | "TARGET_POWERPC64 && reload_completed" | |
13313 | [(set (match_dup 4) | |
13314 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
13315 | (match_dup 3))) | |
13316 | (set (match_dup 0) | |
13317 | (compare:CC (match_dup 4) | |
13318 | (const_int 0)))] | |
13319 | "") | |
f9562f27 | 13320 | |
1fd4e8c1 | 13321 | (define_insn "" |
097657c3 | 13322 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13323 | (compare:CC |
9ebbca7d GK |
13324 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13325 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13326 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13327 | (const_int 0))) |
097657c3 AM |
13328 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13329 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 13330 | "! TARGET_POWERPC64" |
00751805 | 13331 | "@ |
097657c3 AM |
13332 | {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 |
13333 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 | |
9ebbca7d GK |
13334 | # |
13335 | #" | |
b19003d8 | 13336 | [(set_attr "type" "compare") |
9ebbca7d GK |
13337 | (set_attr "length" "8,12,12,16")]) |
13338 | ||
13339 | (define_split | |
097657c3 | 13340 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13341 | (compare:CC |
13342 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13343 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13344 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13345 | (const_int 0))) | |
13346 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13347 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13348 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 13349 | [(set (match_dup 0) |
9ebbca7d | 13350 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13351 | (set (match_dup 4) |
9ebbca7d GK |
13352 | (compare:CC (match_dup 0) |
13353 | (const_int 0)))] | |
13354 | "") | |
1fd4e8c1 | 13355 | |
f9562f27 | 13356 | (define_insn "" |
097657c3 | 13357 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13358 | (compare:CC |
9ebbca7d GK |
13359 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13360 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13361 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13362 | (const_int 0))) |
097657c3 AM |
13363 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13364 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 DE |
13365 | "TARGET_POWERPC64" |
13366 | "@ | |
097657c3 AM |
13367 | addic %0,%1,%k2\;addze. %0,%3 |
13368 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3 | |
9ebbca7d GK |
13369 | # |
13370 | #" | |
f9562f27 | 13371 | [(set_attr "type" "compare") |
9ebbca7d GK |
13372 | (set_attr "length" "8,12,12,16")]) |
13373 | ||
13374 | (define_split | |
097657c3 | 13375 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13376 | (compare:CC |
13377 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13378 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13379 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13380 | (const_int 0))) | |
13381 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13382 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13383 | "TARGET_POWERPC64 && reload_completed" |
097657c3 | 13384 | [(set (match_dup 0) |
9ebbca7d | 13385 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13386 | (set (match_dup 4) |
9ebbca7d GK |
13387 | (compare:CC (match_dup 0) |
13388 | (const_int 0)))] | |
13389 | "") | |
f9562f27 | 13390 | |
1fd4e8c1 | 13391 | (define_insn "" |
cd2b37d9 RK |
13392 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13393 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13394 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 13395 | "! TARGET_POWERPC64" |
ca7f5001 | 13396 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 13397 | [(set_attr "length" "8")]) |
f9562f27 DE |
13398 | |
13399 | (define_insn "" | |
13400 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13401 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13402 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
13403 | "TARGET_POWERPC64" | |
13404 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" | |
13405 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
13406 | \f |
13407 | ;; Define both directions of branch and return. If we need a reload | |
13408 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
13409 | ;; register CC value to there. | |
13410 | ||
13411 | (define_insn "" | |
13412 | [(set (pc) | |
13413 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13414 | [(match_operand 2 | |
b54cf83a | 13415 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13416 | (const_int 0)]) |
13417 | (label_ref (match_operand 0 "" "")) | |
13418 | (pc)))] | |
13419 | "" | |
b19003d8 RK |
13420 | "* |
13421 | { | |
12a4e8c5 | 13422 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
13423 | }" |
13424 | [(set_attr "type" "branch")]) | |
13425 | ||
1fd4e8c1 RK |
13426 | (define_insn "" |
13427 | [(set (pc) | |
13428 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13429 | [(match_operand 1 | |
b54cf83a | 13430 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13431 | (const_int 0)]) |
13432 | (return) | |
13433 | (pc)))] | |
13434 | "direct_return ()" | |
12a4e8c5 GK |
13435 | "* |
13436 | { | |
13437 | return output_cbranch (operands[0], NULL, 0, insn); | |
13438 | }" | |
b7ff3d82 | 13439 | [(set_attr "type" "branch") |
39a10a29 | 13440 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
13441 | |
13442 | (define_insn "" | |
13443 | [(set (pc) | |
13444 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13445 | [(match_operand 2 | |
b54cf83a | 13446 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13447 | (const_int 0)]) |
13448 | (pc) | |
13449 | (label_ref (match_operand 0 "" ""))))] | |
13450 | "" | |
b19003d8 RK |
13451 | "* |
13452 | { | |
12a4e8c5 | 13453 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
13454 | }" |
13455 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13456 | |
13457 | (define_insn "" | |
13458 | [(set (pc) | |
13459 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13460 | [(match_operand 1 | |
b54cf83a | 13461 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13462 | (const_int 0)]) |
13463 | (pc) | |
13464 | (return)))] | |
13465 | "direct_return ()" | |
12a4e8c5 GK |
13466 | "* |
13467 | { | |
13468 | return output_cbranch (operands[0], NULL, 1, insn); | |
13469 | }" | |
b7ff3d82 | 13470 | [(set_attr "type" "branch") |
39a10a29 GK |
13471 | (set_attr "length" "4")]) |
13472 | ||
13473 | ;; Logic on condition register values. | |
13474 | ||
13475 | ; This pattern matches things like | |
13476 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
13477 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
13478 | ; (const_int 1))) | |
13479 | ; which are generated by the branch logic. | |
b54cf83a | 13480 | ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB) |
39a10a29 GK |
13481 | |
13482 | (define_insn "" | |
b54cf83a | 13483 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13484 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" |
b54cf83a | 13485 | [(match_operator:SI 2 |
39a10a29 GK |
13486 | "branch_positive_comparison_operator" |
13487 | [(match_operand 3 | |
b54cf83a | 13488 | "cc_reg_operand" "y,y") |
39a10a29 | 13489 | (const_int 0)]) |
b54cf83a | 13490 | (match_operator:SI 4 |
39a10a29 GK |
13491 | "branch_positive_comparison_operator" |
13492 | [(match_operand 5 | |
b54cf83a | 13493 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13494 | (const_int 0)])]) |
13495 | (const_int 1)))] | |
13496 | "" | |
13497 | "cr%q1 %E0,%j2,%j4" | |
b54cf83a | 13498 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13499 | |
13500 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
13501 | ; Because ~1 has all but the low bit set. | |
13502 | (define_insn "" | |
b54cf83a | 13503 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13504 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" |
b54cf83a | 13505 | [(not:SI (match_operator:SI 2 |
39a10a29 GK |
13506 | "branch_positive_comparison_operator" |
13507 | [(match_operand 3 | |
b54cf83a | 13508 | "cc_reg_operand" "y,y") |
39a10a29 GK |
13509 | (const_int 0)])) |
13510 | (match_operator:SI 4 | |
13511 | "branch_positive_comparison_operator" | |
13512 | [(match_operand 5 | |
b54cf83a | 13513 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13514 | (const_int 0)])]) |
13515 | (const_int -1)))] | |
13516 | "" | |
13517 | "cr%q1 %E0,%j2,%j4" | |
b54cf83a | 13518 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13519 | |
13520 | (define_insn "" | |
b54cf83a | 13521 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
6c873122 | 13522 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 13523 | "branch_positive_comparison_operator" |
6c873122 | 13524 | [(match_operand 2 |
b54cf83a | 13525 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13526 | (const_int 0)]) |
13527 | (const_int 0)))] | |
fe6b547a | 13528 | "!TARGET_SPE" |
251b3667 | 13529 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
b54cf83a | 13530 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13531 | |
13532 | ;; If we are comparing the result of two comparisons, this can be done | |
13533 | ;; using creqv or crxor. | |
13534 | ||
13535 | (define_insn_and_split "" | |
13536 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
13537 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
13538 | [(match_operand 2 "cc_reg_operand" "y") | |
13539 | (const_int 0)]) | |
13540 | (match_operator 3 "branch_comparison_operator" | |
13541 | [(match_operand 4 "cc_reg_operand" "y") | |
13542 | (const_int 0)])))] | |
13543 | "" | |
13544 | "#" | |
13545 | "" | |
13546 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
13547 | (match_dup 5)))] | |
13548 | " | |
13549 | { | |
13550 | int positive_1, positive_2; | |
13551 | ||
13552 | positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode); | |
13553 | positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode); | |
13554 | ||
13555 | if (! positive_1) | |
2d4368e6 | 13556 | operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]), |
39a10a29 | 13557 | GET_CODE (operands[1])), |
2d4368e6 DE |
13558 | SImode, |
13559 | operands[2], const0_rtx); | |
39a10a29 | 13560 | else if (GET_MODE (operands[1]) != SImode) |
2d4368e6 DE |
13561 | operands[1] = gen_rtx (GET_CODE (operands[1]), |
13562 | SImode, | |
13563 | operands[2], const0_rtx); | |
39a10a29 GK |
13564 | |
13565 | if (! positive_2) | |
2d4368e6 | 13566 | operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]), |
39a10a29 | 13567 | GET_CODE (operands[3])), |
2d4368e6 DE |
13568 | SImode, |
13569 | operands[4], const0_rtx); | |
39a10a29 | 13570 | else if (GET_MODE (operands[3]) != SImode) |
2d4368e6 DE |
13571 | operands[3] = gen_rtx (GET_CODE (operands[3]), |
13572 | SImode, | |
13573 | operands[4], const0_rtx); | |
39a10a29 GK |
13574 | |
13575 | if (positive_1 == positive_2) | |
251b3667 DE |
13576 | { |
13577 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
13578 | operands[5] = constm1_rtx; | |
13579 | } | |
13580 | else | |
13581 | { | |
13582 | operands[5] = const1_rtx; | |
13583 | } | |
39a10a29 | 13584 | }") |
1fd4e8c1 RK |
13585 | |
13586 | ;; Unconditional branch and return. | |
13587 | ||
13588 | (define_insn "jump" | |
13589 | [(set (pc) | |
13590 | (label_ref (match_operand 0 "" "")))] | |
13591 | "" | |
b7ff3d82 DE |
13592 | "b %l0" |
13593 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13594 | |
13595 | (define_insn "return" | |
13596 | [(return)] | |
13597 | "direct_return ()" | |
324e52cc TG |
13598 | "{br|blr}" |
13599 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 13600 | |
0ad91047 DE |
13601 | (define_expand "indirect_jump" |
13602 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 13603 | "" |
0ad91047 DE |
13604 | " |
13605 | { | |
13606 | if (TARGET_32BIT) | |
13607 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
13608 | else | |
13609 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
13610 | DONE; | |
13611 | }") | |
13612 | ||
13613 | (define_insn "indirect_jumpsi" | |
b92b324d | 13614 | [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))] |
0ad91047 | 13615 | "TARGET_32BIT" |
b92b324d DE |
13616 | "@ |
13617 | bctr | |
13618 | {br|blr}" | |
324e52cc | 13619 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13620 | |
0ad91047 | 13621 | (define_insn "indirect_jumpdi" |
b92b324d | 13622 | [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))] |
0ad91047 | 13623 | "TARGET_64BIT" |
b92b324d DE |
13624 | "@ |
13625 | bctr | |
13626 | blr" | |
266eb58a DE |
13627 | [(set_attr "type" "jmpreg")]) |
13628 | ||
1fd4e8c1 RK |
13629 | ;; Table jump for switch statements: |
13630 | (define_expand "tablejump" | |
e6ca2c17 DE |
13631 | [(use (match_operand 0 "" "")) |
13632 | (use (label_ref (match_operand 1 "" "")))] | |
13633 | "" | |
13634 | " | |
13635 | { | |
13636 | if (TARGET_32BIT) | |
13637 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
13638 | else | |
13639 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
13640 | DONE; | |
13641 | }") | |
13642 | ||
13643 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
13644 | [(set (match_dup 3) |
13645 | (plus:SI (match_operand:SI 0 "" "") | |
13646 | (match_dup 2))) | |
13647 | (parallel [(set (pc) (match_dup 3)) | |
13648 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13649 | "TARGET_32BIT" |
1fd4e8c1 RK |
13650 | " |
13651 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 13652 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
13653 | operands[3] = gen_reg_rtx (SImode); |
13654 | }") | |
13655 | ||
e6ca2c17 | 13656 | (define_expand "tablejumpdi" |
9ebbca7d GK |
13657 | [(set (match_dup 4) |
13658 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) | |
13659 | (set (match_dup 3) | |
13660 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
13661 | (match_dup 2))) |
13662 | (parallel [(set (pc) (match_dup 3)) | |
13663 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13664 | "TARGET_64BIT" |
e6ca2c17 | 13665 | " |
9ebbca7d | 13666 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 13667 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 13668 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
13669 | }") |
13670 | ||
1fd4e8c1 RK |
13671 | (define_insn "" |
13672 | [(set (pc) | |
c859cda6 | 13673 | (match_operand:SI 0 "register_operand" "c,*l")) |
1fd4e8c1 | 13674 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13675 | "TARGET_32BIT" |
c859cda6 DJ |
13676 | "@ |
13677 | bctr | |
13678 | {br|blr}" | |
a6845123 | 13679 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13680 | |
266eb58a DE |
13681 | (define_insn "" |
13682 | [(set (pc) | |
c859cda6 | 13683 | (match_operand:DI 0 "register_operand" "c,*l")) |
266eb58a | 13684 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13685 | "TARGET_64BIT" |
c859cda6 DJ |
13686 | "@ |
13687 | bctr | |
13688 | blr" | |
266eb58a DE |
13689 | [(set_attr "type" "jmpreg")]) |
13690 | ||
1fd4e8c1 RK |
13691 | (define_insn "nop" |
13692 | [(const_int 0)] | |
13693 | "" | |
ca7f5001 | 13694 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 13695 | \f |
7e69e155 | 13696 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
13697 | ;; so loop.c knows what to generate. |
13698 | ||
5527bf14 RH |
13699 | (define_expand "doloop_end" |
13700 | [(use (match_operand 0 "" "")) ; loop pseudo | |
13701 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
13702 | (use (match_operand 2 "" "")) ; max iterations | |
13703 | (use (match_operand 3 "" "")) ; loop level | |
13704 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
13705 | "" |
13706 | " | |
13707 | { | |
5527bf14 RH |
13708 | /* Only use this on innermost loops. */ |
13709 | if (INTVAL (operands[3]) > 1) | |
13710 | FAIL; | |
0ad91047 | 13711 | if (TARGET_POWERPC64) |
5527bf14 RH |
13712 | { |
13713 | if (GET_MODE (operands[0]) != DImode) | |
13714 | FAIL; | |
13715 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
13716 | } | |
0ad91047 | 13717 | else |
5527bf14 RH |
13718 | { |
13719 | if (GET_MODE (operands[0]) != SImode) | |
13720 | FAIL; | |
13721 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
13722 | } | |
0ad91047 DE |
13723 | DONE; |
13724 | }") | |
13725 | ||
13726 | (define_expand "ctrsi" | |
3cb999d8 DE |
13727 | [(parallel [(set (pc) |
13728 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
13729 | (const_int 1)) | |
13730 | (label_ref (match_operand 1 "" "")) | |
13731 | (pc))) | |
b6c9286a MM |
13732 | (set (match_dup 0) |
13733 | (plus:SI (match_dup 0) | |
13734 | (const_int -1))) | |
5f81043f RK |
13735 | (clobber (match_scratch:CC 2 "")) |
13736 | (clobber (match_scratch:SI 3 ""))])] | |
0ad91047 DE |
13737 | "! TARGET_POWERPC64" |
13738 | "") | |
13739 | ||
13740 | (define_expand "ctrdi" | |
3cb999d8 DE |
13741 | [(parallel [(set (pc) |
13742 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
13743 | (const_int 1)) | |
13744 | (label_ref (match_operand 1 "" "")) | |
13745 | (pc))) | |
0ad91047 DE |
13746 | (set (match_dup 0) |
13747 | (plus:DI (match_dup 0) | |
13748 | (const_int -1))) | |
13749 | (clobber (match_scratch:CC 2 "")) | |
61c07d3c | 13750 | (clobber (match_scratch:DI 3 ""))])] |
0ad91047 | 13751 | "TARGET_POWERPC64" |
61c07d3c | 13752 | "") |
c225ba7b | 13753 | |
1fd4e8c1 RK |
13754 | ;; We need to be able to do this for any operand, including MEM, or we |
13755 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 13756 | ;; JUMP_INSNs. |
0ad91047 | 13757 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
13758 | ;; label MUST be operand 0. |
13759 | ||
0ad91047 | 13760 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 13761 | [(set (pc) |
5f81043f | 13762 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 13763 | (const_int 1)) |
a6845123 | 13764 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13765 | (pc))) |
5f81043f RK |
13766 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
13767 | (plus:SI (match_dup 1) | |
13768 | (const_int -1))) | |
1fd4e8c1 RK |
13769 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13770 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13771 | "! TARGET_POWERPC64" |
b19003d8 RK |
13772 | "* |
13773 | { | |
af87a13e | 13774 | if (which_alternative != 0) |
b19003d8 | 13775 | return \"#\"; |
856a6884 | 13776 | else if (get_attr_length (insn) == 4) |
a6845123 | 13777 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 13778 | else |
f607bc57 | 13779 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 13780 | }" |
baf97f86 | 13781 | [(set_attr "type" "branch") |
914a7297 | 13782 | (set_attr "length" "4,12,16")]) |
7e69e155 | 13783 | |
0ad91047 | 13784 | (define_insn "*ctrsi_internal2" |
5f81043f RK |
13785 | [(set (pc) |
13786 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") | |
13787 | (const_int 1)) | |
13788 | (pc) | |
13789 | (label_ref (match_operand 0 "" "")))) | |
13790 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
13791 | (plus:SI (match_dup 1) | |
13792 | (const_int -1))) | |
13793 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
13794 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
13795 | "! TARGET_POWERPC64" |
13796 | "* | |
13797 | { | |
13798 | if (which_alternative != 0) | |
13799 | return \"#\"; | |
856a6884 | 13800 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13801 | return \"bdz %l0\"; |
13802 | else | |
f607bc57 | 13803 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
13804 | }" |
13805 | [(set_attr "type" "branch") | |
914a7297 | 13806 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
13807 | |
13808 | (define_insn "*ctrdi_internal1" | |
13809 | [(set (pc) | |
61c07d3c | 13810 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
13811 | (const_int 1)) |
13812 | (label_ref (match_operand 0 "" "")) | |
13813 | (pc))) | |
61c07d3c | 13814 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
13815 | (plus:DI (match_dup 1) |
13816 | (const_int -1))) | |
61c07d3c DE |
13817 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13818 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
13819 | "TARGET_POWERPC64" |
13820 | "* | |
13821 | { | |
13822 | if (which_alternative != 0) | |
13823 | return \"#\"; | |
856a6884 | 13824 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13825 | return \"{bdn|bdnz} %l0\"; |
13826 | else | |
f607bc57 | 13827 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
13828 | }" |
13829 | [(set_attr "type" "branch") | |
914a7297 | 13830 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
13831 | |
13832 | (define_insn "*ctrdi_internal2" | |
13833 | [(set (pc) | |
61c07d3c | 13834 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
13835 | (const_int 1)) |
13836 | (pc) | |
13837 | (label_ref (match_operand 0 "" "")))) | |
61c07d3c | 13838 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
13839 | (plus:DI (match_dup 1) |
13840 | (const_int -1))) | |
61c07d3c DE |
13841 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13842 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 | 13843 | "TARGET_POWERPC64" |
5f81043f RK |
13844 | "* |
13845 | { | |
13846 | if (which_alternative != 0) | |
13847 | return \"#\"; | |
856a6884 | 13848 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
13849 | return \"bdz %l0\"; |
13850 | else | |
f607bc57 | 13851 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
13852 | }" |
13853 | [(set_attr "type" "branch") | |
914a7297 | 13854 | (set_attr "length" "4,12,16")]) |
5f81043f | 13855 | |
c225ba7b | 13856 | ;; Similar, but we can use GE since we have a REG_NONNEG. |
0ad91047 DE |
13857 | |
13858 | (define_insn "*ctrsi_internal3" | |
1fd4e8c1 | 13859 | [(set (pc) |
5f81043f | 13860 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 13861 | (const_int 0)) |
a6845123 | 13862 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13863 | (pc))) |
5f81043f RK |
13864 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
13865 | (plus:SI (match_dup 1) | |
13866 | (const_int -1))) | |
1fd4e8c1 RK |
13867 | (clobber (match_scratch:CC 3 "=X,&x,&X")) |
13868 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13869 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
b19003d8 RK |
13870 | "* |
13871 | { | |
af87a13e | 13872 | if (which_alternative != 0) |
b19003d8 | 13873 | return \"#\"; |
856a6884 | 13874 | else if (get_attr_length (insn) == 4) |
a6845123 | 13875 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 13876 | else |
f607bc57 | 13877 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 13878 | }" |
baf97f86 | 13879 | [(set_attr "type" "branch") |
914a7297 | 13880 | (set_attr "length" "4,12,16")]) |
7e69e155 | 13881 | |
0ad91047 | 13882 | (define_insn "*ctrsi_internal4" |
1fd4e8c1 | 13883 | [(set (pc) |
5f81043f RK |
13884 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
13885 | (const_int 0)) | |
13886 | (pc) | |
13887 | (label_ref (match_operand 0 "" "")))) | |
13888 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
13889 | (plus:SI (match_dup 1) | |
13890 | (const_int -1))) | |
13891 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
13892 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13893 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
5f81043f RK |
13894 | "* |
13895 | { | |
13896 | if (which_alternative != 0) | |
13897 | return \"#\"; | |
856a6884 | 13898 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
13899 | return \"bdz %l0\"; |
13900 | else | |
f607bc57 | 13901 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
13902 | }" |
13903 | [(set_attr "type" "branch") | |
914a7297 | 13904 | (set_attr "length" "4,12,16")]) |
5f81043f | 13905 | |
0ad91047 DE |
13906 | (define_insn "*ctrdi_internal3" |
13907 | [(set (pc) | |
61c07d3c | 13908 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
13909 | (const_int 0)) |
13910 | (label_ref (match_operand 0 "" "")) | |
13911 | (pc))) | |
61c07d3c | 13912 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
13913 | (plus:DI (match_dup 1) |
13914 | (const_int -1))) | |
61c07d3c DE |
13915 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13916 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
13917 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
13918 | "* | |
13919 | { | |
13920 | if (which_alternative != 0) | |
13921 | return \"#\"; | |
856a6884 | 13922 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13923 | return \"{bdn|bdnz} %l0\"; |
13924 | else | |
f607bc57 | 13925 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
13926 | }" |
13927 | [(set_attr "type" "branch") | |
914a7297 | 13928 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
13929 | |
13930 | (define_insn "*ctrdi_internal4" | |
13931 | [(set (pc) | |
61c07d3c | 13932 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
13933 | (const_int 0)) |
13934 | (pc) | |
13935 | (label_ref (match_operand 0 "" "")))) | |
61c07d3c | 13936 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
13937 | (plus:DI (match_dup 1) |
13938 | (const_int -1))) | |
61c07d3c DE |
13939 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13940 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
13941 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
13942 | "* | |
13943 | { | |
13944 | if (which_alternative != 0) | |
13945 | return \"#\"; | |
856a6884 | 13946 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13947 | return \"bdz %l0\"; |
13948 | else | |
f607bc57 | 13949 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
13950 | }" |
13951 | [(set_attr "type" "branch") | |
914a7297 | 13952 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
13953 | |
13954 | ;; Similar but use EQ | |
13955 | ||
13956 | (define_insn "*ctrsi_internal5" | |
5f81043f RK |
13957 | [(set (pc) |
13958 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
1fd4e8c1 | 13959 | (const_int 1)) |
a6845123 | 13960 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13961 | (pc))) |
5f81043f RK |
13962 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
13963 | (plus:SI (match_dup 1) | |
13964 | (const_int -1))) | |
1fd4e8c1 RK |
13965 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13966 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13967 | "! TARGET_POWERPC64" |
b19003d8 RK |
13968 | "* |
13969 | { | |
af87a13e | 13970 | if (which_alternative != 0) |
b19003d8 | 13971 | return \"#\"; |
856a6884 | 13972 | else if (get_attr_length (insn) == 4) |
a6845123 | 13973 | return \"bdz %l0\"; |
b19003d8 | 13974 | else |
f607bc57 | 13975 | return \"{bdn|bdnz} $+8\;b %l0\"; |
b19003d8 | 13976 | }" |
baf97f86 | 13977 | [(set_attr "type" "branch") |
914a7297 | 13978 | (set_attr "length" "4,12,16")]) |
1fd4e8c1 | 13979 | |
0ad91047 | 13980 | (define_insn "*ctrsi_internal6" |
5f81043f RK |
13981 | [(set (pc) |
13982 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
13983 | (const_int 1)) | |
13984 | (pc) | |
13985 | (label_ref (match_operand 0 "" "")))) | |
13986 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
13987 | (plus:SI (match_dup 1) | |
13988 | (const_int -1))) | |
13989 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
13990 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
13991 | "! TARGET_POWERPC64" |
13992 | "* | |
13993 | { | |
13994 | if (which_alternative != 0) | |
13995 | return \"#\"; | |
856a6884 | 13996 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13997 | return \"{bdn|bdnz} %l0\"; |
13998 | else | |
f607bc57 | 13999 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14000 | }" |
14001 | [(set_attr "type" "branch") | |
914a7297 | 14002 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
14003 | |
14004 | (define_insn "*ctrdi_internal5" | |
14005 | [(set (pc) | |
61c07d3c | 14006 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
14007 | (const_int 1)) |
14008 | (label_ref (match_operand 0 "" "")) | |
14009 | (pc))) | |
61c07d3c | 14010 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
14011 | (plus:DI (match_dup 1) |
14012 | (const_int -1))) | |
61c07d3c DE |
14013 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14014 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
14015 | "TARGET_POWERPC64" |
14016 | "* | |
14017 | { | |
14018 | if (which_alternative != 0) | |
14019 | return \"#\"; | |
856a6884 | 14020 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14021 | return \"bdz %l0\"; |
14022 | else | |
f607bc57 | 14023 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14024 | }" |
14025 | [(set_attr "type" "branch") | |
914a7297 | 14026 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
14027 | |
14028 | (define_insn "*ctrdi_internal6" | |
14029 | [(set (pc) | |
61c07d3c | 14030 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
14031 | (const_int 1)) |
14032 | (pc) | |
14033 | (label_ref (match_operand 0 "" "")))) | |
61c07d3c | 14034 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
14035 | (plus:DI (match_dup 1) |
14036 | (const_int -1))) | |
61c07d3c DE |
14037 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14038 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 | 14039 | "TARGET_POWERPC64" |
5f81043f RK |
14040 | "* |
14041 | { | |
14042 | if (which_alternative != 0) | |
14043 | return \"#\"; | |
856a6884 | 14044 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14045 | return \"{bdn|bdnz} %l0\"; |
14046 | else | |
f607bc57 | 14047 | return \"bdz $+8\;b %l0\"; |
5f81043f RK |
14048 | }" |
14049 | [(set_attr "type" "branch") | |
914a7297 | 14050 | (set_attr "length" "4,12,16")]) |
5f81043f | 14051 | |
0ad91047 DE |
14052 | ;; Now the splitters if we could not allocate the CTR register |
14053 | ||
1fd4e8c1 RK |
14054 | (define_split |
14055 | [(set (pc) | |
14056 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14057 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14058 | (const_int 1)]) |
14059 | (match_operand 5 "" "") | |
14060 | (match_operand 6 "" ""))) | |
cd2b37d9 | 14061 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
14062 | (plus:SI (match_dup 1) |
14063 | (const_int -1))) | |
1fd4e8c1 RK |
14064 | (clobber (match_scratch:CC 3 "")) |
14065 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 | 14066 | "! TARGET_POWERPC64 && reload_completed" |
1fd4e8c1 | 14067 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14068 | (compare:CC (plus:SI (match_dup 1) |
14069 | (const_int -1)) | |
1fd4e8c1 | 14070 | (const_int 0))) |
5f81043f RK |
14071 | (set (match_dup 0) |
14072 | (plus:SI (match_dup 1) | |
14073 | (const_int -1)))]) | |
14074 | (set (pc) (if_then_else (match_dup 7) | |
14075 | (match_dup 5) | |
14076 | (match_dup 6)))] | |
1fd4e8c1 RK |
14077 | " |
14078 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
14079 | const0_rtx); }") | |
14080 | ||
14081 | (define_split | |
14082 | [(set (pc) | |
14083 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14084 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14085 | (const_int 1)]) |
14086 | (match_operand 5 "" "") | |
14087 | (match_operand 6 "" ""))) | |
9ebbca7d | 14088 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
14089 | (plus:SI (match_dup 1) (const_int -1))) |
14090 | (clobber (match_scratch:CC 3 "")) | |
14091 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 DE |
14092 | "! TARGET_POWERPC64 && reload_completed |
14093 | && ! gpc_reg_operand (operands[0], SImode)" | |
1fd4e8c1 | 14094 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14095 | (compare:CC (plus:SI (match_dup 1) |
14096 | (const_int -1)) | |
1fd4e8c1 | 14097 | (const_int 0))) |
5f81043f RK |
14098 | (set (match_dup 4) |
14099 | (plus:SI (match_dup 1) | |
14100 | (const_int -1)))]) | |
14101 | (set (match_dup 0) | |
14102 | (match_dup 4)) | |
14103 | (set (pc) (if_then_else (match_dup 7) | |
14104 | (match_dup 5) | |
14105 | (match_dup 6)))] | |
1fd4e8c1 RK |
14106 | " |
14107 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
14108 | const0_rtx); }") | |
0ad91047 DE |
14109 | (define_split |
14110 | [(set (pc) | |
14111 | (if_then_else (match_operator 2 "comparison_operator" | |
14112 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14113 | (const_int 1)]) | |
61c07d3c DE |
14114 | (match_operand 5 "" "") |
14115 | (match_operand 6 "" ""))) | |
0ad91047 DE |
14116 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
14117 | (plus:DI (match_dup 1) | |
14118 | (const_int -1))) | |
14119 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c DE |
14120 | (clobber (match_scratch:DI 4 ""))] |
14121 | "TARGET_POWERPC64 && reload_completed" | |
0ad91047 DE |
14122 | [(parallel [(set (match_dup 3) |
14123 | (compare:CC (plus:DI (match_dup 1) | |
14124 | (const_int -1)) | |
14125 | (const_int 0))) | |
14126 | (set (match_dup 0) | |
14127 | (plus:DI (match_dup 1) | |
14128 | (const_int -1)))]) | |
61c07d3c DE |
14129 | (set (pc) (if_then_else (match_dup 7) |
14130 | (match_dup 5) | |
14131 | (match_dup 6)))] | |
0ad91047 | 14132 | " |
61c07d3c | 14133 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], |
0ad91047 DE |
14134 | const0_rtx); }") |
14135 | ||
14136 | (define_split | |
14137 | [(set (pc) | |
14138 | (if_then_else (match_operator 2 "comparison_operator" | |
14139 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14140 | (const_int 1)]) | |
61c07d3c DE |
14141 | (match_operand 5 "" "") |
14142 | (match_operand 6 "" ""))) | |
9ebbca7d | 14143 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
14144 | (plus:DI (match_dup 1) (const_int -1))) |
14145 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 14146 | (clobber (match_scratch:DI 4 ""))] |
0ad91047 DE |
14147 | "TARGET_POWERPC64 && reload_completed |
14148 | && ! gpc_reg_operand (operands[0], DImode)" | |
14149 | [(parallel [(set (match_dup 3) | |
14150 | (compare:CC (plus:DI (match_dup 1) | |
14151 | (const_int -1)) | |
14152 | (const_int 0))) | |
14153 | (set (match_dup 4) | |
14154 | (plus:DI (match_dup 1) | |
14155 | (const_int -1)))]) | |
14156 | (set (match_dup 0) | |
14157 | (match_dup 4)) | |
61c07d3c DE |
14158 | (set (pc) (if_then_else (match_dup 7) |
14159 | (match_dup 5) | |
14160 | (match_dup 6)))] | |
0ad91047 | 14161 | " |
61c07d3c | 14162 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], |
0ad91047 | 14163 | const0_rtx); }") |
c94ccb87 | 14164 | |
e0cd0770 JC |
14165 | \f |
14166 | (define_insn "trap" | |
14167 | [(trap_if (const_int 1) (const_int 0))] | |
14168 | "" | |
14169 | "{t 31,0,0|trap}") | |
14170 | ||
14171 | (define_expand "conditional_trap" | |
14172 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14173 | [(match_dup 2) (match_dup 3)]) | |
14174 | (match_operand 1 "const_int_operand" ""))] | |
14175 | "" | |
14176 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
14177 | operands[2] = rs6000_compare_op0; | |
14178 | operands[3] = rs6000_compare_op1;") | |
14179 | ||
14180 | (define_insn "" | |
14181 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14182 | [(match_operand:SI 1 "register_operand" "r") | |
14183 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
14184 | (const_int 0))] | |
14185 | "" | |
a157febd GK |
14186 | "{t|tw}%V0%I2 %1,%2") |
14187 | ||
14188 | (define_insn "" | |
14189 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14190 | [(match_operand:DI 1 "register_operand" "r") | |
14191 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
14192 | (const_int 0))] | |
14193 | "TARGET_POWERPC64" | |
14194 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
14195 | \f |
14196 | ;; Insns related to generating the function prologue and epilogue. | |
14197 | ||
14198 | (define_expand "prologue" | |
14199 | [(use (const_int 0))] | |
14200 | "TARGET_SCHED_PROLOG" | |
14201 | " | |
14202 | { | |
14203 | rs6000_emit_prologue (); | |
14204 | DONE; | |
14205 | }") | |
14206 | ||
14207 | (define_insn "movesi_from_cr" | |
14208 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
14209 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) | |
615158e2 JJ |
14210 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] |
14211 | UNSPEC_MOVESI_FROM_CR))] | |
9ebbca7d | 14212 | "" |
309323c2 | 14213 | "mfcr %0" |
b54cf83a | 14214 | [(set_attr "type" "mfcr")]) |
9ebbca7d GK |
14215 | |
14216 | (define_insn "*stmw" | |
14217 | [(match_parallel 0 "stmw_operation" | |
14218 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
14219 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
14220 | "TARGET_MULTIPLE" | |
14221 | "{stm|stmw} %2,%1") | |
14222 | ||
14223 | (define_insn "*save_fpregs_si" | |
14224 | [(match_parallel 0 "any_operand" | |
14225 | [(clobber (match_operand:SI 1 "register_operand" "=l")) | |
14226 | (use (match_operand:SI 2 "call_operand" "s")) | |
14227 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14228 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14229 | "TARGET_32BIT" | |
14230 | "bl %z2") | |
14231 | ||
14232 | (define_insn "*save_fpregs_di" | |
14233 | [(match_parallel 0 "any_operand" | |
14234 | [(clobber (match_operand:DI 1 "register_operand" "=l")) | |
14235 | (use (match_operand:DI 2 "call_operand" "s")) | |
14236 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14237 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14238 | "TARGET_64BIT" | |
14239 | "bl %z2") | |
14240 | ||
14241 | ; These are to explain that changes to the stack pointer should | |
14242 | ; not be moved over stores to stack memory. | |
14243 | (define_insn "stack_tie" | |
14244 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
615158e2 | 14245 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] |
9ebbca7d GK |
14246 | "" |
14247 | "" | |
14248 | [(set_attr "length" "0")]) | |
14249 | ||
14250 | ||
14251 | (define_expand "epilogue" | |
14252 | [(use (const_int 0))] | |
14253 | "TARGET_SCHED_PROLOG" | |
14254 | " | |
14255 | { | |
14256 | rs6000_emit_epilogue (FALSE); | |
14257 | DONE; | |
14258 | }") | |
14259 | ||
14260 | ; On some processors, doing the mtcrf one CC register at a time is | |
14261 | ; faster (like on the 604e). On others, doing them all at once is | |
14262 | ; faster; for instance, on the 601 and 750. | |
14263 | ||
14264 | (define_expand "movsi_to_cr_one" | |
35aba846 DE |
14265 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14266 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 | 14267 | (match_dup 2)] UNSPEC_MOVESI_TO_CR))] |
35aba846 DE |
14268 | "" |
14269 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
9ebbca7d GK |
14270 | |
14271 | (define_insn "*movsi_to_cr" | |
35aba846 DE |
14272 | [(match_parallel 0 "mtcrf_operation" |
14273 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") | |
14274 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
14275 | (match_operand 3 "immediate_operand" "n")] | |
615158e2 | 14276 | UNSPEC_MOVESI_TO_CR))])] |
9ebbca7d | 14277 | "" |
e35b9579 GK |
14278 | "* |
14279 | { | |
14280 | int mask = 0; | |
14281 | int i; | |
14282 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14283 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14284 | operands[4] = GEN_INT (mask); | |
14285 | return \"mtcrf %4,%2\"; | |
309323c2 | 14286 | }" |
b54cf83a | 14287 | [(set_attr "type" "mtcr")]) |
9ebbca7d | 14288 | |
b54cf83a | 14289 | (define_insn "*mtcrfsi" |
309323c2 DE |
14290 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14291 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 JJ |
14292 | (match_operand 2 "immediate_operand" "n")] |
14293 | UNSPEC_MOVESI_TO_CR))] | |
309323c2 DE |
14294 | "GET_CODE (operands[0]) == REG |
14295 | && CR_REGNO_P (REGNO (operands[0])) | |
14296 | && GET_CODE (operands[2]) == CONST_INT | |
14297 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
14298 | "mtcrf %R0,%1" | |
b54cf83a | 14299 | [(set_attr "type" "mtcr")]) |
9ebbca7d GK |
14300 | |
14301 | ; The load-multiple instructions have similar properties. | |
14302 | ; Note that "load_multiple" is a name known to the machine-independent | |
14303 | ; code that actually corresponds to the powerpc load-string. | |
14304 | ||
14305 | (define_insn "*lmw" | |
35aba846 DE |
14306 | [(match_parallel 0 "lmw_operation" |
14307 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14308 | (match_operand:SI 2 "memory_operand" "m"))])] | |
14309 | "TARGET_MULTIPLE" | |
14310 | "{lm|lmw} %1,%2") | |
9ebbca7d GK |
14311 | |
14312 | (define_insn "*return_internal_si" | |
e35b9579 GK |
14313 | [(return) |
14314 | (use (match_operand:SI 0 "register_operand" "lc"))] | |
9ebbca7d | 14315 | "TARGET_32BIT" |
cccf3bdc | 14316 | "b%T0" |
9ebbca7d GK |
14317 | [(set_attr "type" "jmpreg")]) |
14318 | ||
14319 | (define_insn "*return_internal_di" | |
e35b9579 GK |
14320 | [(return) |
14321 | (use (match_operand:DI 0 "register_operand" "lc"))] | |
9ebbca7d | 14322 | "TARGET_64BIT" |
cccf3bdc | 14323 | "b%T0" |
9ebbca7d GK |
14324 | [(set_attr "type" "jmpreg")]) |
14325 | ||
14326 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
14327 | ; stuff was in GCC. Oh, and "any_operand" is a bit flexible... | |
14328 | ||
14329 | (define_insn "*return_and_restore_fpregs_si" | |
14330 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
14331 | [(return) |
14332 | (use (match_operand:SI 1 "register_operand" "l")) | |
9ebbca7d GK |
14333 | (use (match_operand:SI 2 "call_operand" "s")) |
14334 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14335 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14336 | "TARGET_32BIT" | |
14337 | "b %z2") | |
14338 | ||
14339 | (define_insn "*return_and_restore_fpregs_di" | |
14340 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
14341 | [(return) |
14342 | (use (match_operand:DI 1 "register_operand" "l")) | |
9ebbca7d GK |
14343 | (use (match_operand:DI 2 "call_operand" "s")) |
14344 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14345 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14346 | "TARGET_64BIT" | |
14347 | "b %z2") | |
14348 | ||
83720594 RH |
14349 | ; This is used in compiling the unwind routines. |
14350 | (define_expand "eh_return" | |
14351 | [(use (match_operand 0 "general_operand" "")) | |
14352 | (use (match_operand 1 "general_operand" ""))] | |
9ebbca7d GK |
14353 | "" |
14354 | " | |
14355 | { | |
3553b09d | 14356 | #if TARGET_AIX |
83720594 | 14357 | rs6000_emit_eh_toc_restore (operands[0]); |
3553b09d | 14358 | #endif |
83720594 RH |
14359 | if (TARGET_32BIT) |
14360 | emit_insn (gen_eh_set_lr_si (operands[1])); | |
9ebbca7d | 14361 | else |
83720594 RH |
14362 | emit_insn (gen_eh_set_lr_di (operands[1])); |
14363 | emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]); | |
9ebbca7d GK |
14364 | DONE; |
14365 | }") | |
14366 | ||
83720594 RH |
14367 | ; We can't expand this before we know where the link register is stored. |
14368 | (define_insn "eh_set_lr_si" | |
615158e2 JJ |
14369 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] |
14370 | UNSPECV_EH_RR) | |
466eb3e0 | 14371 | (clobber (match_scratch:SI 1 "=&b"))] |
83720594 RH |
14372 | "TARGET_32BIT" |
14373 | "#") | |
14374 | ||
14375 | (define_insn "eh_set_lr_di" | |
615158e2 JJ |
14376 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
14377 | UNSPECV_EH_RR) | |
466eb3e0 | 14378 | (clobber (match_scratch:DI 1 "=&b"))] |
83720594 RH |
14379 | "TARGET_64BIT" |
14380 | "#") | |
9ebbca7d GK |
14381 | |
14382 | (define_split | |
615158e2 | 14383 | [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) |
83720594 RH |
14384 | (clobber (match_scratch 1 ""))] |
14385 | "reload_completed" | |
14386 | [(const_int 0)] | |
9ebbca7d GK |
14387 | " |
14388 | { | |
83720594 | 14389 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d | 14390 | |
83720594 RH |
14391 | if (info->lr_save_p) |
14392 | { | |
14393 | rtx frame_rtx = stack_pointer_rtx; | |
14394 | int sp_offset = 0; | |
14395 | rtx tmp; | |
9ebbca7d | 14396 | |
83720594 RH |
14397 | if (frame_pointer_needed |
14398 | || current_function_calls_alloca | |
14399 | || info->total_size > 32767) | |
14400 | { | |
14401 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
14402 | frame_rtx = operands[1]; | |
14403 | } | |
14404 | else if (info->push_p) | |
14405 | sp_offset = info->total_size; | |
9ebbca7d | 14406 | |
83720594 RH |
14407 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); |
14408 | tmp = gen_rtx_MEM (Pmode, tmp); | |
14409 | emit_move_insn (tmp, operands[0]); | |
14410 | } | |
14411 | else | |
14412 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
14413 | DONE; | |
14414 | }") | |
0ac081f6 | 14415 | |
01a2ccd0 DE |
14416 | (define_insn "prefetch" |
14417 | [(prefetch (match_operand:V4SI 0 "address_operand" "p") | |
6041bf2f DE |
14418 | (match_operand:SI 1 "const_int_operand" "n") |
14419 | (match_operand:SI 2 "const_int_operand" "n"))] | |
01a2ccd0 | 14420 | "TARGET_POWERPC" |
6041bf2f DE |
14421 | "* |
14422 | { | |
01a2ccd0 DE |
14423 | if (GET_CODE (operands[0]) == REG) |
14424 | return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; | |
14425 | return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; | |
6041bf2f DE |
14426 | }" |
14427 | [(set_attr "type" "load")]) | |
a3170dc6 | 14428 | |
10ed84db | 14429 | (include "altivec.md") |
a3170dc6 | 14430 | (include "spe.md") |