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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
d24652ee | 2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
409f61cd | 3 | ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 | 5 | |
5de601cf | 6 | ;; This file is part of GCC. |
1fd4e8c1 | 7 | |
5de601cf NC |
8 | ;; GCC is free software; you can redistribute it and/or modify it |
9 | ;; under the terms of the GNU General Public License as published | |
10 | ;; by the Free Software Foundation; either version 2, or (at your | |
11 | ;; option) any later version. | |
1fd4e8c1 | 12 | |
5de601cf NC |
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | ;; License for more details. | |
1fd4e8c1 RK |
17 | |
18 | ;; You should have received a copy of the GNU General Public License | |
5de601cf NC |
19 | ;; along with GCC; see the file COPYING. If not, write to the |
20 | ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | ;; MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d | 24 | |
615158e2 JJ |
25 | ;; |
26 | ;; UNSPEC usage | |
27 | ;; | |
28 | ||
29 | (define_constants | |
30 | [(UNSPEC_FRSP 0) ; frsp for POWER machines | |
31 | (UNSPEC_TIE 5) ; tie stack contents and stack pointer | |
32 | (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC | |
33 | (UNSPEC_TOC 7) ; address of the TOC (more-or-less) | |
34 | (UNSPEC_MOVSI_GOT 8) | |
35 | (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit | |
36 | (UNSPEC_FCTIWZ 10) | |
37 | (UNSPEC_LD_MPIC 15) ; load_macho_picbase | |
38 | (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic | |
39 | (UNSPEC_TLSGD 17) | |
40 | (UNSPEC_TLSLD 18) | |
41 | (UNSPEC_MOVESI_FROM_CR 19) | |
42 | (UNSPEC_MOVESI_TO_CR 20) | |
43 | (UNSPEC_TLSDTPREL 21) | |
44 | (UNSPEC_TLSDTPRELHA 22) | |
45 | (UNSPEC_TLSDTPRELLO 23) | |
46 | (UNSPEC_TLSGOTDTPREL 24) | |
47 | (UNSPEC_TLSTPREL 25) | |
48 | (UNSPEC_TLSTPRELHA 26) | |
49 | (UNSPEC_TLSTPRELLO 27) | |
50 | (UNSPEC_TLSGOTTPREL 28) | |
51 | (UNSPEC_TLSTLS 29) | |
ecb62ae7 | 52 | (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero |
64022b5d | 53 | (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit |
da4c340c | 54 | (UNSPEC_STFIWX 32) |
915167f5 GK |
55 | (UNSPEC_SYNC 33) |
56 | (UNSPEC_SYNC_OP 34) | |
57 | (UNSPEC_SYNC_SWAP 35) | |
58 | (UNSPEC_LWSYNC 36) | |
59 | (UNSPEC_ISYNC 37) | |
432218ba | 60 | (UNSPEC_POPCNTB 38) |
615158e2 JJ |
61 | ]) |
62 | ||
63 | ;; | |
64 | ;; UNSPEC_VOLATILE usage | |
65 | ;; | |
66 | ||
67 | (define_constants | |
68 | [(UNSPECV_BLOCK 0) | |
69 | (UNSPECV_EH_RR 9) ; eh_reg_restore | |
70 | ]) | |
1fd4e8c1 RK |
71 | \f |
72 | ;; Define an insn type attribute. This is used in function unit delay | |
73 | ;; computations. | |
943c15ed | 74 | (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv" |
1fd4e8c1 RK |
75 | (const_string "integer")) |
76 | ||
b19003d8 | 77 | ;; Length (in bytes). |
6ae08853 | 78 | ; '(pc)' in the following doesn't include the instruction itself; it is |
6cbadf36 | 79 | ; calculated as if the instruction had zero size. |
b19003d8 RK |
80 | (define_attr "length" "" |
81 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 82 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 83 | (const_int -32768)) |
6cbadf36 GK |
84 | (lt (minus (match_dup 0) (pc)) |
85 | (const_int 32764))) | |
39a10a29 GK |
86 | (const_int 4) |
87 | (const_int 8)) | |
b19003d8 RK |
88 | (const_int 4))) |
89 | ||
cfb557c4 RK |
90 | ;; Processor type -- this attribute must exactly match the processor_type |
91 | ;; enumeration in rs6000.h. | |
92 | ||
ec507f2d | 93 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5" |
cfb557c4 RK |
94 | (const (symbol_ref "rs6000_cpu_attr"))) |
95 | ||
b54cf83a DE |
96 | (automata_option "ndfa") |
97 | ||
98 | (include "rios1.md") | |
99 | (include "rios2.md") | |
100 | (include "rs64.md") | |
101 | (include "mpc.md") | |
102 | (include "40x.md") | |
02ca7595 | 103 | (include "440.md") |
b54cf83a DE |
104 | (include "603.md") |
105 | (include "6xx.md") | |
106 | (include "7xx.md") | |
107 | (include "7450.md") | |
5e8006fa | 108 | (include "8540.md") |
b54cf83a | 109 | (include "power4.md") |
ec507f2d | 110 | (include "power5.md") |
48d72335 DE |
111 | |
112 | (include "predicates.md") | |
113 | ||
ac9e2cff | 114 | (include "darwin.md") |
309323c2 | 115 | |
1fd4e8c1 | 116 | \f |
915167f5 GK |
117 | ;; Mode macros |
118 | ||
119 | ; This mode macro allows :GPR to be used to indicate the allowable size | |
120 | ; of whole values in GPRs. | |
121 | (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")]) | |
122 | ||
0354e5d8 | 123 | ; Any supported integer mode. |
915167f5 GK |
124 | (define_mode_macro INT [QI HI SI DI TI]) |
125 | ||
0354e5d8 | 126 | ; Any supported integer mode that fits in one register. |
915167f5 GK |
127 | (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")]) |
128 | ||
0354e5d8 GK |
129 | ; SImode or DImode, even if DImode doesn't fit in GPRs. |
130 | (define_mode_macro SDI [SI DI]) | |
131 | ||
132 | ; The size of a pointer. Also, the size of the value that a record-condition | |
133 | ; (one with a '.') will compare. | |
134 | (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")]) | |
2e6c9641 | 135 | |
915167f5 GK |
136 | ; Various instructions that come in SI and DI forms. |
137 | (define_mode_attr larx [(SI "lwarx") (DI "ldarx")]) | |
138 | (define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")]) | |
0354e5d8 GK |
139 | ; A generic w/d attribute, for things like cmpw/cmpd. |
140 | (define_mode_attr wd [(SI "w") (DI "d")]) | |
915167f5 GK |
141 | |
142 | \f | |
1fd4e8c1 RK |
143 | ;; Start with fixed-point load and store insns. Here we put only the more |
144 | ;; complex forms. Basic data transfer is done later. | |
145 | ||
51b8fc2c RK |
146 | (define_expand "zero_extendqidi2" |
147 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
148 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
149 | "TARGET_POWERPC64" | |
150 | "") | |
151 | ||
152 | (define_insn "" | |
153 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
154 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
155 | "TARGET_POWERPC64" | |
156 | "@ | |
157 | lbz%U1%X1 %0,%1 | |
4371f8af | 158 | rldicl %0,%1,0,56" |
51b8fc2c RK |
159 | [(set_attr "type" "load,*")]) |
160 | ||
161 | (define_insn "" | |
9ebbca7d GK |
162 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
163 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 164 | (const_int 0))) |
9ebbca7d | 165 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 166 | "TARGET_64BIT" |
9ebbca7d GK |
167 | "@ |
168 | rldicl. %2,%1,0,56 | |
169 | #" | |
170 | [(set_attr "type" "compare") | |
171 | (set_attr "length" "4,8")]) | |
172 | ||
173 | (define_split | |
174 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
175 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
176 | (const_int 0))) | |
177 | (clobber (match_scratch:DI 2 ""))] | |
178 | "TARGET_POWERPC64 && reload_completed" | |
179 | [(set (match_dup 2) | |
180 | (zero_extend:DI (match_dup 1))) | |
181 | (set (match_dup 0) | |
182 | (compare:CC (match_dup 2) | |
183 | (const_int 0)))] | |
184 | "") | |
51b8fc2c RK |
185 | |
186 | (define_insn "" | |
9ebbca7d GK |
187 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
188 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 189 | (const_int 0))) |
9ebbca7d | 190 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 191 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 192 | "TARGET_64BIT" |
9ebbca7d GK |
193 | "@ |
194 | rldicl. %0,%1,0,56 | |
195 | #" | |
196 | [(set_attr "type" "compare") | |
197 | (set_attr "length" "4,8")]) | |
198 | ||
199 | (define_split | |
200 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
201 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
202 | (const_int 0))) | |
203 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
204 | (zero_extend:DI (match_dup 1)))] | |
205 | "TARGET_POWERPC64 && reload_completed" | |
206 | [(set (match_dup 0) | |
207 | (zero_extend:DI (match_dup 1))) | |
208 | (set (match_dup 2) | |
209 | (compare:CC (match_dup 0) | |
210 | (const_int 0)))] | |
211 | "") | |
51b8fc2c | 212 | |
2bee0449 RK |
213 | (define_insn "extendqidi2" |
214 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
215 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 216 | "TARGET_POWERPC64" |
2bee0449 | 217 | "extsb %0,%1") |
51b8fc2c RK |
218 | |
219 | (define_insn "" | |
9ebbca7d GK |
220 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
221 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 222 | (const_int 0))) |
9ebbca7d | 223 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 224 | "TARGET_64BIT" |
9ebbca7d GK |
225 | "@ |
226 | extsb. %2,%1 | |
227 | #" | |
228 | [(set_attr "type" "compare") | |
229 | (set_attr "length" "4,8")]) | |
230 | ||
231 | (define_split | |
232 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
233 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
234 | (const_int 0))) | |
235 | (clobber (match_scratch:DI 2 ""))] | |
236 | "TARGET_POWERPC64 && reload_completed" | |
237 | [(set (match_dup 2) | |
238 | (sign_extend:DI (match_dup 1))) | |
239 | (set (match_dup 0) | |
240 | (compare:CC (match_dup 2) | |
241 | (const_int 0)))] | |
242 | "") | |
51b8fc2c RK |
243 | |
244 | (define_insn "" | |
9ebbca7d GK |
245 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
246 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 247 | (const_int 0))) |
9ebbca7d | 248 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 249 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 250 | "TARGET_64BIT" |
9ebbca7d GK |
251 | "@ |
252 | extsb. %0,%1 | |
253 | #" | |
254 | [(set_attr "type" "compare") | |
255 | (set_attr "length" "4,8")]) | |
256 | ||
257 | (define_split | |
258 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
259 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
260 | (const_int 0))) | |
261 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
262 | (sign_extend:DI (match_dup 1)))] | |
263 | "TARGET_POWERPC64 && reload_completed" | |
264 | [(set (match_dup 0) | |
265 | (sign_extend:DI (match_dup 1))) | |
266 | (set (match_dup 2) | |
267 | (compare:CC (match_dup 0) | |
268 | (const_int 0)))] | |
269 | "") | |
51b8fc2c RK |
270 | |
271 | (define_expand "zero_extendhidi2" | |
272 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
273 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
274 | "TARGET_POWERPC64" | |
275 | "") | |
276 | ||
277 | (define_insn "" | |
278 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
279 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
280 | "TARGET_POWERPC64" | |
281 | "@ | |
282 | lhz%U1%X1 %0,%1 | |
4371f8af | 283 | rldicl %0,%1,0,48" |
51b8fc2c RK |
284 | [(set_attr "type" "load,*")]) |
285 | ||
286 | (define_insn "" | |
9ebbca7d GK |
287 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
288 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 289 | (const_int 0))) |
9ebbca7d | 290 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 291 | "TARGET_64BIT" |
9ebbca7d GK |
292 | "@ |
293 | rldicl. %2,%1,0,48 | |
294 | #" | |
295 | [(set_attr "type" "compare") | |
296 | (set_attr "length" "4,8")]) | |
297 | ||
298 | (define_split | |
299 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
300 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
301 | (const_int 0))) | |
302 | (clobber (match_scratch:DI 2 ""))] | |
303 | "TARGET_POWERPC64 && reload_completed" | |
304 | [(set (match_dup 2) | |
305 | (zero_extend:DI (match_dup 1))) | |
306 | (set (match_dup 0) | |
307 | (compare:CC (match_dup 2) | |
308 | (const_int 0)))] | |
309 | "") | |
51b8fc2c RK |
310 | |
311 | (define_insn "" | |
9ebbca7d GK |
312 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
313 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 314 | (const_int 0))) |
9ebbca7d | 315 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 316 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 317 | "TARGET_64BIT" |
9ebbca7d GK |
318 | "@ |
319 | rldicl. %0,%1,0,48 | |
320 | #" | |
321 | [(set_attr "type" "compare") | |
322 | (set_attr "length" "4,8")]) | |
323 | ||
324 | (define_split | |
325 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
326 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
327 | (const_int 0))) | |
328 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
329 | (zero_extend:DI (match_dup 1)))] | |
330 | "TARGET_POWERPC64 && reload_completed" | |
331 | [(set (match_dup 0) | |
332 | (zero_extend:DI (match_dup 1))) | |
333 | (set (match_dup 2) | |
334 | (compare:CC (match_dup 0) | |
335 | (const_int 0)))] | |
336 | "") | |
51b8fc2c RK |
337 | |
338 | (define_expand "extendhidi2" | |
339 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
340 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
341 | "TARGET_POWERPC64" | |
342 | "") | |
343 | ||
344 | (define_insn "" | |
345 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
346 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
347 | "TARGET_POWERPC64" | |
348 | "@ | |
349 | lha%U1%X1 %0,%1 | |
350 | extsh %0,%1" | |
b54cf83a | 351 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
352 | |
353 | (define_insn "" | |
9ebbca7d GK |
354 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
355 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 356 | (const_int 0))) |
9ebbca7d | 357 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 358 | "TARGET_64BIT" |
9ebbca7d GK |
359 | "@ |
360 | extsh. %2,%1 | |
361 | #" | |
362 | [(set_attr "type" "compare") | |
363 | (set_attr "length" "4,8")]) | |
364 | ||
365 | (define_split | |
366 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
367 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
368 | (const_int 0))) | |
369 | (clobber (match_scratch:DI 2 ""))] | |
370 | "TARGET_POWERPC64 && reload_completed" | |
371 | [(set (match_dup 2) | |
372 | (sign_extend:DI (match_dup 1))) | |
373 | (set (match_dup 0) | |
374 | (compare:CC (match_dup 2) | |
375 | (const_int 0)))] | |
376 | "") | |
51b8fc2c RK |
377 | |
378 | (define_insn "" | |
9ebbca7d GK |
379 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
380 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 381 | (const_int 0))) |
9ebbca7d | 382 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 383 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 384 | "TARGET_64BIT" |
9ebbca7d GK |
385 | "@ |
386 | extsh. %0,%1 | |
387 | #" | |
388 | [(set_attr "type" "compare") | |
389 | (set_attr "length" "4,8")]) | |
390 | ||
391 | (define_split | |
392 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
393 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
394 | (const_int 0))) | |
395 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
396 | (sign_extend:DI (match_dup 1)))] | |
397 | "TARGET_POWERPC64 && reload_completed" | |
398 | [(set (match_dup 0) | |
399 | (sign_extend:DI (match_dup 1))) | |
400 | (set (match_dup 2) | |
401 | (compare:CC (match_dup 0) | |
402 | (const_int 0)))] | |
403 | "") | |
51b8fc2c RK |
404 | |
405 | (define_expand "zero_extendsidi2" | |
406 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
407 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
408 | "TARGET_POWERPC64" | |
409 | "") | |
410 | ||
411 | (define_insn "" | |
412 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
413 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
414 | "TARGET_POWERPC64" | |
415 | "@ | |
416 | lwz%U1%X1 %0,%1 | |
417 | rldicl %0,%1,0,32" | |
418 | [(set_attr "type" "load,*")]) | |
419 | ||
420 | (define_insn "" | |
9ebbca7d GK |
421 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
422 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 423 | (const_int 0))) |
9ebbca7d | 424 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 425 | "TARGET_64BIT" |
9ebbca7d GK |
426 | "@ |
427 | rldicl. %2,%1,0,32 | |
428 | #" | |
429 | [(set_attr "type" "compare") | |
430 | (set_attr "length" "4,8")]) | |
431 | ||
432 | (define_split | |
433 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
434 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
435 | (const_int 0))) | |
436 | (clobber (match_scratch:DI 2 ""))] | |
437 | "TARGET_POWERPC64 && reload_completed" | |
438 | [(set (match_dup 2) | |
439 | (zero_extend:DI (match_dup 1))) | |
440 | (set (match_dup 0) | |
441 | (compare:CC (match_dup 2) | |
442 | (const_int 0)))] | |
443 | "") | |
51b8fc2c RK |
444 | |
445 | (define_insn "" | |
9ebbca7d GK |
446 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
447 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 448 | (const_int 0))) |
9ebbca7d | 449 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 450 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 451 | "TARGET_64BIT" |
9ebbca7d GK |
452 | "@ |
453 | rldicl. %0,%1,0,32 | |
454 | #" | |
455 | [(set_attr "type" "compare") | |
456 | (set_attr "length" "4,8")]) | |
457 | ||
458 | (define_split | |
459 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
460 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
461 | (const_int 0))) | |
462 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
463 | (zero_extend:DI (match_dup 1)))] | |
464 | "TARGET_POWERPC64 && reload_completed" | |
465 | [(set (match_dup 0) | |
466 | (zero_extend:DI (match_dup 1))) | |
467 | (set (match_dup 2) | |
468 | (compare:CC (match_dup 0) | |
469 | (const_int 0)))] | |
470 | "") | |
51b8fc2c RK |
471 | |
472 | (define_expand "extendsidi2" | |
473 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
474 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
475 | "TARGET_POWERPC64" | |
476 | "") | |
477 | ||
478 | (define_insn "" | |
479 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 480 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
481 | "TARGET_POWERPC64" |
482 | "@ | |
483 | lwa%U1%X1 %0,%1 | |
484 | extsw %0,%1" | |
b54cf83a | 485 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
486 | |
487 | (define_insn "" | |
9ebbca7d GK |
488 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
489 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 490 | (const_int 0))) |
9ebbca7d | 491 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 492 | "TARGET_64BIT" |
9ebbca7d GK |
493 | "@ |
494 | extsw. %2,%1 | |
495 | #" | |
496 | [(set_attr "type" "compare") | |
497 | (set_attr "length" "4,8")]) | |
498 | ||
499 | (define_split | |
500 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
501 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
502 | (const_int 0))) | |
503 | (clobber (match_scratch:DI 2 ""))] | |
504 | "TARGET_POWERPC64 && reload_completed" | |
505 | [(set (match_dup 2) | |
506 | (sign_extend:DI (match_dup 1))) | |
507 | (set (match_dup 0) | |
508 | (compare:CC (match_dup 2) | |
509 | (const_int 0)))] | |
510 | "") | |
51b8fc2c RK |
511 | |
512 | (define_insn "" | |
9ebbca7d GK |
513 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
514 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 515 | (const_int 0))) |
9ebbca7d | 516 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 517 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 518 | "TARGET_64BIT" |
9ebbca7d GK |
519 | "@ |
520 | extsw. %0,%1 | |
521 | #" | |
522 | [(set_attr "type" "compare") | |
523 | (set_attr "length" "4,8")]) | |
524 | ||
525 | (define_split | |
526 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
527 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
528 | (const_int 0))) | |
529 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
530 | (sign_extend:DI (match_dup 1)))] | |
531 | "TARGET_POWERPC64 && reload_completed" | |
532 | [(set (match_dup 0) | |
533 | (sign_extend:DI (match_dup 1))) | |
534 | (set (match_dup 2) | |
535 | (compare:CC (match_dup 0) | |
536 | (const_int 0)))] | |
537 | "") | |
51b8fc2c | 538 | |
1fd4e8c1 | 539 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
540 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
541 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
542 | "" |
543 | "") | |
544 | ||
545 | (define_insn "" | |
cd2b37d9 | 546 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
547 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
548 | "" | |
549 | "@ | |
550 | lbz%U1%X1 %0,%1 | |
005a35b9 | 551 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
552 | [(set_attr "type" "load,*")]) |
553 | ||
554 | (define_insn "" | |
9ebbca7d GK |
555 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
556 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 557 | (const_int 0))) |
9ebbca7d | 558 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 559 | "" |
9ebbca7d GK |
560 | "@ |
561 | {andil.|andi.} %2,%1,0xff | |
562 | #" | |
563 | [(set_attr "type" "compare") | |
564 | (set_attr "length" "4,8")]) | |
565 | ||
566 | (define_split | |
567 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
568 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
569 | (const_int 0))) | |
570 | (clobber (match_scratch:SI 2 ""))] | |
571 | "reload_completed" | |
572 | [(set (match_dup 2) | |
573 | (zero_extend:SI (match_dup 1))) | |
574 | (set (match_dup 0) | |
575 | (compare:CC (match_dup 2) | |
576 | (const_int 0)))] | |
577 | "") | |
1fd4e8c1 RK |
578 | |
579 | (define_insn "" | |
9ebbca7d GK |
580 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
581 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 582 | (const_int 0))) |
9ebbca7d | 583 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
584 | (zero_extend:SI (match_dup 1)))] |
585 | "" | |
9ebbca7d GK |
586 | "@ |
587 | {andil.|andi.} %0,%1,0xff | |
588 | #" | |
589 | [(set_attr "type" "compare") | |
590 | (set_attr "length" "4,8")]) | |
591 | ||
592 | (define_split | |
593 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
594 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
595 | (const_int 0))) | |
596 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
597 | (zero_extend:SI (match_dup 1)))] | |
598 | "reload_completed" | |
599 | [(set (match_dup 0) | |
600 | (zero_extend:SI (match_dup 1))) | |
601 | (set (match_dup 2) | |
602 | (compare:CC (match_dup 0) | |
603 | (const_int 0)))] | |
604 | "") | |
1fd4e8c1 | 605 | |
51b8fc2c RK |
606 | (define_expand "extendqisi2" |
607 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
608 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
609 | "" | |
610 | " | |
611 | { | |
612 | if (TARGET_POWERPC) | |
613 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
614 | else if (TARGET_POWER) | |
615 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
616 | else | |
617 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
618 | DONE; | |
619 | }") | |
620 | ||
621 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
622 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
623 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 624 | "TARGET_POWERPC" |
2bee0449 | 625 | "extsb %0,%1") |
51b8fc2c RK |
626 | |
627 | (define_insn "" | |
9ebbca7d GK |
628 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
629 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 630 | (const_int 0))) |
9ebbca7d | 631 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 632 | "TARGET_POWERPC" |
9ebbca7d GK |
633 | "@ |
634 | extsb. %2,%1 | |
635 | #" | |
636 | [(set_attr "type" "compare") | |
637 | (set_attr "length" "4,8")]) | |
638 | ||
639 | (define_split | |
640 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
641 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
642 | (const_int 0))) | |
643 | (clobber (match_scratch:SI 2 ""))] | |
644 | "TARGET_POWERPC && reload_completed" | |
645 | [(set (match_dup 2) | |
646 | (sign_extend:SI (match_dup 1))) | |
647 | (set (match_dup 0) | |
648 | (compare:CC (match_dup 2) | |
649 | (const_int 0)))] | |
650 | "") | |
51b8fc2c RK |
651 | |
652 | (define_insn "" | |
9ebbca7d GK |
653 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
654 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 655 | (const_int 0))) |
9ebbca7d | 656 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
657 | (sign_extend:SI (match_dup 1)))] |
658 | "TARGET_POWERPC" | |
9ebbca7d GK |
659 | "@ |
660 | extsb. %0,%1 | |
661 | #" | |
662 | [(set_attr "type" "compare") | |
663 | (set_attr "length" "4,8")]) | |
664 | ||
665 | (define_split | |
666 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
667 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
668 | (const_int 0))) | |
669 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
670 | (sign_extend:SI (match_dup 1)))] | |
671 | "TARGET_POWERPC && reload_completed" | |
672 | [(set (match_dup 0) | |
673 | (sign_extend:SI (match_dup 1))) | |
674 | (set (match_dup 2) | |
675 | (compare:CC (match_dup 0) | |
676 | (const_int 0)))] | |
677 | "") | |
51b8fc2c RK |
678 | |
679 | (define_expand "extendqisi2_power" | |
680 | [(parallel [(set (match_dup 2) | |
681 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
682 | (const_int 24))) | |
683 | (clobber (scratch:SI))]) | |
684 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
685 | (ashiftrt:SI (match_dup 2) | |
686 | (const_int 24))) | |
687 | (clobber (scratch:SI))])] | |
688 | "TARGET_POWER" | |
689 | " | |
690 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
691 | operands[2] = gen_reg_rtx (SImode); }") | |
692 | ||
693 | (define_expand "extendqisi2_no_power" | |
694 | [(set (match_dup 2) | |
695 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
696 | (const_int 24))) | |
697 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
698 | (ashiftrt:SI (match_dup 2) | |
699 | (const_int 24)))] | |
700 | "! TARGET_POWER && ! TARGET_POWERPC" | |
701 | " | |
702 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
703 | operands[2] = gen_reg_rtx (SImode); }") | |
704 | ||
1fd4e8c1 | 705 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
706 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
707 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
708 | "" |
709 | "") | |
710 | ||
711 | (define_insn "" | |
cd2b37d9 | 712 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
713 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
714 | "" | |
715 | "@ | |
716 | lbz%U1%X1 %0,%1 | |
005a35b9 | 717 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
718 | [(set_attr "type" "load,*")]) |
719 | ||
720 | (define_insn "" | |
9ebbca7d GK |
721 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
722 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 723 | (const_int 0))) |
9ebbca7d | 724 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 725 | "" |
9ebbca7d GK |
726 | "@ |
727 | {andil.|andi.} %2,%1,0xff | |
728 | #" | |
729 | [(set_attr "type" "compare") | |
730 | (set_attr "length" "4,8")]) | |
731 | ||
732 | (define_split | |
733 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
734 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
735 | (const_int 0))) | |
736 | (clobber (match_scratch:HI 2 ""))] | |
737 | "reload_completed" | |
738 | [(set (match_dup 2) | |
739 | (zero_extend:HI (match_dup 1))) | |
740 | (set (match_dup 0) | |
741 | (compare:CC (match_dup 2) | |
742 | (const_int 0)))] | |
743 | "") | |
1fd4e8c1 | 744 | |
51b8fc2c | 745 | (define_insn "" |
9ebbca7d GK |
746 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
747 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 748 | (const_int 0))) |
9ebbca7d | 749 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
750 | (zero_extend:HI (match_dup 1)))] |
751 | "" | |
9ebbca7d GK |
752 | "@ |
753 | {andil.|andi.} %0,%1,0xff | |
754 | #" | |
755 | [(set_attr "type" "compare") | |
756 | (set_attr "length" "4,8")]) | |
757 | ||
758 | (define_split | |
759 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
760 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
761 | (const_int 0))) | |
762 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
763 | (zero_extend:HI (match_dup 1)))] | |
764 | "reload_completed" | |
765 | [(set (match_dup 0) | |
766 | (zero_extend:HI (match_dup 1))) | |
767 | (set (match_dup 2) | |
768 | (compare:CC (match_dup 0) | |
769 | (const_int 0)))] | |
770 | "") | |
815cdc52 MM |
771 | |
772 | (define_expand "extendqihi2" | |
773 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
774 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
775 | "" | |
776 | " | |
777 | { | |
778 | if (TARGET_POWERPC) | |
779 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
780 | else if (TARGET_POWER) | |
781 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
782 | else | |
783 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
784 | DONE; | |
785 | }") | |
786 | ||
787 | (define_insn "extendqihi2_ppc" | |
788 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
789 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
790 | "TARGET_POWERPC" | |
791 | "extsb %0,%1") | |
792 | ||
793 | (define_insn "" | |
9ebbca7d GK |
794 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
795 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 796 | (const_int 0))) |
9ebbca7d | 797 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 798 | "TARGET_POWERPC" |
9ebbca7d GK |
799 | "@ |
800 | extsb. %2,%1 | |
801 | #" | |
802 | [(set_attr "type" "compare") | |
803 | (set_attr "length" "4,8")]) | |
804 | ||
805 | (define_split | |
806 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
807 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
808 | (const_int 0))) | |
809 | (clobber (match_scratch:HI 2 ""))] | |
810 | "TARGET_POWERPC && reload_completed" | |
811 | [(set (match_dup 2) | |
812 | (sign_extend:HI (match_dup 1))) | |
813 | (set (match_dup 0) | |
814 | (compare:CC (match_dup 2) | |
815 | (const_int 0)))] | |
816 | "") | |
815cdc52 MM |
817 | |
818 | (define_insn "" | |
9ebbca7d GK |
819 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
820 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 821 | (const_int 0))) |
9ebbca7d | 822 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
823 | (sign_extend:HI (match_dup 1)))] |
824 | "TARGET_POWERPC" | |
9ebbca7d GK |
825 | "@ |
826 | extsb. %0,%1 | |
827 | #" | |
828 | [(set_attr "type" "compare") | |
829 | (set_attr "length" "4,8")]) | |
830 | ||
831 | (define_split | |
832 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
833 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
834 | (const_int 0))) | |
835 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
836 | (sign_extend:HI (match_dup 1)))] | |
837 | "TARGET_POWERPC && reload_completed" | |
838 | [(set (match_dup 0) | |
839 | (sign_extend:HI (match_dup 1))) | |
840 | (set (match_dup 2) | |
841 | (compare:CC (match_dup 0) | |
842 | (const_int 0)))] | |
843 | "") | |
51b8fc2c RK |
844 | |
845 | (define_expand "extendqihi2_power" | |
846 | [(parallel [(set (match_dup 2) | |
847 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
848 | (const_int 24))) | |
849 | (clobber (scratch:SI))]) | |
850 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
851 | (ashiftrt:SI (match_dup 2) | |
852 | (const_int 24))) | |
853 | (clobber (scratch:SI))])] | |
854 | "TARGET_POWER" | |
855 | " | |
856 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
857 | operands[1] = gen_lowpart (SImode, operands[1]); | |
858 | operands[2] = gen_reg_rtx (SImode); }") | |
859 | ||
860 | (define_expand "extendqihi2_no_power" | |
861 | [(set (match_dup 2) | |
862 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
863 | (const_int 24))) | |
864 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
865 | (ashiftrt:SI (match_dup 2) | |
866 | (const_int 24)))] | |
867 | "! TARGET_POWER && ! TARGET_POWERPC" | |
868 | " | |
869 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
870 | operands[1] = gen_lowpart (SImode, operands[1]); | |
871 | operands[2] = gen_reg_rtx (SImode); }") | |
872 | ||
1fd4e8c1 | 873 | (define_expand "zero_extendhisi2" |
5f243543 | 874 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 875 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
876 | "" |
877 | "") | |
878 | ||
879 | (define_insn "" | |
cd2b37d9 | 880 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
881 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
882 | "" | |
883 | "@ | |
884 | lhz%U1%X1 %0,%1 | |
005a35b9 | 885 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
886 | [(set_attr "type" "load,*")]) |
887 | ||
888 | (define_insn "" | |
9ebbca7d GK |
889 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
890 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 891 | (const_int 0))) |
9ebbca7d | 892 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 893 | "" |
9ebbca7d GK |
894 | "@ |
895 | {andil.|andi.} %2,%1,0xffff | |
896 | #" | |
897 | [(set_attr "type" "compare") | |
898 | (set_attr "length" "4,8")]) | |
899 | ||
900 | (define_split | |
901 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
902 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
903 | (const_int 0))) | |
904 | (clobber (match_scratch:SI 2 ""))] | |
905 | "reload_completed" | |
906 | [(set (match_dup 2) | |
907 | (zero_extend:SI (match_dup 1))) | |
908 | (set (match_dup 0) | |
909 | (compare:CC (match_dup 2) | |
910 | (const_int 0)))] | |
911 | "") | |
1fd4e8c1 RK |
912 | |
913 | (define_insn "" | |
9ebbca7d GK |
914 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
915 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 916 | (const_int 0))) |
9ebbca7d | 917 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
918 | (zero_extend:SI (match_dup 1)))] |
919 | "" | |
9ebbca7d GK |
920 | "@ |
921 | {andil.|andi.} %0,%1,0xffff | |
922 | #" | |
923 | [(set_attr "type" "compare") | |
924 | (set_attr "length" "4,8")]) | |
925 | ||
926 | (define_split | |
927 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
928 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
929 | (const_int 0))) | |
930 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
931 | (zero_extend:SI (match_dup 1)))] | |
932 | "reload_completed" | |
933 | [(set (match_dup 0) | |
934 | (zero_extend:SI (match_dup 1))) | |
935 | (set (match_dup 2) | |
936 | (compare:CC (match_dup 0) | |
937 | (const_int 0)))] | |
938 | "") | |
1fd4e8c1 RK |
939 | |
940 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
941 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
942 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
943 | "" |
944 | "") | |
945 | ||
946 | (define_insn "" | |
cd2b37d9 | 947 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
948 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
949 | "" | |
950 | "@ | |
951 | lha%U1%X1 %0,%1 | |
ca7f5001 | 952 | {exts|extsh} %0,%1" |
b54cf83a | 953 | [(set_attr "type" "load_ext,*")]) |
1fd4e8c1 RK |
954 | |
955 | (define_insn "" | |
9ebbca7d GK |
956 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
957 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 958 | (const_int 0))) |
9ebbca7d | 959 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 960 | "" |
9ebbca7d GK |
961 | "@ |
962 | {exts.|extsh.} %2,%1 | |
963 | #" | |
964 | [(set_attr "type" "compare") | |
965 | (set_attr "length" "4,8")]) | |
966 | ||
967 | (define_split | |
968 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
969 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
970 | (const_int 0))) | |
971 | (clobber (match_scratch:SI 2 ""))] | |
972 | "reload_completed" | |
973 | [(set (match_dup 2) | |
974 | (sign_extend:SI (match_dup 1))) | |
975 | (set (match_dup 0) | |
976 | (compare:CC (match_dup 2) | |
977 | (const_int 0)))] | |
978 | "") | |
1fd4e8c1 RK |
979 | |
980 | (define_insn "" | |
9ebbca7d GK |
981 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
982 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 983 | (const_int 0))) |
9ebbca7d | 984 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
985 | (sign_extend:SI (match_dup 1)))] |
986 | "" | |
9ebbca7d GK |
987 | "@ |
988 | {exts.|extsh.} %0,%1 | |
989 | #" | |
990 | [(set_attr "type" "compare") | |
991 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 992 | \f |
9ebbca7d GK |
993 | (define_split |
994 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
995 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
996 | (const_int 0))) | |
997 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
998 | (sign_extend:SI (match_dup 1)))] | |
999 | "reload_completed" | |
1000 | [(set (match_dup 0) | |
1001 | (sign_extend:SI (match_dup 1))) | |
1002 | (set (match_dup 2) | |
1003 | (compare:CC (match_dup 0) | |
1004 | (const_int 0)))] | |
1005 | "") | |
1006 | ||
1fd4e8c1 | 1007 | ;; Fixed-point arithmetic insns. |
deb9225a | 1008 | |
4a6ac6a5 DE |
1009 | (define_mode_attr add_op2 [(SI "reg_or_arith_cint_operand") |
1010 | (DI "reg_or_add_cint64_operand")]) | |
1011 | ||
0354e5d8 GK |
1012 | (define_expand "add<mode>3" |
1013 | [(set (match_operand:SDI 0 "gpc_reg_operand" "") | |
1014 | (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "") | |
4a6ac6a5 | 1015 | (match_operand:SDI 2 "<add_op2>" "")))] |
7cd5235b MM |
1016 | "" |
1017 | " | |
1018 | { | |
0354e5d8 GK |
1019 | if (<MODE>mode == DImode && ! TARGET_POWERPC64) |
1020 | { | |
1021 | if (non_short_cint_operand (operands[2], DImode)) | |
1022 | FAIL; | |
1023 | } | |
1024 | else if (GET_CODE (operands[2]) == CONST_INT | |
1025 | && ! add_operand (operands[2], <MODE>mode)) | |
7cd5235b | 1026 | { |
677a9668 | 1027 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
0354e5d8 | 1028 | ? operands[0] : gen_reg_rtx (<MODE>mode)); |
7cd5235b | 1029 | |
2bfcf297 | 1030 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1031 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
0354e5d8 GK |
1032 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode); |
1033 | ||
1034 | if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L')) | |
1035 | FAIL; | |
7cd5235b | 1036 | |
9ebbca7d GK |
1037 | /* The ordering here is important for the prolog expander. |
1038 | When space is allocated from the stack, adding 'low' first may | |
1039 | produce a temporary deallocation (which would be bad). */ | |
0354e5d8 GK |
1040 | emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest))); |
1041 | emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low))); | |
7cd5235b MM |
1042 | DONE; |
1043 | } | |
1044 | }") | |
1045 | ||
0354e5d8 GK |
1046 | ;; Discourage ai/addic because of carry but provide it in an alternative |
1047 | ;; allowing register zero as source. | |
1048 | (define_insn "*add<mode>3_internal1" | |
1049 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r") | |
1050 | (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b") | |
1051 | (match_operand:GPR 2 "add_operand" "r,I,I,L")))] | |
1fd4e8c1 RK |
1052 | "" |
1053 | "@ | |
deb9225a RK |
1054 | {cax|add} %0,%1,%2 |
1055 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1056 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1057 | {cau|addis} %0,%1,%v2" |
1058 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1059 | |
ee890fe2 SS |
1060 | (define_insn "addsi3_high" |
1061 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1062 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1063 | (high:SI (match_operand 2 "" ""))))] | |
1064 | "TARGET_MACHO && !TARGET_64BIT" | |
1065 | "{cau|addis} %0,%1,ha16(%2)" | |
1066 | [(set_attr "length" "4")]) | |
1067 | ||
0354e5d8 | 1068 | (define_insn "*add<mode>3_internal2" |
cb8cc086 | 1069 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
0354e5d8 GK |
1070 | (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r") |
1071 | (match_operand:P 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1072 | (const_int 0))) |
0354e5d8 GK |
1073 | (clobber (match_scratch:P 3 "=r,r,r,r"))] |
1074 | "" | |
deb9225a RK |
1075 | "@ |
1076 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1077 | {ai.|addic.} %3,%1,%2 |
1078 | # | |
1079 | #" | |
a62bfff2 | 1080 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1081 | (set_attr "length" "4,4,8,8")]) |
1082 | ||
1083 | (define_split | |
1084 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
0354e5d8 GK |
1085 | (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "") |
1086 | (match_operand:GPR 2 "reg_or_short_operand" "")) | |
cb8cc086 | 1087 | (const_int 0))) |
0354e5d8 GK |
1088 | (clobber (match_scratch:GPR 3 ""))] |
1089 | "reload_completed" | |
cb8cc086 | 1090 | [(set (match_dup 3) |
0354e5d8 | 1091 | (plus:GPR (match_dup 1) |
cb8cc086 MM |
1092 | (match_dup 2))) |
1093 | (set (match_dup 0) | |
1094 | (compare:CC (match_dup 3) | |
1095 | (const_int 0)))] | |
1096 | "") | |
7e69e155 | 1097 | |
0354e5d8 | 1098 | (define_insn "*add<mode>3_internal3" |
cb8cc086 | 1099 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
0354e5d8 GK |
1100 | (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r") |
1101 | (match_operand:P 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1102 | (const_int 0))) |
0354e5d8 GK |
1103 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r") |
1104 | (plus:P (match_dup 1) | |
1105 | (match_dup 2)))] | |
1106 | "" | |
deb9225a RK |
1107 | "@ |
1108 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1109 | {ai.|addic.} %0,%1,%2 |
1110 | # | |
1111 | #" | |
a62bfff2 | 1112 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1113 | (set_attr "length" "4,4,8,8")]) |
1114 | ||
1115 | (define_split | |
1116 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
0354e5d8 GK |
1117 | (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "") |
1118 | (match_operand:P 2 "reg_or_short_operand" "")) | |
cb8cc086 | 1119 | (const_int 0))) |
0354e5d8 GK |
1120 | (set (match_operand:P 0 "gpc_reg_operand" "") |
1121 | (plus:P (match_dup 1) (match_dup 2)))] | |
1122 | "reload_completed" | |
cb8cc086 | 1123 | [(set (match_dup 0) |
0354e5d8 GK |
1124 | (plus:P (match_dup 1) |
1125 | (match_dup 2))) | |
cb8cc086 MM |
1126 | (set (match_dup 3) |
1127 | (compare:CC (match_dup 0) | |
1128 | (const_int 0)))] | |
1129 | "") | |
7e69e155 | 1130 | |
f357808b RK |
1131 | ;; Split an add that we can't do in one insn into two insns, each of which |
1132 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1133 | ;; add should be last in case the result gets used in an address. | |
1134 | ||
1135 | (define_split | |
0354e5d8 GK |
1136 | [(set (match_operand:GPR 0 "gpc_reg_operand" "") |
1137 | (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "") | |
1138 | (match_operand:GPR 2 "non_add_cint_operand" "")))] | |
1fd4e8c1 | 1139 | "" |
0354e5d8 GK |
1140 | [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3))) |
1141 | (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))] | |
f357808b | 1142 | " |
1fd4e8c1 | 1143 | { |
2bfcf297 | 1144 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1145 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
0354e5d8 | 1146 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode); |
1fd4e8c1 | 1147 | |
e6ca2c17 | 1148 | operands[4] = GEN_INT (low); |
0354e5d8 GK |
1149 | if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L')) |
1150 | operands[3] = GEN_INT (rest); | |
1151 | else if (! no_new_pseudos) | |
1152 | { | |
1153 | operands[3] = gen_reg_rtx (DImode); | |
1154 | emit_move_insn (operands[3], operands[2]); | |
1155 | emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); | |
1156 | DONE; | |
1157 | } | |
1158 | else | |
1159 | FAIL; | |
1fd4e8c1 RK |
1160 | }") |
1161 | ||
0354e5d8 GK |
1162 | (define_insn "one_cmpl<mode>2" |
1163 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1164 | (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1165 | "" |
ca7f5001 RK |
1166 | "nor %0,%1,%1") |
1167 | ||
1168 | (define_insn "" | |
52d3af72 | 1169 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
0354e5d8 | 1170 | (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r")) |
ca7f5001 | 1171 | (const_int 0))) |
0354e5d8 GK |
1172 | (clobber (match_scratch:P 2 "=r,r"))] |
1173 | "" | |
52d3af72 DE |
1174 | "@ |
1175 | nor. %2,%1,%1 | |
1176 | #" | |
1177 | [(set_attr "type" "compare") | |
1178 | (set_attr "length" "4,8")]) | |
1179 | ||
1180 | (define_split | |
1181 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
0354e5d8 | 1182 | (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "")) |
52d3af72 | 1183 | (const_int 0))) |
0354e5d8 GK |
1184 | (clobber (match_scratch:P 2 ""))] |
1185 | "reload_completed" | |
52d3af72 | 1186 | [(set (match_dup 2) |
0354e5d8 | 1187 | (not:P (match_dup 1))) |
52d3af72 DE |
1188 | (set (match_dup 0) |
1189 | (compare:CC (match_dup 2) | |
1190 | (const_int 0)))] | |
1191 | "") | |
ca7f5001 RK |
1192 | |
1193 | (define_insn "" | |
52d3af72 | 1194 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
0354e5d8 | 1195 | (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r")) |
815cdc52 | 1196 | (const_int 0))) |
0354e5d8 GK |
1197 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r") |
1198 | (not:P (match_dup 1)))] | |
1199 | "" | |
52d3af72 DE |
1200 | "@ |
1201 | nor. %0,%1,%1 | |
1202 | #" | |
1203 | [(set_attr "type" "compare") | |
1204 | (set_attr "length" "4,8")]) | |
1205 | ||
1206 | (define_split | |
1207 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
0354e5d8 | 1208 | (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "")) |
52d3af72 | 1209 | (const_int 0))) |
0354e5d8 GK |
1210 | (set (match_operand:P 0 "gpc_reg_operand" "") |
1211 | (not:P (match_dup 1)))] | |
1212 | "reload_completed" | |
52d3af72 | 1213 | [(set (match_dup 0) |
0354e5d8 | 1214 | (not:P (match_dup 1))) |
52d3af72 DE |
1215 | (set (match_dup 2) |
1216 | (compare:CC (match_dup 0) | |
1217 | (const_int 0)))] | |
1218 | "") | |
1fd4e8c1 RK |
1219 | |
1220 | (define_insn "" | |
3d91674b RK |
1221 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1222 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1223 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1224 | "! TARGET_POWERPC" |
ca7f5001 | 1225 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1226 | |
deb9225a | 1227 | (define_insn "" |
0354e5d8 GK |
1228 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") |
1229 | (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I") | |
1230 | (match_operand:GPR 2 "gpc_reg_operand" "r,r")))] | |
deb9225a RK |
1231 | "TARGET_POWERPC" |
1232 | "@ | |
1233 | subf %0,%2,%1 | |
1234 | subfic %0,%2,%1") | |
1235 | ||
1fd4e8c1 | 1236 | (define_insn "" |
cb8cc086 MM |
1237 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1238 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1239 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1240 | (const_int 0))) |
cb8cc086 | 1241 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1242 | "! TARGET_POWERPC" |
cb8cc086 MM |
1243 | "@ |
1244 | {sf.|subfc.} %3,%2,%1 | |
1245 | #" | |
1246 | [(set_attr "type" "compare") | |
1247 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1248 | |
deb9225a | 1249 | (define_insn "" |
cb8cc086 | 1250 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
0354e5d8 GK |
1251 | (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r") |
1252 | (match_operand:P 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1253 | (const_int 0))) |
0354e5d8 GK |
1254 | (clobber (match_scratch:P 3 "=r,r"))] |
1255 | "TARGET_POWERPC" | |
cb8cc086 MM |
1256 | "@ |
1257 | subf. %3,%2,%1 | |
1258 | #" | |
a62bfff2 | 1259 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1260 | (set_attr "length" "4,8")]) |
1261 | ||
1262 | (define_split | |
1263 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
0354e5d8 GK |
1264 | (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "") |
1265 | (match_operand:P 2 "gpc_reg_operand" "")) | |
cb8cc086 | 1266 | (const_int 0))) |
0354e5d8 GK |
1267 | (clobber (match_scratch:P 3 ""))] |
1268 | "reload_completed" | |
cb8cc086 | 1269 | [(set (match_dup 3) |
0354e5d8 | 1270 | (minus:P (match_dup 1) |
cb8cc086 MM |
1271 | (match_dup 2))) |
1272 | (set (match_dup 0) | |
1273 | (compare:CC (match_dup 3) | |
1274 | (const_int 0)))] | |
1275 | "") | |
deb9225a | 1276 | |
1fd4e8c1 | 1277 | (define_insn "" |
cb8cc086 MM |
1278 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1279 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1280 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1281 | (const_int 0))) |
cb8cc086 | 1282 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1283 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1284 | "! TARGET_POWERPC" |
cb8cc086 MM |
1285 | "@ |
1286 | {sf.|subfc.} %0,%2,%1 | |
1287 | #" | |
1288 | [(set_attr "type" "compare") | |
1289 | (set_attr "length" "4,8")]) | |
815cdc52 | 1290 | |
29ae5b89 | 1291 | (define_insn "" |
cb8cc086 | 1292 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
0354e5d8 GK |
1293 | (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r") |
1294 | (match_operand:P 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1295 | (const_int 0))) |
0354e5d8 GK |
1296 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r") |
1297 | (minus:P (match_dup 1) | |
cb8cc086 | 1298 | (match_dup 2)))] |
0354e5d8 | 1299 | "TARGET_POWERPC" |
90612787 DE |
1300 | "@ |
1301 | subf. %0,%2,%1 | |
1302 | #" | |
a62bfff2 | 1303 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1304 | (set_attr "length" "4,8")]) |
1305 | ||
1306 | (define_split | |
1307 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
0354e5d8 GK |
1308 | (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "") |
1309 | (match_operand:P 2 "gpc_reg_operand" "")) | |
cb8cc086 | 1310 | (const_int 0))) |
0354e5d8 GK |
1311 | (set (match_operand:P 0 "gpc_reg_operand" "") |
1312 | (minus:P (match_dup 1) | |
cb8cc086 | 1313 | (match_dup 2)))] |
0354e5d8 | 1314 | "reload_completed" |
cb8cc086 | 1315 | [(set (match_dup 0) |
0354e5d8 | 1316 | (minus:P (match_dup 1) |
cb8cc086 MM |
1317 | (match_dup 2))) |
1318 | (set (match_dup 3) | |
1319 | (compare:CC (match_dup 0) | |
1320 | (const_int 0)))] | |
1321 | "") | |
deb9225a | 1322 | |
0354e5d8 GK |
1323 | (define_mode_attr sub_op2 [(SI "reg_or_arith_cint_operand") |
1324 | (DI "reg_or_sub_cint64_operand")]) | |
1325 | ||
1326 | (define_expand "sub<mode>3" | |
1327 | [(set (match_operand:SDI 0 "gpc_reg_operand" "") | |
1328 | (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "") | |
1329 | (match_operand:SDI 2 "<sub_op2>" "")))] | |
1fd4e8c1 | 1330 | "" |
a0044fb1 RK |
1331 | " |
1332 | { | |
1333 | if (GET_CODE (operands[2]) == CONST_INT) | |
1334 | { | |
0354e5d8 GK |
1335 | emit_insn (gen_add<mode>3 (operands[0], operands[1], |
1336 | negate_rtx (<MODE>mode, operands[2]))); | |
a0044fb1 RK |
1337 | DONE; |
1338 | } | |
1339 | }") | |
1fd4e8c1 RK |
1340 | |
1341 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1342 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1343 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1344 | ;; combine. | |
1fd4e8c1 RK |
1345 | |
1346 | (define_expand "sminsi3" | |
1347 | [(set (match_dup 3) | |
cd2b37d9 | 1348 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1349 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1350 | (const_int 0) | |
1351 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1352 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1353 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1354 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1355 | " |
a3170dc6 AH |
1356 | { |
1357 | if (TARGET_ISEL) | |
1358 | { | |
1359 | operands[2] = force_reg (SImode, operands[2]); | |
1360 | rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); | |
1361 | DONE; | |
1362 | } | |
1363 | ||
1364 | operands[3] = gen_reg_rtx (SImode); | |
1365 | }") | |
1fd4e8c1 | 1366 | |
95ac8e67 RK |
1367 | (define_split |
1368 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1369 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1370 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1371 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1372 | "TARGET_POWER" |
95ac8e67 RK |
1373 | [(set (match_dup 3) |
1374 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1375 | (const_int 0) | |
1376 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1377 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1378 | "") | |
1379 | ||
1fd4e8c1 RK |
1380 | (define_expand "smaxsi3" |
1381 | [(set (match_dup 3) | |
cd2b37d9 | 1382 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1383 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1384 | (const_int 0) | |
1385 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1386 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1387 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1388 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1389 | " |
a3170dc6 AH |
1390 | { |
1391 | if (TARGET_ISEL) | |
1392 | { | |
1393 | operands[2] = force_reg (SImode, operands[2]); | |
1394 | rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); | |
1395 | DONE; | |
1396 | } | |
1397 | operands[3] = gen_reg_rtx (SImode); | |
1398 | }") | |
1fd4e8c1 | 1399 | |
95ac8e67 RK |
1400 | (define_split |
1401 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1402 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1403 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1404 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1405 | "TARGET_POWER" |
95ac8e67 RK |
1406 | [(set (match_dup 3) |
1407 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1408 | (const_int 0) | |
1409 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1410 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1411 | "") | |
1412 | ||
1fd4e8c1 | 1413 | (define_expand "uminsi3" |
cd2b37d9 | 1414 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1415 | (match_dup 5))) |
cd2b37d9 | 1416 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1417 | (match_dup 5))) |
1fd4e8c1 RK |
1418 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1419 | (const_int 0) | |
1420 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1421 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1422 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1423 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1424 | " |
bb68ff55 | 1425 | { |
a3170dc6 AH |
1426 | if (TARGET_ISEL) |
1427 | { | |
1428 | rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]); | |
1429 | DONE; | |
1430 | } | |
bb68ff55 MM |
1431 | operands[3] = gen_reg_rtx (SImode); |
1432 | operands[4] = gen_reg_rtx (SImode); | |
1433 | operands[5] = GEN_INT (-2147483647 - 1); | |
1434 | }") | |
1fd4e8c1 RK |
1435 | |
1436 | (define_expand "umaxsi3" | |
cd2b37d9 | 1437 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1438 | (match_dup 5))) |
cd2b37d9 | 1439 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1440 | (match_dup 5))) |
1fd4e8c1 RK |
1441 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1442 | (const_int 0) | |
1443 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1444 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1445 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1446 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1447 | " |
bb68ff55 | 1448 | { |
a3170dc6 AH |
1449 | if (TARGET_ISEL) |
1450 | { | |
1451 | rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]); | |
1452 | DONE; | |
1453 | } | |
bb68ff55 MM |
1454 | operands[3] = gen_reg_rtx (SImode); |
1455 | operands[4] = gen_reg_rtx (SImode); | |
1456 | operands[5] = GEN_INT (-2147483647 - 1); | |
1457 | }") | |
1fd4e8c1 RK |
1458 | |
1459 | (define_insn "" | |
cd2b37d9 RK |
1460 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1461 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1462 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1463 | (const_int 0) |
1464 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1465 | "TARGET_POWER" |
1fd4e8c1 RK |
1466 | "doz%I2 %0,%1,%2") |
1467 | ||
1468 | (define_insn "" | |
9ebbca7d | 1469 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1470 | (compare:CC |
9ebbca7d GK |
1471 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1472 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1473 | (const_int 0) |
1474 | (minus:SI (match_dup 2) (match_dup 1))) | |
1475 | (const_int 0))) | |
9ebbca7d | 1476 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 1477 | "TARGET_POWER" |
9ebbca7d GK |
1478 | "@ |
1479 | doz%I2. %3,%1,%2 | |
1480 | #" | |
1481 | [(set_attr "type" "delayed_compare") | |
1482 | (set_attr "length" "4,8")]) | |
1483 | ||
1484 | (define_split | |
1485 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1486 | (compare:CC | |
1487 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1488 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1489 | (const_int 0) | |
1490 | (minus:SI (match_dup 2) (match_dup 1))) | |
1491 | (const_int 0))) | |
1492 | (clobber (match_scratch:SI 3 ""))] | |
1493 | "TARGET_POWER && reload_completed" | |
1494 | [(set (match_dup 3) | |
1495 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1496 | (const_int 0) | |
1497 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1498 | (set (match_dup 0) | |
1499 | (compare:CC (match_dup 3) | |
1500 | (const_int 0)))] | |
1501 | "") | |
1fd4e8c1 RK |
1502 | |
1503 | (define_insn "" | |
9ebbca7d | 1504 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1505 | (compare:CC |
9ebbca7d GK |
1506 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1507 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1508 | (const_int 0) |
1509 | (minus:SI (match_dup 2) (match_dup 1))) | |
1510 | (const_int 0))) | |
9ebbca7d | 1511 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1512 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1513 | (const_int 0) | |
1514 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1515 | "TARGET_POWER" |
9ebbca7d GK |
1516 | "@ |
1517 | doz%I2. %0,%1,%2 | |
1518 | #" | |
1519 | [(set_attr "type" "delayed_compare") | |
1520 | (set_attr "length" "4,8")]) | |
1521 | ||
1522 | (define_split | |
1523 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1524 | (compare:CC | |
1525 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1526 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1527 | (const_int 0) | |
1528 | (minus:SI (match_dup 2) (match_dup 1))) | |
1529 | (const_int 0))) | |
1530 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1531 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1532 | (const_int 0) | |
1533 | (minus:SI (match_dup 2) (match_dup 1))))] | |
1534 | "TARGET_POWER && reload_completed" | |
1535 | [(set (match_dup 0) | |
1536 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1537 | (const_int 0) | |
1538 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1539 | (set (match_dup 3) | |
1540 | (compare:CC (match_dup 0) | |
1541 | (const_int 0)))] | |
1542 | "") | |
1fd4e8c1 RK |
1543 | |
1544 | ;; We don't need abs with condition code because such comparisons should | |
1545 | ;; never be done. | |
ea9be077 MM |
1546 | (define_expand "abssi2" |
1547 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1548 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1549 | "" | |
1550 | " | |
1551 | { | |
a3170dc6 AH |
1552 | if (TARGET_ISEL) |
1553 | { | |
1554 | emit_insn (gen_abssi2_isel (operands[0], operands[1])); | |
1555 | DONE; | |
1556 | } | |
1557 | else if (! TARGET_POWER) | |
ea9be077 MM |
1558 | { |
1559 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1560 | DONE; | |
1561 | } | |
1562 | }") | |
1563 | ||
ea112fc4 | 1564 | (define_insn "*abssi2_power" |
cd2b37d9 RK |
1565 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1566 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1567 | "TARGET_POWER" |
1fd4e8c1 RK |
1568 | "abs %0,%1") |
1569 | ||
a3170dc6 AH |
1570 | (define_insn_and_split "abssi2_isel" |
1571 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1572 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8c48b6f5 | 1573 | (clobber (match_scratch:SI 2 "=&b")) |
a3170dc6 AH |
1574 | (clobber (match_scratch:CC 3 "=y"))] |
1575 | "TARGET_ISEL" | |
1576 | "#" | |
1577 | "&& reload_completed" | |
1578 | [(set (match_dup 2) (neg:SI (match_dup 1))) | |
1579 | (set (match_dup 3) | |
1580 | (compare:CC (match_dup 1) | |
1581 | (const_int 0))) | |
1582 | (set (match_dup 0) | |
1583 | (if_then_else:SI (ge (match_dup 3) | |
1584 | (const_int 0)) | |
1585 | (match_dup 1) | |
1586 | (match_dup 2)))] | |
1587 | "") | |
1588 | ||
ea112fc4 | 1589 | (define_insn_and_split "abssi2_nopower" |
ea9be077 | 1590 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1591 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) |
ea9be077 | 1592 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
a3170dc6 | 1593 | "! TARGET_POWER && ! TARGET_ISEL" |
ea112fc4 DE |
1594 | "#" |
1595 | "&& reload_completed" | |
ea9be077 MM |
1596 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1597 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1598 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1599 | "") |
1600 | ||
463b558b | 1601 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1602 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1603 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1604 | "TARGET_POWER" |
1fd4e8c1 RK |
1605 | "nabs %0,%1") |
1606 | ||
ea112fc4 | 1607 | (define_insn_and_split "*nabs_nopower" |
ea9be077 | 1608 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1609 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) |
ea9be077 | 1610 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
0ad91047 | 1611 | "! TARGET_POWER" |
ea112fc4 DE |
1612 | "#" |
1613 | "&& reload_completed" | |
ea9be077 MM |
1614 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1615 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1616 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1617 | "") |
1618 | ||
0354e5d8 GK |
1619 | (define_expand "neg<mode>2" |
1620 | [(set (match_operand:SDI 0 "gpc_reg_operand" "") | |
1621 | (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))] | |
1622 | "" | |
1623 | "") | |
1624 | ||
1625 | (define_insn "*neg<mode>2_internal" | |
1626 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1627 | (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1628 | "" |
1629 | "neg %0,%1") | |
1630 | ||
1631 | (define_insn "" | |
9ebbca7d | 1632 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
0354e5d8 | 1633 | (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 1634 | (const_int 0))) |
0354e5d8 GK |
1635 | (clobber (match_scratch:P 2 "=r,r"))] |
1636 | "" | |
9ebbca7d GK |
1637 | "@ |
1638 | neg. %2,%1 | |
1639 | #" | |
a62bfff2 | 1640 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1641 | (set_attr "length" "4,8")]) |
1642 | ||
1643 | (define_split | |
1644 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
0354e5d8 | 1645 | (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "")) |
9ebbca7d | 1646 | (const_int 0))) |
0354e5d8 GK |
1647 | (clobber (match_scratch:P 2 ""))] |
1648 | "reload_completed" | |
9ebbca7d | 1649 | [(set (match_dup 2) |
0354e5d8 | 1650 | (neg:P (match_dup 1))) |
9ebbca7d GK |
1651 | (set (match_dup 0) |
1652 | (compare:CC (match_dup 2) | |
1653 | (const_int 0)))] | |
1654 | "") | |
1fd4e8c1 RK |
1655 | |
1656 | (define_insn "" | |
9ebbca7d | 1657 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
0354e5d8 | 1658 | (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r")) |
815cdc52 | 1659 | (const_int 0))) |
0354e5d8 GK |
1660 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r") |
1661 | (neg:P (match_dup 1)))] | |
1662 | "" | |
9ebbca7d GK |
1663 | "@ |
1664 | neg. %0,%1 | |
1665 | #" | |
a62bfff2 | 1666 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1667 | (set_attr "length" "4,8")]) |
1668 | ||
1669 | (define_split | |
1670 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
0354e5d8 | 1671 | (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "")) |
9ebbca7d | 1672 | (const_int 0))) |
0354e5d8 GK |
1673 | (set (match_operand:P 0 "gpc_reg_operand" "") |
1674 | (neg:P (match_dup 1)))] | |
4b8a63d6 | 1675 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 1676 | [(set (match_dup 0) |
0354e5d8 | 1677 | (neg:P (match_dup 1))) |
9ebbca7d GK |
1678 | (set (match_dup 2) |
1679 | (compare:CC (match_dup 0) | |
1680 | (const_int 0)))] | |
1681 | "") | |
1fd4e8c1 | 1682 | |
0354e5d8 GK |
1683 | (define_insn "clz<mode>2" |
1684 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1685 | (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] | |
1b1edcfa | 1686 | "" |
0354e5d8 | 1687 | "{cntlz|cntlz<wd>} %0,%1") |
1b1edcfa | 1688 | |
0354e5d8 | 1689 | (define_expand "ctz<mode>2" |
4977bab6 | 1690 | [(set (match_dup 2) |
0354e5d8 GK |
1691 | (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) |
1692 | (parallel [(set (match_dup 3) (and:GPR (match_dup 1) | |
1693 | (match_dup 2))) | |
1b1edcfa | 1694 | (clobber (scratch:CC))]) |
0354e5d8 GK |
1695 | (set (match_dup 4) (clz:GPR (match_dup 3))) |
1696 | (set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1697 | (minus:GPR (match_dup 5) (match_dup 4)))] | |
1fd4e8c1 | 1698 | "" |
4977bab6 | 1699 | { |
0354e5d8 GK |
1700 | operands[2] = gen_reg_rtx (<MODE>mode); |
1701 | operands[3] = gen_reg_rtx (<MODE>mode); | |
1702 | operands[4] = gen_reg_rtx (<MODE>mode); | |
1703 | operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1); | |
4977bab6 | 1704 | }) |
6ae08853 | 1705 | |
0354e5d8 | 1706 | (define_expand "ffs<mode>2" |
1b1edcfa | 1707 | [(set (match_dup 2) |
0354e5d8 GK |
1708 | (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) |
1709 | (parallel [(set (match_dup 3) (and:GPR (match_dup 1) | |
1710 | (match_dup 2))) | |
1b1edcfa | 1711 | (clobber (scratch:CC))]) |
0354e5d8 GK |
1712 | (set (match_dup 4) (clz:GPR (match_dup 3))) |
1713 | (set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1714 | (minus:GPR (match_dup 5) (match_dup 4)))] | |
4977bab6 | 1715 | "" |
1b1edcfa | 1716 | { |
0354e5d8 GK |
1717 | operands[2] = gen_reg_rtx (<MODE>mode); |
1718 | operands[3] = gen_reg_rtx (<MODE>mode); | |
1719 | operands[4] = gen_reg_rtx (<MODE>mode); | |
1720 | operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)); | |
1b1edcfa | 1721 | }) |
6ae08853 | 1722 | |
432218ba DE |
1723 | (define_expand "popcount<mode>2" |
1724 | [(set (match_dup 2) | |
1725 | (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] | |
1726 | UNSPEC_POPCNTB)) | |
1727 | (set (match_dup 3) | |
1728 | (mult:GPR (match_dup 2) (match_dup 4))) | |
1729 | (set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1730 | (lshiftrt:GPR (match_dup 3) (match_dup 5)))] | |
1731 | "TARGET_POPCNTB" | |
1732 | { | |
1733 | operands[2] = gen_reg_rtx (<MODE>mode); | |
1734 | operands[3] = gen_reg_rtx (<MODE>mode); | |
1e0aa44a DE |
1735 | operands[4] = force_reg (<MODE>mode, |
1736 | <MODE>mode == SImode | |
1737 | ? GEN_INT (0x01010101) | |
1738 | : GEN_INT ((HOST_WIDE_INT) | |
1739 | 0x01010101 << 32 | 0x01010101)); | |
432218ba DE |
1740 | operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8); |
1741 | }) | |
1742 | ||
1743 | (define_insn "popcntb<mode>2" | |
1744 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1745 | (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] | |
1746 | UNSPEC_POPCNTB))] | |
1747 | "TARGET_POPCNTB" | |
1748 | "popcntb %0,%1") | |
1749 | ||
ca7f5001 RK |
1750 | (define_expand "mulsi3" |
1751 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1752 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
1753 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
1754 | "" | |
1755 | " | |
1756 | { | |
1757 | if (TARGET_POWER) | |
68b40e7e | 1758 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 1759 | else |
68b40e7e | 1760 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
1761 | DONE; |
1762 | }") | |
1763 | ||
68b40e7e | 1764 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
1765 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1766 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
1767 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
1768 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
1769 | "TARGET_POWER" |
1770 | "@ | |
1771 | {muls|mullw} %0,%1,%2 | |
1772 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1773 | [(set (attr "type") |
c859cda6 DJ |
1774 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1775 | (const_string "imul3") | |
6ae08853 | 1776 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1777 | (const_string "imul2")] |
1778 | (const_string "imul")))]) | |
ca7f5001 | 1779 | |
68b40e7e | 1780 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
1781 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1782 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1783 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 1784 | "! TARGET_POWER" |
1fd4e8c1 | 1785 | "@ |
d904e9ed RK |
1786 | {muls|mullw} %0,%1,%2 |
1787 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1788 | [(set (attr "type") |
c859cda6 DJ |
1789 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1790 | (const_string "imul3") | |
6ae08853 | 1791 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1792 | (const_string "imul2")] |
1793 | (const_string "imul")))]) | |
1fd4e8c1 | 1794 | |
9259f3b0 | 1795 | (define_insn "*mulsi3_mq_internal1" |
9ebbca7d GK |
1796 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1797 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1798 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1799 | (const_int 0))) |
9ebbca7d GK |
1800 | (clobber (match_scratch:SI 3 "=r,r")) |
1801 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 1802 | "TARGET_POWER" |
9ebbca7d GK |
1803 | "@ |
1804 | {muls.|mullw.} %3,%1,%2 | |
1805 | #" | |
9259f3b0 | 1806 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1807 | (set_attr "length" "4,8")]) |
1808 | ||
1809 | (define_split | |
1810 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1811 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1812 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1813 | (const_int 0))) | |
1814 | (clobber (match_scratch:SI 3 "")) | |
1815 | (clobber (match_scratch:SI 4 ""))] | |
1816 | "TARGET_POWER && reload_completed" | |
1817 | [(parallel [(set (match_dup 3) | |
1818 | (mult:SI (match_dup 1) (match_dup 2))) | |
1819 | (clobber (match_dup 4))]) | |
1820 | (set (match_dup 0) | |
1821 | (compare:CC (match_dup 3) | |
1822 | (const_int 0)))] | |
1823 | "") | |
ca7f5001 | 1824 | |
9259f3b0 | 1825 | (define_insn "*mulsi3_no_mq_internal1" |
9ebbca7d GK |
1826 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1827 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1828 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1829 | (const_int 0))) |
9ebbca7d | 1830 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 1831 | "! TARGET_POWER" |
9ebbca7d GK |
1832 | "@ |
1833 | {muls.|mullw.} %3,%1,%2 | |
1834 | #" | |
9259f3b0 | 1835 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1836 | (set_attr "length" "4,8")]) |
1837 | ||
1838 | (define_split | |
1839 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1840 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1841 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1842 | (const_int 0))) | |
1843 | (clobber (match_scratch:SI 3 ""))] | |
1844 | "! TARGET_POWER && reload_completed" | |
1845 | [(set (match_dup 3) | |
1846 | (mult:SI (match_dup 1) (match_dup 2))) | |
1847 | (set (match_dup 0) | |
1848 | (compare:CC (match_dup 3) | |
1849 | (const_int 0)))] | |
1850 | "") | |
1fd4e8c1 | 1851 | |
9259f3b0 | 1852 | (define_insn "*mulsi3_mq_internal2" |
9ebbca7d GK |
1853 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1854 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1855 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1856 | (const_int 0))) |
9ebbca7d | 1857 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 1858 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 1859 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 1860 | "TARGET_POWER" |
9ebbca7d GK |
1861 | "@ |
1862 | {muls.|mullw.} %0,%1,%2 | |
1863 | #" | |
9259f3b0 | 1864 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1865 | (set_attr "length" "4,8")]) |
1866 | ||
1867 | (define_split | |
1868 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1869 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1870 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1871 | (const_int 0))) | |
1872 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1873 | (mult:SI (match_dup 1) (match_dup 2))) | |
1874 | (clobber (match_scratch:SI 4 ""))] | |
1875 | "TARGET_POWER && reload_completed" | |
1876 | [(parallel [(set (match_dup 0) | |
1877 | (mult:SI (match_dup 1) (match_dup 2))) | |
1878 | (clobber (match_dup 4))]) | |
1879 | (set (match_dup 3) | |
1880 | (compare:CC (match_dup 0) | |
1881 | (const_int 0)))] | |
1882 | "") | |
ca7f5001 | 1883 | |
9259f3b0 | 1884 | (define_insn "*mulsi3_no_mq_internal2" |
9ebbca7d GK |
1885 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1886 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1887 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1888 | (const_int 0))) |
9ebbca7d | 1889 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 1890 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 1891 | "! TARGET_POWER" |
9ebbca7d GK |
1892 | "@ |
1893 | {muls.|mullw.} %0,%1,%2 | |
1894 | #" | |
9259f3b0 | 1895 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1896 | (set_attr "length" "4,8")]) |
1897 | ||
1898 | (define_split | |
1899 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1900 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1901 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1902 | (const_int 0))) | |
1903 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1904 | (mult:SI (match_dup 1) (match_dup 2)))] | |
1905 | "! TARGET_POWER && reload_completed" | |
1906 | [(set (match_dup 0) | |
1907 | (mult:SI (match_dup 1) (match_dup 2))) | |
1908 | (set (match_dup 3) | |
1909 | (compare:CC (match_dup 0) | |
1910 | (const_int 0)))] | |
1911 | "") | |
1fd4e8c1 RK |
1912 | |
1913 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
1914 | ;; 0 and remainder to operand 3. | |
1915 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
1916 | ||
8ffd9c51 RK |
1917 | (define_expand "divmodsi4" |
1918 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1919 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1920 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
bb157ff4 | 1921 | (set (match_operand:SI 3 "register_operand" "") |
8ffd9c51 RK |
1922 | (mod:SI (match_dup 1) (match_dup 2)))])] |
1923 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1924 | " | |
1925 | { | |
1926 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1927 | { | |
39403d82 DE |
1928 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1929 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1930 | emit_insn (gen_divss_call ()); |
39403d82 DE |
1931 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1932 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
1933 | DONE; |
1934 | } | |
1935 | }") | |
deb9225a | 1936 | |
bb157ff4 | 1937 | (define_insn "*divmodsi4_internal" |
cd2b37d9 RK |
1938 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1939 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1940 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
bb157ff4 | 1941 | (set (match_operand:SI 3 "register_operand" "=q") |
1fd4e8c1 | 1942 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 1943 | "TARGET_POWER" |
cfb557c4 RK |
1944 | "divs %0,%1,%2" |
1945 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 1946 | |
8ffd9c51 RK |
1947 | (define_expand "udivsi3" |
1948 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1949 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1950 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
1951 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1952 | " | |
1953 | { | |
1954 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1955 | { | |
39403d82 DE |
1956 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1957 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1958 | emit_insn (gen_quous_call ()); |
39403d82 | 1959 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1960 | DONE; |
1961 | } | |
f192bf8b DE |
1962 | else if (TARGET_POWER) |
1963 | { | |
1964 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
1965 | DONE; | |
1966 | } | |
8ffd9c51 | 1967 | }") |
deb9225a | 1968 | |
f192bf8b DE |
1969 | (define_insn "udivsi3_mq" |
1970 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1971 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1972 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1973 | (clobber (match_scratch:SI 3 "=q"))] | |
1974 | "TARGET_POWERPC && TARGET_POWER" | |
1975 | "divwu %0,%1,%2" | |
1976 | [(set_attr "type" "idiv")]) | |
1977 | ||
1978 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
1979 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1980 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1981 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 1982 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 1983 | "divwu %0,%1,%2" |
ca7f5001 RK |
1984 | [(set_attr "type" "idiv")]) |
1985 | ||
1fd4e8c1 | 1986 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 1987 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
1988 | ;; used; for PowerPC, force operands into register and do a normal divide; |
1989 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 1990 | (define_expand "divsi3" |
cd2b37d9 RK |
1991 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1992 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
1993 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
1994 | "" | |
1995 | " | |
1996 | { | |
ca7f5001 | 1997 | if (GET_CODE (operands[2]) == CONST_INT |
2bfcf297 | 1998 | && INTVAL (operands[2]) > 0 |
ca7f5001 RK |
1999 | && exact_log2 (INTVAL (operands[2])) >= 0) |
2000 | ; | |
b6c9286a | 2001 | else if (TARGET_POWERPC) |
f192bf8b DE |
2002 | { |
2003 | operands[2] = force_reg (SImode, operands[2]); | |
2004 | if (TARGET_POWER) | |
2005 | { | |
2006 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
2007 | DONE; | |
2008 | } | |
2009 | } | |
b6c9286a | 2010 | else if (TARGET_POWER) |
1fd4e8c1 | 2011 | FAIL; |
405c5495 | 2012 | else |
8ffd9c51 | 2013 | { |
39403d82 DE |
2014 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2015 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2016 | emit_insn (gen_quoss_call ()); |
39403d82 | 2017 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2018 | DONE; |
2019 | } | |
1fd4e8c1 RK |
2020 | }") |
2021 | ||
f192bf8b DE |
2022 | (define_insn "divsi3_mq" |
2023 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2024 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2025 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2026 | (clobber (match_scratch:SI 3 "=q"))] | |
2027 | "TARGET_POWERPC && TARGET_POWER" | |
2028 | "divw %0,%1,%2" | |
2029 | [(set_attr "type" "idiv")]) | |
2030 | ||
2031 | (define_insn "*divsi3_no_mq" | |
2032 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2033 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2034 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
2035 | "TARGET_POWERPC && ! TARGET_POWER" | |
2036 | "divw %0,%1,%2" | |
2037 | [(set_attr "type" "idiv")]) | |
2038 | ||
1fd4e8c1 | 2039 | (define_expand "modsi3" |
85644414 RK |
2040 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
2041 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 2042 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 2043 | "" |
1fd4e8c1 RK |
2044 | " |
2045 | { | |
481c7efa | 2046 | int i; |
39b52ba2 RK |
2047 | rtx temp1; |
2048 | rtx temp2; | |
2049 | ||
2bfcf297 | 2050 | if (GET_CODE (operands[2]) != CONST_INT |
a65c591c | 2051 | || INTVAL (operands[2]) <= 0 |
2bfcf297 | 2052 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) |
39b52ba2 RK |
2053 | FAIL; |
2054 | ||
2055 | temp1 = gen_reg_rtx (SImode); | |
2056 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 2057 | |
85644414 | 2058 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 2059 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
2060 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
2061 | DONE; | |
1fd4e8c1 RK |
2062 | }") |
2063 | ||
2064 | (define_insn "" | |
cd2b37d9 RK |
2065 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2066 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
2067 | (match_operand:SI 2 "exact_log2_cint_operand" "N")))] |
2068 | "" | |
ca7f5001 | 2069 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
943c15ed DE |
2070 | [(set_attr "type" "two") |
2071 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
2072 | |
2073 | (define_insn "" | |
9ebbca7d GK |
2074 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2075 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2076 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2077 | (const_int 0))) |
9ebbca7d | 2078 | (clobber (match_scratch:SI 3 "=r,r"))] |
2bfcf297 | 2079 | "" |
9ebbca7d GK |
2080 | "@ |
2081 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
2082 | #" | |
b19003d8 | 2083 | [(set_attr "type" "compare") |
9ebbca7d GK |
2084 | (set_attr "length" "8,12")]) |
2085 | ||
2086 | (define_split | |
2087 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2088 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2089 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2090 | (const_int 0))) |
2091 | (clobber (match_scratch:SI 3 ""))] | |
2bfcf297 | 2092 | "reload_completed" |
9ebbca7d GK |
2093 | [(set (match_dup 3) |
2094 | (div:SI (match_dup 1) (match_dup 2))) | |
2095 | (set (match_dup 0) | |
2096 | (compare:CC (match_dup 3) | |
2097 | (const_int 0)))] | |
2098 | "") | |
1fd4e8c1 RK |
2099 | |
2100 | (define_insn "" | |
9ebbca7d GK |
2101 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2102 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2103 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2104 | (const_int 0))) |
9ebbca7d | 2105 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2106 | (div:SI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 2107 | "" |
9ebbca7d GK |
2108 | "@ |
2109 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2110 | #" | |
b19003d8 | 2111 | [(set_attr "type" "compare") |
9ebbca7d GK |
2112 | (set_attr "length" "8,12")]) |
2113 | ||
2114 | (define_split | |
2115 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2116 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2117 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2118 | (const_int 0))) |
2119 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2120 | (div:SI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2121 | "reload_completed" |
9ebbca7d GK |
2122 | [(set (match_dup 0) |
2123 | (div:SI (match_dup 1) (match_dup 2))) | |
2124 | (set (match_dup 3) | |
2125 | (compare:CC (match_dup 0) | |
2126 | (const_int 0)))] | |
2127 | "") | |
1fd4e8c1 RK |
2128 | |
2129 | (define_insn "" | |
cd2b37d9 | 2130 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2131 | (udiv:SI |
996a5f59 | 2132 | (plus:DI (ashift:DI |
cd2b37d9 | 2133 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2134 | (const_int 32)) |
23a900dc | 2135 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2136 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2137 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2138 | (umod:SI |
996a5f59 | 2139 | (plus:DI (ashift:DI |
1fd4e8c1 | 2140 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2141 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2142 | (match_dup 3)))] |
ca7f5001 | 2143 | "TARGET_POWER" |
cfb557c4 RK |
2144 | "div %0,%1,%3" |
2145 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2146 | |
2147 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2148 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2149 | ;; have to worry about the branches. So make a few subroutines here. | |
2150 | ;; | |
2151 | ;; First comes the normal case. | |
2152 | (define_expand "udivmodsi4_normal" | |
2153 | [(set (match_dup 4) (const_int 0)) | |
2154 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2155 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2156 | (const_int 32)) |
2157 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2158 | (match_operand:SI 2 "" ""))) | |
2159 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2160 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2161 | (const_int 32)) |
2162 | (zero_extend:DI (match_dup 1))) | |
2163 | (match_dup 2)))])] | |
ca7f5001 | 2164 | "TARGET_POWER" |
1fd4e8c1 RK |
2165 | " |
2166 | { operands[4] = gen_reg_rtx (SImode); }") | |
2167 | ||
2168 | ;; This handles the branches. | |
2169 | (define_expand "udivmodsi4_tests" | |
2170 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2171 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2172 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2173 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2174 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2175 | (set (match_dup 0) (const_int 1)) | |
2176 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2177 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2178 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2179 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2180 | "TARGET_POWER" |
1fd4e8c1 RK |
2181 | " |
2182 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2183 | operands[6] = gen_reg_rtx (CCmode); | |
2184 | }") | |
2185 | ||
2186 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2187 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2188 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2189 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2190 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2191 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2192 | "" |
1fd4e8c1 RK |
2193 | " |
2194 | { | |
2195 | rtx label = 0; | |
2196 | ||
8ffd9c51 | 2197 | if (! TARGET_POWER) |
c4d38ccb MM |
2198 | { |
2199 | if (! TARGET_POWERPC) | |
2200 | { | |
39403d82 DE |
2201 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2202 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2203 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2204 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2205 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2206 | DONE; |
2207 | } | |
2208 | else | |
2209 | FAIL; | |
2210 | } | |
0081a354 | 2211 | |
1fd4e8c1 RK |
2212 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2213 | { | |
2214 | operands[2] = force_reg (SImode, operands[2]); | |
2215 | label = gen_label_rtx (); | |
2216 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2217 | operands[3], label)); | |
2218 | } | |
2219 | else | |
2220 | operands[2] = force_reg (SImode, operands[2]); | |
2221 | ||
2222 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2223 | operands[3])); | |
2224 | if (label) | |
2225 | emit_label (label); | |
2226 | ||
2227 | DONE; | |
2228 | }") | |
0081a354 | 2229 | |
fada905b MM |
2230 | ;; AIX architecture-independent common-mode multiply (DImode), |
2231 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2232 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2233 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2234 | ;; assumed unused if generating common-mode, so ignore. | |
2235 | (define_insn "mulh_call" | |
2236 | [(set (reg:SI 3) | |
2237 | (truncate:SI | |
2238 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2239 | (sign_extend:DI (reg:SI 4))) | |
2240 | (const_int 32)))) | |
cf27b467 | 2241 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2242 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2243 | "bla __mulh" |
2244 | [(set_attr "type" "imul")]) | |
fada905b MM |
2245 | |
2246 | (define_insn "mull_call" | |
2247 | [(set (reg:DI 3) | |
2248 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2249 | (sign_extend:DI (reg:SI 4)))) | |
2250 | (clobber (match_scratch:SI 0 "=l")) | |
2251 | (clobber (reg:SI 0))] | |
2252 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2253 | "bla __mull" |
2254 | [(set_attr "type" "imul")]) | |
fada905b MM |
2255 | |
2256 | (define_insn "divss_call" | |
2257 | [(set (reg:SI 3) | |
2258 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2259 | (set (reg:SI 4) | |
2260 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2261 | (clobber (match_scratch:SI 0 "=l")) | |
2262 | (clobber (reg:SI 0))] | |
2263 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2264 | "bla __divss" |
2265 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2266 | |
2267 | (define_insn "divus_call" | |
8ffd9c51 RK |
2268 | [(set (reg:SI 3) |
2269 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2270 | (set (reg:SI 4) | |
2271 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2272 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2273 | (clobber (reg:SI 0)) |
2274 | (clobber (match_scratch:CC 1 "=x")) | |
2275 | (clobber (reg:CC 69))] | |
2276 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2277 | "bla __divus" |
2278 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2279 | |
2280 | (define_insn "quoss_call" | |
2281 | [(set (reg:SI 3) | |
2282 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2283 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2284 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2285 | "bla __quoss" |
2286 | [(set_attr "type" "idiv")]) | |
0081a354 | 2287 | |
fada905b MM |
2288 | (define_insn "quous_call" |
2289 | [(set (reg:SI 3) | |
2290 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2291 | (clobber (match_scratch:SI 0 "=l")) | |
2292 | (clobber (reg:SI 0)) | |
2293 | (clobber (match_scratch:CC 1 "=x")) | |
2294 | (clobber (reg:CC 69))] | |
2295 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2296 | "bla __quous" |
2297 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2298 | \f |
bb21487f | 2299 | ;; Logical instructions |
dfbdccdb GK |
2300 | ;; The logical instructions are mostly combined by using match_operator, |
2301 | ;; but the plain AND insns are somewhat different because there is no | |
2302 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2303 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2304 | ||
29ae5b89 JL |
2305 | (define_insn "andsi3" |
2306 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2307 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2308 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2309 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2310 | "" |
2311 | "@ | |
2312 | and %0,%1,%2 | |
ca7f5001 RK |
2313 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2314 | {andil.|andi.} %0,%1,%b2 | |
520308bc DE |
2315 | {andiu.|andis.} %0,%1,%u2" |
2316 | [(set_attr "type" "*,*,compare,compare")]) | |
52d3af72 DE |
2317 | |
2318 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
0ba1b2ff | 2319 | ;; the test again -- this avoids a mfcr which on the higher end |
52d3af72 | 2320 | ;; machines causes an execution serialization |
1fd4e8c1 | 2321 | |
7cd5235b | 2322 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2323 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2324 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2325 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2326 | (const_int 0))) |
52d3af72 DE |
2327 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2328 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2329 | "TARGET_32BIT" |
1fd4e8c1 RK |
2330 | "@ |
2331 | and. %3,%1,%2 | |
ca7f5001 RK |
2332 | {andil.|andi.} %3,%1,%b2 |
2333 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2334 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2335 | # | |
2336 | # | |
2337 | # | |
2338 | #" | |
2339 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2340 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2341 | |
0ba1b2ff AM |
2342 | (define_insn "*andsi3_internal3" |
2343 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2344 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2345 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2346 | (const_int 0))) | |
2347 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) | |
2348 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2349 | "TARGET_64BIT" |
0ba1b2ff AM |
2350 | "@ |
2351 | # | |
2352 | {andil.|andi.} %3,%1,%b2 | |
2353 | {andiu.|andis.} %3,%1,%u2 | |
2354 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 | |
2355 | # | |
2356 | # | |
2357 | # | |
2358 | #" | |
2359 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2360 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2361 | ||
52d3af72 DE |
2362 | (define_split |
2363 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2364 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2365 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 2366 | (const_int 0))) |
52d3af72 DE |
2367 | (clobber (match_scratch:SI 3 "")) |
2368 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2369 | "reload_completed" |
52d3af72 DE |
2370 | [(parallel [(set (match_dup 3) |
2371 | (and:SI (match_dup 1) | |
2372 | (match_dup 2))) | |
2373 | (clobber (match_dup 4))]) | |
2374 | (set (match_dup 0) | |
2375 | (compare:CC (match_dup 3) | |
2376 | (const_int 0)))] | |
2377 | "") | |
2378 | ||
0ba1b2ff AM |
2379 | ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the |
2380 | ;; whole 64 bit reg, and we don't know what is in the high 32 bits. | |
2381 | ||
2382 | (define_split | |
2383 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
2384 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2385 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2386 | (const_int 0))) | |
2387 | (clobber (match_scratch:SI 3 "")) | |
2388 | (clobber (match_scratch:CC 4 ""))] | |
2389 | "TARGET_POWERPC64 && reload_completed" | |
2390 | [(parallel [(set (match_dup 3) | |
2391 | (and:SI (match_dup 1) | |
2392 | (match_dup 2))) | |
2393 | (clobber (match_dup 4))]) | |
2394 | (set (match_dup 0) | |
2395 | (compare:CC (match_dup 3) | |
2396 | (const_int 0)))] | |
2397 | "") | |
2398 | ||
2399 | (define_insn "*andsi3_internal4" | |
52d3af72 DE |
2400 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2401 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2402 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2403 | (const_int 0))) |
2404 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2405 | (and:SI (match_dup 1) | |
2406 | (match_dup 2))) | |
2407 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2408 | "TARGET_32BIT" |
1fd4e8c1 RK |
2409 | "@ |
2410 | and. %0,%1,%2 | |
ca7f5001 RK |
2411 | {andil.|andi.} %0,%1,%b2 |
2412 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2413 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2414 | # | |
2415 | # | |
2416 | # | |
2417 | #" | |
2418 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2419 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2420 | ||
0ba1b2ff AM |
2421 | (define_insn "*andsi3_internal5" |
2422 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2423 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2424 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2425 | (const_int 0))) | |
2426 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2427 | (and:SI (match_dup 1) | |
2428 | (match_dup 2))) | |
2429 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2430 | "TARGET_64BIT" |
0ba1b2ff AM |
2431 | "@ |
2432 | # | |
2433 | {andil.|andi.} %0,%1,%b2 | |
2434 | {andiu.|andis.} %0,%1,%u2 | |
2435 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 | |
2436 | # | |
2437 | # | |
2438 | # | |
2439 | #" | |
2440 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2441 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2442 | ||
52d3af72 DE |
2443 | (define_split |
2444 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2445 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2446 | (match_operand:SI 2 "and_operand" "")) | |
2447 | (const_int 0))) | |
2448 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2449 | (and:SI (match_dup 1) | |
2450 | (match_dup 2))) | |
2451 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2452 | "reload_completed" |
52d3af72 DE |
2453 | [(parallel [(set (match_dup 0) |
2454 | (and:SI (match_dup 1) | |
2455 | (match_dup 2))) | |
2456 | (clobber (match_dup 4))]) | |
2457 | (set (match_dup 3) | |
2458 | (compare:CC (match_dup 0) | |
2459 | (const_int 0)))] | |
2460 | "") | |
1fd4e8c1 | 2461 | |
0ba1b2ff AM |
2462 | (define_split |
2463 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
2464 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2465 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2466 | (const_int 0))) | |
2467 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2468 | (and:SI (match_dup 1) | |
2469 | (match_dup 2))) | |
2470 | (clobber (match_scratch:CC 4 ""))] | |
2471 | "TARGET_POWERPC64 && reload_completed" | |
2472 | [(parallel [(set (match_dup 0) | |
2473 | (and:SI (match_dup 1) | |
2474 | (match_dup 2))) | |
2475 | (clobber (match_dup 4))]) | |
2476 | (set (match_dup 3) | |
2477 | (compare:CC (match_dup 0) | |
2478 | (const_int 0)))] | |
2479 | "") | |
2480 | ||
2481 | ;; Handle the PowerPC64 rlwinm corner case | |
2482 | ||
2483 | (define_insn_and_split "*andsi3_internal6" | |
2484 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2485 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2486 | (match_operand:SI 2 "mask_operand_wrap" "i")))] | |
2487 | "TARGET_POWERPC64" | |
2488 | "#" | |
2489 | "TARGET_POWERPC64" | |
2490 | [(set (match_dup 0) | |
2491 | (and:SI (rotate:SI (match_dup 1) (match_dup 3)) | |
2492 | (match_dup 4))) | |
2493 | (set (match_dup 0) | |
2494 | (rotate:SI (match_dup 0) (match_dup 5)))] | |
2495 | " | |
2496 | { | |
2497 | int mb = extract_MB (operands[2]); | |
2498 | int me = extract_ME (operands[2]); | |
2499 | operands[3] = GEN_INT (me + 1); | |
2500 | operands[5] = GEN_INT (32 - (me + 1)); | |
2501 | operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2502 | }" | |
2503 | [(set_attr "length" "8")]) | |
2504 | ||
7cd5235b | 2505 | (define_expand "iorsi3" |
cd2b37d9 | 2506 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2507 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2508 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 2509 | "" |
f357808b RK |
2510 | " |
2511 | { | |
7cd5235b | 2512 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2513 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2514 | { |
2515 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2516 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2517 | ? operands[0] : gen_reg_rtx (SImode)); |
2518 | ||
a260abc9 DE |
2519 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2520 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2521 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2522 | DONE; |
2523 | } | |
f357808b RK |
2524 | }") |
2525 | ||
7cd5235b | 2526 | (define_expand "xorsi3" |
cd2b37d9 | 2527 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2528 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2529 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 2530 | "" |
7cd5235b | 2531 | " |
1fd4e8c1 | 2532 | { |
7cd5235b | 2533 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2534 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2535 | { |
2536 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2537 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2538 | ? operands[0] : gen_reg_rtx (SImode)); |
2539 | ||
a260abc9 DE |
2540 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2541 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2542 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2543 | DONE; |
2544 | } | |
1fd4e8c1 RK |
2545 | }") |
2546 | ||
dfbdccdb | 2547 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2548 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 2549 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2550 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
2551 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2552 | "" |
2553 | "@ | |
dfbdccdb GK |
2554 | %q3 %0,%1,%2 |
2555 | {%q3il|%q3i} %0,%1,%b2 | |
2556 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2557 | |
dfbdccdb | 2558 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2559 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 2560 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
2561 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
2562 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2563 | (const_int 0))) | |
52d3af72 | 2564 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2565 | "TARGET_32BIT" |
52d3af72 | 2566 | "@ |
dfbdccdb | 2567 | %q4. %3,%1,%2 |
52d3af72 DE |
2568 | #" |
2569 | [(set_attr "type" "compare") | |
2570 | (set_attr "length" "4,8")]) | |
2571 | ||
2572 | (define_split | |
2573 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2574 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2575 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2576 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2577 | (const_int 0))) |
52d3af72 | 2578 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2579 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2580 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2581 | (set (match_dup 0) |
2582 | (compare:CC (match_dup 3) | |
2583 | (const_int 0)))] | |
2584 | "") | |
815cdc52 | 2585 | |
dfbdccdb | 2586 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2587 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2588 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2589 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2590 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2591 | (const_int 0))) | |
52d3af72 | 2592 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2593 | (match_dup 4))] |
4b8a63d6 | 2594 | "TARGET_32BIT" |
52d3af72 | 2595 | "@ |
dfbdccdb | 2596 | %q4. %0,%1,%2 |
52d3af72 DE |
2597 | #" |
2598 | [(set_attr "type" "compare") | |
2599 | (set_attr "length" "4,8")]) | |
2600 | ||
2601 | (define_split | |
e72247f4 | 2602 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2603 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2604 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2605 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2606 | (const_int 0))) |
75540af0 | 2607 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2608 | (match_dup 4))] |
4b8a63d6 | 2609 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2610 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2611 | (set (match_dup 3) |
2612 | (compare:CC (match_dup 0) | |
2613 | (const_int 0)))] | |
2614 | "") | |
1fd4e8c1 | 2615 | |
6ae08853 | 2616 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 2617 | ;; each of which does one 16-bit part. This is used by combine. |
a260abc9 DE |
2618 | |
2619 | (define_split | |
2620 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 2621 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2622 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2623 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 2624 | "" |
dfbdccdb GK |
2625 | [(set (match_dup 0) (match_dup 4)) |
2626 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
2627 | " |
2628 | { | |
dfbdccdb GK |
2629 | rtx i; |
2630 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
1c563bed | 2631 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2632 | operands[1], i); |
dfbdccdb | 2633 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); |
1c563bed | 2634 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2635 | operands[0], i); |
a260abc9 DE |
2636 | }") |
2637 | ||
dfbdccdb | 2638 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 2639 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2640 | (match_operator:SI 3 "boolean_operator" |
2641 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2642 | (match_operand:SI 2 "gpc_reg_operand" "r")]))] |
1fd4e8c1 | 2643 | "" |
dfbdccdb | 2644 | "%q3 %0,%2,%1") |
1fd4e8c1 | 2645 | |
dfbdccdb | 2646 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 2647 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2648 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2649 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2650 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2651 | (const_int 0))) | |
52d3af72 | 2652 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2653 | "TARGET_32BIT" |
52d3af72 | 2654 | "@ |
dfbdccdb | 2655 | %q4. %3,%2,%1 |
52d3af72 DE |
2656 | #" |
2657 | [(set_attr "type" "compare") | |
2658 | (set_attr "length" "4,8")]) | |
2659 | ||
2660 | (define_split | |
2661 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2662 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2663 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2664 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2665 | (const_int 0))) |
52d3af72 | 2666 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2667 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2668 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2669 | (set (match_dup 0) |
2670 | (compare:CC (match_dup 3) | |
2671 | (const_int 0)))] | |
2672 | "") | |
1fd4e8c1 | 2673 | |
dfbdccdb | 2674 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 2675 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2676 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2677 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2678 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2679 | (const_int 0))) | |
52d3af72 | 2680 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2681 | (match_dup 4))] |
4b8a63d6 | 2682 | "TARGET_32BIT" |
52d3af72 | 2683 | "@ |
dfbdccdb | 2684 | %q4. %0,%2,%1 |
52d3af72 DE |
2685 | #" |
2686 | [(set_attr "type" "compare") | |
2687 | (set_attr "length" "4,8")]) | |
2688 | ||
2689 | (define_split | |
e72247f4 | 2690 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2691 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2692 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2693 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2694 | (const_int 0))) |
75540af0 | 2695 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2696 | (match_dup 4))] |
4b8a63d6 | 2697 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2698 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2699 | (set (match_dup 3) |
2700 | (compare:CC (match_dup 0) | |
2701 | (const_int 0)))] | |
2702 | "") | |
2703 | ||
dfbdccdb | 2704 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 2705 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2706 | (match_operator:SI 3 "boolean_operator" |
2707 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2708 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] |
1fd4e8c1 | 2709 | "" |
dfbdccdb | 2710 | "%q3 %0,%1,%2") |
1fd4e8c1 | 2711 | |
dfbdccdb | 2712 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 2713 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2714 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2715 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2716 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2717 | (const_int 0))) | |
52d3af72 | 2718 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2719 | "TARGET_32BIT" |
52d3af72 | 2720 | "@ |
dfbdccdb | 2721 | %q4. %3,%1,%2 |
52d3af72 DE |
2722 | #" |
2723 | [(set_attr "type" "compare") | |
2724 | (set_attr "length" "4,8")]) | |
2725 | ||
2726 | (define_split | |
2727 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2728 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2729 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2730 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2731 | (const_int 0))) |
52d3af72 | 2732 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2733 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2734 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2735 | (set (match_dup 0) |
2736 | (compare:CC (match_dup 3) | |
2737 | (const_int 0)))] | |
2738 | "") | |
1fd4e8c1 | 2739 | |
dfbdccdb | 2740 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 2741 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2742 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2743 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2744 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2745 | (const_int 0))) | |
52d3af72 | 2746 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2747 | (match_dup 4))] |
4b8a63d6 | 2748 | "TARGET_32BIT" |
52d3af72 | 2749 | "@ |
dfbdccdb | 2750 | %q4. %0,%1,%2 |
52d3af72 DE |
2751 | #" |
2752 | [(set_attr "type" "compare") | |
2753 | (set_attr "length" "4,8")]) | |
2754 | ||
2755 | (define_split | |
e72247f4 | 2756 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2757 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2758 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2759 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2760 | (const_int 0))) |
75540af0 | 2761 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2762 | (match_dup 4))] |
4b8a63d6 | 2763 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2764 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2765 | (set (match_dup 3) |
2766 | (compare:CC (match_dup 0) | |
2767 | (const_int 0)))] | |
2768 | "") | |
1fd4e8c1 RK |
2769 | |
2770 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2771 | ;; orders. Don't define forms that only set CR fields because these | |
2772 | ;; would modify an input register. | |
2773 | ||
7cd5235b | 2774 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2775 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2776 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2777 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2778 | (and:SI (match_dup 2) | |
cd2b37d9 | 2779 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2780 | "TARGET_POWER" |
01def764 | 2781 | "maskir %0,%3,%2") |
1fd4e8c1 | 2782 | |
7cd5235b | 2783 | (define_insn "*maskir_internal2" |
242e8072 | 2784 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2785 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2786 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2787 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2788 | (match_dup 2))))] |
ca7f5001 | 2789 | "TARGET_POWER" |
01def764 | 2790 | "maskir %0,%3,%2") |
1fd4e8c1 | 2791 | |
7cd5235b | 2792 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2793 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2794 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2795 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2796 | (and:SI (not:SI (match_dup 2)) |
2797 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2798 | "TARGET_POWER" |
01def764 | 2799 | "maskir %0,%3,%2") |
1fd4e8c1 | 2800 | |
7cd5235b | 2801 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2802 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2803 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2804 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2805 | (and:SI (not:SI (match_dup 2)) | |
2806 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2807 | "TARGET_POWER" |
01def764 | 2808 | "maskir %0,%3,%2") |
1fd4e8c1 | 2809 | |
7cd5235b | 2810 | (define_insn "*maskir_internal5" |
9ebbca7d | 2811 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2812 | (compare:CC |
9ebbca7d GK |
2813 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2814 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 2815 | (and:SI (match_dup 2) |
9ebbca7d | 2816 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 2817 | (const_int 0))) |
9ebbca7d | 2818 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2819 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2820 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2821 | "TARGET_POWER" |
9ebbca7d GK |
2822 | "@ |
2823 | maskir. %0,%3,%2 | |
2824 | #" | |
2825 | [(set_attr "type" "compare") | |
2826 | (set_attr "length" "4,8")]) | |
2827 | ||
2828 | (define_split | |
2829 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2830 | (compare:CC | |
2831 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2832 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2833 | (and:SI (match_dup 2) | |
2834 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
2835 | (const_int 0))) | |
2836 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2837 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2838 | (and:SI (match_dup 2) (match_dup 3))))] | |
2839 | "TARGET_POWER && reload_completed" | |
2840 | [(set (match_dup 0) | |
2841 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2842 | (and:SI (match_dup 2) (match_dup 3)))) | |
2843 | (set (match_dup 4) | |
2844 | (compare:CC (match_dup 0) | |
2845 | (const_int 0)))] | |
2846 | "") | |
1fd4e8c1 | 2847 | |
7cd5235b | 2848 | (define_insn "*maskir_internal6" |
9ebbca7d | 2849 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2850 | (compare:CC |
9ebbca7d GK |
2851 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2852 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
2853 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 2854 | (match_dup 2))) |
1fd4e8c1 | 2855 | (const_int 0))) |
9ebbca7d | 2856 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2857 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2858 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 2859 | "TARGET_POWER" |
9ebbca7d GK |
2860 | "@ |
2861 | maskir. %0,%3,%2 | |
2862 | #" | |
2863 | [(set_attr "type" "compare") | |
2864 | (set_attr "length" "4,8")]) | |
2865 | ||
2866 | (define_split | |
2867 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2868 | (compare:CC | |
2869 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2870 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2871 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2872 | (match_dup 2))) | |
2873 | (const_int 0))) | |
2874 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2875 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2876 | (and:SI (match_dup 3) (match_dup 2))))] | |
2877 | "TARGET_POWER && reload_completed" | |
2878 | [(set (match_dup 0) | |
2879 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2880 | (and:SI (match_dup 3) (match_dup 2)))) | |
2881 | (set (match_dup 4) | |
2882 | (compare:CC (match_dup 0) | |
2883 | (const_int 0)))] | |
2884 | "") | |
1fd4e8c1 | 2885 | |
7cd5235b | 2886 | (define_insn "*maskir_internal7" |
9ebbca7d | 2887 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 2888 | (compare:CC |
9ebbca7d GK |
2889 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
2890 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2891 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2892 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 2893 | (const_int 0))) |
9ebbca7d | 2894 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
2895 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
2896 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2897 | "TARGET_POWER" | |
9ebbca7d GK |
2898 | "@ |
2899 | maskir. %0,%3,%2 | |
2900 | #" | |
2901 | [(set_attr "type" "compare") | |
2902 | (set_attr "length" "4,8")]) | |
2903 | ||
2904 | (define_split | |
2905 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2906 | (compare:CC | |
2907 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
2908 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
2909 | (and:SI (not:SI (match_dup 2)) | |
2910 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2911 | (const_int 0))) | |
2912 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2913 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2914 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2915 | "TARGET_POWER && reload_completed" | |
2916 | [(set (match_dup 0) | |
2917 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2918 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2919 | (set (match_dup 4) | |
2920 | (compare:CC (match_dup 0) | |
2921 | (const_int 0)))] | |
2922 | "") | |
1fd4e8c1 | 2923 | |
7cd5235b | 2924 | (define_insn "*maskir_internal8" |
9ebbca7d | 2925 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2926 | (compare:CC |
9ebbca7d GK |
2927 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
2928 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 2929 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2930 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 2931 | (const_int 0))) |
9ebbca7d | 2932 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2933 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
2934 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 2935 | "TARGET_POWER" |
9ebbca7d GK |
2936 | "@ |
2937 | maskir. %0,%3,%2 | |
2938 | #" | |
2939 | [(set_attr "type" "compare") | |
2940 | (set_attr "length" "4,8")]) | |
fcce224d | 2941 | |
9ebbca7d GK |
2942 | (define_split |
2943 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2944 | (compare:CC | |
2945 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2946 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2947 | (and:SI (not:SI (match_dup 2)) | |
2948 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2949 | (const_int 0))) | |
2950 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2951 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2952 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2953 | "TARGET_POWER && reload_completed" | |
2954 | [(set (match_dup 0) | |
2955 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2956 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2957 | (set (match_dup 4) | |
2958 | (compare:CC (match_dup 0) | |
2959 | (const_int 0)))] | |
2960 | "") | |
fcce224d | 2961 | \f |
1fd4e8c1 RK |
2962 | ;; Rotate and shift insns, in all their variants. These support shifts, |
2963 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 2964 | (define_expand "insv" |
0ad91047 DE |
2965 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
2966 | (match_operand:SI 1 "const_int_operand" "") | |
2967 | (match_operand:SI 2 "const_int_operand" "")) | |
2968 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
2969 | "" |
2970 | " | |
2971 | { | |
2972 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2973 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2974 | compiler if the address of the structure is taken later. */ | |
2975 | if (GET_CODE (operands[0]) == SUBREG | |
2976 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2977 | FAIL; | |
a78e33fc DE |
2978 | |
2979 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
2980 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
2981 | else | |
2982 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
2983 | DONE; | |
034c1be0 MM |
2984 | }") |
2985 | ||
a78e33fc | 2986 | (define_insn "insvsi" |
cd2b37d9 | 2987 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
2988 | (match_operand:SI 1 "const_int_operand" "i") |
2989 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 2990 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
2991 | "" |
2992 | "* | |
2993 | { | |
2994 | int start = INTVAL (operands[2]) & 31; | |
2995 | int size = INTVAL (operands[1]) & 31; | |
2996 | ||
89e9f3a8 MM |
2997 | operands[4] = GEN_INT (32 - start - size); |
2998 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2999 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
3000 | }" |
3001 | [(set_attr "type" "insert_word")]) | |
1fd4e8c1 | 3002 | |
a78e33fc | 3003 | (define_insn "*insvsi_internal1" |
d56d506a RK |
3004 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3005 | (match_operand:SI 1 "const_int_operand" "i") | |
3006 | (match_operand:SI 2 "const_int_operand" "i")) | |
3007 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3008 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3009 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3010 | "* |
3011 | { | |
3012 | int shift = INTVAL (operands[4]) & 31; | |
3013 | int start = INTVAL (operands[2]) & 31; | |
3014 | int size = INTVAL (operands[1]) & 31; | |
3015 | ||
89e9f3a8 MM |
3016 | operands[4] = GEN_INT (shift - start - size); |
3017 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3018 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
3019 | }" |
3020 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3021 | |
a78e33fc | 3022 | (define_insn "*insvsi_internal2" |
d56d506a RK |
3023 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3024 | (match_operand:SI 1 "const_int_operand" "i") | |
3025 | (match_operand:SI 2 "const_int_operand" "i")) | |
3026 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3027 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3028 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3029 | "* |
3030 | { | |
3031 | int shift = INTVAL (operands[4]) & 31; | |
3032 | int start = INTVAL (operands[2]) & 31; | |
3033 | int size = INTVAL (operands[1]) & 31; | |
3034 | ||
89e9f3a8 MM |
3035 | operands[4] = GEN_INT (32 - shift - start - size); |
3036 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3037 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
3038 | }" |
3039 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3040 | |
a78e33fc | 3041 | (define_insn "*insvsi_internal3" |
d56d506a RK |
3042 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3043 | (match_operand:SI 1 "const_int_operand" "i") | |
3044 | (match_operand:SI 2 "const_int_operand" "i")) | |
3045 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3046 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 3047 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3048 | "* |
3049 | { | |
3050 | int shift = INTVAL (operands[4]) & 31; | |
3051 | int start = INTVAL (operands[2]) & 31; | |
3052 | int size = INTVAL (operands[1]) & 31; | |
3053 | ||
89e9f3a8 MM |
3054 | operands[4] = GEN_INT (32 - shift - start - size); |
3055 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3056 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
3057 | }" |
3058 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3059 | |
a78e33fc | 3060 | (define_insn "*insvsi_internal4" |
d56d506a RK |
3061 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3062 | (match_operand:SI 1 "const_int_operand" "i") | |
3063 | (match_operand:SI 2 "const_int_operand" "i")) | |
3064 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3065 | (match_operand:SI 4 "const_int_operand" "i") | |
3066 | (match_operand:SI 5 "const_int_operand" "i")))] | |
3067 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
3068 | "* | |
3069 | { | |
3070 | int extract_start = INTVAL (operands[5]) & 31; | |
3071 | int extract_size = INTVAL (operands[4]) & 31; | |
3072 | int insert_start = INTVAL (operands[2]) & 31; | |
3073 | int insert_size = INTVAL (operands[1]) & 31; | |
3074 | ||
3075 | /* Align extract field with insert field */ | |
3a598fbe | 3076 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 3077 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 3078 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
8e8238f1 DE |
3079 | }" |
3080 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3081 | |
f241bf89 EC |
3082 | ;; combine patterns for rlwimi |
3083 | (define_insn "*insvsi_internal5" | |
3084 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3085 | (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") | |
3086 | (match_operand:SI 1 "mask_operand" "i")) | |
3087 | (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3088 | (match_operand:SI 2 "const_int_operand" "i")) | |
3089 | (match_operand:SI 5 "mask_operand" "i"))))] | |
3090 | "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" | |
3091 | "* | |
3092 | { | |
3093 | int me = extract_ME(operands[5]); | |
3094 | int mb = extract_MB(operands[5]); | |
3095 | operands[4] = GEN_INT(32 - INTVAL(operands[2])); | |
3096 | operands[2] = GEN_INT(mb); | |
3097 | operands[1] = GEN_INT(me); | |
3098 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; | |
3099 | }" | |
3100 | [(set_attr "type" "insert_word")]) | |
3101 | ||
3102 | (define_insn "*insvsi_internal6" | |
3103 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3104 | (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3105 | (match_operand:SI 2 "const_int_operand" "i")) | |
3106 | (match_operand:SI 5 "mask_operand" "i")) | |
3107 | (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") | |
3108 | (match_operand:SI 1 "mask_operand" "i"))))] | |
3109 | "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" | |
3110 | "* | |
3111 | { | |
3112 | int me = extract_ME(operands[5]); | |
3113 | int mb = extract_MB(operands[5]); | |
3114 | operands[4] = GEN_INT(32 - INTVAL(operands[2])); | |
3115 | operands[2] = GEN_INT(mb); | |
3116 | operands[1] = GEN_INT(me); | |
3117 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; | |
3118 | }" | |
3119 | [(set_attr "type" "insert_word")]) | |
3120 | ||
a78e33fc | 3121 | (define_insn "insvdi" |
685f3906 | 3122 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3123 | (match_operand:SI 1 "const_int_operand" "i") |
3124 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3125 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3126 | "TARGET_POWERPC64" | |
3127 | "* | |
3128 | { | |
3129 | int start = INTVAL (operands[2]) & 63; | |
3130 | int size = INTVAL (operands[1]) & 63; | |
3131 | ||
a78e33fc DE |
3132 | operands[1] = GEN_INT (64 - start - size); |
3133 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3134 | }") |
3135 | ||
11ac38b2 DE |
3136 | (define_insn "*insvdi_internal2" |
3137 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
3138 | (match_operand:SI 1 "const_int_operand" "i") | |
3139 | (match_operand:SI 2 "const_int_operand" "i")) | |
3140 | (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") | |
3141 | (match_operand:SI 4 "const_int_operand" "i")))] | |
3142 | "TARGET_POWERPC64 | |
3143 | && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" | |
3144 | "* | |
3145 | { | |
3146 | int shift = INTVAL (operands[4]) & 63; | |
3147 | int start = (INTVAL (operands[2]) & 63) - 32; | |
3148 | int size = INTVAL (operands[1]) & 63; | |
3149 | ||
3150 | operands[4] = GEN_INT (64 - shift - start - size); | |
3151 | operands[2] = GEN_INT (start); | |
3152 | operands[1] = GEN_INT (start + size - 1); | |
3153 | return \"rlwimi %0,%3,%h4,%h2,%h1\"; | |
3154 | }") | |
3155 | ||
3156 | (define_insn "*insvdi_internal3" | |
3157 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
3158 | (match_operand:SI 1 "const_int_operand" "i") | |
3159 | (match_operand:SI 2 "const_int_operand" "i")) | |
3160 | (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") | |
3161 | (match_operand:SI 4 "const_int_operand" "i")))] | |
3162 | "TARGET_POWERPC64 | |
3163 | && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" | |
3164 | "* | |
3165 | { | |
3166 | int shift = INTVAL (operands[4]) & 63; | |
3167 | int start = (INTVAL (operands[2]) & 63) - 32; | |
3168 | int size = INTVAL (operands[1]) & 63; | |
3169 | ||
3170 | operands[4] = GEN_INT (64 - shift - start - size); | |
3171 | operands[2] = GEN_INT (start); | |
3172 | operands[1] = GEN_INT (start + size - 1); | |
3173 | return \"rlwimi %0,%3,%h4,%h2,%h1\"; | |
3174 | }") | |
3175 | ||
034c1be0 | 3176 | (define_expand "extzv" |
0ad91047 DE |
3177 | [(set (match_operand 0 "gpc_reg_operand" "") |
3178 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3179 | (match_operand:SI 2 "const_int_operand" "") | |
3180 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3181 | "" |
3182 | " | |
3183 | { | |
3184 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3185 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3186 | compiler if the address of the structure is taken later. */ | |
3187 | if (GET_CODE (operands[0]) == SUBREG | |
3188 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3189 | FAIL; | |
a78e33fc DE |
3190 | |
3191 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3192 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3193 | else | |
3194 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3195 | DONE; | |
034c1be0 MM |
3196 | }") |
3197 | ||
a78e33fc | 3198 | (define_insn "extzvsi" |
cd2b37d9 RK |
3199 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3200 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3201 | (match_operand:SI 2 "const_int_operand" "i") |
3202 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3203 | "" | |
3204 | "* | |
3205 | { | |
3206 | int start = INTVAL (operands[3]) & 31; | |
3207 | int size = INTVAL (operands[2]) & 31; | |
3208 | ||
3209 | if (start + size >= 32) | |
3210 | operands[3] = const0_rtx; | |
3211 | else | |
89e9f3a8 | 3212 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3213 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3214 | }") |
3215 | ||
a78e33fc | 3216 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3217 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3218 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3219 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3220 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3221 | (const_int 0))) |
9ebbca7d | 3222 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3223 | "" |
1fd4e8c1 RK |
3224 | "* |
3225 | { | |
3226 | int start = INTVAL (operands[3]) & 31; | |
3227 | int size = INTVAL (operands[2]) & 31; | |
3228 | ||
9ebbca7d GK |
3229 | /* Force split for non-cc0 compare. */ |
3230 | if (which_alternative == 1) | |
3231 | return \"#\"; | |
3232 | ||
43a88a8c | 3233 | /* If the bit-field being tested fits in the upper or lower half of a |
a7a975e1 RK |
3234 | word, it is possible to use andiu. or andil. to test it. This is |
3235 | useful because the condition register set-use delay is smaller for | |
3236 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3237 | position is 0 because the LT and GT bits may be set wrong. */ | |
3238 | ||
3239 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3240 | { |
3a598fbe | 3241 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3242 | - (1 << (16 - (start & 15) - size)))); |
3243 | if (start < 16) | |
ca7f5001 | 3244 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3245 | else |
ca7f5001 | 3246 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3247 | } |
7e69e155 | 3248 | |
1fd4e8c1 RK |
3249 | if (start + size >= 32) |
3250 | operands[3] = const0_rtx; | |
3251 | else | |
89e9f3a8 | 3252 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3253 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3254 | }" |
9ebbca7d GK |
3255 | [(set_attr "type" "compare") |
3256 | (set_attr "length" "4,8")]) | |
3257 | ||
3258 | (define_split | |
3259 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3260 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3261 | (match_operand:SI 2 "const_int_operand" "") | |
3262 | (match_operand:SI 3 "const_int_operand" "")) | |
3263 | (const_int 0))) | |
3264 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3265 | "reload_completed" |
9ebbca7d GK |
3266 | [(set (match_dup 4) |
3267 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3268 | (match_dup 3))) | |
3269 | (set (match_dup 0) | |
3270 | (compare:CC (match_dup 4) | |
3271 | (const_int 0)))] | |
3272 | "") | |
1fd4e8c1 | 3273 | |
a78e33fc | 3274 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3275 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3276 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3277 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3278 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3279 | (const_int 0))) |
9ebbca7d | 3280 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3281 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
ce71f754 | 3282 | "" |
1fd4e8c1 RK |
3283 | "* |
3284 | { | |
3285 | int start = INTVAL (operands[3]) & 31; | |
3286 | int size = INTVAL (operands[2]) & 31; | |
3287 | ||
9ebbca7d GK |
3288 | /* Force split for non-cc0 compare. */ |
3289 | if (which_alternative == 1) | |
3290 | return \"#\"; | |
3291 | ||
bc401279 | 3292 | /* Since we are using the output value, we can't ignore any need for |
43a88a8c | 3293 | a shift. The bit-field must end at the LSB. */ |
bc401279 | 3294 | if (start >= 16 && start + size == 32) |
df031c43 | 3295 | { |
bc401279 AM |
3296 | operands[3] = GEN_INT ((1 << size) - 1); |
3297 | return \"{andil.|andi.} %0,%1,%3\"; | |
df031c43 | 3298 | } |
7e69e155 | 3299 | |
1fd4e8c1 RK |
3300 | if (start + size >= 32) |
3301 | operands[3] = const0_rtx; | |
3302 | else | |
89e9f3a8 | 3303 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3304 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3305 | }" |
ce71f754 | 3306 | [(set_attr "type" "compare") |
9ebbca7d GK |
3307 | (set_attr "length" "4,8")]) |
3308 | ||
3309 | (define_split | |
3310 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3311 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3312 | (match_operand:SI 2 "const_int_operand" "") | |
3313 | (match_operand:SI 3 "const_int_operand" "")) | |
3314 | (const_int 0))) | |
3315 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3316 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
ce71f754 | 3317 | "reload_completed" |
9ebbca7d GK |
3318 | [(set (match_dup 0) |
3319 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3320 | (set (match_dup 4) | |
3321 | (compare:CC (match_dup 0) | |
3322 | (const_int 0)))] | |
3323 | "") | |
1fd4e8c1 | 3324 | |
a78e33fc | 3325 | (define_insn "extzvdi" |
685f3906 DE |
3326 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3327 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3328 | (match_operand:SI 2 "const_int_operand" "i") |
3329 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3330 | "TARGET_POWERPC64" |
3331 | "* | |
3332 | { | |
3333 | int start = INTVAL (operands[3]) & 63; | |
3334 | int size = INTVAL (operands[2]) & 63; | |
3335 | ||
3336 | if (start + size >= 64) | |
3337 | operands[3] = const0_rtx; | |
3338 | else | |
89e9f3a8 MM |
3339 | operands[3] = GEN_INT (start + size); |
3340 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3341 | return \"rldicl %0,%1,%3,%2\"; |
3342 | }") | |
3343 | ||
a78e33fc | 3344 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3345 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3346 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3347 | (match_operand:SI 2 "const_int_operand" "i") |
3348 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3349 | (const_int 0))) |
29ae5b89 | 3350 | (clobber (match_scratch:DI 4 "=r"))] |
683bdff7 | 3351 | "TARGET_64BIT" |
685f3906 DE |
3352 | "* |
3353 | { | |
3354 | int start = INTVAL (operands[3]) & 63; | |
3355 | int size = INTVAL (operands[2]) & 63; | |
3356 | ||
3357 | if (start + size >= 64) | |
3358 | operands[3] = const0_rtx; | |
3359 | else | |
89e9f3a8 MM |
3360 | operands[3] = GEN_INT (start + size); |
3361 | operands[2] = GEN_INT (64 - size); | |
685f3906 | 3362 | return \"rldicl. %4,%1,%3,%2\"; |
9a3c428b DE |
3363 | }" |
3364 | [(set_attr "type" "compare")]) | |
685f3906 | 3365 | |
a78e33fc | 3366 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3367 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3368 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3369 | (match_operand:SI 2 "const_int_operand" "i") |
3370 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3371 | (const_int 0))) |
29ae5b89 | 3372 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 | 3373 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
683bdff7 | 3374 | "TARGET_64BIT" |
685f3906 DE |
3375 | "* |
3376 | { | |
3377 | int start = INTVAL (operands[3]) & 63; | |
3378 | int size = INTVAL (operands[2]) & 63; | |
3379 | ||
3380 | if (start + size >= 64) | |
3381 | operands[3] = const0_rtx; | |
3382 | else | |
89e9f3a8 MM |
3383 | operands[3] = GEN_INT (start + size); |
3384 | operands[2] = GEN_INT (64 - size); | |
685f3906 | 3385 | return \"rldicl. %0,%1,%3,%2\"; |
9a3c428b DE |
3386 | }" |
3387 | [(set_attr "type" "compare")]) | |
685f3906 | 3388 | |
1fd4e8c1 | 3389 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3390 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3391 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3392 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3393 | "" | |
ca7f5001 | 3394 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3395 | |
a260abc9 | 3396 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3397 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3398 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3399 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3400 | (const_int 0))) |
9ebbca7d | 3401 | (clobber (match_scratch:SI 3 "=r,r"))] |
ce71f754 | 3402 | "" |
9ebbca7d GK |
3403 | "@ |
3404 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3405 | #" | |
3406 | [(set_attr "type" "delayed_compare") | |
3407 | (set_attr "length" "4,8")]) | |
3408 | ||
3409 | (define_split | |
3410 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3411 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3412 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3413 | (const_int 0))) | |
3414 | (clobber (match_scratch:SI 3 ""))] | |
ce71f754 | 3415 | "reload_completed" |
9ebbca7d GK |
3416 | [(set (match_dup 3) |
3417 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3418 | (set (match_dup 0) | |
3419 | (compare:CC (match_dup 3) | |
3420 | (const_int 0)))] | |
3421 | "") | |
1fd4e8c1 | 3422 | |
a260abc9 | 3423 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3424 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3425 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3426 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3427 | (const_int 0))) |
9ebbca7d | 3428 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3429 | (rotate:SI (match_dup 1) (match_dup 2)))] |
ce71f754 | 3430 | "" |
9ebbca7d GK |
3431 | "@ |
3432 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3433 | #" | |
3434 | [(set_attr "type" "delayed_compare") | |
3435 | (set_attr "length" "4,8")]) | |
3436 | ||
3437 | (define_split | |
3438 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3439 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3440 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3441 | (const_int 0))) | |
3442 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3443 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
ce71f754 | 3444 | "reload_completed" |
9ebbca7d GK |
3445 | [(set (match_dup 0) |
3446 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3447 | (set (match_dup 3) | |
3448 | (compare:CC (match_dup 0) | |
3449 | (const_int 0)))] | |
3450 | "") | |
1fd4e8c1 | 3451 | |
a260abc9 | 3452 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3453 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3454 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3455 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
ce71f754 | 3456 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3457 | "" |
ca7f5001 | 3458 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3459 | |
a260abc9 | 3460 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3461 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3462 | (compare:CC (and:SI |
9ebbca7d GK |
3463 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3464 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3465 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3466 | (const_int 0))) |
9ebbca7d | 3467 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3468 | "" |
9ebbca7d GK |
3469 | "@ |
3470 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3471 | #" | |
3472 | [(set_attr "type" "delayed_compare") | |
3473 | (set_attr "length" "4,8")]) | |
3474 | ||
3475 | (define_split | |
3476 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3477 | (compare:CC (and:SI | |
3478 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3479 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3480 | (match_operand:SI 3 "mask_operand" "")) | |
3481 | (const_int 0))) | |
3482 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3483 | "reload_completed" |
9ebbca7d GK |
3484 | [(set (match_dup 4) |
3485 | (and:SI (rotate:SI (match_dup 1) | |
3486 | (match_dup 2)) | |
3487 | (match_dup 3))) | |
3488 | (set (match_dup 0) | |
3489 | (compare:CC (match_dup 4) | |
3490 | (const_int 0)))] | |
3491 | "") | |
1fd4e8c1 | 3492 | |
a260abc9 | 3493 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3494 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3495 | (compare:CC (and:SI |
9ebbca7d GK |
3496 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3497 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3498 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3499 | (const_int 0))) |
9ebbca7d | 3500 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3501 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3502 | "" |
9ebbca7d GK |
3503 | "@ |
3504 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3505 | #" | |
3506 | [(set_attr "type" "delayed_compare") | |
3507 | (set_attr "length" "4,8")]) | |
3508 | ||
3509 | (define_split | |
3510 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3511 | (compare:CC (and:SI | |
3512 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3513 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3514 | (match_operand:SI 3 "mask_operand" "")) | |
3515 | (const_int 0))) | |
3516 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3517 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3518 | "reload_completed" |
9ebbca7d GK |
3519 | [(set (match_dup 0) |
3520 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3521 | (set (match_dup 4) | |
3522 | (compare:CC (match_dup 0) | |
3523 | (const_int 0)))] | |
3524 | "") | |
1fd4e8c1 | 3525 | |
a260abc9 | 3526 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3527 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3528 | (zero_extend:SI |
3529 | (subreg:QI | |
cd2b37d9 | 3530 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3531 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3532 | "" | |
ca7f5001 | 3533 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3534 | |
a260abc9 | 3535 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3536 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3537 | (compare:CC (zero_extend:SI |
3538 | (subreg:QI | |
9ebbca7d GK |
3539 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3540 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3541 | (const_int 0))) |
9ebbca7d | 3542 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3543 | "" |
9ebbca7d GK |
3544 | "@ |
3545 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3546 | #" | |
3547 | [(set_attr "type" "delayed_compare") | |
3548 | (set_attr "length" "4,8")]) | |
3549 | ||
3550 | (define_split | |
3551 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3552 | (compare:CC (zero_extend:SI | |
3553 | (subreg:QI | |
3554 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3555 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3556 | (const_int 0))) | |
3557 | (clobber (match_scratch:SI 3 ""))] | |
3558 | "reload_completed" | |
3559 | [(set (match_dup 3) | |
3560 | (zero_extend:SI (subreg:QI | |
3561 | (rotate:SI (match_dup 1) | |
3562 | (match_dup 2)) 0))) | |
3563 | (set (match_dup 0) | |
3564 | (compare:CC (match_dup 3) | |
3565 | (const_int 0)))] | |
3566 | "") | |
1fd4e8c1 | 3567 | |
a260abc9 | 3568 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3569 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3570 | (compare:CC (zero_extend:SI |
3571 | (subreg:QI | |
9ebbca7d GK |
3572 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3573 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3574 | (const_int 0))) |
9ebbca7d | 3575 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3576 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3577 | "" | |
9ebbca7d GK |
3578 | "@ |
3579 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3580 | #" | |
3581 | [(set_attr "type" "delayed_compare") | |
3582 | (set_attr "length" "4,8")]) | |
3583 | ||
3584 | (define_split | |
3585 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3586 | (compare:CC (zero_extend:SI | |
3587 | (subreg:QI | |
3588 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3589 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3590 | (const_int 0))) | |
3591 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3592 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3593 | "reload_completed" | |
3594 | [(set (match_dup 0) | |
3595 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3596 | (set (match_dup 3) | |
3597 | (compare:CC (match_dup 0) | |
3598 | (const_int 0)))] | |
3599 | "") | |
1fd4e8c1 | 3600 | |
a260abc9 | 3601 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3602 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3603 | (zero_extend:SI |
3604 | (subreg:HI | |
cd2b37d9 | 3605 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3606 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3607 | "" | |
ca7f5001 | 3608 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3609 | |
a260abc9 | 3610 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3611 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3612 | (compare:CC (zero_extend:SI |
3613 | (subreg:HI | |
9ebbca7d GK |
3614 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3615 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3616 | (const_int 0))) |
9ebbca7d | 3617 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3618 | "" |
9ebbca7d GK |
3619 | "@ |
3620 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3621 | #" | |
3622 | [(set_attr "type" "delayed_compare") | |
3623 | (set_attr "length" "4,8")]) | |
3624 | ||
3625 | (define_split | |
3626 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3627 | (compare:CC (zero_extend:SI | |
3628 | (subreg:HI | |
3629 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3630 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3631 | (const_int 0))) | |
3632 | (clobber (match_scratch:SI 3 ""))] | |
3633 | "reload_completed" | |
3634 | [(set (match_dup 3) | |
3635 | (zero_extend:SI (subreg:HI | |
3636 | (rotate:SI (match_dup 1) | |
3637 | (match_dup 2)) 0))) | |
3638 | (set (match_dup 0) | |
3639 | (compare:CC (match_dup 3) | |
3640 | (const_int 0)))] | |
3641 | "") | |
1fd4e8c1 | 3642 | |
a260abc9 | 3643 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3644 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3645 | (compare:CC (zero_extend:SI |
3646 | (subreg:HI | |
9ebbca7d GK |
3647 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3648 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3649 | (const_int 0))) |
9ebbca7d | 3650 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3651 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3652 | "" | |
9ebbca7d GK |
3653 | "@ |
3654 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3655 | #" | |
3656 | [(set_attr "type" "delayed_compare") | |
3657 | (set_attr "length" "4,8")]) | |
3658 | ||
3659 | (define_split | |
3660 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3661 | (compare:CC (zero_extend:SI | |
3662 | (subreg:HI | |
3663 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3664 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3665 | (const_int 0))) | |
3666 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3667 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3668 | "reload_completed" | |
3669 | [(set (match_dup 0) | |
3670 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3671 | (set (match_dup 3) | |
3672 | (compare:CC (match_dup 0) | |
3673 | (const_int 0)))] | |
3674 | "") | |
1fd4e8c1 RK |
3675 | |
3676 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3677 | ;; SHIFT_COUNT_TRUNCATED. | |
3678 | ||
ca7f5001 RK |
3679 | (define_expand "ashlsi3" |
3680 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3681 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3682 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3683 | "" | |
3684 | " | |
3685 | { | |
3686 | if (TARGET_POWER) | |
3687 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3688 | else | |
25c341fa | 3689 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3690 | DONE; |
3691 | }") | |
3692 | ||
3693 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3694 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3695 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3696 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3697 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3698 | "TARGET_POWER" |
1fd4e8c1 RK |
3699 | "@ |
3700 | sle %0,%1,%2 | |
9ebbca7d | 3701 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3702 | |
25c341fa | 3703 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3704 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3705 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3706 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3707 | "! TARGET_POWER" |
9ebbca7d | 3708 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3709 | |
3710 | (define_insn "" | |
9ebbca7d GK |
3711 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3712 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3713 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3714 | (const_int 0))) |
9ebbca7d GK |
3715 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
3716 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 3717 | "TARGET_POWER" |
1fd4e8c1 RK |
3718 | "@ |
3719 | sle. %3,%1,%2 | |
9ebbca7d GK |
3720 | {sli.|slwi.} %3,%1,%h2 |
3721 | # | |
3722 | #" | |
3723 | [(set_attr "type" "delayed_compare") | |
3724 | (set_attr "length" "4,4,8,8")]) | |
3725 | ||
3726 | (define_split | |
3727 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3728 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3729 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3730 | (const_int 0))) | |
3731 | (clobber (match_scratch:SI 3 "")) | |
3732 | (clobber (match_scratch:SI 4 ""))] | |
3733 | "TARGET_POWER && reload_completed" | |
3734 | [(parallel [(set (match_dup 3) | |
3735 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3736 | (clobber (match_dup 4))]) | |
3737 | (set (match_dup 0) | |
3738 | (compare:CC (match_dup 3) | |
3739 | (const_int 0)))] | |
3740 | "") | |
25c341fa | 3741 | |
ca7f5001 | 3742 | (define_insn "" |
9ebbca7d GK |
3743 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3744 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3745 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3746 | (const_int 0))) |
9ebbca7d | 3747 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 3748 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3749 | "@ |
3750 | {sl|slw}%I2. %3,%1,%h2 | |
3751 | #" | |
3752 | [(set_attr "type" "delayed_compare") | |
3753 | (set_attr "length" "4,8")]) | |
3754 | ||
3755 | (define_split | |
3756 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3757 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3758 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3759 | (const_int 0))) | |
3760 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3761 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3762 | [(set (match_dup 3) |
3763 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3764 | (set (match_dup 0) | |
3765 | (compare:CC (match_dup 3) | |
3766 | (const_int 0)))] | |
3767 | "") | |
1fd4e8c1 RK |
3768 | |
3769 | (define_insn "" | |
9ebbca7d GK |
3770 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3771 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3772 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3773 | (const_int 0))) |
9ebbca7d | 3774 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 3775 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3776 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 3777 | "TARGET_POWER" |
1fd4e8c1 RK |
3778 | "@ |
3779 | sle. %0,%1,%2 | |
9ebbca7d GK |
3780 | {sli.|slwi.} %0,%1,%h2 |
3781 | # | |
3782 | #" | |
3783 | [(set_attr "type" "delayed_compare") | |
3784 | (set_attr "length" "4,4,8,8")]) | |
3785 | ||
3786 | (define_split | |
3787 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3788 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3789 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3790 | (const_int 0))) | |
3791 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3792 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3793 | (clobber (match_scratch:SI 4 ""))] | |
3794 | "TARGET_POWER && reload_completed" | |
3795 | [(parallel [(set (match_dup 0) | |
3796 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3797 | (clobber (match_dup 4))]) | |
3798 | (set (match_dup 3) | |
3799 | (compare:CC (match_dup 0) | |
3800 | (const_int 0)))] | |
3801 | "") | |
25c341fa | 3802 | |
ca7f5001 | 3803 | (define_insn "" |
9ebbca7d GK |
3804 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3805 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3806 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3807 | (const_int 0))) |
9ebbca7d | 3808 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 3809 | (ashift:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 3810 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3811 | "@ |
3812 | {sl|slw}%I2. %0,%1,%h2 | |
3813 | #" | |
3814 | [(set_attr "type" "delayed_compare") | |
3815 | (set_attr "length" "4,8")]) | |
3816 | ||
3817 | (define_split | |
3818 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3819 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3820 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3821 | (const_int 0))) | |
3822 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3823 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 3824 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3825 | [(set (match_dup 0) |
3826 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3827 | (set (match_dup 3) | |
3828 | (compare:CC (match_dup 0) | |
3829 | (const_int 0)))] | |
3830 | "") | |
1fd4e8c1 | 3831 | |
915167f5 | 3832 | (define_insn "rlwinm" |
cd2b37d9 RK |
3833 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3834 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3835 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3836 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3837 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 3838 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3839 | |
3840 | (define_insn "" | |
9ebbca7d | 3841 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3842 | (compare:CC |
9ebbca7d GK |
3843 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3844 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3845 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3846 | (const_int 0))) |
9ebbca7d | 3847 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3848 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3849 | "@ |
3850 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
3851 | #" | |
3852 | [(set_attr "type" "delayed_compare") | |
3853 | (set_attr "length" "4,8")]) | |
3854 | ||
3855 | (define_split | |
3856 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3857 | (compare:CC | |
3858 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3859 | (match_operand:SI 2 "const_int_operand" "")) | |
3860 | (match_operand:SI 3 "mask_operand" "")) | |
3861 | (const_int 0))) | |
3862 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3863 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3864 | [(set (match_dup 4) |
3865 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
3866 | (match_dup 3))) | |
3867 | (set (match_dup 0) | |
3868 | (compare:CC (match_dup 4) | |
3869 | (const_int 0)))] | |
3870 | "") | |
1fd4e8c1 RK |
3871 | |
3872 | (define_insn "" | |
9ebbca7d | 3873 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3874 | (compare:CC |
9ebbca7d GK |
3875 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3876 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3877 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3878 | (const_int 0))) |
9ebbca7d | 3879 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3880 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3881 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3882 | "@ |
3883 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
3884 | #" | |
3885 | [(set_attr "type" "delayed_compare") | |
3886 | (set_attr "length" "4,8")]) | |
3887 | ||
3888 | (define_split | |
3889 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3890 | (compare:CC | |
3891 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3892 | (match_operand:SI 2 "const_int_operand" "")) | |
3893 | (match_operand:SI 3 "mask_operand" "")) | |
3894 | (const_int 0))) | |
3895 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3896 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3897 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3898 | [(set (match_dup 0) |
3899 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3900 | (set (match_dup 4) | |
3901 | (compare:CC (match_dup 0) | |
3902 | (const_int 0)))] | |
3903 | "") | |
1fd4e8c1 | 3904 | |
ca7f5001 | 3905 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3906 | ;; "sli x,x,0". |
ca7f5001 RK |
3907 | (define_expand "lshrsi3" |
3908 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3909 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3910 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3911 | "" | |
3912 | " | |
3913 | { | |
3914 | if (TARGET_POWER) | |
3915 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
3916 | else | |
25c341fa | 3917 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3918 | DONE; |
3919 | }") | |
3920 | ||
3921 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
3922 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
3923 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3924 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
3925 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 3926 | "TARGET_POWER" |
1fd4e8c1 RK |
3927 | "@ |
3928 | sre %0,%1,%2 | |
bdf423cb | 3929 | mr %0,%1 |
ca7f5001 RK |
3930 | {s%A2i|s%A2wi} %0,%1,%h2") |
3931 | ||
25c341fa | 3932 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
3933 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3934 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3935 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 3936 | "! TARGET_POWER" |
bdf423cb MM |
3937 | "@ |
3938 | mr %0,%1 | |
3939 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
3940 | |
3941 | (define_insn "" | |
9ebbca7d GK |
3942 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
3943 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3944 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3945 | (const_int 0))) |
9ebbca7d GK |
3946 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
3947 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 3948 | "TARGET_POWER" |
1fd4e8c1 | 3949 | "@ |
29ae5b89 JL |
3950 | sre. %3,%1,%2 |
3951 | mr. %1,%1 | |
9ebbca7d GK |
3952 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
3953 | # | |
3954 | # | |
3955 | #" | |
3956 | [(set_attr "type" "delayed_compare") | |
3957 | (set_attr "length" "4,4,4,8,8,8")]) | |
3958 | ||
3959 | (define_split | |
3960 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3961 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3962 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3963 | (const_int 0))) | |
3964 | (clobber (match_scratch:SI 3 "")) | |
3965 | (clobber (match_scratch:SI 4 ""))] | |
3966 | "TARGET_POWER && reload_completed" | |
3967 | [(parallel [(set (match_dup 3) | |
3968 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3969 | (clobber (match_dup 4))]) | |
3970 | (set (match_dup 0) | |
3971 | (compare:CC (match_dup 3) | |
3972 | (const_int 0)))] | |
3973 | "") | |
ca7f5001 RK |
3974 | |
3975 | (define_insn "" | |
9ebbca7d GK |
3976 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3977 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3978 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 3979 | (const_int 0))) |
9ebbca7d | 3980 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
4b8a63d6 | 3981 | "! TARGET_POWER && TARGET_32BIT" |
bdf423cb MM |
3982 | "@ |
3983 | mr. %1,%1 | |
9ebbca7d GK |
3984 | {sr|srw}%I2. %3,%1,%h2 |
3985 | # | |
3986 | #" | |
3987 | [(set_attr "type" "delayed_compare") | |
3988 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 3989 | |
9ebbca7d GK |
3990 | (define_split |
3991 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3992 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3993 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3994 | (const_int 0))) | |
3995 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3996 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3997 | [(set (match_dup 3) |
3998 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3999 | (set (match_dup 0) | |
4000 | (compare:CC (match_dup 3) | |
4001 | (const_int 0)))] | |
4002 | "") | |
4003 | ||
4004 | (define_insn "" | |
4005 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
4006 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4007 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4008 | (const_int 0))) |
9ebbca7d | 4009 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 4010 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4011 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 4012 | "TARGET_POWER" |
1fd4e8c1 | 4013 | "@ |
29ae5b89 JL |
4014 | sre. %0,%1,%2 |
4015 | mr. %0,%1 | |
9ebbca7d GK |
4016 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
4017 | # | |
4018 | # | |
4019 | #" | |
4020 | [(set_attr "type" "delayed_compare") | |
4021 | (set_attr "length" "4,4,4,8,8,8")]) | |
4022 | ||
4023 | (define_split | |
4024 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4025 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4026 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4027 | (const_int 0))) | |
4028 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4029 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4030 | (clobber (match_scratch:SI 4 ""))] | |
4031 | "TARGET_POWER && reload_completed" | |
4032 | [(parallel [(set (match_dup 0) | |
4033 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4034 | (clobber (match_dup 4))]) | |
4035 | (set (match_dup 3) | |
4036 | (compare:CC (match_dup 0) | |
4037 | (const_int 0)))] | |
4038 | "") | |
ca7f5001 RK |
4039 | |
4040 | (define_insn "" | |
9ebbca7d GK |
4041 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4042 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4043 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 4044 | (const_int 0))) |
9ebbca7d | 4045 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 4046 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 4047 | "! TARGET_POWER && TARGET_32BIT" |
29ae5b89 JL |
4048 | "@ |
4049 | mr. %0,%1 | |
9ebbca7d GK |
4050 | {sr|srw}%I2. %0,%1,%h2 |
4051 | # | |
4052 | #" | |
4053 | [(set_attr "type" "delayed_compare") | |
4054 | (set_attr "length" "4,4,8,8")]) | |
4055 | ||
4056 | (define_split | |
4057 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4058 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4059 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4060 | (const_int 0))) | |
4061 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4062 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 4063 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
4064 | [(set (match_dup 0) |
4065 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4066 | (set (match_dup 3) | |
4067 | (compare:CC (match_dup 0) | |
4068 | (const_int 0)))] | |
4069 | "") | |
1fd4e8c1 RK |
4070 | |
4071 | (define_insn "" | |
cd2b37d9 RK |
4072 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4073 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4074 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 4075 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 4076 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 4077 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
4078 | |
4079 | (define_insn "" | |
9ebbca7d | 4080 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4081 | (compare:CC |
9ebbca7d GK |
4082 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4083 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 4084 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4085 | (const_int 0))) |
9ebbca7d | 4086 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 4087 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4088 | "@ |
4089 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
4090 | #" | |
4091 | [(set_attr "type" "delayed_compare") | |
4092 | (set_attr "length" "4,8")]) | |
4093 | ||
4094 | (define_split | |
4095 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4096 | (compare:CC | |
4097 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4098 | (match_operand:SI 2 "const_int_operand" "")) | |
4099 | (match_operand:SI 3 "mask_operand" "")) | |
4100 | (const_int 0))) | |
4101 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 4102 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4103 | [(set (match_dup 4) |
4104 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
4105 | (match_dup 3))) | |
4106 | (set (match_dup 0) | |
4107 | (compare:CC (match_dup 4) | |
4108 | (const_int 0)))] | |
4109 | "") | |
1fd4e8c1 RK |
4110 | |
4111 | (define_insn "" | |
9ebbca7d | 4112 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4113 | (compare:CC |
9ebbca7d GK |
4114 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4115 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 4116 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4117 | (const_int 0))) |
9ebbca7d | 4118 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4119 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 4120 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4121 | "@ |
4122 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
4123 | #" | |
4124 | [(set_attr "type" "delayed_compare") | |
4125 | (set_attr "length" "4,8")]) | |
4126 | ||
4127 | (define_split | |
4128 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4129 | (compare:CC | |
4130 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4131 | (match_operand:SI 2 "const_int_operand" "")) | |
4132 | (match_operand:SI 3 "mask_operand" "")) | |
4133 | (const_int 0))) | |
4134 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4135 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 4136 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4137 | [(set (match_dup 0) |
4138 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4139 | (set (match_dup 4) | |
4140 | (compare:CC (match_dup 0) | |
4141 | (const_int 0)))] | |
4142 | "") | |
1fd4e8c1 RK |
4143 | |
4144 | (define_insn "" | |
cd2b37d9 | 4145 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4146 | (zero_extend:SI |
4147 | (subreg:QI | |
cd2b37d9 | 4148 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4149 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4150 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4151 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4152 | |
4153 | (define_insn "" | |
9ebbca7d | 4154 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4155 | (compare:CC |
4156 | (zero_extend:SI | |
4157 | (subreg:QI | |
9ebbca7d GK |
4158 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4159 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4160 | (const_int 0))) |
9ebbca7d | 4161 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4162 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4163 | "@ |
4164 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4165 | #" | |
4166 | [(set_attr "type" "delayed_compare") | |
4167 | (set_attr "length" "4,8")]) | |
4168 | ||
4169 | (define_split | |
4170 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4171 | (compare:CC | |
4172 | (zero_extend:SI | |
4173 | (subreg:QI | |
4174 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4175 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4176 | (const_int 0))) | |
4177 | (clobber (match_scratch:SI 3 ""))] | |
4178 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4179 | [(set (match_dup 3) | |
4180 | (zero_extend:SI (subreg:QI | |
4181 | (lshiftrt:SI (match_dup 1) | |
4182 | (match_dup 2)) 0))) | |
4183 | (set (match_dup 0) | |
4184 | (compare:CC (match_dup 3) | |
4185 | (const_int 0)))] | |
4186 | "") | |
1fd4e8c1 RK |
4187 | |
4188 | (define_insn "" | |
9ebbca7d | 4189 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4190 | (compare:CC |
4191 | (zero_extend:SI | |
4192 | (subreg:QI | |
9ebbca7d GK |
4193 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4194 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4195 | (const_int 0))) |
9ebbca7d | 4196 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4197 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4198 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4199 | "@ |
4200 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4201 | #" | |
4202 | [(set_attr "type" "delayed_compare") | |
4203 | (set_attr "length" "4,8")]) | |
4204 | ||
4205 | (define_split | |
4206 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4207 | (compare:CC | |
4208 | (zero_extend:SI | |
4209 | (subreg:QI | |
4210 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4211 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4212 | (const_int 0))) | |
4213 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4214 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4215 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4216 | [(set (match_dup 0) | |
4217 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4218 | (set (match_dup 3) | |
4219 | (compare:CC (match_dup 0) | |
4220 | (const_int 0)))] | |
4221 | "") | |
1fd4e8c1 RK |
4222 | |
4223 | (define_insn "" | |
cd2b37d9 | 4224 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4225 | (zero_extend:SI |
4226 | (subreg:HI | |
cd2b37d9 | 4227 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4228 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4229 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4230 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4231 | |
4232 | (define_insn "" | |
9ebbca7d | 4233 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4234 | (compare:CC |
4235 | (zero_extend:SI | |
4236 | (subreg:HI | |
9ebbca7d GK |
4237 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4238 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4239 | (const_int 0))) |
9ebbca7d | 4240 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4241 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4242 | "@ |
4243 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4244 | #" | |
4245 | [(set_attr "type" "delayed_compare") | |
4246 | (set_attr "length" "4,8")]) | |
4247 | ||
4248 | (define_split | |
4249 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4250 | (compare:CC | |
4251 | (zero_extend:SI | |
4252 | (subreg:HI | |
4253 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4254 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4255 | (const_int 0))) | |
4256 | (clobber (match_scratch:SI 3 ""))] | |
4257 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4258 | [(set (match_dup 3) | |
4259 | (zero_extend:SI (subreg:HI | |
4260 | (lshiftrt:SI (match_dup 1) | |
4261 | (match_dup 2)) 0))) | |
4262 | (set (match_dup 0) | |
4263 | (compare:CC (match_dup 3) | |
4264 | (const_int 0)))] | |
4265 | "") | |
1fd4e8c1 RK |
4266 | |
4267 | (define_insn "" | |
9ebbca7d | 4268 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4269 | (compare:CC |
4270 | (zero_extend:SI | |
4271 | (subreg:HI | |
9ebbca7d GK |
4272 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4273 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4274 | (const_int 0))) |
9ebbca7d | 4275 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4276 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4277 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4278 | "@ |
4279 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4280 | #" | |
4281 | [(set_attr "type" "delayed_compare") | |
4282 | (set_attr "length" "4,8")]) | |
4283 | ||
4284 | (define_split | |
4285 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4286 | (compare:CC | |
4287 | (zero_extend:SI | |
4288 | (subreg:HI | |
4289 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4290 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4291 | (const_int 0))) | |
4292 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4293 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4294 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4295 | [(set (match_dup 0) | |
4296 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4297 | (set (match_dup 3) | |
4298 | (compare:CC (match_dup 0) | |
4299 | (const_int 0)))] | |
4300 | "") | |
1fd4e8c1 RK |
4301 | |
4302 | (define_insn "" | |
cd2b37d9 | 4303 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4304 | (const_int 1) |
cd2b37d9 RK |
4305 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4306 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4307 | (const_int 31)))] |
ca7f5001 | 4308 | "TARGET_POWER" |
1fd4e8c1 RK |
4309 | "rrib %0,%1,%2") |
4310 | ||
4311 | (define_insn "" | |
cd2b37d9 | 4312 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4313 | (const_int 1) |
cd2b37d9 RK |
4314 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4315 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4316 | (const_int 31)))] |
ca7f5001 | 4317 | "TARGET_POWER" |
1fd4e8c1 RK |
4318 | "rrib %0,%1,%2") |
4319 | ||
4320 | (define_insn "" | |
cd2b37d9 | 4321 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4322 | (const_int 1) |
cd2b37d9 RK |
4323 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4324 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4325 | (const_int 1) |
4326 | (const_int 0)))] | |
ca7f5001 | 4327 | "TARGET_POWER" |
1fd4e8c1 RK |
4328 | "rrib %0,%1,%2") |
4329 | ||
ca7f5001 RK |
4330 | (define_expand "ashrsi3" |
4331 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4332 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4333 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4334 | "" | |
4335 | " | |
4336 | { | |
4337 | if (TARGET_POWER) | |
4338 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4339 | else | |
25c341fa | 4340 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4341 | DONE; |
4342 | }") | |
4343 | ||
4344 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4345 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4346 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4347 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4348 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4349 | "TARGET_POWER" |
1fd4e8c1 RK |
4350 | "@ |
4351 | srea %0,%1,%2 | |
ca7f5001 RK |
4352 | {srai|srawi} %0,%1,%h2") |
4353 | ||
25c341fa | 4354 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4355 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4356 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4357 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4358 | "! TARGET_POWER" |
d904e9ed | 4359 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4360 | |
4361 | (define_insn "" | |
9ebbca7d GK |
4362 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4363 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4364 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4365 | (const_int 0))) |
9ebbca7d GK |
4366 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4367 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4368 | "TARGET_POWER" |
1fd4e8c1 RK |
4369 | "@ |
4370 | srea. %3,%1,%2 | |
9ebbca7d GK |
4371 | {srai.|srawi.} %3,%1,%h2 |
4372 | # | |
4373 | #" | |
4374 | [(set_attr "type" "delayed_compare") | |
4375 | (set_attr "length" "4,4,8,8")]) | |
4376 | ||
4377 | (define_split | |
4378 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4379 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4380 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4381 | (const_int 0))) | |
4382 | (clobber (match_scratch:SI 3 "")) | |
4383 | (clobber (match_scratch:SI 4 ""))] | |
4384 | "TARGET_POWER && reload_completed" | |
4385 | [(parallel [(set (match_dup 3) | |
4386 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4387 | (clobber (match_dup 4))]) | |
4388 | (set (match_dup 0) | |
4389 | (compare:CC (match_dup 3) | |
4390 | (const_int 0)))] | |
4391 | "") | |
ca7f5001 RK |
4392 | |
4393 | (define_insn "" | |
9ebbca7d GK |
4394 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4395 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4396 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4397 | (const_int 0))) |
9ebbca7d | 4398 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4399 | "! TARGET_POWER" |
9ebbca7d GK |
4400 | "@ |
4401 | {sra|sraw}%I2. %3,%1,%h2 | |
4402 | #" | |
4403 | [(set_attr "type" "delayed_compare") | |
4404 | (set_attr "length" "4,8")]) | |
4405 | ||
4406 | (define_split | |
4407 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4408 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4409 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4410 | (const_int 0))) | |
4411 | (clobber (match_scratch:SI 3 ""))] | |
4412 | "! TARGET_POWER && reload_completed" | |
4413 | [(set (match_dup 3) | |
4414 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4415 | (set (match_dup 0) | |
4416 | (compare:CC (match_dup 3) | |
4417 | (const_int 0)))] | |
4418 | "") | |
1fd4e8c1 RK |
4419 | |
4420 | (define_insn "" | |
9ebbca7d GK |
4421 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4422 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4423 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4424 | (const_int 0))) |
9ebbca7d | 4425 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4426 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4427 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4428 | "TARGET_POWER" |
1fd4e8c1 RK |
4429 | "@ |
4430 | srea. %0,%1,%2 | |
9ebbca7d GK |
4431 | {srai.|srawi.} %0,%1,%h2 |
4432 | # | |
4433 | #" | |
4434 | [(set_attr "type" "delayed_compare") | |
4435 | (set_attr "length" "4,4,8,8")]) | |
4436 | ||
4437 | (define_split | |
4438 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4439 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4440 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4441 | (const_int 0))) | |
4442 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4443 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4444 | (clobber (match_scratch:SI 4 ""))] | |
4445 | "TARGET_POWER && reload_completed" | |
4446 | [(parallel [(set (match_dup 0) | |
4447 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4448 | (clobber (match_dup 4))]) | |
4449 | (set (match_dup 3) | |
4450 | (compare:CC (match_dup 0) | |
4451 | (const_int 0)))] | |
4452 | "") | |
1fd4e8c1 | 4453 | |
ca7f5001 | 4454 | (define_insn "" |
9ebbca7d GK |
4455 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4456 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4457 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4458 | (const_int 0))) |
9ebbca7d | 4459 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4460 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4461 | "! TARGET_POWER" |
9ebbca7d GK |
4462 | "@ |
4463 | {sra|sraw}%I2. %0,%1,%h2 | |
4464 | #" | |
4465 | [(set_attr "type" "delayed_compare") | |
4466 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4467 | \f |
9ebbca7d GK |
4468 | (define_split |
4469 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4470 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4471 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4472 | (const_int 0))) | |
4473 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4474 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4475 | "! TARGET_POWER && reload_completed" | |
4476 | [(set (match_dup 0) | |
4477 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4478 | (set (match_dup 3) | |
4479 | (compare:CC (match_dup 0) | |
4480 | (const_int 0)))] | |
4481 | "") | |
4482 | ||
1fd4e8c1 RK |
4483 | ;; Floating-point insns, excluding normal data motion. |
4484 | ;; | |
ca7f5001 RK |
4485 | ;; PowerPC has a full set of single-precision floating point instructions. |
4486 | ;; | |
4487 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4488 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4489 | ;; The only conversions we will do will be when storing to memory. In that | |
4490 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4491 | ;; |
4492 | ;; Note that when we store into a single-precision memory location, we need to | |
4493 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4494 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4495 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4496 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4497 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4498 | ||
99176a91 AH |
4499 | (define_expand "extendsfdf2" |
4500 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
97c54d9a | 4501 | (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))] |
99176a91 AH |
4502 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" |
4503 | "") | |
4504 | ||
4505 | (define_insn_and_split "*extendsfdf2_fpr" | |
97c54d9a DE |
4506 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f") |
4507 | (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))] | |
a3170dc6 | 4508 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
11ac38b2 DE |
4509 | "@ |
4510 | # | |
97c54d9a DE |
4511 | fmr %0,%1 |
4512 | lfs%U1%X1 %0,%1" | |
d7b1468b | 4513 | "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])" |
11ac38b2 | 4514 | [(const_int 0)] |
5c30aff8 | 4515 | { |
11ac38b2 DE |
4516 | emit_note (NOTE_INSN_DELETED); |
4517 | DONE; | |
4518 | } | |
97c54d9a | 4519 | [(set_attr "type" "fp,fp,fpload")]) |
1fd4e8c1 | 4520 | |
7a2f7870 AH |
4521 | (define_expand "truncdfsf2" |
4522 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4523 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4524 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4525 | "") | |
4526 | ||
99176a91 | 4527 | (define_insn "*truncdfsf2_fpr" |
cd2b37d9 RK |
4528 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4529 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4530 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
dcac138d | 4531 | "frsp %0,%1" |
1fd4e8c1 RK |
4532 | [(set_attr "type" "fp")]) |
4533 | ||
455350f4 RK |
4534 | (define_insn "aux_truncdfsf2" |
4535 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
615158e2 | 4536 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))] |
a3170dc6 | 4537 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
455350f4 RK |
4538 | "frsp %0,%1" |
4539 | [(set_attr "type" "fp")]) | |
4540 | ||
a3170dc6 AH |
4541 | (define_expand "negsf2" |
4542 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4543 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4544 | "TARGET_HARD_FLOAT" | |
4545 | "") | |
4546 | ||
4547 | (define_insn "*negsf2" | |
cd2b37d9 RK |
4548 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4549 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4550 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4551 | "fneg %0,%1" |
4552 | [(set_attr "type" "fp")]) | |
4553 | ||
a3170dc6 AH |
4554 | (define_expand "abssf2" |
4555 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4556 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4557 | "TARGET_HARD_FLOAT" | |
4558 | "") | |
4559 | ||
4560 | (define_insn "*abssf2" | |
cd2b37d9 RK |
4561 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4562 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4563 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4564 | "fabs %0,%1" |
4565 | [(set_attr "type" "fp")]) | |
4566 | ||
4567 | (define_insn "" | |
cd2b37d9 RK |
4568 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4569 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4570 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4571 | "fnabs %0,%1" |
4572 | [(set_attr "type" "fp")]) | |
4573 | ||
ca7f5001 RK |
4574 | (define_expand "addsf3" |
4575 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4576 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4577 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4578 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4579 | "") |
4580 | ||
4581 | (define_insn "" | |
cd2b37d9 RK |
4582 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4583 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4584 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4585 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4586 | "fadds %0,%1,%2" |
ca7f5001 RK |
4587 | [(set_attr "type" "fp")]) |
4588 | ||
4589 | (define_insn "" | |
4590 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4591 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4592 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4593 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4594 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4595 | [(set_attr "type" "fp")]) |
4596 | ||
4597 | (define_expand "subsf3" | |
4598 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4599 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4600 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4601 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4602 | "") |
4603 | ||
4604 | (define_insn "" | |
4605 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4606 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4607 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4608 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4609 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4610 | [(set_attr "type" "fp")]) |
4611 | ||
ca7f5001 | 4612 | (define_insn "" |
cd2b37d9 RK |
4613 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4614 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4615 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4616 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4617 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4618 | [(set_attr "type" "fp")]) |
4619 | ||
4620 | (define_expand "mulsf3" | |
4621 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4622 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4623 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4624 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4625 | "") |
4626 | ||
4627 | (define_insn "" | |
4628 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4629 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4630 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4631 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4632 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4633 | [(set_attr "type" "fp")]) |
4634 | ||
ca7f5001 | 4635 | (define_insn "" |
cd2b37d9 RK |
4636 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4637 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4638 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4639 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4640 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4641 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4642 | |
ca7f5001 RK |
4643 | (define_expand "divsf3" |
4644 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4645 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4646 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4647 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4648 | "") |
4649 | ||
4650 | (define_insn "" | |
cd2b37d9 RK |
4651 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4652 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4653 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4654 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4655 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4656 | [(set_attr "type" "sdiv")]) |
4657 | ||
4658 | (define_insn "" | |
4659 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4660 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4661 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4662 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4663 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4664 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4665 | |
4666 | (define_insn "" | |
cd2b37d9 RK |
4667 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4668 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4669 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4670 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4671 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4672 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4673 | [(set_attr "type" "fp")]) |
4674 | ||
4675 | (define_insn "" | |
4676 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4677 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4678 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4679 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4680 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4681 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4682 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4683 | |
4684 | (define_insn "" | |
cd2b37d9 RK |
4685 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4686 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4687 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4688 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4689 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4690 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4691 | [(set_attr "type" "fp")]) |
4692 | ||
4693 | (define_insn "" | |
4694 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4695 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4696 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4697 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4698 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4699 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4700 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4701 | |
4702 | (define_insn "" | |
cd2b37d9 RK |
4703 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4704 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4705 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4706 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4707 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4708 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4709 | "fnmadds %0,%1,%2,%3" | |
4710 | [(set_attr "type" "fp")]) | |
4711 | ||
4712 | (define_insn "" | |
4713 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4714 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4715 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4716 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4717 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4718 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4719 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4720 | [(set_attr "type" "fp")]) |
4721 | ||
4722 | (define_insn "" | |
4723 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4724 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4725 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4726 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4727 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4728 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4729 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4730 | |
16823694 GK |
4731 | (define_insn "" |
4732 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4733 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4734 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4735 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4736 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4737 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4738 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4739 | [(set_attr "type" "dmul")]) | |
4740 | ||
1fd4e8c1 | 4741 | (define_insn "" |
cd2b37d9 RK |
4742 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4743 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4744 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4745 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4746 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4747 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4748 | "fnmsubs %0,%1,%2,%3" | |
4749 | [(set_attr "type" "fp")]) | |
4750 | ||
4751 | (define_insn "" | |
4752 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4753 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4754 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4755 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4756 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4757 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4758 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4759 | [(set_attr "type" "fp")]) |
4760 | ||
4761 | (define_insn "" | |
4762 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4763 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4764 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4765 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4766 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4767 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 4768 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4769 | |
16823694 GK |
4770 | (define_insn "" |
4771 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4772 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4773 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4774 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4775 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4776 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4777 | "{fnms|fnmsub} %0,%1,%2,%3" | |
4778 | [(set_attr "type" "fp")]) | |
4779 | ||
ca7f5001 RK |
4780 | (define_expand "sqrtsf2" |
4781 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4782 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 4783 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4784 | "") |
4785 | ||
4786 | (define_insn "" | |
4787 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4788 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4789 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4790 | "fsqrts %0,%1" |
4791 | [(set_attr "type" "ssqrt")]) | |
4792 | ||
4793 | (define_insn "" | |
4794 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4795 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4796 | "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4797 | "fsqrt %0,%1" |
4798 | [(set_attr "type" "dsqrt")]) | |
4799 | ||
0530bc70 AP |
4800 | (define_expand "copysignsf3" |
4801 | [(set (match_dup 3) | |
4802 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" ""))) | |
4803 | (set (match_dup 4) | |
4804 | (neg:SF (abs:SF (match_dup 1)))) | |
4805 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
4806 | (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "") | |
4807 | (match_dup 5)) | |
4808 | (match_dup 3) | |
4809 | (match_dup 4)))] | |
4810 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS | |
4811 | && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)" | |
4812 | { | |
4813 | operands[3] = gen_reg_rtx (SFmode); | |
4814 | operands[4] = gen_reg_rtx (SFmode); | |
4815 | operands[5] = CONST0_RTX (SFmode); | |
4816 | }) | |
4817 | ||
4818 | (define_expand "copysigndf3" | |
4819 | [(set (match_dup 3) | |
4820 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" ""))) | |
4821 | (set (match_dup 4) | |
4822 | (neg:DF (abs:DF (match_dup 1)))) | |
4823 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
4824 | (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "") | |
4825 | (match_dup 5)) | |
4826 | (match_dup 3) | |
4827 | (match_dup 4)))] | |
4828 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS | |
4829 | && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)" | |
4830 | { | |
4831 | operands[3] = gen_reg_rtx (DFmode); | |
4832 | operands[4] = gen_reg_rtx (DFmode); | |
4833 | operands[5] = CONST0_RTX (DFmode); | |
4834 | }) | |
4835 | ||
94d7001a RK |
4836 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4837 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4838 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 | 4839 | ;; combine. |
7ae4d8d4 | 4840 | (define_expand "smaxsf3" |
8e871c05 | 4841 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4842 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
4843 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4844 | (match_dup 1) |
4845 | (match_dup 2)))] | |
89e73849 | 4846 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 4847 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
2f607b94 | 4848 | |
7ae4d8d4 | 4849 | (define_expand "sminsf3" |
50a0b056 GK |
4850 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
4851 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
4852 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
4853 | (match_dup 2) | |
4854 | (match_dup 1)))] | |
89e73849 | 4855 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 4856 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 4857 | |
8e871c05 RK |
4858 | (define_split |
4859 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4860 | (match_operator:SF 3 "min_max_operator" |
4861 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
4862 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
89e73849 | 4863 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 GK |
4864 | [(const_int 0)] |
4865 | " | |
6ae08853 | 4866 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
4867 | operands[1], operands[2]); |
4868 | DONE; | |
4869 | }") | |
2f607b94 | 4870 | |
a3170dc6 AH |
4871 | (define_expand "movsicc" |
4872 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4873 | (if_then_else:SI (match_operand 1 "comparison_operator" "") | |
4874 | (match_operand:SI 2 "gpc_reg_operand" "") | |
4875 | (match_operand:SI 3 "gpc_reg_operand" "")))] | |
4876 | "TARGET_ISEL" | |
4877 | " | |
4878 | { | |
4879 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) | |
4880 | DONE; | |
4881 | else | |
4882 | FAIL; | |
4883 | }") | |
4884 | ||
4885 | ;; We use the BASE_REGS for the isel input operands because, if rA is | |
4886 | ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB | |
4887 | ;; because we may switch the operands and rB may end up being rA. | |
4888 | ;; | |
4889 | ;; We need 2 patterns: an unsigned and a signed pattern. We could | |
4890 | ;; leave out the mode in operand 4 and use one pattern, but reload can | |
4891 | ;; change the mode underneath our feet and then gets confused trying | |
4892 | ;; to reload the value. | |
4893 | (define_insn "isel_signed" | |
4894 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4895 | (if_then_else:SI | |
4896 | (match_operator 1 "comparison_operator" | |
4897 | [(match_operand:CC 4 "cc_reg_operand" "y") | |
4898 | (const_int 0)]) | |
4899 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4900 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4901 | "TARGET_ISEL" | |
4902 | "* | |
4903 | { return output_isel (operands); }" | |
4904 | [(set_attr "length" "4")]) | |
4905 | ||
4906 | (define_insn "isel_unsigned" | |
4907 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4908 | (if_then_else:SI | |
4909 | (match_operator 1 "comparison_operator" | |
4910 | [(match_operand:CCUNS 4 "cc_reg_operand" "y") | |
4911 | (const_int 0)]) | |
4912 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4913 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4914 | "TARGET_ISEL" | |
4915 | "* | |
4916 | { return output_isel (operands); }" | |
4917 | [(set_attr "length" "4")]) | |
4918 | ||
94d7001a | 4919 | (define_expand "movsfcc" |
0ad91047 | 4920 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 4921 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4922 | (match_operand:SF 2 "gpc_reg_operand" "") |
4923 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 4924 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4925 | " |
4926 | { | |
50a0b056 GK |
4927 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4928 | DONE; | |
94d7001a | 4929 | else |
50a0b056 | 4930 | FAIL; |
94d7001a | 4931 | }") |
d56d506a | 4932 | |
50a0b056 | 4933 | (define_insn "*fselsfsf4" |
8e871c05 RK |
4934 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4935 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4936 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4937 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4938 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4939 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
4940 | "fsel %0,%1,%2,%3" |
4941 | [(set_attr "type" "fp")]) | |
2f607b94 | 4942 | |
50a0b056 | 4943 | (define_insn "*fseldfsf4" |
94d7001a RK |
4944 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4945 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 4946 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4947 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4948 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4949 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4950 | "fsel %0,%1,%2,%3" |
4951 | [(set_attr "type" "fp")]) | |
d56d506a | 4952 | |
7a2f7870 AH |
4953 | (define_expand "negdf2" |
4954 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4955 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4956 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4957 | "") | |
4958 | ||
99176a91 | 4959 | (define_insn "*negdf2_fpr" |
cd2b37d9 RK |
4960 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4961 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4962 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4963 | "fneg %0,%1" |
4964 | [(set_attr "type" "fp")]) | |
4965 | ||
7a2f7870 AH |
4966 | (define_expand "absdf2" |
4967 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4968 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4969 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4970 | "") | |
4971 | ||
99176a91 | 4972 | (define_insn "*absdf2_fpr" |
cd2b37d9 RK |
4973 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4974 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4975 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4976 | "fabs %0,%1" |
4977 | [(set_attr "type" "fp")]) | |
4978 | ||
99176a91 | 4979 | (define_insn "*nabsdf2_fpr" |
cd2b37d9 RK |
4980 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4981 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4982 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4983 | "fnabs %0,%1" |
4984 | [(set_attr "type" "fp")]) | |
4985 | ||
7a2f7870 AH |
4986 | (define_expand "adddf3" |
4987 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4988 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4989 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4990 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4991 | "") | |
4992 | ||
99176a91 | 4993 | (define_insn "*adddf3_fpr" |
cd2b37d9 RK |
4994 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4995 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4996 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4997 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4998 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
4999 | [(set_attr "type" "fp")]) |
5000 | ||
7a2f7870 AH |
5001 | (define_expand "subdf3" |
5002 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5003 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
5004 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
5005 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
5006 | "") | |
5007 | ||
99176a91 | 5008 | (define_insn "*subdf3_fpr" |
cd2b37d9 RK |
5009 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5010 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
5011 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5012 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 5013 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
5014 | [(set_attr "type" "fp")]) |
5015 | ||
7a2f7870 AH |
5016 | (define_expand "muldf3" |
5017 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5018 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
5019 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
5020 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
5021 | "") | |
5022 | ||
99176a91 | 5023 | (define_insn "*muldf3_fpr" |
cd2b37d9 RK |
5024 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5025 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5026 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5027 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 5028 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 5029 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 5030 | |
7a2f7870 AH |
5031 | (define_expand "divdf3" |
5032 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5033 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
5034 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
5035 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
5036 | "") | |
5037 | ||
99176a91 | 5038 | (define_insn "*divdf3_fpr" |
cd2b37d9 RK |
5039 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5040 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
5041 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5042 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 5043 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 5044 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
5045 | |
5046 | (define_insn "" | |
cd2b37d9 RK |
5047 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5048 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5049 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5050 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5051 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 5052 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 5053 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5054 | |
5055 | (define_insn "" | |
cd2b37d9 RK |
5056 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5057 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5058 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5059 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5060 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 5061 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 5062 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5063 | |
5064 | (define_insn "" | |
cd2b37d9 RK |
5065 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5066 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5067 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5068 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
5069 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
5070 | && HONOR_SIGNED_ZEROS (DFmode)" | |
5071 | "{fnma|fnmadd} %0,%1,%2,%3" | |
5072 | [(set_attr "type" "dmul")]) | |
5073 | ||
5074 | (define_insn "" | |
5075 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5076 | (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) | |
5077 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5078 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5079 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
5080 | && ! HONOR_SIGNED_ZEROS (DFmode)" | |
ca7f5001 | 5081 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 5082 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5083 | |
5084 | (define_insn "" | |
cd2b37d9 RK |
5085 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5086 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5087 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5088 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
5089 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
5090 | && HONOR_SIGNED_ZEROS (DFmode)" | |
5091 | "{fnms|fnmsub} %0,%1,%2,%3" | |
5092 | [(set_attr "type" "dmul")]) | |
5093 | ||
5094 | (define_insn "" | |
5095 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5096 | (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") | |
5097 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5098 | (match_operand:DF 2 "gpc_reg_operand" "f"))))] | |
6ae08853 | 5099 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
16823694 | 5100 | && ! HONOR_SIGNED_ZEROS (DFmode)" |
ca7f5001 | 5101 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 5102 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
5103 | |
5104 | (define_insn "sqrtdf2" | |
5105 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5106 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5107 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
5108 | "fsqrt %0,%1" |
5109 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 5110 | |
50a0b056 | 5111 | ;; The conditional move instructions allow us to perform max and min |
6ae08853 | 5112 | ;; operations even when |
b77dfefc | 5113 | |
7ae4d8d4 | 5114 | (define_expand "smaxdf3" |
8e871c05 | 5115 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
5116 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
5117 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
5118 | (match_dup 1) |
5119 | (match_dup 2)))] | |
89e73849 | 5120 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 5121 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
b77dfefc | 5122 | |
7ae4d8d4 | 5123 | (define_expand "smindf3" |
50a0b056 GK |
5124 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5125 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
5126 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
5127 | (match_dup 2) | |
5128 | (match_dup 1)))] | |
89e73849 | 5129 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 5130 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 5131 | |
8e871c05 RK |
5132 | (define_split |
5133 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
5134 | (match_operator:DF 3 "min_max_operator" |
5135 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
5136 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
89e73849 | 5137 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 GK |
5138 | [(const_int 0)] |
5139 | " | |
6ae08853 | 5140 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
5141 | operands[1], operands[2]); |
5142 | DONE; | |
5143 | }") | |
b77dfefc | 5144 | |
94d7001a | 5145 | (define_expand "movdfcc" |
0ad91047 | 5146 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 5147 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5148 | (match_operand:DF 2 "gpc_reg_operand" "") |
5149 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 5150 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
5151 | " |
5152 | { | |
50a0b056 GK |
5153 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5154 | DONE; | |
94d7001a | 5155 | else |
50a0b056 | 5156 | FAIL; |
94d7001a | 5157 | }") |
d56d506a | 5158 | |
50a0b056 | 5159 | (define_insn "*fseldfdf4" |
8e871c05 RK |
5160 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5161 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5162 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5163 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5164 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5165 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
5166 | "fsel %0,%1,%2,%3" |
5167 | [(set_attr "type" "fp")]) | |
d56d506a | 5168 | |
50a0b056 | 5169 | (define_insn "*fselsfdf4" |
94d7001a RK |
5170 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5171 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5172 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5173 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5174 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5175 | "TARGET_PPC_GFXOPT" | |
5176 | "fsel %0,%1,%2,%3" | |
5177 | [(set_attr "type" "fp")]) | |
1fd4e8c1 | 5178 | \f |
d095928f AH |
5179 | ;; Conversions to and from floating-point. |
5180 | ||
5181 | (define_expand "fixuns_truncsfsi2" | |
5182 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5183 | (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5184 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5185 | "") | |
5186 | ||
5187 | (define_expand "fix_truncsfsi2" | |
5188 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5189 | (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5190 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5191 | "") | |
5192 | ||
9ebbca7d GK |
5193 | ; For each of these conversions, there is a define_expand, a define_insn |
5194 | ; with a '#' template, and a define_split (with C code). The idea is | |
5195 | ; to allow constant folding with the template of the define_insn, | |
5196 | ; then to have the insns split later (between sched1 and final). | |
5197 | ||
1fd4e8c1 | 5198 | (define_expand "floatsidf2" |
802a0058 MM |
5199 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5200 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5201 | (use (match_dup 2)) | |
5202 | (use (match_dup 3)) | |
208c89ce | 5203 | (clobber (match_dup 4)) |
a7df97e6 | 5204 | (clobber (match_dup 5)) |
9ebbca7d | 5205 | (clobber (match_dup 6))])] |
a3170dc6 | 5206 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5207 | " |
5208 | { | |
99176a91 AH |
5209 | if (TARGET_E500_DOUBLE) |
5210 | { | |
5211 | emit_insn (gen_spe_floatsidf2 (operands[0], operands[1])); | |
5212 | DONE; | |
5213 | } | |
05d49501 AM |
5214 | if (TARGET_POWERPC64) |
5215 | { | |
5216 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5217 | rtx t1 = gen_reg_rtx (DImode); | |
5218 | rtx t2 = gen_reg_rtx (DImode); | |
5219 | emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); | |
5220 | DONE; | |
5221 | } | |
5222 | ||
802a0058 | 5223 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5224 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); |
9ebbca7d GK |
5225 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5226 | operands[5] = gen_reg_rtx (DFmode); | |
5227 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5228 | }") |
5229 | ||
230215f5 | 5230 | (define_insn_and_split "*floatsidf2_internal" |
802a0058 MM |
5231 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") |
5232 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5233 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5234 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5235 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 DJ |
5236 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) |
5237 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] | |
a3170dc6 | 5238 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5239 | "#" |
230215f5 GK |
5240 | "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))" |
5241 | [(pc)] | |
208c89ce MM |
5242 | " |
5243 | { | |
9ebbca7d | 5244 | rtx lowword, highword; |
230215f5 GK |
5245 | gcc_assert (MEM_P (operands[4])); |
5246 | highword = adjust_address (operands[4], SImode, 0); | |
5247 | lowword = adjust_address (operands[4], SImode, 4); | |
9ebbca7d GK |
5248 | if (! WORDS_BIG_ENDIAN) |
5249 | { | |
5250 | rtx tmp; | |
5251 | tmp = highword; highword = lowword; lowword = tmp; | |
5252 | } | |
5253 | ||
6ae08853 | 5254 | emit_insn (gen_xorsi3 (operands[6], operands[1], |
9ebbca7d | 5255 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); |
230215f5 GK |
5256 | emit_move_insn (lowword, operands[6]); |
5257 | emit_move_insn (highword, operands[2]); | |
9ebbca7d GK |
5258 | emit_move_insn (operands[5], operands[4]); |
5259 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5260 | DONE; | |
230215f5 GK |
5261 | }" |
5262 | [(set_attr "length" "24")]) | |
802a0058 | 5263 | |
a3170dc6 AH |
5264 | (define_expand "floatunssisf2" |
5265 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5266 | (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5267 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5268 | "") | |
5269 | ||
802a0058 MM |
5270 | (define_expand "floatunssidf2" |
5271 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5272 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5273 | (use (match_dup 2)) | |
5274 | (use (match_dup 3)) | |
a7df97e6 | 5275 | (clobber (match_dup 4)) |
9ebbca7d | 5276 | (clobber (match_dup 5))])] |
99176a91 | 5277 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" |
1fd4e8c1 RK |
5278 | " |
5279 | { | |
99176a91 AH |
5280 | if (TARGET_E500_DOUBLE) |
5281 | { | |
5282 | emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1])); | |
5283 | DONE; | |
5284 | } | |
05d49501 AM |
5285 | if (TARGET_POWERPC64) |
5286 | { | |
5287 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5288 | rtx t1 = gen_reg_rtx (DImode); | |
5289 | rtx t2 = gen_reg_rtx (DImode); | |
5290 | emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, | |
5291 | t1, t2)); | |
5292 | DONE; | |
5293 | } | |
5294 | ||
802a0058 | 5295 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5296 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); |
9ebbca7d GK |
5297 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5298 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5299 | }") |
5300 | ||
230215f5 | 5301 | (define_insn_and_split "*floatunssidf2_internal" |
802a0058 MM |
5302 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") |
5303 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5304 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5305 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5306 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 | 5307 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] |
a3170dc6 | 5308 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5309 | "#" |
230215f5 GK |
5310 | "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))" |
5311 | [(pc)] | |
9ebbca7d | 5312 | " |
802a0058 | 5313 | { |
9ebbca7d | 5314 | rtx lowword, highword; |
230215f5 GK |
5315 | gcc_assert (MEM_P (operands[4])); |
5316 | highword = adjust_address (operands[4], SImode, 0); | |
5317 | lowword = adjust_address (operands[4], SImode, 4); | |
9ebbca7d | 5318 | if (! WORDS_BIG_ENDIAN) |
f6968f59 | 5319 | { |
9ebbca7d GK |
5320 | rtx tmp; |
5321 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5322 | } |
802a0058 | 5323 | |
230215f5 GK |
5324 | emit_move_insn (lowword, operands[1]); |
5325 | emit_move_insn (highword, operands[2]); | |
9ebbca7d GK |
5326 | emit_move_insn (operands[5], operands[4]); |
5327 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5328 | DONE; | |
230215f5 GK |
5329 | }" |
5330 | [(set_attr "length" "20")]) | |
1fd4e8c1 | 5331 | |
51b75924 GK |
5332 | ; In the TARGET_PPC_GFXOPT case, this could and probably should |
5333 | ; take a memory destination; but actually making this work is hard. | |
1fd4e8c1 | 5334 | (define_expand "fix_truncdfsi2" |
51b75924 | 5335 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
802a0058 MM |
5336 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
5337 | (clobber (match_dup 2)) | |
9ebbca7d | 5338 | (clobber (match_dup 3))])] |
99176a91 AH |
5339 | "(TARGET_POWER2 || TARGET_POWERPC) |
5340 | && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
1fd4e8c1 RK |
5341 | " |
5342 | { | |
99176a91 AH |
5343 | if (TARGET_E500_DOUBLE) |
5344 | { | |
5345 | emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1])); | |
5346 | DONE; | |
5347 | } | |
802a0058 | 5348 | operands[2] = gen_reg_rtx (DImode); |
da4c340c GK |
5349 | if (TARGET_PPC_GFXOPT) |
5350 | { | |
5351 | rtx orig_dest = operands[0]; | |
5352 | if (GET_CODE (orig_dest) != MEM) | |
5353 | operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0); | |
5354 | emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1], | |
5355 | operands[2])); | |
5356 | if (operands[0] != orig_dest) | |
5357 | emit_move_insn (orig_dest, operands[0]); | |
5358 | DONE; | |
5359 | } | |
9ebbca7d | 5360 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5361 | }") |
5362 | ||
da4c340c | 5363 | (define_insn_and_split "*fix_truncdfsi2_internal" |
802a0058 MM |
5364 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5365 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
e3485bbc | 5366 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) |
9ebbca7d | 5367 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
a3170dc6 | 5368 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5369 | "#" |
230215f5 | 5370 | "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))" |
da4c340c | 5371 | [(pc)] |
9ebbca7d | 5372 | " |
802a0058 | 5373 | { |
9ebbca7d | 5374 | rtx lowword; |
230215f5 GK |
5375 | gcc_assert (MEM_P (operands[3])); |
5376 | lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0); | |
802a0058 | 5377 | |
9ebbca7d GK |
5378 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5379 | emit_move_insn (operands[3], operands[2]); | |
230215f5 | 5380 | emit_move_insn (operands[0], lowword); |
9ebbca7d | 5381 | DONE; |
da4c340c GK |
5382 | }" |
5383 | [(set_attr "length" "16")]) | |
5384 | ||
5385 | (define_insn_and_split "fix_truncdfsi2_internal_gfxopt" | |
5386 | [(set (match_operand:SI 0 "memory_operand" "=Z") | |
5387 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5388 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))] | |
5389 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS | |
5390 | && TARGET_PPC_GFXOPT" | |
5391 | "#" | |
5392 | "&& 1" | |
5393 | [(pc)] | |
5394 | " | |
5395 | { | |
5396 | emit_insn (gen_fctiwz (operands[2], operands[1])); | |
5397 | emit_insn (gen_stfiwx (operands[0], operands[2])); | |
5398 | DONE; | |
5399 | }" | |
5400 | [(set_attr "length" "16")]) | |
802a0058 | 5401 | |
615158e2 | 5402 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) |
9ebbca7d GK |
5403 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) |
5404 | ; because the first makes it clear that operand 0 is not live | |
5405 | ; before the instruction. | |
5406 | (define_insn "fctiwz" | |
da4c340c | 5407 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") |
615158e2 JJ |
5408 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] |
5409 | UNSPEC_FCTIWZ))] | |
a3170dc6 | 5410 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
a260abc9 DE |
5411 | "{fcirz|fctiwz} %0,%1" |
5412 | [(set_attr "type" "fp")]) | |
5413 | ||
da4c340c GK |
5414 | ; An UNSPEC is used so we don't have to support SImode in FP registers. |
5415 | (define_insn "stfiwx" | |
5416 | [(set (match_operand:SI 0 "memory_operand" "=Z") | |
5417 | (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")] | |
5418 | UNSPEC_STFIWX))] | |
5419 | "TARGET_PPC_GFXOPT" | |
5420 | "stfiwx %1,%y0" | |
5421 | [(set_attr "type" "fpstore")]) | |
5422 | ||
a3170dc6 AH |
5423 | (define_expand "floatsisf2" |
5424 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5425 | (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5426 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5427 | "") | |
5428 | ||
a473029f RK |
5429 | (define_insn "floatdidf2" |
5430 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 5431 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] |
a3170dc6 | 5432 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5433 | "fcfid %0,%1" |
5434 | [(set_attr "type" "fp")]) | |
5435 | ||
05d49501 AM |
5436 | (define_insn_and_split "floatsidf_ppc64" |
5437 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5438 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5439 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5440 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5441 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5442 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5443 | "#" |
ecb62ae7 | 5444 | "&& 1" |
05d49501 AM |
5445 | [(set (match_dup 3) (sign_extend:DI (match_dup 1))) |
5446 | (set (match_dup 2) (match_dup 3)) | |
5447 | (set (match_dup 4) (match_dup 2)) | |
5448 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5449 | "") | |
5450 | ||
5451 | (define_insn_and_split "floatunssidf_ppc64" | |
5452 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5453 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5454 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5455 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5456 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5457 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5458 | "#" |
ecb62ae7 | 5459 | "&& 1" |
05d49501 AM |
5460 | [(set (match_dup 3) (zero_extend:DI (match_dup 1))) |
5461 | (set (match_dup 2) (match_dup 3)) | |
5462 | (set (match_dup 4) (match_dup 2)) | |
5463 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5464 | "") | |
5465 | ||
a473029f | 5466 | (define_insn "fix_truncdfdi2" |
61c07d3c | 5467 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
a473029f | 5468 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] |
a3170dc6 | 5469 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5470 | "fctidz %0,%1" |
5471 | [(set_attr "type" "fp")]) | |
ea112fc4 | 5472 | |
678b7733 AM |
5473 | (define_expand "floatdisf2" |
5474 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5475 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] | |
994cf173 | 5476 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
678b7733 AM |
5477 | " |
5478 | { | |
994cf173 | 5479 | rtx val = operands[1]; |
678b7733 AM |
5480 | if (!flag_unsafe_math_optimizations) |
5481 | { | |
5482 | rtx label = gen_label_rtx (); | |
994cf173 AM |
5483 | val = gen_reg_rtx (DImode); |
5484 | emit_insn (gen_floatdisf2_internal2 (val, operands[1], label)); | |
678b7733 AM |
5485 | emit_label (label); |
5486 | } | |
994cf173 | 5487 | emit_insn (gen_floatdisf2_internal1 (operands[0], val)); |
678b7733 AM |
5488 | DONE; |
5489 | }") | |
5490 | ||
5491 | ;; This is not IEEE compliant if rounding mode is "round to nearest". | |
5492 | ;; If the DI->DF conversion is inexact, then it's possible to suffer | |
5493 | ;; from double rounding. | |
5494 | (define_insn_and_split "floatdisf2_internal1" | |
ea112fc4 | 5495 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
61c07d3c | 5496 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 | 5497 | (clobber (match_scratch:DF 2 "=f"))] |
678b7733 | 5498 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ea112fc4 DE |
5499 | "#" |
5500 | "&& reload_completed" | |
5501 | [(set (match_dup 2) | |
5502 | (float:DF (match_dup 1))) | |
5503 | (set (match_dup 0) | |
5504 | (float_truncate:SF (match_dup 2)))] | |
5505 | "") | |
678b7733 AM |
5506 | |
5507 | ;; Twiddles bits to avoid double rounding. | |
b6d08ca1 | 5508 | ;; Bits that might be truncated when converting to DFmode are replaced |
678b7733 AM |
5509 | ;; by a bit that won't be lost at that stage, but is below the SFmode |
5510 | ;; rounding position. | |
5511 | (define_expand "floatdisf2_internal2" | |
994cf173 AM |
5512 | [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "") |
5513 | (const_int 53))) | |
5514 | (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1) | |
5515 | (const_int 2047))) | |
5516 | (clobber (scratch:CC))]) | |
5517 | (set (match_dup 3) (plus:DI (match_dup 3) | |
5518 | (const_int 1))) | |
5519 | (set (match_dup 0) (plus:DI (match_dup 0) | |
5520 | (const_int 2047))) | |
5521 | (set (match_dup 4) (compare:CCUNS (match_dup 3) | |
5522 | (const_int 3))) | |
5523 | (set (match_dup 0) (ior:DI (match_dup 0) | |
5524 | (match_dup 1))) | |
5525 | (parallel [(set (match_dup 0) (and:DI (match_dup 0) | |
5526 | (const_int -2048))) | |
5527 | (clobber (scratch:CC))]) | |
5528 | (set (pc) (if_then_else (geu (match_dup 4) (const_int 0)) | |
5529 | (label_ref (match_operand:DI 2 "" "")) | |
678b7733 | 5530 | (pc))) |
994cf173 AM |
5531 | (set (match_dup 0) (match_dup 1))] |
5532 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" | |
678b7733 AM |
5533 | " |
5534 | { | |
678b7733 | 5535 | operands[3] = gen_reg_rtx (DImode); |
994cf173 | 5536 | operands[4] = gen_reg_rtx (CCUNSmode); |
678b7733 | 5537 | }") |
1fd4e8c1 RK |
5538 | \f |
5539 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5540 | ;; of instructions. The & constraints are to prevent the register |
5541 | ;; allocator from allocating registers that overlap with the inputs | |
5542 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5543 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5544 | |
266eb58a | 5545 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5546 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5547 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5548 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5549 | "! TARGET_POWERPC64" |
0f645302 MM |
5550 | "* |
5551 | { | |
5552 | if (WORDS_BIG_ENDIAN) | |
5553 | return (GET_CODE (operands[2])) != CONST_INT | |
5554 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5555 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5556 | else | |
5557 | return (GET_CODE (operands[2])) != CONST_INT | |
5558 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5559 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5560 | }" | |
943c15ed DE |
5561 | [(set_attr "type" "two") |
5562 | (set_attr "length" "8")]) | |
1fd4e8c1 | 5563 | |
266eb58a | 5564 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5565 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5566 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5567 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5568 | "! TARGET_POWERPC64" |
5502823b RK |
5569 | "* |
5570 | { | |
0f645302 MM |
5571 | if (WORDS_BIG_ENDIAN) |
5572 | return (GET_CODE (operands[1]) != CONST_INT) | |
5573 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5574 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5575 | else | |
5576 | return (GET_CODE (operands[1]) != CONST_INT) | |
5577 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5578 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5579 | }" |
943c15ed DE |
5580 | [(set_attr "type" "two") |
5581 | (set_attr "length" "8")]) | |
ca7f5001 | 5582 | |
266eb58a | 5583 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5584 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5585 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5586 | "! TARGET_POWERPC64" |
5502823b RK |
5587 | "* |
5588 | { | |
5589 | return (WORDS_BIG_ENDIAN) | |
5590 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5591 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5592 | }" | |
943c15ed DE |
5593 | [(set_attr "type" "two") |
5594 | (set_attr "length" "8")]) | |
ca7f5001 | 5595 | |
8ffd9c51 RK |
5596 | (define_expand "mulsidi3" |
5597 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5598 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5599 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5600 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5601 | " |
5602 | { | |
5603 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5604 | { | |
39403d82 DE |
5605 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5606 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5607 | emit_insn (gen_mull_call ()); |
cf27b467 | 5608 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5609 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5610 | else |
5611 | { | |
5612 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5613 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5614 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5615 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5616 | } |
8ffd9c51 RK |
5617 | DONE; |
5618 | } | |
5619 | else if (TARGET_POWER) | |
5620 | { | |
5621 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5622 | DONE; | |
5623 | } | |
5624 | }") | |
deb9225a | 5625 | |
8ffd9c51 | 5626 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5627 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5628 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5629 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5630 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5631 | "TARGET_POWER" |
b19003d8 | 5632 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5633 | [(set_attr "type" "imul") |
5634 | (set_attr "length" "8")]) | |
deb9225a | 5635 | |
f192bf8b | 5636 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5637 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5638 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5639 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5640 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5641 | "* |
5642 | { | |
5643 | return (WORDS_BIG_ENDIAN) | |
5644 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5645 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5646 | }" | |
8ffd9c51 RK |
5647 | [(set_attr "type" "imul") |
5648 | (set_attr "length" "8")]) | |
deb9225a | 5649 | |
ebedb4dd MM |
5650 | (define_split |
5651 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5652 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5653 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5654 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5655 | [(set (match_dup 3) |
5656 | (truncate:SI | |
5657 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5658 | (sign_extend:DI (match_dup 2))) | |
5659 | (const_int 32)))) | |
5660 | (set (match_dup 4) | |
5661 | (mult:SI (match_dup 1) | |
5662 | (match_dup 2)))] | |
5663 | " | |
5664 | { | |
5665 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5666 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5667 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5668 | }") | |
5669 | ||
f192bf8b DE |
5670 | (define_expand "umulsidi3" |
5671 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5672 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5673 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5674 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5675 | " | |
5676 | { | |
5677 | if (TARGET_POWER) | |
5678 | { | |
5679 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5680 | DONE; | |
5681 | } | |
5682 | }") | |
5683 | ||
5684 | (define_insn "umulsidi3_mq" | |
5685 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5686 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5687 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5688 | (clobber (match_scratch:SI 3 "=q"))] | |
5689 | "TARGET_POWERPC && TARGET_POWER" | |
5690 | "* | |
5691 | { | |
5692 | return (WORDS_BIG_ENDIAN) | |
5693 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5694 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5695 | }" | |
5696 | [(set_attr "type" "imul") | |
5697 | (set_attr "length" "8")]) | |
5698 | ||
5699 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5700 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5701 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5702 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5703 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5704 | "* |
5705 | { | |
5706 | return (WORDS_BIG_ENDIAN) | |
5707 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5708 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5709 | }" | |
5710 | [(set_attr "type" "imul") | |
5711 | (set_attr "length" "8")]) | |
5712 | ||
ebedb4dd MM |
5713 | (define_split |
5714 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5715 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5716 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5717 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5718 | [(set (match_dup 3) |
5719 | (truncate:SI | |
5720 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5721 | (zero_extend:DI (match_dup 2))) | |
5722 | (const_int 32)))) | |
5723 | (set (match_dup 4) | |
5724 | (mult:SI (match_dup 1) | |
5725 | (match_dup 2)))] | |
5726 | " | |
5727 | { | |
5728 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5729 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5730 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5731 | }") | |
5732 | ||
8ffd9c51 RK |
5733 | (define_expand "smulsi3_highpart" |
5734 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5735 | (truncate:SI | |
5736 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5737 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5738 | (sign_extend:DI | |
5739 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5740 | (const_int 32))))] | |
5741 | "" | |
5742 | " | |
5743 | { | |
5744 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5745 | { | |
39403d82 DE |
5746 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5747 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5748 | emit_insn (gen_mulh_call ()); |
39403d82 | 5749 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5750 | DONE; |
5751 | } | |
5752 | else if (TARGET_POWER) | |
5753 | { | |
5754 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5755 | DONE; | |
5756 | } | |
5757 | }") | |
deb9225a | 5758 | |
8ffd9c51 RK |
5759 | (define_insn "smulsi3_highpart_mq" |
5760 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5761 | (truncate:SI | |
fada905b MM |
5762 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5763 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5764 | (sign_extend:DI | |
5765 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5766 | (const_int 32)))) |
5767 | (clobber (match_scratch:SI 3 "=q"))] | |
5768 | "TARGET_POWER" | |
5769 | "mul %0,%1,%2" | |
5770 | [(set_attr "type" "imul")]) | |
deb9225a | 5771 | |
f192bf8b | 5772 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5773 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5774 | (truncate:SI | |
fada905b MM |
5775 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5776 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5777 | (sign_extend:DI | |
5778 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5779 | (const_int 32))))] |
f192bf8b | 5780 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5781 | "mulhw %0,%1,%2" |
5782 | [(set_attr "type" "imul")]) | |
deb9225a | 5783 | |
f192bf8b DE |
5784 | (define_expand "umulsi3_highpart" |
5785 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5786 | (truncate:SI | |
5787 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5788 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5789 | (zero_extend:DI | |
5790 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5791 | (const_int 32))))] | |
5792 | "TARGET_POWERPC" | |
5793 | " | |
5794 | { | |
5795 | if (TARGET_POWER) | |
5796 | { | |
5797 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5798 | DONE; | |
5799 | } | |
5800 | }") | |
5801 | ||
5802 | (define_insn "umulsi3_highpart_mq" | |
5803 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5804 | (truncate:SI | |
5805 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5806 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5807 | (zero_extend:DI | |
5808 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5809 | (const_int 32)))) | |
5810 | (clobber (match_scratch:SI 3 "=q"))] | |
5811 | "TARGET_POWERPC && TARGET_POWER" | |
5812 | "mulhwu %0,%1,%2" | |
5813 | [(set_attr "type" "imul")]) | |
5814 | ||
5815 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5816 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5817 | (truncate:SI | |
5818 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5819 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5820 | (zero_extend:DI | |
5821 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5822 | (const_int 32))))] | |
f192bf8b | 5823 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5824 | "mulhwu %0,%1,%2" |
5825 | [(set_attr "type" "imul")]) | |
5826 | ||
5827 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5828 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5829 | ;; why we have the strange constraints below. | |
5830 | (define_insn "ashldi3_power" | |
5831 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5832 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5833 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5834 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5835 | "TARGET_POWER" | |
5836 | "@ | |
5837 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5838 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5839 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5840 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5841 | [(set_attr "length" "8")]) | |
5842 | ||
5843 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5844 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5845 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5846 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5847 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5848 | "TARGET_POWER" | |
5849 | "@ | |
47ad8c61 | 5850 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5851 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5852 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5853 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5854 | [(set_attr "length" "8")]) | |
5855 | ||
5856 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5857 | ;; just handle shifts by constants. | |
5858 | (define_insn "ashrdi3_power" | |
7093ddee | 5859 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5860 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5861 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5862 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5863 | "TARGET_POWER" | |
5864 | "@ | |
5865 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5866 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5867 | [(set_attr "length" "8")]) | |
4aa74a4f FS |
5868 | |
5869 | (define_insn "ashrdi3_no_power" | |
5870 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") | |
5871 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5872 | (match_operand:SI 2 "const_int_operand" "M,i")))] | |
97727e85 | 5873 | "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN" |
4aa74a4f FS |
5874 | "@ |
5875 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5876 | {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" | |
943c15ed DE |
5877 | [(set_attr "type" "two,three") |
5878 | (set_attr "length" "8,12")]) | |
683bdff7 FJ |
5879 | |
5880 | (define_insn "*ashrdisi3_noppc64" | |
5881 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 5882 | (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
683bdff7 FJ |
5883 | (const_int 32)) 4))] |
5884 | "TARGET_32BIT && !TARGET_POWERPC64" | |
5885 | "* | |
5886 | { | |
5887 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
5888 | return \"\"; | |
5889 | else | |
5890 | return \"mr %0,%1\"; | |
5891 | }" | |
6ae08853 | 5892 | [(set_attr "length" "4")]) |
683bdff7 | 5893 | |
266eb58a DE |
5894 | \f |
5895 | ;; PowerPC64 DImode operations. | |
5896 | ||
ea112fc4 | 5897 | (define_insn_and_split "absdi2" |
266eb58a | 5898 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 5899 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) |
266eb58a DE |
5900 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
5901 | "TARGET_POWERPC64" | |
ea112fc4 DE |
5902 | "#" |
5903 | "&& reload_completed" | |
a260abc9 | 5904 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5905 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 5906 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
5907 | "") |
5908 | ||
ea112fc4 | 5909 | (define_insn_and_split "*nabsdi2" |
266eb58a | 5910 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 5911 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) |
266eb58a DE |
5912 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
5913 | "TARGET_POWERPC64" | |
ea112fc4 DE |
5914 | "#" |
5915 | "&& reload_completed" | |
a260abc9 | 5916 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5917 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 5918 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
5919 | "") |
5920 | ||
266eb58a DE |
5921 | (define_insn "muldi3" |
5922 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5923 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5924 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
5925 | "TARGET_POWERPC64" | |
5926 | "mulld %0,%1,%2" | |
3cb999d8 | 5927 | [(set_attr "type" "lmul")]) |
266eb58a | 5928 | |
9259f3b0 DE |
5929 | (define_insn "*muldi3_internal1" |
5930 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
5931 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
5932 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
5933 | (const_int 0))) | |
5934 | (clobber (match_scratch:DI 3 "=r,r"))] | |
5935 | "TARGET_POWERPC64" | |
5936 | "@ | |
5937 | mulld. %3,%1,%2 | |
5938 | #" | |
5939 | [(set_attr "type" "lmul_compare") | |
5940 | (set_attr "length" "4,8")]) | |
5941 | ||
5942 | (define_split | |
5943 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5944 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5945 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5946 | (const_int 0))) | |
5947 | (clobber (match_scratch:DI 3 ""))] | |
5948 | "TARGET_POWERPC64 && reload_completed" | |
5949 | [(set (match_dup 3) | |
5950 | (mult:DI (match_dup 1) (match_dup 2))) | |
5951 | (set (match_dup 0) | |
5952 | (compare:CC (match_dup 3) | |
5953 | (const_int 0)))] | |
5954 | "") | |
5955 | ||
5956 | (define_insn "*muldi3_internal2" | |
5957 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") | |
5958 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
5959 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
5960 | (const_int 0))) | |
5961 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5962 | (mult:DI (match_dup 1) (match_dup 2)))] | |
5963 | "TARGET_POWERPC64" | |
5964 | "@ | |
5965 | mulld. %0,%1,%2 | |
5966 | #" | |
5967 | [(set_attr "type" "lmul_compare") | |
5968 | (set_attr "length" "4,8")]) | |
5969 | ||
5970 | (define_split | |
5971 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5972 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5973 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5974 | (const_int 0))) | |
5975 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5976 | (mult:DI (match_dup 1) (match_dup 2)))] | |
5977 | "TARGET_POWERPC64 && reload_completed" | |
5978 | [(set (match_dup 0) | |
5979 | (mult:DI (match_dup 1) (match_dup 2))) | |
5980 | (set (match_dup 3) | |
5981 | (compare:CC (match_dup 0) | |
5982 | (const_int 0)))] | |
5983 | "") | |
5984 | ||
266eb58a DE |
5985 | (define_insn "smuldi3_highpart" |
5986 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5987 | (truncate:DI | |
5988 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
5989 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5990 | (sign_extend:TI | |
5991 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
5992 | (const_int 64))))] | |
5993 | "TARGET_POWERPC64" | |
5994 | "mulhd %0,%1,%2" | |
3cb999d8 | 5995 | [(set_attr "type" "lmul")]) |
266eb58a DE |
5996 | |
5997 | (define_insn "umuldi3_highpart" | |
5998 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5999 | (truncate:DI | |
6000 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
6001 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6002 | (zero_extend:TI | |
6003 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6004 | (const_int 64))))] | |
6005 | "TARGET_POWERPC64" | |
6006 | "mulhdu %0,%1,%2" | |
3cb999d8 | 6007 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6008 | |
6009 | (define_expand "divdi3" | |
6010 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6011 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6012 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6013 | "TARGET_POWERPC64" | |
6014 | " | |
6015 | { | |
6016 | if (GET_CODE (operands[2]) == CONST_INT | |
2bfcf297 | 6017 | && INTVAL (operands[2]) > 0 |
266eb58a DE |
6018 | && exact_log2 (INTVAL (operands[2])) >= 0) |
6019 | ; | |
6020 | else | |
6021 | operands[2] = force_reg (DImode, operands[2]); | |
6022 | }") | |
6023 | ||
6024 | (define_expand "moddi3" | |
6025 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6026 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6027 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6028 | "TARGET_POWERPC64" | |
6029 | " | |
6030 | { | |
2bfcf297 | 6031 | int i; |
266eb58a DE |
6032 | rtx temp1; |
6033 | rtx temp2; | |
6034 | ||
2bfcf297 DB |
6035 | if (GET_CODE (operands[2]) != CONST_INT |
6036 | || INTVAL (operands[2]) <= 0 | |
6037 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) | |
266eb58a DE |
6038 | FAIL; |
6039 | ||
6040 | temp1 = gen_reg_rtx (DImode); | |
6041 | temp2 = gen_reg_rtx (DImode); | |
6042 | ||
6043 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6044 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6045 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6046 | DONE; | |
6047 | }") | |
6048 | ||
6049 | (define_insn "" | |
6050 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6051 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
6052 | (match_operand:DI 2 "exact_log2_cint_operand" "N")))] |
6053 | "TARGET_POWERPC64" | |
266eb58a | 6054 | "sradi %0,%1,%p2\;addze %0,%0" |
943c15ed DE |
6055 | [(set_attr "type" "two") |
6056 | (set_attr "length" "8")]) | |
266eb58a DE |
6057 | |
6058 | (define_insn "" | |
9ebbca7d GK |
6059 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6060 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6061 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6062 | (const_int 0))) |
9ebbca7d | 6063 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6064 | "TARGET_64BIT" |
9ebbca7d GK |
6065 | "@ |
6066 | sradi %3,%1,%p2\;addze. %3,%3 | |
6067 | #" | |
266eb58a | 6068 | [(set_attr "type" "compare") |
9ebbca7d GK |
6069 | (set_attr "length" "8,12")]) |
6070 | ||
6071 | (define_split | |
6072 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6073 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6074 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6075 | (const_int 0))) |
6076 | (clobber (match_scratch:DI 3 ""))] | |
2bfcf297 | 6077 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6078 | [(set (match_dup 3) |
6079 | (div:DI (match_dup 1) (match_dup 2))) | |
6080 | (set (match_dup 0) | |
6081 | (compare:CC (match_dup 3) | |
6082 | (const_int 0)))] | |
6083 | "") | |
266eb58a DE |
6084 | |
6085 | (define_insn "" | |
9ebbca7d GK |
6086 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6087 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6088 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6089 | (const_int 0))) |
9ebbca7d | 6090 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6091 | (div:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6092 | "TARGET_64BIT" |
9ebbca7d GK |
6093 | "@ |
6094 | sradi %0,%1,%p2\;addze. %0,%0 | |
6095 | #" | |
266eb58a | 6096 | [(set_attr "type" "compare") |
9ebbca7d | 6097 | (set_attr "length" "8,12")]) |
266eb58a | 6098 | |
9ebbca7d GK |
6099 | (define_split |
6100 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6101 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6102 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6103 | (const_int 0))) |
6104 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6105 | (div:DI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 6106 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6107 | [(set (match_dup 0) |
6108 | (div:DI (match_dup 1) (match_dup 2))) | |
6109 | (set (match_dup 3) | |
6110 | (compare:CC (match_dup 0) | |
6111 | (const_int 0)))] | |
6112 | "") | |
6113 | ||
6114 | (define_insn "" | |
6115 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6116 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6117 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6118 | "TARGET_POWERPC64" |
6119 | "divd %0,%1,%2" | |
3cb999d8 | 6120 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6121 | |
6122 | (define_insn "udivdi3" | |
6123 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6124 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6125 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6126 | "TARGET_POWERPC64" | |
6127 | "divdu %0,%1,%2" | |
3cb999d8 | 6128 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6129 | |
6130 | (define_insn "rotldi3" | |
6131 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6132 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6133 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6134 | "TARGET_POWERPC64" | |
a66078ee | 6135 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6136 | |
a260abc9 | 6137 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6138 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6139 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6140 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6141 | (const_int 0))) |
9ebbca7d | 6142 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6143 | "TARGET_64BIT" |
9ebbca7d GK |
6144 | "@ |
6145 | rld%I2cl. %3,%1,%H2,0 | |
6146 | #" | |
6147 | [(set_attr "type" "delayed_compare") | |
6148 | (set_attr "length" "4,8")]) | |
6149 | ||
6150 | (define_split | |
6151 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6152 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6153 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6154 | (const_int 0))) | |
6155 | (clobber (match_scratch:DI 3 ""))] | |
6156 | "TARGET_POWERPC64 && reload_completed" | |
6157 | [(set (match_dup 3) | |
6158 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6159 | (set (match_dup 0) | |
6160 | (compare:CC (match_dup 3) | |
6161 | (const_int 0)))] | |
6162 | "") | |
266eb58a | 6163 | |
a260abc9 | 6164 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6165 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6166 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6167 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6168 | (const_int 0))) |
9ebbca7d | 6169 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6170 | (rotate:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6171 | "TARGET_64BIT" |
9ebbca7d GK |
6172 | "@ |
6173 | rld%I2cl. %0,%1,%H2,0 | |
6174 | #" | |
6175 | [(set_attr "type" "delayed_compare") | |
6176 | (set_attr "length" "4,8")]) | |
6177 | ||
6178 | (define_split | |
6179 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6180 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6181 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6182 | (const_int 0))) | |
6183 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6184 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6185 | "TARGET_POWERPC64 && reload_completed" | |
6186 | [(set (match_dup 0) | |
6187 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6188 | (set (match_dup 3) | |
6189 | (compare:CC (match_dup 0) | |
6190 | (const_int 0)))] | |
6191 | "") | |
266eb58a | 6192 | |
a260abc9 DE |
6193 | (define_insn "*rotldi3_internal4" |
6194 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6195 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6196 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
ce71f754 | 6197 | (match_operand:DI 3 "mask64_operand" "n")))] |
a260abc9 DE |
6198 | "TARGET_POWERPC64" |
6199 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6200 | ||
6201 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6202 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6203 | (compare:CC (and:DI |
9ebbca7d GK |
6204 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6205 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6206 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6207 | (const_int 0))) |
9ebbca7d | 6208 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6209 | "TARGET_64BIT" |
9ebbca7d GK |
6210 | "@ |
6211 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6212 | #" | |
6213 | [(set_attr "type" "delayed_compare") | |
6214 | (set_attr "length" "4,8")]) | |
6215 | ||
6216 | (define_split | |
6217 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6218 | (compare:CC (and:DI | |
6219 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6220 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6221 | (match_operand:DI 3 "mask64_operand" "")) | |
6222 | (const_int 0))) | |
6223 | (clobber (match_scratch:DI 4 ""))] | |
6224 | "TARGET_POWERPC64 && reload_completed" | |
6225 | [(set (match_dup 4) | |
6226 | (and:DI (rotate:DI (match_dup 1) | |
6227 | (match_dup 2)) | |
6228 | (match_dup 3))) | |
6229 | (set (match_dup 0) | |
6230 | (compare:CC (match_dup 4) | |
6231 | (const_int 0)))] | |
6232 | "") | |
a260abc9 DE |
6233 | |
6234 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6235 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6236 | (compare:CC (and:DI |
9ebbca7d GK |
6237 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6238 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6239 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6240 | (const_int 0))) |
9ebbca7d | 6241 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6242 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6243 | "TARGET_64BIT" |
9ebbca7d GK |
6244 | "@ |
6245 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6246 | #" | |
6247 | [(set_attr "type" "delayed_compare") | |
6248 | (set_attr "length" "4,8")]) | |
6249 | ||
6250 | (define_split | |
6251 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6252 | (compare:CC (and:DI | |
6253 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6254 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6255 | (match_operand:DI 3 "mask64_operand" "")) | |
6256 | (const_int 0))) | |
6257 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6258 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6259 | "TARGET_POWERPC64 && reload_completed" | |
6260 | [(set (match_dup 0) | |
6261 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6262 | (set (match_dup 4) | |
6263 | (compare:CC (match_dup 0) | |
6264 | (const_int 0)))] | |
6265 | "") | |
a260abc9 DE |
6266 | |
6267 | (define_insn "*rotldi3_internal7" | |
6268 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6269 | (zero_extend:DI | |
6270 | (subreg:QI | |
6271 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6272 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6273 | "TARGET_POWERPC64" | |
6274 | "rld%I2cl %0,%1,%H2,56") | |
6275 | ||
6276 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6277 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6278 | (compare:CC (zero_extend:DI |
6279 | (subreg:QI | |
9ebbca7d GK |
6280 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6281 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6282 | (const_int 0))) |
9ebbca7d | 6283 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6284 | "TARGET_64BIT" |
9ebbca7d GK |
6285 | "@ |
6286 | rld%I2cl. %3,%1,%H2,56 | |
6287 | #" | |
6288 | [(set_attr "type" "delayed_compare") | |
6289 | (set_attr "length" "4,8")]) | |
6290 | ||
6291 | (define_split | |
6292 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6293 | (compare:CC (zero_extend:DI | |
6294 | (subreg:QI | |
6295 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6296 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6297 | (const_int 0))) | |
6298 | (clobber (match_scratch:DI 3 ""))] | |
6299 | "TARGET_POWERPC64 && reload_completed" | |
6300 | [(set (match_dup 3) | |
6301 | (zero_extend:DI (subreg:QI | |
6302 | (rotate:DI (match_dup 1) | |
6303 | (match_dup 2)) 0))) | |
6304 | (set (match_dup 0) | |
6305 | (compare:CC (match_dup 3) | |
6306 | (const_int 0)))] | |
6307 | "") | |
a260abc9 DE |
6308 | |
6309 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6310 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6311 | (compare:CC (zero_extend:DI |
6312 | (subreg:QI | |
9ebbca7d GK |
6313 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6314 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6315 | (const_int 0))) |
9ebbca7d | 6316 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6317 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6318 | "TARGET_64BIT" |
9ebbca7d GK |
6319 | "@ |
6320 | rld%I2cl. %0,%1,%H2,56 | |
6321 | #" | |
6322 | [(set_attr "type" "delayed_compare") | |
6323 | (set_attr "length" "4,8")]) | |
6324 | ||
6325 | (define_split | |
6326 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6327 | (compare:CC (zero_extend:DI | |
6328 | (subreg:QI | |
6329 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6330 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6331 | (const_int 0))) | |
6332 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6333 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6334 | "TARGET_POWERPC64 && reload_completed" | |
6335 | [(set (match_dup 0) | |
6336 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6337 | (set (match_dup 3) | |
6338 | (compare:CC (match_dup 0) | |
6339 | (const_int 0)))] | |
6340 | "") | |
a260abc9 DE |
6341 | |
6342 | (define_insn "*rotldi3_internal10" | |
6343 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6344 | (zero_extend:DI | |
6345 | (subreg:HI | |
6346 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6347 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6348 | "TARGET_POWERPC64" | |
6349 | "rld%I2cl %0,%1,%H2,48") | |
6350 | ||
6351 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6352 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6353 | (compare:CC (zero_extend:DI |
6354 | (subreg:HI | |
9ebbca7d GK |
6355 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6356 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6357 | (const_int 0))) |
9ebbca7d | 6358 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6359 | "TARGET_64BIT" |
9ebbca7d GK |
6360 | "@ |
6361 | rld%I2cl. %3,%1,%H2,48 | |
6362 | #" | |
6363 | [(set_attr "type" "delayed_compare") | |
6364 | (set_attr "length" "4,8")]) | |
6365 | ||
6366 | (define_split | |
6367 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6368 | (compare:CC (zero_extend:DI | |
6369 | (subreg:HI | |
6370 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6371 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6372 | (const_int 0))) | |
6373 | (clobber (match_scratch:DI 3 ""))] | |
6374 | "TARGET_POWERPC64 && reload_completed" | |
6375 | [(set (match_dup 3) | |
6376 | (zero_extend:DI (subreg:HI | |
6377 | (rotate:DI (match_dup 1) | |
6378 | (match_dup 2)) 0))) | |
6379 | (set (match_dup 0) | |
6380 | (compare:CC (match_dup 3) | |
6381 | (const_int 0)))] | |
6382 | "") | |
a260abc9 DE |
6383 | |
6384 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6385 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6386 | (compare:CC (zero_extend:DI |
6387 | (subreg:HI | |
9ebbca7d GK |
6388 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6389 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6390 | (const_int 0))) |
9ebbca7d | 6391 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6392 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6393 | "TARGET_64BIT" |
9ebbca7d GK |
6394 | "@ |
6395 | rld%I2cl. %0,%1,%H2,48 | |
6396 | #" | |
6397 | [(set_attr "type" "delayed_compare") | |
6398 | (set_attr "length" "4,8")]) | |
6399 | ||
6400 | (define_split | |
6401 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6402 | (compare:CC (zero_extend:DI | |
6403 | (subreg:HI | |
6404 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6405 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6406 | (const_int 0))) | |
6407 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6408 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6409 | "TARGET_POWERPC64 && reload_completed" | |
6410 | [(set (match_dup 0) | |
6411 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6412 | (set (match_dup 3) | |
6413 | (compare:CC (match_dup 0) | |
6414 | (const_int 0)))] | |
6415 | "") | |
a260abc9 DE |
6416 | |
6417 | (define_insn "*rotldi3_internal13" | |
6418 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6419 | (zero_extend:DI | |
6420 | (subreg:SI | |
6421 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6422 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6423 | "TARGET_POWERPC64" | |
6424 | "rld%I2cl %0,%1,%H2,32") | |
6425 | ||
6426 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6427 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6428 | (compare:CC (zero_extend:DI |
6429 | (subreg:SI | |
9ebbca7d GK |
6430 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6431 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6432 | (const_int 0))) |
9ebbca7d | 6433 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6434 | "TARGET_64BIT" |
9ebbca7d GK |
6435 | "@ |
6436 | rld%I2cl. %3,%1,%H2,32 | |
6437 | #" | |
6438 | [(set_attr "type" "delayed_compare") | |
6439 | (set_attr "length" "4,8")]) | |
6440 | ||
6441 | (define_split | |
6442 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6443 | (compare:CC (zero_extend:DI | |
6444 | (subreg:SI | |
6445 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6446 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6447 | (const_int 0))) | |
6448 | (clobber (match_scratch:DI 3 ""))] | |
6449 | "TARGET_POWERPC64 && reload_completed" | |
6450 | [(set (match_dup 3) | |
6451 | (zero_extend:DI (subreg:SI | |
6452 | (rotate:DI (match_dup 1) | |
6453 | (match_dup 2)) 0))) | |
6454 | (set (match_dup 0) | |
6455 | (compare:CC (match_dup 3) | |
6456 | (const_int 0)))] | |
6457 | "") | |
a260abc9 DE |
6458 | |
6459 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6460 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6461 | (compare:CC (zero_extend:DI |
6462 | (subreg:SI | |
9ebbca7d GK |
6463 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6464 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6465 | (const_int 0))) |
9ebbca7d | 6466 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6467 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6468 | "TARGET_64BIT" |
9ebbca7d GK |
6469 | "@ |
6470 | rld%I2cl. %0,%1,%H2,32 | |
6471 | #" | |
6472 | [(set_attr "type" "delayed_compare") | |
6473 | (set_attr "length" "4,8")]) | |
6474 | ||
6475 | (define_split | |
6476 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6477 | (compare:CC (zero_extend:DI | |
6478 | (subreg:SI | |
6479 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6480 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6481 | (const_int 0))) | |
6482 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6483 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6484 | "TARGET_POWERPC64 && reload_completed" | |
6485 | [(set (match_dup 0) | |
6486 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6487 | (set (match_dup 3) | |
6488 | (compare:CC (match_dup 0) | |
6489 | (const_int 0)))] | |
6490 | "") | |
a260abc9 | 6491 | |
266eb58a DE |
6492 | (define_expand "ashldi3" |
6493 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6494 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6495 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6496 | "TARGET_POWERPC64 || TARGET_POWER" | |
6497 | " | |
6498 | { | |
6499 | if (TARGET_POWERPC64) | |
6500 | ; | |
6501 | else if (TARGET_POWER) | |
6502 | { | |
6503 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6504 | DONE; | |
6505 | } | |
6506 | else | |
6507 | FAIL; | |
6508 | }") | |
6509 | ||
e2c953b6 | 6510 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
6511 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6512 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6513 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6514 | "TARGET_POWERPC64" | |
943c15ed | 6515 | "sld%I2 %0,%1,%H2") |
6ae08853 | 6516 | |
e2c953b6 | 6517 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
6518 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6519 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6520 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6521 | (const_int 0))) |
9ebbca7d | 6522 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6523 | "TARGET_64BIT" |
9ebbca7d GK |
6524 | "@ |
6525 | sld%I2. %3,%1,%H2 | |
6526 | #" | |
6527 | [(set_attr "type" "delayed_compare") | |
6528 | (set_attr "length" "4,8")]) | |
6ae08853 | 6529 | |
9ebbca7d GK |
6530 | (define_split |
6531 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6532 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6533 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6534 | (const_int 0))) | |
6535 | (clobber (match_scratch:DI 3 ""))] | |
6536 | "TARGET_POWERPC64 && reload_completed" | |
6537 | [(set (match_dup 3) | |
6538 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6539 | (set (match_dup 0) | |
6540 | (compare:CC (match_dup 3) | |
6541 | (const_int 0)))] | |
6542 | "") | |
6543 | ||
e2c953b6 | 6544 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
6545 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6546 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6547 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6548 | (const_int 0))) |
9ebbca7d | 6549 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6550 | (ashift:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6551 | "TARGET_64BIT" |
9ebbca7d GK |
6552 | "@ |
6553 | sld%I2. %0,%1,%H2 | |
6554 | #" | |
6555 | [(set_attr "type" "delayed_compare") | |
6556 | (set_attr "length" "4,8")]) | |
6557 | ||
6558 | (define_split | |
6559 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6560 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6561 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6562 | (const_int 0))) | |
6563 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6564 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6565 | "TARGET_POWERPC64 && reload_completed" | |
6566 | [(set (match_dup 0) | |
6567 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6568 | (set (match_dup 3) | |
6569 | (compare:CC (match_dup 0) | |
6570 | (const_int 0)))] | |
6571 | "") | |
266eb58a | 6572 | |
e2c953b6 | 6573 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
6574 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6575 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6576 | (match_operand:SI 2 "const_int_operand" "i")) | |
c5059423 AM |
6577 | (match_operand:DI 3 "const_int_operand" "n")))] |
6578 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" | |
e2c953b6 | 6579 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 6580 | |
e2c953b6 | 6581 | (define_insn "ashldi3_internal5" |
9ebbca7d | 6582 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6583 | (compare:CC |
9ebbca7d GK |
6584 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6585 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6586 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6587 | (const_int 0))) |
9ebbca7d | 6588 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6589 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6590 | "@ |
e2c953b6 | 6591 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
6592 | #" |
6593 | [(set_attr "type" "delayed_compare") | |
6594 | (set_attr "length" "4,8")]) | |
6595 | ||
6596 | (define_split | |
6597 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6598 | (compare:CC | |
6599 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6600 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6601 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6602 | (const_int 0))) |
6603 | (clobber (match_scratch:DI 4 ""))] | |
c5059423 AM |
6604 | "TARGET_POWERPC64 && reload_completed |
6605 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
9ebbca7d GK |
6606 | [(set (match_dup 4) |
6607 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 6608 | (match_dup 3))) |
9ebbca7d GK |
6609 | (set (match_dup 0) |
6610 | (compare:CC (match_dup 4) | |
6611 | (const_int 0)))] | |
6612 | "") | |
3cb999d8 | 6613 | |
e2c953b6 | 6614 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 6615 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6616 | (compare:CC |
9ebbca7d GK |
6617 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6618 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6619 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6620 | (const_int 0))) |
9ebbca7d | 6621 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 6622 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6623 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6624 | "@ |
e2c953b6 | 6625 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
6626 | #" |
6627 | [(set_attr "type" "delayed_compare") | |
6628 | (set_attr "length" "4,8")]) | |
6629 | ||
6630 | (define_split | |
6631 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6632 | (compare:CC | |
6633 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6634 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6635 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6636 | (const_int 0))) |
6637 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6638 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
c5059423 AM |
6639 | "TARGET_POWERPC64 && reload_completed |
6640 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
6641 | [(set (match_dup 0) | |
6642 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6643 | (match_dup 3))) | |
6644 | (set (match_dup 4) | |
6645 | (compare:CC (match_dup 0) | |
6646 | (const_int 0)))] | |
6647 | "") | |
6648 | ||
6649 | (define_insn "*ashldi3_internal7" | |
6650 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6651 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6652 | (match_operand:SI 2 "const_int_operand" "i")) | |
ce71f754 | 6653 | (match_operand:DI 3 "mask64_operand" "n")))] |
c5059423 AM |
6654 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" |
6655 | "rldicr %0,%1,%H2,%S3") | |
6656 | ||
6657 | (define_insn "ashldi3_internal8" | |
6658 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6659 | (compare:CC | |
6660 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6661 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6662 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6663 | (const_int 0))) |
6664 | (clobber (match_scratch:DI 4 "=r,r"))] | |
683bdff7 | 6665 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6666 | "@ |
6667 | rldicr. %4,%1,%H2,%S3 | |
6668 | #" | |
6669 | [(set_attr "type" "delayed_compare") | |
6670 | (set_attr "length" "4,8")]) | |
6671 | ||
6672 | (define_split | |
6673 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6674 | (compare:CC | |
6675 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6676 | (match_operand:SI 2 "const_int_operand" "")) | |
6677 | (match_operand:DI 3 "mask64_operand" "")) | |
6678 | (const_int 0))) | |
6679 | (clobber (match_scratch:DI 4 ""))] | |
6680 | "TARGET_POWERPC64 && reload_completed | |
6681 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6682 | [(set (match_dup 4) | |
6683 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6684 | (match_dup 3))) | |
6685 | (set (match_dup 0) | |
6686 | (compare:CC (match_dup 4) | |
6687 | (const_int 0)))] | |
6688 | "") | |
6689 | ||
6690 | (define_insn "*ashldi3_internal9" | |
6691 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
6692 | (compare:CC | |
6693 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6694 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6695 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6696 | (const_int 0))) |
6697 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6698 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 6699 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6700 | "@ |
6701 | rldicr. %0,%1,%H2,%S3 | |
6702 | #" | |
6703 | [(set_attr "type" "delayed_compare") | |
6704 | (set_attr "length" "4,8")]) | |
6705 | ||
6706 | (define_split | |
6707 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6708 | (compare:CC | |
6709 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6710 | (match_operand:SI 2 "const_int_operand" "")) | |
6711 | (match_operand:DI 3 "mask64_operand" "")) | |
6712 | (const_int 0))) | |
6713 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6714 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6715 | "TARGET_POWERPC64 && reload_completed | |
6716 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
9ebbca7d | 6717 | [(set (match_dup 0) |
e2c953b6 DE |
6718 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
6719 | (match_dup 3))) | |
9ebbca7d GK |
6720 | (set (match_dup 4) |
6721 | (compare:CC (match_dup 0) | |
6722 | (const_int 0)))] | |
6723 | "") | |
6724 | ||
6725 | (define_expand "lshrdi3" | |
266eb58a DE |
6726 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6727 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6728 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6729 | "TARGET_POWERPC64 || TARGET_POWER" | |
6730 | " | |
6731 | { | |
6732 | if (TARGET_POWERPC64) | |
6733 | ; | |
6734 | else if (TARGET_POWER) | |
6735 | { | |
6736 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
6737 | DONE; | |
6738 | } | |
6739 | else | |
6740 | FAIL; | |
6741 | }") | |
6742 | ||
e2c953b6 | 6743 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
6744 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6745 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6746 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6747 | "TARGET_POWERPC64" | |
a66078ee | 6748 | "srd%I2 %0,%1,%H2") |
266eb58a | 6749 | |
e2c953b6 | 6750 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
6751 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6752 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6753 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 6754 | (const_int 0))) |
9ebbca7d | 6755 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6756 | "TARGET_64BIT " |
9ebbca7d GK |
6757 | "@ |
6758 | srd%I2. %3,%1,%H2 | |
6759 | #" | |
6760 | [(set_attr "type" "delayed_compare") | |
6761 | (set_attr "length" "4,8")]) | |
6762 | ||
6763 | (define_split | |
6764 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6765 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6766 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6767 | (const_int 0))) | |
6768 | (clobber (match_scratch:DI 3 ""))] | |
6769 | "TARGET_POWERPC64 && reload_completed" | |
6770 | [(set (match_dup 3) | |
6771 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6772 | (set (match_dup 0) | |
6773 | (compare:CC (match_dup 3) | |
6774 | (const_int 0)))] | |
6775 | "") | |
266eb58a | 6776 | |
e2c953b6 | 6777 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
6778 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6779 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6780 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6781 | (const_int 0))) |
9ebbca7d | 6782 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 6783 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6784 | "TARGET_64BIT" |
9ebbca7d GK |
6785 | "@ |
6786 | srd%I2. %0,%1,%H2 | |
6787 | #" | |
6788 | [(set_attr "type" "delayed_compare") | |
6789 | (set_attr "length" "4,8")]) | |
6790 | ||
6791 | (define_split | |
6792 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6793 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6794 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6795 | (const_int 0))) | |
6796 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6797 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
6798 | "TARGET_POWERPC64 && reload_completed" | |
6799 | [(set (match_dup 0) | |
6800 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6801 | (set (match_dup 3) | |
6802 | (compare:CC (match_dup 0) | |
6803 | (const_int 0)))] | |
6804 | "") | |
266eb58a DE |
6805 | |
6806 | (define_expand "ashrdi3" | |
6807 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6808 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6809 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
97727e85 | 6810 | "WORDS_BIG_ENDIAN" |
266eb58a DE |
6811 | " |
6812 | { | |
6813 | if (TARGET_POWERPC64) | |
6814 | ; | |
6815 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
6816 | { | |
6817 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
6818 | DONE; | |
6819 | } | |
97727e85 AH |
6820 | else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT |
6821 | && WORDS_BIG_ENDIAN) | |
4aa74a4f FS |
6822 | { |
6823 | emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); | |
6824 | DONE; | |
6825 | } | |
266eb58a DE |
6826 | else |
6827 | FAIL; | |
6828 | }") | |
6829 | ||
e2c953b6 | 6830 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
6831 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6832 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6833 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6834 | "TARGET_POWERPC64" | |
375490e0 | 6835 | "srad%I2 %0,%1,%H2") |
266eb58a | 6836 | |
e2c953b6 | 6837 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
6838 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6839 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6840 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6841 | (const_int 0))) |
9ebbca7d | 6842 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6843 | "TARGET_64BIT" |
9ebbca7d GK |
6844 | "@ |
6845 | srad%I2. %3,%1,%H2 | |
6846 | #" | |
6847 | [(set_attr "type" "delayed_compare") | |
6848 | (set_attr "length" "4,8")]) | |
6849 | ||
6850 | (define_split | |
6851 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6852 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6853 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6854 | (const_int 0))) | |
6855 | (clobber (match_scratch:DI 3 ""))] | |
6856 | "TARGET_POWERPC64 && reload_completed" | |
6857 | [(set (match_dup 3) | |
6858 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6859 | (set (match_dup 0) | |
6860 | (compare:CC (match_dup 3) | |
6861 | (const_int 0)))] | |
6862 | "") | |
266eb58a | 6863 | |
e2c953b6 | 6864 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
6865 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6866 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6867 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6868 | (const_int 0))) |
9ebbca7d | 6869 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6870 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6871 | "TARGET_64BIT" |
9ebbca7d GK |
6872 | "@ |
6873 | srad%I2. %0,%1,%H2 | |
6874 | #" | |
6875 | [(set_attr "type" "delayed_compare") | |
6876 | (set_attr "length" "4,8")]) | |
6877 | ||
6878 | (define_split | |
6879 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6880 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6881 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6882 | (const_int 0))) | |
6883 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6884 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
6885 | "TARGET_POWERPC64 && reload_completed" | |
6886 | [(set (match_dup 0) | |
6887 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6888 | (set (match_dup 3) | |
6889 | (compare:CC (match_dup 0) | |
6890 | (const_int 0)))] | |
6891 | "") | |
815cdc52 | 6892 | |
29ae5b89 | 6893 | (define_insn "anddi3" |
e1e2e653 NS |
6894 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
6895 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r") | |
6896 | (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t"))) | |
6897 | (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))] | |
6ffc8580 | 6898 | "TARGET_POWERPC64" |
266eb58a DE |
6899 | "@ |
6900 | and %0,%1,%2 | |
29ae5b89 | 6901 | rldic%B2 %0,%1,0,%S2 |
e1e2e653 | 6902 | rlwinm %0,%1,0,%m2,%M2 |
29ae5b89 | 6903 | andi. %0,%1,%b2 |
0ba1b2ff AM |
6904 | andis. %0,%1,%u2 |
6905 | #" | |
e1e2e653 NS |
6906 | [(set_attr "type" "*,*,*,compare,compare,*") |
6907 | (set_attr "length" "4,4,4,4,4,8")]) | |
0ba1b2ff AM |
6908 | |
6909 | (define_split | |
6910 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6911 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6912 | (match_operand:DI 2 "mask64_2_operand" ""))) | |
6913 | (clobber (match_scratch:CC 3 ""))] | |
6914 | "TARGET_POWERPC64 | |
6915 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
6916 | && !mask64_operand (operands[2], DImode)" | |
6917 | [(set (match_dup 0) | |
6918 | (and:DI (rotate:DI (match_dup 1) | |
6919 | (match_dup 4)) | |
6920 | (match_dup 5))) | |
6921 | (set (match_dup 0) | |
6922 | (and:DI (rotate:DI (match_dup 0) | |
6923 | (match_dup 6)) | |
6924 | (match_dup 7)))] | |
0ba1b2ff AM |
6925 | { |
6926 | build_mask64_2_operands (operands[2], &operands[4]); | |
e1e2e653 | 6927 | }) |
266eb58a | 6928 | |
a260abc9 | 6929 | (define_insn "*anddi3_internal2" |
0ba1b2ff AM |
6930 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
6931 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
6932 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 6933 | (const_int 0))) |
0ba1b2ff AM |
6934 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r")) |
6935 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] | |
683bdff7 | 6936 | "TARGET_64BIT" |
266eb58a DE |
6937 | "@ |
6938 | and. %3,%1,%2 | |
6c873122 | 6939 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
6940 | andi. %3,%1,%b2 |
6941 | andis. %3,%1,%u2 | |
9ebbca7d GK |
6942 | # |
6943 | # | |
6944 | # | |
0ba1b2ff AM |
6945 | # |
6946 | # | |
9ebbca7d | 6947 | #" |
0ba1b2ff AM |
6948 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
6949 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
6950 | |
6951 | (define_split | |
6952 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6953 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6954 | (match_operand:DI 2 "and64_operand" "")) | |
6955 | (const_int 0))) | |
6956 | (clobber (match_scratch:DI 3 "")) | |
6957 | (clobber (match_scratch:CC 4 ""))] | |
6958 | "TARGET_POWERPC64 && reload_completed" | |
6959 | [(parallel [(set (match_dup 3) | |
6960 | (and:DI (match_dup 1) | |
6961 | (match_dup 2))) | |
6962 | (clobber (match_dup 4))]) | |
6963 | (set (match_dup 0) | |
6964 | (compare:CC (match_dup 3) | |
6965 | (const_int 0)))] | |
6966 | "") | |
266eb58a | 6967 | |
0ba1b2ff AM |
6968 | (define_split |
6969 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
6970 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6971 | (match_operand:DI 2 "mask64_2_operand" "")) | |
6972 | (const_int 0))) | |
6973 | (clobber (match_scratch:DI 3 "")) | |
6974 | (clobber (match_scratch:CC 4 ""))] | |
6975 | "TARGET_POWERPC64 && reload_completed | |
6976 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
6977 | && !mask64_operand (operands[2], DImode)" | |
6978 | [(set (match_dup 3) | |
6979 | (and:DI (rotate:DI (match_dup 1) | |
6980 | (match_dup 5)) | |
6981 | (match_dup 6))) | |
6982 | (parallel [(set (match_dup 0) | |
6983 | (compare:CC (and:DI (rotate:DI (match_dup 3) | |
6984 | (match_dup 7)) | |
6985 | (match_dup 8)) | |
6986 | (const_int 0))) | |
6987 | (clobber (match_dup 3))])] | |
6988 | " | |
6989 | { | |
6990 | build_mask64_2_operands (operands[2], &operands[5]); | |
6991 | }") | |
6992 | ||
a260abc9 | 6993 | (define_insn "*anddi3_internal3" |
0ba1b2ff AM |
6994 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
6995 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
6996 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 6997 | (const_int 0))) |
0ba1b2ff | 6998 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
9ebbca7d | 6999 | (and:DI (match_dup 1) (match_dup 2))) |
0ba1b2ff | 7000 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] |
683bdff7 | 7001 | "TARGET_64BIT" |
266eb58a DE |
7002 | "@ |
7003 | and. %0,%1,%2 | |
6c873122 | 7004 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
7005 | andi. %0,%1,%b2 |
7006 | andis. %0,%1,%u2 | |
9ebbca7d GK |
7007 | # |
7008 | # | |
7009 | # | |
0ba1b2ff AM |
7010 | # |
7011 | # | |
9ebbca7d | 7012 | #" |
0ba1b2ff AM |
7013 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7014 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7015 | |
7016 | (define_split | |
7017 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7018 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7019 | (match_operand:DI 2 "and64_operand" "")) | |
7020 | (const_int 0))) | |
7021 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7022 | (and:DI (match_dup 1) (match_dup 2))) | |
7023 | (clobber (match_scratch:CC 4 ""))] | |
7024 | "TARGET_POWERPC64 && reload_completed" | |
7025 | [(parallel [(set (match_dup 0) | |
7026 | (and:DI (match_dup 1) (match_dup 2))) | |
7027 | (clobber (match_dup 4))]) | |
7028 | (set (match_dup 3) | |
7029 | (compare:CC (match_dup 0) | |
7030 | (const_int 0)))] | |
7031 | "") | |
266eb58a | 7032 | |
0ba1b2ff AM |
7033 | (define_split |
7034 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
7035 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7036 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7037 | (const_int 0))) | |
7038 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7039 | (and:DI (match_dup 1) (match_dup 2))) | |
7040 | (clobber (match_scratch:CC 4 ""))] | |
7041 | "TARGET_POWERPC64 && reload_completed | |
7042 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7043 | && !mask64_operand (operands[2], DImode)" | |
7044 | [(set (match_dup 0) | |
7045 | (and:DI (rotate:DI (match_dup 1) | |
7046 | (match_dup 5)) | |
7047 | (match_dup 6))) | |
7048 | (parallel [(set (match_dup 3) | |
7049 | (compare:CC (and:DI (rotate:DI (match_dup 0) | |
7050 | (match_dup 7)) | |
7051 | (match_dup 8)) | |
7052 | (const_int 0))) | |
7053 | (set (match_dup 0) | |
7054 | (and:DI (rotate:DI (match_dup 0) | |
7055 | (match_dup 7)) | |
7056 | (match_dup 8)))])] | |
7057 | " | |
7058 | { | |
7059 | build_mask64_2_operands (operands[2], &operands[5]); | |
7060 | }") | |
7061 | ||
a260abc9 | 7062 | (define_expand "iordi3" |
266eb58a | 7063 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 7064 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 7065 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 7066 | "TARGET_POWERPC64" |
266eb58a DE |
7067 | " |
7068 | { | |
dfbdccdb | 7069 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 7070 | { |
dfbdccdb | 7071 | HOST_WIDE_INT value; |
677a9668 | 7072 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 7073 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 7074 | |
dfbdccdb GK |
7075 | if (GET_CODE (operands[2]) == CONST_INT) |
7076 | { | |
7077 | value = INTVAL (operands[2]); | |
7078 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7079 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7080 | } | |
e2c953b6 | 7081 | else |
dfbdccdb GK |
7082 | { |
7083 | value = CONST_DOUBLE_LOW (operands[2]); | |
7084 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7085 | immed_double_const (value | |
7086 | & (~ (HOST_WIDE_INT) 0xffff), | |
7087 | 0, DImode))); | |
7088 | } | |
e2c953b6 | 7089 | |
9ebbca7d GK |
7090 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7091 | DONE; | |
7092 | } | |
266eb58a DE |
7093 | }") |
7094 | ||
a260abc9 DE |
7095 | (define_expand "xordi3" |
7096 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7097 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 7098 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
7099 | "TARGET_POWERPC64" |
7100 | " | |
7101 | { | |
dfbdccdb | 7102 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 7103 | { |
dfbdccdb | 7104 | HOST_WIDE_INT value; |
677a9668 | 7105 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
7106 | ? operands[0] : gen_reg_rtx (DImode)); |
7107 | ||
dfbdccdb GK |
7108 | if (GET_CODE (operands[2]) == CONST_INT) |
7109 | { | |
7110 | value = INTVAL (operands[2]); | |
7111 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7112 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7113 | } | |
e2c953b6 | 7114 | else |
dfbdccdb GK |
7115 | { |
7116 | value = CONST_DOUBLE_LOW (operands[2]); | |
7117 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7118 | immed_double_const (value | |
7119 | & (~ (HOST_WIDE_INT) 0xffff), | |
7120 | 0, DImode))); | |
7121 | } | |
e2c953b6 | 7122 | |
9ebbca7d GK |
7123 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7124 | DONE; | |
7125 | } | |
a260abc9 DE |
7126 | }") |
7127 | ||
dfbdccdb | 7128 | (define_insn "*booldi3_internal1" |
266eb58a | 7129 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 7130 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7131 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
7132 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 7133 | "TARGET_POWERPC64" |
1fd4e8c1 | 7134 | "@ |
dfbdccdb GK |
7135 | %q3 %0,%1,%2 |
7136 | %q3i %0,%1,%b2 | |
7137 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 7138 | |
dfbdccdb | 7139 | (define_insn "*booldi3_internal2" |
9ebbca7d | 7140 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 7141 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
7142 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
7143 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7144 | (const_int 0))) | |
9ebbca7d | 7145 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7146 | "TARGET_64BIT" |
9ebbca7d | 7147 | "@ |
dfbdccdb | 7148 | %q4. %3,%1,%2 |
9ebbca7d GK |
7149 | #" |
7150 | [(set_attr "type" "compare") | |
7151 | (set_attr "length" "4,8")]) | |
7152 | ||
7153 | (define_split | |
7154 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7155 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7156 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7157 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7158 | (const_int 0))) |
9ebbca7d GK |
7159 | (clobber (match_scratch:DI 3 ""))] |
7160 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7161 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7162 | (set (match_dup 0) |
7163 | (compare:CC (match_dup 3) | |
7164 | (const_int 0)))] | |
7165 | "") | |
1fd4e8c1 | 7166 | |
dfbdccdb | 7167 | (define_insn "*booldi3_internal3" |
9ebbca7d | 7168 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7169 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7170 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7171 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7172 | (const_int 0))) | |
9ebbca7d | 7173 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7174 | (match_dup 4))] |
683bdff7 | 7175 | "TARGET_64BIT" |
9ebbca7d | 7176 | "@ |
dfbdccdb | 7177 | %q4. %0,%1,%2 |
9ebbca7d GK |
7178 | #" |
7179 | [(set_attr "type" "compare") | |
7180 | (set_attr "length" "4,8")]) | |
7181 | ||
7182 | (define_split | |
e72247f4 | 7183 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7184 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7185 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7186 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7187 | (const_int 0))) |
75540af0 | 7188 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7189 | (match_dup 4))] |
9ebbca7d | 7190 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7191 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7192 | (set (match_dup 3) |
7193 | (compare:CC (match_dup 0) | |
7194 | (const_int 0)))] | |
7195 | "") | |
1fd4e8c1 | 7196 | |
6ae08853 | 7197 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 7198 | ;; each of which does one 16-bit part. This is used by combine. |
266eb58a DE |
7199 | |
7200 | (define_split | |
7201 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 7202 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7203 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7204 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7205 | "TARGET_POWERPC64" |
dfbdccdb GK |
7206 | [(set (match_dup 0) (match_dup 4)) |
7207 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7208 | " |
7209 | { | |
dfbdccdb | 7210 | rtx i3,i4; |
6ae08853 | 7211 | |
9ebbca7d GK |
7212 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7213 | { | |
7214 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7215 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7216 | 0, DImode); |
dfbdccdb | 7217 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7218 | } |
7219 | else | |
7220 | { | |
dfbdccdb | 7221 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7222 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7223 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7224 | } |
1c563bed | 7225 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7226 | operands[1], i3); |
1c563bed | 7227 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7228 | operands[0], i4); |
1fd4e8c1 RK |
7229 | }") |
7230 | ||
dfbdccdb | 7231 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7232 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7233 | (match_operator:DI 3 "boolean_operator" |
7234 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7235 | (match_operand:DI 2 "gpc_reg_operand" "r")]))] |
a473029f | 7236 | "TARGET_POWERPC64" |
1d328b19 | 7237 | "%q3 %0,%2,%1") |
a473029f | 7238 | |
dfbdccdb | 7239 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7240 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7241 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7242 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7243 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7244 | (const_int 0))) | |
9ebbca7d | 7245 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7246 | "TARGET_64BIT" |
9ebbca7d | 7247 | "@ |
1d328b19 | 7248 | %q4. %3,%2,%1 |
9ebbca7d GK |
7249 | #" |
7250 | [(set_attr "type" "compare") | |
7251 | (set_attr "length" "4,8")]) | |
7252 | ||
7253 | (define_split | |
7254 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7255 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7256 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7257 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7258 | (const_int 0))) |
9ebbca7d GK |
7259 | (clobber (match_scratch:DI 3 ""))] |
7260 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7261 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7262 | (set (match_dup 0) |
7263 | (compare:CC (match_dup 3) | |
7264 | (const_int 0)))] | |
7265 | "") | |
a473029f | 7266 | |
dfbdccdb | 7267 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7268 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7269 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7270 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7271 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7272 | (const_int 0))) | |
9ebbca7d | 7273 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7274 | (match_dup 4))] |
683bdff7 | 7275 | "TARGET_64BIT" |
9ebbca7d | 7276 | "@ |
1d328b19 | 7277 | %q4. %0,%2,%1 |
9ebbca7d GK |
7278 | #" |
7279 | [(set_attr "type" "compare") | |
7280 | (set_attr "length" "4,8")]) | |
7281 | ||
7282 | (define_split | |
e72247f4 | 7283 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7284 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7285 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7286 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7287 | (const_int 0))) |
75540af0 | 7288 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7289 | (match_dup 4))] |
9ebbca7d | 7290 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7291 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7292 | (set (match_dup 3) |
7293 | (compare:CC (match_dup 0) | |
7294 | (const_int 0)))] | |
7295 | "") | |
266eb58a | 7296 | |
dfbdccdb | 7297 | (define_insn "*boolccdi3_internal1" |
a473029f | 7298 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7299 | (match_operator:DI 3 "boolean_operator" |
7300 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7301 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] |
a473029f | 7302 | "TARGET_POWERPC64" |
dfbdccdb | 7303 | "%q3 %0,%1,%2") |
a473029f | 7304 | |
dfbdccdb | 7305 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7306 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7307 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7308 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7309 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7310 | (const_int 0))) | |
9ebbca7d | 7311 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7312 | "TARGET_64BIT" |
9ebbca7d | 7313 | "@ |
dfbdccdb | 7314 | %q4. %3,%1,%2 |
9ebbca7d GK |
7315 | #" |
7316 | [(set_attr "type" "compare") | |
7317 | (set_attr "length" "4,8")]) | |
7318 | ||
7319 | (define_split | |
7320 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7321 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7322 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7323 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7324 | (const_int 0))) |
9ebbca7d GK |
7325 | (clobber (match_scratch:DI 3 ""))] |
7326 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7327 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7328 | (set (match_dup 0) |
7329 | (compare:CC (match_dup 3) | |
7330 | (const_int 0)))] | |
7331 | "") | |
266eb58a | 7332 | |
dfbdccdb | 7333 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7334 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7335 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7336 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7337 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7338 | (const_int 0))) | |
9ebbca7d | 7339 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7340 | (match_dup 4))] |
683bdff7 | 7341 | "TARGET_64BIT" |
9ebbca7d | 7342 | "@ |
dfbdccdb | 7343 | %q4. %0,%1,%2 |
9ebbca7d GK |
7344 | #" |
7345 | [(set_attr "type" "compare") | |
7346 | (set_attr "length" "4,8")]) | |
7347 | ||
7348 | (define_split | |
e72247f4 | 7349 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7350 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7351 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7352 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7353 | (const_int 0))) |
75540af0 | 7354 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7355 | (match_dup 4))] |
9ebbca7d | 7356 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7357 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7358 | (set (match_dup 3) |
7359 | (compare:CC (match_dup 0) | |
7360 | (const_int 0)))] | |
7361 | "") | |
dfbdccdb | 7362 | \f |
1fd4e8c1 | 7363 | ;; Now define ways of moving data around. |
4697a36c MM |
7364 | |
7365 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
7366 | ;; The output of this could be r0, but we make a very strong |
7367 | ;; preference for a base register because it will usually | |
7368 | ;; be needed there. | |
4697a36c | 7369 | (define_insn "elf_high" |
9ebbca7d | 7370 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 7371 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 7372 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 7373 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
7374 | |
7375 | (define_insn "elf_low" | |
9ebbca7d GK |
7376 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
7377 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 7378 | (match_operand 2 "" "")))] |
0ad91047 | 7379 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
7380 | "@ |
7381 | {cal|la} %0,%2@l(%1) | |
81eace42 | 7382 | {ai|addic} %0,%1,%K2") |
4697a36c | 7383 | |
ee890fe2 | 7384 | |
766a866c MM |
7385 | ;; Set up a register with a value from the GOT table |
7386 | ||
7387 | (define_expand "movsi_got" | |
52d3af72 | 7388 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7389 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
615158e2 | 7390 | (match_dup 2)] UNSPEC_MOVSI_GOT))] |
f607bc57 | 7391 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7392 | " |
7393 | { | |
38c1f2d7 MM |
7394 | if (GET_CODE (operands[1]) == CONST) |
7395 | { | |
7396 | rtx offset = const0_rtx; | |
7397 | HOST_WIDE_INT value; | |
7398 | ||
7399 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7400 | value = INTVAL (offset); | |
7401 | if (value != 0) | |
7402 | { | |
677a9668 | 7403 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7404 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7405 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7406 | DONE; | |
7407 | } | |
7408 | } | |
7409 | ||
c4c40373 | 7410 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7411 | }") |
7412 | ||
84f414bc | 7413 | (define_insn "*movsi_got_internal" |
52d3af72 | 7414 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d | 7415 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7416 | (match_operand:SI 2 "gpc_reg_operand" "b")] |
7417 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7418 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7419 | "{l|lwz} %0,%a1@got(%2)" |
7420 | [(set_attr "type" "load")]) | |
7421 | ||
b22b9b3e JL |
7422 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7423 | ;; didn't get allocated to a hard register. | |
6ae08853 | 7424 | (define_split |
75540af0 | 7425 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7426 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7427 | (match_operand:SI 2 "memory_operand" "")] |
7428 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7429 | "DEFAULT_ABI == ABI_V4 |
b22b9b3e JL |
7430 | && flag_pic == 1 |
7431 | && (reload_in_progress || reload_completed)" | |
7432 | [(set (match_dup 0) (match_dup 2)) | |
615158e2 JJ |
7433 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] |
7434 | UNSPEC_MOVSI_GOT))] | |
b22b9b3e JL |
7435 | "") |
7436 | ||
1fd4e8c1 RK |
7437 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7438 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7439 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7440 | ;; integers in the TOC. | |
7441 | (define_expand "movsi" | |
7442 | [(set (match_operand:SI 0 "general_operand" "") | |
7443 | (match_operand:SI 1 "any_operand" ""))] | |
7444 | "" | |
fb4d4348 | 7445 | "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") |
1fd4e8c1 | 7446 | |
ee890fe2 SS |
7447 | (define_insn "movsi_low" |
7448 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
f585a356 | 7449 | (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
ee890fe2 SS |
7450 | (match_operand 2 "" ""))))] |
7451 | "TARGET_MACHO && ! TARGET_64BIT" | |
7452 | "{l|lwz} %0,lo16(%2)(%1)" | |
7453 | [(set_attr "type" "load") | |
7454 | (set_attr "length" "4")]) | |
7455 | ||
acad7ed3 | 7456 | (define_insn "*movsi_internal1" |
165a5bad | 7457 | [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") |
a004eb82 | 7458 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] |
19d5775a RK |
7459 | "gpc_reg_operand (operands[0], SImode) |
7460 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7461 | "@ |
deb9225a | 7462 | mr %0,%1 |
b9442c72 | 7463 | {cal|la} %0,%a1 |
ca7f5001 RK |
7464 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7465 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7466 | {lil|li} %0,%1 |
802a0058 | 7467 | {liu|lis} %0,%v1 |
beaec479 | 7468 | # |
aee86b38 | 7469 | {cal|la} %0,%a1 |
1fd4e8c1 | 7470 | mf%1 %0 |
5c23c401 | 7471 | mt%0 %1 |
e76e75bb | 7472 | mt%0 %1 |
a004eb82 | 7473 | mt%0 %1 |
e34eaae5 | 7474 | {cror 0,0,0|nop}" |
02ca7595 | 7475 | [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*") |
a004eb82 | 7476 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7477 | |
77fa0940 RK |
7478 | ;; Split a load of a large constant into the appropriate two-insn |
7479 | ;; sequence. | |
7480 | ||
7481 | (define_split | |
7482 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7483 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7484 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7485 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7486 | [(set (match_dup 0) | |
7487 | (match_dup 2)) | |
7488 | (set (match_dup 0) | |
7489 | (ior:SI (match_dup 0) | |
7490 | (match_dup 3)))] | |
7491 | " | |
af8cb5c5 DE |
7492 | { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2); |
7493 | ||
7494 | if (tem == operands[0]) | |
7495 | DONE; | |
7496 | else | |
7497 | FAIL; | |
77fa0940 RK |
7498 | }") |
7499 | ||
acad7ed3 | 7500 | (define_insn "*movsi_internal2" |
bb84cb12 DE |
7501 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
7502 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r") | |
1fd4e8c1 | 7503 | (const_int 0))) |
bb84cb12 | 7504 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
4b8a63d6 | 7505 | "TARGET_32BIT" |
9ebbca7d | 7506 | "@ |
bb84cb12 | 7507 | {cmpi|cmpwi} %2,%0,0 |
9ebbca7d GK |
7508 | mr. %0,%1 |
7509 | #" | |
bb84cb12 DE |
7510 | [(set_attr "type" "cmp,compare,cmp") |
7511 | (set_attr "length" "4,4,8")]) | |
7512 | ||
9ebbca7d GK |
7513 | (define_split |
7514 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
7515 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
7516 | (const_int 0))) | |
7517 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
4b8a63d6 | 7518 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
7519 | [(set (match_dup 0) (match_dup 1)) |
7520 | (set (match_dup 2) | |
7521 | (compare:CC (match_dup 0) | |
7522 | (const_int 0)))] | |
7523 | "") | |
bb84cb12 | 7524 | \f |
1fd4e8c1 RK |
7525 | (define_expand "movhi" |
7526 | [(set (match_operand:HI 0 "general_operand" "") | |
7527 | (match_operand:HI 1 "any_operand" ""))] | |
7528 | "" | |
fb4d4348 | 7529 | "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") |
1fd4e8c1 | 7530 | |
e34eaae5 | 7531 | (define_insn "*movhi_internal" |
fb81d7ce RK |
7532 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7533 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7534 | "gpc_reg_operand (operands[0], HImode) |
7535 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7536 | "@ |
deb9225a | 7537 | mr %0,%1 |
1fd4e8c1 RK |
7538 | lhz%U1%X1 %0,%1 |
7539 | sth%U0%X0 %1,%0 | |
19d5775a | 7540 | {lil|li} %0,%w1 |
1fd4e8c1 | 7541 | mf%1 %0 |
e76e75bb | 7542 | mt%0 %1 |
fb81d7ce | 7543 | mt%0 %1 |
e34eaae5 | 7544 | {cror 0,0,0|nop}" |
02ca7595 | 7545 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7546 | |
7547 | (define_expand "movqi" | |
7548 | [(set (match_operand:QI 0 "general_operand" "") | |
7549 | (match_operand:QI 1 "any_operand" ""))] | |
7550 | "" | |
fb4d4348 | 7551 | "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") |
1fd4e8c1 | 7552 | |
e34eaae5 | 7553 | (define_insn "*movqi_internal" |
fb81d7ce RK |
7554 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7555 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7556 | "gpc_reg_operand (operands[0], QImode) |
7557 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7558 | "@ |
deb9225a | 7559 | mr %0,%1 |
1fd4e8c1 RK |
7560 | lbz%U1%X1 %0,%1 |
7561 | stb%U0%X0 %1,%0 | |
19d5775a | 7562 | {lil|li} %0,%1 |
1fd4e8c1 | 7563 | mf%1 %0 |
e76e75bb | 7564 | mt%0 %1 |
fb81d7ce | 7565 | mt%0 %1 |
e34eaae5 | 7566 | {cror 0,0,0|nop}" |
02ca7595 | 7567 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7568 | \f |
7569 | ;; Here is how to move condition codes around. When we store CC data in | |
7570 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7571 | ;; This lets us not shift in the most common case of CR0. | |
7572 | (define_expand "movcc" | |
7573 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7574 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7575 | "" | |
7576 | "") | |
7577 | ||
a65c591c | 7578 | (define_insn "*movcc_internal1" |
b54cf83a DE |
7579 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m") |
7580 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))] | |
1fd4e8c1 RK |
7581 | "register_operand (operands[0], CCmode) |
7582 | || register_operand (operands[1], CCmode)" | |
7583 | "@ | |
7584 | mcrf %0,%1 | |
7585 | mtcrf 128,%1 | |
ca7f5001 | 7586 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
2c4a9cff DE |
7587 | mfcr %0%Q1 |
7588 | mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 | |
deb9225a | 7589 | mr %0,%1 |
b54cf83a | 7590 | mf%1 %0 |
b991a865 GK |
7591 | mt%0 %1 |
7592 | mt%0 %1 | |
ca7f5001 RK |
7593 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7594 | {st%U0%U1|stw%U0%U1} %1,%0" | |
2c4a9cff DE |
7595 | [(set (attr "type") |
7596 | (cond [(eq_attr "alternative" "0") | |
7597 | (const_string "cr_logical") | |
7598 | (eq_attr "alternative" "1,2") | |
7599 | (const_string "mtcr") | |
7600 | (eq_attr "alternative" "5,7") | |
7601 | (const_string "integer") | |
7602 | (eq_attr "alternative" "6") | |
7603 | (const_string "mfjmpr") | |
7604 | (eq_attr "alternative" "8") | |
7605 | (const_string "mtjmpr") | |
7606 | (eq_attr "alternative" "9") | |
7607 | (const_string "load") | |
7608 | (eq_attr "alternative" "10") | |
7609 | (const_string "store") | |
7610 | (ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
7611 | (const_string "mfcrf") | |
7612 | ] | |
7613 | (const_string "mfcr"))) | |
b991a865 | 7614 | (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7615 | \f |
e52e05ca MM |
7616 | ;; For floating-point, we normally deal with the floating-point registers |
7617 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7618 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7619 | ;; value is a simple constant or already in memory, we deal with this by | |
7620 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7621 | (define_expand "movsf" |
7622 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7623 | (match_operand:SF 1 "any_operand" ""))] | |
7624 | "" | |
fb4d4348 | 7625 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 7626 | |
1fd4e8c1 | 7627 | (define_split |
cd2b37d9 | 7628 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7629 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7630 | "reload_completed |
5ae4759c MM |
7631 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7632 | || (GET_CODE (operands[0]) == SUBREG | |
7633 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7634 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7635 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7636 | " |
7637 | { | |
7638 | long l; | |
7639 | REAL_VALUE_TYPE rv; | |
7640 | ||
7641 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7642 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7643 | |
f99f88e0 DE |
7644 | if (! TARGET_POWERPC64) |
7645 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7646 | else | |
7647 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7648 | |
2496c7bd | 7649 | operands[3] = gen_int_mode (l, SImode); |
a260abc9 DE |
7650 | }") |
7651 | ||
c4c40373 | 7652 | (define_insn "*movsf_hardfloat" |
ae6669e7 DJ |
7653 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r") |
7654 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))] | |
d14a6d05 | 7655 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7656 | || gpc_reg_operand (operands[1], SFmode)) |
7657 | && (TARGET_HARD_FLOAT && TARGET_FPRS)" | |
1fd4e8c1 | 7658 | "@ |
f99f88e0 DE |
7659 | mr %0,%1 |
7660 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7661 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7662 | fmr %0,%1 |
7663 | lfs%U1%X1 %0,%1 | |
c4c40373 | 7664 | stfs%U0%X0 %1,%0 |
b991a865 GK |
7665 | mt%0 %1 |
7666 | mt%0 %1 | |
7667 | mf%1 %0 | |
e0740893 | 7668 | {cror 0,0,0|nop} |
c4c40373 MM |
7669 | # |
7670 | #" | |
ae6669e7 DJ |
7671 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*") |
7672 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7673 | |
c4c40373 | 7674 | (define_insn "*movsf_softfloat" |
dd0fbae2 MK |
7675 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h") |
7676 | (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))] | |
d14a6d05 | 7677 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7678 | || gpc_reg_operand (operands[1], SFmode)) |
7679 | && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" | |
d14a6d05 MM |
7680 | "@ |
7681 | mr %0,%1 | |
b991a865 GK |
7682 | mt%0 %1 |
7683 | mt%0 %1 | |
7684 | mf%1 %0 | |
d14a6d05 MM |
7685 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7686 | {st%U0%X0|stw%U0%X0} %1,%0 | |
7687 | {lil|li} %0,%1 | |
802a0058 | 7688 | {liu|lis} %0,%v1 |
aee86b38 | 7689 | {cal|la} %0,%a1 |
c4c40373 | 7690 | # |
dd0fbae2 MK |
7691 | # |
7692 | {cror 0,0,0|nop}" | |
7693 | [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*") | |
7694 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")]) | |
d14a6d05 | 7695 | |
1fd4e8c1 RK |
7696 | \f |
7697 | (define_expand "movdf" | |
7698 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
7699 | (match_operand:DF 1 "any_operand" ""))] | |
7700 | "" | |
fb4d4348 | 7701 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
7702 | |
7703 | (define_split | |
cd2b37d9 | 7704 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 7705 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 7706 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7707 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7708 | || (GET_CODE (operands[0]) == SUBREG | |
7709 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7710 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7711 | [(set (match_dup 2) (match_dup 4)) |
7712 | (set (match_dup 3) (match_dup 1))] | |
7713 | " | |
7714 | { | |
5ae4759c | 7715 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
7716 | HOST_WIDE_INT value = INTVAL (operands[1]); |
7717 | ||
5ae4759c MM |
7718 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7719 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
7720 | #if HOST_BITS_PER_WIDE_INT == 32 |
7721 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
7722 | #else | |
7723 | operands[4] = GEN_INT (value >> 32); | |
a65c591c | 7724 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
5f59ecb7 | 7725 | #endif |
c4c40373 MM |
7726 | }") |
7727 | ||
c4c40373 MM |
7728 | (define_split |
7729 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
7730 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 7731 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7732 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7733 | || (GET_CODE (operands[0]) == SUBREG | |
7734 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7735 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7736 | [(set (match_dup 2) (match_dup 4)) |
7737 | (set (match_dup 3) (match_dup 5))] | |
7738 | " | |
7739 | { | |
5ae4759c | 7740 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
7741 | long l[2]; |
7742 | REAL_VALUE_TYPE rv; | |
7743 | ||
7744 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7745 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7746 | ||
5ae4759c MM |
7747 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7748 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
2496c7bd LB |
7749 | operands[4] = gen_int_mode (l[endian], SImode); |
7750 | operands[5] = gen_int_mode (l[1 - endian], SImode); | |
c4c40373 MM |
7751 | }") |
7752 | ||
efc08378 DE |
7753 | (define_split |
7754 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 7755 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 7756 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7757 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7758 | || (GET_CODE (operands[0]) == SUBREG | |
7759 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7760 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 7761 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 7762 | " |
a260abc9 DE |
7763 | { |
7764 | int endian = (WORDS_BIG_ENDIAN == 0); | |
7765 | long l[2]; | |
7766 | REAL_VALUE_TYPE rv; | |
4977bab6 | 7767 | #if HOST_BITS_PER_WIDE_INT >= 64 |
5b029315 | 7768 | HOST_WIDE_INT val; |
4977bab6 | 7769 | #endif |
a260abc9 DE |
7770 | |
7771 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7772 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7773 | ||
7774 | operands[2] = gen_lowpart (DImode, operands[0]); | |
7775 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
5b029315 | 7776 | #if HOST_BITS_PER_WIDE_INT >= 64 |
a2419b96 DE |
7777 | val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 |
7778 | | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); | |
5b029315 | 7779 | |
f5264b52 | 7780 | operands[3] = gen_int_mode (val, DImode); |
5b029315 | 7781 | #else |
a260abc9 | 7782 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); |
5b029315 | 7783 | #endif |
a260abc9 | 7784 | }") |
efc08378 | 7785 | |
4eae5fe1 | 7786 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 7787 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
7788 | ;; a non-offsettable memref, but also it is less efficient than loading |
7789 | ;; the constant into an FP register, since it will probably be used there. | |
7790 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
7791 | ;; of handling these non-offsettable values. | |
c4c40373 | 7792 | (define_insn "*movdf_hardfloat32" |
914a7297 DE |
7793 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") |
7794 | (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] | |
a3170dc6 | 7795 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
7796 | && (gpc_reg_operand (operands[0], DFmode) |
7797 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
7798 | "* |
7799 | { | |
7800 | switch (which_alternative) | |
7801 | { | |
a260abc9 | 7802 | default: |
37409796 | 7803 | gcc_unreachable (); |
e7113111 RK |
7804 | case 0: |
7805 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
7806 | the first register operand 0 is the same as the second register |
7807 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 7808 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 7809 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 7810 | else |
deb9225a | 7811 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 7812 | case 1: |
819e019c EC |
7813 | if (GET_CODE (operands[1]) == MEM |
7814 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0), | |
7815 | reload_completed || reload_in_progress) | |
7816 | || GET_CODE (XEXP (operands[1], 0)) == REG | |
7817 | || GET_CODE (XEXP (operands[1], 0)) == LO_SUM | |
69f51a21 | 7818 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC |
819e019c | 7819 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)) |
000034eb DE |
7820 | { |
7821 | /* If the low-address word is used in the address, we must load | |
7822 | it last. Otherwise, load it first. Note that we cannot have | |
7823 | auto-increment in that case since the address register is | |
7824 | known to be dead. */ | |
7825 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
7826 | operands[1], 0)) | |
7827 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
7828 | else | |
7829 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7830 | } | |
e7113111 | 7831 | else |
000034eb DE |
7832 | { |
7833 | rtx addreg; | |
7834 | ||
000034eb DE |
7835 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
7836 | if (refers_to_regno_p (REGNO (operands[0]), | |
7837 | REGNO (operands[0]) + 1, | |
7838 | operands[1], 0)) | |
7839 | { | |
7840 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 7841 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 7842 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 7843 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
7844 | } |
7845 | else | |
7846 | { | |
2b97222d | 7847 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 7848 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 7849 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
7850 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
7851 | return \"\"; | |
7852 | } | |
7853 | } | |
e7113111 | 7854 | case 2: |
819e019c EC |
7855 | if (GET_CODE (operands[0]) == MEM |
7856 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0), | |
7857 | reload_completed || reload_in_progress) | |
7858 | || GET_CODE (XEXP (operands[0], 0)) == REG | |
7859 | || GET_CODE (XEXP (operands[0], 0)) == LO_SUM | |
69f51a21 | 7860 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC |
819e019c | 7861 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)) |
000034eb DE |
7862 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
7863 | else | |
7864 | { | |
7865 | rtx addreg; | |
7866 | ||
000034eb | 7867 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 7868 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 7869 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 7870 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
7871 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
7872 | return \"\"; | |
7873 | } | |
e7113111 | 7874 | case 3: |
914a7297 | 7875 | return \"fmr %0,%1\"; |
e7113111 | 7876 | case 4: |
914a7297 | 7877 | return \"lfd%U1%X1 %0,%1\"; |
e7113111 | 7878 | case 5: |
914a7297 | 7879 | return \"stfd%U0%X0 %1,%0\"; |
e7113111 | 7880 | case 6: |
c4c40373 | 7881 | case 7: |
c4c40373 | 7882 | case 8: |
914a7297 | 7883 | return \"#\"; |
e7113111 RK |
7884 | } |
7885 | }" | |
943c15ed | 7886 | [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*") |
914a7297 | 7887 | (set_attr "length" "8,16,16,4,4,4,8,12,16")]) |
51b8fc2c | 7888 | |
c4c40373 | 7889 | (define_insn "*movdf_softfloat32" |
1427100a DE |
7890 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
7891 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
7a2f7870 | 7892 | "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) |
52d3af72 DE |
7893 | && (gpc_reg_operand (operands[0], DFmode) |
7894 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
7895 | "* |
7896 | { | |
7897 | switch (which_alternative) | |
7898 | { | |
a260abc9 | 7899 | default: |
37409796 | 7900 | gcc_unreachable (); |
dc4f83ca MM |
7901 | case 0: |
7902 | /* We normally copy the low-numbered register first. However, if | |
7903 | the first register operand 0 is the same as the second register of | |
7904 | operand 1, we must copy in the opposite order. */ | |
7905 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
7906 | return \"mr %L0,%L1\;mr %0,%1\"; | |
7907 | else | |
7908 | return \"mr %0,%1\;mr %L0,%L1\"; | |
7909 | case 1: | |
3cb999d8 DE |
7910 | /* If the low-address word is used in the address, we must load |
7911 | it last. Otherwise, load it first. Note that we cannot have | |
7912 | auto-increment in that case since the address register is | |
7913 | known to be dead. */ | |
dc4f83ca | 7914 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 7915 | operands[1], 0)) |
dc4f83ca MM |
7916 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
7917 | else | |
7918 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7919 | case 2: | |
7920 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
7921 | case 3: | |
c4c40373 MM |
7922 | case 4: |
7923 | case 5: | |
dc4f83ca MM |
7924 | return \"#\"; |
7925 | } | |
7926 | }" | |
943c15ed | 7927 | [(set_attr "type" "two,load,store,*,*,*") |
c4c40373 | 7928 | (set_attr "length" "8,8,8,8,12,16")]) |
dc4f83ca | 7929 | |
d2288d5d HP |
7930 | ; ld/std require word-aligned displacements -> 'Y' constraint. |
7931 | ; List Y->r and r->Y before r->r for reload. | |
c4c40373 | 7932 | (define_insn "*movdf_hardfloat64" |
ae6669e7 DJ |
7933 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r") |
7934 | (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] | |
a3170dc6 | 7935 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
7936 | && (gpc_reg_operand (operands[0], DFmode) |
7937 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 7938 | "@ |
96bb8ed3 | 7939 | std%U0%X0 %1,%0 |
3364872d FJ |
7940 | ld%U1%X1 %0,%1 |
7941 | mr %0,%1 | |
3d5570cb | 7942 | fmr %0,%1 |
f63184ac | 7943 | lfd%U1%X1 %0,%1 |
914a7297 DE |
7944 | stfd%U0%X0 %1,%0 |
7945 | mt%0 %1 | |
7946 | mf%1 %0 | |
e0740893 | 7947 | {cror 0,0,0|nop} |
914a7297 DE |
7948 | # |
7949 | # | |
7950 | #" | |
ae6669e7 DJ |
7951 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*") |
7952 | (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")]) | |
dc4f83ca | 7953 | |
c4c40373 | 7954 | (define_insn "*movdf_softfloat64" |
d2288d5d HP |
7955 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h") |
7956 | (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))] | |
a3170dc6 | 7957 | "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
7958 | && (gpc_reg_operand (operands[0], DFmode) |
7959 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca | 7960 | "@ |
d2288d5d HP |
7961 | ld%U1%X1 %0,%1 |
7962 | std%U0%X0 %1,%0 | |
dc4f83ca | 7963 | mr %0,%1 |
914a7297 DE |
7964 | mt%0 %1 |
7965 | mf%1 %0 | |
c4c40373 MM |
7966 | # |
7967 | # | |
e2d0915c | 7968 | # |
e0740893 | 7969 | {cror 0,0,0|nop}" |
d2288d5d | 7970 | [(set_attr "type" "load,store,*,*,*,*,*,*,*") |
e2d0915c | 7971 | (set_attr "length" "4,4,4,4,4,8,12,16,4")]) |
1fd4e8c1 | 7972 | \f |
06f4e019 DE |
7973 | (define_expand "movtf" |
7974 | [(set (match_operand:TF 0 "general_operand" "") | |
7975 | (match_operand:TF 1 "any_operand" ""))] | |
39e63627 GK |
7976 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7977 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
7978 | "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") |
7979 | ||
a9baceb1 GK |
7980 | ; It's important to list the o->f and f->o moves before f->f because |
7981 | ; otherwise reload, given m->f, will try to pick f->f and reload it, | |
409f61cd | 7982 | ; which doesn't make progress. Likewise r->Y must be before r->r. |
a9baceb1 | 7983 | (define_insn_and_split "*movtf_internal" |
409f61cd AM |
7984 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r") |
7985 | (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))] | |
39e63627 GK |
7986 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7987 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
06f4e019 DE |
7988 | && (gpc_reg_operand (operands[0], TFmode) |
7989 | || gpc_reg_operand (operands[1], TFmode))" | |
a9baceb1 | 7990 | "#" |
ecb62ae7 | 7991 | "&& reload_completed" |
a9baceb1 GK |
7992 | [(pc)] |
7993 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } | |
112ccb83 | 7994 | [(set_attr "length" "8,8,8,20,20,16")]) |
06f4e019 | 7995 | |
ecb62ae7 GK |
7996 | (define_expand "extenddftf2" |
7997 | [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
7998 | (float_extend:TF (match_operand:DF 1 "input_operand" ""))) | |
7999 | (use (match_dup 2))])] | |
39e63627 GK |
8000 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8001 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8002 | { |
ecb62ae7 GK |
8003 | operands[2] = CONST0_RTX (DFmode); |
8004 | }) | |
06f4e019 | 8005 | |
ecb62ae7 GK |
8006 | (define_insn_and_split "*extenddftf2_internal" |
8007 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r") | |
8008 | (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF"))) | |
97c54d9a | 8009 | (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))] |
39e63627 GK |
8010 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8011 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 GK |
8012 | "#" |
8013 | "&& reload_completed" | |
8014 | [(pc)] | |
06f4e019 | 8015 | { |
ecb62ae7 GK |
8016 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; |
8017 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); | |
8018 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word), | |
8019 | operands[1]); | |
8020 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word), | |
8021 | operands[2]); | |
8022 | DONE; | |
6ae08853 | 8023 | }) |
ecb62ae7 GK |
8024 | |
8025 | (define_expand "extendsftf2" | |
8026 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
8027 | (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
8028 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8029 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
8030 | { | |
8031 | rtx tmp = gen_reg_rtx (DFmode); | |
8032 | emit_insn (gen_extendsfdf2 (tmp, operands[1])); | |
8033 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
8034 | DONE; | |
8035 | }) | |
06f4e019 | 8036 | |
8cb320b8 | 8037 | (define_expand "trunctfdf2" |
589b3fda DE |
8038 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
8039 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))] | |
39e63627 GK |
8040 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8041 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
589b3fda | 8042 | "") |
8cb320b8 DE |
8043 | |
8044 | (define_insn_and_split "trunctfdf2_internal1" | |
8045 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f") | |
8046 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))] | |
8047 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT | |
8048 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
8049 | "@ | |
8050 | # | |
8051 | fmr %0,%1" | |
8052 | "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" | |
8053 | [(const_int 0)] | |
8054 | { | |
8055 | emit_note (NOTE_INSN_DELETED); | |
8056 | DONE; | |
8057 | } | |
8058 | [(set_attr "type" "fp")]) | |
8059 | ||
8060 | (define_insn "trunctfdf2_internal2" | |
8061 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8062 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
8063 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT | |
8064 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8065 | "fadd %0,%1,%L1" |
8cb320b8 | 8066 | [(set_attr "type" "fp")]) |
06f4e019 DE |
8067 | |
8068 | (define_insn_and_split "trunctfsf2" | |
8069 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
ea112fc4 DE |
8070 | (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8071 | (clobber (match_scratch:DF 2 "=f"))] | |
39e63627 GK |
8072 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8073 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8074 | "#" |
ea112fc4 | 8075 | "&& reload_completed" |
06f4e019 DE |
8076 | [(set (match_dup 2) |
8077 | (float_truncate:DF (match_dup 1))) | |
8078 | (set (match_dup 0) | |
8079 | (float_truncate:SF (match_dup 2)))] | |
ea112fc4 | 8080 | "") |
06f4e019 | 8081 | |
0c90aa3c | 8082 | (define_expand "floatsitf2" |
ea112fc4 | 8083 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
0c90aa3c | 8084 | (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))] |
39e63627 GK |
8085 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8086 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
0c90aa3c GK |
8087 | { |
8088 | rtx tmp = gen_reg_rtx (DFmode); | |
8089 | expand_float (tmp, operands[1], false); | |
8090 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
8091 | DONE; | |
8092 | }) | |
06f4e019 | 8093 | |
ecb62ae7 GK |
8094 | ; fadd, but rounding towards zero. |
8095 | ; This is probably not the optimal code sequence. | |
8096 | (define_insn "fix_trunc_helper" | |
8097 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8098 | (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")] | |
8099 | UNSPEC_FIX_TRUNC_TF)) | |
8100 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))] | |
8101 | "TARGET_HARD_FLOAT && TARGET_FPRS" | |
8102 | "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" | |
8103 | [(set_attr "type" "fp") | |
8104 | (set_attr "length" "20")]) | |
8105 | ||
0c90aa3c | 8106 | (define_expand "fix_trunctfsi2" |
ecb62ae7 GK |
8107 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
8108 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" ""))) | |
8109 | (clobber (match_dup 2)) | |
8110 | (clobber (match_dup 3)) | |
8111 | (clobber (match_dup 4)) | |
8112 | (clobber (match_dup 5))])] | |
8113 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8114 | && (TARGET_POWER2 || TARGET_POWERPC) | |
8115 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
8116 | { | |
8117 | operands[2] = gen_reg_rtx (DFmode); | |
8118 | operands[3] = gen_reg_rtx (DFmode); | |
8119 | operands[4] = gen_reg_rtx (DImode); | |
8120 | operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
8121 | }) | |
8122 | ||
8123 | (define_insn_and_split "*fix_trunctfsi2_internal" | |
61c07d3c | 8124 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ecb62ae7 GK |
8125 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8126 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=f")) | |
8127 | (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f")) | |
8128 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f")) | |
8129 | (clobber (match_operand:DI 5 "memory_operand" "=o"))] | |
39e63627 GK |
8130 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8131 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 | 8132 | "#" |
230215f5 | 8133 | "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))" |
ecb62ae7 | 8134 | [(pc)] |
0c90aa3c | 8135 | { |
ecb62ae7 GK |
8136 | rtx lowword; |
8137 | emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3])); | |
8138 | ||
230215f5 GK |
8139 | gcc_assert (MEM_P (operands[5])); |
8140 | lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0); | |
ecb62ae7 GK |
8141 | |
8142 | emit_insn (gen_fctiwz (operands[4], operands[2])); | |
8143 | emit_move_insn (operands[5], operands[4]); | |
230215f5 | 8144 | emit_move_insn (operands[0], lowword); |
0c90aa3c GK |
8145 | DONE; |
8146 | }) | |
06f4e019 DE |
8147 | |
8148 | (define_insn "negtf2" | |
8149 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8150 | (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8151 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8152 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8153 | "* |
8154 | { | |
8155 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8156 | return \"fneg %L0,%L1\;fneg %0,%1\"; | |
8157 | else | |
8158 | return \"fneg %0,%1\;fneg %L0,%L1\"; | |
8159 | }" | |
8160 | [(set_attr "type" "fp") | |
8161 | (set_attr "length" "8")]) | |
8162 | ||
1a402dc1 | 8163 | (define_expand "abstf2" |
06f4e019 DE |
8164 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
8165 | (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8166 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8167 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 8168 | " |
06f4e019 | 8169 | { |
1a402dc1 AM |
8170 | rtx label = gen_label_rtx (); |
8171 | emit_insn (gen_abstf2_internal (operands[0], operands[1], label)); | |
8172 | emit_label (label); | |
8173 | DONE; | |
8174 | }") | |
06f4e019 | 8175 | |
1a402dc1 | 8176 | (define_expand "abstf2_internal" |
06f4e019 | 8177 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
1a402dc1 AM |
8178 | (match_operand:TF 1 "gpc_reg_operand" "f")) |
8179 | (set (match_dup 3) (match_dup 5)) | |
8180 | (set (match_dup 5) (abs:DF (match_dup 5))) | |
8181 | (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5))) | |
8182 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
8183 | (label_ref (match_operand 2 "" "")) | |
8184 | (pc))) | |
8185 | (set (match_dup 6) (neg:DF (match_dup 6)))] | |
39e63627 GK |
8186 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8187 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 8188 | " |
06f4e019 | 8189 | { |
1a402dc1 AM |
8190 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); |
8191 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; | |
8192 | operands[3] = gen_reg_rtx (DFmode); | |
8193 | operands[4] = gen_reg_rtx (CCFPmode); | |
8194 | operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); | |
8195 | operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); | |
8196 | }") | |
06f4e019 | 8197 | \f |
1fd4e8c1 RK |
8198 | ;; Next come the multi-word integer load and store and the load and store |
8199 | ;; multiple insns. | |
8200 | (define_expand "movdi" | |
8201 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 8202 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 | 8203 | "" |
fb4d4348 | 8204 | "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") |
1fd4e8c1 | 8205 | |
112ccb83 GK |
8206 | ; List r->r after r->"o<>", otherwise reload will try to reload a |
8207 | ; non-offsettable address by using r->r which won't make progress. | |
acad7ed3 | 8208 | (define_insn "*movdi_internal32" |
343f6bbf | 8209 | [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r") |
112ccb83 | 8210 | (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))] |
a260abc9 | 8211 | "! TARGET_POWERPC64 |
4e74d8ec MM |
8212 | && (gpc_reg_operand (operands[0], DImode) |
8213 | || gpc_reg_operand (operands[1], DImode))" | |
112ccb83 GK |
8214 | "@ |
8215 | # | |
8216 | # | |
8217 | # | |
8218 | fmr %0,%1 | |
8219 | lfd%U1%X1 %0,%1 | |
8220 | stfd%U0%X0 %1,%0 | |
8221 | #" | |
8222 | [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")]) | |
4e74d8ec MM |
8223 | |
8224 | (define_split | |
8225 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8226 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 8227 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8228 | [(set (match_dup 2) (match_dup 4)) |
8229 | (set (match_dup 3) (match_dup 1))] | |
8230 | " | |
8231 | { | |
5f59ecb7 | 8232 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
8233 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8234 | DImode); | |
8235 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8236 | DImode); | |
75d39459 | 8237 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 8238 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 8239 | #else |
5f59ecb7 | 8240 | operands[4] = GEN_INT (value >> 32); |
a65c591c | 8241 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
75d39459 | 8242 | #endif |
4e74d8ec MM |
8243 | }") |
8244 | ||
3a1f863f DE |
8245 | (define_split |
8246 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
8247 | (match_operand:DI 1 "input_operand" ""))] | |
6ae08853 | 8248 | "reload_completed && !TARGET_POWERPC64 |
3a1f863f | 8249 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
8250 | [(pc)] |
8251 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
3a1f863f | 8252 | |
acad7ed3 | 8253 | (define_insn "*movdi_internal64" |
343f6bbf | 8254 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h") |
9615f239 | 8255 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 8256 | "TARGET_POWERPC64 |
4e74d8ec MM |
8257 | && (gpc_reg_operand (operands[0], DImode) |
8258 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 8259 | "@ |
3d5570cb RK |
8260 | mr %0,%1 |
8261 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8262 | std%U0%X0 %1,%0 |
3d5570cb | 8263 | li %0,%1 |
802a0058 | 8264 | lis %0,%v1 |
e6ca2c17 | 8265 | # |
aee86b38 | 8266 | {cal|la} %0,%a1 |
3d5570cb RK |
8267 | fmr %0,%1 |
8268 | lfd%U1%X1 %0,%1 | |
8269 | stfd%U0%X0 %1,%0 | |
8270 | mf%1 %0 | |
08075ead | 8271 | mt%0 %1 |
e34eaae5 | 8272 | {cror 0,0,0|nop}" |
02ca7595 | 8273 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*") |
e6ca2c17 DE |
8274 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
8275 | ||
5f59ecb7 | 8276 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
8277 | (define_insn "" |
8278 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8279 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
8280 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8281 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
8282 | && num_insns_constant (operands[1], DImode) == 1" |
8283 | "* | |
8284 | { | |
8285 | return ((unsigned HOST_WIDE_INT) | |
8286 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
8287 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
8288 | }") | |
8289 | ||
a260abc9 DE |
8290 | ;; Generate all one-bits and clear left or right. |
8291 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8292 | (define_split | |
8293 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8294 | (match_operand:DI 1 "mask64_operand" ""))] | |
8295 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8296 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8297 | (set (match_dup 0) |
a260abc9 DE |
8298 | (and:DI (rotate:DI (match_dup 0) |
8299 | (const_int 0)) | |
8300 | (match_dup 1)))] | |
8301 | "") | |
8302 | ||
8303 | ;; Split a load of a large constant into the appropriate five-instruction | |
8304 | ;; sequence. Handle anything in a constant number of insns. | |
8305 | ;; When non-easy constants can go in the TOC, this should use | |
8306 | ;; easy_fp_constant predicate. | |
8307 | (define_split | |
8308 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8309 | (match_operand:DI 1 "const_int_operand" ""))] |
8310 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8311 | [(set (match_dup 0) (match_dup 2)) | |
8312 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
e6ca2c17 | 8313 | " |
2bfcf297 DB |
8314 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8315 | ||
8316 | if (tem == operands[0]) | |
8317 | DONE; | |
e8d791dd | 8318 | else |
2bfcf297 | 8319 | FAIL; |
5f59ecb7 | 8320 | }") |
e6ca2c17 | 8321 | |
5f59ecb7 DE |
8322 | (define_split |
8323 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8324 | (match_operand:DI 1 "const_double_operand" ""))] |
8325 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8326 | [(set (match_dup 0) (match_dup 2)) | |
8327 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
5f59ecb7 | 8328 | " |
2bfcf297 DB |
8329 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8330 | ||
8331 | if (tem == operands[0]) | |
8332 | DONE; | |
8333 | else | |
8334 | FAIL; | |
e6ca2c17 | 8335 | }") |
08075ead | 8336 | |
acad7ed3 | 8337 | (define_insn "*movdi_internal2" |
bb84cb12 DE |
8338 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
8339 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r") | |
08075ead | 8340 | (const_int 0))) |
bb84cb12 | 8341 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
683bdff7 | 8342 | "TARGET_64BIT" |
9ebbca7d | 8343 | "@ |
bb84cb12 | 8344 | cmpdi %2,%0,0 |
9ebbca7d GK |
8345 | mr. %0,%1 |
8346 | #" | |
bb84cb12 DE |
8347 | [(set_attr "type" "cmp,compare,cmp") |
8348 | (set_attr "length" "4,4,8")]) | |
acad7ed3 | 8349 | |
9ebbca7d GK |
8350 | (define_split |
8351 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8352 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
8353 | (const_int 0))) | |
8354 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8355 | "TARGET_POWERPC64 && reload_completed" | |
8356 | [(set (match_dup 0) (match_dup 1)) | |
8357 | (set (match_dup 2) | |
8358 | (compare:CC (match_dup 0) | |
8359 | (const_int 0)))] | |
8360 | "") | |
acad7ed3 | 8361 | \f |
1fd4e8c1 RK |
8362 | ;; TImode is similar, except that we usually want to compute the address into |
8363 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8364 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8365 | (define_expand "movti" |
8366 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
8367 | (match_operand:TI 1 "general_operand" "")) | |
8368 | (clobber (scratch:SI))])] | |
3a1f863f | 8369 | "" |
fb4d4348 | 8370 | "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") |
1fd4e8c1 RK |
8371 | |
8372 | ;; We say that MQ is clobbered in the last alternative because the first | |
8373 | ;; alternative would never get used otherwise since it would need a reload | |
8374 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8375 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8376 | ;; giving the SCRATCH mq. | |
3a1f863f | 8377 | |
a260abc9 | 8378 | (define_insn "*movti_power" |
7f514158 AM |
8379 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r") |
8380 | (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n")) | |
8381 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))] | |
6ae08853 | 8382 | "TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8383 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8384 | "* |
8385 | { | |
8386 | switch (which_alternative) | |
8387 | { | |
dc4f83ca | 8388 | default: |
37409796 | 8389 | gcc_unreachable (); |
dc4f83ca | 8390 | |
1fd4e8c1 | 8391 | case 0: |
3a1f863f DE |
8392 | if (TARGET_STRING) |
8393 | return \"{stsi|stswi} %1,%P0,16\"; | |
1fd4e8c1 | 8394 | case 1: |
1fd4e8c1 | 8395 | case 2: |
3a1f863f | 8396 | return \"#\"; |
1fd4e8c1 RK |
8397 | case 3: |
8398 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8399 | fall through to generating four loads. */ | |
e876481c DE |
8400 | if (TARGET_STRING |
8401 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8402 | return \"{lsi|lswi} %0,%P1,16\"; |
82e41834 | 8403 | /* ... fall through ... */ |
1fd4e8c1 | 8404 | case 4: |
7f514158 | 8405 | case 5: |
3a1f863f | 8406 | return \"#\"; |
1fd4e8c1 RK |
8407 | } |
8408 | }" | |
7f514158 | 8409 | [(set_attr "type" "store,store,*,load,load,*")]) |
51b8fc2c | 8410 | |
a260abc9 | 8411 | (define_insn "*movti_string" |
7f514158 AM |
8412 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r") |
8413 | (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))] | |
3a1f863f | 8414 | "! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8415 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8416 | "* | |
8417 | { | |
8418 | switch (which_alternative) | |
8419 | { | |
8420 | default: | |
37409796 | 8421 | gcc_unreachable (); |
dc4f83ca | 8422 | case 0: |
3a1f863f DE |
8423 | if (TARGET_STRING) |
8424 | return \"{stsi|stswi} %1,%P0,16\"; | |
dc4f83ca | 8425 | case 1: |
cd1d3445 | 8426 | case 2: |
3a1f863f | 8427 | return \"#\"; |
cd1d3445 DE |
8428 | case 3: |
8429 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8430 | fall through to generating four loads. */ | |
6ae08853 | 8431 | if (TARGET_STRING |
3a1f863f | 8432 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) |
cd1d3445 DE |
8433 | return \"{lsi|lswi} %0,%P1,16\"; |
8434 | /* ... fall through ... */ | |
8435 | case 4: | |
7f514158 | 8436 | case 5: |
3a1f863f | 8437 | return \"#\"; |
dc4f83ca MM |
8438 | } |
8439 | }" | |
7f514158 | 8440 | [(set_attr "type" "store,store,*,load,load,*")]) |
dc4f83ca | 8441 | |
a260abc9 | 8442 | (define_insn "*movti_ppc64" |
112ccb83 GK |
8443 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r") |
8444 | (match_operand:TI 1 "input_operand" "r,r,m"))] | |
51b8fc2c RK |
8445 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) |
8446 | || gpc_reg_operand (operands[1], TImode))" | |
112ccb83 | 8447 | "#" |
3a1f863f DE |
8448 | [(set_attr "type" "*,load,store")]) |
8449 | ||
7f514158 AM |
8450 | (define_split |
8451 | [(set (match_operand:TI 0 "gpc_reg_operand" "") | |
8452 | (match_operand:TI 1 "const_double_operand" ""))] | |
8453 | "TARGET_POWERPC64" | |
8454 | [(set (match_dup 2) (match_dup 4)) | |
8455 | (set (match_dup 3) (match_dup 5))] | |
8456 | " | |
8457 | { | |
8458 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, | |
8459 | TImode); | |
8460 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8461 | TImode); | |
8462 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
8463 | { | |
8464 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
8465 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
8466 | } | |
8467 | else if (GET_CODE (operands[1]) == CONST_INT) | |
8468 | { | |
8469 | operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0)); | |
8470 | operands[5] = operands[1]; | |
8471 | } | |
8472 | else | |
8473 | FAIL; | |
8474 | }") | |
8475 | ||
3a1f863f DE |
8476 | (define_split |
8477 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
8478 | (match_operand:TI 1 "input_operand" ""))] | |
a9baceb1 | 8479 | "reload_completed |
3a1f863f | 8480 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
8481 | [(pc)] |
8482 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
1fd4e8c1 RK |
8483 | \f |
8484 | (define_expand "load_multiple" | |
2f622005 RK |
8485 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8486 | (match_operand:SI 1 "" "")) | |
8487 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8488 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8489 | " |
8490 | { | |
8491 | int regno; | |
8492 | int count; | |
792760b9 | 8493 | rtx op1; |
1fd4e8c1 RK |
8494 | int i; |
8495 | ||
8496 | /* Support only loading a constant number of fixed-point registers from | |
8497 | memory and only bother with this if more than two; the machine | |
8498 | doesn't support more than eight. */ | |
8499 | if (GET_CODE (operands[2]) != CONST_INT | |
8500 | || INTVAL (operands[2]) <= 2 | |
8501 | || INTVAL (operands[2]) > 8 | |
8502 | || GET_CODE (operands[1]) != MEM | |
8503 | || GET_CODE (operands[0]) != REG | |
8504 | || REGNO (operands[0]) >= 32) | |
8505 | FAIL; | |
8506 | ||
8507 | count = INTVAL (operands[2]); | |
8508 | regno = REGNO (operands[0]); | |
8509 | ||
39403d82 | 8510 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
8511 | op1 = replace_equiv_address (operands[1], |
8512 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
8513 | |
8514 | for (i = 0; i < count; i++) | |
8515 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8516 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
7ef788f0 | 8517 | adjust_address_nv (op1, SImode, i * 4)); |
1fd4e8c1 RK |
8518 | }") |
8519 | ||
9caa3eb2 | 8520 | (define_insn "*ldmsi8" |
1fd4e8c1 | 8521 | [(match_parallel 0 "load_multiple_operation" |
9caa3eb2 DE |
8522 | [(set (match_operand:SI 2 "gpc_reg_operand" "") |
8523 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8524 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8525 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8526 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8527 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8528 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8529 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8530 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8531 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8532 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8533 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8534 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8535 | (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
8536 | (set (match_operand:SI 9 "gpc_reg_operand" "") | |
8537 | (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] | |
8538 | "TARGET_STRING && XVECLEN (operands[0], 0) == 8" | |
1fd4e8c1 | 8539 | "* |
9caa3eb2 DE |
8540 | { return rs6000_output_load_multiple (operands); }" |
8541 | [(set_attr "type" "load") | |
8542 | (set_attr "length" "32")]) | |
1fd4e8c1 | 8543 | |
9caa3eb2 DE |
8544 | (define_insn "*ldmsi7" |
8545 | [(match_parallel 0 "load_multiple_operation" | |
8546 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8547 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8548 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8549 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8550 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8551 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8552 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8553 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8554 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8555 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8556 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8557 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8558 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8559 | (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] | |
8560 | "TARGET_STRING && XVECLEN (operands[0], 0) == 7" | |
8561 | "* | |
8562 | { return rs6000_output_load_multiple (operands); }" | |
8563 | [(set_attr "type" "load") | |
8564 | (set_attr "length" "32")]) | |
8565 | ||
8566 | (define_insn "*ldmsi6" | |
8567 | [(match_parallel 0 "load_multiple_operation" | |
8568 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8569 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8570 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8571 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8572 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8573 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8574 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8575 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8576 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8577 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8578 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8579 | (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] | |
8580 | "TARGET_STRING && XVECLEN (operands[0], 0) == 6" | |
8581 | "* | |
8582 | { return rs6000_output_load_multiple (operands); }" | |
8583 | [(set_attr "type" "load") | |
8584 | (set_attr "length" "32")]) | |
8585 | ||
8586 | (define_insn "*ldmsi5" | |
8587 | [(match_parallel 0 "load_multiple_operation" | |
8588 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8589 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8590 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8591 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8592 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8593 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8594 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8595 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8596 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8597 | (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] | |
8598 | "TARGET_STRING && XVECLEN (operands[0], 0) == 5" | |
8599 | "* | |
8600 | { return rs6000_output_load_multiple (operands); }" | |
8601 | [(set_attr "type" "load") | |
8602 | (set_attr "length" "32")]) | |
8603 | ||
8604 | (define_insn "*ldmsi4" | |
8605 | [(match_parallel 0 "load_multiple_operation" | |
8606 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8607 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8608 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8609 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8610 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8611 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8612 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8613 | (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] | |
8614 | "TARGET_STRING && XVECLEN (operands[0], 0) == 4" | |
8615 | "* | |
8616 | { return rs6000_output_load_multiple (operands); }" | |
8617 | [(set_attr "type" "load") | |
8618 | (set_attr "length" "32")]) | |
8619 | ||
8620 | (define_insn "*ldmsi3" | |
8621 | [(match_parallel 0 "load_multiple_operation" | |
8622 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8623 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8624 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8625 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8626 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8627 | (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] | |
8628 | "TARGET_STRING && XVECLEN (operands[0], 0) == 3" | |
8629 | "* | |
8630 | { return rs6000_output_load_multiple (operands); }" | |
b19003d8 | 8631 | [(set_attr "type" "load") |
e82ee4cc | 8632 | (set_attr "length" "32")]) |
b19003d8 | 8633 | |
1fd4e8c1 | 8634 | (define_expand "store_multiple" |
2f622005 RK |
8635 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8636 | (match_operand:SI 1 "" "")) | |
8637 | (clobber (scratch:SI)) | |
8638 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8639 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8640 | " |
8641 | { | |
8642 | int regno; | |
8643 | int count; | |
8644 | rtx to; | |
792760b9 | 8645 | rtx op0; |
1fd4e8c1 RK |
8646 | int i; |
8647 | ||
8648 | /* Support only storing a constant number of fixed-point registers to | |
8649 | memory and only bother with this if more than two; the machine | |
8650 | doesn't support more than eight. */ | |
8651 | if (GET_CODE (operands[2]) != CONST_INT | |
8652 | || INTVAL (operands[2]) <= 2 | |
8653 | || INTVAL (operands[2]) > 8 | |
8654 | || GET_CODE (operands[0]) != MEM | |
8655 | || GET_CODE (operands[1]) != REG | |
8656 | || REGNO (operands[1]) >= 32) | |
8657 | FAIL; | |
8658 | ||
8659 | count = INTVAL (operands[2]); | |
8660 | regno = REGNO (operands[1]); | |
8661 | ||
39403d82 | 8662 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 8663 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 8664 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
8665 | |
8666 | XVECEXP (operands[3], 0, 0) | |
7ef788f0 | 8667 | = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]); |
39403d82 | 8668 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8669 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8670 | |
8671 | for (i = 1; i < count; i++) | |
8672 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8673 | = gen_rtx_SET (VOIDmode, |
7ef788f0 | 8674 | adjust_address_nv (op0, SImode, i * 4), |
c5c76735 | 8675 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
8676 | }") |
8677 | ||
9caa3eb2 | 8678 | (define_insn "*store_multiple_power" |
1fd4e8c1 RK |
8679 | [(match_parallel 0 "store_multiple_operation" |
8680 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 8681 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 8682 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 8683 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
8684 | "{stsi|stswi} %2,%P1,%O0" |
8685 | [(set_attr "type" "store")]) | |
d14a6d05 | 8686 | |
e46e3130 | 8687 | (define_insn "*stmsi8" |
d14a6d05 | 8688 | [(match_parallel 0 "store_multiple_operation" |
e46e3130 DJ |
8689 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
8690 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8691 | (clobber (match_scratch:SI 3 "X")) | |
8692 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8693 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8694 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8695 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8696 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8697 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8698 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8699 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8700 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8701 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
8702 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
8703 | (match_operand:SI 9 "gpc_reg_operand" "r")) | |
8704 | (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
8705 | (match_operand:SI 10 "gpc_reg_operand" "r"))])] | |
8706 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9" | |
8707 | "{stsi|stswi} %2,%1,%O0" | |
8708 | [(set_attr "type" "store")]) | |
8709 | ||
8710 | (define_insn "*stmsi7" | |
8711 | [(match_parallel 0 "store_multiple_operation" | |
8712 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8713 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8714 | (clobber (match_scratch:SI 3 "X")) | |
8715 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8716 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8717 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8718 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8719 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8720 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8721 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8722 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8723 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8724 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
8725 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
8726 | (match_operand:SI 9 "gpc_reg_operand" "r"))])] | |
8727 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8" | |
8728 | "{stsi|stswi} %2,%1,%O0" | |
8729 | [(set_attr "type" "store")]) | |
8730 | ||
8731 | (define_insn "*stmsi6" | |
8732 | [(match_parallel 0 "store_multiple_operation" | |
8733 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8734 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8735 | (clobber (match_scratch:SI 3 "X")) | |
8736 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8737 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8738 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8739 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8740 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8741 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8742 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8743 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8744 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8745 | (match_operand:SI 8 "gpc_reg_operand" "r"))])] | |
8746 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7" | |
8747 | "{stsi|stswi} %2,%1,%O0" | |
8748 | [(set_attr "type" "store")]) | |
8749 | ||
8750 | (define_insn "*stmsi5" | |
8751 | [(match_parallel 0 "store_multiple_operation" | |
8752 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8753 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8754 | (clobber (match_scratch:SI 3 "X")) | |
8755 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8756 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8757 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8758 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8759 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8760 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8761 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8762 | (match_operand:SI 7 "gpc_reg_operand" "r"))])] | |
8763 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6" | |
8764 | "{stsi|stswi} %2,%1,%O0" | |
8765 | [(set_attr "type" "store")]) | |
8766 | ||
8767 | (define_insn "*stmsi4" | |
8768 | [(match_parallel 0 "store_multiple_operation" | |
8769 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8770 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8771 | (clobber (match_scratch:SI 3 "X")) | |
8772 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8773 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8774 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8775 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8776 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8777 | (match_operand:SI 6 "gpc_reg_operand" "r"))])] | |
8778 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5" | |
b7ff3d82 DE |
8779 | "{stsi|stswi} %2,%1,%O0" |
8780 | [(set_attr "type" "store")]) | |
7e69e155 | 8781 | |
e46e3130 DJ |
8782 | (define_insn "*stmsi3" |
8783 | [(match_parallel 0 "store_multiple_operation" | |
8784 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8785 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8786 | (clobber (match_scratch:SI 3 "X")) | |
8787 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8788 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8789 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8790 | (match_operand:SI 5 "gpc_reg_operand" "r"))])] | |
8791 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4" | |
8792 | "{stsi|stswi} %2,%1,%O0" | |
8793 | [(set_attr "type" "store")]) | |
7e69e155 | 8794 | \f |
fba73eb1 DE |
8795 | (define_expand "clrmemsi" |
8796 | [(parallel [(set (match_operand:BLK 0 "" "") | |
8797 | (const_int 0)) | |
8798 | (use (match_operand:SI 1 "" "")) | |
8799 | (use (match_operand:SI 2 "" ""))])] | |
8800 | "" | |
8801 | " | |
8802 | { | |
8803 | if (expand_block_clear (operands)) | |
8804 | DONE; | |
8805 | else | |
8806 | FAIL; | |
8807 | }") | |
8808 | ||
7e69e155 MM |
8809 | ;; String/block move insn. |
8810 | ;; Argument 0 is the destination | |
8811 | ;; Argument 1 is the source | |
8812 | ;; Argument 2 is the length | |
8813 | ;; Argument 3 is the alignment | |
8814 | ||
70128ad9 | 8815 | (define_expand "movmemsi" |
b6c9286a MM |
8816 | [(parallel [(set (match_operand:BLK 0 "" "") |
8817 | (match_operand:BLK 1 "" "")) | |
8818 | (use (match_operand:SI 2 "" "")) | |
8819 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
8820 | "" |
8821 | " | |
8822 | { | |
8823 | if (expand_block_move (operands)) | |
8824 | DONE; | |
8825 | else | |
8826 | FAIL; | |
8827 | }") | |
8828 | ||
8829 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8830 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
8831 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 8832 | (define_expand "movmemsi_8reg" |
b6c9286a MM |
8833 | [(parallel [(set (match_operand 0 "" "") |
8834 | (match_operand 1 "" "")) | |
8835 | (use (match_operand 2 "" "")) | |
8836 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
8837 | (clobber (reg:SI 5)) |
8838 | (clobber (reg:SI 6)) | |
8839 | (clobber (reg:SI 7)) | |
8840 | (clobber (reg:SI 8)) | |
8841 | (clobber (reg:SI 9)) | |
8842 | (clobber (reg:SI 10)) | |
8843 | (clobber (reg:SI 11)) | |
8844 | (clobber (reg:SI 12)) | |
3c67b673 | 8845 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8846 | "TARGET_STRING" |
8847 | "") | |
8848 | ||
8849 | (define_insn "" | |
52d3af72 DE |
8850 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8851 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8852 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8853 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8854 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8855 | (clobber (reg:SI 6)) |
8856 | (clobber (reg:SI 7)) | |
8857 | (clobber (reg:SI 8)) | |
8858 | (clobber (reg:SI 9)) | |
8859 | (clobber (reg:SI 10)) | |
8860 | (clobber (reg:SI 11)) | |
8861 | (clobber (reg:SI 12)) | |
3c67b673 | 8862 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 8863 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
8864 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8865 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8866 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8867 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8868 | && REGNO (operands[4]) == 5" |
8869 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8870 | [(set_attr "type" "load") |
8871 | (set_attr "length" "8")]) | |
7e69e155 MM |
8872 | |
8873 | (define_insn "" | |
52d3af72 DE |
8874 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8875 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8876 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8877 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8878 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8879 | (clobber (reg:SI 6)) |
8880 | (clobber (reg:SI 7)) | |
8881 | (clobber (reg:SI 8)) | |
8882 | (clobber (reg:SI 9)) | |
8883 | (clobber (reg:SI 10)) | |
8884 | (clobber (reg:SI 11)) | |
8885 | (clobber (reg:SI 12)) | |
3c67b673 | 8886 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8887 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
8888 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8889 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8890 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8891 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8892 | && REGNO (operands[4]) == 5" |
8893 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8894 | [(set_attr "type" "load") |
8895 | (set_attr "length" "8")]) | |
7e69e155 | 8896 | |
09a625f7 TR |
8897 | (define_insn "" |
8898 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
8899 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
8900 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
8901 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8902 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
8903 | (clobber (reg:SI 6)) | |
8904 | (clobber (reg:SI 7)) | |
8905 | (clobber (reg:SI 8)) | |
8906 | (clobber (reg:SI 9)) | |
8907 | (clobber (reg:SI 10)) | |
8908 | (clobber (reg:SI 11)) | |
8909 | (clobber (reg:SI 12)) | |
8910 | (clobber (match_scratch:SI 5 "X"))] | |
8911 | "TARGET_STRING && TARGET_POWERPC64 | |
8912 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) | |
8913 | || INTVAL (operands[2]) == 0) | |
8914 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
8915 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
8916 | && REGNO (operands[4]) == 5" | |
8917 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
8918 | [(set_attr "type" "load") | |
8919 | (set_attr "length" "8")]) | |
8920 | ||
7e69e155 | 8921 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the |
f9562f27 DE |
8922 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
8923 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 8924 | (define_expand "movmemsi_6reg" |
b6c9286a MM |
8925 | [(parallel [(set (match_operand 0 "" "") |
8926 | (match_operand 1 "" "")) | |
8927 | (use (match_operand 2 "" "")) | |
8928 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
8929 | (clobber (reg:SI 5)) |
8930 | (clobber (reg:SI 6)) | |
7e69e155 MM |
8931 | (clobber (reg:SI 7)) |
8932 | (clobber (reg:SI 8)) | |
8933 | (clobber (reg:SI 9)) | |
8934 | (clobber (reg:SI 10)) | |
3c67b673 | 8935 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8936 | "TARGET_STRING" |
8937 | "") | |
8938 | ||
8939 | (define_insn "" | |
52d3af72 DE |
8940 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8941 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8942 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8943 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8944 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8945 | (clobber (reg:SI 6)) |
8946 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8947 | (clobber (reg:SI 8)) |
8948 | (clobber (reg:SI 9)) | |
8949 | (clobber (reg:SI 10)) | |
3c67b673 | 8950 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
8951 | "TARGET_STRING && TARGET_POWER |
8952 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
8953 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8954 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8955 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8956 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8957 | [(set_attr "type" "load") |
8958 | (set_attr "length" "8")]) | |
7e69e155 MM |
8959 | |
8960 | (define_insn "" | |
52d3af72 DE |
8961 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8962 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8963 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8964 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8965 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8966 | (clobber (reg:SI 6)) |
8967 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8968 | (clobber (reg:SI 8)) |
8969 | (clobber (reg:SI 9)) | |
8970 | (clobber (reg:SI 10)) | |
3c67b673 | 8971 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8972 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8973 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
8974 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8975 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8976 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8977 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8978 | [(set_attr "type" "load") |
8979 | (set_attr "length" "8")]) | |
7e69e155 | 8980 | |
09a625f7 TR |
8981 | (define_insn "" |
8982 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
8983 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
8984 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
8985 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8986 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
8987 | (clobber (reg:SI 6)) | |
8988 | (clobber (reg:SI 7)) | |
8989 | (clobber (reg:SI 8)) | |
8990 | (clobber (reg:SI 9)) | |
8991 | (clobber (reg:SI 10)) | |
8992 | (clobber (match_scratch:SI 5 "X"))] | |
8993 | "TARGET_STRING && TARGET_POWERPC64 | |
8994 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 | |
8995 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) | |
8996 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8997 | && REGNO (operands[4]) == 5" | |
8998 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
8999 | [(set_attr "type" "load") | |
9000 | (set_attr "length" "8")]) | |
9001 | ||
f9562f27 DE |
9002 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
9003 | ;; problems with TImode. | |
9004 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 9005 | (define_expand "movmemsi_4reg" |
b6c9286a MM |
9006 | [(parallel [(set (match_operand 0 "" "") |
9007 | (match_operand 1 "" "")) | |
9008 | (use (match_operand 2 "" "")) | |
9009 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9010 | (clobber (reg:SI 5)) |
9011 | (clobber (reg:SI 6)) | |
9012 | (clobber (reg:SI 7)) | |
9013 | (clobber (reg:SI 8)) | |
3c67b673 | 9014 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9015 | "TARGET_STRING" |
9016 | "") | |
9017 | ||
9018 | (define_insn "" | |
52d3af72 DE |
9019 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9020 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9021 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9022 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9023 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9024 | (clobber (reg:SI 6)) |
9025 | (clobber (reg:SI 7)) | |
9026 | (clobber (reg:SI 8)) | |
3c67b673 | 9027 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9028 | "TARGET_STRING && TARGET_POWER |
9029 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
9030 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9031 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9032 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9033 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9034 | [(set_attr "type" "load") |
9035 | (set_attr "length" "8")]) | |
7e69e155 MM |
9036 | |
9037 | (define_insn "" | |
52d3af72 DE |
9038 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9039 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9040 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9041 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9042 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9043 | (clobber (reg:SI 6)) |
9044 | (clobber (reg:SI 7)) | |
9045 | (clobber (reg:SI 8)) | |
3c67b673 | 9046 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9047 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9048 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
9049 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9050 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9051 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9052 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9053 | [(set_attr "type" "load") |
9054 | (set_attr "length" "8")]) | |
7e69e155 | 9055 | |
09a625f7 TR |
9056 | (define_insn "" |
9057 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9058 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9059 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9060 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9061 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9062 | (clobber (reg:SI 6)) | |
9063 | (clobber (reg:SI 7)) | |
9064 | (clobber (reg:SI 8)) | |
9065 | (clobber (match_scratch:SI 5 "X"))] | |
9066 | "TARGET_STRING && TARGET_POWERPC64 | |
9067 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
9068 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) | |
9069 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9070 | && REGNO (operands[4]) == 5" | |
9071 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9072 | [(set_attr "type" "load") | |
9073 | (set_attr "length" "8")]) | |
9074 | ||
7e69e155 | 9075 | ;; Move up to 8 bytes at a time. |
70128ad9 | 9076 | (define_expand "movmemsi_2reg" |
b6c9286a MM |
9077 | [(parallel [(set (match_operand 0 "" "") |
9078 | (match_operand 1 "" "")) | |
9079 | (use (match_operand 2 "" "")) | |
9080 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9081 | (clobber (match_scratch:DI 4 "")) |
9082 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 9083 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
9084 | "") |
9085 | ||
9086 | (define_insn "" | |
52d3af72 DE |
9087 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9088 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9089 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9090 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9091 | (clobber (match_scratch:DI 4 "=&r")) | |
9092 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 9093 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
9094 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
9095 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9096 | [(set_attr "type" "load") |
9097 | (set_attr "length" "8")]) | |
7e69e155 MM |
9098 | |
9099 | (define_insn "" | |
52d3af72 DE |
9100 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9101 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9102 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9103 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9104 | (clobber (match_scratch:DI 4 "=&r")) | |
9105 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 9106 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 9107 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 9108 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9109 | [(set_attr "type" "load") |
9110 | (set_attr "length" "8")]) | |
7e69e155 MM |
9111 | |
9112 | ;; Move up to 4 bytes at a time. | |
70128ad9 | 9113 | (define_expand "movmemsi_1reg" |
b6c9286a MM |
9114 | [(parallel [(set (match_operand 0 "" "") |
9115 | (match_operand 1 "" "")) | |
9116 | (use (match_operand 2 "" "")) | |
9117 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9118 | (clobber (match_scratch:SI 4 "")) |
9119 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
9120 | "TARGET_STRING" |
9121 | "") | |
9122 | ||
9123 | (define_insn "" | |
52d3af72 DE |
9124 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9125 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9126 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9127 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9128 | (clobber (match_scratch:SI 4 "=&r")) | |
9129 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
9130 | "TARGET_STRING && TARGET_POWER |
9131 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9132 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9133 | [(set_attr "type" "load") |
9134 | (set_attr "length" "8")]) | |
7e69e155 MM |
9135 | |
9136 | (define_insn "" | |
52d3af72 DE |
9137 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9138 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9139 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9140 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9141 | (clobber (match_scratch:SI 4 "=&r")) | |
9142 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 9143 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9144 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
09a625f7 TR |
9145 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
9146 | [(set_attr "type" "load") | |
9147 | (set_attr "length" "8")]) | |
9148 | ||
9149 | (define_insn "" | |
9150 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9151 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9152 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9153 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9154 | (clobber (match_scratch:SI 4 "=&r")) | |
9155 | (clobber (match_scratch:SI 5 "X"))] | |
9156 | "TARGET_STRING && TARGET_POWERPC64 | |
9157 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9158 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9159 | [(set_attr "type" "load") |
9160 | (set_attr "length" "8")]) | |
7e69e155 | 9161 | |
1fd4e8c1 | 9162 | \f |
7e69e155 | 9163 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
9164 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
9165 | ;; do cases where the increment is not the size of the object. | |
9166 | ;; | |
9167 | ;; In all these cases, we use operands 0 and 1 for the register being | |
9168 | ;; incremented because those are the operands that local-alloc will | |
9169 | ;; tie and these are the pair most likely to be tieable (and the ones | |
9170 | ;; that will benefit the most). | |
9171 | ||
38c1f2d7 | 9172 | (define_insn "*movdi_update1" |
51b8fc2c | 9173 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 9174 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 9175 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) |
51b8fc2c RK |
9176 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") |
9177 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9178 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9179 | "@ |
9180 | ldux %3,%0,%2 | |
9181 | ldu %3,%2(%0)" | |
b54cf83a | 9182 | [(set_attr "type" "load_ux,load_u")]) |
287f13ff | 9183 | |
2e6c9641 FJ |
9184 | (define_insn "movdi_<mode>_update" |
9185 | [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") | |
9186 | (match_operand:P 2 "reg_or_aligned_short_operand" "r,I"))) | |
51b8fc2c | 9187 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) |
2e6c9641 FJ |
9188 | (set (match_operand:P 0 "gpc_reg_operand" "=b,b") |
9189 | (plus:P (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9190 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9191 | "@ |
9192 | stdux %3,%0,%2 | |
b7ff3d82 | 9193 | stdu %3,%2(%0)" |
b54cf83a | 9194 | [(set_attr "type" "store_ux,store_u")]) |
51b8fc2c | 9195 | |
38c1f2d7 | 9196 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
9197 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
9198 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9199 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9200 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9201 | (plus:SI (match_dup 1) (match_dup 2)))] |
f7b3ab8a | 9202 | "TARGET_UPDATE" |
1fd4e8c1 | 9203 | "@ |
ca7f5001 RK |
9204 | {lux|lwzux} %3,%0,%2 |
9205 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a DE |
9206 | [(set_attr "type" "load_ux,load_u")]) |
9207 | ||
9208 | (define_insn "*movsi_update2" | |
9209 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
9210 | (sign_extend:DI | |
9211 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
9212 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
9213 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
9214 | (plus:DI (match_dup 1) (match_dup 2)))] | |
9215 | "TARGET_POWERPC64" | |
9216 | "lwaux %3,%0,%2" | |
9217 | [(set_attr "type" "load_ext_ux")]) | |
1fd4e8c1 | 9218 | |
4697a36c | 9219 | (define_insn "movsi_update" |
cd2b37d9 | 9220 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9221 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9222 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
9223 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9224 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9225 | "TARGET_UPDATE" |
1fd4e8c1 | 9226 | "@ |
ca7f5001 | 9227 | {stux|stwux} %3,%0,%2 |
b7ff3d82 | 9228 | {stu|stwu} %3,%2(%0)" |
b54cf83a | 9229 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9230 | |
b54cf83a | 9231 | (define_insn "*movhi_update1" |
cd2b37d9 RK |
9232 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
9233 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9234 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9235 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9236 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9237 | "TARGET_UPDATE" |
1fd4e8c1 | 9238 | "@ |
5f243543 RK |
9239 | lhzux %3,%0,%2 |
9240 | lhzu %3,%2(%0)" | |
b54cf83a | 9241 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9242 | |
38c1f2d7 | 9243 | (define_insn "*movhi_update2" |
cd2b37d9 | 9244 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9245 | (zero_extend:SI |
cd2b37d9 | 9246 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9247 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9248 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9249 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9250 | "TARGET_UPDATE" |
1fd4e8c1 | 9251 | "@ |
5f243543 RK |
9252 | lhzux %3,%0,%2 |
9253 | lhzu %3,%2(%0)" | |
b54cf83a | 9254 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9255 | |
38c1f2d7 | 9256 | (define_insn "*movhi_update3" |
cd2b37d9 | 9257 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9258 | (sign_extend:SI |
cd2b37d9 | 9259 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9260 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9261 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9262 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9263 | "TARGET_UPDATE" |
1fd4e8c1 | 9264 | "@ |
5f243543 RK |
9265 | lhaux %3,%0,%2 |
9266 | lhau %3,%2(%0)" | |
b54cf83a | 9267 | [(set_attr "type" "load_ext_ux,load_ext_u")]) |
1fd4e8c1 | 9268 | |
38c1f2d7 | 9269 | (define_insn "*movhi_update4" |
cd2b37d9 | 9270 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9271 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9272 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
9273 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9274 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9275 | "TARGET_UPDATE" |
1fd4e8c1 | 9276 | "@ |
5f243543 | 9277 | sthux %3,%0,%2 |
b7ff3d82 | 9278 | sthu %3,%2(%0)" |
b54cf83a | 9279 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9280 | |
38c1f2d7 | 9281 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
9282 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
9283 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9284 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9285 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9286 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9287 | "TARGET_UPDATE" |
1fd4e8c1 | 9288 | "@ |
5f243543 RK |
9289 | lbzux %3,%0,%2 |
9290 | lbzu %3,%2(%0)" | |
b54cf83a | 9291 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9292 | |
38c1f2d7 | 9293 | (define_insn "*movqi_update2" |
cd2b37d9 | 9294 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9295 | (zero_extend:SI |
cd2b37d9 | 9296 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9297 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9298 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9299 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9300 | "TARGET_UPDATE" |
1fd4e8c1 | 9301 | "@ |
5f243543 RK |
9302 | lbzux %3,%0,%2 |
9303 | lbzu %3,%2(%0)" | |
b54cf83a | 9304 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9305 | |
38c1f2d7 | 9306 | (define_insn "*movqi_update3" |
cd2b37d9 | 9307 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9308 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9309 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
9310 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9311 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9312 | "TARGET_UPDATE" |
1fd4e8c1 | 9313 | "@ |
5f243543 | 9314 | stbux %3,%0,%2 |
b7ff3d82 | 9315 | stbu %3,%2(%0)" |
b54cf83a | 9316 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9317 | |
38c1f2d7 | 9318 | (define_insn "*movsf_update1" |
cd2b37d9 | 9319 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 9320 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9321 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9322 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9323 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9324 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9325 | "@ |
5f243543 RK |
9326 | lfsux %3,%0,%2 |
9327 | lfsu %3,%2(%0)" | |
b54cf83a | 9328 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9329 | |
38c1f2d7 | 9330 | (define_insn "*movsf_update2" |
cd2b37d9 | 9331 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9332 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9333 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
9334 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9335 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9336 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9337 | "@ |
85fff2f3 | 9338 | stfsux %3,%0,%2 |
b7ff3d82 | 9339 | stfsu %3,%2(%0)" |
b54cf83a | 9340 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
1fd4e8c1 | 9341 | |
38c1f2d7 MM |
9342 | (define_insn "*movsf_update3" |
9343 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
9344 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9345 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
9346 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9347 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9348 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9349 | "@ |
9350 | {lux|lwzux} %3,%0,%2 | |
9351 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a | 9352 | [(set_attr "type" "load_ux,load_u")]) |
38c1f2d7 MM |
9353 | |
9354 | (define_insn "*movsf_update4" | |
9355 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9356 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
9357 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
9358 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9359 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9360 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9361 | "@ |
9362 | {stux|stwux} %3,%0,%2 | |
9363 | {stu|stwu} %3,%2(%0)" | |
b54cf83a | 9364 | [(set_attr "type" "store_ux,store_u")]) |
38c1f2d7 MM |
9365 | |
9366 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
9367 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
9368 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9369 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9370 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9371 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9372 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9373 | "@ |
5f243543 RK |
9374 | lfdux %3,%0,%2 |
9375 | lfdu %3,%2(%0)" | |
b54cf83a | 9376 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9377 | |
38c1f2d7 | 9378 | (define_insn "*movdf_update2" |
cd2b37d9 | 9379 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9380 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9381 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
9382 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9383 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9384 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9385 | "@ |
5f243543 | 9386 | stfdux %3,%0,%2 |
b7ff3d82 | 9387 | stfdu %3,%2(%0)" |
b54cf83a | 9388 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
4c70a4f3 RK |
9389 | |
9390 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
9391 | ||
90f81f99 AP |
9392 | (define_insn "*lfq_power2" |
9393 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
9394 | (match_operand:TF 1 "memory_operand" ""))] | |
9395 | "TARGET_POWER2 | |
9396 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
9397 | "lfq%U1%X1 %0,%1") | |
9398 | ||
9399 | (define_peephole2 | |
9400 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4c70a4f3 | 9401 | (match_operand:DF 1 "memory_operand" "")) |
90f81f99 | 9402 | (set (match_operand:DF 2 "gpc_reg_operand" "") |
4c70a4f3 RK |
9403 | (match_operand:DF 3 "memory_operand" ""))] |
9404 | "TARGET_POWER2 | |
a3170dc6 | 9405 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9406 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
90f81f99 AP |
9407 | && mems_ok_for_quad_peep (operands[1], operands[3])" |
9408 | [(set (match_dup 0) | |
9409 | (match_dup 1))] | |
9410 | "operands[1] = widen_memory_access (operands[1], TFmode, 0); | |
9411 | operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));") | |
4c70a4f3 | 9412 | |
90f81f99 AP |
9413 | (define_insn "*stfq_power2" |
9414 | [(set (match_operand:TF 0 "memory_operand" "") | |
9415 | (match_operand:TF 1 "gpc_reg_operand" "f"))] | |
9416 | "TARGET_POWER2 | |
9417 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
9418 | "stfq%U0%X0 %1,%0") | |
9419 | ||
9420 | ||
9421 | (define_peephole2 | |
4c70a4f3 | 9422 | [(set (match_operand:DF 0 "memory_operand" "") |
90f81f99 | 9423 | (match_operand:DF 1 "gpc_reg_operand" "")) |
4c70a4f3 | 9424 | (set (match_operand:DF 2 "memory_operand" "") |
90f81f99 | 9425 | (match_operand:DF 3 "gpc_reg_operand" ""))] |
4c70a4f3 | 9426 | "TARGET_POWER2 |
a3170dc6 | 9427 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9428 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
90f81f99 AP |
9429 | && mems_ok_for_quad_peep (operands[0], operands[2])" |
9430 | [(set (match_dup 0) | |
9431 | (match_dup 1))] | |
9432 | "operands[0] = widen_memory_access (operands[0], TFmode, 0); | |
9433 | operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));") | |
2f4d9502 NS |
9434 | |
9435 | ;; after inserting conditional returns we can sometimes have | |
9436 | ;; unnecessary register moves. Unfortunately we cannot have a | |
9437 | ;; modeless peephole here, because some single SImode sets have early | |
9438 | ;; clobber outputs. Although those sets expand to multi-ppc-insn | |
9439 | ;; sequences, using get_attr_length here will smash the operands | |
9440 | ;; array. Neither is there an early_cobbler_p predicate. | |
9441 | (define_peephole2 | |
9442 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
9443 | (match_operand:DF 1 "any_operand" "")) | |
9444 | (set (match_operand:DF 2 "gpc_reg_operand" "") | |
9445 | (match_dup 0))] | |
9446 | "peep2_reg_dead_p (2, operands[0])" | |
9447 | [(set (match_dup 2) (match_dup 1))]) | |
9448 | ||
9449 | (define_peephole2 | |
9450 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
9451 | (match_operand:SF 1 "any_operand" "")) | |
9452 | (set (match_operand:SF 2 "gpc_reg_operand" "") | |
9453 | (match_dup 0))] | |
9454 | "peep2_reg_dead_p (2, operands[0])" | |
9455 | [(set (match_dup 2) (match_dup 1))]) | |
9456 | ||
1fd4e8c1 | 9457 | \f |
c4501e62 JJ |
9458 | ;; TLS support. |
9459 | ||
9460 | ;; "b" output constraint here and on tls_ld to support tls linker optimization. | |
9461 | (define_insn "tls_gd_32" | |
b150f4f3 DE |
9462 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9463 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9464 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9465 | UNSPEC_TLSGD))] | |
9466 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9467 | "addi %0,%1,%2@got@tlsgd") | |
9468 | ||
9469 | (define_insn "tls_gd_64" | |
b150f4f3 DE |
9470 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9471 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9472 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9473 | UNSPEC_TLSGD))] | |
9474 | "HAVE_AS_TLS && TARGET_64BIT" | |
9475 | "addi %0,%1,%2@got@tlsgd") | |
9476 | ||
9477 | (define_insn "tls_ld_32" | |
b150f4f3 DE |
9478 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9479 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9480 | UNSPEC_TLSLD))] |
9481 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9482 | "addi %0,%1,%&@got@tlsld") | |
9483 | ||
9484 | (define_insn "tls_ld_64" | |
b150f4f3 DE |
9485 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9486 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9487 | UNSPEC_TLSLD))] |
9488 | "HAVE_AS_TLS && TARGET_64BIT" | |
9489 | "addi %0,%1,%&@got@tlsld") | |
9490 | ||
9491 | (define_insn "tls_dtprel_32" | |
b150f4f3 DE |
9492 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9493 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9494 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9495 | UNSPEC_TLSDTPREL))] | |
9496 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9497 | "addi %0,%1,%2@dtprel") | |
9498 | ||
9499 | (define_insn "tls_dtprel_64" | |
b150f4f3 DE |
9500 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9501 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9502 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9503 | UNSPEC_TLSDTPREL))] | |
9504 | "HAVE_AS_TLS && TARGET_64BIT" | |
9505 | "addi %0,%1,%2@dtprel") | |
9506 | ||
9507 | (define_insn "tls_dtprel_ha_32" | |
b150f4f3 DE |
9508 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9509 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9510 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9511 | UNSPEC_TLSDTPRELHA))] | |
9512 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9513 | "addis %0,%1,%2@dtprel@ha") | |
9514 | ||
9515 | (define_insn "tls_dtprel_ha_64" | |
b150f4f3 DE |
9516 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9517 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9518 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9519 | UNSPEC_TLSDTPRELHA))] | |
9520 | "HAVE_AS_TLS && TARGET_64BIT" | |
9521 | "addis %0,%1,%2@dtprel@ha") | |
9522 | ||
9523 | (define_insn "tls_dtprel_lo_32" | |
b150f4f3 DE |
9524 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9525 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9526 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9527 | UNSPEC_TLSDTPRELLO))] | |
9528 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9529 | "addi %0,%1,%2@dtprel@l") | |
9530 | ||
9531 | (define_insn "tls_dtprel_lo_64" | |
b150f4f3 DE |
9532 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9533 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9534 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9535 | UNSPEC_TLSDTPRELLO))] | |
9536 | "HAVE_AS_TLS && TARGET_64BIT" | |
9537 | "addi %0,%1,%2@dtprel@l") | |
9538 | ||
9539 | (define_insn "tls_got_dtprel_32" | |
b150f4f3 DE |
9540 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9541 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9542 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9543 | UNSPEC_TLSGOTDTPREL))] | |
9544 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9545 | "lwz %0,%2@got@dtprel(%1)") | |
9546 | ||
9547 | (define_insn "tls_got_dtprel_64" | |
b150f4f3 DE |
9548 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9549 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9550 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9551 | UNSPEC_TLSGOTDTPREL))] | |
9552 | "HAVE_AS_TLS && TARGET_64BIT" | |
9553 | "ld %0,%2@got@dtprel(%1)") | |
9554 | ||
9555 | (define_insn "tls_tprel_32" | |
b150f4f3 DE |
9556 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9557 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9558 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9559 | UNSPEC_TLSTPREL))] | |
9560 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9561 | "addi %0,%1,%2@tprel") | |
9562 | ||
9563 | (define_insn "tls_tprel_64" | |
b150f4f3 DE |
9564 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9565 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9566 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9567 | UNSPEC_TLSTPREL))] | |
9568 | "HAVE_AS_TLS && TARGET_64BIT" | |
9569 | "addi %0,%1,%2@tprel") | |
9570 | ||
9571 | (define_insn "tls_tprel_ha_32" | |
b150f4f3 DE |
9572 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9573 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9574 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9575 | UNSPEC_TLSTPRELHA))] | |
9576 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9577 | "addis %0,%1,%2@tprel@ha") | |
9578 | ||
9579 | (define_insn "tls_tprel_ha_64" | |
b150f4f3 DE |
9580 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9581 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9582 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9583 | UNSPEC_TLSTPRELHA))] | |
9584 | "HAVE_AS_TLS && TARGET_64BIT" | |
9585 | "addis %0,%1,%2@tprel@ha") | |
9586 | ||
9587 | (define_insn "tls_tprel_lo_32" | |
b150f4f3 DE |
9588 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9589 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9590 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9591 | UNSPEC_TLSTPRELLO))] | |
9592 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9593 | "addi %0,%1,%2@tprel@l") | |
9594 | ||
9595 | (define_insn "tls_tprel_lo_64" | |
b150f4f3 DE |
9596 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9597 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9598 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9599 | UNSPEC_TLSTPRELLO))] | |
9600 | "HAVE_AS_TLS && TARGET_64BIT" | |
9601 | "addi %0,%1,%2@tprel@l") | |
9602 | ||
c1207243 | 9603 | ;; "b" output constraint here and on tls_tls input to support linker tls |
c4501e62 JJ |
9604 | ;; optimization. The linker may edit the instructions emitted by a |
9605 | ;; tls_got_tprel/tls_tls pair to addis,addi. | |
9606 | (define_insn "tls_got_tprel_32" | |
b150f4f3 DE |
9607 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9608 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9609 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9610 | UNSPEC_TLSGOTTPREL))] | |
9611 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9612 | "lwz %0,%2@got@tprel(%1)") | |
9613 | ||
9614 | (define_insn "tls_got_tprel_64" | |
b150f4f3 DE |
9615 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9616 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9617 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9618 | UNSPEC_TLSGOTTPREL))] | |
9619 | "HAVE_AS_TLS && TARGET_64BIT" | |
9620 | "ld %0,%2@got@tprel(%1)") | |
9621 | ||
9622 | (define_insn "tls_tls_32" | |
b150f4f3 DE |
9623 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9624 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9625 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9626 | UNSPEC_TLSTLS))] | |
9627 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9628 | "add %0,%1,%2@tls") | |
9629 | ||
9630 | (define_insn "tls_tls_64" | |
b150f4f3 DE |
9631 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9632 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9633 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9634 | UNSPEC_TLSTLS))] | |
9635 | "HAVE_AS_TLS && TARGET_64BIT" | |
9636 | "add %0,%1,%2@tls") | |
9637 | \f | |
1fd4e8c1 RK |
9638 | ;; Next come insns related to the calling sequence. |
9639 | ;; | |
9640 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 9641 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
9642 | |
9643 | (define_expand "allocate_stack" | |
52d3af72 | 9644 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9645 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
9646 | (set (reg 1) | |
9647 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
9648 | "" |
9649 | " | |
4697a36c | 9650 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 9651 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 9652 | rtx neg_op0; |
1fd4e8c1 RK |
9653 | |
9654 | emit_move_insn (chain, stack_bot); | |
4697a36c | 9655 | |
a157febd GK |
9656 | /* Check stack bounds if necessary. */ |
9657 | if (current_function_limit_stack) | |
9658 | { | |
9659 | rtx available; | |
6ae08853 | 9660 | available = expand_binop (Pmode, sub_optab, |
a157febd GK |
9661 | stack_pointer_rtx, stack_limit_rtx, |
9662 | NULL_RTX, 1, OPTAB_WIDEN); | |
9663 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
9664 | } | |
9665 | ||
e9a25f70 JL |
9666 | if (GET_CODE (operands[1]) != CONST_INT |
9667 | || INTVAL (operands[1]) < -32767 | |
9668 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
9669 | { |
9670 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 9671 | if (TARGET_32BIT) |
e9a25f70 | 9672 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 9673 | else |
e9a25f70 | 9674 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
9675 | } |
9676 | else | |
e9a25f70 | 9677 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 9678 | |
38c1f2d7 | 9679 | if (TARGET_UPDATE) |
2e6c9641 | 9680 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update)) |
38c1f2d7 | 9681 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); |
4697a36c | 9682 | |
38c1f2d7 MM |
9683 | else |
9684 | { | |
9685 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
9686 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 9687 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 9688 | } |
e9a25f70 JL |
9689 | |
9690 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
9691 | DONE; |
9692 | }") | |
59257ff7 RK |
9693 | |
9694 | ;; These patterns say how to save and restore the stack pointer. We need not | |
9695 | ;; save the stack pointer at function level since we are careful to | |
9696 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9697 | ;; when we restore the stack pointer. | |
9698 | ;; | |
9699 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9700 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9701 | ;; save area is a memory location. | |
9702 | ||
9703 | (define_expand "save_stack_function" | |
ff381587 MM |
9704 | [(match_operand 0 "any_operand" "") |
9705 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9706 | "" |
ff381587 | 9707 | "DONE;") |
59257ff7 RK |
9708 | |
9709 | (define_expand "restore_stack_function" | |
ff381587 MM |
9710 | [(match_operand 0 "any_operand" "") |
9711 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9712 | "" |
ff381587 | 9713 | "DONE;") |
59257ff7 RK |
9714 | |
9715 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
9716 | [(use (match_operand 0 "register_operand" "")) |
9717 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 9718 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 9719 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
9720 | "" |
9721 | " | |
dfdfa60f DE |
9722 | { |
9723 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 9724 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 9725 | }") |
59257ff7 RK |
9726 | |
9727 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
9728 | [(match_operand 0 "memory_operand" "") |
9729 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
9730 | "" |
9731 | " | |
9732 | { | |
a260abc9 | 9733 | rtx temp = gen_reg_rtx (Pmode); |
11b25716 | 9734 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
9735 | |
9736 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 9737 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
39e453d7 DE |
9738 | emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp); |
9739 | emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word), | |
a260abc9 | 9740 | operands[1]); |
59257ff7 RK |
9741 | DONE; |
9742 | }") | |
7e69e155 | 9743 | |
59257ff7 | 9744 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
9745 | [(match_operand 0 "register_operand" "") |
9746 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
9747 | "" |
9748 | " | |
9749 | { | |
a260abc9 | 9750 | rtx temp = gen_reg_rtx (Pmode); |
11b25716 | 9751 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
9752 | |
9753 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 | 9754 | emit_move_insn (temp, |
39e453d7 | 9755 | adjust_address_nv (operands[1], Pmode, 0)); |
a260abc9 | 9756 | emit_move_insn (operands[0], |
39e453d7 | 9757 | adjust_address_nv (operands[1], Pmode, units_per_word)); |
39403d82 | 9758 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
9759 | DONE; |
9760 | }") | |
9ebbca7d GK |
9761 | \f |
9762 | ;; TOC register handling. | |
b6c9286a | 9763 | |
9ebbca7d | 9764 | ;; Code to initialize the TOC register... |
f0f6a223 | 9765 | |
9ebbca7d | 9766 | (define_insn "load_toc_aix_si" |
e72247f4 | 9767 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
615158e2 | 9768 | (unspec:SI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 9769 | (use (reg:SI 2))])] |
2bfcf297 | 9770 | "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" |
f0f6a223 RK |
9771 | "* |
9772 | { | |
9ebbca7d GK |
9773 | char buf[30]; |
9774 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 9775 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9776 | operands[2] = gen_rtx_REG (Pmode, 2); |
9777 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
9778 | }" |
9779 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
9780 | |
9781 | (define_insn "load_toc_aix_di" | |
e72247f4 | 9782 | [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
615158e2 | 9783 | (unspec:DI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 9784 | (use (reg:DI 2))])] |
2bfcf297 | 9785 | "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" |
9ebbca7d GK |
9786 | "* |
9787 | { | |
9788 | char buf[30]; | |
f585a356 DE |
9789 | #ifdef TARGET_RELOCATABLE |
9790 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", | |
9791 | !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); | |
9792 | #else | |
9ebbca7d | 9793 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); |
f585a356 | 9794 | #endif |
2bfcf297 DB |
9795 | if (TARGET_ELF) |
9796 | strcat (buf, \"@toc\"); | |
a8a05998 | 9797 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9798 | operands[2] = gen_rtx_REG (Pmode, 2); |
9799 | return \"ld %0,%1(%2)\"; | |
9800 | }" | |
9801 | [(set_attr "type" "load")]) | |
9802 | ||
9803 | (define_insn "load_toc_v4_pic_si" | |
9804 | [(set (match_operand:SI 0 "register_operand" "=l") | |
615158e2 | 9805 | (unspec:SI [(const_int 0)] UNSPEC_TOC))] |
f607bc57 | 9806 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" |
9ebbca7d GK |
9807 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
9808 | [(set_attr "type" "branch") | |
9809 | (set_attr "length" "4")]) | |
9810 | ||
9ebbca7d GK |
9811 | (define_insn "load_toc_v4_PIC_1" |
9812 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9813 | (match_operand:SI 1 "immediate_operand" "s")) | |
c4501e62 | 9814 | (use (unspec [(match_dup 1)] UNSPEC_TOC))] |
20b71b17 | 9815 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
df7a8989 | 9816 | "bcl 20,31,%1\\n%1:" |
9ebbca7d GK |
9817 | [(set_attr "type" "branch") |
9818 | (set_attr "length" "4")]) | |
9819 | ||
9820 | (define_insn "load_toc_v4_PIC_1b" | |
9821 | [(set (match_operand:SI 0 "register_operand" "=l") | |
0e5be35b | 9822 | (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] |
c4501e62 | 9823 | UNSPEC_TOCPTR))] |
20b71b17 | 9824 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
0e5be35b | 9825 | "bcl 20,31,$+8\\n\\t.long %1-$" |
9ebbca7d GK |
9826 | [(set_attr "type" "branch") |
9827 | (set_attr "length" "8")]) | |
9828 | ||
9829 | (define_insn "load_toc_v4_PIC_2" | |
f585a356 | 9830 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
a2900460 | 9831 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
9ebbca7d GK |
9832 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") |
9833 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
20b71b17 | 9834 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
9ebbca7d GK |
9835 | "{l|lwz} %0,%2-%3(%1)" |
9836 | [(set_attr "type" "load")]) | |
9837 | ||
f51eee6a | 9838 | |
9ebbca7d GK |
9839 | ;; If the TOC is shared over a translation unit, as happens with all |
9840 | ;; the kinds of PIC that we support, we need to restore the TOC | |
9841 | ;; pointer only when jumping over units of translation. | |
f51eee6a | 9842 | ;; On Darwin, we need to reload the picbase. |
9ebbca7d GK |
9843 | |
9844 | (define_expand "builtin_setjmp_receiver" | |
9845 | [(use (label_ref (match_operand 0 "" "")))] | |
f607bc57 | 9846 | "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
f51eee6a GK |
9847 | || (TARGET_TOC && TARGET_MINIMAL_TOC) |
9848 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" | |
9ebbca7d GK |
9849 | " |
9850 | { | |
84d7dd4a | 9851 | #if TARGET_MACHO |
f51eee6a GK |
9852 | if (DEFAULT_ABI == ABI_DARWIN) |
9853 | { | |
d24652ee | 9854 | const char *picbase = machopic_function_base_name (); |
485bad26 | 9855 | rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase)); |
f51eee6a GK |
9856 | rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
9857 | rtx tmplabrtx; | |
9858 | char tmplab[20]; | |
9859 | ||
9860 | ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", | |
9861 | CODE_LABEL_NUMBER (operands[0])); | |
485bad26 | 9862 | tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); |
f51eee6a | 9863 | |
b8a55285 AP |
9864 | emit_insn (gen_load_macho_picbase (picreg, tmplabrtx)); |
9865 | emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); | |
f51eee6a GK |
9866 | } |
9867 | else | |
84d7dd4a | 9868 | #endif |
f51eee6a | 9869 | rs6000_emit_load_toc_table (FALSE); |
9ebbca7d GK |
9870 | DONE; |
9871 | }") | |
9872 | \f | |
9873 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
9874 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
9875 | ;; pointer to its TOC, and whose third word contains a value to place in the |
9876 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 9877 | ;; "trampoline" need not have any executable code. |
b6c9286a | 9878 | |
cccf3bdc DE |
9879 | (define_expand "call_indirect_aix32" |
9880 | [(set (match_dup 2) | |
9881 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
9882 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9883 | (reg:SI 2)) | |
9884 | (set (reg:SI 2) | |
9885 | (mem:SI (plus:SI (match_dup 0) | |
9886 | (const_int 4)))) | |
9887 | (set (reg:SI 11) | |
9888 | (mem:SI (plus:SI (match_dup 0) | |
9889 | (const_int 8)))) | |
9890 | (parallel [(call (mem:SI (match_dup 2)) | |
9891 | (match_operand 1 "" "")) | |
9892 | (use (reg:SI 2)) | |
9893 | (use (reg:SI 11)) | |
9894 | (set (reg:SI 2) | |
9895 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9896 | (clobber (scratch:SI))])] | |
9897 | "TARGET_32BIT" | |
9898 | " | |
9899 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9900 | |
cccf3bdc DE |
9901 | (define_expand "call_indirect_aix64" |
9902 | [(set (match_dup 2) | |
9903 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
9904 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9905 | (reg:DI 2)) | |
9906 | (set (reg:DI 2) | |
9907 | (mem:DI (plus:DI (match_dup 0) | |
9908 | (const_int 8)))) | |
9909 | (set (reg:DI 11) | |
9910 | (mem:DI (plus:DI (match_dup 0) | |
9911 | (const_int 16)))) | |
9912 | (parallel [(call (mem:SI (match_dup 2)) | |
9913 | (match_operand 1 "" "")) | |
9914 | (use (reg:DI 2)) | |
9915 | (use (reg:DI 11)) | |
9916 | (set (reg:DI 2) | |
9917 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9918 | (clobber (scratch:SI))])] | |
9919 | "TARGET_64BIT" | |
9920 | " | |
9921 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 9922 | |
cccf3bdc DE |
9923 | (define_expand "call_value_indirect_aix32" |
9924 | [(set (match_dup 3) | |
9925 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
9926 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9927 | (reg:SI 2)) | |
9928 | (set (reg:SI 2) | |
9929 | (mem:SI (plus:SI (match_dup 1) | |
9930 | (const_int 4)))) | |
9931 | (set (reg:SI 11) | |
9932 | (mem:SI (plus:SI (match_dup 1) | |
9933 | (const_int 8)))) | |
9934 | (parallel [(set (match_operand 0 "" "") | |
9935 | (call (mem:SI (match_dup 3)) | |
9936 | (match_operand 2 "" ""))) | |
9937 | (use (reg:SI 2)) | |
9938 | (use (reg:SI 11)) | |
9939 | (set (reg:SI 2) | |
9940 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9941 | (clobber (scratch:SI))])] | |
9942 | "TARGET_32BIT" | |
9943 | " | |
9944 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9945 | |
cccf3bdc DE |
9946 | (define_expand "call_value_indirect_aix64" |
9947 | [(set (match_dup 3) | |
9948 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
9949 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9950 | (reg:DI 2)) | |
9951 | (set (reg:DI 2) | |
9952 | (mem:DI (plus:DI (match_dup 1) | |
9953 | (const_int 8)))) | |
9954 | (set (reg:DI 11) | |
9955 | (mem:DI (plus:DI (match_dup 1) | |
9956 | (const_int 16)))) | |
9957 | (parallel [(set (match_operand 0 "" "") | |
9958 | (call (mem:SI (match_dup 3)) | |
9959 | (match_operand 2 "" ""))) | |
9960 | (use (reg:DI 2)) | |
9961 | (use (reg:DI 11)) | |
9962 | (set (reg:DI 2) | |
9963 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9964 | (clobber (scratch:SI))])] | |
9965 | "TARGET_64BIT" | |
9966 | " | |
9967 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 9968 | |
b6c9286a | 9969 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 9970 | (define_expand "call" |
a260abc9 | 9971 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 9972 | (match_operand 1 "" "")) |
4697a36c | 9973 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
9974 | (clobber (scratch:SI))])] |
9975 | "" | |
9976 | " | |
9977 | { | |
ee890fe2 | 9978 | #if TARGET_MACHO |
ab82a49f | 9979 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
9980 | operands[0] = machopic_indirect_call_target (operands[0]); |
9981 | #endif | |
9982 | ||
37409796 NS |
9983 | gcc_assert (GET_CODE (operands[0]) == MEM); |
9984 | gcc_assert (GET_CODE (operands[1]) == CONST_INT); | |
1fd4e8c1 RK |
9985 | |
9986 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 9987 | |
6a4cee5f | 9988 | if (GET_CODE (operands[0]) != SYMBOL_REF |
473f51b6 | 9989 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0])) |
efdba735 | 9990 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0)) |
1fd4e8c1 | 9991 | { |
6a4cee5f MM |
9992 | if (INTVAL (operands[2]) & CALL_LONG) |
9993 | operands[0] = rs6000_longcall_ref (operands[0]); | |
9994 | ||
37409796 NS |
9995 | switch (DEFAULT_ABI) |
9996 | { | |
9997 | case ABI_V4: | |
9998 | case ABI_DARWIN: | |
9999 | operands[0] = force_reg (Pmode, operands[0]); | |
10000 | break; | |
1fd4e8c1 | 10001 | |
37409796 | 10002 | case ABI_AIX: |
cccf3bdc DE |
10003 | /* AIX function pointers are really pointers to a three word |
10004 | area. */ | |
10005 | emit_call_insn (TARGET_32BIT | |
10006 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
10007 | operands[0]), | |
10008 | operands[1]) | |
10009 | : gen_call_indirect_aix64 (force_reg (DImode, | |
10010 | operands[0]), | |
10011 | operands[1])); | |
10012 | DONE; | |
37409796 NS |
10013 | |
10014 | default: | |
10015 | gcc_unreachable (); | |
b6c9286a | 10016 | } |
1fd4e8c1 RK |
10017 | } |
10018 | }") | |
10019 | ||
10020 | (define_expand "call_value" | |
10021 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 10022 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 10023 | (match_operand 2 "" ""))) |
4697a36c | 10024 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
10025 | (clobber (scratch:SI))])] |
10026 | "" | |
10027 | " | |
10028 | { | |
ee890fe2 | 10029 | #if TARGET_MACHO |
ab82a49f | 10030 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
10031 | operands[1] = machopic_indirect_call_target (operands[1]); |
10032 | #endif | |
10033 | ||
37409796 NS |
10034 | gcc_assert (GET_CODE (operands[1]) == MEM); |
10035 | gcc_assert (GET_CODE (operands[2]) == CONST_INT); | |
1fd4e8c1 RK |
10036 | |
10037 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 10038 | |
6a4cee5f | 10039 | if (GET_CODE (operands[1]) != SYMBOL_REF |
473f51b6 | 10040 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1])) |
efdba735 | 10041 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0)) |
1fd4e8c1 | 10042 | { |
6756293c | 10043 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
10044 | operands[1] = rs6000_longcall_ref (operands[1]); |
10045 | ||
37409796 NS |
10046 | switch (DEFAULT_ABI) |
10047 | { | |
10048 | case ABI_V4: | |
10049 | case ABI_DARWIN: | |
10050 | operands[1] = force_reg (Pmode, operands[1]); | |
10051 | break; | |
1fd4e8c1 | 10052 | |
37409796 | 10053 | case ABI_AIX: |
cccf3bdc DE |
10054 | /* AIX function pointers are really pointers to a three word |
10055 | area. */ | |
10056 | emit_call_insn (TARGET_32BIT | |
10057 | ? gen_call_value_indirect_aix32 (operands[0], | |
10058 | force_reg (SImode, | |
10059 | operands[1]), | |
10060 | operands[2]) | |
10061 | : gen_call_value_indirect_aix64 (operands[0], | |
10062 | force_reg (DImode, | |
10063 | operands[1]), | |
10064 | operands[2])); | |
10065 | DONE; | |
37409796 NS |
10066 | |
10067 | default: | |
10068 | gcc_unreachable (); | |
b6c9286a | 10069 | } |
1fd4e8c1 RK |
10070 | } |
10071 | }") | |
10072 | ||
04780ee7 | 10073 | ;; Call to function in current module. No TOC pointer reload needed. |
a0ab749a | 10074 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10075 | ;; either the function was not prototyped, or it was prototyped as a |
10076 | ;; variable argument function. It is > 0 if FP registers were passed | |
10077 | ;; and < 0 if they were not. | |
04780ee7 | 10078 | |
a260abc9 | 10079 | (define_insn "*call_local32" |
4697a36c MM |
10080 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
10081 | (match_operand 1 "" "g,g")) | |
10082 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10083 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 10084 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
10085 | "* |
10086 | { | |
6a4cee5f MM |
10087 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
10088 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10089 | ||
10090 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10091 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 10092 | |
a226df46 | 10093 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 10094 | }" |
b7ff3d82 DE |
10095 | [(set_attr "type" "branch") |
10096 | (set_attr "length" "4,8")]) | |
04780ee7 | 10097 | |
a260abc9 DE |
10098 | (define_insn "*call_local64" |
10099 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10100 | (match_operand 1 "" "g,g")) | |
10101 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10102 | (clobber (match_scratch:SI 3 "=l,l"))] | |
10103 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10104 | "* | |
10105 | { | |
10106 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10107 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10108 | ||
10109 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10110 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10111 | ||
10112 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
10113 | }" | |
10114 | [(set_attr "type" "branch") | |
10115 | (set_attr "length" "4,8")]) | |
10116 | ||
cccf3bdc | 10117 | (define_insn "*call_value_local32" |
d18dba68 | 10118 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10119 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) |
10120 | (match_operand 2 "" "g,g"))) | |
10121 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10122 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10123 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10124 | "* | |
10125 | { | |
10126 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10127 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10128 | ||
10129 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10130 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10131 | ||
10132 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10133 | }" | |
10134 | [(set_attr "type" "branch") | |
10135 | (set_attr "length" "4,8")]) | |
10136 | ||
10137 | ||
cccf3bdc | 10138 | (define_insn "*call_value_local64" |
d18dba68 | 10139 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10140 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) |
10141 | (match_operand 2 "" "g,g"))) | |
10142 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10143 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10144 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10145 | "* | |
10146 | { | |
10147 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10148 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10149 | ||
10150 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10151 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10152 | ||
10153 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10154 | }" | |
10155 | [(set_attr "type" "branch") | |
10156 | (set_attr "length" "4,8")]) | |
10157 | ||
04780ee7 | 10158 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 10159 | ;; pointer (r2) after the call unless this is System V. |
a0ab749a | 10160 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10161 | ;; either the function was not prototyped, or it was prototyped as a |
10162 | ;; variable argument function. It is > 0 if FP registers were passed | |
10163 | ;; and < 0 if they were not. | |
04780ee7 | 10164 | |
cccf3bdc DE |
10165 | (define_insn "*call_indirect_nonlocal_aix32" |
10166 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) | |
10167 | (match_operand 1 "" "g")) | |
10168 | (use (reg:SI 2)) | |
10169 | (use (reg:SI 11)) | |
10170 | (set (reg:SI 2) | |
10171 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
c77e04ae | 10172 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10173 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
10174 | "b%T0l\;{l|lwz} 2,20(1)" | |
10175 | [(set_attr "type" "jmpreg") | |
10176 | (set_attr "length" "8")]) | |
10177 | ||
a260abc9 | 10178 | (define_insn "*call_nonlocal_aix32" |
cc4d5fec | 10179 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10180 | (match_operand 1 "" "g")) |
10181 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10182 | (clobber (match_scratch:SI 3 "=l"))] | |
10183 | "TARGET_32BIT | |
10184 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10185 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10186 | "bl %z0\;%." |
b7ff3d82 | 10187 | [(set_attr "type" "branch") |
cccf3bdc DE |
10188 | (set_attr "length" "8")]) |
10189 | ||
10190 | (define_insn "*call_indirect_nonlocal_aix64" | |
10191 | [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) | |
10192 | (match_operand 1 "" "g")) | |
10193 | (use (reg:DI 2)) | |
10194 | (use (reg:DI 11)) | |
10195 | (set (reg:DI 2) | |
10196 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
c77e04ae | 10197 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10198 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
10199 | "b%T0l\;ld 2,40(1)" | |
10200 | [(set_attr "type" "jmpreg") | |
10201 | (set_attr "length" "8")]) | |
59313e4e | 10202 | |
a260abc9 | 10203 | (define_insn "*call_nonlocal_aix64" |
cc4d5fec | 10204 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10205 | (match_operand 1 "" "g")) |
10206 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10207 | (clobber (match_scratch:SI 3 "=l"))] | |
6ae08853 | 10208 | "TARGET_64BIT |
9ebbca7d | 10209 | && DEFAULT_ABI == ABI_AIX |
a260abc9 | 10210 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10211 | "bl %z0\;%." |
a260abc9 | 10212 | [(set_attr "type" "branch") |
cccf3bdc | 10213 | (set_attr "length" "8")]) |
7509c759 | 10214 | |
cccf3bdc | 10215 | (define_insn "*call_value_indirect_nonlocal_aix32" |
d18dba68 | 10216 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10217 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) |
10218 | (match_operand 2 "" "g"))) | |
10219 | (use (reg:SI 2)) | |
10220 | (use (reg:SI 11)) | |
10221 | (set (reg:SI 2) | |
10222 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10223 | (clobber (match_scratch:SI 3 "=l"))] | |
10224 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" | |
10225 | "b%T1l\;{l|lwz} 2,20(1)" | |
10226 | [(set_attr "type" "jmpreg") | |
10227 | (set_attr "length" "8")]) | |
1fd4e8c1 | 10228 | |
cccf3bdc | 10229 | (define_insn "*call_value_nonlocal_aix32" |
d18dba68 | 10230 | [(set (match_operand 0 "" "") |
cc4d5fec | 10231 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10232 | (match_operand 2 "" "g"))) |
10233 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10234 | (clobber (match_scratch:SI 4 "=l"))] | |
10235 | "TARGET_32BIT | |
10236 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10237 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 10238 | "bl %z1\;%." |
b7ff3d82 | 10239 | [(set_attr "type" "branch") |
cccf3bdc | 10240 | (set_attr "length" "8")]) |
04780ee7 | 10241 | |
cccf3bdc | 10242 | (define_insn "*call_value_indirect_nonlocal_aix64" |
d18dba68 | 10243 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10244 | (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) |
10245 | (match_operand 2 "" "g"))) | |
10246 | (use (reg:DI 2)) | |
10247 | (use (reg:DI 11)) | |
10248 | (set (reg:DI 2) | |
10249 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10250 | (clobber (match_scratch:SI 3 "=l"))] | |
10251 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" | |
10252 | "b%T1l\;ld 2,40(1)" | |
10253 | [(set_attr "type" "jmpreg") | |
10254 | (set_attr "length" "8")]) | |
10255 | ||
10256 | (define_insn "*call_value_nonlocal_aix64" | |
d18dba68 | 10257 | [(set (match_operand 0 "" "") |
cc4d5fec | 10258 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10259 | (match_operand 2 "" "g"))) |
10260 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10261 | (clobber (match_scratch:SI 4 "=l"))] | |
6ae08853 | 10262 | "TARGET_64BIT |
9ebbca7d | 10263 | && DEFAULT_ABI == ABI_AIX |
5a19791c | 10264 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
10265 | "bl %z1\;%." |
10266 | [(set_attr "type" "branch") | |
10267 | (set_attr "length" "8")]) | |
10268 | ||
10269 | ;; A function pointer under System V is just a normal pointer | |
10270 | ;; operands[0] is the function pointer | |
10271 | ;; operands[1] is the stack size to clean up | |
10272 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
10273 | ;; which indicates how to set cr1 | |
10274 | ||
a5c76ee6 ZW |
10275 | (define_insn "*call_indirect_nonlocal_sysv" |
10276 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl")) | |
10277 | (match_operand 1 "" "g,g")) | |
10278 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10279 | (clobber (match_scratch:SI 3 "=l,l"))] | |
50d440bc | 10280 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10281 | || DEFAULT_ABI == ABI_DARWIN" |
911f679c | 10282 | { |
cccf3bdc | 10283 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10284 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f | 10285 | |
cccf3bdc | 10286 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
a5c76ee6 | 10287 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10288 | |
a5c76ee6 ZW |
10289 | return "b%T0l"; |
10290 | } | |
10291 | [(set_attr "type" "jmpreg,jmpreg") | |
10292 | (set_attr "length" "4,8")]) | |
cccf3bdc | 10293 | |
a5c76ee6 ZW |
10294 | (define_insn "*call_nonlocal_sysv" |
10295 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10296 | (match_operand 1 "" "g,g")) | |
10297 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10298 | (clobber (match_scratch:SI 3 "=l,l"))] | |
efdba735 SH |
10299 | "(DEFAULT_ABI == ABI_DARWIN |
10300 | || (DEFAULT_ABI == ABI_V4 | |
10301 | && (INTVAL (operands[2]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10302 | { |
10303 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10304 | output_asm_insn ("crxor 6,6,6", operands); | |
10305 | ||
10306 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10307 | output_asm_insn ("creqv 6,6,6", operands); | |
10308 | ||
c989f2f7 | 10309 | #if TARGET_MACHO |
efdba735 SH |
10310 | return output_call(insn, operands, 0, 2); |
10311 | #else | |
a5c76ee6 | 10312 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0"; |
6ae08853 | 10313 | #endif |
a5c76ee6 ZW |
10314 | } |
10315 | [(set_attr "type" "branch,branch") | |
10316 | (set_attr "length" "4,8")]) | |
10317 | ||
10318 | (define_insn "*call_value_indirect_nonlocal_sysv" | |
d18dba68 | 10319 | [(set (match_operand 0 "" "") |
a5c76ee6 ZW |
10320 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl")) |
10321 | (match_operand 2 "" "g,g"))) | |
10322 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10323 | (clobber (match_scratch:SI 4 "=l,l"))] | |
50d440bc | 10324 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10325 | || DEFAULT_ABI == ABI_DARWIN" |
b6c9286a | 10326 | { |
6a4cee5f | 10327 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10328 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f MM |
10329 | |
10330 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
a5c76ee6 | 10331 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10332 | |
a5c76ee6 ZW |
10333 | return "b%T1l"; |
10334 | } | |
10335 | [(set_attr "type" "jmpreg,jmpreg") | |
10336 | (set_attr "length" "4,8")]) | |
10337 | ||
10338 | (define_insn "*call_value_nonlocal_sysv" | |
10339 | [(set (match_operand 0 "" "") | |
10340 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10341 | (match_operand 2 "" "g,g"))) | |
10342 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10343 | (clobber (match_scratch:SI 4 "=l,l"))] | |
efdba735 SH |
10344 | "(DEFAULT_ABI == ABI_DARWIN |
10345 | || (DEFAULT_ABI == ABI_V4 | |
10346 | && (INTVAL (operands[3]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10347 | { |
10348 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10349 | output_asm_insn ("crxor 6,6,6", operands); | |
10350 | ||
10351 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10352 | output_asm_insn ("creqv 6,6,6", operands); | |
10353 | ||
c989f2f7 | 10354 | #if TARGET_MACHO |
efdba735 SH |
10355 | return output_call(insn, operands, 1, 3); |
10356 | #else | |
a5c76ee6 | 10357 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1"; |
6ae08853 | 10358 | #endif |
a5c76ee6 ZW |
10359 | } |
10360 | [(set_attr "type" "branch,branch") | |
10361 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
10362 | |
10363 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
10364 | (define_expand "untyped_call" |
10365 | [(parallel [(call (match_operand 0 "" "") | |
10366 | (const_int 0)) | |
10367 | (match_operand 1 "" "") | |
10368 | (match_operand 2 "" "")])] | |
10369 | "" | |
10370 | " | |
10371 | { | |
10372 | int i; | |
10373 | ||
7d70b8b2 | 10374 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
10375 | |
10376 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10377 | { | |
10378 | rtx set = XVECEXP (operands[2], 0, i); | |
10379 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10380 | } | |
10381 | ||
10382 | /* The optimizer does not know that the call sets the function value | |
10383 | registers we stored in the result block. We avoid problems by | |
10384 | claiming that all hard registers are used and clobbered at this | |
10385 | point. */ | |
10386 | emit_insn (gen_blockage ()); | |
10387 | ||
10388 | DONE; | |
10389 | }") | |
10390 | ||
5e1bf043 DJ |
10391 | ;; sibling call patterns |
10392 | (define_expand "sibcall" | |
10393 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) | |
10394 | (match_operand 1 "" "")) | |
10395 | (use (match_operand 2 "" "")) | |
fe352c29 | 10396 | (use (match_operand 3 "" "")) |
5e1bf043 DJ |
10397 | (return)])] |
10398 | "" | |
10399 | " | |
10400 | { | |
10401 | #if TARGET_MACHO | |
ab82a49f | 10402 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10403 | operands[0] = machopic_indirect_call_target (operands[0]); |
10404 | #endif | |
10405 | ||
37409796 NS |
10406 | gcc_assert (GET_CODE (operands[0]) == MEM); |
10407 | gcc_assert (GET_CODE (operands[1]) == CONST_INT); | |
5e1bf043 DJ |
10408 | |
10409 | operands[0] = XEXP (operands[0], 0); | |
fe352c29 | 10410 | operands[3] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10411 | |
10412 | }") | |
10413 | ||
10414 | ;; this and similar patterns must be marked as using LR, otherwise | |
10415 | ;; dataflow will try to delete the store into it. This is true | |
10416 | ;; even when the actual reg to jump to is in CTR, when LR was | |
10417 | ;; saved and restored around the PIC-setting BCL. | |
10418 | (define_insn "*sibcall_local32" | |
10419 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) | |
10420 | (match_operand 1 "" "g,g")) | |
10421 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10422 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10423 | (return)] |
10424 | "(INTVAL (operands[2]) & CALL_LONG) == 0" | |
10425 | "* | |
10426 | { | |
10427 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10428 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10429 | ||
10430 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10431 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10432 | ||
10433 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10434 | }" | |
10435 | [(set_attr "type" "branch") | |
10436 | (set_attr "length" "4,8")]) | |
10437 | ||
10438 | (define_insn "*sibcall_local64" | |
10439 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10440 | (match_operand 1 "" "g,g")) | |
10441 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10442 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10443 | (return)] |
10444 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10445 | "* | |
10446 | { | |
10447 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10448 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10449 | ||
10450 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10451 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10452 | ||
10453 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10454 | }" | |
10455 | [(set_attr "type" "branch") | |
10456 | (set_attr "length" "4,8")]) | |
10457 | ||
10458 | (define_insn "*sibcall_value_local32" | |
10459 | [(set (match_operand 0 "" "") | |
10460 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
10461 | (match_operand 2 "" "g,g"))) | |
10462 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10463 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10464 | (return)] |
10465 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10466 | "* | |
10467 | { | |
10468 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10469 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10470 | ||
10471 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10472 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10473 | ||
10474 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10475 | }" | |
10476 | [(set_attr "type" "branch") | |
10477 | (set_attr "length" "4,8")]) | |
10478 | ||
10479 | ||
10480 | (define_insn "*sibcall_value_local64" | |
10481 | [(set (match_operand 0 "" "") | |
10482 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
10483 | (match_operand 2 "" "g,g"))) | |
10484 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10485 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10486 | (return)] |
10487 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10488 | "* | |
10489 | { | |
10490 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10491 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10492 | ||
10493 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10494 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10495 | ||
10496 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10497 | }" | |
10498 | [(set_attr "type" "branch") | |
10499 | (set_attr "length" "4,8")]) | |
10500 | ||
10501 | (define_insn "*sibcall_nonlocal_aix32" | |
10502 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) | |
10503 | (match_operand 1 "" "g")) | |
10504 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10505 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 DJ |
10506 | (return)] |
10507 | "TARGET_32BIT | |
10508 | && DEFAULT_ABI == ABI_AIX | |
10509 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10510 | "b %z0" | |
10511 | [(set_attr "type" "branch") | |
10512 | (set_attr "length" "4")]) | |
10513 | ||
10514 | (define_insn "*sibcall_nonlocal_aix64" | |
10515 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) | |
10516 | (match_operand 1 "" "g")) | |
10517 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10518 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 | 10519 | (return)] |
6ae08853 | 10520 | "TARGET_64BIT |
5e1bf043 DJ |
10521 | && DEFAULT_ABI == ABI_AIX |
10522 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10523 | "b %z0" | |
10524 | [(set_attr "type" "branch") | |
10525 | (set_attr "length" "4")]) | |
10526 | ||
10527 | (define_insn "*sibcall_value_nonlocal_aix32" | |
10528 | [(set (match_operand 0 "" "") | |
10529 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) | |
10530 | (match_operand 2 "" "g"))) | |
10531 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10532 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 DJ |
10533 | (return)] |
10534 | "TARGET_32BIT | |
10535 | && DEFAULT_ABI == ABI_AIX | |
10536 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10537 | "b %z1" | |
10538 | [(set_attr "type" "branch") | |
10539 | (set_attr "length" "4")]) | |
10540 | ||
10541 | (define_insn "*sibcall_value_nonlocal_aix64" | |
10542 | [(set (match_operand 0 "" "") | |
10543 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) | |
10544 | (match_operand 2 "" "g"))) | |
10545 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10546 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 | 10547 | (return)] |
6ae08853 | 10548 | "TARGET_64BIT |
5e1bf043 DJ |
10549 | && DEFAULT_ABI == ABI_AIX |
10550 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10551 | "b %z1" | |
10552 | [(set_attr "type" "branch") | |
10553 | (set_attr "length" "4")]) | |
10554 | ||
10555 | (define_insn "*sibcall_nonlocal_sysv" | |
10556 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10557 | (match_operand 1 "" "")) | |
10558 | (use (match_operand 2 "immediate_operand" "O,n")) | |
fe352c29 | 10559 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10560 | (return)] |
10561 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10562 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10563 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
10564 | "* | |
10565 | { | |
10566 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10567 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10568 | ||
10569 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10570 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10571 | ||
10572 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\"; | |
10573 | }" | |
10574 | [(set_attr "type" "branch,branch") | |
10575 | (set_attr "length" "4,8")]) | |
10576 | ||
10577 | (define_expand "sibcall_value" | |
10578 | [(parallel [(set (match_operand 0 "register_operand" "") | |
10579 | (call (mem:SI (match_operand 1 "address_operand" "")) | |
10580 | (match_operand 2 "" ""))) | |
10581 | (use (match_operand 3 "" "")) | |
fe352c29 | 10582 | (use (match_operand 4 "" "")) |
5e1bf043 DJ |
10583 | (return)])] |
10584 | "" | |
10585 | " | |
10586 | { | |
10587 | #if TARGET_MACHO | |
ab82a49f | 10588 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10589 | operands[1] = machopic_indirect_call_target (operands[1]); |
10590 | #endif | |
10591 | ||
37409796 NS |
10592 | gcc_assert (GET_CODE (operands[1]) == MEM); |
10593 | gcc_assert (GET_CODE (operands[2]) == CONST_INT); | |
5e1bf043 DJ |
10594 | |
10595 | operands[1] = XEXP (operands[1], 0); | |
fe352c29 | 10596 | operands[4] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10597 | |
10598 | }") | |
10599 | ||
10600 | (define_insn "*sibcall_value_nonlocal_sysv" | |
10601 | [(set (match_operand 0 "" "") | |
10602 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10603 | (match_operand 2 "" ""))) | |
10604 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10605 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10606 | (return)] |
10607 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10608 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10609 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
10610 | "* | |
10611 | { | |
10612 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10613 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10614 | ||
10615 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10616 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10617 | ||
10618 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\"; | |
10619 | }" | |
10620 | [(set_attr "type" "branch,branch") | |
10621 | (set_attr "length" "4,8")]) | |
10622 | ||
10623 | (define_expand "sibcall_epilogue" | |
10624 | [(use (const_int 0))] | |
10625 | "TARGET_SCHED_PROLOG" | |
10626 | " | |
10627 | { | |
10628 | rs6000_emit_epilogue (TRUE); | |
10629 | DONE; | |
10630 | }") | |
10631 | ||
e6f948e3 RK |
10632 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and |
10633 | ;; all of memory. This blocks insns from being moved across this point. | |
10634 | ||
10635 | (define_insn "blockage" | |
615158e2 | 10636 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)] |
e6f948e3 RK |
10637 | "" |
10638 | "") | |
1fd4e8c1 RK |
10639 | \f |
10640 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 10641 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
10642 | ;; |
10643 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
10644 | ;; insns, and branches. We store the operands of compares until we see | |
10645 | ;; how it is used. | |
10646 | (define_expand "cmpsi" | |
10647 | [(set (cc0) | |
cd2b37d9 | 10648 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10649 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
10650 | "" | |
10651 | " | |
10652 | { | |
10653 | /* Take care of the possibility that operands[1] might be negative but | |
10654 | this might be a logical operation. That insn doesn't exist. */ | |
10655 | if (GET_CODE (operands[1]) == CONST_INT | |
10656 | && INTVAL (operands[1]) < 0) | |
10657 | operands[1] = force_reg (SImode, operands[1]); | |
10658 | ||
10659 | rs6000_compare_op0 = operands[0]; | |
10660 | rs6000_compare_op1 = operands[1]; | |
10661 | rs6000_compare_fp_p = 0; | |
10662 | DONE; | |
10663 | }") | |
10664 | ||
266eb58a DE |
10665 | (define_expand "cmpdi" |
10666 | [(set (cc0) | |
10667 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
10668 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
10669 | "TARGET_POWERPC64" | |
10670 | " | |
10671 | { | |
10672 | /* Take care of the possibility that operands[1] might be negative but | |
10673 | this might be a logical operation. That insn doesn't exist. */ | |
10674 | if (GET_CODE (operands[1]) == CONST_INT | |
10675 | && INTVAL (operands[1]) < 0) | |
10676 | operands[1] = force_reg (DImode, operands[1]); | |
10677 | ||
10678 | rs6000_compare_op0 = operands[0]; | |
10679 | rs6000_compare_op1 = operands[1]; | |
10680 | rs6000_compare_fp_p = 0; | |
10681 | DONE; | |
10682 | }") | |
10683 | ||
1fd4e8c1 | 10684 | (define_expand "cmpsf" |
cd2b37d9 RK |
10685 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
10686 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 10687 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10688 | " |
10689 | { | |
10690 | rs6000_compare_op0 = operands[0]; | |
10691 | rs6000_compare_op1 = operands[1]; | |
10692 | rs6000_compare_fp_p = 1; | |
10693 | DONE; | |
10694 | }") | |
10695 | ||
10696 | (define_expand "cmpdf" | |
cd2b37d9 RK |
10697 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
10698 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
7a2f7870 | 10699 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" |
1fd4e8c1 RK |
10700 | " |
10701 | { | |
10702 | rs6000_compare_op0 = operands[0]; | |
10703 | rs6000_compare_op1 = operands[1]; | |
10704 | rs6000_compare_fp_p = 1; | |
10705 | DONE; | |
10706 | }") | |
10707 | ||
d6f99ca4 | 10708 | (define_expand "cmptf" |
e7a4130e DE |
10709 | [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "") |
10710 | (match_operand:TF 1 "gpc_reg_operand" "")))] | |
39e63627 GK |
10711 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
10712 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
d6f99ca4 DE |
10713 | " |
10714 | { | |
10715 | rs6000_compare_op0 = operands[0]; | |
10716 | rs6000_compare_op1 = operands[1]; | |
10717 | rs6000_compare_fp_p = 1; | |
10718 | DONE; | |
10719 | }") | |
10720 | ||
1fd4e8c1 | 10721 | (define_expand "beq" |
39a10a29 | 10722 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10723 | "" |
39a10a29 | 10724 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10725 | |
10726 | (define_expand "bne" | |
39a10a29 | 10727 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10728 | "" |
39a10a29 | 10729 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 10730 | |
39a10a29 GK |
10731 | (define_expand "bge" |
10732 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10733 | "" |
39a10a29 | 10734 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
10735 | |
10736 | (define_expand "bgt" | |
39a10a29 | 10737 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10738 | "" |
39a10a29 | 10739 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
10740 | |
10741 | (define_expand "ble" | |
39a10a29 | 10742 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10743 | "" |
39a10a29 | 10744 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 10745 | |
39a10a29 GK |
10746 | (define_expand "blt" |
10747 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10748 | "" |
39a10a29 | 10749 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 10750 | |
39a10a29 GK |
10751 | (define_expand "bgeu" |
10752 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10753 | "" |
39a10a29 | 10754 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 10755 | |
39a10a29 GK |
10756 | (define_expand "bgtu" |
10757 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10758 | "" |
39a10a29 | 10759 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 10760 | |
39a10a29 GK |
10761 | (define_expand "bleu" |
10762 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10763 | "" |
39a10a29 | 10764 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 10765 | |
39a10a29 GK |
10766 | (define_expand "bltu" |
10767 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10768 | "" |
39a10a29 | 10769 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 10770 | |
1c882ea4 | 10771 | (define_expand "bunordered" |
39a10a29 | 10772 | [(use (match_operand 0 "" ""))] |
7a1bf2f9 | 10773 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
39a10a29 | 10774 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
10775 | |
10776 | (define_expand "bordered" | |
39a10a29 | 10777 | [(use (match_operand 0 "" ""))] |
7a1bf2f9 | 10778 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
39a10a29 | 10779 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
10780 | |
10781 | (define_expand "buneq" | |
39a10a29 | 10782 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10783 | "" |
39a10a29 | 10784 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
10785 | |
10786 | (define_expand "bunge" | |
39a10a29 | 10787 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10788 | "" |
39a10a29 | 10789 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
10790 | |
10791 | (define_expand "bungt" | |
39a10a29 | 10792 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10793 | "" |
39a10a29 | 10794 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
10795 | |
10796 | (define_expand "bunle" | |
39a10a29 | 10797 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10798 | "" |
39a10a29 | 10799 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
10800 | |
10801 | (define_expand "bunlt" | |
39a10a29 | 10802 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10803 | "" |
39a10a29 | 10804 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
10805 | |
10806 | (define_expand "bltgt" | |
39a10a29 | 10807 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10808 | "" |
39a10a29 | 10809 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 10810 | |
1fd4e8c1 RK |
10811 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
10812 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
10813 | ;; with an scc insns. However, due to the order that combine see the | |
10814 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
10815 | ;; the cases we don't want to handle. | |
10816 | (define_expand "seq" | |
39a10a29 | 10817 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10818 | "" |
39a10a29 | 10819 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10820 | |
10821 | (define_expand "sne" | |
39a10a29 | 10822 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10823 | "" |
10824 | " | |
6ae08853 | 10825 | { |
39a10a29 | 10826 | if (! rs6000_compare_fp_p) |
1fd4e8c1 RK |
10827 | FAIL; |
10828 | ||
6ae08853 | 10829 | rs6000_emit_sCOND (NE, operands[0]); |
39a10a29 | 10830 | DONE; |
1fd4e8c1 RK |
10831 | }") |
10832 | ||
b7053a3f GK |
10833 | ;; A >= 0 is best done the portable way for A an integer. |
10834 | (define_expand "sge" | |
39a10a29 | 10835 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10836 | "" |
10837 | " | |
5638268e | 10838 | { |
e56d7409 | 10839 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
1fd4e8c1 RK |
10840 | FAIL; |
10841 | ||
b7053a3f | 10842 | rs6000_emit_sCOND (GE, operands[0]); |
39a10a29 | 10843 | DONE; |
1fd4e8c1 RK |
10844 | }") |
10845 | ||
b7053a3f GK |
10846 | ;; A > 0 is best done using the portable sequence, so fail in that case. |
10847 | (define_expand "sgt" | |
39a10a29 | 10848 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10849 | "" |
10850 | " | |
5638268e | 10851 | { |
e56d7409 | 10852 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
1fd4e8c1 RK |
10853 | FAIL; |
10854 | ||
6ae08853 | 10855 | rs6000_emit_sCOND (GT, operands[0]); |
39a10a29 | 10856 | DONE; |
1fd4e8c1 RK |
10857 | }") |
10858 | ||
b7053a3f GK |
10859 | ;; A <= 0 is best done the portable way for A an integer. |
10860 | (define_expand "sle" | |
39a10a29 | 10861 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10862 | "" |
5638268e DE |
10863 | " |
10864 | { | |
e56d7409 | 10865 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
5638268e DE |
10866 | FAIL; |
10867 | ||
6ae08853 | 10868 | rs6000_emit_sCOND (LE, operands[0]); |
5638268e DE |
10869 | DONE; |
10870 | }") | |
1fd4e8c1 | 10871 | |
b7053a3f GK |
10872 | ;; A < 0 is best done in the portable way for A an integer. |
10873 | (define_expand "slt" | |
39a10a29 | 10874 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10875 | "" |
10876 | " | |
5638268e | 10877 | { |
e56d7409 | 10878 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
1fd4e8c1 RK |
10879 | FAIL; |
10880 | ||
6ae08853 | 10881 | rs6000_emit_sCOND (LT, operands[0]); |
39a10a29 | 10882 | DONE; |
1fd4e8c1 RK |
10883 | }") |
10884 | ||
b7053a3f GK |
10885 | (define_expand "sgeu" |
10886 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10887 | "" | |
10888 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") | |
10889 | ||
1fd4e8c1 | 10890 | (define_expand "sgtu" |
39a10a29 | 10891 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10892 | "" |
39a10a29 | 10893 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 10894 | |
b7053a3f GK |
10895 | (define_expand "sleu" |
10896 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10897 | "" | |
10898 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") | |
10899 | ||
1fd4e8c1 | 10900 | (define_expand "sltu" |
39a10a29 | 10901 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10902 | "" |
39a10a29 | 10903 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 10904 | |
b7053a3f | 10905 | (define_expand "sunordered" |
39a10a29 | 10906 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
7836a61f | 10907 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
b7053a3f | 10908 | "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }") |
1fd4e8c1 | 10909 | |
b7053a3f | 10910 | (define_expand "sordered" |
39a10a29 | 10911 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
7836a61f | 10912 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
b7053a3f GK |
10913 | "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }") |
10914 | ||
10915 | (define_expand "suneq" | |
10916 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10917 | "" | |
10918 | "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }") | |
10919 | ||
10920 | (define_expand "sunge" | |
10921 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10922 | "" | |
10923 | "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }") | |
10924 | ||
10925 | (define_expand "sungt" | |
10926 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10927 | "" | |
10928 | "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }") | |
10929 | ||
10930 | (define_expand "sunle" | |
10931 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10932 | "" | |
10933 | "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }") | |
10934 | ||
10935 | (define_expand "sunlt" | |
10936 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10937 | "" | |
10938 | "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }") | |
10939 | ||
10940 | (define_expand "sltgt" | |
10941 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10942 | "" | |
10943 | "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }") | |
10944 | ||
1fd4e8c1 RK |
10945 | \f |
10946 | ;; Here are the actual compare insns. | |
acad7ed3 | 10947 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 10948 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 10949 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
10950 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
10951 | "" | |
7f340546 | 10952 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
b54cf83a | 10953 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 10954 | |
acad7ed3 | 10955 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
10956 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
10957 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
10958 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
10959 | "TARGET_POWERPC64" | |
10960 | "cmpd%I2 %0,%1,%2" | |
b54cf83a | 10961 | [(set_attr "type" "cmp")]) |
266eb58a | 10962 | |
f357808b RK |
10963 | ;; If we are comparing a register for equality with a large constant, |
10964 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
10965 | ;; register for the result of the XOR. | |
10966 | ||
10967 | (define_split | |
10968 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 10969 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 10970 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 10971 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
10972 | "find_single_use (operands[0], insn, 0) |
10973 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
10974 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
10975 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
10976 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
10977 | " | |
10978 | { | |
10979 | /* Get the constant we are comparing against, C, and see what it looks like | |
10980 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
10981 | with C to get the sign-extended value. */ | |
10982 | ||
5f59ecb7 | 10983 | HOST_WIDE_INT c = INTVAL (operands[2]); |
a65c591c | 10984 | HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; |
5f59ecb7 | 10985 | HOST_WIDE_INT xorv = c ^ sextc; |
f357808b | 10986 | |
89e9f3a8 MM |
10987 | operands[4] = GEN_INT (xorv); |
10988 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
10989 | }") |
10990 | ||
acad7ed3 | 10991 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 10992 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 10993 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 10994 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 10995 | "" |
e2c953b6 | 10996 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
b54cf83a | 10997 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 10998 | |
acad7ed3 | 10999 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
11000 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
11001 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 11002 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 11003 | "" |
e2c953b6 | 11004 | "cmpld%I2 %0,%1,%b2" |
b54cf83a | 11005 | [(set_attr "type" "cmp")]) |
266eb58a | 11006 | |
1fd4e8c1 RK |
11007 | ;; The following two insns don't exist as single insns, but if we provide |
11008 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
11009 | ;; of the required delay between a compare and branch. We generate code for | |
11010 | ;; them by splitting. | |
11011 | ||
11012 | (define_insn "" | |
11013 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11014 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11015 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 11016 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11017 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11018 | "" | |
baf97f86 RK |
11019 | "#" |
11020 | [(set_attr "length" "8")]) | |
7e69e155 | 11021 | |
1fd4e8c1 RK |
11022 | (define_insn "" |
11023 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11024 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11025 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 11026 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11027 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11028 | "" | |
baf97f86 RK |
11029 | "#" |
11030 | [(set_attr "length" "8")]) | |
7e69e155 | 11031 | |
1fd4e8c1 RK |
11032 | (define_split |
11033 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 11034 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11035 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 11036 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11037 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11038 | "" | |
11039 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
11040 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11041 | ||
11042 | (define_split | |
11043 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 11044 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11045 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 11046 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11047 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11048 | "" | |
11049 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
11050 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11051 | ||
acad7ed3 | 11052 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 11053 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11054 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
11055 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11056 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11057 | "fcmpu %0,%1,%2" |
11058 | [(set_attr "type" "fpcompare")]) | |
11059 | ||
acad7ed3 | 11060 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 11061 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11062 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
11063 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11064 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11065 | "fcmpu %0,%1,%2" |
11066 | [(set_attr "type" "fpcompare")]) | |
d6f99ca4 DE |
11067 | |
11068 | ;; Only need to compare second words if first words equal | |
11069 | (define_insn "*cmptf_internal1" | |
11070 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
11071 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
11072 | (match_operand:TF 2 "gpc_reg_operand" "f")))] | |
de17c25f | 11073 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT |
39e63627 | 11074 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" |
ecb62ae7 | 11075 | "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" |
d6f99ca4 DE |
11076 | [(set_attr "type" "fpcompare") |
11077 | (set_attr "length" "12")]) | |
de17c25f DE |
11078 | |
11079 | (define_insn_and_split "*cmptf_internal2" | |
11080 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
11081 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
11082 | (match_operand:TF 2 "gpc_reg_operand" "f"))) | |
11083 | (clobber (match_scratch:DF 3 "=f")) | |
11084 | (clobber (match_scratch:DF 4 "=f")) | |
11085 | (clobber (match_scratch:DF 5 "=f")) | |
11086 | (clobber (match_scratch:DF 6 "=f")) | |
11087 | (clobber (match_scratch:DF 7 "=f")) | |
11088 | (clobber (match_scratch:DF 8 "=f")) | |
11089 | (clobber (match_scratch:DF 9 "=f")) | |
11090 | (clobber (match_scratch:DF 10 "=f"))] | |
11091 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT | |
11092 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
11093 | "#" | |
11094 | "&& reload_completed" | |
11095 | [(set (match_dup 3) (match_dup 13)) | |
11096 | (set (match_dup 4) (match_dup 14)) | |
11097 | (set (match_dup 9) (abs:DF (match_dup 5))) | |
11098 | (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3))) | |
11099 | (set (pc) (if_then_else (ne (match_dup 0) (const_int 0)) | |
11100 | (label_ref (match_dup 11)) | |
11101 | (pc))) | |
11102 | (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7))) | |
11103 | (set (pc) (label_ref (match_dup 12))) | |
11104 | (match_dup 11) | |
11105 | (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7))) | |
11106 | (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8))) | |
11107 | (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9))) | |
11108 | (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4))) | |
11109 | (match_dup 12)] | |
11110 | { | |
11111 | REAL_VALUE_TYPE rv; | |
11112 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; | |
11113 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); | |
11114 | ||
11115 | operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word); | |
11116 | operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word); | |
11117 | operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word); | |
11118 | operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word); | |
11119 | operands[11] = gen_label_rtx (); | |
11120 | operands[12] = gen_label_rtx (); | |
11121 | real_inf (&rv); | |
11122 | operands[13] = force_const_mem (DFmode, | |
11123 | CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode)); | |
11124 | operands[14] = force_const_mem (DFmode, | |
11125 | CONST_DOUBLE_FROM_REAL_VALUE (dconst0, | |
11126 | DFmode)); | |
11127 | if (TARGET_TOC) | |
11128 | { | |
11129 | operands[13] = gen_const_mem (DFmode, | |
11130 | create_TOC_reference (XEXP (operands[13], 0))); | |
11131 | operands[14] = gen_const_mem (DFmode, | |
11132 | create_TOC_reference (XEXP (operands[14], 0))); | |
11133 | set_mem_alias_set (operands[13], get_TOC_alias_set ()); | |
11134 | set_mem_alias_set (operands[14], get_TOC_alias_set ()); | |
11135 | } | |
11136 | }) | |
1fd4e8c1 RK |
11137 | \f |
11138 | ;; Now we have the scc insns. We can do some combinations because of the | |
11139 | ;; way the machine works. | |
11140 | ;; | |
11141 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
11142 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
11143 | ;; cases the insns below which don't use an intermediate CR field will | |
11144 | ;; be used instead. | |
1fd4e8c1 | 11145 | (define_insn "" |
cd2b37d9 | 11146 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11147 | (match_operator:SI 1 "scc_comparison_operator" |
11148 | [(match_operand 2 "cc_reg_operand" "y") | |
11149 | (const_int 0)]))] | |
11150 | "" | |
2c4a9cff DE |
11151 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
11152 | [(set (attr "type") | |
11153 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11154 | (const_string "mfcrf") | |
11155 | ] | |
11156 | (const_string "mfcr"))) | |
c1618c0c | 11157 | (set_attr "length" "8")]) |
1fd4e8c1 | 11158 | |
423c1189 | 11159 | ;; Same as above, but get the GT bit. |
64022b5d | 11160 | (define_insn "move_from_CR_gt_bit" |
423c1189 | 11161 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
64022b5d | 11162 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))] |
423c1189 | 11163 | "TARGET_E500" |
64022b5d | 11164 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31" |
423c1189 | 11165 | [(set_attr "type" "mfcr") |
c1618c0c | 11166 | (set_attr "length" "8")]) |
423c1189 | 11167 | |
a3170dc6 AH |
11168 | ;; Same as above, but get the OV/ORDERED bit. |
11169 | (define_insn "move_from_CR_ov_bit" | |
11170 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
615158e2 | 11171 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))] |
a3170dc6 | 11172 | "TARGET_ISEL" |
b7053a3f | 11173 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1" |
b54cf83a | 11174 | [(set_attr "type" "mfcr") |
c1618c0c | 11175 | (set_attr "length" "8")]) |
a3170dc6 | 11176 | |
1fd4e8c1 | 11177 | (define_insn "" |
9ebbca7d GK |
11178 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
11179 | (match_operator:DI 1 "scc_comparison_operator" | |
11180 | [(match_operand 2 "cc_reg_operand" "y") | |
11181 | (const_int 0)]))] | |
11182 | "TARGET_POWERPC64" | |
2c4a9cff DE |
11183 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
11184 | [(set (attr "type") | |
11185 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11186 | (const_string "mfcrf") | |
11187 | ] | |
11188 | (const_string "mfcr"))) | |
c1618c0c | 11189 | (set_attr "length" "8")]) |
9ebbca7d GK |
11190 | |
11191 | (define_insn "" | |
11192 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 11193 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 11194 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
11195 | (const_int 0)]) |
11196 | (const_int 0))) | |
9ebbca7d | 11197 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11198 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
4b8a63d6 | 11199 | "TARGET_32BIT" |
9ebbca7d | 11200 | "@ |
2c4a9cff | 11201 | mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1 |
9ebbca7d | 11202 | #" |
b19003d8 | 11203 | [(set_attr "type" "delayed_compare") |
c1618c0c | 11204 | (set_attr "length" "8,16")]) |
9ebbca7d GK |
11205 | |
11206 | (define_split | |
11207 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11208 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
11209 | [(match_operand 2 "cc_reg_operand" "") | |
11210 | (const_int 0)]) | |
11211 | (const_int 0))) | |
11212 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
11213 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
4b8a63d6 | 11214 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11215 | [(set (match_dup 3) |
11216 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
11217 | (set (match_dup 0) | |
11218 | (compare:CC (match_dup 3) | |
11219 | (const_int 0)))] | |
11220 | "") | |
1fd4e8c1 RK |
11221 | |
11222 | (define_insn "" | |
cd2b37d9 | 11223 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11224 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
11225 | [(match_operand 2 "cc_reg_operand" "y") | |
11226 | (const_int 0)]) | |
11227 | (match_operand:SI 3 "const_int_operand" "n")))] | |
11228 | "" | |
11229 | "* | |
11230 | { | |
11231 | int is_bit = ccr_bit (operands[1], 1); | |
11232 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11233 | int count; | |
11234 | ||
11235 | if (is_bit >= put_bit) | |
11236 | count = is_bit - put_bit; | |
11237 | else | |
11238 | count = 32 - (put_bit - is_bit); | |
11239 | ||
89e9f3a8 MM |
11240 | operands[4] = GEN_INT (count); |
11241 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 11242 | |
2c4a9cff | 11243 | return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 | 11244 | }" |
2c4a9cff DE |
11245 | [(set (attr "type") |
11246 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11247 | (const_string "mfcrf") | |
11248 | ] | |
11249 | (const_string "mfcr"))) | |
c1618c0c | 11250 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
11251 | |
11252 | (define_insn "" | |
9ebbca7d | 11253 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11254 | (compare:CC |
11255 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 11256 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 11257 | (const_int 0)]) |
9ebbca7d | 11258 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 11259 | (const_int 0))) |
9ebbca7d | 11260 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11261 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
11262 | (match_dup 3)))] | |
ce71f754 | 11263 | "" |
1fd4e8c1 RK |
11264 | "* |
11265 | { | |
11266 | int is_bit = ccr_bit (operands[1], 1); | |
11267 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11268 | int count; | |
11269 | ||
9ebbca7d GK |
11270 | /* Force split for non-cc0 compare. */ |
11271 | if (which_alternative == 1) | |
11272 | return \"#\"; | |
11273 | ||
1fd4e8c1 RK |
11274 | if (is_bit >= put_bit) |
11275 | count = is_bit - put_bit; | |
11276 | else | |
11277 | count = 32 - (put_bit - is_bit); | |
11278 | ||
89e9f3a8 MM |
11279 | operands[5] = GEN_INT (count); |
11280 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 11281 | |
2c4a9cff | 11282 | return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 11283 | }" |
b19003d8 | 11284 | [(set_attr "type" "delayed_compare") |
c1618c0c | 11285 | (set_attr "length" "8,16")]) |
9ebbca7d GK |
11286 | |
11287 | (define_split | |
11288 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11289 | (compare:CC | |
11290 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
11291 | [(match_operand 2 "cc_reg_operand" "") | |
11292 | (const_int 0)]) | |
11293 | (match_operand:SI 3 "const_int_operand" "")) | |
11294 | (const_int 0))) | |
11295 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
11296 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11297 | (match_dup 3)))] | |
ce71f754 | 11298 | "reload_completed" |
9ebbca7d GK |
11299 | [(set (match_dup 4) |
11300 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11301 | (match_dup 3))) | |
11302 | (set (match_dup 0) | |
11303 | (compare:CC (match_dup 4) | |
11304 | (const_int 0)))] | |
11305 | "") | |
1fd4e8c1 | 11306 | |
c5defebb RK |
11307 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
11308 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
11309 | ||
11310 | (define_peephole | |
cd2b37d9 | 11311 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
11312 | (match_operator:SI 1 "scc_comparison_operator" |
11313 | [(match_operand 2 "cc_reg_operand" "y") | |
11314 | (const_int 0)])) | |
cd2b37d9 | 11315 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
11316 | (match_operator:SI 4 "scc_comparison_operator" |
11317 | [(match_operand 5 "cc_reg_operand" "y") | |
11318 | (const_int 0)]))] | |
309323c2 | 11319 | "REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11320 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11321 | [(set_attr "type" "mfcr") |
c1618c0c | 11322 | (set_attr "length" "12")]) |
c5defebb | 11323 | |
9ebbca7d GK |
11324 | (define_peephole |
11325 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11326 | (match_operator:DI 1 "scc_comparison_operator" | |
11327 | [(match_operand 2 "cc_reg_operand" "y") | |
11328 | (const_int 0)])) | |
11329 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
11330 | (match_operator:DI 4 "scc_comparison_operator" | |
11331 | [(match_operand 5 "cc_reg_operand" "y") | |
11332 | (const_int 0)]))] | |
309323c2 | 11333 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11334 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11335 | [(set_attr "type" "mfcr") |
c1618c0c | 11336 | (set_attr "length" "12")]) |
9ebbca7d | 11337 | |
1fd4e8c1 RK |
11338 | ;; There are some scc insns that can be done directly, without a compare. |
11339 | ;; These are faster because they don't involve the communications between | |
11340 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
11341 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
11342 | ;; | |
11343 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
11344 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
11345 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
11346 | ;; cases where it is no more expensive than (neg (scc ..)). | |
11347 | ||
11348 | ;; Have reload force a constant into a register for the simple insns that | |
11349 | ;; otherwise won't accept constants. We do this because it is faster than | |
11350 | ;; the cmp/mfcr sequence we would otherwise generate. | |
11351 | ||
11352 | (define_insn "" | |
cd2b37d9 RK |
11353 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
11354 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 11355 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 11356 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
683bdff7 | 11357 | "TARGET_32BIT" |
1fd4e8c1 | 11358 | "@ |
ca7f5001 | 11359 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 11360 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
11361 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
11362 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
11363 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
943c15ed DE |
11364 | [(set_attr "type" "three,two,three,three,three") |
11365 | (set_attr "length" "12,8,12,12,12")]) | |
1fd4e8c1 | 11366 | |
a260abc9 DE |
11367 | (define_insn "" |
11368 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
11369 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
11370 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
11371 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
683bdff7 | 11372 | "TARGET_64BIT" |
a260abc9 DE |
11373 | "@ |
11374 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11375 | subfic %3,%1,0\;adde %0,%3,%1 | |
11376 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11377 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11378 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
943c15ed DE |
11379 | [(set_attr "type" "three,two,three,three,three") |
11380 | (set_attr "length" "12,8,12,12,12")]) | |
a260abc9 | 11381 | |
1fd4e8c1 | 11382 | (define_insn "" |
9ebbca7d | 11383 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11384 | (compare:CC |
9ebbca7d GK |
11385 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11386 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 11387 | (const_int 0))) |
9ebbca7d | 11388 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 11389 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11390 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
683bdff7 | 11391 | "TARGET_32BIT" |
1fd4e8c1 | 11392 | "@ |
ca7f5001 RK |
11393 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11394 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
11395 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
11396 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
11397 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11398 | # | |
11399 | # | |
11400 | # | |
11401 | # | |
11402 | #" | |
b19003d8 | 11403 | [(set_attr "type" "compare") |
9ebbca7d GK |
11404 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11405 | ||
11406 | (define_split | |
11407 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11408 | (compare:CC | |
11409 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11410 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11411 | (const_int 0))) | |
11412 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11413 | (eq:SI (match_dup 1) (match_dup 2))) | |
11414 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 11415 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11416 | [(parallel [(set (match_dup 0) |
11417 | (eq:SI (match_dup 1) (match_dup 2))) | |
11418 | (clobber (match_dup 3))]) | |
11419 | (set (match_dup 4) | |
11420 | (compare:CC (match_dup 0) | |
11421 | (const_int 0)))] | |
11422 | "") | |
b19003d8 | 11423 | |
a260abc9 | 11424 | (define_insn "" |
9ebbca7d | 11425 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 11426 | (compare:CC |
9ebbca7d GK |
11427 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11428 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 11429 | (const_int 0))) |
9ebbca7d | 11430 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 11431 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11432 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
683bdff7 | 11433 | "TARGET_64BIT" |
a260abc9 DE |
11434 | "@ |
11435 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11436 | subfic %3,%1,0\;adde. %0,%3,%1 | |
11437 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11438 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
11439 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
11440 | # | |
11441 | # | |
11442 | # | |
11443 | # | |
11444 | #" | |
a260abc9 | 11445 | [(set_attr "type" "compare") |
9ebbca7d GK |
11446 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11447 | ||
11448 | (define_split | |
11449 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11450 | (compare:CC | |
11451 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11452 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
11453 | (const_int 0))) | |
11454 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11455 | (eq:DI (match_dup 1) (match_dup 2))) | |
11456 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11457 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11458 | [(parallel [(set (match_dup 0) |
11459 | (eq:DI (match_dup 1) (match_dup 2))) | |
11460 | (clobber (match_dup 3))]) | |
11461 | (set (match_dup 4) | |
11462 | (compare:CC (match_dup 0) | |
11463 | (const_int 0)))] | |
11464 | "") | |
a260abc9 | 11465 | |
b19003d8 RK |
11466 | ;; We have insns of the form shown by the first define_insn below. If |
11467 | ;; there is something inside the comparison operation, we must split it. | |
11468 | (define_split | |
11469 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
11470 | (plus:SI (match_operator 1 "comparison_operator" | |
11471 | [(match_operand:SI 2 "" "") | |
11472 | (match_operand:SI 3 | |
11473 | "reg_or_cint_operand" "")]) | |
11474 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
11475 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
11476 | "! gpc_reg_operand (operands[2], SImode)" | |
11477 | [(set (match_dup 5) (match_dup 2)) | |
11478 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
11479 | (match_dup 4)))]) | |
1fd4e8c1 RK |
11480 | |
11481 | (define_insn "" | |
5276df18 | 11482 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") |
cd2b37d9 | 11483 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11484 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
5276df18 | 11485 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] |
683bdff7 | 11486 | "TARGET_32BIT" |
1fd4e8c1 | 11487 | "@ |
5276df18 DE |
11488 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11489 | {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 | |
11490 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11491 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11492 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" | |
943c15ed DE |
11493 | [(set_attr "type" "three,two,three,three,three") |
11494 | (set_attr "length" "12,8,12,12,12")]) | |
1fd4e8c1 RK |
11495 | |
11496 | (define_insn "" | |
9ebbca7d | 11497 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11498 | (compare:CC |
1fd4e8c1 | 11499 | (plus:SI |
9ebbca7d GK |
11500 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11501 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11502 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11503 | (const_int 0))) |
9ebbca7d | 11504 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
683bdff7 | 11505 | "TARGET_32BIT" |
1fd4e8c1 | 11506 | "@ |
ca7f5001 | 11507 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 11508 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
11509 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11510 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
11511 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11512 | # | |
11513 | # | |
11514 | # | |
11515 | # | |
11516 | #" | |
b19003d8 | 11517 | [(set_attr "type" "compare") |
9ebbca7d GK |
11518 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11519 | ||
11520 | (define_split | |
11521 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11522 | (compare:CC | |
11523 | (plus:SI | |
11524 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11525 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11526 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11527 | (const_int 0))) | |
11528 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11529 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11530 | [(set (match_dup 4) |
11531 | (plus:SI (eq:SI (match_dup 1) | |
11532 | (match_dup 2)) | |
11533 | (match_dup 3))) | |
11534 | (set (match_dup 0) | |
11535 | (compare:CC (match_dup 4) | |
11536 | (const_int 0)))] | |
11537 | "") | |
1fd4e8c1 RK |
11538 | |
11539 | (define_insn "" | |
0387639b | 11540 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11541 | (compare:CC |
1fd4e8c1 | 11542 | (plus:SI |
9ebbca7d GK |
11543 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11544 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11545 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11546 | (const_int 0))) |
0387639b DE |
11547 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") |
11548 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 11549 | "TARGET_32BIT" |
1fd4e8c1 | 11550 | "@ |
0387639b DE |
11551 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11552 | {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 | |
11553 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11554 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11555 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11556 | # |
11557 | # | |
11558 | # | |
11559 | # | |
11560 | #" | |
11561 | [(set_attr "type" "compare") | |
11562 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
11563 | ||
11564 | (define_split | |
0387639b | 11565 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11566 | (compare:CC |
11567 | (plus:SI | |
11568 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11569 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11570 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11571 | (const_int 0))) | |
11572 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
0387639b | 11573 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 11574 | "TARGET_32BIT && reload_completed" |
0387639b | 11575 | [(set (match_dup 0) |
9ebbca7d | 11576 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
0387639b | 11577 | (set (match_dup 4) |
9ebbca7d GK |
11578 | (compare:CC (match_dup 0) |
11579 | (const_int 0)))] | |
11580 | "") | |
11581 | ||
1fd4e8c1 | 11582 | (define_insn "" |
cd2b37d9 | 11583 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 11584 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11585 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
683bdff7 | 11586 | "TARGET_32BIT" |
1fd4e8c1 | 11587 | "@ |
ca7f5001 RK |
11588 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11589 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
11590 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11591 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11592 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
943c15ed DE |
11593 | [(set_attr "type" "three,two,three,three,three") |
11594 | (set_attr "length" "12,8,12,12,12")]) | |
1fd4e8c1 | 11595 | |
ea9be077 MM |
11596 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
11597 | ;; since it nabs/sr is just as fast. | |
463b558b | 11598 | (define_insn "*ne0" |
b4e95693 | 11599 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
11600 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
11601 | (const_int 31))) | |
11602 | (clobber (match_scratch:SI 2 "=&r"))] | |
683bdff7 | 11603 | "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL" |
ea9be077 | 11604 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
943c15ed DE |
11605 | [(set_attr "type" "two") |
11606 | (set_attr "length" "8")]) | |
ea9be077 | 11607 | |
a260abc9 DE |
11608 | (define_insn "" |
11609 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11610 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11611 | (const_int 63))) | |
11612 | (clobber (match_scratch:DI 2 "=&r"))] | |
683bdff7 | 11613 | "TARGET_64BIT" |
a260abc9 | 11614 | "addic %2,%1,-1\;subfe %0,%2,%1" |
943c15ed DE |
11615 | [(set_attr "type" "two") |
11616 | (set_attr "length" "8")]) | |
a260abc9 | 11617 | |
1fd4e8c1 RK |
11618 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
11619 | (define_insn "" | |
cd2b37d9 | 11620 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 11621 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 11622 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11623 | (const_int 31)) |
cd2b37d9 | 11624 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11625 | (clobber (match_scratch:SI 3 "=&r"))] |
683bdff7 | 11626 | "TARGET_32BIT" |
ca7f5001 | 11627 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
943c15ed DE |
11628 | [(set_attr "type" "two") |
11629 | (set_attr "length" "8")]) | |
1fd4e8c1 | 11630 | |
a260abc9 DE |
11631 | (define_insn "" |
11632 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11633 | (plus:DI (lshiftrt:DI | |
11634 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11635 | (const_int 63)) | |
11636 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11637 | (clobber (match_scratch:DI 3 "=&r"))] | |
683bdff7 | 11638 | "TARGET_64BIT" |
a260abc9 | 11639 | "addic %3,%1,-1\;addze %0,%2" |
943c15ed DE |
11640 | [(set_attr "type" "two") |
11641 | (set_attr "length" "8")]) | |
a260abc9 | 11642 | |
1fd4e8c1 | 11643 | (define_insn "" |
9ebbca7d | 11644 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11645 | (compare:CC |
11646 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11647 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11648 | (const_int 31)) |
9ebbca7d | 11649 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11650 | (const_int 0))) |
889b90a1 GK |
11651 | (clobber (match_scratch:SI 3 "=&r,&r")) |
11652 | (clobber (match_scratch:SI 4 "=X,&r"))] | |
683bdff7 | 11653 | "TARGET_32BIT" |
9ebbca7d GK |
11654 | "@ |
11655 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
11656 | #" | |
b19003d8 | 11657 | [(set_attr "type" "compare") |
9ebbca7d GK |
11658 | (set_attr "length" "8,12")]) |
11659 | ||
11660 | (define_split | |
11661 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11662 | (compare:CC | |
11663 | (plus:SI (lshiftrt:SI | |
11664 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11665 | (const_int 31)) | |
11666 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11667 | (const_int 0))) | |
889b90a1 GK |
11668 | (clobber (match_scratch:SI 3 "")) |
11669 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11670 | "TARGET_32BIT && reload_completed" |
889b90a1 | 11671 | [(parallel [(set (match_dup 3) |
ce71f754 AM |
11672 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) |
11673 | (const_int 31)) | |
11674 | (match_dup 2))) | |
889b90a1 | 11675 | (clobber (match_dup 4))]) |
9ebbca7d GK |
11676 | (set (match_dup 0) |
11677 | (compare:CC (match_dup 3) | |
11678 | (const_int 0)))] | |
11679 | "") | |
1fd4e8c1 | 11680 | |
a260abc9 | 11681 | (define_insn "" |
9ebbca7d | 11682 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11683 | (compare:CC |
11684 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11685 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11686 | (const_int 63)) |
9ebbca7d | 11687 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11688 | (const_int 0))) |
9ebbca7d | 11689 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 11690 | "TARGET_64BIT" |
9ebbca7d GK |
11691 | "@ |
11692 | addic %3,%1,-1\;addze. %3,%2 | |
11693 | #" | |
a260abc9 | 11694 | [(set_attr "type" "compare") |
9ebbca7d GK |
11695 | (set_attr "length" "8,12")]) |
11696 | ||
11697 | (define_split | |
11698 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11699 | (compare:CC | |
11700 | (plus:DI (lshiftrt:DI | |
11701 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11702 | (const_int 63)) | |
11703 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11704 | (const_int 0))) | |
11705 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11706 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11707 | [(set (match_dup 3) |
11708 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
11709 | (const_int 63)) | |
11710 | (match_dup 2))) | |
11711 | (set (match_dup 0) | |
11712 | (compare:CC (match_dup 3) | |
11713 | (const_int 0)))] | |
11714 | "") | |
a260abc9 | 11715 | |
1fd4e8c1 | 11716 | (define_insn "" |
9ebbca7d | 11717 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11718 | (compare:CC |
11719 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11720 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11721 | (const_int 31)) |
9ebbca7d | 11722 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11723 | (const_int 0))) |
9ebbca7d | 11724 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11725 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
11726 | (match_dup 2))) | |
9ebbca7d | 11727 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 11728 | "TARGET_32BIT" |
9ebbca7d GK |
11729 | "@ |
11730 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
11731 | #" | |
b19003d8 | 11732 | [(set_attr "type" "compare") |
9ebbca7d GK |
11733 | (set_attr "length" "8,12")]) |
11734 | ||
11735 | (define_split | |
11736 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11737 | (compare:CC | |
11738 | (plus:SI (lshiftrt:SI | |
11739 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11740 | (const_int 31)) | |
11741 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11742 | (const_int 0))) | |
11743 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11744 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11745 | (match_dup 2))) | |
11746 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 11747 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11748 | [(parallel [(set (match_dup 0) |
11749 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11750 | (match_dup 2))) | |
11751 | (clobber (match_dup 3))]) | |
11752 | (set (match_dup 4) | |
11753 | (compare:CC (match_dup 0) | |
11754 | (const_int 0)))] | |
11755 | "") | |
1fd4e8c1 | 11756 | |
a260abc9 | 11757 | (define_insn "" |
9ebbca7d | 11758 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11759 | (compare:CC |
11760 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11761 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11762 | (const_int 63)) |
9ebbca7d | 11763 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11764 | (const_int 0))) |
9ebbca7d | 11765 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
11766 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
11767 | (match_dup 2))) | |
9ebbca7d | 11768 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 11769 | "TARGET_64BIT" |
9ebbca7d GK |
11770 | "@ |
11771 | addic %3,%1,-1\;addze. %0,%2 | |
11772 | #" | |
a260abc9 | 11773 | [(set_attr "type" "compare") |
9ebbca7d GK |
11774 | (set_attr "length" "8,12")]) |
11775 | ||
11776 | (define_split | |
11777 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11778 | (compare:CC | |
11779 | (plus:DI (lshiftrt:DI | |
11780 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11781 | (const_int 63)) | |
11782 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11783 | (const_int 0))) | |
11784 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11785 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11786 | (match_dup 2))) | |
11787 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11788 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11789 | [(parallel [(set (match_dup 0) |
11790 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11791 | (match_dup 2))) | |
11792 | (clobber (match_dup 3))]) | |
11793 | (set (match_dup 4) | |
11794 | (compare:CC (match_dup 0) | |
11795 | (const_int 0)))] | |
11796 | "") | |
a260abc9 | 11797 | |
1fd4e8c1 | 11798 | (define_insn "" |
cd2b37d9 RK |
11799 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11800 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
11801 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
11802 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 11803 | "TARGET_POWER" |
1fd4e8c1 | 11804 | "@ |
ca7f5001 | 11805 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 11806 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11807 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11808 | |
11809 | (define_insn "" | |
9ebbca7d | 11810 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11811 | (compare:CC |
9ebbca7d GK |
11812 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11813 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 11814 | (const_int 0))) |
9ebbca7d | 11815 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11816 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11817 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 11818 | "TARGET_POWER" |
1fd4e8c1 | 11819 | "@ |
ca7f5001 | 11820 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
11821 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
11822 | # | |
11823 | #" | |
11824 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
11825 | (set_attr "length" "12,12,16,16")]) | |
11826 | ||
11827 | (define_split | |
11828 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11829 | (compare:CC | |
11830 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11831 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11832 | (const_int 0))) | |
11833 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11834 | (le:SI (match_dup 1) (match_dup 2))) | |
11835 | (clobber (match_scratch:SI 3 ""))] | |
11836 | "TARGET_POWER && reload_completed" | |
11837 | [(parallel [(set (match_dup 0) | |
11838 | (le:SI (match_dup 1) (match_dup 2))) | |
11839 | (clobber (match_dup 3))]) | |
11840 | (set (match_dup 4) | |
11841 | (compare:CC (match_dup 0) | |
11842 | (const_int 0)))] | |
11843 | "") | |
1fd4e8c1 RK |
11844 | |
11845 | (define_insn "" | |
097657c3 | 11846 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 11847 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 11848 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
097657c3 | 11849 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
ca7f5001 | 11850 | "TARGET_POWER" |
1fd4e8c1 | 11851 | "@ |
097657c3 AM |
11852 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11853 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" | |
b19003d8 | 11854 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11855 | |
11856 | (define_insn "" | |
9ebbca7d | 11857 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11858 | (compare:CC |
9ebbca7d GK |
11859 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11860 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
11861 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11862 | (const_int 0))) |
9ebbca7d | 11863 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 11864 | "TARGET_POWER" |
1fd4e8c1 | 11865 | "@ |
ca7f5001 | 11866 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
11867 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
11868 | # | |
11869 | #" | |
b19003d8 | 11870 | [(set_attr "type" "compare") |
9ebbca7d GK |
11871 | (set_attr "length" "12,12,16,16")]) |
11872 | ||
11873 | (define_split | |
11874 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11875 | (compare:CC | |
11876 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11877 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11878 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11879 | (const_int 0))) | |
11880 | (clobber (match_scratch:SI 4 ""))] | |
11881 | "TARGET_POWER && reload_completed" | |
11882 | [(set (match_dup 4) | |
11883 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 11884 | (match_dup 3))) |
9ebbca7d GK |
11885 | (set (match_dup 0) |
11886 | (compare:CC (match_dup 4) | |
11887 | (const_int 0)))] | |
11888 | "") | |
1fd4e8c1 RK |
11889 | |
11890 | (define_insn "" | |
097657c3 | 11891 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11892 | (compare:CC |
9ebbca7d GK |
11893 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11894 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
11895 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11896 | (const_int 0))) |
097657c3 AM |
11897 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
11898 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 11899 | "TARGET_POWER" |
1fd4e8c1 | 11900 | "@ |
097657c3 AM |
11901 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11902 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11903 | # |
11904 | #" | |
b19003d8 | 11905 | [(set_attr "type" "compare") |
9ebbca7d GK |
11906 | (set_attr "length" "12,12,16,16")]) |
11907 | ||
11908 | (define_split | |
097657c3 | 11909 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11910 | (compare:CC |
11911 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11912 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11913 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11914 | (const_int 0))) | |
11915 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 11916 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 11917 | "TARGET_POWER && reload_completed" |
097657c3 | 11918 | [(set (match_dup 0) |
9ebbca7d | 11919 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 11920 | (set (match_dup 4) |
9ebbca7d GK |
11921 | (compare:CC (match_dup 0) |
11922 | (const_int 0)))] | |
11923 | "") | |
1fd4e8c1 RK |
11924 | |
11925 | (define_insn "" | |
cd2b37d9 RK |
11926 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11927 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11928 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 11929 | "TARGET_POWER" |
1fd4e8c1 | 11930 | "@ |
ca7f5001 RK |
11931 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11932 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 11933 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11934 | |
11935 | (define_insn "" | |
cd2b37d9 RK |
11936 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11937 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11938 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
4b8a63d6 | 11939 | "TARGET_32BIT" |
ca7f5001 | 11940 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
943c15ed DE |
11941 | [(set_attr "type" "three") |
11942 | (set_attr "length" "12")]) | |
1fd4e8c1 | 11943 | |
f9562f27 DE |
11944 | (define_insn "" |
11945 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11946 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
11947 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 11948 | "TARGET_64BIT" |
f9562f27 | 11949 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" |
943c15ed DE |
11950 | [(set_attr "type" "three") |
11951 | (set_attr "length" "12")]) | |
f9562f27 DE |
11952 | |
11953 | (define_insn "" | |
9ebbca7d | 11954 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 11955 | (compare:CC |
9ebbca7d GK |
11956 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
11957 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 11958 | (const_int 0))) |
9ebbca7d | 11959 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 11960 | (leu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 11961 | "TARGET_64BIT" |
9ebbca7d GK |
11962 | "@ |
11963 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
11964 | #" | |
f9562f27 | 11965 | [(set_attr "type" "compare") |
9ebbca7d GK |
11966 | (set_attr "length" "12,16")]) |
11967 | ||
11968 | (define_split | |
11969 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11970 | (compare:CC | |
11971 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11972 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
11973 | (const_int 0))) | |
11974 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11975 | (leu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 11976 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11977 | [(set (match_dup 0) |
11978 | (leu:DI (match_dup 1) (match_dup 2))) | |
11979 | (set (match_dup 3) | |
11980 | (compare:CC (match_dup 0) | |
11981 | (const_int 0)))] | |
11982 | "") | |
f9562f27 | 11983 | |
1fd4e8c1 | 11984 | (define_insn "" |
9ebbca7d | 11985 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11986 | (compare:CC |
9ebbca7d GK |
11987 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11988 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11989 | (const_int 0))) |
9ebbca7d | 11990 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11991 | (leu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 11992 | "TARGET_32BIT" |
9ebbca7d GK |
11993 | "@ |
11994 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
11995 | #" | |
b19003d8 | 11996 | [(set_attr "type" "compare") |
9ebbca7d GK |
11997 | (set_attr "length" "12,16")]) |
11998 | ||
11999 | (define_split | |
12000 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12001 | (compare:CC | |
12002 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12003 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12004 | (const_int 0))) | |
12005 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12006 | (leu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12007 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12008 | [(set (match_dup 0) |
12009 | (leu:SI (match_dup 1) (match_dup 2))) | |
12010 | (set (match_dup 3) | |
12011 | (compare:CC (match_dup 0) | |
12012 | (const_int 0)))] | |
12013 | "") | |
1fd4e8c1 RK |
12014 | |
12015 | (define_insn "" | |
80103f96 | 12016 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12017 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12018 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
80103f96 | 12019 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
683bdff7 | 12020 | "TARGET_32BIT" |
80103f96 | 12021 | "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" |
943c15ed DE |
12022 | [(set_attr "type" "two") |
12023 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
12024 | |
12025 | (define_insn "" | |
9ebbca7d | 12026 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12027 | (compare:CC |
9ebbca7d GK |
12028 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12029 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12030 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12031 | (const_int 0))) |
9ebbca7d | 12032 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 12033 | "TARGET_32BIT" |
9ebbca7d GK |
12034 | "@ |
12035 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
12036 | #" | |
b19003d8 | 12037 | [(set_attr "type" "compare") |
9ebbca7d GK |
12038 | (set_attr "length" "8,12")]) |
12039 | ||
12040 | (define_split | |
12041 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12042 | (compare:CC | |
12043 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12044 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12045 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12046 | (const_int 0))) | |
12047 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12048 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12049 | [(set (match_dup 4) |
12050 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
12051 | (match_dup 3))) | |
12052 | (set (match_dup 0) | |
12053 | (compare:CC (match_dup 4) | |
12054 | (const_int 0)))] | |
12055 | "") | |
1fd4e8c1 RK |
12056 | |
12057 | (define_insn "" | |
097657c3 | 12058 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12059 | (compare:CC |
9ebbca7d GK |
12060 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12061 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12062 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12063 | (const_int 0))) |
097657c3 AM |
12064 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12065 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12066 | "TARGET_32BIT" |
9ebbca7d | 12067 | "@ |
097657c3 | 12068 | {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 |
9ebbca7d | 12069 | #" |
b19003d8 | 12070 | [(set_attr "type" "compare") |
9ebbca7d GK |
12071 | (set_attr "length" "8,12")]) |
12072 | ||
12073 | (define_split | |
097657c3 | 12074 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12075 | (compare:CC |
12076 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12077 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12078 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12079 | (const_int 0))) | |
12080 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12081 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12082 | "TARGET_32BIT && reload_completed" |
097657c3 | 12083 | [(set (match_dup 0) |
9ebbca7d | 12084 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12085 | (set (match_dup 4) |
9ebbca7d GK |
12086 | (compare:CC (match_dup 0) |
12087 | (const_int 0)))] | |
12088 | "") | |
1fd4e8c1 RK |
12089 | |
12090 | (define_insn "" | |
cd2b37d9 RK |
12091 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12092 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12093 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
683bdff7 | 12094 | "TARGET_32BIT" |
ca7f5001 | 12095 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
943c15ed DE |
12096 | [(set_attr "type" "three") |
12097 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
12098 | |
12099 | (define_insn "" | |
097657c3 | 12100 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
1fd4e8c1 | 12101 | (and:SI (neg:SI |
cd2b37d9 | 12102 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12103 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
097657c3 | 12104 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
683bdff7 | 12105 | "TARGET_32BIT" |
097657c3 | 12106 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" |
943c15ed DE |
12107 | [(set_attr "type" "three") |
12108 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
12109 | |
12110 | (define_insn "" | |
9ebbca7d | 12111 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12112 | (compare:CC |
12113 | (and:SI (neg:SI | |
9ebbca7d GK |
12114 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12115 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12116 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12117 | (const_int 0))) |
9ebbca7d | 12118 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 12119 | "TARGET_32BIT" |
9ebbca7d GK |
12120 | "@ |
12121 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
12122 | #" | |
12123 | [(set_attr "type" "compare") | |
12124 | (set_attr "length" "12,16")]) | |
12125 | ||
12126 | (define_split | |
12127 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12128 | (compare:CC | |
12129 | (and:SI (neg:SI | |
12130 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12131 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12132 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12133 | (const_int 0))) | |
12134 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12135 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 12136 | [(set (match_dup 4) |
097657c3 AM |
12137 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) |
12138 | (match_dup 3))) | |
9ebbca7d GK |
12139 | (set (match_dup 0) |
12140 | (compare:CC (match_dup 4) | |
12141 | (const_int 0)))] | |
12142 | "") | |
1fd4e8c1 RK |
12143 | |
12144 | (define_insn "" | |
097657c3 | 12145 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12146 | (compare:CC |
12147 | (and:SI (neg:SI | |
9ebbca7d GK |
12148 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12149 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12150 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12151 | (const_int 0))) |
097657c3 AM |
12152 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12153 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 12154 | "TARGET_32BIT" |
9ebbca7d | 12155 | "@ |
097657c3 | 12156 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
9ebbca7d | 12157 | #" |
b19003d8 | 12158 | [(set_attr "type" "compare") |
9ebbca7d GK |
12159 | (set_attr "length" "12,16")]) |
12160 | ||
12161 | (define_split | |
097657c3 | 12162 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12163 | (compare:CC |
12164 | (and:SI (neg:SI | |
12165 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12166 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12167 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12168 | (const_int 0))) | |
12169 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12170 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 12171 | "TARGET_32BIT && reload_completed" |
097657c3 AM |
12172 | [(set (match_dup 0) |
12173 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) | |
12174 | (match_dup 3))) | |
12175 | (set (match_dup 4) | |
9ebbca7d GK |
12176 | (compare:CC (match_dup 0) |
12177 | (const_int 0)))] | |
12178 | "") | |
1fd4e8c1 RK |
12179 | |
12180 | (define_insn "" | |
cd2b37d9 RK |
12181 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12182 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12183 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 12184 | "TARGET_POWER" |
7f340546 | 12185 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12186 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12187 | |
12188 | (define_insn "" | |
9ebbca7d | 12189 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12190 | (compare:CC |
9ebbca7d GK |
12191 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12192 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12193 | (const_int 0))) |
9ebbca7d | 12194 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12195 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12196 | "TARGET_POWER" |
9ebbca7d GK |
12197 | "@ |
12198 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12199 | #" | |
29ae5b89 | 12200 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12201 | (set_attr "length" "12,16")]) |
12202 | ||
12203 | (define_split | |
12204 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12205 | (compare:CC | |
12206 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12207 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12208 | (const_int 0))) | |
12209 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12210 | (lt:SI (match_dup 1) (match_dup 2)))] | |
12211 | "TARGET_POWER && reload_completed" | |
12212 | [(set (match_dup 0) | |
12213 | (lt:SI (match_dup 1) (match_dup 2))) | |
12214 | (set (match_dup 3) | |
12215 | (compare:CC (match_dup 0) | |
12216 | (const_int 0)))] | |
12217 | "") | |
1fd4e8c1 RK |
12218 | |
12219 | (define_insn "" | |
097657c3 | 12220 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12221 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12222 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12223 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12224 | "TARGET_POWER" |
097657c3 | 12225 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 12226 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12227 | |
12228 | (define_insn "" | |
9ebbca7d | 12229 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12230 | (compare:CC |
9ebbca7d GK |
12231 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12232 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12233 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12234 | (const_int 0))) |
9ebbca7d | 12235 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12236 | "TARGET_POWER" |
9ebbca7d GK |
12237 | "@ |
12238 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12239 | #" | |
b19003d8 | 12240 | [(set_attr "type" "compare") |
9ebbca7d GK |
12241 | (set_attr "length" "12,16")]) |
12242 | ||
12243 | (define_split | |
12244 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12245 | (compare:CC | |
12246 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12247 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12248 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12249 | (const_int 0))) | |
12250 | (clobber (match_scratch:SI 4 ""))] | |
12251 | "TARGET_POWER && reload_completed" | |
12252 | [(set (match_dup 4) | |
12253 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12254 | (match_dup 3))) |
9ebbca7d GK |
12255 | (set (match_dup 0) |
12256 | (compare:CC (match_dup 4) | |
12257 | (const_int 0)))] | |
12258 | "") | |
1fd4e8c1 RK |
12259 | |
12260 | (define_insn "" | |
097657c3 | 12261 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12262 | (compare:CC |
9ebbca7d GK |
12263 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12264 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12265 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12266 | (const_int 0))) |
097657c3 AM |
12267 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12268 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12269 | "TARGET_POWER" |
9ebbca7d | 12270 | "@ |
097657c3 | 12271 | doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 12272 | #" |
b19003d8 | 12273 | [(set_attr "type" "compare") |
9ebbca7d GK |
12274 | (set_attr "length" "12,16")]) |
12275 | ||
12276 | (define_split | |
097657c3 | 12277 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12278 | (compare:CC |
12279 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12280 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12281 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12282 | (const_int 0))) | |
12283 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12284 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12285 | "TARGET_POWER && reload_completed" |
097657c3 | 12286 | [(set (match_dup 0) |
9ebbca7d | 12287 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12288 | (set (match_dup 4) |
9ebbca7d GK |
12289 | (compare:CC (match_dup 0) |
12290 | (const_int 0)))] | |
12291 | "") | |
1fd4e8c1 RK |
12292 | |
12293 | (define_insn "" | |
cd2b37d9 RK |
12294 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12295 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12296 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12297 | "TARGET_POWER" |
12298 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12299 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12300 | |
c0600ecd | 12301 | (define_insn_and_split "" |
cd2b37d9 RK |
12302 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12303 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12304 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
683bdff7 | 12305 | "TARGET_32BIT" |
c0600ecd DE |
12306 | "#" |
12307 | "TARGET_32BIT" | |
12308 | [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2)))) | |
12309 | (set (match_dup 0) (neg:SI (match_dup 0)))] | |
12310 | "") | |
12311 | ||
12312 | (define_insn_and_split "" | |
12313 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12314 | (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12315 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
12316 | "TARGET_64BIT" | |
12317 | "#" | |
12318 | "TARGET_64BIT" | |
12319 | [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2)))) | |
12320 | (set (match_dup 0) (neg:DI (match_dup 0)))] | |
12321 | "") | |
1fd4e8c1 RK |
12322 | |
12323 | (define_insn "" | |
9ebbca7d | 12324 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12325 | (compare:CC |
9ebbca7d GK |
12326 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12327 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12328 | (const_int 0))) |
9ebbca7d | 12329 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12330 | (ltu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12331 | "TARGET_32BIT" |
1fd4e8c1 | 12332 | "@ |
ca7f5001 | 12333 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
12334 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
12335 | # | |
12336 | #" | |
b19003d8 | 12337 | [(set_attr "type" "compare") |
9ebbca7d GK |
12338 | (set_attr "length" "12,12,16,16")]) |
12339 | ||
12340 | (define_split | |
12341 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12342 | (compare:CC | |
12343 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12344 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12345 | (const_int 0))) | |
12346 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12347 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12348 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12349 | [(set (match_dup 0) |
12350 | (ltu:SI (match_dup 1) (match_dup 2))) | |
12351 | (set (match_dup 3) | |
12352 | (compare:CC (match_dup 0) | |
12353 | (const_int 0)))] | |
12354 | "") | |
1fd4e8c1 | 12355 | |
c0600ecd | 12356 | (define_insn_and_split "" |
04fa46cf | 12357 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
c0600ecd DE |
12358 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12359 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
12360 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))] | |
683bdff7 | 12361 | "TARGET_32BIT" |
c0600ecd | 12362 | "#" |
04fa46cf | 12363 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" |
c0600ecd DE |
12364 | [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2)))) |
12365 | (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))] | |
12366 | "") | |
12367 | ||
12368 | (define_insn_and_split "" | |
04fa46cf | 12369 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
c0600ecd DE |
12370 | (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12371 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")) | |
12372 | (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))] | |
12373 | "TARGET_64BIT" | |
12374 | "#" | |
04fa46cf | 12375 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" |
c0600ecd DE |
12376 | [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2)))) |
12377 | (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))] | |
12378 | "") | |
1fd4e8c1 RK |
12379 | |
12380 | (define_insn "" | |
9ebbca7d | 12381 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12382 | (compare:CC |
9ebbca7d GK |
12383 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12384 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12385 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12386 | (const_int 0))) |
9ebbca7d | 12387 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12388 | "TARGET_32BIT" |
1fd4e8c1 | 12389 | "@ |
c9dbf840 DE |
12390 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 |
12391 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 | |
9ebbca7d GK |
12392 | # |
12393 | #" | |
b19003d8 | 12394 | [(set_attr "type" "compare") |
9ebbca7d GK |
12395 | (set_attr "length" "12,12,16,16")]) |
12396 | ||
12397 | (define_split | |
12398 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12399 | (compare:CC | |
12400 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12401 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12402 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12403 | (const_int 0))) | |
12404 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12405 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12406 | [(set (match_dup 4) |
12407 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12408 | (match_dup 3))) |
9ebbca7d GK |
12409 | (set (match_dup 0) |
12410 | (compare:CC (match_dup 4) | |
12411 | (const_int 0)))] | |
12412 | "") | |
1fd4e8c1 RK |
12413 | |
12414 | (define_insn "" | |
097657c3 | 12415 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12416 | (compare:CC |
9ebbca7d GK |
12417 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12418 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12419 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12420 | (const_int 0))) |
097657c3 AM |
12421 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12422 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12423 | "TARGET_32BIT" |
1fd4e8c1 | 12424 | "@ |
c9dbf840 DE |
12425 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 |
12426 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 | |
9ebbca7d GK |
12427 | # |
12428 | #" | |
b19003d8 | 12429 | [(set_attr "type" "compare") |
9ebbca7d GK |
12430 | (set_attr "length" "12,12,16,16")]) |
12431 | ||
12432 | (define_split | |
097657c3 | 12433 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12434 | (compare:CC |
12435 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12436 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12437 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12438 | (const_int 0))) | |
12439 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12440 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12441 | "TARGET_32BIT && reload_completed" |
097657c3 | 12442 | [(set (match_dup 0) |
9ebbca7d | 12443 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12444 | (set (match_dup 4) |
9ebbca7d GK |
12445 | (compare:CC (match_dup 0) |
12446 | (const_int 0)))] | |
12447 | "") | |
1fd4e8c1 RK |
12448 | |
12449 | (define_insn "" | |
cd2b37d9 RK |
12450 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12451 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12452 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
683bdff7 | 12453 | "TARGET_32BIT" |
1fd4e8c1 | 12454 | "@ |
ca7f5001 RK |
12455 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
12456 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
943c15ed | 12457 | [(set_attr "type" "two") |
c0600ecd DE |
12458 | (set_attr "length" "8")]) |
12459 | ||
12460 | (define_insn "" | |
12461 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12462 | (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12463 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))] | |
12464 | "TARGET_64BIT" | |
12465 | "@ | |
12466 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 | |
12467 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
943c15ed | 12468 | [(set_attr "type" "two") |
c0600ecd | 12469 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
12470 | |
12471 | (define_insn "" | |
cd2b37d9 RK |
12472 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12473 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
12474 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
12475 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
12476 | "TARGET_POWER" |
12477 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 12478 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12479 | |
9ebbca7d GK |
12480 | (define_insn "" |
12481 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 12482 | (compare:CC |
9ebbca7d GK |
12483 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12484 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12485 | (const_int 0))) |
9ebbca7d | 12486 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12487 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12488 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 12489 | "TARGET_POWER" |
9ebbca7d GK |
12490 | "@ |
12491 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
12492 | #" | |
12493 | [(set_attr "type" "compare") | |
12494 | (set_attr "length" "12,16")]) | |
12495 | ||
12496 | (define_split | |
12497 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12498 | (compare:CC | |
12499 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12500 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12501 | (const_int 0))) | |
12502 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12503 | (ge:SI (match_dup 1) (match_dup 2))) | |
12504 | (clobber (match_scratch:SI 3 ""))] | |
12505 | "TARGET_POWER && reload_completed" | |
12506 | [(parallel [(set (match_dup 0) | |
097657c3 AM |
12507 | (ge:SI (match_dup 1) (match_dup 2))) |
12508 | (clobber (match_dup 3))]) | |
9ebbca7d GK |
12509 | (set (match_dup 4) |
12510 | (compare:CC (match_dup 0) | |
12511 | (const_int 0)))] | |
12512 | "") | |
12513 | ||
1fd4e8c1 | 12514 | (define_insn "" |
097657c3 | 12515 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12516 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12517 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12518 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12519 | "TARGET_POWER" |
097657c3 | 12520 | "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" |
b19003d8 | 12521 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12522 | |
12523 | (define_insn "" | |
9ebbca7d | 12524 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12525 | (compare:CC |
9ebbca7d GK |
12526 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12527 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12528 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12529 | (const_int 0))) |
9ebbca7d | 12530 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12531 | "TARGET_POWER" |
9ebbca7d GK |
12532 | "@ |
12533 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
12534 | #" | |
b19003d8 | 12535 | [(set_attr "type" "compare") |
9ebbca7d GK |
12536 | (set_attr "length" "12,16")]) |
12537 | ||
12538 | (define_split | |
12539 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12540 | (compare:CC | |
12541 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12542 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12543 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12544 | (const_int 0))) | |
12545 | (clobber (match_scratch:SI 4 ""))] | |
12546 | "TARGET_POWER && reload_completed" | |
12547 | [(set (match_dup 4) | |
12548 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12549 | (match_dup 3))) |
9ebbca7d GK |
12550 | (set (match_dup 0) |
12551 | (compare:CC (match_dup 4) | |
12552 | (const_int 0)))] | |
12553 | "") | |
1fd4e8c1 RK |
12554 | |
12555 | (define_insn "" | |
097657c3 | 12556 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12557 | (compare:CC |
9ebbca7d GK |
12558 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12559 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12560 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12561 | (const_int 0))) |
097657c3 AM |
12562 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12563 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12564 | "TARGET_POWER" |
9ebbca7d | 12565 | "@ |
097657c3 | 12566 | doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
9ebbca7d | 12567 | #" |
b19003d8 | 12568 | [(set_attr "type" "compare") |
9ebbca7d GK |
12569 | (set_attr "length" "12,16")]) |
12570 | ||
12571 | (define_split | |
097657c3 | 12572 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12573 | (compare:CC |
12574 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12575 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12576 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12577 | (const_int 0))) | |
12578 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12579 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12580 | "TARGET_POWER && reload_completed" |
097657c3 | 12581 | [(set (match_dup 0) |
9ebbca7d | 12582 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12583 | (set (match_dup 4) |
9ebbca7d GK |
12584 | (compare:CC (match_dup 0) |
12585 | (const_int 0)))] | |
12586 | "") | |
1fd4e8c1 RK |
12587 | |
12588 | (define_insn "" | |
cd2b37d9 RK |
12589 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12590 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12591 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12592 | "TARGET_POWER" |
12593 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12594 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12595 | |
1fd4e8c1 | 12596 | (define_insn "" |
cd2b37d9 RK |
12597 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12598 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12599 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
683bdff7 | 12600 | "TARGET_32BIT" |
1fd4e8c1 | 12601 | "@ |
ca7f5001 RK |
12602 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
12603 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
943c15ed DE |
12604 | [(set_attr "type" "three") |
12605 | (set_attr "length" "12")]) | |
1fd4e8c1 | 12606 | |
f9562f27 DE |
12607 | (define_insn "" |
12608 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12609 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12610 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
683bdff7 | 12611 | "TARGET_64BIT" |
f9562f27 DE |
12612 | "@ |
12613 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
12614 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
943c15ed DE |
12615 | [(set_attr "type" "three") |
12616 | (set_attr "length" "12")]) | |
f9562f27 | 12617 | |
1fd4e8c1 | 12618 | (define_insn "" |
9ebbca7d | 12619 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12620 | (compare:CC |
9ebbca7d GK |
12621 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12622 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12623 | (const_int 0))) |
9ebbca7d | 12624 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12625 | (geu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12626 | "TARGET_32BIT" |
1fd4e8c1 | 12627 | "@ |
ca7f5001 | 12628 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
12629 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
12630 | # | |
12631 | #" | |
b19003d8 | 12632 | [(set_attr "type" "compare") |
9ebbca7d GK |
12633 | (set_attr "length" "12,12,16,16")]) |
12634 | ||
12635 | (define_split | |
12636 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12637 | (compare:CC | |
12638 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12639 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12640 | (const_int 0))) | |
12641 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12642 | (geu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12643 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12644 | [(set (match_dup 0) |
12645 | (geu:SI (match_dup 1) (match_dup 2))) | |
12646 | (set (match_dup 3) | |
12647 | (compare:CC (match_dup 0) | |
12648 | (const_int 0)))] | |
12649 | "") | |
1fd4e8c1 | 12650 | |
f9562f27 | 12651 | (define_insn "" |
9ebbca7d | 12652 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12653 | (compare:CC |
9ebbca7d GK |
12654 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12655 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 12656 | (const_int 0))) |
9ebbca7d | 12657 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 | 12658 | (geu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12659 | "TARGET_64BIT" |
f9562f27 DE |
12660 | "@ |
12661 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
12662 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
12663 | # | |
12664 | #" | |
f9562f27 | 12665 | [(set_attr "type" "compare") |
9ebbca7d GK |
12666 | (set_attr "length" "12,12,16,16")]) |
12667 | ||
12668 | (define_split | |
12669 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12670 | (compare:CC | |
12671 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12672 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
12673 | (const_int 0))) | |
12674 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12675 | (geu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12676 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12677 | [(set (match_dup 0) |
12678 | (geu:DI (match_dup 1) (match_dup 2))) | |
12679 | (set (match_dup 3) | |
12680 | (compare:CC (match_dup 0) | |
12681 | (const_int 0)))] | |
12682 | "") | |
f9562f27 | 12683 | |
1fd4e8c1 | 12684 | (define_insn "" |
80103f96 | 12685 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 12686 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12687 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
80103f96 | 12688 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
683bdff7 | 12689 | "TARGET_32BIT" |
1fd4e8c1 | 12690 | "@ |
80103f96 FS |
12691 | {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 |
12692 | {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" | |
943c15ed DE |
12693 | [(set_attr "type" "two") |
12694 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
12695 | |
12696 | (define_insn "" | |
9ebbca7d | 12697 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12698 | (compare:CC |
9ebbca7d GK |
12699 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12700 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12701 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12702 | (const_int 0))) |
9ebbca7d | 12703 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12704 | "TARGET_32BIT" |
1fd4e8c1 | 12705 | "@ |
ca7f5001 | 12706 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12707 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
12708 | # | |
12709 | #" | |
b19003d8 | 12710 | [(set_attr "type" "compare") |
9ebbca7d GK |
12711 | (set_attr "length" "8,8,12,12")]) |
12712 | ||
12713 | (define_split | |
12714 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12715 | (compare:CC | |
12716 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12717 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12718 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12719 | (const_int 0))) | |
12720 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12721 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12722 | [(set (match_dup 4) |
12723 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
12724 | (match_dup 3))) | |
12725 | (set (match_dup 0) | |
12726 | (compare:CC (match_dup 4) | |
12727 | (const_int 0)))] | |
12728 | "") | |
1fd4e8c1 RK |
12729 | |
12730 | (define_insn "" | |
097657c3 | 12731 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12732 | (compare:CC |
9ebbca7d GK |
12733 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12734 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12735 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12736 | (const_int 0))) |
097657c3 AM |
12737 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12738 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12739 | "TARGET_32BIT" |
1fd4e8c1 | 12740 | "@ |
097657c3 AM |
12741 | {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 |
12742 | {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12743 | # |
12744 | #" | |
b19003d8 | 12745 | [(set_attr "type" "compare") |
9ebbca7d GK |
12746 | (set_attr "length" "8,8,12,12")]) |
12747 | ||
12748 | (define_split | |
097657c3 | 12749 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12750 | (compare:CC |
12751 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12752 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12753 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12754 | (const_int 0))) | |
12755 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12756 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12757 | "TARGET_32BIT && reload_completed" |
097657c3 | 12758 | [(set (match_dup 0) |
9ebbca7d | 12759 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12760 | (set (match_dup 4) |
9ebbca7d GK |
12761 | (compare:CC (match_dup 0) |
12762 | (const_int 0)))] | |
12763 | "") | |
1fd4e8c1 RK |
12764 | |
12765 | (define_insn "" | |
cd2b37d9 RK |
12766 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12767 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12768 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
683bdff7 | 12769 | "TARGET_32BIT" |
1fd4e8c1 | 12770 | "@ |
ca7f5001 | 12771 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 12772 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
943c15ed DE |
12773 | [(set_attr "type" "three") |
12774 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
12775 | |
12776 | (define_insn "" | |
097657c3 | 12777 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
1fd4e8c1 | 12778 | (and:SI (neg:SI |
cd2b37d9 | 12779 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12780 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
097657c3 | 12781 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
683bdff7 | 12782 | "TARGET_32BIT" |
1fd4e8c1 | 12783 | "@ |
097657c3 AM |
12784 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 |
12785 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" | |
943c15ed DE |
12786 | [(set_attr "type" "three") |
12787 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
12788 | |
12789 | (define_insn "" | |
9ebbca7d | 12790 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12791 | (compare:CC |
12792 | (and:SI (neg:SI | |
9ebbca7d GK |
12793 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12794 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12795 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12796 | (const_int 0))) |
9ebbca7d | 12797 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12798 | "TARGET_32BIT" |
1fd4e8c1 | 12799 | "@ |
ca7f5001 | 12800 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
12801 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
12802 | # | |
12803 | #" | |
b19003d8 | 12804 | [(set_attr "type" "compare") |
9ebbca7d GK |
12805 | (set_attr "length" "12,12,16,16")]) |
12806 | ||
12807 | (define_split | |
12808 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12809 | (compare:CC | |
12810 | (and:SI (neg:SI | |
12811 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12812 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12813 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12814 | (const_int 0))) | |
12815 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12816 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 12817 | [(set (match_dup 4) |
097657c3 AM |
12818 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) |
12819 | (match_dup 3))) | |
9ebbca7d GK |
12820 | (set (match_dup 0) |
12821 | (compare:CC (match_dup 4) | |
12822 | (const_int 0)))] | |
12823 | "") | |
1fd4e8c1 RK |
12824 | |
12825 | (define_insn "" | |
097657c3 | 12826 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12827 | (compare:CC |
12828 | (and:SI (neg:SI | |
9ebbca7d GK |
12829 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12830 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12831 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12832 | (const_int 0))) |
097657c3 AM |
12833 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12834 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 12835 | "TARGET_32BIT" |
1fd4e8c1 | 12836 | "@ |
097657c3 AM |
12837 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
12838 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 | |
9ebbca7d GK |
12839 | # |
12840 | #" | |
b19003d8 | 12841 | [(set_attr "type" "compare") |
9ebbca7d GK |
12842 | (set_attr "length" "12,12,16,16")]) |
12843 | ||
12844 | (define_split | |
097657c3 | 12845 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12846 | (compare:CC |
12847 | (and:SI (neg:SI | |
12848 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12849 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12850 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12851 | (const_int 0))) | |
12852 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12853 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 12854 | "TARGET_32BIT && reload_completed" |
097657c3 | 12855 | [(set (match_dup 0) |
9ebbca7d | 12856 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
097657c3 | 12857 | (set (match_dup 4) |
9ebbca7d GK |
12858 | (compare:CC (match_dup 0) |
12859 | (const_int 0)))] | |
12860 | "") | |
1fd4e8c1 RK |
12861 | |
12862 | (define_insn "" | |
cd2b37d9 RK |
12863 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12864 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12865 | (const_int 0)))] |
683bdff7 | 12866 | "TARGET_32BIT" |
ca7f5001 | 12867 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
943c15ed DE |
12868 | [(set_attr "type" "three") |
12869 | (set_attr "length" "12")]) | |
1fd4e8c1 | 12870 | |
f9562f27 DE |
12871 | (define_insn "" |
12872 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12873 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12874 | (const_int 0)))] | |
683bdff7 | 12875 | "TARGET_64BIT" |
f9562f27 | 12876 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" |
943c15ed DE |
12877 | [(set_attr "type" "three") |
12878 | (set_attr "length" "12")]) | |
f9562f27 | 12879 | |
1fd4e8c1 | 12880 | (define_insn "" |
9ebbca7d | 12881 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12882 | (compare:CC |
9ebbca7d | 12883 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
12884 | (const_int 0)) |
12885 | (const_int 0))) | |
9ebbca7d | 12886 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12887 | (gt:SI (match_dup 1) (const_int 0)))] |
683bdff7 | 12888 | "TARGET_32BIT" |
9ebbca7d GK |
12889 | "@ |
12890 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
12891 | #" | |
29ae5b89 | 12892 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12893 | (set_attr "length" "12,16")]) |
12894 | ||
12895 | (define_split | |
12896 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
12897 | (compare:CC | |
12898 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12899 | (const_int 0)) | |
12900 | (const_int 0))) | |
12901 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12902 | (gt:SI (match_dup 1) (const_int 0)))] | |
683bdff7 | 12903 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12904 | [(set (match_dup 0) |
12905 | (gt:SI (match_dup 1) (const_int 0))) | |
12906 | (set (match_dup 2) | |
12907 | (compare:CC (match_dup 0) | |
12908 | (const_int 0)))] | |
12909 | "") | |
1fd4e8c1 | 12910 | |
f9562f27 | 12911 | (define_insn "" |
9ebbca7d | 12912 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 12913 | (compare:CC |
9ebbca7d | 12914 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
12915 | (const_int 0)) |
12916 | (const_int 0))) | |
9ebbca7d | 12917 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 12918 | (gt:DI (match_dup 1) (const_int 0)))] |
683bdff7 | 12919 | "TARGET_64BIT" |
9ebbca7d GK |
12920 | "@ |
12921 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
12922 | #" | |
f9562f27 | 12923 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12924 | (set_attr "length" "12,16")]) |
12925 | ||
12926 | (define_split | |
12927 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
12928 | (compare:CC | |
12929 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12930 | (const_int 0)) | |
12931 | (const_int 0))) | |
12932 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12933 | (gt:DI (match_dup 1) (const_int 0)))] | |
683bdff7 | 12934 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12935 | [(set (match_dup 0) |
12936 | (gt:DI (match_dup 1) (const_int 0))) | |
12937 | (set (match_dup 2) | |
12938 | (compare:CC (match_dup 0) | |
12939 | (const_int 0)))] | |
12940 | "") | |
f9562f27 | 12941 | |
1fd4e8c1 | 12942 | (define_insn "" |
cd2b37d9 RK |
12943 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12944 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12945 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
12946 | "TARGET_POWER" |
12947 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 12948 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12949 | |
12950 | (define_insn "" | |
9ebbca7d | 12951 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12952 | (compare:CC |
9ebbca7d GK |
12953 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12954 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 12955 | (const_int 0))) |
9ebbca7d | 12956 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12957 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12958 | "TARGET_POWER" |
9ebbca7d GK |
12959 | "@ |
12960 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12961 | #" | |
29ae5b89 | 12962 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12963 | (set_attr "length" "12,16")]) |
12964 | ||
12965 | (define_split | |
12966 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12967 | (compare:CC | |
12968 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12969 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12970 | (const_int 0))) | |
12971 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12972 | (gt:SI (match_dup 1) (match_dup 2)))] | |
12973 | "TARGET_POWER && reload_completed" | |
12974 | [(set (match_dup 0) | |
12975 | (gt:SI (match_dup 1) (match_dup 2))) | |
12976 | (set (match_dup 3) | |
12977 | (compare:CC (match_dup 0) | |
12978 | (const_int 0)))] | |
12979 | "") | |
1fd4e8c1 RK |
12980 | |
12981 | (define_insn "" | |
80103f96 | 12982 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12983 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12984 | (const_int 0)) |
80103f96 | 12985 | (match_operand:SI 2 "gpc_reg_operand" "r")))] |
683bdff7 | 12986 | "TARGET_32BIT" |
80103f96 | 12987 | "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" |
943c15ed DE |
12988 | [(set_attr "type" "three") |
12989 | (set_attr "length" "12")]) | |
1fd4e8c1 | 12990 | |
f9562f27 | 12991 | (define_insn "" |
097657c3 | 12992 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
f9562f27 DE |
12993 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
12994 | (const_int 0)) | |
097657c3 | 12995 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
683bdff7 | 12996 | "TARGET_64BIT" |
097657c3 | 12997 | "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" |
943c15ed DE |
12998 | [(set_attr "type" "three") |
12999 | (set_attr "length" "12")]) | |
f9562f27 | 13000 | |
1fd4e8c1 | 13001 | (define_insn "" |
9ebbca7d | 13002 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13003 | (compare:CC |
9ebbca7d | 13004 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 13005 | (const_int 0)) |
9ebbca7d | 13006 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 13007 | (const_int 0))) |
9ebbca7d | 13008 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 13009 | "TARGET_32BIT" |
9ebbca7d GK |
13010 | "@ |
13011 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
13012 | #" | |
b19003d8 | 13013 | [(set_attr "type" "compare") |
9ebbca7d GK |
13014 | (set_attr "length" "12,16")]) |
13015 | ||
13016 | (define_split | |
13017 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13018 | (compare:CC | |
13019 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13020 | (const_int 0)) | |
13021 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
13022 | (const_int 0))) | |
13023 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 13024 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13025 | [(set (match_dup 3) |
13026 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
13027 | (match_dup 2))) | |
13028 | (set (match_dup 0) | |
13029 | (compare:CC (match_dup 3) | |
13030 | (const_int 0)))] | |
13031 | "") | |
1fd4e8c1 | 13032 | |
f9562f27 | 13033 | (define_insn "" |
9ebbca7d | 13034 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 13035 | (compare:CC |
9ebbca7d | 13036 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13037 | (const_int 0)) |
9ebbca7d | 13038 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13039 | (const_int 0))) |
9ebbca7d | 13040 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 13041 | "TARGET_64BIT" |
9ebbca7d GK |
13042 | "@ |
13043 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
13044 | #" | |
f9562f27 | 13045 | [(set_attr "type" "compare") |
9ebbca7d GK |
13046 | (set_attr "length" "12,16")]) |
13047 | ||
13048 | (define_split | |
13049 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13050 | (compare:CC | |
13051 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13052 | (const_int 0)) | |
13053 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13054 | (const_int 0))) | |
13055 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 13056 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13057 | [(set (match_dup 3) |
13058 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
097657c3 | 13059 | (match_dup 2))) |
9ebbca7d GK |
13060 | (set (match_dup 0) |
13061 | (compare:CC (match_dup 3) | |
13062 | (const_int 0)))] | |
13063 | "") | |
f9562f27 | 13064 | |
1fd4e8c1 | 13065 | (define_insn "" |
097657c3 | 13066 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
9ebbca7d GK |
13067 | (compare:CC |
13068 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
13069 | (const_int 0)) | |
13070 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
13071 | (const_int 0))) | |
097657c3 AM |
13072 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13073 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 13074 | "TARGET_32BIT" |
9ebbca7d | 13075 | "@ |
097657c3 | 13076 | {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 |
9ebbca7d GK |
13077 | #" |
13078 | [(set_attr "type" "compare") | |
13079 | (set_attr "length" "12,16")]) | |
13080 | ||
13081 | (define_split | |
097657c3 | 13082 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
1fd4e8c1 | 13083 | (compare:CC |
9ebbca7d | 13084 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 13085 | (const_int 0)) |
9ebbca7d | 13086 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 13087 | (const_int 0))) |
9ebbca7d | 13088 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
097657c3 | 13089 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 13090 | "TARGET_32BIT && reload_completed" |
097657c3 | 13091 | [(set (match_dup 0) |
9ebbca7d | 13092 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13093 | (set (match_dup 3) |
9ebbca7d GK |
13094 | (compare:CC (match_dup 0) |
13095 | (const_int 0)))] | |
13096 | "") | |
1fd4e8c1 | 13097 | |
f9562f27 | 13098 | (define_insn "" |
097657c3 | 13099 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13100 | (compare:CC |
9ebbca7d | 13101 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13102 | (const_int 0)) |
9ebbca7d | 13103 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13104 | (const_int 0))) |
097657c3 AM |
13105 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
13106 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 13107 | "TARGET_64BIT" |
9ebbca7d | 13108 | "@ |
097657c3 | 13109 | addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 |
9ebbca7d | 13110 | #" |
f9562f27 | 13111 | [(set_attr "type" "compare") |
9ebbca7d GK |
13112 | (set_attr "length" "12,16")]) |
13113 | ||
13114 | (define_split | |
097657c3 | 13115 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13116 | (compare:CC |
13117 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13118 | (const_int 0)) | |
13119 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13120 | (const_int 0))) | |
13121 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13122 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 13123 | "TARGET_64BIT && reload_completed" |
097657c3 | 13124 | [(set (match_dup 0) |
9ebbca7d | 13125 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13126 | (set (match_dup 3) |
9ebbca7d GK |
13127 | (compare:CC (match_dup 0) |
13128 | (const_int 0)))] | |
13129 | "") | |
f9562f27 | 13130 | |
1fd4e8c1 | 13131 | (define_insn "" |
097657c3 | 13132 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13133 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13134 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
097657c3 | 13135 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 13136 | "TARGET_POWER" |
097657c3 | 13137 | "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 13138 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13139 | |
13140 | (define_insn "" | |
9ebbca7d | 13141 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13142 | (compare:CC |
9ebbca7d GK |
13143 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13144 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13145 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13146 | (const_int 0))) |
9ebbca7d | 13147 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 13148 | "TARGET_POWER" |
9ebbca7d GK |
13149 | "@ |
13150 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
13151 | #" | |
b19003d8 | 13152 | [(set_attr "type" "compare") |
9ebbca7d GK |
13153 | (set_attr "length" "12,16")]) |
13154 | ||
13155 | (define_split | |
13156 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13157 | (compare:CC | |
13158 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13159 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13160 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13161 | (const_int 0))) | |
13162 | (clobber (match_scratch:SI 4 ""))] | |
13163 | "TARGET_POWER && reload_completed" | |
13164 | [(set (match_dup 4) | |
097657c3 | 13165 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d GK |
13166 | (set (match_dup 0) |
13167 | (compare:CC (match_dup 4) | |
13168 | (const_int 0)))] | |
13169 | "") | |
1fd4e8c1 RK |
13170 | |
13171 | (define_insn "" | |
097657c3 | 13172 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13173 | (compare:CC |
9ebbca7d GK |
13174 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13175 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13176 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13177 | (const_int 0))) |
097657c3 AM |
13178 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13179 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 13180 | "TARGET_POWER" |
9ebbca7d | 13181 | "@ |
097657c3 | 13182 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 13183 | #" |
b19003d8 | 13184 | [(set_attr "type" "compare") |
9ebbca7d GK |
13185 | (set_attr "length" "12,16")]) |
13186 | ||
13187 | (define_split | |
097657c3 | 13188 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13189 | (compare:CC |
13190 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13191 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13192 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13193 | (const_int 0))) | |
13194 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13195 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13196 | "TARGET_POWER && reload_completed" |
097657c3 | 13197 | [(set (match_dup 0) |
9ebbca7d | 13198 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13199 | (set (match_dup 4) |
9ebbca7d GK |
13200 | (compare:CC (match_dup 0) |
13201 | (const_int 0)))] | |
13202 | "") | |
1fd4e8c1 RK |
13203 | |
13204 | (define_insn "" | |
cd2b37d9 RK |
13205 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13206 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13207 | (const_int 0))))] |
683bdff7 | 13208 | "TARGET_32BIT" |
ca7f5001 | 13209 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
943c15ed DE |
13210 | [(set_attr "type" "three") |
13211 | (set_attr "length" "12")]) | |
1fd4e8c1 | 13212 | |
f9562f27 DE |
13213 | (define_insn "" |
13214 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13215 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13216 | (const_int 0))))] | |
683bdff7 | 13217 | "TARGET_64BIT" |
8377288b | 13218 | "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63" |
943c15ed DE |
13219 | [(set_attr "type" "three") |
13220 | (set_attr "length" "12")]) | |
f9562f27 | 13221 | |
1fd4e8c1 | 13222 | (define_insn "" |
cd2b37d9 RK |
13223 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13224 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13225 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
13226 | "TARGET_POWER" |
13227 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 13228 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13229 | |
c0600ecd | 13230 | (define_insn_and_split "" |
cd2b37d9 | 13231 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c0600ecd DE |
13232 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
13233 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13234 | "TARGET_32BIT" |
c0600ecd DE |
13235 | "#" |
13236 | "TARGET_32BIT" | |
13237 | [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2)))) | |
13238 | (set (match_dup 0) (neg:SI (match_dup 0)))] | |
13239 | "") | |
1fd4e8c1 | 13240 | |
c0600ecd | 13241 | (define_insn_and_split "" |
f9562f27 | 13242 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
c0600ecd DE |
13243 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
13244 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13245 | "TARGET_64BIT" |
c0600ecd DE |
13246 | "#" |
13247 | "TARGET_64BIT" | |
13248 | [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2)))) | |
13249 | (set (match_dup 0) (neg:DI (match_dup 0)))] | |
13250 | "") | |
f9562f27 | 13251 | |
1fd4e8c1 | 13252 | (define_insn "" |
9ebbca7d | 13253 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13254 | (compare:CC |
9ebbca7d GK |
13255 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13256 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 13257 | (const_int 0))) |
9ebbca7d | 13258 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13259 | (gtu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 13260 | "TARGET_32BIT" |
9ebbca7d GK |
13261 | "@ |
13262 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
13263 | #" | |
b19003d8 | 13264 | [(set_attr "type" "compare") |
9ebbca7d GK |
13265 | (set_attr "length" "12,16")]) |
13266 | ||
13267 | (define_split | |
13268 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13269 | (compare:CC | |
13270 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13271 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13272 | (const_int 0))) | |
13273 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13274 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 13275 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13276 | [(set (match_dup 0) |
13277 | (gtu:SI (match_dup 1) (match_dup 2))) | |
13278 | (set (match_dup 3) | |
13279 | (compare:CC (match_dup 0) | |
13280 | (const_int 0)))] | |
13281 | "") | |
1fd4e8c1 | 13282 | |
f9562f27 | 13283 | (define_insn "" |
9ebbca7d | 13284 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13285 | (compare:CC |
9ebbca7d GK |
13286 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13287 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 13288 | (const_int 0))) |
9ebbca7d | 13289 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 13290 | (gtu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 13291 | "TARGET_64BIT" |
9ebbca7d GK |
13292 | "@ |
13293 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
13294 | #" | |
f9562f27 | 13295 | [(set_attr "type" "compare") |
9ebbca7d GK |
13296 | (set_attr "length" "12,16")]) |
13297 | ||
13298 | (define_split | |
13299 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13300 | (compare:CC | |
13301 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13302 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13303 | (const_int 0))) | |
13304 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13305 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 13306 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13307 | [(set (match_dup 0) |
13308 | (gtu:DI (match_dup 1) (match_dup 2))) | |
13309 | (set (match_dup 3) | |
13310 | (compare:CC (match_dup 0) | |
13311 | (const_int 0)))] | |
13312 | "") | |
f9562f27 | 13313 | |
c0600ecd | 13314 | (define_insn_and_split "" |
04fa46cf | 13315 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
c0600ecd DE |
13316 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
13317 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
13318 | (match_operand:SI 3 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13319 | "TARGET_32BIT" |
c0600ecd | 13320 | "#" |
04fa46cf | 13321 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" |
c0600ecd DE |
13322 | [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2)))) |
13323 | (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))] | |
13324 | "") | |
1fd4e8c1 | 13325 | |
c0600ecd | 13326 | (define_insn_and_split "" |
04fa46cf | 13327 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
c0600ecd DE |
13328 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
13329 | (match_operand:DI 2 "reg_or_short_operand" "rI")) | |
13330 | (match_operand:DI 3 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13331 | "TARGET_64BIT" |
c0600ecd | 13332 | "#" |
04fa46cf | 13333 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" |
c0600ecd DE |
13334 | [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2)))) |
13335 | (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))] | |
13336 | "") | |
f9562f27 | 13337 | |
1fd4e8c1 | 13338 | (define_insn "" |
9ebbca7d | 13339 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13340 | (compare:CC |
9ebbca7d GK |
13341 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13342 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13343 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13344 | (const_int 0))) |
9ebbca7d | 13345 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13346 | "TARGET_32BIT" |
00751805 | 13347 | "@ |
19378cf8 | 13348 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
c9dbf840 | 13349 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 |
9ebbca7d GK |
13350 | # |
13351 | #" | |
b19003d8 | 13352 | [(set_attr "type" "compare") |
9ebbca7d GK |
13353 | (set_attr "length" "8,12,12,16")]) |
13354 | ||
13355 | (define_split | |
13356 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13357 | (compare:CC | |
13358 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13359 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13360 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13361 | (const_int 0))) | |
13362 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 13363 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13364 | [(set (match_dup 4) |
13365 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 13366 | (match_dup 3))) |
9ebbca7d GK |
13367 | (set (match_dup 0) |
13368 | (compare:CC (match_dup 4) | |
13369 | (const_int 0)))] | |
13370 | "") | |
1fd4e8c1 | 13371 | |
f9562f27 | 13372 | (define_insn "" |
9ebbca7d | 13373 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13374 | (compare:CC |
9ebbca7d GK |
13375 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13376 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13377 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13378 | (const_int 0))) |
9ebbca7d | 13379 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13380 | "TARGET_64BIT" |
f9562f27 DE |
13381 | "@ |
13382 | addic %4,%1,%k2\;addze. %4,%3 | |
c9dbf840 | 13383 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3 |
9ebbca7d GK |
13384 | # |
13385 | #" | |
f9562f27 | 13386 | [(set_attr "type" "compare") |
9ebbca7d GK |
13387 | (set_attr "length" "8,12,12,16")]) |
13388 | ||
13389 | (define_split | |
13390 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13391 | (compare:CC | |
13392 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13393 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13394 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13395 | (const_int 0))) | |
13396 | (clobber (match_scratch:DI 4 ""))] | |
683bdff7 | 13397 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13398 | [(set (match_dup 4) |
13399 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
13400 | (match_dup 3))) | |
13401 | (set (match_dup 0) | |
13402 | (compare:CC (match_dup 4) | |
13403 | (const_int 0)))] | |
13404 | "") | |
f9562f27 | 13405 | |
1fd4e8c1 | 13406 | (define_insn "" |
097657c3 | 13407 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13408 | (compare:CC |
9ebbca7d GK |
13409 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13410 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13411 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13412 | (const_int 0))) |
097657c3 AM |
13413 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13414 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 13415 | "TARGET_32BIT" |
00751805 | 13416 | "@ |
097657c3 | 13417 | {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 |
c9dbf840 | 13418 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 |
9ebbca7d GK |
13419 | # |
13420 | #" | |
b19003d8 | 13421 | [(set_attr "type" "compare") |
9ebbca7d GK |
13422 | (set_attr "length" "8,12,12,16")]) |
13423 | ||
13424 | (define_split | |
097657c3 | 13425 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13426 | (compare:CC |
13427 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13428 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13429 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13430 | (const_int 0))) | |
13431 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13432 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 13433 | "TARGET_32BIT && reload_completed" |
097657c3 | 13434 | [(set (match_dup 0) |
9ebbca7d | 13435 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13436 | (set (match_dup 4) |
9ebbca7d GK |
13437 | (compare:CC (match_dup 0) |
13438 | (const_int 0)))] | |
13439 | "") | |
1fd4e8c1 | 13440 | |
f9562f27 | 13441 | (define_insn "" |
097657c3 | 13442 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13443 | (compare:CC |
9ebbca7d GK |
13444 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13445 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13446 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13447 | (const_int 0))) |
097657c3 AM |
13448 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13449 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 13450 | "TARGET_64BIT" |
f9562f27 | 13451 | "@ |
097657c3 | 13452 | addic %0,%1,%k2\;addze. %0,%3 |
c9dbf840 | 13453 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3 |
9ebbca7d GK |
13454 | # |
13455 | #" | |
f9562f27 | 13456 | [(set_attr "type" "compare") |
9ebbca7d GK |
13457 | (set_attr "length" "8,12,12,16")]) |
13458 | ||
13459 | (define_split | |
097657c3 | 13460 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13461 | (compare:CC |
13462 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13463 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13464 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13465 | (const_int 0))) | |
13466 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13467 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 13468 | "TARGET_64BIT && reload_completed" |
097657c3 | 13469 | [(set (match_dup 0) |
9ebbca7d | 13470 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13471 | (set (match_dup 4) |
9ebbca7d GK |
13472 | (compare:CC (match_dup 0) |
13473 | (const_int 0)))] | |
13474 | "") | |
f9562f27 | 13475 | |
1fd4e8c1 | 13476 | (define_insn "" |
cd2b37d9 RK |
13477 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13478 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13479 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
683bdff7 | 13480 | "TARGET_32BIT" |
ca7f5001 | 13481 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
943c15ed | 13482 | [(set_attr "type" "two") |
c0600ecd | 13483 | (set_attr "length" "8")]) |
f9562f27 DE |
13484 | |
13485 | (define_insn "" | |
13486 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13487 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13488 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
683bdff7 | 13489 | "TARGET_64BIT" |
f9562f27 | 13490 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" |
943c15ed | 13491 | [(set_attr "type" "two") |
c0600ecd | 13492 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
13493 | \f |
13494 | ;; Define both directions of branch and return. If we need a reload | |
13495 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
13496 | ;; register CC value to there. | |
13497 | ||
13498 | (define_insn "" | |
13499 | [(set (pc) | |
13500 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13501 | [(match_operand 2 | |
b54cf83a | 13502 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13503 | (const_int 0)]) |
13504 | (label_ref (match_operand 0 "" "")) | |
13505 | (pc)))] | |
13506 | "" | |
b19003d8 RK |
13507 | "* |
13508 | { | |
12a4e8c5 | 13509 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
13510 | }" |
13511 | [(set_attr "type" "branch")]) | |
13512 | ||
1fd4e8c1 RK |
13513 | (define_insn "" |
13514 | [(set (pc) | |
13515 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13516 | [(match_operand 1 | |
b54cf83a | 13517 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13518 | (const_int 0)]) |
13519 | (return) | |
13520 | (pc)))] | |
13521 | "direct_return ()" | |
12a4e8c5 GK |
13522 | "* |
13523 | { | |
13524 | return output_cbranch (operands[0], NULL, 0, insn); | |
13525 | }" | |
b7ff3d82 | 13526 | [(set_attr "type" "branch") |
39a10a29 | 13527 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
13528 | |
13529 | (define_insn "" | |
13530 | [(set (pc) | |
13531 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13532 | [(match_operand 2 | |
b54cf83a | 13533 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13534 | (const_int 0)]) |
13535 | (pc) | |
13536 | (label_ref (match_operand 0 "" ""))))] | |
13537 | "" | |
b19003d8 RK |
13538 | "* |
13539 | { | |
12a4e8c5 | 13540 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
13541 | }" |
13542 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13543 | |
13544 | (define_insn "" | |
13545 | [(set (pc) | |
13546 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13547 | [(match_operand 1 | |
b54cf83a | 13548 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13549 | (const_int 0)]) |
13550 | (pc) | |
13551 | (return)))] | |
13552 | "direct_return ()" | |
12a4e8c5 GK |
13553 | "* |
13554 | { | |
13555 | return output_cbranch (operands[0], NULL, 1, insn); | |
13556 | }" | |
b7ff3d82 | 13557 | [(set_attr "type" "branch") |
39a10a29 GK |
13558 | (set_attr "length" "4")]) |
13559 | ||
13560 | ;; Logic on condition register values. | |
13561 | ||
13562 | ; This pattern matches things like | |
13563 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
13564 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
13565 | ; (const_int 1))) | |
13566 | ; which are generated by the branch logic. | |
b54cf83a | 13567 | ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB) |
39a10a29 | 13568 | |
423c1189 | 13569 | (define_insn "*cceq_ior_compare" |
b54cf83a | 13570 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13571 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" |
b54cf83a | 13572 | [(match_operator:SI 2 |
39a10a29 GK |
13573 | "branch_positive_comparison_operator" |
13574 | [(match_operand 3 | |
b54cf83a | 13575 | "cc_reg_operand" "y,y") |
39a10a29 | 13576 | (const_int 0)]) |
b54cf83a | 13577 | (match_operator:SI 4 |
39a10a29 GK |
13578 | "branch_positive_comparison_operator" |
13579 | [(match_operand 5 | |
b54cf83a | 13580 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13581 | (const_int 0)])]) |
13582 | (const_int 1)))] | |
24fab1d3 | 13583 | "" |
39a10a29 | 13584 | "cr%q1 %E0,%j2,%j4" |
b54cf83a | 13585 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13586 | |
13587 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
13588 | ; Because ~1 has all but the low bit set. | |
13589 | (define_insn "" | |
b54cf83a | 13590 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13591 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" |
b54cf83a | 13592 | [(not:SI (match_operator:SI 2 |
39a10a29 GK |
13593 | "branch_positive_comparison_operator" |
13594 | [(match_operand 3 | |
b54cf83a | 13595 | "cc_reg_operand" "y,y") |
39a10a29 GK |
13596 | (const_int 0)])) |
13597 | (match_operator:SI 4 | |
13598 | "branch_positive_comparison_operator" | |
13599 | [(match_operand 5 | |
b54cf83a | 13600 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13601 | (const_int 0)])]) |
13602 | (const_int -1)))] | |
13603 | "" | |
13604 | "cr%q1 %E0,%j2,%j4" | |
b54cf83a | 13605 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 | 13606 | |
423c1189 | 13607 | (define_insn "*cceq_rev_compare" |
b54cf83a | 13608 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
6c873122 | 13609 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 13610 | "branch_positive_comparison_operator" |
6c873122 | 13611 | [(match_operand 2 |
b54cf83a | 13612 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13613 | (const_int 0)]) |
13614 | (const_int 0)))] | |
423c1189 | 13615 | "" |
251b3667 | 13616 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
b54cf83a | 13617 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13618 | |
13619 | ;; If we are comparing the result of two comparisons, this can be done | |
13620 | ;; using creqv or crxor. | |
13621 | ||
13622 | (define_insn_and_split "" | |
13623 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
13624 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
13625 | [(match_operand 2 "cc_reg_operand" "y") | |
13626 | (const_int 0)]) | |
13627 | (match_operator 3 "branch_comparison_operator" | |
13628 | [(match_operand 4 "cc_reg_operand" "y") | |
13629 | (const_int 0)])))] | |
13630 | "" | |
13631 | "#" | |
13632 | "" | |
13633 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
13634 | (match_dup 5)))] | |
13635 | " | |
13636 | { | |
13637 | int positive_1, positive_2; | |
13638 | ||
364849ee DE |
13639 | positive_1 = branch_positive_comparison_operator (operands[1], |
13640 | GET_MODE (operands[1])); | |
13641 | positive_2 = branch_positive_comparison_operator (operands[3], | |
13642 | GET_MODE (operands[3])); | |
39a10a29 GK |
13643 | |
13644 | if (! positive_1) | |
1c563bed | 13645 | operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]), |
0f4c242b KH |
13646 | GET_CODE (operands[1])), |
13647 | SImode, | |
13648 | operands[2], const0_rtx); | |
39a10a29 | 13649 | else if (GET_MODE (operands[1]) != SImode) |
0f4c242b KH |
13650 | operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, |
13651 | operands[2], const0_rtx); | |
39a10a29 GK |
13652 | |
13653 | if (! positive_2) | |
1c563bed | 13654 | operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]), |
0f4c242b KH |
13655 | GET_CODE (operands[3])), |
13656 | SImode, | |
13657 | operands[4], const0_rtx); | |
39a10a29 | 13658 | else if (GET_MODE (operands[3]) != SImode) |
0f4c242b KH |
13659 | operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
13660 | operands[4], const0_rtx); | |
39a10a29 GK |
13661 | |
13662 | if (positive_1 == positive_2) | |
251b3667 DE |
13663 | { |
13664 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
13665 | operands[5] = constm1_rtx; | |
13666 | } | |
13667 | else | |
13668 | { | |
13669 | operands[5] = const1_rtx; | |
13670 | } | |
39a10a29 | 13671 | }") |
1fd4e8c1 RK |
13672 | |
13673 | ;; Unconditional branch and return. | |
13674 | ||
13675 | (define_insn "jump" | |
13676 | [(set (pc) | |
13677 | (label_ref (match_operand 0 "" "")))] | |
13678 | "" | |
b7ff3d82 DE |
13679 | "b %l0" |
13680 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13681 | |
13682 | (define_insn "return" | |
13683 | [(return)] | |
13684 | "direct_return ()" | |
324e52cc TG |
13685 | "{br|blr}" |
13686 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 13687 | |
0ad91047 DE |
13688 | (define_expand "indirect_jump" |
13689 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 13690 | "" |
0ad91047 DE |
13691 | " |
13692 | { | |
13693 | if (TARGET_32BIT) | |
13694 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
13695 | else | |
13696 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
13697 | DONE; | |
13698 | }") | |
13699 | ||
13700 | (define_insn "indirect_jumpsi" | |
b92b324d | 13701 | [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))] |
0ad91047 | 13702 | "TARGET_32BIT" |
b92b324d DE |
13703 | "@ |
13704 | bctr | |
13705 | {br|blr}" | |
324e52cc | 13706 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13707 | |
0ad91047 | 13708 | (define_insn "indirect_jumpdi" |
b92b324d | 13709 | [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))] |
0ad91047 | 13710 | "TARGET_64BIT" |
b92b324d DE |
13711 | "@ |
13712 | bctr | |
13713 | blr" | |
266eb58a DE |
13714 | [(set_attr "type" "jmpreg")]) |
13715 | ||
1fd4e8c1 RK |
13716 | ;; Table jump for switch statements: |
13717 | (define_expand "tablejump" | |
e6ca2c17 DE |
13718 | [(use (match_operand 0 "" "")) |
13719 | (use (label_ref (match_operand 1 "" "")))] | |
13720 | "" | |
13721 | " | |
13722 | { | |
13723 | if (TARGET_32BIT) | |
13724 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
13725 | else | |
13726 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
13727 | DONE; | |
13728 | }") | |
13729 | ||
13730 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
13731 | [(set (match_dup 3) |
13732 | (plus:SI (match_operand:SI 0 "" "") | |
13733 | (match_dup 2))) | |
13734 | (parallel [(set (pc) (match_dup 3)) | |
13735 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13736 | "TARGET_32BIT" |
1fd4e8c1 RK |
13737 | " |
13738 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 13739 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
13740 | operands[3] = gen_reg_rtx (SImode); |
13741 | }") | |
13742 | ||
e6ca2c17 | 13743 | (define_expand "tablejumpdi" |
6ae08853 | 13744 | [(set (match_dup 4) |
9ebbca7d GK |
13745 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) |
13746 | (set (match_dup 3) | |
13747 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
13748 | (match_dup 2))) |
13749 | (parallel [(set (pc) (match_dup 3)) | |
13750 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13751 | "TARGET_64BIT" |
e6ca2c17 | 13752 | " |
9ebbca7d | 13753 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 13754 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 13755 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
13756 | }") |
13757 | ||
1fd4e8c1 RK |
13758 | (define_insn "" |
13759 | [(set (pc) | |
c859cda6 | 13760 | (match_operand:SI 0 "register_operand" "c,*l")) |
1fd4e8c1 | 13761 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13762 | "TARGET_32BIT" |
c859cda6 DJ |
13763 | "@ |
13764 | bctr | |
13765 | {br|blr}" | |
a6845123 | 13766 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13767 | |
266eb58a DE |
13768 | (define_insn "" |
13769 | [(set (pc) | |
c859cda6 | 13770 | (match_operand:DI 0 "register_operand" "c,*l")) |
266eb58a | 13771 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13772 | "TARGET_64BIT" |
c859cda6 DJ |
13773 | "@ |
13774 | bctr | |
13775 | blr" | |
266eb58a DE |
13776 | [(set_attr "type" "jmpreg")]) |
13777 | ||
1fd4e8c1 RK |
13778 | (define_insn "nop" |
13779 | [(const_int 0)] | |
13780 | "" | |
ca7f5001 | 13781 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 13782 | \f |
7e69e155 | 13783 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
13784 | ;; so loop.c knows what to generate. |
13785 | ||
5527bf14 RH |
13786 | (define_expand "doloop_end" |
13787 | [(use (match_operand 0 "" "")) ; loop pseudo | |
13788 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
13789 | (use (match_operand 2 "" "")) ; max iterations | |
13790 | (use (match_operand 3 "" "")) ; loop level | |
13791 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
13792 | "" |
13793 | " | |
13794 | { | |
5527bf14 RH |
13795 | /* Only use this on innermost loops. */ |
13796 | if (INTVAL (operands[3]) > 1) | |
13797 | FAIL; | |
683bdff7 | 13798 | if (TARGET_64BIT) |
5527bf14 RH |
13799 | { |
13800 | if (GET_MODE (operands[0]) != DImode) | |
13801 | FAIL; | |
13802 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
13803 | } | |
0ad91047 | 13804 | else |
5527bf14 RH |
13805 | { |
13806 | if (GET_MODE (operands[0]) != SImode) | |
13807 | FAIL; | |
13808 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
13809 | } | |
0ad91047 DE |
13810 | DONE; |
13811 | }") | |
13812 | ||
13813 | (define_expand "ctrsi" | |
3cb999d8 DE |
13814 | [(parallel [(set (pc) |
13815 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
13816 | (const_int 1)) | |
13817 | (label_ref (match_operand 1 "" "")) | |
13818 | (pc))) | |
b6c9286a MM |
13819 | (set (match_dup 0) |
13820 | (plus:SI (match_dup 0) | |
13821 | (const_int -1))) | |
5f81043f RK |
13822 | (clobber (match_scratch:CC 2 "")) |
13823 | (clobber (match_scratch:SI 3 ""))])] | |
683bdff7 | 13824 | "TARGET_32BIT" |
0ad91047 DE |
13825 | "") |
13826 | ||
13827 | (define_expand "ctrdi" | |
3cb999d8 DE |
13828 | [(parallel [(set (pc) |
13829 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
13830 | (const_int 1)) | |
13831 | (label_ref (match_operand 1 "" "")) | |
13832 | (pc))) | |
0ad91047 DE |
13833 | (set (match_dup 0) |
13834 | (plus:DI (match_dup 0) | |
13835 | (const_int -1))) | |
13836 | (clobber (match_scratch:CC 2 "")) | |
61c07d3c | 13837 | (clobber (match_scratch:DI 3 ""))])] |
683bdff7 | 13838 | "TARGET_64BIT" |
61c07d3c | 13839 | "") |
c225ba7b | 13840 | |
1fd4e8c1 RK |
13841 | ;; We need to be able to do this for any operand, including MEM, or we |
13842 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 13843 | ;; JUMP_INSNs. |
0ad91047 | 13844 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
13845 | ;; label MUST be operand 0. |
13846 | ||
0ad91047 | 13847 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 13848 | [(set (pc) |
43b68ce5 | 13849 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
1fd4e8c1 | 13850 | (const_int 1)) |
a6845123 | 13851 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13852 | (pc))) |
b150f4f3 | 13853 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
13854 | (plus:SI (match_dup 1) |
13855 | (const_int -1))) | |
43b68ce5 DE |
13856 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
13857 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 13858 | "TARGET_32BIT" |
b19003d8 RK |
13859 | "* |
13860 | { | |
af87a13e | 13861 | if (which_alternative != 0) |
b19003d8 | 13862 | return \"#\"; |
856a6884 | 13863 | else if (get_attr_length (insn) == 4) |
a6845123 | 13864 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 13865 | else |
f607bc57 | 13866 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 13867 | }" |
baf97f86 | 13868 | [(set_attr "type" "branch") |
5a195cb5 | 13869 | (set_attr "length" "*,12,16,16")]) |
7e69e155 | 13870 | |
0ad91047 | 13871 | (define_insn "*ctrsi_internal2" |
5f81043f | 13872 | [(set (pc) |
43b68ce5 | 13873 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
5f81043f RK |
13874 | (const_int 1)) |
13875 | (pc) | |
13876 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 13877 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
13878 | (plus:SI (match_dup 1) |
13879 | (const_int -1))) | |
43b68ce5 DE |
13880 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
13881 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 13882 | "TARGET_32BIT" |
0ad91047 DE |
13883 | "* |
13884 | { | |
13885 | if (which_alternative != 0) | |
13886 | return \"#\"; | |
856a6884 | 13887 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13888 | return \"bdz %l0\"; |
13889 | else | |
f607bc57 | 13890 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
13891 | }" |
13892 | [(set_attr "type" "branch") | |
5a195cb5 | 13893 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
13894 | |
13895 | (define_insn "*ctrdi_internal1" | |
13896 | [(set (pc) | |
43b68ce5 | 13897 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
13898 | (const_int 1)) |
13899 | (label_ref (match_operand 0 "" "")) | |
13900 | (pc))) | |
b150f4f3 | 13901 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
13902 | (plus:DI (match_dup 1) |
13903 | (const_int -1))) | |
43b68ce5 DE |
13904 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
13905 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 13906 | "TARGET_64BIT" |
0ad91047 DE |
13907 | "* |
13908 | { | |
13909 | if (which_alternative != 0) | |
13910 | return \"#\"; | |
856a6884 | 13911 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13912 | return \"{bdn|bdnz} %l0\"; |
13913 | else | |
f607bc57 | 13914 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
13915 | }" |
13916 | [(set_attr "type" "branch") | |
5a195cb5 | 13917 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
13918 | |
13919 | (define_insn "*ctrdi_internal2" | |
13920 | [(set (pc) | |
43b68ce5 | 13921 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
13922 | (const_int 1)) |
13923 | (pc) | |
13924 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 13925 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
13926 | (plus:DI (match_dup 1) |
13927 | (const_int -1))) | |
43b68ce5 DE |
13928 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
13929 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 13930 | "TARGET_64BIT" |
5f81043f RK |
13931 | "* |
13932 | { | |
13933 | if (which_alternative != 0) | |
13934 | return \"#\"; | |
856a6884 | 13935 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
13936 | return \"bdz %l0\"; |
13937 | else | |
f607bc57 | 13938 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
13939 | }" |
13940 | [(set_attr "type" "branch") | |
5a195cb5 | 13941 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 13942 | |
0ad91047 DE |
13943 | ;; Similar but use EQ |
13944 | ||
13945 | (define_insn "*ctrsi_internal5" | |
5f81043f | 13946 | [(set (pc) |
43b68ce5 | 13947 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
1fd4e8c1 | 13948 | (const_int 1)) |
a6845123 | 13949 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13950 | (pc))) |
b150f4f3 | 13951 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
13952 | (plus:SI (match_dup 1) |
13953 | (const_int -1))) | |
43b68ce5 DE |
13954 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
13955 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 13956 | "TARGET_32BIT" |
b19003d8 RK |
13957 | "* |
13958 | { | |
af87a13e | 13959 | if (which_alternative != 0) |
b19003d8 | 13960 | return \"#\"; |
856a6884 | 13961 | else if (get_attr_length (insn) == 4) |
a6845123 | 13962 | return \"bdz %l0\"; |
b19003d8 | 13963 | else |
f607bc57 | 13964 | return \"{bdn|bdnz} $+8\;b %l0\"; |
b19003d8 | 13965 | }" |
baf97f86 | 13966 | [(set_attr "type" "branch") |
5a195cb5 | 13967 | (set_attr "length" "*,12,16,16")]) |
1fd4e8c1 | 13968 | |
0ad91047 | 13969 | (define_insn "*ctrsi_internal6" |
5f81043f | 13970 | [(set (pc) |
43b68ce5 | 13971 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
5f81043f RK |
13972 | (const_int 1)) |
13973 | (pc) | |
13974 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 13975 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
13976 | (plus:SI (match_dup 1) |
13977 | (const_int -1))) | |
43b68ce5 DE |
13978 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
13979 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 13980 | "TARGET_32BIT" |
0ad91047 DE |
13981 | "* |
13982 | { | |
13983 | if (which_alternative != 0) | |
13984 | return \"#\"; | |
856a6884 | 13985 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13986 | return \"{bdn|bdnz} %l0\"; |
13987 | else | |
f607bc57 | 13988 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
13989 | }" |
13990 | [(set_attr "type" "branch") | |
5a195cb5 | 13991 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
13992 | |
13993 | (define_insn "*ctrdi_internal5" | |
13994 | [(set (pc) | |
43b68ce5 | 13995 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
13996 | (const_int 1)) |
13997 | (label_ref (match_operand 0 "" "")) | |
13998 | (pc))) | |
b150f4f3 | 13999 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14000 | (plus:DI (match_dup 1) |
14001 | (const_int -1))) | |
43b68ce5 DE |
14002 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14003 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14004 | "TARGET_64BIT" |
0ad91047 DE |
14005 | "* |
14006 | { | |
14007 | if (which_alternative != 0) | |
14008 | return \"#\"; | |
856a6884 | 14009 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14010 | return \"bdz %l0\"; |
14011 | else | |
f607bc57 | 14012 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14013 | }" |
14014 | [(set_attr "type" "branch") | |
5a195cb5 | 14015 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14016 | |
14017 | (define_insn "*ctrdi_internal6" | |
14018 | [(set (pc) | |
43b68ce5 | 14019 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14020 | (const_int 1)) |
14021 | (pc) | |
14022 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14023 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14024 | (plus:DI (match_dup 1) |
14025 | (const_int -1))) | |
43b68ce5 DE |
14026 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14027 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14028 | "TARGET_64BIT" |
5f81043f RK |
14029 | "* |
14030 | { | |
14031 | if (which_alternative != 0) | |
14032 | return \"#\"; | |
856a6884 | 14033 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14034 | return \"{bdn|bdnz} %l0\"; |
14035 | else | |
f607bc57 | 14036 | return \"bdz $+8\;b %l0\"; |
5f81043f RK |
14037 | }" |
14038 | [(set_attr "type" "branch") | |
5a195cb5 | 14039 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 14040 | |
0ad91047 DE |
14041 | ;; Now the splitters if we could not allocate the CTR register |
14042 | ||
1fd4e8c1 RK |
14043 | (define_split |
14044 | [(set (pc) | |
14045 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14046 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14047 | (const_int 1)]) |
14048 | (match_operand 5 "" "") | |
14049 | (match_operand 6 "" ""))) | |
cd2b37d9 | 14050 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
14051 | (plus:SI (match_dup 1) |
14052 | (const_int -1))) | |
1fd4e8c1 RK |
14053 | (clobber (match_scratch:CC 3 "")) |
14054 | (clobber (match_scratch:SI 4 ""))] | |
4b8a63d6 | 14055 | "TARGET_32BIT && reload_completed" |
1fd4e8c1 | 14056 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14057 | (compare:CC (plus:SI (match_dup 1) |
14058 | (const_int -1)) | |
1fd4e8c1 | 14059 | (const_int 0))) |
5f81043f RK |
14060 | (set (match_dup 0) |
14061 | (plus:SI (match_dup 1) | |
14062 | (const_int -1)))]) | |
14063 | (set (pc) (if_then_else (match_dup 7) | |
14064 | (match_dup 5) | |
14065 | (match_dup 6)))] | |
1fd4e8c1 | 14066 | " |
0f4c242b KH |
14067 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14068 | operands[3], const0_rtx); }") | |
1fd4e8c1 RK |
14069 | |
14070 | (define_split | |
14071 | [(set (pc) | |
14072 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14073 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14074 | (const_int 1)]) |
14075 | (match_operand 5 "" "") | |
14076 | (match_operand 6 "" ""))) | |
9ebbca7d | 14077 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
14078 | (plus:SI (match_dup 1) (const_int -1))) |
14079 | (clobber (match_scratch:CC 3 "")) | |
14080 | (clobber (match_scratch:SI 4 ""))] | |
4b8a63d6 | 14081 | "TARGET_32BIT && reload_completed |
0ad91047 | 14082 | && ! gpc_reg_operand (operands[0], SImode)" |
1fd4e8c1 | 14083 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14084 | (compare:CC (plus:SI (match_dup 1) |
14085 | (const_int -1)) | |
1fd4e8c1 | 14086 | (const_int 0))) |
5f81043f RK |
14087 | (set (match_dup 4) |
14088 | (plus:SI (match_dup 1) | |
14089 | (const_int -1)))]) | |
14090 | (set (match_dup 0) | |
14091 | (match_dup 4)) | |
14092 | (set (pc) (if_then_else (match_dup 7) | |
14093 | (match_dup 5) | |
14094 | (match_dup 6)))] | |
1fd4e8c1 | 14095 | " |
0f4c242b KH |
14096 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14097 | operands[3], const0_rtx); }") | |
0ad91047 DE |
14098 | (define_split |
14099 | [(set (pc) | |
14100 | (if_then_else (match_operator 2 "comparison_operator" | |
14101 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14102 | (const_int 1)]) | |
61c07d3c DE |
14103 | (match_operand 5 "" "") |
14104 | (match_operand 6 "" ""))) | |
0ad91047 DE |
14105 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
14106 | (plus:DI (match_dup 1) | |
14107 | (const_int -1))) | |
14108 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 14109 | (clobber (match_scratch:DI 4 ""))] |
683bdff7 | 14110 | "TARGET_64BIT && reload_completed" |
0ad91047 DE |
14111 | [(parallel [(set (match_dup 3) |
14112 | (compare:CC (plus:DI (match_dup 1) | |
14113 | (const_int -1)) | |
14114 | (const_int 0))) | |
14115 | (set (match_dup 0) | |
14116 | (plus:DI (match_dup 1) | |
14117 | (const_int -1)))]) | |
61c07d3c DE |
14118 | (set (pc) (if_then_else (match_dup 7) |
14119 | (match_dup 5) | |
14120 | (match_dup 6)))] | |
0ad91047 | 14121 | " |
0f4c242b KH |
14122 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14123 | operands[3], const0_rtx); }") | |
0ad91047 DE |
14124 | |
14125 | (define_split | |
14126 | [(set (pc) | |
14127 | (if_then_else (match_operator 2 "comparison_operator" | |
14128 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14129 | (const_int 1)]) | |
61c07d3c DE |
14130 | (match_operand 5 "" "") |
14131 | (match_operand 6 "" ""))) | |
9ebbca7d | 14132 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
14133 | (plus:DI (match_dup 1) (const_int -1))) |
14134 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 14135 | (clobber (match_scratch:DI 4 ""))] |
683bdff7 | 14136 | "TARGET_64BIT && reload_completed |
0ad91047 DE |
14137 | && ! gpc_reg_operand (operands[0], DImode)" |
14138 | [(parallel [(set (match_dup 3) | |
14139 | (compare:CC (plus:DI (match_dup 1) | |
14140 | (const_int -1)) | |
14141 | (const_int 0))) | |
14142 | (set (match_dup 4) | |
14143 | (plus:DI (match_dup 1) | |
14144 | (const_int -1)))]) | |
14145 | (set (match_dup 0) | |
14146 | (match_dup 4)) | |
61c07d3c DE |
14147 | (set (pc) (if_then_else (match_dup 7) |
14148 | (match_dup 5) | |
14149 | (match_dup 6)))] | |
0ad91047 | 14150 | " |
0f4c242b KH |
14151 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14152 | operands[3], const0_rtx); }") | |
e0cd0770 JC |
14153 | \f |
14154 | (define_insn "trap" | |
14155 | [(trap_if (const_int 1) (const_int 0))] | |
14156 | "" | |
14157 | "{t 31,0,0|trap}") | |
14158 | ||
14159 | (define_expand "conditional_trap" | |
14160 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14161 | [(match_dup 2) (match_dup 3)]) | |
14162 | (match_operand 1 "const_int_operand" ""))] | |
14163 | "" | |
14164 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
14165 | operands[2] = rs6000_compare_op0; | |
14166 | operands[3] = rs6000_compare_op1;") | |
14167 | ||
14168 | (define_insn "" | |
14169 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14170 | [(match_operand:SI 1 "register_operand" "r") | |
14171 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
14172 | (const_int 0))] | |
14173 | "" | |
a157febd GK |
14174 | "{t|tw}%V0%I2 %1,%2") |
14175 | ||
14176 | (define_insn "" | |
14177 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14178 | [(match_operand:DI 1 "register_operand" "r") | |
14179 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
14180 | (const_int 0))] | |
14181 | "TARGET_POWERPC64" | |
14182 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
14183 | \f |
14184 | ;; Insns related to generating the function prologue and epilogue. | |
14185 | ||
14186 | (define_expand "prologue" | |
14187 | [(use (const_int 0))] | |
14188 | "TARGET_SCHED_PROLOG" | |
14189 | " | |
14190 | { | |
14191 | rs6000_emit_prologue (); | |
14192 | DONE; | |
14193 | }") | |
14194 | ||
2c4a9cff DE |
14195 | (define_insn "*movesi_from_cr_one" |
14196 | [(match_parallel 0 "mfcr_operation" | |
14197 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14198 | (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y") | |
14199 | (match_operand 3 "immediate_operand" "n")] | |
14200 | UNSPEC_MOVESI_FROM_CR))])] | |
14201 | "TARGET_MFCRF" | |
14202 | "* | |
14203 | { | |
14204 | int mask = 0; | |
14205 | int i; | |
14206 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14207 | { | |
14208 | mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14209 | operands[4] = GEN_INT (mask); | |
14210 | output_asm_insn (\"mfcr %1,%4\", operands); | |
14211 | } | |
14212 | return \"\"; | |
14213 | }" | |
14214 | [(set_attr "type" "mfcrf")]) | |
14215 | ||
9ebbca7d GK |
14216 | (define_insn "movesi_from_cr" |
14217 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 14218 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) |
615158e2 JJ |
14219 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] |
14220 | UNSPEC_MOVESI_FROM_CR))] | |
9ebbca7d | 14221 | "" |
309323c2 | 14222 | "mfcr %0" |
b54cf83a | 14223 | [(set_attr "type" "mfcr")]) |
9ebbca7d GK |
14224 | |
14225 | (define_insn "*stmw" | |
e033a023 DE |
14226 | [(match_parallel 0 "stmw_operation" |
14227 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
14228 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
14229 | "TARGET_MULTIPLE" | |
14230 | "{stm|stmw} %2,%1") | |
6ae08853 | 14231 | |
9ebbca7d | 14232 | (define_insn "*save_fpregs_si" |
85d346f1 | 14233 | [(match_parallel 0 "any_parallel_operand" |
e033a023 DE |
14234 | [(clobber (match_operand:SI 1 "register_operand" "=l")) |
14235 | (use (match_operand:SI 2 "call_operand" "s")) | |
14236 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14237 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14238 | "TARGET_32BIT" | |
14239 | "bl %z2" | |
14240 | [(set_attr "type" "branch") | |
14241 | (set_attr "length" "4")]) | |
9ebbca7d GK |
14242 | |
14243 | (define_insn "*save_fpregs_di" | |
85d346f1 | 14244 | [(match_parallel 0 "any_parallel_operand" |
e033a023 DE |
14245 | [(clobber (match_operand:DI 1 "register_operand" "=l")) |
14246 | (use (match_operand:DI 2 "call_operand" "s")) | |
14247 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14248 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14249 | "TARGET_64BIT" | |
14250 | "bl %z2" | |
14251 | [(set_attr "type" "branch") | |
14252 | (set_attr "length" "4")]) | |
9ebbca7d GK |
14253 | |
14254 | ; These are to explain that changes to the stack pointer should | |
14255 | ; not be moved over stores to stack memory. | |
14256 | (define_insn "stack_tie" | |
14257 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
615158e2 | 14258 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] |
9ebbca7d GK |
14259 | "" |
14260 | "" | |
14261 | [(set_attr "length" "0")]) | |
14262 | ||
14263 | ||
14264 | (define_expand "epilogue" | |
14265 | [(use (const_int 0))] | |
14266 | "TARGET_SCHED_PROLOG" | |
14267 | " | |
14268 | { | |
14269 | rs6000_emit_epilogue (FALSE); | |
14270 | DONE; | |
14271 | }") | |
14272 | ||
14273 | ; On some processors, doing the mtcrf one CC register at a time is | |
14274 | ; faster (like on the 604e). On others, doing them all at once is | |
14275 | ; faster; for instance, on the 601 and 750. | |
14276 | ||
14277 | (define_expand "movsi_to_cr_one" | |
35aba846 DE |
14278 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14279 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 | 14280 | (match_dup 2)] UNSPEC_MOVESI_TO_CR))] |
35aba846 DE |
14281 | "" |
14282 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
9ebbca7d GK |
14283 | |
14284 | (define_insn "*movsi_to_cr" | |
35aba846 DE |
14285 | [(match_parallel 0 "mtcrf_operation" |
14286 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") | |
14287 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
14288 | (match_operand 3 "immediate_operand" "n")] | |
615158e2 | 14289 | UNSPEC_MOVESI_TO_CR))])] |
9ebbca7d | 14290 | "" |
e35b9579 GK |
14291 | "* |
14292 | { | |
14293 | int mask = 0; | |
14294 | int i; | |
14295 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14296 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14297 | operands[4] = GEN_INT (mask); | |
14298 | return \"mtcrf %4,%2\"; | |
309323c2 | 14299 | }" |
b54cf83a | 14300 | [(set_attr "type" "mtcr")]) |
9ebbca7d | 14301 | |
b54cf83a | 14302 | (define_insn "*mtcrfsi" |
309323c2 DE |
14303 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14304 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 JJ |
14305 | (match_operand 2 "immediate_operand" "n")] |
14306 | UNSPEC_MOVESI_TO_CR))] | |
6ae08853 | 14307 | "GET_CODE (operands[0]) == REG |
309323c2 DE |
14308 | && CR_REGNO_P (REGNO (operands[0])) |
14309 | && GET_CODE (operands[2]) == CONST_INT | |
14310 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
14311 | "mtcrf %R0,%1" | |
b54cf83a | 14312 | [(set_attr "type" "mtcr")]) |
9ebbca7d GK |
14313 | |
14314 | ; The load-multiple instructions have similar properties. | |
14315 | ; Note that "load_multiple" is a name known to the machine-independent | |
14316 | ; code that actually corresponds to the powerpc load-string. | |
14317 | ||
14318 | (define_insn "*lmw" | |
35aba846 DE |
14319 | [(match_parallel 0 "lmw_operation" |
14320 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14321 | (match_operand:SI 2 "memory_operand" "m"))])] | |
14322 | "TARGET_MULTIPLE" | |
14323 | "{lm|lmw} %1,%2") | |
6ae08853 | 14324 | |
9ebbca7d | 14325 | (define_insn "*return_internal_si" |
e35b9579 GK |
14326 | [(return) |
14327 | (use (match_operand:SI 0 "register_operand" "lc"))] | |
9ebbca7d | 14328 | "TARGET_32BIT" |
cccf3bdc | 14329 | "b%T0" |
9ebbca7d GK |
14330 | [(set_attr "type" "jmpreg")]) |
14331 | ||
14332 | (define_insn "*return_internal_di" | |
e35b9579 GK |
14333 | [(return) |
14334 | (use (match_operand:DI 0 "register_operand" "lc"))] | |
9ebbca7d | 14335 | "TARGET_64BIT" |
cccf3bdc | 14336 | "b%T0" |
9ebbca7d GK |
14337 | [(set_attr "type" "jmpreg")]) |
14338 | ||
14339 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
85d346f1 | 14340 | ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible... |
9ebbca7d GK |
14341 | |
14342 | (define_insn "*return_and_restore_fpregs_si" | |
85d346f1 | 14343 | [(match_parallel 0 "any_parallel_operand" |
e35b9579 GK |
14344 | [(return) |
14345 | (use (match_operand:SI 1 "register_operand" "l")) | |
9ebbca7d GK |
14346 | (use (match_operand:SI 2 "call_operand" "s")) |
14347 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14348 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14349 | "TARGET_32BIT" | |
14350 | "b %z2") | |
14351 | ||
14352 | (define_insn "*return_and_restore_fpregs_di" | |
85d346f1 | 14353 | [(match_parallel 0 "any_parallel_operand" |
e35b9579 GK |
14354 | [(return) |
14355 | (use (match_operand:DI 1 "register_operand" "l")) | |
9ebbca7d GK |
14356 | (use (match_operand:DI 2 "call_operand" "s")) |
14357 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14358 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14359 | "TARGET_64BIT" | |
14360 | "b %z2") | |
14361 | ||
83720594 RH |
14362 | ; This is used in compiling the unwind routines. |
14363 | (define_expand "eh_return" | |
34dc173c | 14364 | [(use (match_operand 0 "general_operand" ""))] |
9ebbca7d GK |
14365 | "" |
14366 | " | |
14367 | { | |
83720594 | 14368 | if (TARGET_32BIT) |
34dc173c | 14369 | emit_insn (gen_eh_set_lr_si (operands[0])); |
9ebbca7d | 14370 | else |
34dc173c | 14371 | emit_insn (gen_eh_set_lr_di (operands[0])); |
9ebbca7d GK |
14372 | DONE; |
14373 | }") | |
14374 | ||
83720594 RH |
14375 | ; We can't expand this before we know where the link register is stored. |
14376 | (define_insn "eh_set_lr_si" | |
615158e2 JJ |
14377 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] |
14378 | UNSPECV_EH_RR) | |
466eb3e0 | 14379 | (clobber (match_scratch:SI 1 "=&b"))] |
83720594 RH |
14380 | "TARGET_32BIT" |
14381 | "#") | |
14382 | ||
14383 | (define_insn "eh_set_lr_di" | |
615158e2 JJ |
14384 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
14385 | UNSPECV_EH_RR) | |
466eb3e0 | 14386 | (clobber (match_scratch:DI 1 "=&b"))] |
83720594 RH |
14387 | "TARGET_64BIT" |
14388 | "#") | |
9ebbca7d GK |
14389 | |
14390 | (define_split | |
615158e2 | 14391 | [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) |
83720594 RH |
14392 | (clobber (match_scratch 1 ""))] |
14393 | "reload_completed" | |
14394 | [(const_int 0)] | |
9ebbca7d GK |
14395 | " |
14396 | { | |
d1d0c603 | 14397 | rs6000_emit_eh_reg_restore (operands[0], operands[1]); |
83720594 RH |
14398 | DONE; |
14399 | }") | |
0ac081f6 | 14400 | |
01a2ccd0 DE |
14401 | (define_insn "prefetch" |
14402 | [(prefetch (match_operand:V4SI 0 "address_operand" "p") | |
6041bf2f DE |
14403 | (match_operand:SI 1 "const_int_operand" "n") |
14404 | (match_operand:SI 2 "const_int_operand" "n"))] | |
01a2ccd0 | 14405 | "TARGET_POWERPC" |
6041bf2f DE |
14406 | "* |
14407 | { | |
01a2ccd0 DE |
14408 | if (GET_CODE (operands[0]) == REG) |
14409 | return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; | |
14410 | return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; | |
6041bf2f DE |
14411 | }" |
14412 | [(set_attr "type" "load")]) | |
915167f5 GK |
14413 | \f |
14414 | ; Atomic instructions | |
14415 | ||
14416 | (define_insn "memory_barrier" | |
14417 | [(set (mem:BLK (match_scratch 0 "X")) | |
14418 | (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_SYNC))] | |
14419 | "" | |
14420 | "{ics|sync}") | |
14421 | ||
14422 | (define_insn "sync_compare_and_swap<mode>" | |
14423 | [(set (match_operand:GPR 1 "memory_operand" "+Z") | |
14424 | (unspec:GPR [(match_dup 1) | |
14425 | (match_operand:GPR 2 "reg_or_short_operand" "rI") | |
14426 | (match_operand:GPR 3 "gpc_reg_operand" "r")] | |
14427 | UNSPEC_SYNC_SWAP)) | |
14428 | (set (match_operand:GPR 0 "gpc_reg_operand" "=&r") (match_dup 1)) | |
14429 | (set (mem:BLK (match_scratch 5 "X")) | |
14430 | (unspec:BLK [(mem:BLK (match_scratch 6 "X"))] UNSPEC_SYNC)) | |
14431 | (clobber (match_scratch:CC 4 "=&x"))] | |
14432 | "TARGET_POWERPC" | |
0354e5d8 | 14433 | "sync\n\t<larx> %0,%y1\n\tcmp<wd>%I2 %0,%2\n\tbne- $+12\n\t<stcx> %3,%y1\n\tbne- $-16\n\tisync" |
915167f5 GK |
14434 | [(set_attr "length" "28")]) |
14435 | ||
14436 | (define_expand "sync_add<mode>" | |
14437 | [(use (match_operand:INT1 0 "memory_operand" "")) | |
14438 | (use (match_operand:INT1 1 "add_operand" ""))] | |
14439 | "TARGET_POWERPC" | |
14440 | " | |
14441 | { | |
14442 | rs6000_emit_sync (PLUS, <MODE>mode, operands[0], operands[1], | |
14443 | NULL_RTX, NULL_RTX, true); | |
14444 | DONE; | |
14445 | }") | |
14446 | ||
14447 | (define_expand "sync_sub<mode>" | |
14448 | [(use (match_operand:GPR 0 "memory_operand" "")) | |
14449 | (use (match_operand:GPR 1 "gpc_reg_operand" ""))] | |
14450 | "TARGET_POWERPC" | |
14451 | " | |
14452 | { | |
14453 | rs6000_emit_sync (MINUS, <MODE>mode, operands[0], operands[1], | |
14454 | NULL_RTX, NULL_RTX, true); | |
14455 | DONE; | |
14456 | }") | |
14457 | ||
14458 | (define_expand "sync_ior<mode>" | |
14459 | [(use (match_operand:INT1 0 "memory_operand" "")) | |
14460 | (use (match_operand:INT1 1 "logical_operand" ""))] | |
14461 | "TARGET_POWERPC" | |
14462 | " | |
14463 | { | |
14464 | rs6000_emit_sync (IOR, <MODE>mode, operands[0], operands[1], | |
14465 | NULL_RTX, NULL_RTX, true); | |
14466 | DONE; | |
14467 | }") | |
14468 | ||
14469 | (define_expand "sync_and<mode>" | |
14470 | [(use (match_operand:INT1 0 "memory_operand" "")) | |
14471 | (use (match_operand:INT1 1 "and_operand" ""))] | |
14472 | "TARGET_POWERPC" | |
14473 | " | |
14474 | { | |
14475 | rs6000_emit_sync (AND, <MODE>mode, operands[0], operands[1], | |
14476 | NULL_RTX, NULL_RTX, true); | |
14477 | DONE; | |
14478 | }") | |
14479 | ||
14480 | (define_expand "sync_xor<mode>" | |
14481 | [(use (match_operand:INT1 0 "memory_operand" "")) | |
14482 | (use (match_operand:INT1 1 "logical_operand" ""))] | |
14483 | "TARGET_POWERPC" | |
14484 | " | |
14485 | { | |
14486 | rs6000_emit_sync (XOR, <MODE>mode, operands[0], operands[1], | |
14487 | NULL_RTX, NULL_RTX, true); | |
14488 | DONE; | |
14489 | }") | |
14490 | ||
14491 | (define_expand "sync_nand<mode>" | |
14492 | [(use (match_operand:INT1 0 "memory_operand" "")) | |
14493 | (use (match_operand:INT1 1 "gpc_reg_operand" ""))] | |
14494 | "TARGET_POWERPC" | |
14495 | " | |
14496 | { | |
14497 | rs6000_emit_sync (AND, <MODE>mode, | |
14498 | gen_rtx_NOT (<MODE>mode, operands[0]), | |
14499 | operands[1], | |
14500 | NULL_RTX, NULL_RTX, true); | |
14501 | DONE; | |
14502 | }") | |
14503 | ||
14504 | (define_expand "sync_old_add<mode>" | |
14505 | [(use (match_operand:INT1 0 "gpc_reg_operand" "")) | |
14506 | (use (match_operand:INT1 1 "memory_operand" "")) | |
14507 | (use (match_operand:INT1 2 "add_operand" ""))] | |
14508 | "TARGET_POWERPC" | |
14509 | " | |
14510 | { | |
14511 | rs6000_emit_sync (PLUS, <MODE>mode, operands[1], operands[2], | |
14512 | operands[0], NULL_RTX, true); | |
14513 | DONE; | |
14514 | }") | |
14515 | ||
14516 | (define_expand "sync_old_sub<mode>" | |
14517 | [(use (match_operand:GPR 0 "gpc_reg_operand" "")) | |
14518 | (use (match_operand:GPR 1 "memory_operand" "")) | |
14519 | (use (match_operand:GPR 2 "gpc_reg_operand" ""))] | |
14520 | "TARGET_POWERPC" | |
14521 | " | |
14522 | { | |
14523 | rs6000_emit_sync (MINUS, <MODE>mode, operands[1], operands[2], | |
14524 | operands[0], NULL_RTX, true); | |
14525 | DONE; | |
14526 | }") | |
14527 | ||
14528 | (define_expand "sync_old_ior<mode>" | |
14529 | [(use (match_operand:INT1 0 "gpc_reg_operand" "")) | |
14530 | (use (match_operand:INT1 1 "memory_operand" "")) | |
14531 | (use (match_operand:INT1 2 "logical_operand" ""))] | |
14532 | "TARGET_POWERPC" | |
14533 | " | |
14534 | { | |
14535 | rs6000_emit_sync (IOR, <MODE>mode, operands[1], operands[2], | |
14536 | operands[0], NULL_RTX, true); | |
14537 | DONE; | |
14538 | }") | |
14539 | ||
14540 | (define_expand "sync_old_and<mode>" | |
14541 | [(use (match_operand:INT1 0 "gpc_reg_operand" "")) | |
14542 | (use (match_operand:INT1 1 "memory_operand" "")) | |
14543 | (use (match_operand:INT1 2 "and_operand" ""))] | |
14544 | "TARGET_POWERPC" | |
14545 | " | |
14546 | { | |
14547 | rs6000_emit_sync (AND, <MODE>mode, operands[1], operands[2], | |
14548 | operands[0], NULL_RTX, true); | |
14549 | DONE; | |
14550 | }") | |
14551 | ||
14552 | (define_expand "sync_old_xor<mode>" | |
14553 | [(use (match_operand:INT1 0 "gpc_reg_operand" "")) | |
14554 | (use (match_operand:INT1 1 "memory_operand" "")) | |
14555 | (use (match_operand:INT1 2 "logical_operand" ""))] | |
14556 | "TARGET_POWERPC" | |
14557 | " | |
14558 | { | |
14559 | rs6000_emit_sync (XOR, <MODE>mode, operands[1], operands[2], | |
14560 | operands[0], NULL_RTX, true); | |
14561 | DONE; | |
14562 | }") | |
14563 | ||
14564 | (define_expand "sync_old_nand<mode>" | |
14565 | [(use (match_operand:INT1 0 "gpc_reg_operand" "")) | |
14566 | (use (match_operand:INT1 1 "memory_operand" "")) | |
14567 | (use (match_operand:INT1 2 "gpc_reg_operand" ""))] | |
14568 | "TARGET_POWERPC" | |
14569 | " | |
14570 | { | |
14571 | rs6000_emit_sync (AND, <MODE>mode, | |
14572 | gen_rtx_NOT (<MODE>mode, operands[1]), | |
14573 | operands[2], | |
14574 | operands[0], NULL_RTX, true); | |
14575 | DONE; | |
14576 | }") | |
14577 | ||
14578 | (define_expand "sync_new_add<mode>" | |
14579 | [(use (match_operand:INT1 0 "gpc_reg_operand" "")) | |
14580 | (use (match_operand:INT1 1 "memory_operand" "")) | |
14581 | (use (match_operand:INT1 2 "add_operand" ""))] | |
14582 | "TARGET_POWERPC" | |
14583 | " | |
14584 | { | |
14585 | rs6000_emit_sync (PLUS, <MODE>mode, operands[1], operands[2], | |
14586 | NULL_RTX, operands[0], true); | |
14587 | DONE; | |
14588 | }") | |
14589 | ||
14590 | (define_expand "sync_new_sub<mode>" | |
14591 | [(use (match_operand:GPR 0 "gpc_reg_operand" "")) | |
14592 | (use (match_operand:GPR 1 "memory_operand" "")) | |
14593 | (use (match_operand:GPR 2 "gpc_reg_operand" ""))] | |
14594 | "TARGET_POWERPC" | |
14595 | " | |
14596 | { | |
14597 | rs6000_emit_sync (MINUS, <MODE>mode, operands[1], operands[2], | |
14598 | NULL_RTX, operands[0], true); | |
14599 | DONE; | |
14600 | }") | |
14601 | ||
14602 | (define_expand "sync_new_ior<mode>" | |
14603 | [(use (match_operand:INT1 0 "gpc_reg_operand" "")) | |
14604 | (use (match_operand:INT1 1 "memory_operand" "")) | |
14605 | (use (match_operand:INT1 2 "logical_operand" ""))] | |
14606 | "TARGET_POWERPC" | |
14607 | " | |
14608 | { | |
14609 | rs6000_emit_sync (IOR, <MODE>mode, operands[1], operands[2], | |
14610 | NULL_RTX, operands[0], true); | |
14611 | DONE; | |
14612 | }") | |
14613 | ||
14614 | (define_expand "sync_new_and<mode>" | |
14615 | [(use (match_operand:INT1 0 "gpc_reg_operand" "")) | |
14616 | (use (match_operand:INT1 1 "memory_operand" "")) | |
14617 | (use (match_operand:INT1 2 "and_operand" ""))] | |
14618 | "TARGET_POWERPC" | |
14619 | " | |
14620 | { | |
14621 | rs6000_emit_sync (AND, <MODE>mode, operands[1], operands[2], | |
14622 | NULL_RTX, operands[0], true); | |
14623 | DONE; | |
14624 | }") | |
14625 | ||
14626 | (define_expand "sync_new_xor<mode>" | |
14627 | [(use (match_operand:INT1 0 "gpc_reg_operand" "")) | |
14628 | (use (match_operand:INT1 1 "memory_operand" "")) | |
14629 | (use (match_operand:INT1 2 "logical_operand" ""))] | |
14630 | "TARGET_POWERPC" | |
14631 | " | |
14632 | { | |
14633 | rs6000_emit_sync (XOR, <MODE>mode, operands[1], operands[2], | |
14634 | NULL_RTX, operands[0], true); | |
14635 | DONE; | |
14636 | }") | |
14637 | ||
14638 | (define_expand "sync_new_nand<mode>" | |
14639 | [(use (match_operand:INT1 0 "gpc_reg_operand" "")) | |
14640 | (use (match_operand:INT1 1 "memory_operand" "")) | |
14641 | (use (match_operand:INT1 2 "gpc_reg_operand" ""))] | |
14642 | "TARGET_POWERPC" | |
14643 | " | |
14644 | { | |
14645 | rs6000_emit_sync (AND, <MODE>mode, | |
14646 | gen_rtx_NOT (<MODE>mode, operands[1]), | |
14647 | operands[2], | |
14648 | NULL_RTX, operands[0], true); | |
14649 | DONE; | |
14650 | }") | |
14651 | ||
14652 | ; the sync_*_internal patterns all have these operands: | |
14653 | ; 0 - memory location | |
14654 | ; 1 - operand | |
14655 | ; 2 - value in memory after operation | |
14656 | ; 3 - value in memory immediately before operation | |
14657 | ||
14658 | (define_insn "*sync_add<mode>_internal" | |
14659 | [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r,&r") | |
14660 | (plus:GPR (match_operand:GPR 0 "memory_operand" "+Z,Z") | |
14661 | (match_operand:GPR 1 "add_operand" "rI,L"))) | |
14662 | (set (match_operand:GPR 3 "gpc_reg_operand" "=&b,&b") (match_dup 0)) | |
14663 | (set (match_dup 0) | |
14664 | (unspec:GPR [(plus:GPR (match_dup 0) (match_dup 1))] | |
14665 | UNSPEC_SYNC_OP)) | |
14666 | (clobber (match_scratch:CC 4 "=&x,&x"))] | |
14667 | "TARGET_POWERPC" | |
14668 | "@ | |
8635a919 GK |
14669 | <larx> %3,%y0\n\tadd%I1 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- $-12 |
14670 | <larx> %3,%y0\n\taddis %2,%3,%v1\n\t<stcx> %2,%y0\n\tbne- $-12" | |
915167f5 GK |
14671 | [(set_attr "length" "16,16")]) |
14672 | ||
14673 | (define_insn "*sync_addshort_internal" | |
14674 | [(set (match_operand:SI 2 "gpc_reg_operand" "=&r") | |
14675 | (ior:SI (and:SI (plus:SI (match_operand:SI 0 "memory_operand" "+Z") | |
14676 | (match_operand:SI 1 "add_operand" "rI")) | |
14677 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
14678 | (and:SI (not:SI (match_dup 4)) (match_dup 0)))) | |
14679 | (set (match_operand:SI 3 "gpc_reg_operand" "=&b") (match_dup 0)) | |
14680 | (set (match_dup 0) | |
14681 | (unspec:SI [(ior:SI (and:SI (plus:SI (match_dup 0) (match_dup 1)) | |
14682 | (match_dup 4)) | |
14683 | (and:SI (not:SI (match_dup 4)) (match_dup 0)))] | |
14684 | UNSPEC_SYNC_OP)) | |
14685 | (clobber (match_scratch:CC 5 "=&x")) | |
14686 | (clobber (match_scratch:SI 6 "=&r"))] | |
14687 | "TARGET_POWERPC" | |
8635a919 | 14688 | "lwarx %3,%y0\n\tadd%I1 %2,%3,%1\n\tandc %6,%3,%4\n\tand %2,%2,%4\n\tor %2,%2,%6\n\tstwcx. %2,%y0\n\tbne- $-24" |
915167f5 GK |
14689 | [(set_attr "length" "28")]) |
14690 | ||
14691 | (define_insn "*sync_sub<mode>_internal" | |
14692 | [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r") | |
14693 | (minus:GPR (match_operand:GPR 0 "memory_operand" "+Z") | |
14694 | (match_operand:GPR 1 "gpc_reg_operand" "r"))) | |
14695 | (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0)) | |
14696 | (set (match_dup 0) | |
14697 | (unspec:GPR [(minus:GPR (match_dup 0) (match_dup 1))] | |
14698 | UNSPEC_SYNC_OP)) | |
14699 | (clobber (match_scratch:CC 4 "=&x"))] | |
14700 | "TARGET_POWERPC" | |
8635a919 | 14701 | "<larx> %3,%y0\n\tsubf %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- $-12" |
915167f5 GK |
14702 | [(set_attr "length" "16")]) |
14703 | ||
14704 | (define_insn "*sync_andsi_internal" | |
14705 | [(set (match_operand:SI 2 "gpc_reg_operand" "=&r,&r,&r,&r") | |
14706 | (and:SI (match_operand:SI 0 "memory_operand" "+Z,Z,Z,Z") | |
14707 | (match_operand:SI 1 "and_operand" "r,T,K,L"))) | |
14708 | (set (match_operand:SI 3 "gpc_reg_operand" "=&b,&b,&b,&b") (match_dup 0)) | |
14709 | (set (match_dup 0) | |
14710 | (unspec:SI [(and:SI (match_dup 0) (match_dup 1))] | |
14711 | UNSPEC_SYNC_OP)) | |
14712 | (clobber (match_scratch:CC 4 "=&x,&x,&x,&x"))] | |
14713 | "TARGET_POWERPC" | |
14714 | "@ | |
8635a919 GK |
14715 | lwarx %3,%y0\n\tand %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- $-12 |
14716 | lwarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstwcx. %2,%y0\n\tbne- $-12 | |
14717 | lwarx %3,%y0\n\tandi. %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- $-12 | |
14718 | lwarx %3,%y0\n\tandis. %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- $-12" | |
915167f5 GK |
14719 | [(set_attr "length" "16,16,16,16")]) |
14720 | ||
14721 | (define_insn "*sync_anddi_internal" | |
14722 | [(set (match_operand:DI 2 "gpc_reg_operand" "=&r,&r,&r,&r,&r") | |
14723 | (and:DI (match_operand:DI 0 "memory_operand" "+Z,Z,Z,Z,Z") | |
14724 | (match_operand:DI 1 "and_operand" "r,S,T,K,J"))) | |
14725 | (set (match_operand:DI 3 "gpc_reg_operand" "=&b,&b,&b,&b,&b") (match_dup 0)) | |
14726 | (set (match_dup 0) | |
14727 | (unspec:DI [(and:DI (match_dup 0) (match_dup 1))] | |
14728 | UNSPEC_SYNC_OP)) | |
14729 | (clobber (match_scratch:CC 4 "=&x,&x,&x,&x,&x"))] | |
14730 | "TARGET_POWERPC64" | |
14731 | "@ | |
8635a919 GK |
14732 | ldarx %3,%y0\n\tand %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- $-12 |
14733 | ldarx %3,%y0\n\trldic%B1 %2,%3,0,%S1\n\tstdcx. %2,%y0\n\tbne- $-12 | |
14734 | ldarx %3,%y0\n\trlwinm %2,%3,0,%m1,%M1\n\tstdcx. %2,%y0\n\tbne- $-12 | |
14735 | ldarx %3,%y0\n\tandi. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- $-12 | |
14736 | ldarx %3,%y0\n\tandis. %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- $-12" | |
915167f5 GK |
14737 | [(set_attr "length" "16,16,16,16,16")]) |
14738 | ||
14739 | (define_insn "*sync_boolsi_internal" | |
14740 | [(set (match_operand:SI 2 "gpc_reg_operand" "=&r,&r,&r") | |
14741 | (match_operator:SI 4 "boolean_or_operator" | |
14742 | [(match_operand:SI 0 "memory_operand" "+Z,Z,Z") | |
14743 | (match_operand:SI 1 "logical_operand" "r,K,L")])) | |
14744 | (set (match_operand:SI 3 "gpc_reg_operand" "=&b,&b,&b") (match_dup 0)) | |
14745 | (set (match_dup 0) (unspec:SI [(match_dup 4)] UNSPEC_SYNC_OP)) | |
14746 | (clobber (match_scratch:CC 5 "=&x,&x,&x"))] | |
14747 | "TARGET_POWERPC" | |
14748 | "@ | |
8635a919 GK |
14749 | lwarx %3,%y0\n\t%q4 %2,%3,%1\n\tstwcx. %2,%y0\n\tbne- $-12 |
14750 | lwarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstwcx. %2,%y0\n\tbne- $-12 | |
14751 | lwarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstwcx. %2,%y0\n\tbne- $-12" | |
915167f5 GK |
14752 | [(set_attr "length" "16,16,16")]) |
14753 | ||
14754 | (define_insn "*sync_booldi_internal" | |
14755 | [(set (match_operand:DI 2 "gpc_reg_operand" "=&r,&r,&r") | |
14756 | (match_operator:DI 4 "boolean_or_operator" | |
14757 | [(match_operand:DI 0 "memory_operand" "+Z,Z,Z") | |
14758 | (match_operand:DI 1 "logical_operand" "r,K,JF")])) | |
14759 | (set (match_operand:DI 3 "gpc_reg_operand" "=&b,&b,&b") (match_dup 0)) | |
14760 | (set (match_dup 0) (unspec:DI [(match_dup 4)] UNSPEC_SYNC_OP)) | |
14761 | (clobber (match_scratch:CC 5 "=&x,&x,&x"))] | |
14762 | "TARGET_POWERPC64" | |
14763 | "@ | |
8635a919 GK |
14764 | ldarx %3,%y0\n\t%q4 %2,%3,%1\n\tstdcx. %2,%y0\n\tbne- $-12 |
14765 | ldarx %3,%y0\n\t%q4i %2,%3,%b1\n\tstdcx. %2,%y0\n\tbne- $-12 | |
14766 | ldarx %3,%y0\n\t%q4is %2,%3,%u1\n\tstdcx. %2,%y0\n\tbne- $-12" | |
915167f5 GK |
14767 | [(set_attr "length" "16,16,16")]) |
14768 | ||
14769 | (define_insn "*sync_boolc<mode>_internal" | |
14770 | [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r") | |
14771 | (match_operator:GPR 4 "boolean_operator" | |
14772 | [(not:GPR (match_operand:GPR 0 "memory_operand" "+Z")) | |
14773 | (match_operand:GPR 1 "gpc_reg_operand" "r")])) | |
14774 | (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0)) | |
14775 | (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP)) | |
14776 | (clobber (match_scratch:CC 5 "=&x"))] | |
14777 | "TARGET_POWERPC" | |
8635a919 | 14778 | "<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- $-12" |
915167f5 GK |
14779 | [(set_attr "length" "16")]) |
14780 | ||
14781 | (define_insn "*sync_boolc<mode>_internal2" | |
14782 | [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r") | |
14783 | (match_operator:GPR 4 "boolean_operator" | |
14784 | [(not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")) | |
14785 | (match_operand:GPR 0 "memory_operand" "+Z")])) | |
14786 | (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0)) | |
14787 | (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP)) | |
14788 | (clobber (match_scratch:CC 5 "=&x"))] | |
14789 | "TARGET_POWERPC" | |
8635a919 | 14790 | "<larx> %3,%y0\n\t%q4 %2,%3,%1\n\t<stcx> %2,%y0\n\tbne- $-12" |
915167f5 GK |
14791 | [(set_attr "length" "16")]) |
14792 | ||
14793 | (define_insn "*sync_boolcc<mode>_internal" | |
14794 | [(set (match_operand:GPR 2 "gpc_reg_operand" "=&r") | |
14795 | (match_operator:GPR 4 "boolean_operator" | |
14796 | [(not:GPR (match_operand:GPR 0 "memory_operand" "+Z")) | |
14797 | (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))])) | |
14798 | (set (match_operand:GPR 3 "gpc_reg_operand" "=&b") (match_dup 0)) | |
14799 | (set (match_dup 0) (unspec:GPR [(match_dup 4)] UNSPEC_SYNC_OP)) | |
14800 | (clobber (match_scratch:CC 5 "=&x"))] | |
14801 | "TARGET_POWERPC" | |
8635a919 | 14802 | "<larx> %3,%y0\n\t%q4 %2,%1,%3\n\t<stcx> %2,%y0\n\tbne- $-12" |
915167f5 GK |
14803 | [(set_attr "length" "16")]) |
14804 | ||
14805 | (define_insn "isync" | |
14806 | [(set (mem:BLK (match_scratch 0 "X")) | |
14807 | (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_ISYNC))] | |
14808 | "TARGET_POWERPC" | |
14809 | "isync") | |
14810 | ||
14811 | (define_insn "sync_lock_test_and_set<mode>" | |
14812 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=&r") | |
14813 | (match_operand:GPR 1 "memory_operand" "+Z")) | |
14814 | (set (match_dup 1) (unspec:GPR [(match_operand:GPR 2 "gpc_reg_operand" "r")] | |
14815 | UNSPEC_SYNC_OP)) | |
14816 | (clobber (match_scratch:CC 3 "=&x")) | |
14817 | (set (mem:BLK (match_scratch 4 "X")) | |
14818 | (unspec:BLK [(mem:BLK (match_scratch 5 "X"))] UNSPEC_ISYNC))] | |
14819 | "TARGET_POWERPC" | |
8635a919 | 14820 | "<larx> %0,%y1\n\t<stcx> %2,%y1\n\tbne- $-8\n\tisync" |
915167f5 GK |
14821 | [(set_attr "length" "16")]) |
14822 | ||
14823 | (define_expand "sync_lock_release<mode>" | |
8635a919 GK |
14824 | [(set (match_operand:INT 0 "memory_operand") |
14825 | (match_operand:INT 1 "any_operand"))] | |
915167f5 GK |
14826 | "" |
14827 | " | |
14828 | { | |
14829 | emit_insn (gen_lwsync ()); | |
8635a919 | 14830 | emit_move_insn (operands[0], operands[1]); |
915167f5 GK |
14831 | DONE; |
14832 | }") | |
14833 | ||
8635a919 | 14834 | ; Some AIX assemblers don't accept lwsync, so we use a .long. |
915167f5 GK |
14835 | (define_insn "lwsync" |
14836 | [(set (mem:BLK (match_scratch 0 "X")) | |
14837 | (unspec:BLK [(mem:BLK (match_scratch 1 "X"))] UNSPEC_LWSYNC))] | |
14838 | "" | |
8635a919 | 14839 | ".long 0x7c2004ac") |
915167f5 GK |
14840 | |
14841 | \f | |
a3170dc6 | 14842 | |
10ed84db | 14843 | (include "altivec.md") |
a3170dc6 | 14844 | (include "spe.md") |