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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
9ebbca7d | 2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
792760b9 | 3 | ;; 1999, 2000, 2001 Free Software Foundation, Inc. |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 RK |
5 | |
6 | ;; This file is part of GNU CC. | |
7 | ||
8 | ;; GNU CC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 2, or (at your option) | |
11 | ;; any later version. | |
12 | ||
13 | ;; GNU CC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GNU CC; see the file COPYING. If not, write to | |
3f63df56 RK |
20 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | ;; Boston, MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d GK |
24 | |
25 | ;; `unspec' values used in rs6000.md: | |
26 | ;; Number Use | |
27 | ;; 0 frsp for POWER machines | |
28 | ;; 0/v blockage | |
29 | ;; 5 used to tie the stack contents and the stack pointer | |
30 | ;; 6 address of a word pointing to the TOC | |
31 | ;; 7 address of the TOC (more-or-less) | |
32 | ;; 8 movsi_got | |
33 | ;; 9/v eh_reg_restore | |
34 | ;; 10 fctiwz | |
35 | ;; 19 movesi_from_cr | |
36 | ;; 20 movesi_to_cr | |
1fd4e8c1 RK |
37 | \f |
38 | ;; Define an insn type attribute. This is used in function unit delay | |
39 | ;; computations. | |
c859cda6 | 40 | (define_attr "type" "integer,load,store,fpload,fpstore,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat,altivec" |
1fd4e8c1 RK |
41 | (const_string "integer")) |
42 | ||
b19003d8 | 43 | ;; Length (in bytes). |
6cbadf36 GK |
44 | ; '(pc)' in the following doesn't include the instruction itself; it is |
45 | ; calculated as if the instruction had zero size. | |
b19003d8 RK |
46 | (define_attr "length" "" |
47 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 48 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 49 | (const_int -32768)) |
6cbadf36 GK |
50 | (lt (minus (match_dup 0) (pc)) |
51 | (const_int 32764))) | |
39a10a29 GK |
52 | (const_int 4) |
53 | (const_int 8)) | |
b19003d8 RK |
54 | (const_int 4))) |
55 | ||
cfb557c4 RK |
56 | ;; Processor type -- this attribute must exactly match the processor_type |
57 | ;; enumeration in rs6000.h. | |
58 | ||
fe7f5677 | 59 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450" |
cfb557c4 RK |
60 | (const (symbol_ref "rs6000_cpu_attr"))) |
61 | ||
62 | ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY | |
63 | ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) | |
64 | ||
b7ff3d82 | 65 | ; Load/Store Unit -- pure PowerPC only |
51b8fc2c | 66 | ; (POWER and 601 use Integer Unit) |
cfb557c4 RK |
67 | (define_function_unit "lsu" 1 0 |
68 | (and (eq_attr "type" "load") | |
ed947a96 | 69 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400")) |
b6c9286a | 70 | 2 1) |
cfb557c4 | 71 | |
ed947a96 | 72 | (define_function_unit "lsu" 1 0 |
f18c054f | 73 | (and (eq_attr "type" "load,vecload") |
ed947a96 DJ |
74 | (eq_attr "cpu" "ppc7450")) |
75 | 3 1) | |
76 | ||
cfb557c4 | 77 | (define_function_unit "lsu" 1 0 |
b7ff3d82 | 78 | (and (eq_attr "type" "store,fpstore") |
ed947a96 | 79 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 80 | 1 1) |
b6c9286a | 81 | |
ed947a96 DJ |
82 | (define_function_unit "lsu" 1 0 |
83 | (and (eq_attr "type" "store,fpstore") | |
84 | (eq_attr "cpu" "ppc750,ppc7400")) | |
85 | 2 1) | |
86 | ||
87 | (define_function_unit "lsu" 1 0 | |
f18c054f | 88 | (and (eq_attr "type" "store,vecstore") |
ed947a96 DJ |
89 | (eq_attr "cpu" "ppc7450")) |
90 | 3 1) | |
91 | ||
92 | (define_function_unit "lsu" 1 0 | |
93 | (and (eq_attr "type" "fpstore") | |
94 | (eq_attr "cpu" "ppc7450")) | |
95 | 3 3) | |
96 | ||
b6c9286a MM |
97 | (define_function_unit "lsu" 1 0 |
98 | (and (eq_attr "type" "fpload") | |
ed947a96 | 99 | (eq_attr "cpu" "mpccore,ppc603,ppc750,ppc7400")) |
b6c9286a | 100 | 2 1) |
cfb557c4 | 101 | |
ed947a96 DJ |
102 | (define_function_unit "lsu" 1 0 |
103 | (and (eq_attr "type" "fpload") | |
104 | (eq_attr "cpu" "ppc7450")) | |
105 | 4 1) | |
106 | ||
b7ff3d82 DE |
107 | (define_function_unit "lsu" 1 0 |
108 | (and (eq_attr "type" "fpload") | |
3cb999d8 | 109 | (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 DE |
110 | 3 1) |
111 | ||
cfb557c4 RK |
112 | (define_function_unit "iu" 1 0 |
113 | (and (eq_attr "type" "load") | |
fe7f5677 | 114 | (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601")) |
b6c9286a | 115 | 2 1) |
cfb557c4 RK |
116 | |
117 | (define_function_unit "iu" 1 0 | |
b7ff3d82 | 118 | (and (eq_attr "type" "store,fpstore") |
fe7f5677 | 119 | (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601")) |
b7ff3d82 DE |
120 | 1 1) |
121 | ||
122 | (define_function_unit "fpu" 1 0 | |
123 | (and (eq_attr "type" "fpstore") | |
3624a679 | 124 | (eq_attr "cpu" "rios1,ppc601")) |
b7ff3d82 | 125 | 0 1) |
cfb557c4 | 126 | |
49a0b204 | 127 | (define_function_unit "iu" 1 0 |
b7ff3d82 | 128 | (and (eq_attr "type" "fpload") |
b6c9286a | 129 | (eq_attr "cpu" "rios1")) |
b7ff3d82 DE |
130 | 2 1) |
131 | ||
132 | (define_function_unit "iu" 1 0 | |
133 | (and (eq_attr "type" "fpload") | |
134 | (eq_attr "cpu" "ppc601")) | |
135 | 3 1) | |
136 | ||
137 | (define_function_unit "iu2" 2 0 | |
138 | (and (eq_attr "type" "load,fpload") | |
139 | (eq_attr "cpu" "rios2")) | |
140 | 2 1) | |
141 | ||
142 | (define_function_unit "iu2" 2 0 | |
143 | (and (eq_attr "type" "store,fpstore") | |
144 | (eq_attr "cpu" "rios2")) | |
145 | 1 1) | |
146 | ||
3cb999d8 | 147 | ; Integer Unit (RIOS1, PPC601, PPC603, RS64a) |
b7ff3d82 DE |
148 | (define_function_unit "iu" 1 0 |
149 | (and (eq_attr "type" "integer") | |
fe7f5677 | 150 | (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603")) |
b7ff3d82 | 151 | 1 1) |
49a0b204 | 152 | |
39a10a29 GK |
153 | (define_function_unit "iu" 1 0 |
154 | (and (eq_attr "type" "cr_logical") | |
fe7f5677 | 155 | (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601")) |
39a10a29 GK |
156 | 1 1) |
157 | ||
da0ae67f | 158 | (define_function_unit "iu" 1 0 |
c859cda6 | 159 | (and (eq_attr "type" "imul,imul2,imul3") |
da0ae67f MM |
160 | (eq_attr "cpu" "ppc403")) |
161 | 4 4) | |
162 | ||
cfb557c4 | 163 | (define_function_unit "iu" 1 0 |
fe7f5677 DE |
164 | (and (eq_attr "type" "imul") |
165 | (eq_attr "cpu" "ppc405")) | |
166 | 4 3) | |
167 | ||
168 | (define_function_unit "iu" 1 0 | |
169 | (and (eq_attr "type" "imul2,imul3") | |
170 | (eq_attr "cpu" "ppc405")) | |
171 | 3 2) | |
172 | ||
173 | (define_function_unit "iu" 1 0 | |
174 | (and (eq_attr "type" "imul") | |
175 | (eq_attr "cpu" "rios1")) | |
51b8fc2c | 176 | 5 5) |
cfb557c4 | 177 | |
fe7f5677 DE |
178 | (define_function_unit "iu" 1 0 |
179 | (and (eq_attr "type" "imul2") | |
180 | (eq_attr "cpu" "rios1")) | |
181 | 4 4) | |
182 | ||
183 | (define_function_unit "iu" 1 0 | |
184 | (and (eq_attr "type" "imul3") | |
185 | (eq_attr "cpu" "rios1")) | |
186 | 3 3) | |
187 | ||
3cb999d8 | 188 | (define_function_unit "iu" 1 0 |
c859cda6 | 189 | (and (eq_attr "type" "imul,imul2,imul3") |
fe7f5677 DE |
190 | (eq_attr "cpu" "ppc601,ppc603")) |
191 | 5 5) | |
192 | ||
193 | (define_function_unit "iu" 1 0 | |
194 | (and (eq_attr "type" "imul") | |
195 | (eq_attr "cpu" "rs64a")) | |
196 | 20 20) | |
197 | ||
198 | (define_function_unit "iu" 1 0 | |
199 | (and (eq_attr "type" "imul2") | |
3cb999d8 | 200 | (eq_attr "cpu" "rs64a")) |
fe7f5677 DE |
201 | 12 12) |
202 | ||
203 | (define_function_unit "iu" 1 0 | |
204 | (and (eq_attr "type" "imul3") | |
205 | (eq_attr "cpu" "rs64a")) | |
206 | 8 8) | |
3cb999d8 DE |
207 | |
208 | (define_function_unit "iu" 1 0 | |
209 | (and (eq_attr "type" "lmul") | |
210 | (eq_attr "cpu" "rs64a")) | |
211 | 34 34) | |
212 | ||
cfb557c4 RK |
213 | (define_function_unit "iu" 1 0 |
214 | (and (eq_attr "type" "idiv") | |
ca7f5001 | 215 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 216 | 19 19) |
cfb557c4 | 217 | |
3cb999d8 DE |
218 | (define_function_unit "iu" 1 0 |
219 | (and (eq_attr "type" "idiv") | |
220 | (eq_attr "cpu" "rs64a")) | |
221 | 66 66) | |
222 | ||
223 | (define_function_unit "iu" 1 0 | |
224 | (and (eq_attr "type" "ldiv") | |
225 | (eq_attr "cpu" "rs64a")) | |
226 | 66 66) | |
227 | ||
cfb557c4 RK |
228 | (define_function_unit "iu" 1 0 |
229 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
230 | (eq_attr "cpu" "ppc403")) |
231 | 33 33) | |
51b8fc2c | 232 | |
fe7f5677 DE |
233 | (define_function_unit "iu" 1 0 |
234 | (and (eq_attr "type" "idiv") | |
235 | (eq_attr "cpu" "ppc405")) | |
236 | 35 35) | |
237 | ||
da0ae67f MM |
238 | (define_function_unit "iu" 1 0 |
239 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
240 | (eq_attr "cpu" "ppc601")) |
241 | 36 36) | |
da0ae67f | 242 | |
51b8fc2c RK |
243 | (define_function_unit "iu" 1 0 |
244 | (and (eq_attr "type" "idiv") | |
b7ff3d82 | 245 | (eq_attr "cpu" "ppc603")) |
51b8fc2c RK |
246 | 37 36) |
247 | ||
248 | ; RIOS2 has two integer units: a primary one which can perform all | |
249 | ; operations and a secondary one which is fed in lock step with the first | |
b6c9286a MM |
250 | ; and can perform "simple" integer operations. |
251 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
252 | ; for the complex insns. | |
51b8fc2c RK |
253 | (define_function_unit "iu2" 2 0 |
254 | (and (eq_attr "type" "integer") | |
255 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 256 | 1 1) |
b6c9286a MM |
257 | |
258 | (define_function_unit "iu2" 2 0 | |
c859cda6 | 259 | (and (eq_attr "type" "imul,imul2,imul3") |
b6c9286a MM |
260 | (eq_attr "cpu" "rios2")) |
261 | 2 2) | |
262 | ||
263 | (define_function_unit "iu2" 2 0 | |
264 | (and (eq_attr "type" "idiv") | |
265 | (eq_attr "cpu" "rios2")) | |
266 | 13 13) | |
51b8fc2c RK |
267 | |
268 | (define_function_unit "imuldiv" 1 0 | |
c859cda6 | 269 | (and (eq_attr "type" "imul,imul2,imul3") |
51b8fc2c | 270 | (eq_attr "cpu" "rios2")) |
b6c9286a MM |
271 | 2 2) |
272 | ||
51b8fc2c RK |
273 | (define_function_unit "imuldiv" 1 0 |
274 | (and (eq_attr "type" "idiv") | |
275 | (eq_attr "cpu" "rios2")) | |
b6c9286a | 276 | 13 13) |
51b8fc2c | 277 | |
cf27b467 MM |
278 | ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions |
279 | ; Divide latency varies greatly from 2-11, use 6 as average | |
280 | (define_function_unit "imuldiv" 1 0 | |
c859cda6 | 281 | (and (eq_attr "type" "imul,imul2,imul3") |
cf27b467 MM |
282 | (eq_attr "cpu" "mpccore")) |
283 | 2 1) | |
284 | ||
285 | (define_function_unit "imuldiv" 1 0 | |
286 | (and (eq_attr "type" "idiv") | |
287 | (eq_attr "cpu" "mpccore")) | |
288 | 6 6) | |
289 | ||
cac8ce95 | 290 | ; PPC604{,e} has two units that perform integer operations |
b6c9286a MM |
291 | ; and one unit for divide/multiply operations (and move |
292 | ; from/to spr). | |
293 | (define_function_unit "iu2" 2 0 | |
51b8fc2c | 294 | (and (eq_attr "type" "integer") |
3cb999d8 | 295 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 296 | 1 1) |
51b8fc2c RK |
297 | |
298 | (define_function_unit "imuldiv" 1 0 | |
c859cda6 | 299 | (and (eq_attr "type" "imul,imul2,imul3") |
3cb999d8 | 300 | (eq_attr "cpu" "ppc604")) |
b7ff3d82 | 301 | 4 2) |
51b8fc2c | 302 | |
3cb999d8 | 303 | (define_function_unit "imuldiv" 1 0 |
c859cda6 | 304 | (and (eq_attr "type" "imul,imul2,imul3") |
fe7f5677 DE |
305 | (eq_attr "cpu" "ppc604e")) |
306 | 2 1) | |
307 | ||
308 | (define_function_unit "imuldiv" 1 0 | |
309 | (and (eq_attr "type" "imul") | |
3cb999d8 DE |
310 | (eq_attr "cpu" "ppc620,ppc630")) |
311 | 5 3) | |
312 | ||
313 | (define_function_unit "imuldiv" 1 0 | |
fe7f5677 | 314 | (and (eq_attr "type" "imul2") |
3cb999d8 | 315 | (eq_attr "cpu" "ppc620,ppc630")) |
fe7f5677 | 316 | 4 3) |
3cb999d8 | 317 | |
cac8ce95 | 318 | (define_function_unit "imuldiv" 1 0 |
fe7f5677 DE |
319 | (and (eq_attr "type" "imul3") |
320 | (eq_attr "cpu" "ppc620,ppc630")) | |
321 | 3 3) | |
322 | ||
323 | (define_function_unit "imuldiv" 1 0 | |
324 | (and (eq_attr "type" "lmul") | |
325 | (eq_attr "cpu" "ppc620,ppc630")) | |
326 | 7 5) | |
cac8ce95 | 327 | |
51b8fc2c RK |
328 | (define_function_unit "imuldiv" 1 0 |
329 | (and (eq_attr "type" "idiv") | |
3cb999d8 | 330 | (eq_attr "cpu" "ppc604,ppc604e")) |
b7ff3d82 | 331 | 20 19) |
cfb557c4 | 332 | |
3cb999d8 DE |
333 | (define_function_unit "imuldiv" 1 0 |
334 | (and (eq_attr "type" "idiv") | |
335 | (eq_attr "cpu" "ppc620")) | |
336 | 37 36) | |
337 | ||
338 | (define_function_unit "imuldiv" 1 0 | |
339 | (and (eq_attr "type" "idiv") | |
340 | (eq_attr "cpu" "ppc630")) | |
341 | 21 20) | |
342 | ||
343 | (define_function_unit "imuldiv" 1 0 | |
344 | (and (eq_attr "type" "ldiv") | |
345 | (eq_attr "cpu" "ppc620,ppc630")) | |
346 | 37 36) | |
347 | ||
ed947a96 DJ |
348 | ; PPC7450 has 3 integer units (for most integer insns) and one mul/div |
349 | ; unit, which also does CR-logical insns and move to/from SPR. | |
2212663f DB |
350 | ; It also has 4 vector units, one for each type of vector instruction. |
351 | ; However, we can only dispatch 2 instructions per cycle. | |
352 | ; We model this as saying that dispatching two of the same type of instruction | |
353 | ; in a row incurs a single cycle delay. | |
ed947a96 DJ |
354 | (define_function_unit "iu3" 3 0 |
355 | (and (eq_attr "type" "integer") | |
356 | (eq_attr "cpu" "ppc7450")) | |
357 | 1 1) | |
358 | ||
359 | (define_function_unit "imuldiv" 1 0 | |
360 | (and (eq_attr "type" "imul") | |
361 | (eq_attr "cpu" "ppc7450")) | |
fd3b43f2 | 362 | 4 2) |
ed947a96 | 363 | |
c859cda6 DJ |
364 | (define_function_unit "imuldiv" 1 0 |
365 | (and (eq_attr "type" "imul2,imul3") | |
366 | (eq_attr "cpu" "ppc7450")) | |
367 | 3 1) | |
368 | ||
ed947a96 DJ |
369 | (define_function_unit "imuldiv" 1 0 |
370 | (and (eq_attr "type" "idiv") | |
371 | (eq_attr "cpu" "ppc7450")) | |
372 | 23 23) | |
373 | ||
374 | (define_function_unit "imuldiv" 1 0 | |
375 | (and (eq_attr "type" "cr_logical") | |
376 | (eq_attr "cpu" "ppc7450")) | |
377 | 1 1) | |
2212663f | 378 | (define_function_unit "vec_alu2" 2 0 |
f18c054f DB |
379 | (and (eq_attr "type" "vecsimple") |
380 | (eq_attr "cpu" "ppc7450")) | |
2212663f DB |
381 | 1 2 [(eq_attr "type" "vecsimple")]) |
382 | (define_function_unit "vec_alu2" 2 0 | |
383 | (and (eq_attr "type" "vecsimple") | |
384 | (eq_attr "cpu" "ppc7450")) | |
385 | 1 1 [(eq_attr "type" "!vecsimple")]) | |
386 | (define_function_unit "vec_alu2" 2 0 | |
f18c054f DB |
387 | (and (eq_attr "type" "veccomplex") |
388 | (eq_attr "cpu" "ppc7450")) | |
2212663f DB |
389 | 4 2 [(eq_attr "type" "veccomplex")]) |
390 | (define_function_unit "vec_alu2" 2 0 | |
391 | (and (eq_attr "type" "veccomplex") | |
392 | (eq_attr "cpu" "ppc7450")) | |
393 | 4 1 [(eq_attr "type" "!veccomplex")]) | |
394 | (define_function_unit "vec_alu2" 2 0 | |
f18c054f DB |
395 | (and (eq_attr "type" "veccmp") |
396 | (eq_attr "cpu" "ppc7450")) | |
2212663f DB |
397 | 2 2 [(eq_attr "type" "veccmp")]) |
398 | (define_function_unit "vec_alu2" 2 0 | |
399 | (and (eq_attr "type" "veccmp") | |
400 | (eq_attr "cpu" "ppc7450")) | |
401 | 2 1 [(eq_attr "type" "!veccmp")]) | |
402 | (define_function_unit "vec_alu2" 2 0 | |
f18c054f DB |
403 | (and (eq_attr "type" "vecfloat") |
404 | (eq_attr "cpu" "ppc7450")) | |
2212663f DB |
405 | 4 2 [(eq_attr "type" "vecfloat")]) |
406 | (define_function_unit "vec_alu2" 2 0 | |
407 | (and (eq_attr "type" "vecfloat") | |
408 | (eq_attr "cpu" "ppc7450")) | |
409 | 4 1 [(eq_attr "type" "!vecfloat")]) | |
410 | (define_function_unit "vec_alu2" 2 0 | |
f18c054f DB |
411 | (and (eq_attr "type" "vecperm") |
412 | (eq_attr "cpu" "ppc7450")) | |
2212663f DB |
413 | 2 2 [(eq_attr "type" "vecperm")]) |
414 | (define_function_unit "vec_alu2" 2 0 | |
415 | (and (eq_attr "type" "vecperm") | |
416 | (eq_attr "cpu" "ppc7450")) | |
417 | 2 1 [(eq_attr "type" "!vecperm")]) | |
ed947a96 | 418 | |
bef84347 VM |
419 | ; PPC750 has two integer units: a primary one which can perform all |
420 | ; operations and a secondary one which is fed in lock step with the first | |
421 | ; and can perform "simple" integer operations. | |
422 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
423 | ; for the complex insns. | |
424 | (define_function_unit "iu2" 2 0 | |
425 | (and (eq_attr "type" "integer") | |
ed947a96 | 426 | (eq_attr "cpu" "ppc750,ppc7400")) |
bef84347 VM |
427 | 1 1) |
428 | ||
429 | (define_function_unit "iu2" 2 0 | |
430 | (and (eq_attr "type" "imul") | |
ed947a96 DJ |
431 | (eq_attr "cpu" "ppc750,ppc7400")) |
432 | 4 4) | |
433 | ||
c859cda6 DJ |
434 | (define_function_unit "iu2" 2 0 |
435 | (and (eq_attr "type" "imul2") | |
436 | (eq_attr "cpu" "ppc750,ppc7400")) | |
437 | 3 2) | |
438 | ||
439 | (define_function_unit "iu2" 2 0 | |
440 | (and (eq_attr "type" "imul3") | |
441 | (eq_attr "cpu" "ppc750,ppc7400")) | |
442 | 2 1) | |
443 | ||
ed947a96 DJ |
444 | (define_function_unit "iu2" 2 0 |
445 | (and (eq_attr "type" "idiv") | |
446 | (eq_attr "cpu" "ppc750,ppc7400")) | |
447 | 19 19) | |
bef84347 VM |
448 | |
449 | (define_function_unit "imuldiv" 1 0 | |
450 | (and (eq_attr "type" "imul") | |
ed947a96 DJ |
451 | (eq_attr "cpu" "ppc750,ppc7400")) |
452 | 4 4) | |
bef84347 | 453 | |
c859cda6 DJ |
454 | (define_function_unit "imuldiv" 1 0 |
455 | (and (eq_attr "type" "imul2") | |
456 | (eq_attr "cpu" "ppc750,ppc7400")) | |
457 | 3 2) | |
458 | ||
459 | (define_function_unit "imuldiv" 1 0 | |
460 | (and (eq_attr "type" "imul3") | |
461 | (eq_attr "cpu" "ppc750,ppc7400")) | |
462 | 2 1) | |
463 | ||
bef84347 VM |
464 | (define_function_unit "imuldiv" 1 0 |
465 | (and (eq_attr "type" "idiv") | |
ed947a96 | 466 | (eq_attr "cpu" "ppc750,ppc7400")) |
bef84347 VM |
467 | 19 19) |
468 | ||
39a10a29 GK |
469 | ; CR-logical operations are execute-serialized, that is they don't |
470 | ; start (and block the function unit) until all preceding operations | |
471 | ; have finished. They don't block dispatch of other insns, though. | |
472 | ; I've imitated this by giving them longer latency. | |
473 | (define_function_unit "sru" 1 0 | |
474 | (and (eq_attr "type" "cr_logical") | |
ed947a96 | 475 | (eq_attr "cpu" "ppc603,ppc750,ppc7400")) |
39a10a29 GK |
476 | 3 2) |
477 | ||
b6c9286a | 478 | ; compare is done on integer unit, but feeds insns which |
acc5239d | 479 | ; execute on the branch unit. |
b6c9286a MM |
480 | (define_function_unit "iu" 1 0 |
481 | (and (eq_attr "type" "compare") | |
b7ff3d82 DE |
482 | (eq_attr "cpu" "rios1")) |
483 | 4 1) | |
484 | ||
485 | (define_function_unit "iu" 1 0 | |
486 | (and (eq_attr "type" "delayed_compare") | |
487 | (eq_attr "cpu" "rios1")) | |
488 | 5 1) | |
489 | ||
490 | (define_function_unit "iu" 1 0 | |
491 | (and (eq_attr "type" "compare,delayed_compare") | |
fe7f5677 | 492 | (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 493 | 3 1) |
b6c9286a | 494 | |
ed947a96 DJ |
495 | ; some extra cycles added by TARGET_SCHED_ADJUST_COST between compare |
496 | ; and a following branch, to reduce mispredicts | |
ed947a96 DJ |
497 | (define_function_unit "iu3" 3 0 |
498 | (and (eq_attr "type" "compare,delayed_compare") | |
499 | (eq_attr "cpu" "ppc7450")) | |
500 | 1 1) | |
501 | ||
b6c9286a | 502 | (define_function_unit "iu2" 2 0 |
b7ff3d82 | 503 | (and (eq_attr "type" "compare,delayed_compare") |
b6c9286a | 504 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 505 | 3 1) |
b6c9286a | 506 | |
b6c9286a | 507 | (define_function_unit "iu2" 2 0 |
b7ff3d82 | 508 | (and (eq_attr "type" "compare,delayed_compare") |
ed947a96 | 509 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400")) |
b6c9286a | 510 | 1 1) |
cfb557c4 | 511 | |
b6c9286a MM |
512 | ; fp compare uses fp unit |
513 | (define_function_unit "fpu" 1 0 | |
cfb557c4 | 514 | (and (eq_attr "type" "fpcompare") |
b6c9286a | 515 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 516 | 9 1) |
cfb557c4 | 517 | |
b6c9286a MM |
518 | ; rios1 and rios2 have different fpcompare delays |
519 | (define_function_unit "fpu2" 2 0 | |
cfb557c4 | 520 | (and (eq_attr "type" "fpcompare") |
3cb999d8 | 521 | (eq_attr "cpu" "rios2,ppc630")) |
b6c9286a MM |
522 | 5 1) |
523 | ||
524 | ; on ppc601 and ppc603, fpcompare takes also 2 cycles from | |
525 | ; the integer unit | |
526 | ; here we do not define delays, just occupy the unit. The dependencies | |
b7ff3d82 | 527 | ; will be assigned by the fpcompare definition in the fpu. |
b6c9286a MM |
528 | (define_function_unit "iu" 1 0 |
529 | (and (eq_attr "type" "fpcompare") | |
b7ff3d82 | 530 | (eq_attr "cpu" "ppc601,ppc603")) |
b6c9286a MM |
531 | 0 2) |
532 | ||
533 | ; fp compare uses fp unit | |
534 | (define_function_unit "fpu" 1 0 | |
535 | (and (eq_attr "type" "fpcompare") | |
ed947a96 | 536 | (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630")) |
b6c9286a | 537 | 5 1) |
cfb557c4 | 538 | |
ed947a96 DJ |
539 | (define_function_unit "fpu" 1 0 |
540 | (and (eq_attr "type" "fpcompare") | |
541 | (eq_attr "cpu" "ppc750,ppc7400,ppc7450")) | |
542 | 3 1) | |
543 | ||
cf27b467 MM |
544 | (define_function_unit "fpu" 1 0 |
545 | (and (eq_attr "type" "fpcompare") | |
546 | (eq_attr "cpu" "mpccore")) | |
547 | 1 1) | |
548 | ||
cfb557c4 | 549 | (define_function_unit "bpu" 1 0 |
324e52cc | 550 | (and (eq_attr "type" "mtjmpr") |
3cb999d8 | 551 | (eq_attr "cpu" "rios1,rios2,rs64a")) |
b7ff3d82 | 552 | 5 1) |
cfb557c4 RK |
553 | |
554 | (define_function_unit "bpu" 1 0 | |
324e52cc | 555 | (and (eq_attr "type" "mtjmpr") |
fe7f5677 | 556 | (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 557 | 4 1) |
cfb557c4 | 558 | |
c859cda6 DJ |
559 | (define_function_unit "sru" 1 0 |
560 | (and (eq_attr "type" "mtjmpr") | |
561 | (eq_attr "cpu" "ppc750,ppc7400")) | |
562 | 2 2) | |
563 | ||
564 | (define_function_unit "imuldiv" 1 0 | |
565 | (and (eq_attr "type" "mtjmpr") | |
566 | (eq_attr "cpu" "ppc7450")) | |
567 | 2 2) | |
568 | ||
39a10a29 GK |
569 | (define_function_unit "bpu" 1 0 |
570 | (and (eq_attr "type" "cr_logical") | |
5638268e | 571 | (eq_attr "cpu" "rios1,rios2,ppc604")) |
39a10a29 GK |
572 | 4 1) |
573 | ||
574 | (define_function_unit "cru" 1 0 | |
575 | (and (eq_attr "type" "cr_logical") | |
5638268e DE |
576 | (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a")) |
577 | 1 1) | |
39a10a29 | 578 | |
b6c9286a MM |
579 | ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines. |
580 | (define_function_unit "bpu" 1 0 | |
581 | (eq_attr "type" "jmpreg") | |
b7ff3d82 | 582 | 1 1) |
b6c9286a MM |
583 | |
584 | (define_function_unit "bpu" 1 0 | |
585 | (eq_attr "type" "branch") | |
b7ff3d82 | 586 | 1 1) |
b6c9286a | 587 | |
cf27b467 | 588 | ; Floating Point Unit |
cfb557c4 | 589 | (define_function_unit "fpu" 1 0 |
51b8fc2c | 590 | (and (eq_attr "type" "fp,dmul") |
2661cdd9 | 591 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 592 | 2 1) |
cfb557c4 | 593 | |
cf27b467 MM |
594 | (define_function_unit "fpu" 1 0 |
595 | (and (eq_attr "type" "fp") | |
3cb999d8 DE |
596 | (eq_attr "cpu" "rs64a,mpccore")) |
597 | 4 2) | |
cf27b467 | 598 | |
cfb557c4 RK |
599 | (define_function_unit "fpu" 1 0 |
600 | (and (eq_attr "type" "fp") | |
51b8fc2c | 601 | (eq_attr "cpu" "ppc601")) |
b7ff3d82 | 602 | 4 1) |
cfb557c4 | 603 | |
51b8fc2c RK |
604 | (define_function_unit "fpu" 1 0 |
605 | (and (eq_attr "type" "fp") | |
ed947a96 | 606 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750,ppc7400")) |
b6c9286a | 607 | 3 1) |
51b8fc2c | 608 | |
ed947a96 DJ |
609 | (define_function_unit "fpu" 1 0 |
610 | (and (eq_attr "type" "fp,dmul") | |
611 | (eq_attr "cpu" "ppc7450")) | |
612 | 5 1) | |
613 | ||
3cb999d8 DE |
614 | (define_function_unit "fpu" 1 0 |
615 | (and (eq_attr "type" "dmul") | |
616 | (eq_attr "cpu" "rs64a")) | |
617 | 7 2) | |
618 | ||
cf27b467 MM |
619 | (define_function_unit "fpu" 1 0 |
620 | (and (eq_attr "type" "dmul") | |
621 | (eq_attr "cpu" "mpccore")) | |
622 | 5 5) | |
623 | ||
cfb557c4 RK |
624 | (define_function_unit "fpu" 1 0 |
625 | (and (eq_attr "type" "dmul") | |
51b8fc2c | 626 | (eq_attr "cpu" "ppc601")) |
b6c9286a | 627 | 5 2) |
cfb557c4 | 628 | |
b6c9286a | 629 | ; is this true? |
cfb557c4 RK |
630 | (define_function_unit "fpu" 1 0 |
631 | (and (eq_attr "type" "dmul") | |
bef84347 | 632 | (eq_attr "cpu" "ppc603,ppc750")) |
51b8fc2c | 633 | 4 2) |
cfb557c4 RK |
634 | |
635 | (define_function_unit "fpu" 1 0 | |
51b8fc2c | 636 | (and (eq_attr "type" "dmul") |
ed947a96 | 637 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc7400")) |
b6c9286a | 638 | 3 1) |
51b8fc2c RK |
639 | |
640 | (define_function_unit "fpu" 1 0 | |
641 | (and (eq_attr "type" "sdiv,ddiv") | |
2661cdd9 | 642 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 643 | 19 19) |
cfb557c4 | 644 | |
3cb999d8 DE |
645 | (define_function_unit "fpu" 1 0 |
646 | (and (eq_attr "type" "sdiv") | |
647 | (eq_attr "cpu" "rs64a")) | |
648 | 31 31) | |
649 | ||
cfb557c4 RK |
650 | (define_function_unit "fpu" 1 0 |
651 | (and (eq_attr "type" "sdiv") | |
ed947a96 | 652 | (eq_attr "cpu" "ppc601,ppc750,ppc7400")) |
51b8fc2c RK |
653 | 17 17) |
654 | ||
ed947a96 DJ |
655 | (define_function_unit "fpu" 1 0 |
656 | (and (eq_attr "type" "sdiv") | |
657 | (eq_attr "cpu" "ppc7450")) | |
658 | 21 21) | |
659 | ||
cf27b467 MM |
660 | (define_function_unit "fpu" 1 0 |
661 | (and (eq_attr "type" "sdiv") | |
662 | (eq_attr "cpu" "mpccore")) | |
663 | 10 10) | |
664 | ||
51b8fc2c RK |
665 | (define_function_unit "fpu" 1 0 |
666 | (and (eq_attr "type" "sdiv") | |
cac8ce95 | 667 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620")) |
51b8fc2c | 668 | 18 18) |
cfb557c4 | 669 | |
cf27b467 MM |
670 | (define_function_unit "fpu" 1 0 |
671 | (and (eq_attr "type" "ddiv") | |
672 | (eq_attr "cpu" "mpccore")) | |
673 | 17 17) | |
674 | ||
cfb557c4 RK |
675 | (define_function_unit "fpu" 1 0 |
676 | (and (eq_attr "type" "ddiv") | |
ed947a96 | 677 | (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620,ppc7400")) |
51b8fc2c | 678 | 31 31) |
cfb557c4 | 679 | |
ed947a96 DJ |
680 | (define_function_unit "fpu" 1 0 |
681 | (and (eq_attr "type" "ddiv") | |
682 | (eq_attr "cpu" "ppc7450")) | |
683 | 35 35) | |
684 | ||
cfb557c4 RK |
685 | (define_function_unit "fpu" 1 0 |
686 | (and (eq_attr "type" "ddiv") | |
b7ff3d82 | 687 | (eq_attr "cpu" "ppc603")) |
51b8fc2c | 688 | 33 33) |
cfb557c4 RK |
689 | |
690 | (define_function_unit "fpu" 1 0 | |
691 | (and (eq_attr "type" "ssqrt") | |
a473029f | 692 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 693 | 31 31) |
cfb557c4 RK |
694 | |
695 | (define_function_unit "fpu" 1 0 | |
696 | (and (eq_attr "type" "dsqrt") | |
a473029f | 697 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 698 | 31 31) |
b73d04f2 | 699 | |
51b8fc2c | 700 | ; RIOS2 has two symmetric FPUs. |
cfb557c4 RK |
701 | (define_function_unit "fpu2" 2 0 |
702 | (and (eq_attr "type" "fp") | |
4652f1d4 | 703 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 704 | 2 1) |
cfb557c4 | 705 | |
3cb999d8 DE |
706 | (define_function_unit "fpu2" 2 0 |
707 | (and (eq_attr "type" "fp") | |
708 | (eq_attr "cpu" "ppc630")) | |
709 | 3 1) | |
710 | ||
cfb557c4 RK |
711 | (define_function_unit "fpu2" 2 0 |
712 | (and (eq_attr "type" "dmul") | |
713 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 714 | 2 1) |
cfb557c4 | 715 | |
3cb999d8 DE |
716 | (define_function_unit "fpu2" 2 0 |
717 | (and (eq_attr "type" "dmul") | |
718 | (eq_attr "cpu" "ppc630")) | |
719 | 3 1) | |
720 | ||
cfb557c4 | 721 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 722 | (and (eq_attr "type" "sdiv,ddiv") |
cfb557c4 | 723 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 724 | 17 17) |
ca7f5001 | 725 | |
3cb999d8 DE |
726 | (define_function_unit "fpu2" 2 0 |
727 | (and (eq_attr "type" "sdiv") | |
728 | (eq_attr "cpu" "ppc630")) | |
729 | 17 17) | |
730 | ||
731 | (define_function_unit "fpu2" 2 0 | |
732 | (and (eq_attr "type" "ddiv") | |
733 | (eq_attr "cpu" "ppc630")) | |
734 | 21 21) | |
735 | ||
ca7f5001 | 736 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 737 | (and (eq_attr "type" "ssqrt,dsqrt") |
ca7f5001 | 738 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 739 | 26 26) |
b6c9286a | 740 | |
3cb999d8 DE |
741 | (define_function_unit "fpu2" 2 0 |
742 | (and (eq_attr "type" "ssqrt") | |
743 | (eq_attr "cpu" "ppc630")) | |
744 | 18 18) | |
745 | ||
746 | (define_function_unit "fpu2" 2 0 | |
747 | (and (eq_attr "type" "dsqrt") | |
748 | (eq_attr "cpu" "ppc630")) | |
749 | 26 26) | |
750 | ||
1fd4e8c1 RK |
751 | \f |
752 | ;; Start with fixed-point load and store insns. Here we put only the more | |
753 | ;; complex forms. Basic data transfer is done later. | |
754 | ||
51b8fc2c RK |
755 | (define_expand "zero_extendqidi2" |
756 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
757 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
758 | "TARGET_POWERPC64" | |
759 | "") | |
760 | ||
761 | (define_insn "" | |
762 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
763 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
764 | "TARGET_POWERPC64" | |
765 | "@ | |
766 | lbz%U1%X1 %0,%1 | |
4371f8af | 767 | rldicl %0,%1,0,56" |
51b8fc2c RK |
768 | [(set_attr "type" "load,*")]) |
769 | ||
770 | (define_insn "" | |
9ebbca7d GK |
771 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
772 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 773 | (const_int 0))) |
9ebbca7d | 774 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 775 | "TARGET_POWERPC64" |
9ebbca7d GK |
776 | "@ |
777 | rldicl. %2,%1,0,56 | |
778 | #" | |
779 | [(set_attr "type" "compare") | |
780 | (set_attr "length" "4,8")]) | |
781 | ||
782 | (define_split | |
783 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
784 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
785 | (const_int 0))) | |
786 | (clobber (match_scratch:DI 2 ""))] | |
787 | "TARGET_POWERPC64 && reload_completed" | |
788 | [(set (match_dup 2) | |
789 | (zero_extend:DI (match_dup 1))) | |
790 | (set (match_dup 0) | |
791 | (compare:CC (match_dup 2) | |
792 | (const_int 0)))] | |
793 | "") | |
51b8fc2c RK |
794 | |
795 | (define_insn "" | |
9ebbca7d GK |
796 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
797 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 798 | (const_int 0))) |
9ebbca7d | 799 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 800 | (zero_extend:DI (match_dup 1)))] |
58e09803 | 801 | "TARGET_POWERPC64" |
9ebbca7d GK |
802 | "@ |
803 | rldicl. %0,%1,0,56 | |
804 | #" | |
805 | [(set_attr "type" "compare") | |
806 | (set_attr "length" "4,8")]) | |
807 | ||
808 | (define_split | |
809 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
810 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
811 | (const_int 0))) | |
812 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
813 | (zero_extend:DI (match_dup 1)))] | |
814 | "TARGET_POWERPC64 && reload_completed" | |
815 | [(set (match_dup 0) | |
816 | (zero_extend:DI (match_dup 1))) | |
817 | (set (match_dup 2) | |
818 | (compare:CC (match_dup 0) | |
819 | (const_int 0)))] | |
820 | "") | |
51b8fc2c | 821 | |
2bee0449 RK |
822 | (define_insn "extendqidi2" |
823 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
824 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 825 | "TARGET_POWERPC64" |
2bee0449 | 826 | "extsb %0,%1") |
51b8fc2c RK |
827 | |
828 | (define_insn "" | |
9ebbca7d GK |
829 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
830 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 831 | (const_int 0))) |
9ebbca7d | 832 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 833 | "TARGET_POWERPC64" |
9ebbca7d GK |
834 | "@ |
835 | extsb. %2,%1 | |
836 | #" | |
837 | [(set_attr "type" "compare") | |
838 | (set_attr "length" "4,8")]) | |
839 | ||
840 | (define_split | |
841 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
842 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
843 | (const_int 0))) | |
844 | (clobber (match_scratch:DI 2 ""))] | |
845 | "TARGET_POWERPC64 && reload_completed" | |
846 | [(set (match_dup 2) | |
847 | (sign_extend:DI (match_dup 1))) | |
848 | (set (match_dup 0) | |
849 | (compare:CC (match_dup 2) | |
850 | (const_int 0)))] | |
851 | "") | |
51b8fc2c RK |
852 | |
853 | (define_insn "" | |
9ebbca7d GK |
854 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
855 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 856 | (const_int 0))) |
9ebbca7d | 857 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
858 | (sign_extend:DI (match_dup 1)))] |
859 | "TARGET_POWERPC64" | |
9ebbca7d GK |
860 | "@ |
861 | extsb. %0,%1 | |
862 | #" | |
863 | [(set_attr "type" "compare") | |
864 | (set_attr "length" "4,8")]) | |
865 | ||
866 | (define_split | |
867 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
868 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
869 | (const_int 0))) | |
870 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
871 | (sign_extend:DI (match_dup 1)))] | |
872 | "TARGET_POWERPC64 && reload_completed" | |
873 | [(set (match_dup 0) | |
874 | (sign_extend:DI (match_dup 1))) | |
875 | (set (match_dup 2) | |
876 | (compare:CC (match_dup 0) | |
877 | (const_int 0)))] | |
878 | "") | |
51b8fc2c RK |
879 | |
880 | (define_expand "zero_extendhidi2" | |
881 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
882 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
883 | "TARGET_POWERPC64" | |
884 | "") | |
885 | ||
886 | (define_insn "" | |
887 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
888 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
889 | "TARGET_POWERPC64" | |
890 | "@ | |
891 | lhz%U1%X1 %0,%1 | |
4371f8af | 892 | rldicl %0,%1,0,48" |
51b8fc2c RK |
893 | [(set_attr "type" "load,*")]) |
894 | ||
895 | (define_insn "" | |
9ebbca7d GK |
896 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
897 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 898 | (const_int 0))) |
9ebbca7d | 899 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 900 | "TARGET_POWERPC64" |
9ebbca7d GK |
901 | "@ |
902 | rldicl. %2,%1,0,48 | |
903 | #" | |
904 | [(set_attr "type" "compare") | |
905 | (set_attr "length" "4,8")]) | |
906 | ||
907 | (define_split | |
908 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
909 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
910 | (const_int 0))) | |
911 | (clobber (match_scratch:DI 2 ""))] | |
912 | "TARGET_POWERPC64 && reload_completed" | |
913 | [(set (match_dup 2) | |
914 | (zero_extend:DI (match_dup 1))) | |
915 | (set (match_dup 0) | |
916 | (compare:CC (match_dup 2) | |
917 | (const_int 0)))] | |
918 | "") | |
51b8fc2c RK |
919 | |
920 | (define_insn "" | |
9ebbca7d GK |
921 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
922 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 923 | (const_int 0))) |
9ebbca7d | 924 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
925 | (zero_extend:DI (match_dup 1)))] |
926 | "TARGET_POWERPC64" | |
9ebbca7d GK |
927 | "@ |
928 | rldicl. %0,%1,0,48 | |
929 | #" | |
930 | [(set_attr "type" "compare") | |
931 | (set_attr "length" "4,8")]) | |
932 | ||
933 | (define_split | |
934 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
935 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
936 | (const_int 0))) | |
937 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
938 | (zero_extend:DI (match_dup 1)))] | |
939 | "TARGET_POWERPC64 && reload_completed" | |
940 | [(set (match_dup 0) | |
941 | (zero_extend:DI (match_dup 1))) | |
942 | (set (match_dup 2) | |
943 | (compare:CC (match_dup 0) | |
944 | (const_int 0)))] | |
945 | "") | |
51b8fc2c RK |
946 | |
947 | (define_expand "extendhidi2" | |
948 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
949 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
950 | "TARGET_POWERPC64" | |
951 | "") | |
952 | ||
953 | (define_insn "" | |
954 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
955 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
956 | "TARGET_POWERPC64" | |
957 | "@ | |
958 | lha%U1%X1 %0,%1 | |
959 | extsh %0,%1" | |
960 | [(set_attr "type" "load,*")]) | |
961 | ||
962 | (define_insn "" | |
9ebbca7d GK |
963 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
964 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 965 | (const_int 0))) |
9ebbca7d | 966 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 967 | "TARGET_POWERPC64" |
9ebbca7d GK |
968 | "@ |
969 | extsh. %2,%1 | |
970 | #" | |
971 | [(set_attr "type" "compare") | |
972 | (set_attr "length" "4,8")]) | |
973 | ||
974 | (define_split | |
975 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
976 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
977 | (const_int 0))) | |
978 | (clobber (match_scratch:DI 2 ""))] | |
979 | "TARGET_POWERPC64 && reload_completed" | |
980 | [(set (match_dup 2) | |
981 | (sign_extend:DI (match_dup 1))) | |
982 | (set (match_dup 0) | |
983 | (compare:CC (match_dup 2) | |
984 | (const_int 0)))] | |
985 | "") | |
51b8fc2c RK |
986 | |
987 | (define_insn "" | |
9ebbca7d GK |
988 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
989 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 990 | (const_int 0))) |
9ebbca7d | 991 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
992 | (sign_extend:DI (match_dup 1)))] |
993 | "TARGET_POWERPC64" | |
9ebbca7d GK |
994 | "@ |
995 | extsh. %0,%1 | |
996 | #" | |
997 | [(set_attr "type" "compare") | |
998 | (set_attr "length" "4,8")]) | |
999 | ||
1000 | (define_split | |
1001 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1002 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1003 | (const_int 0))) | |
1004 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
1005 | (sign_extend:DI (match_dup 1)))] | |
1006 | "TARGET_POWERPC64 && reload_completed" | |
1007 | [(set (match_dup 0) | |
1008 | (sign_extend:DI (match_dup 1))) | |
1009 | (set (match_dup 2) | |
1010 | (compare:CC (match_dup 0) | |
1011 | (const_int 0)))] | |
1012 | "") | |
51b8fc2c RK |
1013 | |
1014 | (define_expand "zero_extendsidi2" | |
1015 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1016 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1017 | "TARGET_POWERPC64" | |
1018 | "") | |
1019 | ||
1020 | (define_insn "" | |
1021 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
1022 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
1023 | "TARGET_POWERPC64" | |
1024 | "@ | |
1025 | lwz%U1%X1 %0,%1 | |
1026 | rldicl %0,%1,0,32" | |
1027 | [(set_attr "type" "load,*")]) | |
1028 | ||
1029 | (define_insn "" | |
9ebbca7d GK |
1030 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1031 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1032 | (const_int 0))) |
9ebbca7d | 1033 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 1034 | "TARGET_POWERPC64" |
9ebbca7d GK |
1035 | "@ |
1036 | rldicl. %2,%1,0,32 | |
1037 | #" | |
1038 | [(set_attr "type" "compare") | |
1039 | (set_attr "length" "4,8")]) | |
1040 | ||
1041 | (define_split | |
1042 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1043 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1044 | (const_int 0))) | |
1045 | (clobber (match_scratch:DI 2 ""))] | |
1046 | "TARGET_POWERPC64 && reload_completed" | |
1047 | [(set (match_dup 2) | |
1048 | (zero_extend:DI (match_dup 1))) | |
1049 | (set (match_dup 0) | |
1050 | (compare:CC (match_dup 2) | |
1051 | (const_int 0)))] | |
1052 | "") | |
51b8fc2c RK |
1053 | |
1054 | (define_insn "" | |
9ebbca7d GK |
1055 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1056 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1057 | (const_int 0))) |
9ebbca7d | 1058 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1059 | (zero_extend:DI (match_dup 1)))] |
1060 | "TARGET_POWERPC64" | |
9ebbca7d GK |
1061 | "@ |
1062 | rldicl. %0,%1,0,32 | |
1063 | #" | |
1064 | [(set_attr "type" "compare") | |
1065 | (set_attr "length" "4,8")]) | |
1066 | ||
1067 | (define_split | |
1068 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1069 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1070 | (const_int 0))) | |
1071 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
1072 | (zero_extend:DI (match_dup 1)))] | |
1073 | "TARGET_POWERPC64 && reload_completed" | |
1074 | [(set (match_dup 0) | |
1075 | (zero_extend:DI (match_dup 1))) | |
1076 | (set (match_dup 2) | |
1077 | (compare:CC (match_dup 0) | |
1078 | (const_int 0)))] | |
1079 | "") | |
51b8fc2c RK |
1080 | |
1081 | (define_expand "extendsidi2" | |
1082 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1083 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1084 | "TARGET_POWERPC64" | |
1085 | "") | |
1086 | ||
1087 | (define_insn "" | |
1088 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 1089 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
1090 | "TARGET_POWERPC64" |
1091 | "@ | |
1092 | lwa%U1%X1 %0,%1 | |
1093 | extsw %0,%1" | |
1094 | [(set_attr "type" "load,*")]) | |
1095 | ||
1096 | (define_insn "" | |
9ebbca7d GK |
1097 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1098 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1099 | (const_int 0))) |
9ebbca7d | 1100 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 1101 | "TARGET_POWERPC64" |
9ebbca7d GK |
1102 | "@ |
1103 | extsw. %2,%1 | |
1104 | #" | |
1105 | [(set_attr "type" "compare") | |
1106 | (set_attr "length" "4,8")]) | |
1107 | ||
1108 | (define_split | |
1109 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1110 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1111 | (const_int 0))) | |
1112 | (clobber (match_scratch:DI 2 ""))] | |
1113 | "TARGET_POWERPC64 && reload_completed" | |
1114 | [(set (match_dup 2) | |
1115 | (sign_extend:DI (match_dup 1))) | |
1116 | (set (match_dup 0) | |
1117 | (compare:CC (match_dup 2) | |
1118 | (const_int 0)))] | |
1119 | "") | |
51b8fc2c RK |
1120 | |
1121 | (define_insn "" | |
9ebbca7d GK |
1122 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1123 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1124 | (const_int 0))) |
9ebbca7d | 1125 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1126 | (sign_extend:DI (match_dup 1)))] |
1127 | "TARGET_POWERPC64" | |
9ebbca7d GK |
1128 | "@ |
1129 | extsw. %0,%1 | |
1130 | #" | |
1131 | [(set_attr "type" "compare") | |
1132 | (set_attr "length" "4,8")]) | |
1133 | ||
1134 | (define_split | |
1135 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1136 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1137 | (const_int 0))) | |
1138 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
1139 | (sign_extend:DI (match_dup 1)))] | |
1140 | "TARGET_POWERPC64 && reload_completed" | |
1141 | [(set (match_dup 0) | |
1142 | (sign_extend:DI (match_dup 1))) | |
1143 | (set (match_dup 2) | |
1144 | (compare:CC (match_dup 0) | |
1145 | (const_int 0)))] | |
1146 | "") | |
51b8fc2c | 1147 | |
1fd4e8c1 | 1148 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
1149 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1150 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1151 | "" |
1152 | "") | |
1153 | ||
1154 | (define_insn "" | |
cd2b37d9 | 1155 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1156 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
1157 | "" | |
1158 | "@ | |
1159 | lbz%U1%X1 %0,%1 | |
005a35b9 | 1160 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
1161 | [(set_attr "type" "load,*")]) |
1162 | ||
1163 | (define_insn "" | |
9ebbca7d GK |
1164 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1165 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1166 | (const_int 0))) |
9ebbca7d | 1167 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1168 | "" |
9ebbca7d GK |
1169 | "@ |
1170 | {andil.|andi.} %2,%1,0xff | |
1171 | #" | |
1172 | [(set_attr "type" "compare") | |
1173 | (set_attr "length" "4,8")]) | |
1174 | ||
1175 | (define_split | |
1176 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1177 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1178 | (const_int 0))) | |
1179 | (clobber (match_scratch:SI 2 ""))] | |
1180 | "reload_completed" | |
1181 | [(set (match_dup 2) | |
1182 | (zero_extend:SI (match_dup 1))) | |
1183 | (set (match_dup 0) | |
1184 | (compare:CC (match_dup 2) | |
1185 | (const_int 0)))] | |
1186 | "") | |
1fd4e8c1 RK |
1187 | |
1188 | (define_insn "" | |
9ebbca7d GK |
1189 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1190 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1191 | (const_int 0))) |
9ebbca7d | 1192 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1193 | (zero_extend:SI (match_dup 1)))] |
1194 | "" | |
9ebbca7d GK |
1195 | "@ |
1196 | {andil.|andi.} %0,%1,0xff | |
1197 | #" | |
1198 | [(set_attr "type" "compare") | |
1199 | (set_attr "length" "4,8")]) | |
1200 | ||
1201 | (define_split | |
1202 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1203 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1204 | (const_int 0))) | |
1205 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1206 | (zero_extend:SI (match_dup 1)))] | |
1207 | "reload_completed" | |
1208 | [(set (match_dup 0) | |
1209 | (zero_extend:SI (match_dup 1))) | |
1210 | (set (match_dup 2) | |
1211 | (compare:CC (match_dup 0) | |
1212 | (const_int 0)))] | |
1213 | "") | |
1fd4e8c1 | 1214 | |
51b8fc2c RK |
1215 | (define_expand "extendqisi2" |
1216 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1217 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
1218 | "" | |
1219 | " | |
1220 | { | |
1221 | if (TARGET_POWERPC) | |
1222 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
1223 | else if (TARGET_POWER) | |
1224 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
1225 | else | |
1226 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
1227 | DONE; | |
1228 | }") | |
1229 | ||
1230 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
1231 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1232 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 1233 | "TARGET_POWERPC" |
2bee0449 | 1234 | "extsb %0,%1") |
51b8fc2c RK |
1235 | |
1236 | (define_insn "" | |
9ebbca7d GK |
1237 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1238 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1239 | (const_int 0))) |
9ebbca7d | 1240 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 1241 | "TARGET_POWERPC" |
9ebbca7d GK |
1242 | "@ |
1243 | extsb. %2,%1 | |
1244 | #" | |
1245 | [(set_attr "type" "compare") | |
1246 | (set_attr "length" "4,8")]) | |
1247 | ||
1248 | (define_split | |
1249 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1250 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1251 | (const_int 0))) | |
1252 | (clobber (match_scratch:SI 2 ""))] | |
1253 | "TARGET_POWERPC && reload_completed" | |
1254 | [(set (match_dup 2) | |
1255 | (sign_extend:SI (match_dup 1))) | |
1256 | (set (match_dup 0) | |
1257 | (compare:CC (match_dup 2) | |
1258 | (const_int 0)))] | |
1259 | "") | |
51b8fc2c RK |
1260 | |
1261 | (define_insn "" | |
9ebbca7d GK |
1262 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1263 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1264 | (const_int 0))) |
9ebbca7d | 1265 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1266 | (sign_extend:SI (match_dup 1)))] |
1267 | "TARGET_POWERPC" | |
9ebbca7d GK |
1268 | "@ |
1269 | extsb. %0,%1 | |
1270 | #" | |
1271 | [(set_attr "type" "compare") | |
1272 | (set_attr "length" "4,8")]) | |
1273 | ||
1274 | (define_split | |
1275 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1276 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1277 | (const_int 0))) | |
1278 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1279 | (sign_extend:SI (match_dup 1)))] | |
1280 | "TARGET_POWERPC && reload_completed" | |
1281 | [(set (match_dup 0) | |
1282 | (sign_extend:SI (match_dup 1))) | |
1283 | (set (match_dup 2) | |
1284 | (compare:CC (match_dup 0) | |
1285 | (const_int 0)))] | |
1286 | "") | |
51b8fc2c RK |
1287 | |
1288 | (define_expand "extendqisi2_power" | |
1289 | [(parallel [(set (match_dup 2) | |
1290 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1291 | (const_int 24))) | |
1292 | (clobber (scratch:SI))]) | |
1293 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1294 | (ashiftrt:SI (match_dup 2) | |
1295 | (const_int 24))) | |
1296 | (clobber (scratch:SI))])] | |
1297 | "TARGET_POWER" | |
1298 | " | |
1299 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1300 | operands[2] = gen_reg_rtx (SImode); }") | |
1301 | ||
1302 | (define_expand "extendqisi2_no_power" | |
1303 | [(set (match_dup 2) | |
1304 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1305 | (const_int 24))) | |
1306 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1307 | (ashiftrt:SI (match_dup 2) | |
1308 | (const_int 24)))] | |
1309 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1310 | " | |
1311 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1312 | operands[2] = gen_reg_rtx (SImode); }") | |
1313 | ||
1fd4e8c1 | 1314 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
1315 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
1316 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1317 | "" |
1318 | "") | |
1319 | ||
1320 | (define_insn "" | |
cd2b37d9 | 1321 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1322 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
1323 | "" | |
1324 | "@ | |
1325 | lbz%U1%X1 %0,%1 | |
005a35b9 | 1326 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
1327 | [(set_attr "type" "load,*")]) |
1328 | ||
1329 | (define_insn "" | |
9ebbca7d GK |
1330 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1331 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1332 | (const_int 0))) |
9ebbca7d | 1333 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 1334 | "" |
9ebbca7d GK |
1335 | "@ |
1336 | {andil.|andi.} %2,%1,0xff | |
1337 | #" | |
1338 | [(set_attr "type" "compare") | |
1339 | (set_attr "length" "4,8")]) | |
1340 | ||
1341 | (define_split | |
1342 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1343 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1344 | (const_int 0))) | |
1345 | (clobber (match_scratch:HI 2 ""))] | |
1346 | "reload_completed" | |
1347 | [(set (match_dup 2) | |
1348 | (zero_extend:HI (match_dup 1))) | |
1349 | (set (match_dup 0) | |
1350 | (compare:CC (match_dup 2) | |
1351 | (const_int 0)))] | |
1352 | "") | |
1fd4e8c1 | 1353 | |
51b8fc2c | 1354 | (define_insn "" |
9ebbca7d GK |
1355 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1356 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1357 | (const_int 0))) |
9ebbca7d | 1358 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
1359 | (zero_extend:HI (match_dup 1)))] |
1360 | "" | |
9ebbca7d GK |
1361 | "@ |
1362 | {andil.|andi.} %0,%1,0xff | |
1363 | #" | |
1364 | [(set_attr "type" "compare") | |
1365 | (set_attr "length" "4,8")]) | |
1366 | ||
1367 | (define_split | |
1368 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1369 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1370 | (const_int 0))) | |
1371 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1372 | (zero_extend:HI (match_dup 1)))] | |
1373 | "reload_completed" | |
1374 | [(set (match_dup 0) | |
1375 | (zero_extend:HI (match_dup 1))) | |
1376 | (set (match_dup 2) | |
1377 | (compare:CC (match_dup 0) | |
1378 | (const_int 0)))] | |
1379 | "") | |
815cdc52 MM |
1380 | |
1381 | (define_expand "extendqihi2" | |
1382 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
1383 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
1384 | "" | |
1385 | " | |
1386 | { | |
1387 | if (TARGET_POWERPC) | |
1388 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
1389 | else if (TARGET_POWER) | |
1390 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
1391 | else | |
1392 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
1393 | DONE; | |
1394 | }") | |
1395 | ||
1396 | (define_insn "extendqihi2_ppc" | |
1397 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
1398 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
1399 | "TARGET_POWERPC" | |
1400 | "extsb %0,%1") | |
1401 | ||
1402 | (define_insn "" | |
9ebbca7d GK |
1403 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1404 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1405 | (const_int 0))) |
9ebbca7d | 1406 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 1407 | "TARGET_POWERPC" |
9ebbca7d GK |
1408 | "@ |
1409 | extsb. %2,%1 | |
1410 | #" | |
1411 | [(set_attr "type" "compare") | |
1412 | (set_attr "length" "4,8")]) | |
1413 | ||
1414 | (define_split | |
1415 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1416 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1417 | (const_int 0))) | |
1418 | (clobber (match_scratch:HI 2 ""))] | |
1419 | "TARGET_POWERPC && reload_completed" | |
1420 | [(set (match_dup 2) | |
1421 | (sign_extend:HI (match_dup 1))) | |
1422 | (set (match_dup 0) | |
1423 | (compare:CC (match_dup 2) | |
1424 | (const_int 0)))] | |
1425 | "") | |
815cdc52 MM |
1426 | |
1427 | (define_insn "" | |
9ebbca7d GK |
1428 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1429 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1430 | (const_int 0))) |
9ebbca7d | 1431 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1432 | (sign_extend:HI (match_dup 1)))] |
1433 | "TARGET_POWERPC" | |
9ebbca7d GK |
1434 | "@ |
1435 | extsb. %0,%1 | |
1436 | #" | |
1437 | [(set_attr "type" "compare") | |
1438 | (set_attr "length" "4,8")]) | |
1439 | ||
1440 | (define_split | |
1441 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1442 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1443 | (const_int 0))) | |
1444 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1445 | (sign_extend:HI (match_dup 1)))] | |
1446 | "TARGET_POWERPC && reload_completed" | |
1447 | [(set (match_dup 0) | |
1448 | (sign_extend:HI (match_dup 1))) | |
1449 | (set (match_dup 2) | |
1450 | (compare:CC (match_dup 0) | |
1451 | (const_int 0)))] | |
1452 | "") | |
51b8fc2c RK |
1453 | |
1454 | (define_expand "extendqihi2_power" | |
1455 | [(parallel [(set (match_dup 2) | |
1456 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1457 | (const_int 24))) | |
1458 | (clobber (scratch:SI))]) | |
1459 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
1460 | (ashiftrt:SI (match_dup 2) | |
1461 | (const_int 24))) | |
1462 | (clobber (scratch:SI))])] | |
1463 | "TARGET_POWER" | |
1464 | " | |
1465 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1466 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1467 | operands[2] = gen_reg_rtx (SImode); }") | |
1468 | ||
1469 | (define_expand "extendqihi2_no_power" | |
1470 | [(set (match_dup 2) | |
1471 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1472 | (const_int 24))) | |
1473 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1474 | (ashiftrt:SI (match_dup 2) | |
1475 | (const_int 24)))] | |
1476 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1477 | " | |
1478 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1479 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1480 | operands[2] = gen_reg_rtx (SImode); }") | |
1481 | ||
1fd4e8c1 | 1482 | (define_expand "zero_extendhisi2" |
5f243543 | 1483 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 1484 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
1485 | "" |
1486 | "") | |
1487 | ||
1488 | (define_insn "" | |
cd2b37d9 | 1489 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1490 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1491 | "" | |
1492 | "@ | |
1493 | lhz%U1%X1 %0,%1 | |
005a35b9 | 1494 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
1495 | [(set_attr "type" "load,*")]) |
1496 | ||
1497 | (define_insn "" | |
9ebbca7d GK |
1498 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1499 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1500 | (const_int 0))) |
9ebbca7d | 1501 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1502 | "" |
9ebbca7d GK |
1503 | "@ |
1504 | {andil.|andi.} %2,%1,0xffff | |
1505 | #" | |
1506 | [(set_attr "type" "compare") | |
1507 | (set_attr "length" "4,8")]) | |
1508 | ||
1509 | (define_split | |
1510 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1511 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1512 | (const_int 0))) | |
1513 | (clobber (match_scratch:SI 2 ""))] | |
1514 | "reload_completed" | |
1515 | [(set (match_dup 2) | |
1516 | (zero_extend:SI (match_dup 1))) | |
1517 | (set (match_dup 0) | |
1518 | (compare:CC (match_dup 2) | |
1519 | (const_int 0)))] | |
1520 | "") | |
1fd4e8c1 RK |
1521 | |
1522 | (define_insn "" | |
9ebbca7d GK |
1523 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1524 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1525 | (const_int 0))) |
9ebbca7d | 1526 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1527 | (zero_extend:SI (match_dup 1)))] |
1528 | "" | |
9ebbca7d GK |
1529 | "@ |
1530 | {andil.|andi.} %0,%1,0xffff | |
1531 | #" | |
1532 | [(set_attr "type" "compare") | |
1533 | (set_attr "length" "4,8")]) | |
1534 | ||
1535 | (define_split | |
1536 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1537 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1538 | (const_int 0))) | |
1539 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1540 | (zero_extend:SI (match_dup 1)))] | |
1541 | "reload_completed" | |
1542 | [(set (match_dup 0) | |
1543 | (zero_extend:SI (match_dup 1))) | |
1544 | (set (match_dup 2) | |
1545 | (compare:CC (match_dup 0) | |
1546 | (const_int 0)))] | |
1547 | "") | |
1fd4e8c1 RK |
1548 | |
1549 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
1550 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1551 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1552 | "" |
1553 | "") | |
1554 | ||
1555 | (define_insn "" | |
cd2b37d9 | 1556 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1557 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1558 | "" | |
1559 | "@ | |
1560 | lha%U1%X1 %0,%1 | |
ca7f5001 | 1561 | {exts|extsh} %0,%1" |
1fd4e8c1 RK |
1562 | [(set_attr "type" "load,*")]) |
1563 | ||
1564 | (define_insn "" | |
9ebbca7d GK |
1565 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1566 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1567 | (const_int 0))) |
9ebbca7d | 1568 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1569 | "" |
9ebbca7d GK |
1570 | "@ |
1571 | {exts.|extsh.} %2,%1 | |
1572 | #" | |
1573 | [(set_attr "type" "compare") | |
1574 | (set_attr "length" "4,8")]) | |
1575 | ||
1576 | (define_split | |
1577 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1578 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1579 | (const_int 0))) | |
1580 | (clobber (match_scratch:SI 2 ""))] | |
1581 | "reload_completed" | |
1582 | [(set (match_dup 2) | |
1583 | (sign_extend:SI (match_dup 1))) | |
1584 | (set (match_dup 0) | |
1585 | (compare:CC (match_dup 2) | |
1586 | (const_int 0)))] | |
1587 | "") | |
1fd4e8c1 RK |
1588 | |
1589 | (define_insn "" | |
9ebbca7d GK |
1590 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1591 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1592 | (const_int 0))) |
9ebbca7d | 1593 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1594 | (sign_extend:SI (match_dup 1)))] |
1595 | "" | |
9ebbca7d GK |
1596 | "@ |
1597 | {exts.|extsh.} %0,%1 | |
1598 | #" | |
1599 | [(set_attr "type" "compare") | |
1600 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1601 | \f |
9ebbca7d GK |
1602 | (define_split |
1603 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1604 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1605 | (const_int 0))) | |
1606 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1607 | (sign_extend:SI (match_dup 1)))] | |
1608 | "reload_completed" | |
1609 | [(set (match_dup 0) | |
1610 | (sign_extend:SI (match_dup 1))) | |
1611 | (set (match_dup 2) | |
1612 | (compare:CC (match_dup 0) | |
1613 | (const_int 0)))] | |
1614 | "") | |
1615 | ||
1fd4e8c1 | 1616 | ;; Fixed-point arithmetic insns. |
deb9225a RK |
1617 | |
1618 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
1619 | ;; allowing register zero as source. | |
7cd5235b MM |
1620 | (define_expand "addsi3" |
1621 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1622 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 1623 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
7cd5235b MM |
1624 | "" |
1625 | " | |
1626 | { | |
677a9668 DE |
1627 | if (GET_CODE (operands[2]) == CONST_INT |
1628 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 1629 | { |
677a9668 | 1630 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
1631 | ? operands[0] : gen_reg_rtx (SImode)); |
1632 | ||
2bfcf297 | 1633 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1634 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 1635 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
7cd5235b | 1636 | |
9ebbca7d GK |
1637 | /* The ordering here is important for the prolog expander. |
1638 | When space is allocated from the stack, adding 'low' first may | |
1639 | produce a temporary deallocation (which would be bad). */ | |
2bfcf297 | 1640 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest))); |
7cd5235b MM |
1641 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); |
1642 | DONE; | |
1643 | } | |
1644 | }") | |
1645 | ||
1646 | (define_insn "*addsi3_internal1" | |
1647 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
1648 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 1649 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1650 | "" |
1651 | "@ | |
deb9225a RK |
1652 | {cax|add} %0,%1,%2 |
1653 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1654 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1655 | {cau|addis} %0,%1,%v2" |
1656 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1657 | |
ee890fe2 SS |
1658 | (define_insn "addsi3_high" |
1659 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1660 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1661 | (high:SI (match_operand 2 "" ""))))] | |
1662 | "TARGET_MACHO && !TARGET_64BIT" | |
1663 | "{cau|addis} %0,%1,ha16(%2)" | |
1664 | [(set_attr "length" "4")]) | |
1665 | ||
7cd5235b | 1666 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1667 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1668 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1669 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1670 | (const_int 0))) |
cb8cc086 | 1671 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
0ad91047 | 1672 | "! TARGET_POWERPC64" |
deb9225a RK |
1673 | "@ |
1674 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1675 | {ai.|addic.} %3,%1,%2 |
1676 | # | |
1677 | #" | |
1678 | [(set_attr "type" "compare") | |
1679 | (set_attr "length" "4,4,8,8")]) | |
1680 | ||
1681 | (define_split | |
1682 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1683 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1684 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1685 | (const_int 0))) | |
1686 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1687 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1688 | [(set (match_dup 3) |
1689 | (plus:SI (match_dup 1) | |
1690 | (match_dup 2))) | |
1691 | (set (match_dup 0) | |
1692 | (compare:CC (match_dup 3) | |
1693 | (const_int 0)))] | |
1694 | "") | |
7e69e155 | 1695 | |
7cd5235b | 1696 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1697 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1698 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1699 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1700 | (const_int 0))) |
cb8cc086 MM |
1701 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1702 | (plus:SI (match_dup 1) | |
1703 | (match_dup 2)))] | |
0ad91047 | 1704 | "! TARGET_POWERPC64" |
deb9225a RK |
1705 | "@ |
1706 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1707 | {ai.|addic.} %0,%1,%2 |
1708 | # | |
1709 | #" | |
1710 | [(set_attr "type" "compare") | |
1711 | (set_attr "length" "4,4,8,8")]) | |
1712 | ||
1713 | (define_split | |
1714 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1715 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1716 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1717 | (const_int 0))) | |
1718 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1719 | (plus:SI (match_dup 1) (match_dup 2)))] | |
0ad91047 | 1720 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1721 | [(set (match_dup 0) |
1722 | (plus:SI (match_dup 1) | |
1723 | (match_dup 2))) | |
1724 | (set (match_dup 3) | |
1725 | (compare:CC (match_dup 0) | |
1726 | (const_int 0)))] | |
1727 | "") | |
7e69e155 | 1728 | |
f357808b RK |
1729 | ;; Split an add that we can't do in one insn into two insns, each of which |
1730 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1731 | ;; add should be last in case the result gets used in an address. | |
1732 | ||
1733 | (define_split | |
cd2b37d9 RK |
1734 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1735 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1736 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1737 | "" |
f357808b RK |
1738 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1739 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1740 | " | |
1fd4e8c1 | 1741 | { |
2bfcf297 | 1742 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1743 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 1744 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
1fd4e8c1 | 1745 | |
2bfcf297 | 1746 | operands[3] = GEN_INT (rest); |
e6ca2c17 | 1747 | operands[4] = GEN_INT (low); |
1fd4e8c1 RK |
1748 | }") |
1749 | ||
8de2a197 | 1750 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1751 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1752 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1753 | "" |
ca7f5001 RK |
1754 | "nor %0,%1,%1") |
1755 | ||
1756 | (define_insn "" | |
52d3af72 DE |
1757 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1758 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1759 | (const_int 0))) |
52d3af72 | 1760 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1761 | "! TARGET_POWERPC64" |
52d3af72 DE |
1762 | "@ |
1763 | nor. %2,%1,%1 | |
1764 | #" | |
1765 | [(set_attr "type" "compare") | |
1766 | (set_attr "length" "4,8")]) | |
1767 | ||
1768 | (define_split | |
1769 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1770 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1771 | (const_int 0))) | |
1772 | (clobber (match_scratch:SI 2 ""))] | |
0ad91047 | 1773 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1774 | [(set (match_dup 2) |
1775 | (not:SI (match_dup 1))) | |
1776 | (set (match_dup 0) | |
1777 | (compare:CC (match_dup 2) | |
1778 | (const_int 0)))] | |
1779 | "") | |
ca7f5001 RK |
1780 | |
1781 | (define_insn "" | |
52d3af72 DE |
1782 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1783 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1784 | (const_int 0))) |
52d3af72 | 1785 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1786 | (not:SI (match_dup 1)))] |
0ad91047 | 1787 | "! TARGET_POWERPC64" |
52d3af72 DE |
1788 | "@ |
1789 | nor. %0,%1,%1 | |
1790 | #" | |
1791 | [(set_attr "type" "compare") | |
1792 | (set_attr "length" "4,8")]) | |
1793 | ||
1794 | (define_split | |
1795 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1796 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1797 | (const_int 0))) | |
1cb18e3c | 1798 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
52d3af72 | 1799 | (not:SI (match_dup 1)))] |
0ad91047 | 1800 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1801 | [(set (match_dup 0) |
1802 | (not:SI (match_dup 1))) | |
1803 | (set (match_dup 2) | |
1804 | (compare:CC (match_dup 0) | |
1805 | (const_int 0)))] | |
1806 | "") | |
1fd4e8c1 RK |
1807 | |
1808 | (define_insn "" | |
3d91674b RK |
1809 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1810 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1811 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1812 | "! TARGET_POWERPC" |
ca7f5001 | 1813 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1814 | |
deb9225a RK |
1815 | (define_insn "" |
1816 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1817 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1818 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1819 | "TARGET_POWERPC" | |
1820 | "@ | |
1821 | subf %0,%2,%1 | |
1822 | subfic %0,%2,%1") | |
1823 | ||
1fd4e8c1 | 1824 | (define_insn "" |
cb8cc086 MM |
1825 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1826 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1827 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1828 | (const_int 0))) |
cb8cc086 | 1829 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1830 | "! TARGET_POWERPC" |
cb8cc086 MM |
1831 | "@ |
1832 | {sf.|subfc.} %3,%2,%1 | |
1833 | #" | |
1834 | [(set_attr "type" "compare") | |
1835 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1836 | |
deb9225a | 1837 | (define_insn "" |
cb8cc086 MM |
1838 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1839 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1840 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1841 | (const_int 0))) |
cb8cc086 | 1842 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 1843 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
cb8cc086 MM |
1844 | "@ |
1845 | subf. %3,%2,%1 | |
1846 | #" | |
1847 | [(set_attr "type" "compare") | |
1848 | (set_attr "length" "4,8")]) | |
1849 | ||
1850 | (define_split | |
1851 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1852 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1853 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1854 | (const_int 0))) | |
1855 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1856 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1857 | [(set (match_dup 3) |
1858 | (minus:SI (match_dup 1) | |
1859 | (match_dup 2))) | |
1860 | (set (match_dup 0) | |
1861 | (compare:CC (match_dup 3) | |
1862 | (const_int 0)))] | |
1863 | "") | |
deb9225a | 1864 | |
1fd4e8c1 | 1865 | (define_insn "" |
cb8cc086 MM |
1866 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1867 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1868 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1869 | (const_int 0))) |
cb8cc086 | 1870 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1871 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1872 | "! TARGET_POWERPC" |
cb8cc086 MM |
1873 | "@ |
1874 | {sf.|subfc.} %0,%2,%1 | |
1875 | #" | |
1876 | [(set_attr "type" "compare") | |
1877 | (set_attr "length" "4,8")]) | |
815cdc52 | 1878 | |
29ae5b89 | 1879 | (define_insn "" |
cb8cc086 MM |
1880 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1881 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1882 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1883 | (const_int 0))) |
cb8cc086 MM |
1884 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1885 | (minus:SI (match_dup 1) | |
1886 | (match_dup 2)))] | |
0ad91047 | 1887 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
90612787 DE |
1888 | "@ |
1889 | subf. %0,%2,%1 | |
1890 | #" | |
cb8cc086 MM |
1891 | [(set_attr "type" "compare") |
1892 | (set_attr "length" "4,8")]) | |
1893 | ||
1894 | (define_split | |
1895 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1896 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1897 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1898 | (const_int 0))) | |
1899 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1900 | (minus:SI (match_dup 1) | |
1901 | (match_dup 2)))] | |
0ad91047 | 1902 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1903 | [(set (match_dup 0) |
1904 | (minus:SI (match_dup 1) | |
1905 | (match_dup 2))) | |
1906 | (set (match_dup 3) | |
1907 | (compare:CC (match_dup 0) | |
1908 | (const_int 0)))] | |
1909 | "") | |
deb9225a | 1910 | |
1fd4e8c1 | 1911 | (define_expand "subsi3" |
cd2b37d9 | 1912 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1913 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
f6bf7de2 | 1914 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
1fd4e8c1 | 1915 | "" |
a0044fb1 RK |
1916 | " |
1917 | { | |
1918 | if (GET_CODE (operands[2]) == CONST_INT) | |
1919 | { | |
1920 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1921 | negate_rtx (SImode, operands[2]))); | |
1922 | DONE; | |
1923 | } | |
1924 | }") | |
1fd4e8c1 RK |
1925 | |
1926 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1927 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1928 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1929 | ;; combine. | |
1fd4e8c1 RK |
1930 | |
1931 | (define_expand "sminsi3" | |
1932 | [(set (match_dup 3) | |
cd2b37d9 | 1933 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1934 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1935 | (const_int 0) | |
1936 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1937 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1938 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1939 | "TARGET_POWER" |
1fd4e8c1 RK |
1940 | " |
1941 | { operands[3] = gen_reg_rtx (SImode); }") | |
1942 | ||
95ac8e67 RK |
1943 | (define_split |
1944 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1945 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1946 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1947 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1948 | "TARGET_POWER" |
95ac8e67 RK |
1949 | [(set (match_dup 3) |
1950 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1951 | (const_int 0) | |
1952 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1953 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1954 | "") | |
1955 | ||
1fd4e8c1 RK |
1956 | (define_expand "smaxsi3" |
1957 | [(set (match_dup 3) | |
cd2b37d9 | 1958 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1959 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1960 | (const_int 0) | |
1961 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1962 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1963 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1964 | "TARGET_POWER" |
1fd4e8c1 RK |
1965 | " |
1966 | { operands[3] = gen_reg_rtx (SImode); }") | |
1967 | ||
95ac8e67 RK |
1968 | (define_split |
1969 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1970 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1971 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1972 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1973 | "TARGET_POWER" |
95ac8e67 RK |
1974 | [(set (match_dup 3) |
1975 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1976 | (const_int 0) | |
1977 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1978 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1979 | "") | |
1980 | ||
1fd4e8c1 | 1981 | (define_expand "uminsi3" |
cd2b37d9 | 1982 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1983 | (match_dup 5))) |
cd2b37d9 | 1984 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1985 | (match_dup 5))) |
1fd4e8c1 RK |
1986 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1987 | (const_int 0) | |
1988 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1989 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1990 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1991 | "TARGET_POWER" |
1fd4e8c1 | 1992 | " |
bb68ff55 MM |
1993 | { |
1994 | operands[3] = gen_reg_rtx (SImode); | |
1995 | operands[4] = gen_reg_rtx (SImode); | |
1996 | operands[5] = GEN_INT (-2147483647 - 1); | |
1997 | }") | |
1fd4e8c1 RK |
1998 | |
1999 | (define_expand "umaxsi3" | |
cd2b37d9 | 2000 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 2001 | (match_dup 5))) |
cd2b37d9 | 2002 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 2003 | (match_dup 5))) |
1fd4e8c1 RK |
2004 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
2005 | (const_int 0) | |
2006 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 2007 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 2008 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 2009 | "TARGET_POWER" |
1fd4e8c1 | 2010 | " |
bb68ff55 MM |
2011 | { |
2012 | operands[3] = gen_reg_rtx (SImode); | |
2013 | operands[4] = gen_reg_rtx (SImode); | |
2014 | operands[5] = GEN_INT (-2147483647 - 1); | |
2015 | }") | |
1fd4e8c1 RK |
2016 | |
2017 | (define_insn "" | |
cd2b37d9 RK |
2018 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2019 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 2020 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
2021 | (const_int 0) |
2022 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 2023 | "TARGET_POWER" |
1fd4e8c1 RK |
2024 | "doz%I2 %0,%1,%2") |
2025 | ||
2026 | (define_insn "" | |
9ebbca7d | 2027 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2028 | (compare:CC |
9ebbca7d GK |
2029 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
2030 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
2031 | (const_int 0) |
2032 | (minus:SI (match_dup 2) (match_dup 1))) | |
2033 | (const_int 0))) | |
9ebbca7d | 2034 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 2035 | "TARGET_POWER" |
9ebbca7d GK |
2036 | "@ |
2037 | doz%I2. %3,%1,%2 | |
2038 | #" | |
2039 | [(set_attr "type" "delayed_compare") | |
2040 | (set_attr "length" "4,8")]) | |
2041 | ||
2042 | (define_split | |
2043 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2044 | (compare:CC | |
2045 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
2046 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
2047 | (const_int 0) | |
2048 | (minus:SI (match_dup 2) (match_dup 1))) | |
2049 | (const_int 0))) | |
2050 | (clobber (match_scratch:SI 3 ""))] | |
2051 | "TARGET_POWER && reload_completed" | |
2052 | [(set (match_dup 3) | |
2053 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
2054 | (const_int 0) | |
2055 | (minus:SI (match_dup 2) (match_dup 1)))) | |
2056 | (set (match_dup 0) | |
2057 | (compare:CC (match_dup 3) | |
2058 | (const_int 0)))] | |
2059 | "") | |
1fd4e8c1 RK |
2060 | |
2061 | (define_insn "" | |
9ebbca7d | 2062 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2063 | (compare:CC |
9ebbca7d GK |
2064 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
2065 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
2066 | (const_int 0) |
2067 | (minus:SI (match_dup 2) (match_dup 1))) | |
2068 | (const_int 0))) | |
9ebbca7d | 2069 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
2070 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
2071 | (const_int 0) | |
2072 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 2073 | "TARGET_POWER" |
9ebbca7d GK |
2074 | "@ |
2075 | doz%I2. %0,%1,%2 | |
2076 | #" | |
2077 | [(set_attr "type" "delayed_compare") | |
2078 | (set_attr "length" "4,8")]) | |
2079 | ||
2080 | (define_split | |
2081 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2082 | (compare:CC | |
2083 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
2084 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
2085 | (const_int 0) | |
2086 | (minus:SI (match_dup 2) (match_dup 1))) | |
2087 | (const_int 0))) | |
2088 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2089 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
2090 | (const_int 0) | |
2091 | (minus:SI (match_dup 2) (match_dup 1))))] | |
2092 | "TARGET_POWER && reload_completed" | |
2093 | [(set (match_dup 0) | |
2094 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
2095 | (const_int 0) | |
2096 | (minus:SI (match_dup 2) (match_dup 1)))) | |
2097 | (set (match_dup 3) | |
2098 | (compare:CC (match_dup 0) | |
2099 | (const_int 0)))] | |
2100 | "") | |
1fd4e8c1 RK |
2101 | |
2102 | ;; We don't need abs with condition code because such comparisons should | |
2103 | ;; never be done. | |
ea9be077 MM |
2104 | (define_expand "abssi2" |
2105 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2106 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
2107 | "" | |
2108 | " | |
2109 | { | |
0ad91047 | 2110 | if (! TARGET_POWER) |
ea9be077 MM |
2111 | { |
2112 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
2113 | DONE; | |
2114 | } | |
2115 | }") | |
2116 | ||
2117 | (define_insn "abssi2_power" | |
cd2b37d9 RK |
2118 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2119 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 2120 | "TARGET_POWER" |
1fd4e8c1 RK |
2121 | "abs %0,%1") |
2122 | ||
ea9be077 MM |
2123 | (define_insn "abssi2_nopower" |
2124 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
2125 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
2126 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 2127 | "! TARGET_POWER" |
3595d104 MM |
2128 | "* |
2129 | { | |
2130 | return (TARGET_POWERPC) | |
2131 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\" | |
2132 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\"; | |
2133 | }" | |
ea9be077 MM |
2134 | [(set_attr "length" "12")]) |
2135 | ||
2136 | (define_split | |
1cb18e3c DE |
2137 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2138 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2139 | (clobber (match_scratch:SI 2 ""))] | |
0ad91047 | 2140 | "! TARGET_POWER && reload_completed" |
ea9be077 MM |
2141 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
2142 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 2143 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
2144 | "") |
2145 | ||
463b558b | 2146 | (define_insn "*nabs_power" |
cd2b37d9 RK |
2147 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2148 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 2149 | "TARGET_POWER" |
1fd4e8c1 RK |
2150 | "nabs %0,%1") |
2151 | ||
463b558b | 2152 | (define_insn "*nabs_no_power" |
ea9be077 MM |
2153 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
2154 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
2155 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 2156 | "! TARGET_POWER" |
3595d104 MM |
2157 | "* |
2158 | { | |
2159 | return (TARGET_POWERPC) | |
2160 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\" | |
2161 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\"; | |
2162 | }" | |
ea9be077 MM |
2163 | [(set_attr "length" "12")]) |
2164 | ||
2165 | (define_split | |
75540af0 JH |
2166 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2167 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))) | |
2168 | (clobber (match_scratch:SI 2 ""))] | |
0ad91047 | 2169 | "! TARGET_POWER && reload_completed" |
ea9be077 MM |
2170 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
2171 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 2172 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
2173 | "") |
2174 | ||
1fd4e8c1 | 2175 | (define_insn "negsi2" |
cd2b37d9 RK |
2176 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2177 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
2178 | "" |
2179 | "neg %0,%1") | |
2180 | ||
2181 | (define_insn "" | |
9ebbca7d GK |
2182 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2183 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2184 | (const_int 0))) |
9ebbca7d | 2185 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 2186 | "! TARGET_POWERPC64" |
9ebbca7d GK |
2187 | "@ |
2188 | neg. %2,%1 | |
2189 | #" | |
2190 | [(set_attr "type" "compare") | |
2191 | (set_attr "length" "4,8")]) | |
2192 | ||
2193 | (define_split | |
2194 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2195 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2196 | (const_int 0))) | |
2197 | (clobber (match_scratch:SI 2 ""))] | |
2198 | "! TARGET_POWERPC64 && reload_completed" | |
2199 | [(set (match_dup 2) | |
2200 | (neg:SI (match_dup 1))) | |
2201 | (set (match_dup 0) | |
2202 | (compare:CC (match_dup 2) | |
2203 | (const_int 0)))] | |
2204 | "") | |
1fd4e8c1 RK |
2205 | |
2206 | (define_insn "" | |
9ebbca7d GK |
2207 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
2208 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2209 | (const_int 0))) |
9ebbca7d | 2210 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 2211 | (neg:SI (match_dup 1)))] |
0ad91047 | 2212 | "! TARGET_POWERPC64" |
9ebbca7d GK |
2213 | "@ |
2214 | neg. %0,%1 | |
2215 | #" | |
2216 | [(set_attr "type" "compare") | |
2217 | (set_attr "length" "4,8")]) | |
2218 | ||
2219 | (define_split | |
2220 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
2221 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2222 | (const_int 0))) | |
2223 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2224 | (neg:SI (match_dup 1)))] | |
2225 | "! TARGET_POWERPC64 && reload_completed" | |
2226 | [(set (match_dup 0) | |
2227 | (neg:SI (match_dup 1))) | |
2228 | (set (match_dup 2) | |
2229 | (compare:CC (match_dup 0) | |
2230 | (const_int 0)))] | |
2231 | "") | |
1fd4e8c1 RK |
2232 | |
2233 | (define_insn "ffssi2" | |
242e8072 RK |
2234 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
2235 | (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 2236 | "" |
7f340546 | 2237 | "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" |
b19003d8 | 2238 | [(set_attr "length" "16")]) |
1fd4e8c1 | 2239 | |
ca7f5001 RK |
2240 | (define_expand "mulsi3" |
2241 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
2242 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
2243 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
2244 | "" | |
2245 | " | |
2246 | { | |
2247 | if (TARGET_POWER) | |
68b40e7e | 2248 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 2249 | else |
68b40e7e | 2250 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
2251 | DONE; |
2252 | }") | |
2253 | ||
68b40e7e | 2254 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
2255 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2256 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
2257 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
2258 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
2259 | "TARGET_POWER" |
2260 | "@ | |
2261 | {muls|mullw} %0,%1,%2 | |
2262 | {muli|mulli} %0,%1,%2" | |
c859cda6 DJ |
2263 | [(set (attr "type") |
2264 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") | |
2265 | (const_string "imul3") | |
2266 | (match_operand:SI 2 "short_cint_operand" "") | |
2267 | (const_string "imul2")] | |
2268 | (const_string "imul")))]) | |
ca7f5001 | 2269 | |
68b40e7e | 2270 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
2271 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2272 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2273 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 2274 | "! TARGET_POWER" |
1fd4e8c1 | 2275 | "@ |
d904e9ed RK |
2276 | {muls|mullw} %0,%1,%2 |
2277 | {muli|mulli} %0,%1,%2" | |
c859cda6 DJ |
2278 | [(set (attr "type") |
2279 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") | |
2280 | (const_string "imul3") | |
2281 | (match_operand:SI 2 "short_cint_operand" "") | |
2282 | (const_string "imul2")] | |
2283 | (const_string "imul")))]) | |
1fd4e8c1 RK |
2284 | |
2285 | (define_insn "" | |
9ebbca7d GK |
2286 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2287 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2288 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2289 | (const_int 0))) |
9ebbca7d GK |
2290 | (clobber (match_scratch:SI 3 "=r,r")) |
2291 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 2292 | "TARGET_POWER" |
9ebbca7d GK |
2293 | "@ |
2294 | {muls.|mullw.} %3,%1,%2 | |
2295 | #" | |
2296 | [(set_attr "type" "delayed_compare") | |
2297 | (set_attr "length" "4,8")]) | |
2298 | ||
2299 | (define_split | |
2300 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2301 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2302 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2303 | (const_int 0))) | |
2304 | (clobber (match_scratch:SI 3 "")) | |
2305 | (clobber (match_scratch:SI 4 ""))] | |
2306 | "TARGET_POWER && reload_completed" | |
2307 | [(parallel [(set (match_dup 3) | |
2308 | (mult:SI (match_dup 1) (match_dup 2))) | |
2309 | (clobber (match_dup 4))]) | |
2310 | (set (match_dup 0) | |
2311 | (compare:CC (match_dup 3) | |
2312 | (const_int 0)))] | |
2313 | "") | |
ca7f5001 RK |
2314 | |
2315 | (define_insn "" | |
9ebbca7d GK |
2316 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2317 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2318 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2319 | (const_int 0))) |
9ebbca7d | 2320 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 2321 | "! TARGET_POWER" |
9ebbca7d GK |
2322 | "@ |
2323 | {muls.|mullw.} %3,%1,%2 | |
2324 | #" | |
2325 | [(set_attr "type" "delayed_compare") | |
2326 | (set_attr "length" "4,8")]) | |
2327 | ||
2328 | (define_split | |
2329 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2330 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2331 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2332 | (const_int 0))) | |
2333 | (clobber (match_scratch:SI 3 ""))] | |
2334 | "! TARGET_POWER && reload_completed" | |
2335 | [(set (match_dup 3) | |
2336 | (mult:SI (match_dup 1) (match_dup 2))) | |
2337 | (set (match_dup 0) | |
2338 | (compare:CC (match_dup 3) | |
2339 | (const_int 0)))] | |
2340 | "") | |
1fd4e8c1 RK |
2341 | |
2342 | (define_insn "" | |
9ebbca7d GK |
2343 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2344 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2345 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2346 | (const_int 0))) |
9ebbca7d | 2347 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2348 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 2349 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 2350 | "TARGET_POWER" |
9ebbca7d GK |
2351 | "@ |
2352 | {muls.|mullw.} %0,%1,%2 | |
2353 | #" | |
2354 | [(set_attr "type" "delayed_compare") | |
2355 | (set_attr "length" "4,8")]) | |
2356 | ||
2357 | (define_split | |
2358 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2359 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2360 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2361 | (const_int 0))) | |
2362 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2363 | (mult:SI (match_dup 1) (match_dup 2))) | |
2364 | (clobber (match_scratch:SI 4 ""))] | |
2365 | "TARGET_POWER && reload_completed" | |
2366 | [(parallel [(set (match_dup 0) | |
2367 | (mult:SI (match_dup 1) (match_dup 2))) | |
2368 | (clobber (match_dup 4))]) | |
2369 | (set (match_dup 3) | |
2370 | (compare:CC (match_dup 0) | |
2371 | (const_int 0)))] | |
2372 | "") | |
ca7f5001 RK |
2373 | |
2374 | (define_insn "" | |
9ebbca7d GK |
2375 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2376 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2377 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2378 | (const_int 0))) |
9ebbca7d | 2379 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 2380 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 2381 | "! TARGET_POWER" |
9ebbca7d GK |
2382 | "@ |
2383 | {muls.|mullw.} %0,%1,%2 | |
2384 | #" | |
2385 | [(set_attr "type" "delayed_compare") | |
2386 | (set_attr "length" "4,8")]) | |
2387 | ||
2388 | (define_split | |
2389 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2390 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2391 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2392 | (const_int 0))) | |
2393 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2394 | (mult:SI (match_dup 1) (match_dup 2)))] | |
2395 | "! TARGET_POWER && reload_completed" | |
2396 | [(set (match_dup 0) | |
2397 | (mult:SI (match_dup 1) (match_dup 2))) | |
2398 | (set (match_dup 3) | |
2399 | (compare:CC (match_dup 0) | |
2400 | (const_int 0)))] | |
2401 | "") | |
1fd4e8c1 RK |
2402 | |
2403 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
2404 | ;; 0 and remainder to operand 3. | |
2405 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
2406 | ||
8ffd9c51 RK |
2407 | (define_expand "divmodsi4" |
2408 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2409 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2410 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2411 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
2412 | (mod:SI (match_dup 1) (match_dup 2)))])] | |
2413 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2414 | " | |
2415 | { | |
2416 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2417 | { | |
39403d82 DE |
2418 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2419 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2420 | emit_insn (gen_divss_call ()); |
39403d82 DE |
2421 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2422 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
2423 | DONE; |
2424 | } | |
2425 | }") | |
deb9225a | 2426 | |
fada905b | 2427 | (define_insn "" |
cd2b37d9 RK |
2428 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2429 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2430 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2431 | (set (match_operand:SI 3 "gpc_reg_operand" "=q") | |
1fd4e8c1 | 2432 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 2433 | "TARGET_POWER" |
cfb557c4 RK |
2434 | "divs %0,%1,%2" |
2435 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 2436 | |
8ffd9c51 RK |
2437 | (define_expand "udivsi3" |
2438 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2439 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2440 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
2441 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2442 | " | |
2443 | { | |
2444 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2445 | { | |
39403d82 DE |
2446 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2447 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2448 | emit_insn (gen_quous_call ()); |
39403d82 | 2449 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2450 | DONE; |
2451 | } | |
f192bf8b DE |
2452 | else if (TARGET_POWER) |
2453 | { | |
2454 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
2455 | DONE; | |
2456 | } | |
8ffd9c51 | 2457 | }") |
deb9225a | 2458 | |
f192bf8b DE |
2459 | (define_insn "udivsi3_mq" |
2460 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2461 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2462 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2463 | (clobber (match_scratch:SI 3 "=q"))] | |
2464 | "TARGET_POWERPC && TARGET_POWER" | |
2465 | "divwu %0,%1,%2" | |
2466 | [(set_attr "type" "idiv")]) | |
2467 | ||
2468 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
2469 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2470 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2471 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 2472 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 2473 | "divwu %0,%1,%2" |
ca7f5001 RK |
2474 | [(set_attr "type" "idiv")]) |
2475 | ||
1fd4e8c1 | 2476 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 2477 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
2478 | ;; used; for PowerPC, force operands into register and do a normal divide; |
2479 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 2480 | (define_expand "divsi3" |
cd2b37d9 RK |
2481 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2482 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
2483 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
2484 | "" | |
2485 | " | |
2486 | { | |
ca7f5001 | 2487 | if (GET_CODE (operands[2]) == CONST_INT |
2bfcf297 | 2488 | && INTVAL (operands[2]) > 0 |
ca7f5001 RK |
2489 | && exact_log2 (INTVAL (operands[2])) >= 0) |
2490 | ; | |
b6c9286a | 2491 | else if (TARGET_POWERPC) |
f192bf8b DE |
2492 | { |
2493 | operands[2] = force_reg (SImode, operands[2]); | |
2494 | if (TARGET_POWER) | |
2495 | { | |
2496 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
2497 | DONE; | |
2498 | } | |
2499 | } | |
b6c9286a | 2500 | else if (TARGET_POWER) |
1fd4e8c1 | 2501 | FAIL; |
405c5495 | 2502 | else |
8ffd9c51 | 2503 | { |
39403d82 DE |
2504 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2505 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2506 | emit_insn (gen_quoss_call ()); |
39403d82 | 2507 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2508 | DONE; |
2509 | } | |
1fd4e8c1 RK |
2510 | }") |
2511 | ||
f192bf8b DE |
2512 | (define_insn "divsi3_mq" |
2513 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2514 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2515 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2516 | (clobber (match_scratch:SI 3 "=q"))] | |
2517 | "TARGET_POWERPC && TARGET_POWER" | |
2518 | "divw %0,%1,%2" | |
2519 | [(set_attr "type" "idiv")]) | |
2520 | ||
2521 | (define_insn "*divsi3_no_mq" | |
2522 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2523 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2524 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
2525 | "TARGET_POWERPC && ! TARGET_POWER" | |
2526 | "divw %0,%1,%2" | |
2527 | [(set_attr "type" "idiv")]) | |
2528 | ||
1fd4e8c1 | 2529 | (define_expand "modsi3" |
85644414 RK |
2530 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
2531 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 2532 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 2533 | "" |
1fd4e8c1 RK |
2534 | " |
2535 | { | |
481c7efa | 2536 | int i; |
39b52ba2 RK |
2537 | rtx temp1; |
2538 | rtx temp2; | |
2539 | ||
2bfcf297 | 2540 | if (GET_CODE (operands[2]) != CONST_INT |
a65c591c | 2541 | || INTVAL (operands[2]) <= 0 |
2bfcf297 | 2542 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) |
39b52ba2 RK |
2543 | FAIL; |
2544 | ||
2545 | temp1 = gen_reg_rtx (SImode); | |
2546 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 2547 | |
85644414 | 2548 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 2549 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
2550 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
2551 | DONE; | |
1fd4e8c1 RK |
2552 | }") |
2553 | ||
2554 | (define_insn "" | |
cd2b37d9 RK |
2555 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2556 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
2557 | (match_operand:SI 2 "exact_log2_cint_operand" "N")))] |
2558 | "" | |
ca7f5001 | 2559 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 2560 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
2561 | |
2562 | (define_insn "" | |
9ebbca7d GK |
2563 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2564 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2565 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2566 | (const_int 0))) |
9ebbca7d | 2567 | (clobber (match_scratch:SI 3 "=r,r"))] |
2bfcf297 | 2568 | "" |
9ebbca7d GK |
2569 | "@ |
2570 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
2571 | #" | |
b19003d8 | 2572 | [(set_attr "type" "compare") |
9ebbca7d GK |
2573 | (set_attr "length" "8,12")]) |
2574 | ||
2575 | (define_split | |
2576 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2577 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2578 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2579 | (const_int 0))) |
2580 | (clobber (match_scratch:SI 3 ""))] | |
2bfcf297 | 2581 | "reload_completed" |
9ebbca7d GK |
2582 | [(set (match_dup 3) |
2583 | (div:SI (match_dup 1) (match_dup 2))) | |
2584 | (set (match_dup 0) | |
2585 | (compare:CC (match_dup 3) | |
2586 | (const_int 0)))] | |
2587 | "") | |
1fd4e8c1 RK |
2588 | |
2589 | (define_insn "" | |
9ebbca7d GK |
2590 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2591 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2592 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2593 | (const_int 0))) |
9ebbca7d | 2594 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2595 | (div:SI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 2596 | "" |
9ebbca7d GK |
2597 | "@ |
2598 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2599 | #" | |
b19003d8 | 2600 | [(set_attr "type" "compare") |
9ebbca7d GK |
2601 | (set_attr "length" "8,12")]) |
2602 | ||
2603 | (define_split | |
2604 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2605 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2606 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2607 | (const_int 0))) |
2608 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2609 | (div:SI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2610 | "reload_completed" |
9ebbca7d GK |
2611 | [(set (match_dup 0) |
2612 | (div:SI (match_dup 1) (match_dup 2))) | |
2613 | (set (match_dup 3) | |
2614 | (compare:CC (match_dup 0) | |
2615 | (const_int 0)))] | |
2616 | "") | |
1fd4e8c1 RK |
2617 | |
2618 | (define_insn "" | |
cd2b37d9 | 2619 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2620 | (udiv:SI |
996a5f59 | 2621 | (plus:DI (ashift:DI |
cd2b37d9 | 2622 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2623 | (const_int 32)) |
23a900dc | 2624 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2625 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2626 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2627 | (umod:SI |
996a5f59 | 2628 | (plus:DI (ashift:DI |
1fd4e8c1 | 2629 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2630 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2631 | (match_dup 3)))] |
ca7f5001 | 2632 | "TARGET_POWER" |
cfb557c4 RK |
2633 | "div %0,%1,%3" |
2634 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2635 | |
2636 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2637 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2638 | ;; have to worry about the branches. So make a few subroutines here. | |
2639 | ;; | |
2640 | ;; First comes the normal case. | |
2641 | (define_expand "udivmodsi4_normal" | |
2642 | [(set (match_dup 4) (const_int 0)) | |
2643 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2644 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2645 | (const_int 32)) |
2646 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2647 | (match_operand:SI 2 "" ""))) | |
2648 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2649 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2650 | (const_int 32)) |
2651 | (zero_extend:DI (match_dup 1))) | |
2652 | (match_dup 2)))])] | |
ca7f5001 | 2653 | "TARGET_POWER" |
1fd4e8c1 RK |
2654 | " |
2655 | { operands[4] = gen_reg_rtx (SImode); }") | |
2656 | ||
2657 | ;; This handles the branches. | |
2658 | (define_expand "udivmodsi4_tests" | |
2659 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2660 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2661 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2662 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2663 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2664 | (set (match_dup 0) (const_int 1)) | |
2665 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2666 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2667 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2668 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2669 | "TARGET_POWER" |
1fd4e8c1 RK |
2670 | " |
2671 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2672 | operands[6] = gen_reg_rtx (CCmode); | |
2673 | }") | |
2674 | ||
2675 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2676 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2677 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2678 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2679 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2680 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2681 | "" |
1fd4e8c1 RK |
2682 | " |
2683 | { | |
2684 | rtx label = 0; | |
2685 | ||
8ffd9c51 | 2686 | if (! TARGET_POWER) |
c4d38ccb MM |
2687 | { |
2688 | if (! TARGET_POWERPC) | |
2689 | { | |
39403d82 DE |
2690 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2691 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2692 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2693 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2694 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2695 | DONE; |
2696 | } | |
2697 | else | |
2698 | FAIL; | |
2699 | } | |
0081a354 | 2700 | |
1fd4e8c1 RK |
2701 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2702 | { | |
2703 | operands[2] = force_reg (SImode, operands[2]); | |
2704 | label = gen_label_rtx (); | |
2705 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2706 | operands[3], label)); | |
2707 | } | |
2708 | else | |
2709 | operands[2] = force_reg (SImode, operands[2]); | |
2710 | ||
2711 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2712 | operands[3])); | |
2713 | if (label) | |
2714 | emit_label (label); | |
2715 | ||
2716 | DONE; | |
2717 | }") | |
0081a354 | 2718 | |
fada905b MM |
2719 | ;; AIX architecture-independent common-mode multiply (DImode), |
2720 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2721 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2722 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2723 | ;; assumed unused if generating common-mode, so ignore. | |
2724 | (define_insn "mulh_call" | |
2725 | [(set (reg:SI 3) | |
2726 | (truncate:SI | |
2727 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2728 | (sign_extend:DI (reg:SI 4))) | |
2729 | (const_int 32)))) | |
cf27b467 | 2730 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2731 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2732 | "bla __mulh" |
2733 | [(set_attr "type" "imul")]) | |
fada905b MM |
2734 | |
2735 | (define_insn "mull_call" | |
2736 | [(set (reg:DI 3) | |
2737 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2738 | (sign_extend:DI (reg:SI 4)))) | |
2739 | (clobber (match_scratch:SI 0 "=l")) | |
2740 | (clobber (reg:SI 0))] | |
2741 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2742 | "bla __mull" |
2743 | [(set_attr "type" "imul")]) | |
fada905b MM |
2744 | |
2745 | (define_insn "divss_call" | |
2746 | [(set (reg:SI 3) | |
2747 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2748 | (set (reg:SI 4) | |
2749 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2750 | (clobber (match_scratch:SI 0 "=l")) | |
2751 | (clobber (reg:SI 0))] | |
2752 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2753 | "bla __divss" |
2754 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2755 | |
2756 | (define_insn "divus_call" | |
8ffd9c51 RK |
2757 | [(set (reg:SI 3) |
2758 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2759 | (set (reg:SI 4) | |
2760 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2761 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2762 | (clobber (reg:SI 0)) |
2763 | (clobber (match_scratch:CC 1 "=x")) | |
2764 | (clobber (reg:CC 69))] | |
2765 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2766 | "bla __divus" |
2767 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2768 | |
2769 | (define_insn "quoss_call" | |
2770 | [(set (reg:SI 3) | |
2771 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2772 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2773 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2774 | "bla __quoss" |
2775 | [(set_attr "type" "idiv")]) | |
0081a354 | 2776 | |
fada905b MM |
2777 | (define_insn "quous_call" |
2778 | [(set (reg:SI 3) | |
2779 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2780 | (clobber (match_scratch:SI 0 "=l")) | |
2781 | (clobber (reg:SI 0)) | |
2782 | (clobber (match_scratch:CC 1 "=x")) | |
2783 | (clobber (reg:CC 69))] | |
2784 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2785 | "bla __quous" |
2786 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2787 | \f |
bb21487f | 2788 | ;; Logical instructions |
dfbdccdb GK |
2789 | ;; The logical instructions are mostly combined by using match_operator, |
2790 | ;; but the plain AND insns are somewhat different because there is no | |
2791 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2792 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2793 | ||
29ae5b89 JL |
2794 | (define_insn "andsi3" |
2795 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2796 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2797 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2798 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2799 | "" |
2800 | "@ | |
2801 | and %0,%1,%2 | |
ca7f5001 RK |
2802 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2803 | {andil.|andi.} %0,%1,%b2 | |
9ebbca7d | 2804 | {andiu.|andis.} %0,%1,%u2") |
52d3af72 DE |
2805 | |
2806 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
2807 | ;; the test again -- this avoids a mcrf which on the higher end | |
2808 | ;; machines causes an execution serialization | |
1fd4e8c1 | 2809 | |
7cd5235b | 2810 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2811 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2812 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2813 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2814 | (const_int 0))) |
52d3af72 DE |
2815 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2816 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2817 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2818 | "@ |
2819 | and. %3,%1,%2 | |
ca7f5001 RK |
2820 | {andil.|andi.} %3,%1,%b2 |
2821 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2822 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2823 | # | |
2824 | # | |
2825 | # | |
2826 | #" | |
2827 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2828 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2829 | |
52d3af72 DE |
2830 | (define_split |
2831 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2832 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2833 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 2834 | (const_int 0))) |
52d3af72 DE |
2835 | (clobber (match_scratch:SI 3 "")) |
2836 | (clobber (match_scratch:CC 4 ""))] | |
0ad91047 | 2837 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2838 | [(parallel [(set (match_dup 3) |
2839 | (and:SI (match_dup 1) | |
2840 | (match_dup 2))) | |
2841 | (clobber (match_dup 4))]) | |
2842 | (set (match_dup 0) | |
2843 | (compare:CC (match_dup 3) | |
2844 | (const_int 0)))] | |
2845 | "") | |
2846 | ||
2847 | (define_insn "*andsi3_internal3" | |
2848 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2849 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2850 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2851 | (const_int 0))) |
2852 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2853 | (and:SI (match_dup 1) | |
2854 | (match_dup 2))) | |
2855 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2856 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2857 | "@ |
2858 | and. %0,%1,%2 | |
ca7f5001 RK |
2859 | {andil.|andi.} %0,%1,%b2 |
2860 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2861 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2862 | # | |
2863 | # | |
2864 | # | |
2865 | #" | |
2866 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2867 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2868 | ||
2869 | (define_split | |
2870 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2871 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2872 | (match_operand:SI 2 "and_operand" "")) | |
2873 | (const_int 0))) | |
2874 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2875 | (and:SI (match_dup 1) | |
2876 | (match_dup 2))) | |
2877 | (clobber (match_scratch:CC 4 ""))] | |
0ad91047 | 2878 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2879 | [(parallel [(set (match_dup 0) |
2880 | (and:SI (match_dup 1) | |
2881 | (match_dup 2))) | |
2882 | (clobber (match_dup 4))]) | |
2883 | (set (match_dup 3) | |
2884 | (compare:CC (match_dup 0) | |
2885 | (const_int 0)))] | |
2886 | "") | |
1fd4e8c1 | 2887 | |
7cd5235b | 2888 | (define_expand "iorsi3" |
cd2b37d9 | 2889 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2890 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2891 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 2892 | "" |
f357808b RK |
2893 | " |
2894 | { | |
7cd5235b | 2895 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2896 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2897 | { |
2898 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2899 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2900 | ? operands[0] : gen_reg_rtx (SImode)); |
2901 | ||
a260abc9 DE |
2902 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2903 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2904 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2905 | DONE; |
2906 | } | |
f357808b RK |
2907 | }") |
2908 | ||
7cd5235b | 2909 | (define_expand "xorsi3" |
cd2b37d9 | 2910 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2911 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2912 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 2913 | "" |
7cd5235b | 2914 | " |
1fd4e8c1 | 2915 | { |
7cd5235b | 2916 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2917 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2918 | { |
2919 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2920 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2921 | ? operands[0] : gen_reg_rtx (SImode)); |
2922 | ||
a260abc9 DE |
2923 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2924 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2925 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2926 | DONE; |
2927 | } | |
1fd4e8c1 RK |
2928 | }") |
2929 | ||
dfbdccdb | 2930 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2931 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 2932 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2933 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
2934 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2935 | "" |
2936 | "@ | |
dfbdccdb GK |
2937 | %q3 %0,%1,%2 |
2938 | {%q3il|%q3i} %0,%1,%b2 | |
2939 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2940 | |
dfbdccdb | 2941 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2942 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 2943 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
2944 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
2945 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2946 | (const_int 0))) | |
52d3af72 | 2947 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2948 | "! TARGET_POWERPC64" |
52d3af72 | 2949 | "@ |
dfbdccdb | 2950 | %q4. %3,%1,%2 |
52d3af72 DE |
2951 | #" |
2952 | [(set_attr "type" "compare") | |
2953 | (set_attr "length" "4,8")]) | |
2954 | ||
2955 | (define_split | |
2956 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2957 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2958 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2959 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2960 | (const_int 0))) |
52d3af72 | 2961 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2962 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2963 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2964 | (set (match_dup 0) |
2965 | (compare:CC (match_dup 3) | |
2966 | (const_int 0)))] | |
2967 | "") | |
815cdc52 | 2968 | |
dfbdccdb | 2969 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2970 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2971 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2972 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2973 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2974 | (const_int 0))) | |
52d3af72 | 2975 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2976 | (match_dup 4))] |
0ad91047 | 2977 | "! TARGET_POWERPC64" |
52d3af72 | 2978 | "@ |
dfbdccdb | 2979 | %q4. %0,%1,%2 |
52d3af72 DE |
2980 | #" |
2981 | [(set_attr "type" "compare") | |
2982 | (set_attr "length" "4,8")]) | |
2983 | ||
2984 | (define_split | |
e72247f4 | 2985 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2986 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2987 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2988 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2989 | (const_int 0))) |
75540af0 | 2990 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2991 | (match_dup 4))] |
0ad91047 | 2992 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2993 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2994 | (set (match_dup 3) |
2995 | (compare:CC (match_dup 0) | |
2996 | (const_int 0)))] | |
2997 | "") | |
1fd4e8c1 | 2998 | |
dfbdccdb GK |
2999 | ;; Split an logical operation that we can't do in one insn into two insns, |
3000 | ;; each of which does one 16-bit part. This is used by combine. | |
a260abc9 DE |
3001 | |
3002 | (define_split | |
3003 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 3004 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
3005 | [(match_operand:SI 1 "gpc_reg_operand" "") |
3006 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 3007 | "" |
dfbdccdb GK |
3008 | [(set (match_dup 0) (match_dup 4)) |
3009 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
3010 | " |
3011 | { | |
dfbdccdb GK |
3012 | rtx i; |
3013 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
3014 | operands[4] = gen_rtx (GET_CODE (operands[3]), SImode, | |
3015 | operands[1], i); | |
3016 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
3017 | operands[5] = gen_rtx (GET_CODE (operands[3]), SImode, | |
3018 | operands[0], i); | |
a260abc9 DE |
3019 | }") |
3020 | ||
dfbdccdb | 3021 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 3022 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
3023 | (match_operator:SI 3 "boolean_operator" |
3024 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 3025 | (match_operand:SI 2 "gpc_reg_operand" "r")]))] |
1fd4e8c1 | 3026 | "" |
dfbdccdb | 3027 | "%q3 %0,%2,%1") |
1fd4e8c1 | 3028 | |
dfbdccdb | 3029 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 3030 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
3031 | (compare:CC (match_operator:SI 4 "boolean_operator" |
3032 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
3033 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
3034 | (const_int 0))) | |
52d3af72 | 3035 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3036 | "! TARGET_POWERPC64" |
52d3af72 | 3037 | "@ |
dfbdccdb | 3038 | %q4. %3,%2,%1 |
52d3af72 DE |
3039 | #" |
3040 | [(set_attr "type" "compare") | |
3041 | (set_attr "length" "4,8")]) | |
3042 | ||
3043 | (define_split | |
3044 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 3045 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3046 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
3047 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 3048 | (const_int 0))) |
52d3af72 | 3049 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 3050 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3051 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
3052 | (set (match_dup 0) |
3053 | (compare:CC (match_dup 3) | |
3054 | (const_int 0)))] | |
3055 | "") | |
1fd4e8c1 | 3056 | |
dfbdccdb | 3057 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 3058 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
3059 | (compare:CC (match_operator:SI 4 "boolean_operator" |
3060 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
3061 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
3062 | (const_int 0))) | |
52d3af72 | 3063 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 3064 | (match_dup 4))] |
0ad91047 | 3065 | "! TARGET_POWERPC64" |
52d3af72 | 3066 | "@ |
dfbdccdb | 3067 | %q4. %0,%2,%1 |
52d3af72 DE |
3068 | #" |
3069 | [(set_attr "type" "compare") | |
3070 | (set_attr "length" "4,8")]) | |
3071 | ||
3072 | (define_split | |
e72247f4 | 3073 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 3074 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3075 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
3076 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 3077 | (const_int 0))) |
75540af0 | 3078 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 3079 | (match_dup 4))] |
0ad91047 | 3080 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3081 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
3082 | (set (match_dup 3) |
3083 | (compare:CC (match_dup 0) | |
3084 | (const_int 0)))] | |
3085 | "") | |
3086 | ||
dfbdccdb | 3087 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 3088 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
3089 | (match_operator:SI 3 "boolean_operator" |
3090 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 3091 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] |
1fd4e8c1 | 3092 | "" |
dfbdccdb | 3093 | "%q3 %0,%1,%2") |
1fd4e8c1 | 3094 | |
dfbdccdb | 3095 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 3096 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
3097 | (compare:CC (match_operator:SI 4 "boolean_operator" |
3098 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
3099 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
3100 | (const_int 0))) | |
52d3af72 | 3101 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3102 | "! TARGET_POWERPC64" |
52d3af72 | 3103 | "@ |
dfbdccdb | 3104 | %q4. %3,%1,%2 |
52d3af72 DE |
3105 | #" |
3106 | [(set_attr "type" "compare") | |
3107 | (set_attr "length" "4,8")]) | |
3108 | ||
3109 | (define_split | |
3110 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 3111 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3112 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
3113 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 3114 | (const_int 0))) |
52d3af72 | 3115 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 3116 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3117 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
3118 | (set (match_dup 0) |
3119 | (compare:CC (match_dup 3) | |
3120 | (const_int 0)))] | |
3121 | "") | |
1fd4e8c1 | 3122 | |
dfbdccdb | 3123 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 3124 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
3125 | (compare:CC (match_operator:SI 4 "boolean_operator" |
3126 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
3127 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
3128 | (const_int 0))) | |
52d3af72 | 3129 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 3130 | (match_dup 4))] |
0ad91047 | 3131 | "! TARGET_POWERPC64" |
52d3af72 | 3132 | "@ |
dfbdccdb | 3133 | %q4. %0,%1,%2 |
52d3af72 DE |
3134 | #" |
3135 | [(set_attr "type" "compare") | |
3136 | (set_attr "length" "4,8")]) | |
3137 | ||
3138 | (define_split | |
e72247f4 | 3139 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 3140 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3141 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
3142 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 3143 | (const_int 0))) |
75540af0 | 3144 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 3145 | (match_dup 4))] |
0ad91047 | 3146 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3147 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
3148 | (set (match_dup 3) |
3149 | (compare:CC (match_dup 0) | |
3150 | (const_int 0)))] | |
3151 | "") | |
1fd4e8c1 RK |
3152 | |
3153 | ;; maskir insn. We need four forms because things might be in arbitrary | |
3154 | ;; orders. Don't define forms that only set CR fields because these | |
3155 | ;; would modify an input register. | |
3156 | ||
7cd5235b | 3157 | (define_insn "*maskir_internal1" |
cd2b37d9 | 3158 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
3159 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
3160 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
3161 | (and:SI (match_dup 2) | |
cd2b37d9 | 3162 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 3163 | "TARGET_POWER" |
01def764 | 3164 | "maskir %0,%3,%2") |
1fd4e8c1 | 3165 | |
7cd5235b | 3166 | (define_insn "*maskir_internal2" |
242e8072 | 3167 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
3168 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
3169 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 3170 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 3171 | (match_dup 2))))] |
ca7f5001 | 3172 | "TARGET_POWER" |
01def764 | 3173 | "maskir %0,%3,%2") |
1fd4e8c1 | 3174 | |
7cd5235b | 3175 | (define_insn "*maskir_internal3" |
cd2b37d9 | 3176 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 3177 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 3178 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
3179 | (and:SI (not:SI (match_dup 2)) |
3180 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 3181 | "TARGET_POWER" |
01def764 | 3182 | "maskir %0,%3,%2") |
1fd4e8c1 | 3183 | |
7cd5235b | 3184 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
3185 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3186 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
3187 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
3188 | (and:SI (not:SI (match_dup 2)) | |
3189 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 3190 | "TARGET_POWER" |
01def764 | 3191 | "maskir %0,%3,%2") |
1fd4e8c1 | 3192 | |
7cd5235b | 3193 | (define_insn "*maskir_internal5" |
9ebbca7d | 3194 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3195 | (compare:CC |
9ebbca7d GK |
3196 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
3197 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 3198 | (and:SI (match_dup 2) |
9ebbca7d | 3199 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 3200 | (const_int 0))) |
9ebbca7d | 3201 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3202 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
3203 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 3204 | "TARGET_POWER" |
9ebbca7d GK |
3205 | "@ |
3206 | maskir. %0,%3,%2 | |
3207 | #" | |
3208 | [(set_attr "type" "compare") | |
3209 | (set_attr "length" "4,8")]) | |
3210 | ||
3211 | (define_split | |
3212 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3213 | (compare:CC | |
3214 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
3215 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
3216 | (and:SI (match_dup 2) | |
3217 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
3218 | (const_int 0))) | |
3219 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3220 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3221 | (and:SI (match_dup 2) (match_dup 3))))] | |
3222 | "TARGET_POWER && reload_completed" | |
3223 | [(set (match_dup 0) | |
3224 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3225 | (and:SI (match_dup 2) (match_dup 3)))) | |
3226 | (set (match_dup 4) | |
3227 | (compare:CC (match_dup 0) | |
3228 | (const_int 0)))] | |
3229 | "") | |
1fd4e8c1 | 3230 | |
7cd5235b | 3231 | (define_insn "*maskir_internal6" |
9ebbca7d | 3232 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3233 | (compare:CC |
9ebbca7d GK |
3234 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
3235 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
3236 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 3237 | (match_dup 2))) |
1fd4e8c1 | 3238 | (const_int 0))) |
9ebbca7d | 3239 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3240 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
3241 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 3242 | "TARGET_POWER" |
9ebbca7d GK |
3243 | "@ |
3244 | maskir. %0,%3,%2 | |
3245 | #" | |
3246 | [(set_attr "type" "compare") | |
3247 | (set_attr "length" "4,8")]) | |
3248 | ||
3249 | (define_split | |
3250 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3251 | (compare:CC | |
3252 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
3253 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
3254 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3255 | (match_dup 2))) | |
3256 | (const_int 0))) | |
3257 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3258 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3259 | (and:SI (match_dup 3) (match_dup 2))))] | |
3260 | "TARGET_POWER && reload_completed" | |
3261 | [(set (match_dup 0) | |
3262 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3263 | (and:SI (match_dup 3) (match_dup 2)))) | |
3264 | (set (match_dup 4) | |
3265 | (compare:CC (match_dup 0) | |
3266 | (const_int 0)))] | |
3267 | "") | |
1fd4e8c1 | 3268 | |
7cd5235b | 3269 | (define_insn "*maskir_internal7" |
9ebbca7d | 3270 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 3271 | (compare:CC |
9ebbca7d GK |
3272 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
3273 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 3274 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3275 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 3276 | (const_int 0))) |
9ebbca7d | 3277 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
3278 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
3279 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3280 | "TARGET_POWER" | |
9ebbca7d GK |
3281 | "@ |
3282 | maskir. %0,%3,%2 | |
3283 | #" | |
3284 | [(set_attr "type" "compare") | |
3285 | (set_attr "length" "4,8")]) | |
3286 | ||
3287 | (define_split | |
3288 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3289 | (compare:CC | |
3290 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
3291 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
3292 | (and:SI (not:SI (match_dup 2)) | |
3293 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3294 | (const_int 0))) | |
3295 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3296 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3297 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3298 | "TARGET_POWER && reload_completed" | |
3299 | [(set (match_dup 0) | |
3300 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3301 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3302 | (set (match_dup 4) | |
3303 | (compare:CC (match_dup 0) | |
3304 | (const_int 0)))] | |
3305 | "") | |
1fd4e8c1 | 3306 | |
7cd5235b | 3307 | (define_insn "*maskir_internal8" |
9ebbca7d | 3308 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3309 | (compare:CC |
9ebbca7d GK |
3310 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
3311 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 3312 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3313 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 3314 | (const_int 0))) |
9ebbca7d | 3315 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3316 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
3317 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 3318 | "TARGET_POWER" |
9ebbca7d GK |
3319 | "@ |
3320 | maskir. %0,%3,%2 | |
3321 | #" | |
3322 | [(set_attr "type" "compare") | |
3323 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 3324 | \f |
9ebbca7d GK |
3325 | (define_split |
3326 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3327 | (compare:CC | |
3328 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3329 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
3330 | (and:SI (not:SI (match_dup 2)) | |
3331 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3332 | (const_int 0))) | |
3333 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3334 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3335 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3336 | "TARGET_POWER && reload_completed" | |
3337 | [(set (match_dup 0) | |
3338 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3339 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3340 | (set (match_dup 4) | |
3341 | (compare:CC (match_dup 0) | |
3342 | (const_int 0)))] | |
3343 | "") | |
3344 | ||
1fd4e8c1 RK |
3345 | ;; Rotate and shift insns, in all their variants. These support shifts, |
3346 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 3347 | (define_expand "insv" |
0ad91047 DE |
3348 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
3349 | (match_operand:SI 1 "const_int_operand" "") | |
3350 | (match_operand:SI 2 "const_int_operand" "")) | |
3351 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
3352 | "" |
3353 | " | |
3354 | { | |
3355 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3356 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3357 | compiler if the address of the structure is taken later. */ | |
3358 | if (GET_CODE (operands[0]) == SUBREG | |
3359 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3360 | FAIL; | |
a78e33fc DE |
3361 | |
3362 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
3363 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
3364 | else | |
3365 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
3366 | DONE; | |
034c1be0 MM |
3367 | }") |
3368 | ||
a78e33fc | 3369 | (define_insn "insvsi" |
cd2b37d9 | 3370 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
3371 | (match_operand:SI 1 "const_int_operand" "i") |
3372 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 3373 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
3374 | "" |
3375 | "* | |
3376 | { | |
3377 | int start = INTVAL (operands[2]) & 31; | |
3378 | int size = INTVAL (operands[1]) & 31; | |
3379 | ||
89e9f3a8 MM |
3380 | operands[4] = GEN_INT (32 - start - size); |
3381 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3382 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
1fd4e8c1 RK |
3383 | }") |
3384 | ||
a78e33fc | 3385 | (define_insn "*insvsi_internal1" |
d56d506a RK |
3386 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3387 | (match_operand:SI 1 "const_int_operand" "i") | |
3388 | (match_operand:SI 2 "const_int_operand" "i")) | |
3389 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3390 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3391 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3392 | "* |
3393 | { | |
3394 | int shift = INTVAL (operands[4]) & 31; | |
3395 | int start = INTVAL (operands[2]) & 31; | |
3396 | int size = INTVAL (operands[1]) & 31; | |
3397 | ||
89e9f3a8 MM |
3398 | operands[4] = GEN_INT (shift - start - size); |
3399 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3400 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3401 | }") |
3402 | ||
a78e33fc | 3403 | (define_insn "*insvsi_internal2" |
d56d506a RK |
3404 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3405 | (match_operand:SI 1 "const_int_operand" "i") | |
3406 | (match_operand:SI 2 "const_int_operand" "i")) | |
3407 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3408 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3409 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3410 | "* |
3411 | { | |
3412 | int shift = INTVAL (operands[4]) & 31; | |
3413 | int start = INTVAL (operands[2]) & 31; | |
3414 | int size = INTVAL (operands[1]) & 31; | |
3415 | ||
89e9f3a8 MM |
3416 | operands[4] = GEN_INT (32 - shift - start - size); |
3417 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3418 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3419 | }") |
3420 | ||
a78e33fc | 3421 | (define_insn "*insvsi_internal3" |
d56d506a RK |
3422 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3423 | (match_operand:SI 1 "const_int_operand" "i") | |
3424 | (match_operand:SI 2 "const_int_operand" "i")) | |
3425 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3426 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 3427 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3428 | "* |
3429 | { | |
3430 | int shift = INTVAL (operands[4]) & 31; | |
3431 | int start = INTVAL (operands[2]) & 31; | |
3432 | int size = INTVAL (operands[1]) & 31; | |
3433 | ||
89e9f3a8 MM |
3434 | operands[4] = GEN_INT (32 - shift - start - size); |
3435 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3436 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3437 | }") |
3438 | ||
a78e33fc | 3439 | (define_insn "*insvsi_internal4" |
d56d506a RK |
3440 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3441 | (match_operand:SI 1 "const_int_operand" "i") | |
3442 | (match_operand:SI 2 "const_int_operand" "i")) | |
3443 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3444 | (match_operand:SI 4 "const_int_operand" "i") | |
3445 | (match_operand:SI 5 "const_int_operand" "i")))] | |
3446 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
3447 | "* | |
3448 | { | |
3449 | int extract_start = INTVAL (operands[5]) & 31; | |
3450 | int extract_size = INTVAL (operands[4]) & 31; | |
3451 | int insert_start = INTVAL (operands[2]) & 31; | |
3452 | int insert_size = INTVAL (operands[1]) & 31; | |
3453 | ||
3454 | /* Align extract field with insert field */ | |
3a598fbe | 3455 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 3456 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 3457 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
d56d506a RK |
3458 | }") |
3459 | ||
a78e33fc | 3460 | (define_insn "insvdi" |
685f3906 | 3461 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3462 | (match_operand:SI 1 "const_int_operand" "i") |
3463 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3464 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3465 | "TARGET_POWERPC64" | |
3466 | "* | |
3467 | { | |
3468 | int start = INTVAL (operands[2]) & 63; | |
3469 | int size = INTVAL (operands[1]) & 63; | |
3470 | ||
a78e33fc DE |
3471 | operands[1] = GEN_INT (64 - start - size); |
3472 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3473 | }") |
3474 | ||
034c1be0 | 3475 | (define_expand "extzv" |
0ad91047 DE |
3476 | [(set (match_operand 0 "gpc_reg_operand" "") |
3477 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3478 | (match_operand:SI 2 "const_int_operand" "") | |
3479 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3480 | "" |
3481 | " | |
3482 | { | |
3483 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3484 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3485 | compiler if the address of the structure is taken later. */ | |
3486 | if (GET_CODE (operands[0]) == SUBREG | |
3487 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3488 | FAIL; | |
a78e33fc DE |
3489 | |
3490 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3491 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3492 | else | |
3493 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3494 | DONE; | |
034c1be0 MM |
3495 | }") |
3496 | ||
a78e33fc | 3497 | (define_insn "extzvsi" |
cd2b37d9 RK |
3498 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3499 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3500 | (match_operand:SI 2 "const_int_operand" "i") |
3501 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3502 | "" | |
3503 | "* | |
3504 | { | |
3505 | int start = INTVAL (operands[3]) & 31; | |
3506 | int size = INTVAL (operands[2]) & 31; | |
3507 | ||
3508 | if (start + size >= 32) | |
3509 | operands[3] = const0_rtx; | |
3510 | else | |
89e9f3a8 | 3511 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3512 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3513 | }") |
3514 | ||
a78e33fc | 3515 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3516 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3517 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3518 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3519 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3520 | (const_int 0))) |
9ebbca7d | 3521 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3522 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
3523 | "* |
3524 | { | |
3525 | int start = INTVAL (operands[3]) & 31; | |
3526 | int size = INTVAL (operands[2]) & 31; | |
3527 | ||
9ebbca7d GK |
3528 | /* Force split for non-cc0 compare. */ |
3529 | if (which_alternative == 1) | |
3530 | return \"#\"; | |
3531 | ||
a7a975e1 RK |
3532 | /* If the bitfield being tested fits in the upper or lower half of a |
3533 | word, it is possible to use andiu. or andil. to test it. This is | |
3534 | useful because the condition register set-use delay is smaller for | |
3535 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3536 | position is 0 because the LT and GT bits may be set wrong. */ | |
3537 | ||
3538 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3539 | { |
3a598fbe | 3540 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3541 | - (1 << (16 - (start & 15) - size)))); |
3542 | if (start < 16) | |
ca7f5001 | 3543 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3544 | else |
ca7f5001 | 3545 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3546 | } |
7e69e155 | 3547 | |
1fd4e8c1 RK |
3548 | if (start + size >= 32) |
3549 | operands[3] = const0_rtx; | |
3550 | else | |
89e9f3a8 | 3551 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3552 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3553 | }" |
9ebbca7d GK |
3554 | [(set_attr "type" "compare") |
3555 | (set_attr "length" "4,8")]) | |
3556 | ||
3557 | (define_split | |
3558 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3559 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3560 | (match_operand:SI 2 "const_int_operand" "") | |
3561 | (match_operand:SI 3 "const_int_operand" "")) | |
3562 | (const_int 0))) | |
3563 | (clobber (match_scratch:SI 4 ""))] | |
3564 | "! TARGET_POWERPC64 && reload_completed" | |
3565 | [(set (match_dup 4) | |
3566 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3567 | (match_dup 3))) | |
3568 | (set (match_dup 0) | |
3569 | (compare:CC (match_dup 4) | |
3570 | (const_int 0)))] | |
3571 | "") | |
1fd4e8c1 | 3572 | |
a78e33fc | 3573 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3574 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3575 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3576 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3577 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3578 | (const_int 0))) |
9ebbca7d | 3579 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3580 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
0ad91047 | 3581 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
3582 | "* |
3583 | { | |
3584 | int start = INTVAL (operands[3]) & 31; | |
3585 | int size = INTVAL (operands[2]) & 31; | |
3586 | ||
9ebbca7d GK |
3587 | /* Force split for non-cc0 compare. */ |
3588 | if (which_alternative == 1) | |
3589 | return \"#\"; | |
3590 | ||
a7a975e1 | 3591 | if (start >= 16 && start + size == 32) |
df031c43 | 3592 | { |
89e9f3a8 | 3593 | operands[3] = GEN_INT ((1 << (32 - start)) - 1); |
ca7f5001 | 3594 | return \"{andil.|andi.} %0,%1,%3\"; |
df031c43 | 3595 | } |
7e69e155 | 3596 | |
1fd4e8c1 RK |
3597 | if (start + size >= 32) |
3598 | operands[3] = const0_rtx; | |
3599 | else | |
89e9f3a8 | 3600 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3601 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3602 | }" |
9ebbca7d GK |
3603 | [(set_attr "type" "delayed_compare") |
3604 | (set_attr "length" "4,8")]) | |
3605 | ||
3606 | (define_split | |
3607 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3608 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3609 | (match_operand:SI 2 "const_int_operand" "") | |
3610 | (match_operand:SI 3 "const_int_operand" "")) | |
3611 | (const_int 0))) | |
3612 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3613 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
3614 | "! TARGET_POWERPC64 && reload_completed" | |
3615 | [(set (match_dup 0) | |
3616 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3617 | (set (match_dup 4) | |
3618 | (compare:CC (match_dup 0) | |
3619 | (const_int 0)))] | |
3620 | "") | |
1fd4e8c1 | 3621 | |
a78e33fc | 3622 | (define_insn "extzvdi" |
685f3906 DE |
3623 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3624 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3625 | (match_operand:SI 2 "const_int_operand" "i") |
3626 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3627 | "TARGET_POWERPC64" |
3628 | "* | |
3629 | { | |
3630 | int start = INTVAL (operands[3]) & 63; | |
3631 | int size = INTVAL (operands[2]) & 63; | |
3632 | ||
3633 | if (start + size >= 64) | |
3634 | operands[3] = const0_rtx; | |
3635 | else | |
89e9f3a8 MM |
3636 | operands[3] = GEN_INT (start + size); |
3637 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3638 | return \"rldicl %0,%1,%3,%2\"; |
3639 | }") | |
3640 | ||
a78e33fc | 3641 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3642 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3643 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3644 | (match_operand:SI 2 "const_int_operand" "i") |
3645 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3646 | (const_int 0))) |
29ae5b89 | 3647 | (clobber (match_scratch:DI 4 "=r"))] |
685f3906 DE |
3648 | "TARGET_POWERPC64" |
3649 | "* | |
3650 | { | |
3651 | int start = INTVAL (operands[3]) & 63; | |
3652 | int size = INTVAL (operands[2]) & 63; | |
3653 | ||
3654 | if (start + size >= 64) | |
3655 | operands[3] = const0_rtx; | |
3656 | else | |
89e9f3a8 MM |
3657 | operands[3] = GEN_INT (start + size); |
3658 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3659 | return \"rldicl. %4,%1,%3,%2\"; |
3660 | }") | |
3661 | ||
a78e33fc | 3662 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3663 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3664 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3665 | (match_operand:SI 2 "const_int_operand" "i") |
3666 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3667 | (const_int 0))) |
29ae5b89 | 3668 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 DE |
3669 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
3670 | "TARGET_POWERPC64" | |
3671 | "* | |
3672 | { | |
3673 | int start = INTVAL (operands[3]) & 63; | |
3674 | int size = INTVAL (operands[2]) & 63; | |
3675 | ||
3676 | if (start + size >= 64) | |
3677 | operands[3] = const0_rtx; | |
3678 | else | |
89e9f3a8 MM |
3679 | operands[3] = GEN_INT (start + size); |
3680 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3681 | return \"rldicl. %0,%1,%3,%2\"; |
3682 | }") | |
3683 | ||
1fd4e8c1 | 3684 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3685 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3686 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3687 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3688 | "" | |
ca7f5001 | 3689 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3690 | |
a260abc9 | 3691 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3692 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3693 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3694 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3695 | (const_int 0))) |
9ebbca7d | 3696 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3697 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3698 | "@ |
3699 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3700 | #" | |
3701 | [(set_attr "type" "delayed_compare") | |
3702 | (set_attr "length" "4,8")]) | |
3703 | ||
3704 | (define_split | |
3705 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3706 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3707 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3708 | (const_int 0))) | |
3709 | (clobber (match_scratch:SI 3 ""))] | |
3710 | "! TARGET_POWERPC64 && reload_completed" | |
3711 | [(set (match_dup 3) | |
3712 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3713 | (set (match_dup 0) | |
3714 | (compare:CC (match_dup 3) | |
3715 | (const_int 0)))] | |
3716 | "") | |
1fd4e8c1 | 3717 | |
a260abc9 | 3718 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3719 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3720 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3721 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3722 | (const_int 0))) |
9ebbca7d | 3723 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3724 | (rotate:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3725 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3726 | "@ |
3727 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3728 | #" | |
3729 | [(set_attr "type" "delayed_compare") | |
3730 | (set_attr "length" "4,8")]) | |
3731 | ||
3732 | (define_split | |
3733 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3734 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3735 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3736 | (const_int 0))) | |
3737 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3738 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
3739 | "! TARGET_POWERPC64 && reload_completed" | |
3740 | [(set (match_dup 0) | |
3741 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3742 | (set (match_dup 3) | |
3743 | (compare:CC (match_dup 0) | |
3744 | (const_int 0)))] | |
3745 | "") | |
1fd4e8c1 | 3746 | |
a260abc9 | 3747 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3748 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3749 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3750 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
9615f239 | 3751 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 3752 | "" |
ca7f5001 | 3753 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3754 | |
a260abc9 | 3755 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3756 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3757 | (compare:CC (and:SI |
9ebbca7d GK |
3758 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3759 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
3760 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3761 | (const_int 0))) |
9ebbca7d | 3762 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3763 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3764 | "@ |
3765 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3766 | #" | |
3767 | [(set_attr "type" "delayed_compare") | |
3768 | (set_attr "length" "4,8")]) | |
3769 | ||
3770 | (define_split | |
3771 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3772 | (compare:CC (and:SI | |
3773 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3774 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3775 | (match_operand:SI 3 "mask_operand" "")) | |
3776 | (const_int 0))) | |
3777 | (clobber (match_scratch:SI 4 ""))] | |
3778 | "! TARGET_POWERPC64 && reload_completed" | |
3779 | [(set (match_dup 4) | |
3780 | (and:SI (rotate:SI (match_dup 1) | |
3781 | (match_dup 2)) | |
3782 | (match_dup 3))) | |
3783 | (set (match_dup 0) | |
3784 | (compare:CC (match_dup 4) | |
3785 | (const_int 0)))] | |
3786 | "") | |
1fd4e8c1 | 3787 | |
a260abc9 | 3788 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3789 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3790 | (compare:CC (and:SI |
9ebbca7d GK |
3791 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3792 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
3793 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3794 | (const_int 0))) |
9ebbca7d | 3795 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3796 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 3797 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3798 | "@ |
3799 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3800 | #" | |
3801 | [(set_attr "type" "delayed_compare") | |
3802 | (set_attr "length" "4,8")]) | |
3803 | ||
3804 | (define_split | |
3805 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3806 | (compare:CC (and:SI | |
3807 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3808 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3809 | (match_operand:SI 3 "mask_operand" "")) | |
3810 | (const_int 0))) | |
3811 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3812 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
3813 | "! TARGET_POWERPC64 && reload_completed" | |
3814 | [(set (match_dup 0) | |
3815 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3816 | (set (match_dup 4) | |
3817 | (compare:CC (match_dup 0) | |
3818 | (const_int 0)))] | |
3819 | "") | |
1fd4e8c1 | 3820 | |
a260abc9 | 3821 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3822 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3823 | (zero_extend:SI |
3824 | (subreg:QI | |
cd2b37d9 | 3825 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3826 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3827 | "" | |
ca7f5001 | 3828 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3829 | |
a260abc9 | 3830 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3831 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3832 | (compare:CC (zero_extend:SI |
3833 | (subreg:QI | |
9ebbca7d GK |
3834 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3835 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3836 | (const_int 0))) |
9ebbca7d | 3837 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3838 | "" |
9ebbca7d GK |
3839 | "@ |
3840 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3841 | #" | |
3842 | [(set_attr "type" "delayed_compare") | |
3843 | (set_attr "length" "4,8")]) | |
3844 | ||
3845 | (define_split | |
3846 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3847 | (compare:CC (zero_extend:SI | |
3848 | (subreg:QI | |
3849 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3850 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3851 | (const_int 0))) | |
3852 | (clobber (match_scratch:SI 3 ""))] | |
3853 | "reload_completed" | |
3854 | [(set (match_dup 3) | |
3855 | (zero_extend:SI (subreg:QI | |
3856 | (rotate:SI (match_dup 1) | |
3857 | (match_dup 2)) 0))) | |
3858 | (set (match_dup 0) | |
3859 | (compare:CC (match_dup 3) | |
3860 | (const_int 0)))] | |
3861 | "") | |
1fd4e8c1 | 3862 | |
a260abc9 | 3863 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3864 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3865 | (compare:CC (zero_extend:SI |
3866 | (subreg:QI | |
9ebbca7d GK |
3867 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3868 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3869 | (const_int 0))) |
9ebbca7d | 3870 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3871 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3872 | "" | |
9ebbca7d GK |
3873 | "@ |
3874 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3875 | #" | |
3876 | [(set_attr "type" "delayed_compare") | |
3877 | (set_attr "length" "4,8")]) | |
3878 | ||
3879 | (define_split | |
3880 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3881 | (compare:CC (zero_extend:SI | |
3882 | (subreg:QI | |
3883 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3884 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3885 | (const_int 0))) | |
3886 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3887 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3888 | "reload_completed" | |
3889 | [(set (match_dup 0) | |
3890 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3891 | (set (match_dup 3) | |
3892 | (compare:CC (match_dup 0) | |
3893 | (const_int 0)))] | |
3894 | "") | |
1fd4e8c1 | 3895 | |
a260abc9 | 3896 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3897 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3898 | (zero_extend:SI |
3899 | (subreg:HI | |
cd2b37d9 | 3900 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3901 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3902 | "" | |
ca7f5001 | 3903 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3904 | |
a260abc9 | 3905 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3906 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3907 | (compare:CC (zero_extend:SI |
3908 | (subreg:HI | |
9ebbca7d GK |
3909 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3910 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3911 | (const_int 0))) |
9ebbca7d | 3912 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3913 | "" |
9ebbca7d GK |
3914 | "@ |
3915 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3916 | #" | |
3917 | [(set_attr "type" "delayed_compare") | |
3918 | (set_attr "length" "4,8")]) | |
3919 | ||
3920 | (define_split | |
3921 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3922 | (compare:CC (zero_extend:SI | |
3923 | (subreg:HI | |
3924 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3925 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3926 | (const_int 0))) | |
3927 | (clobber (match_scratch:SI 3 ""))] | |
3928 | "reload_completed" | |
3929 | [(set (match_dup 3) | |
3930 | (zero_extend:SI (subreg:HI | |
3931 | (rotate:SI (match_dup 1) | |
3932 | (match_dup 2)) 0))) | |
3933 | (set (match_dup 0) | |
3934 | (compare:CC (match_dup 3) | |
3935 | (const_int 0)))] | |
3936 | "") | |
1fd4e8c1 | 3937 | |
a260abc9 | 3938 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3939 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3940 | (compare:CC (zero_extend:SI |
3941 | (subreg:HI | |
9ebbca7d GK |
3942 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3943 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3944 | (const_int 0))) |
9ebbca7d | 3945 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3946 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3947 | "" | |
9ebbca7d GK |
3948 | "@ |
3949 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3950 | #" | |
3951 | [(set_attr "type" "delayed_compare") | |
3952 | (set_attr "length" "4,8")]) | |
3953 | ||
3954 | (define_split | |
3955 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3956 | (compare:CC (zero_extend:SI | |
3957 | (subreg:HI | |
3958 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3959 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3960 | (const_int 0))) | |
3961 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3962 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3963 | "reload_completed" | |
3964 | [(set (match_dup 0) | |
3965 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3966 | (set (match_dup 3) | |
3967 | (compare:CC (match_dup 0) | |
3968 | (const_int 0)))] | |
3969 | "") | |
1fd4e8c1 RK |
3970 | |
3971 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3972 | ;; SHIFT_COUNT_TRUNCATED. | |
3973 | ||
ca7f5001 RK |
3974 | (define_expand "ashlsi3" |
3975 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3976 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3977 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3978 | "" | |
3979 | " | |
3980 | { | |
3981 | if (TARGET_POWER) | |
3982 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3983 | else | |
25c341fa | 3984 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3985 | DONE; |
3986 | }") | |
3987 | ||
3988 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3989 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3990 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3991 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3992 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3993 | "TARGET_POWER" |
1fd4e8c1 RK |
3994 | "@ |
3995 | sle %0,%1,%2 | |
9ebbca7d | 3996 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3997 | |
25c341fa | 3998 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3999 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4000 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4001 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4002 | "! TARGET_POWER" |
9ebbca7d | 4003 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4004 | |
4005 | (define_insn "" | |
9ebbca7d GK |
4006 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4007 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4008 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4009 | (const_int 0))) |
9ebbca7d GK |
4010 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4011 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4012 | "TARGET_POWER" |
1fd4e8c1 RK |
4013 | "@ |
4014 | sle. %3,%1,%2 | |
9ebbca7d GK |
4015 | {sli.|slwi.} %3,%1,%h2 |
4016 | # | |
4017 | #" | |
4018 | [(set_attr "type" "delayed_compare") | |
4019 | (set_attr "length" "4,4,8,8")]) | |
4020 | ||
4021 | (define_split | |
4022 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4023 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4024 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4025 | (const_int 0))) | |
4026 | (clobber (match_scratch:SI 3 "")) | |
4027 | (clobber (match_scratch:SI 4 ""))] | |
4028 | "TARGET_POWER && reload_completed" | |
4029 | [(parallel [(set (match_dup 3) | |
4030 | (ashift:SI (match_dup 1) (match_dup 2))) | |
4031 | (clobber (match_dup 4))]) | |
4032 | (set (match_dup 0) | |
4033 | (compare:CC (match_dup 3) | |
4034 | (const_int 0)))] | |
4035 | "") | |
25c341fa | 4036 | |
ca7f5001 | 4037 | (define_insn "" |
9ebbca7d GK |
4038 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4039 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4040 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4041 | (const_int 0))) |
9ebbca7d | 4042 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 4043 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
4044 | "@ |
4045 | {sl|slw}%I2. %3,%1,%h2 | |
4046 | #" | |
4047 | [(set_attr "type" "delayed_compare") | |
4048 | (set_attr "length" "4,8")]) | |
4049 | ||
4050 | (define_split | |
4051 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4052 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4053 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4054 | (const_int 0))) | |
4055 | (clobber (match_scratch:SI 3 ""))] | |
4056 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4057 | [(set (match_dup 3) | |
4058 | (ashift:SI (match_dup 1) (match_dup 2))) | |
4059 | (set (match_dup 0) | |
4060 | (compare:CC (match_dup 3) | |
4061 | (const_int 0)))] | |
4062 | "") | |
1fd4e8c1 RK |
4063 | |
4064 | (define_insn "" | |
9ebbca7d GK |
4065 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4066 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4067 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4068 | (const_int 0))) |
9ebbca7d | 4069 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4070 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4071 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4072 | "TARGET_POWER" |
1fd4e8c1 RK |
4073 | "@ |
4074 | sle. %0,%1,%2 | |
9ebbca7d GK |
4075 | {sli.|slwi.} %0,%1,%h2 |
4076 | # | |
4077 | #" | |
4078 | [(set_attr "type" "delayed_compare") | |
4079 | (set_attr "length" "4,4,8,8")]) | |
4080 | ||
4081 | (define_split | |
4082 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4083 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4084 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4085 | (const_int 0))) | |
4086 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4087 | (ashift:SI (match_dup 1) (match_dup 2))) | |
4088 | (clobber (match_scratch:SI 4 ""))] | |
4089 | "TARGET_POWER && reload_completed" | |
4090 | [(parallel [(set (match_dup 0) | |
4091 | (ashift:SI (match_dup 1) (match_dup 2))) | |
4092 | (clobber (match_dup 4))]) | |
4093 | (set (match_dup 3) | |
4094 | (compare:CC (match_dup 0) | |
4095 | (const_int 0)))] | |
4096 | "") | |
25c341fa | 4097 | |
ca7f5001 | 4098 | (define_insn "" |
9ebbca7d GK |
4099 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4100 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4101 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4102 | (const_int 0))) |
9ebbca7d | 4103 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4104 | (ashift:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 4105 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
4106 | "@ |
4107 | {sl|slw}%I2. %0,%1,%h2 | |
4108 | #" | |
4109 | [(set_attr "type" "delayed_compare") | |
4110 | (set_attr "length" "4,8")]) | |
4111 | ||
4112 | (define_split | |
4113 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4114 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4115 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4116 | (const_int 0))) | |
4117 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4118 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
4119 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4120 | [(set (match_dup 0) | |
4121 | (ashift:SI (match_dup 1) (match_dup 2))) | |
4122 | (set (match_dup 3) | |
4123 | (compare:CC (match_dup 0) | |
4124 | (const_int 0)))] | |
4125 | "") | |
1fd4e8c1 RK |
4126 | |
4127 | (define_insn "" | |
cd2b37d9 RK |
4128 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4129 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4130 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 4131 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 4132 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 4133 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
4134 | |
4135 | (define_insn "" | |
9ebbca7d | 4136 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4137 | (compare:CC |
9ebbca7d GK |
4138 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4139 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4140 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4141 | (const_int 0))) |
9ebbca7d | 4142 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 4143 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4144 | "@ |
4145 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
4146 | #" | |
4147 | [(set_attr "type" "delayed_compare") | |
4148 | (set_attr "length" "4,8")]) | |
4149 | ||
4150 | (define_split | |
4151 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4152 | (compare:CC | |
4153 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4154 | (match_operand:SI 2 "const_int_operand" "")) | |
4155 | (match_operand:SI 3 "mask_operand" "")) | |
4156 | (const_int 0))) | |
4157 | (clobber (match_scratch:SI 4 ""))] | |
4158 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" | |
4159 | [(set (match_dup 4) | |
4160 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
4161 | (match_dup 3))) | |
4162 | (set (match_dup 0) | |
4163 | (compare:CC (match_dup 4) | |
4164 | (const_int 0)))] | |
4165 | "") | |
1fd4e8c1 RK |
4166 | |
4167 | (define_insn "" | |
9ebbca7d | 4168 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4169 | (compare:CC |
9ebbca7d GK |
4170 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4171 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4172 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4173 | (const_int 0))) |
9ebbca7d | 4174 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4175 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 4176 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4177 | "@ |
4178 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
4179 | #" | |
4180 | [(set_attr "type" "delayed_compare") | |
4181 | (set_attr "length" "4,8")]) | |
4182 | ||
4183 | (define_split | |
4184 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4185 | (compare:CC | |
4186 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4187 | (match_operand:SI 2 "const_int_operand" "")) | |
4188 | (match_operand:SI 3 "mask_operand" "")) | |
4189 | (const_int 0))) | |
4190 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4191 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4192 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" | |
4193 | [(set (match_dup 0) | |
4194 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4195 | (set (match_dup 4) | |
4196 | (compare:CC (match_dup 0) | |
4197 | (const_int 0)))] | |
4198 | "") | |
1fd4e8c1 | 4199 | |
ca7f5001 | 4200 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 4201 | ;; "sli x,x,0". |
ca7f5001 RK |
4202 | (define_expand "lshrsi3" |
4203 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
4204 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
4205 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
4206 | "" | |
4207 | " | |
4208 | { | |
4209 | if (TARGET_POWER) | |
4210 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
4211 | else | |
25c341fa | 4212 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4213 | DONE; |
4214 | }") | |
4215 | ||
4216 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
4217 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
4218 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
4219 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
4220 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 4221 | "TARGET_POWER" |
1fd4e8c1 RK |
4222 | "@ |
4223 | sre %0,%1,%2 | |
bdf423cb | 4224 | mr %0,%1 |
ca7f5001 RK |
4225 | {s%A2i|s%A2wi} %0,%1,%h2") |
4226 | ||
25c341fa | 4227 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
4228 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4229 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4230 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 4231 | "! TARGET_POWER" |
bdf423cb MM |
4232 | "@ |
4233 | mr %0,%1 | |
4234 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
4235 | |
4236 | (define_insn "" | |
9ebbca7d GK |
4237 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
4238 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4239 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4240 | (const_int 0))) |
9ebbca7d GK |
4241 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
4242 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 4243 | "TARGET_POWER" |
1fd4e8c1 | 4244 | "@ |
29ae5b89 JL |
4245 | sre. %3,%1,%2 |
4246 | mr. %1,%1 | |
9ebbca7d GK |
4247 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
4248 | # | |
4249 | # | |
4250 | #" | |
4251 | [(set_attr "type" "delayed_compare") | |
4252 | (set_attr "length" "4,4,4,8,8,8")]) | |
4253 | ||
4254 | (define_split | |
4255 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4256 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4257 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4258 | (const_int 0))) | |
4259 | (clobber (match_scratch:SI 3 "")) | |
4260 | (clobber (match_scratch:SI 4 ""))] | |
4261 | "TARGET_POWER && reload_completed" | |
4262 | [(parallel [(set (match_dup 3) | |
4263 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4264 | (clobber (match_dup 4))]) | |
4265 | (set (match_dup 0) | |
4266 | (compare:CC (match_dup 3) | |
4267 | (const_int 0)))] | |
4268 | "") | |
ca7f5001 RK |
4269 | |
4270 | (define_insn "" | |
9ebbca7d GK |
4271 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4272 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4273 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 4274 | (const_int 0))) |
9ebbca7d | 4275 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
0ad91047 | 4276 | "! TARGET_POWER && ! TARGET_POWERPC64" |
bdf423cb MM |
4277 | "@ |
4278 | mr. %1,%1 | |
9ebbca7d GK |
4279 | {sr|srw}%I2. %3,%1,%h2 |
4280 | # | |
4281 | #" | |
4282 | [(set_attr "type" "delayed_compare") | |
4283 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 4284 | |
9ebbca7d GK |
4285 | (define_split |
4286 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4287 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4288 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4289 | (const_int 0))) | |
4290 | (clobber (match_scratch:SI 3 ""))] | |
4291 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4292 | [(set (match_dup 3) | |
4293 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4294 | (set (match_dup 0) | |
4295 | (compare:CC (match_dup 3) | |
4296 | (const_int 0)))] | |
4297 | "") | |
4298 | ||
4299 | (define_insn "" | |
4300 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
4301 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4302 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4303 | (const_int 0))) |
9ebbca7d | 4304 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 4305 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4306 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 4307 | "TARGET_POWER" |
1fd4e8c1 | 4308 | "@ |
29ae5b89 JL |
4309 | sre. %0,%1,%2 |
4310 | mr. %0,%1 | |
9ebbca7d GK |
4311 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
4312 | # | |
4313 | # | |
4314 | #" | |
4315 | [(set_attr "type" "delayed_compare") | |
4316 | (set_attr "length" "4,4,4,8,8,8")]) | |
4317 | ||
4318 | (define_split | |
4319 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4320 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4321 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4322 | (const_int 0))) | |
4323 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4324 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4325 | (clobber (match_scratch:SI 4 ""))] | |
4326 | "TARGET_POWER && reload_completed" | |
4327 | [(parallel [(set (match_dup 0) | |
4328 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4329 | (clobber (match_dup 4))]) | |
4330 | (set (match_dup 3) | |
4331 | (compare:CC (match_dup 0) | |
4332 | (const_int 0)))] | |
4333 | "") | |
ca7f5001 RK |
4334 | |
4335 | (define_insn "" | |
9ebbca7d GK |
4336 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4337 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4338 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 4339 | (const_int 0))) |
9ebbca7d | 4340 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 4341 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 4342 | "! TARGET_POWER && ! TARGET_POWERPC64" |
29ae5b89 JL |
4343 | "@ |
4344 | mr. %0,%1 | |
9ebbca7d GK |
4345 | {sr|srw}%I2. %0,%1,%h2 |
4346 | # | |
4347 | #" | |
4348 | [(set_attr "type" "delayed_compare") | |
4349 | (set_attr "length" "4,4,8,8")]) | |
4350 | ||
4351 | (define_split | |
4352 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4353 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4354 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4355 | (const_int 0))) | |
4356 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4357 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4358 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4359 | [(set (match_dup 0) | |
4360 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4361 | (set (match_dup 3) | |
4362 | (compare:CC (match_dup 0) | |
4363 | (const_int 0)))] | |
4364 | "") | |
1fd4e8c1 RK |
4365 | |
4366 | (define_insn "" | |
cd2b37d9 RK |
4367 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4368 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4369 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 4370 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 4371 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 4372 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
4373 | |
4374 | (define_insn "" | |
9ebbca7d | 4375 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4376 | (compare:CC |
9ebbca7d GK |
4377 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4378 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4379 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4380 | (const_int 0))) |
9ebbca7d | 4381 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 4382 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4383 | "@ |
4384 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
4385 | #" | |
4386 | [(set_attr "type" "delayed_compare") | |
4387 | (set_attr "length" "4,8")]) | |
4388 | ||
4389 | (define_split | |
4390 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4391 | (compare:CC | |
4392 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4393 | (match_operand:SI 2 "const_int_operand" "")) | |
4394 | (match_operand:SI 3 "mask_operand" "")) | |
4395 | (const_int 0))) | |
4396 | (clobber (match_scratch:SI 4 ""))] | |
4397 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" | |
4398 | [(set (match_dup 4) | |
4399 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
4400 | (match_dup 3))) | |
4401 | (set (match_dup 0) | |
4402 | (compare:CC (match_dup 4) | |
4403 | (const_int 0)))] | |
4404 | "") | |
1fd4e8c1 RK |
4405 | |
4406 | (define_insn "" | |
9ebbca7d | 4407 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4408 | (compare:CC |
9ebbca7d GK |
4409 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4410 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4411 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4412 | (const_int 0))) |
9ebbca7d | 4413 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4414 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 4415 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4416 | "@ |
4417 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
4418 | #" | |
4419 | [(set_attr "type" "delayed_compare") | |
4420 | (set_attr "length" "4,8")]) | |
4421 | ||
4422 | (define_split | |
4423 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4424 | (compare:CC | |
4425 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4426 | (match_operand:SI 2 "const_int_operand" "")) | |
4427 | (match_operand:SI 3 "mask_operand" "")) | |
4428 | (const_int 0))) | |
4429 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4430 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4431 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" | |
4432 | [(set (match_dup 0) | |
4433 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4434 | (set (match_dup 4) | |
4435 | (compare:CC (match_dup 0) | |
4436 | (const_int 0)))] | |
4437 | "") | |
1fd4e8c1 RK |
4438 | |
4439 | (define_insn "" | |
cd2b37d9 | 4440 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4441 | (zero_extend:SI |
4442 | (subreg:QI | |
cd2b37d9 | 4443 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4444 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4445 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4446 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4447 | |
4448 | (define_insn "" | |
9ebbca7d | 4449 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4450 | (compare:CC |
4451 | (zero_extend:SI | |
4452 | (subreg:QI | |
9ebbca7d GK |
4453 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4454 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4455 | (const_int 0))) |
9ebbca7d | 4456 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4457 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4458 | "@ |
4459 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4460 | #" | |
4461 | [(set_attr "type" "delayed_compare") | |
4462 | (set_attr "length" "4,8")]) | |
4463 | ||
4464 | (define_split | |
4465 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4466 | (compare:CC | |
4467 | (zero_extend:SI | |
4468 | (subreg:QI | |
4469 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4470 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4471 | (const_int 0))) | |
4472 | (clobber (match_scratch:SI 3 ""))] | |
4473 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4474 | [(set (match_dup 3) | |
4475 | (zero_extend:SI (subreg:QI | |
4476 | (lshiftrt:SI (match_dup 1) | |
4477 | (match_dup 2)) 0))) | |
4478 | (set (match_dup 0) | |
4479 | (compare:CC (match_dup 3) | |
4480 | (const_int 0)))] | |
4481 | "") | |
1fd4e8c1 RK |
4482 | |
4483 | (define_insn "" | |
9ebbca7d | 4484 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4485 | (compare:CC |
4486 | (zero_extend:SI | |
4487 | (subreg:QI | |
9ebbca7d GK |
4488 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4489 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4490 | (const_int 0))) |
9ebbca7d | 4491 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4492 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4493 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4494 | "@ |
4495 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4496 | #" | |
4497 | [(set_attr "type" "delayed_compare") | |
4498 | (set_attr "length" "4,8")]) | |
4499 | ||
4500 | (define_split | |
4501 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4502 | (compare:CC | |
4503 | (zero_extend:SI | |
4504 | (subreg:QI | |
4505 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4506 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4507 | (const_int 0))) | |
4508 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4509 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4510 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4511 | [(set (match_dup 0) | |
4512 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4513 | (set (match_dup 3) | |
4514 | (compare:CC (match_dup 0) | |
4515 | (const_int 0)))] | |
4516 | "") | |
1fd4e8c1 RK |
4517 | |
4518 | (define_insn "" | |
cd2b37d9 | 4519 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4520 | (zero_extend:SI |
4521 | (subreg:HI | |
cd2b37d9 | 4522 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4523 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4524 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4525 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4526 | |
4527 | (define_insn "" | |
9ebbca7d | 4528 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4529 | (compare:CC |
4530 | (zero_extend:SI | |
4531 | (subreg:HI | |
9ebbca7d GK |
4532 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4533 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4534 | (const_int 0))) |
9ebbca7d | 4535 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4536 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4537 | "@ |
4538 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4539 | #" | |
4540 | [(set_attr "type" "delayed_compare") | |
4541 | (set_attr "length" "4,8")]) | |
4542 | ||
4543 | (define_split | |
4544 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4545 | (compare:CC | |
4546 | (zero_extend:SI | |
4547 | (subreg:HI | |
4548 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4549 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4550 | (const_int 0))) | |
4551 | (clobber (match_scratch:SI 3 ""))] | |
4552 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4553 | [(set (match_dup 3) | |
4554 | (zero_extend:SI (subreg:HI | |
4555 | (lshiftrt:SI (match_dup 1) | |
4556 | (match_dup 2)) 0))) | |
4557 | (set (match_dup 0) | |
4558 | (compare:CC (match_dup 3) | |
4559 | (const_int 0)))] | |
4560 | "") | |
1fd4e8c1 RK |
4561 | |
4562 | (define_insn "" | |
9ebbca7d | 4563 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4564 | (compare:CC |
4565 | (zero_extend:SI | |
4566 | (subreg:HI | |
9ebbca7d GK |
4567 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4568 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4569 | (const_int 0))) |
9ebbca7d | 4570 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4571 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4572 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4573 | "@ |
4574 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4575 | #" | |
4576 | [(set_attr "type" "delayed_compare") | |
4577 | (set_attr "length" "4,8")]) | |
4578 | ||
4579 | (define_split | |
4580 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4581 | (compare:CC | |
4582 | (zero_extend:SI | |
4583 | (subreg:HI | |
4584 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4585 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4586 | (const_int 0))) | |
4587 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4588 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4589 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4590 | [(set (match_dup 0) | |
4591 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4592 | (set (match_dup 3) | |
4593 | (compare:CC (match_dup 0) | |
4594 | (const_int 0)))] | |
4595 | "") | |
1fd4e8c1 RK |
4596 | |
4597 | (define_insn "" | |
cd2b37d9 | 4598 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4599 | (const_int 1) |
cd2b37d9 RK |
4600 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4601 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4602 | (const_int 31)))] |
ca7f5001 | 4603 | "TARGET_POWER" |
1fd4e8c1 RK |
4604 | "rrib %0,%1,%2") |
4605 | ||
4606 | (define_insn "" | |
cd2b37d9 | 4607 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4608 | (const_int 1) |
cd2b37d9 RK |
4609 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4610 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4611 | (const_int 31)))] |
ca7f5001 | 4612 | "TARGET_POWER" |
1fd4e8c1 RK |
4613 | "rrib %0,%1,%2") |
4614 | ||
4615 | (define_insn "" | |
cd2b37d9 | 4616 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4617 | (const_int 1) |
cd2b37d9 RK |
4618 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4619 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4620 | (const_int 1) |
4621 | (const_int 0)))] | |
ca7f5001 | 4622 | "TARGET_POWER" |
1fd4e8c1 RK |
4623 | "rrib %0,%1,%2") |
4624 | ||
ca7f5001 RK |
4625 | (define_expand "ashrsi3" |
4626 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4627 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4628 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4629 | "" | |
4630 | " | |
4631 | { | |
4632 | if (TARGET_POWER) | |
4633 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4634 | else | |
25c341fa | 4635 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4636 | DONE; |
4637 | }") | |
4638 | ||
4639 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4640 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4641 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4642 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4643 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4644 | "TARGET_POWER" |
1fd4e8c1 RK |
4645 | "@ |
4646 | srea %0,%1,%2 | |
ca7f5001 RK |
4647 | {srai|srawi} %0,%1,%h2") |
4648 | ||
25c341fa | 4649 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4650 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4651 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4652 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4653 | "! TARGET_POWER" |
d904e9ed | 4654 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4655 | |
4656 | (define_insn "" | |
9ebbca7d GK |
4657 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4658 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4659 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4660 | (const_int 0))) |
9ebbca7d GK |
4661 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4662 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4663 | "TARGET_POWER" |
1fd4e8c1 RK |
4664 | "@ |
4665 | srea. %3,%1,%2 | |
9ebbca7d GK |
4666 | {srai.|srawi.} %3,%1,%h2 |
4667 | # | |
4668 | #" | |
4669 | [(set_attr "type" "delayed_compare") | |
4670 | (set_attr "length" "4,4,8,8")]) | |
4671 | ||
4672 | (define_split | |
4673 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4674 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4675 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4676 | (const_int 0))) | |
4677 | (clobber (match_scratch:SI 3 "")) | |
4678 | (clobber (match_scratch:SI 4 ""))] | |
4679 | "TARGET_POWER && reload_completed" | |
4680 | [(parallel [(set (match_dup 3) | |
4681 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4682 | (clobber (match_dup 4))]) | |
4683 | (set (match_dup 0) | |
4684 | (compare:CC (match_dup 3) | |
4685 | (const_int 0)))] | |
4686 | "") | |
ca7f5001 RK |
4687 | |
4688 | (define_insn "" | |
9ebbca7d GK |
4689 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4690 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4691 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4692 | (const_int 0))) |
9ebbca7d | 4693 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4694 | "! TARGET_POWER" |
9ebbca7d GK |
4695 | "@ |
4696 | {sra|sraw}%I2. %3,%1,%h2 | |
4697 | #" | |
4698 | [(set_attr "type" "delayed_compare") | |
4699 | (set_attr "length" "4,8")]) | |
4700 | ||
4701 | (define_split | |
4702 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4703 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4704 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4705 | (const_int 0))) | |
4706 | (clobber (match_scratch:SI 3 ""))] | |
4707 | "! TARGET_POWER && reload_completed" | |
4708 | [(set (match_dup 3) | |
4709 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4710 | (set (match_dup 0) | |
4711 | (compare:CC (match_dup 3) | |
4712 | (const_int 0)))] | |
4713 | "") | |
1fd4e8c1 RK |
4714 | |
4715 | (define_insn "" | |
9ebbca7d GK |
4716 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4717 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4718 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4719 | (const_int 0))) |
9ebbca7d | 4720 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4721 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4722 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4723 | "TARGET_POWER" |
1fd4e8c1 RK |
4724 | "@ |
4725 | srea. %0,%1,%2 | |
9ebbca7d GK |
4726 | {srai.|srawi.} %0,%1,%h2 |
4727 | # | |
4728 | #" | |
4729 | [(set_attr "type" "delayed_compare") | |
4730 | (set_attr "length" "4,4,8,8")]) | |
4731 | ||
4732 | (define_split | |
4733 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4734 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4735 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4736 | (const_int 0))) | |
4737 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4738 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4739 | (clobber (match_scratch:SI 4 ""))] | |
4740 | "TARGET_POWER && reload_completed" | |
4741 | [(parallel [(set (match_dup 0) | |
4742 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4743 | (clobber (match_dup 4))]) | |
4744 | (set (match_dup 3) | |
4745 | (compare:CC (match_dup 0) | |
4746 | (const_int 0)))] | |
4747 | "") | |
1fd4e8c1 | 4748 | |
ca7f5001 | 4749 | (define_insn "" |
9ebbca7d GK |
4750 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4751 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4752 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4753 | (const_int 0))) |
9ebbca7d | 4754 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4755 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4756 | "! TARGET_POWER" |
9ebbca7d GK |
4757 | "@ |
4758 | {sra|sraw}%I2. %0,%1,%h2 | |
4759 | #" | |
4760 | [(set_attr "type" "delayed_compare") | |
4761 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4762 | \f |
9ebbca7d GK |
4763 | (define_split |
4764 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4765 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4766 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4767 | (const_int 0))) | |
4768 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4769 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4770 | "! TARGET_POWER && reload_completed" | |
4771 | [(set (match_dup 0) | |
4772 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4773 | (set (match_dup 3) | |
4774 | (compare:CC (match_dup 0) | |
4775 | (const_int 0)))] | |
4776 | "") | |
4777 | ||
1fd4e8c1 RK |
4778 | ;; Floating-point insns, excluding normal data motion. |
4779 | ;; | |
ca7f5001 RK |
4780 | ;; PowerPC has a full set of single-precision floating point instructions. |
4781 | ;; | |
4782 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4783 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4784 | ;; The only conversions we will do will be when storing to memory. In that | |
4785 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4786 | ;; |
4787 | ;; Note that when we store into a single-precision memory location, we need to | |
4788 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4789 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4790 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4791 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4792 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4793 | ||
e8112008 | 4794 | (define_insn "extendsfdf2" |
cd2b37d9 | 4795 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
e8112008 | 4796 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] |
d14a6d05 | 4797 | "TARGET_HARD_FLOAT" |
e8112008 | 4798 | "* |
5c30aff8 | 4799 | { |
e8112008 RK |
4800 | if (REGNO (operands[0]) == REGNO (operands[1])) |
4801 | return \"\"; | |
4802 | else | |
4803 | return \"fmr %0,%1\"; | |
4804 | }" | |
4805 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4806 | |
4807 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
4808 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4809 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4810 | "TARGET_HARD_FLOAT" |
dcac138d | 4811 | "frsp %0,%1" |
1fd4e8c1 RK |
4812 | [(set_attr "type" "fp")]) |
4813 | ||
455350f4 RK |
4814 | (define_insn "aux_truncdfsf2" |
4815 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4816 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))] | |
4817 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" | |
4818 | "frsp %0,%1" | |
4819 | [(set_attr "type" "fp")]) | |
4820 | ||
1fd4e8c1 | 4821 | (define_insn "negsf2" |
cd2b37d9 RK |
4822 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4823 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4824 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4825 | "fneg %0,%1" |
4826 | [(set_attr "type" "fp")]) | |
4827 | ||
4828 | (define_insn "abssf2" | |
cd2b37d9 RK |
4829 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4830 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4831 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4832 | "fabs %0,%1" |
4833 | [(set_attr "type" "fp")]) | |
4834 | ||
4835 | (define_insn "" | |
cd2b37d9 RK |
4836 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4837 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 4838 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4839 | "fnabs %0,%1" |
4840 | [(set_attr "type" "fp")]) | |
4841 | ||
ca7f5001 RK |
4842 | (define_expand "addsf3" |
4843 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4844 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4845 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4846 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4847 | "") |
4848 | ||
4849 | (define_insn "" | |
cd2b37d9 RK |
4850 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4851 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4852 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4853 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4854 | "fadds %0,%1,%2" |
ca7f5001 RK |
4855 | [(set_attr "type" "fp")]) |
4856 | ||
4857 | (define_insn "" | |
4858 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4859 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4860 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4861 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4862 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4863 | [(set_attr "type" "fp")]) |
4864 | ||
4865 | (define_expand "subsf3" | |
4866 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4867 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4868 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4869 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4870 | "") |
4871 | ||
4872 | (define_insn "" | |
4873 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4874 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4875 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4876 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4877 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4878 | [(set_attr "type" "fp")]) |
4879 | ||
ca7f5001 | 4880 | (define_insn "" |
cd2b37d9 RK |
4881 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4882 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4883 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4884 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4885 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4886 | [(set_attr "type" "fp")]) |
4887 | ||
4888 | (define_expand "mulsf3" | |
4889 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4890 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4891 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4892 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4893 | "") |
4894 | ||
4895 | (define_insn "" | |
4896 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4897 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4898 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4899 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4900 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4901 | [(set_attr "type" "fp")]) |
4902 | ||
ca7f5001 | 4903 | (define_insn "" |
cd2b37d9 RK |
4904 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4905 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4906 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4907 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4908 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4909 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4910 | |
ca7f5001 RK |
4911 | (define_expand "divsf3" |
4912 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4913 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4914 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4915 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4916 | "") |
4917 | ||
4918 | (define_insn "" | |
cd2b37d9 RK |
4919 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4920 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4921 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4922 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4923 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4924 | [(set_attr "type" "sdiv")]) |
4925 | ||
4926 | (define_insn "" | |
4927 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4928 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4929 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4930 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4931 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4932 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4933 | |
4934 | (define_insn "" | |
cd2b37d9 RK |
4935 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4936 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4937 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4938 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4939 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4940 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4941 | [(set_attr "type" "fp")]) |
4942 | ||
4943 | (define_insn "" | |
4944 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4945 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4946 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4947 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4948 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4949 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4950 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4951 | |
4952 | (define_insn "" | |
cd2b37d9 RK |
4953 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4954 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4955 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4956 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4957 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4958 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4959 | [(set_attr "type" "fp")]) |
4960 | ||
4961 | (define_insn "" | |
4962 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4963 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4964 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4965 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4966 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4967 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4968 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4969 | |
4970 | (define_insn "" | |
cd2b37d9 RK |
4971 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4972 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4973 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4974 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4975 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4976 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4977 | [(set_attr "type" "fp")]) |
4978 | ||
4979 | (define_insn "" | |
4980 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4981 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4982 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4983 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4984 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4985 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4986 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4987 | |
4988 | (define_insn "" | |
cd2b37d9 RK |
4989 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4990 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4991 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4992 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4993 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4994 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4995 | [(set_attr "type" "fp")]) |
4996 | ||
4997 | (define_insn "" | |
4998 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4999 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5000 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5001 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 5002 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 5003 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 5004 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 5005 | |
ca7f5001 RK |
5006 | (define_expand "sqrtsf2" |
5007 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5008 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 5009 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
5010 | "") |
5011 | ||
5012 | (define_insn "" | |
5013 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5014 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5015 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT" |
ca7f5001 RK |
5016 | "fsqrts %0,%1" |
5017 | [(set_attr "type" "ssqrt")]) | |
5018 | ||
5019 | (define_insn "" | |
5020 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5021 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5022 | "TARGET_POWER2 && TARGET_HARD_FLOAT" |
ca7f5001 RK |
5023 | "fsqrt %0,%1" |
5024 | [(set_attr "type" "dsqrt")]) | |
5025 | ||
94d7001a RK |
5026 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
5027 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
5028 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
5029 | ;; combine. |
5030 | (define_expand "maxsf3" | |
8e871c05 | 5031 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
5032 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
5033 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
5034 | (match_dup 1) |
5035 | (match_dup 2)))] | |
50a0b056 GK |
5036 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
5037 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") | |
2f607b94 | 5038 | |
8e871c05 | 5039 | (define_expand "minsf3" |
50a0b056 GK |
5040 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
5041 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
5042 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
5043 | (match_dup 2) | |
5044 | (match_dup 1)))] | |
d14a6d05 | 5045 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 | 5046 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 5047 | |
8e871c05 RK |
5048 | (define_split |
5049 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
5050 | (match_operator:SF 3 "min_max_operator" |
5051 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
5052 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
d14a6d05 | 5053 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 GK |
5054 | [(const_int 0)] |
5055 | " | |
5056 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
5057 | operands[1], operands[2]); | |
5058 | DONE; | |
5059 | }") | |
2f607b94 | 5060 | |
94d7001a | 5061 | (define_expand "movsfcc" |
0ad91047 | 5062 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 5063 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5064 | (match_operand:SF 2 "gpc_reg_operand" "") |
5065 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 5066 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
5067 | " |
5068 | { | |
50a0b056 GK |
5069 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5070 | DONE; | |
94d7001a | 5071 | else |
50a0b056 | 5072 | FAIL; |
94d7001a | 5073 | }") |
d56d506a | 5074 | |
50a0b056 | 5075 | (define_insn "*fselsfsf4" |
8e871c05 RK |
5076 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5077 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5078 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5079 | (match_operand:SF 2 "gpc_reg_operand" "f") |
5080 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5081 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5082 | "fsel %0,%1,%2,%3" |
5083 | [(set_attr "type" "fp")]) | |
2f607b94 | 5084 | |
50a0b056 | 5085 | (define_insn "*fseldfsf4" |
94d7001a RK |
5086 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5087 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 5088 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5089 | (match_operand:SF 2 "gpc_reg_operand" "f") |
5090 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5091 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
5092 | "fsel %0,%1,%2,%3" |
5093 | [(set_attr "type" "fp")]) | |
d56d506a | 5094 | |
1fd4e8c1 | 5095 | (define_insn "negdf2" |
cd2b37d9 RK |
5096 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5097 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5098 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5099 | "fneg %0,%1" |
5100 | [(set_attr "type" "fp")]) | |
5101 | ||
5102 | (define_insn "absdf2" | |
cd2b37d9 RK |
5103 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5104 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5105 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5106 | "fabs %0,%1" |
5107 | [(set_attr "type" "fp")]) | |
5108 | ||
5109 | (define_insn "" | |
cd2b37d9 RK |
5110 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5111 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 5112 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5113 | "fnabs %0,%1" |
5114 | [(set_attr "type" "fp")]) | |
5115 | ||
5116 | (define_insn "adddf3" | |
cd2b37d9 RK |
5117 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5118 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5119 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5120 | "TARGET_HARD_FLOAT" |
ca7f5001 | 5121 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
5122 | [(set_attr "type" "fp")]) |
5123 | ||
5124 | (define_insn "subdf3" | |
cd2b37d9 RK |
5125 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5126 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
5127 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5128 | "TARGET_HARD_FLOAT" |
ca7f5001 | 5129 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
5130 | [(set_attr "type" "fp")]) |
5131 | ||
5132 | (define_insn "muldf3" | |
cd2b37d9 RK |
5133 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5134 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5135 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5136 | "TARGET_HARD_FLOAT" |
ca7f5001 | 5137 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 5138 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5139 | |
5140 | (define_insn "divdf3" | |
cd2b37d9 RK |
5141 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5142 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
5143 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5144 | "TARGET_HARD_FLOAT" |
ca7f5001 | 5145 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 5146 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
5147 | |
5148 | (define_insn "" | |
cd2b37d9 RK |
5149 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5150 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5151 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5152 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 5153 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5154 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 5155 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5156 | |
5157 | (define_insn "" | |
cd2b37d9 RK |
5158 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5159 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5160 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5161 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 5162 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5163 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 5164 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5165 | |
5166 | (define_insn "" | |
cd2b37d9 RK |
5167 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5168 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5169 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5170 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 5171 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5172 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 5173 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5174 | |
5175 | (define_insn "" | |
cd2b37d9 RK |
5176 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5177 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5178 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5179 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 5180 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5181 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 5182 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
5183 | |
5184 | (define_insn "sqrtdf2" | |
5185 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5186 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5187 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
5188 | "fsqrt %0,%1" |
5189 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 5190 | |
50a0b056 GK |
5191 | ;; The conditional move instructions allow us to perform max and min |
5192 | ;; operations even when | |
b77dfefc | 5193 | |
8e871c05 | 5194 | (define_expand "maxdf3" |
8e871c05 | 5195 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
5196 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
5197 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
5198 | (match_dup 1) |
5199 | (match_dup 2)))] | |
50a0b056 GK |
5200 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
5201 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") | |
b77dfefc | 5202 | |
8e871c05 | 5203 | (define_expand "mindf3" |
50a0b056 GK |
5204 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5205 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
5206 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
5207 | (match_dup 2) | |
5208 | (match_dup 1)))] | |
d14a6d05 | 5209 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 | 5210 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 5211 | |
8e871c05 RK |
5212 | (define_split |
5213 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
5214 | (match_operator:DF 3 "min_max_operator" |
5215 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
5216 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
d14a6d05 | 5217 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 GK |
5218 | [(const_int 0)] |
5219 | " | |
5220 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
5221 | operands[1], operands[2]); | |
5222 | DONE; | |
5223 | }") | |
b77dfefc | 5224 | |
94d7001a | 5225 | (define_expand "movdfcc" |
0ad91047 | 5226 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 5227 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5228 | (match_operand:DF 2 "gpc_reg_operand" "") |
5229 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 5230 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
5231 | " |
5232 | { | |
50a0b056 GK |
5233 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5234 | DONE; | |
94d7001a | 5235 | else |
50a0b056 | 5236 | FAIL; |
94d7001a | 5237 | }") |
d56d506a | 5238 | |
50a0b056 | 5239 | (define_insn "*fseldfdf4" |
8e871c05 RK |
5240 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5241 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5242 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5243 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5244 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5245 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5246 | "fsel %0,%1,%2,%3" |
5247 | [(set_attr "type" "fp")]) | |
d56d506a | 5248 | |
50a0b056 | 5249 | (define_insn "*fselsfdf4" |
94d7001a RK |
5250 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5251 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5252 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5253 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5254 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5255 | "TARGET_PPC_GFXOPT" | |
5256 | "fsel %0,%1,%2,%3" | |
5257 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5258 | \f |
5259 | ;; Conversions to and from floating-point. | |
802a0058 | 5260 | |
9ebbca7d GK |
5261 | ; For each of these conversions, there is a define_expand, a define_insn |
5262 | ; with a '#' template, and a define_split (with C code). The idea is | |
5263 | ; to allow constant folding with the template of the define_insn, | |
5264 | ; then to have the insns split later (between sched1 and final). | |
5265 | ||
1fd4e8c1 | 5266 | (define_expand "floatsidf2" |
802a0058 MM |
5267 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5268 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5269 | (use (match_dup 2)) | |
5270 | (use (match_dup 3)) | |
208c89ce | 5271 | (clobber (match_dup 4)) |
a7df97e6 | 5272 | (clobber (match_dup 5)) |
9ebbca7d | 5273 | (clobber (match_dup 6))])] |
31bfaa0b | 5274 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5275 | " |
5276 | { | |
802a0058 MM |
5277 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5278 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); | |
9ebbca7d GK |
5279 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5280 | operands[5] = gen_reg_rtx (DFmode); | |
5281 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5282 | }") |
5283 | ||
802a0058 MM |
5284 | (define_insn "*floatsidf2_internal" |
5285 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5286 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5287 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5288 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d GK |
5289 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
5290 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=f")) | |
5291 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=r"))] | |
31bfaa0b | 5292 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 5293 | "#" |
a7df97e6 | 5294 | [(set_attr "length" "24")]) |
802a0058 MM |
5295 | |
5296 | (define_split | |
dbe3df29 | 5297 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
5298 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
5299 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5300 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5301 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5302 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5303 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
31bfaa0b | 5304 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5305 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5306 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5307 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5308 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5309 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5310 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5311 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
208c89ce MM |
5312 | " |
5313 | { | |
9ebbca7d GK |
5314 | rtx lowword, highword; |
5315 | if (GET_CODE (operands[4]) != MEM) | |
5316 | abort(); | |
5317 | highword = XEXP (operands[4], 0); | |
5318 | lowword = plus_constant (highword, 4); | |
5319 | if (! WORDS_BIG_ENDIAN) | |
5320 | { | |
5321 | rtx tmp; | |
5322 | tmp = highword; highword = lowword; lowword = tmp; | |
5323 | } | |
5324 | ||
5325 | emit_insn (gen_xorsi3 (operands[6], operands[1], | |
5326 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); | |
5327 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); | |
5328 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5329 | emit_move_insn (operands[5], operands[4]); | |
5330 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5331 | DONE; | |
208c89ce | 5332 | }") |
802a0058 MM |
5333 | |
5334 | (define_expand "floatunssidf2" | |
5335 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5336 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5337 | (use (match_dup 2)) | |
5338 | (use (match_dup 3)) | |
a7df97e6 | 5339 | (clobber (match_dup 4)) |
9ebbca7d | 5340 | (clobber (match_dup 5))])] |
31bfaa0b | 5341 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5342 | " |
5343 | { | |
802a0058 MM |
5344 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5345 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode)); | |
9ebbca7d GK |
5346 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5347 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5348 | }") |
5349 | ||
802a0058 MM |
5350 | (define_insn "*floatunssidf2_internal" |
5351 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5352 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5353 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5354 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d GK |
5355 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
5356 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))] | |
31bfaa0b | 5357 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 5358 | "#" |
a7df97e6 | 5359 | [(set_attr "length" "20")]) |
802a0058 MM |
5360 | |
5361 | (define_split | |
5362 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5363 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5364 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5365 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5366 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5367 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
31bfaa0b | 5368 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5369 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5370 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5371 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5372 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5373 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5374 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
5375 | " | |
802a0058 | 5376 | { |
9ebbca7d GK |
5377 | rtx lowword, highword; |
5378 | if (GET_CODE (operands[4]) != MEM) | |
5379 | abort(); | |
5380 | highword = XEXP (operands[4], 0); | |
5381 | lowword = plus_constant (highword, 4); | |
5382 | if (! WORDS_BIG_ENDIAN) | |
f6968f59 | 5383 | { |
9ebbca7d GK |
5384 | rtx tmp; |
5385 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5386 | } |
802a0058 | 5387 | |
9ebbca7d GK |
5388 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); |
5389 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5390 | emit_move_insn (operands[5], operands[4]); | |
5391 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5392 | DONE; | |
5393 | }") | |
1fd4e8c1 | 5394 | |
1fd4e8c1 | 5395 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
5396 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5397 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5398 | (clobber (match_dup 2)) | |
9ebbca7d | 5399 | (clobber (match_dup 3))])] |
9cb8fcaf | 5400 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5401 | " |
5402 | { | |
802a0058 | 5403 | operands[2] = gen_reg_rtx (DImode); |
9ebbca7d | 5404 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5405 | }") |
5406 | ||
802a0058 MM |
5407 | (define_insn "*fix_truncdfsi2_internal" |
5408 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5409 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5410 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) | |
9ebbca7d | 5411 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
9cb8fcaf | 5412 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
802a0058 | 5413 | "#" |
9ebbca7d | 5414 | [(set_attr "length" "16")]) |
802a0058 MM |
5415 | |
5416 | (define_split | |
5417 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
75540af0 | 5418 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
802a0058 | 5419 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
9ebbca7d | 5420 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] |
9cb8fcaf | 5421 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
9ebbca7d | 5422 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
75540af0 | 5423 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
9ebbca7d GK |
5424 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
5425 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] | |
5426 | " | |
802a0058 | 5427 | { |
9ebbca7d GK |
5428 | rtx lowword; |
5429 | if (GET_CODE (operands[3]) != MEM) | |
5430 | abort(); | |
5431 | lowword = XEXP (operands[3], 0); | |
5432 | if (WORDS_BIG_ENDIAN) | |
5433 | lowword = plus_constant (lowword, 4); | |
802a0058 | 5434 | |
9ebbca7d GK |
5435 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5436 | emit_move_insn (operands[3], operands[2]); | |
5437 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
5438 | DONE; | |
5439 | }") | |
802a0058 | 5440 | |
9ebbca7d GK |
5441 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10)) |
5442 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) | |
5443 | ; because the first makes it clear that operand 0 is not live | |
5444 | ; before the instruction. | |
5445 | (define_insn "fctiwz" | |
5446 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
5447 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))] | |
a260abc9 DE |
5448 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
5449 | "{fcirz|fctiwz} %0,%1" | |
5450 | [(set_attr "type" "fp")]) | |
5451 | ||
a473029f RK |
5452 | (define_insn "floatdidf2" |
5453 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5454 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5455 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
5456 | "fcfid %0,%1" |
5457 | [(set_attr "type" "fp")]) | |
5458 | ||
5459 | (define_insn "fix_truncdfdi2" | |
5460 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
5461 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5462 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
5463 | "fctidz %0,%1" |
5464 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5465 | \f |
5466 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5467 | ;; of instructions. The & constraints are to prevent the register |
5468 | ;; allocator from allocating registers that overlap with the inputs | |
5469 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5470 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5471 | |
266eb58a | 5472 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5473 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5474 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5475 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5476 | "! TARGET_POWERPC64" |
0f645302 MM |
5477 | "* |
5478 | { | |
5479 | if (WORDS_BIG_ENDIAN) | |
5480 | return (GET_CODE (operands[2])) != CONST_INT | |
5481 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5482 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5483 | else | |
5484 | return (GET_CODE (operands[2])) != CONST_INT | |
5485 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5486 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5487 | }" | |
b19003d8 | 5488 | [(set_attr "length" "8")]) |
1fd4e8c1 | 5489 | |
266eb58a | 5490 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5491 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5492 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5493 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5494 | "! TARGET_POWERPC64" |
5502823b RK |
5495 | "* |
5496 | { | |
0f645302 MM |
5497 | if (WORDS_BIG_ENDIAN) |
5498 | return (GET_CODE (operands[1]) != CONST_INT) | |
5499 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5500 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5501 | else | |
5502 | return (GET_CODE (operands[1]) != CONST_INT) | |
5503 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5504 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5505 | }" |
ca7f5001 RK |
5506 | [(set_attr "length" "8")]) |
5507 | ||
266eb58a | 5508 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5509 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5510 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5511 | "! TARGET_POWERPC64" |
5502823b RK |
5512 | "* |
5513 | { | |
5514 | return (WORDS_BIG_ENDIAN) | |
5515 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5516 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5517 | }" | |
ca7f5001 RK |
5518 | [(set_attr "length" "8")]) |
5519 | ||
8ffd9c51 RK |
5520 | (define_expand "mulsidi3" |
5521 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5522 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5523 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5524 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5525 | " |
5526 | { | |
5527 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5528 | { | |
39403d82 DE |
5529 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5530 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5531 | emit_insn (gen_mull_call ()); |
cf27b467 | 5532 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5533 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5534 | else |
5535 | { | |
5536 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5537 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5538 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5539 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5540 | } |
8ffd9c51 RK |
5541 | DONE; |
5542 | } | |
5543 | else if (TARGET_POWER) | |
5544 | { | |
5545 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5546 | DONE; | |
5547 | } | |
5548 | }") | |
deb9225a | 5549 | |
8ffd9c51 | 5550 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5551 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5552 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5553 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5554 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5555 | "TARGET_POWER" |
b19003d8 | 5556 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5557 | [(set_attr "type" "imul") |
5558 | (set_attr "length" "8")]) | |
deb9225a | 5559 | |
f192bf8b | 5560 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5561 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5562 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5563 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5564 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5565 | "* |
5566 | { | |
5567 | return (WORDS_BIG_ENDIAN) | |
5568 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5569 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5570 | }" | |
8ffd9c51 RK |
5571 | [(set_attr "type" "imul") |
5572 | (set_attr "length" "8")]) | |
deb9225a | 5573 | |
ebedb4dd MM |
5574 | (define_split |
5575 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5576 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5577 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5578 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5579 | [(set (match_dup 3) |
5580 | (truncate:SI | |
5581 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5582 | (sign_extend:DI (match_dup 2))) | |
5583 | (const_int 32)))) | |
5584 | (set (match_dup 4) | |
5585 | (mult:SI (match_dup 1) | |
5586 | (match_dup 2)))] | |
5587 | " | |
5588 | { | |
5589 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5590 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5591 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5592 | }") | |
5593 | ||
f192bf8b DE |
5594 | (define_expand "umulsidi3" |
5595 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5596 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5597 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5598 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5599 | " | |
5600 | { | |
5601 | if (TARGET_POWER) | |
5602 | { | |
5603 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5604 | DONE; | |
5605 | } | |
5606 | }") | |
5607 | ||
5608 | (define_insn "umulsidi3_mq" | |
5609 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5610 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5611 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5612 | (clobber (match_scratch:SI 3 "=q"))] | |
5613 | "TARGET_POWERPC && TARGET_POWER" | |
5614 | "* | |
5615 | { | |
5616 | return (WORDS_BIG_ENDIAN) | |
5617 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5618 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5619 | }" | |
5620 | [(set_attr "type" "imul") | |
5621 | (set_attr "length" "8")]) | |
5622 | ||
5623 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5624 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5625 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5626 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5627 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5628 | "* |
5629 | { | |
5630 | return (WORDS_BIG_ENDIAN) | |
5631 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5632 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5633 | }" | |
5634 | [(set_attr "type" "imul") | |
5635 | (set_attr "length" "8")]) | |
5636 | ||
ebedb4dd MM |
5637 | (define_split |
5638 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5639 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5640 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5641 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5642 | [(set (match_dup 3) |
5643 | (truncate:SI | |
5644 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5645 | (zero_extend:DI (match_dup 2))) | |
5646 | (const_int 32)))) | |
5647 | (set (match_dup 4) | |
5648 | (mult:SI (match_dup 1) | |
5649 | (match_dup 2)))] | |
5650 | " | |
5651 | { | |
5652 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5653 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5654 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5655 | }") | |
5656 | ||
8ffd9c51 RK |
5657 | (define_expand "smulsi3_highpart" |
5658 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5659 | (truncate:SI | |
5660 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5661 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5662 | (sign_extend:DI | |
5663 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5664 | (const_int 32))))] | |
5665 | "" | |
5666 | " | |
5667 | { | |
5668 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5669 | { | |
39403d82 DE |
5670 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5671 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5672 | emit_insn (gen_mulh_call ()); |
39403d82 | 5673 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5674 | DONE; |
5675 | } | |
5676 | else if (TARGET_POWER) | |
5677 | { | |
5678 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5679 | DONE; | |
5680 | } | |
5681 | }") | |
deb9225a | 5682 | |
8ffd9c51 RK |
5683 | (define_insn "smulsi3_highpart_mq" |
5684 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5685 | (truncate:SI | |
fada905b MM |
5686 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5687 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5688 | (sign_extend:DI | |
5689 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5690 | (const_int 32)))) |
5691 | (clobber (match_scratch:SI 3 "=q"))] | |
5692 | "TARGET_POWER" | |
5693 | "mul %0,%1,%2" | |
5694 | [(set_attr "type" "imul")]) | |
deb9225a | 5695 | |
f192bf8b | 5696 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5697 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5698 | (truncate:SI | |
fada905b MM |
5699 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5700 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5701 | (sign_extend:DI | |
5702 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5703 | (const_int 32))))] |
f192bf8b | 5704 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5705 | "mulhw %0,%1,%2" |
5706 | [(set_attr "type" "imul")]) | |
deb9225a | 5707 | |
f192bf8b DE |
5708 | (define_expand "umulsi3_highpart" |
5709 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5710 | (truncate:SI | |
5711 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5712 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5713 | (zero_extend:DI | |
5714 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5715 | (const_int 32))))] | |
5716 | "TARGET_POWERPC" | |
5717 | " | |
5718 | { | |
5719 | if (TARGET_POWER) | |
5720 | { | |
5721 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5722 | DONE; | |
5723 | } | |
5724 | }") | |
5725 | ||
5726 | (define_insn "umulsi3_highpart_mq" | |
5727 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5728 | (truncate:SI | |
5729 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5730 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5731 | (zero_extend:DI | |
5732 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5733 | (const_int 32)))) | |
5734 | (clobber (match_scratch:SI 3 "=q"))] | |
5735 | "TARGET_POWERPC && TARGET_POWER" | |
5736 | "mulhwu %0,%1,%2" | |
5737 | [(set_attr "type" "imul")]) | |
5738 | ||
5739 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5740 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5741 | (truncate:SI | |
5742 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5743 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5744 | (zero_extend:DI | |
5745 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5746 | (const_int 32))))] | |
f192bf8b | 5747 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5748 | "mulhwu %0,%1,%2" |
5749 | [(set_attr "type" "imul")]) | |
5750 | ||
5751 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5752 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5753 | ;; why we have the strange constraints below. | |
5754 | (define_insn "ashldi3_power" | |
5755 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5756 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5757 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5758 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5759 | "TARGET_POWER" | |
5760 | "@ | |
5761 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5762 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5763 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5764 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5765 | [(set_attr "length" "8")]) | |
5766 | ||
5767 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5768 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5769 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5770 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5771 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5772 | "TARGET_POWER" | |
5773 | "@ | |
47ad8c61 | 5774 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5775 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5776 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5777 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5778 | [(set_attr "length" "8")]) | |
5779 | ||
5780 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5781 | ;; just handle shifts by constants. | |
5782 | (define_insn "ashrdi3_power" | |
7093ddee | 5783 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5784 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5785 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5786 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5787 | "TARGET_POWER" | |
5788 | "@ | |
5789 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5790 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5791 | [(set_attr "length" "8")]) | |
5792 | \f | |
5793 | ;; PowerPC64 DImode operations. | |
5794 | ||
5795 | (define_expand "adddi3" | |
5796 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5797 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 5798 | (match_operand:DI 2 "reg_or_add_cint64_operand" "")))] |
266eb58a DE |
5799 | "" |
5800 | " | |
5801 | { | |
a260abc9 DE |
5802 | if (! TARGET_POWERPC64) |
5803 | { | |
5804 | if (non_short_cint_operand (operands[2], DImode)) | |
5805 | FAIL; | |
5806 | } | |
5807 | else | |
5808 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 5809 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 5810 | { |
677a9668 | 5811 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
5812 | ? operands[0] : gen_reg_rtx (DImode)); |
5813 | ||
2bfcf297 | 5814 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5815 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5816 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
a260abc9 | 5817 | |
2bfcf297 DB |
5818 | if (!CONST_OK_FOR_LETTER_P (rest, 'L')) |
5819 | FAIL; | |
a260abc9 | 5820 | |
2bfcf297 DB |
5821 | /* The ordering here is important for the prolog expander. |
5822 | When space is allocated from the stack, adding 'low' first may | |
5823 | produce a temporary deallocation (which would be bad). */ | |
5824 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest))); | |
a260abc9 DE |
5825 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); |
5826 | DONE; | |
5827 | } | |
266eb58a DE |
5828 | }") |
5829 | ||
5830 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
5831 | ;; allowing register zero as source. | |
5832 | ||
a260abc9 | 5833 | (define_insn "*adddi3_internal1" |
266eb58a DE |
5834 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
5835 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 5836 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
5837 | "TARGET_POWERPC64" |
5838 | "@ | |
5839 | add %0,%1,%2 | |
5840 | addi %0,%1,%2 | |
5841 | addic %0,%1,%2 | |
802a0058 | 5842 | addis %0,%1,%v2") |
266eb58a | 5843 | |
a260abc9 | 5844 | (define_insn "*adddi3_internal2" |
9ebbca7d GK |
5845 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
5846 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5847 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5848 | (const_int 0))) |
9ebbca7d | 5849 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
266eb58a DE |
5850 | "TARGET_POWERPC64" |
5851 | "@ | |
5852 | add. %3,%1,%2 | |
9ebbca7d GK |
5853 | addic. %3,%1,%2 |
5854 | # | |
5855 | #" | |
5856 | [(set_attr "type" "compare") | |
5857 | (set_attr "length" "4,4,8,8")]) | |
5858 | ||
5859 | (define_split | |
5860 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5861 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5862 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5863 | (const_int 0))) | |
5864 | (clobber (match_scratch:DI 3 ""))] | |
5865 | "TARGET_POWERPC64 && reload_completed" | |
5866 | [(set (match_dup 3) | |
5867 | (plus:DI (match_dup 1) (match_dup 2))) | |
5868 | (set (match_dup 0) | |
5869 | (compare:CC (match_dup 3) | |
5870 | (const_int 0)))] | |
5871 | "") | |
266eb58a | 5872 | |
a260abc9 | 5873 | (define_insn "*adddi3_internal3" |
9ebbca7d GK |
5874 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
5875 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5876 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5877 | (const_int 0))) |
9ebbca7d | 5878 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
266eb58a DE |
5879 | (plus:DI (match_dup 1) (match_dup 2)))] |
5880 | "TARGET_POWERPC64" | |
5881 | "@ | |
5882 | add. %0,%1,%2 | |
9ebbca7d GK |
5883 | addic. %0,%1,%2 |
5884 | # | |
5885 | #" | |
5886 | [(set_attr "type" "compare") | |
5887 | (set_attr "length" "4,4,8,8")]) | |
5888 | ||
5889 | (define_split | |
5890 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5891 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5892 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5893 | (const_int 0))) | |
5894 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5895 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5896 | "TARGET_POWERPC64 && reload_completed" | |
5897 | [(set (match_dup 0) | |
5898 | (plus:DI (match_dup 1) (match_dup 2))) | |
5899 | (set (match_dup 3) | |
5900 | (compare:CC (match_dup 0) | |
5901 | (const_int 0)))] | |
5902 | "") | |
266eb58a DE |
5903 | |
5904 | ;; Split an add that we can't do in one insn into two insns, each of which | |
5905 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
5906 | ;; add should be last in case the result gets used in an address. | |
5907 | ||
5908 | (define_split | |
5909 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5910 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5911 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
5912 | "TARGET_POWERPC64" | |
5913 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
5914 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
5915 | " | |
5916 | { | |
2bfcf297 | 5917 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5918 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5919 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
266eb58a | 5920 | |
2bfcf297 DB |
5921 | operands[4] = GEN_INT (low); |
5922 | if (CONST_OK_FOR_LETTER_P (rest, 'L')) | |
5923 | operands[3] = GEN_INT (rest); | |
5924 | else if (! no_new_pseudos) | |
38886f37 | 5925 | { |
2bfcf297 DB |
5926 | operands[3] = gen_reg_rtx (DImode); |
5927 | emit_move_insn (operands[3], operands[2]); | |
5928 | emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); | |
5929 | DONE; | |
38886f37 | 5930 | } |
2bfcf297 DB |
5931 | else |
5932 | FAIL; | |
266eb58a DE |
5933 | }") |
5934 | ||
5935 | (define_insn "one_cmpldi2" | |
5936 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5937 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5938 | "TARGET_POWERPC64" | |
5939 | "nor %0,%1,%1") | |
5940 | ||
5941 | (define_insn "" | |
9ebbca7d GK |
5942 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5943 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5944 | (const_int 0))) |
9ebbca7d | 5945 | (clobber (match_scratch:DI 2 "=r,r"))] |
266eb58a | 5946 | "TARGET_POWERPC64" |
9ebbca7d GK |
5947 | "@ |
5948 | nor. %2,%1,%1 | |
5949 | #" | |
5950 | [(set_attr "type" "compare") | |
5951 | (set_attr "length" "4,8")]) | |
5952 | ||
5953 | (define_split | |
5954 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5955 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5956 | (const_int 0))) | |
5957 | (clobber (match_scratch:DI 2 ""))] | |
5958 | "TARGET_POWERPC64 && reload_completed" | |
5959 | [(set (match_dup 2) | |
5960 | (not:DI (match_dup 1))) | |
5961 | (set (match_dup 0) | |
5962 | (compare:CC (match_dup 2) | |
5963 | (const_int 0)))] | |
5964 | "") | |
266eb58a DE |
5965 | |
5966 | (define_insn "" | |
9ebbca7d GK |
5967 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5968 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5969 | (const_int 0))) |
9ebbca7d | 5970 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
5971 | (not:DI (match_dup 1)))] |
5972 | "TARGET_POWERPC64" | |
9ebbca7d GK |
5973 | "@ |
5974 | nor. %0,%1,%1 | |
5975 | #" | |
5976 | [(set_attr "type" "compare") | |
5977 | (set_attr "length" "4,8")]) | |
5978 | ||
5979 | (define_split | |
5980 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5981 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5982 | (const_int 0))) | |
5983 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5984 | (not:DI (match_dup 1)))] | |
5985 | "TARGET_POWERPC64 && reload_completed" | |
5986 | [(set (match_dup 0) | |
5987 | (not:DI (match_dup 1))) | |
5988 | (set (match_dup 2) | |
5989 | (compare:CC (match_dup 0) | |
5990 | (const_int 0)))] | |
5991 | "") | |
266eb58a DE |
5992 | |
5993 | (define_insn "" | |
5994 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5995 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
5996 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
5997 | "TARGET_POWERPC64" | |
5998 | "@ | |
5999 | subf %0,%2,%1 | |
6000 | subfic %0,%2,%1") | |
6001 | ||
6002 | (define_insn "" | |
9ebbca7d GK |
6003 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6004 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6005 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 6006 | (const_int 0))) |
9ebbca7d | 6007 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6008 | "TARGET_POWERPC64" |
9ebbca7d GK |
6009 | "@ |
6010 | subf. %3,%2,%1 | |
6011 | #" | |
6012 | [(set_attr "type" "compare") | |
6013 | (set_attr "length" "4,8")]) | |
6014 | ||
6015 | (define_split | |
6016 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6017 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6018 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6019 | (const_int 0))) | |
6020 | (clobber (match_scratch:DI 3 ""))] | |
6021 | "TARGET_POWERPC64 && reload_completed" | |
6022 | [(set (match_dup 3) | |
6023 | (minus:DI (match_dup 1) (match_dup 2))) | |
6024 | (set (match_dup 0) | |
6025 | (compare:CC (match_dup 3) | |
6026 | (const_int 0)))] | |
6027 | "") | |
266eb58a DE |
6028 | |
6029 | (define_insn "" | |
9ebbca7d GK |
6030 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6031 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6032 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 6033 | (const_int 0))) |
9ebbca7d | 6034 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6035 | (minus:DI (match_dup 1) (match_dup 2)))] |
6036 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6037 | "@ |
6038 | subf. %0,%2,%1 | |
6039 | #" | |
6040 | [(set_attr "type" "compare") | |
6041 | (set_attr "length" "4,8")]) | |
6042 | ||
6043 | (define_split | |
6044 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6045 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6046 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6047 | (const_int 0))) | |
6048 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6049 | (minus:DI (match_dup 1) (match_dup 2)))] | |
6050 | "TARGET_POWERPC64 && reload_completed" | |
6051 | [(set (match_dup 0) | |
6052 | (minus:DI (match_dup 1) (match_dup 2))) | |
6053 | (set (match_dup 3) | |
6054 | (compare:CC (match_dup 0) | |
6055 | (const_int 0)))] | |
6056 | "") | |
266eb58a DE |
6057 | |
6058 | (define_expand "subdi3" | |
6059 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6060 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
2bfcf297 | 6061 | (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))] |
266eb58a DE |
6062 | "" |
6063 | " | |
6064 | { | |
6065 | if (GET_CODE (operands[2]) == CONST_INT) | |
6066 | { | |
6067 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
6068 | negate_rtx (DImode, operands[2]))); | |
6069 | DONE; | |
6070 | } | |
6071 | }") | |
6072 | ||
6073 | (define_insn "absdi2" | |
6074 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
6075 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
6076 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
6077 | "TARGET_POWERPC64" | |
a260abc9 | 6078 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0" |
266eb58a DE |
6079 | [(set_attr "length" "12")]) |
6080 | ||
6081 | (define_split | |
75540af0 JH |
6082 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6083 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
6084 | (clobber (match_scratch:DI 2 ""))] | |
266eb58a | 6085 | "TARGET_POWERPC64 && reload_completed" |
a260abc9 | 6086 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6087 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 6088 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
6089 | "") |
6090 | ||
19ba8161 | 6091 | (define_insn "*nabsdi2" |
266eb58a DE |
6092 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
6093 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
6094 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
6095 | "TARGET_POWERPC64" | |
a260abc9 | 6096 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2" |
266eb58a DE |
6097 | [(set_attr "length" "12")]) |
6098 | ||
6099 | (define_split | |
75540af0 JH |
6100 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6101 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))) | |
6102 | (clobber (match_scratch:DI 2 ""))] | |
266eb58a | 6103 | "TARGET_POWERPC64 && reload_completed" |
a260abc9 | 6104 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6105 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 6106 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
6107 | "") |
6108 | ||
6109 | (define_expand "negdi2" | |
6110 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6111 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
6112 | "" | |
6113 | "") | |
6114 | ||
6115 | (define_insn "" | |
6116 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6117 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6118 | "TARGET_POWERPC64" | |
6119 | "neg %0,%1") | |
6120 | ||
6121 | (define_insn "" | |
9ebbca7d GK |
6122 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6123 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 6124 | (const_int 0))) |
9ebbca7d | 6125 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 6126 | "TARGET_POWERPC64" |
9ebbca7d GK |
6127 | "@ |
6128 | neg. %2,%1 | |
6129 | #" | |
6130 | [(set_attr "type" "compare") | |
6131 | (set_attr "length" "4,8")]) | |
6132 | ||
6133 | (define_split | |
6134 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6135 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6136 | (const_int 0))) | |
6137 | (clobber (match_scratch:DI 2 ""))] | |
6138 | "TARGET_POWERPC64 && reload_completed" | |
6139 | [(set (match_dup 2) | |
6140 | (neg:DI (match_dup 1))) | |
6141 | (set (match_dup 0) | |
6142 | (compare:CC (match_dup 2) | |
6143 | (const_int 0)))] | |
6144 | "") | |
815cdc52 | 6145 | |
29ae5b89 | 6146 | (define_insn "" |
9ebbca7d GK |
6147 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
6148 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 6149 | (const_int 0))) |
9ebbca7d | 6150 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 6151 | (neg:DI (match_dup 1)))] |
29ae5b89 | 6152 | "TARGET_POWERPC64" |
9ebbca7d GK |
6153 | "@ |
6154 | neg. %0,%1 | |
6155 | #" | |
6156 | [(set_attr "type" "compare") | |
6157 | (set_attr "length" "4,8")]) | |
6158 | ||
6159 | (define_split | |
6160 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
6161 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6162 | (const_int 0))) | |
6163 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6164 | (neg:DI (match_dup 1)))] | |
6165 | "TARGET_POWERPC64 && reload_completed" | |
6166 | [(set (match_dup 0) | |
6167 | (neg:DI (match_dup 1))) | |
6168 | (set (match_dup 2) | |
6169 | (compare:CC (match_dup 0) | |
6170 | (const_int 0)))] | |
6171 | "") | |
266eb58a DE |
6172 | |
6173 | (define_insn "ffsdi2" | |
6174 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
6175 | (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6176 | "TARGET_POWERPC64" | |
6177 | "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64" | |
6178 | [(set_attr "length" "16")]) | |
6179 | ||
6180 | (define_insn "muldi3" | |
6181 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6182 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
6183 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6184 | "TARGET_POWERPC64" | |
6185 | "mulld %0,%1,%2" | |
3cb999d8 | 6186 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6187 | |
6188 | (define_insn "smuldi3_highpart" | |
6189 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6190 | (truncate:DI | |
6191 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
6192 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6193 | (sign_extend:TI | |
6194 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6195 | (const_int 64))))] | |
6196 | "TARGET_POWERPC64" | |
6197 | "mulhd %0,%1,%2" | |
3cb999d8 | 6198 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6199 | |
6200 | (define_insn "umuldi3_highpart" | |
6201 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6202 | (truncate:DI | |
6203 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
6204 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6205 | (zero_extend:TI | |
6206 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6207 | (const_int 64))))] | |
6208 | "TARGET_POWERPC64" | |
6209 | "mulhdu %0,%1,%2" | |
3cb999d8 | 6210 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6211 | |
6212 | (define_expand "divdi3" | |
6213 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6214 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6215 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6216 | "TARGET_POWERPC64" | |
6217 | " | |
6218 | { | |
6219 | if (GET_CODE (operands[2]) == CONST_INT | |
2bfcf297 | 6220 | && INTVAL (operands[2]) > 0 |
266eb58a DE |
6221 | && exact_log2 (INTVAL (operands[2])) >= 0) |
6222 | ; | |
6223 | else | |
6224 | operands[2] = force_reg (DImode, operands[2]); | |
6225 | }") | |
6226 | ||
6227 | (define_expand "moddi3" | |
6228 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6229 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6230 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6231 | "TARGET_POWERPC64" | |
6232 | " | |
6233 | { | |
2bfcf297 | 6234 | int i; |
266eb58a DE |
6235 | rtx temp1; |
6236 | rtx temp2; | |
6237 | ||
2bfcf297 DB |
6238 | if (GET_CODE (operands[2]) != CONST_INT |
6239 | || INTVAL (operands[2]) <= 0 | |
6240 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) | |
266eb58a DE |
6241 | FAIL; |
6242 | ||
6243 | temp1 = gen_reg_rtx (DImode); | |
6244 | temp2 = gen_reg_rtx (DImode); | |
6245 | ||
6246 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6247 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6248 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6249 | DONE; | |
6250 | }") | |
6251 | ||
6252 | (define_insn "" | |
6253 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6254 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
6255 | (match_operand:DI 2 "exact_log2_cint_operand" "N")))] |
6256 | "TARGET_POWERPC64" | |
266eb58a DE |
6257 | "sradi %0,%1,%p2\;addze %0,%0" |
6258 | [(set_attr "length" "8")]) | |
6259 | ||
6260 | (define_insn "" | |
9ebbca7d GK |
6261 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6262 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6263 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6264 | (const_int 0))) |
9ebbca7d | 6265 | (clobber (match_scratch:DI 3 "=r,r"))] |
2bfcf297 | 6266 | "TARGET_POWERPC64" |
9ebbca7d GK |
6267 | "@ |
6268 | sradi %3,%1,%p2\;addze. %3,%3 | |
6269 | #" | |
266eb58a | 6270 | [(set_attr "type" "compare") |
9ebbca7d GK |
6271 | (set_attr "length" "8,12")]) |
6272 | ||
6273 | (define_split | |
6274 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6275 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6276 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6277 | (const_int 0))) |
6278 | (clobber (match_scratch:DI 3 ""))] | |
2bfcf297 | 6279 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6280 | [(set (match_dup 3) |
6281 | (div:DI (match_dup 1) (match_dup 2))) | |
6282 | (set (match_dup 0) | |
6283 | (compare:CC (match_dup 3) | |
6284 | (const_int 0)))] | |
6285 | "") | |
266eb58a DE |
6286 | |
6287 | (define_insn "" | |
9ebbca7d GK |
6288 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6289 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6290 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6291 | (const_int 0))) |
9ebbca7d | 6292 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6293 | (div:DI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 6294 | "TARGET_POWERPC64" |
9ebbca7d GK |
6295 | "@ |
6296 | sradi %0,%1,%p2\;addze. %0,%0 | |
6297 | #" | |
266eb58a | 6298 | [(set_attr "type" "compare") |
9ebbca7d | 6299 | (set_attr "length" "8,12")]) |
266eb58a | 6300 | |
9ebbca7d GK |
6301 | (define_split |
6302 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6303 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6304 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6305 | (const_int 0))) |
6306 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6307 | (div:DI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 6308 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6309 | [(set (match_dup 0) |
6310 | (div:DI (match_dup 1) (match_dup 2))) | |
6311 | (set (match_dup 3) | |
6312 | (compare:CC (match_dup 0) | |
6313 | (const_int 0)))] | |
6314 | "") | |
6315 | ||
6316 | (define_insn "" | |
6317 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6318 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6319 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6320 | "TARGET_POWERPC64" |
6321 | "divd %0,%1,%2" | |
3cb999d8 | 6322 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6323 | |
6324 | (define_insn "udivdi3" | |
6325 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6326 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6327 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6328 | "TARGET_POWERPC64" | |
6329 | "divdu %0,%1,%2" | |
3cb999d8 | 6330 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6331 | |
6332 | (define_insn "rotldi3" | |
6333 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6334 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6335 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6336 | "TARGET_POWERPC64" | |
a66078ee | 6337 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6338 | |
a260abc9 | 6339 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6340 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6341 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6342 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6343 | (const_int 0))) |
9ebbca7d | 6344 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6345 | "TARGET_POWERPC64" |
9ebbca7d GK |
6346 | "@ |
6347 | rld%I2cl. %3,%1,%H2,0 | |
6348 | #" | |
6349 | [(set_attr "type" "delayed_compare") | |
6350 | (set_attr "length" "4,8")]) | |
6351 | ||
6352 | (define_split | |
6353 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6354 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6355 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6356 | (const_int 0))) | |
6357 | (clobber (match_scratch:DI 3 ""))] | |
6358 | "TARGET_POWERPC64 && reload_completed" | |
6359 | [(set (match_dup 3) | |
6360 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6361 | (set (match_dup 0) | |
6362 | (compare:CC (match_dup 3) | |
6363 | (const_int 0)))] | |
6364 | "") | |
266eb58a | 6365 | |
a260abc9 | 6366 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6367 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6368 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6369 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6370 | (const_int 0))) |
9ebbca7d | 6371 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6372 | (rotate:DI (match_dup 1) (match_dup 2)))] |
6373 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6374 | "@ |
6375 | rld%I2cl. %0,%1,%H2,0 | |
6376 | #" | |
6377 | [(set_attr "type" "delayed_compare") | |
6378 | (set_attr "length" "4,8")]) | |
6379 | ||
6380 | (define_split | |
6381 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6382 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6383 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6384 | (const_int 0))) | |
6385 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6386 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6387 | "TARGET_POWERPC64 && reload_completed" | |
6388 | [(set (match_dup 0) | |
6389 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6390 | (set (match_dup 3) | |
6391 | (compare:CC (match_dup 0) | |
6392 | (const_int 0)))] | |
6393 | "") | |
266eb58a | 6394 | |
a260abc9 DE |
6395 | (define_insn "*rotldi3_internal4" |
6396 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6397 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6398 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
6399 | (match_operand:DI 3 "mask64_operand" "S")))] | |
6400 | "TARGET_POWERPC64" | |
6401 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6402 | ||
6403 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6404 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6405 | (compare:CC (and:DI |
9ebbca7d GK |
6406 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6407 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
6408 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
a260abc9 | 6409 | (const_int 0))) |
9ebbca7d | 6410 | (clobber (match_scratch:DI 4 "=r,r"))] |
a260abc9 | 6411 | "TARGET_POWERPC64" |
9ebbca7d GK |
6412 | "@ |
6413 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6414 | #" | |
6415 | [(set_attr "type" "delayed_compare") | |
6416 | (set_attr "length" "4,8")]) | |
6417 | ||
6418 | (define_split | |
6419 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6420 | (compare:CC (and:DI | |
6421 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6422 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6423 | (match_operand:DI 3 "mask64_operand" "")) | |
6424 | (const_int 0))) | |
6425 | (clobber (match_scratch:DI 4 ""))] | |
6426 | "TARGET_POWERPC64 && reload_completed" | |
6427 | [(set (match_dup 4) | |
6428 | (and:DI (rotate:DI (match_dup 1) | |
6429 | (match_dup 2)) | |
6430 | (match_dup 3))) | |
6431 | (set (match_dup 0) | |
6432 | (compare:CC (match_dup 4) | |
6433 | (const_int 0)))] | |
6434 | "") | |
a260abc9 DE |
6435 | |
6436 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6437 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6438 | (compare:CC (and:DI |
9ebbca7d GK |
6439 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6440 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
6441 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
a260abc9 | 6442 | (const_int 0))) |
9ebbca7d | 6443 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6444 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
6445 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6446 | "@ |
6447 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6448 | #" | |
6449 | [(set_attr "type" "delayed_compare") | |
6450 | (set_attr "length" "4,8")]) | |
6451 | ||
6452 | (define_split | |
6453 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6454 | (compare:CC (and:DI | |
6455 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6456 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6457 | (match_operand:DI 3 "mask64_operand" "")) | |
6458 | (const_int 0))) | |
6459 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6460 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6461 | "TARGET_POWERPC64 && reload_completed" | |
6462 | [(set (match_dup 0) | |
6463 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6464 | (set (match_dup 4) | |
6465 | (compare:CC (match_dup 0) | |
6466 | (const_int 0)))] | |
6467 | "") | |
a260abc9 DE |
6468 | |
6469 | (define_insn "*rotldi3_internal7" | |
6470 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6471 | (zero_extend:DI | |
6472 | (subreg:QI | |
6473 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6474 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6475 | "TARGET_POWERPC64" | |
6476 | "rld%I2cl %0,%1,%H2,56") | |
6477 | ||
6478 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6479 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6480 | (compare:CC (zero_extend:DI |
6481 | (subreg:QI | |
9ebbca7d GK |
6482 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6483 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6484 | (const_int 0))) |
9ebbca7d | 6485 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6486 | "TARGET_POWERPC64" |
9ebbca7d GK |
6487 | "@ |
6488 | rld%I2cl. %3,%1,%H2,56 | |
6489 | #" | |
6490 | [(set_attr "type" "delayed_compare") | |
6491 | (set_attr "length" "4,8")]) | |
6492 | ||
6493 | (define_split | |
6494 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6495 | (compare:CC (zero_extend:DI | |
6496 | (subreg:QI | |
6497 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6498 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6499 | (const_int 0))) | |
6500 | (clobber (match_scratch:DI 3 ""))] | |
6501 | "TARGET_POWERPC64 && reload_completed" | |
6502 | [(set (match_dup 3) | |
6503 | (zero_extend:DI (subreg:QI | |
6504 | (rotate:DI (match_dup 1) | |
6505 | (match_dup 2)) 0))) | |
6506 | (set (match_dup 0) | |
6507 | (compare:CC (match_dup 3) | |
6508 | (const_int 0)))] | |
6509 | "") | |
a260abc9 DE |
6510 | |
6511 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6512 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6513 | (compare:CC (zero_extend:DI |
6514 | (subreg:QI | |
9ebbca7d GK |
6515 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6516 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6517 | (const_int 0))) |
9ebbca7d | 6518 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6519 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6520 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6521 | "@ |
6522 | rld%I2cl. %0,%1,%H2,56 | |
6523 | #" | |
6524 | [(set_attr "type" "delayed_compare") | |
6525 | (set_attr "length" "4,8")]) | |
6526 | ||
6527 | (define_split | |
6528 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6529 | (compare:CC (zero_extend:DI | |
6530 | (subreg:QI | |
6531 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6532 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6533 | (const_int 0))) | |
6534 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6535 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6536 | "TARGET_POWERPC64 && reload_completed" | |
6537 | [(set (match_dup 0) | |
6538 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6539 | (set (match_dup 3) | |
6540 | (compare:CC (match_dup 0) | |
6541 | (const_int 0)))] | |
6542 | "") | |
a260abc9 DE |
6543 | |
6544 | (define_insn "*rotldi3_internal10" | |
6545 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6546 | (zero_extend:DI | |
6547 | (subreg:HI | |
6548 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6549 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6550 | "TARGET_POWERPC64" | |
6551 | "rld%I2cl %0,%1,%H2,48") | |
6552 | ||
6553 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6554 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6555 | (compare:CC (zero_extend:DI |
6556 | (subreg:HI | |
9ebbca7d GK |
6557 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6558 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6559 | (const_int 0))) |
9ebbca7d | 6560 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6561 | "TARGET_POWERPC64" |
9ebbca7d GK |
6562 | "@ |
6563 | rld%I2cl. %3,%1,%H2,48 | |
6564 | #" | |
6565 | [(set_attr "type" "delayed_compare") | |
6566 | (set_attr "length" "4,8")]) | |
6567 | ||
6568 | (define_split | |
6569 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6570 | (compare:CC (zero_extend:DI | |
6571 | (subreg:HI | |
6572 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6573 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6574 | (const_int 0))) | |
6575 | (clobber (match_scratch:DI 3 ""))] | |
6576 | "TARGET_POWERPC64 && reload_completed" | |
6577 | [(set (match_dup 3) | |
6578 | (zero_extend:DI (subreg:HI | |
6579 | (rotate:DI (match_dup 1) | |
6580 | (match_dup 2)) 0))) | |
6581 | (set (match_dup 0) | |
6582 | (compare:CC (match_dup 3) | |
6583 | (const_int 0)))] | |
6584 | "") | |
a260abc9 DE |
6585 | |
6586 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6587 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6588 | (compare:CC (zero_extend:DI |
6589 | (subreg:HI | |
9ebbca7d GK |
6590 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6591 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6592 | (const_int 0))) |
9ebbca7d | 6593 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6594 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6595 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6596 | "@ |
6597 | rld%I2cl. %0,%1,%H2,48 | |
6598 | #" | |
6599 | [(set_attr "type" "delayed_compare") | |
6600 | (set_attr "length" "4,8")]) | |
6601 | ||
6602 | (define_split | |
6603 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6604 | (compare:CC (zero_extend:DI | |
6605 | (subreg:HI | |
6606 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6607 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6608 | (const_int 0))) | |
6609 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6610 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6611 | "TARGET_POWERPC64 && reload_completed" | |
6612 | [(set (match_dup 0) | |
6613 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6614 | (set (match_dup 3) | |
6615 | (compare:CC (match_dup 0) | |
6616 | (const_int 0)))] | |
6617 | "") | |
a260abc9 DE |
6618 | |
6619 | (define_insn "*rotldi3_internal13" | |
6620 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6621 | (zero_extend:DI | |
6622 | (subreg:SI | |
6623 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6624 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6625 | "TARGET_POWERPC64" | |
6626 | "rld%I2cl %0,%1,%H2,32") | |
6627 | ||
6628 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6629 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6630 | (compare:CC (zero_extend:DI |
6631 | (subreg:SI | |
9ebbca7d GK |
6632 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6633 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6634 | (const_int 0))) |
9ebbca7d | 6635 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6636 | "TARGET_POWERPC64" |
9ebbca7d GK |
6637 | "@ |
6638 | rld%I2cl. %3,%1,%H2,32 | |
6639 | #" | |
6640 | [(set_attr "type" "delayed_compare") | |
6641 | (set_attr "length" "4,8")]) | |
6642 | ||
6643 | (define_split | |
6644 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6645 | (compare:CC (zero_extend:DI | |
6646 | (subreg:SI | |
6647 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6648 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6649 | (const_int 0))) | |
6650 | (clobber (match_scratch:DI 3 ""))] | |
6651 | "TARGET_POWERPC64 && reload_completed" | |
6652 | [(set (match_dup 3) | |
6653 | (zero_extend:DI (subreg:SI | |
6654 | (rotate:DI (match_dup 1) | |
6655 | (match_dup 2)) 0))) | |
6656 | (set (match_dup 0) | |
6657 | (compare:CC (match_dup 3) | |
6658 | (const_int 0)))] | |
6659 | "") | |
a260abc9 DE |
6660 | |
6661 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6662 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6663 | (compare:CC (zero_extend:DI |
6664 | (subreg:SI | |
9ebbca7d GK |
6665 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6666 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6667 | (const_int 0))) |
9ebbca7d | 6668 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6669 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6670 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6671 | "@ |
6672 | rld%I2cl. %0,%1,%H2,32 | |
6673 | #" | |
6674 | [(set_attr "type" "delayed_compare") | |
6675 | (set_attr "length" "4,8")]) | |
6676 | ||
6677 | (define_split | |
6678 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6679 | (compare:CC (zero_extend:DI | |
6680 | (subreg:SI | |
6681 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6682 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6683 | (const_int 0))) | |
6684 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6685 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6686 | "TARGET_POWERPC64 && reload_completed" | |
6687 | [(set (match_dup 0) | |
6688 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6689 | (set (match_dup 3) | |
6690 | (compare:CC (match_dup 0) | |
6691 | (const_int 0)))] | |
6692 | "") | |
a260abc9 | 6693 | |
266eb58a DE |
6694 | (define_expand "ashldi3" |
6695 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6696 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6697 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6698 | "TARGET_POWERPC64 || TARGET_POWER" | |
6699 | " | |
6700 | { | |
6701 | if (TARGET_POWERPC64) | |
6702 | ; | |
6703 | else if (TARGET_POWER) | |
6704 | { | |
6705 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6706 | DONE; | |
6707 | } | |
6708 | else | |
6709 | FAIL; | |
6710 | }") | |
6711 | ||
e2c953b6 | 6712 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
6713 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6714 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6715 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6716 | "TARGET_POWERPC64" | |
a66078ee | 6717 | "sld%I2 %0,%1,%H2" |
266eb58a DE |
6718 | [(set_attr "length" "8")]) |
6719 | ||
e2c953b6 | 6720 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
6721 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6722 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6723 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6724 | (const_int 0))) |
9ebbca7d | 6725 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6726 | "TARGET_POWERPC64" |
9ebbca7d GK |
6727 | "@ |
6728 | sld%I2. %3,%1,%H2 | |
6729 | #" | |
6730 | [(set_attr "type" "delayed_compare") | |
6731 | (set_attr "length" "4,8")]) | |
29ae5b89 | 6732 | |
9ebbca7d GK |
6733 | (define_split |
6734 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6735 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6736 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6737 | (const_int 0))) | |
6738 | (clobber (match_scratch:DI 3 ""))] | |
6739 | "TARGET_POWERPC64 && reload_completed" | |
6740 | [(set (match_dup 3) | |
6741 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6742 | (set (match_dup 0) | |
6743 | (compare:CC (match_dup 3) | |
6744 | (const_int 0)))] | |
6745 | "") | |
6746 | ||
e2c953b6 | 6747 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
6748 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6749 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6750 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6751 | (const_int 0))) |
9ebbca7d | 6752 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6753 | (ashift:DI (match_dup 1) (match_dup 2)))] |
6754 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6755 | "@ |
6756 | sld%I2. %0,%1,%H2 | |
6757 | #" | |
6758 | [(set_attr "type" "delayed_compare") | |
6759 | (set_attr "length" "4,8")]) | |
6760 | ||
6761 | (define_split | |
6762 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6763 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6764 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6765 | (const_int 0))) | |
6766 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6767 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6768 | "TARGET_POWERPC64 && reload_completed" | |
6769 | [(set (match_dup 0) | |
6770 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6771 | (set (match_dup 3) | |
6772 | (compare:CC (match_dup 0) | |
6773 | (const_int 0)))] | |
6774 | "") | |
266eb58a | 6775 | |
e2c953b6 | 6776 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
6777 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6778 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6779 | (match_operand:SI 2 "const_int_operand" "i")) | |
c5059423 AM |
6780 | (match_operand:DI 3 "const_int_operand" "n")))] |
6781 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" | |
e2c953b6 | 6782 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 6783 | |
e2c953b6 | 6784 | (define_insn "ashldi3_internal5" |
9ebbca7d | 6785 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6786 | (compare:CC |
9ebbca7d GK |
6787 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6788 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6789 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6790 | (const_int 0))) |
9ebbca7d | 6791 | (clobber (match_scratch:DI 4 "=r,r"))] |
c5059423 | 6792 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6793 | "@ |
e2c953b6 | 6794 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
6795 | #" |
6796 | [(set_attr "type" "delayed_compare") | |
6797 | (set_attr "length" "4,8")]) | |
6798 | ||
6799 | (define_split | |
6800 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6801 | (compare:CC | |
6802 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6803 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6804 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6805 | (const_int 0))) |
6806 | (clobber (match_scratch:DI 4 ""))] | |
c5059423 AM |
6807 | "TARGET_POWERPC64 && reload_completed |
6808 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
9ebbca7d GK |
6809 | [(set (match_dup 4) |
6810 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 6811 | (match_dup 3))) |
9ebbca7d GK |
6812 | (set (match_dup 0) |
6813 | (compare:CC (match_dup 4) | |
6814 | (const_int 0)))] | |
6815 | "") | |
3cb999d8 | 6816 | |
e2c953b6 | 6817 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 6818 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6819 | (compare:CC |
9ebbca7d GK |
6820 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6821 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6822 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6823 | (const_int 0))) |
9ebbca7d | 6824 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 6825 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
c5059423 | 6826 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6827 | "@ |
e2c953b6 | 6828 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
6829 | #" |
6830 | [(set_attr "type" "delayed_compare") | |
6831 | (set_attr "length" "4,8")]) | |
6832 | ||
6833 | (define_split | |
6834 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6835 | (compare:CC | |
6836 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6837 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6838 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6839 | (const_int 0))) |
6840 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6841 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
c5059423 AM |
6842 | "TARGET_POWERPC64 && reload_completed |
6843 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
6844 | [(set (match_dup 0) | |
6845 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6846 | (match_dup 3))) | |
6847 | (set (match_dup 4) | |
6848 | (compare:CC (match_dup 0) | |
6849 | (const_int 0)))] | |
6850 | "") | |
6851 | ||
6852 | (define_insn "*ashldi3_internal7" | |
6853 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6854 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6855 | (match_operand:SI 2 "const_int_operand" "i")) | |
6856 | (match_operand:DI 3 "mask64_operand" "S")))] | |
6857 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6858 | "rldicr %0,%1,%H2,%S3") | |
6859 | ||
6860 | (define_insn "ashldi3_internal8" | |
6861 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6862 | (compare:CC | |
6863 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6864 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
6865 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
6866 | (const_int 0))) | |
6867 | (clobber (match_scratch:DI 4 "=r,r"))] | |
6868 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6869 | "@ | |
6870 | rldicr. %4,%1,%H2,%S3 | |
6871 | #" | |
6872 | [(set_attr "type" "delayed_compare") | |
6873 | (set_attr "length" "4,8")]) | |
6874 | ||
6875 | (define_split | |
6876 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6877 | (compare:CC | |
6878 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6879 | (match_operand:SI 2 "const_int_operand" "")) | |
6880 | (match_operand:DI 3 "mask64_operand" "")) | |
6881 | (const_int 0))) | |
6882 | (clobber (match_scratch:DI 4 ""))] | |
6883 | "TARGET_POWERPC64 && reload_completed | |
6884 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6885 | [(set (match_dup 4) | |
6886 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6887 | (match_dup 3))) | |
6888 | (set (match_dup 0) | |
6889 | (compare:CC (match_dup 4) | |
6890 | (const_int 0)))] | |
6891 | "") | |
6892 | ||
6893 | (define_insn "*ashldi3_internal9" | |
6894 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
6895 | (compare:CC | |
6896 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6897 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
6898 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
6899 | (const_int 0))) | |
6900 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6901 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6902 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6903 | "@ | |
6904 | rldicr. %0,%1,%H2,%S3 | |
6905 | #" | |
6906 | [(set_attr "type" "delayed_compare") | |
6907 | (set_attr "length" "4,8")]) | |
6908 | ||
6909 | (define_split | |
6910 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6911 | (compare:CC | |
6912 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6913 | (match_operand:SI 2 "const_int_operand" "")) | |
6914 | (match_operand:DI 3 "mask64_operand" "")) | |
6915 | (const_int 0))) | |
6916 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6917 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6918 | "TARGET_POWERPC64 && reload_completed | |
6919 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
9ebbca7d | 6920 | [(set (match_dup 0) |
e2c953b6 DE |
6921 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
6922 | (match_dup 3))) | |
9ebbca7d GK |
6923 | (set (match_dup 4) |
6924 | (compare:CC (match_dup 0) | |
6925 | (const_int 0)))] | |
6926 | "") | |
6927 | ||
6928 | (define_expand "lshrdi3" | |
266eb58a DE |
6929 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6930 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6931 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6932 | "TARGET_POWERPC64 || TARGET_POWER" | |
6933 | " | |
6934 | { | |
6935 | if (TARGET_POWERPC64) | |
6936 | ; | |
6937 | else if (TARGET_POWER) | |
6938 | { | |
6939 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
6940 | DONE; | |
6941 | } | |
6942 | else | |
6943 | FAIL; | |
6944 | }") | |
6945 | ||
e2c953b6 | 6946 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
6947 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6948 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6949 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6950 | "TARGET_POWERPC64" | |
a66078ee | 6951 | "srd%I2 %0,%1,%H2") |
266eb58a | 6952 | |
e2c953b6 | 6953 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
6954 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6955 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6956 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 6957 | (const_int 0))) |
9ebbca7d | 6958 | (clobber (match_scratch:DI 3 "=r,r"))] |
29ae5b89 | 6959 | "TARGET_POWERPC64" |
9ebbca7d GK |
6960 | "@ |
6961 | srd%I2. %3,%1,%H2 | |
6962 | #" | |
6963 | [(set_attr "type" "delayed_compare") | |
6964 | (set_attr "length" "4,8")]) | |
6965 | ||
6966 | (define_split | |
6967 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6968 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6969 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6970 | (const_int 0))) | |
6971 | (clobber (match_scratch:DI 3 ""))] | |
6972 | "TARGET_POWERPC64 && reload_completed" | |
6973 | [(set (match_dup 3) | |
6974 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6975 | (set (match_dup 0) | |
6976 | (compare:CC (match_dup 3) | |
6977 | (const_int 0)))] | |
6978 | "") | |
266eb58a | 6979 | |
e2c953b6 | 6980 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
6981 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6982 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6983 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6984 | (const_int 0))) |
9ebbca7d | 6985 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 JL |
6986 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
6987 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6988 | "@ |
6989 | srd%I2. %0,%1,%H2 | |
6990 | #" | |
6991 | [(set_attr "type" "delayed_compare") | |
6992 | (set_attr "length" "4,8")]) | |
6993 | ||
6994 | (define_split | |
6995 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6996 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6997 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6998 | (const_int 0))) | |
6999 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7000 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
7001 | "TARGET_POWERPC64 && reload_completed" | |
7002 | [(set (match_dup 0) | |
7003 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
7004 | (set (match_dup 3) | |
7005 | (compare:CC (match_dup 0) | |
7006 | (const_int 0)))] | |
7007 | "") | |
266eb58a DE |
7008 | |
7009 | (define_expand "ashrdi3" | |
7010 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7011 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7012 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
7013 | "TARGET_POWERPC64 || TARGET_POWER" | |
7014 | " | |
7015 | { | |
7016 | if (TARGET_POWERPC64) | |
7017 | ; | |
7018 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
7019 | { | |
7020 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
7021 | DONE; | |
7022 | } | |
7023 | else | |
7024 | FAIL; | |
7025 | }") | |
7026 | ||
e2c953b6 | 7027 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
7028 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7029 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7030 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
7031 | "TARGET_POWERPC64" | |
375490e0 | 7032 | "srad%I2 %0,%1,%H2") |
266eb58a | 7033 | |
e2c953b6 | 7034 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
7035 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
7036 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7037 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7038 | (const_int 0))) |
9ebbca7d | 7039 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7040 | "TARGET_POWERPC64" |
9ebbca7d GK |
7041 | "@ |
7042 | srad%I2. %3,%1,%H2 | |
7043 | #" | |
7044 | [(set_attr "type" "delayed_compare") | |
7045 | (set_attr "length" "4,8")]) | |
7046 | ||
7047 | (define_split | |
7048 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7049 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7050 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7051 | (const_int 0))) | |
7052 | (clobber (match_scratch:DI 3 ""))] | |
7053 | "TARGET_POWERPC64 && reload_completed" | |
7054 | [(set (match_dup 3) | |
7055 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7056 | (set (match_dup 0) | |
7057 | (compare:CC (match_dup 3) | |
7058 | (const_int 0)))] | |
7059 | "") | |
266eb58a | 7060 | |
e2c953b6 | 7061 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
7062 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7063 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7064 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7065 | (const_int 0))) |
9ebbca7d | 7066 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
7067 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
7068 | "TARGET_POWERPC64" | |
9ebbca7d GK |
7069 | "@ |
7070 | srad%I2. %0,%1,%H2 | |
7071 | #" | |
7072 | [(set_attr "type" "delayed_compare") | |
7073 | (set_attr "length" "4,8")]) | |
7074 | ||
7075 | (define_split | |
7076 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7077 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7078 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7079 | (const_int 0))) | |
7080 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7081 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
7082 | "TARGET_POWERPC64 && reload_completed" | |
7083 | [(set (match_dup 0) | |
7084 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7085 | (set (match_dup 3) | |
7086 | (compare:CC (match_dup 0) | |
7087 | (const_int 0)))] | |
7088 | "") | |
815cdc52 | 7089 | |
29ae5b89 JL |
7090 | (define_insn "anddi3" |
7091 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") | |
7092 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
7093 | (match_operand:DI 2 "and64_operand" "?r,S,K,J"))) | |
7094 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] | |
6ffc8580 | 7095 | "TARGET_POWERPC64" |
266eb58a DE |
7096 | "@ |
7097 | and %0,%1,%2 | |
29ae5b89 JL |
7098 | rldic%B2 %0,%1,0,%S2 |
7099 | andi. %0,%1,%b2 | |
7100 | andis. %0,%1,%u2") | |
266eb58a | 7101 | |
a260abc9 | 7102 | (define_insn "*anddi3_internal2" |
6c873122 | 7103 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y") |
9ebbca7d | 7104 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,") |
6c873122 | 7105 | (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J")) |
266eb58a | 7106 | (const_int 0))) |
9ebbca7d | 7107 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r")) |
6c873122 | 7108 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))] |
6ffc8580 | 7109 | "TARGET_POWERPC64" |
266eb58a DE |
7110 | "@ |
7111 | and. %3,%1,%2 | |
6c873122 | 7112 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
7113 | andi. %3,%1,%b2 |
7114 | andis. %3,%1,%u2 | |
9ebbca7d GK |
7115 | # |
7116 | # | |
7117 | # | |
7118 | #" | |
6c873122 | 7119 | [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare") |
9ebbca7d GK |
7120 | (set_attr "length" "4,4,4,4,8,8,8,8")]) |
7121 | ||
7122 | (define_split | |
7123 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7124 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7125 | (match_operand:DI 2 "and64_operand" "")) | |
7126 | (const_int 0))) | |
7127 | (clobber (match_scratch:DI 3 "")) | |
7128 | (clobber (match_scratch:CC 4 ""))] | |
7129 | "TARGET_POWERPC64 && reload_completed" | |
7130 | [(parallel [(set (match_dup 3) | |
7131 | (and:DI (match_dup 1) | |
7132 | (match_dup 2))) | |
7133 | (clobber (match_dup 4))]) | |
7134 | (set (match_dup 0) | |
7135 | (compare:CC (match_dup 3) | |
7136 | (const_int 0)))] | |
7137 | "") | |
266eb58a | 7138 | |
a260abc9 | 7139 | (define_insn "*anddi3_internal3" |
6c873122 | 7140 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y") |
9ebbca7d | 7141 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") |
6c873122 | 7142 | (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J")) |
266eb58a | 7143 | (const_int 0))) |
9ebbca7d GK |
7144 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") |
7145 | (and:DI (match_dup 1) (match_dup 2))) | |
6c873122 | 7146 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))] |
6ffc8580 | 7147 | "TARGET_POWERPC64" |
266eb58a DE |
7148 | "@ |
7149 | and. %0,%1,%2 | |
6c873122 | 7150 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
7151 | andi. %0,%1,%b2 |
7152 | andis. %0,%1,%u2 | |
9ebbca7d GK |
7153 | # |
7154 | # | |
7155 | # | |
7156 | #" | |
6c873122 | 7157 | [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare") |
9ebbca7d GK |
7158 | (set_attr "length" "4,4,4,4,8,8,8,8")]) |
7159 | ||
7160 | (define_split | |
7161 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7162 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7163 | (match_operand:DI 2 "and64_operand" "")) | |
7164 | (const_int 0))) | |
7165 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7166 | (and:DI (match_dup 1) (match_dup 2))) | |
7167 | (clobber (match_scratch:CC 4 ""))] | |
7168 | "TARGET_POWERPC64 && reload_completed" | |
7169 | [(parallel [(set (match_dup 0) | |
7170 | (and:DI (match_dup 1) (match_dup 2))) | |
7171 | (clobber (match_dup 4))]) | |
7172 | (set (match_dup 3) | |
7173 | (compare:CC (match_dup 0) | |
7174 | (const_int 0)))] | |
7175 | "") | |
266eb58a | 7176 | |
a260abc9 | 7177 | (define_expand "iordi3" |
266eb58a | 7178 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 7179 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 7180 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 7181 | "TARGET_POWERPC64" |
266eb58a DE |
7182 | " |
7183 | { | |
dfbdccdb | 7184 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 7185 | { |
dfbdccdb | 7186 | HOST_WIDE_INT value; |
677a9668 | 7187 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 7188 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 7189 | |
dfbdccdb GK |
7190 | if (GET_CODE (operands[2]) == CONST_INT) |
7191 | { | |
7192 | value = INTVAL (operands[2]); | |
7193 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7194 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7195 | } | |
e2c953b6 | 7196 | else |
dfbdccdb GK |
7197 | { |
7198 | value = CONST_DOUBLE_LOW (operands[2]); | |
7199 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7200 | immed_double_const (value | |
7201 | & (~ (HOST_WIDE_INT) 0xffff), | |
7202 | 0, DImode))); | |
7203 | } | |
e2c953b6 | 7204 | |
9ebbca7d GK |
7205 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7206 | DONE; | |
7207 | } | |
266eb58a DE |
7208 | }") |
7209 | ||
a260abc9 DE |
7210 | (define_expand "xordi3" |
7211 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7212 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 7213 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
7214 | "TARGET_POWERPC64" |
7215 | " | |
7216 | { | |
dfbdccdb | 7217 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 7218 | { |
dfbdccdb | 7219 | HOST_WIDE_INT value; |
677a9668 | 7220 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
7221 | ? operands[0] : gen_reg_rtx (DImode)); |
7222 | ||
dfbdccdb GK |
7223 | if (GET_CODE (operands[2]) == CONST_INT) |
7224 | { | |
7225 | value = INTVAL (operands[2]); | |
7226 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7227 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7228 | } | |
e2c953b6 | 7229 | else |
dfbdccdb GK |
7230 | { |
7231 | value = CONST_DOUBLE_LOW (operands[2]); | |
7232 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7233 | immed_double_const (value | |
7234 | & (~ (HOST_WIDE_INT) 0xffff), | |
7235 | 0, DImode))); | |
7236 | } | |
e2c953b6 | 7237 | |
9ebbca7d GK |
7238 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7239 | DONE; | |
7240 | } | |
a260abc9 DE |
7241 | }") |
7242 | ||
dfbdccdb | 7243 | (define_insn "*booldi3_internal1" |
266eb58a | 7244 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 7245 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7246 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
7247 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 7248 | "TARGET_POWERPC64" |
1fd4e8c1 | 7249 | "@ |
dfbdccdb GK |
7250 | %q3 %0,%1,%2 |
7251 | %q3i %0,%1,%b2 | |
7252 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 7253 | |
dfbdccdb | 7254 | (define_insn "*booldi3_internal2" |
9ebbca7d | 7255 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 7256 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
7257 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
7258 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7259 | (const_int 0))) | |
9ebbca7d | 7260 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7261 | "TARGET_POWERPC64" |
9ebbca7d | 7262 | "@ |
dfbdccdb | 7263 | %q4. %3,%1,%2 |
9ebbca7d GK |
7264 | #" |
7265 | [(set_attr "type" "compare") | |
7266 | (set_attr "length" "4,8")]) | |
7267 | ||
7268 | (define_split | |
7269 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7270 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7271 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7272 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7273 | (const_int 0))) |
9ebbca7d GK |
7274 | (clobber (match_scratch:DI 3 ""))] |
7275 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7276 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7277 | (set (match_dup 0) |
7278 | (compare:CC (match_dup 3) | |
7279 | (const_int 0)))] | |
7280 | "") | |
1fd4e8c1 | 7281 | |
dfbdccdb | 7282 | (define_insn "*booldi3_internal3" |
9ebbca7d | 7283 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7284 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7285 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7286 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7287 | (const_int 0))) | |
9ebbca7d | 7288 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7289 | (match_dup 4))] |
266eb58a | 7290 | "TARGET_POWERPC64" |
9ebbca7d | 7291 | "@ |
dfbdccdb | 7292 | %q4. %0,%1,%2 |
9ebbca7d GK |
7293 | #" |
7294 | [(set_attr "type" "compare") | |
7295 | (set_attr "length" "4,8")]) | |
7296 | ||
7297 | (define_split | |
e72247f4 | 7298 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7299 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7300 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7301 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7302 | (const_int 0))) |
75540af0 | 7303 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7304 | (match_dup 4))] |
9ebbca7d | 7305 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7306 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7307 | (set (match_dup 3) |
7308 | (compare:CC (match_dup 0) | |
7309 | (const_int 0)))] | |
7310 | "") | |
1fd4e8c1 | 7311 | |
dfbdccdb GK |
7312 | ;; Split an logical operation that we can't do in one insn into two insns, |
7313 | ;; each of which does one 16-bit part. This is used by combine. | |
266eb58a DE |
7314 | |
7315 | (define_split | |
7316 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 7317 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7318 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7319 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7320 | "TARGET_POWERPC64" |
dfbdccdb GK |
7321 | [(set (match_dup 0) (match_dup 4)) |
7322 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7323 | " |
7324 | { | |
dfbdccdb GK |
7325 | rtx i3,i4; |
7326 | ||
9ebbca7d GK |
7327 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7328 | { | |
7329 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7330 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7331 | 0, DImode); |
dfbdccdb | 7332 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7333 | } |
7334 | else | |
7335 | { | |
dfbdccdb | 7336 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7337 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7338 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7339 | } |
dfbdccdb GK |
7340 | operands[4] = gen_rtx (GET_CODE (operands[3]), DImode, |
7341 | operands[1], i3); | |
7342 | operands[5] = gen_rtx (GET_CODE (operands[3]), DImode, | |
7343 | operands[0], i4); | |
1fd4e8c1 RK |
7344 | }") |
7345 | ||
dfbdccdb | 7346 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7347 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7348 | (match_operator:DI 3 "boolean_operator" |
7349 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7350 | (match_operand:DI 2 "gpc_reg_operand" "r")]))] |
a473029f | 7351 | "TARGET_POWERPC64" |
1d328b19 | 7352 | "%q3 %0,%2,%1") |
a473029f | 7353 | |
dfbdccdb | 7354 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7355 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7356 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7357 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7358 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7359 | (const_int 0))) | |
9ebbca7d | 7360 | (clobber (match_scratch:DI 3 "=r,r"))] |
a473029f | 7361 | "TARGET_POWERPC64" |
9ebbca7d | 7362 | "@ |
1d328b19 | 7363 | %q4. %3,%2,%1 |
9ebbca7d GK |
7364 | #" |
7365 | [(set_attr "type" "compare") | |
7366 | (set_attr "length" "4,8")]) | |
7367 | ||
7368 | (define_split | |
7369 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7370 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7371 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7372 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7373 | (const_int 0))) |
9ebbca7d GK |
7374 | (clobber (match_scratch:DI 3 ""))] |
7375 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7376 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7377 | (set (match_dup 0) |
7378 | (compare:CC (match_dup 3) | |
7379 | (const_int 0)))] | |
7380 | "") | |
a473029f | 7381 | |
dfbdccdb | 7382 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7383 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7384 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7385 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7386 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7387 | (const_int 0))) | |
9ebbca7d | 7388 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7389 | (match_dup 4))] |
a473029f | 7390 | "TARGET_POWERPC64" |
9ebbca7d | 7391 | "@ |
1d328b19 | 7392 | %q4. %0,%2,%1 |
9ebbca7d GK |
7393 | #" |
7394 | [(set_attr "type" "compare") | |
7395 | (set_attr "length" "4,8")]) | |
7396 | ||
7397 | (define_split | |
e72247f4 | 7398 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7399 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7400 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7401 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7402 | (const_int 0))) |
75540af0 | 7403 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7404 | (match_dup 4))] |
9ebbca7d | 7405 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7406 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7407 | (set (match_dup 3) |
7408 | (compare:CC (match_dup 0) | |
7409 | (const_int 0)))] | |
7410 | "") | |
266eb58a | 7411 | |
dfbdccdb | 7412 | (define_insn "*boolccdi3_internal1" |
a473029f | 7413 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7414 | (match_operator:DI 3 "boolean_operator" |
7415 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7416 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] |
a473029f | 7417 | "TARGET_POWERPC64" |
dfbdccdb | 7418 | "%q3 %0,%1,%2") |
a473029f | 7419 | |
dfbdccdb | 7420 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7421 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7422 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7423 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7424 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7425 | (const_int 0))) | |
9ebbca7d | 7426 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7427 | "TARGET_POWERPC64" |
9ebbca7d | 7428 | "@ |
dfbdccdb | 7429 | %q4. %3,%1,%2 |
9ebbca7d GK |
7430 | #" |
7431 | [(set_attr "type" "compare") | |
7432 | (set_attr "length" "4,8")]) | |
7433 | ||
7434 | (define_split | |
7435 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7436 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7437 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7438 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7439 | (const_int 0))) |
9ebbca7d GK |
7440 | (clobber (match_scratch:DI 3 ""))] |
7441 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7442 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7443 | (set (match_dup 0) |
7444 | (compare:CC (match_dup 3) | |
7445 | (const_int 0)))] | |
7446 | "") | |
266eb58a | 7447 | |
dfbdccdb | 7448 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7449 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7450 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7451 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7452 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7453 | (const_int 0))) | |
9ebbca7d | 7454 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7455 | (match_dup 4))] |
29ae5b89 | 7456 | "TARGET_POWERPC64" |
9ebbca7d | 7457 | "@ |
dfbdccdb | 7458 | %q4. %0,%1,%2 |
9ebbca7d GK |
7459 | #" |
7460 | [(set_attr "type" "compare") | |
7461 | (set_attr "length" "4,8")]) | |
7462 | ||
7463 | (define_split | |
e72247f4 | 7464 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7465 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7466 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7467 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7468 | (const_int 0))) |
75540af0 | 7469 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7470 | (match_dup 4))] |
9ebbca7d | 7471 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7472 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7473 | (set (match_dup 3) |
7474 | (compare:CC (match_dup 0) | |
7475 | (const_int 0)))] | |
7476 | "") | |
dfbdccdb | 7477 | \f |
1fd4e8c1 | 7478 | ;; Now define ways of moving data around. |
4697a36c MM |
7479 | |
7480 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
7481 | ;; The output of this could be r0, but we make a very strong |
7482 | ;; preference for a base register because it will usually | |
7483 | ;; be needed there. | |
4697a36c | 7484 | (define_insn "elf_high" |
9ebbca7d | 7485 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 7486 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 7487 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 7488 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
7489 | |
7490 | (define_insn "elf_low" | |
9ebbca7d GK |
7491 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
7492 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 7493 | (match_operand 2 "" "")))] |
0ad91047 | 7494 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
7495 | "@ |
7496 | {cal|la} %0,%2@l(%1) | |
81eace42 | 7497 | {ai|addic} %0,%1,%K2") |
4697a36c | 7498 | |
ee890fe2 SS |
7499 | ;; Mach-O PIC trickery. |
7500 | (define_insn "macho_high" | |
7501 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") | |
7502 | (high:SI (match_operand 1 "" "")))] | |
7503 | "TARGET_MACHO && ! TARGET_64BIT" | |
7504 | "{liu|lis} %0,ha16(%1)") | |
7505 | ||
7506 | (define_insn "macho_low" | |
7507 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
7508 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
7509 | (match_operand 2 "" "")))] | |
7510 | "TARGET_MACHO && ! TARGET_64BIT" | |
7511 | "@ | |
7512 | {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} | |
7513 | {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") | |
7514 | ||
766a866c MM |
7515 | ;; Set up a register with a value from the GOT table |
7516 | ||
7517 | (define_expand "movsi_got" | |
52d3af72 | 7518 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d GK |
7519 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
7520 | (match_dup 2)] 8))] | |
f607bc57 | 7521 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7522 | " |
7523 | { | |
38c1f2d7 MM |
7524 | if (GET_CODE (operands[1]) == CONST) |
7525 | { | |
7526 | rtx offset = const0_rtx; | |
7527 | HOST_WIDE_INT value; | |
7528 | ||
7529 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7530 | value = INTVAL (offset); | |
7531 | if (value != 0) | |
7532 | { | |
677a9668 | 7533 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7534 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7535 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7536 | DONE; | |
7537 | } | |
7538 | } | |
7539 | ||
c4c40373 | 7540 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7541 | }") |
7542 | ||
84f414bc | 7543 | (define_insn "*movsi_got_internal" |
52d3af72 | 7544 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d GK |
7545 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
7546 | (match_operand:SI 2 "gpc_reg_operand" "b")] 8))] | |
f607bc57 | 7547 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7548 | "{l|lwz} %0,%a1@got(%2)" |
7549 | [(set_attr "type" "load")]) | |
7550 | ||
b22b9b3e JL |
7551 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7552 | ;; didn't get allocated to a hard register. | |
7553 | (define_split | |
75540af0 | 7554 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7555 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
75540af0 | 7556 | (match_operand:SI 2 "memory_operand" "")] 8))] |
f607bc57 | 7557 | "DEFAULT_ABI == ABI_V4 |
b22b9b3e JL |
7558 | && flag_pic == 1 |
7559 | && (reload_in_progress || reload_completed)" | |
7560 | [(set (match_dup 0) (match_dup 2)) | |
9ebbca7d | 7561 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))] |
b22b9b3e JL |
7562 | "") |
7563 | ||
1fd4e8c1 RK |
7564 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7565 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7566 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7567 | ;; integers in the TOC. | |
7568 | (define_expand "movsi" | |
7569 | [(set (match_operand:SI 0 "general_operand" "") | |
7570 | (match_operand:SI 1 "any_operand" ""))] | |
7571 | "" | |
fb4d4348 | 7572 | "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") |
1fd4e8c1 | 7573 | |
ee890fe2 SS |
7574 | (define_insn "movsi_low" |
7575 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
f585a356 | 7576 | (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
ee890fe2 SS |
7577 | (match_operand 2 "" ""))))] |
7578 | "TARGET_MACHO && ! TARGET_64BIT" | |
7579 | "{l|lwz} %0,lo16(%2)(%1)" | |
7580 | [(set_attr "type" "load") | |
7581 | (set_attr "length" "4")]) | |
7582 | ||
c859cda6 | 7583 | (define_insn "movsi_low_st" |
f585a356 | 7584 | [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
c859cda6 DJ |
7585 | (match_operand 2 "" ""))) |
7586 | (match_operand:SI 0 "gpc_reg_operand" "r"))] | |
7587 | "TARGET_MACHO && ! TARGET_64BIT" | |
7588 | "{st|stw} %0,lo16(%2)(%1)" | |
7589 | [(set_attr "type" "store") | |
7590 | (set_attr "length" "4")]) | |
7591 | ||
7592 | (define_insn "movdf_low" | |
234e114c | 7593 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") |
f585a356 | 7594 | (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 DJ |
7595 | (match_operand 2 "" ""))))] |
7596 | "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" | |
234e114c DJ |
7597 | "* |
7598 | { | |
7599 | switch (which_alternative) | |
7600 | { | |
7601 | case 0: | |
7602 | return \"lfd %0,lo16(%2)(%1)\"; | |
7603 | case 1: | |
7604 | { | |
7605 | rtx operands2[4]; | |
7606 | operands2[0] = operands[0]; | |
7607 | operands2[1] = operands[1]; | |
7608 | operands2[2] = operands[2]; | |
1db02437 | 7609 | operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
234e114c DJ |
7610 | output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands); |
7611 | /* We cannot rely on ha16(low half)==ha16(high half), alas, | |
7612 | although in practice it almost always is. */ | |
7613 | output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2); | |
7614 | return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\"); | |
7615 | } | |
7616 | default: | |
7617 | abort(); | |
7618 | } | |
7619 | }" | |
c859cda6 | 7620 | [(set_attr "type" "load") |
234e114c | 7621 | (set_attr "length" "4,12")]) |
c859cda6 DJ |
7622 | |
7623 | (define_insn "movdf_low_st" | |
f585a356 | 7624 | [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
c859cda6 DJ |
7625 | (match_operand 2 "" ""))) |
7626 | (match_operand:DF 0 "gpc_reg_operand" "f"))] | |
7627 | "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" | |
7628 | "stfd %0,lo16(%2)(%1)" | |
7629 | [(set_attr "type" "store") | |
7630 | (set_attr "length" "4")]) | |
7631 | ||
7632 | (define_insn "movsf_low" | |
fd3b43f2 | 7633 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") |
f585a356 | 7634 | (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 DJ |
7635 | (match_operand 2 "" ""))))] |
7636 | "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" | |
fd3b43f2 DJ |
7637 | "@ |
7638 | lfs %0,lo16(%2)(%1) | |
7639 | {l|lwz} %0,lo16(%2)(%1)" | |
c859cda6 DJ |
7640 | [(set_attr "type" "load") |
7641 | (set_attr "length" "4")]) | |
7642 | ||
7643 | (define_insn "movsf_low_st" | |
f585a356 | 7644 | [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 7645 | (match_operand 2 "" ""))) |
fd3b43f2 | 7646 | (match_operand:SF 0 "gpc_reg_operand" "f,!r"))] |
c859cda6 | 7647 | "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" |
fd3b43f2 DJ |
7648 | "@ |
7649 | stfs %0,lo16(%2)(%1) | |
7650 | {st|stw} %0,lo16(%2)(%1)" | |
c859cda6 DJ |
7651 | [(set_attr "type" "store") |
7652 | (set_attr "length" "4")]) | |
7653 | ||
acad7ed3 | 7654 | (define_insn "*movsi_internal1" |
a004eb82 AH |
7655 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") |
7656 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] | |
19d5775a RK |
7657 | "gpc_reg_operand (operands[0], SImode) |
7658 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7659 | "@ |
deb9225a | 7660 | mr %0,%1 |
b9442c72 | 7661 | {cal|la} %0,%a1 |
ca7f5001 RK |
7662 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7663 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7664 | {lil|li} %0,%1 |
802a0058 | 7665 | {liu|lis} %0,%v1 |
beaec479 | 7666 | # |
aee86b38 | 7667 | {cal|la} %0,%a1 |
1fd4e8c1 | 7668 | mf%1 %0 |
5c23c401 | 7669 | mt%0 %1 |
e76e75bb | 7670 | mt%0 %1 |
a004eb82 | 7671 | mt%0 %1 |
e76e75bb | 7672 | cror 0,0,0" |
a004eb82 AH |
7673 | [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*,*") |
7674 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) | |
1fd4e8c1 | 7675 | |
77fa0940 RK |
7676 | ;; Split a load of a large constant into the appropriate two-insn |
7677 | ;; sequence. | |
7678 | ||
7679 | (define_split | |
7680 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7681 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7682 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7683 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7684 | [(set (match_dup 0) | |
7685 | (match_dup 2)) | |
7686 | (set (match_dup 0) | |
7687 | (ior:SI (match_dup 0) | |
7688 | (match_dup 3)))] | |
7689 | " | |
7690 | { | |
5f59ecb7 | 7691 | operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); |
89e9f3a8 | 7692 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); |
77fa0940 RK |
7693 | }") |
7694 | ||
acad7ed3 | 7695 | (define_insn "*movsi_internal2" |
9ebbca7d GK |
7696 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
7697 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 7698 | (const_int 0))) |
9ebbca7d | 7699 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
0ad91047 | 7700 | "! TARGET_POWERPC64" |
9ebbca7d GK |
7701 | "@ |
7702 | mr. %0,%1 | |
7703 | #" | |
7704 | [(set_attr "type" "compare") | |
7705 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 7706 | \f |
9ebbca7d GK |
7707 | (define_split |
7708 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
7709 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
7710 | (const_int 0))) | |
7711 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
7712 | "! TARGET_POWERPC64 && reload_completed" | |
7713 | [(set (match_dup 0) (match_dup 1)) | |
7714 | (set (match_dup 2) | |
7715 | (compare:CC (match_dup 0) | |
7716 | (const_int 0)))] | |
7717 | "") | |
7718 | ||
1fd4e8c1 RK |
7719 | (define_expand "movhi" |
7720 | [(set (match_operand:HI 0 "general_operand" "") | |
7721 | (match_operand:HI 1 "any_operand" ""))] | |
7722 | "" | |
fb4d4348 | 7723 | "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") |
1fd4e8c1 RK |
7724 | |
7725 | (define_insn "" | |
fb81d7ce RK |
7726 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7727 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7728 | "gpc_reg_operand (operands[0], HImode) |
7729 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7730 | "@ |
deb9225a | 7731 | mr %0,%1 |
1fd4e8c1 RK |
7732 | lhz%U1%X1 %0,%1 |
7733 | sth%U0%X0 %1,%0 | |
19d5775a | 7734 | {lil|li} %0,%w1 |
1fd4e8c1 | 7735 | mf%1 %0 |
e76e75bb | 7736 | mt%0 %1 |
fb81d7ce | 7737 | mt%0 %1 |
e76e75bb | 7738 | cror 0,0,0" |
b7ff3d82 | 7739 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7740 | |
7741 | (define_expand "movqi" | |
7742 | [(set (match_operand:QI 0 "general_operand" "") | |
7743 | (match_operand:QI 1 "any_operand" ""))] | |
7744 | "" | |
fb4d4348 | 7745 | "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") |
1fd4e8c1 RK |
7746 | |
7747 | (define_insn "" | |
fb81d7ce RK |
7748 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7749 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7750 | "gpc_reg_operand (operands[0], QImode) |
7751 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7752 | "@ |
deb9225a | 7753 | mr %0,%1 |
1fd4e8c1 RK |
7754 | lbz%U1%X1 %0,%1 |
7755 | stb%U0%X0 %1,%0 | |
19d5775a | 7756 | {lil|li} %0,%1 |
1fd4e8c1 | 7757 | mf%1 %0 |
e76e75bb | 7758 | mt%0 %1 |
fb81d7ce | 7759 | mt%0 %1 |
e76e75bb | 7760 | cror 0,0,0" |
b7ff3d82 | 7761 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7762 | \f |
7763 | ;; Here is how to move condition codes around. When we store CC data in | |
7764 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7765 | ;; This lets us not shift in the most common case of CR0. | |
7766 | (define_expand "movcc" | |
7767 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7768 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7769 | "" | |
7770 | "") | |
7771 | ||
a65c591c | 7772 | (define_insn "*movcc_internal1" |
1fd4e8c1 RK |
7773 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") |
7774 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] | |
7775 | "register_operand (operands[0], CCmode) | |
7776 | || register_operand (operands[1], CCmode)" | |
7777 | "@ | |
7778 | mcrf %0,%1 | |
7779 | mtcrf 128,%1 | |
ca7f5001 | 7780 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
1fd4e8c1 | 7781 | mfcr %0 |
ca7f5001 | 7782 | mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 |
deb9225a | 7783 | mr %0,%1 |
ca7f5001 RK |
7784 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7785 | {st%U0%U1|stw%U0%U1} %1,%0" | |
b7ff3d82 | 7786 | [(set_attr "type" "*,*,*,compare,*,*,load,store") |
b19003d8 | 7787 | (set_attr "length" "*,*,12,*,8,*,*,*")]) |
1fd4e8c1 | 7788 | \f |
e52e05ca MM |
7789 | ;; For floating-point, we normally deal with the floating-point registers |
7790 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7791 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7792 | ;; value is a simple constant or already in memory, we deal with this by | |
7793 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7794 | (define_expand "movsf" |
7795 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7796 | (match_operand:SF 1 "any_operand" ""))] | |
7797 | "" | |
fb4d4348 | 7798 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 7799 | |
1fd4e8c1 | 7800 | (define_split |
cd2b37d9 | 7801 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7802 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7803 | "reload_completed |
5ae4759c MM |
7804 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7805 | || (GET_CODE (operands[0]) == SUBREG | |
7806 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7807 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7808 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7809 | " |
7810 | { | |
7811 | long l; | |
7812 | REAL_VALUE_TYPE rv; | |
7813 | ||
7814 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7815 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7816 | |
f99f88e0 DE |
7817 | if (! TARGET_POWERPC64) |
7818 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7819 | else | |
7820 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7821 | |
2496c7bd | 7822 | operands[3] = gen_int_mode (l, SImode); |
a260abc9 DE |
7823 | }") |
7824 | ||
c4c40373 | 7825 | (define_insn "*movsf_hardfloat" |
f99f88e0 DE |
7826 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r") |
7827 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))] | |
d14a6d05 MM |
7828 | "(gpc_reg_operand (operands[0], SFmode) |
7829 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT" | |
1fd4e8c1 | 7830 | "@ |
f99f88e0 DE |
7831 | mr %0,%1 |
7832 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7833 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7834 | fmr %0,%1 |
7835 | lfs%U1%X1 %0,%1 | |
c4c40373 MM |
7836 | stfs%U0%X0 %1,%0 |
7837 | # | |
7838 | #" | |
f99f88e0 DE |
7839 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*") |
7840 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7841 | |
c4c40373 MM |
7842 | (define_insn "*movsf_softfloat" |
7843 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r") | |
9615f239 | 7844 | (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))] |
d14a6d05 MM |
7845 | "(gpc_reg_operand (operands[0], SFmode) |
7846 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT" | |
7847 | "@ | |
7848 | mr %0,%1 | |
7849 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7850 | {st%U0%X0|stw%U0%X0} %1,%0 | |
7851 | {lil|li} %0,%1 | |
802a0058 | 7852 | {liu|lis} %0,%v1 |
aee86b38 | 7853 | {cal|la} %0,%a1 |
c4c40373 MM |
7854 | # |
7855 | #" | |
7856 | [(set_attr "type" "*,load,store,*,*,*,*,*") | |
7857 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7858 | |
1fd4e8c1 RK |
7859 | \f |
7860 | (define_expand "movdf" | |
7861 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
7862 | (match_operand:DF 1 "any_operand" ""))] | |
7863 | "" | |
fb4d4348 | 7864 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
7865 | |
7866 | (define_split | |
cd2b37d9 | 7867 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 7868 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 7869 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7870 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7871 | || (GET_CODE (operands[0]) == SUBREG | |
7872 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7873 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7874 | [(set (match_dup 2) (match_dup 4)) |
7875 | (set (match_dup 3) (match_dup 1))] | |
7876 | " | |
7877 | { | |
5ae4759c | 7878 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
7879 | HOST_WIDE_INT value = INTVAL (operands[1]); |
7880 | ||
5ae4759c MM |
7881 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7882 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
7883 | #if HOST_BITS_PER_WIDE_INT == 32 |
7884 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
7885 | #else | |
7886 | operands[4] = GEN_INT (value >> 32); | |
a65c591c | 7887 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
5f59ecb7 | 7888 | #endif |
c4c40373 MM |
7889 | }") |
7890 | ||
c4c40373 MM |
7891 | (define_split |
7892 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
7893 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 7894 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7895 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7896 | || (GET_CODE (operands[0]) == SUBREG | |
7897 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7898 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7899 | [(set (match_dup 2) (match_dup 4)) |
7900 | (set (match_dup 3) (match_dup 5))] | |
7901 | " | |
7902 | { | |
5ae4759c | 7903 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
7904 | long l[2]; |
7905 | REAL_VALUE_TYPE rv; | |
7906 | ||
7907 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7908 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7909 | ||
5ae4759c MM |
7910 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7911 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
2496c7bd LB |
7912 | operands[4] = gen_int_mode (l[endian], SImode); |
7913 | operands[5] = gen_int_mode (l[1 - endian], SImode); | |
c4c40373 MM |
7914 | }") |
7915 | ||
efc08378 DE |
7916 | (define_split |
7917 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 7918 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 7919 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7920 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7921 | || (GET_CODE (operands[0]) == SUBREG | |
7922 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7923 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 7924 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 7925 | " |
a260abc9 DE |
7926 | { |
7927 | int endian = (WORDS_BIG_ENDIAN == 0); | |
7928 | long l[2]; | |
7929 | REAL_VALUE_TYPE rv; | |
5b029315 | 7930 | HOST_WIDE_INT val; |
a260abc9 DE |
7931 | |
7932 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7933 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7934 | ||
7935 | operands[2] = gen_lowpart (DImode, operands[0]); | |
7936 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
5b029315 TR |
7937 | #if HOST_BITS_PER_WIDE_INT >= 64 |
7938 | val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 | | |
7939 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); | |
7940 | ||
7941 | operands[3] = immed_double_const (val, -(val < 0), DImode); | |
7942 | #else | |
a260abc9 | 7943 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); |
5b029315 | 7944 | #endif |
a260abc9 | 7945 | }") |
efc08378 | 7946 | |
4eae5fe1 | 7947 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 7948 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
7949 | ;; a non-offsettable memref, but also it is less efficient than loading |
7950 | ;; the constant into an FP register, since it will probably be used there. | |
7951 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
7952 | ;; of handling these non-offsettable values. | |
c4c40373 | 7953 | (define_insn "*movdf_hardfloat32" |
000034eb DE |
7954 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
7955 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 7956 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
7957 | && (gpc_reg_operand (operands[0], DFmode) |
7958 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
7959 | "* |
7960 | { | |
7961 | switch (which_alternative) | |
7962 | { | |
a260abc9 | 7963 | default: |
a6c2a102 | 7964 | abort (); |
e7113111 RK |
7965 | case 0: |
7966 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
7967 | the first register operand 0 is the same as the second register |
7968 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 7969 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 7970 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 7971 | else |
deb9225a | 7972 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 7973 | case 1: |
2b97222d DE |
7974 | if (offsettable_memref_p (operands[1]) |
7975 | || (GET_CODE (operands[1]) == MEM | |
69f51a21 DE |
7976 | && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM |
7977 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC | |
7978 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))) | |
000034eb DE |
7979 | { |
7980 | /* If the low-address word is used in the address, we must load | |
7981 | it last. Otherwise, load it first. Note that we cannot have | |
7982 | auto-increment in that case since the address register is | |
7983 | known to be dead. */ | |
7984 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
7985 | operands[1], 0)) | |
7986 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
7987 | else | |
7988 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7989 | } | |
e7113111 | 7990 | else |
000034eb DE |
7991 | { |
7992 | rtx addreg; | |
7993 | ||
000034eb DE |
7994 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
7995 | if (refers_to_regno_p (REGNO (operands[0]), | |
7996 | REGNO (operands[0]) + 1, | |
7997 | operands[1], 0)) | |
7998 | { | |
7999 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 8000 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 8001 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 8002 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
8003 | } |
8004 | else | |
8005 | { | |
2b97222d | 8006 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 8007 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8008 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
8009 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8010 | return \"\"; | |
8011 | } | |
8012 | } | |
e7113111 | 8013 | case 2: |
2b97222d DE |
8014 | if (offsettable_memref_p (operands[0]) |
8015 | || (GET_CODE (operands[0]) == MEM | |
69f51a21 DE |
8016 | && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM |
8017 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC | |
8018 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))) | |
000034eb DE |
8019 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8020 | else | |
8021 | { | |
8022 | rtx addreg; | |
8023 | ||
000034eb | 8024 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 8025 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 8026 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8027 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
8028 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8029 | return \"\"; | |
8030 | } | |
e7113111 | 8031 | case 3: |
e7113111 | 8032 | case 4: |
e7113111 | 8033 | case 5: |
c4c40373 | 8034 | return \"#\"; |
e7113111 | 8035 | case 6: |
c4c40373 MM |
8036 | return \"fmr %0,%1\"; |
8037 | case 7: | |
8038 | return \"lfd%U1%X1 %0,%1\"; | |
8039 | case 8: | |
e7113111 RK |
8040 | return \"stfd%U0%X0 %1,%0\"; |
8041 | } | |
8042 | }" | |
c4c40373 | 8043 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
2f76d42c | 8044 | (set_attr "length" "8,16,16,8,12,16,*,*,*")]) |
51b8fc2c | 8045 | |
c4c40373 | 8046 | (define_insn "*movdf_softfloat32" |
1427100a DE |
8047 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
8048 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 8049 | "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
8050 | && (gpc_reg_operand (operands[0], DFmode) |
8051 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8052 | "* |
8053 | { | |
8054 | switch (which_alternative) | |
8055 | { | |
a260abc9 | 8056 | default: |
a6c2a102 | 8057 | abort (); |
dc4f83ca MM |
8058 | case 0: |
8059 | /* We normally copy the low-numbered register first. However, if | |
8060 | the first register operand 0 is the same as the second register of | |
8061 | operand 1, we must copy in the opposite order. */ | |
8062 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8063 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8064 | else | |
8065 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8066 | case 1: | |
3cb999d8 DE |
8067 | /* If the low-address word is used in the address, we must load |
8068 | it last. Otherwise, load it first. Note that we cannot have | |
8069 | auto-increment in that case since the address register is | |
8070 | known to be dead. */ | |
dc4f83ca | 8071 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 8072 | operands[1], 0)) |
dc4f83ca MM |
8073 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
8074 | else | |
8075 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8076 | case 2: | |
8077 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
8078 | case 3: | |
c4c40373 MM |
8079 | case 4: |
8080 | case 5: | |
dc4f83ca MM |
8081 | return \"#\"; |
8082 | } | |
8083 | }" | |
c4c40373 MM |
8084 | [(set_attr "type" "*,load,store,*,*,*") |
8085 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 8086 | |
c4c40373 | 8087 | (define_insn "*movdf_hardfloat64" |
1427100a DE |
8088 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
8089 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 8090 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
8091 | && (gpc_reg_operand (operands[0], DFmode) |
8092 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 8093 | "@ |
3d5570cb RK |
8094 | mr %0,%1 |
8095 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8096 | std%U0%X0 %1,%0 |
3d5570cb | 8097 | # |
c4c40373 MM |
8098 | # |
8099 | # | |
3d5570cb | 8100 | fmr %0,%1 |
f63184ac | 8101 | lfd%U1%X1 %0,%1 |
3d5570cb | 8102 | stfd%U0%X0 %1,%0" |
c4c40373 MM |
8103 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
8104 | (set_attr "length" "4,4,4,8,12,16,4,4,4")]) | |
dc4f83ca | 8105 | |
c4c40373 | 8106 | (define_insn "*movdf_softfloat64" |
1427100a DE |
8107 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
8108 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 8109 | "TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
8110 | && (gpc_reg_operand (operands[0], DFmode) |
8111 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8112 | "@ |
8113 | mr %0,%1 | |
8114 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8115 | std%U0%X0 %1,%0 |
c4c40373 MM |
8116 | # |
8117 | # | |
dc4f83ca | 8118 | #" |
c4c40373 MM |
8119 | [(set_attr "type" "*,load,store,*,*,*") |
8120 | (set_attr "length" "*,*,*,8,12,16")]) | |
1fd4e8c1 | 8121 | \f |
06f4e019 DE |
8122 | (define_expand "movtf" |
8123 | [(set (match_operand:TF 0 "general_operand" "") | |
8124 | (match_operand:TF 1 "any_operand" ""))] | |
8125 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8126 | "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") | |
8127 | ||
8128 | (define_insn "*movtf_internal" | |
8129 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,m,!r,!r,!r") | |
8130 | (match_operand:TF 1 "input_operand" "f,m,f,G,H,F"))] | |
8131 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128 | |
8132 | && (gpc_reg_operand (operands[0], TFmode) | |
8133 | || gpc_reg_operand (operands[1], TFmode))" | |
8134 | "* | |
8135 | { | |
8136 | switch (which_alternative) | |
8137 | { | |
8138 | default: | |
8139 | abort (); | |
8140 | case 0: | |
8141 | /* We normally copy the low-numbered register first. However, if | |
8142 | the first register operand 0 is the same as the second register of | |
8143 | operand 1, we must copy in the opposite order. */ | |
8144 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8145 | return \"fmr %L0,%L1\;fmr %0,%1\"; | |
8146 | else | |
8147 | return \"fmr %0,%1\;fmr %L0,%L1\"; | |
8148 | case 1: | |
8149 | return \"lfd %0,%1\;lfd %L0,%L1\"; | |
8150 | case 2: | |
8151 | return \"stfd %1,%0\;stfd %L1,%L0\"; | |
8152 | case 3: | |
8153 | case 4: | |
8154 | case 5: | |
8155 | return \"#\"; | |
8156 | } | |
8157 | }" | |
8158 | [(set_attr "type" "fp,fpload,fpstore,*,*,*") | |
8159 | (set_attr "length" "8,8,8,12,16,20")]) | |
8160 | ||
8161 | (define_split | |
8162 | [(set (match_operand:TF 0 "gpc_reg_operand" "") | |
8163 | (match_operand:TF 1 "const_double_operand" ""))] | |
8164 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8165 | [(set (match_dup 3) (match_dup 1)) | |
8166 | (set (match_dup 0) | |
8167 | (float_extend:TF (match_dup 3)))] | |
8168 | " | |
8169 | { | |
8170 | operands[2] = operand_subword (operands[1], 0, 0, DFmode); | |
8171 | operands[3] = gen_reg_rtx (DFmode); | |
8172 | }") | |
8173 | ||
8174 | (define_insn_and_split "extenddftf2" | |
8175 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8176 | (float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
8177 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8178 | "#" | |
8179 | "" | |
8180 | [(set (match_dup 2) (match_dup 3))] | |
8181 | " | |
8182 | { | |
8183 | operands[2] = gen_rtx_REG (DFmode, REGNO (operands[0] + 1)); | |
8184 | operands[3] = CONST0_RTX (DFmode); | |
8185 | }") | |
8186 | ||
8187 | (define_insn_and_split "extendsftf2" | |
8188 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8189 | (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
8190 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8191 | "#" | |
8192 | "" | |
8193 | [(set (match_dup 2) (match_dup 3))] | |
8194 | " | |
8195 | { | |
8196 | operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0] + 1)); | |
8197 | operands[3] = CONST0_RTX (SFmode); | |
8198 | }") | |
8199 | ||
8200 | (define_insn "trunctfdf2" | |
8201 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8202 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
8203 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8204 | "fadd %0,%1,%L1" | |
8205 | [(set_attr "type" "fp") | |
8206 | (set_attr "length" "8")]) | |
8207 | ||
8208 | (define_insn_and_split "trunctfsf2" | |
8209 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
8210 | (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
8211 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8212 | "#" | |
8213 | "" | |
8214 | [(set (match_dup 2) | |
8215 | (float_truncate:DF (match_dup 1))) | |
8216 | (set (match_dup 0) | |
8217 | (float_truncate:SF (match_dup 2)))] | |
8218 | " | |
8219 | { | |
8220 | operands[2] = gen_reg_rtx (DFmode); | |
8221 | }") | |
8222 | ||
8223 | (define_expand "floatditf2" | |
8224 | [(set (match_dup 2) | |
8225 | (float:DF (match_operand:DI 1 "gpc_reg_operand" ""))) | |
8226 | (set (match_operand:TF 0 "gpc_reg_operand" "") | |
8227 | (float_extend:TF (match_dup 2)))] | |
8228 | "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 | |
8229 | && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8230 | "{ operands[2] = gen_reg_rtx (DFmode); }") | |
8231 | ||
8232 | (define_expand "floatsitf2" | |
8233 | [(set (match_dup 2) | |
8234 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
8235 | (set (match_operand:TF 0 "gpc_reg_operand" "") | |
8236 | (float_extend:TF (match_dup 2)))] | |
8237 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8238 | "{ operands[2] = gen_reg_rtx (DFmode); }") | |
8239 | ||
8240 | (define_expand "fix_trunctfdi2" | |
8241 | [(set (match_dup 2) | |
8242 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" ""))) | |
8243 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
8244 | (fix:SI (match_dup 2)))] | |
8245 | "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 | |
8246 | && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8247 | "{ operands[2] = gen_reg_rtx (DFmode); }") | |
8248 | ||
8249 | (define_expand "fix_trunctfsi2" | |
8250 | [(set (match_dup 2) | |
8251 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" ""))) | |
8252 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
8253 | (fix:SI (match_dup 2)))] | |
8254 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8255 | "{ operands[2] = gen_reg_rtx (DFmode); }") | |
8256 | ||
8257 | (define_insn "negtf2" | |
8258 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8259 | (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
8260 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8261 | "* | |
8262 | { | |
8263 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8264 | return \"fneg %L0,%L1\;fneg %0,%1\"; | |
8265 | else | |
8266 | return \"fneg %0,%1\;fneg %L0,%L1\"; | |
8267 | }" | |
8268 | [(set_attr "type" "fp") | |
8269 | (set_attr "length" "8")]) | |
8270 | ||
8271 | (define_insn "abstf2" | |
8272 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8273 | (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
8274 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8275 | "* | |
8276 | { | |
8277 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8278 | return \"fabs %L0,%L1\;fabs %0,%1\"; | |
8279 | else | |
8280 | return \"fabs %0,%1\;fabs %L0,%L1\"; | |
8281 | }" | |
8282 | [(set_attr "type" "fp") | |
8283 | (set_attr "length" "8")]) | |
8284 | ||
8285 | (define_insn "" | |
8286 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8287 | (neg:TF (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f"))))] | |
8288 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8289 | "* | |
8290 | { | |
8291 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8292 | return \"fnabs %L0,%L1\;fnabs %0,%1\"; | |
8293 | else | |
8294 | return \"fnabs %0,%1\;fnabs %L0,%L1\"; | |
8295 | }" | |
8296 | [(set_attr "type" "fp") | |
8297 | (set_attr "length" "8")]) | |
8298 | \f | |
1fd4e8c1 RK |
8299 | ;; Next come the multi-word integer load and store and the load and store |
8300 | ;; multiple insns. | |
8301 | (define_expand "movdi" | |
8302 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 8303 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 | 8304 | "" |
fb4d4348 | 8305 | "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") |
1fd4e8c1 | 8306 | |
acad7ed3 | 8307 | (define_insn "*movdi_internal32" |
4e74d8ec MM |
8308 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") |
8309 | (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] | |
a260abc9 | 8310 | "! TARGET_POWERPC64 |
4e74d8ec MM |
8311 | && (gpc_reg_operand (operands[0], DImode) |
8312 | || gpc_reg_operand (operands[1], DImode))" | |
1fd4e8c1 RK |
8313 | "* |
8314 | { | |
8315 | switch (which_alternative) | |
8316 | { | |
a260abc9 | 8317 | default: |
a6c2a102 | 8318 | abort (); |
1fd4e8c1 RK |
8319 | case 0: |
8320 | /* We normally copy the low-numbered register first. However, if | |
8321 | the first register operand 0 is the same as the second register of | |
8322 | operand 1, we must copy in the opposite order. */ | |
8323 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 8324 | return \"mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 8325 | else |
deb9225a | 8326 | return \"mr %0,%1\;mr %L0,%L1\"; |
1fd4e8c1 RK |
8327 | case 1: |
8328 | /* If the low-address word is used in the address, we must load it | |
8329 | last. Otherwise, load it first. Note that we cannot have | |
8330 | auto-increment in that case since the address register is known to be | |
8331 | dead. */ | |
8332 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 8333 | operands[1], 0)) |
ca7f5001 | 8334 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
1fd4e8c1 | 8335 | else |
ca7f5001 | 8336 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 | 8337 | case 2: |
ca7f5001 | 8338 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8ffd9c51 RK |
8339 | case 3: |
8340 | return \"fmr %0,%1\"; | |
8341 | case 4: | |
8342 | return \"lfd%U1%X1 %0,%1\"; | |
8343 | case 5: | |
8344 | return \"stfd%U0%X0 %1,%0\"; | |
4e74d8ec MM |
8345 | case 6: |
8346 | case 7: | |
8347 | case 8: | |
8348 | case 9: | |
8349 | case 10: | |
8350 | return \"#\"; | |
1fd4e8c1 RK |
8351 | } |
8352 | }" | |
4e74d8ec MM |
8353 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*") |
8354 | (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")]) | |
8355 | ||
8356 | (define_split | |
8357 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8358 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 8359 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8360 | [(set (match_dup 2) (match_dup 4)) |
8361 | (set (match_dup 3) (match_dup 1))] | |
8362 | " | |
8363 | { | |
5f59ecb7 | 8364 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
8365 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8366 | DImode); | |
8367 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8368 | DImode); | |
75d39459 | 8369 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 8370 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 8371 | #else |
5f59ecb7 | 8372 | operands[4] = GEN_INT (value >> 32); |
a65c591c | 8373 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
75d39459 | 8374 | #endif |
4e74d8ec MM |
8375 | }") |
8376 | ||
4e74d8ec MM |
8377 | (define_split |
8378 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8379 | (match_operand:DI 1 "const_double_operand" ""))] | |
75d39459 | 8380 | "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8381 | [(set (match_dup 2) (match_dup 4)) |
8382 | (set (match_dup 3) (match_dup 5))] | |
8383 | " | |
8384 | { | |
bdaa0181 GK |
8385 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8386 | DImode); | |
8387 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8388 | DImode); | |
f6968f59 MM |
8389 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
8390 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
4e74d8ec MM |
8391 | }") |
8392 | ||
acad7ed3 | 8393 | (define_insn "*movdi_internal64" |
e6ca2c17 | 8394 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h") |
9615f239 | 8395 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 8396 | "TARGET_POWERPC64 |
4e74d8ec MM |
8397 | && (gpc_reg_operand (operands[0], DImode) |
8398 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 8399 | "@ |
3d5570cb RK |
8400 | mr %0,%1 |
8401 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8402 | std%U0%X0 %1,%0 |
3d5570cb | 8403 | li %0,%1 |
802a0058 | 8404 | lis %0,%v1 |
e6ca2c17 | 8405 | # |
aee86b38 | 8406 | {cal|la} %0,%a1 |
3d5570cb RK |
8407 | fmr %0,%1 |
8408 | lfd%U1%X1 %0,%1 | |
8409 | stfd%U0%X0 %1,%0 | |
8410 | mf%1 %0 | |
08075ead DE |
8411 | mt%0 %1 |
8412 | cror 0,0,0" | |
b7ff3d82 | 8413 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*") |
e6ca2c17 DE |
8414 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
8415 | ||
5f59ecb7 | 8416 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
8417 | (define_insn "" |
8418 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8419 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
8420 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8421 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
8422 | && num_insns_constant (operands[1], DImode) == 1" |
8423 | "* | |
8424 | { | |
8425 | return ((unsigned HOST_WIDE_INT) | |
8426 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
8427 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
8428 | }") | |
8429 | ||
a260abc9 DE |
8430 | ;; Generate all one-bits and clear left or right. |
8431 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8432 | (define_split | |
8433 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8434 | (match_operand:DI 1 "mask64_operand" ""))] | |
8435 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8436 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8437 | (set (match_dup 0) |
a260abc9 DE |
8438 | (and:DI (rotate:DI (match_dup 0) |
8439 | (const_int 0)) | |
8440 | (match_dup 1)))] | |
8441 | "") | |
8442 | ||
8443 | ;; Split a load of a large constant into the appropriate five-instruction | |
8444 | ;; sequence. Handle anything in a constant number of insns. | |
8445 | ;; When non-easy constants can go in the TOC, this should use | |
8446 | ;; easy_fp_constant predicate. | |
8447 | (define_split | |
8448 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8449 | (match_operand:DI 1 "const_int_operand" ""))] |
8450 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8451 | [(set (match_dup 0) (match_dup 2)) | |
8452 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
e6ca2c17 | 8453 | " |
2bfcf297 DB |
8454 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8455 | ||
8456 | if (tem == operands[0]) | |
8457 | DONE; | |
e8d791dd | 8458 | else |
2bfcf297 | 8459 | FAIL; |
5f59ecb7 | 8460 | }") |
e6ca2c17 | 8461 | |
5f59ecb7 DE |
8462 | (define_split |
8463 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8464 | (match_operand:DI 1 "const_double_operand" ""))] |
8465 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8466 | [(set (match_dup 0) (match_dup 2)) | |
8467 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
5f59ecb7 | 8468 | " |
2bfcf297 DB |
8469 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8470 | ||
8471 | if (tem == operands[0]) | |
8472 | DONE; | |
8473 | else | |
8474 | FAIL; | |
e6ca2c17 | 8475 | }") |
08075ead | 8476 | |
2bfcf297 | 8477 | ;; Split a load of a large constant into the appropriate five-instruction |
acad7ed3 | 8478 | (define_insn "*movdi_internal2" |
9ebbca7d GK |
8479 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
8480 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
08075ead | 8481 | (const_int 0))) |
9ebbca7d | 8482 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
08075ead | 8483 | "TARGET_POWERPC64" |
9ebbca7d GK |
8484 | "@ |
8485 | mr. %0,%1 | |
8486 | #" | |
8487 | [(set_attr "type" "compare") | |
8488 | (set_attr "length" "4,8")]) | |
acad7ed3 | 8489 | |
9ebbca7d GK |
8490 | (define_split |
8491 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8492 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
8493 | (const_int 0))) | |
8494 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8495 | "TARGET_POWERPC64 && reload_completed" | |
8496 | [(set (match_dup 0) (match_dup 1)) | |
8497 | (set (match_dup 2) | |
8498 | (compare:CC (match_dup 0) | |
8499 | (const_int 0)))] | |
8500 | "") | |
acad7ed3 | 8501 | \f |
1fd4e8c1 RK |
8502 | ;; TImode is similar, except that we usually want to compute the address into |
8503 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8504 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8505 | (define_expand "movti" |
8506 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
8507 | (match_operand:TI 1 "general_operand" "")) | |
8508 | (clobber (scratch:SI))])] | |
7e69e155 | 8509 | "TARGET_STRING || TARGET_POWERPC64" |
fb4d4348 | 8510 | "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") |
1fd4e8c1 RK |
8511 | |
8512 | ;; We say that MQ is clobbered in the last alternative because the first | |
8513 | ;; alternative would never get used otherwise since it would need a reload | |
8514 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8515 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8516 | ;; giving the SCRATCH mq. | |
a260abc9 | 8517 | (define_insn "*movti_power" |
e1469d0d | 8518 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
8519 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
8520 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
7e69e155 | 8521 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8522 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8523 | "* |
8524 | { | |
8525 | switch (which_alternative) | |
8526 | { | |
dc4f83ca MM |
8527 | default: |
8528 | abort (); | |
8529 | ||
1fd4e8c1 | 8530 | case 0: |
ca7f5001 | 8531 | return \"{stsi|stswi} %1,%P0,16\"; |
1fd4e8c1 RK |
8532 | |
8533 | case 1: | |
ca7f5001 | 8534 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
1fd4e8c1 RK |
8535 | |
8536 | case 2: | |
8537 | /* Normally copy registers with lowest numbered register copied first. | |
8538 | But copy in the other order if the first register of the output | |
8539 | is the second, third, or fourth register in the input. */ | |
8540 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8541 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
deb9225a | 8542 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 8543 | else |
deb9225a | 8544 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; |
1fd4e8c1 RK |
8545 | case 3: |
8546 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8547 | fall through to generating four loads. */ | |
8548 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8549 | return \"{lsi|lswi} %0,%P1,16\"; |
82e41834 | 8550 | /* ... fall through ... */ |
1fd4e8c1 RK |
8551 | case 4: |
8552 | /* If the address register is the same as the register for the lowest- | |
8553 | addressed word, load it last. Similarly for the next two words. | |
8554 | Otherwise load lowest address to highest. */ | |
8555 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8556 | operands[1], 0)) | |
ca7f5001 | 8557 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; |
1fd4e8c1 RK |
8558 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, |
8559 | REGNO (operands[0]) + 2, operands[1], 0)) | |
ca7f5001 | 8560 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 RK |
8561 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, |
8562 | REGNO (operands[0]) + 3, operands[1], 0)) | |
ca7f5001 | 8563 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; |
1fd4e8c1 | 8564 | else |
ca7f5001 | 8565 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; |
1fd4e8c1 RK |
8566 | } |
8567 | }" | |
b7ff3d82 | 8568 | [(set_attr "type" "store,store,*,load,load") |
b19003d8 | 8569 | (set_attr "length" "*,16,16,*,16")]) |
51b8fc2c | 8570 | |
a260abc9 | 8571 | (define_insn "*movti_string" |
dc4f83ca MM |
8572 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r") |
8573 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,m")) | |
8574 | (clobber (match_scratch:SI 2 "=X,X,X"))] | |
0ad91047 | 8575 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8576 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8577 | "* | |
8578 | { | |
8579 | switch (which_alternative) | |
8580 | { | |
8581 | default: | |
8582 | abort (); | |
8583 | ||
8584 | case 0: | |
8585 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; | |
8586 | ||
8587 | case 1: | |
8588 | /* Normally copy registers with lowest numbered register copied first. | |
8589 | But copy in the other order if the first register of the output | |
8590 | is the second, third, or fourth register in the input. */ | |
8591 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8592 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
8593 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; | |
8594 | else | |
8595 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; | |
8596 | case 2: | |
8597 | /* If the address register is the same as the register for the lowest- | |
8598 | addressed word, load it last. Similarly for the next two words. | |
8599 | Otherwise load lowest address to highest. */ | |
8600 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8601 | operands[1], 0)) | |
8602 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; | |
8603 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, | |
8604 | REGNO (operands[0]) + 2, operands[1], 0)) | |
8605 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; | |
8606 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, | |
8607 | REGNO (operands[0]) + 3, operands[1], 0)) | |
8608 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; | |
8609 | else | |
8610 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; | |
8611 | } | |
8612 | }" | |
b7ff3d82 | 8613 | [(set_attr "type" "store,*,load") |
dc4f83ca MM |
8614 | (set_attr "length" "16,16,16")]) |
8615 | ||
a260abc9 | 8616 | (define_insn "*movti_ppc64" |
51b8fc2c RK |
8617 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") |
8618 | (match_operand:TI 1 "input_operand" "r,m,r"))] | |
8619 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) | |
8620 | || gpc_reg_operand (operands[1], TImode))" | |
8621 | "* | |
8622 | { | |
8623 | switch (which_alternative) | |
8624 | { | |
a260abc9 | 8625 | default: |
a6c2a102 | 8626 | abort (); |
51b8fc2c RK |
8627 | case 0: |
8628 | /* We normally copy the low-numbered register first. However, if | |
8629 | the first register operand 0 is the same as the second register of | |
8630 | operand 1, we must copy in the opposite order. */ | |
8631 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8632 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8633 | else | |
8634 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8635 | case 1: | |
8636 | /* If the low-address word is used in the address, we must load it | |
8637 | last. Otherwise, load it first. Note that we cannot have | |
8638 | auto-increment in that case since the address register is known to be | |
8639 | dead. */ | |
8640 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 8641 | operands[1], 0)) |
51b8fc2c RK |
8642 | return \"ld %L0,%L1\;ld %0,%1\"; |
8643 | else | |
8644 | return \"ld%U1 %0,%1\;ld %L0,%L1\"; | |
8645 | case 2: | |
8646 | return \"std%U0 %1,%0\;std %L1,%L0\"; | |
8647 | } | |
8648 | }" | |
b7ff3d82 | 8649 | [(set_attr "type" "*,load,store") |
51b8fc2c | 8650 | (set_attr "length" "8,8,8")]) |
1fd4e8c1 RK |
8651 | \f |
8652 | (define_expand "load_multiple" | |
2f622005 RK |
8653 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8654 | (match_operand:SI 1 "" "")) | |
8655 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8656 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8657 | " |
8658 | { | |
8659 | int regno; | |
8660 | int count; | |
792760b9 | 8661 | rtx op1; |
1fd4e8c1 RK |
8662 | int i; |
8663 | ||
8664 | /* Support only loading a constant number of fixed-point registers from | |
8665 | memory and only bother with this if more than two; the machine | |
8666 | doesn't support more than eight. */ | |
8667 | if (GET_CODE (operands[2]) != CONST_INT | |
8668 | || INTVAL (operands[2]) <= 2 | |
8669 | || INTVAL (operands[2]) > 8 | |
8670 | || GET_CODE (operands[1]) != MEM | |
8671 | || GET_CODE (operands[0]) != REG | |
8672 | || REGNO (operands[0]) >= 32) | |
8673 | FAIL; | |
8674 | ||
8675 | count = INTVAL (operands[2]); | |
8676 | regno = REGNO (operands[0]); | |
8677 | ||
39403d82 | 8678 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
8679 | op1 = replace_equiv_address (operands[1], |
8680 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
8681 | |
8682 | for (i = 0; i < count; i++) | |
8683 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8684 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
792760b9 | 8685 | adjust_address (op1, SImode, i * 4)); |
1fd4e8c1 RK |
8686 | }") |
8687 | ||
8688 | (define_insn "" | |
8689 | [(match_parallel 0 "load_multiple_operation" | |
cd2b37d9 | 8690 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") |
52d3af72 | 8691 | (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])] |
7e69e155 | 8692 | "TARGET_STRING" |
1fd4e8c1 RK |
8693 | "* |
8694 | { | |
8695 | /* We have to handle the case where the pseudo used to contain the address | |
e82ee4cc RK |
8696 | is assigned to one of the output registers. */ |
8697 | int i, j; | |
8698 | int words = XVECLEN (operands[0], 0); | |
8699 | rtx xop[10]; | |
8700 | ||
8701 | if (XVECLEN (operands[0], 0) == 1) | |
8702 | return \"{l|lwz} %1,0(%2)\"; | |
1fd4e8c1 | 8703 | |
e82ee4cc | 8704 | for (i = 0; i < words; i++) |
1fd4e8c1 RK |
8705 | if (refers_to_regno_p (REGNO (operands[1]) + i, |
8706 | REGNO (operands[1]) + i + 1, operands[2], 0)) | |
8707 | { | |
e82ee4cc RK |
8708 | if (i == words-1) |
8709 | { | |
8710 | xop[0] = operands[1]; | |
8711 | xop[1] = operands[2]; | |
8712 | xop[2] = GEN_INT (4 * (words-1)); | |
d89ddcfd | 8713 | output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop); |
e82ee4cc RK |
8714 | return \"\"; |
8715 | } | |
8716 | else if (i == 0) | |
8717 | { | |
8718 | xop[0] = operands[1]; | |
39403d82 | 8719 | xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
e82ee4cc RK |
8720 | xop[2] = GEN_INT (4 * (words-1)); |
8721 | output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop); | |
8722 | return \"\"; | |
8723 | } | |
8724 | else | |
8725 | { | |
8726 | for (j = 0; j < words; j++) | |
8727 | if (j != i) | |
8728 | { | |
39403d82 | 8729 | xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j); |
e82ee4cc RK |
8730 | xop[1] = operands[2]; |
8731 | xop[2] = GEN_INT (j * 4); | |
8732 | output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop); | |
8733 | } | |
8734 | xop[0] = operands[2]; | |
8735 | xop[1] = GEN_INT (i * 4); | |
8736 | output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop); | |
8737 | return \"\"; | |
8738 | } | |
1fd4e8c1 RK |
8739 | } |
8740 | ||
e82ee4cc | 8741 | return \"{lsi|lswi} %1,%2,%N0\"; |
1fd4e8c1 | 8742 | }" |
b19003d8 | 8743 | [(set_attr "type" "load") |
e82ee4cc | 8744 | (set_attr "length" "32")]) |
b19003d8 | 8745 | |
b7ff3d82 | 8746 | \f |
1fd4e8c1 | 8747 | (define_expand "store_multiple" |
2f622005 RK |
8748 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8749 | (match_operand:SI 1 "" "")) | |
8750 | (clobber (scratch:SI)) | |
8751 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8752 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8753 | " |
8754 | { | |
8755 | int regno; | |
8756 | int count; | |
8757 | rtx to; | |
792760b9 | 8758 | rtx op0; |
1fd4e8c1 RK |
8759 | int i; |
8760 | ||
8761 | /* Support only storing a constant number of fixed-point registers to | |
8762 | memory and only bother with this if more than two; the machine | |
8763 | doesn't support more than eight. */ | |
8764 | if (GET_CODE (operands[2]) != CONST_INT | |
8765 | || INTVAL (operands[2]) <= 2 | |
8766 | || INTVAL (operands[2]) > 8 | |
8767 | || GET_CODE (operands[0]) != MEM | |
8768 | || GET_CODE (operands[1]) != REG | |
8769 | || REGNO (operands[1]) >= 32) | |
8770 | FAIL; | |
8771 | ||
8772 | count = INTVAL (operands[2]); | |
8773 | regno = REGNO (operands[1]); | |
8774 | ||
39403d82 | 8775 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 8776 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 8777 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
8778 | |
8779 | XVECEXP (operands[3], 0, 0) | |
68350f4f | 8780 | = gen_rtx_SET (VOIDmode, adjust_address (op0, SImode, 0), operands[1]); |
39403d82 | 8781 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8782 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8783 | |
8784 | for (i = 1; i < count; i++) | |
8785 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8786 | = gen_rtx_SET (VOIDmode, |
792760b9 | 8787 | adjust_address (op0, SImode, i * 4), |
c5c76735 | 8788 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
8789 | }") |
8790 | ||
8791 | (define_insn "" | |
8792 | [(match_parallel 0 "store_multiple_operation" | |
8793 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 8794 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 8795 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 8796 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
8797 | "{stsi|stswi} %2,%P1,%O0" |
8798 | [(set_attr "type" "store")]) | |
d14a6d05 MM |
8799 | |
8800 | (define_insn "" | |
8801 | [(match_parallel 0 "store_multiple_operation" | |
52d3af72 | 8802 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
d14a6d05 MM |
8803 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
8804 | (clobber (match_scratch:SI 3 "X"))])] | |
0ad91047 | 8805 | "TARGET_STRING && ! TARGET_POWER" |
b7ff3d82 DE |
8806 | "{stsi|stswi} %2,%1,%O0" |
8807 | [(set_attr "type" "store")]) | |
7e69e155 MM |
8808 | |
8809 | \f | |
8810 | ;; String/block move insn. | |
8811 | ;; Argument 0 is the destination | |
8812 | ;; Argument 1 is the source | |
8813 | ;; Argument 2 is the length | |
8814 | ;; Argument 3 is the alignment | |
8815 | ||
8816 | (define_expand "movstrsi" | |
b6c9286a MM |
8817 | [(parallel [(set (match_operand:BLK 0 "" "") |
8818 | (match_operand:BLK 1 "" "")) | |
8819 | (use (match_operand:SI 2 "" "")) | |
8820 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
8821 | "" |
8822 | " | |
8823 | { | |
8824 | if (expand_block_move (operands)) | |
8825 | DONE; | |
8826 | else | |
8827 | FAIL; | |
8828 | }") | |
8829 | ||
8830 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8831 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
8832 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8833 | (define_expand "movstrsi_8reg" |
b6c9286a MM |
8834 | [(parallel [(set (match_operand 0 "" "") |
8835 | (match_operand 1 "" "")) | |
8836 | (use (match_operand 2 "" "")) | |
8837 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
8838 | (clobber (reg:SI 5)) |
8839 | (clobber (reg:SI 6)) | |
8840 | (clobber (reg:SI 7)) | |
8841 | (clobber (reg:SI 8)) | |
8842 | (clobber (reg:SI 9)) | |
8843 | (clobber (reg:SI 10)) | |
8844 | (clobber (reg:SI 11)) | |
8845 | (clobber (reg:SI 12)) | |
3c67b673 | 8846 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8847 | "TARGET_STRING" |
8848 | "") | |
8849 | ||
8850 | (define_insn "" | |
52d3af72 DE |
8851 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8852 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8853 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8854 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8855 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8856 | (clobber (reg:SI 6)) |
8857 | (clobber (reg:SI 7)) | |
8858 | (clobber (reg:SI 8)) | |
8859 | (clobber (reg:SI 9)) | |
8860 | (clobber (reg:SI 10)) | |
8861 | (clobber (reg:SI 11)) | |
8862 | (clobber (reg:SI 12)) | |
3c67b673 | 8863 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 8864 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
8865 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8866 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8867 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8868 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8869 | && REGNO (operands[4]) == 5" |
8870 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8871 | [(set_attr "type" "load") |
8872 | (set_attr "length" "8")]) | |
7e69e155 MM |
8873 | |
8874 | (define_insn "" | |
52d3af72 DE |
8875 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8876 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8877 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8878 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8879 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8880 | (clobber (reg:SI 6)) |
8881 | (clobber (reg:SI 7)) | |
8882 | (clobber (reg:SI 8)) | |
8883 | (clobber (reg:SI 9)) | |
8884 | (clobber (reg:SI 10)) | |
8885 | (clobber (reg:SI 11)) | |
8886 | (clobber (reg:SI 12)) | |
3c67b673 | 8887 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8888 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
8889 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8890 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8891 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8892 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8893 | && REGNO (operands[4]) == 5" |
8894 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8895 | [(set_attr "type" "load") |
8896 | (set_attr "length" "8")]) | |
7e69e155 | 8897 | |
09a625f7 TR |
8898 | (define_insn "" |
8899 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
8900 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
8901 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
8902 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8903 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
8904 | (clobber (reg:SI 6)) | |
8905 | (clobber (reg:SI 7)) | |
8906 | (clobber (reg:SI 8)) | |
8907 | (clobber (reg:SI 9)) | |
8908 | (clobber (reg:SI 10)) | |
8909 | (clobber (reg:SI 11)) | |
8910 | (clobber (reg:SI 12)) | |
8911 | (clobber (match_scratch:SI 5 "X"))] | |
8912 | "TARGET_STRING && TARGET_POWERPC64 | |
8913 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) | |
8914 | || INTVAL (operands[2]) == 0) | |
8915 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
8916 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
8917 | && REGNO (operands[4]) == 5" | |
8918 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
8919 | [(set_attr "type" "load") | |
8920 | (set_attr "length" "8")]) | |
8921 | ||
7e69e155 | 8922 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the |
f9562f27 DE |
8923 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
8924 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8925 | (define_expand "movstrsi_6reg" |
b6c9286a MM |
8926 | [(parallel [(set (match_operand 0 "" "") |
8927 | (match_operand 1 "" "")) | |
8928 | (use (match_operand 2 "" "")) | |
8929 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
8930 | (clobber (reg:SI 5)) |
8931 | (clobber (reg:SI 6)) | |
7e69e155 MM |
8932 | (clobber (reg:SI 7)) |
8933 | (clobber (reg:SI 8)) | |
8934 | (clobber (reg:SI 9)) | |
8935 | (clobber (reg:SI 10)) | |
3c67b673 | 8936 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8937 | "TARGET_STRING" |
8938 | "") | |
8939 | ||
8940 | (define_insn "" | |
52d3af72 DE |
8941 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8942 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8943 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8944 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8945 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8946 | (clobber (reg:SI 6)) |
8947 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8948 | (clobber (reg:SI 8)) |
8949 | (clobber (reg:SI 9)) | |
8950 | (clobber (reg:SI 10)) | |
3c67b673 | 8951 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
8952 | "TARGET_STRING && TARGET_POWER |
8953 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
8954 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8955 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8956 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8957 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8958 | [(set_attr "type" "load") |
8959 | (set_attr "length" "8")]) | |
7e69e155 MM |
8960 | |
8961 | (define_insn "" | |
52d3af72 DE |
8962 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8963 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8964 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8965 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8966 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8967 | (clobber (reg:SI 6)) |
8968 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8969 | (clobber (reg:SI 8)) |
8970 | (clobber (reg:SI 9)) | |
8971 | (clobber (reg:SI 10)) | |
3c67b673 | 8972 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8973 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8974 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
8975 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8976 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8977 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8978 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8979 | [(set_attr "type" "load") |
8980 | (set_attr "length" "8")]) | |
7e69e155 | 8981 | |
09a625f7 TR |
8982 | (define_insn "" |
8983 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
8984 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
8985 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
8986 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8987 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
8988 | (clobber (reg:SI 6)) | |
8989 | (clobber (reg:SI 7)) | |
8990 | (clobber (reg:SI 8)) | |
8991 | (clobber (reg:SI 9)) | |
8992 | (clobber (reg:SI 10)) | |
8993 | (clobber (match_scratch:SI 5 "X"))] | |
8994 | "TARGET_STRING && TARGET_POWERPC64 | |
8995 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 | |
8996 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) | |
8997 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8998 | && REGNO (operands[4]) == 5" | |
8999 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9000 | [(set_attr "type" "load") | |
9001 | (set_attr "length" "8")]) | |
9002 | ||
f9562f27 DE |
9003 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
9004 | ;; problems with TImode. | |
9005 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9006 | (define_expand "movstrsi_4reg" |
b6c9286a MM |
9007 | [(parallel [(set (match_operand 0 "" "") |
9008 | (match_operand 1 "" "")) | |
9009 | (use (match_operand 2 "" "")) | |
9010 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9011 | (clobber (reg:SI 5)) |
9012 | (clobber (reg:SI 6)) | |
9013 | (clobber (reg:SI 7)) | |
9014 | (clobber (reg:SI 8)) | |
3c67b673 | 9015 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9016 | "TARGET_STRING" |
9017 | "") | |
9018 | ||
9019 | (define_insn "" | |
52d3af72 DE |
9020 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9021 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9022 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9023 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9024 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9025 | (clobber (reg:SI 6)) |
9026 | (clobber (reg:SI 7)) | |
9027 | (clobber (reg:SI 8)) | |
3c67b673 | 9028 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9029 | "TARGET_STRING && TARGET_POWER |
9030 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
9031 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9032 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9033 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9034 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9035 | [(set_attr "type" "load") |
9036 | (set_attr "length" "8")]) | |
7e69e155 MM |
9037 | |
9038 | (define_insn "" | |
52d3af72 DE |
9039 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9040 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9041 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9042 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9043 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9044 | (clobber (reg:SI 6)) |
9045 | (clobber (reg:SI 7)) | |
9046 | (clobber (reg:SI 8)) | |
3c67b673 | 9047 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9048 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9049 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
9050 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9051 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9052 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9053 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9054 | [(set_attr "type" "load") |
9055 | (set_attr "length" "8")]) | |
7e69e155 | 9056 | |
09a625f7 TR |
9057 | (define_insn "" |
9058 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9059 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9060 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9061 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9062 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9063 | (clobber (reg:SI 6)) | |
9064 | (clobber (reg:SI 7)) | |
9065 | (clobber (reg:SI 8)) | |
9066 | (clobber (match_scratch:SI 5 "X"))] | |
9067 | "TARGET_STRING && TARGET_POWERPC64 | |
9068 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
9069 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) | |
9070 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9071 | && REGNO (operands[4]) == 5" | |
9072 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9073 | [(set_attr "type" "load") | |
9074 | (set_attr "length" "8")]) | |
9075 | ||
7e69e155 MM |
9076 | ;; Move up to 8 bytes at a time. |
9077 | (define_expand "movstrsi_2reg" | |
b6c9286a MM |
9078 | [(parallel [(set (match_operand 0 "" "") |
9079 | (match_operand 1 "" "")) | |
9080 | (use (match_operand 2 "" "")) | |
9081 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9082 | (clobber (match_scratch:DI 4 "")) |
9083 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 9084 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
9085 | "") |
9086 | ||
9087 | (define_insn "" | |
52d3af72 DE |
9088 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9089 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9090 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9091 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9092 | (clobber (match_scratch:DI 4 "=&r")) | |
9093 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 9094 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
9095 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
9096 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9097 | [(set_attr "type" "load") |
9098 | (set_attr "length" "8")]) | |
7e69e155 MM |
9099 | |
9100 | (define_insn "" | |
52d3af72 DE |
9101 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9102 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9103 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9104 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9105 | (clobber (match_scratch:DI 4 "=&r")) | |
9106 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 9107 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 9108 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 9109 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9110 | [(set_attr "type" "load") |
9111 | (set_attr "length" "8")]) | |
7e69e155 MM |
9112 | |
9113 | ;; Move up to 4 bytes at a time. | |
9114 | (define_expand "movstrsi_1reg" | |
b6c9286a MM |
9115 | [(parallel [(set (match_operand 0 "" "") |
9116 | (match_operand 1 "" "")) | |
9117 | (use (match_operand 2 "" "")) | |
9118 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9119 | (clobber (match_scratch:SI 4 "")) |
9120 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
9121 | "TARGET_STRING" |
9122 | "") | |
9123 | ||
9124 | (define_insn "" | |
52d3af72 DE |
9125 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9126 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9127 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9128 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9129 | (clobber (match_scratch:SI 4 "=&r")) | |
9130 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
9131 | "TARGET_STRING && TARGET_POWER |
9132 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9133 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9134 | [(set_attr "type" "load") |
9135 | (set_attr "length" "8")]) | |
7e69e155 MM |
9136 | |
9137 | (define_insn "" | |
52d3af72 DE |
9138 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9139 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9140 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9141 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9142 | (clobber (match_scratch:SI 4 "=&r")) | |
9143 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 9144 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9145 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
09a625f7 TR |
9146 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
9147 | [(set_attr "type" "load") | |
9148 | (set_attr "length" "8")]) | |
9149 | ||
9150 | (define_insn "" | |
9151 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9152 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9153 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9154 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9155 | (clobber (match_scratch:SI 4 "=&r")) | |
9156 | (clobber (match_scratch:SI 5 "X"))] | |
9157 | "TARGET_STRING && TARGET_POWERPC64 | |
9158 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9159 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9160 | [(set_attr "type" "load") |
9161 | (set_attr "length" "8")]) | |
7e69e155 | 9162 | |
1fd4e8c1 | 9163 | \f |
7e69e155 | 9164 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
9165 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
9166 | ;; do cases where the increment is not the size of the object. | |
9167 | ;; | |
9168 | ;; In all these cases, we use operands 0 and 1 for the register being | |
9169 | ;; incremented because those are the operands that local-alloc will | |
9170 | ;; tie and these are the pair most likely to be tieable (and the ones | |
9171 | ;; that will benefit the most). | |
9172 | ||
38c1f2d7 | 9173 | (define_insn "*movdi_update1" |
51b8fc2c | 9174 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 9175 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 9176 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) |
51b8fc2c RK |
9177 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") |
9178 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9179 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9180 | "@ |
9181 | ldux %3,%0,%2 | |
9182 | ldu %3,%2(%0)" | |
9183 | [(set_attr "type" "load")]) | |
9184 | ||
38c1f2d7 | 9185 | (define_insn "*movdi_update2" |
287f13ff RK |
9186 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") |
9187 | (sign_extend:DI | |
9188 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
9189 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
9190 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
9191 | (plus:DI (match_dup 1) (match_dup 2)))] | |
9192 | "TARGET_POWERPC64" | |
9193 | "lwaux %3,%0,%2" | |
9194 | [(set_attr "type" "load")]) | |
9195 | ||
4697a36c | 9196 | (define_insn "movdi_update" |
51b8fc2c | 9197 | [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 9198 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))) |
51b8fc2c RK |
9199 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) |
9200 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
9201 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9202 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9203 | "@ |
9204 | stdux %3,%0,%2 | |
b7ff3d82 DE |
9205 | stdu %3,%2(%0)" |
9206 | [(set_attr "type" "store")]) | |
51b8fc2c | 9207 | |
38c1f2d7 | 9208 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
9209 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
9210 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9211 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9212 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
9213 | (plus:SI (match_dup 1) (match_dup 2)))] |
9214 | "" | |
9215 | "@ | |
ca7f5001 RK |
9216 | {lux|lwzux} %3,%0,%2 |
9217 | {lu|lwzu} %3,%2(%0)" | |
cfb557c4 | 9218 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9219 | |
4697a36c | 9220 | (define_insn "movsi_update" |
cd2b37d9 | 9221 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9222 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9223 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
9224 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9225 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9226 | "TARGET_UPDATE" |
1fd4e8c1 | 9227 | "@ |
ca7f5001 | 9228 | {stux|stwux} %3,%0,%2 |
b7ff3d82 DE |
9229 | {stu|stwu} %3,%2(%0)" |
9230 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 9231 | |
38c1f2d7 | 9232 | (define_insn "*movhi_update" |
cd2b37d9 RK |
9233 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
9234 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9235 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9236 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9237 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9238 | "TARGET_UPDATE" |
1fd4e8c1 | 9239 | "@ |
5f243543 RK |
9240 | lhzux %3,%0,%2 |
9241 | lhzu %3,%2(%0)" | |
cfb557c4 | 9242 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9243 | |
38c1f2d7 | 9244 | (define_insn "*movhi_update2" |
cd2b37d9 | 9245 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9246 | (zero_extend:SI |
cd2b37d9 | 9247 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9248 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9249 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9250 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9251 | "TARGET_UPDATE" |
1fd4e8c1 | 9252 | "@ |
5f243543 RK |
9253 | lhzux %3,%0,%2 |
9254 | lhzu %3,%2(%0)" | |
cfb557c4 | 9255 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9256 | |
38c1f2d7 | 9257 | (define_insn "*movhi_update3" |
cd2b37d9 | 9258 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9259 | (sign_extend:SI |
cd2b37d9 | 9260 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9261 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9262 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9263 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9264 | "TARGET_UPDATE" |
1fd4e8c1 | 9265 | "@ |
5f243543 RK |
9266 | lhaux %3,%0,%2 |
9267 | lhau %3,%2(%0)" | |
cfb557c4 | 9268 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9269 | |
38c1f2d7 | 9270 | (define_insn "*movhi_update4" |
cd2b37d9 | 9271 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9272 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9273 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
9274 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9275 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9276 | "TARGET_UPDATE" |
1fd4e8c1 | 9277 | "@ |
5f243543 | 9278 | sthux %3,%0,%2 |
b7ff3d82 DE |
9279 | sthu %3,%2(%0)" |
9280 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 9281 | |
38c1f2d7 | 9282 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
9283 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
9284 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9285 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9286 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9287 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9288 | "TARGET_UPDATE" |
1fd4e8c1 | 9289 | "@ |
5f243543 RK |
9290 | lbzux %3,%0,%2 |
9291 | lbzu %3,%2(%0)" | |
cfb557c4 | 9292 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9293 | |
38c1f2d7 | 9294 | (define_insn "*movqi_update2" |
cd2b37d9 | 9295 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9296 | (zero_extend:SI |
cd2b37d9 | 9297 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9298 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9299 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9300 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9301 | "TARGET_UPDATE" |
1fd4e8c1 | 9302 | "@ |
5f243543 RK |
9303 | lbzux %3,%0,%2 |
9304 | lbzu %3,%2(%0)" | |
cfb557c4 | 9305 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9306 | |
38c1f2d7 | 9307 | (define_insn "*movqi_update3" |
cd2b37d9 | 9308 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9309 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9310 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
9311 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9312 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9313 | "TARGET_UPDATE" |
1fd4e8c1 | 9314 | "@ |
5f243543 | 9315 | stbux %3,%0,%2 |
b7ff3d82 DE |
9316 | stbu %3,%2(%0)" |
9317 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 9318 | |
38c1f2d7 | 9319 | (define_insn "*movsf_update1" |
cd2b37d9 | 9320 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 9321 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9322 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9323 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9324 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9325 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9326 | "@ |
5f243543 RK |
9327 | lfsux %3,%0,%2 |
9328 | lfsu %3,%2(%0)" | |
cfb557c4 | 9329 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 9330 | |
38c1f2d7 | 9331 | (define_insn "*movsf_update2" |
cd2b37d9 | 9332 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9333 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9334 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
9335 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9336 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9337 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9338 | "@ |
85fff2f3 | 9339 | stfsux %3,%0,%2 |
b7ff3d82 DE |
9340 | stfsu %3,%2(%0)" |
9341 | [(set_attr "type" "fpstore")]) | |
1fd4e8c1 | 9342 | |
38c1f2d7 MM |
9343 | (define_insn "*movsf_update3" |
9344 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
9345 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9346 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
9347 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9348 | (plus:SI (match_dup 1) (match_dup 2)))] | |
9349 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
9350 | "@ | |
9351 | {lux|lwzux} %3,%0,%2 | |
9352 | {lu|lwzu} %3,%2(%0)" | |
9353 | [(set_attr "type" "load")]) | |
9354 | ||
9355 | (define_insn "*movsf_update4" | |
9356 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9357 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
9358 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
9359 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9360 | (plus:SI (match_dup 1) (match_dup 2)))] | |
9361 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
9362 | "@ | |
9363 | {stux|stwux} %3,%0,%2 | |
9364 | {stu|stwu} %3,%2(%0)" | |
9365 | [(set_attr "type" "store")]) | |
9366 | ||
9367 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
9368 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
9369 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9370 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9371 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9372 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9373 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9374 | "@ |
5f243543 RK |
9375 | lfdux %3,%0,%2 |
9376 | lfdu %3,%2(%0)" | |
cfb557c4 | 9377 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 9378 | |
38c1f2d7 | 9379 | (define_insn "*movdf_update2" |
cd2b37d9 | 9380 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9381 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9382 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
9383 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9384 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9385 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9386 | "@ |
5f243543 | 9387 | stfdux %3,%0,%2 |
b7ff3d82 DE |
9388 | stfdu %3,%2(%0)" |
9389 | [(set_attr "type" "fpstore")]) | |
4c70a4f3 RK |
9390 | |
9391 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
9392 | ||
9393 | (define_peephole | |
9394 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
9395 | (match_operand:DF 1 "memory_operand" "")) | |
9396 | (set (match_operand:DF 2 "gpc_reg_operand" "=f") | |
9397 | (match_operand:DF 3 "memory_operand" ""))] | |
9398 | "TARGET_POWER2 | |
d14a6d05 | 9399 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
9400 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
9401 | && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) | |
9402 | && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" | |
9403 | "lfq%U1%X1 %0,%1") | |
9404 | ||
9405 | (define_peephole | |
9406 | [(set (match_operand:DF 0 "memory_operand" "") | |
9407 | (match_operand:DF 1 "gpc_reg_operand" "f")) | |
9408 | (set (match_operand:DF 2 "memory_operand" "") | |
9409 | (match_operand:DF 3 "gpc_reg_operand" "f"))] | |
9410 | "TARGET_POWER2 | |
d14a6d05 | 9411 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
9412 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
9413 | && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) | |
9414 | && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" | |
9415 | "stfq%U0%X0 %1,%0") | |
1fd4e8c1 RK |
9416 | \f |
9417 | ;; Next come insns related to the calling sequence. | |
9418 | ;; | |
9419 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 9420 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
9421 | |
9422 | (define_expand "allocate_stack" | |
52d3af72 | 9423 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9424 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
9425 | (set (reg 1) | |
9426 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
9427 | "" |
9428 | " | |
4697a36c | 9429 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 9430 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 9431 | rtx neg_op0; |
1fd4e8c1 RK |
9432 | |
9433 | emit_move_insn (chain, stack_bot); | |
4697a36c | 9434 | |
a157febd GK |
9435 | /* Check stack bounds if necessary. */ |
9436 | if (current_function_limit_stack) | |
9437 | { | |
9438 | rtx available; | |
9439 | available = expand_binop (Pmode, sub_optab, | |
9440 | stack_pointer_rtx, stack_limit_rtx, | |
9441 | NULL_RTX, 1, OPTAB_WIDEN); | |
9442 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
9443 | } | |
9444 | ||
e9a25f70 JL |
9445 | if (GET_CODE (operands[1]) != CONST_INT |
9446 | || INTVAL (operands[1]) < -32767 | |
9447 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
9448 | { |
9449 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 9450 | if (TARGET_32BIT) |
e9a25f70 | 9451 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 9452 | else |
e9a25f70 | 9453 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
9454 | } |
9455 | else | |
e9a25f70 | 9456 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 9457 | |
38c1f2d7 MM |
9458 | if (TARGET_UPDATE) |
9459 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) | |
9460 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); | |
4697a36c | 9461 | |
38c1f2d7 MM |
9462 | else |
9463 | { | |
9464 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
9465 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 9466 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 9467 | } |
e9a25f70 JL |
9468 | |
9469 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
9470 | DONE; |
9471 | }") | |
59257ff7 RK |
9472 | |
9473 | ;; These patterns say how to save and restore the stack pointer. We need not | |
9474 | ;; save the stack pointer at function level since we are careful to | |
9475 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9476 | ;; when we restore the stack pointer. | |
9477 | ;; | |
9478 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9479 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9480 | ;; save area is a memory location. | |
9481 | ||
9482 | (define_expand "save_stack_function" | |
ff381587 MM |
9483 | [(match_operand 0 "any_operand" "") |
9484 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9485 | "" |
ff381587 | 9486 | "DONE;") |
59257ff7 RK |
9487 | |
9488 | (define_expand "restore_stack_function" | |
ff381587 MM |
9489 | [(match_operand 0 "any_operand" "") |
9490 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9491 | "" |
ff381587 | 9492 | "DONE;") |
59257ff7 RK |
9493 | |
9494 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
9495 | [(use (match_operand 0 "register_operand" "")) |
9496 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 9497 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 9498 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
9499 | "" |
9500 | " | |
dfdfa60f DE |
9501 | { |
9502 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 9503 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 9504 | }") |
59257ff7 RK |
9505 | |
9506 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
9507 | [(match_operand 0 "memory_operand" "") |
9508 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
9509 | "" |
9510 | " | |
9511 | { | |
a260abc9 | 9512 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
9513 | |
9514 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 9515 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
c5c76735 JL |
9516 | emit_move_insn (operand_subword (operands[0], 0, 0, |
9517 | (TARGET_32BIT ? DImode : TImode)), | |
a260abc9 DE |
9518 | temp); |
9519 | emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)), | |
9520 | operands[1]); | |
59257ff7 RK |
9521 | DONE; |
9522 | }") | |
7e69e155 | 9523 | |
59257ff7 | 9524 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
9525 | [(match_operand 0 "register_operand" "") |
9526 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
9527 | "" |
9528 | " | |
9529 | { | |
a260abc9 | 9530 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
9531 | |
9532 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 DE |
9533 | emit_move_insn (temp, |
9534 | operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode))); | |
9535 | emit_move_insn (operands[0], | |
c5c76735 JL |
9536 | operand_subword (operands[1], 1, 0, |
9537 | (TARGET_32BIT ? DImode : TImode))); | |
39403d82 | 9538 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
9539 | DONE; |
9540 | }") | |
9ebbca7d GK |
9541 | \f |
9542 | ;; TOC register handling. | |
b6c9286a | 9543 | |
9ebbca7d | 9544 | ;; Code to initialize the TOC register... |
f0f6a223 | 9545 | |
9ebbca7d | 9546 | (define_insn "load_toc_aix_si" |
e72247f4 | 9547 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
46aaf10d DE |
9548 | (unspec:SI [(const_int 0)] 7)) |
9549 | (use (reg:SI 2))])] | |
2bfcf297 | 9550 | "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" |
f0f6a223 RK |
9551 | "* |
9552 | { | |
9ebbca7d GK |
9553 | char buf[30]; |
9554 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 9555 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9556 | operands[2] = gen_rtx_REG (Pmode, 2); |
9557 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
9558 | }" |
9559 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
9560 | |
9561 | (define_insn "load_toc_aix_di" | |
e72247f4 | 9562 | [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
46aaf10d DE |
9563 | (unspec:DI [(const_int 0)] 7)) |
9564 | (use (reg:DI 2))])] | |
2bfcf297 | 9565 | "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" |
9ebbca7d GK |
9566 | "* |
9567 | { | |
9568 | char buf[30]; | |
f585a356 DE |
9569 | #ifdef TARGET_RELOCATABLE |
9570 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", | |
9571 | !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); | |
9572 | #else | |
9ebbca7d | 9573 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); |
f585a356 | 9574 | #endif |
2bfcf297 DB |
9575 | if (TARGET_ELF) |
9576 | strcat (buf, \"@toc\"); | |
a8a05998 | 9577 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9578 | operands[2] = gen_rtx_REG (Pmode, 2); |
9579 | return \"ld %0,%1(%2)\"; | |
9580 | }" | |
9581 | [(set_attr "type" "load")]) | |
9582 | ||
9583 | (define_insn "load_toc_v4_pic_si" | |
9584 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9585 | (unspec:SI [(const_int 0)] 7))] | |
f607bc57 | 9586 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" |
9ebbca7d GK |
9587 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
9588 | [(set_attr "type" "branch") | |
9589 | (set_attr "length" "4")]) | |
9590 | ||
9ebbca7d GK |
9591 | (define_insn "load_toc_v4_PIC_1" |
9592 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9593 | (match_operand:SI 1 "immediate_operand" "s")) | |
9594 | (unspec [(match_dup 1)] 7)] | |
9595 | "TARGET_ELF && flag_pic == 2" | |
9596 | "bl %1\\n%1:" | |
9597 | [(set_attr "type" "branch") | |
9598 | (set_attr "length" "4")]) | |
9599 | ||
9600 | (define_insn "load_toc_v4_PIC_1b" | |
9601 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9602 | (match_operand:SI 1 "immediate_operand" "s")) | |
9603 | (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)] | |
9604 | "TARGET_ELF && flag_pic == 2" | |
9605 | "bl %1\\n\\t.long %2-%1+4\\n%1:" | |
9606 | [(set_attr "type" "branch") | |
9607 | (set_attr "length" "8")]) | |
9608 | ||
9609 | (define_insn "load_toc_v4_PIC_2" | |
f585a356 DE |
9610 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9611 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
9ebbca7d GK |
9612 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") |
9613 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
9614 | "TARGET_ELF && flag_pic == 2" | |
9615 | "{l|lwz} %0,%2-%3(%1)" | |
9616 | [(set_attr "type" "load")]) | |
9617 | ||
ee890fe2 SS |
9618 | (define_insn "load_macho_picbase" |
9619 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9620 | (unspec:SI [(const_int 0)] 15))] | |
9621 | "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" | |
9622 | "* | |
9623 | { | |
9624 | #if TARGET_MACHO | |
9625 | char *picbase = machopic_function_base_name (); | |
9626 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1)); | |
9627 | #endif | |
9628 | return \"bcl 20,31,%1\\n%1:\"; | |
9629 | }" | |
9630 | [(set_attr "type" "branch") | |
9631 | (set_attr "length" "4")]) | |
9632 | ||
9ebbca7d GK |
9633 | ;; If the TOC is shared over a translation unit, as happens with all |
9634 | ;; the kinds of PIC that we support, we need to restore the TOC | |
9635 | ;; pointer only when jumping over units of translation. | |
9636 | ||
9637 | (define_expand "builtin_setjmp_receiver" | |
9638 | [(use (label_ref (match_operand 0 "" "")))] | |
f607bc57 | 9639 | "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
9ebbca7d GK |
9640 | || (TARGET_TOC && TARGET_MINIMAL_TOC)" |
9641 | " | |
9642 | { | |
9643 | rs6000_emit_load_toc_table (FALSE); | |
9644 | DONE; | |
9645 | }") | |
9646 | \f | |
9647 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
9648 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
9649 | ;; pointer to its TOC, and whose third word contains a value to place in the |
9650 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 9651 | ;; "trampoline" need not have any executable code. |
b6c9286a | 9652 | |
cccf3bdc DE |
9653 | (define_expand "call_indirect_aix32" |
9654 | [(set (match_dup 2) | |
9655 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
9656 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9657 | (reg:SI 2)) | |
9658 | (set (reg:SI 2) | |
9659 | (mem:SI (plus:SI (match_dup 0) | |
9660 | (const_int 4)))) | |
9661 | (set (reg:SI 11) | |
9662 | (mem:SI (plus:SI (match_dup 0) | |
9663 | (const_int 8)))) | |
9664 | (parallel [(call (mem:SI (match_dup 2)) | |
9665 | (match_operand 1 "" "")) | |
9666 | (use (reg:SI 2)) | |
9667 | (use (reg:SI 11)) | |
9668 | (set (reg:SI 2) | |
9669 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9670 | (clobber (scratch:SI))])] | |
9671 | "TARGET_32BIT" | |
9672 | " | |
9673 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9674 | |
cccf3bdc DE |
9675 | (define_expand "call_indirect_aix64" |
9676 | [(set (match_dup 2) | |
9677 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
9678 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9679 | (reg:DI 2)) | |
9680 | (set (reg:DI 2) | |
9681 | (mem:DI (plus:DI (match_dup 0) | |
9682 | (const_int 8)))) | |
9683 | (set (reg:DI 11) | |
9684 | (mem:DI (plus:DI (match_dup 0) | |
9685 | (const_int 16)))) | |
9686 | (parallel [(call (mem:SI (match_dup 2)) | |
9687 | (match_operand 1 "" "")) | |
9688 | (use (reg:DI 2)) | |
9689 | (use (reg:DI 11)) | |
9690 | (set (reg:DI 2) | |
9691 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9692 | (clobber (scratch:SI))])] | |
9693 | "TARGET_64BIT" | |
9694 | " | |
9695 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 9696 | |
cccf3bdc DE |
9697 | (define_expand "call_value_indirect_aix32" |
9698 | [(set (match_dup 3) | |
9699 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
9700 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9701 | (reg:SI 2)) | |
9702 | (set (reg:SI 2) | |
9703 | (mem:SI (plus:SI (match_dup 1) | |
9704 | (const_int 4)))) | |
9705 | (set (reg:SI 11) | |
9706 | (mem:SI (plus:SI (match_dup 1) | |
9707 | (const_int 8)))) | |
9708 | (parallel [(set (match_operand 0 "" "") | |
9709 | (call (mem:SI (match_dup 3)) | |
9710 | (match_operand 2 "" ""))) | |
9711 | (use (reg:SI 2)) | |
9712 | (use (reg:SI 11)) | |
9713 | (set (reg:SI 2) | |
9714 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9715 | (clobber (scratch:SI))])] | |
9716 | "TARGET_32BIT" | |
9717 | " | |
9718 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9719 | |
cccf3bdc DE |
9720 | (define_expand "call_value_indirect_aix64" |
9721 | [(set (match_dup 3) | |
9722 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
9723 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9724 | (reg:DI 2)) | |
9725 | (set (reg:DI 2) | |
9726 | (mem:DI (plus:DI (match_dup 1) | |
9727 | (const_int 8)))) | |
9728 | (set (reg:DI 11) | |
9729 | (mem:DI (plus:DI (match_dup 1) | |
9730 | (const_int 16)))) | |
9731 | (parallel [(set (match_operand 0 "" "") | |
9732 | (call (mem:SI (match_dup 3)) | |
9733 | (match_operand 2 "" ""))) | |
9734 | (use (reg:DI 2)) | |
9735 | (use (reg:DI 11)) | |
9736 | (set (reg:DI 2) | |
9737 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9738 | (clobber (scratch:SI))])] | |
9739 | "TARGET_64BIT" | |
9740 | " | |
9741 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 9742 | |
b6c9286a | 9743 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 9744 | (define_expand "call" |
a260abc9 | 9745 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 9746 | (match_operand 1 "" "")) |
4697a36c | 9747 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
9748 | (clobber (scratch:SI))])] |
9749 | "" | |
9750 | " | |
9751 | { | |
ee890fe2 SS |
9752 | #if TARGET_MACHO |
9753 | if (flag_pic) | |
9754 | operands[0] = machopic_indirect_call_target (operands[0]); | |
9755 | #endif | |
9756 | ||
1fd4e8c1 RK |
9757 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) |
9758 | abort (); | |
9759 | ||
9760 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 9761 | |
6a4cee5f MM |
9762 | if (GET_CODE (operands[0]) != SYMBOL_REF |
9763 | || (INTVAL (operands[2]) & CALL_LONG) != 0) | |
1fd4e8c1 | 9764 | { |
6a4cee5f MM |
9765 | if (INTVAL (operands[2]) & CALL_LONG) |
9766 | operands[0] = rs6000_longcall_ref (operands[0]); | |
9767 | ||
cccf3bdc DE |
9768 | if (DEFAULT_ABI == ABI_V4 |
9769 | || DEFAULT_ABI == ABI_AIX_NODESC | |
f607bc57 | 9770 | || DEFAULT_ABI == ABI_DARWIN) |
cccf3bdc | 9771 | operands[0] = force_reg (Pmode, operands[0]); |
1fd4e8c1 | 9772 | |
cccf3bdc DE |
9773 | else if (DEFAULT_ABI == ABI_AIX) |
9774 | { | |
9775 | /* AIX function pointers are really pointers to a three word | |
9776 | area. */ | |
9777 | emit_call_insn (TARGET_32BIT | |
9778 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
9779 | operands[0]), | |
9780 | operands[1]) | |
9781 | : gen_call_indirect_aix64 (force_reg (DImode, | |
9782 | operands[0]), | |
9783 | operands[1])); | |
9784 | DONE; | |
b6c9286a | 9785 | } |
cccf3bdc DE |
9786 | else |
9787 | abort (); | |
1fd4e8c1 RK |
9788 | } |
9789 | }") | |
9790 | ||
9791 | (define_expand "call_value" | |
9792 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 9793 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 9794 | (match_operand 2 "" ""))) |
4697a36c | 9795 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
9796 | (clobber (scratch:SI))])] |
9797 | "" | |
9798 | " | |
9799 | { | |
ee890fe2 SS |
9800 | #if TARGET_MACHO |
9801 | if (flag_pic) | |
9802 | operands[1] = machopic_indirect_call_target (operands[1]); | |
9803 | #endif | |
9804 | ||
1fd4e8c1 RK |
9805 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) |
9806 | abort (); | |
9807 | ||
9808 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 9809 | |
6a4cee5f MM |
9810 | if (GET_CODE (operands[1]) != SYMBOL_REF |
9811 | || (INTVAL (operands[3]) & CALL_LONG) != 0) | |
1fd4e8c1 | 9812 | { |
6756293c | 9813 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
9814 | operands[1] = rs6000_longcall_ref (operands[1]); |
9815 | ||
cccf3bdc DE |
9816 | if (DEFAULT_ABI == ABI_V4 |
9817 | || DEFAULT_ABI == ABI_AIX_NODESC | |
f607bc57 | 9818 | || DEFAULT_ABI == ABI_DARWIN) |
cccf3bdc | 9819 | operands[0] = force_reg (Pmode, operands[0]); |
1fd4e8c1 | 9820 | |
cccf3bdc DE |
9821 | else if (DEFAULT_ABI == ABI_AIX) |
9822 | { | |
9823 | /* AIX function pointers are really pointers to a three word | |
9824 | area. */ | |
9825 | emit_call_insn (TARGET_32BIT | |
9826 | ? gen_call_value_indirect_aix32 (operands[0], | |
9827 | force_reg (SImode, | |
9828 | operands[1]), | |
9829 | operands[2]) | |
9830 | : gen_call_value_indirect_aix64 (operands[0], | |
9831 | force_reg (DImode, | |
9832 | operands[1]), | |
9833 | operands[2])); | |
9834 | DONE; | |
b6c9286a | 9835 | } |
cccf3bdc DE |
9836 | else |
9837 | abort (); | |
1fd4e8c1 RK |
9838 | } |
9839 | }") | |
9840 | ||
04780ee7 | 9841 | ;; Call to function in current module. No TOC pointer reload needed. |
4697a36c MM |
9842 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
9843 | ;; either the function was not prototyped, or it was prototyped as a | |
9844 | ;; variable argument function. It is > 0 if FP registers were passed | |
9845 | ;; and < 0 if they were not. | |
04780ee7 | 9846 | |
a260abc9 | 9847 | (define_insn "*call_local32" |
4697a36c MM |
9848 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
9849 | (match_operand 1 "" "g,g")) | |
9850 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9851 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 9852 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
9853 | "* |
9854 | { | |
6a4cee5f MM |
9855 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
9856 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9857 | ||
9858 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9859 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 9860 | |
a226df46 | 9861 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 9862 | }" |
b7ff3d82 DE |
9863 | [(set_attr "type" "branch") |
9864 | (set_attr "length" "4,8")]) | |
04780ee7 | 9865 | |
a260abc9 DE |
9866 | (define_insn "*call_local64" |
9867 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
9868 | (match_operand 1 "" "g,g")) | |
9869 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9870 | (clobber (match_scratch:SI 3 "=l,l"))] | |
9871 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
9872 | "* | |
9873 | { | |
9874 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
9875 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9876 | ||
9877 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9878 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9879 | ||
9880 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
9881 | }" | |
9882 | [(set_attr "type" "branch") | |
9883 | (set_attr "length" "4,8")]) | |
9884 | ||
cccf3bdc | 9885 | (define_insn "*call_value_local32" |
d18dba68 | 9886 | [(set (match_operand 0 "" "") |
a260abc9 DE |
9887 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) |
9888 | (match_operand 2 "" "g,g"))) | |
9889 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9890 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9891 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
9892 | "* | |
9893 | { | |
9894 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9895 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9896 | ||
9897 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9898 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9899 | ||
9900 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9901 | }" | |
9902 | [(set_attr "type" "branch") | |
9903 | (set_attr "length" "4,8")]) | |
9904 | ||
9905 | ||
cccf3bdc | 9906 | (define_insn "*call_value_local64" |
d18dba68 | 9907 | [(set (match_operand 0 "" "") |
a260abc9 DE |
9908 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) |
9909 | (match_operand 2 "" "g,g"))) | |
9910 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9911 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9912 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
9913 | "* | |
9914 | { | |
9915 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9916 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9917 | ||
9918 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9919 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9920 | ||
9921 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9922 | }" | |
9923 | [(set_attr "type" "branch") | |
9924 | (set_attr "length" "4,8")]) | |
9925 | ||
04780ee7 | 9926 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 9927 | ;; pointer (r2) after the call unless this is System V. |
4697a36c MM |
9928 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
9929 | ;; either the function was not prototyped, or it was prototyped as a | |
9930 | ;; variable argument function. It is > 0 if FP registers were passed | |
9931 | ;; and < 0 if they were not. | |
04780ee7 | 9932 | |
cccf3bdc DE |
9933 | (define_insn "*call_indirect_nonlocal_aix32" |
9934 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) | |
9935 | (match_operand 1 "" "g")) | |
9936 | (use (reg:SI 2)) | |
9937 | (use (reg:SI 11)) | |
9938 | (set (reg:SI 2) | |
9939 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
c77e04ae | 9940 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
9941 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
9942 | "b%T0l\;{l|lwz} 2,20(1)" | |
9943 | [(set_attr "type" "jmpreg") | |
9944 | (set_attr "length" "8")]) | |
9945 | ||
a260abc9 | 9946 | (define_insn "*call_nonlocal_aix32" |
cc4d5fec | 9947 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
9948 | (match_operand 1 "" "g")) |
9949 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
9950 | (clobber (match_scratch:SI 3 "=l"))] | |
9951 | "TARGET_32BIT | |
9952 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 9953 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 9954 | "bl %z0\;%." |
b7ff3d82 | 9955 | [(set_attr "type" "branch") |
cccf3bdc DE |
9956 | (set_attr "length" "8")]) |
9957 | ||
9958 | (define_insn "*call_indirect_nonlocal_aix64" | |
9959 | [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) | |
9960 | (match_operand 1 "" "g")) | |
9961 | (use (reg:DI 2)) | |
9962 | (use (reg:DI 11)) | |
9963 | (set (reg:DI 2) | |
9964 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
c77e04ae | 9965 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
9966 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
9967 | "b%T0l\;ld 2,40(1)" | |
9968 | [(set_attr "type" "jmpreg") | |
9969 | (set_attr "length" "8")]) | |
59313e4e | 9970 | |
a260abc9 | 9971 | (define_insn "*call_nonlocal_aix64" |
cc4d5fec | 9972 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
9973 | (match_operand 1 "" "g")) |
9974 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
9975 | (clobber (match_scratch:SI 3 "=l"))] | |
9ebbca7d GK |
9976 | "TARGET_64BIT |
9977 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 9978 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 9979 | "bl %z0\;%." |
a260abc9 | 9980 | [(set_attr "type" "branch") |
cccf3bdc | 9981 | (set_attr "length" "8")]) |
7509c759 | 9982 | |
cccf3bdc | 9983 | (define_insn "*call_value_indirect_nonlocal_aix32" |
d18dba68 | 9984 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
9985 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) |
9986 | (match_operand 2 "" "g"))) | |
9987 | (use (reg:SI 2)) | |
9988 | (use (reg:SI 11)) | |
9989 | (set (reg:SI 2) | |
9990 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9991 | (clobber (match_scratch:SI 3 "=l"))] | |
9992 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" | |
9993 | "b%T1l\;{l|lwz} 2,20(1)" | |
9994 | [(set_attr "type" "jmpreg") | |
9995 | (set_attr "length" "8")]) | |
1fd4e8c1 | 9996 | |
cccf3bdc | 9997 | (define_insn "*call_value_nonlocal_aix32" |
d18dba68 | 9998 | [(set (match_operand 0 "" "") |
cc4d5fec | 9999 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10000 | (match_operand 2 "" "g"))) |
10001 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10002 | (clobber (match_scratch:SI 4 "=l"))] | |
10003 | "TARGET_32BIT | |
10004 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10005 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 10006 | "bl %z1\;%." |
b7ff3d82 | 10007 | [(set_attr "type" "branch") |
cccf3bdc | 10008 | (set_attr "length" "8")]) |
04780ee7 | 10009 | |
cccf3bdc | 10010 | (define_insn "*call_value_indirect_nonlocal_aix64" |
d18dba68 | 10011 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10012 | (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) |
10013 | (match_operand 2 "" "g"))) | |
10014 | (use (reg:DI 2)) | |
10015 | (use (reg:DI 11)) | |
10016 | (set (reg:DI 2) | |
10017 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10018 | (clobber (match_scratch:SI 3 "=l"))] | |
10019 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" | |
10020 | "b%T1l\;ld 2,40(1)" | |
10021 | [(set_attr "type" "jmpreg") | |
10022 | (set_attr "length" "8")]) | |
10023 | ||
10024 | (define_insn "*call_value_nonlocal_aix64" | |
d18dba68 | 10025 | [(set (match_operand 0 "" "") |
cc4d5fec | 10026 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10027 | (match_operand 2 "" "g"))) |
10028 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10029 | (clobber (match_scratch:SI 4 "=l"))] | |
9ebbca7d GK |
10030 | "TARGET_64BIT |
10031 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10032 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
10033 | "bl %z1\;%." |
10034 | [(set_attr "type" "branch") | |
10035 | (set_attr "length" "8")]) | |
10036 | ||
10037 | ;; A function pointer under System V is just a normal pointer | |
10038 | ;; operands[0] is the function pointer | |
10039 | ;; operands[1] is the stack size to clean up | |
10040 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
10041 | ;; which indicates how to set cr1 | |
10042 | ||
10043 | (define_insn "*call_nonlocal_sysv" | |
10044 | [(call (mem:SI (match_operand:SI 0 "call_operand" "cl,cl,s,s")) | |
10045 | (match_operand 1 "" "g,g,g,g")) | |
10046 | (use (match_operand:SI 2 "immediate_operand" "O,n,O,n")) | |
10047 | (clobber (match_scratch:SI 3 "=l,l,l,l"))] | |
10048 | "DEFAULT_ABI == ABI_AIX_NODESC | |
10049 | || DEFAULT_ABI == ABI_V4 | |
f607bc57 | 10050 | || DEFAULT_ABI == ABI_DARWIN" |
911f679c MM |
10051 | "* |
10052 | { | |
cccf3bdc | 10053 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
6a4cee5f MM |
10054 | output_asm_insn (\"crxor 6,6,6\", operands); |
10055 | ||
cccf3bdc | 10056 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
6a4cee5f | 10057 | output_asm_insn (\"creqv 6,6,6\", operands); |
7509c759 | 10058 | |
cccf3bdc DE |
10059 | switch (which_alternative) |
10060 | { | |
10061 | default: | |
10062 | abort (); | |
10063 | case 0: | |
10064 | case 1: | |
10065 | return \"b%T0l\"; | |
10066 | case 2: | |
10067 | case 3: | |
10068 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\"; | |
10069 | } | |
b6c9286a | 10070 | }" |
cccf3bdc DE |
10071 | [(set_attr "type" "jmpreg,jmpreg,branch,branch") |
10072 | (set_attr "length" "4,8,4,8")]) | |
10073 | ||
10074 | (define_insn "*call_value_nonlocal_sysv" | |
d18dba68 | 10075 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10076 | (call (mem:SI (match_operand:SI 1 "call_operand" "cl,cl,s,s")) |
10077 | (match_operand 2 "" "g,g,g,g"))) | |
10078 | (use (match_operand:SI 3 "immediate_operand" "O,n,O,n")) | |
10079 | (clobber (match_scratch:SI 4 "=l,l,l,l"))] | |
10080 | "DEFAULT_ABI == ABI_AIX_NODESC | |
10081 | || DEFAULT_ABI == ABI_V4 | |
f607bc57 | 10082 | || DEFAULT_ABI == ABI_DARWIN" |
b6c9286a MM |
10083 | "* |
10084 | { | |
6a4cee5f MM |
10085 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
10086 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10087 | ||
10088 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10089 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 10090 | |
cccf3bdc DE |
10091 | switch (which_alternative) |
10092 | { | |
10093 | default: | |
10094 | abort (); | |
10095 | case 0: | |
10096 | case 1: | |
10097 | return \"b%T1l\"; | |
10098 | case 2: | |
10099 | case 3: | |
10100 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\"; | |
10101 | } | |
911f679c | 10102 | }" |
cccf3bdc DE |
10103 | [(set_attr "type" "jmpreg,jmpreg,branch,branch") |
10104 | (set_attr "length" "4,8,4,8")]) | |
e6f948e3 RK |
10105 | |
10106 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
10107 | (define_expand "untyped_call" |
10108 | [(parallel [(call (match_operand 0 "" "") | |
10109 | (const_int 0)) | |
10110 | (match_operand 1 "" "") | |
10111 | (match_operand 2 "" "")])] | |
10112 | "" | |
10113 | " | |
10114 | { | |
10115 | int i; | |
10116 | ||
7d70b8b2 | 10117 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
10118 | |
10119 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10120 | { | |
10121 | rtx set = XVECEXP (operands[2], 0, i); | |
10122 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10123 | } | |
10124 | ||
10125 | /* The optimizer does not know that the call sets the function value | |
10126 | registers we stored in the result block. We avoid problems by | |
10127 | claiming that all hard registers are used and clobbered at this | |
10128 | point. */ | |
10129 | emit_insn (gen_blockage ()); | |
10130 | ||
10131 | DONE; | |
10132 | }") | |
10133 | ||
10134 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
10135 | ;; all of memory. This blocks insns from being moved across this point. | |
10136 | ||
10137 | (define_insn "blockage" | |
10138 | [(unspec_volatile [(const_int 0)] 0)] | |
10139 | "" | |
10140 | "") | |
1fd4e8c1 RK |
10141 | \f |
10142 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 10143 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
10144 | ;; |
10145 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
10146 | ;; insns, and branches. We store the operands of compares until we see | |
10147 | ;; how it is used. | |
10148 | (define_expand "cmpsi" | |
10149 | [(set (cc0) | |
cd2b37d9 | 10150 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10151 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
10152 | "" | |
10153 | " | |
10154 | { | |
10155 | /* Take care of the possibility that operands[1] might be negative but | |
10156 | this might be a logical operation. That insn doesn't exist. */ | |
10157 | if (GET_CODE (operands[1]) == CONST_INT | |
10158 | && INTVAL (operands[1]) < 0) | |
10159 | operands[1] = force_reg (SImode, operands[1]); | |
10160 | ||
10161 | rs6000_compare_op0 = operands[0]; | |
10162 | rs6000_compare_op1 = operands[1]; | |
10163 | rs6000_compare_fp_p = 0; | |
10164 | DONE; | |
10165 | }") | |
10166 | ||
266eb58a DE |
10167 | (define_expand "cmpdi" |
10168 | [(set (cc0) | |
10169 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
10170 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
10171 | "TARGET_POWERPC64" | |
10172 | " | |
10173 | { | |
10174 | /* Take care of the possibility that operands[1] might be negative but | |
10175 | this might be a logical operation. That insn doesn't exist. */ | |
10176 | if (GET_CODE (operands[1]) == CONST_INT | |
10177 | && INTVAL (operands[1]) < 0) | |
10178 | operands[1] = force_reg (DImode, operands[1]); | |
10179 | ||
10180 | rs6000_compare_op0 = operands[0]; | |
10181 | rs6000_compare_op1 = operands[1]; | |
10182 | rs6000_compare_fp_p = 0; | |
10183 | DONE; | |
10184 | }") | |
10185 | ||
1fd4e8c1 | 10186 | (define_expand "cmpsf" |
cd2b37d9 RK |
10187 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
10188 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 10189 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10190 | " |
10191 | { | |
10192 | rs6000_compare_op0 = operands[0]; | |
10193 | rs6000_compare_op1 = operands[1]; | |
10194 | rs6000_compare_fp_p = 1; | |
10195 | DONE; | |
10196 | }") | |
10197 | ||
10198 | (define_expand "cmpdf" | |
cd2b37d9 RK |
10199 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
10200 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 10201 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10202 | " |
10203 | { | |
10204 | rs6000_compare_op0 = operands[0]; | |
10205 | rs6000_compare_op1 = operands[1]; | |
10206 | rs6000_compare_fp_p = 1; | |
10207 | DONE; | |
10208 | }") | |
10209 | ||
d6f99ca4 | 10210 | (define_expand "cmptf" |
e7a4130e DE |
10211 | [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "") |
10212 | (match_operand:TF 1 "gpc_reg_operand" "")))] | |
d6f99ca4 DE |
10213 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" |
10214 | " | |
10215 | { | |
10216 | rs6000_compare_op0 = operands[0]; | |
10217 | rs6000_compare_op1 = operands[1]; | |
10218 | rs6000_compare_fp_p = 1; | |
10219 | DONE; | |
10220 | }") | |
10221 | ||
1fd4e8c1 | 10222 | (define_expand "beq" |
39a10a29 | 10223 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10224 | "" |
39a10a29 | 10225 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10226 | |
10227 | (define_expand "bne" | |
39a10a29 | 10228 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10229 | "" |
39a10a29 | 10230 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 10231 | |
39a10a29 GK |
10232 | (define_expand "bge" |
10233 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10234 | "" |
39a10a29 | 10235 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
10236 | |
10237 | (define_expand "bgt" | |
39a10a29 | 10238 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10239 | "" |
39a10a29 | 10240 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
10241 | |
10242 | (define_expand "ble" | |
39a10a29 | 10243 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10244 | "" |
39a10a29 | 10245 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 10246 | |
39a10a29 GK |
10247 | (define_expand "blt" |
10248 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10249 | "" |
39a10a29 | 10250 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 10251 | |
39a10a29 GK |
10252 | (define_expand "bgeu" |
10253 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10254 | "" |
39a10a29 | 10255 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 10256 | |
39a10a29 GK |
10257 | (define_expand "bgtu" |
10258 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10259 | "" |
39a10a29 | 10260 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 10261 | |
39a10a29 GK |
10262 | (define_expand "bleu" |
10263 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10264 | "" |
39a10a29 | 10265 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 10266 | |
39a10a29 GK |
10267 | (define_expand "bltu" |
10268 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10269 | "" |
39a10a29 | 10270 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 10271 | |
1c882ea4 | 10272 | (define_expand "bunordered" |
39a10a29 | 10273 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10274 | "" |
39a10a29 | 10275 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
10276 | |
10277 | (define_expand "bordered" | |
39a10a29 | 10278 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10279 | "" |
39a10a29 | 10280 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
10281 | |
10282 | (define_expand "buneq" | |
39a10a29 | 10283 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10284 | "" |
39a10a29 | 10285 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
10286 | |
10287 | (define_expand "bunge" | |
39a10a29 | 10288 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10289 | "" |
39a10a29 | 10290 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
10291 | |
10292 | (define_expand "bungt" | |
39a10a29 | 10293 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10294 | "" |
39a10a29 | 10295 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
10296 | |
10297 | (define_expand "bunle" | |
39a10a29 | 10298 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10299 | "" |
39a10a29 | 10300 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
10301 | |
10302 | (define_expand "bunlt" | |
39a10a29 | 10303 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10304 | "" |
39a10a29 | 10305 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
10306 | |
10307 | (define_expand "bltgt" | |
39a10a29 | 10308 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10309 | "" |
39a10a29 | 10310 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 10311 | |
1fd4e8c1 RK |
10312 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
10313 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
10314 | ;; with an scc insns. However, due to the order that combine see the | |
10315 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
10316 | ;; the cases we don't want to handle. | |
10317 | (define_expand "seq" | |
39a10a29 | 10318 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10319 | "" |
39a10a29 | 10320 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10321 | |
10322 | (define_expand "sne" | |
39a10a29 | 10323 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10324 | "" |
10325 | " | |
39a10a29 GK |
10326 | { |
10327 | if (! rs6000_compare_fp_p) | |
1fd4e8c1 RK |
10328 | FAIL; |
10329 | ||
39a10a29 GK |
10330 | rs6000_emit_sCOND (NE, operands[0]); |
10331 | DONE; | |
1fd4e8c1 RK |
10332 | }") |
10333 | ||
10334 | ;; A > 0 is best done using the portable sequence, so fail in that case. | |
10335 | (define_expand "sgt" | |
39a10a29 | 10336 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10337 | "" |
10338 | " | |
5638268e DE |
10339 | { |
10340 | if (! rs6000_compare_fp_p | |
10341 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
10342 | FAIL; |
10343 | ||
39a10a29 GK |
10344 | rs6000_emit_sCOND (GT, operands[0]); |
10345 | DONE; | |
1fd4e8c1 RK |
10346 | }") |
10347 | ||
10348 | ;; A < 0 is best done in the portable way for A an integer. | |
10349 | (define_expand "slt" | |
39a10a29 | 10350 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10351 | "" |
10352 | " | |
5638268e DE |
10353 | { |
10354 | if (! rs6000_compare_fp_p | |
10355 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
10356 | FAIL; |
10357 | ||
39a10a29 GK |
10358 | rs6000_emit_sCOND (LT, operands[0]); |
10359 | DONE; | |
1fd4e8c1 RK |
10360 | }") |
10361 | ||
5638268e | 10362 | ;; A >= 0 is best done the portable way for A an integer. |
1fd4e8c1 | 10363 | (define_expand "sge" |
39a10a29 | 10364 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10365 | "" |
5638268e DE |
10366 | " |
10367 | { | |
10368 | if (! rs6000_compare_fp_p | |
10369 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
10370 | FAIL; | |
10371 | ||
10372 | rs6000_emit_sCOND (GE, operands[0]); | |
10373 | DONE; | |
10374 | }") | |
1fd4e8c1 RK |
10375 | |
10376 | ;; A <= 0 is best done the portable way for A an integer. | |
10377 | (define_expand "sle" | |
39a10a29 | 10378 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10379 | "" |
10380 | " | |
5638268e DE |
10381 | { |
10382 | if (! rs6000_compare_fp_p | |
10383 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
10384 | FAIL; |
10385 | ||
39a10a29 GK |
10386 | rs6000_emit_sCOND (LE, operands[0]); |
10387 | DONE; | |
1fd4e8c1 RK |
10388 | }") |
10389 | ||
10390 | (define_expand "sgtu" | |
39a10a29 | 10391 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10392 | "" |
39a10a29 | 10393 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10394 | |
10395 | (define_expand "sltu" | |
39a10a29 | 10396 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10397 | "" |
39a10a29 | 10398 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10399 | |
10400 | (define_expand "sgeu" | |
39a10a29 | 10401 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10402 | "" |
39a10a29 | 10403 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10404 | |
10405 | (define_expand "sleu" | |
39a10a29 | 10406 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10407 | "" |
39a10a29 | 10408 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10409 | \f |
10410 | ;; Here are the actual compare insns. | |
acad7ed3 | 10411 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 10412 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 10413 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
10414 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
10415 | "" | |
7f340546 | 10416 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
1fd4e8c1 RK |
10417 | [(set_attr "type" "compare")]) |
10418 | ||
acad7ed3 | 10419 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
10420 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
10421 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
10422 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
10423 | "TARGET_POWERPC64" | |
10424 | "cmpd%I2 %0,%1,%2" | |
10425 | [(set_attr "type" "compare")]) | |
10426 | ||
f357808b RK |
10427 | ;; If we are comparing a register for equality with a large constant, |
10428 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
10429 | ;; register for the result of the XOR. | |
10430 | ||
10431 | (define_split | |
10432 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 10433 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 10434 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 10435 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
10436 | "find_single_use (operands[0], insn, 0) |
10437 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
10438 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
10439 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
10440 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
10441 | " | |
10442 | { | |
10443 | /* Get the constant we are comparing against, C, and see what it looks like | |
10444 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
10445 | with C to get the sign-extended value. */ | |
10446 | ||
5f59ecb7 | 10447 | HOST_WIDE_INT c = INTVAL (operands[2]); |
a65c591c | 10448 | HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; |
5f59ecb7 | 10449 | HOST_WIDE_INT xorv = c ^ sextc; |
f357808b | 10450 | |
89e9f3a8 MM |
10451 | operands[4] = GEN_INT (xorv); |
10452 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
10453 | }") |
10454 | ||
acad7ed3 | 10455 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 10456 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 10457 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 10458 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 10459 | "" |
e2c953b6 | 10460 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
1fd4e8c1 RK |
10461 | [(set_attr "type" "compare")]) |
10462 | ||
acad7ed3 | 10463 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
10464 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
10465 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 10466 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 10467 | "" |
e2c953b6 | 10468 | "cmpld%I2 %0,%1,%b2" |
266eb58a DE |
10469 | [(set_attr "type" "compare")]) |
10470 | ||
1fd4e8c1 RK |
10471 | ;; The following two insns don't exist as single insns, but if we provide |
10472 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
10473 | ;; of the required delay between a compare and branch. We generate code for | |
10474 | ;; them by splitting. | |
10475 | ||
10476 | (define_insn "" | |
10477 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 10478 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10479 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 10480 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10481 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
10482 | "" | |
baf97f86 RK |
10483 | "#" |
10484 | [(set_attr "length" "8")]) | |
7e69e155 | 10485 | |
1fd4e8c1 RK |
10486 | (define_insn "" |
10487 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 10488 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10489 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 10490 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10491 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
10492 | "" | |
baf97f86 RK |
10493 | "#" |
10494 | [(set_attr "length" "8")]) | |
7e69e155 | 10495 | |
1fd4e8c1 RK |
10496 | (define_split |
10497 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 10498 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10499 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 10500 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10501 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10502 | "" | |
10503 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
10504 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10505 | ||
10506 | (define_split | |
10507 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 10508 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10509 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 10510 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10511 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10512 | "" | |
10513 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
10514 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10515 | ||
acad7ed3 | 10516 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 10517 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10518 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
10519 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 10520 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10521 | "fcmpu %0,%1,%2" |
10522 | [(set_attr "type" "fpcompare")]) | |
10523 | ||
acad7ed3 | 10524 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 10525 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10526 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
10527 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 10528 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10529 | "fcmpu %0,%1,%2" |
10530 | [(set_attr "type" "fpcompare")]) | |
d6f99ca4 DE |
10531 | |
10532 | ;; Only need to compare second words if first words equal | |
10533 | (define_insn "*cmptf_internal1" | |
10534 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
10535 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
10536 | (match_operand:TF 2 "gpc_reg_operand" "f")))] | |
10537 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
2e7d5318 | 10538 | "fcmpu %0,%1,%2\;bne %0,$+4\;fcmpu %0,%L1,%L2" |
d6f99ca4 DE |
10539 | [(set_attr "type" "fpcompare") |
10540 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
10541 | \f |
10542 | ;; Now we have the scc insns. We can do some combinations because of the | |
10543 | ;; way the machine works. | |
10544 | ;; | |
10545 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
10546 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
10547 | ;; cases the insns below which don't use an intermediate CR field will | |
10548 | ;; be used instead. | |
1fd4e8c1 | 10549 | (define_insn "" |
cd2b37d9 | 10550 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10551 | (match_operator:SI 1 "scc_comparison_operator" |
10552 | [(match_operand 2 "cc_reg_operand" "y") | |
10553 | (const_int 0)]))] | |
10554 | "" | |
ca7f5001 | 10555 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" |
b19003d8 | 10556 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10557 | |
10558 | (define_insn "" | |
9ebbca7d GK |
10559 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
10560 | (match_operator:DI 1 "scc_comparison_operator" | |
10561 | [(match_operand 2 "cc_reg_operand" "y") | |
10562 | (const_int 0)]))] | |
10563 | "TARGET_POWERPC64" | |
10564 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" | |
10565 | [(set_attr "length" "12")]) | |
10566 | ||
10567 | (define_insn "" | |
10568 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 10569 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 10570 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
10571 | (const_int 0)]) |
10572 | (const_int 0))) | |
9ebbca7d | 10573 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10574 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
0ad91047 | 10575 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10576 | "@ |
10577 | %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1 | |
10578 | #" | |
b19003d8 | 10579 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
10580 | (set_attr "length" "12,16")]) |
10581 | ||
10582 | (define_split | |
10583 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10584 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
10585 | [(match_operand 2 "cc_reg_operand" "") | |
10586 | (const_int 0)]) | |
10587 | (const_int 0))) | |
10588 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
10589 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
10590 | "! TARGET_POWERPC64 && reload_completed" | |
10591 | [(set (match_dup 3) | |
10592 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
10593 | (set (match_dup 0) | |
10594 | (compare:CC (match_dup 3) | |
10595 | (const_int 0)))] | |
10596 | "") | |
1fd4e8c1 RK |
10597 | |
10598 | (define_insn "" | |
cd2b37d9 | 10599 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10600 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
10601 | [(match_operand 2 "cc_reg_operand" "y") | |
10602 | (const_int 0)]) | |
10603 | (match_operand:SI 3 "const_int_operand" "n")))] | |
10604 | "" | |
10605 | "* | |
10606 | { | |
10607 | int is_bit = ccr_bit (operands[1], 1); | |
10608 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
10609 | int count; | |
10610 | ||
10611 | if (is_bit >= put_bit) | |
10612 | count = is_bit - put_bit; | |
10613 | else | |
10614 | count = 32 - (put_bit - is_bit); | |
10615 | ||
89e9f3a8 MM |
10616 | operands[4] = GEN_INT (count); |
10617 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 10618 | |
ca7f5001 | 10619 | return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 RK |
10620 | }" |
10621 | [(set_attr "length" "12")]) | |
1fd4e8c1 RK |
10622 | |
10623 | (define_insn "" | |
9ebbca7d | 10624 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10625 | (compare:CC |
10626 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 10627 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 10628 | (const_int 0)]) |
9ebbca7d | 10629 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 10630 | (const_int 0))) |
9ebbca7d | 10631 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
10632 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
10633 | (match_dup 3)))] | |
9ebbca7d | 10634 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
10635 | "* |
10636 | { | |
10637 | int is_bit = ccr_bit (operands[1], 1); | |
10638 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
10639 | int count; | |
10640 | ||
9ebbca7d GK |
10641 | /* Force split for non-cc0 compare. */ |
10642 | if (which_alternative == 1) | |
10643 | return \"#\"; | |
10644 | ||
1fd4e8c1 RK |
10645 | if (is_bit >= put_bit) |
10646 | count = is_bit - put_bit; | |
10647 | else | |
10648 | count = 32 - (put_bit - is_bit); | |
10649 | ||
89e9f3a8 MM |
10650 | operands[5] = GEN_INT (count); |
10651 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 10652 | |
ca7f5001 | 10653 | return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 10654 | }" |
b19003d8 | 10655 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
10656 | (set_attr "length" "12,16")]) |
10657 | ||
10658 | (define_split | |
10659 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10660 | (compare:CC | |
10661 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
10662 | [(match_operand 2 "cc_reg_operand" "") | |
10663 | (const_int 0)]) | |
10664 | (match_operand:SI 3 "const_int_operand" "")) | |
10665 | (const_int 0))) | |
10666 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
10667 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
10668 | (match_dup 3)))] | |
10669 | "! TARGET_POWERPC64 && reload_completed" | |
10670 | [(set (match_dup 4) | |
10671 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
10672 | (match_dup 3))) | |
10673 | (set (match_dup 0) | |
10674 | (compare:CC (match_dup 4) | |
10675 | (const_int 0)))] | |
10676 | "") | |
1fd4e8c1 | 10677 | |
c5defebb RK |
10678 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
10679 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
10680 | ||
10681 | (define_peephole | |
cd2b37d9 | 10682 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
10683 | (match_operator:SI 1 "scc_comparison_operator" |
10684 | [(match_operand 2 "cc_reg_operand" "y") | |
10685 | (const_int 0)])) | |
cd2b37d9 | 10686 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
10687 | (match_operator:SI 4 "scc_comparison_operator" |
10688 | [(match_operand 5 "cc_reg_operand" "y") | |
10689 | (const_int 0)]))] | |
10690 | "REGNO (operands[2]) != REGNO (operands[5])" | |
ca7f5001 | 10691 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b19003d8 | 10692 | [(set_attr "length" "20")]) |
c5defebb | 10693 | |
9ebbca7d GK |
10694 | (define_peephole |
10695 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10696 | (match_operator:DI 1 "scc_comparison_operator" | |
10697 | [(match_operand 2 "cc_reg_operand" "y") | |
10698 | (const_int 0)])) | |
10699 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
10700 | (match_operator:DI 4 "scc_comparison_operator" | |
10701 | [(match_operand 5 "cc_reg_operand" "y") | |
10702 | (const_int 0)]))] | |
10703 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" | |
10704 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" | |
10705 | [(set_attr "length" "20")]) | |
10706 | ||
1fd4e8c1 RK |
10707 | ;; There are some scc insns that can be done directly, without a compare. |
10708 | ;; These are faster because they don't involve the communications between | |
10709 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
10710 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
10711 | ;; | |
10712 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
10713 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
10714 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
10715 | ;; cases where it is no more expensive than (neg (scc ..)). | |
10716 | ||
10717 | ;; Have reload force a constant into a register for the simple insns that | |
10718 | ;; otherwise won't accept constants. We do this because it is faster than | |
10719 | ;; the cmp/mfcr sequence we would otherwise generate. | |
10720 | ||
10721 | (define_insn "" | |
cd2b37d9 RK |
10722 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
10723 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 10724 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 10725 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
f9562f27 | 10726 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10727 | "@ |
ca7f5001 | 10728 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 10729 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
10730 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
10731 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
10732 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 10733 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 10734 | |
a260abc9 DE |
10735 | (define_insn "" |
10736 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
10737 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
10738 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
10739 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
10740 | "TARGET_POWERPC64" | |
10741 | "@ | |
10742 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
10743 | subfic %3,%1,0\;adde %0,%3,%1 | |
10744 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
10745 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
10746 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
10747 | [(set_attr "length" "12,8,12,12,12")]) | |
10748 | ||
1fd4e8c1 | 10749 | (define_insn "" |
9ebbca7d | 10750 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 10751 | (compare:CC |
9ebbca7d GK |
10752 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10753 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 10754 | (const_int 0))) |
9ebbca7d | 10755 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 10756 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 10757 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
f9562f27 | 10758 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10759 | "@ |
ca7f5001 RK |
10760 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
10761 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
10762 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
10763 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
10764 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
10765 | # | |
10766 | # | |
10767 | # | |
10768 | # | |
10769 | #" | |
b19003d8 | 10770 | [(set_attr "type" "compare") |
9ebbca7d GK |
10771 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
10772 | ||
10773 | (define_split | |
10774 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10775 | (compare:CC | |
10776 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10777 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
10778 | (const_int 0))) | |
10779 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10780 | (eq:SI (match_dup 1) (match_dup 2))) | |
10781 | (clobber (match_scratch:SI 3 ""))] | |
10782 | "! TARGET_POWERPC64 && reload_completed" | |
10783 | [(parallel [(set (match_dup 0) | |
10784 | (eq:SI (match_dup 1) (match_dup 2))) | |
10785 | (clobber (match_dup 3))]) | |
10786 | (set (match_dup 4) | |
10787 | (compare:CC (match_dup 0) | |
10788 | (const_int 0)))] | |
10789 | "") | |
b19003d8 | 10790 | |
a260abc9 | 10791 | (define_insn "" |
9ebbca7d | 10792 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 10793 | (compare:CC |
9ebbca7d GK |
10794 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10795 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 10796 | (const_int 0))) |
9ebbca7d | 10797 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 10798 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 10799 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
a260abc9 DE |
10800 | "TARGET_POWERPC64" |
10801 | "@ | |
10802 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
10803 | subfic %3,%1,0\;adde. %0,%3,%1 | |
10804 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
10805 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
10806 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
10807 | # | |
10808 | # | |
10809 | # | |
10810 | # | |
10811 | #" | |
a260abc9 | 10812 | [(set_attr "type" "compare") |
9ebbca7d GK |
10813 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
10814 | ||
10815 | (define_split | |
10816 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10817 | (compare:CC | |
10818 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
10819 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
10820 | (const_int 0))) | |
10821 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
10822 | (eq:DI (match_dup 1) (match_dup 2))) | |
10823 | (clobber (match_scratch:DI 3 ""))] | |
10824 | "TARGET_POWERPC64 && reload_completed" | |
10825 | [(parallel [(set (match_dup 0) | |
10826 | (eq:DI (match_dup 1) (match_dup 2))) | |
10827 | (clobber (match_dup 3))]) | |
10828 | (set (match_dup 4) | |
10829 | (compare:CC (match_dup 0) | |
10830 | (const_int 0)))] | |
10831 | "") | |
a260abc9 | 10832 | |
b19003d8 RK |
10833 | ;; We have insns of the form shown by the first define_insn below. If |
10834 | ;; there is something inside the comparison operation, we must split it. | |
10835 | (define_split | |
10836 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
10837 | (plus:SI (match_operator 1 "comparison_operator" | |
10838 | [(match_operand:SI 2 "" "") | |
10839 | (match_operand:SI 3 | |
10840 | "reg_or_cint_operand" "")]) | |
10841 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
10842 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
10843 | "! gpc_reg_operand (operands[2], SImode)" | |
10844 | [(set (match_dup 5) (match_dup 2)) | |
10845 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
10846 | (match_dup 4)))]) | |
1fd4e8c1 RK |
10847 | |
10848 | (define_insn "" | |
5276df18 | 10849 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") |
cd2b37d9 | 10850 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 10851 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
5276df18 | 10852 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] |
f9562f27 | 10853 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10854 | "@ |
5276df18 DE |
10855 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
10856 | {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 | |
10857 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
10858 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
10859 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" | |
b19003d8 | 10860 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
10861 | |
10862 | (define_insn "" | |
9ebbca7d | 10863 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 10864 | (compare:CC |
1fd4e8c1 | 10865 | (plus:SI |
9ebbca7d GK |
10866 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10867 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
10868 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 10869 | (const_int 0))) |
9ebbca7d | 10870 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 10871 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10872 | "@ |
ca7f5001 | 10873 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 10874 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
10875 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
10876 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
10877 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
10878 | # | |
10879 | # | |
10880 | # | |
10881 | # | |
10882 | #" | |
b19003d8 | 10883 | [(set_attr "type" "compare") |
9ebbca7d GK |
10884 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
10885 | ||
10886 | (define_split | |
10887 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10888 | (compare:CC | |
10889 | (plus:SI | |
10890 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10891 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
10892 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10893 | (const_int 0))) | |
10894 | (clobber (match_scratch:SI 4 ""))] | |
10895 | "! TARGET_POWERPC64 && reload_completed" | |
10896 | [(set (match_dup 4) | |
10897 | (plus:SI (eq:SI (match_dup 1) | |
10898 | (match_dup 2)) | |
10899 | (match_dup 3))) | |
10900 | (set (match_dup 0) | |
10901 | (compare:CC (match_dup 4) | |
10902 | (const_int 0)))] | |
10903 | "") | |
1fd4e8c1 RK |
10904 | |
10905 | (define_insn "" | |
9ebbca7d | 10906 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 10907 | (compare:CC |
1fd4e8c1 | 10908 | (plus:SI |
9ebbca7d GK |
10909 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10910 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
10911 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 10912 | (const_int 0))) |
9ebbca7d | 10913 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 10914 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 10915 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 10916 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10917 | "@ |
ca7f5001 | 10918 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
19378cf8 | 10919 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3 |
ca7f5001 RK |
10920 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
10921 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
10922 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
10923 | # | |
10924 | # | |
10925 | # | |
10926 | # | |
10927 | #" | |
10928 | [(set_attr "type" "compare") | |
10929 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
10930 | ||
10931 | (define_split | |
10932 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
10933 | (compare:CC | |
10934 | (plus:SI | |
10935 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10936 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
10937 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10938 | (const_int 0))) | |
10939 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10940 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10941 | (clobber (match_scratch:SI 4 ""))] | |
10942 | "! TARGET_POWERPC64 && reload_completed" | |
10943 | [(parallel [(set (match_dup 0) | |
10944 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10945 | (clobber (match_dup 4))]) | |
10946 | (set (match_dup 5) | |
10947 | (compare:CC (match_dup 0) | |
10948 | (const_int 0)))] | |
10949 | "") | |
10950 | ||
1fd4e8c1 | 10951 | (define_insn "" |
cd2b37d9 | 10952 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 10953 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 10954 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
f9562f27 | 10955 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10956 | "@ |
ca7f5001 RK |
10957 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
10958 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
10959 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
10960 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
10961 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 10962 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 10963 | |
ea9be077 MM |
10964 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
10965 | ;; since it nabs/sr is just as fast. | |
463b558b | 10966 | (define_insn "*ne0" |
b4e95693 | 10967 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
10968 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
10969 | (const_int 31))) | |
10970 | (clobber (match_scratch:SI 2 "=&r"))] | |
9ebbca7d | 10971 | "! TARGET_POWER && ! TARGET_POWERPC64" |
ea9be077 MM |
10972 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
10973 | [(set_attr "length" "8")]) | |
10974 | ||
a260abc9 DE |
10975 | (define_insn "" |
10976 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10977 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
10978 | (const_int 63))) | |
10979 | (clobber (match_scratch:DI 2 "=&r"))] | |
10980 | "TARGET_POWERPC64" | |
10981 | "addic %2,%1,-1\;subfe %0,%2,%1" | |
10982 | [(set_attr "length" "8")]) | |
10983 | ||
1fd4e8c1 RK |
10984 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
10985 | (define_insn "" | |
cd2b37d9 | 10986 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 10987 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 10988 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10989 | (const_int 31)) |
cd2b37d9 | 10990 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10991 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 10992 | "! TARGET_POWERPC64" |
ca7f5001 | 10993 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 10994 | [(set_attr "length" "8")]) |
1fd4e8c1 | 10995 | |
a260abc9 DE |
10996 | (define_insn "" |
10997 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10998 | (plus:DI (lshiftrt:DI | |
10999 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11000 | (const_int 63)) | |
11001 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11002 | (clobber (match_scratch:DI 3 "=&r"))] | |
11003 | "TARGET_POWERPC64" | |
11004 | "addic %3,%1,-1\;addze %0,%2" | |
11005 | [(set_attr "length" "8")]) | |
11006 | ||
1fd4e8c1 | 11007 | (define_insn "" |
9ebbca7d | 11008 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11009 | (compare:CC |
11010 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11011 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11012 | (const_int 31)) |
9ebbca7d | 11013 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11014 | (const_int 0))) |
889b90a1 GK |
11015 | (clobber (match_scratch:SI 3 "=&r,&r")) |
11016 | (clobber (match_scratch:SI 4 "=X,&r"))] | |
f9562f27 | 11017 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11018 | "@ |
11019 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
11020 | #" | |
b19003d8 | 11021 | [(set_attr "type" "compare") |
9ebbca7d GK |
11022 | (set_attr "length" "8,12")]) |
11023 | ||
11024 | (define_split | |
11025 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11026 | (compare:CC | |
11027 | (plus:SI (lshiftrt:SI | |
11028 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11029 | (const_int 31)) | |
11030 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11031 | (const_int 0))) | |
889b90a1 GK |
11032 | (clobber (match_scratch:SI 3 "")) |
11033 | (clobber (match_scratch:SI 4 ""))] | |
9ebbca7d | 11034 | "! TARGET_POWERPC64 && reload_completed" |
889b90a1 GK |
11035 | [(parallel [(set (match_dup 3) |
11036 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) | |
11037 | (const_int 31)) | |
11038 | (match_dup 2))) | |
11039 | (clobber (match_dup 4))]) | |
9ebbca7d GK |
11040 | (set (match_dup 0) |
11041 | (compare:CC (match_dup 3) | |
11042 | (const_int 0)))] | |
11043 | "") | |
1fd4e8c1 | 11044 | |
a260abc9 | 11045 | (define_insn "" |
9ebbca7d | 11046 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11047 | (compare:CC |
11048 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11049 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11050 | (const_int 63)) |
9ebbca7d | 11051 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11052 | (const_int 0))) |
9ebbca7d | 11053 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 11054 | "TARGET_POWERPC64" |
9ebbca7d GK |
11055 | "@ |
11056 | addic %3,%1,-1\;addze. %3,%2 | |
11057 | #" | |
a260abc9 | 11058 | [(set_attr "type" "compare") |
9ebbca7d GK |
11059 | (set_attr "length" "8,12")]) |
11060 | ||
11061 | (define_split | |
11062 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11063 | (compare:CC | |
11064 | (plus:DI (lshiftrt:DI | |
11065 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11066 | (const_int 63)) | |
11067 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11068 | (const_int 0))) | |
11069 | (clobber (match_scratch:DI 3 ""))] | |
11070 | "TARGET_POWERPC64 && reload_completed" | |
11071 | [(set (match_dup 3) | |
11072 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
11073 | (const_int 63)) | |
11074 | (match_dup 2))) | |
11075 | (set (match_dup 0) | |
11076 | (compare:CC (match_dup 3) | |
11077 | (const_int 0)))] | |
11078 | "") | |
a260abc9 | 11079 | |
1fd4e8c1 | 11080 | (define_insn "" |
9ebbca7d | 11081 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11082 | (compare:CC |
11083 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11084 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11085 | (const_int 31)) |
9ebbca7d | 11086 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11087 | (const_int 0))) |
9ebbca7d | 11088 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11089 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
11090 | (match_dup 2))) | |
9ebbca7d | 11091 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 11092 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11093 | "@ |
11094 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
11095 | #" | |
b19003d8 | 11096 | [(set_attr "type" "compare") |
9ebbca7d GK |
11097 | (set_attr "length" "8,12")]) |
11098 | ||
11099 | (define_split | |
11100 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11101 | (compare:CC | |
11102 | (plus:SI (lshiftrt:SI | |
11103 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11104 | (const_int 31)) | |
11105 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11106 | (const_int 0))) | |
11107 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11108 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11109 | (match_dup 2))) | |
11110 | (clobber (match_scratch:SI 3 ""))] | |
11111 | "! TARGET_POWERPC64 && reload_completed" | |
11112 | [(parallel [(set (match_dup 0) | |
11113 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11114 | (match_dup 2))) | |
11115 | (clobber (match_dup 3))]) | |
11116 | (set (match_dup 4) | |
11117 | (compare:CC (match_dup 0) | |
11118 | (const_int 0)))] | |
11119 | "") | |
1fd4e8c1 | 11120 | |
a260abc9 | 11121 | (define_insn "" |
9ebbca7d | 11122 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11123 | (compare:CC |
11124 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11125 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11126 | (const_int 63)) |
9ebbca7d | 11127 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11128 | (const_int 0))) |
9ebbca7d | 11129 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
11130 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
11131 | (match_dup 2))) | |
9ebbca7d | 11132 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 11133 | "TARGET_POWERPC64" |
9ebbca7d GK |
11134 | "@ |
11135 | addic %3,%1,-1\;addze. %0,%2 | |
11136 | #" | |
a260abc9 | 11137 | [(set_attr "type" "compare") |
9ebbca7d GK |
11138 | (set_attr "length" "8,12")]) |
11139 | ||
11140 | (define_split | |
11141 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11142 | (compare:CC | |
11143 | (plus:DI (lshiftrt:DI | |
11144 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11145 | (const_int 63)) | |
11146 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11147 | (const_int 0))) | |
11148 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11149 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11150 | (match_dup 2))) | |
11151 | (clobber (match_scratch:DI 3 ""))] | |
11152 | "TARGET_POWERPC64 && reload_completed" | |
11153 | [(parallel [(set (match_dup 0) | |
11154 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11155 | (match_dup 2))) | |
11156 | (clobber (match_dup 3))]) | |
11157 | (set (match_dup 4) | |
11158 | (compare:CC (match_dup 0) | |
11159 | (const_int 0)))] | |
11160 | "") | |
a260abc9 | 11161 | |
1fd4e8c1 | 11162 | (define_insn "" |
cd2b37d9 RK |
11163 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11164 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
11165 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
11166 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 11167 | "TARGET_POWER" |
1fd4e8c1 | 11168 | "@ |
ca7f5001 | 11169 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 11170 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11171 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11172 | |
11173 | (define_insn "" | |
9ebbca7d | 11174 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11175 | (compare:CC |
9ebbca7d GK |
11176 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11177 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 11178 | (const_int 0))) |
9ebbca7d | 11179 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11180 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11181 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 11182 | "TARGET_POWER" |
1fd4e8c1 | 11183 | "@ |
ca7f5001 | 11184 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
11185 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
11186 | # | |
11187 | #" | |
11188 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
11189 | (set_attr "length" "12,12,16,16")]) | |
11190 | ||
11191 | (define_split | |
11192 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11193 | (compare:CC | |
11194 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11195 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11196 | (const_int 0))) | |
11197 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11198 | (le:SI (match_dup 1) (match_dup 2))) | |
11199 | (clobber (match_scratch:SI 3 ""))] | |
11200 | "TARGET_POWER && reload_completed" | |
11201 | [(parallel [(set (match_dup 0) | |
11202 | (le:SI (match_dup 1) (match_dup 2))) | |
11203 | (clobber (match_dup 3))]) | |
11204 | (set (match_dup 4) | |
11205 | (compare:CC (match_dup 0) | |
11206 | (const_int 0)))] | |
11207 | "") | |
1fd4e8c1 RK |
11208 | |
11209 | (define_insn "" | |
cd2b37d9 RK |
11210 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11211 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11212 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
cd2b37d9 | 11213 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11214 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11215 | "TARGET_POWER" |
1fd4e8c1 | 11216 | "@ |
ca7f5001 RK |
11217 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
11218 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" | |
b19003d8 | 11219 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11220 | |
11221 | (define_insn "" | |
9ebbca7d | 11222 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11223 | (compare:CC |
9ebbca7d GK |
11224 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11225 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
11226 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11227 | (const_int 0))) |
9ebbca7d | 11228 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 11229 | "TARGET_POWER" |
1fd4e8c1 | 11230 | "@ |
ca7f5001 | 11231 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
11232 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
11233 | # | |
11234 | #" | |
b19003d8 | 11235 | [(set_attr "type" "compare") |
9ebbca7d GK |
11236 | (set_attr "length" "12,12,16,16")]) |
11237 | ||
11238 | (define_split | |
11239 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11240 | (compare:CC | |
11241 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11242 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11243 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11244 | (const_int 0))) | |
11245 | (clobber (match_scratch:SI 4 ""))] | |
11246 | "TARGET_POWER && reload_completed" | |
11247 | [(set (match_dup 4) | |
11248 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
11249 | (match_dup 3))) | |
11250 | (set (match_dup 0) | |
11251 | (compare:CC (match_dup 4) | |
11252 | (const_int 0)))] | |
11253 | "") | |
1fd4e8c1 RK |
11254 | |
11255 | (define_insn "" | |
9ebbca7d | 11256 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11257 | (compare:CC |
9ebbca7d GK |
11258 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11259 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
11260 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11261 | (const_int 0))) |
9ebbca7d | 11262 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11263 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11264 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 11265 | "TARGET_POWER" |
1fd4e8c1 | 11266 | "@ |
ca7f5001 | 11267 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
11268 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3 |
11269 | # | |
11270 | #" | |
b19003d8 | 11271 | [(set_attr "type" "compare") |
9ebbca7d GK |
11272 | (set_attr "length" "12,12,16,16")]) |
11273 | ||
11274 | (define_split | |
11275 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11276 | (compare:CC | |
11277 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11278 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11279 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11280 | (const_int 0))) | |
11281 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11282 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11283 | (clobber (match_scratch:SI 4 ""))] | |
11284 | "TARGET_POWER && reload_completed" | |
11285 | [(parallel [(set (match_dup 0) | |
11286 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11287 | (clobber (match_dup 4))]) | |
11288 | (set (match_dup 5) | |
11289 | (compare:CC (match_dup 0) | |
11290 | (const_int 0)))] | |
11291 | "") | |
1fd4e8c1 RK |
11292 | |
11293 | (define_insn "" | |
cd2b37d9 RK |
11294 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11295 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11296 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 11297 | "TARGET_POWER" |
1fd4e8c1 | 11298 | "@ |
ca7f5001 RK |
11299 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11300 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 11301 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11302 | |
11303 | (define_insn "" | |
cd2b37d9 RK |
11304 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11305 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11306 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 11307 | "! TARGET_POWERPC64" |
ca7f5001 | 11308 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 11309 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11310 | |
f9562f27 DE |
11311 | (define_insn "" |
11312 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11313 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
11314 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
11315 | "TARGET_POWERPC64" | |
11316 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" | |
11317 | [(set_attr "length" "12")]) | |
11318 | ||
11319 | (define_insn "" | |
9ebbca7d | 11320 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 11321 | (compare:CC |
9ebbca7d GK |
11322 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
11323 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 11324 | (const_int 0))) |
9ebbca7d | 11325 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
11326 | (leu:DI (match_dup 1) (match_dup 2)))] |
11327 | "TARGET_POWERPC64" | |
9ebbca7d GK |
11328 | "@ |
11329 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
11330 | #" | |
f9562f27 | 11331 | [(set_attr "type" "compare") |
9ebbca7d GK |
11332 | (set_attr "length" "12,16")]) |
11333 | ||
11334 | (define_split | |
11335 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11336 | (compare:CC | |
11337 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11338 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
11339 | (const_int 0))) | |
11340 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11341 | (leu:DI (match_dup 1) (match_dup 2)))] | |
11342 | "TARGET_POWERPC64 && reload_completed" | |
11343 | [(set (match_dup 0) | |
11344 | (leu:DI (match_dup 1) (match_dup 2))) | |
11345 | (set (match_dup 3) | |
11346 | (compare:CC (match_dup 0) | |
11347 | (const_int 0)))] | |
11348 | "") | |
f9562f27 | 11349 | |
1fd4e8c1 | 11350 | (define_insn "" |
9ebbca7d | 11351 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11352 | (compare:CC |
9ebbca7d GK |
11353 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11354 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11355 | (const_int 0))) |
9ebbca7d | 11356 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11357 | (leu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11358 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11359 | "@ |
11360 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
11361 | #" | |
b19003d8 | 11362 | [(set_attr "type" "compare") |
9ebbca7d GK |
11363 | (set_attr "length" "12,16")]) |
11364 | ||
11365 | (define_split | |
11366 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11367 | (compare:CC | |
11368 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11369 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11370 | (const_int 0))) | |
11371 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11372 | (leu:SI (match_dup 1) (match_dup 2)))] | |
11373 | "! TARGET_POWERPC64 && reload_completed" | |
11374 | [(set (match_dup 0) | |
11375 | (leu:SI (match_dup 1) (match_dup 2))) | |
11376 | (set (match_dup 3) | |
11377 | (compare:CC (match_dup 0) | |
11378 | (const_int 0)))] | |
11379 | "") | |
1fd4e8c1 | 11380 | |
f9562f27 | 11381 | (define_insn "" |
9ebbca7d | 11382 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 11383 | (compare:CC |
9ebbca7d GK |
11384 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
11385 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 11386 | (const_int 0))) |
9ebbca7d | 11387 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
11388 | (leu:DI (match_dup 1) (match_dup 2)))] |
11389 | "TARGET_POWERPC64" | |
9ebbca7d GK |
11390 | "@ |
11391 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
11392 | #" | |
f9562f27 | 11393 | [(set_attr "type" "compare") |
9ebbca7d | 11394 | (set_attr "length" "12,16")]) |
f9562f27 | 11395 | |
1fd4e8c1 | 11396 | (define_insn "" |
cd2b37d9 RK |
11397 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11398 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11399 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 11400 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11401 | (clobber (match_scratch:SI 4 "=&r"))] |
f9562f27 | 11402 | "! TARGET_POWERPC64" |
ca7f5001 | 11403 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 11404 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
11405 | |
11406 | (define_insn "" | |
9ebbca7d | 11407 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11408 | (compare:CC |
9ebbca7d GK |
11409 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11410 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11411 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11412 | (const_int 0))) |
9ebbca7d | 11413 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11414 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11415 | "@ |
11416 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
11417 | #" | |
b19003d8 | 11418 | [(set_attr "type" "compare") |
9ebbca7d GK |
11419 | (set_attr "length" "8,12")]) |
11420 | ||
11421 | (define_split | |
11422 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11423 | (compare:CC | |
11424 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11425 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11426 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11427 | (const_int 0))) | |
11428 | (clobber (match_scratch:SI 4 ""))] | |
11429 | "! TARGET_POWERPC64 && reload_completed" | |
11430 | [(set (match_dup 4) | |
11431 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
11432 | (match_dup 3))) | |
11433 | (set (match_dup 0) | |
11434 | (compare:CC (match_dup 4) | |
11435 | (const_int 0)))] | |
11436 | "") | |
1fd4e8c1 RK |
11437 | |
11438 | (define_insn "" | |
9ebbca7d | 11439 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11440 | (compare:CC |
9ebbca7d GK |
11441 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11442 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11443 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11444 | (const_int 0))) |
9ebbca7d | 11445 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11446 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11447 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11448 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11449 | "@ |
11450 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3 | |
11451 | #" | |
b19003d8 | 11452 | [(set_attr "type" "compare") |
9ebbca7d GK |
11453 | (set_attr "length" "8,12")]) |
11454 | ||
11455 | (define_split | |
11456 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11457 | (compare:CC | |
11458 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11459 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11460 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11461 | (const_int 0))) | |
11462 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11463 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11464 | (clobber (match_scratch:SI 4 ""))] | |
11465 | "! TARGET_POWERPC64 && reload_completed" | |
11466 | [(parallel [(set (match_dup 0) | |
11467 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11468 | (clobber (match_dup 4))]) | |
11469 | (set (match_dup 5) | |
11470 | (compare:CC (match_dup 0) | |
11471 | (const_int 0)))] | |
11472 | "") | |
1fd4e8c1 RK |
11473 | |
11474 | (define_insn "" | |
cd2b37d9 RK |
11475 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11476 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11477 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 11478 | "! TARGET_POWERPC64" |
ca7f5001 | 11479 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 11480 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11481 | |
11482 | (define_insn "" | |
cd2b37d9 | 11483 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 11484 | (and:SI (neg:SI |
cd2b37d9 | 11485 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11486 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
cd2b37d9 | 11487 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11488 | (clobber (match_scratch:SI 4 "=&r"))] |
f9562f27 | 11489 | "! TARGET_POWERPC64" |
ca7f5001 | 11490 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" |
b19003d8 | 11491 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11492 | |
11493 | (define_insn "" | |
9ebbca7d | 11494 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11495 | (compare:CC |
11496 | (and:SI (neg:SI | |
9ebbca7d GK |
11497 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11498 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11499 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11500 | (const_int 0))) |
9ebbca7d | 11501 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11502 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11503 | "@ |
11504 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
11505 | #" | |
11506 | [(set_attr "type" "compare") | |
11507 | (set_attr "length" "12,16")]) | |
11508 | ||
11509 | (define_split | |
11510 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11511 | (compare:CC | |
11512 | (and:SI (neg:SI | |
11513 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11514 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11515 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11516 | (const_int 0))) | |
11517 | (clobber (match_scratch:SI 4 ""))] | |
11518 | "! TARGET_POWERPC64 && reload_completed" | |
11519 | [(set (match_dup 4) | |
11520 | (and:SI (neg:SI (leu:SI (match_dup 1) | |
11521 | (match_dup 2))) | |
11522 | (match_dup 3))) | |
11523 | (set (match_dup 0) | |
11524 | (compare:CC (match_dup 4) | |
11525 | (const_int 0)))] | |
11526 | "") | |
1fd4e8c1 RK |
11527 | |
11528 | (define_insn "" | |
9ebbca7d | 11529 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11530 | (compare:CC |
11531 | (and:SI (neg:SI | |
9ebbca7d GK |
11532 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11533 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11534 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11535 | (const_int 0))) |
9ebbca7d | 11536 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11537 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
9ebbca7d | 11538 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11539 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11540 | "@ |
11541 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 | |
11542 | #" | |
b19003d8 | 11543 | [(set_attr "type" "compare") |
9ebbca7d GK |
11544 | (set_attr "length" "12,16")]) |
11545 | ||
11546 | (define_split | |
11547 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11548 | (compare:CC | |
11549 | (and:SI (neg:SI | |
11550 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11551 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11552 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11553 | (const_int 0))) | |
11554 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11555 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11556 | (clobber (match_scratch:SI 4 ""))] | |
11557 | "! TARGET_POWERPC64 && reload_completed" | |
11558 | [(parallel [(set (match_dup 0) | |
11559 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11560 | (clobber (match_dup 4))]) | |
11561 | (set (match_dup 5) | |
11562 | (compare:CC (match_dup 0) | |
11563 | (const_int 0)))] | |
11564 | "") | |
1fd4e8c1 RK |
11565 | |
11566 | (define_insn "" | |
cd2b37d9 RK |
11567 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11568 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11569 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 11570 | "TARGET_POWER" |
7f340546 | 11571 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11572 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11573 | |
11574 | (define_insn "" | |
9ebbca7d | 11575 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11576 | (compare:CC |
9ebbca7d GK |
11577 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11578 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11579 | (const_int 0))) |
9ebbca7d | 11580 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11581 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 11582 | "TARGET_POWER" |
9ebbca7d GK |
11583 | "@ |
11584 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
11585 | #" | |
29ae5b89 | 11586 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11587 | (set_attr "length" "12,16")]) |
11588 | ||
11589 | (define_split | |
11590 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11591 | (compare:CC | |
11592 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11593 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11594 | (const_int 0))) | |
11595 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11596 | (lt:SI (match_dup 1) (match_dup 2)))] | |
11597 | "TARGET_POWER && reload_completed" | |
11598 | [(set (match_dup 0) | |
11599 | (lt:SI (match_dup 1) (match_dup 2))) | |
11600 | (set (match_dup 3) | |
11601 | (compare:CC (match_dup 0) | |
11602 | (const_int 0)))] | |
11603 | "") | |
1fd4e8c1 RK |
11604 | |
11605 | (define_insn "" | |
cd2b37d9 RK |
11606 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11607 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11608 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 11609 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11610 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
11611 | "TARGET_POWER" |
11612 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 11613 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11614 | |
11615 | (define_insn "" | |
9ebbca7d | 11616 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11617 | (compare:CC |
9ebbca7d GK |
11618 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11619 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11620 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11621 | (const_int 0))) |
9ebbca7d | 11622 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11623 | "TARGET_POWER" |
9ebbca7d GK |
11624 | "@ |
11625 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
11626 | #" | |
b19003d8 | 11627 | [(set_attr "type" "compare") |
9ebbca7d GK |
11628 | (set_attr "length" "12,16")]) |
11629 | ||
11630 | (define_split | |
11631 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11632 | (compare:CC | |
11633 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11634 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11635 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11636 | (const_int 0))) | |
11637 | (clobber (match_scratch:SI 4 ""))] | |
11638 | "TARGET_POWER && reload_completed" | |
11639 | [(set (match_dup 4) | |
11640 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
11641 | (match_dup 3))) | |
11642 | (set (match_dup 0) | |
11643 | (compare:CC (match_dup 4) | |
11644 | (const_int 0)))] | |
11645 | "") | |
1fd4e8c1 RK |
11646 | |
11647 | (define_insn "" | |
9ebbca7d | 11648 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11649 | (compare:CC |
9ebbca7d GK |
11650 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11651 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11652 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11653 | (const_int 0))) |
9ebbca7d | 11654 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11655 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11656 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11657 | "TARGET_POWER" |
9ebbca7d GK |
11658 | "@ |
11659 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 | |
11660 | #" | |
b19003d8 | 11661 | [(set_attr "type" "compare") |
9ebbca7d GK |
11662 | (set_attr "length" "12,16")]) |
11663 | ||
11664 | (define_split | |
11665 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11666 | (compare:CC | |
11667 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11668 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11669 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11670 | (const_int 0))) | |
11671 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11672 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11673 | (clobber (match_scratch:SI 4 ""))] | |
11674 | "TARGET_POWER && reload_completed" | |
11675 | [(parallel [(set (match_dup 0) | |
11676 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11677 | (clobber (match_dup 4))]) | |
11678 | (set (match_dup 5) | |
11679 | (compare:CC (match_dup 0) | |
11680 | (const_int 0)))] | |
11681 | "") | |
1fd4e8c1 RK |
11682 | |
11683 | (define_insn "" | |
cd2b37d9 RK |
11684 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11685 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11686 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
11687 | "TARGET_POWER" |
11688 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 11689 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11690 | |
11691 | (define_insn "" | |
cd2b37d9 RK |
11692 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11693 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11694 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 11695 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11696 | "@ |
ca7f5001 RK |
11697 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
11698 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 11699 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11700 | |
11701 | (define_insn "" | |
9ebbca7d | 11702 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11703 | (compare:CC |
9ebbca7d GK |
11704 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11705 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 11706 | (const_int 0))) |
9ebbca7d | 11707 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11708 | (ltu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11709 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11710 | "@ |
ca7f5001 | 11711 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
11712 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
11713 | # | |
11714 | #" | |
b19003d8 | 11715 | [(set_attr "type" "compare") |
9ebbca7d GK |
11716 | (set_attr "length" "12,12,16,16")]) |
11717 | ||
11718 | (define_split | |
11719 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11720 | (compare:CC | |
11721 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11722 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11723 | (const_int 0))) | |
11724 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11725 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
11726 | "! TARGET_POWERPC64 && reload_completed" | |
11727 | [(set (match_dup 0) | |
11728 | (ltu:SI (match_dup 1) (match_dup 2))) | |
11729 | (set (match_dup 3) | |
11730 | (compare:CC (match_dup 0) | |
11731 | (const_int 0)))] | |
11732 | "") | |
1fd4e8c1 RK |
11733 | |
11734 | (define_insn "" | |
19378cf8 MM |
11735 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11736 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
11737 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
11738 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI"))) | |
11739 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
f9562f27 | 11740 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11741 | "@ |
ca7f5001 | 11742 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 |
04be6346 | 11743 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
b19003d8 | 11744 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11745 | |
11746 | (define_insn "" | |
9ebbca7d | 11747 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11748 | (compare:CC |
9ebbca7d GK |
11749 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11750 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11751 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11752 | (const_int 0))) |
9ebbca7d | 11753 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11754 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11755 | "@ |
ca7f5001 | 11756 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
9ebbca7d GK |
11757 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
11758 | # | |
11759 | #" | |
b19003d8 | 11760 | [(set_attr "type" "compare") |
9ebbca7d GK |
11761 | (set_attr "length" "12,12,16,16")]) |
11762 | ||
11763 | (define_split | |
11764 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11765 | (compare:CC | |
11766 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11767 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11768 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11769 | (const_int 0))) | |
11770 | (clobber (match_scratch:SI 4 ""))] | |
11771 | "! TARGET_POWERPC64 && reload_completed" | |
11772 | [(set (match_dup 4) | |
11773 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
11774 | (match_dup 3))) | |
11775 | (set (match_dup 0) | |
11776 | (compare:CC (match_dup 4) | |
11777 | (const_int 0)))] | |
11778 | "") | |
1fd4e8c1 RK |
11779 | |
11780 | (define_insn "" | |
9ebbca7d | 11781 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11782 | (compare:CC |
9ebbca7d GK |
11783 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11784 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11785 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11786 | (const_int 0))) |
9ebbca7d | 11787 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11788 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11789 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11790 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11791 | "@ |
ca7f5001 | 11792 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
9ebbca7d GK |
11793 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
11794 | # | |
11795 | #" | |
b19003d8 | 11796 | [(set_attr "type" "compare") |
9ebbca7d GK |
11797 | (set_attr "length" "12,12,16,16")]) |
11798 | ||
11799 | (define_split | |
11800 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11801 | (compare:CC | |
11802 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11803 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11804 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11805 | (const_int 0))) | |
11806 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11807 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11808 | (clobber (match_scratch:SI 4 ""))] | |
11809 | "! TARGET_POWERPC64 && reload_completed" | |
11810 | [(parallel [(set (match_dup 0) | |
11811 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11812 | (clobber (match_dup 4))]) | |
11813 | (set (match_dup 5) | |
11814 | (compare:CC (match_dup 0) | |
11815 | (const_int 0)))] | |
11816 | "") | |
1fd4e8c1 RK |
11817 | |
11818 | (define_insn "" | |
cd2b37d9 RK |
11819 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11820 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11821 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
f9562f27 | 11822 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11823 | "@ |
ca7f5001 RK |
11824 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
11825 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11826 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
11827 | |
11828 | (define_insn "" | |
cd2b37d9 RK |
11829 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11830 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
11831 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
11832 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
11833 | "TARGET_POWER" |
11834 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 11835 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11836 | |
9ebbca7d GK |
11837 | (define_insn "" |
11838 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 11839 | (compare:CC |
9ebbca7d GK |
11840 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11841 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11842 | (const_int 0))) |
9ebbca7d | 11843 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11844 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11845 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 11846 | "TARGET_POWER" |
9ebbca7d GK |
11847 | "@ |
11848 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
11849 | #" | |
11850 | [(set_attr "type" "compare") | |
11851 | (set_attr "length" "12,16")]) | |
11852 | ||
11853 | (define_split | |
11854 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11855 | (compare:CC | |
11856 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11857 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11858 | (const_int 0))) | |
11859 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11860 | (ge:SI (match_dup 1) (match_dup 2))) | |
11861 | (clobber (match_scratch:SI 3 ""))] | |
11862 | "TARGET_POWER && reload_completed" | |
11863 | [(parallel [(set (match_dup 0) | |
11864 | (ge:SI (match_dup 1) (match_dup 2))) | |
11865 | (clobber (match_dup 3))]) | |
11866 | (set (match_dup 4) | |
11867 | (compare:CC (match_dup 0) | |
11868 | (const_int 0)))] | |
11869 | "") | |
11870 | ||
1fd4e8c1 | 11871 | (define_insn "" |
cd2b37d9 RK |
11872 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11873 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11874 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 11875 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11876 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
11877 | "TARGET_POWER" |
11878 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" | |
b19003d8 | 11879 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11880 | |
11881 | (define_insn "" | |
9ebbca7d | 11882 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11883 | (compare:CC |
9ebbca7d GK |
11884 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11885 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11886 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11887 | (const_int 0))) |
9ebbca7d | 11888 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11889 | "TARGET_POWER" |
9ebbca7d GK |
11890 | "@ |
11891 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
11892 | #" | |
b19003d8 | 11893 | [(set_attr "type" "compare") |
9ebbca7d GK |
11894 | (set_attr "length" "12,16")]) |
11895 | ||
11896 | (define_split | |
11897 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11898 | (compare:CC | |
11899 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11900 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11901 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11902 | (const_int 0))) | |
11903 | (clobber (match_scratch:SI 4 ""))] | |
11904 | "TARGET_POWER && reload_completed" | |
11905 | [(set (match_dup 4) | |
11906 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
11907 | (match_dup 3))) | |
11908 | (set (match_dup 0) | |
11909 | (compare:CC (match_dup 4) | |
11910 | (const_int 0)))] | |
11911 | "") | |
1fd4e8c1 RK |
11912 | |
11913 | (define_insn "" | |
9ebbca7d | 11914 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11915 | (compare:CC |
9ebbca7d GK |
11916 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11917 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11918 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11919 | (const_int 0))) |
9ebbca7d | 11920 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11921 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11922 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11923 | "TARGET_POWER" |
9ebbca7d GK |
11924 | "@ |
11925 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
11926 | #" | |
b19003d8 | 11927 | [(set_attr "type" "compare") |
9ebbca7d GK |
11928 | (set_attr "length" "12,16")]) |
11929 | ||
11930 | (define_split | |
11931 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11932 | (compare:CC | |
11933 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11934 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11935 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11936 | (const_int 0))) | |
11937 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11938 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11939 | (clobber (match_scratch:SI 4 ""))] | |
11940 | "TARGET_POWER && reload_completed" | |
11941 | [(parallel [(set (match_dup 0) | |
11942 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11943 | (clobber (match_dup 4))]) | |
11944 | (set (match_dup 5) | |
11945 | (compare:CC (match_dup 0) | |
11946 | (const_int 0)))] | |
11947 | "") | |
1fd4e8c1 RK |
11948 | |
11949 | (define_insn "" | |
cd2b37d9 RK |
11950 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11951 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11952 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
11953 | "TARGET_POWER" |
11954 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11955 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11956 | |
1fd4e8c1 | 11957 | (define_insn "" |
cd2b37d9 RK |
11958 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11959 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11960 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 11961 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11962 | "@ |
ca7f5001 RK |
11963 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
11964 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 11965 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11966 | |
f9562f27 DE |
11967 | (define_insn "" |
11968 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
11969 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
11970 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
11971 | "TARGET_POWERPC64" | |
11972 | "@ | |
11973 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
11974 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
11975 | [(set_attr "length" "12")]) | |
11976 | ||
1fd4e8c1 | 11977 | (define_insn "" |
9ebbca7d | 11978 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11979 | (compare:CC |
9ebbca7d GK |
11980 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11981 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 11982 | (const_int 0))) |
9ebbca7d | 11983 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11984 | (geu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11985 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11986 | "@ |
ca7f5001 | 11987 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
11988 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
11989 | # | |
11990 | #" | |
b19003d8 | 11991 | [(set_attr "type" "compare") |
9ebbca7d GK |
11992 | (set_attr "length" "12,12,16,16")]) |
11993 | ||
11994 | (define_split | |
11995 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11996 | (compare:CC | |
11997 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11998 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11999 | (const_int 0))) | |
12000 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12001 | (geu:SI (match_dup 1) (match_dup 2)))] | |
12002 | "! TARGET_POWERPC64 && reload_completed" | |
12003 | [(set (match_dup 0) | |
12004 | (geu:SI (match_dup 1) (match_dup 2))) | |
12005 | (set (match_dup 3) | |
12006 | (compare:CC (match_dup 0) | |
12007 | (const_int 0)))] | |
12008 | "") | |
1fd4e8c1 | 12009 | |
f9562f27 | 12010 | (define_insn "" |
9ebbca7d | 12011 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12012 | (compare:CC |
9ebbca7d GK |
12013 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12014 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 12015 | (const_int 0))) |
9ebbca7d | 12016 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 DE |
12017 | (geu:DI (match_dup 1) (match_dup 2)))] |
12018 | "TARGET_POWERPC64" | |
12019 | "@ | |
12020 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
12021 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
12022 | # | |
12023 | #" | |
f9562f27 | 12024 | [(set_attr "type" "compare") |
9ebbca7d GK |
12025 | (set_attr "length" "12,12,16,16")]) |
12026 | ||
12027 | (define_split | |
12028 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12029 | (compare:CC | |
12030 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12031 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
12032 | (const_int 0))) | |
12033 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12034 | (geu:DI (match_dup 1) (match_dup 2)))] | |
12035 | "TARGET_POWERPC64 && reload_completed" | |
12036 | [(set (match_dup 0) | |
12037 | (geu:DI (match_dup 1) (match_dup 2))) | |
12038 | (set (match_dup 3) | |
12039 | (compare:CC (match_dup 0) | |
12040 | (const_int 0)))] | |
12041 | "") | |
f9562f27 | 12042 | |
1fd4e8c1 | 12043 | (define_insn "" |
cd2b37d9 RK |
12044 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12045 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12046 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
cd2b37d9 | 12047 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 12048 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 12049 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12050 | "@ |
ca7f5001 RK |
12051 | {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3 |
12052 | {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 12053 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12054 | |
12055 | (define_insn "" | |
9ebbca7d | 12056 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12057 | (compare:CC |
9ebbca7d GK |
12058 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12059 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12060 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12061 | (const_int 0))) |
9ebbca7d | 12062 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12063 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12064 | "@ |
ca7f5001 | 12065 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12066 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
12067 | # | |
12068 | #" | |
b19003d8 | 12069 | [(set_attr "type" "compare") |
9ebbca7d GK |
12070 | (set_attr "length" "8,8,12,12")]) |
12071 | ||
12072 | (define_split | |
12073 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12074 | (compare:CC | |
12075 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12076 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12077 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12078 | (const_int 0))) | |
12079 | (clobber (match_scratch:SI 4 ""))] | |
12080 | "! TARGET_POWERPC64 && reload_completed" | |
12081 | [(set (match_dup 4) | |
12082 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
12083 | (match_dup 3))) | |
12084 | (set (match_dup 0) | |
12085 | (compare:CC (match_dup 4) | |
12086 | (const_int 0)))] | |
12087 | "") | |
1fd4e8c1 RK |
12088 | |
12089 | (define_insn "" | |
9ebbca7d | 12090 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12091 | (compare:CC |
9ebbca7d GK |
12092 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12093 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12094 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12095 | (const_int 0))) |
9ebbca7d | 12096 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12097 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12098 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12099 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12100 | "@ |
ca7f5001 | 12101 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
12102 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3 |
12103 | # | |
12104 | #" | |
b19003d8 | 12105 | [(set_attr "type" "compare") |
9ebbca7d GK |
12106 | (set_attr "length" "8,8,12,12")]) |
12107 | ||
12108 | (define_split | |
12109 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12110 | (compare:CC | |
12111 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12112 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12113 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12114 | (const_int 0))) | |
12115 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12116 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12117 | (clobber (match_scratch:SI 4 ""))] | |
12118 | "! TARGET_POWERPC64 && reload_completed" | |
12119 | [(parallel [(set (match_dup 0) | |
12120 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12121 | (clobber (match_dup 4))]) | |
12122 | (set (match_dup 5) | |
12123 | (compare:CC (match_dup 0) | |
12124 | (const_int 0)))] | |
12125 | "") | |
1fd4e8c1 RK |
12126 | |
12127 | (define_insn "" | |
cd2b37d9 RK |
12128 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12129 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12130 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
f9562f27 | 12131 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12132 | "@ |
ca7f5001 | 12133 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 12134 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 12135 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12136 | |
12137 | (define_insn "" | |
cd2b37d9 | 12138 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12139 | (and:SI (neg:SI |
cd2b37d9 | 12140 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12141 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
cd2b37d9 | 12142 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 12143 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 12144 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12145 | "@ |
ca7f5001 RK |
12146 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 |
12147 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" | |
b19003d8 | 12148 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12149 | |
12150 | (define_insn "" | |
9ebbca7d | 12151 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12152 | (compare:CC |
12153 | (and:SI (neg:SI | |
9ebbca7d GK |
12154 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12155 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12156 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12157 | (const_int 0))) |
9ebbca7d | 12158 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12159 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12160 | "@ |
ca7f5001 | 12161 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
12162 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
12163 | # | |
12164 | #" | |
b19003d8 | 12165 | [(set_attr "type" "compare") |
9ebbca7d GK |
12166 | (set_attr "length" "12,12,16,16")]) |
12167 | ||
12168 | (define_split | |
12169 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12170 | (compare:CC | |
12171 | (and:SI (neg:SI | |
12172 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12173 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12174 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12175 | (const_int 0))) | |
12176 | (clobber (match_scratch:SI 4 ""))] | |
12177 | "! TARGET_POWERPC64 && reload_completed" | |
12178 | [(set (match_dup 4) | |
12179 | (and:SI (neg:SI (geu:SI (match_dup 1) | |
12180 | (match_dup 2))) | |
12181 | (match_dup 3))) | |
12182 | (set (match_dup 0) | |
12183 | (compare:CC (match_dup 4) | |
12184 | (const_int 0)))] | |
12185 | "") | |
1fd4e8c1 RK |
12186 | |
12187 | (define_insn "" | |
9ebbca7d | 12188 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12189 | (compare:CC |
12190 | (and:SI (neg:SI | |
9ebbca7d GK |
12191 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12192 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12193 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12194 | (const_int 0))) |
9ebbca7d | 12195 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12196 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
9ebbca7d | 12197 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12198 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12199 | "@ |
ca7f5001 | 12200 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
9ebbca7d GK |
12201 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
12202 | # | |
12203 | #" | |
b19003d8 | 12204 | [(set_attr "type" "compare") |
9ebbca7d GK |
12205 | (set_attr "length" "12,12,16,16")]) |
12206 | ||
12207 | (define_split | |
12208 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12209 | (compare:CC | |
12210 | (and:SI (neg:SI | |
12211 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12212 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12213 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12214 | (const_int 0))) | |
12215 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12216 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
12217 | (clobber (match_scratch:SI 4 ""))] | |
12218 | "! TARGET_POWERPC64 && reload_completed" | |
12219 | [(parallel [(set (match_dup 0) | |
12220 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
12221 | (clobber (match_dup 4))]) | |
12222 | (set (match_dup 5) | |
12223 | (compare:CC (match_dup 0) | |
12224 | (const_int 0)))] | |
12225 | "") | |
1fd4e8c1 RK |
12226 | |
12227 | (define_insn "" | |
cd2b37d9 RK |
12228 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12229 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12230 | (const_int 0)))] |
f9562f27 | 12231 | "! TARGET_POWERPC64" |
ca7f5001 | 12232 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12233 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12234 | |
f9562f27 DE |
12235 | (define_insn "" |
12236 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12237 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12238 | (const_int 0)))] | |
12239 | "TARGET_POWERPC64" | |
12240 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" | |
12241 | [(set_attr "length" "12")]) | |
12242 | ||
1fd4e8c1 | 12243 | (define_insn "" |
9ebbca7d | 12244 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12245 | (compare:CC |
9ebbca7d | 12246 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
12247 | (const_int 0)) |
12248 | (const_int 0))) | |
9ebbca7d | 12249 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12250 | (gt:SI (match_dup 1) (const_int 0)))] |
f9562f27 | 12251 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12252 | "@ |
12253 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
12254 | #" | |
29ae5b89 | 12255 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12256 | (set_attr "length" "12,16")]) |
12257 | ||
12258 | (define_split | |
12259 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
12260 | (compare:CC | |
12261 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12262 | (const_int 0)) | |
12263 | (const_int 0))) | |
12264 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12265 | (gt:SI (match_dup 1) (const_int 0)))] | |
12266 | "! TARGET_POWERPC64 && reload_completed" | |
12267 | [(set (match_dup 0) | |
12268 | (gt:SI (match_dup 1) (const_int 0))) | |
12269 | (set (match_dup 2) | |
12270 | (compare:CC (match_dup 0) | |
12271 | (const_int 0)))] | |
12272 | "") | |
1fd4e8c1 | 12273 | |
f9562f27 | 12274 | (define_insn "" |
9ebbca7d | 12275 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 12276 | (compare:CC |
9ebbca7d | 12277 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
12278 | (const_int 0)) |
12279 | (const_int 0))) | |
9ebbca7d | 12280 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
12281 | (gt:DI (match_dup 1) (const_int 0)))] |
12282 | "TARGET_POWERPC64" | |
9ebbca7d GK |
12283 | "@ |
12284 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
12285 | #" | |
f9562f27 | 12286 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12287 | (set_attr "length" "12,16")]) |
12288 | ||
12289 | (define_split | |
12290 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
12291 | (compare:CC | |
12292 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12293 | (const_int 0)) | |
12294 | (const_int 0))) | |
12295 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12296 | (gt:DI (match_dup 1) (const_int 0)))] | |
12297 | "TARGET_POWERPC64 && reload_completed" | |
12298 | [(set (match_dup 0) | |
12299 | (gt:DI (match_dup 1) (const_int 0))) | |
12300 | (set (match_dup 2) | |
12301 | (compare:CC (match_dup 0) | |
12302 | (const_int 0)))] | |
12303 | "") | |
f9562f27 | 12304 | |
1fd4e8c1 | 12305 | (define_insn "" |
cd2b37d9 RK |
12306 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12307 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12308 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
12309 | "TARGET_POWER" |
12310 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 12311 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12312 | |
12313 | (define_insn "" | |
9ebbca7d | 12314 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12315 | (compare:CC |
9ebbca7d GK |
12316 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12317 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 12318 | (const_int 0))) |
9ebbca7d | 12319 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12320 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12321 | "TARGET_POWER" |
9ebbca7d GK |
12322 | "@ |
12323 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12324 | #" | |
29ae5b89 | 12325 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12326 | (set_attr "length" "12,16")]) |
12327 | ||
12328 | (define_split | |
12329 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12330 | (compare:CC | |
12331 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12332 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12333 | (const_int 0))) | |
12334 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12335 | (gt:SI (match_dup 1) (match_dup 2)))] | |
12336 | "TARGET_POWER && reload_completed" | |
12337 | [(set (match_dup 0) | |
12338 | (gt:SI (match_dup 1) (match_dup 2))) | |
12339 | (set (match_dup 3) | |
12340 | (compare:CC (match_dup 0) | |
12341 | (const_int 0)))] | |
12342 | "") | |
1fd4e8c1 RK |
12343 | |
12344 | (define_insn "" | |
cd2b37d9 RK |
12345 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12346 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12347 | (const_int 0)) |
cd2b37d9 | 12348 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 12349 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 12350 | "! TARGET_POWERPC64" |
ca7f5001 | 12351 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2" |
b19003d8 | 12352 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12353 | |
f9562f27 DE |
12354 | (define_insn "" |
12355 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12356 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12357 | (const_int 0)) | |
12358 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
12359 | (clobber (match_scratch:DI 3 "=&r"))] | |
12360 | "TARGET_POWERPC64" | |
12361 | "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2" | |
12362 | [(set_attr "length" "12")]) | |
12363 | ||
1fd4e8c1 | 12364 | (define_insn "" |
9ebbca7d | 12365 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12366 | (compare:CC |
9ebbca7d | 12367 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12368 | (const_int 0)) |
9ebbca7d | 12369 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 12370 | (const_int 0))) |
9ebbca7d | 12371 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 12372 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12373 | "@ |
12374 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
12375 | #" | |
b19003d8 | 12376 | [(set_attr "type" "compare") |
9ebbca7d GK |
12377 | (set_attr "length" "12,16")]) |
12378 | ||
12379 | (define_split | |
12380 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12381 | (compare:CC | |
12382 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12383 | (const_int 0)) | |
12384 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
12385 | (const_int 0))) | |
12386 | (clobber (match_scratch:SI 3 ""))] | |
12387 | "! TARGET_POWERPC64 && reload_completed" | |
12388 | [(set (match_dup 3) | |
12389 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
12390 | (match_dup 2))) | |
12391 | (set (match_dup 0) | |
12392 | (compare:CC (match_dup 3) | |
12393 | (const_int 0)))] | |
12394 | "") | |
1fd4e8c1 | 12395 | |
f9562f27 | 12396 | (define_insn "" |
9ebbca7d | 12397 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 12398 | (compare:CC |
9ebbca7d | 12399 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 12400 | (const_int 0)) |
9ebbca7d | 12401 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 12402 | (const_int 0))) |
9ebbca7d | 12403 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 12404 | "TARGET_POWERPC64" |
9ebbca7d GK |
12405 | "@ |
12406 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
12407 | #" | |
f9562f27 | 12408 | [(set_attr "type" "compare") |
9ebbca7d GK |
12409 | (set_attr "length" "12,16")]) |
12410 | ||
12411 | (define_split | |
12412 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12413 | (compare:CC | |
12414 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12415 | (const_int 0)) | |
12416 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12417 | (const_int 0))) | |
12418 | (clobber (match_scratch:DI 3 ""))] | |
12419 | "TARGET_POWERPC64 && reload_completed" | |
12420 | [(set (match_dup 3) | |
12421 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
12422 | (match_dup 2))) | |
12423 | (set (match_dup 0) | |
12424 | (compare:CC (match_dup 3) | |
12425 | (const_int 0)))] | |
12426 | "") | |
f9562f27 | 12427 | |
1fd4e8c1 | 12428 | (define_insn "" |
9ebbca7d GK |
12429 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
12430 | (compare:CC | |
12431 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12432 | (const_int 0)) | |
12433 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
12434 | (const_int 0))) | |
12435 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
12436 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) | |
12437 | (clobber (match_scratch:SI 3 "=&r,&r"))] | |
12438 | "! TARGET_POWERPC64" | |
12439 | "@ | |
12440 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2 | |
12441 | #" | |
12442 | [(set_attr "type" "compare") | |
12443 | (set_attr "length" "12,16")]) | |
12444 | ||
12445 | (define_split | |
12446 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
1fd4e8c1 | 12447 | (compare:CC |
9ebbca7d | 12448 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 12449 | (const_int 0)) |
9ebbca7d | 12450 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 12451 | (const_int 0))) |
9ebbca7d | 12452 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 12453 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
9ebbca7d GK |
12454 | (clobber (match_scratch:SI 3 ""))] |
12455 | "! TARGET_POWERPC64 && reload_completed" | |
12456 | [(parallel [(set (match_dup 0) | |
12457 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) | |
12458 | (clobber (match_dup 3))]) | |
12459 | (set (match_dup 4) | |
12460 | (compare:CC (match_dup 0) | |
12461 | (const_int 0)))] | |
12462 | "") | |
1fd4e8c1 | 12463 | |
f9562f27 | 12464 | (define_insn "" |
9ebbca7d | 12465 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
f9562f27 | 12466 | (compare:CC |
9ebbca7d | 12467 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 12468 | (const_int 0)) |
9ebbca7d | 12469 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 12470 | (const_int 0))) |
9ebbca7d | 12471 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 12472 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
9ebbca7d | 12473 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 12474 | "TARGET_POWERPC64" |
9ebbca7d GK |
12475 | "@ |
12476 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2 | |
12477 | #" | |
f9562f27 | 12478 | [(set_attr "type" "compare") |
9ebbca7d GK |
12479 | (set_attr "length" "12,16")]) |
12480 | ||
12481 | (define_split | |
12482 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12483 | (compare:CC | |
12484 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12485 | (const_int 0)) | |
12486 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12487 | (const_int 0))) | |
12488 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12489 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) | |
12490 | (clobber (match_scratch:DI 3 ""))] | |
12491 | "TARGET_POWERPC64 && reload_completed" | |
12492 | [(parallel [(set (match_dup 0) | |
12493 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) | |
12494 | (clobber (match_dup 3))]) | |
12495 | (set (match_dup 4) | |
12496 | (compare:CC (match_dup 0) | |
12497 | (const_int 0)))] | |
12498 | "") | |
f9562f27 | 12499 | |
1fd4e8c1 | 12500 | (define_insn "" |
cd2b37d9 RK |
12501 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12502 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12503 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
cd2b37d9 | 12504 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 12505 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
12506 | "TARGET_POWER" |
12507 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 12508 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12509 | |
12510 | (define_insn "" | |
9ebbca7d | 12511 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12512 | (compare:CC |
9ebbca7d GK |
12513 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12514 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
12515 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12516 | (const_int 0))) |
9ebbca7d | 12517 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12518 | "TARGET_POWER" |
9ebbca7d GK |
12519 | "@ |
12520 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12521 | #" | |
b19003d8 | 12522 | [(set_attr "type" "compare") |
9ebbca7d GK |
12523 | (set_attr "length" "12,16")]) |
12524 | ||
12525 | (define_split | |
12526 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12527 | (compare:CC | |
12528 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12529 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12530 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12531 | (const_int 0))) | |
12532 | (clobber (match_scratch:SI 4 ""))] | |
12533 | "TARGET_POWER && reload_completed" | |
12534 | [(set (match_dup 4) | |
12535 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) | |
12536 | (match_dup 3))) | |
12537 | (set (match_dup 0) | |
12538 | (compare:CC (match_dup 4) | |
12539 | (const_int 0)))] | |
12540 | "") | |
1fd4e8c1 RK |
12541 | |
12542 | (define_insn "" | |
9ebbca7d | 12543 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12544 | (compare:CC |
9ebbca7d GK |
12545 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12546 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
12547 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12548 | (const_int 0))) |
9ebbca7d | 12549 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12550 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12551 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12552 | "TARGET_POWER" |
9ebbca7d GK |
12553 | "@ |
12554 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 | |
12555 | #" | |
b19003d8 | 12556 | [(set_attr "type" "compare") |
9ebbca7d GK |
12557 | (set_attr "length" "12,16")]) |
12558 | ||
12559 | (define_split | |
12560 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12561 | (compare:CC | |
12562 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12563 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12564 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12565 | (const_int 0))) | |
12566 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12567 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12568 | (clobber (match_scratch:SI 4 ""))] | |
12569 | "TARGET_POWER && reload_completed" | |
12570 | [(parallel [(set (match_dup 0) | |
12571 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12572 | (clobber (match_dup 4))]) | |
12573 | (set (match_dup 5) | |
12574 | (compare:CC (match_dup 0) | |
12575 | (const_int 0)))] | |
12576 | "") | |
1fd4e8c1 RK |
12577 | |
12578 | (define_insn "" | |
cd2b37d9 RK |
12579 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12580 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12581 | (const_int 0))))] |
f9562f27 | 12582 | "! TARGET_POWERPC64" |
ca7f5001 | 12583 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 12584 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12585 | |
f9562f27 DE |
12586 | (define_insn "" |
12587 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12588 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12589 | (const_int 0))))] | |
12590 | "TARGET_POWERPC64" | |
8377288b | 12591 | "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63" |
f9562f27 DE |
12592 | [(set_attr "length" "12")]) |
12593 | ||
1fd4e8c1 | 12594 | (define_insn "" |
cd2b37d9 RK |
12595 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12596 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12597 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
12598 | "TARGET_POWER" |
12599 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12600 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12601 | |
12602 | (define_insn "" | |
cd2b37d9 RK |
12603 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12604 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12605 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 12606 | "! TARGET_POWERPC64" |
ca7f5001 | 12607 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 12608 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12609 | |
f9562f27 DE |
12610 | (define_insn "" |
12611 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12612 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12613 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
12614 | "TARGET_POWERPC64" | |
12615 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0" | |
12616 | [(set_attr "length" "12")]) | |
12617 | ||
1fd4e8c1 | 12618 | (define_insn "" |
9ebbca7d | 12619 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12620 | (compare:CC |
9ebbca7d GK |
12621 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12622 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12623 | (const_int 0))) |
9ebbca7d | 12624 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12625 | (gtu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 12626 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12627 | "@ |
12628 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
12629 | #" | |
b19003d8 | 12630 | [(set_attr "type" "compare") |
9ebbca7d GK |
12631 | (set_attr "length" "12,16")]) |
12632 | ||
12633 | (define_split | |
12634 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12635 | (compare:CC | |
12636 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12637 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12638 | (const_int 0))) | |
12639 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12640 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
12641 | "! TARGET_POWERPC64 && reload_completed" | |
12642 | [(set (match_dup 0) | |
12643 | (gtu:SI (match_dup 1) (match_dup 2))) | |
12644 | (set (match_dup 3) | |
12645 | (compare:CC (match_dup 0) | |
12646 | (const_int 0)))] | |
12647 | "") | |
1fd4e8c1 | 12648 | |
f9562f27 | 12649 | (define_insn "" |
9ebbca7d | 12650 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12651 | (compare:CC |
9ebbca7d GK |
12652 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12653 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 12654 | (const_int 0))) |
9ebbca7d | 12655 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
12656 | (gtu:DI (match_dup 1) (match_dup 2)))] |
12657 | "TARGET_POWERPC64" | |
9ebbca7d GK |
12658 | "@ |
12659 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
12660 | #" | |
f9562f27 | 12661 | [(set_attr "type" "compare") |
9ebbca7d GK |
12662 | (set_attr "length" "12,16")]) |
12663 | ||
12664 | (define_split | |
12665 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12666 | (compare:CC | |
12667 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12668 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12669 | (const_int 0))) | |
12670 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12671 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
12672 | "TARGET_POWERPC64 && reload_completed" | |
12673 | [(set (match_dup 0) | |
12674 | (gtu:DI (match_dup 1) (match_dup 2))) | |
12675 | (set (match_dup 3) | |
12676 | (compare:CC (match_dup 0) | |
12677 | (const_int 0)))] | |
12678 | "") | |
f9562f27 | 12679 | |
1fd4e8c1 | 12680 | (define_insn "" |
19378cf8 MM |
12681 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12682 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12683 | (match_operand:SI 2 "reg_or_short_operand" "I,rI")) | |
12684 | (match_operand:SI 3 "reg_or_short_operand" "r,rI"))) | |
12685 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
f9562f27 | 12686 | "! TARGET_POWERPC64" |
00751805 | 12687 | "@ |
ca7f5001 | 12688 | {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3 |
ca7f5001 | 12689 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
19378cf8 | 12690 | [(set_attr "length" "8,12")]) |
1fd4e8c1 | 12691 | |
f9562f27 DE |
12692 | (define_insn "" |
12693 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12694 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12695 | (match_operand:DI 2 "reg_or_short_operand" "I,rI")) | |
12696 | (match_operand:DI 3 "reg_or_short_operand" "r,rI"))) | |
12697 | (clobber (match_scratch:DI 4 "=&r,&r"))] | |
12698 | "TARGET_POWERPC64" | |
12699 | "@ | |
12700 | addic %4,%1,%k2\;addze %0,%3 | |
12701 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3" | |
12702 | [(set_attr "length" "8,12")]) | |
12703 | ||
1fd4e8c1 | 12704 | (define_insn "" |
9ebbca7d | 12705 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12706 | (compare:CC |
9ebbca7d GK |
12707 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12708 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
12709 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12710 | (const_int 0))) |
9ebbca7d | 12711 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12712 | "! TARGET_POWERPC64" |
00751805 | 12713 | "@ |
19378cf8 | 12714 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12715 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
12716 | # | |
12717 | #" | |
b19003d8 | 12718 | [(set_attr "type" "compare") |
9ebbca7d GK |
12719 | (set_attr "length" "8,12,12,16")]) |
12720 | ||
12721 | (define_split | |
12722 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12723 | (compare:CC | |
12724 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12725 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12726 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12727 | (const_int 0))) | |
12728 | (clobber (match_scratch:SI 4 ""))] | |
12729 | "! TARGET_POWERPC64 && reload_completed" | |
12730 | [(set (match_dup 4) | |
12731 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
12732 | (match_dup 3))) | |
12733 | (set (match_dup 0) | |
12734 | (compare:CC (match_dup 4) | |
12735 | (const_int 0)))] | |
12736 | "") | |
1fd4e8c1 | 12737 | |
f9562f27 | 12738 | (define_insn "" |
9ebbca7d | 12739 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12740 | (compare:CC |
9ebbca7d GK |
12741 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12742 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
12743 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 12744 | (const_int 0))) |
9ebbca7d | 12745 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
12746 | "TARGET_POWERPC64" |
12747 | "@ | |
12748 | addic %4,%1,%k2\;addze. %4,%3 | |
9ebbca7d GK |
12749 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3 |
12750 | # | |
12751 | #" | |
f9562f27 | 12752 | [(set_attr "type" "compare") |
9ebbca7d GK |
12753 | (set_attr "length" "8,12,12,16")]) |
12754 | ||
12755 | (define_split | |
12756 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12757 | (compare:CC | |
12758 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12759 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12760 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
12761 | (const_int 0))) | |
12762 | (clobber (match_scratch:DI 4 ""))] | |
12763 | "TARGET_POWERPC64 && reload_completed" | |
12764 | [(set (match_dup 4) | |
12765 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
12766 | (match_dup 3))) | |
12767 | (set (match_dup 0) | |
12768 | (compare:CC (match_dup 4) | |
12769 | (const_int 0)))] | |
12770 | "") | |
f9562f27 | 12771 | |
1fd4e8c1 | 12772 | (define_insn "" |
9ebbca7d | 12773 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12774 | (compare:CC |
9ebbca7d GK |
12775 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12776 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
12777 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12778 | (const_int 0))) |
9ebbca7d | 12779 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12780 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12781 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12782 | "! TARGET_POWERPC64" |
00751805 | 12783 | "@ |
ca7f5001 | 12784 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
12785 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
12786 | # | |
12787 | #" | |
b19003d8 | 12788 | [(set_attr "type" "compare") |
9ebbca7d GK |
12789 | (set_attr "length" "8,12,12,16")]) |
12790 | ||
12791 | (define_split | |
12792 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12793 | (compare:CC | |
12794 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12795 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12796 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12797 | (const_int 0))) | |
12798 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12799 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12800 | (clobber (match_scratch:SI 4 ""))] | |
12801 | "! TARGET_POWERPC64 && reload_completed" | |
12802 | [(parallel [(set (match_dup 0) | |
12803 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12804 | (clobber (match_dup 4))]) | |
12805 | (set (match_dup 5) | |
12806 | (compare:CC (match_dup 0) | |
12807 | (const_int 0)))] | |
12808 | "") | |
1fd4e8c1 | 12809 | |
f9562f27 | 12810 | (define_insn "" |
9ebbca7d | 12811 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12812 | (compare:CC |
9ebbca7d GK |
12813 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12814 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
12815 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 12816 | (const_int 0))) |
9ebbca7d | 12817 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 | 12818 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12819 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
12820 | "TARGET_POWERPC64" |
12821 | "@ | |
12822 | addic %4,%1,%k2\;addze. %0,%3 | |
9ebbca7d GK |
12823 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3 |
12824 | # | |
12825 | #" | |
f9562f27 | 12826 | [(set_attr "type" "compare") |
9ebbca7d GK |
12827 | (set_attr "length" "8,12,12,16")]) |
12828 | ||
12829 | (define_split | |
12830 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12831 | (compare:CC | |
12832 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12833 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12834 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
12835 | (const_int 0))) | |
12836 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12837 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12838 | (clobber (match_scratch:DI 4 ""))] | |
12839 | "TARGET_POWERPC64 && reload_completed" | |
12840 | [(parallel [(set (match_dup 0) | |
12841 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12842 | (clobber (match_dup 4))]) | |
12843 | (set (match_dup 5) | |
12844 | (compare:CC (match_dup 0) | |
12845 | (const_int 0)))] | |
12846 | "") | |
f9562f27 | 12847 | |
1fd4e8c1 | 12848 | (define_insn "" |
cd2b37d9 RK |
12849 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12850 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12851 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 12852 | "! TARGET_POWERPC64" |
ca7f5001 | 12853 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 12854 | [(set_attr "length" "8")]) |
f9562f27 DE |
12855 | |
12856 | (define_insn "" | |
12857 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12858 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12859 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
12860 | "TARGET_POWERPC64" | |
12861 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" | |
12862 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
12863 | \f |
12864 | ;; Define both directions of branch and return. If we need a reload | |
12865 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
12866 | ;; register CC value to there. | |
12867 | ||
12868 | (define_insn "" | |
12869 | [(set (pc) | |
12870 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
12871 | [(match_operand 2 | |
12872 | "cc_reg_operand" "x,?y") | |
12873 | (const_int 0)]) | |
12874 | (label_ref (match_operand 0 "" "")) | |
12875 | (pc)))] | |
12876 | "" | |
b19003d8 RK |
12877 | "* |
12878 | { | |
12a4e8c5 | 12879 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
12880 | }" |
12881 | [(set_attr "type" "branch")]) | |
12882 | ||
1fd4e8c1 RK |
12883 | (define_insn "" |
12884 | [(set (pc) | |
12885 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
12886 | [(match_operand 1 | |
12887 | "cc_reg_operand" "x,?y") | |
12888 | (const_int 0)]) | |
12889 | (return) | |
12890 | (pc)))] | |
12891 | "direct_return ()" | |
12a4e8c5 GK |
12892 | "* |
12893 | { | |
12894 | return output_cbranch (operands[0], NULL, 0, insn); | |
12895 | }" | |
b7ff3d82 | 12896 | [(set_attr "type" "branch") |
39a10a29 | 12897 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
12898 | |
12899 | (define_insn "" | |
12900 | [(set (pc) | |
12901 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
12902 | [(match_operand 2 | |
12903 | "cc_reg_operand" "x,?y") | |
12904 | (const_int 0)]) | |
12905 | (pc) | |
12906 | (label_ref (match_operand 0 "" ""))))] | |
12907 | "" | |
b19003d8 RK |
12908 | "* |
12909 | { | |
12a4e8c5 | 12910 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
12911 | }" |
12912 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
12913 | |
12914 | (define_insn "" | |
12915 | [(set (pc) | |
12916 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
12917 | [(match_operand 1 | |
12918 | "cc_reg_operand" "x,?y") | |
12919 | (const_int 0)]) | |
12920 | (pc) | |
12921 | (return)))] | |
12922 | "direct_return ()" | |
12a4e8c5 GK |
12923 | "* |
12924 | { | |
12925 | return output_cbranch (operands[0], NULL, 1, insn); | |
12926 | }" | |
b7ff3d82 | 12927 | [(set_attr "type" "branch") |
39a10a29 GK |
12928 | (set_attr "length" "4")]) |
12929 | ||
12930 | ;; Logic on condition register values. | |
12931 | ||
12932 | ; This pattern matches things like | |
12933 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
12934 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
12935 | ; (const_int 1))) | |
12936 | ; which are generated by the branch logic. | |
12937 | ||
12938 | (define_insn "" | |
12939 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12940 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" | |
12941 | [(match_operator:SI 2 | |
12942 | "branch_positive_comparison_operator" | |
12943 | [(match_operand 3 | |
12944 | "cc_reg_operand" "y") | |
12945 | (const_int 0)]) | |
12946 | (match_operator:SI 4 | |
12947 | "branch_positive_comparison_operator" | |
12948 | [(match_operand 5 | |
12949 | "cc_reg_operand" "y") | |
12950 | (const_int 0)])]) | |
12951 | (const_int 1)))] | |
12952 | "" | |
12953 | "cr%q1 %E0,%j2,%j4" | |
12954 | [(set_attr "type" "cr_logical")]) | |
12955 | ||
12956 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
12957 | ; Because ~1 has all but the low bit set. | |
12958 | (define_insn "" | |
12959 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12960 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" | |
12961 | [(not:SI (match_operator:SI 2 | |
12962 | "branch_positive_comparison_operator" | |
12963 | [(match_operand 3 | |
12964 | "cc_reg_operand" "y") | |
12965 | (const_int 0)])) | |
12966 | (match_operator:SI 4 | |
12967 | "branch_positive_comparison_operator" | |
12968 | [(match_operand 5 | |
12969 | "cc_reg_operand" "y") | |
12970 | (const_int 0)])]) | |
12971 | (const_int -1)))] | |
12972 | "" | |
12973 | "cr%q1 %E0,%j2,%j4" | |
12974 | [(set_attr "type" "cr_logical")]) | |
12975 | ||
12976 | (define_insn "" | |
12977 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
6c873122 | 12978 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 12979 | "branch_positive_comparison_operator" |
6c873122 | 12980 | [(match_operand 2 |
39a10a29 GK |
12981 | "cc_reg_operand" "y") |
12982 | (const_int 0)]) | |
12983 | (const_int 0)))] | |
12984 | "" | |
251b3667 | 12985 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
39a10a29 GK |
12986 | [(set_attr "type" "cr_logical")]) |
12987 | ||
12988 | ;; If we are comparing the result of two comparisons, this can be done | |
12989 | ;; using creqv or crxor. | |
12990 | ||
12991 | (define_insn_and_split "" | |
12992 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12993 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
12994 | [(match_operand 2 "cc_reg_operand" "y") | |
12995 | (const_int 0)]) | |
12996 | (match_operator 3 "branch_comparison_operator" | |
12997 | [(match_operand 4 "cc_reg_operand" "y") | |
12998 | (const_int 0)])))] | |
12999 | "" | |
13000 | "#" | |
13001 | "" | |
13002 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
13003 | (match_dup 5)))] | |
13004 | " | |
13005 | { | |
13006 | int positive_1, positive_2; | |
13007 | ||
13008 | positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode); | |
13009 | positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode); | |
13010 | ||
13011 | if (! positive_1) | |
2d4368e6 | 13012 | operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]), |
39a10a29 | 13013 | GET_CODE (operands[1])), |
2d4368e6 DE |
13014 | SImode, |
13015 | operands[2], const0_rtx); | |
39a10a29 | 13016 | else if (GET_MODE (operands[1]) != SImode) |
2d4368e6 DE |
13017 | operands[1] = gen_rtx (GET_CODE (operands[1]), |
13018 | SImode, | |
13019 | operands[2], const0_rtx); | |
39a10a29 GK |
13020 | |
13021 | if (! positive_2) | |
2d4368e6 | 13022 | operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]), |
39a10a29 | 13023 | GET_CODE (operands[3])), |
2d4368e6 DE |
13024 | SImode, |
13025 | operands[4], const0_rtx); | |
39a10a29 | 13026 | else if (GET_MODE (operands[3]) != SImode) |
2d4368e6 DE |
13027 | operands[3] = gen_rtx (GET_CODE (operands[3]), |
13028 | SImode, | |
13029 | operands[4], const0_rtx); | |
39a10a29 GK |
13030 | |
13031 | if (positive_1 == positive_2) | |
251b3667 DE |
13032 | { |
13033 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
13034 | operands[5] = constm1_rtx; | |
13035 | } | |
13036 | else | |
13037 | { | |
13038 | operands[5] = const1_rtx; | |
13039 | } | |
39a10a29 | 13040 | }") |
1fd4e8c1 RK |
13041 | |
13042 | ;; Unconditional branch and return. | |
13043 | ||
13044 | (define_insn "jump" | |
13045 | [(set (pc) | |
13046 | (label_ref (match_operand 0 "" "")))] | |
13047 | "" | |
b7ff3d82 DE |
13048 | "b %l0" |
13049 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13050 | |
13051 | (define_insn "return" | |
13052 | [(return)] | |
13053 | "direct_return ()" | |
324e52cc TG |
13054 | "{br|blr}" |
13055 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 13056 | |
0ad91047 DE |
13057 | (define_expand "indirect_jump" |
13058 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 13059 | "" |
0ad91047 DE |
13060 | " |
13061 | { | |
13062 | if (TARGET_32BIT) | |
13063 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
13064 | else | |
13065 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
13066 | DONE; | |
13067 | }") | |
13068 | ||
13069 | (define_insn "indirect_jumpsi" | |
b92b324d | 13070 | [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))] |
0ad91047 | 13071 | "TARGET_32BIT" |
b92b324d DE |
13072 | "@ |
13073 | bctr | |
13074 | {br|blr}" | |
324e52cc | 13075 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13076 | |
0ad91047 | 13077 | (define_insn "indirect_jumpdi" |
b92b324d | 13078 | [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))] |
0ad91047 | 13079 | "TARGET_64BIT" |
b92b324d DE |
13080 | "@ |
13081 | bctr | |
13082 | blr" | |
266eb58a DE |
13083 | [(set_attr "type" "jmpreg")]) |
13084 | ||
1fd4e8c1 RK |
13085 | ;; Table jump for switch statements: |
13086 | (define_expand "tablejump" | |
e6ca2c17 DE |
13087 | [(use (match_operand 0 "" "")) |
13088 | (use (label_ref (match_operand 1 "" "")))] | |
13089 | "" | |
13090 | " | |
13091 | { | |
13092 | if (TARGET_32BIT) | |
13093 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
13094 | else | |
13095 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
13096 | DONE; | |
13097 | }") | |
13098 | ||
13099 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
13100 | [(set (match_dup 3) |
13101 | (plus:SI (match_operand:SI 0 "" "") | |
13102 | (match_dup 2))) | |
13103 | (parallel [(set (pc) (match_dup 3)) | |
13104 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13105 | "TARGET_32BIT" |
1fd4e8c1 RK |
13106 | " |
13107 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 13108 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
13109 | operands[3] = gen_reg_rtx (SImode); |
13110 | }") | |
13111 | ||
e6ca2c17 | 13112 | (define_expand "tablejumpdi" |
9ebbca7d GK |
13113 | [(set (match_dup 4) |
13114 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) | |
13115 | (set (match_dup 3) | |
13116 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
13117 | (match_dup 2))) |
13118 | (parallel [(set (pc) (match_dup 3)) | |
13119 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13120 | "TARGET_64BIT" |
e6ca2c17 | 13121 | " |
9ebbca7d | 13122 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 13123 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 13124 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
13125 | }") |
13126 | ||
1fd4e8c1 RK |
13127 | (define_insn "" |
13128 | [(set (pc) | |
c859cda6 | 13129 | (match_operand:SI 0 "register_operand" "c,*l")) |
1fd4e8c1 | 13130 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13131 | "TARGET_32BIT" |
c859cda6 DJ |
13132 | "@ |
13133 | bctr | |
13134 | {br|blr}" | |
a6845123 | 13135 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13136 | |
266eb58a DE |
13137 | (define_insn "" |
13138 | [(set (pc) | |
c859cda6 | 13139 | (match_operand:DI 0 "register_operand" "c,*l")) |
266eb58a | 13140 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13141 | "TARGET_64BIT" |
c859cda6 DJ |
13142 | "@ |
13143 | bctr | |
13144 | blr" | |
266eb58a DE |
13145 | [(set_attr "type" "jmpreg")]) |
13146 | ||
1fd4e8c1 RK |
13147 | (define_insn "nop" |
13148 | [(const_int 0)] | |
13149 | "" | |
ca7f5001 | 13150 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 13151 | \f |
7e69e155 | 13152 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
13153 | ;; so loop.c knows what to generate. |
13154 | ||
5527bf14 RH |
13155 | (define_expand "doloop_end" |
13156 | [(use (match_operand 0 "" "")) ; loop pseudo | |
13157 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
13158 | (use (match_operand 2 "" "")) ; max iterations | |
13159 | (use (match_operand 3 "" "")) ; loop level | |
13160 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
13161 | "" |
13162 | " | |
13163 | { | |
5527bf14 RH |
13164 | /* Only use this on innermost loops. */ |
13165 | if (INTVAL (operands[3]) > 1) | |
13166 | FAIL; | |
0ad91047 | 13167 | if (TARGET_POWERPC64) |
5527bf14 RH |
13168 | { |
13169 | if (GET_MODE (operands[0]) != DImode) | |
13170 | FAIL; | |
13171 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
13172 | } | |
0ad91047 | 13173 | else |
5527bf14 RH |
13174 | { |
13175 | if (GET_MODE (operands[0]) != SImode) | |
13176 | FAIL; | |
13177 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
13178 | } | |
0ad91047 DE |
13179 | DONE; |
13180 | }") | |
13181 | ||
13182 | (define_expand "ctrsi" | |
3cb999d8 DE |
13183 | [(parallel [(set (pc) |
13184 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
13185 | (const_int 1)) | |
13186 | (label_ref (match_operand 1 "" "")) | |
13187 | (pc))) | |
b6c9286a MM |
13188 | (set (match_dup 0) |
13189 | (plus:SI (match_dup 0) | |
13190 | (const_int -1))) | |
5f81043f RK |
13191 | (clobber (match_scratch:CC 2 "")) |
13192 | (clobber (match_scratch:SI 3 ""))])] | |
0ad91047 DE |
13193 | "! TARGET_POWERPC64" |
13194 | "") | |
13195 | ||
13196 | (define_expand "ctrdi" | |
3cb999d8 DE |
13197 | [(parallel [(set (pc) |
13198 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
13199 | (const_int 1)) | |
13200 | (label_ref (match_operand 1 "" "")) | |
13201 | (pc))) | |
0ad91047 DE |
13202 | (set (match_dup 0) |
13203 | (plus:DI (match_dup 0) | |
13204 | (const_int -1))) | |
13205 | (clobber (match_scratch:CC 2 "")) | |
13206 | (clobber (match_scratch:DI 3 ""))])] | |
13207 | "TARGET_POWERPC64" | |
c225ba7b RK |
13208 | "") |
13209 | ||
1fd4e8c1 RK |
13210 | ;; We need to be able to do this for any operand, including MEM, or we |
13211 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 13212 | ;; JUMP_INSNs. |
0ad91047 | 13213 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
13214 | ;; label MUST be operand 0. |
13215 | ||
0ad91047 | 13216 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 13217 | [(set (pc) |
5f81043f | 13218 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 13219 | (const_int 1)) |
a6845123 | 13220 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13221 | (pc))) |
5f81043f RK |
13222 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
13223 | (plus:SI (match_dup 1) | |
13224 | (const_int -1))) | |
1fd4e8c1 RK |
13225 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13226 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13227 | "! TARGET_POWERPC64" |
b19003d8 RK |
13228 | "* |
13229 | { | |
af87a13e | 13230 | if (which_alternative != 0) |
b19003d8 | 13231 | return \"#\"; |
856a6884 | 13232 | else if (get_attr_length (insn) == 4) |
a6845123 | 13233 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 13234 | else |
f607bc57 | 13235 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 13236 | }" |
baf97f86 RK |
13237 | [(set_attr "type" "branch") |
13238 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 13239 | |
0ad91047 | 13240 | (define_insn "*ctrsi_internal2" |
5f81043f RK |
13241 | [(set (pc) |
13242 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") | |
13243 | (const_int 1)) | |
13244 | (pc) | |
13245 | (label_ref (match_operand 0 "" "")))) | |
13246 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
13247 | (plus:SI (match_dup 1) | |
13248 | (const_int -1))) | |
13249 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
13250 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
13251 | "! TARGET_POWERPC64" |
13252 | "* | |
13253 | { | |
13254 | if (which_alternative != 0) | |
13255 | return \"#\"; | |
856a6884 | 13256 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13257 | return \"bdz %l0\"; |
13258 | else | |
f607bc57 | 13259 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
13260 | }" |
13261 | [(set_attr "type" "branch") | |
13262 | (set_attr "length" "*,12,16")]) | |
13263 | ||
13264 | (define_insn "*ctrdi_internal1" | |
13265 | [(set (pc) | |
c94ccb87 | 13266 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") |
0ad91047 DE |
13267 | (const_int 1)) |
13268 | (label_ref (match_operand 0 "" "")) | |
13269 | (pc))) | |
c94ccb87 | 13270 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") |
0ad91047 DE |
13271 | (plus:DI (match_dup 1) |
13272 | (const_int -1))) | |
c94ccb87 AM |
13273 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
13274 | (clobber (match_scratch:DI 4 "=X,X,r,r"))] | |
0ad91047 DE |
13275 | "TARGET_POWERPC64" |
13276 | "* | |
13277 | { | |
13278 | if (which_alternative != 0) | |
13279 | return \"#\"; | |
856a6884 | 13280 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13281 | return \"{bdn|bdnz} %l0\"; |
13282 | else | |
f607bc57 | 13283 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
13284 | }" |
13285 | [(set_attr "type" "branch") | |
c94ccb87 | 13286 | (set_attr "length" "*,12,16,24")]) |
0ad91047 DE |
13287 | |
13288 | (define_insn "*ctrdi_internal2" | |
13289 | [(set (pc) | |
c94ccb87 | 13290 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") |
0ad91047 DE |
13291 | (const_int 1)) |
13292 | (pc) | |
13293 | (label_ref (match_operand 0 "" "")))) | |
c94ccb87 | 13294 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") |
0ad91047 DE |
13295 | (plus:DI (match_dup 1) |
13296 | (const_int -1))) | |
c94ccb87 AM |
13297 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
13298 | (clobber (match_scratch:DI 4 "=X,X,r,r"))] | |
0ad91047 | 13299 | "TARGET_POWERPC64" |
5f81043f RK |
13300 | "* |
13301 | { | |
13302 | if (which_alternative != 0) | |
13303 | return \"#\"; | |
856a6884 | 13304 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
13305 | return \"bdz %l0\"; |
13306 | else | |
f607bc57 | 13307 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
13308 | }" |
13309 | [(set_attr "type" "branch") | |
c94ccb87 | 13310 | (set_attr "length" "*,12,16,24")]) |
5f81043f | 13311 | |
c225ba7b | 13312 | ;; Similar, but we can use GE since we have a REG_NONNEG. |
0ad91047 DE |
13313 | |
13314 | (define_insn "*ctrsi_internal3" | |
1fd4e8c1 | 13315 | [(set (pc) |
5f81043f | 13316 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 13317 | (const_int 0)) |
a6845123 | 13318 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13319 | (pc))) |
5f81043f RK |
13320 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
13321 | (plus:SI (match_dup 1) | |
13322 | (const_int -1))) | |
1fd4e8c1 RK |
13323 | (clobber (match_scratch:CC 3 "=X,&x,&X")) |
13324 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13325 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
b19003d8 RK |
13326 | "* |
13327 | { | |
af87a13e | 13328 | if (which_alternative != 0) |
b19003d8 | 13329 | return \"#\"; |
856a6884 | 13330 | else if (get_attr_length (insn) == 4) |
a6845123 | 13331 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 13332 | else |
f607bc57 | 13333 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 13334 | }" |
baf97f86 RK |
13335 | [(set_attr "type" "branch") |
13336 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 13337 | |
0ad91047 | 13338 | (define_insn "*ctrsi_internal4" |
1fd4e8c1 | 13339 | [(set (pc) |
5f81043f RK |
13340 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
13341 | (const_int 0)) | |
13342 | (pc) | |
13343 | (label_ref (match_operand 0 "" "")))) | |
13344 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
13345 | (plus:SI (match_dup 1) | |
13346 | (const_int -1))) | |
13347 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
13348 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13349 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
5f81043f RK |
13350 | "* |
13351 | { | |
13352 | if (which_alternative != 0) | |
13353 | return \"#\"; | |
856a6884 | 13354 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
13355 | return \"bdz %l0\"; |
13356 | else | |
f607bc57 | 13357 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
13358 | }" |
13359 | [(set_attr "type" "branch") | |
13360 | (set_attr "length" "*,12,16")]) | |
13361 | ||
0ad91047 DE |
13362 | (define_insn "*ctrdi_internal3" |
13363 | [(set (pc) | |
c94ccb87 | 13364 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") |
0ad91047 DE |
13365 | (const_int 0)) |
13366 | (label_ref (match_operand 0 "" "")) | |
13367 | (pc))) | |
c94ccb87 | 13368 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") |
0ad91047 DE |
13369 | (plus:DI (match_dup 1) |
13370 | (const_int -1))) | |
c94ccb87 AM |
13371 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
13372 | (clobber (match_scratch:DI 4 "=X,X,r,r"))] | |
0ad91047 DE |
13373 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
13374 | "* | |
13375 | { | |
13376 | if (which_alternative != 0) | |
13377 | return \"#\"; | |
856a6884 | 13378 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13379 | return \"{bdn|bdnz} %l0\"; |
13380 | else | |
f607bc57 | 13381 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
13382 | }" |
13383 | [(set_attr "type" "branch") | |
c94ccb87 | 13384 | (set_attr "length" "*,12,16,24")]) |
0ad91047 DE |
13385 | |
13386 | (define_insn "*ctrdi_internal4" | |
13387 | [(set (pc) | |
c94ccb87 | 13388 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") |
0ad91047 DE |
13389 | (const_int 0)) |
13390 | (pc) | |
13391 | (label_ref (match_operand 0 "" "")))) | |
c94ccb87 | 13392 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") |
0ad91047 DE |
13393 | (plus:DI (match_dup 1) |
13394 | (const_int -1))) | |
c94ccb87 AM |
13395 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
13396 | (clobber (match_scratch:DI 4 "=X,X,r,r"))] | |
0ad91047 DE |
13397 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
13398 | "* | |
13399 | { | |
13400 | if (which_alternative != 0) | |
13401 | return \"#\"; | |
856a6884 | 13402 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13403 | return \"bdz %l0\"; |
13404 | else | |
f607bc57 | 13405 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
13406 | }" |
13407 | [(set_attr "type" "branch") | |
c94ccb87 | 13408 | (set_attr "length" "*,12,16,24")]) |
0ad91047 DE |
13409 | |
13410 | ;; Similar but use EQ | |
13411 | ||
13412 | (define_insn "*ctrsi_internal5" | |
5f81043f RK |
13413 | [(set (pc) |
13414 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
1fd4e8c1 | 13415 | (const_int 1)) |
a6845123 | 13416 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13417 | (pc))) |
5f81043f RK |
13418 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
13419 | (plus:SI (match_dup 1) | |
13420 | (const_int -1))) | |
1fd4e8c1 RK |
13421 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13422 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13423 | "! TARGET_POWERPC64" |
b19003d8 RK |
13424 | "* |
13425 | { | |
af87a13e | 13426 | if (which_alternative != 0) |
b19003d8 | 13427 | return \"#\"; |
856a6884 | 13428 | else if (get_attr_length (insn) == 4) |
a6845123 | 13429 | return \"bdz %l0\"; |
b19003d8 | 13430 | else |
f607bc57 | 13431 | return \"{bdn|bdnz} $+8\;b %l0\"; |
b19003d8 | 13432 | }" |
baf97f86 RK |
13433 | [(set_attr "type" "branch") |
13434 | (set_attr "length" "*,12,16")]) | |
1fd4e8c1 | 13435 | |
0ad91047 | 13436 | (define_insn "*ctrsi_internal6" |
5f81043f RK |
13437 | [(set (pc) |
13438 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
13439 | (const_int 1)) | |
13440 | (pc) | |
13441 | (label_ref (match_operand 0 "" "")))) | |
13442 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
13443 | (plus:SI (match_dup 1) | |
13444 | (const_int -1))) | |
13445 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
13446 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
13447 | "! TARGET_POWERPC64" |
13448 | "* | |
13449 | { | |
13450 | if (which_alternative != 0) | |
13451 | return \"#\"; | |
856a6884 | 13452 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13453 | return \"{bdn|bdnz} %l0\"; |
13454 | else | |
f607bc57 | 13455 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
13456 | }" |
13457 | [(set_attr "type" "branch") | |
13458 | (set_attr "length" "*,12,16")]) | |
13459 | ||
13460 | (define_insn "*ctrdi_internal5" | |
13461 | [(set (pc) | |
c94ccb87 | 13462 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") |
0ad91047 DE |
13463 | (const_int 1)) |
13464 | (label_ref (match_operand 0 "" "")) | |
13465 | (pc))) | |
c94ccb87 | 13466 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") |
0ad91047 DE |
13467 | (plus:DI (match_dup 1) |
13468 | (const_int -1))) | |
c94ccb87 AM |
13469 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
13470 | (clobber (match_scratch:DI 4 "=X,X,r,r"))] | |
0ad91047 DE |
13471 | "TARGET_POWERPC64" |
13472 | "* | |
13473 | { | |
13474 | if (which_alternative != 0) | |
13475 | return \"#\"; | |
856a6884 | 13476 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13477 | return \"bdz %l0\"; |
13478 | else | |
f607bc57 | 13479 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
13480 | }" |
13481 | [(set_attr "type" "branch") | |
c94ccb87 | 13482 | (set_attr "length" "*,12,16,24")]) |
0ad91047 DE |
13483 | |
13484 | (define_insn "*ctrdi_internal6" | |
13485 | [(set (pc) | |
c94ccb87 | 13486 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,!*f") |
0ad91047 DE |
13487 | (const_int 1)) |
13488 | (pc) | |
13489 | (label_ref (match_operand 0 "" "")))) | |
c94ccb87 | 13490 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f") |
0ad91047 DE |
13491 | (plus:DI (match_dup 1) |
13492 | (const_int -1))) | |
c94ccb87 AM |
13493 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
13494 | (clobber (match_scratch:DI 4 "=X,X,r,r"))] | |
0ad91047 | 13495 | "TARGET_POWERPC64" |
5f81043f RK |
13496 | "* |
13497 | { | |
13498 | if (which_alternative != 0) | |
13499 | return \"#\"; | |
856a6884 | 13500 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
13501 | return \"{bdn|bdnz} %l0\"; |
13502 | else | |
f607bc57 | 13503 | return \"bdz $+8\;b %l0\"; |
5f81043f RK |
13504 | }" |
13505 | [(set_attr "type" "branch") | |
c94ccb87 | 13506 | (set_attr "length" "*,12,16,24")]) |
5f81043f | 13507 | |
0ad91047 DE |
13508 | ;; Now the splitters if we could not allocate the CTR register |
13509 | ||
1fd4e8c1 RK |
13510 | (define_split |
13511 | [(set (pc) | |
13512 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 13513 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
13514 | (const_int 1)]) |
13515 | (match_operand 5 "" "") | |
13516 | (match_operand 6 "" ""))) | |
cd2b37d9 | 13517 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
13518 | (plus:SI (match_dup 1) |
13519 | (const_int -1))) | |
1fd4e8c1 RK |
13520 | (clobber (match_scratch:CC 3 "")) |
13521 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 | 13522 | "! TARGET_POWERPC64 && reload_completed" |
1fd4e8c1 | 13523 | [(parallel [(set (match_dup 3) |
5f81043f RK |
13524 | (compare:CC (plus:SI (match_dup 1) |
13525 | (const_int -1)) | |
1fd4e8c1 | 13526 | (const_int 0))) |
5f81043f RK |
13527 | (set (match_dup 0) |
13528 | (plus:SI (match_dup 1) | |
13529 | (const_int -1)))]) | |
13530 | (set (pc) (if_then_else (match_dup 7) | |
13531 | (match_dup 5) | |
13532 | (match_dup 6)))] | |
1fd4e8c1 RK |
13533 | " |
13534 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13535 | const0_rtx); }") | |
13536 | ||
13537 | (define_split | |
13538 | [(set (pc) | |
13539 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 13540 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
13541 | (const_int 1)]) |
13542 | (match_operand 5 "" "") | |
13543 | (match_operand 6 "" ""))) | |
9ebbca7d | 13544 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
13545 | (plus:SI (match_dup 1) (const_int -1))) |
13546 | (clobber (match_scratch:CC 3 "")) | |
13547 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 DE |
13548 | "! TARGET_POWERPC64 && reload_completed |
13549 | && ! gpc_reg_operand (operands[0], SImode)" | |
1fd4e8c1 | 13550 | [(parallel [(set (match_dup 3) |
5f81043f RK |
13551 | (compare:CC (plus:SI (match_dup 1) |
13552 | (const_int -1)) | |
1fd4e8c1 | 13553 | (const_int 0))) |
5f81043f RK |
13554 | (set (match_dup 4) |
13555 | (plus:SI (match_dup 1) | |
13556 | (const_int -1)))]) | |
13557 | (set (match_dup 0) | |
13558 | (match_dup 4)) | |
13559 | (set (pc) (if_then_else (match_dup 7) | |
13560 | (match_dup 5) | |
13561 | (match_dup 6)))] | |
1fd4e8c1 RK |
13562 | " |
13563 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13564 | const0_rtx); }") | |
0ad91047 DE |
13565 | (define_split |
13566 | [(set (pc) | |
13567 | (if_then_else (match_operator 2 "comparison_operator" | |
13568 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
13569 | (const_int 1)]) | |
13570 | (match_operand 5 "" "") | |
13571 | (match_operand 6 "" ""))) | |
13572 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13573 | (plus:DI (match_dup 1) | |
13574 | (const_int -1))) | |
13575 | (clobber (match_scratch:CC 3 "")) | |
13576 | (clobber (match_scratch:DI 4 ""))] | |
c94ccb87 | 13577 | "TARGET_POWERPC64 && reload_completed && INT_REGNO_P (REGNO (operands[0]))" |
0ad91047 DE |
13578 | [(parallel [(set (match_dup 3) |
13579 | (compare:CC (plus:DI (match_dup 1) | |
13580 | (const_int -1)) | |
13581 | (const_int 0))) | |
13582 | (set (match_dup 0) | |
13583 | (plus:DI (match_dup 1) | |
13584 | (const_int -1)))]) | |
13585 | (set (pc) (if_then_else (match_dup 7) | |
13586 | (match_dup 5) | |
13587 | (match_dup 6)))] | |
13588 | " | |
13589 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13590 | const0_rtx); }") | |
13591 | ||
13592 | (define_split | |
13593 | [(set (pc) | |
13594 | (if_then_else (match_operator 2 "comparison_operator" | |
13595 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
13596 | (const_int 1)]) | |
13597 | (match_operand 5 "" "") | |
13598 | (match_operand 6 "" ""))) | |
9ebbca7d | 13599 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
13600 | (plus:DI (match_dup 1) (const_int -1))) |
13601 | (clobber (match_scratch:CC 3 "")) | |
13602 | (clobber (match_scratch:DI 4 ""))] | |
13603 | "TARGET_POWERPC64 && reload_completed | |
13604 | && ! gpc_reg_operand (operands[0], DImode)" | |
13605 | [(parallel [(set (match_dup 3) | |
13606 | (compare:CC (plus:DI (match_dup 1) | |
13607 | (const_int -1)) | |
13608 | (const_int 0))) | |
13609 | (set (match_dup 4) | |
13610 | (plus:DI (match_dup 1) | |
13611 | (const_int -1)))]) | |
13612 | (set (match_dup 0) | |
13613 | (match_dup 4)) | |
13614 | (set (pc) (if_then_else (match_dup 7) | |
13615 | (match_dup 5) | |
13616 | (match_dup 6)))] | |
13617 | " | |
13618 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13619 | const0_rtx); }") | |
c94ccb87 AM |
13620 | |
13621 | (define_split | |
13622 | [(set (pc) | |
13623 | (if_then_else (match_operator 2 "comparison_operator" | |
13624 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
13625 | (const_int 1)]) | |
13626 | (match_operand 5 "" "") | |
13627 | (match_operand 6 "" ""))) | |
13628 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13629 | (plus:DI (match_dup 1) | |
13630 | (const_int -1))) | |
13631 | (clobber (match_scratch:CC 3 "")) | |
13632 | (clobber (match_scratch:DI 4 ""))] | |
13633 | "TARGET_POWERPC64 && reload_completed && FP_REGNO_P (REGNO (operands[0]))" | |
13634 | [(set (match_dup 8) | |
13635 | (match_dup 1)) | |
13636 | (set (match_dup 4) | |
13637 | (match_dup 8)) | |
13638 | (parallel [(set (match_dup 3) | |
13639 | (compare:CC (plus:DI (match_dup 4) | |
13640 | (const_int -1)) | |
13641 | (const_int 0))) | |
13642 | (set (match_dup 4) | |
13643 | (plus:DI (match_dup 4) | |
13644 | (const_int -1)))]) | |
13645 | (set (match_dup 8) | |
13646 | (match_dup 4)) | |
13647 | (set (match_dup 0) | |
13648 | (match_dup 8)) | |
13649 | (set (pc) (if_then_else (match_dup 7) | |
13650 | (match_dup 5) | |
13651 | (match_dup 6)))] | |
13652 | " | |
13653 | { | |
13654 | operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13655 | const0_rtx); | |
13656 | operands[8] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
13657 | }") | |
13658 | ||
e0cd0770 JC |
13659 | \f |
13660 | (define_insn "trap" | |
13661 | [(trap_if (const_int 1) (const_int 0))] | |
13662 | "" | |
13663 | "{t 31,0,0|trap}") | |
13664 | ||
13665 | (define_expand "conditional_trap" | |
13666 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
13667 | [(match_dup 2) (match_dup 3)]) | |
13668 | (match_operand 1 "const_int_operand" ""))] | |
13669 | "" | |
13670 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
13671 | operands[2] = rs6000_compare_op0; | |
13672 | operands[3] = rs6000_compare_op1;") | |
13673 | ||
13674 | (define_insn "" | |
13675 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
13676 | [(match_operand:SI 1 "register_operand" "r") | |
13677 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
13678 | (const_int 0))] | |
13679 | "" | |
a157febd GK |
13680 | "{t|tw}%V0%I2 %1,%2") |
13681 | ||
13682 | (define_insn "" | |
13683 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
13684 | [(match_operand:DI 1 "register_operand" "r") | |
13685 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
13686 | (const_int 0))] | |
13687 | "TARGET_POWERPC64" | |
13688 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
13689 | \f |
13690 | ;; Insns related to generating the function prologue and epilogue. | |
13691 | ||
13692 | (define_expand "prologue" | |
13693 | [(use (const_int 0))] | |
13694 | "TARGET_SCHED_PROLOG" | |
13695 | " | |
13696 | { | |
13697 | rs6000_emit_prologue (); | |
13698 | DONE; | |
13699 | }") | |
13700 | ||
13701 | (define_insn "movesi_from_cr" | |
13702 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
13703 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) | |
13704 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))] | |
13705 | "" | |
13706 | "mfcr %0") | |
13707 | ||
13708 | (define_insn "*stmw" | |
13709 | [(match_parallel 0 "stmw_operation" | |
13710 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
13711 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
13712 | "TARGET_MULTIPLE" | |
13713 | "{stm|stmw} %2,%1") | |
13714 | ||
13715 | (define_insn "*save_fpregs_si" | |
13716 | [(match_parallel 0 "any_operand" | |
13717 | [(clobber (match_operand:SI 1 "register_operand" "=l")) | |
13718 | (use (match_operand:SI 2 "call_operand" "s")) | |
13719 | (set (match_operand:DF 3 "memory_operand" "=m") | |
13720 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
13721 | "TARGET_32BIT" | |
13722 | "bl %z2") | |
13723 | ||
13724 | (define_insn "*save_fpregs_di" | |
13725 | [(match_parallel 0 "any_operand" | |
13726 | [(clobber (match_operand:DI 1 "register_operand" "=l")) | |
13727 | (use (match_operand:DI 2 "call_operand" "s")) | |
13728 | (set (match_operand:DF 3 "memory_operand" "=m") | |
13729 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
13730 | "TARGET_64BIT" | |
13731 | "bl %z2") | |
13732 | ||
13733 | ; These are to explain that changes to the stack pointer should | |
13734 | ; not be moved over stores to stack memory. | |
13735 | (define_insn "stack_tie" | |
13736 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
13737 | (unspec:BLK [(match_dup 0)] 5))] | |
13738 | "" | |
13739 | "" | |
13740 | [(set_attr "length" "0")]) | |
13741 | ||
13742 | ||
13743 | (define_expand "epilogue" | |
13744 | [(use (const_int 0))] | |
13745 | "TARGET_SCHED_PROLOG" | |
13746 | " | |
13747 | { | |
13748 | rs6000_emit_epilogue (FALSE); | |
13749 | DONE; | |
13750 | }") | |
13751 | ||
13752 | ; On some processors, doing the mtcrf one CC register at a time is | |
13753 | ; faster (like on the 604e). On others, doing them all at once is | |
13754 | ; faster; for instance, on the 601 and 750. | |
13755 | ||
13756 | (define_expand "movsi_to_cr_one" | |
13757 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
13758 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
13759 | (match_dup 2)] 20))] | |
13760 | "" | |
13761 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
13762 | ||
13763 | (define_insn "*movsi_to_cr" | |
13764 | [(match_parallel 0 "mtcrf_operation" | |
e35b9579 GK |
13765 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") |
13766 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
13767 | (match_operand 3 "immediate_operand" "n")] | |
9ebbca7d GK |
13768 | 20))])] |
13769 | "" | |
e35b9579 GK |
13770 | "* |
13771 | { | |
13772 | int mask = 0; | |
13773 | int i; | |
13774 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
13775 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
13776 | operands[4] = GEN_INT (mask); | |
13777 | return \"mtcrf %4,%2\"; | |
13778 | }") | |
9ebbca7d GK |
13779 | |
13780 | (define_insn "" | |
13781 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
13782 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
13783 | (match_operand 2 "immediate_operand" "n")] 20))] | |
13784 | "GET_CODE (operands[0]) == REG | |
13785 | && CR_REGNO_P (REGNO (operands[0])) | |
13786 | && GET_CODE (operands[2]) == CONST_INT | |
13787 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
13788 | "mtcrf %R0,%1") | |
13789 | ||
13790 | ; The load-multiple instructions have similar properties. | |
13791 | ; Note that "load_multiple" is a name known to the machine-independent | |
13792 | ; code that actually corresponds to the powerpc load-string. | |
13793 | ||
13794 | (define_insn "*lmw" | |
13795 | [(match_parallel 0 "lmw_operation" | |
13796 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
13797 | (match_operand:SI 2 "memory_operand" "m"))])] | |
13798 | "TARGET_MULTIPLE" | |
13799 | "{lm|lmw} %1,%2") | |
13800 | ||
13801 | (define_insn "*return_internal_si" | |
e35b9579 GK |
13802 | [(return) |
13803 | (use (match_operand:SI 0 "register_operand" "lc"))] | |
9ebbca7d | 13804 | "TARGET_32BIT" |
cccf3bdc | 13805 | "b%T0" |
9ebbca7d GK |
13806 | [(set_attr "type" "jmpreg")]) |
13807 | ||
13808 | (define_insn "*return_internal_di" | |
e35b9579 GK |
13809 | [(return) |
13810 | (use (match_operand:DI 0 "register_operand" "lc"))] | |
9ebbca7d | 13811 | "TARGET_64BIT" |
cccf3bdc | 13812 | "b%T0" |
9ebbca7d GK |
13813 | [(set_attr "type" "jmpreg")]) |
13814 | ||
13815 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
13816 | ; stuff was in GCC. Oh, and "any_operand" is a bit flexible... | |
13817 | ||
13818 | (define_insn "*return_and_restore_fpregs_si" | |
13819 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
13820 | [(return) |
13821 | (use (match_operand:SI 1 "register_operand" "l")) | |
9ebbca7d GK |
13822 | (use (match_operand:SI 2 "call_operand" "s")) |
13823 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
13824 | (match_operand:DF 4 "memory_operand" "m"))])] | |
13825 | "TARGET_32BIT" | |
13826 | "b %z2") | |
13827 | ||
13828 | (define_insn "*return_and_restore_fpregs_di" | |
13829 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
13830 | [(return) |
13831 | (use (match_operand:DI 1 "register_operand" "l")) | |
9ebbca7d GK |
13832 | (use (match_operand:DI 2 "call_operand" "s")) |
13833 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
13834 | (match_operand:DF 4 "memory_operand" "m"))])] | |
13835 | "TARGET_64BIT" | |
13836 | "b %z2") | |
13837 | ||
83720594 RH |
13838 | ; This is used in compiling the unwind routines. |
13839 | (define_expand "eh_return" | |
13840 | [(use (match_operand 0 "general_operand" "")) | |
13841 | (use (match_operand 1 "general_operand" ""))] | |
9ebbca7d GK |
13842 | "" |
13843 | " | |
13844 | { | |
3553b09d | 13845 | #if TARGET_AIX |
83720594 | 13846 | rs6000_emit_eh_toc_restore (operands[0]); |
3553b09d | 13847 | #endif |
83720594 RH |
13848 | if (TARGET_32BIT) |
13849 | emit_insn (gen_eh_set_lr_si (operands[1])); | |
9ebbca7d | 13850 | else |
83720594 RH |
13851 | emit_insn (gen_eh_set_lr_di (operands[1])); |
13852 | emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]); | |
9ebbca7d GK |
13853 | DONE; |
13854 | }") | |
13855 | ||
83720594 RH |
13856 | ; We can't expand this before we know where the link register is stored. |
13857 | (define_insn "eh_set_lr_si" | |
13858 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9) | |
466eb3e0 | 13859 | (clobber (match_scratch:SI 1 "=&b"))] |
83720594 RH |
13860 | "TARGET_32BIT" |
13861 | "#") | |
13862 | ||
13863 | (define_insn "eh_set_lr_di" | |
13864 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9) | |
466eb3e0 | 13865 | (clobber (match_scratch:DI 1 "=&b"))] |
83720594 RH |
13866 | "TARGET_64BIT" |
13867 | "#") | |
9ebbca7d GK |
13868 | |
13869 | (define_split | |
83720594 RH |
13870 | [(unspec_volatile [(match_operand 0 "register_operand" "")] 9) |
13871 | (clobber (match_scratch 1 ""))] | |
13872 | "reload_completed" | |
13873 | [(const_int 0)] | |
9ebbca7d GK |
13874 | " |
13875 | { | |
83720594 | 13876 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d | 13877 | |
83720594 RH |
13878 | if (info->lr_save_p) |
13879 | { | |
13880 | rtx frame_rtx = stack_pointer_rtx; | |
13881 | int sp_offset = 0; | |
13882 | rtx tmp; | |
9ebbca7d | 13883 | |
83720594 RH |
13884 | if (frame_pointer_needed |
13885 | || current_function_calls_alloca | |
13886 | || info->total_size > 32767) | |
13887 | { | |
13888 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
13889 | frame_rtx = operands[1]; | |
13890 | } | |
13891 | else if (info->push_p) | |
13892 | sp_offset = info->total_size; | |
9ebbca7d | 13893 | |
83720594 RH |
13894 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); |
13895 | tmp = gen_rtx_MEM (Pmode, tmp); | |
13896 | emit_move_insn (tmp, operands[0]); | |
13897 | } | |
13898 | else | |
13899 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
13900 | DONE; | |
13901 | }") | |
0ac081f6 | 13902 | |
01a2ccd0 DE |
13903 | (define_insn "prefetch" |
13904 | [(prefetch (match_operand:V4SI 0 "address_operand" "p") | |
6041bf2f DE |
13905 | (match_operand:SI 1 "const_int_operand" "n") |
13906 | (match_operand:SI 2 "const_int_operand" "n"))] | |
01a2ccd0 | 13907 | "TARGET_POWERPC" |
6041bf2f DE |
13908 | "* |
13909 | { | |
01a2ccd0 DE |
13910 | if (GET_CODE (operands[0]) == REG) |
13911 | return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; | |
13912 | return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; | |
6041bf2f DE |
13913 | }" |
13914 | [(set_attr "type" "load")]) | |
13915 | \f | |
0ac081f6 AH |
13916 | ;; AltiVec patterns |
13917 | ||
13918 | ;; Generic LVX load instruction. | |
f18c054f | 13919 | (define_insn "altivec_lvx_4si" |
0ec4e2a8 | 13920 | [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") |
0ac081f6 AH |
13921 | (match_operand:V4SI 1 "memory_operand" "m"))] |
13922 | "TARGET_ALTIVEC" | |
9bddde52 | 13923 | "lvx %0,%y1" |
f18c054f DB |
13924 | [(set_attr "type" "vecload")]) |
13925 | ||
13926 | (define_insn "altivec_lvx_8hi" | |
0ec4e2a8 | 13927 | [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") |
f18c054f DB |
13928 | (match_operand:V8HI 1 "memory_operand" "m"))] |
13929 | "TARGET_ALTIVEC" | |
13930 | "lvx %0,%y1" | |
13931 | [(set_attr "type" "vecload")]) | |
13932 | ||
13933 | (define_insn "altivec_lvx_16qi" | |
0ec4e2a8 | 13934 | [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") |
f18c054f DB |
13935 | (match_operand:V16QI 1 "memory_operand" "m"))] |
13936 | "TARGET_ALTIVEC" | |
13937 | "lvx %0,%y1" | |
13938 | [(set_attr "type" "vecload")]) | |
13939 | ||
13940 | (define_insn "altivec_lvx_4sf" | |
0ec4e2a8 | 13941 | [(set (match_operand:V4SF 0 "altivec_register_operand" "=v") |
f18c054f DB |
13942 | (match_operand:V4SF 1 "memory_operand" "m"))] |
13943 | "TARGET_ALTIVEC" | |
13944 | "lvx %0,%y1" | |
13945 | [(set_attr "type" "vecload")]) | |
0ac081f6 AH |
13946 | |
13947 | ;; Generic STVX store instruction. | |
f18c054f | 13948 | (define_insn "altivec_stvx_4si" |
0ac081f6 | 13949 | [(set (match_operand:V4SI 0 "memory_operand" "=m") |
0ec4e2a8 | 13950 | (match_operand:V4SI 1 "altivec_register_operand" "v"))] |
0ac081f6 | 13951 | "TARGET_ALTIVEC" |
9bddde52 | 13952 | "stvx %1,%y0" |
f18c054f DB |
13953 | [(set_attr "type" "vecstore")]) |
13954 | ||
13955 | (define_insn "altivec_stvx_8hi" | |
13956 | [(set (match_operand:V8HI 0 "memory_operand" "=m") | |
0ec4e2a8 | 13957 | (match_operand:V8HI 1 "altivec_register_operand" "v"))] |
f18c054f DB |
13958 | "TARGET_ALTIVEC" |
13959 | "stvx %1,%y0" | |
13960 | [(set_attr "type" "vecstore")]) | |
13961 | ||
13962 | (define_insn "altivec_stvx_16qi" | |
13963 | [(set (match_operand:V16QI 0 "memory_operand" "=m") | |
0ec4e2a8 | 13964 | (match_operand:V16QI 1 "altivec_register_operand" "v"))] |
f18c054f DB |
13965 | "TARGET_ALTIVEC" |
13966 | "stvx %1,%y0" | |
13967 | [(set_attr "type" "vecstore")]) | |
13968 | ||
13969 | (define_insn "altivec_stvx_4sf" | |
13970 | [(set (match_operand:V4SF 0 "memory_operand" "=m") | |
0ec4e2a8 | 13971 | (match_operand:V4SF 1 "altivec_register_operand" "v"))] |
f18c054f DB |
13972 | "TARGET_ALTIVEC" |
13973 | "stvx %1,%y0" | |
13974 | [(set_attr "type" "vecstore")]) | |
0ac081f6 AH |
13975 | |
13976 | ;; Vector move instructions. | |
13977 | (define_expand "movv4si" | |
13978 | [(set (match_operand:V4SI 0 "nonimmediate_operand" "") | |
13979 | (match_operand:V4SI 1 "any_operand" ""))] | |
13980 | "TARGET_ALTIVEC" | |
13981 | "{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }") | |
13982 | ||
13983 | (define_insn "*movv4si_internal" | |
04428ad4 AH |
13984 | [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,o,r,r") |
13985 | (match_operand:V4SI 1 "input_operand" "v,m,v,r,o,r"))] | |
0ac081f6 AH |
13986 | "TARGET_ALTIVEC" |
13987 | "@ | |
9bddde52 | 13988 | stvx %1,%y0 |
f3fe2696 | 13989 | lvx %0,%y1 |
0ec4e2a8 | 13990 | vor %0,%1,%1 |
78c875e8 AH |
13991 | stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 |
13992 | lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 | |
13993 | mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" | |
0ec4e2a8 | 13994 | [(set_attr "type" "altivec") |
78c875e8 | 13995 | (set_attr "length" "*,*,*,16,16,16")]) |
0ac081f6 AH |
13996 | |
13997 | (define_expand "movv8hi" | |
13998 | [(set (match_operand:V8HI 0 "nonimmediate_operand" "") | |
13999 | (match_operand:V8HI 1 "any_operand" ""))] | |
14000 | "TARGET_ALTIVEC" | |
14001 | "{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }") | |
14002 | ||
14003 | (define_insn "*movv8hi_internal1" | |
04428ad4 AH |
14004 | [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,o,r,r") |
14005 | (match_operand:V8HI 1 "input_operand" "v,m,v,r,o,r"))] | |
0ac081f6 AH |
14006 | "TARGET_ALTIVEC" |
14007 | "@ | |
9bddde52 | 14008 | stvx %1,%y0 |
f3fe2696 | 14009 | lvx %0,%y1 |
0ec4e2a8 | 14010 | vor %0,%1,%1 |
78c875e8 AH |
14011 | stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 |
14012 | lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 | |
14013 | mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" | |
0ec4e2a8 | 14014 | [(set_attr "type" "altivec") |
78c875e8 | 14015 | (set_attr "length" "*,*,*,16,16,16")]) |
0ac081f6 AH |
14016 | |
14017 | (define_expand "movv16qi" | |
14018 | [(set (match_operand:V16QI 0 "nonimmediate_operand" "") | |
14019 | (match_operand:V16QI 1 "any_operand" ""))] | |
14020 | "TARGET_ALTIVEC" | |
14021 | "{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }") | |
14022 | ||
14023 | (define_insn "*movv16qi_internal1" | |
04428ad4 AH |
14024 | [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,o,r,r") |
14025 | (match_operand:V16QI 1 "input_operand" "v,m,v,r,o,r"))] | |
0ac081f6 AH |
14026 | "TARGET_ALTIVEC" |
14027 | "@ | |
9bddde52 | 14028 | stvx %1,%y0 |
f3fe2696 | 14029 | lvx %0,%y1 |
0ec4e2a8 | 14030 | vor %0,%1,%1 |
78c875e8 AH |
14031 | stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 |
14032 | lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 | |
14033 | mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" | |
0ec4e2a8 | 14034 | [(set_attr "type" "altivec") |
78c875e8 | 14035 | (set_attr "length" "*,*,*,16,16,16")]) |
0ac081f6 AH |
14036 | |
14037 | (define_expand "movv4sf" | |
14038 | [(set (match_operand:V4SF 0 "nonimmediate_operand" "") | |
14039 | (match_operand:V4SF 1 "any_operand" ""))] | |
14040 | "TARGET_ALTIVEC" | |
14041 | "{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }") | |
14042 | ||
14043 | (define_insn "*movv4sf_internal1" | |
04428ad4 AH |
14044 | [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,o,r,r") |
14045 | (match_operand:V4SF 1 "input_operand" "v,m,v,r,o,r"))] | |
0ac081f6 AH |
14046 | "TARGET_ALTIVEC" |
14047 | "@ | |
9bddde52 | 14048 | stvx %1,%y0 |
f3fe2696 | 14049 | lvx %0,%y1 |
0ec4e2a8 | 14050 | vor %0,%1,%1 |
78c875e8 AH |
14051 | stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 |
14052 | lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 | |
14053 | mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" | |
0ec4e2a8 | 14054 | [(set_attr "type" "altivec") |
78c875e8 | 14055 | (set_attr "length" "*,*,*,16,16,16")]) |
0ac081f6 | 14056 | |
b188f760 AH |
14057 | (define_insn "get_vrsave_internal" |
14058 | [(set (match_operand:SI 0 "register_operand" "=r") | |
14059 | (unspec:SI [(reg:SI 109)] 214))] | |
14060 | "TARGET_ALTIVEC" | |
14061 | "* | |
14062 | { | |
14063 | if (TARGET_MACHO) | |
376aec5d | 14064 | return \"mfspr %0,256\"; |
b188f760 | 14065 | else |
376aec5d | 14066 | return \"mfvrsave %0\"; |
b188f760 AH |
14067 | }" |
14068 | [(set_attr "type" "altivec")]) | |
14069 | ||
00b960c7 AH |
14070 | (define_insn "*set_vrsave_internal" |
14071 | [(match_parallel 0 "vrsave_operation" | |
14072 | [(set (reg:SI 109) | |
a004eb82 AH |
14073 | (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r") |
14074 | (reg:SI 109)] 30))])] | |
00b960c7 | 14075 | "TARGET_ALTIVEC" |
b188f760 AH |
14076 | "* |
14077 | { | |
14078 | if (TARGET_MACHO) | |
376aec5d | 14079 | return \"mtspr 256,%1\"; |
b188f760 AH |
14080 | else |
14081 | return \"mtvrsave %1\"; | |
14082 | }" | |
00b960c7 AH |
14083 | [(set_attr "type" "altivec")]) |
14084 | ||
69ef87e2 AH |
14085 | ;; Vector clears |
14086 | (define_insn "*movv4si_const0" | |
14087 | [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") | |
14088 | (match_operand:V4SI 1 "zero_constant" ""))] | |
14089 | "TARGET_ALTIVEC" | |
14090 | "vxor %0,%0,%0" | |
14091 | [(set_attr "type" "vecsimple")]) | |
14092 | ||
14093 | (define_insn "*movv4sf_const0" | |
14094 | [(set (match_operand:V4SF 0 "altivec_register_operand" "=v") | |
14095 | (match_operand:V4SF 1 "zero_constant" ""))] | |
14096 | ||
14097 | "TARGET_ALTIVEC" | |
14098 | "vxor %0,%0,%0" | |
14099 | [(set_attr "type" "vecsimple")]) | |
14100 | ||
14101 | (define_insn "*movv8hi_const0" | |
14102 | [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") | |
14103 | (match_operand:V8HI 1 "zero_constant" ""))] | |
14104 | "TARGET_ALTIVEC" | |
14105 | "vxor %0,%0,%0" | |
14106 | [(set_attr "type" "vecsimple")]) | |
14107 | ||
14108 | (define_insn "*movv16qi_const0" | |
14109 | [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") | |
14110 | (match_operand:V16QI 1 "zero_constant" ""))] | |
14111 | "TARGET_ALTIVEC" | |
14112 | "vxor %0,%0,%0" | |
14113 | [(set_attr "type" "vecsimple")]) | |
14114 | ||
0ac081f6 AH |
14115 | ;; Simple binary operations. |
14116 | ||
f18c054f | 14117 | (define_insn "addv16qi3" |
0ac081f6 | 14118 | [(set (match_operand:V16QI 0 "register_operand" "=v") |
f18c054f DB |
14119 | (plus:V16QI (match_operand:V16QI 1 "register_operand" "v") |
14120 | (match_operand:V16QI 2 "register_operand" "v")))] | |
0ac081f6 | 14121 | "TARGET_ALTIVEC" |
9bddde52 | 14122 | "vaddubm %0,%1,%2" |
f18c054f | 14123 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14124 | |
f18c054f | 14125 | (define_insn "addv8hi3" |
0ac081f6 | 14126 | [(set (match_operand:V8HI 0 "register_operand" "=v") |
f18c054f DB |
14127 | (plus:V8HI (match_operand:V8HI 1 "register_operand" "v") |
14128 | (match_operand:V8HI 2 "register_operand" "v")))] | |
0ac081f6 | 14129 | "TARGET_ALTIVEC" |
9bddde52 | 14130 | "vadduhm %0,%1,%2" |
f18c054f | 14131 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14132 | |
f18c054f | 14133 | (define_insn "addv4si3" |
0ac081f6 | 14134 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
14135 | (plus:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14136 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 14137 | "TARGET_ALTIVEC" |
9bddde52 | 14138 | "vadduwm %0,%1,%2" |
f18c054f | 14139 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14140 | |
f18c054f | 14141 | (define_insn "addv4sf3" |
0ac081f6 | 14142 | [(set (match_operand:V4SF 0 "register_operand" "=v") |
f18c054f DB |
14143 | (plus:V4SF (match_operand:V4SF 1 "register_operand" "v") |
14144 | (match_operand:V4SF 2 "register_operand" "v")))] | |
0ac081f6 | 14145 | "TARGET_ALTIVEC" |
9bddde52 | 14146 | "vaddfp %0,%1,%2" |
f18c054f | 14147 | [(set_attr "type" "vecfloat")]) |
0ac081f6 AH |
14148 | |
14149 | (define_insn "altivec_vaddcuw" | |
14150 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14151 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14152 | (match_operand:V4SI 2 "register_operand" "v")] 35))] | |
14153 | "TARGET_ALTIVEC" | |
9bddde52 | 14154 | "vaddcuw %0,%1,%2" |
f18c054f | 14155 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14156 | |
14157 | (define_insn "altivec_vaddubs" | |
14158 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14159 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14160 | (match_operand:V16QI 2 "register_operand" "v")] 36))] | |
14161 | "TARGET_ALTIVEC" | |
9bddde52 | 14162 | "vaddubs %0,%1,%2" |
f18c054f | 14163 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14164 | |
14165 | (define_insn "altivec_vaddsbs" | |
14166 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14167 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14168 | (match_operand:V16QI 2 "register_operand" "v")] 37))] | |
14169 | "TARGET_ALTIVEC" | |
9bddde52 | 14170 | "vaddsbs %0,%1,%2" |
f18c054f | 14171 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14172 | |
14173 | (define_insn "altivec_vadduhs" | |
14174 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14175 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14176 | (match_operand:V8HI 2 "register_operand" "v")] 38))] | |
14177 | "TARGET_ALTIVEC" | |
9bddde52 | 14178 | "vadduhs %0,%1,%2" |
f18c054f | 14179 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14180 | |
14181 | (define_insn "altivec_vaddshs" | |
14182 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14183 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14184 | (match_operand:V8HI 2 "register_operand" "v")] 39))] | |
14185 | "TARGET_ALTIVEC" | |
9bddde52 | 14186 | "vaddshs %0,%1,%2" |
f18c054f | 14187 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14188 | |
14189 | (define_insn "altivec_vadduws" | |
14190 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14191 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14192 | (match_operand:V4SI 2 "register_operand" "v")] 40))] | |
14193 | "TARGET_ALTIVEC" | |
9bddde52 | 14194 | "vadduws %0,%1,%2" |
f18c054f | 14195 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14196 | |
14197 | (define_insn "altivec_vaddsws" | |
14198 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14199 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14200 | (match_operand:V4SI 2 "register_operand" "v")] 41))] | |
14201 | "TARGET_ALTIVEC" | |
9bddde52 | 14202 | "vaddsws %0,%1,%2" |
f18c054f | 14203 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14204 | |
f18c054f | 14205 | (define_insn "andv4si3" |
0ac081f6 | 14206 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
14207 | (and:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14208 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 14209 | "TARGET_ALTIVEC" |
9bddde52 | 14210 | "vand %0,%1,%2" |
f18c054f | 14211 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14212 | |
14213 | (define_insn "altivec_vandc" | |
14214 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
2212663f DB |
14215 | (and:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14216 | (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))))] | |
0ac081f6 | 14217 | "TARGET_ALTIVEC" |
9bddde52 | 14218 | "vandc %0,%1,%2" |
f18c054f | 14219 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14220 | |
14221 | (define_insn "altivec_vavgub" | |
14222 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14223 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14224 | (match_operand:V16QI 2 "register_operand" "v")] 44))] | |
14225 | "TARGET_ALTIVEC" | |
9bddde52 | 14226 | "vavgub %0,%1,%2" |
f18c054f | 14227 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14228 | |
14229 | (define_insn "altivec_vavgsb" | |
14230 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14231 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14232 | (match_operand:V16QI 2 "register_operand" "v")] 45))] | |
14233 | "TARGET_ALTIVEC" | |
9bddde52 | 14234 | "vavgsb %0,%1,%2" |
f18c054f | 14235 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14236 | |
14237 | (define_insn "altivec_vavguh" | |
14238 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14239 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14240 | (match_operand:V8HI 2 "register_operand" "v")] 46))] | |
14241 | "TARGET_ALTIVEC" | |
9bddde52 | 14242 | "vavguh %0,%1,%2" |
f18c054f | 14243 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14244 | |
14245 | (define_insn "altivec_vavgsh" | |
14246 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14247 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14248 | (match_operand:V8HI 2 "register_operand" "v")] 47))] | |
14249 | "TARGET_ALTIVEC" | |
9bddde52 | 14250 | "vavgsh %0,%1,%2" |
f18c054f | 14251 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14252 | |
14253 | (define_insn "altivec_vavguw" | |
14254 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14255 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14256 | (match_operand:V4SI 2 "register_operand" "v")] 48))] | |
14257 | "TARGET_ALTIVEC" | |
9bddde52 | 14258 | "vavguw %0,%1,%2" |
f18c054f | 14259 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14260 | |
14261 | (define_insn "altivec_vavgsw" | |
14262 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14263 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14264 | (match_operand:V4SI 2 "register_operand" "v")] 49))] | |
14265 | "TARGET_ALTIVEC" | |
9bddde52 | 14266 | "vavgsw %0,%1,%2" |
f18c054f | 14267 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14268 | |
14269 | (define_insn "altivec_vcmpbfp" | |
14270 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14271 | (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") | |
14272 | (match_operand:V4SF 2 "register_operand" "v")] 50))] | |
14273 | "TARGET_ALTIVEC" | |
9bddde52 | 14274 | "vcmpbfp %0,%1,%2" |
f18c054f | 14275 | [(set_attr "type" "veccmp")]) |
0ac081f6 AH |
14276 | |
14277 | (define_insn "altivec_vcmpequb" | |
14278 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14279 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14280 | (match_operand:V16QI 2 "register_operand" "v")] 51))] | |
14281 | "TARGET_ALTIVEC" | |
9bddde52 | 14282 | "vcmpequb %0,%1,%2" |
f18c054f | 14283 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14284 | |
14285 | (define_insn "altivec_vcmpequh" | |
14286 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14287 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14288 | (match_operand:V8HI 2 "register_operand" "v")] 52))] | |
14289 | "TARGET_ALTIVEC" | |
9bddde52 | 14290 | "vcmpequh %0,%1,%2" |
f18c054f | 14291 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14292 | |
14293 | (define_insn "altivec_vcmpequw" | |
14294 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14295 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14296 | (match_operand:V4SI 2 "register_operand" "v")] 53))] | |
14297 | "TARGET_ALTIVEC" | |
9bddde52 | 14298 | "vcmpequw %0,%1,%2" |
f18c054f | 14299 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14300 | |
14301 | (define_insn "altivec_vcmpeqfp" | |
14302 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14303 | (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") | |
14304 | (match_operand:V4SF 2 "register_operand" "v")] 54))] | |
14305 | "TARGET_ALTIVEC" | |
9bddde52 | 14306 | "vcmpeqfp %0,%1,%2" |
f18c054f | 14307 | [(set_attr "type" "veccmp")]) |
0ac081f6 AH |
14308 | |
14309 | (define_insn "altivec_vcmpgefp" | |
14310 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14311 | (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") | |
14312 | (match_operand:V4SF 2 "register_operand" "v")] 55))] | |
14313 | "TARGET_ALTIVEC" | |
9bddde52 | 14314 | "vcmpgefp %0,%1,%2" |
f18c054f | 14315 | [(set_attr "type" "veccmp")]) |
0ac081f6 AH |
14316 | |
14317 | (define_insn "altivec_vcmpgtub" | |
14318 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14319 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14320 | (match_operand:V16QI 2 "register_operand" "v")] 56))] | |
14321 | "TARGET_ALTIVEC" | |
9bddde52 | 14322 | "vcmpgtub %0,%1,%2" |
f18c054f | 14323 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14324 | |
14325 | (define_insn "altivec_vcmpgtsb" | |
14326 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14327 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14328 | (match_operand:V16QI 2 "register_operand" "v")] 57))] | |
14329 | "TARGET_ALTIVEC" | |
9bddde52 | 14330 | "vcmpgtsb %0,%1,%2" |
f18c054f | 14331 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14332 | |
14333 | (define_insn "altivec_vcmpgtuh" | |
14334 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14335 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14336 | (match_operand:V8HI 2 "register_operand" "v")] 58))] | |
14337 | "TARGET_ALTIVEC" | |
9bddde52 | 14338 | "vcmpgtuh %0,%1,%2" |
f18c054f | 14339 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14340 | |
14341 | (define_insn "altivec_vcmpgtsh" | |
14342 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14343 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14344 | (match_operand:V8HI 2 "register_operand" "v")] 59))] | |
14345 | "TARGET_ALTIVEC" | |
9bddde52 | 14346 | "vcmpgtsh %0,%1,%2" |
f18c054f | 14347 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14348 | |
14349 | (define_insn "altivec_vcmpgtuw" | |
14350 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14351 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14352 | (match_operand:V4SI 2 "register_operand" "v")] 60))] | |
14353 | "TARGET_ALTIVEC" | |
9bddde52 | 14354 | "vcmpgtuw %0,%1,%2" |
f18c054f | 14355 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14356 | |
14357 | (define_insn "altivec_vcmpgtsw" | |
14358 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14359 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14360 | (match_operand:V4SI 2 "register_operand" "v")] 61))] | |
14361 | "TARGET_ALTIVEC" | |
9bddde52 | 14362 | "vcmpgtsw %0,%1,%2" |
f18c054f | 14363 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14364 | |
14365 | (define_insn "altivec_vcmpgtfp" | |
14366 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14367 | (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") | |
14368 | (match_operand:V4SF 2 "register_operand" "v")] 62))] | |
14369 | "TARGET_ALTIVEC" | |
9bddde52 | 14370 | "vcmpgtfp %0,%1,%2" |
f18c054f | 14371 | [(set_attr "type" "veccmp")]) |
0ac081f6 | 14372 | |
2212663f DB |
14373 | ;; Fused multiply add |
14374 | (define_insn "altivec_vmaddfp" | |
14375 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
14376 | (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") | |
14377 | (match_operand:V4SF 2 "register_operand" "v")) | |
14378 | (match_operand:V4SF 3 "register_operand" "v")))] | |
14379 | "TARGET_ALTIVEC" | |
14380 | "vmaddfp %0,%1,%2,%3" | |
14381 | [(set_attr "type" "vecfloat")]) | |
14382 | ||
14383 | ;; The unspec here is a vec splat of 0. We do multiply as a fused | |
14384 | ;; multiply-add with an add of a 0 vector. | |
14385 | ||
14386 | (define_expand "mulv4sf3" | |
14387 | [(set (match_dup 3) (unspec:V4SF [(const_int 0)] 142)) | |
14388 | (set (match_operand:V4SF 0 "register_operand" "=v") | |
14389 | (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") | |
14390 | (match_operand:V4SF 2 "register_operand" "v")) | |
14391 | (match_dup 3)))] | |
14392 | "TARGET_ALTIVEC && TARGET_FUSED_MADD" | |
14393 | " | |
14394 | { operands[3] = gen_reg_rtx (V4SFmode); }") | |
14395 | ||
14396 | ;; Fused multiply subtract | |
14397 | (define_insn "altivec_vnmsubfp" | |
14398 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
14399 | (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") | |
14400 | (match_operand:V4SF 2 "register_operand" "v")) | |
14401 | (match_operand:V4SF 3 "register_operand" "v")))] | |
14402 | "TARGET_ALTIVEC" | |
95385cbb | 14403 | "vnmsubfp %0,%1,%2,%3" |
2212663f DB |
14404 | [(set_attr "type" "vecfloat")]) |
14405 | ||
14406 | ||
14407 | (define_insn "altivec_vmsumubm" | |
14408 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14409 | (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") | |
14410 | (match_operand:V16QI 2 "register_operand" "v") | |
14411 | (match_operand:V4SI 3 "register_operand" "v")] 65))] | |
14412 | "TARGET_ALTIVEC" | |
14413 | "vmsumubm %0, %1, %2, %3" | |
14414 | [(set_attr "type" "veccomplex")]) | |
14415 | ||
14416 | (define_insn "altivec_vmsummbm" | |
14417 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14418 | (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") | |
14419 | (match_operand:V16QI 2 "register_operand" "v") | |
14420 | (match_operand:V4SI 3 "register_operand" "v")] 66))] | |
14421 | "TARGET_ALTIVEC" | |
14422 | "vmsumubm %0, %1, %2, %3" | |
14423 | [(set_attr "type" "veccomplex")]) | |
14424 | ||
14425 | (define_insn "altivec_vmsumuhm" | |
14426 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14427 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
14428 | (match_operand:V8HI 2 "register_operand" "v") | |
14429 | (match_operand:V4SI 3 "register_operand" "v")] 67))] | |
14430 | "TARGET_ALTIVEC" | |
14431 | "vmsumuhm %0, %1, %2, %3" | |
14432 | [(set_attr "type" "veccomplex")]) | |
14433 | ||
14434 | (define_insn "altivec_vmsumshm" | |
14435 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14436 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
14437 | (match_operand:V8HI 2 "register_operand" "v") | |
14438 | (match_operand:V4SI 3 "register_operand" "v")] 68))] | |
14439 | "TARGET_ALTIVEC" | |
14440 | "vmsumshm %0, %1, %2, %3" | |
14441 | [(set_attr "type" "veccomplex")]) | |
14442 | ||
14443 | (define_insn "altivec_vmsumuhs" | |
14444 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14445 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
14446 | (match_operand:V8HI 2 "register_operand" "v") | |
14447 | (match_operand:V4SI 3 "register_operand" "v")] 69))] | |
14448 | "TARGET_ALTIVEC" | |
14449 | "vmsumuhs %0, %1, %2, %3" | |
14450 | [(set_attr "type" "veccomplex")]) | |
14451 | ||
14452 | (define_insn "altivec_vmsumshs" | |
14453 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14454 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
14455 | (match_operand:V8HI 2 "register_operand" "v") | |
14456 | (match_operand:V4SI 3 "register_operand" "v")] 70))] | |
14457 | "TARGET_ALTIVEC" | |
14458 | "vmsumshs %0, %1, %2, %3" | |
14459 | [(set_attr "type" "veccomplex")]) | |
14460 | ||
f18c054f | 14461 | (define_insn "umaxv16qi3" |
0ac081f6 | 14462 | [(set (match_operand:V16QI 0 "register_operand" "=v") |
f18c054f DB |
14463 | (umax:V16QI (match_operand:V16QI 1 "register_operand" "v") |
14464 | (match_operand:V16QI 2 "register_operand" "v")))] | |
0ac081f6 | 14465 | "TARGET_ALTIVEC" |
9bddde52 | 14466 | "vmaxub %0,%1,%2" |
f18c054f | 14467 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14468 | |
f18c054f | 14469 | (define_insn "smaxv16qi3" |
0ac081f6 | 14470 | [(set (match_operand:V16QI 0 "register_operand" "=v") |
f18c054f DB |
14471 | (smax:V16QI (match_operand:V16QI 1 "register_operand" "v") |
14472 | (match_operand:V16QI 2 "register_operand" "v")))] | |
0ac081f6 | 14473 | "TARGET_ALTIVEC" |
9bddde52 | 14474 | "vmaxsb %0,%1,%2" |
f18c054f | 14475 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14476 | |
f18c054f | 14477 | (define_insn "umaxv8hi3" |
0ac081f6 | 14478 | [(set (match_operand:V8HI 0 "register_operand" "=v") |
f18c054f DB |
14479 | (umax:V8HI (match_operand:V8HI 1 "register_operand" "v") |
14480 | (match_operand:V8HI 2 "register_operand" "v")))] | |
0ac081f6 | 14481 | "TARGET_ALTIVEC" |
9bddde52 | 14482 | "vmaxuh %0,%1,%2" |
f18c054f | 14483 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14484 | |
f18c054f | 14485 | (define_insn "smaxv8hi3" |
0ac081f6 | 14486 | [(set (match_operand:V8HI 0 "register_operand" "=v") |
f18c054f DB |
14487 | (smax:V8HI (match_operand:V8HI 1 "register_operand" "v") |
14488 | (match_operand:V8HI 2 "register_operand" "v")))] | |
0ac081f6 | 14489 | "TARGET_ALTIVEC" |
9bddde52 | 14490 | "vmaxsh %0,%1,%2" |
f18c054f | 14491 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14492 | |
f18c054f | 14493 | (define_insn "umaxv4si3" |
0ac081f6 | 14494 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
14495 | (umax:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14496 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 14497 | "TARGET_ALTIVEC" |
9bddde52 | 14498 | "vmaxuw %0,%1,%2" |
f18c054f | 14499 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14500 | |
f18c054f | 14501 | (define_insn "smaxv4si3" |
0ac081f6 | 14502 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
14503 | (smax:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14504 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 14505 | "TARGET_ALTIVEC" |
9bddde52 | 14506 | "vmaxsw %0,%1,%2" |
f18c054f | 14507 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14508 | |
f18c054f | 14509 | (define_insn "smaxv4sf3" |
0ac081f6 | 14510 | [(set (match_operand:V4SF 0 "register_operand" "=v") |
f18c054f DB |
14511 | (smax:V4SF (match_operand:V4SF 1 "register_operand" "v") |
14512 | (match_operand:V4SF 2 "register_operand" "v")))] | |
0ac081f6 | 14513 | "TARGET_ALTIVEC" |
9bddde52 | 14514 | "vmaxfp %0,%1,%2" |
f18c054f | 14515 | [(set_attr "type" "veccmp")]) |
0ac081f6 | 14516 | |
2212663f DB |
14517 | (define_insn "altivec_vmhaddshs" |
14518 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14519 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14520 | (match_operand:V8HI 2 "register_operand" "v") | |
14521 | (match_operand:V8HI 3 "register_operand" "v")] 71))] | |
14522 | "TARGET_ALTIVEC" | |
14523 | "vmhaddshs %0, %1, %2, %3" | |
14524 | [(set_attr "type" "veccomplex")]) | |
14525 | (define_insn "altivec_vmhraddshs" | |
14526 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14527 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14528 | (match_operand:V8HI 2 "register_operand" "v") | |
14529 | (match_operand:V8HI 3 "register_operand" "v")] 72))] | |
14530 | "TARGET_ALTIVEC" | |
14531 | "vmhraddshs %0, %1, %2, %3" | |
14532 | [(set_attr "type" "veccomplex")]) | |
14533 | (define_insn "altivec_vmladduhm" | |
14534 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14535 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14536 | (match_operand:V8HI 2 "register_operand" "v") | |
14537 | (match_operand:V8HI 3 "register_operand" "v")] 73))] | |
14538 | "TARGET_ALTIVEC" | |
14539 | "vmladduhm %0, %1, %2, %3" | |
14540 | [(set_attr "type" "veccomplex")]) | |
14541 | ||
0ac081f6 AH |
14542 | (define_insn "altivec_vmrghb" |
14543 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
2212663f DB |
14544 | (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v") |
14545 | (parallel [(const_int 8) | |
14546 | (const_int 9) | |
14547 | (const_int 10) | |
14548 | (const_int 11) | |
14549 | (const_int 12) | |
14550 | (const_int 13) | |
14551 | (const_int 14) | |
14552 | (const_int 15) | |
14553 | (const_int 0) | |
14554 | (const_int 1) | |
14555 | (const_int 2) | |
14556 | (const_int 3) | |
14557 | (const_int 4) | |
14558 | (const_int 5) | |
14559 | (const_int 6) | |
14560 | (const_int 7)])) | |
14561 | (match_operand:V16QI 2 "register_operand" "v") | |
14562 | (const_int 255)))] | |
0ac081f6 | 14563 | "TARGET_ALTIVEC" |
9bddde52 | 14564 | "vmrghb %0,%1,%2" |
f18c054f | 14565 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14566 | |
14567 | (define_insn "altivec_vmrghh" | |
14568 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
2212663f DB |
14569 | (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v") |
14570 | (parallel [(const_int 4) | |
14571 | (const_int 5) | |
14572 | (const_int 6) | |
14573 | (const_int 7) | |
14574 | (const_int 0) | |
14575 | (const_int 1) | |
14576 | (const_int 2) | |
14577 | (const_int 3)])) | |
14578 | (match_operand:V8HI 2 "register_operand" "v") | |
14579 | (const_int 15)))] | |
0ac081f6 | 14580 | "TARGET_ALTIVEC" |
9bddde52 | 14581 | "vmrghh %0,%1,%2" |
f18c054f | 14582 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14583 | |
14584 | (define_insn "altivec_vmrghw" | |
14585 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
2212663f DB |
14586 | (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14587 | (parallel [(const_int 2) | |
14588 | (const_int 3) | |
14589 | (const_int 0) | |
14590 | (const_int 1)])) | |
14591 | (match_operand:V4SI 2 "register_operand" "v") | |
14592 | (const_int 12)))] | |
0ac081f6 | 14593 | "TARGET_ALTIVEC" |
9bddde52 | 14594 | "vmrghw %0,%1,%2" |
f18c054f | 14595 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14596 | |
14597 | (define_insn "altivec_vmrglb" | |
14598 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
2212663f | 14599 | (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v") |
a50cfd52 DE |
14600 | |
14601 | (parallel [(const_int 0) | |
2212663f DB |
14602 | (const_int 1) |
14603 | (const_int 2) | |
14604 | (const_int 3) | |
14605 | (const_int 4) | |
14606 | (const_int 5) | |
a50cfd52 DE |
14607 | (const_int 6) |
14608 | (const_int 7) | |
14609 | (const_int 8) | |
14610 | (const_int 9) | |
14611 | (const_int 10) | |
14612 | (const_int 11) | |
14613 | (const_int 12) | |
14614 | (const_int 13) | |
14615 | (const_int 14) | |
14616 | (const_int 15)])) | |
2212663f DB |
14617 | (match_operand:V16QI 1 "register_operand" "v") |
14618 | (const_int 255)))] | |
0ac081f6 | 14619 | "TARGET_ALTIVEC" |
9bddde52 | 14620 | "vmrglb %0,%1,%2" |
f18c054f | 14621 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14622 | |
14623 | (define_insn "altivec_vmrglh" | |
14624 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
2212663f | 14625 | (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v") |
a50cfd52 | 14626 | (parallel [(const_int 0) |
2212663f DB |
14627 | (const_int 1) |
14628 | (const_int 2) | |
a50cfd52 DE |
14629 | (const_int 3) |
14630 | (const_int 4) | |
14631 | (const_int 5) | |
14632 | (const_int 6) | |
14633 | (const_int 7)])) | |
2212663f DB |
14634 | (match_operand:V8HI 1 "register_operand" "v") |
14635 | (const_int 15)))] | |
0ac081f6 | 14636 | "TARGET_ALTIVEC" |
9bddde52 | 14637 | "vmrglh %0,%1,%2" |
f18c054f | 14638 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14639 | |
14640 | (define_insn "altivec_vmrglw" | |
14641 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
2212663f | 14642 | (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v") |
a50cfd52 DE |
14643 | (parallel [(const_int 0) |
14644 | (const_int 1) | |
14645 | (const_int 2) | |
14646 | (const_int 3)])) | |
2212663f DB |
14647 | (match_operand:V4SI 1 "register_operand" "v") |
14648 | (const_int 12)))] | |
0ac081f6 | 14649 | "TARGET_ALTIVEC" |
9bddde52 | 14650 | "vmrglw %0,%1,%2" |
f18c054f | 14651 | [(set_attr "type" "vecperm")]) |
0ac081f6 | 14652 | |
f18c054f | 14653 | (define_insn "uminv16qi3" |
0ac081f6 | 14654 | [(set (match_operand:V16QI 0 "register_operand" "=v") |
f18c054f DB |
14655 | (umin:V16QI (match_operand:V16QI 1 "register_operand" "v") |
14656 | (match_operand:V16QI 2 "register_operand" "v")))] | |
0ac081f6 | 14657 | "TARGET_ALTIVEC" |
9bddde52 | 14658 | "vminub %0,%1,%2" |
f18c054f | 14659 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14660 | |
f18c054f | 14661 | (define_insn "sminv16qi3" |
0ac081f6 | 14662 | [(set (match_operand:V16QI 0 "register_operand" "=v") |
f18c054f DB |
14663 | (smin:V16QI (match_operand:V16QI 1 "register_operand" "v") |
14664 | (match_operand:V16QI 2 "register_operand" "v")))] | |
0ac081f6 | 14665 | "TARGET_ALTIVEC" |
9bddde52 | 14666 | "vminsb %0,%1,%2" |
f18c054f | 14667 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14668 | |
f18c054f | 14669 | (define_insn "uminv8hi3" |
0ac081f6 | 14670 | [(set (match_operand:V8HI 0 "register_operand" "=v") |
f18c054f DB |
14671 | (umin:V8HI (match_operand:V8HI 1 "register_operand" "v") |
14672 | (match_operand:V8HI 2 "register_operand" "v")))] | |
0ac081f6 | 14673 | "TARGET_ALTIVEC" |
9bddde52 | 14674 | "vminuh %0,%1,%2" |
f18c054f | 14675 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14676 | |
f18c054f | 14677 | (define_insn "sminv8hi3" |
0ac081f6 | 14678 | [(set (match_operand:V8HI 0 "register_operand" "=v") |
f18c054f DB |
14679 | (smin:V8HI (match_operand:V8HI 1 "register_operand" "v") |
14680 | (match_operand:V8HI 2 "register_operand" "v")))] | |
0ac081f6 | 14681 | "TARGET_ALTIVEC" |
9bddde52 | 14682 | "vminsh %0,%1,%2" |
f18c054f | 14683 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14684 | |
f18c054f | 14685 | (define_insn "uminv4si3" |
0ac081f6 | 14686 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
14687 | (umin:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14688 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 14689 | "TARGET_ALTIVEC" |
9bddde52 | 14690 | "vminuw %0,%1,%2" |
f18c054f | 14691 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14692 | |
f18c054f | 14693 | (define_insn "sminv4si3" |
0ac081f6 | 14694 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
14695 | (smin:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14696 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 14697 | "TARGET_ALTIVEC" |
9bddde52 | 14698 | "vminsw %0,%1,%2" |
f18c054f | 14699 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14700 | |
f18c054f | 14701 | (define_insn "sminv4sf3" |
0ac081f6 | 14702 | [(set (match_operand:V4SF 0 "register_operand" "=v") |
f18c054f DB |
14703 | (smin:V4SF (match_operand:V4SF 1 "register_operand" "v") |
14704 | (match_operand:V4SF 2 "register_operand" "v")))] | |
0ac081f6 | 14705 | "TARGET_ALTIVEC" |
9bddde52 | 14706 | "vminfp %0,%1,%2" |
f18c054f | 14707 | [(set_attr "type" "veccmp")]) |
0ac081f6 AH |
14708 | |
14709 | (define_insn "altivec_vmuleub" | |
14710 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14711 | (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") | |
14712 | (match_operand:V16QI 2 "register_operand" "v")] 83))] | |
14713 | "TARGET_ALTIVEC" | |
9bddde52 | 14714 | "vmuleub %0,%1,%2" |
f18c054f | 14715 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
14716 | |
14717 | (define_insn "altivec_vmulesb" | |
14718 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14719 | (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") | |
14720 | (match_operand:V16QI 2 "register_operand" "v")] 84))] | |
14721 | "TARGET_ALTIVEC" | |
9bddde52 | 14722 | "vmulesb %0,%1,%2" |
f18c054f | 14723 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
14724 | |
14725 | (define_insn "altivec_vmuleuh" | |
14726 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14727 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
14728 | (match_operand:V8HI 2 "register_operand" "v")] 85))] | |
14729 | "TARGET_ALTIVEC" | |
9bddde52 | 14730 | "vmuleuh %0,%1,%2" |
f18c054f | 14731 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
14732 | |
14733 | (define_insn "altivec_vmulesh" | |
14734 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14735 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
14736 | (match_operand:V8HI 2 "register_operand" "v")] 86))] | |
14737 | "TARGET_ALTIVEC" | |
9bddde52 | 14738 | "vmulesh %0,%1,%2" |
f18c054f | 14739 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
14740 | |
14741 | (define_insn "altivec_vmuloub" | |
14742 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14743 | (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") | |
14744 | (match_operand:V16QI 2 "register_operand" "v")] 87))] | |
14745 | "TARGET_ALTIVEC" | |
9bddde52 | 14746 | "vmuloub %0,%1,%2" |
f18c054f | 14747 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
14748 | |
14749 | (define_insn "altivec_vmulosb" | |
14750 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14751 | (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") | |
14752 | (match_operand:V16QI 2 "register_operand" "v")] 88))] | |
14753 | "TARGET_ALTIVEC" | |
9bddde52 | 14754 | "vmulosb %0,%1,%2" |
f18c054f | 14755 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
14756 | |
14757 | (define_insn "altivec_vmulouh" | |
14758 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14759 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
14760 | (match_operand:V8HI 2 "register_operand" "v")] 89))] | |
14761 | "TARGET_ALTIVEC" | |
9bddde52 | 14762 | "vmulouh %0,%1,%2" |
f18c054f | 14763 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
14764 | |
14765 | (define_insn "altivec_vmulosh" | |
14766 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14767 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
14768 | (match_operand:V8HI 2 "register_operand" "v")] 90))] | |
14769 | "TARGET_ALTIVEC" | |
9bddde52 | 14770 | "vmulosh %0,%1,%2" |
f18c054f | 14771 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
14772 | |
14773 | (define_insn "altivec_vnor" | |
14774 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
f18c054f DB |
14775 | (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14776 | (match_operand:V4SI 2 "register_operand" "v"))))] | |
0ac081f6 | 14777 | "TARGET_ALTIVEC" |
9bddde52 | 14778 | "vnor %0,%1,%2" |
f18c054f | 14779 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14780 | |
f18c054f | 14781 | (define_insn "iorv4si3" |
0ac081f6 | 14782 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
14783 | (ior:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14784 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 14785 | "TARGET_ALTIVEC" |
9bddde52 | 14786 | "vor %0,%1,%2" |
f18c054f | 14787 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14788 | |
14789 | (define_insn "altivec_vpkuhum" | |
14790 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14791 | (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") | |
14792 | (match_operand:V8HI 2 "register_operand" "v")] 93))] | |
14793 | "TARGET_ALTIVEC" | |
9bddde52 | 14794 | "vpkuhum %0,%1,%2" |
f18c054f | 14795 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14796 | |
14797 | (define_insn "altivec_vpkuwum" | |
14798 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14799 | (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") | |
14800 | (match_operand:V4SI 2 "register_operand" "v")] 94))] | |
14801 | "TARGET_ALTIVEC" | |
9bddde52 | 14802 | "vpkuwum %0,%1,%2" |
f18c054f | 14803 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14804 | |
14805 | (define_insn "altivec_vpkpx" | |
14806 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14807 | (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") | |
14808 | (match_operand:V4SI 2 "register_operand" "v")] 95))] | |
14809 | "TARGET_ALTIVEC" | |
9bddde52 | 14810 | "vpkpx %0,%1,%2" |
f18c054f | 14811 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14812 | |
14813 | (define_insn "altivec_vpkuhss" | |
14814 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14815 | (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") | |
14816 | (match_operand:V8HI 2 "register_operand" "v")] 96))] | |
14817 | "TARGET_ALTIVEC" | |
9bddde52 | 14818 | "vpkuhss %0,%1,%2" |
f18c054f | 14819 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14820 | |
14821 | (define_insn "altivec_vpkshss" | |
14822 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14823 | (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") | |
14824 | (match_operand:V8HI 2 "register_operand" "v")] 97))] | |
14825 | "TARGET_ALTIVEC" | |
9bddde52 | 14826 | "vpkshss %0,%1,%2" |
f18c054f | 14827 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14828 | |
14829 | (define_insn "altivec_vpkuwss" | |
14830 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14831 | (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") | |
14832 | (match_operand:V4SI 2 "register_operand" "v")] 98))] | |
14833 | "TARGET_ALTIVEC" | |
9bddde52 | 14834 | "vpkuwss %0,%1,%2" |
f18c054f | 14835 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14836 | |
14837 | (define_insn "altivec_vpkswss" | |
14838 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14839 | (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") | |
14840 | (match_operand:V4SI 2 "register_operand" "v")] 99))] | |
14841 | "TARGET_ALTIVEC" | |
9bddde52 | 14842 | "vpkswss %0,%1,%2" |
f18c054f | 14843 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14844 | |
14845 | (define_insn "altivec_vpkuhus" | |
14846 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14847 | (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") | |
14848 | (match_operand:V8HI 2 "register_operand" "v")] 100))] | |
14849 | "TARGET_ALTIVEC" | |
9bddde52 | 14850 | "vpkuhus %0,%1,%2" |
f18c054f | 14851 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14852 | |
14853 | (define_insn "altivec_vpkshus" | |
14854 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14855 | (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") | |
14856 | (match_operand:V8HI 2 "register_operand" "v")] 101))] | |
14857 | "TARGET_ALTIVEC" | |
9bddde52 | 14858 | "vpkshus %0,%1,%2" |
f18c054f | 14859 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14860 | |
14861 | (define_insn "altivec_vpkuwus" | |
14862 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14863 | (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") | |
14864 | (match_operand:V4SI 2 "register_operand" "v")] 102))] | |
14865 | "TARGET_ALTIVEC" | |
9bddde52 | 14866 | "vpkuwus %0,%1,%2" |
f18c054f | 14867 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14868 | |
14869 | (define_insn "altivec_vpkswus" | |
14870 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14871 | (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") | |
14872 | (match_operand:V4SI 2 "register_operand" "v")] 103))] | |
14873 | "TARGET_ALTIVEC" | |
9bddde52 | 14874 | "vpkswus %0,%1,%2" |
f18c054f | 14875 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14876 | |
14877 | (define_insn "altivec_vrlb" | |
14878 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14879 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14880 | (match_operand:V16QI 2 "register_operand" "v")] 104))] | |
14881 | "TARGET_ALTIVEC" | |
9bddde52 | 14882 | "vrlb %0,%1,%2" |
f18c054f | 14883 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14884 | |
14885 | (define_insn "altivec_vrlh" | |
14886 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14887 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14888 | (match_operand:V8HI 2 "register_operand" "v")] 105))] | |
14889 | "TARGET_ALTIVEC" | |
9bddde52 | 14890 | "vrlh %0,%1,%2" |
f18c054f | 14891 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14892 | |
14893 | (define_insn "altivec_vrlw" | |
14894 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14895 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14896 | (match_operand:V4SI 2 "register_operand" "v")] 106))] | |
14897 | "TARGET_ALTIVEC" | |
9bddde52 | 14898 | "vrlw %0,%1,%2" |
f18c054f | 14899 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14900 | |
14901 | (define_insn "altivec_vslb" | |
14902 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14903 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14904 | (match_operand:V16QI 2 "register_operand" "v")] 107))] | |
14905 | "TARGET_ALTIVEC" | |
9bddde52 | 14906 | "vslb %0,%1,%2" |
f18c054f | 14907 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14908 | |
14909 | (define_insn "altivec_vslh" | |
14910 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14911 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14912 | (match_operand:V8HI 2 "register_operand" "v")] 108))] | |
14913 | "TARGET_ALTIVEC" | |
9bddde52 | 14914 | "vslh %0,%1,%2" |
f18c054f | 14915 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14916 | |
14917 | (define_insn "altivec_vslw" | |
14918 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14919 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14920 | (match_operand:V4SI 2 "register_operand" "v")] 109))] | |
14921 | "TARGET_ALTIVEC" | |
9bddde52 | 14922 | "vslw %0,%1,%2" |
f18c054f | 14923 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14924 | |
14925 | (define_insn "altivec_vsl" | |
14926 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14927 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14928 | (match_operand:V4SI 2 "register_operand" "v")] 110))] | |
14929 | "TARGET_ALTIVEC" | |
9bddde52 | 14930 | "vsl %0,%1,%2" |
f18c054f | 14931 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14932 | |
14933 | (define_insn "altivec_vslo" | |
14934 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14935 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14936 | (match_operand:V4SI 2 "register_operand" "v")] 111))] | |
14937 | "TARGET_ALTIVEC" | |
9bddde52 | 14938 | "vslo %0,%1,%2" |
f18c054f | 14939 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14940 | |
14941 | (define_insn "altivec_vsrb" | |
14942 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14943 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14944 | (match_operand:V16QI 2 "register_operand" "v")] 112))] | |
14945 | "TARGET_ALTIVEC" | |
9bddde52 | 14946 | "vsrb %0,%1,%2" |
f18c054f | 14947 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14948 | |
f18c054f | 14949 | (define_insn "altivec_vsrh" |
0ac081f6 AH |
14950 | [(set (match_operand:V8HI 0 "register_operand" "=v") |
14951 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14952 | (match_operand:V8HI 2 "register_operand" "v")] 113))] | |
14953 | "TARGET_ALTIVEC" | |
f18c054f DB |
14954 | "vsrh %0,%1,%2" |
14955 | [(set_attr "type" "vecsimple")]) | |
0ac081f6 | 14956 | |
f18c054f | 14957 | (define_insn "altivec_vsrw" |
0ac081f6 AH |
14958 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
14959 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14960 | (match_operand:V4SI 2 "register_operand" "v")] 114))] | |
14961 | "TARGET_ALTIVEC" | |
f18c054f DB |
14962 | "vsrw %0,%1,%2" |
14963 | [(set_attr "type" "vecsimple")]) | |
0ac081f6 AH |
14964 | |
14965 | (define_insn "altivec_vsrab" | |
14966 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14967 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14968 | (match_operand:V16QI 2 "register_operand" "v")] 115))] | |
14969 | "TARGET_ALTIVEC" | |
9bddde52 | 14970 | "vsrab %0,%1,%2" |
f18c054f | 14971 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14972 | |
14973 | (define_insn "altivec_vsrah" | |
14974 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14975 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14976 | (match_operand:V8HI 2 "register_operand" "v")] 116))] | |
14977 | "TARGET_ALTIVEC" | |
9bddde52 | 14978 | "vsrah %0,%1,%2" |
f18c054f | 14979 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14980 | |
14981 | (define_insn "altivec_vsraw" | |
14982 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14983 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14984 | (match_operand:V4SI 2 "register_operand" "v")] 117))] | |
14985 | "TARGET_ALTIVEC" | |
9bddde52 | 14986 | "vsraw %0,%1,%2" |
f18c054f | 14987 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14988 | |
14989 | (define_insn "altivec_vsr" | |
14990 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14991 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14992 | (match_operand:V4SI 2 "register_operand" "v")] 118))] | |
14993 | "TARGET_ALTIVEC" | |
9bddde52 | 14994 | "vsr %0,%1,%2" |
f18c054f | 14995 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14996 | |
14997 | (define_insn "altivec_vsro" | |
14998 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14999 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15000 | (match_operand:V4SI 2 "register_operand" "v")] 119))] | |
15001 | "TARGET_ALTIVEC" | |
9bddde52 | 15002 | "vsro %0,%1,%2" |
f18c054f | 15003 | [(set_attr "type" "vecperm")]) |
0ac081f6 | 15004 | |
f18c054f | 15005 | (define_insn "subv16qi3" |
0ac081f6 | 15006 | [(set (match_operand:V16QI 0 "register_operand" "=v") |
f18c054f DB |
15007 | (minus:V16QI (match_operand:V16QI 1 "register_operand" "v") |
15008 | (match_operand:V16QI 2 "register_operand" "v")))] | |
0ac081f6 | 15009 | "TARGET_ALTIVEC" |
9bddde52 | 15010 | "vsububm %0,%1,%2" |
f18c054f | 15011 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 15012 | |
f18c054f | 15013 | (define_insn "subv8hi3" |
0ac081f6 | 15014 | [(set (match_operand:V8HI 0 "register_operand" "=v") |
f18c054f DB |
15015 | (minus:V8HI (match_operand:V8HI 1 "register_operand" "v") |
15016 | (match_operand:V8HI 2 "register_operand" "v")))] | |
0ac081f6 | 15017 | "TARGET_ALTIVEC" |
9bddde52 | 15018 | "vsubuhm %0,%1,%2" |
f18c054f | 15019 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 15020 | |
f18c054f | 15021 | (define_insn "subv4si3" |
0ac081f6 | 15022 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
15023 | (minus:V4SI (match_operand:V4SI 1 "register_operand" "v") |
15024 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 15025 | "TARGET_ALTIVEC" |
9bddde52 | 15026 | "vsubuwm %0,%1,%2" |
f18c054f | 15027 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 15028 | |
f18c054f | 15029 | (define_insn "subv4sf3" |
0ac081f6 | 15030 | [(set (match_operand:V4SF 0 "register_operand" "=v") |
f18c054f DB |
15031 | (minus:V4SF (match_operand:V4SF 1 "register_operand" "v") |
15032 | (match_operand:V4SF 2 "register_operand" "v")))] | |
0ac081f6 | 15033 | "TARGET_ALTIVEC" |
9bddde52 | 15034 | "vsubfp %0,%1,%2" |
f18c054f | 15035 | [(set_attr "type" "vecfloat")]) |
0ac081f6 AH |
15036 | |
15037 | (define_insn "altivec_vsubcuw" | |
15038 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15039 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15040 | (match_operand:V4SI 2 "register_operand" "v")] 124))] | |
15041 | "TARGET_ALTIVEC" | |
9bddde52 | 15042 | "vsubcuw %0,%1,%2" |
f18c054f | 15043 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15044 | |
15045 | (define_insn "altivec_vsububs" | |
15046 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15047 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
15048 | (match_operand:V16QI 2 "register_operand" "v")] 125))] | |
15049 | "TARGET_ALTIVEC" | |
9bddde52 | 15050 | "vsububs %0,%1,%2" |
f18c054f | 15051 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15052 | |
15053 | (define_insn "altivec_vsubsbs" | |
15054 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15055 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
15056 | (match_operand:V16QI 2 "register_operand" "v")] 126))] | |
15057 | "TARGET_ALTIVEC" | |
9bddde52 | 15058 | "vsubsbs %0,%1,%2" |
f18c054f | 15059 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15060 | |
15061 | (define_insn "altivec_vsubuhs" | |
15062 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15063 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
15064 | (match_operand:V8HI 2 "register_operand" "v")] 127))] | |
15065 | "TARGET_ALTIVEC" | |
9bddde52 | 15066 | "vsubuhs %0,%1,%2" |
f18c054f | 15067 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15068 | |
15069 | (define_insn "altivec_vsubshs" | |
15070 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15071 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
15072 | (match_operand:V8HI 2 "register_operand" "v")] 128))] | |
15073 | "TARGET_ALTIVEC" | |
9bddde52 | 15074 | "vsubshs %0,%1,%2" |
f18c054f | 15075 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15076 | |
15077 | (define_insn "altivec_vsubuws" | |
15078 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15079 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15080 | (match_operand:V4SI 2 "register_operand" "v")] 129))] | |
15081 | "TARGET_ALTIVEC" | |
9bddde52 | 15082 | "vsubuws %0,%1,%2" |
f18c054f | 15083 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15084 | |
15085 | (define_insn "altivec_vsubsws" | |
15086 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15087 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15088 | (match_operand:V4SI 2 "register_operand" "v")] 130))] | |
15089 | "TARGET_ALTIVEC" | |
9bddde52 | 15090 | "vsubsws %0,%1,%2" |
f18c054f | 15091 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15092 | |
15093 | (define_insn "altivec_vsum4ubs" | |
15094 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15095 | (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") | |
15096 | (match_operand:V4SI 2 "register_operand" "v")] 131))] | |
15097 | "TARGET_ALTIVEC" | |
9bddde52 | 15098 | "vsum4ubs %0,%1,%2" |
f18c054f | 15099 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15100 | |
15101 | (define_insn "altivec_vsum4sbs" | |
15102 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15103 | (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") | |
15104 | (match_operand:V4SI 2 "register_operand" "v")] 132))] | |
15105 | "TARGET_ALTIVEC" | |
9bddde52 | 15106 | "vsum4sbs %0,%1,%2" |
f18c054f | 15107 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15108 | |
15109 | (define_insn "altivec_vsum4shs" | |
15110 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15111 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
15112 | (match_operand:V4SI 2 "register_operand" "v")] 133))] | |
15113 | "TARGET_ALTIVEC" | |
9bddde52 | 15114 | "vsum4shs %0,%1,%2" |
f18c054f | 15115 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15116 | |
15117 | (define_insn "altivec_vsum2sws" | |
15118 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15119 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15120 | (match_operand:V4SI 2 "register_operand" "v")] 134))] | |
15121 | "TARGET_ALTIVEC" | |
9bddde52 | 15122 | "vsum2sws %0,%1,%2" |
f18c054f | 15123 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15124 | |
15125 | (define_insn "altivec_vsumsws" | |
15126 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15127 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15128 | (match_operand:V4SI 2 "register_operand" "v")] 135))] | |
15129 | "TARGET_ALTIVEC" | |
9bddde52 | 15130 | "vsumsws %0,%1,%2" |
f18c054f | 15131 | [(set_attr "type" "veccomplex")]) |
0ac081f6 | 15132 | |
f18c054f | 15133 | (define_insn "xorv4si3" |
0ac081f6 | 15134 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
15135 | (xor:V4SI (match_operand:V4SI 1 "register_operand" "v") |
15136 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 15137 | "TARGET_ALTIVEC" |
9bddde52 | 15138 | "vxor %0,%1,%2" |
f18c054f | 15139 | [(set_attr "type" "vecsimple")]) |
2212663f DB |
15140 | |
15141 | (define_insn "altivec_vspltb" | |
15142 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15143 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
15144 | (match_operand:QI 2 "immediate_operand" "i")] 136))] | |
15145 | "TARGET_ALTIVEC" | |
15146 | "vspltb %0,%1,%2" | |
15147 | [(set_attr "type" "vecperm")]) | |
100c4561 | 15148 | |
2212663f DB |
15149 | (define_insn "altivec_vsplth" |
15150 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15151 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
15152 | (match_operand:QI 2 "immediate_operand" "i")] 137))] | |
15153 | "TARGET_ALTIVEC" | |
15154 | "vsplth %0,%1,%2" | |
15155 | [(set_attr "type" "vecperm")]) | |
15156 | ||
15157 | (define_insn "altivec_vspltw" | |
15158 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15159 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15160 | (match_operand:QI 2 "immediate_operand" "i")] 138))] | |
15161 | "TARGET_ALTIVEC" | |
15162 | "vspltw %0,%1,%2" | |
15163 | [(set_attr "type" "vecperm")]) | |
15164 | ||
15165 | (define_insn "altivec_vspltisb" | |
15166 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15167 | (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")] 139))] | |
15168 | "TARGET_ALTIVEC" | |
15169 | "vspltisb %0, %1" | |
15170 | [(set_attr "type" "vecsimple")]) | |
15171 | ||
15172 | ||
15173 | (define_insn "altivec_vspltish" | |
15174 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15175 | (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")] 140))] | |
15176 | "TARGET_ALTIVEC" | |
15177 | "vspltish %0, %1" | |
15178 | [(set_attr "type" "vecsimple")]) | |
15179 | ||
15180 | (define_insn "altivec_vspltisw" | |
15181 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15182 | (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")] 141))] | |
15183 | "TARGET_ALTIVEC" | |
15184 | "vspltisw %0, %1" | |
15185 | [(set_attr "type" "vecsimple")]) | |
15186 | ||
15187 | (define_insn "" | |
15188 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15189 | (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))] | |
15190 | "TARGET_ALTIVEC" | |
15191 | "vspltisw %0, %1" | |
15192 | [(set_attr "type" "vecsimple")]) | |
15193 | ||
15194 | (define_insn "ftruncv4sf2" | |
617e0e1d DB |
15195 | [(set (match_operand:V4SF 0 "register_operand" "=v") |
15196 | (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))] | |
15197 | "TARGET_ALTIVEC" | |
15198 | "vrfiz %0, %1" | |
15199 | [(set_attr "type" "vecfloat")]) | |
2212663f DB |
15200 | |
15201 | (define_insn "altivec_vperm_4si" | |
15202 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15203 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15204 | (match_operand:V4SI 2 "register_operand" "v") | |
15205 | (match_operand:V16QI 3 "register_operand" "v")] 144))] | |
15206 | "TARGET_ALTIVEC" | |
15207 | "vperm %0,%1,%2,%3" | |
15208 | [(set_attr "type" "vecperm")]) | |
15209 | ||
15210 | (define_insn "altivec_vperm_4sf" | |
15211 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15212 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") | |
15213 | (match_operand:V4SF 2 "register_operand" "v") | |
15214 | (match_operand:V16QI 3 "register_operand" "v")] 145))] | |
15215 | "TARGET_ALTIVEC" | |
15216 | "vperm %0,%1,%2,%3" | |
15217 | [(set_attr "type" "vecperm")]) | |
15218 | ||
15219 | (define_insn "altivec_vperm_8hi" | |
15220 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15221 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
15222 | (match_operand:V8HI 2 "register_operand" "v") | |
15223 | (match_operand:V16QI 3 "register_operand" "v")] 146))] | |
15224 | "TARGET_ALTIVEC" | |
15225 | "vperm %0,%1,%2,%3" | |
15226 | [(set_attr "type" "vecperm")]) | |
15227 | ||
15228 | (define_insn "altivec_vperm_16qi" | |
15229 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15230 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
15231 | (match_operand:V16QI 2 "register_operand" "v") | |
15232 | (match_operand:V16QI 3 "register_operand" "v")] 147))] | |
15233 | "TARGET_ALTIVEC" | |
15234 | "vperm %0,%1,%2,%3" | |
15235 | [(set_attr "type" "vecperm")]) | |
617e0e1d DB |
15236 | |
15237 | (define_insn "altivec_vrfip" | |
15238 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15239 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))] | |
15240 | "TARGET_ALTIVEC" | |
15241 | "vrfip %0, %1" | |
15242 | [(set_attr "type" "vecfloat")]) | |
15243 | ||
15244 | (define_insn "altivec_vrfin" | |
15245 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15246 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))] | |
15247 | "TARGET_ALTIVEC" | |
15248 | "vrfin %0, %1" | |
15249 | [(set_attr "type" "vecfloat")]) | |
15250 | ||
15251 | (define_insn "altivec_vrfim" | |
15252 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15253 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))] | |
15254 | "TARGET_ALTIVEC" | |
15255 | "vrfim %0, %1" | |
15256 | [(set_attr "type" "vecfloat")]) | |
15257 | ||
15258 | (define_insn "altivec_vcfux" | |
15259 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15260 | (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") | |
15261 | (match_operand:QI 2 "immediate_operand" "i")] 151))] | |
15262 | "TARGET_ALTIVEC" | |
15263 | "vcfux %0, %1, %2" | |
15264 | [(set_attr "type" "vecfloat")]) | |
15265 | ||
15266 | (define_insn "altivec_vcfsx" | |
15267 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15268 | (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") | |
15269 | (match_operand:QI 2 "immediate_operand" "i")] 152))] | |
15270 | "TARGET_ALTIVEC" | |
15271 | "vcfsx %0, %1, %2" | |
15272 | [(set_attr "type" "vecfloat")]) | |
15273 | ||
15274 | (define_insn "altivec_vctuxs" | |
15275 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15276 | (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") | |
15277 | (match_operand:QI 2 "immediate_operand" "i")] 153))] | |
15278 | "TARGET_ALTIVEC" | |
95385cbb | 15279 | "vctuxs %0, %1, %2" |
617e0e1d DB |
15280 | [(set_attr "type" "vecfloat")]) |
15281 | ||
15282 | (define_insn "altivec_vctsxs" | |
15283 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15284 | (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") | |
15285 | (match_operand:QI 2 "immediate_operand" "i")] 154))] | |
15286 | "TARGET_ALTIVEC" | |
15287 | "vctsxs %0, %1, %2" | |
15288 | [(set_attr "type" "vecfloat")]) | |
15289 | ||
15290 | (define_insn "altivec_vlogefp" | |
15291 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15292 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))] | |
15293 | "TARGET_ALTIVEC" | |
15294 | "vlogefp %0, %1" | |
15295 | [(set_attr "type" "vecfloat")]) | |
15296 | ||
15297 | (define_insn "altivec_vexptefp" | |
15298 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15299 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))] | |
15300 | "TARGET_ALTIVEC" | |
15301 | "vexptefp %0, %1" | |
15302 | [(set_attr "type" "vecfloat")]) | |
15303 | ||
15304 | (define_insn "altivec_vrsqrtefp" | |
15305 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15306 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))] | |
15307 | "TARGET_ALTIVEC" | |
15308 | "vrsqrtefp %0, %1" | |
15309 | [(set_attr "type" "vecfloat")]) | |
15310 | ||
15311 | (define_insn "altivec_vrefp" | |
15312 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15313 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))] | |
15314 | "TARGET_ALTIVEC" | |
15315 | "vrefp %0, %1" | |
15316 | [(set_attr "type" "vecfloat")]) | |
15317 | ||
15318 | (define_insn "altivec_vsel_4si" | |
15319 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15320 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15321 | (match_operand:V4SI 2 "register_operand" "v") | |
15322 | (match_operand:V4SI 3 "register_operand" "v")] 159))] | |
15323 | "TARGET_ALTIVEC" | |
15324 | "vsel %0,%1,%2,%3" | |
15325 | [(set_attr "type" "vecperm")]) | |
15326 | ||
15327 | (define_insn "altivec_vsel_4sf" | |
15328 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15329 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") | |
15330 | (match_operand:V4SF 2 "register_operand" "v") | |
15331 | (match_operand:V4SI 3 "register_operand" "v")] 160))] | |
15332 | "TARGET_ALTIVEC" | |
15333 | "vsel %0,%1,%2,%3" | |
15334 | [(set_attr "type" "vecperm")]) | |
15335 | ||
15336 | (define_insn "altivec_vsel_8hi" | |
15337 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15338 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
15339 | (match_operand:V8HI 2 "register_operand" "v") | |
15340 | (match_operand:V8HI 3 "register_operand" "v")] 161))] | |
15341 | "TARGET_ALTIVEC" | |
15342 | "vsel %0,%1,%2,%3" | |
15343 | [(set_attr "type" "vecperm")]) | |
15344 | ||
15345 | (define_insn "altivec_vsel_16qi" | |
15346 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15347 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
15348 | (match_operand:V16QI 2 "register_operand" "v") | |
15349 | (match_operand:V16QI 3 "register_operand" "v")] 162))] | |
15350 | "TARGET_ALTIVEC" | |
15351 | "vsel %0,%1,%2,%3" | |
15352 | [(set_attr "type" "vecperm")]) | |
15353 | ||
24408032 AH |
15354 | (define_insn "altivec_vsldoi_4si" |
15355 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15356 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15357 | (match_operand:V4SI 2 "register_operand" "v") | |
15358 | (match_operand:QI 3 "immediate_operand" "i")] 163))] | |
15359 | "TARGET_ALTIVEC" | |
15360 | "vsldoi %0, %1, %2, %3" | |
15361 | [(set_attr "type" "vecperm")]) | |
15362 | ||
15363 | (define_insn "altivec_vsldoi_4sf" | |
15364 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15365 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") | |
15366 | (match_operand:V4SF 2 "register_operand" "v") | |
15367 | (match_operand:QI 3 "immediate_operand" "i")] 164))] | |
15368 | "TARGET_ALTIVEC" | |
15369 | "vsldoi %0, %1, %2, %3" | |
15370 | [(set_attr "type" "vecperm")]) | |
617e0e1d | 15371 | |
24408032 AH |
15372 | (define_insn "altivec_vsldoi_8hi" |
15373 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15374 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
15375 | (match_operand:V8HI 2 "register_operand" "v") | |
15376 | (match_operand:QI 3 "immediate_operand" "i")] 165))] | |
15377 | "TARGET_ALTIVEC" | |
15378 | "vsldoi %0, %1, %2, %3" | |
15379 | [(set_attr "type" "vecperm")]) | |
15380 | ||
15381 | (define_insn "altivec_vsldoi_16qi" | |
15382 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15383 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
15384 | (match_operand:V16QI 2 "register_operand" "v") | |
15385 | (match_operand:QI 3 "immediate_operand" "i")] 166))] | |
15386 | "TARGET_ALTIVEC" | |
15387 | "vsldoi %0, %1, %2, %3" | |
15388 | [(set_attr "type" "vecperm")]) | |
20e26713 AH |
15389 | |
15390 | (define_insn "altivec_vupkhsb" | |
15391 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15392 | (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))] | |
15393 | "TARGET_ALTIVEC" | |
15394 | "vupkhsb %0, %1" | |
15395 | [(set_attr "type" "vecperm")]) | |
15396 | ||
15397 | (define_insn "altivec_vupkhpx" | |
15398 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15399 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))] | |
15400 | "TARGET_ALTIVEC" | |
15401 | "vupkhpx %0, %1" | |
15402 | [(set_attr "type" "vecperm")]) | |
15403 | ||
15404 | (define_insn "altivec_vupkhsh" | |
15405 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15406 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))] | |
15407 | "TARGET_ALTIVEC" | |
15408 | "vupkhsh %0, %1" | |
15409 | [(set_attr "type" "vecperm")]) | |
15410 | ||
15411 | (define_insn "altivec_vupklsb" | |
15412 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15413 | (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))] | |
15414 | "TARGET_ALTIVEC" | |
15415 | "vupklsb %0, %1" | |
15416 | [(set_attr "type" "vecperm")]) | |
15417 | ||
15418 | (define_insn "altivec_vupklpx" | |
15419 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15420 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))] | |
15421 | "TARGET_ALTIVEC" | |
15422 | "vupklpx %0, %1" | |
15423 | [(set_attr "type" "vecperm")]) | |
15424 | ||
15425 | (define_insn "altivec_vupklsh" | |
15426 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15427 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))] | |
15428 | "TARGET_ALTIVEC" | |
15429 | "vupklsh %0, %1" | |
15430 | [(set_attr "type" "vecperm")]) | |
fa066a23 AH |
15431 | |
15432 | ;; AltiVec predicates. | |
15433 | ||
ae4b4a02 AH |
15434 | (define_expand "cr6_test_for_zero" |
15435 | [(set (match_operand:SI 0 "register_operand" "=r") | |
15436 | (eq:SI (reg:CC 74) | |
15437 | (const_int 0)))] | |
fa066a23 | 15438 | "TARGET_ALTIVEC" |
768070a0 | 15439 | "") |
fa066a23 | 15440 | |
ae4b4a02 AH |
15441 | (define_expand "cr6_test_for_zero_reverse" |
15442 | [(set (match_operand:SI 0 "register_operand" "=r") | |
15443 | (eq:SI (reg:CC 74) | |
15444 | (const_int 0))) | |
15445 | (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))] | |
fa066a23 | 15446 | "TARGET_ALTIVEC" |
ae4b4a02 | 15447 | "") |
fa066a23 | 15448 | |
ae4b4a02 AH |
15449 | (define_expand "cr6_test_for_lt" |
15450 | [(set (match_operand:SI 0 "register_operand" "=r") | |
15451 | (lt:SI (reg:CC 74) | |
15452 | (const_int 0)))] | |
fa066a23 | 15453 | "TARGET_ALTIVEC" |
ae4b4a02 | 15454 | "") |
fa066a23 | 15455 | |
ae4b4a02 AH |
15456 | (define_expand "cr6_test_for_lt_reverse" |
15457 | [(set (match_operand:SI 0 "register_operand" "=r") | |
15458 | (lt:SI (reg:CC 74) | |
15459 | (const_int 0))) | |
15460 | (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))] | |
fa066a23 | 15461 | "TARGET_ALTIVEC" |
ae4b4a02 | 15462 | "") |
fa066a23 | 15463 | |
ae4b4a02 AH |
15464 | ;; We can get away with generating the opcode on the fly (%3 below) |
15465 | ;; because all the predicates have the same scheduling parameters. | |
fa066a23 | 15466 | |
ae4b4a02 AH |
15467 | (define_insn "altivec_predicate_v4si" |
15468 | [(set (reg:CC 74) | |
15469 | (unspec:CC [(match_operand:V4SI 1 "register_operand" "v") | |
15470 | (match_operand:V4SI 2 "register_operand" "v") | |
15471 | (match_operand 3 "any_operand" "")] 173)) | |
15472 | (clobber (match_scratch:V4SI 0 "=v"))] | |
fa066a23 | 15473 | "TARGET_ALTIVEC" |
ae4b4a02 | 15474 | "%3 %0,%1,%2" |
fa066a23 AH |
15475 | [(set_attr "type" "veccmp")]) |
15476 | ||
ae4b4a02 AH |
15477 | (define_insn "altivec_predicate_v4sf" |
15478 | [(set (reg:CC 74) | |
15479 | (unspec:CC [(match_operand:V4SF 1 "register_operand" "v") | |
15480 | (match_operand:V4SF 2 "register_operand" "v") | |
15481 | (match_operand 3 "any_operand" "")] 174)) | |
15482 | (clobber (match_scratch:V4SF 0 "=v"))] | |
fa066a23 | 15483 | "TARGET_ALTIVEC" |
ae4b4a02 | 15484 | "%3 %0,%1,%2" |
fa066a23 AH |
15485 | [(set_attr "type" "veccmp")]) |
15486 | ||
ae4b4a02 AH |
15487 | (define_insn "altivec_predicate_v8hi" |
15488 | [(set (reg:CC 74) | |
15489 | (unspec:CC [(match_operand:V8HI 1 "register_operand" "v") | |
15490 | (match_operand:V8HI 2 "register_operand" "v") | |
15491 | (match_operand 3 "any_operand" "")] 175)) | |
15492 | (clobber (match_scratch:V8HI 0 "=v"))] | |
fa066a23 | 15493 | "TARGET_ALTIVEC" |
ae4b4a02 | 15494 | "%3 %0,%1,%2" |
fa066a23 AH |
15495 | [(set_attr "type" "veccmp")]) |
15496 | ||
ae4b4a02 AH |
15497 | (define_insn "altivec_predicate_v16qi" |
15498 | [(set (reg:CC 74) | |
15499 | (unspec:CC [(match_operand:V16QI 1 "register_operand" "v") | |
15500 | (match_operand:V16QI 2 "register_operand" "v") | |
15501 | (match_operand 3 "any_operand" "")] 175)) | |
15502 | (clobber (match_scratch:V16QI 0 "=v"))] | |
fa066a23 | 15503 | "TARGET_ALTIVEC" |
ae4b4a02 | 15504 | "%3 %0,%1,%2" |
fa066a23 AH |
15505 | [(set_attr "type" "veccmp")]) |
15506 | ||
95385cbb AH |
15507 | (define_insn "altivec_mtvscr" |
15508 | [(unspec [(match_operand:V4SI 0 "register_operand" "v")] 186)] | |
15509 | "TARGET_ALTIVEC" | |
15510 | "mtvscr %0" | |
15511 | [(set_attr "type" "vecsimple")]) | |
15512 | ||
15513 | (define_insn "altivec_mfvscr" | |
15514 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15515 | (unspec:V8HI [(const_int 0)] 187))] | |
15516 | "TARGET_ALTIVEC" | |
15517 | "mfvscr %0" | |
15518 | [(set_attr "type" "vecsimple")]) | |
15519 | ||
15520 | (define_insn "altivec_dssall" | |
15521 | [(unspec [(const_int 0)] 188)] | |
15522 | "TARGET_ALTIVEC" | |
15523 | "dssall" | |
15524 | [(set_attr "type" "vecsimple")]) | |
15525 | ||
15526 | (define_insn "altivec_dss" | |
15527 | [(unspec [(match_operand:QI 0 "immediate_operand" "i")] 189)] | |
15528 | "TARGET_ALTIVEC" | |
15529 | "dss %0" | |
15530 | [(set_attr "type" "vecsimple")]) | |
15531 | ||
15532 | (define_insn "altivec_dst" | |
15533 | [(unspec [(match_operand:SI 0 "register_operand" "b") | |
15534 | (match_operand:SI 1 "register_operand" "r") | |
15535 | (match_operand:QI 2 "immediate_operand" "i")] 190)] | |
15536 | "TARGET_ALTIVEC" | |
15537 | "dst %0,%1,%2" | |
15538 | [(set_attr "type" "vecsimple")]) | |
15539 | ||
15540 | (define_insn "altivec_dstt" | |
15541 | [(unspec [(match_operand:SI 0 "register_operand" "b") | |
15542 | (match_operand:SI 1 "register_operand" "r") | |
15543 | (match_operand:QI 2 "immediate_operand" "i")] 191)] | |
15544 | "TARGET_ALTIVEC" | |
15545 | "dstt %0,%1,%2" | |
15546 | [(set_attr "type" "vecsimple")]) | |
15547 | ||
15548 | (define_insn "altivec_dstst" | |
15549 | [(unspec [(match_operand:SI 0 "register_operand" "b") | |
15550 | (match_operand:SI 1 "register_operand" "r") | |
15551 | (match_operand:QI 2 "immediate_operand" "i")] 192)] | |
15552 | "TARGET_ALTIVEC" | |
15553 | "dstst %0,%1,%2" | |
15554 | [(set_attr "type" "vecsimple")]) | |
15555 | ||
15556 | (define_insn "altivec_dststt" | |
15557 | [(unspec [(match_operand:SI 0 "register_operand" "b") | |
15558 | (match_operand:SI 1 "register_operand" "r") | |
15559 | (match_operand:QI 2 "immediate_operand" "i")] 193)] | |
15560 | "TARGET_ALTIVEC" | |
15561 | "dststt %0,%1,%2" | |
15562 | [(set_attr "type" "vecsimple")]) | |
15563 | ||
15564 | (define_insn "altivec_lvsl" | |
15565 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
acfab996 | 15566 | (unspec:V16QI [(match_operand:SI 1 "register_operand" "b") |
95385cbb AH |
15567 | (match_operand:SI 2 "register_operand" "r")] 194))] |
15568 | "TARGET_ALTIVEC" | |
15569 | "lvsl %0,%1,%2" | |
15570 | [(set_attr "type" "vecload")]) | |
15571 | ||
15572 | (define_insn "altivec_lvsr" | |
15573 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
acfab996 | 15574 | (unspec:V16QI [(match_operand:SI 1 "register_operand" "b") |
95385cbb AH |
15575 | (match_operand:SI 2 "register_operand" "r")] 195))] |
15576 | "TARGET_ALTIVEC" | |
15577 | "lvsr %0,%1,%2" | |
15578 | [(set_attr "type" "vecload")]) | |
6525c0e7 | 15579 | |
69ef87e2 AH |
15580 | ;; Parallel some of the LVE* and STV*'s with unspecs because some have |
15581 | ;; identical rtl but different instructions-- and gcc gets confused. | |
15582 | ||
6525c0e7 | 15583 | (define_insn "altivec_lvebx" |
69ef87e2 AH |
15584 | [(parallel |
15585 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15586 | (mem:V16QI (plus:SI (match_operand:SI 1 "register_operand" "b") | |
15587 | (match_operand:SI 2 "register_operand" "r")))) | |
15588 | (unspec [(const_int 0)] 196)])] | |
6525c0e7 AH |
15589 | "TARGET_ALTIVEC" |
15590 | "lvebx %0,%1,%2" | |
15591 | [(set_attr "type" "vecload")]) | |
15592 | ||
15593 | (define_insn "altivec_lvehx" | |
69ef87e2 AH |
15594 | [(parallel |
15595 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15596 | (mem:V8HI | |
15597 | (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b") | |
15598 | (match_operand:SI 2 "register_operand" "r")) | |
15599 | (const_int -2)))) | |
15600 | (unspec [(const_int 0)] 197)])] | |
6525c0e7 AH |
15601 | "TARGET_ALTIVEC" |
15602 | "lvehx %0,%1,%2" | |
15603 | [(set_attr "type" "vecload")]) | |
15604 | ||
15605 | (define_insn "altivec_lvewx" | |
69ef87e2 AH |
15606 | [(parallel |
15607 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15608 | (mem:V4SI | |
15609 | (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b") | |
15610 | (match_operand:SI 2 "register_operand" "r")) | |
15611 | (const_int -4)))) | |
15612 | (unspec [(const_int 0)] 198)])] | |
6525c0e7 AH |
15613 | "TARGET_ALTIVEC" |
15614 | "lvewx %0,%1,%2" | |
15615 | [(set_attr "type" "vecload")]) | |
15616 | ||
15617 | (define_insn "altivec_lvxl" | |
69ef87e2 AH |
15618 | [(parallel |
15619 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15620 | (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b") | |
15621 | (match_operand:SI 2 "register_operand" "r")))) | |
15622 | (unspec [(const_int 0)] 213)])] | |
6525c0e7 AH |
15623 | "TARGET_ALTIVEC" |
15624 | "lvxl %0,%1,%2" | |
15625 | [(set_attr "type" "vecload")]) | |
15626 | ||
15627 | (define_insn "altivec_lvx" | |
15628 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
69ef87e2 AH |
15629 | (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b") |
15630 | (match_operand:SI 2 "register_operand" "r"))))] | |
6525c0e7 AH |
15631 | "TARGET_ALTIVEC" |
15632 | "lvx %0,%1,%2" | |
15633 | [(set_attr "type" "vecload")]) | |
15634 | ||
15635 | (define_insn "altivec_stvx" | |
acfab996 AH |
15636 | [(parallel |
15637 | [(set (mem:V4SI | |
15638 | (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") | |
15639 | (match_operand:SI 1 "register_operand" "r")) | |
15640 | (const_int -16))) | |
15641 | (match_operand:V4SI 2 "register_operand" "v")) | |
15642 | (unspec [(const_int 0)] 201)])] | |
6525c0e7 AH |
15643 | "TARGET_ALTIVEC" |
15644 | "stvx %2,%0,%1" | |
15645 | [(set_attr "type" "vecstore")]) | |
15646 | ||
15647 | (define_insn "altivec_stvxl" | |
15648 | [(parallel | |
15649 | [(set (mem:V4SI | |
acfab996 | 15650 | (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") |
6525c0e7 AH |
15651 | (match_operand:SI 1 "register_operand" "r")) |
15652 | (const_int -16))) | |
15653 | (match_operand:V4SI 2 "register_operand" "v")) | |
acfab996 | 15654 | (unspec [(const_int 0)] 202)])] |
6525c0e7 AH |
15655 | "TARGET_ALTIVEC" |
15656 | "stvxl %2,%0,%1" | |
15657 | [(set_attr "type" "vecstore")]) | |
15658 | ||
15659 | (define_insn "altivec_stvebx" | |
15660 | [(parallel | |
15661 | [(set (mem:V16QI | |
acfab996 | 15662 | (plus:SI (match_operand:SI 0 "register_operand" "b") |
6525c0e7 AH |
15663 | (match_operand:SI 1 "register_operand" "r"))) |
15664 | (match_operand:V16QI 2 "register_operand" "v")) | |
acfab996 | 15665 | (unspec [(const_int 0)] 203)])] |
6525c0e7 AH |
15666 | "TARGET_ALTIVEC" |
15667 | "stvebx %2,%0,%1" | |
15668 | [(set_attr "type" "vecstore")]) | |
15669 | ||
15670 | (define_insn "altivec_stvehx" | |
acfab996 AH |
15671 | [(parallel |
15672 | [(set (mem:V8HI | |
15673 | (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") | |
15674 | (match_operand:SI 1 "register_operand" "r")) | |
15675 | (const_int -2))) | |
15676 | (match_operand:V8HI 2 "register_operand" "v")) | |
15677 | (unspec [(const_int 0)] 204)])] | |
6525c0e7 AH |
15678 | "TARGET_ALTIVEC" |
15679 | "stvehx %2,%0,%1" | |
15680 | [(set_attr "type" "vecstore")]) | |
15681 | ||
15682 | (define_insn "altivec_stvewx" | |
acfab996 AH |
15683 | [(parallel |
15684 | [(set (mem:V4SI | |
15685 | (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") | |
15686 | (match_operand:SI 1 "register_operand" "r")) | |
15687 | (const_int -4))) | |
15688 | (match_operand:V4SI 2 "register_operand" "v")) | |
15689 | (unspec [(const_int 0)] 205)])] | |
6525c0e7 AH |
15690 | "TARGET_ALTIVEC" |
15691 | "stvewx %2,%0,%1" | |
15692 | [(set_attr "type" "vecstore")]) | |
100c4561 AH |
15693 | |
15694 | (define_insn "absv16qi2" | |
15695 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15696 | (abs:V16QI (match_operand:V16QI 1 "register_operand" "v"))) | |
15697 | (clobber (match_scratch:V16QI 2 "=v")) | |
15698 | (clobber (match_scratch:V16QI 3 "=v"))] | |
15699 | "TARGET_ALTIVEC" | |
15700 | "vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3" | |
15701 | [(set_attr "type" "altivec") | |
15702 | (set_attr "length" "12")]) | |
15703 | ||
15704 | (define_insn "absv8hi2" | |
15705 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15706 | (abs:V8HI (match_operand:V8HI 1 "register_operand" "v"))) | |
15707 | (clobber (match_scratch:V8HI 2 "=v")) | |
15708 | (clobber (match_scratch:V8HI 3 "=v"))] | |
15709 | "TARGET_ALTIVEC" | |
15710 | "vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3" | |
15711 | [(set_attr "type" "altivec") | |
15712 | (set_attr "length" "12")]) | |
15713 | ||
15714 | (define_insn "absv4si2" | |
15715 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15716 | (abs:V4SI (match_operand:V4SI 1 "register_operand" "v"))) | |
15717 | (clobber (match_scratch:V4SI 2 "=v")) | |
15718 | (clobber (match_scratch:V4SI 3 "=v"))] | |
15719 | "TARGET_ALTIVEC" | |
15720 | "vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3" | |
15721 | [(set_attr "type" "altivec") | |
15722 | (set_attr "length" "12")]) | |
15723 | ||
15724 | (define_insn "absv4sf2" | |
15725 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15726 | (abs:V4SF (match_operand:V4SF 1 "register_operand" "v"))) | |
15727 | (clobber (match_scratch:V4SF 2 "=v")) | |
15728 | (clobber (match_scratch:V4SF 3 "=v"))] | |
15729 | "TARGET_ALTIVEC" | |
15730 | "vspltisw %2, -1\;vslw %3,%2,%2\;vandc %0,%1,%3" | |
15731 | [(set_attr "type" "altivec") | |
15732 | (set_attr "length" "12")]) | |
15733 | ||
15734 | (define_insn "altivec_abss_v16qi" | |
15735 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15736 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210)) | |
15737 | (clobber (match_scratch:V16QI 2 "=v")) | |
15738 | (clobber (match_scratch:V16QI 3 "=v"))] | |
15739 | "TARGET_ALTIVEC" | |
15740 | "vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3" | |
15741 | [(set_attr "type" "altivec") | |
15742 | (set_attr "length" "12")]) | |
15743 | ||
15744 | (define_insn "altivec_abss_v8hi" | |
15745 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15746 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211)) | |
15747 | (clobber (match_scratch:V8HI 2 "=v")) | |
15748 | (clobber (match_scratch:V8HI 3 "=v"))] | |
15749 | "TARGET_ALTIVEC" | |
15750 | "vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3" | |
15751 | [(set_attr "type" "altivec") | |
15752 | (set_attr "length" "12")]) | |
15753 | ||
15754 | (define_insn "altivec_abss_v4si" | |
15755 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15756 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212)) | |
15757 | (clobber (match_scratch:V4SI 2 "=v")) | |
15758 | (clobber (match_scratch:V4SI 3 "=v"))] | |
15759 | "TARGET_ALTIVEC" | |
15760 | "vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3" | |
15761 | [(set_attr "type" "altivec") | |
15762 | (set_attr "length" "12")]) |