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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
d24652ee GK |
2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | ;; 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. | |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 RK |
5 | |
6 | ;; This file is part of GNU CC. | |
7 | ||
8 | ;; GNU CC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 2, or (at your option) | |
11 | ;; any later version. | |
12 | ||
13 | ;; GNU CC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GNU CC; see the file COPYING. If not, write to | |
3f63df56 RK |
20 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | ;; Boston, MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d GK |
24 | |
25 | ;; `unspec' values used in rs6000.md: | |
26 | ;; Number Use | |
27 | ;; 0 frsp for POWER machines | |
28 | ;; 0/v blockage | |
29 | ;; 5 used to tie the stack contents and the stack pointer | |
30 | ;; 6 address of a word pointing to the TOC | |
31 | ;; 7 address of the TOC (more-or-less) | |
32 | ;; 8 movsi_got | |
33 | ;; 9/v eh_reg_restore | |
34 | ;; 10 fctiwz | |
f51eee6a GK |
35 | ;; 15 load_macho_picbase |
36 | ;; 16 macho_correct_pic | |
9ebbca7d GK |
37 | ;; 19 movesi_from_cr |
38 | ;; 20 movesi_to_cr | |
1fd4e8c1 RK |
39 | \f |
40 | ;; Define an insn type attribute. This is used in function unit delay | |
41 | ;; computations. | |
310b9b1d | 42 | (define_attr "type" "integer,load,store,fpload,fpstore,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat" |
1fd4e8c1 RK |
43 | (const_string "integer")) |
44 | ||
b19003d8 | 45 | ;; Length (in bytes). |
6cbadf36 GK |
46 | ; '(pc)' in the following doesn't include the instruction itself; it is |
47 | ; calculated as if the instruction had zero size. | |
b19003d8 RK |
48 | (define_attr "length" "" |
49 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 50 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 51 | (const_int -32768)) |
6cbadf36 GK |
52 | (lt (minus (match_dup 0) (pc)) |
53 | (const_int 32764))) | |
39a10a29 GK |
54 | (const_int 4) |
55 | (const_int 8)) | |
b19003d8 RK |
56 | (const_int 4))) |
57 | ||
cfb557c4 RK |
58 | ;; Processor type -- this attribute must exactly match the processor_type |
59 | ;; enumeration in rs6000.h. | |
60 | ||
9a5cd606 | 61 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4" |
cfb557c4 RK |
62 | (const (symbol_ref "rs6000_cpu_attr"))) |
63 | ||
64 | ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY | |
65 | ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) | |
66 | ||
b7ff3d82 | 67 | ; Load/Store Unit -- pure PowerPC only |
51b8fc2c | 68 | ; (POWER and 601 use Integer Unit) |
cfb557c4 RK |
69 | (define_function_unit "lsu" 1 0 |
70 | (and (eq_attr "type" "load") | |
ed947a96 | 71 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400")) |
b6c9286a | 72 | 2 1) |
cfb557c4 | 73 | |
ed947a96 | 74 | (define_function_unit "lsu" 1 0 |
f18c054f | 75 | (and (eq_attr "type" "load,vecload") |
ed947a96 DJ |
76 | (eq_attr "cpu" "ppc7450")) |
77 | 3 1) | |
78 | ||
cfb557c4 | 79 | (define_function_unit "lsu" 1 0 |
b7ff3d82 | 80 | (and (eq_attr "type" "store,fpstore") |
ed947a96 | 81 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 82 | 1 1) |
b6c9286a | 83 | |
ed947a96 DJ |
84 | (define_function_unit "lsu" 1 0 |
85 | (and (eq_attr "type" "store,fpstore") | |
86 | (eq_attr "cpu" "ppc750,ppc7400")) | |
87 | 2 1) | |
88 | ||
89 | (define_function_unit "lsu" 1 0 | |
f18c054f | 90 | (and (eq_attr "type" "store,vecstore") |
ed947a96 DJ |
91 | (eq_attr "cpu" "ppc7450")) |
92 | 3 1) | |
93 | ||
94 | (define_function_unit "lsu" 1 0 | |
95 | (and (eq_attr "type" "fpstore") | |
96 | (eq_attr "cpu" "ppc7450")) | |
97 | 3 3) | |
98 | ||
b6c9286a MM |
99 | (define_function_unit "lsu" 1 0 |
100 | (and (eq_attr "type" "fpload") | |
ed947a96 | 101 | (eq_attr "cpu" "mpccore,ppc603,ppc750,ppc7400")) |
b6c9286a | 102 | 2 1) |
cfb557c4 | 103 | |
ed947a96 DJ |
104 | (define_function_unit "lsu" 1 0 |
105 | (and (eq_attr "type" "fpload") | |
106 | (eq_attr "cpu" "ppc7450")) | |
107 | 4 1) | |
108 | ||
b7ff3d82 DE |
109 | (define_function_unit "lsu" 1 0 |
110 | (and (eq_attr "type" "fpload") | |
3cb999d8 | 111 | (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 DE |
112 | 3 1) |
113 | ||
cfb557c4 RK |
114 | (define_function_unit "iu" 1 0 |
115 | (and (eq_attr "type" "load") | |
fe7f5677 | 116 | (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601")) |
b6c9286a | 117 | 2 1) |
cfb557c4 RK |
118 | |
119 | (define_function_unit "iu" 1 0 | |
b7ff3d82 | 120 | (and (eq_attr "type" "store,fpstore") |
fe7f5677 | 121 | (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601")) |
b7ff3d82 DE |
122 | 1 1) |
123 | ||
124 | (define_function_unit "fpu" 1 0 | |
125 | (and (eq_attr "type" "fpstore") | |
3624a679 | 126 | (eq_attr "cpu" "rios1,ppc601")) |
b7ff3d82 | 127 | 0 1) |
cfb557c4 | 128 | |
49a0b204 | 129 | (define_function_unit "iu" 1 0 |
b7ff3d82 | 130 | (and (eq_attr "type" "fpload") |
b6c9286a | 131 | (eq_attr "cpu" "rios1")) |
b7ff3d82 DE |
132 | 2 1) |
133 | ||
134 | (define_function_unit "iu" 1 0 | |
135 | (and (eq_attr "type" "fpload") | |
136 | (eq_attr "cpu" "ppc601")) | |
137 | 3 1) | |
138 | ||
139 | (define_function_unit "iu2" 2 0 | |
140 | (and (eq_attr "type" "load,fpload") | |
141 | (eq_attr "cpu" "rios2")) | |
142 | 2 1) | |
143 | ||
144 | (define_function_unit "iu2" 2 0 | |
145 | (and (eq_attr "type" "store,fpstore") | |
146 | (eq_attr "cpu" "rios2")) | |
147 | 1 1) | |
148 | ||
3cb999d8 | 149 | ; Integer Unit (RIOS1, PPC601, PPC603, RS64a) |
b7ff3d82 DE |
150 | (define_function_unit "iu" 1 0 |
151 | (and (eq_attr "type" "integer") | |
fe7f5677 | 152 | (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603")) |
b7ff3d82 | 153 | 1 1) |
49a0b204 | 154 | |
39a10a29 GK |
155 | (define_function_unit "iu" 1 0 |
156 | (and (eq_attr "type" "cr_logical") | |
fe7f5677 | 157 | (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601")) |
39a10a29 GK |
158 | 1 1) |
159 | ||
da0ae67f | 160 | (define_function_unit "iu" 1 0 |
c859cda6 | 161 | (and (eq_attr "type" "imul,imul2,imul3") |
da0ae67f MM |
162 | (eq_attr "cpu" "ppc403")) |
163 | 4 4) | |
164 | ||
cfb557c4 | 165 | (define_function_unit "iu" 1 0 |
fe7f5677 DE |
166 | (and (eq_attr "type" "imul") |
167 | (eq_attr "cpu" "ppc405")) | |
168 | 4 3) | |
169 | ||
170 | (define_function_unit "iu" 1 0 | |
171 | (and (eq_attr "type" "imul2,imul3") | |
172 | (eq_attr "cpu" "ppc405")) | |
173 | 3 2) | |
174 | ||
175 | (define_function_unit "iu" 1 0 | |
176 | (and (eq_attr "type" "imul") | |
177 | (eq_attr "cpu" "rios1")) | |
51b8fc2c | 178 | 5 5) |
cfb557c4 | 179 | |
fe7f5677 DE |
180 | (define_function_unit "iu" 1 0 |
181 | (and (eq_attr "type" "imul2") | |
182 | (eq_attr "cpu" "rios1")) | |
183 | 4 4) | |
184 | ||
185 | (define_function_unit "iu" 1 0 | |
186 | (and (eq_attr "type" "imul3") | |
187 | (eq_attr "cpu" "rios1")) | |
188 | 3 3) | |
189 | ||
3cb999d8 | 190 | (define_function_unit "iu" 1 0 |
c859cda6 | 191 | (and (eq_attr "type" "imul,imul2,imul3") |
fe7f5677 DE |
192 | (eq_attr "cpu" "ppc601,ppc603")) |
193 | 5 5) | |
194 | ||
195 | (define_function_unit "iu" 1 0 | |
196 | (and (eq_attr "type" "imul") | |
197 | (eq_attr "cpu" "rs64a")) | |
198 | 20 20) | |
199 | ||
200 | (define_function_unit "iu" 1 0 | |
201 | (and (eq_attr "type" "imul2") | |
3cb999d8 | 202 | (eq_attr "cpu" "rs64a")) |
fe7f5677 DE |
203 | 12 12) |
204 | ||
205 | (define_function_unit "iu" 1 0 | |
206 | (and (eq_attr "type" "imul3") | |
207 | (eq_attr "cpu" "rs64a")) | |
208 | 8 8) | |
3cb999d8 DE |
209 | |
210 | (define_function_unit "iu" 1 0 | |
211 | (and (eq_attr "type" "lmul") | |
212 | (eq_attr "cpu" "rs64a")) | |
213 | 34 34) | |
214 | ||
cfb557c4 RK |
215 | (define_function_unit "iu" 1 0 |
216 | (and (eq_attr "type" "idiv") | |
ca7f5001 | 217 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 218 | 19 19) |
cfb557c4 | 219 | |
3cb999d8 DE |
220 | (define_function_unit "iu" 1 0 |
221 | (and (eq_attr "type" "idiv") | |
222 | (eq_attr "cpu" "rs64a")) | |
223 | 66 66) | |
224 | ||
225 | (define_function_unit "iu" 1 0 | |
226 | (and (eq_attr "type" "ldiv") | |
227 | (eq_attr "cpu" "rs64a")) | |
228 | 66 66) | |
229 | ||
cfb557c4 RK |
230 | (define_function_unit "iu" 1 0 |
231 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
232 | (eq_attr "cpu" "ppc403")) |
233 | 33 33) | |
51b8fc2c | 234 | |
fe7f5677 DE |
235 | (define_function_unit "iu" 1 0 |
236 | (and (eq_attr "type" "idiv") | |
237 | (eq_attr "cpu" "ppc405")) | |
238 | 35 35) | |
239 | ||
da0ae67f MM |
240 | (define_function_unit "iu" 1 0 |
241 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
242 | (eq_attr "cpu" "ppc601")) |
243 | 36 36) | |
da0ae67f | 244 | |
51b8fc2c RK |
245 | (define_function_unit "iu" 1 0 |
246 | (and (eq_attr "type" "idiv") | |
b7ff3d82 | 247 | (eq_attr "cpu" "ppc603")) |
51b8fc2c RK |
248 | 37 36) |
249 | ||
250 | ; RIOS2 has two integer units: a primary one which can perform all | |
251 | ; operations and a secondary one which is fed in lock step with the first | |
b6c9286a MM |
252 | ; and can perform "simple" integer operations. |
253 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
254 | ; for the complex insns. | |
51b8fc2c RK |
255 | (define_function_unit "iu2" 2 0 |
256 | (and (eq_attr "type" "integer") | |
257 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 258 | 1 1) |
b6c9286a MM |
259 | |
260 | (define_function_unit "iu2" 2 0 | |
c859cda6 | 261 | (and (eq_attr "type" "imul,imul2,imul3") |
b6c9286a MM |
262 | (eq_attr "cpu" "rios2")) |
263 | 2 2) | |
264 | ||
265 | (define_function_unit "iu2" 2 0 | |
266 | (and (eq_attr "type" "idiv") | |
267 | (eq_attr "cpu" "rios2")) | |
268 | 13 13) | |
51b8fc2c RK |
269 | |
270 | (define_function_unit "imuldiv" 1 0 | |
c859cda6 | 271 | (and (eq_attr "type" "imul,imul2,imul3") |
51b8fc2c | 272 | (eq_attr "cpu" "rios2")) |
b6c9286a MM |
273 | 2 2) |
274 | ||
51b8fc2c RK |
275 | (define_function_unit "imuldiv" 1 0 |
276 | (and (eq_attr "type" "idiv") | |
277 | (eq_attr "cpu" "rios2")) | |
b6c9286a | 278 | 13 13) |
51b8fc2c | 279 | |
cf27b467 MM |
280 | ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions |
281 | ; Divide latency varies greatly from 2-11, use 6 as average | |
282 | (define_function_unit "imuldiv" 1 0 | |
c859cda6 | 283 | (and (eq_attr "type" "imul,imul2,imul3") |
cf27b467 MM |
284 | (eq_attr "cpu" "mpccore")) |
285 | 2 1) | |
286 | ||
287 | (define_function_unit "imuldiv" 1 0 | |
288 | (and (eq_attr "type" "idiv") | |
289 | (eq_attr "cpu" "mpccore")) | |
290 | 6 6) | |
291 | ||
cac8ce95 | 292 | ; PPC604{,e} has two units that perform integer operations |
b6c9286a MM |
293 | ; and one unit for divide/multiply operations (and move |
294 | ; from/to spr). | |
295 | (define_function_unit "iu2" 2 0 | |
51b8fc2c | 296 | (and (eq_attr "type" "integer") |
3cb999d8 | 297 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 298 | 1 1) |
51b8fc2c RK |
299 | |
300 | (define_function_unit "imuldiv" 1 0 | |
c859cda6 | 301 | (and (eq_attr "type" "imul,imul2,imul3") |
3cb999d8 | 302 | (eq_attr "cpu" "ppc604")) |
b7ff3d82 | 303 | 4 2) |
51b8fc2c | 304 | |
3cb999d8 | 305 | (define_function_unit "imuldiv" 1 0 |
c859cda6 | 306 | (and (eq_attr "type" "imul,imul2,imul3") |
fe7f5677 DE |
307 | (eq_attr "cpu" "ppc604e")) |
308 | 2 1) | |
309 | ||
310 | (define_function_unit "imuldiv" 1 0 | |
311 | (and (eq_attr "type" "imul") | |
3cb999d8 DE |
312 | (eq_attr "cpu" "ppc620,ppc630")) |
313 | 5 3) | |
314 | ||
315 | (define_function_unit "imuldiv" 1 0 | |
fe7f5677 | 316 | (and (eq_attr "type" "imul2") |
3cb999d8 | 317 | (eq_attr "cpu" "ppc620,ppc630")) |
fe7f5677 | 318 | 4 3) |
3cb999d8 | 319 | |
cac8ce95 | 320 | (define_function_unit "imuldiv" 1 0 |
fe7f5677 DE |
321 | (and (eq_attr "type" "imul3") |
322 | (eq_attr "cpu" "ppc620,ppc630")) | |
323 | 3 3) | |
324 | ||
325 | (define_function_unit "imuldiv" 1 0 | |
326 | (and (eq_attr "type" "lmul") | |
327 | (eq_attr "cpu" "ppc620,ppc630")) | |
328 | 7 5) | |
cac8ce95 | 329 | |
51b8fc2c RK |
330 | (define_function_unit "imuldiv" 1 0 |
331 | (and (eq_attr "type" "idiv") | |
3cb999d8 | 332 | (eq_attr "cpu" "ppc604,ppc604e")) |
b7ff3d82 | 333 | 20 19) |
cfb557c4 | 334 | |
3cb999d8 DE |
335 | (define_function_unit "imuldiv" 1 0 |
336 | (and (eq_attr "type" "idiv") | |
337 | (eq_attr "cpu" "ppc620")) | |
338 | 37 36) | |
339 | ||
340 | (define_function_unit "imuldiv" 1 0 | |
341 | (and (eq_attr "type" "idiv") | |
342 | (eq_attr "cpu" "ppc630")) | |
343 | 21 20) | |
344 | ||
345 | (define_function_unit "imuldiv" 1 0 | |
346 | (and (eq_attr "type" "ldiv") | |
347 | (eq_attr "cpu" "ppc620,ppc630")) | |
348 | 37 36) | |
349 | ||
ed947a96 DJ |
350 | ; PPC7450 has 3 integer units (for most integer insns) and one mul/div |
351 | ; unit, which also does CR-logical insns and move to/from SPR. | |
2212663f DB |
352 | ; It also has 4 vector units, one for each type of vector instruction. |
353 | ; However, we can only dispatch 2 instructions per cycle. | |
354 | ; We model this as saying that dispatching two of the same type of instruction | |
355 | ; in a row incurs a single cycle delay. | |
ed947a96 DJ |
356 | (define_function_unit "iu3" 3 0 |
357 | (and (eq_attr "type" "integer") | |
358 | (eq_attr "cpu" "ppc7450")) | |
359 | 1 1) | |
360 | ||
361 | (define_function_unit "imuldiv" 1 0 | |
362 | (and (eq_attr "type" "imul") | |
363 | (eq_attr "cpu" "ppc7450")) | |
fd3b43f2 | 364 | 4 2) |
ed947a96 | 365 | |
c859cda6 DJ |
366 | (define_function_unit "imuldiv" 1 0 |
367 | (and (eq_attr "type" "imul2,imul3") | |
368 | (eq_attr "cpu" "ppc7450")) | |
369 | 3 1) | |
370 | ||
ed947a96 DJ |
371 | (define_function_unit "imuldiv" 1 0 |
372 | (and (eq_attr "type" "idiv") | |
373 | (eq_attr "cpu" "ppc7450")) | |
374 | 23 23) | |
375 | ||
376 | (define_function_unit "imuldiv" 1 0 | |
377 | (and (eq_attr "type" "cr_logical") | |
378 | (eq_attr "cpu" "ppc7450")) | |
379 | 1 1) | |
309323c2 | 380 | |
2212663f | 381 | (define_function_unit "vec_alu2" 2 0 |
f18c054f DB |
382 | (and (eq_attr "type" "vecsimple") |
383 | (eq_attr "cpu" "ppc7450")) | |
2212663f | 384 | 1 2 [(eq_attr "type" "vecsimple")]) |
309323c2 | 385 | |
2212663f DB |
386 | (define_function_unit "vec_alu2" 2 0 |
387 | (and (eq_attr "type" "vecsimple") | |
388 | (eq_attr "cpu" "ppc7450")) | |
389 | 1 1 [(eq_attr "type" "!vecsimple")]) | |
309323c2 | 390 | |
2212663f | 391 | (define_function_unit "vec_alu2" 2 0 |
f18c054f DB |
392 | (and (eq_attr "type" "veccomplex") |
393 | (eq_attr "cpu" "ppc7450")) | |
2212663f | 394 | 4 2 [(eq_attr "type" "veccomplex")]) |
309323c2 | 395 | |
2212663f DB |
396 | (define_function_unit "vec_alu2" 2 0 |
397 | (and (eq_attr "type" "veccomplex") | |
398 | (eq_attr "cpu" "ppc7450")) | |
399 | 4 1 [(eq_attr "type" "!veccomplex")]) | |
309323c2 | 400 | |
2212663f | 401 | (define_function_unit "vec_alu2" 2 0 |
f18c054f DB |
402 | (and (eq_attr "type" "veccmp") |
403 | (eq_attr "cpu" "ppc7450")) | |
2212663f | 404 | 2 2 [(eq_attr "type" "veccmp")]) |
309323c2 | 405 | |
2212663f DB |
406 | (define_function_unit "vec_alu2" 2 0 |
407 | (and (eq_attr "type" "veccmp") | |
408 | (eq_attr "cpu" "ppc7450")) | |
409 | 2 1 [(eq_attr "type" "!veccmp")]) | |
309323c2 | 410 | |
2212663f | 411 | (define_function_unit "vec_alu2" 2 0 |
f18c054f DB |
412 | (and (eq_attr "type" "vecfloat") |
413 | (eq_attr "cpu" "ppc7450")) | |
2212663f | 414 | 4 2 [(eq_attr "type" "vecfloat")]) |
309323c2 | 415 | |
2212663f DB |
416 | (define_function_unit "vec_alu2" 2 0 |
417 | (and (eq_attr "type" "vecfloat") | |
418 | (eq_attr "cpu" "ppc7450")) | |
419 | 4 1 [(eq_attr "type" "!vecfloat")]) | |
309323c2 | 420 | |
2212663f | 421 | (define_function_unit "vec_alu2" 2 0 |
f18c054f DB |
422 | (and (eq_attr "type" "vecperm") |
423 | (eq_attr "cpu" "ppc7450")) | |
2212663f | 424 | 2 2 [(eq_attr "type" "vecperm")]) |
309323c2 | 425 | |
2212663f DB |
426 | (define_function_unit "vec_alu2" 2 0 |
427 | (and (eq_attr "type" "vecperm") | |
428 | (eq_attr "cpu" "ppc7450")) | |
429 | 2 1 [(eq_attr "type" "!vecperm")]) | |
ed947a96 | 430 | |
bef84347 VM |
431 | ; PPC750 has two integer units: a primary one which can perform all |
432 | ; operations and a secondary one which is fed in lock step with the first | |
433 | ; and can perform "simple" integer operations. | |
434 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
435 | ; for the complex insns. | |
436 | (define_function_unit "iu2" 2 0 | |
437 | (and (eq_attr "type" "integer") | |
ed947a96 | 438 | (eq_attr "cpu" "ppc750,ppc7400")) |
bef84347 VM |
439 | 1 1) |
440 | ||
441 | (define_function_unit "iu2" 2 0 | |
442 | (and (eq_attr "type" "imul") | |
ed947a96 DJ |
443 | (eq_attr "cpu" "ppc750,ppc7400")) |
444 | 4 4) | |
445 | ||
c859cda6 DJ |
446 | (define_function_unit "iu2" 2 0 |
447 | (and (eq_attr "type" "imul2") | |
448 | (eq_attr "cpu" "ppc750,ppc7400")) | |
449 | 3 2) | |
450 | ||
451 | (define_function_unit "iu2" 2 0 | |
452 | (and (eq_attr "type" "imul3") | |
453 | (eq_attr "cpu" "ppc750,ppc7400")) | |
454 | 2 1) | |
455 | ||
ed947a96 DJ |
456 | (define_function_unit "iu2" 2 0 |
457 | (and (eq_attr "type" "idiv") | |
458 | (eq_attr "cpu" "ppc750,ppc7400")) | |
459 | 19 19) | |
bef84347 VM |
460 | |
461 | (define_function_unit "imuldiv" 1 0 | |
462 | (and (eq_attr "type" "imul") | |
ed947a96 DJ |
463 | (eq_attr "cpu" "ppc750,ppc7400")) |
464 | 4 4) | |
bef84347 | 465 | |
c859cda6 DJ |
466 | (define_function_unit "imuldiv" 1 0 |
467 | (and (eq_attr "type" "imul2") | |
468 | (eq_attr "cpu" "ppc750,ppc7400")) | |
469 | 3 2) | |
470 | ||
471 | (define_function_unit "imuldiv" 1 0 | |
472 | (and (eq_attr "type" "imul3") | |
473 | (eq_attr "cpu" "ppc750,ppc7400")) | |
474 | 2 1) | |
475 | ||
bef84347 VM |
476 | (define_function_unit "imuldiv" 1 0 |
477 | (and (eq_attr "type" "idiv") | |
ed947a96 | 478 | (eq_attr "cpu" "ppc750,ppc7400")) |
bef84347 VM |
479 | 19 19) |
480 | ||
39a10a29 GK |
481 | ; CR-logical operations are execute-serialized, that is they don't |
482 | ; start (and block the function unit) until all preceding operations | |
483 | ; have finished. They don't block dispatch of other insns, though. | |
484 | ; I've imitated this by giving them longer latency. | |
485 | (define_function_unit "sru" 1 0 | |
486 | (and (eq_attr "type" "cr_logical") | |
ed947a96 | 487 | (eq_attr "cpu" "ppc603,ppc750,ppc7400")) |
39a10a29 GK |
488 | 3 2) |
489 | ||
b6c9286a | 490 | ; compare is done on integer unit, but feeds insns which |
acc5239d | 491 | ; execute on the branch unit. |
b6c9286a MM |
492 | (define_function_unit "iu" 1 0 |
493 | (and (eq_attr "type" "compare") | |
b7ff3d82 DE |
494 | (eq_attr "cpu" "rios1")) |
495 | 4 1) | |
496 | ||
497 | (define_function_unit "iu" 1 0 | |
498 | (and (eq_attr "type" "delayed_compare") | |
499 | (eq_attr "cpu" "rios1")) | |
500 | 5 1) | |
501 | ||
502 | (define_function_unit "iu" 1 0 | |
503 | (and (eq_attr "type" "compare,delayed_compare") | |
309323c2 | 504 | (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc601,ppc603")) |
b7ff3d82 | 505 | 3 1) |
b6c9286a | 506 | |
ed947a96 DJ |
507 | ; some extra cycles added by TARGET_SCHED_ADJUST_COST between compare |
508 | ; and a following branch, to reduce mispredicts | |
ed947a96 DJ |
509 | (define_function_unit "iu3" 3 0 |
510 | (and (eq_attr "type" "compare,delayed_compare") | |
511 | (eq_attr "cpu" "ppc7450")) | |
512 | 1 1) | |
513 | ||
b6c9286a | 514 | (define_function_unit "iu2" 2 0 |
b7ff3d82 | 515 | (and (eq_attr "type" "compare,delayed_compare") |
b6c9286a | 516 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 517 | 3 1) |
b6c9286a | 518 | |
b6c9286a | 519 | (define_function_unit "iu2" 2 0 |
b7ff3d82 | 520 | (and (eq_attr "type" "compare,delayed_compare") |
ed947a96 | 521 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400")) |
b6c9286a | 522 | 1 1) |
cfb557c4 | 523 | |
b6c9286a MM |
524 | ; fp compare uses fp unit |
525 | (define_function_unit "fpu" 1 0 | |
cfb557c4 | 526 | (and (eq_attr "type" "fpcompare") |
b6c9286a | 527 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 528 | 9 1) |
cfb557c4 | 529 | |
b6c9286a MM |
530 | ; rios1 and rios2 have different fpcompare delays |
531 | (define_function_unit "fpu2" 2 0 | |
cfb557c4 | 532 | (and (eq_attr "type" "fpcompare") |
3cb999d8 | 533 | (eq_attr "cpu" "rios2,ppc630")) |
b6c9286a MM |
534 | 5 1) |
535 | ||
536 | ; on ppc601 and ppc603, fpcompare takes also 2 cycles from | |
537 | ; the integer unit | |
538 | ; here we do not define delays, just occupy the unit. The dependencies | |
b7ff3d82 | 539 | ; will be assigned by the fpcompare definition in the fpu. |
b6c9286a MM |
540 | (define_function_unit "iu" 1 0 |
541 | (and (eq_attr "type" "fpcompare") | |
b7ff3d82 | 542 | (eq_attr "cpu" "ppc601,ppc603")) |
b6c9286a MM |
543 | 0 2) |
544 | ||
545 | ; fp compare uses fp unit | |
546 | (define_function_unit "fpu" 1 0 | |
547 | (and (eq_attr "type" "fpcompare") | |
e3485bbc | 548 | (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620")) |
b6c9286a | 549 | 5 1) |
cfb557c4 | 550 | |
ed947a96 DJ |
551 | (define_function_unit "fpu" 1 0 |
552 | (and (eq_attr "type" "fpcompare") | |
553 | (eq_attr "cpu" "ppc750,ppc7400,ppc7450")) | |
554 | 3 1) | |
555 | ||
cf27b467 MM |
556 | (define_function_unit "fpu" 1 0 |
557 | (and (eq_attr "type" "fpcompare") | |
558 | (eq_attr "cpu" "mpccore")) | |
559 | 1 1) | |
560 | ||
cfb557c4 | 561 | (define_function_unit "bpu" 1 0 |
324e52cc | 562 | (and (eq_attr "type" "mtjmpr") |
3cb999d8 | 563 | (eq_attr "cpu" "rios1,rios2,rs64a")) |
b7ff3d82 | 564 | 5 1) |
cfb557c4 RK |
565 | |
566 | (define_function_unit "bpu" 1 0 | |
324e52cc | 567 | (and (eq_attr "type" "mtjmpr") |
fe7f5677 | 568 | (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 569 | 4 1) |
cfb557c4 | 570 | |
c859cda6 DJ |
571 | (define_function_unit "sru" 1 0 |
572 | (and (eq_attr "type" "mtjmpr") | |
573 | (eq_attr "cpu" "ppc750,ppc7400")) | |
574 | 2 2) | |
575 | ||
576 | (define_function_unit "imuldiv" 1 0 | |
577 | (and (eq_attr "type" "mtjmpr") | |
578 | (eq_attr "cpu" "ppc7450")) | |
579 | 2 2) | |
580 | ||
39a10a29 GK |
581 | (define_function_unit "bpu" 1 0 |
582 | (and (eq_attr "type" "cr_logical") | |
5638268e | 583 | (eq_attr "cpu" "rios1,rios2,ppc604")) |
39a10a29 GK |
584 | 4 1) |
585 | ||
586 | (define_function_unit "cru" 1 0 | |
587 | (and (eq_attr "type" "cr_logical") | |
5638268e DE |
588 | (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a")) |
589 | 1 1) | |
39a10a29 | 590 | |
b6c9286a MM |
591 | ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines. |
592 | (define_function_unit "bpu" 1 0 | |
593 | (eq_attr "type" "jmpreg") | |
b7ff3d82 | 594 | 1 1) |
b6c9286a MM |
595 | |
596 | (define_function_unit "bpu" 1 0 | |
597 | (eq_attr "type" "branch") | |
b7ff3d82 | 598 | 1 1) |
b6c9286a | 599 | |
cf27b467 | 600 | ; Floating Point Unit |
cfb557c4 | 601 | (define_function_unit "fpu" 1 0 |
51b8fc2c | 602 | (and (eq_attr "type" "fp,dmul") |
2661cdd9 | 603 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 604 | 2 1) |
cfb557c4 | 605 | |
cf27b467 MM |
606 | (define_function_unit "fpu" 1 0 |
607 | (and (eq_attr "type" "fp") | |
3cb999d8 DE |
608 | (eq_attr "cpu" "rs64a,mpccore")) |
609 | 4 2) | |
cf27b467 | 610 | |
cfb557c4 RK |
611 | (define_function_unit "fpu" 1 0 |
612 | (and (eq_attr "type" "fp") | |
51b8fc2c | 613 | (eq_attr "cpu" "ppc601")) |
b7ff3d82 | 614 | 4 1) |
cfb557c4 | 615 | |
51b8fc2c RK |
616 | (define_function_unit "fpu" 1 0 |
617 | (and (eq_attr "type" "fp") | |
ed947a96 | 618 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750,ppc7400")) |
b6c9286a | 619 | 3 1) |
51b8fc2c | 620 | |
ed947a96 DJ |
621 | (define_function_unit "fpu" 1 0 |
622 | (and (eq_attr "type" "fp,dmul") | |
623 | (eq_attr "cpu" "ppc7450")) | |
624 | 5 1) | |
625 | ||
3cb999d8 DE |
626 | (define_function_unit "fpu" 1 0 |
627 | (and (eq_attr "type" "dmul") | |
628 | (eq_attr "cpu" "rs64a")) | |
629 | 7 2) | |
630 | ||
cf27b467 MM |
631 | (define_function_unit "fpu" 1 0 |
632 | (and (eq_attr "type" "dmul") | |
633 | (eq_attr "cpu" "mpccore")) | |
634 | 5 5) | |
635 | ||
cfb557c4 RK |
636 | (define_function_unit "fpu" 1 0 |
637 | (and (eq_attr "type" "dmul") | |
51b8fc2c | 638 | (eq_attr "cpu" "ppc601")) |
b6c9286a | 639 | 5 2) |
cfb557c4 | 640 | |
b6c9286a | 641 | ; is this true? |
cfb557c4 RK |
642 | (define_function_unit "fpu" 1 0 |
643 | (and (eq_attr "type" "dmul") | |
bef84347 | 644 | (eq_attr "cpu" "ppc603,ppc750")) |
51b8fc2c | 645 | 4 2) |
cfb557c4 RK |
646 | |
647 | (define_function_unit "fpu" 1 0 | |
51b8fc2c | 648 | (and (eq_attr "type" "dmul") |
ed947a96 | 649 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc7400")) |
b6c9286a | 650 | 3 1) |
51b8fc2c RK |
651 | |
652 | (define_function_unit "fpu" 1 0 | |
653 | (and (eq_attr "type" "sdiv,ddiv") | |
2661cdd9 | 654 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 655 | 19 19) |
cfb557c4 | 656 | |
3cb999d8 DE |
657 | (define_function_unit "fpu" 1 0 |
658 | (and (eq_attr "type" "sdiv") | |
659 | (eq_attr "cpu" "rs64a")) | |
660 | 31 31) | |
661 | ||
cfb557c4 RK |
662 | (define_function_unit "fpu" 1 0 |
663 | (and (eq_attr "type" "sdiv") | |
ed947a96 | 664 | (eq_attr "cpu" "ppc601,ppc750,ppc7400")) |
51b8fc2c RK |
665 | 17 17) |
666 | ||
ed947a96 DJ |
667 | (define_function_unit "fpu" 1 0 |
668 | (and (eq_attr "type" "sdiv") | |
669 | (eq_attr "cpu" "ppc7450")) | |
670 | 21 21) | |
671 | ||
cf27b467 MM |
672 | (define_function_unit "fpu" 1 0 |
673 | (and (eq_attr "type" "sdiv") | |
674 | (eq_attr "cpu" "mpccore")) | |
675 | 10 10) | |
676 | ||
51b8fc2c RK |
677 | (define_function_unit "fpu" 1 0 |
678 | (and (eq_attr "type" "sdiv") | |
cac8ce95 | 679 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620")) |
51b8fc2c | 680 | 18 18) |
cfb557c4 | 681 | |
cf27b467 MM |
682 | (define_function_unit "fpu" 1 0 |
683 | (and (eq_attr "type" "ddiv") | |
684 | (eq_attr "cpu" "mpccore")) | |
685 | 17 17) | |
686 | ||
cfb557c4 RK |
687 | (define_function_unit "fpu" 1 0 |
688 | (and (eq_attr "type" "ddiv") | |
ed947a96 | 689 | (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620,ppc7400")) |
51b8fc2c | 690 | 31 31) |
cfb557c4 | 691 | |
ed947a96 DJ |
692 | (define_function_unit "fpu" 1 0 |
693 | (and (eq_attr "type" "ddiv") | |
694 | (eq_attr "cpu" "ppc7450")) | |
695 | 35 35) | |
696 | ||
cfb557c4 RK |
697 | (define_function_unit "fpu" 1 0 |
698 | (and (eq_attr "type" "ddiv") | |
b7ff3d82 | 699 | (eq_attr "cpu" "ppc603")) |
51b8fc2c | 700 | 33 33) |
cfb557c4 RK |
701 | |
702 | (define_function_unit "fpu" 1 0 | |
703 | (and (eq_attr "type" "ssqrt") | |
a473029f | 704 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 705 | 31 31) |
cfb557c4 RK |
706 | |
707 | (define_function_unit "fpu" 1 0 | |
708 | (and (eq_attr "type" "dsqrt") | |
a473029f | 709 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 710 | 31 31) |
b73d04f2 | 711 | |
51b8fc2c | 712 | ; RIOS2 has two symmetric FPUs. |
cfb557c4 | 713 | (define_function_unit "fpu2" 2 0 |
309323c2 | 714 | (and (eq_attr "type" "fp,dmul") |
cfb557c4 | 715 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 716 | 2 1) |
cfb557c4 | 717 | |
3cb999d8 | 718 | (define_function_unit "fpu2" 2 0 |
309323c2 | 719 | (and (eq_attr "type" "fp,dmul") |
3cb999d8 DE |
720 | (eq_attr "cpu" "ppc630")) |
721 | 3 1) | |
722 | ||
cfb557c4 | 723 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 724 | (and (eq_attr "type" "sdiv,ddiv") |
cfb557c4 | 725 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 726 | 17 17) |
ca7f5001 | 727 | |
3cb999d8 DE |
728 | (define_function_unit "fpu2" 2 0 |
729 | (and (eq_attr "type" "sdiv") | |
730 | (eq_attr "cpu" "ppc630")) | |
731 | 17 17) | |
732 | ||
733 | (define_function_unit "fpu2" 2 0 | |
734 | (and (eq_attr "type" "ddiv") | |
735 | (eq_attr "cpu" "ppc630")) | |
736 | 21 21) | |
737 | ||
ca7f5001 | 738 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 739 | (and (eq_attr "type" "ssqrt,dsqrt") |
ca7f5001 | 740 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 741 | 26 26) |
b6c9286a | 742 | |
3cb999d8 DE |
743 | (define_function_unit "fpu2" 2 0 |
744 | (and (eq_attr "type" "ssqrt") | |
745 | (eq_attr "cpu" "ppc630")) | |
746 | 18 18) | |
747 | ||
748 | (define_function_unit "fpu2" 2 0 | |
749 | (and (eq_attr "type" "dsqrt") | |
750 | (eq_attr "cpu" "ppc630")) | |
751 | 26 26) | |
752 | ||
309323c2 DE |
753 | ;; Power4 |
754 | (define_function_unit "lsu2" 2 0 | |
755 | (and (eq_attr "type" "load") | |
756 | (eq_attr "cpu" "power4")) | |
757 | 3 1) | |
758 | ||
759 | (define_function_unit "lsu2" 2 0 | |
760 | (and (eq_attr "type" "fpload") | |
761 | (eq_attr "cpu" "power4")) | |
762 | 5 1) | |
763 | ||
764 | (define_function_unit "lsu2" 2 0 | |
765 | (and (eq_attr "type" "store,fpstore") | |
766 | (eq_attr "cpu" "power4")) | |
767 | 1 1) | |
768 | ||
769 | (define_function_unit "iu2" 2 0 | |
770 | (and (eq_attr "type" "integer") | |
771 | (eq_attr "cpu" "power4")) | |
772 | 2 1) | |
773 | ||
774 | (define_function_unit "iu2" 2 0 | |
775 | (and (eq_attr "type" "imul,lmul") | |
776 | (eq_attr "cpu" "power4")) | |
777 | 7 6) | |
778 | ||
779 | (define_function_unit "iu2" 2 0 | |
780 | (and (eq_attr "type" "imul2") | |
781 | (eq_attr "cpu" "power4")) | |
782 | 5 4) | |
783 | ||
784 | (define_function_unit "iu2" 2 0 | |
785 | (and (eq_attr "type" "imul3") | |
786 | (eq_attr "cpu" "power4")) | |
787 | 4 3) | |
788 | ||
789 | (define_function_unit "iu2" 2 0 | |
790 | (and (eq_attr "type" "idiv") | |
791 | (eq_attr "cpu" "power4")) | |
792 | 36 35) | |
793 | ||
794 | (define_function_unit "iu2" 2 0 | |
795 | (and (eq_attr "type" "ldiv") | |
796 | (eq_attr "cpu" "power4")) | |
797 | 68 67) | |
798 | ||
799 | (define_function_unit "imuldiv" 1 0 | |
800 | (and (eq_attr "type" "idiv") | |
801 | (eq_attr "cpu" "power4")) | |
802 | 36 35) | |
803 | ||
804 | (define_function_unit "imuldiv" 1 0 | |
805 | (and (eq_attr "type" "ldiv") | |
806 | (eq_attr "cpu" "power4")) | |
807 | 68 67) | |
808 | ||
809 | (define_function_unit "iu2" 2 0 | |
e3485bbc | 810 | (and (eq_attr "type" "compare") |
309323c2 | 811 | (eq_attr "cpu" "power4")) |
e3485bbc | 812 | 3 1) |
309323c2 DE |
813 | |
814 | (define_function_unit "iu2" 2 0 | |
e3485bbc | 815 | (and (eq_attr "type" "delayed_compare") |
309323c2 | 816 | (eq_attr "cpu" "power4")) |
e3485bbc | 817 | 4 1) |
309323c2 DE |
818 | |
819 | (define_function_unit "bpu" 1 0 | |
820 | (and (eq_attr "type" "mtjmpr") | |
821 | (eq_attr "cpu" "power4")) | |
822 | 3 1) | |
823 | ||
824 | (define_function_unit "bpu" 1 0 | |
825 | (and (eq_attr "type" "jmpreg,branch") | |
826 | (eq_attr "cpu" "power4")) | |
827 | 2 1) | |
828 | ||
829 | (define_function_unit "cru" 1 0 | |
830 | (and (eq_attr "type" "cr_logical") | |
831 | (eq_attr "cpu" "power4")) | |
832 | 4 1) | |
833 | ||
834 | (define_function_unit "fpu2" 2 0 | |
835 | (and (eq_attr "type" "fp,dmul") | |
836 | (eq_attr "cpu" "power4")) | |
837 | 6 1) | |
838 | ||
e3485bbc DE |
839 | ; adjust_cost increases the cost of dependent branches, |
840 | ; so shave a few cycles off for fpcompare. | |
309323c2 DE |
841 | (define_function_unit "fpu2" 2 0 |
842 | (and (eq_attr "type" "fpcompare") | |
843 | (eq_attr "cpu" "power4")) | |
e3485bbc | 844 | 5 1) |
309323c2 DE |
845 | |
846 | (define_function_unit "fpu2" 2 0 | |
847 | (and (eq_attr "type" "sdiv,ddiv") | |
848 | (eq_attr "cpu" "power4")) | |
849 | 33 28) | |
850 | ||
851 | (define_function_unit "fpu2" 2 0 | |
852 | (and (eq_attr "type" "ssqrt,dsqrt") | |
853 | (eq_attr "cpu" "power4")) | |
854 | 40 35) | |
855 | ||
1fd4e8c1 RK |
856 | \f |
857 | ;; Start with fixed-point load and store insns. Here we put only the more | |
858 | ;; complex forms. Basic data transfer is done later. | |
859 | ||
51b8fc2c RK |
860 | (define_expand "zero_extendqidi2" |
861 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
862 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
863 | "TARGET_POWERPC64" | |
864 | "") | |
865 | ||
866 | (define_insn "" | |
867 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
868 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
869 | "TARGET_POWERPC64" | |
870 | "@ | |
871 | lbz%U1%X1 %0,%1 | |
4371f8af | 872 | rldicl %0,%1,0,56" |
51b8fc2c RK |
873 | [(set_attr "type" "load,*")]) |
874 | ||
875 | (define_insn "" | |
9ebbca7d GK |
876 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
877 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 878 | (const_int 0))) |
9ebbca7d | 879 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 880 | "TARGET_POWERPC64" |
9ebbca7d GK |
881 | "@ |
882 | rldicl. %2,%1,0,56 | |
883 | #" | |
884 | [(set_attr "type" "compare") | |
885 | (set_attr "length" "4,8")]) | |
886 | ||
887 | (define_split | |
888 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
889 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
890 | (const_int 0))) | |
891 | (clobber (match_scratch:DI 2 ""))] | |
892 | "TARGET_POWERPC64 && reload_completed" | |
893 | [(set (match_dup 2) | |
894 | (zero_extend:DI (match_dup 1))) | |
895 | (set (match_dup 0) | |
896 | (compare:CC (match_dup 2) | |
897 | (const_int 0)))] | |
898 | "") | |
51b8fc2c RK |
899 | |
900 | (define_insn "" | |
9ebbca7d GK |
901 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
902 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 903 | (const_int 0))) |
9ebbca7d | 904 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 905 | (zero_extend:DI (match_dup 1)))] |
58e09803 | 906 | "TARGET_POWERPC64" |
9ebbca7d GK |
907 | "@ |
908 | rldicl. %0,%1,0,56 | |
909 | #" | |
910 | [(set_attr "type" "compare") | |
911 | (set_attr "length" "4,8")]) | |
912 | ||
913 | (define_split | |
914 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
915 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
916 | (const_int 0))) | |
917 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
918 | (zero_extend:DI (match_dup 1)))] | |
919 | "TARGET_POWERPC64 && reload_completed" | |
920 | [(set (match_dup 0) | |
921 | (zero_extend:DI (match_dup 1))) | |
922 | (set (match_dup 2) | |
923 | (compare:CC (match_dup 0) | |
924 | (const_int 0)))] | |
925 | "") | |
51b8fc2c | 926 | |
2bee0449 RK |
927 | (define_insn "extendqidi2" |
928 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
929 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 930 | "TARGET_POWERPC64" |
2bee0449 | 931 | "extsb %0,%1") |
51b8fc2c RK |
932 | |
933 | (define_insn "" | |
9ebbca7d GK |
934 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
935 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 936 | (const_int 0))) |
9ebbca7d | 937 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 938 | "TARGET_POWERPC64" |
9ebbca7d GK |
939 | "@ |
940 | extsb. %2,%1 | |
941 | #" | |
942 | [(set_attr "type" "compare") | |
943 | (set_attr "length" "4,8")]) | |
944 | ||
945 | (define_split | |
946 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
947 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
948 | (const_int 0))) | |
949 | (clobber (match_scratch:DI 2 ""))] | |
950 | "TARGET_POWERPC64 && reload_completed" | |
951 | [(set (match_dup 2) | |
952 | (sign_extend:DI (match_dup 1))) | |
953 | (set (match_dup 0) | |
954 | (compare:CC (match_dup 2) | |
955 | (const_int 0)))] | |
956 | "") | |
51b8fc2c RK |
957 | |
958 | (define_insn "" | |
9ebbca7d GK |
959 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
960 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 961 | (const_int 0))) |
9ebbca7d | 962 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
963 | (sign_extend:DI (match_dup 1)))] |
964 | "TARGET_POWERPC64" | |
9ebbca7d GK |
965 | "@ |
966 | extsb. %0,%1 | |
967 | #" | |
968 | [(set_attr "type" "compare") | |
969 | (set_attr "length" "4,8")]) | |
970 | ||
971 | (define_split | |
972 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
973 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
974 | (const_int 0))) | |
975 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
976 | (sign_extend:DI (match_dup 1)))] | |
977 | "TARGET_POWERPC64 && reload_completed" | |
978 | [(set (match_dup 0) | |
979 | (sign_extend:DI (match_dup 1))) | |
980 | (set (match_dup 2) | |
981 | (compare:CC (match_dup 0) | |
982 | (const_int 0)))] | |
983 | "") | |
51b8fc2c RK |
984 | |
985 | (define_expand "zero_extendhidi2" | |
986 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
987 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
988 | "TARGET_POWERPC64" | |
989 | "") | |
990 | ||
991 | (define_insn "" | |
992 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
993 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
994 | "TARGET_POWERPC64" | |
995 | "@ | |
996 | lhz%U1%X1 %0,%1 | |
4371f8af | 997 | rldicl %0,%1,0,48" |
51b8fc2c RK |
998 | [(set_attr "type" "load,*")]) |
999 | ||
1000 | (define_insn "" | |
9ebbca7d GK |
1001 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1002 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1003 | (const_int 0))) |
9ebbca7d | 1004 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 1005 | "TARGET_POWERPC64" |
9ebbca7d GK |
1006 | "@ |
1007 | rldicl. %2,%1,0,48 | |
1008 | #" | |
1009 | [(set_attr "type" "compare") | |
1010 | (set_attr "length" "4,8")]) | |
1011 | ||
1012 | (define_split | |
1013 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1014 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1015 | (const_int 0))) | |
1016 | (clobber (match_scratch:DI 2 ""))] | |
1017 | "TARGET_POWERPC64 && reload_completed" | |
1018 | [(set (match_dup 2) | |
1019 | (zero_extend:DI (match_dup 1))) | |
1020 | (set (match_dup 0) | |
1021 | (compare:CC (match_dup 2) | |
1022 | (const_int 0)))] | |
1023 | "") | |
51b8fc2c RK |
1024 | |
1025 | (define_insn "" | |
9ebbca7d GK |
1026 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1027 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1028 | (const_int 0))) |
9ebbca7d | 1029 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1030 | (zero_extend:DI (match_dup 1)))] |
1031 | "TARGET_POWERPC64" | |
9ebbca7d GK |
1032 | "@ |
1033 | rldicl. %0,%1,0,48 | |
1034 | #" | |
1035 | [(set_attr "type" "compare") | |
1036 | (set_attr "length" "4,8")]) | |
1037 | ||
1038 | (define_split | |
1039 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1040 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1041 | (const_int 0))) | |
1042 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
1043 | (zero_extend:DI (match_dup 1)))] | |
1044 | "TARGET_POWERPC64 && reload_completed" | |
1045 | [(set (match_dup 0) | |
1046 | (zero_extend:DI (match_dup 1))) | |
1047 | (set (match_dup 2) | |
1048 | (compare:CC (match_dup 0) | |
1049 | (const_int 0)))] | |
1050 | "") | |
51b8fc2c RK |
1051 | |
1052 | (define_expand "extendhidi2" | |
1053 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1054 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1055 | "TARGET_POWERPC64" | |
1056 | "") | |
1057 | ||
1058 | (define_insn "" | |
1059 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
1060 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
1061 | "TARGET_POWERPC64" | |
1062 | "@ | |
1063 | lha%U1%X1 %0,%1 | |
1064 | extsh %0,%1" | |
1065 | [(set_attr "type" "load,*")]) | |
1066 | ||
1067 | (define_insn "" | |
9ebbca7d GK |
1068 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1069 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1070 | (const_int 0))) |
9ebbca7d | 1071 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 1072 | "TARGET_POWERPC64" |
9ebbca7d GK |
1073 | "@ |
1074 | extsh. %2,%1 | |
1075 | #" | |
1076 | [(set_attr "type" "compare") | |
1077 | (set_attr "length" "4,8")]) | |
1078 | ||
1079 | (define_split | |
1080 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1081 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1082 | (const_int 0))) | |
1083 | (clobber (match_scratch:DI 2 ""))] | |
1084 | "TARGET_POWERPC64 && reload_completed" | |
1085 | [(set (match_dup 2) | |
1086 | (sign_extend:DI (match_dup 1))) | |
1087 | (set (match_dup 0) | |
1088 | (compare:CC (match_dup 2) | |
1089 | (const_int 0)))] | |
1090 | "") | |
51b8fc2c RK |
1091 | |
1092 | (define_insn "" | |
9ebbca7d GK |
1093 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1094 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1095 | (const_int 0))) |
9ebbca7d | 1096 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1097 | (sign_extend:DI (match_dup 1)))] |
1098 | "TARGET_POWERPC64" | |
9ebbca7d GK |
1099 | "@ |
1100 | extsh. %0,%1 | |
1101 | #" | |
1102 | [(set_attr "type" "compare") | |
1103 | (set_attr "length" "4,8")]) | |
1104 | ||
1105 | (define_split | |
1106 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1107 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1108 | (const_int 0))) | |
1109 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
1110 | (sign_extend:DI (match_dup 1)))] | |
1111 | "TARGET_POWERPC64 && reload_completed" | |
1112 | [(set (match_dup 0) | |
1113 | (sign_extend:DI (match_dup 1))) | |
1114 | (set (match_dup 2) | |
1115 | (compare:CC (match_dup 0) | |
1116 | (const_int 0)))] | |
1117 | "") | |
51b8fc2c RK |
1118 | |
1119 | (define_expand "zero_extendsidi2" | |
1120 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1121 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1122 | "TARGET_POWERPC64" | |
1123 | "") | |
1124 | ||
1125 | (define_insn "" | |
1126 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
1127 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
1128 | "TARGET_POWERPC64" | |
1129 | "@ | |
1130 | lwz%U1%X1 %0,%1 | |
1131 | rldicl %0,%1,0,32" | |
1132 | [(set_attr "type" "load,*")]) | |
1133 | ||
1134 | (define_insn "" | |
9ebbca7d GK |
1135 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1136 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1137 | (const_int 0))) |
9ebbca7d | 1138 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 1139 | "TARGET_POWERPC64" |
9ebbca7d GK |
1140 | "@ |
1141 | rldicl. %2,%1,0,32 | |
1142 | #" | |
1143 | [(set_attr "type" "compare") | |
1144 | (set_attr "length" "4,8")]) | |
1145 | ||
1146 | (define_split | |
1147 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1148 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1149 | (const_int 0))) | |
1150 | (clobber (match_scratch:DI 2 ""))] | |
1151 | "TARGET_POWERPC64 && reload_completed" | |
1152 | [(set (match_dup 2) | |
1153 | (zero_extend:DI (match_dup 1))) | |
1154 | (set (match_dup 0) | |
1155 | (compare:CC (match_dup 2) | |
1156 | (const_int 0)))] | |
1157 | "") | |
51b8fc2c RK |
1158 | |
1159 | (define_insn "" | |
9ebbca7d GK |
1160 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1161 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1162 | (const_int 0))) |
9ebbca7d | 1163 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1164 | (zero_extend:DI (match_dup 1)))] |
1165 | "TARGET_POWERPC64" | |
9ebbca7d GK |
1166 | "@ |
1167 | rldicl. %0,%1,0,32 | |
1168 | #" | |
1169 | [(set_attr "type" "compare") | |
1170 | (set_attr "length" "4,8")]) | |
1171 | ||
1172 | (define_split | |
1173 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1174 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1175 | (const_int 0))) | |
1176 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
1177 | (zero_extend:DI (match_dup 1)))] | |
1178 | "TARGET_POWERPC64 && reload_completed" | |
1179 | [(set (match_dup 0) | |
1180 | (zero_extend:DI (match_dup 1))) | |
1181 | (set (match_dup 2) | |
1182 | (compare:CC (match_dup 0) | |
1183 | (const_int 0)))] | |
1184 | "") | |
51b8fc2c RK |
1185 | |
1186 | (define_expand "extendsidi2" | |
1187 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1188 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1189 | "TARGET_POWERPC64" | |
1190 | "") | |
1191 | ||
1192 | (define_insn "" | |
1193 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 1194 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
1195 | "TARGET_POWERPC64" |
1196 | "@ | |
1197 | lwa%U1%X1 %0,%1 | |
1198 | extsw %0,%1" | |
1199 | [(set_attr "type" "load,*")]) | |
1200 | ||
1201 | (define_insn "" | |
9ebbca7d GK |
1202 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1203 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1204 | (const_int 0))) |
9ebbca7d | 1205 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 1206 | "TARGET_POWERPC64" |
9ebbca7d GK |
1207 | "@ |
1208 | extsw. %2,%1 | |
1209 | #" | |
1210 | [(set_attr "type" "compare") | |
1211 | (set_attr "length" "4,8")]) | |
1212 | ||
1213 | (define_split | |
1214 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1215 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1216 | (const_int 0))) | |
1217 | (clobber (match_scratch:DI 2 ""))] | |
1218 | "TARGET_POWERPC64 && reload_completed" | |
1219 | [(set (match_dup 2) | |
1220 | (sign_extend:DI (match_dup 1))) | |
1221 | (set (match_dup 0) | |
1222 | (compare:CC (match_dup 2) | |
1223 | (const_int 0)))] | |
1224 | "") | |
51b8fc2c RK |
1225 | |
1226 | (define_insn "" | |
9ebbca7d GK |
1227 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1228 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1229 | (const_int 0))) |
9ebbca7d | 1230 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1231 | (sign_extend:DI (match_dup 1)))] |
1232 | "TARGET_POWERPC64" | |
9ebbca7d GK |
1233 | "@ |
1234 | extsw. %0,%1 | |
1235 | #" | |
1236 | [(set_attr "type" "compare") | |
1237 | (set_attr "length" "4,8")]) | |
1238 | ||
1239 | (define_split | |
1240 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1241 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1242 | (const_int 0))) | |
1243 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
1244 | (sign_extend:DI (match_dup 1)))] | |
1245 | "TARGET_POWERPC64 && reload_completed" | |
1246 | [(set (match_dup 0) | |
1247 | (sign_extend:DI (match_dup 1))) | |
1248 | (set (match_dup 2) | |
1249 | (compare:CC (match_dup 0) | |
1250 | (const_int 0)))] | |
1251 | "") | |
51b8fc2c | 1252 | |
1fd4e8c1 | 1253 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
1254 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1255 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1256 | "" |
1257 | "") | |
1258 | ||
1259 | (define_insn "" | |
cd2b37d9 | 1260 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1261 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
1262 | "" | |
1263 | "@ | |
1264 | lbz%U1%X1 %0,%1 | |
005a35b9 | 1265 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
1266 | [(set_attr "type" "load,*")]) |
1267 | ||
1268 | (define_insn "" | |
9ebbca7d GK |
1269 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1270 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1271 | (const_int 0))) |
9ebbca7d | 1272 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1273 | "" |
9ebbca7d GK |
1274 | "@ |
1275 | {andil.|andi.} %2,%1,0xff | |
1276 | #" | |
1277 | [(set_attr "type" "compare") | |
1278 | (set_attr "length" "4,8")]) | |
1279 | ||
1280 | (define_split | |
1281 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1282 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1283 | (const_int 0))) | |
1284 | (clobber (match_scratch:SI 2 ""))] | |
1285 | "reload_completed" | |
1286 | [(set (match_dup 2) | |
1287 | (zero_extend:SI (match_dup 1))) | |
1288 | (set (match_dup 0) | |
1289 | (compare:CC (match_dup 2) | |
1290 | (const_int 0)))] | |
1291 | "") | |
1fd4e8c1 RK |
1292 | |
1293 | (define_insn "" | |
9ebbca7d GK |
1294 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1295 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1296 | (const_int 0))) |
9ebbca7d | 1297 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1298 | (zero_extend:SI (match_dup 1)))] |
1299 | "" | |
9ebbca7d GK |
1300 | "@ |
1301 | {andil.|andi.} %0,%1,0xff | |
1302 | #" | |
1303 | [(set_attr "type" "compare") | |
1304 | (set_attr "length" "4,8")]) | |
1305 | ||
1306 | (define_split | |
1307 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1308 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1309 | (const_int 0))) | |
1310 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1311 | (zero_extend:SI (match_dup 1)))] | |
1312 | "reload_completed" | |
1313 | [(set (match_dup 0) | |
1314 | (zero_extend:SI (match_dup 1))) | |
1315 | (set (match_dup 2) | |
1316 | (compare:CC (match_dup 0) | |
1317 | (const_int 0)))] | |
1318 | "") | |
1fd4e8c1 | 1319 | |
51b8fc2c RK |
1320 | (define_expand "extendqisi2" |
1321 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1322 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
1323 | "" | |
1324 | " | |
1325 | { | |
1326 | if (TARGET_POWERPC) | |
1327 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
1328 | else if (TARGET_POWER) | |
1329 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
1330 | else | |
1331 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
1332 | DONE; | |
1333 | }") | |
1334 | ||
1335 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
1336 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1337 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 1338 | "TARGET_POWERPC" |
2bee0449 | 1339 | "extsb %0,%1") |
51b8fc2c RK |
1340 | |
1341 | (define_insn "" | |
9ebbca7d GK |
1342 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1343 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1344 | (const_int 0))) |
9ebbca7d | 1345 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 1346 | "TARGET_POWERPC" |
9ebbca7d GK |
1347 | "@ |
1348 | extsb. %2,%1 | |
1349 | #" | |
1350 | [(set_attr "type" "compare") | |
1351 | (set_attr "length" "4,8")]) | |
1352 | ||
1353 | (define_split | |
1354 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1355 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1356 | (const_int 0))) | |
1357 | (clobber (match_scratch:SI 2 ""))] | |
1358 | "TARGET_POWERPC && reload_completed" | |
1359 | [(set (match_dup 2) | |
1360 | (sign_extend:SI (match_dup 1))) | |
1361 | (set (match_dup 0) | |
1362 | (compare:CC (match_dup 2) | |
1363 | (const_int 0)))] | |
1364 | "") | |
51b8fc2c RK |
1365 | |
1366 | (define_insn "" | |
9ebbca7d GK |
1367 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1368 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1369 | (const_int 0))) |
9ebbca7d | 1370 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1371 | (sign_extend:SI (match_dup 1)))] |
1372 | "TARGET_POWERPC" | |
9ebbca7d GK |
1373 | "@ |
1374 | extsb. %0,%1 | |
1375 | #" | |
1376 | [(set_attr "type" "compare") | |
1377 | (set_attr "length" "4,8")]) | |
1378 | ||
1379 | (define_split | |
1380 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1381 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1382 | (const_int 0))) | |
1383 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1384 | (sign_extend:SI (match_dup 1)))] | |
1385 | "TARGET_POWERPC && reload_completed" | |
1386 | [(set (match_dup 0) | |
1387 | (sign_extend:SI (match_dup 1))) | |
1388 | (set (match_dup 2) | |
1389 | (compare:CC (match_dup 0) | |
1390 | (const_int 0)))] | |
1391 | "") | |
51b8fc2c RK |
1392 | |
1393 | (define_expand "extendqisi2_power" | |
1394 | [(parallel [(set (match_dup 2) | |
1395 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1396 | (const_int 24))) | |
1397 | (clobber (scratch:SI))]) | |
1398 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1399 | (ashiftrt:SI (match_dup 2) | |
1400 | (const_int 24))) | |
1401 | (clobber (scratch:SI))])] | |
1402 | "TARGET_POWER" | |
1403 | " | |
1404 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1405 | operands[2] = gen_reg_rtx (SImode); }") | |
1406 | ||
1407 | (define_expand "extendqisi2_no_power" | |
1408 | [(set (match_dup 2) | |
1409 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1410 | (const_int 24))) | |
1411 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1412 | (ashiftrt:SI (match_dup 2) | |
1413 | (const_int 24)))] | |
1414 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1415 | " | |
1416 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1417 | operands[2] = gen_reg_rtx (SImode); }") | |
1418 | ||
1fd4e8c1 | 1419 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
1420 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
1421 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1422 | "" |
1423 | "") | |
1424 | ||
1425 | (define_insn "" | |
cd2b37d9 | 1426 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1427 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
1428 | "" | |
1429 | "@ | |
1430 | lbz%U1%X1 %0,%1 | |
005a35b9 | 1431 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
1432 | [(set_attr "type" "load,*")]) |
1433 | ||
1434 | (define_insn "" | |
9ebbca7d GK |
1435 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1436 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1437 | (const_int 0))) |
9ebbca7d | 1438 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 1439 | "" |
9ebbca7d GK |
1440 | "@ |
1441 | {andil.|andi.} %2,%1,0xff | |
1442 | #" | |
1443 | [(set_attr "type" "compare") | |
1444 | (set_attr "length" "4,8")]) | |
1445 | ||
1446 | (define_split | |
1447 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1448 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1449 | (const_int 0))) | |
1450 | (clobber (match_scratch:HI 2 ""))] | |
1451 | "reload_completed" | |
1452 | [(set (match_dup 2) | |
1453 | (zero_extend:HI (match_dup 1))) | |
1454 | (set (match_dup 0) | |
1455 | (compare:CC (match_dup 2) | |
1456 | (const_int 0)))] | |
1457 | "") | |
1fd4e8c1 | 1458 | |
51b8fc2c | 1459 | (define_insn "" |
9ebbca7d GK |
1460 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1461 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1462 | (const_int 0))) |
9ebbca7d | 1463 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
1464 | (zero_extend:HI (match_dup 1)))] |
1465 | "" | |
9ebbca7d GK |
1466 | "@ |
1467 | {andil.|andi.} %0,%1,0xff | |
1468 | #" | |
1469 | [(set_attr "type" "compare") | |
1470 | (set_attr "length" "4,8")]) | |
1471 | ||
1472 | (define_split | |
1473 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1474 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1475 | (const_int 0))) | |
1476 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1477 | (zero_extend:HI (match_dup 1)))] | |
1478 | "reload_completed" | |
1479 | [(set (match_dup 0) | |
1480 | (zero_extend:HI (match_dup 1))) | |
1481 | (set (match_dup 2) | |
1482 | (compare:CC (match_dup 0) | |
1483 | (const_int 0)))] | |
1484 | "") | |
815cdc52 MM |
1485 | |
1486 | (define_expand "extendqihi2" | |
1487 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
1488 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
1489 | "" | |
1490 | " | |
1491 | { | |
1492 | if (TARGET_POWERPC) | |
1493 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
1494 | else if (TARGET_POWER) | |
1495 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
1496 | else | |
1497 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
1498 | DONE; | |
1499 | }") | |
1500 | ||
1501 | (define_insn "extendqihi2_ppc" | |
1502 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
1503 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
1504 | "TARGET_POWERPC" | |
1505 | "extsb %0,%1") | |
1506 | ||
1507 | (define_insn "" | |
9ebbca7d GK |
1508 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1509 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1510 | (const_int 0))) |
9ebbca7d | 1511 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 1512 | "TARGET_POWERPC" |
9ebbca7d GK |
1513 | "@ |
1514 | extsb. %2,%1 | |
1515 | #" | |
1516 | [(set_attr "type" "compare") | |
1517 | (set_attr "length" "4,8")]) | |
1518 | ||
1519 | (define_split | |
1520 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1521 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1522 | (const_int 0))) | |
1523 | (clobber (match_scratch:HI 2 ""))] | |
1524 | "TARGET_POWERPC && reload_completed" | |
1525 | [(set (match_dup 2) | |
1526 | (sign_extend:HI (match_dup 1))) | |
1527 | (set (match_dup 0) | |
1528 | (compare:CC (match_dup 2) | |
1529 | (const_int 0)))] | |
1530 | "") | |
815cdc52 MM |
1531 | |
1532 | (define_insn "" | |
9ebbca7d GK |
1533 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1534 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1535 | (const_int 0))) |
9ebbca7d | 1536 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1537 | (sign_extend:HI (match_dup 1)))] |
1538 | "TARGET_POWERPC" | |
9ebbca7d GK |
1539 | "@ |
1540 | extsb. %0,%1 | |
1541 | #" | |
1542 | [(set_attr "type" "compare") | |
1543 | (set_attr "length" "4,8")]) | |
1544 | ||
1545 | (define_split | |
1546 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1547 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1548 | (const_int 0))) | |
1549 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1550 | (sign_extend:HI (match_dup 1)))] | |
1551 | "TARGET_POWERPC && reload_completed" | |
1552 | [(set (match_dup 0) | |
1553 | (sign_extend:HI (match_dup 1))) | |
1554 | (set (match_dup 2) | |
1555 | (compare:CC (match_dup 0) | |
1556 | (const_int 0)))] | |
1557 | "") | |
51b8fc2c RK |
1558 | |
1559 | (define_expand "extendqihi2_power" | |
1560 | [(parallel [(set (match_dup 2) | |
1561 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1562 | (const_int 24))) | |
1563 | (clobber (scratch:SI))]) | |
1564 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
1565 | (ashiftrt:SI (match_dup 2) | |
1566 | (const_int 24))) | |
1567 | (clobber (scratch:SI))])] | |
1568 | "TARGET_POWER" | |
1569 | " | |
1570 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1571 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1572 | operands[2] = gen_reg_rtx (SImode); }") | |
1573 | ||
1574 | (define_expand "extendqihi2_no_power" | |
1575 | [(set (match_dup 2) | |
1576 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1577 | (const_int 24))) | |
1578 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1579 | (ashiftrt:SI (match_dup 2) | |
1580 | (const_int 24)))] | |
1581 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1582 | " | |
1583 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1584 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1585 | operands[2] = gen_reg_rtx (SImode); }") | |
1586 | ||
1fd4e8c1 | 1587 | (define_expand "zero_extendhisi2" |
5f243543 | 1588 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 1589 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
1590 | "" |
1591 | "") | |
1592 | ||
1593 | (define_insn "" | |
cd2b37d9 | 1594 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1595 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1596 | "" | |
1597 | "@ | |
1598 | lhz%U1%X1 %0,%1 | |
005a35b9 | 1599 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
1600 | [(set_attr "type" "load,*")]) |
1601 | ||
1602 | (define_insn "" | |
9ebbca7d GK |
1603 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1604 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1605 | (const_int 0))) |
9ebbca7d | 1606 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1607 | "" |
9ebbca7d GK |
1608 | "@ |
1609 | {andil.|andi.} %2,%1,0xffff | |
1610 | #" | |
1611 | [(set_attr "type" "compare") | |
1612 | (set_attr "length" "4,8")]) | |
1613 | ||
1614 | (define_split | |
1615 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1616 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1617 | (const_int 0))) | |
1618 | (clobber (match_scratch:SI 2 ""))] | |
1619 | "reload_completed" | |
1620 | [(set (match_dup 2) | |
1621 | (zero_extend:SI (match_dup 1))) | |
1622 | (set (match_dup 0) | |
1623 | (compare:CC (match_dup 2) | |
1624 | (const_int 0)))] | |
1625 | "") | |
1fd4e8c1 RK |
1626 | |
1627 | (define_insn "" | |
9ebbca7d GK |
1628 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1629 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1630 | (const_int 0))) |
9ebbca7d | 1631 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1632 | (zero_extend:SI (match_dup 1)))] |
1633 | "" | |
9ebbca7d GK |
1634 | "@ |
1635 | {andil.|andi.} %0,%1,0xffff | |
1636 | #" | |
1637 | [(set_attr "type" "compare") | |
1638 | (set_attr "length" "4,8")]) | |
1639 | ||
1640 | (define_split | |
1641 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1642 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1643 | (const_int 0))) | |
1644 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1645 | (zero_extend:SI (match_dup 1)))] | |
1646 | "reload_completed" | |
1647 | [(set (match_dup 0) | |
1648 | (zero_extend:SI (match_dup 1))) | |
1649 | (set (match_dup 2) | |
1650 | (compare:CC (match_dup 0) | |
1651 | (const_int 0)))] | |
1652 | "") | |
1fd4e8c1 RK |
1653 | |
1654 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
1655 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1656 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1657 | "" |
1658 | "") | |
1659 | ||
1660 | (define_insn "" | |
cd2b37d9 | 1661 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1662 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1663 | "" | |
1664 | "@ | |
1665 | lha%U1%X1 %0,%1 | |
ca7f5001 | 1666 | {exts|extsh} %0,%1" |
1fd4e8c1 RK |
1667 | [(set_attr "type" "load,*")]) |
1668 | ||
1669 | (define_insn "" | |
9ebbca7d GK |
1670 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1671 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1672 | (const_int 0))) |
9ebbca7d | 1673 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1674 | "" |
9ebbca7d GK |
1675 | "@ |
1676 | {exts.|extsh.} %2,%1 | |
1677 | #" | |
1678 | [(set_attr "type" "compare") | |
1679 | (set_attr "length" "4,8")]) | |
1680 | ||
1681 | (define_split | |
1682 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1683 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1684 | (const_int 0))) | |
1685 | (clobber (match_scratch:SI 2 ""))] | |
1686 | "reload_completed" | |
1687 | [(set (match_dup 2) | |
1688 | (sign_extend:SI (match_dup 1))) | |
1689 | (set (match_dup 0) | |
1690 | (compare:CC (match_dup 2) | |
1691 | (const_int 0)))] | |
1692 | "") | |
1fd4e8c1 RK |
1693 | |
1694 | (define_insn "" | |
9ebbca7d GK |
1695 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1696 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1697 | (const_int 0))) |
9ebbca7d | 1698 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1699 | (sign_extend:SI (match_dup 1)))] |
1700 | "" | |
9ebbca7d GK |
1701 | "@ |
1702 | {exts.|extsh.} %0,%1 | |
1703 | #" | |
1704 | [(set_attr "type" "compare") | |
1705 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1706 | \f |
9ebbca7d GK |
1707 | (define_split |
1708 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1709 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1710 | (const_int 0))) | |
1711 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1712 | (sign_extend:SI (match_dup 1)))] | |
1713 | "reload_completed" | |
1714 | [(set (match_dup 0) | |
1715 | (sign_extend:SI (match_dup 1))) | |
1716 | (set (match_dup 2) | |
1717 | (compare:CC (match_dup 0) | |
1718 | (const_int 0)))] | |
1719 | "") | |
1720 | ||
1fd4e8c1 | 1721 | ;; Fixed-point arithmetic insns. |
deb9225a RK |
1722 | |
1723 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
1724 | ;; allowing register zero as source. | |
7cd5235b MM |
1725 | (define_expand "addsi3" |
1726 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1727 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 1728 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
7cd5235b MM |
1729 | "" |
1730 | " | |
1731 | { | |
677a9668 DE |
1732 | if (GET_CODE (operands[2]) == CONST_INT |
1733 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 1734 | { |
677a9668 | 1735 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
1736 | ? operands[0] : gen_reg_rtx (SImode)); |
1737 | ||
2bfcf297 | 1738 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1739 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 1740 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
7cd5235b | 1741 | |
9ebbca7d GK |
1742 | /* The ordering here is important for the prolog expander. |
1743 | When space is allocated from the stack, adding 'low' first may | |
1744 | produce a temporary deallocation (which would be bad). */ | |
2bfcf297 | 1745 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest))); |
7cd5235b MM |
1746 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); |
1747 | DONE; | |
1748 | } | |
1749 | }") | |
1750 | ||
1751 | (define_insn "*addsi3_internal1" | |
1752 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
1753 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 1754 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1755 | "" |
1756 | "@ | |
deb9225a RK |
1757 | {cax|add} %0,%1,%2 |
1758 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1759 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1760 | {cau|addis} %0,%1,%v2" |
1761 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1762 | |
ee890fe2 SS |
1763 | (define_insn "addsi3_high" |
1764 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1765 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1766 | (high:SI (match_operand 2 "" ""))))] | |
1767 | "TARGET_MACHO && !TARGET_64BIT" | |
1768 | "{cau|addis} %0,%1,ha16(%2)" | |
1769 | [(set_attr "length" "4")]) | |
1770 | ||
7cd5235b | 1771 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1772 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1773 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1774 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1775 | (const_int 0))) |
cb8cc086 | 1776 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
0ad91047 | 1777 | "! TARGET_POWERPC64" |
deb9225a RK |
1778 | "@ |
1779 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1780 | {ai.|addic.} %3,%1,%2 |
1781 | # | |
1782 | #" | |
1783 | [(set_attr "type" "compare") | |
1784 | (set_attr "length" "4,4,8,8")]) | |
1785 | ||
1786 | (define_split | |
1787 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1788 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1789 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1790 | (const_int 0))) | |
1791 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1792 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1793 | [(set (match_dup 3) |
1794 | (plus:SI (match_dup 1) | |
1795 | (match_dup 2))) | |
1796 | (set (match_dup 0) | |
1797 | (compare:CC (match_dup 3) | |
1798 | (const_int 0)))] | |
1799 | "") | |
7e69e155 | 1800 | |
7cd5235b | 1801 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1802 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1803 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1804 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1805 | (const_int 0))) |
cb8cc086 MM |
1806 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1807 | (plus:SI (match_dup 1) | |
1808 | (match_dup 2)))] | |
0ad91047 | 1809 | "! TARGET_POWERPC64" |
deb9225a RK |
1810 | "@ |
1811 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1812 | {ai.|addic.} %0,%1,%2 |
1813 | # | |
1814 | #" | |
1815 | [(set_attr "type" "compare") | |
1816 | (set_attr "length" "4,4,8,8")]) | |
1817 | ||
1818 | (define_split | |
1819 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1820 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1821 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1822 | (const_int 0))) | |
1823 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1824 | (plus:SI (match_dup 1) (match_dup 2)))] | |
0ad91047 | 1825 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1826 | [(set (match_dup 0) |
1827 | (plus:SI (match_dup 1) | |
1828 | (match_dup 2))) | |
1829 | (set (match_dup 3) | |
1830 | (compare:CC (match_dup 0) | |
1831 | (const_int 0)))] | |
1832 | "") | |
7e69e155 | 1833 | |
f357808b RK |
1834 | ;; Split an add that we can't do in one insn into two insns, each of which |
1835 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1836 | ;; add should be last in case the result gets used in an address. | |
1837 | ||
1838 | (define_split | |
cd2b37d9 RK |
1839 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1840 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1841 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1842 | "" |
f357808b RK |
1843 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1844 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1845 | " | |
1fd4e8c1 | 1846 | { |
2bfcf297 | 1847 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1848 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 1849 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
1fd4e8c1 | 1850 | |
2bfcf297 | 1851 | operands[3] = GEN_INT (rest); |
e6ca2c17 | 1852 | operands[4] = GEN_INT (low); |
1fd4e8c1 RK |
1853 | }") |
1854 | ||
8de2a197 | 1855 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1856 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1857 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1858 | "" |
ca7f5001 RK |
1859 | "nor %0,%1,%1") |
1860 | ||
1861 | (define_insn "" | |
52d3af72 DE |
1862 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1863 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1864 | (const_int 0))) |
52d3af72 | 1865 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1866 | "! TARGET_POWERPC64" |
52d3af72 DE |
1867 | "@ |
1868 | nor. %2,%1,%1 | |
1869 | #" | |
1870 | [(set_attr "type" "compare") | |
1871 | (set_attr "length" "4,8")]) | |
1872 | ||
1873 | (define_split | |
1874 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1875 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1876 | (const_int 0))) | |
1877 | (clobber (match_scratch:SI 2 ""))] | |
0ad91047 | 1878 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1879 | [(set (match_dup 2) |
1880 | (not:SI (match_dup 1))) | |
1881 | (set (match_dup 0) | |
1882 | (compare:CC (match_dup 2) | |
1883 | (const_int 0)))] | |
1884 | "") | |
ca7f5001 RK |
1885 | |
1886 | (define_insn "" | |
52d3af72 DE |
1887 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1888 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1889 | (const_int 0))) |
52d3af72 | 1890 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1891 | (not:SI (match_dup 1)))] |
0ad91047 | 1892 | "! TARGET_POWERPC64" |
52d3af72 DE |
1893 | "@ |
1894 | nor. %0,%1,%1 | |
1895 | #" | |
1896 | [(set_attr "type" "compare") | |
1897 | (set_attr "length" "4,8")]) | |
1898 | ||
1899 | (define_split | |
1900 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1901 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1902 | (const_int 0))) | |
1cb18e3c | 1903 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
52d3af72 | 1904 | (not:SI (match_dup 1)))] |
0ad91047 | 1905 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1906 | [(set (match_dup 0) |
1907 | (not:SI (match_dup 1))) | |
1908 | (set (match_dup 2) | |
1909 | (compare:CC (match_dup 0) | |
1910 | (const_int 0)))] | |
1911 | "") | |
1fd4e8c1 RK |
1912 | |
1913 | (define_insn "" | |
3d91674b RK |
1914 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1915 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1916 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1917 | "! TARGET_POWERPC" |
ca7f5001 | 1918 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1919 | |
deb9225a RK |
1920 | (define_insn "" |
1921 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1922 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1923 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1924 | "TARGET_POWERPC" | |
1925 | "@ | |
1926 | subf %0,%2,%1 | |
1927 | subfic %0,%2,%1") | |
1928 | ||
1fd4e8c1 | 1929 | (define_insn "" |
cb8cc086 MM |
1930 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1931 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1932 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1933 | (const_int 0))) |
cb8cc086 | 1934 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1935 | "! TARGET_POWERPC" |
cb8cc086 MM |
1936 | "@ |
1937 | {sf.|subfc.} %3,%2,%1 | |
1938 | #" | |
1939 | [(set_attr "type" "compare") | |
1940 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1941 | |
deb9225a | 1942 | (define_insn "" |
cb8cc086 MM |
1943 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1944 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1945 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1946 | (const_int 0))) |
cb8cc086 | 1947 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 1948 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
cb8cc086 MM |
1949 | "@ |
1950 | subf. %3,%2,%1 | |
1951 | #" | |
1952 | [(set_attr "type" "compare") | |
1953 | (set_attr "length" "4,8")]) | |
1954 | ||
1955 | (define_split | |
1956 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1957 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1958 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1959 | (const_int 0))) | |
1960 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1961 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1962 | [(set (match_dup 3) |
1963 | (minus:SI (match_dup 1) | |
1964 | (match_dup 2))) | |
1965 | (set (match_dup 0) | |
1966 | (compare:CC (match_dup 3) | |
1967 | (const_int 0)))] | |
1968 | "") | |
deb9225a | 1969 | |
1fd4e8c1 | 1970 | (define_insn "" |
cb8cc086 MM |
1971 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1972 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1973 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1974 | (const_int 0))) |
cb8cc086 | 1975 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1976 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1977 | "! TARGET_POWERPC" |
cb8cc086 MM |
1978 | "@ |
1979 | {sf.|subfc.} %0,%2,%1 | |
1980 | #" | |
1981 | [(set_attr "type" "compare") | |
1982 | (set_attr "length" "4,8")]) | |
815cdc52 | 1983 | |
29ae5b89 | 1984 | (define_insn "" |
cb8cc086 MM |
1985 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1986 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1987 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1988 | (const_int 0))) |
cb8cc086 MM |
1989 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1990 | (minus:SI (match_dup 1) | |
1991 | (match_dup 2)))] | |
0ad91047 | 1992 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
90612787 DE |
1993 | "@ |
1994 | subf. %0,%2,%1 | |
1995 | #" | |
cb8cc086 MM |
1996 | [(set_attr "type" "compare") |
1997 | (set_attr "length" "4,8")]) | |
1998 | ||
1999 | (define_split | |
2000 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2001 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2002 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2003 | (const_int 0))) | |
2004 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2005 | (minus:SI (match_dup 1) | |
2006 | (match_dup 2)))] | |
0ad91047 | 2007 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
2008 | [(set (match_dup 0) |
2009 | (minus:SI (match_dup 1) | |
2010 | (match_dup 2))) | |
2011 | (set (match_dup 3) | |
2012 | (compare:CC (match_dup 0) | |
2013 | (const_int 0)))] | |
2014 | "") | |
deb9225a | 2015 | |
1fd4e8c1 | 2016 | (define_expand "subsi3" |
cd2b37d9 | 2017 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 2018 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
f6bf7de2 | 2019 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
1fd4e8c1 | 2020 | "" |
a0044fb1 RK |
2021 | " |
2022 | { | |
2023 | if (GET_CODE (operands[2]) == CONST_INT) | |
2024 | { | |
2025 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
2026 | negate_rtx (SImode, operands[2]))); | |
2027 | DONE; | |
2028 | } | |
2029 | }") | |
1fd4e8c1 RK |
2030 | |
2031 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
2032 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
2033 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
2034 | ;; combine. | |
1fd4e8c1 RK |
2035 | |
2036 | (define_expand "sminsi3" | |
2037 | [(set (match_dup 3) | |
cd2b37d9 | 2038 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
2039 | (match_operand:SI 2 "reg_or_short_operand" "")) |
2040 | (const_int 0) | |
2041 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 2042 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 2043 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 2044 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 2045 | " |
a3170dc6 AH |
2046 | { |
2047 | if (TARGET_ISEL) | |
2048 | { | |
2049 | operands[2] = force_reg (SImode, operands[2]); | |
2050 | rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); | |
2051 | DONE; | |
2052 | } | |
2053 | ||
2054 | operands[3] = gen_reg_rtx (SImode); | |
2055 | }") | |
1fd4e8c1 | 2056 | |
95ac8e67 RK |
2057 | (define_split |
2058 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2059 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2060 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
2061 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 2062 | "TARGET_POWER" |
95ac8e67 RK |
2063 | [(set (match_dup 3) |
2064 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
2065 | (const_int 0) | |
2066 | (minus:SI (match_dup 2) (match_dup 1)))) | |
2067 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
2068 | "") | |
2069 | ||
1fd4e8c1 RK |
2070 | (define_expand "smaxsi3" |
2071 | [(set (match_dup 3) | |
cd2b37d9 | 2072 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
2073 | (match_operand:SI 2 "reg_or_short_operand" "")) |
2074 | (const_int 0) | |
2075 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 2076 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 2077 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 2078 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 2079 | " |
a3170dc6 AH |
2080 | { |
2081 | if (TARGET_ISEL) | |
2082 | { | |
2083 | operands[2] = force_reg (SImode, operands[2]); | |
2084 | rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); | |
2085 | DONE; | |
2086 | } | |
2087 | operands[3] = gen_reg_rtx (SImode); | |
2088 | }") | |
1fd4e8c1 | 2089 | |
95ac8e67 RK |
2090 | (define_split |
2091 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2092 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2093 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
2094 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 2095 | "TARGET_POWER" |
95ac8e67 RK |
2096 | [(set (match_dup 3) |
2097 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
2098 | (const_int 0) | |
2099 | (minus:SI (match_dup 2) (match_dup 1)))) | |
2100 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
2101 | "") | |
2102 | ||
1fd4e8c1 | 2103 | (define_expand "uminsi3" |
cd2b37d9 | 2104 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 2105 | (match_dup 5))) |
cd2b37d9 | 2106 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 2107 | (match_dup 5))) |
1fd4e8c1 RK |
2108 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
2109 | (const_int 0) | |
2110 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 2111 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 2112 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 2113 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 2114 | " |
bb68ff55 | 2115 | { |
a3170dc6 AH |
2116 | if (TARGET_ISEL) |
2117 | { | |
2118 | rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]); | |
2119 | DONE; | |
2120 | } | |
bb68ff55 MM |
2121 | operands[3] = gen_reg_rtx (SImode); |
2122 | operands[4] = gen_reg_rtx (SImode); | |
2123 | operands[5] = GEN_INT (-2147483647 - 1); | |
2124 | }") | |
1fd4e8c1 RK |
2125 | |
2126 | (define_expand "umaxsi3" | |
cd2b37d9 | 2127 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 2128 | (match_dup 5))) |
cd2b37d9 | 2129 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 2130 | (match_dup 5))) |
1fd4e8c1 RK |
2131 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
2132 | (const_int 0) | |
2133 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 2134 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 2135 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 2136 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 2137 | " |
bb68ff55 | 2138 | { |
a3170dc6 AH |
2139 | if (TARGET_ISEL) |
2140 | { | |
2141 | rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]); | |
2142 | DONE; | |
2143 | } | |
bb68ff55 MM |
2144 | operands[3] = gen_reg_rtx (SImode); |
2145 | operands[4] = gen_reg_rtx (SImode); | |
2146 | operands[5] = GEN_INT (-2147483647 - 1); | |
2147 | }") | |
1fd4e8c1 RK |
2148 | |
2149 | (define_insn "" | |
cd2b37d9 RK |
2150 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2151 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 2152 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
2153 | (const_int 0) |
2154 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 2155 | "TARGET_POWER" |
1fd4e8c1 RK |
2156 | "doz%I2 %0,%1,%2") |
2157 | ||
2158 | (define_insn "" | |
9ebbca7d | 2159 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2160 | (compare:CC |
9ebbca7d GK |
2161 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
2162 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
2163 | (const_int 0) |
2164 | (minus:SI (match_dup 2) (match_dup 1))) | |
2165 | (const_int 0))) | |
9ebbca7d | 2166 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 2167 | "TARGET_POWER" |
9ebbca7d GK |
2168 | "@ |
2169 | doz%I2. %3,%1,%2 | |
2170 | #" | |
2171 | [(set_attr "type" "delayed_compare") | |
2172 | (set_attr "length" "4,8")]) | |
2173 | ||
2174 | (define_split | |
2175 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2176 | (compare:CC | |
2177 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
2178 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
2179 | (const_int 0) | |
2180 | (minus:SI (match_dup 2) (match_dup 1))) | |
2181 | (const_int 0))) | |
2182 | (clobber (match_scratch:SI 3 ""))] | |
2183 | "TARGET_POWER && reload_completed" | |
2184 | [(set (match_dup 3) | |
2185 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
2186 | (const_int 0) | |
2187 | (minus:SI (match_dup 2) (match_dup 1)))) | |
2188 | (set (match_dup 0) | |
2189 | (compare:CC (match_dup 3) | |
2190 | (const_int 0)))] | |
2191 | "") | |
1fd4e8c1 RK |
2192 | |
2193 | (define_insn "" | |
9ebbca7d | 2194 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2195 | (compare:CC |
9ebbca7d GK |
2196 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
2197 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
2198 | (const_int 0) |
2199 | (minus:SI (match_dup 2) (match_dup 1))) | |
2200 | (const_int 0))) | |
9ebbca7d | 2201 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
2202 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
2203 | (const_int 0) | |
2204 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 2205 | "TARGET_POWER" |
9ebbca7d GK |
2206 | "@ |
2207 | doz%I2. %0,%1,%2 | |
2208 | #" | |
2209 | [(set_attr "type" "delayed_compare") | |
2210 | (set_attr "length" "4,8")]) | |
2211 | ||
2212 | (define_split | |
2213 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2214 | (compare:CC | |
2215 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
2216 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
2217 | (const_int 0) | |
2218 | (minus:SI (match_dup 2) (match_dup 1))) | |
2219 | (const_int 0))) | |
2220 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2221 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
2222 | (const_int 0) | |
2223 | (minus:SI (match_dup 2) (match_dup 1))))] | |
2224 | "TARGET_POWER && reload_completed" | |
2225 | [(set (match_dup 0) | |
2226 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
2227 | (const_int 0) | |
2228 | (minus:SI (match_dup 2) (match_dup 1)))) | |
2229 | (set (match_dup 3) | |
2230 | (compare:CC (match_dup 0) | |
2231 | (const_int 0)))] | |
2232 | "") | |
1fd4e8c1 RK |
2233 | |
2234 | ;; We don't need abs with condition code because such comparisons should | |
2235 | ;; never be done. | |
ea9be077 MM |
2236 | (define_expand "abssi2" |
2237 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2238 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
2239 | "" | |
2240 | " | |
2241 | { | |
a3170dc6 AH |
2242 | if (TARGET_ISEL) |
2243 | { | |
2244 | emit_insn (gen_abssi2_isel (operands[0], operands[1])); | |
2245 | DONE; | |
2246 | } | |
2247 | else if (! TARGET_POWER) | |
ea9be077 MM |
2248 | { |
2249 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
2250 | DONE; | |
2251 | } | |
2252 | }") | |
2253 | ||
ea112fc4 | 2254 | (define_insn "*abssi2_power" |
cd2b37d9 RK |
2255 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2256 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 2257 | "TARGET_POWER" |
1fd4e8c1 RK |
2258 | "abs %0,%1") |
2259 | ||
a3170dc6 AH |
2260 | (define_insn_and_split "abssi2_isel" |
2261 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2262 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
2263 | (clobber (match_scratch:SI 2 "=b")) | |
2264 | (clobber (match_scratch:CC 3 "=y"))] | |
2265 | "TARGET_ISEL" | |
2266 | "#" | |
2267 | "&& reload_completed" | |
2268 | [(set (match_dup 2) (neg:SI (match_dup 1))) | |
2269 | (set (match_dup 3) | |
2270 | (compare:CC (match_dup 1) | |
2271 | (const_int 0))) | |
2272 | (set (match_dup 0) | |
2273 | (if_then_else:SI (ge (match_dup 3) | |
2274 | (const_int 0)) | |
2275 | (match_dup 1) | |
2276 | (match_dup 2)))] | |
2277 | "") | |
2278 | ||
ea112fc4 | 2279 | (define_insn_and_split "abssi2_nopower" |
ea9be077 | 2280 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 2281 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) |
ea9be077 | 2282 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
a3170dc6 | 2283 | "! TARGET_POWER && ! TARGET_ISEL" |
ea112fc4 DE |
2284 | "#" |
2285 | "&& reload_completed" | |
ea9be077 MM |
2286 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
2287 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 2288 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
2289 | "") |
2290 | ||
463b558b | 2291 | (define_insn "*nabs_power" |
cd2b37d9 RK |
2292 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2293 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 2294 | "TARGET_POWER" |
1fd4e8c1 RK |
2295 | "nabs %0,%1") |
2296 | ||
ea112fc4 | 2297 | (define_insn_and_split "*nabs_nopower" |
ea9be077 | 2298 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 2299 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) |
ea9be077 | 2300 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
0ad91047 | 2301 | "! TARGET_POWER" |
ea112fc4 DE |
2302 | "#" |
2303 | "&& reload_completed" | |
ea9be077 MM |
2304 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
2305 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 2306 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
2307 | "") |
2308 | ||
1fd4e8c1 | 2309 | (define_insn "negsi2" |
cd2b37d9 RK |
2310 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2311 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
2312 | "" |
2313 | "neg %0,%1") | |
2314 | ||
2315 | (define_insn "" | |
9ebbca7d GK |
2316 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2317 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2318 | (const_int 0))) |
9ebbca7d | 2319 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 2320 | "! TARGET_POWERPC64" |
9ebbca7d GK |
2321 | "@ |
2322 | neg. %2,%1 | |
2323 | #" | |
2324 | [(set_attr "type" "compare") | |
2325 | (set_attr "length" "4,8")]) | |
2326 | ||
2327 | (define_split | |
2328 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2329 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2330 | (const_int 0))) | |
2331 | (clobber (match_scratch:SI 2 ""))] | |
2332 | "! TARGET_POWERPC64 && reload_completed" | |
2333 | [(set (match_dup 2) | |
2334 | (neg:SI (match_dup 1))) | |
2335 | (set (match_dup 0) | |
2336 | (compare:CC (match_dup 2) | |
2337 | (const_int 0)))] | |
2338 | "") | |
1fd4e8c1 RK |
2339 | |
2340 | (define_insn "" | |
9ebbca7d GK |
2341 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
2342 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2343 | (const_int 0))) |
9ebbca7d | 2344 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 2345 | (neg:SI (match_dup 1)))] |
0ad91047 | 2346 | "! TARGET_POWERPC64" |
9ebbca7d GK |
2347 | "@ |
2348 | neg. %0,%1 | |
2349 | #" | |
2350 | [(set_attr "type" "compare") | |
2351 | (set_attr "length" "4,8")]) | |
2352 | ||
2353 | (define_split | |
2354 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
2355 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2356 | (const_int 0))) | |
2357 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2358 | (neg:SI (match_dup 1)))] | |
2359 | "! TARGET_POWERPC64 && reload_completed" | |
2360 | [(set (match_dup 0) | |
2361 | (neg:SI (match_dup 1))) | |
2362 | (set (match_dup 2) | |
2363 | (compare:CC (match_dup 0) | |
2364 | (const_int 0)))] | |
2365 | "") | |
1fd4e8c1 | 2366 | |
1b1edcfa DE |
2367 | (define_insn "clzsi2" |
2368 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2369 | (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
2370 | "" | |
2371 | "{cntlz|cntlzw} %0,%1") | |
2372 | ||
2373 | (define_expand "ctzsi2" | |
4977bab6 | 2374 | [(set (match_dup 2) |
1b1edcfa | 2375 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
4977bab6 | 2376 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) |
1b1edcfa DE |
2377 | (match_dup 2))) |
2378 | (clobber (scratch:CC))]) | |
d865b122 | 2379 | (set (match_dup 4) (clz:SI (match_dup 3))) |
4977bab6 | 2380 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 2381 | (minus:SI (const_int 31) (match_dup 4)))] |
1fd4e8c1 | 2382 | "" |
4977bab6 ZW |
2383 | { |
2384 | operands[2] = gen_reg_rtx (SImode); | |
2385 | operands[3] = gen_reg_rtx (SImode); | |
2386 | operands[4] = gen_reg_rtx (SImode); | |
2387 | }) | |
2388 | ||
1b1edcfa DE |
2389 | (define_expand "ffssi2" |
2390 | [(set (match_dup 2) | |
2391 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
2392 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) | |
2393 | (match_dup 2))) | |
2394 | (clobber (scratch:CC))]) | |
2395 | (set (match_dup 4) (clz:SI (match_dup 3))) | |
2396 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2397 | (minus:SI (const_int 32) (match_dup 4)))] | |
4977bab6 | 2398 | "" |
1b1edcfa DE |
2399 | { |
2400 | operands[2] = gen_reg_rtx (SImode); | |
2401 | operands[3] = gen_reg_rtx (SImode); | |
2402 | operands[4] = gen_reg_rtx (SImode); | |
2403 | }) | |
2404 | ||
ca7f5001 RK |
2405 | (define_expand "mulsi3" |
2406 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
2407 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
2408 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
2409 | "" | |
2410 | " | |
2411 | { | |
2412 | if (TARGET_POWER) | |
68b40e7e | 2413 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 2414 | else |
68b40e7e | 2415 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
2416 | DONE; |
2417 | }") | |
2418 | ||
68b40e7e | 2419 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
2420 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2421 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
2422 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
2423 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
2424 | "TARGET_POWER" |
2425 | "@ | |
2426 | {muls|mullw} %0,%1,%2 | |
2427 | {muli|mulli} %0,%1,%2" | |
c859cda6 DJ |
2428 | [(set (attr "type") |
2429 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") | |
2430 | (const_string "imul3") | |
2431 | (match_operand:SI 2 "short_cint_operand" "") | |
2432 | (const_string "imul2")] | |
2433 | (const_string "imul")))]) | |
ca7f5001 | 2434 | |
68b40e7e | 2435 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
2436 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2437 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2438 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 2439 | "! TARGET_POWER" |
1fd4e8c1 | 2440 | "@ |
d904e9ed RK |
2441 | {muls|mullw} %0,%1,%2 |
2442 | {muli|mulli} %0,%1,%2" | |
c859cda6 DJ |
2443 | [(set (attr "type") |
2444 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") | |
2445 | (const_string "imul3") | |
2446 | (match_operand:SI 2 "short_cint_operand" "") | |
2447 | (const_string "imul2")] | |
2448 | (const_string "imul")))]) | |
1fd4e8c1 RK |
2449 | |
2450 | (define_insn "" | |
9ebbca7d GK |
2451 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2452 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2453 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2454 | (const_int 0))) |
9ebbca7d GK |
2455 | (clobber (match_scratch:SI 3 "=r,r")) |
2456 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 2457 | "TARGET_POWER" |
9ebbca7d GK |
2458 | "@ |
2459 | {muls.|mullw.} %3,%1,%2 | |
2460 | #" | |
2461 | [(set_attr "type" "delayed_compare") | |
2462 | (set_attr "length" "4,8")]) | |
2463 | ||
2464 | (define_split | |
2465 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2466 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2467 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2468 | (const_int 0))) | |
2469 | (clobber (match_scratch:SI 3 "")) | |
2470 | (clobber (match_scratch:SI 4 ""))] | |
2471 | "TARGET_POWER && reload_completed" | |
2472 | [(parallel [(set (match_dup 3) | |
2473 | (mult:SI (match_dup 1) (match_dup 2))) | |
2474 | (clobber (match_dup 4))]) | |
2475 | (set (match_dup 0) | |
2476 | (compare:CC (match_dup 3) | |
2477 | (const_int 0)))] | |
2478 | "") | |
ca7f5001 RK |
2479 | |
2480 | (define_insn "" | |
9ebbca7d GK |
2481 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2482 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2483 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2484 | (const_int 0))) |
9ebbca7d | 2485 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 2486 | "! TARGET_POWER" |
9ebbca7d GK |
2487 | "@ |
2488 | {muls.|mullw.} %3,%1,%2 | |
2489 | #" | |
2490 | [(set_attr "type" "delayed_compare") | |
2491 | (set_attr "length" "4,8")]) | |
2492 | ||
2493 | (define_split | |
2494 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2495 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2496 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2497 | (const_int 0))) | |
2498 | (clobber (match_scratch:SI 3 ""))] | |
2499 | "! TARGET_POWER && reload_completed" | |
2500 | [(set (match_dup 3) | |
2501 | (mult:SI (match_dup 1) (match_dup 2))) | |
2502 | (set (match_dup 0) | |
2503 | (compare:CC (match_dup 3) | |
2504 | (const_int 0)))] | |
2505 | "") | |
1fd4e8c1 RK |
2506 | |
2507 | (define_insn "" | |
9ebbca7d GK |
2508 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2509 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2510 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2511 | (const_int 0))) |
9ebbca7d | 2512 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2513 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 2514 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 2515 | "TARGET_POWER" |
9ebbca7d GK |
2516 | "@ |
2517 | {muls.|mullw.} %0,%1,%2 | |
2518 | #" | |
2519 | [(set_attr "type" "delayed_compare") | |
2520 | (set_attr "length" "4,8")]) | |
2521 | ||
2522 | (define_split | |
2523 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2524 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2525 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2526 | (const_int 0))) | |
2527 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2528 | (mult:SI (match_dup 1) (match_dup 2))) | |
2529 | (clobber (match_scratch:SI 4 ""))] | |
2530 | "TARGET_POWER && reload_completed" | |
2531 | [(parallel [(set (match_dup 0) | |
2532 | (mult:SI (match_dup 1) (match_dup 2))) | |
2533 | (clobber (match_dup 4))]) | |
2534 | (set (match_dup 3) | |
2535 | (compare:CC (match_dup 0) | |
2536 | (const_int 0)))] | |
2537 | "") | |
ca7f5001 RK |
2538 | |
2539 | (define_insn "" | |
9ebbca7d GK |
2540 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2541 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2542 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2543 | (const_int 0))) |
9ebbca7d | 2544 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 2545 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 2546 | "! TARGET_POWER" |
9ebbca7d GK |
2547 | "@ |
2548 | {muls.|mullw.} %0,%1,%2 | |
2549 | #" | |
2550 | [(set_attr "type" "delayed_compare") | |
2551 | (set_attr "length" "4,8")]) | |
2552 | ||
2553 | (define_split | |
2554 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2555 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2556 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2557 | (const_int 0))) | |
2558 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2559 | (mult:SI (match_dup 1) (match_dup 2)))] | |
2560 | "! TARGET_POWER && reload_completed" | |
2561 | [(set (match_dup 0) | |
2562 | (mult:SI (match_dup 1) (match_dup 2))) | |
2563 | (set (match_dup 3) | |
2564 | (compare:CC (match_dup 0) | |
2565 | (const_int 0)))] | |
2566 | "") | |
1fd4e8c1 RK |
2567 | |
2568 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
2569 | ;; 0 and remainder to operand 3. | |
2570 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
2571 | ||
8ffd9c51 RK |
2572 | (define_expand "divmodsi4" |
2573 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2574 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2575 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
bb157ff4 | 2576 | (set (match_operand:SI 3 "register_operand" "") |
8ffd9c51 RK |
2577 | (mod:SI (match_dup 1) (match_dup 2)))])] |
2578 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2579 | " | |
2580 | { | |
2581 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2582 | { | |
39403d82 DE |
2583 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2584 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2585 | emit_insn (gen_divss_call ()); |
39403d82 DE |
2586 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2587 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
2588 | DONE; |
2589 | } | |
2590 | }") | |
deb9225a | 2591 | |
bb157ff4 | 2592 | (define_insn "*divmodsi4_internal" |
cd2b37d9 RK |
2593 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2594 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2595 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
bb157ff4 | 2596 | (set (match_operand:SI 3 "register_operand" "=q") |
1fd4e8c1 | 2597 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 2598 | "TARGET_POWER" |
cfb557c4 RK |
2599 | "divs %0,%1,%2" |
2600 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 2601 | |
8ffd9c51 RK |
2602 | (define_expand "udivsi3" |
2603 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2604 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2605 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
2606 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2607 | " | |
2608 | { | |
2609 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2610 | { | |
39403d82 DE |
2611 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2612 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2613 | emit_insn (gen_quous_call ()); |
39403d82 | 2614 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2615 | DONE; |
2616 | } | |
f192bf8b DE |
2617 | else if (TARGET_POWER) |
2618 | { | |
2619 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
2620 | DONE; | |
2621 | } | |
8ffd9c51 | 2622 | }") |
deb9225a | 2623 | |
f192bf8b DE |
2624 | (define_insn "udivsi3_mq" |
2625 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2626 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2627 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2628 | (clobber (match_scratch:SI 3 "=q"))] | |
2629 | "TARGET_POWERPC && TARGET_POWER" | |
2630 | "divwu %0,%1,%2" | |
2631 | [(set_attr "type" "idiv")]) | |
2632 | ||
2633 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
2634 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2635 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2636 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 2637 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 2638 | "divwu %0,%1,%2" |
ca7f5001 RK |
2639 | [(set_attr "type" "idiv")]) |
2640 | ||
1fd4e8c1 | 2641 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 2642 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
2643 | ;; used; for PowerPC, force operands into register and do a normal divide; |
2644 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 2645 | (define_expand "divsi3" |
cd2b37d9 RK |
2646 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2647 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
2648 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
2649 | "" | |
2650 | " | |
2651 | { | |
ca7f5001 | 2652 | if (GET_CODE (operands[2]) == CONST_INT |
2bfcf297 | 2653 | && INTVAL (operands[2]) > 0 |
ca7f5001 RK |
2654 | && exact_log2 (INTVAL (operands[2])) >= 0) |
2655 | ; | |
b6c9286a | 2656 | else if (TARGET_POWERPC) |
f192bf8b DE |
2657 | { |
2658 | operands[2] = force_reg (SImode, operands[2]); | |
2659 | if (TARGET_POWER) | |
2660 | { | |
2661 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
2662 | DONE; | |
2663 | } | |
2664 | } | |
b6c9286a | 2665 | else if (TARGET_POWER) |
1fd4e8c1 | 2666 | FAIL; |
405c5495 | 2667 | else |
8ffd9c51 | 2668 | { |
39403d82 DE |
2669 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2670 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2671 | emit_insn (gen_quoss_call ()); |
39403d82 | 2672 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2673 | DONE; |
2674 | } | |
1fd4e8c1 RK |
2675 | }") |
2676 | ||
f192bf8b DE |
2677 | (define_insn "divsi3_mq" |
2678 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2679 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2680 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2681 | (clobber (match_scratch:SI 3 "=q"))] | |
2682 | "TARGET_POWERPC && TARGET_POWER" | |
2683 | "divw %0,%1,%2" | |
2684 | [(set_attr "type" "idiv")]) | |
2685 | ||
2686 | (define_insn "*divsi3_no_mq" | |
2687 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2688 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2689 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
2690 | "TARGET_POWERPC && ! TARGET_POWER" | |
2691 | "divw %0,%1,%2" | |
2692 | [(set_attr "type" "idiv")]) | |
2693 | ||
1fd4e8c1 | 2694 | (define_expand "modsi3" |
85644414 RK |
2695 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
2696 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 2697 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 2698 | "" |
1fd4e8c1 RK |
2699 | " |
2700 | { | |
481c7efa | 2701 | int i; |
39b52ba2 RK |
2702 | rtx temp1; |
2703 | rtx temp2; | |
2704 | ||
2bfcf297 | 2705 | if (GET_CODE (operands[2]) != CONST_INT |
a65c591c | 2706 | || INTVAL (operands[2]) <= 0 |
2bfcf297 | 2707 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) |
39b52ba2 RK |
2708 | FAIL; |
2709 | ||
2710 | temp1 = gen_reg_rtx (SImode); | |
2711 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 2712 | |
85644414 | 2713 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 2714 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
2715 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
2716 | DONE; | |
1fd4e8c1 RK |
2717 | }") |
2718 | ||
2719 | (define_insn "" | |
cd2b37d9 RK |
2720 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2721 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
2722 | (match_operand:SI 2 "exact_log2_cint_operand" "N")))] |
2723 | "" | |
ca7f5001 | 2724 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 2725 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
2726 | |
2727 | (define_insn "" | |
9ebbca7d GK |
2728 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2729 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2730 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2731 | (const_int 0))) |
9ebbca7d | 2732 | (clobber (match_scratch:SI 3 "=r,r"))] |
2bfcf297 | 2733 | "" |
9ebbca7d GK |
2734 | "@ |
2735 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
2736 | #" | |
b19003d8 | 2737 | [(set_attr "type" "compare") |
9ebbca7d GK |
2738 | (set_attr "length" "8,12")]) |
2739 | ||
2740 | (define_split | |
2741 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2742 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2743 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2744 | (const_int 0))) |
2745 | (clobber (match_scratch:SI 3 ""))] | |
2bfcf297 | 2746 | "reload_completed" |
9ebbca7d GK |
2747 | [(set (match_dup 3) |
2748 | (div:SI (match_dup 1) (match_dup 2))) | |
2749 | (set (match_dup 0) | |
2750 | (compare:CC (match_dup 3) | |
2751 | (const_int 0)))] | |
2752 | "") | |
1fd4e8c1 RK |
2753 | |
2754 | (define_insn "" | |
9ebbca7d GK |
2755 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2756 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2757 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2758 | (const_int 0))) |
9ebbca7d | 2759 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2760 | (div:SI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 2761 | "" |
9ebbca7d GK |
2762 | "@ |
2763 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2764 | #" | |
b19003d8 | 2765 | [(set_attr "type" "compare") |
9ebbca7d GK |
2766 | (set_attr "length" "8,12")]) |
2767 | ||
2768 | (define_split | |
2769 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2770 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2771 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2772 | (const_int 0))) |
2773 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2774 | (div:SI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2775 | "reload_completed" |
9ebbca7d GK |
2776 | [(set (match_dup 0) |
2777 | (div:SI (match_dup 1) (match_dup 2))) | |
2778 | (set (match_dup 3) | |
2779 | (compare:CC (match_dup 0) | |
2780 | (const_int 0)))] | |
2781 | "") | |
1fd4e8c1 RK |
2782 | |
2783 | (define_insn "" | |
cd2b37d9 | 2784 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2785 | (udiv:SI |
996a5f59 | 2786 | (plus:DI (ashift:DI |
cd2b37d9 | 2787 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2788 | (const_int 32)) |
23a900dc | 2789 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2790 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2791 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2792 | (umod:SI |
996a5f59 | 2793 | (plus:DI (ashift:DI |
1fd4e8c1 | 2794 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2795 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2796 | (match_dup 3)))] |
ca7f5001 | 2797 | "TARGET_POWER" |
cfb557c4 RK |
2798 | "div %0,%1,%3" |
2799 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2800 | |
2801 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2802 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2803 | ;; have to worry about the branches. So make a few subroutines here. | |
2804 | ;; | |
2805 | ;; First comes the normal case. | |
2806 | (define_expand "udivmodsi4_normal" | |
2807 | [(set (match_dup 4) (const_int 0)) | |
2808 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2809 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2810 | (const_int 32)) |
2811 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2812 | (match_operand:SI 2 "" ""))) | |
2813 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2814 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2815 | (const_int 32)) |
2816 | (zero_extend:DI (match_dup 1))) | |
2817 | (match_dup 2)))])] | |
ca7f5001 | 2818 | "TARGET_POWER" |
1fd4e8c1 RK |
2819 | " |
2820 | { operands[4] = gen_reg_rtx (SImode); }") | |
2821 | ||
2822 | ;; This handles the branches. | |
2823 | (define_expand "udivmodsi4_tests" | |
2824 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2825 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2826 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2827 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2828 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2829 | (set (match_dup 0) (const_int 1)) | |
2830 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2831 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2832 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2833 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2834 | "TARGET_POWER" |
1fd4e8c1 RK |
2835 | " |
2836 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2837 | operands[6] = gen_reg_rtx (CCmode); | |
2838 | }") | |
2839 | ||
2840 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2841 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2842 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2843 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2844 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2845 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2846 | "" |
1fd4e8c1 RK |
2847 | " |
2848 | { | |
2849 | rtx label = 0; | |
2850 | ||
8ffd9c51 | 2851 | if (! TARGET_POWER) |
c4d38ccb MM |
2852 | { |
2853 | if (! TARGET_POWERPC) | |
2854 | { | |
39403d82 DE |
2855 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2856 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2857 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2858 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2859 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2860 | DONE; |
2861 | } | |
2862 | else | |
2863 | FAIL; | |
2864 | } | |
0081a354 | 2865 | |
1fd4e8c1 RK |
2866 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2867 | { | |
2868 | operands[2] = force_reg (SImode, operands[2]); | |
2869 | label = gen_label_rtx (); | |
2870 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2871 | operands[3], label)); | |
2872 | } | |
2873 | else | |
2874 | operands[2] = force_reg (SImode, operands[2]); | |
2875 | ||
2876 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2877 | operands[3])); | |
2878 | if (label) | |
2879 | emit_label (label); | |
2880 | ||
2881 | DONE; | |
2882 | }") | |
0081a354 | 2883 | |
fada905b MM |
2884 | ;; AIX architecture-independent common-mode multiply (DImode), |
2885 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2886 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2887 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2888 | ;; assumed unused if generating common-mode, so ignore. | |
2889 | (define_insn "mulh_call" | |
2890 | [(set (reg:SI 3) | |
2891 | (truncate:SI | |
2892 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2893 | (sign_extend:DI (reg:SI 4))) | |
2894 | (const_int 32)))) | |
cf27b467 | 2895 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2896 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2897 | "bla __mulh" |
2898 | [(set_attr "type" "imul")]) | |
fada905b MM |
2899 | |
2900 | (define_insn "mull_call" | |
2901 | [(set (reg:DI 3) | |
2902 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2903 | (sign_extend:DI (reg:SI 4)))) | |
2904 | (clobber (match_scratch:SI 0 "=l")) | |
2905 | (clobber (reg:SI 0))] | |
2906 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2907 | "bla __mull" |
2908 | [(set_attr "type" "imul")]) | |
fada905b MM |
2909 | |
2910 | (define_insn "divss_call" | |
2911 | [(set (reg:SI 3) | |
2912 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2913 | (set (reg:SI 4) | |
2914 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2915 | (clobber (match_scratch:SI 0 "=l")) | |
2916 | (clobber (reg:SI 0))] | |
2917 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2918 | "bla __divss" |
2919 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2920 | |
2921 | (define_insn "divus_call" | |
8ffd9c51 RK |
2922 | [(set (reg:SI 3) |
2923 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2924 | (set (reg:SI 4) | |
2925 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2926 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2927 | (clobber (reg:SI 0)) |
2928 | (clobber (match_scratch:CC 1 "=x")) | |
2929 | (clobber (reg:CC 69))] | |
2930 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2931 | "bla __divus" |
2932 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2933 | |
2934 | (define_insn "quoss_call" | |
2935 | [(set (reg:SI 3) | |
2936 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2937 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2938 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2939 | "bla __quoss" |
2940 | [(set_attr "type" "idiv")]) | |
0081a354 | 2941 | |
fada905b MM |
2942 | (define_insn "quous_call" |
2943 | [(set (reg:SI 3) | |
2944 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2945 | (clobber (match_scratch:SI 0 "=l")) | |
2946 | (clobber (reg:SI 0)) | |
2947 | (clobber (match_scratch:CC 1 "=x")) | |
2948 | (clobber (reg:CC 69))] | |
2949 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2950 | "bla __quous" |
2951 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2952 | \f |
bb21487f | 2953 | ;; Logical instructions |
dfbdccdb GK |
2954 | ;; The logical instructions are mostly combined by using match_operator, |
2955 | ;; but the plain AND insns are somewhat different because there is no | |
2956 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2957 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2958 | ||
29ae5b89 JL |
2959 | (define_insn "andsi3" |
2960 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2961 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2962 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2963 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2964 | "" |
2965 | "@ | |
2966 | and %0,%1,%2 | |
ca7f5001 RK |
2967 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2968 | {andil.|andi.} %0,%1,%b2 | |
9ebbca7d | 2969 | {andiu.|andis.} %0,%1,%u2") |
52d3af72 DE |
2970 | |
2971 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
0ba1b2ff | 2972 | ;; the test again -- this avoids a mfcr which on the higher end |
52d3af72 | 2973 | ;; machines causes an execution serialization |
1fd4e8c1 | 2974 | |
7cd5235b | 2975 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2976 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2977 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2978 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2979 | (const_int 0))) |
52d3af72 DE |
2980 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2981 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2982 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2983 | "@ |
2984 | and. %3,%1,%2 | |
ca7f5001 RK |
2985 | {andil.|andi.} %3,%1,%b2 |
2986 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2987 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2988 | # | |
2989 | # | |
2990 | # | |
2991 | #" | |
2992 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2993 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2994 | |
0ba1b2ff AM |
2995 | (define_insn "*andsi3_internal3" |
2996 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2997 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2998 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2999 | (const_int 0))) | |
3000 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) | |
3001 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
3002 | "TARGET_POWERPC64" | |
3003 | "@ | |
3004 | # | |
3005 | {andil.|andi.} %3,%1,%b2 | |
3006 | {andiu.|andis.} %3,%1,%u2 | |
3007 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 | |
3008 | # | |
3009 | # | |
3010 | # | |
3011 | #" | |
3012 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
3013 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
3014 | ||
52d3af72 DE |
3015 | (define_split |
3016 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3017 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3018 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 3019 | (const_int 0))) |
52d3af72 DE |
3020 | (clobber (match_scratch:SI 3 "")) |
3021 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 3022 | "reload_completed" |
52d3af72 DE |
3023 | [(parallel [(set (match_dup 3) |
3024 | (and:SI (match_dup 1) | |
3025 | (match_dup 2))) | |
3026 | (clobber (match_dup 4))]) | |
3027 | (set (match_dup 0) | |
3028 | (compare:CC (match_dup 3) | |
3029 | (const_int 0)))] | |
3030 | "") | |
3031 | ||
0ba1b2ff AM |
3032 | ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the |
3033 | ;; whole 64 bit reg, and we don't know what is in the high 32 bits. | |
3034 | ||
3035 | (define_split | |
3036 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
3037 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3038 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
3039 | (const_int 0))) | |
3040 | (clobber (match_scratch:SI 3 "")) | |
3041 | (clobber (match_scratch:CC 4 ""))] | |
3042 | "TARGET_POWERPC64 && reload_completed" | |
3043 | [(parallel [(set (match_dup 3) | |
3044 | (and:SI (match_dup 1) | |
3045 | (match_dup 2))) | |
3046 | (clobber (match_dup 4))]) | |
3047 | (set (match_dup 0) | |
3048 | (compare:CC (match_dup 3) | |
3049 | (const_int 0)))] | |
3050 | "") | |
3051 | ||
3052 | (define_insn "*andsi3_internal4" | |
52d3af72 DE |
3053 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
3054 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 3055 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
3056 | (const_int 0))) |
3057 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
3058 | (and:SI (match_dup 1) | |
3059 | (match_dup 2))) | |
3060 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 3061 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
3062 | "@ |
3063 | and. %0,%1,%2 | |
ca7f5001 RK |
3064 | {andil.|andi.} %0,%1,%b2 |
3065 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
3066 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
3067 | # | |
3068 | # | |
3069 | # | |
3070 | #" | |
3071 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
3072 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
3073 | ||
0ba1b2ff AM |
3074 | (define_insn "*andsi3_internal5" |
3075 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
3076 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
3077 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
3078 | (const_int 0))) | |
3079 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
3080 | (and:SI (match_dup 1) | |
3081 | (match_dup 2))) | |
3082 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
3083 | "TARGET_POWERPC64" | |
3084 | "@ | |
3085 | # | |
3086 | {andil.|andi.} %0,%1,%b2 | |
3087 | {andiu.|andis.} %0,%1,%u2 | |
3088 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 | |
3089 | # | |
3090 | # | |
3091 | # | |
3092 | #" | |
3093 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
3094 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
3095 | ||
52d3af72 DE |
3096 | (define_split |
3097 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3098 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3099 | (match_operand:SI 2 "and_operand" "")) | |
3100 | (const_int 0))) | |
3101 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3102 | (and:SI (match_dup 1) | |
3103 | (match_dup 2))) | |
3104 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 3105 | "reload_completed" |
52d3af72 DE |
3106 | [(parallel [(set (match_dup 0) |
3107 | (and:SI (match_dup 1) | |
3108 | (match_dup 2))) | |
3109 | (clobber (match_dup 4))]) | |
3110 | (set (match_dup 3) | |
3111 | (compare:CC (match_dup 0) | |
3112 | (const_int 0)))] | |
3113 | "") | |
1fd4e8c1 | 3114 | |
0ba1b2ff AM |
3115 | (define_split |
3116 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
3117 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3118 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
3119 | (const_int 0))) | |
3120 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3121 | (and:SI (match_dup 1) | |
3122 | (match_dup 2))) | |
3123 | (clobber (match_scratch:CC 4 ""))] | |
3124 | "TARGET_POWERPC64 && reload_completed" | |
3125 | [(parallel [(set (match_dup 0) | |
3126 | (and:SI (match_dup 1) | |
3127 | (match_dup 2))) | |
3128 | (clobber (match_dup 4))]) | |
3129 | (set (match_dup 3) | |
3130 | (compare:CC (match_dup 0) | |
3131 | (const_int 0)))] | |
3132 | "") | |
3133 | ||
3134 | ;; Handle the PowerPC64 rlwinm corner case | |
3135 | ||
3136 | (define_insn_and_split "*andsi3_internal6" | |
3137 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3138 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3139 | (match_operand:SI 2 "mask_operand_wrap" "i")))] | |
3140 | "TARGET_POWERPC64" | |
3141 | "#" | |
3142 | "TARGET_POWERPC64" | |
3143 | [(set (match_dup 0) | |
3144 | (and:SI (rotate:SI (match_dup 1) (match_dup 3)) | |
3145 | (match_dup 4))) | |
3146 | (set (match_dup 0) | |
3147 | (rotate:SI (match_dup 0) (match_dup 5)))] | |
3148 | " | |
3149 | { | |
3150 | int mb = extract_MB (operands[2]); | |
3151 | int me = extract_ME (operands[2]); | |
3152 | operands[3] = GEN_INT (me + 1); | |
3153 | operands[5] = GEN_INT (32 - (me + 1)); | |
3154 | operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
3155 | }" | |
3156 | [(set_attr "length" "8")]) | |
3157 | ||
3158 | (define_insn_and_split "*andsi3_internal7" | |
3159 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") | |
3160 | (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r") | |
3161 | (match_operand:SI 1 "mask_operand_wrap" "i,i")) | |
3162 | (const_int 0))) | |
3163 | (clobber (match_scratch:SI 3 "=r,r"))] | |
3164 | "TARGET_POWERPC64" | |
3165 | "#" | |
3166 | "TARGET_POWERPC64" | |
3167 | [(parallel [(set (match_dup 2) | |
3168 | (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4)) | |
3169 | (match_dup 5)) | |
3170 | (const_int 0))) | |
3171 | (clobber (match_dup 3))])] | |
3172 | " | |
3173 | { | |
3174 | int mb = extract_MB (operands[1]); | |
3175 | int me = extract_ME (operands[1]); | |
3176 | operands[4] = GEN_INT (me + 1); | |
3177 | operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
3178 | }" | |
3179 | [(set_attr "type" "delayed_compare,compare") | |
3180 | (set_attr "length" "4,8")]) | |
3181 | ||
3182 | (define_insn_and_split "*andsi3_internal8" | |
3183 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y") | |
3184 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3185 | (match_operand:SI 2 "mask_operand_wrap" "i,i")) | |
3186 | (const_int 0))) | |
3187 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
3188 | (and:SI (match_dup 1) | |
3189 | (match_dup 2)))] | |
3190 | "TARGET_POWERPC64" | |
3191 | "#" | |
3192 | "TARGET_POWERPC64" | |
3193 | [(parallel [(set (match_dup 3) | |
3194 | (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4)) | |
3195 | (match_dup 5)) | |
3196 | (const_int 0))) | |
3197 | (set (match_dup 0) | |
3198 | (and:SI (rotate:SI (match_dup 1) (match_dup 4)) | |
3199 | (match_dup 5)))]) | |
3200 | (set (match_dup 0) | |
3201 | (rotate:SI (match_dup 0) (match_dup 6)))] | |
3202 | " | |
3203 | { | |
3204 | int mb = extract_MB (operands[2]); | |
3205 | int me = extract_ME (operands[2]); | |
3206 | operands[4] = GEN_INT (me + 1); | |
3207 | operands[6] = GEN_INT (32 - (me + 1)); | |
3208 | operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
3209 | }" | |
3210 | [(set_attr "type" "delayed_compare,compare") | |
3211 | (set_attr "length" "8,12")]) | |
3212 | ||
7cd5235b | 3213 | (define_expand "iorsi3" |
cd2b37d9 | 3214 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 3215 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 3216 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 3217 | "" |
f357808b RK |
3218 | " |
3219 | { | |
7cd5235b | 3220 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 3221 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
3222 | { |
3223 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 3224 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
3225 | ? operands[0] : gen_reg_rtx (SImode)); |
3226 | ||
a260abc9 DE |
3227 | emit_insn (gen_iorsi3 (tmp, operands[1], |
3228 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
3229 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
3230 | DONE; |
3231 | } | |
f357808b RK |
3232 | }") |
3233 | ||
7cd5235b | 3234 | (define_expand "xorsi3" |
cd2b37d9 | 3235 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 3236 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 3237 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 3238 | "" |
7cd5235b | 3239 | " |
1fd4e8c1 | 3240 | { |
7cd5235b | 3241 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 3242 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
3243 | { |
3244 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 3245 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
3246 | ? operands[0] : gen_reg_rtx (SImode)); |
3247 | ||
a260abc9 DE |
3248 | emit_insn (gen_xorsi3 (tmp, operands[1], |
3249 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
3250 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
3251 | DONE; |
3252 | } | |
1fd4e8c1 RK |
3253 | }") |
3254 | ||
dfbdccdb | 3255 | (define_insn "*boolsi3_internal1" |
7cd5235b | 3256 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 3257 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
3258 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
3259 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
3260 | "" |
3261 | "@ | |
dfbdccdb GK |
3262 | %q3 %0,%1,%2 |
3263 | {%q3il|%q3i} %0,%1,%b2 | |
3264 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 3265 | |
dfbdccdb | 3266 | (define_insn "*boolsi3_internal2" |
52d3af72 | 3267 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 3268 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
3269 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
3270 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
3271 | (const_int 0))) | |
52d3af72 | 3272 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3273 | "! TARGET_POWERPC64" |
52d3af72 | 3274 | "@ |
dfbdccdb | 3275 | %q4. %3,%1,%2 |
52d3af72 DE |
3276 | #" |
3277 | [(set_attr "type" "compare") | |
3278 | (set_attr "length" "4,8")]) | |
3279 | ||
3280 | (define_split | |
3281 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 3282 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3283 | [(match_operand:SI 1 "gpc_reg_operand" "") |
3284 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 3285 | (const_int 0))) |
52d3af72 | 3286 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 3287 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3288 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
3289 | (set (match_dup 0) |
3290 | (compare:CC (match_dup 3) | |
3291 | (const_int 0)))] | |
3292 | "") | |
815cdc52 | 3293 | |
dfbdccdb | 3294 | (define_insn "*boolsi3_internal3" |
52d3af72 | 3295 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
3296 | (compare:CC (match_operator:SI 4 "boolean_operator" |
3297 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
3298 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
3299 | (const_int 0))) | |
52d3af72 | 3300 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 3301 | (match_dup 4))] |
0ad91047 | 3302 | "! TARGET_POWERPC64" |
52d3af72 | 3303 | "@ |
dfbdccdb | 3304 | %q4. %0,%1,%2 |
52d3af72 DE |
3305 | #" |
3306 | [(set_attr "type" "compare") | |
3307 | (set_attr "length" "4,8")]) | |
3308 | ||
3309 | (define_split | |
e72247f4 | 3310 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 3311 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3312 | [(match_operand:SI 1 "gpc_reg_operand" "") |
3313 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 3314 | (const_int 0))) |
75540af0 | 3315 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 3316 | (match_dup 4))] |
0ad91047 | 3317 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3318 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
3319 | (set (match_dup 3) |
3320 | (compare:CC (match_dup 0) | |
3321 | (const_int 0)))] | |
3322 | "") | |
1fd4e8c1 | 3323 | |
5bdc5878 | 3324 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 3325 | ;; each of which does one 16-bit part. This is used by combine. |
a260abc9 DE |
3326 | |
3327 | (define_split | |
3328 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 3329 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
3330 | [(match_operand:SI 1 "gpc_reg_operand" "") |
3331 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 3332 | "" |
dfbdccdb GK |
3333 | [(set (match_dup 0) (match_dup 4)) |
3334 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
3335 | " |
3336 | { | |
dfbdccdb GK |
3337 | rtx i; |
3338 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
3339 | operands[4] = gen_rtx (GET_CODE (operands[3]), SImode, | |
3340 | operands[1], i); | |
3341 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
3342 | operands[5] = gen_rtx (GET_CODE (operands[3]), SImode, | |
3343 | operands[0], i); | |
a260abc9 DE |
3344 | }") |
3345 | ||
dfbdccdb | 3346 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 3347 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
3348 | (match_operator:SI 3 "boolean_operator" |
3349 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 3350 | (match_operand:SI 2 "gpc_reg_operand" "r")]))] |
1fd4e8c1 | 3351 | "" |
dfbdccdb | 3352 | "%q3 %0,%2,%1") |
1fd4e8c1 | 3353 | |
dfbdccdb | 3354 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 3355 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
3356 | (compare:CC (match_operator:SI 4 "boolean_operator" |
3357 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
3358 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
3359 | (const_int 0))) | |
52d3af72 | 3360 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3361 | "! TARGET_POWERPC64" |
52d3af72 | 3362 | "@ |
dfbdccdb | 3363 | %q4. %3,%2,%1 |
52d3af72 DE |
3364 | #" |
3365 | [(set_attr "type" "compare") | |
3366 | (set_attr "length" "4,8")]) | |
3367 | ||
3368 | (define_split | |
3369 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 3370 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3371 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
3372 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 3373 | (const_int 0))) |
52d3af72 | 3374 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 3375 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3376 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
3377 | (set (match_dup 0) |
3378 | (compare:CC (match_dup 3) | |
3379 | (const_int 0)))] | |
3380 | "") | |
1fd4e8c1 | 3381 | |
dfbdccdb | 3382 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 3383 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
3384 | (compare:CC (match_operator:SI 4 "boolean_operator" |
3385 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
3386 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
3387 | (const_int 0))) | |
52d3af72 | 3388 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 3389 | (match_dup 4))] |
0ad91047 | 3390 | "! TARGET_POWERPC64" |
52d3af72 | 3391 | "@ |
dfbdccdb | 3392 | %q4. %0,%2,%1 |
52d3af72 DE |
3393 | #" |
3394 | [(set_attr "type" "compare") | |
3395 | (set_attr "length" "4,8")]) | |
3396 | ||
3397 | (define_split | |
e72247f4 | 3398 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 3399 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3400 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
3401 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 3402 | (const_int 0))) |
75540af0 | 3403 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 3404 | (match_dup 4))] |
0ad91047 | 3405 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3406 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
3407 | (set (match_dup 3) |
3408 | (compare:CC (match_dup 0) | |
3409 | (const_int 0)))] | |
3410 | "") | |
3411 | ||
dfbdccdb | 3412 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 3413 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
3414 | (match_operator:SI 3 "boolean_operator" |
3415 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 3416 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] |
1fd4e8c1 | 3417 | "" |
dfbdccdb | 3418 | "%q3 %0,%1,%2") |
1fd4e8c1 | 3419 | |
dfbdccdb | 3420 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 3421 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
3422 | (compare:CC (match_operator:SI 4 "boolean_operator" |
3423 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
3424 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
3425 | (const_int 0))) | |
52d3af72 | 3426 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3427 | "! TARGET_POWERPC64" |
52d3af72 | 3428 | "@ |
dfbdccdb | 3429 | %q4. %3,%1,%2 |
52d3af72 DE |
3430 | #" |
3431 | [(set_attr "type" "compare") | |
3432 | (set_attr "length" "4,8")]) | |
3433 | ||
3434 | (define_split | |
3435 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 3436 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3437 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
3438 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 3439 | (const_int 0))) |
52d3af72 | 3440 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 3441 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3442 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
3443 | (set (match_dup 0) |
3444 | (compare:CC (match_dup 3) | |
3445 | (const_int 0)))] | |
3446 | "") | |
1fd4e8c1 | 3447 | |
dfbdccdb | 3448 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 3449 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
3450 | (compare:CC (match_operator:SI 4 "boolean_operator" |
3451 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
3452 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
3453 | (const_int 0))) | |
52d3af72 | 3454 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 3455 | (match_dup 4))] |
0ad91047 | 3456 | "! TARGET_POWERPC64" |
52d3af72 | 3457 | "@ |
dfbdccdb | 3458 | %q4. %0,%1,%2 |
52d3af72 DE |
3459 | #" |
3460 | [(set_attr "type" "compare") | |
3461 | (set_attr "length" "4,8")]) | |
3462 | ||
3463 | (define_split | |
e72247f4 | 3464 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 3465 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3466 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
3467 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 3468 | (const_int 0))) |
75540af0 | 3469 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 3470 | (match_dup 4))] |
0ad91047 | 3471 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3472 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
3473 | (set (match_dup 3) |
3474 | (compare:CC (match_dup 0) | |
3475 | (const_int 0)))] | |
3476 | "") | |
1fd4e8c1 RK |
3477 | |
3478 | ;; maskir insn. We need four forms because things might be in arbitrary | |
3479 | ;; orders. Don't define forms that only set CR fields because these | |
3480 | ;; would modify an input register. | |
3481 | ||
7cd5235b | 3482 | (define_insn "*maskir_internal1" |
cd2b37d9 | 3483 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
3484 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
3485 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
3486 | (and:SI (match_dup 2) | |
cd2b37d9 | 3487 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 3488 | "TARGET_POWER" |
01def764 | 3489 | "maskir %0,%3,%2") |
1fd4e8c1 | 3490 | |
7cd5235b | 3491 | (define_insn "*maskir_internal2" |
242e8072 | 3492 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
3493 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
3494 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 3495 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 3496 | (match_dup 2))))] |
ca7f5001 | 3497 | "TARGET_POWER" |
01def764 | 3498 | "maskir %0,%3,%2") |
1fd4e8c1 | 3499 | |
7cd5235b | 3500 | (define_insn "*maskir_internal3" |
cd2b37d9 | 3501 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 3502 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 3503 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
3504 | (and:SI (not:SI (match_dup 2)) |
3505 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 3506 | "TARGET_POWER" |
01def764 | 3507 | "maskir %0,%3,%2") |
1fd4e8c1 | 3508 | |
7cd5235b | 3509 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
3510 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3511 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
3512 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
3513 | (and:SI (not:SI (match_dup 2)) | |
3514 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 3515 | "TARGET_POWER" |
01def764 | 3516 | "maskir %0,%3,%2") |
1fd4e8c1 | 3517 | |
7cd5235b | 3518 | (define_insn "*maskir_internal5" |
9ebbca7d | 3519 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3520 | (compare:CC |
9ebbca7d GK |
3521 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
3522 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 3523 | (and:SI (match_dup 2) |
9ebbca7d | 3524 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 3525 | (const_int 0))) |
9ebbca7d | 3526 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3527 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
3528 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 3529 | "TARGET_POWER" |
9ebbca7d GK |
3530 | "@ |
3531 | maskir. %0,%3,%2 | |
3532 | #" | |
3533 | [(set_attr "type" "compare") | |
3534 | (set_attr "length" "4,8")]) | |
3535 | ||
3536 | (define_split | |
3537 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3538 | (compare:CC | |
3539 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
3540 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
3541 | (and:SI (match_dup 2) | |
3542 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
3543 | (const_int 0))) | |
3544 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3545 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3546 | (and:SI (match_dup 2) (match_dup 3))))] | |
3547 | "TARGET_POWER && reload_completed" | |
3548 | [(set (match_dup 0) | |
3549 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3550 | (and:SI (match_dup 2) (match_dup 3)))) | |
3551 | (set (match_dup 4) | |
3552 | (compare:CC (match_dup 0) | |
3553 | (const_int 0)))] | |
3554 | "") | |
1fd4e8c1 | 3555 | |
7cd5235b | 3556 | (define_insn "*maskir_internal6" |
9ebbca7d | 3557 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3558 | (compare:CC |
9ebbca7d GK |
3559 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
3560 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
3561 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 3562 | (match_dup 2))) |
1fd4e8c1 | 3563 | (const_int 0))) |
9ebbca7d | 3564 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3565 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
3566 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 3567 | "TARGET_POWER" |
9ebbca7d GK |
3568 | "@ |
3569 | maskir. %0,%3,%2 | |
3570 | #" | |
3571 | [(set_attr "type" "compare") | |
3572 | (set_attr "length" "4,8")]) | |
3573 | ||
3574 | (define_split | |
3575 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3576 | (compare:CC | |
3577 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
3578 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
3579 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3580 | (match_dup 2))) | |
3581 | (const_int 0))) | |
3582 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3583 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3584 | (and:SI (match_dup 3) (match_dup 2))))] | |
3585 | "TARGET_POWER && reload_completed" | |
3586 | [(set (match_dup 0) | |
3587 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3588 | (and:SI (match_dup 3) (match_dup 2)))) | |
3589 | (set (match_dup 4) | |
3590 | (compare:CC (match_dup 0) | |
3591 | (const_int 0)))] | |
3592 | "") | |
1fd4e8c1 | 3593 | |
7cd5235b | 3594 | (define_insn "*maskir_internal7" |
9ebbca7d | 3595 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 3596 | (compare:CC |
9ebbca7d GK |
3597 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
3598 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 3599 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3600 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 3601 | (const_int 0))) |
9ebbca7d | 3602 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
3603 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
3604 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3605 | "TARGET_POWER" | |
9ebbca7d GK |
3606 | "@ |
3607 | maskir. %0,%3,%2 | |
3608 | #" | |
3609 | [(set_attr "type" "compare") | |
3610 | (set_attr "length" "4,8")]) | |
3611 | ||
3612 | (define_split | |
3613 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3614 | (compare:CC | |
3615 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
3616 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
3617 | (and:SI (not:SI (match_dup 2)) | |
3618 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3619 | (const_int 0))) | |
3620 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3621 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3622 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3623 | "TARGET_POWER && reload_completed" | |
3624 | [(set (match_dup 0) | |
3625 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3626 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3627 | (set (match_dup 4) | |
3628 | (compare:CC (match_dup 0) | |
3629 | (const_int 0)))] | |
3630 | "") | |
1fd4e8c1 | 3631 | |
7cd5235b | 3632 | (define_insn "*maskir_internal8" |
9ebbca7d | 3633 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3634 | (compare:CC |
9ebbca7d GK |
3635 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
3636 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 3637 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3638 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 3639 | (const_int 0))) |
9ebbca7d | 3640 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3641 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
3642 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 3643 | "TARGET_POWER" |
9ebbca7d GK |
3644 | "@ |
3645 | maskir. %0,%3,%2 | |
3646 | #" | |
3647 | [(set_attr "type" "compare") | |
3648 | (set_attr "length" "4,8")]) | |
fcce224d | 3649 | |
9ebbca7d GK |
3650 | (define_split |
3651 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3652 | (compare:CC | |
3653 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3654 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
3655 | (and:SI (not:SI (match_dup 2)) | |
3656 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3657 | (const_int 0))) | |
3658 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3659 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3660 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3661 | "TARGET_POWER && reload_completed" | |
3662 | [(set (match_dup 0) | |
3663 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3664 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3665 | (set (match_dup 4) | |
3666 | (compare:CC (match_dup 0) | |
3667 | (const_int 0)))] | |
3668 | "") | |
fcce224d | 3669 | \f |
1fd4e8c1 RK |
3670 | ;; Rotate and shift insns, in all their variants. These support shifts, |
3671 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 3672 | (define_expand "insv" |
0ad91047 DE |
3673 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
3674 | (match_operand:SI 1 "const_int_operand" "") | |
3675 | (match_operand:SI 2 "const_int_operand" "")) | |
3676 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
3677 | "" |
3678 | " | |
3679 | { | |
3680 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3681 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3682 | compiler if the address of the structure is taken later. */ | |
3683 | if (GET_CODE (operands[0]) == SUBREG | |
3684 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3685 | FAIL; | |
a78e33fc DE |
3686 | |
3687 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
3688 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
3689 | else | |
3690 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
3691 | DONE; | |
034c1be0 MM |
3692 | }") |
3693 | ||
a78e33fc | 3694 | (define_insn "insvsi" |
cd2b37d9 | 3695 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
3696 | (match_operand:SI 1 "const_int_operand" "i") |
3697 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 3698 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
3699 | "" |
3700 | "* | |
3701 | { | |
3702 | int start = INTVAL (operands[2]) & 31; | |
3703 | int size = INTVAL (operands[1]) & 31; | |
3704 | ||
89e9f3a8 MM |
3705 | operands[4] = GEN_INT (32 - start - size); |
3706 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3707 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
1fd4e8c1 RK |
3708 | }") |
3709 | ||
a78e33fc | 3710 | (define_insn "*insvsi_internal1" |
d56d506a RK |
3711 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3712 | (match_operand:SI 1 "const_int_operand" "i") | |
3713 | (match_operand:SI 2 "const_int_operand" "i")) | |
3714 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3715 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3716 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3717 | "* |
3718 | { | |
3719 | int shift = INTVAL (operands[4]) & 31; | |
3720 | int start = INTVAL (operands[2]) & 31; | |
3721 | int size = INTVAL (operands[1]) & 31; | |
3722 | ||
89e9f3a8 MM |
3723 | operands[4] = GEN_INT (shift - start - size); |
3724 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3725 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3726 | }") |
3727 | ||
a78e33fc | 3728 | (define_insn "*insvsi_internal2" |
d56d506a RK |
3729 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3730 | (match_operand:SI 1 "const_int_operand" "i") | |
3731 | (match_operand:SI 2 "const_int_operand" "i")) | |
3732 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3733 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3734 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3735 | "* |
3736 | { | |
3737 | int shift = INTVAL (operands[4]) & 31; | |
3738 | int start = INTVAL (operands[2]) & 31; | |
3739 | int size = INTVAL (operands[1]) & 31; | |
3740 | ||
89e9f3a8 MM |
3741 | operands[4] = GEN_INT (32 - shift - start - size); |
3742 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3743 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3744 | }") |
3745 | ||
a78e33fc | 3746 | (define_insn "*insvsi_internal3" |
d56d506a RK |
3747 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3748 | (match_operand:SI 1 "const_int_operand" "i") | |
3749 | (match_operand:SI 2 "const_int_operand" "i")) | |
3750 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3751 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 3752 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3753 | "* |
3754 | { | |
3755 | int shift = INTVAL (operands[4]) & 31; | |
3756 | int start = INTVAL (operands[2]) & 31; | |
3757 | int size = INTVAL (operands[1]) & 31; | |
3758 | ||
89e9f3a8 MM |
3759 | operands[4] = GEN_INT (32 - shift - start - size); |
3760 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3761 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3762 | }") |
3763 | ||
a78e33fc | 3764 | (define_insn "*insvsi_internal4" |
d56d506a RK |
3765 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3766 | (match_operand:SI 1 "const_int_operand" "i") | |
3767 | (match_operand:SI 2 "const_int_operand" "i")) | |
3768 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3769 | (match_operand:SI 4 "const_int_operand" "i") | |
3770 | (match_operand:SI 5 "const_int_operand" "i")))] | |
3771 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
3772 | "* | |
3773 | { | |
3774 | int extract_start = INTVAL (operands[5]) & 31; | |
3775 | int extract_size = INTVAL (operands[4]) & 31; | |
3776 | int insert_start = INTVAL (operands[2]) & 31; | |
3777 | int insert_size = INTVAL (operands[1]) & 31; | |
3778 | ||
3779 | /* Align extract field with insert field */ | |
3a598fbe | 3780 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 3781 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 3782 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
d56d506a RK |
3783 | }") |
3784 | ||
a78e33fc | 3785 | (define_insn "insvdi" |
685f3906 | 3786 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3787 | (match_operand:SI 1 "const_int_operand" "i") |
3788 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3789 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3790 | "TARGET_POWERPC64" | |
3791 | "* | |
3792 | { | |
3793 | int start = INTVAL (operands[2]) & 63; | |
3794 | int size = INTVAL (operands[1]) & 63; | |
3795 | ||
a78e33fc DE |
3796 | operands[1] = GEN_INT (64 - start - size); |
3797 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3798 | }") |
3799 | ||
034c1be0 | 3800 | (define_expand "extzv" |
0ad91047 DE |
3801 | [(set (match_operand 0 "gpc_reg_operand" "") |
3802 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3803 | (match_operand:SI 2 "const_int_operand" "") | |
3804 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3805 | "" |
3806 | " | |
3807 | { | |
3808 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3809 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3810 | compiler if the address of the structure is taken later. */ | |
3811 | if (GET_CODE (operands[0]) == SUBREG | |
3812 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3813 | FAIL; | |
a78e33fc DE |
3814 | |
3815 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3816 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3817 | else | |
3818 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3819 | DONE; | |
034c1be0 MM |
3820 | }") |
3821 | ||
a78e33fc | 3822 | (define_insn "extzvsi" |
cd2b37d9 RK |
3823 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3824 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3825 | (match_operand:SI 2 "const_int_operand" "i") |
3826 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3827 | "" | |
3828 | "* | |
3829 | { | |
3830 | int start = INTVAL (operands[3]) & 31; | |
3831 | int size = INTVAL (operands[2]) & 31; | |
3832 | ||
3833 | if (start + size >= 32) | |
3834 | operands[3] = const0_rtx; | |
3835 | else | |
89e9f3a8 | 3836 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3837 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3838 | }") |
3839 | ||
a78e33fc | 3840 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3841 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3842 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3843 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3844 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3845 | (const_int 0))) |
9ebbca7d | 3846 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3847 | "" |
1fd4e8c1 RK |
3848 | "* |
3849 | { | |
3850 | int start = INTVAL (operands[3]) & 31; | |
3851 | int size = INTVAL (operands[2]) & 31; | |
3852 | ||
9ebbca7d GK |
3853 | /* Force split for non-cc0 compare. */ |
3854 | if (which_alternative == 1) | |
3855 | return \"#\"; | |
3856 | ||
43a88a8c | 3857 | /* If the bit-field being tested fits in the upper or lower half of a |
a7a975e1 RK |
3858 | word, it is possible to use andiu. or andil. to test it. This is |
3859 | useful because the condition register set-use delay is smaller for | |
3860 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3861 | position is 0 because the LT and GT bits may be set wrong. */ | |
3862 | ||
3863 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3864 | { |
3a598fbe | 3865 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3866 | - (1 << (16 - (start & 15) - size)))); |
3867 | if (start < 16) | |
ca7f5001 | 3868 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3869 | else |
ca7f5001 | 3870 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3871 | } |
7e69e155 | 3872 | |
1fd4e8c1 RK |
3873 | if (start + size >= 32) |
3874 | operands[3] = const0_rtx; | |
3875 | else | |
89e9f3a8 | 3876 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3877 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3878 | }" |
9ebbca7d GK |
3879 | [(set_attr "type" "compare") |
3880 | (set_attr "length" "4,8")]) | |
3881 | ||
3882 | (define_split | |
3883 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3884 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3885 | (match_operand:SI 2 "const_int_operand" "") | |
3886 | (match_operand:SI 3 "const_int_operand" "")) | |
3887 | (const_int 0))) | |
3888 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3889 | "reload_completed" |
9ebbca7d GK |
3890 | [(set (match_dup 4) |
3891 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3892 | (match_dup 3))) | |
3893 | (set (match_dup 0) | |
3894 | (compare:CC (match_dup 4) | |
3895 | (const_int 0)))] | |
3896 | "") | |
1fd4e8c1 | 3897 | |
a78e33fc | 3898 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3899 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3900 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3901 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3902 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3903 | (const_int 0))) |
9ebbca7d | 3904 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3905 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
ce71f754 | 3906 | "" |
1fd4e8c1 RK |
3907 | "* |
3908 | { | |
3909 | int start = INTVAL (operands[3]) & 31; | |
3910 | int size = INTVAL (operands[2]) & 31; | |
3911 | ||
9ebbca7d GK |
3912 | /* Force split for non-cc0 compare. */ |
3913 | if (which_alternative == 1) | |
3914 | return \"#\"; | |
3915 | ||
bc401279 | 3916 | /* Since we are using the output value, we can't ignore any need for |
43a88a8c | 3917 | a shift. The bit-field must end at the LSB. */ |
bc401279 | 3918 | if (start >= 16 && start + size == 32) |
df031c43 | 3919 | { |
bc401279 AM |
3920 | operands[3] = GEN_INT ((1 << size) - 1); |
3921 | return \"{andil.|andi.} %0,%1,%3\"; | |
df031c43 | 3922 | } |
7e69e155 | 3923 | |
1fd4e8c1 RK |
3924 | if (start + size >= 32) |
3925 | operands[3] = const0_rtx; | |
3926 | else | |
89e9f3a8 | 3927 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3928 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3929 | }" |
ce71f754 | 3930 | [(set_attr "type" "compare") |
9ebbca7d GK |
3931 | (set_attr "length" "4,8")]) |
3932 | ||
3933 | (define_split | |
3934 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3935 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3936 | (match_operand:SI 2 "const_int_operand" "") | |
3937 | (match_operand:SI 3 "const_int_operand" "")) | |
3938 | (const_int 0))) | |
3939 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3940 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
ce71f754 | 3941 | "reload_completed" |
9ebbca7d GK |
3942 | [(set (match_dup 0) |
3943 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3944 | (set (match_dup 4) | |
3945 | (compare:CC (match_dup 0) | |
3946 | (const_int 0)))] | |
3947 | "") | |
1fd4e8c1 | 3948 | |
a78e33fc | 3949 | (define_insn "extzvdi" |
685f3906 DE |
3950 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3951 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3952 | (match_operand:SI 2 "const_int_operand" "i") |
3953 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3954 | "TARGET_POWERPC64" |
3955 | "* | |
3956 | { | |
3957 | int start = INTVAL (operands[3]) & 63; | |
3958 | int size = INTVAL (operands[2]) & 63; | |
3959 | ||
3960 | if (start + size >= 64) | |
3961 | operands[3] = const0_rtx; | |
3962 | else | |
89e9f3a8 MM |
3963 | operands[3] = GEN_INT (start + size); |
3964 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3965 | return \"rldicl %0,%1,%3,%2\"; |
3966 | }") | |
3967 | ||
a78e33fc | 3968 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3969 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3970 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3971 | (match_operand:SI 2 "const_int_operand" "i") |
3972 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3973 | (const_int 0))) |
29ae5b89 | 3974 | (clobber (match_scratch:DI 4 "=r"))] |
685f3906 DE |
3975 | "TARGET_POWERPC64" |
3976 | "* | |
3977 | { | |
3978 | int start = INTVAL (operands[3]) & 63; | |
3979 | int size = INTVAL (operands[2]) & 63; | |
3980 | ||
3981 | if (start + size >= 64) | |
3982 | operands[3] = const0_rtx; | |
3983 | else | |
89e9f3a8 MM |
3984 | operands[3] = GEN_INT (start + size); |
3985 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3986 | return \"rldicl. %4,%1,%3,%2\"; |
3987 | }") | |
3988 | ||
a78e33fc | 3989 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3990 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3991 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3992 | (match_operand:SI 2 "const_int_operand" "i") |
3993 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3994 | (const_int 0))) |
29ae5b89 | 3995 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 DE |
3996 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
3997 | "TARGET_POWERPC64" | |
3998 | "* | |
3999 | { | |
4000 | int start = INTVAL (operands[3]) & 63; | |
4001 | int size = INTVAL (operands[2]) & 63; | |
4002 | ||
4003 | if (start + size >= 64) | |
4004 | operands[3] = const0_rtx; | |
4005 | else | |
89e9f3a8 MM |
4006 | operands[3] = GEN_INT (start + size); |
4007 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
4008 | return \"rldicl. %0,%1,%3,%2\"; |
4009 | }") | |
4010 | ||
1fd4e8c1 | 4011 | (define_insn "rotlsi3" |
cd2b37d9 RK |
4012 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4013 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4014 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
4015 | "" | |
ca7f5001 | 4016 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 4017 | |
a260abc9 | 4018 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
4019 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4020 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4021 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 4022 | (const_int 0))) |
9ebbca7d | 4023 | (clobber (match_scratch:SI 3 "=r,r"))] |
ce71f754 | 4024 | "" |
9ebbca7d GK |
4025 | "@ |
4026 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
4027 | #" | |
4028 | [(set_attr "type" "delayed_compare") | |
4029 | (set_attr "length" "4,8")]) | |
4030 | ||
4031 | (define_split | |
4032 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4033 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4034 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4035 | (const_int 0))) | |
4036 | (clobber (match_scratch:SI 3 ""))] | |
ce71f754 | 4037 | "reload_completed" |
9ebbca7d GK |
4038 | [(set (match_dup 3) |
4039 | (rotate:SI (match_dup 1) (match_dup 2))) | |
4040 | (set (match_dup 0) | |
4041 | (compare:CC (match_dup 3) | |
4042 | (const_int 0)))] | |
4043 | "") | |
1fd4e8c1 | 4044 | |
a260abc9 | 4045 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
4046 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4047 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4048 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 4049 | (const_int 0))) |
9ebbca7d | 4050 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4051 | (rotate:SI (match_dup 1) (match_dup 2)))] |
ce71f754 | 4052 | "" |
9ebbca7d GK |
4053 | "@ |
4054 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
4055 | #" | |
4056 | [(set_attr "type" "delayed_compare") | |
4057 | (set_attr "length" "4,8")]) | |
4058 | ||
4059 | (define_split | |
4060 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4061 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4062 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4063 | (const_int 0))) | |
4064 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4065 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
ce71f754 | 4066 | "reload_completed" |
9ebbca7d GK |
4067 | [(set (match_dup 0) |
4068 | (rotate:SI (match_dup 1) (match_dup 2))) | |
4069 | (set (match_dup 3) | |
4070 | (compare:CC (match_dup 0) | |
4071 | (const_int 0)))] | |
4072 | "") | |
1fd4e8c1 | 4073 | |
a260abc9 | 4074 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
4075 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4076 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4077 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
ce71f754 | 4078 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 4079 | "" |
ca7f5001 | 4080 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 4081 | |
a260abc9 | 4082 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 4083 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4084 | (compare:CC (and:SI |
9ebbca7d GK |
4085 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4086 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 4087 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4088 | (const_int 0))) |
9ebbca7d | 4089 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 4090 | "" |
9ebbca7d GK |
4091 | "@ |
4092 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
4093 | #" | |
4094 | [(set_attr "type" "delayed_compare") | |
4095 | (set_attr "length" "4,8")]) | |
4096 | ||
4097 | (define_split | |
4098 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4099 | (compare:CC (and:SI | |
4100 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4101 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4102 | (match_operand:SI 3 "mask_operand" "")) | |
4103 | (const_int 0))) | |
4104 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 4105 | "reload_completed" |
9ebbca7d GK |
4106 | [(set (match_dup 4) |
4107 | (and:SI (rotate:SI (match_dup 1) | |
4108 | (match_dup 2)) | |
4109 | (match_dup 3))) | |
4110 | (set (match_dup 0) | |
4111 | (compare:CC (match_dup 4) | |
4112 | (const_int 0)))] | |
4113 | "") | |
1fd4e8c1 | 4114 | |
a260abc9 | 4115 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 4116 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4117 | (compare:CC (and:SI |
9ebbca7d GK |
4118 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4119 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 4120 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4121 | (const_int 0))) |
9ebbca7d | 4122 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4123 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 4124 | "" |
9ebbca7d GK |
4125 | "@ |
4126 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
4127 | #" | |
4128 | [(set_attr "type" "delayed_compare") | |
4129 | (set_attr "length" "4,8")]) | |
4130 | ||
4131 | (define_split | |
4132 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4133 | (compare:CC (and:SI | |
4134 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4135 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4136 | (match_operand:SI 3 "mask_operand" "")) | |
4137 | (const_int 0))) | |
4138 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4139 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 4140 | "reload_completed" |
9ebbca7d GK |
4141 | [(set (match_dup 0) |
4142 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4143 | (set (match_dup 4) | |
4144 | (compare:CC (match_dup 0) | |
4145 | (const_int 0)))] | |
4146 | "") | |
1fd4e8c1 | 4147 | |
a260abc9 | 4148 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 4149 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4150 | (zero_extend:SI |
4151 | (subreg:QI | |
cd2b37d9 | 4152 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
4153 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
4154 | "" | |
ca7f5001 | 4155 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 4156 | |
a260abc9 | 4157 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 4158 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4159 | (compare:CC (zero_extend:SI |
4160 | (subreg:QI | |
9ebbca7d GK |
4161 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4162 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 4163 | (const_int 0))) |
9ebbca7d | 4164 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 4165 | "" |
9ebbca7d GK |
4166 | "@ |
4167 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
4168 | #" | |
4169 | [(set_attr "type" "delayed_compare") | |
4170 | (set_attr "length" "4,8")]) | |
4171 | ||
4172 | (define_split | |
4173 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4174 | (compare:CC (zero_extend:SI | |
4175 | (subreg:QI | |
4176 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4177 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
4178 | (const_int 0))) | |
4179 | (clobber (match_scratch:SI 3 ""))] | |
4180 | "reload_completed" | |
4181 | [(set (match_dup 3) | |
4182 | (zero_extend:SI (subreg:QI | |
4183 | (rotate:SI (match_dup 1) | |
4184 | (match_dup 2)) 0))) | |
4185 | (set (match_dup 0) | |
4186 | (compare:CC (match_dup 3) | |
4187 | (const_int 0)))] | |
4188 | "") | |
1fd4e8c1 | 4189 | |
a260abc9 | 4190 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 4191 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4192 | (compare:CC (zero_extend:SI |
4193 | (subreg:QI | |
9ebbca7d GK |
4194 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4195 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 4196 | (const_int 0))) |
9ebbca7d | 4197 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
4198 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
4199 | "" | |
9ebbca7d GK |
4200 | "@ |
4201 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
4202 | #" | |
4203 | [(set_attr "type" "delayed_compare") | |
4204 | (set_attr "length" "4,8")]) | |
4205 | ||
4206 | (define_split | |
4207 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4208 | (compare:CC (zero_extend:SI | |
4209 | (subreg:QI | |
4210 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4211 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
4212 | (const_int 0))) | |
4213 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4214 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
4215 | "reload_completed" | |
4216 | [(set (match_dup 0) | |
4217 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
4218 | (set (match_dup 3) | |
4219 | (compare:CC (match_dup 0) | |
4220 | (const_int 0)))] | |
4221 | "") | |
1fd4e8c1 | 4222 | |
a260abc9 | 4223 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 4224 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4225 | (zero_extend:SI |
4226 | (subreg:HI | |
cd2b37d9 | 4227 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
4228 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
4229 | "" | |
ca7f5001 | 4230 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 4231 | |
a260abc9 | 4232 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 4233 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4234 | (compare:CC (zero_extend:SI |
4235 | (subreg:HI | |
9ebbca7d GK |
4236 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4237 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 4238 | (const_int 0))) |
9ebbca7d | 4239 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 4240 | "" |
9ebbca7d GK |
4241 | "@ |
4242 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
4243 | #" | |
4244 | [(set_attr "type" "delayed_compare") | |
4245 | (set_attr "length" "4,8")]) | |
4246 | ||
4247 | (define_split | |
4248 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4249 | (compare:CC (zero_extend:SI | |
4250 | (subreg:HI | |
4251 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4252 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
4253 | (const_int 0))) | |
4254 | (clobber (match_scratch:SI 3 ""))] | |
4255 | "reload_completed" | |
4256 | [(set (match_dup 3) | |
4257 | (zero_extend:SI (subreg:HI | |
4258 | (rotate:SI (match_dup 1) | |
4259 | (match_dup 2)) 0))) | |
4260 | (set (match_dup 0) | |
4261 | (compare:CC (match_dup 3) | |
4262 | (const_int 0)))] | |
4263 | "") | |
1fd4e8c1 | 4264 | |
a260abc9 | 4265 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 4266 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4267 | (compare:CC (zero_extend:SI |
4268 | (subreg:HI | |
9ebbca7d GK |
4269 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4270 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 4271 | (const_int 0))) |
9ebbca7d | 4272 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
4273 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
4274 | "" | |
9ebbca7d GK |
4275 | "@ |
4276 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
4277 | #" | |
4278 | [(set_attr "type" "delayed_compare") | |
4279 | (set_attr "length" "4,8")]) | |
4280 | ||
4281 | (define_split | |
4282 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4283 | (compare:CC (zero_extend:SI | |
4284 | (subreg:HI | |
4285 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4286 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
4287 | (const_int 0))) | |
4288 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4289 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
4290 | "reload_completed" | |
4291 | [(set (match_dup 0) | |
4292 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
4293 | (set (match_dup 3) | |
4294 | (compare:CC (match_dup 0) | |
4295 | (const_int 0)))] | |
4296 | "") | |
1fd4e8c1 RK |
4297 | |
4298 | ;; Note that we use "sle." instead of "sl." so that we can set | |
4299 | ;; SHIFT_COUNT_TRUNCATED. | |
4300 | ||
ca7f5001 RK |
4301 | (define_expand "ashlsi3" |
4302 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
4303 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
4304 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
4305 | "" | |
4306 | " | |
4307 | { | |
4308 | if (TARGET_POWER) | |
4309 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
4310 | else | |
25c341fa | 4311 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4312 | DONE; |
4313 | }") | |
4314 | ||
4315 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
4316 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4317 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4318 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4319 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4320 | "TARGET_POWER" |
1fd4e8c1 RK |
4321 | "@ |
4322 | sle %0,%1,%2 | |
9ebbca7d | 4323 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 4324 | |
25c341fa | 4325 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
4326 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4327 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4328 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4329 | "! TARGET_POWER" |
9ebbca7d | 4330 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4331 | |
4332 | (define_insn "" | |
9ebbca7d GK |
4333 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4334 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4335 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4336 | (const_int 0))) |
9ebbca7d GK |
4337 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4338 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4339 | "TARGET_POWER" |
1fd4e8c1 RK |
4340 | "@ |
4341 | sle. %3,%1,%2 | |
9ebbca7d GK |
4342 | {sli.|slwi.} %3,%1,%h2 |
4343 | # | |
4344 | #" | |
4345 | [(set_attr "type" "delayed_compare") | |
4346 | (set_attr "length" "4,4,8,8")]) | |
4347 | ||
4348 | (define_split | |
4349 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4350 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4351 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4352 | (const_int 0))) | |
4353 | (clobber (match_scratch:SI 3 "")) | |
4354 | (clobber (match_scratch:SI 4 ""))] | |
4355 | "TARGET_POWER && reload_completed" | |
4356 | [(parallel [(set (match_dup 3) | |
4357 | (ashift:SI (match_dup 1) (match_dup 2))) | |
4358 | (clobber (match_dup 4))]) | |
4359 | (set (match_dup 0) | |
4360 | (compare:CC (match_dup 3) | |
4361 | (const_int 0)))] | |
4362 | "") | |
25c341fa | 4363 | |
ca7f5001 | 4364 | (define_insn "" |
9ebbca7d GK |
4365 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4366 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4367 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4368 | (const_int 0))) |
9ebbca7d | 4369 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 4370 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
4371 | "@ |
4372 | {sl|slw}%I2. %3,%1,%h2 | |
4373 | #" | |
4374 | [(set_attr "type" "delayed_compare") | |
4375 | (set_attr "length" "4,8")]) | |
4376 | ||
4377 | (define_split | |
4378 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4379 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4380 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4381 | (const_int 0))) | |
4382 | (clobber (match_scratch:SI 3 ""))] | |
4383 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4384 | [(set (match_dup 3) | |
4385 | (ashift:SI (match_dup 1) (match_dup 2))) | |
4386 | (set (match_dup 0) | |
4387 | (compare:CC (match_dup 3) | |
4388 | (const_int 0)))] | |
4389 | "") | |
1fd4e8c1 RK |
4390 | |
4391 | (define_insn "" | |
9ebbca7d GK |
4392 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4393 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4394 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4395 | (const_int 0))) |
9ebbca7d | 4396 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4397 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4398 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4399 | "TARGET_POWER" |
1fd4e8c1 RK |
4400 | "@ |
4401 | sle. %0,%1,%2 | |
9ebbca7d GK |
4402 | {sli.|slwi.} %0,%1,%h2 |
4403 | # | |
4404 | #" | |
4405 | [(set_attr "type" "delayed_compare") | |
4406 | (set_attr "length" "4,4,8,8")]) | |
4407 | ||
4408 | (define_split | |
4409 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4410 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4411 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4412 | (const_int 0))) | |
4413 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4414 | (ashift:SI (match_dup 1) (match_dup 2))) | |
4415 | (clobber (match_scratch:SI 4 ""))] | |
4416 | "TARGET_POWER && reload_completed" | |
4417 | [(parallel [(set (match_dup 0) | |
4418 | (ashift:SI (match_dup 1) (match_dup 2))) | |
4419 | (clobber (match_dup 4))]) | |
4420 | (set (match_dup 3) | |
4421 | (compare:CC (match_dup 0) | |
4422 | (const_int 0)))] | |
4423 | "") | |
25c341fa | 4424 | |
ca7f5001 | 4425 | (define_insn "" |
9ebbca7d GK |
4426 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4427 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4428 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4429 | (const_int 0))) |
9ebbca7d | 4430 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4431 | (ashift:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 4432 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
4433 | "@ |
4434 | {sl|slw}%I2. %0,%1,%h2 | |
4435 | #" | |
4436 | [(set_attr "type" "delayed_compare") | |
4437 | (set_attr "length" "4,8")]) | |
4438 | ||
4439 | (define_split | |
4440 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4441 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4442 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4443 | (const_int 0))) | |
4444 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4445 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
4446 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4447 | [(set (match_dup 0) | |
4448 | (ashift:SI (match_dup 1) (match_dup 2))) | |
4449 | (set (match_dup 3) | |
4450 | (compare:CC (match_dup 0) | |
4451 | (const_int 0)))] | |
4452 | "") | |
1fd4e8c1 RK |
4453 | |
4454 | (define_insn "" | |
cd2b37d9 RK |
4455 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4456 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4457 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 4458 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 4459 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 4460 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
4461 | |
4462 | (define_insn "" | |
9ebbca7d | 4463 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4464 | (compare:CC |
9ebbca7d GK |
4465 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4466 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 4467 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4468 | (const_int 0))) |
9ebbca7d | 4469 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 4470 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4471 | "@ |
4472 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
4473 | #" | |
4474 | [(set_attr "type" "delayed_compare") | |
4475 | (set_attr "length" "4,8")]) | |
4476 | ||
4477 | (define_split | |
4478 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4479 | (compare:CC | |
4480 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4481 | (match_operand:SI 2 "const_int_operand" "")) | |
4482 | (match_operand:SI 3 "mask_operand" "")) | |
4483 | (const_int 0))) | |
4484 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 4485 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4486 | [(set (match_dup 4) |
4487 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
4488 | (match_dup 3))) | |
4489 | (set (match_dup 0) | |
4490 | (compare:CC (match_dup 4) | |
4491 | (const_int 0)))] | |
4492 | "") | |
1fd4e8c1 RK |
4493 | |
4494 | (define_insn "" | |
9ebbca7d | 4495 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4496 | (compare:CC |
9ebbca7d GK |
4497 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4498 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 4499 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4500 | (const_int 0))) |
9ebbca7d | 4501 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4502 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 4503 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4504 | "@ |
4505 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
4506 | #" | |
4507 | [(set_attr "type" "delayed_compare") | |
4508 | (set_attr "length" "4,8")]) | |
4509 | ||
4510 | (define_split | |
4511 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4512 | (compare:CC | |
4513 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4514 | (match_operand:SI 2 "const_int_operand" "")) | |
4515 | (match_operand:SI 3 "mask_operand" "")) | |
4516 | (const_int 0))) | |
4517 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4518 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 4519 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4520 | [(set (match_dup 0) |
4521 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4522 | (set (match_dup 4) | |
4523 | (compare:CC (match_dup 0) | |
4524 | (const_int 0)))] | |
4525 | "") | |
1fd4e8c1 | 4526 | |
ca7f5001 | 4527 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 4528 | ;; "sli x,x,0". |
ca7f5001 RK |
4529 | (define_expand "lshrsi3" |
4530 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
4531 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
4532 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
4533 | "" | |
4534 | " | |
4535 | { | |
4536 | if (TARGET_POWER) | |
4537 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
4538 | else | |
25c341fa | 4539 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4540 | DONE; |
4541 | }") | |
4542 | ||
4543 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
4544 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
4545 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
4546 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
4547 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 4548 | "TARGET_POWER" |
1fd4e8c1 RK |
4549 | "@ |
4550 | sre %0,%1,%2 | |
bdf423cb | 4551 | mr %0,%1 |
ca7f5001 RK |
4552 | {s%A2i|s%A2wi} %0,%1,%h2") |
4553 | ||
25c341fa | 4554 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
4555 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4556 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4557 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 4558 | "! TARGET_POWER" |
bdf423cb MM |
4559 | "@ |
4560 | mr %0,%1 | |
4561 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
4562 | |
4563 | (define_insn "" | |
9ebbca7d GK |
4564 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
4565 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4566 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4567 | (const_int 0))) |
9ebbca7d GK |
4568 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
4569 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 4570 | "TARGET_POWER" |
1fd4e8c1 | 4571 | "@ |
29ae5b89 JL |
4572 | sre. %3,%1,%2 |
4573 | mr. %1,%1 | |
9ebbca7d GK |
4574 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
4575 | # | |
4576 | # | |
4577 | #" | |
4578 | [(set_attr "type" "delayed_compare") | |
4579 | (set_attr "length" "4,4,4,8,8,8")]) | |
4580 | ||
4581 | (define_split | |
4582 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4583 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4584 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4585 | (const_int 0))) | |
4586 | (clobber (match_scratch:SI 3 "")) | |
4587 | (clobber (match_scratch:SI 4 ""))] | |
4588 | "TARGET_POWER && reload_completed" | |
4589 | [(parallel [(set (match_dup 3) | |
4590 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4591 | (clobber (match_dup 4))]) | |
4592 | (set (match_dup 0) | |
4593 | (compare:CC (match_dup 3) | |
4594 | (const_int 0)))] | |
4595 | "") | |
ca7f5001 RK |
4596 | |
4597 | (define_insn "" | |
9ebbca7d GK |
4598 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4599 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4600 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 4601 | (const_int 0))) |
9ebbca7d | 4602 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
0ad91047 | 4603 | "! TARGET_POWER && ! TARGET_POWERPC64" |
bdf423cb MM |
4604 | "@ |
4605 | mr. %1,%1 | |
9ebbca7d GK |
4606 | {sr|srw}%I2. %3,%1,%h2 |
4607 | # | |
4608 | #" | |
4609 | [(set_attr "type" "delayed_compare") | |
4610 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 4611 | |
9ebbca7d GK |
4612 | (define_split |
4613 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4614 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4615 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4616 | (const_int 0))) | |
4617 | (clobber (match_scratch:SI 3 ""))] | |
4618 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4619 | [(set (match_dup 3) | |
4620 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4621 | (set (match_dup 0) | |
4622 | (compare:CC (match_dup 3) | |
4623 | (const_int 0)))] | |
4624 | "") | |
4625 | ||
4626 | (define_insn "" | |
4627 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
4628 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4629 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4630 | (const_int 0))) |
9ebbca7d | 4631 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 4632 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4633 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 4634 | "TARGET_POWER" |
1fd4e8c1 | 4635 | "@ |
29ae5b89 JL |
4636 | sre. %0,%1,%2 |
4637 | mr. %0,%1 | |
9ebbca7d GK |
4638 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
4639 | # | |
4640 | # | |
4641 | #" | |
4642 | [(set_attr "type" "delayed_compare") | |
4643 | (set_attr "length" "4,4,4,8,8,8")]) | |
4644 | ||
4645 | (define_split | |
4646 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4647 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4648 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4649 | (const_int 0))) | |
4650 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4651 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4652 | (clobber (match_scratch:SI 4 ""))] | |
4653 | "TARGET_POWER && reload_completed" | |
4654 | [(parallel [(set (match_dup 0) | |
4655 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4656 | (clobber (match_dup 4))]) | |
4657 | (set (match_dup 3) | |
4658 | (compare:CC (match_dup 0) | |
4659 | (const_int 0)))] | |
4660 | "") | |
ca7f5001 RK |
4661 | |
4662 | (define_insn "" | |
9ebbca7d GK |
4663 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4664 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4665 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 4666 | (const_int 0))) |
9ebbca7d | 4667 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 4668 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 4669 | "! TARGET_POWER && ! TARGET_POWERPC64" |
29ae5b89 JL |
4670 | "@ |
4671 | mr. %0,%1 | |
9ebbca7d GK |
4672 | {sr|srw}%I2. %0,%1,%h2 |
4673 | # | |
4674 | #" | |
4675 | [(set_attr "type" "delayed_compare") | |
4676 | (set_attr "length" "4,4,8,8")]) | |
4677 | ||
4678 | (define_split | |
4679 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4680 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4681 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4682 | (const_int 0))) | |
4683 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4684 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4685 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4686 | [(set (match_dup 0) | |
4687 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4688 | (set (match_dup 3) | |
4689 | (compare:CC (match_dup 0) | |
4690 | (const_int 0)))] | |
4691 | "") | |
1fd4e8c1 RK |
4692 | |
4693 | (define_insn "" | |
cd2b37d9 RK |
4694 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4695 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4696 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 4697 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 4698 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 4699 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
4700 | |
4701 | (define_insn "" | |
9ebbca7d | 4702 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4703 | (compare:CC |
9ebbca7d GK |
4704 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4705 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 4706 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4707 | (const_int 0))) |
9ebbca7d | 4708 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 4709 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4710 | "@ |
4711 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
4712 | #" | |
4713 | [(set_attr "type" "delayed_compare") | |
4714 | (set_attr "length" "4,8")]) | |
4715 | ||
4716 | (define_split | |
4717 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4718 | (compare:CC | |
4719 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4720 | (match_operand:SI 2 "const_int_operand" "")) | |
4721 | (match_operand:SI 3 "mask_operand" "")) | |
4722 | (const_int 0))) | |
4723 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 4724 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4725 | [(set (match_dup 4) |
4726 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
4727 | (match_dup 3))) | |
4728 | (set (match_dup 0) | |
4729 | (compare:CC (match_dup 4) | |
4730 | (const_int 0)))] | |
4731 | "") | |
1fd4e8c1 RK |
4732 | |
4733 | (define_insn "" | |
9ebbca7d | 4734 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4735 | (compare:CC |
9ebbca7d GK |
4736 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4737 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 4738 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4739 | (const_int 0))) |
9ebbca7d | 4740 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4741 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 4742 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4743 | "@ |
4744 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
4745 | #" | |
4746 | [(set_attr "type" "delayed_compare") | |
4747 | (set_attr "length" "4,8")]) | |
4748 | ||
4749 | (define_split | |
4750 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4751 | (compare:CC | |
4752 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4753 | (match_operand:SI 2 "const_int_operand" "")) | |
4754 | (match_operand:SI 3 "mask_operand" "")) | |
4755 | (const_int 0))) | |
4756 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4757 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 4758 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4759 | [(set (match_dup 0) |
4760 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4761 | (set (match_dup 4) | |
4762 | (compare:CC (match_dup 0) | |
4763 | (const_int 0)))] | |
4764 | "") | |
1fd4e8c1 RK |
4765 | |
4766 | (define_insn "" | |
cd2b37d9 | 4767 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4768 | (zero_extend:SI |
4769 | (subreg:QI | |
cd2b37d9 | 4770 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4771 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4772 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4773 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4774 | |
4775 | (define_insn "" | |
9ebbca7d | 4776 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4777 | (compare:CC |
4778 | (zero_extend:SI | |
4779 | (subreg:QI | |
9ebbca7d GK |
4780 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4781 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4782 | (const_int 0))) |
9ebbca7d | 4783 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4784 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4785 | "@ |
4786 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4787 | #" | |
4788 | [(set_attr "type" "delayed_compare") | |
4789 | (set_attr "length" "4,8")]) | |
4790 | ||
4791 | (define_split | |
4792 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4793 | (compare:CC | |
4794 | (zero_extend:SI | |
4795 | (subreg:QI | |
4796 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4797 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4798 | (const_int 0))) | |
4799 | (clobber (match_scratch:SI 3 ""))] | |
4800 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4801 | [(set (match_dup 3) | |
4802 | (zero_extend:SI (subreg:QI | |
4803 | (lshiftrt:SI (match_dup 1) | |
4804 | (match_dup 2)) 0))) | |
4805 | (set (match_dup 0) | |
4806 | (compare:CC (match_dup 3) | |
4807 | (const_int 0)))] | |
4808 | "") | |
1fd4e8c1 RK |
4809 | |
4810 | (define_insn "" | |
9ebbca7d | 4811 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4812 | (compare:CC |
4813 | (zero_extend:SI | |
4814 | (subreg:QI | |
9ebbca7d GK |
4815 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4816 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4817 | (const_int 0))) |
9ebbca7d | 4818 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4819 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4820 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4821 | "@ |
4822 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4823 | #" | |
4824 | [(set_attr "type" "delayed_compare") | |
4825 | (set_attr "length" "4,8")]) | |
4826 | ||
4827 | (define_split | |
4828 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4829 | (compare:CC | |
4830 | (zero_extend:SI | |
4831 | (subreg:QI | |
4832 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4833 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4834 | (const_int 0))) | |
4835 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4836 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4837 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4838 | [(set (match_dup 0) | |
4839 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4840 | (set (match_dup 3) | |
4841 | (compare:CC (match_dup 0) | |
4842 | (const_int 0)))] | |
4843 | "") | |
1fd4e8c1 RK |
4844 | |
4845 | (define_insn "" | |
cd2b37d9 | 4846 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4847 | (zero_extend:SI |
4848 | (subreg:HI | |
cd2b37d9 | 4849 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4850 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4851 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4852 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4853 | |
4854 | (define_insn "" | |
9ebbca7d | 4855 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4856 | (compare:CC |
4857 | (zero_extend:SI | |
4858 | (subreg:HI | |
9ebbca7d GK |
4859 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4860 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4861 | (const_int 0))) |
9ebbca7d | 4862 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4863 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4864 | "@ |
4865 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4866 | #" | |
4867 | [(set_attr "type" "delayed_compare") | |
4868 | (set_attr "length" "4,8")]) | |
4869 | ||
4870 | (define_split | |
4871 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4872 | (compare:CC | |
4873 | (zero_extend:SI | |
4874 | (subreg:HI | |
4875 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4876 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4877 | (const_int 0))) | |
4878 | (clobber (match_scratch:SI 3 ""))] | |
4879 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4880 | [(set (match_dup 3) | |
4881 | (zero_extend:SI (subreg:HI | |
4882 | (lshiftrt:SI (match_dup 1) | |
4883 | (match_dup 2)) 0))) | |
4884 | (set (match_dup 0) | |
4885 | (compare:CC (match_dup 3) | |
4886 | (const_int 0)))] | |
4887 | "") | |
1fd4e8c1 RK |
4888 | |
4889 | (define_insn "" | |
9ebbca7d | 4890 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4891 | (compare:CC |
4892 | (zero_extend:SI | |
4893 | (subreg:HI | |
9ebbca7d GK |
4894 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4895 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4896 | (const_int 0))) |
9ebbca7d | 4897 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4898 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4899 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4900 | "@ |
4901 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4902 | #" | |
4903 | [(set_attr "type" "delayed_compare") | |
4904 | (set_attr "length" "4,8")]) | |
4905 | ||
4906 | (define_split | |
4907 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4908 | (compare:CC | |
4909 | (zero_extend:SI | |
4910 | (subreg:HI | |
4911 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4912 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4913 | (const_int 0))) | |
4914 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4915 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4916 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4917 | [(set (match_dup 0) | |
4918 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4919 | (set (match_dup 3) | |
4920 | (compare:CC (match_dup 0) | |
4921 | (const_int 0)))] | |
4922 | "") | |
1fd4e8c1 RK |
4923 | |
4924 | (define_insn "" | |
cd2b37d9 | 4925 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4926 | (const_int 1) |
cd2b37d9 RK |
4927 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4928 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4929 | (const_int 31)))] |
ca7f5001 | 4930 | "TARGET_POWER" |
1fd4e8c1 RK |
4931 | "rrib %0,%1,%2") |
4932 | ||
4933 | (define_insn "" | |
cd2b37d9 | 4934 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4935 | (const_int 1) |
cd2b37d9 RK |
4936 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4937 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4938 | (const_int 31)))] |
ca7f5001 | 4939 | "TARGET_POWER" |
1fd4e8c1 RK |
4940 | "rrib %0,%1,%2") |
4941 | ||
4942 | (define_insn "" | |
cd2b37d9 | 4943 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4944 | (const_int 1) |
cd2b37d9 RK |
4945 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4946 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4947 | (const_int 1) |
4948 | (const_int 0)))] | |
ca7f5001 | 4949 | "TARGET_POWER" |
1fd4e8c1 RK |
4950 | "rrib %0,%1,%2") |
4951 | ||
ca7f5001 RK |
4952 | (define_expand "ashrsi3" |
4953 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4954 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4955 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4956 | "" | |
4957 | " | |
4958 | { | |
4959 | if (TARGET_POWER) | |
4960 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4961 | else | |
25c341fa | 4962 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4963 | DONE; |
4964 | }") | |
4965 | ||
4966 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4967 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4968 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4969 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4970 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4971 | "TARGET_POWER" |
1fd4e8c1 RK |
4972 | "@ |
4973 | srea %0,%1,%2 | |
ca7f5001 RK |
4974 | {srai|srawi} %0,%1,%h2") |
4975 | ||
25c341fa | 4976 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4977 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4978 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4979 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4980 | "! TARGET_POWER" |
d904e9ed | 4981 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4982 | |
4983 | (define_insn "" | |
9ebbca7d GK |
4984 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4985 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4986 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4987 | (const_int 0))) |
9ebbca7d GK |
4988 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4989 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4990 | "TARGET_POWER" |
1fd4e8c1 RK |
4991 | "@ |
4992 | srea. %3,%1,%2 | |
9ebbca7d GK |
4993 | {srai.|srawi.} %3,%1,%h2 |
4994 | # | |
4995 | #" | |
4996 | [(set_attr "type" "delayed_compare") | |
4997 | (set_attr "length" "4,4,8,8")]) | |
4998 | ||
4999 | (define_split | |
5000 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5001 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
5002 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
5003 | (const_int 0))) | |
5004 | (clobber (match_scratch:SI 3 "")) | |
5005 | (clobber (match_scratch:SI 4 ""))] | |
5006 | "TARGET_POWER && reload_completed" | |
5007 | [(parallel [(set (match_dup 3) | |
5008 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
5009 | (clobber (match_dup 4))]) | |
5010 | (set (match_dup 0) | |
5011 | (compare:CC (match_dup 3) | |
5012 | (const_int 0)))] | |
5013 | "") | |
ca7f5001 RK |
5014 | |
5015 | (define_insn "" | |
9ebbca7d GK |
5016 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5017 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
5018 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 5019 | (const_int 0))) |
9ebbca7d | 5020 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 5021 | "! TARGET_POWER" |
9ebbca7d GK |
5022 | "@ |
5023 | {sra|sraw}%I2. %3,%1,%h2 | |
5024 | #" | |
5025 | [(set_attr "type" "delayed_compare") | |
5026 | (set_attr "length" "4,8")]) | |
5027 | ||
5028 | (define_split | |
5029 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5030 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
5031 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
5032 | (const_int 0))) | |
5033 | (clobber (match_scratch:SI 3 ""))] | |
5034 | "! TARGET_POWER && reload_completed" | |
5035 | [(set (match_dup 3) | |
5036 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
5037 | (set (match_dup 0) | |
5038 | (compare:CC (match_dup 3) | |
5039 | (const_int 0)))] | |
5040 | "") | |
1fd4e8c1 RK |
5041 | |
5042 | (define_insn "" | |
9ebbca7d GK |
5043 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
5044 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
5045 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 5046 | (const_int 0))) |
9ebbca7d | 5047 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 5048 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 5049 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 5050 | "TARGET_POWER" |
1fd4e8c1 RK |
5051 | "@ |
5052 | srea. %0,%1,%2 | |
9ebbca7d GK |
5053 | {srai.|srawi.} %0,%1,%h2 |
5054 | # | |
5055 | #" | |
5056 | [(set_attr "type" "delayed_compare") | |
5057 | (set_attr "length" "4,4,8,8")]) | |
5058 | ||
5059 | (define_split | |
5060 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5061 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
5062 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
5063 | (const_int 0))) | |
5064 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
5065 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
5066 | (clobber (match_scratch:SI 4 ""))] | |
5067 | "TARGET_POWER && reload_completed" | |
5068 | [(parallel [(set (match_dup 0) | |
5069 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
5070 | (clobber (match_dup 4))]) | |
5071 | (set (match_dup 3) | |
5072 | (compare:CC (match_dup 0) | |
5073 | (const_int 0)))] | |
5074 | "") | |
1fd4e8c1 | 5075 | |
ca7f5001 | 5076 | (define_insn "" |
9ebbca7d GK |
5077 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
5078 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
5079 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 5080 | (const_int 0))) |
9ebbca7d | 5081 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 5082 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 5083 | "! TARGET_POWER" |
9ebbca7d GK |
5084 | "@ |
5085 | {sra|sraw}%I2. %0,%1,%h2 | |
5086 | #" | |
5087 | [(set_attr "type" "delayed_compare") | |
5088 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 5089 | \f |
9ebbca7d GK |
5090 | (define_split |
5091 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5092 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
5093 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
5094 | (const_int 0))) | |
5095 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
5096 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
5097 | "! TARGET_POWER && reload_completed" | |
5098 | [(set (match_dup 0) | |
5099 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
5100 | (set (match_dup 3) | |
5101 | (compare:CC (match_dup 0) | |
5102 | (const_int 0)))] | |
5103 | "") | |
5104 | ||
1fd4e8c1 RK |
5105 | ;; Floating-point insns, excluding normal data motion. |
5106 | ;; | |
ca7f5001 RK |
5107 | ;; PowerPC has a full set of single-precision floating point instructions. |
5108 | ;; | |
5109 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
5110 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
5111 | ;; The only conversions we will do will be when storing to memory. In that | |
5112 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
5113 | ;; |
5114 | ;; Note that when we store into a single-precision memory location, we need to | |
5115 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
5116 | ;; need a scratch register for the frsp. But this is difficult when the store | |
5117 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
5118 | ;; this case, we just lose precision that we would have otherwise gotten but | |
5119 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
5120 | ||
e8112008 | 5121 | (define_insn "extendsfdf2" |
cd2b37d9 | 5122 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
e8112008 | 5123 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] |
a3170dc6 | 5124 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
e8112008 | 5125 | "* |
5c30aff8 | 5126 | { |
e8112008 RK |
5127 | if (REGNO (operands[0]) == REGNO (operands[1])) |
5128 | return \"\"; | |
5129 | else | |
5130 | return \"fmr %0,%1\"; | |
5131 | }" | |
5132 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5133 | |
5134 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
5135 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5136 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5137 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
dcac138d | 5138 | "frsp %0,%1" |
1fd4e8c1 RK |
5139 | [(set_attr "type" "fp")]) |
5140 | ||
455350f4 RK |
5141 | (define_insn "aux_truncdfsf2" |
5142 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5143 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))] | |
a3170dc6 | 5144 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
455350f4 RK |
5145 | "frsp %0,%1" |
5146 | [(set_attr "type" "fp")]) | |
5147 | ||
a3170dc6 AH |
5148 | (define_expand "negsf2" |
5149 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5150 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5151 | "TARGET_HARD_FLOAT" | |
5152 | "") | |
5153 | ||
5154 | (define_insn "*negsf2" | |
cd2b37d9 RK |
5155 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5156 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5157 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5158 | "fneg %0,%1" |
5159 | [(set_attr "type" "fp")]) | |
5160 | ||
a3170dc6 AH |
5161 | (define_expand "abssf2" |
5162 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5163 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5164 | "TARGET_HARD_FLOAT" | |
5165 | "") | |
5166 | ||
5167 | (define_insn "*abssf2" | |
cd2b37d9 RK |
5168 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5169 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5170 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5171 | "fabs %0,%1" |
5172 | [(set_attr "type" "fp")]) | |
5173 | ||
5174 | (define_insn "" | |
cd2b37d9 RK |
5175 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5176 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 5177 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5178 | "fnabs %0,%1" |
5179 | [(set_attr "type" "fp")]) | |
5180 | ||
ca7f5001 RK |
5181 | (define_expand "addsf3" |
5182 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5183 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
5184 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 5185 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
5186 | "") |
5187 | ||
5188 | (define_insn "" | |
cd2b37d9 RK |
5189 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5190 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5191 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5192 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 5193 | "fadds %0,%1,%2" |
ca7f5001 RK |
5194 | [(set_attr "type" "fp")]) |
5195 | ||
5196 | (define_insn "" | |
5197 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5198 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5199 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5200 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 5201 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
5202 | [(set_attr "type" "fp")]) |
5203 | ||
5204 | (define_expand "subsf3" | |
5205 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5206 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
5207 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 5208 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
5209 | "") |
5210 | ||
5211 | (define_insn "" | |
5212 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5213 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
5214 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5215 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 5216 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
5217 | [(set_attr "type" "fp")]) |
5218 | ||
ca7f5001 | 5219 | (define_insn "" |
cd2b37d9 RK |
5220 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5221 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
5222 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5223 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 5224 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
5225 | [(set_attr "type" "fp")]) |
5226 | ||
5227 | (define_expand "mulsf3" | |
5228 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5229 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
5230 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 5231 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
5232 | "") |
5233 | ||
5234 | (define_insn "" | |
5235 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5236 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5237 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5238 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 5239 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
5240 | [(set_attr "type" "fp")]) |
5241 | ||
ca7f5001 | 5242 | (define_insn "" |
cd2b37d9 RK |
5243 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5244 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5245 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5246 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 5247 | "{fm|fmul} %0,%1,%2" |
0780f386 | 5248 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 5249 | |
ca7f5001 RK |
5250 | (define_expand "divsf3" |
5251 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5252 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
5253 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 5254 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
5255 | "") |
5256 | ||
5257 | (define_insn "" | |
cd2b37d9 RK |
5258 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5259 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
5260 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5261 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 5262 | "fdivs %0,%1,%2" |
ca7f5001 RK |
5263 | [(set_attr "type" "sdiv")]) |
5264 | ||
5265 | (define_insn "" | |
5266 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5267 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
5268 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5269 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 5270 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 5271 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
5272 | |
5273 | (define_insn "" | |
cd2b37d9 RK |
5274 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5275 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5276 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5277 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5278 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 5279 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
5280 | [(set_attr "type" "fp")]) |
5281 | ||
5282 | (define_insn "" | |
5283 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5284 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5285 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5286 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5287 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 5288 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 5289 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5290 | |
5291 | (define_insn "" | |
cd2b37d9 RK |
5292 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5293 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5294 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5295 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5296 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 5297 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
5298 | [(set_attr "type" "fp")]) |
5299 | ||
5300 | (define_insn "" | |
5301 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5302 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5303 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5304 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5305 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 5306 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 5307 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5308 | |
5309 | (define_insn "" | |
cd2b37d9 RK |
5310 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5311 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5312 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5313 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
5314 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
5315 | && HONOR_SIGNED_ZEROS (SFmode)" | |
5316 | "fnmadds %0,%1,%2,%3" | |
5317 | [(set_attr "type" "fp")]) | |
5318 | ||
5319 | (define_insn "" | |
5320 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5321 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
5322 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5323 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
5324 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
5325 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 5326 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
5327 | [(set_attr "type" "fp")]) |
5328 | ||
5329 | (define_insn "" | |
5330 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5331 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5332 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5333 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 5334 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 5335 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 5336 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 5337 | |
16823694 GK |
5338 | (define_insn "" |
5339 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5340 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
5341 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5342 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
5343 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
5344 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
5345 | "{fnma|fnmadd} %0,%1,%2,%3" | |
5346 | [(set_attr "type" "dmul")]) | |
5347 | ||
1fd4e8c1 | 5348 | (define_insn "" |
cd2b37d9 RK |
5349 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5350 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5351 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5352 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
5353 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
5354 | && HONOR_SIGNED_ZEROS (SFmode)" | |
5355 | "fnmsubs %0,%1,%2,%3" | |
5356 | [(set_attr "type" "fp")]) | |
5357 | ||
5358 | (define_insn "" | |
5359 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5360 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
5361 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5362 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
5363 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
5364 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 5365 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
5366 | [(set_attr "type" "fp")]) |
5367 | ||
5368 | (define_insn "" | |
5369 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5370 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5371 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5372 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 5373 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 5374 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 5375 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 5376 | |
16823694 GK |
5377 | (define_insn "" |
5378 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5379 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
5380 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5381 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
5382 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
5383 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
5384 | "{fnms|fnmsub} %0,%1,%2,%3" | |
5385 | [(set_attr "type" "fp")]) | |
5386 | ||
ca7f5001 RK |
5387 | (define_expand "sqrtsf2" |
5388 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5389 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 5390 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
5391 | "") |
5392 | ||
5393 | (define_insn "" | |
5394 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5395 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5396 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
5397 | "fsqrts %0,%1" |
5398 | [(set_attr "type" "ssqrt")]) | |
5399 | ||
5400 | (define_insn "" | |
5401 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5402 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5403 | "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
5404 | "fsqrt %0,%1" |
5405 | [(set_attr "type" "dsqrt")]) | |
5406 | ||
94d7001a RK |
5407 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
5408 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
5409 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
5410 | ;; combine. |
5411 | (define_expand "maxsf3" | |
8e871c05 | 5412 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
5413 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
5414 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
5415 | (match_dup 1) |
5416 | (match_dup 2)))] | |
a3170dc6 | 5417 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 5418 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
2f607b94 | 5419 | |
8e871c05 | 5420 | (define_expand "minsf3" |
50a0b056 GK |
5421 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
5422 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
5423 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
5424 | (match_dup 2) | |
5425 | (match_dup 1)))] | |
a3170dc6 | 5426 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 5427 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 5428 | |
8e871c05 RK |
5429 | (define_split |
5430 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
5431 | (match_operator:SF 3 "min_max_operator" |
5432 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
5433 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
a3170dc6 | 5434 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 GK |
5435 | [(const_int 0)] |
5436 | " | |
5437 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
5438 | operands[1], operands[2]); | |
5439 | DONE; | |
5440 | }") | |
2f607b94 | 5441 | |
a3170dc6 AH |
5442 | (define_expand "movsicc" |
5443 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5444 | (if_then_else:SI (match_operand 1 "comparison_operator" "") | |
5445 | (match_operand:SI 2 "gpc_reg_operand" "") | |
5446 | (match_operand:SI 3 "gpc_reg_operand" "")))] | |
5447 | "TARGET_ISEL" | |
5448 | " | |
5449 | { | |
5450 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) | |
5451 | DONE; | |
5452 | else | |
5453 | FAIL; | |
5454 | }") | |
5455 | ||
5456 | ;; We use the BASE_REGS for the isel input operands because, if rA is | |
5457 | ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB | |
5458 | ;; because we may switch the operands and rB may end up being rA. | |
5459 | ;; | |
5460 | ;; We need 2 patterns: an unsigned and a signed pattern. We could | |
5461 | ;; leave out the mode in operand 4 and use one pattern, but reload can | |
5462 | ;; change the mode underneath our feet and then gets confused trying | |
5463 | ;; to reload the value. | |
5464 | (define_insn "isel_signed" | |
5465 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5466 | (if_then_else:SI | |
5467 | (match_operator 1 "comparison_operator" | |
5468 | [(match_operand:CC 4 "cc_reg_operand" "y") | |
5469 | (const_int 0)]) | |
5470 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
5471 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
5472 | "TARGET_ISEL" | |
5473 | "* | |
5474 | { return output_isel (operands); }" | |
5475 | [(set_attr "length" "4")]) | |
5476 | ||
5477 | (define_insn "isel_unsigned" | |
5478 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5479 | (if_then_else:SI | |
5480 | (match_operator 1 "comparison_operator" | |
5481 | [(match_operand:CCUNS 4 "cc_reg_operand" "y") | |
5482 | (const_int 0)]) | |
5483 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
5484 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
5485 | "TARGET_ISEL" | |
5486 | "* | |
5487 | { return output_isel (operands); }" | |
5488 | [(set_attr "length" "4")]) | |
5489 | ||
94d7001a | 5490 | (define_expand "movsfcc" |
0ad91047 | 5491 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 5492 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5493 | (match_operand:SF 2 "gpc_reg_operand" "") |
5494 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 5495 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
5496 | " |
5497 | { | |
50a0b056 GK |
5498 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5499 | DONE; | |
94d7001a | 5500 | else |
50a0b056 | 5501 | FAIL; |
94d7001a | 5502 | }") |
d56d506a | 5503 | |
50a0b056 | 5504 | (define_insn "*fselsfsf4" |
8e871c05 RK |
5505 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5506 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5507 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5508 | (match_operand:SF 2 "gpc_reg_operand" "f") |
5509 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5510 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
5511 | "fsel %0,%1,%2,%3" |
5512 | [(set_attr "type" "fp")]) | |
2f607b94 | 5513 | |
50a0b056 | 5514 | (define_insn "*fseldfsf4" |
94d7001a RK |
5515 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5516 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 5517 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5518 | (match_operand:SF 2 "gpc_reg_operand" "f") |
5519 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5520 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
5521 | "fsel %0,%1,%2,%3" |
5522 | [(set_attr "type" "fp")]) | |
d56d506a | 5523 | |
1fd4e8c1 | 5524 | (define_insn "negdf2" |
cd2b37d9 RK |
5525 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5526 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5527 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5528 | "fneg %0,%1" |
5529 | [(set_attr "type" "fp")]) | |
5530 | ||
5531 | (define_insn "absdf2" | |
cd2b37d9 RK |
5532 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5533 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5534 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5535 | "fabs %0,%1" |
5536 | [(set_attr "type" "fp")]) | |
5537 | ||
5538 | (define_insn "" | |
cd2b37d9 RK |
5539 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5540 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 5541 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5542 | "fnabs %0,%1" |
5543 | [(set_attr "type" "fp")]) | |
5544 | ||
5545 | (define_insn "adddf3" | |
cd2b37d9 RK |
5546 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5547 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5548 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5549 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 5550 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
5551 | [(set_attr "type" "fp")]) |
5552 | ||
5553 | (define_insn "subdf3" | |
cd2b37d9 RK |
5554 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5555 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
5556 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5557 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 5558 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
5559 | [(set_attr "type" "fp")]) |
5560 | ||
5561 | (define_insn "muldf3" | |
cd2b37d9 RK |
5562 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5563 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5564 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5565 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 5566 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 5567 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5568 | |
5569 | (define_insn "divdf3" | |
cd2b37d9 RK |
5570 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5571 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
5572 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5573 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 5574 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 5575 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
5576 | |
5577 | (define_insn "" | |
cd2b37d9 RK |
5578 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5579 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5580 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5581 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5582 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 5583 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 5584 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5585 | |
5586 | (define_insn "" | |
cd2b37d9 RK |
5587 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5588 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5589 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5590 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5591 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 5592 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 5593 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5594 | |
5595 | (define_insn "" | |
cd2b37d9 RK |
5596 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5597 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5598 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5599 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
5600 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
5601 | && HONOR_SIGNED_ZEROS (DFmode)" | |
5602 | "{fnma|fnmadd} %0,%1,%2,%3" | |
5603 | [(set_attr "type" "dmul")]) | |
5604 | ||
5605 | (define_insn "" | |
5606 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5607 | (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) | |
5608 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5609 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5610 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
5611 | && ! HONOR_SIGNED_ZEROS (DFmode)" | |
ca7f5001 | 5612 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 5613 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5614 | |
5615 | (define_insn "" | |
cd2b37d9 RK |
5616 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5617 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5618 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5619 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
5620 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
5621 | && HONOR_SIGNED_ZEROS (DFmode)" | |
5622 | "{fnms|fnmsub} %0,%1,%2,%3" | |
5623 | [(set_attr "type" "dmul")]) | |
5624 | ||
5625 | (define_insn "" | |
5626 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5627 | (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") | |
5628 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5629 | (match_operand:DF 2 "gpc_reg_operand" "f"))))] | |
5630 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
5631 | && ! HONOR_SIGNED_ZEROS (DFmode)" | |
ca7f5001 | 5632 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 5633 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
5634 | |
5635 | (define_insn "sqrtdf2" | |
5636 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5637 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5638 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
5639 | "fsqrt %0,%1" |
5640 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 5641 | |
50a0b056 GK |
5642 | ;; The conditional move instructions allow us to perform max and min |
5643 | ;; operations even when | |
b77dfefc | 5644 | |
8e871c05 | 5645 | (define_expand "maxdf3" |
8e871c05 | 5646 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
5647 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
5648 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
5649 | (match_dup 1) |
5650 | (match_dup 2)))] | |
a3170dc6 | 5651 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 5652 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
b77dfefc | 5653 | |
8e871c05 | 5654 | (define_expand "mindf3" |
50a0b056 GK |
5655 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5656 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
5657 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
5658 | (match_dup 2) | |
5659 | (match_dup 1)))] | |
a3170dc6 | 5660 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 5661 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 5662 | |
8e871c05 RK |
5663 | (define_split |
5664 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
5665 | (match_operator:DF 3 "min_max_operator" |
5666 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
5667 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
a3170dc6 | 5668 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 GK |
5669 | [(const_int 0)] |
5670 | " | |
5671 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
5672 | operands[1], operands[2]); | |
5673 | DONE; | |
5674 | }") | |
b77dfefc | 5675 | |
94d7001a | 5676 | (define_expand "movdfcc" |
0ad91047 | 5677 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 5678 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5679 | (match_operand:DF 2 "gpc_reg_operand" "") |
5680 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 5681 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
5682 | " |
5683 | { | |
50a0b056 GK |
5684 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5685 | DONE; | |
94d7001a | 5686 | else |
50a0b056 | 5687 | FAIL; |
94d7001a | 5688 | }") |
d56d506a | 5689 | |
50a0b056 | 5690 | (define_insn "*fseldfdf4" |
8e871c05 RK |
5691 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5692 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5693 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5694 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5695 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5696 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
5697 | "fsel %0,%1,%2,%3" |
5698 | [(set_attr "type" "fp")]) | |
d56d506a | 5699 | |
50a0b056 | 5700 | (define_insn "*fselsfdf4" |
94d7001a RK |
5701 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5702 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5703 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5704 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5705 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5706 | "TARGET_PPC_GFXOPT" | |
5707 | "fsel %0,%1,%2,%3" | |
5708 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5709 | \f |
5710 | ;; Conversions to and from floating-point. | |
802a0058 | 5711 | |
a3170dc6 AH |
5712 | (define_expand "fixunssfsi2" |
5713 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5714 | (unsigned_fix:SI (fix:SF (match_operand:SF 1 "gpc_reg_operand" ""))))] | |
5715 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5716 | "") | |
5717 | ||
5718 | (define_expand "fix_truncsfsi2" | |
5719 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5720 | (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5721 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5722 | "") | |
5723 | ||
9ebbca7d GK |
5724 | ; For each of these conversions, there is a define_expand, a define_insn |
5725 | ; with a '#' template, and a define_split (with C code). The idea is | |
5726 | ; to allow constant folding with the template of the define_insn, | |
5727 | ; then to have the insns split later (between sched1 and final). | |
5728 | ||
1fd4e8c1 | 5729 | (define_expand "floatsidf2" |
802a0058 MM |
5730 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5731 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5732 | (use (match_dup 2)) | |
5733 | (use (match_dup 3)) | |
208c89ce | 5734 | (clobber (match_dup 4)) |
a7df97e6 | 5735 | (clobber (match_dup 5)) |
9ebbca7d | 5736 | (clobber (match_dup 6))])] |
a3170dc6 | 5737 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5738 | " |
5739 | { | |
05d49501 AM |
5740 | if (TARGET_POWERPC64) |
5741 | { | |
5742 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5743 | rtx t1 = gen_reg_rtx (DImode); | |
5744 | rtx t2 = gen_reg_rtx (DImode); | |
5745 | emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); | |
5746 | DONE; | |
5747 | } | |
5748 | ||
802a0058 | 5749 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5750 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); |
9ebbca7d GK |
5751 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5752 | operands[5] = gen_reg_rtx (DFmode); | |
5753 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5754 | }") |
5755 | ||
802a0058 MM |
5756 | (define_insn "*floatsidf2_internal" |
5757 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5758 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5759 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5760 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5761 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 DJ |
5762 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) |
5763 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] | |
a3170dc6 | 5764 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5765 | "#" |
a7df97e6 | 5766 | [(set_attr "length" "24")]) |
802a0058 MM |
5767 | |
5768 | (define_split | |
dbe3df29 | 5769 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
5770 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
5771 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5772 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5773 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5774 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5775 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
a3170dc6 | 5776 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5777 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5778 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5779 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5780 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5781 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5782 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5783 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
208c89ce MM |
5784 | " |
5785 | { | |
9ebbca7d GK |
5786 | rtx lowword, highword; |
5787 | if (GET_CODE (operands[4]) != MEM) | |
5788 | abort(); | |
5789 | highword = XEXP (operands[4], 0); | |
5790 | lowword = plus_constant (highword, 4); | |
5791 | if (! WORDS_BIG_ENDIAN) | |
5792 | { | |
5793 | rtx tmp; | |
5794 | tmp = highword; highword = lowword; lowword = tmp; | |
5795 | } | |
5796 | ||
5797 | emit_insn (gen_xorsi3 (operands[6], operands[1], | |
5798 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); | |
5799 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); | |
5800 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5801 | emit_move_insn (operands[5], operands[4]); | |
5802 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5803 | DONE; | |
208c89ce | 5804 | }") |
802a0058 | 5805 | |
a3170dc6 AH |
5806 | (define_expand "floatunssisf2" |
5807 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5808 | (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5809 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5810 | "") | |
5811 | ||
802a0058 MM |
5812 | (define_expand "floatunssidf2" |
5813 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5814 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5815 | (use (match_dup 2)) | |
5816 | (use (match_dup 3)) | |
a7df97e6 | 5817 | (clobber (match_dup 4)) |
9ebbca7d | 5818 | (clobber (match_dup 5))])] |
a3170dc6 | 5819 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5820 | " |
5821 | { | |
05d49501 AM |
5822 | if (TARGET_POWERPC64) |
5823 | { | |
5824 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5825 | rtx t1 = gen_reg_rtx (DImode); | |
5826 | rtx t2 = gen_reg_rtx (DImode); | |
5827 | emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, | |
5828 | t1, t2)); | |
5829 | DONE; | |
5830 | } | |
5831 | ||
802a0058 | 5832 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5833 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); |
9ebbca7d GK |
5834 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5835 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5836 | }") |
5837 | ||
802a0058 MM |
5838 | (define_insn "*floatunssidf2_internal" |
5839 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5840 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5841 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5842 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5843 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 | 5844 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] |
a3170dc6 | 5845 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5846 | "#" |
a7df97e6 | 5847 | [(set_attr "length" "20")]) |
802a0058 MM |
5848 | |
5849 | (define_split | |
5850 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5851 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5852 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5853 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5854 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5855 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
a3170dc6 | 5856 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5857 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5858 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5859 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5860 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5861 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5862 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
5863 | " | |
802a0058 | 5864 | { |
9ebbca7d GK |
5865 | rtx lowword, highword; |
5866 | if (GET_CODE (operands[4]) != MEM) | |
5867 | abort(); | |
5868 | highword = XEXP (operands[4], 0); | |
5869 | lowword = plus_constant (highword, 4); | |
5870 | if (! WORDS_BIG_ENDIAN) | |
f6968f59 | 5871 | { |
9ebbca7d GK |
5872 | rtx tmp; |
5873 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5874 | } |
802a0058 | 5875 | |
9ebbca7d GK |
5876 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); |
5877 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5878 | emit_move_insn (operands[5], operands[4]); | |
5879 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5880 | DONE; | |
5881 | }") | |
1fd4e8c1 | 5882 | |
1fd4e8c1 | 5883 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
5884 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5885 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5886 | (clobber (match_dup 2)) | |
9ebbca7d | 5887 | (clobber (match_dup 3))])] |
a3170dc6 | 5888 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5889 | " |
5890 | { | |
802a0058 | 5891 | operands[2] = gen_reg_rtx (DImode); |
9ebbca7d | 5892 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5893 | }") |
5894 | ||
802a0058 MM |
5895 | (define_insn "*fix_truncdfsi2_internal" |
5896 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5897 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
e3485bbc | 5898 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) |
9ebbca7d | 5899 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
a3170dc6 | 5900 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5901 | "#" |
9ebbca7d | 5902 | [(set_attr "length" "16")]) |
802a0058 MM |
5903 | |
5904 | (define_split | |
5905 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
75540af0 | 5906 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
802a0058 | 5907 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
9ebbca7d | 5908 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] |
a3170dc6 | 5909 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d | 5910 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
75540af0 | 5911 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
9ebbca7d GK |
5912 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
5913 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] | |
5914 | " | |
802a0058 | 5915 | { |
9ebbca7d GK |
5916 | rtx lowword; |
5917 | if (GET_CODE (operands[3]) != MEM) | |
5918 | abort(); | |
5919 | lowword = XEXP (operands[3], 0); | |
5920 | if (WORDS_BIG_ENDIAN) | |
5921 | lowword = plus_constant (lowword, 4); | |
802a0058 | 5922 | |
9ebbca7d GK |
5923 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5924 | emit_move_insn (operands[3], operands[2]); | |
5925 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
5926 | DONE; | |
5927 | }") | |
802a0058 | 5928 | |
9ebbca7d GK |
5929 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10)) |
5930 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) | |
5931 | ; because the first makes it clear that operand 0 is not live | |
5932 | ; before the instruction. | |
5933 | (define_insn "fctiwz" | |
61c07d3c | 5934 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
9ebbca7d | 5935 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))] |
a3170dc6 | 5936 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
a260abc9 DE |
5937 | "{fcirz|fctiwz} %0,%1" |
5938 | [(set_attr "type" "fp")]) | |
5939 | ||
a3170dc6 AH |
5940 | (define_expand "floatsisf2" |
5941 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5942 | (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5943 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5944 | "") | |
5945 | ||
a473029f RK |
5946 | (define_insn "floatdidf2" |
5947 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 5948 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] |
a3170dc6 | 5949 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5950 | "fcfid %0,%1" |
5951 | [(set_attr "type" "fp")]) | |
5952 | ||
05d49501 AM |
5953 | (define_insn_and_split "floatsidf_ppc64" |
5954 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5955 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5956 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5957 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5958 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5959 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 AM |
5960 | "#" |
5961 | "" | |
5962 | [(set (match_dup 3) (sign_extend:DI (match_dup 1))) | |
5963 | (set (match_dup 2) (match_dup 3)) | |
5964 | (set (match_dup 4) (match_dup 2)) | |
5965 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5966 | "") | |
5967 | ||
5968 | (define_insn_and_split "floatunssidf_ppc64" | |
5969 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5970 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5971 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5972 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5973 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5974 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 AM |
5975 | "#" |
5976 | "" | |
5977 | [(set (match_dup 3) (zero_extend:DI (match_dup 1))) | |
5978 | (set (match_dup 2) (match_dup 3)) | |
5979 | (set (match_dup 4) (match_dup 2)) | |
5980 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5981 | "") | |
5982 | ||
a473029f | 5983 | (define_insn "fix_truncdfdi2" |
61c07d3c | 5984 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
a473029f | 5985 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] |
a3170dc6 | 5986 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5987 | "fctidz %0,%1" |
5988 | [(set_attr "type" "fp")]) | |
ea112fc4 | 5989 | |
678b7733 AM |
5990 | (define_expand "floatdisf2" |
5991 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5992 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] | |
5993 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" | |
5994 | " | |
5995 | { | |
5996 | if (!flag_unsafe_math_optimizations) | |
5997 | { | |
5998 | rtx label = gen_label_rtx (); | |
5999 | emit_insn (gen_floatdisf2_internal2 (operands[1], label)); | |
6000 | emit_label (label); | |
6001 | } | |
6002 | emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1])); | |
6003 | DONE; | |
6004 | }") | |
6005 | ||
6006 | ;; This is not IEEE compliant if rounding mode is "round to nearest". | |
6007 | ;; If the DI->DF conversion is inexact, then it's possible to suffer | |
6008 | ;; from double rounding. | |
6009 | (define_insn_and_split "floatdisf2_internal1" | |
ea112fc4 | 6010 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
61c07d3c | 6011 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 | 6012 | (clobber (match_scratch:DF 2 "=f"))] |
678b7733 | 6013 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ea112fc4 DE |
6014 | "#" |
6015 | "&& reload_completed" | |
6016 | [(set (match_dup 2) | |
6017 | (float:DF (match_dup 1))) | |
6018 | (set (match_dup 0) | |
6019 | (float_truncate:SF (match_dup 2)))] | |
6020 | "") | |
678b7733 AM |
6021 | |
6022 | ;; Twiddles bits to avoid double rounding. | |
b6d08ca1 | 6023 | ;; Bits that might be truncated when converting to DFmode are replaced |
678b7733 AM |
6024 | ;; by a bit that won't be lost at that stage, but is below the SFmode |
6025 | ;; rounding position. | |
6026 | (define_expand "floatdisf2_internal2" | |
42a6388c AM |
6027 | [(parallel [(set (match_dup 4) |
6028 | (compare:CC (and:DI (match_operand:DI 0 "" "") | |
6029 | (const_int 2047)) | |
6030 | (const_int 0))) | |
6031 | (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047))) | |
6032 | (clobber (match_scratch:CC 7 ""))]) | |
678b7733 AM |
6033 | (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53))) |
6034 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1))) | |
6035 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
6036 | (label_ref (match_operand:DI 1 "" "")) | |
6037 | (pc))) | |
6038 | (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2))) | |
6039 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
6040 | (label_ref (match_dup 1)) | |
6041 | (pc))) | |
6042 | (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2))) | |
6043 | (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))] | |
6044 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" | |
6045 | " | |
6046 | { | |
6047 | operands[2] = gen_reg_rtx (DImode); | |
6048 | operands[3] = gen_reg_rtx (DImode); | |
6049 | operands[4] = gen_reg_rtx (CCmode); | |
6050 | operands[5] = gen_reg_rtx (CCUNSmode); | |
6051 | }") | |
1fd4e8c1 RK |
6052 | \f |
6053 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
6054 | ;; of instructions. The & constraints are to prevent the register |
6055 | ;; allocator from allocating registers that overlap with the inputs | |
6056 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 6057 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 6058 | |
266eb58a | 6059 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
6060 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
6061 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
6062 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 6063 | "! TARGET_POWERPC64" |
0f645302 MM |
6064 | "* |
6065 | { | |
6066 | if (WORDS_BIG_ENDIAN) | |
6067 | return (GET_CODE (operands[2])) != CONST_INT | |
6068 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
6069 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
6070 | else | |
6071 | return (GET_CODE (operands[2])) != CONST_INT | |
6072 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
6073 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
6074 | }" | |
b19003d8 | 6075 | [(set_attr "length" "8")]) |
1fd4e8c1 | 6076 | |
266eb58a | 6077 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
6078 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
6079 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
6080 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 6081 | "! TARGET_POWERPC64" |
5502823b RK |
6082 | "* |
6083 | { | |
0f645302 MM |
6084 | if (WORDS_BIG_ENDIAN) |
6085 | return (GET_CODE (operands[1]) != CONST_INT) | |
6086 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
6087 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
6088 | else | |
6089 | return (GET_CODE (operands[1]) != CONST_INT) | |
6090 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
6091 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 6092 | }" |
ca7f5001 RK |
6093 | [(set_attr "length" "8")]) |
6094 | ||
266eb58a | 6095 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
6096 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
6097 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 6098 | "! TARGET_POWERPC64" |
5502823b RK |
6099 | "* |
6100 | { | |
6101 | return (WORDS_BIG_ENDIAN) | |
6102 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
6103 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
6104 | }" | |
ca7f5001 RK |
6105 | [(set_attr "length" "8")]) |
6106 | ||
8ffd9c51 RK |
6107 | (define_expand "mulsidi3" |
6108 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6109 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
6110 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 6111 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
6112 | " |
6113 | { | |
6114 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
6115 | { | |
39403d82 DE |
6116 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
6117 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 6118 | emit_insn (gen_mull_call ()); |
cf27b467 | 6119 | if (WORDS_BIG_ENDIAN) |
39403d82 | 6120 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
6121 | else |
6122 | { | |
6123 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 6124 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 6125 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 6126 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 6127 | } |
8ffd9c51 RK |
6128 | DONE; |
6129 | } | |
6130 | else if (TARGET_POWER) | |
6131 | { | |
6132 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
6133 | DONE; | |
6134 | } | |
6135 | }") | |
deb9225a | 6136 | |
8ffd9c51 | 6137 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 6138 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 6139 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 6140 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 6141 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 6142 | "TARGET_POWER" |
b19003d8 | 6143 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
6144 | [(set_attr "type" "imul") |
6145 | (set_attr "length" "8")]) | |
deb9225a | 6146 | |
f192bf8b | 6147 | (define_insn "*mulsidi3_no_mq" |
425c176f | 6148 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
6149 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
6150 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 6151 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
6152 | "* |
6153 | { | |
6154 | return (WORDS_BIG_ENDIAN) | |
6155 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
6156 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
6157 | }" | |
8ffd9c51 RK |
6158 | [(set_attr "type" "imul") |
6159 | (set_attr "length" "8")]) | |
deb9225a | 6160 | |
ebedb4dd MM |
6161 | (define_split |
6162 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6163 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
6164 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 6165 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
6166 | [(set (match_dup 3) |
6167 | (truncate:SI | |
6168 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
6169 | (sign_extend:DI (match_dup 2))) | |
6170 | (const_int 32)))) | |
6171 | (set (match_dup 4) | |
6172 | (mult:SI (match_dup 1) | |
6173 | (match_dup 2)))] | |
6174 | " | |
6175 | { | |
6176 | int endian = (WORDS_BIG_ENDIAN == 0); | |
6177 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
6178 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
6179 | }") | |
6180 | ||
f192bf8b DE |
6181 | (define_expand "umulsidi3" |
6182 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6183 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
6184 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
6185 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
6186 | " | |
6187 | { | |
6188 | if (TARGET_POWER) | |
6189 | { | |
6190 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
6191 | DONE; | |
6192 | } | |
6193 | }") | |
6194 | ||
6195 | (define_insn "umulsidi3_mq" | |
6196 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
6197 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
6198 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
6199 | (clobber (match_scratch:SI 3 "=q"))] | |
6200 | "TARGET_POWERPC && TARGET_POWER" | |
6201 | "* | |
6202 | { | |
6203 | return (WORDS_BIG_ENDIAN) | |
6204 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
6205 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
6206 | }" | |
6207 | [(set_attr "type" "imul") | |
6208 | (set_attr "length" "8")]) | |
6209 | ||
6210 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
6211 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
6212 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
6213 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 6214 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
6215 | "* |
6216 | { | |
6217 | return (WORDS_BIG_ENDIAN) | |
6218 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
6219 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
6220 | }" | |
6221 | [(set_attr "type" "imul") | |
6222 | (set_attr "length" "8")]) | |
6223 | ||
ebedb4dd MM |
6224 | (define_split |
6225 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6226 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
6227 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 6228 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
6229 | [(set (match_dup 3) |
6230 | (truncate:SI | |
6231 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
6232 | (zero_extend:DI (match_dup 2))) | |
6233 | (const_int 32)))) | |
6234 | (set (match_dup 4) | |
6235 | (mult:SI (match_dup 1) | |
6236 | (match_dup 2)))] | |
6237 | " | |
6238 | { | |
6239 | int endian = (WORDS_BIG_ENDIAN == 0); | |
6240 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
6241 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
6242 | }") | |
6243 | ||
8ffd9c51 RK |
6244 | (define_expand "smulsi3_highpart" |
6245 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
6246 | (truncate:SI | |
6247 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
6248 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
6249 | (sign_extend:DI | |
6250 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
6251 | (const_int 32))))] | |
6252 | "" | |
6253 | " | |
6254 | { | |
6255 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
6256 | { | |
39403d82 DE |
6257 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
6258 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 6259 | emit_insn (gen_mulh_call ()); |
39403d82 | 6260 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
6261 | DONE; |
6262 | } | |
6263 | else if (TARGET_POWER) | |
6264 | { | |
6265 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
6266 | DONE; | |
6267 | } | |
6268 | }") | |
deb9225a | 6269 | |
8ffd9c51 RK |
6270 | (define_insn "smulsi3_highpart_mq" |
6271 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6272 | (truncate:SI | |
fada905b MM |
6273 | (lshiftrt:DI (mult:DI (sign_extend:DI |
6274 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
6275 | (sign_extend:DI | |
6276 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
6277 | (const_int 32)))) |
6278 | (clobber (match_scratch:SI 3 "=q"))] | |
6279 | "TARGET_POWER" | |
6280 | "mul %0,%1,%2" | |
6281 | [(set_attr "type" "imul")]) | |
deb9225a | 6282 | |
f192bf8b | 6283 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
6284 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6285 | (truncate:SI | |
fada905b MM |
6286 | (lshiftrt:DI (mult:DI (sign_extend:DI |
6287 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
6288 | (sign_extend:DI | |
6289 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 6290 | (const_int 32))))] |
f192bf8b | 6291 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
6292 | "mulhw %0,%1,%2" |
6293 | [(set_attr "type" "imul")]) | |
deb9225a | 6294 | |
f192bf8b DE |
6295 | (define_expand "umulsi3_highpart" |
6296 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
6297 | (truncate:SI | |
6298 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
6299 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
6300 | (zero_extend:DI | |
6301 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
6302 | (const_int 32))))] | |
6303 | "TARGET_POWERPC" | |
6304 | " | |
6305 | { | |
6306 | if (TARGET_POWER) | |
6307 | { | |
6308 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
6309 | DONE; | |
6310 | } | |
6311 | }") | |
6312 | ||
6313 | (define_insn "umulsi3_highpart_mq" | |
6314 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6315 | (truncate:SI | |
6316 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
6317 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
6318 | (zero_extend:DI | |
6319 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
6320 | (const_int 32)))) | |
6321 | (clobber (match_scratch:SI 3 "=q"))] | |
6322 | "TARGET_POWERPC && TARGET_POWER" | |
6323 | "mulhwu %0,%1,%2" | |
6324 | [(set_attr "type" "imul")]) | |
6325 | ||
6326 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
6327 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6328 | (truncate:SI | |
6329 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
6330 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
6331 | (zero_extend:DI | |
6332 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
6333 | (const_int 32))))] | |
f192bf8b | 6334 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
6335 | "mulhwu %0,%1,%2" |
6336 | [(set_attr "type" "imul")]) | |
6337 | ||
6338 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
6339 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
6340 | ;; why we have the strange constraints below. | |
6341 | (define_insn "ashldi3_power" | |
6342 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
6343 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
6344 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
6345 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
6346 | "TARGET_POWER" | |
6347 | "@ | |
6348 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
6349 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
6350 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
6351 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
6352 | [(set_attr "length" "8")]) | |
6353 | ||
6354 | (define_insn "lshrdi3_power" | |
47ad8c61 | 6355 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
6356 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
6357 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
6358 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
6359 | "TARGET_POWER" | |
6360 | "@ | |
47ad8c61 | 6361 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
6362 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
6363 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
6364 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
6365 | [(set_attr "length" "8")]) | |
6366 | ||
6367 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
6368 | ;; just handle shifts by constants. | |
6369 | (define_insn "ashrdi3_power" | |
7093ddee | 6370 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
6371 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6372 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
6373 | (clobber (match_scratch:SI 3 "=X,q"))] | |
6374 | "TARGET_POWER" | |
6375 | "@ | |
6376 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
6377 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
6378 | [(set_attr "length" "8")]) | |
4aa74a4f FS |
6379 | |
6380 | (define_insn "ashrdi3_no_power" | |
6381 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") | |
6382 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6383 | (match_operand:SI 2 "const_int_operand" "M,i")))] | |
6384 | "TARGET_32BIT && !TARGET_POWER" | |
6385 | "@ | |
6386 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
6387 | {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" | |
6388 | [(set_attr "length" "8,12")]) | |
266eb58a DE |
6389 | \f |
6390 | ;; PowerPC64 DImode operations. | |
6391 | ||
6392 | (define_expand "adddi3" | |
6393 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6394 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6395 | (match_operand:DI 2 "reg_or_add_cint64_operand" "")))] |
266eb58a DE |
6396 | "" |
6397 | " | |
6398 | { | |
a260abc9 DE |
6399 | if (! TARGET_POWERPC64) |
6400 | { | |
6401 | if (non_short_cint_operand (operands[2], DImode)) | |
6402 | FAIL; | |
6403 | } | |
6404 | else | |
6405 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 6406 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 6407 | { |
677a9668 | 6408 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
6409 | ? operands[0] : gen_reg_rtx (DImode)); |
6410 | ||
2bfcf297 | 6411 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 6412 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 6413 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
a260abc9 | 6414 | |
2bfcf297 DB |
6415 | if (!CONST_OK_FOR_LETTER_P (rest, 'L')) |
6416 | FAIL; | |
a260abc9 | 6417 | |
2bfcf297 DB |
6418 | /* The ordering here is important for the prolog expander. |
6419 | When space is allocated from the stack, adding 'low' first may | |
6420 | produce a temporary deallocation (which would be bad). */ | |
6421 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest))); | |
a260abc9 DE |
6422 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); |
6423 | DONE; | |
6424 | } | |
266eb58a DE |
6425 | }") |
6426 | ||
6427 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
6428 | ;; allowing register zero as source. | |
6429 | ||
a260abc9 | 6430 | (define_insn "*adddi3_internal1" |
266eb58a DE |
6431 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
6432 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 6433 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
6434 | "TARGET_POWERPC64" |
6435 | "@ | |
6436 | add %0,%1,%2 | |
6437 | addi %0,%1,%2 | |
6438 | addic %0,%1,%2 | |
802a0058 | 6439 | addis %0,%1,%v2") |
266eb58a | 6440 | |
a260abc9 | 6441 | (define_insn "*adddi3_internal2" |
9ebbca7d GK |
6442 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
6443 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
6444 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 6445 | (const_int 0))) |
9ebbca7d | 6446 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
266eb58a DE |
6447 | "TARGET_POWERPC64" |
6448 | "@ | |
6449 | add. %3,%1,%2 | |
9ebbca7d GK |
6450 | addic. %3,%1,%2 |
6451 | # | |
6452 | #" | |
6453 | [(set_attr "type" "compare") | |
6454 | (set_attr "length" "4,4,8,8")]) | |
6455 | ||
6456 | (define_split | |
6457 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6458 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6459 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
6460 | (const_int 0))) | |
6461 | (clobber (match_scratch:DI 3 ""))] | |
6462 | "TARGET_POWERPC64 && reload_completed" | |
6463 | [(set (match_dup 3) | |
6464 | (plus:DI (match_dup 1) (match_dup 2))) | |
6465 | (set (match_dup 0) | |
6466 | (compare:CC (match_dup 3) | |
6467 | (const_int 0)))] | |
6468 | "") | |
266eb58a | 6469 | |
a260abc9 | 6470 | (define_insn "*adddi3_internal3" |
9ebbca7d GK |
6471 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
6472 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
6473 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 6474 | (const_int 0))) |
9ebbca7d | 6475 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
266eb58a DE |
6476 | (plus:DI (match_dup 1) (match_dup 2)))] |
6477 | "TARGET_POWERPC64" | |
6478 | "@ | |
6479 | add. %0,%1,%2 | |
9ebbca7d GK |
6480 | addic. %0,%1,%2 |
6481 | # | |
6482 | #" | |
6483 | [(set_attr "type" "compare") | |
6484 | (set_attr "length" "4,4,8,8")]) | |
6485 | ||
6486 | (define_split | |
6487 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6488 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6489 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
6490 | (const_int 0))) | |
6491 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6492 | (plus:DI (match_dup 1) (match_dup 2)))] | |
6493 | "TARGET_POWERPC64 && reload_completed" | |
6494 | [(set (match_dup 0) | |
6495 | (plus:DI (match_dup 1) (match_dup 2))) | |
6496 | (set (match_dup 3) | |
6497 | (compare:CC (match_dup 0) | |
6498 | (const_int 0)))] | |
6499 | "") | |
266eb58a DE |
6500 | |
6501 | ;; Split an add that we can't do in one insn into two insns, each of which | |
6502 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
6503 | ;; add should be last in case the result gets used in an address. | |
6504 | ||
6505 | (define_split | |
6506 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6507 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6508 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
6509 | "TARGET_POWERPC64" | |
6510 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
6511 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
6512 | " | |
6513 | { | |
2bfcf297 | 6514 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 6515 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 6516 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
266eb58a | 6517 | |
2bfcf297 DB |
6518 | operands[4] = GEN_INT (low); |
6519 | if (CONST_OK_FOR_LETTER_P (rest, 'L')) | |
6520 | operands[3] = GEN_INT (rest); | |
6521 | else if (! no_new_pseudos) | |
38886f37 | 6522 | { |
2bfcf297 DB |
6523 | operands[3] = gen_reg_rtx (DImode); |
6524 | emit_move_insn (operands[3], operands[2]); | |
6525 | emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); | |
6526 | DONE; | |
38886f37 | 6527 | } |
2bfcf297 DB |
6528 | else |
6529 | FAIL; | |
266eb58a DE |
6530 | }") |
6531 | ||
6532 | (define_insn "one_cmpldi2" | |
6533 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6534 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6535 | "TARGET_POWERPC64" | |
6536 | "nor %0,%1,%1") | |
6537 | ||
6538 | (define_insn "" | |
9ebbca7d GK |
6539 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6540 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 6541 | (const_int 0))) |
9ebbca7d | 6542 | (clobber (match_scratch:DI 2 "=r,r"))] |
266eb58a | 6543 | "TARGET_POWERPC64" |
9ebbca7d GK |
6544 | "@ |
6545 | nor. %2,%1,%1 | |
6546 | #" | |
6547 | [(set_attr "type" "compare") | |
6548 | (set_attr "length" "4,8")]) | |
6549 | ||
6550 | (define_split | |
6551 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6552 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6553 | (const_int 0))) | |
6554 | (clobber (match_scratch:DI 2 ""))] | |
6555 | "TARGET_POWERPC64 && reload_completed" | |
6556 | [(set (match_dup 2) | |
6557 | (not:DI (match_dup 1))) | |
6558 | (set (match_dup 0) | |
6559 | (compare:CC (match_dup 2) | |
6560 | (const_int 0)))] | |
6561 | "") | |
266eb58a DE |
6562 | |
6563 | (define_insn "" | |
9ebbca7d GK |
6564 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
6565 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 6566 | (const_int 0))) |
9ebbca7d | 6567 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6568 | (not:DI (match_dup 1)))] |
6569 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6570 | "@ |
6571 | nor. %0,%1,%1 | |
6572 | #" | |
6573 | [(set_attr "type" "compare") | |
6574 | (set_attr "length" "4,8")]) | |
6575 | ||
6576 | (define_split | |
6577 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
6578 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6579 | (const_int 0))) | |
6580 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6581 | (not:DI (match_dup 1)))] | |
6582 | "TARGET_POWERPC64 && reload_completed" | |
6583 | [(set (match_dup 0) | |
6584 | (not:DI (match_dup 1))) | |
6585 | (set (match_dup 2) | |
6586 | (compare:CC (match_dup 0) | |
6587 | (const_int 0)))] | |
6588 | "") | |
266eb58a DE |
6589 | |
6590 | (define_insn "" | |
6591 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6592 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
6593 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
6594 | "TARGET_POWERPC64" | |
6595 | "@ | |
6596 | subf %0,%2,%1 | |
6597 | subfic %0,%2,%1") | |
6598 | ||
6599 | (define_insn "" | |
9ebbca7d GK |
6600 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6601 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6602 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 6603 | (const_int 0))) |
9ebbca7d | 6604 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6605 | "TARGET_POWERPC64" |
9ebbca7d GK |
6606 | "@ |
6607 | subf. %3,%2,%1 | |
6608 | #" | |
6609 | [(set_attr "type" "compare") | |
6610 | (set_attr "length" "4,8")]) | |
6611 | ||
6612 | (define_split | |
6613 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6614 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6615 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6616 | (const_int 0))) | |
6617 | (clobber (match_scratch:DI 3 ""))] | |
6618 | "TARGET_POWERPC64 && reload_completed" | |
6619 | [(set (match_dup 3) | |
6620 | (minus:DI (match_dup 1) (match_dup 2))) | |
6621 | (set (match_dup 0) | |
6622 | (compare:CC (match_dup 3) | |
6623 | (const_int 0)))] | |
6624 | "") | |
266eb58a DE |
6625 | |
6626 | (define_insn "" | |
9ebbca7d GK |
6627 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6628 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6629 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 6630 | (const_int 0))) |
9ebbca7d | 6631 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6632 | (minus:DI (match_dup 1) (match_dup 2)))] |
6633 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6634 | "@ |
6635 | subf. %0,%2,%1 | |
6636 | #" | |
6637 | [(set_attr "type" "compare") | |
6638 | (set_attr "length" "4,8")]) | |
6639 | ||
6640 | (define_split | |
6641 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6642 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6643 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6644 | (const_int 0))) | |
6645 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6646 | (minus:DI (match_dup 1) (match_dup 2)))] | |
6647 | "TARGET_POWERPC64 && reload_completed" | |
6648 | [(set (match_dup 0) | |
6649 | (minus:DI (match_dup 1) (match_dup 2))) | |
6650 | (set (match_dup 3) | |
6651 | (compare:CC (match_dup 0) | |
6652 | (const_int 0)))] | |
6653 | "") | |
266eb58a DE |
6654 | |
6655 | (define_expand "subdi3" | |
6656 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6657 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
2bfcf297 | 6658 | (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))] |
266eb58a DE |
6659 | "" |
6660 | " | |
6661 | { | |
6662 | if (GET_CODE (operands[2]) == CONST_INT) | |
6663 | { | |
6664 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
6665 | negate_rtx (DImode, operands[2]))); | |
6666 | DONE; | |
6667 | } | |
6668 | }") | |
6669 | ||
ea112fc4 | 6670 | (define_insn_and_split "absdi2" |
266eb58a | 6671 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 6672 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) |
266eb58a DE |
6673 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
6674 | "TARGET_POWERPC64" | |
ea112fc4 DE |
6675 | "#" |
6676 | "&& reload_completed" | |
a260abc9 | 6677 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6678 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 6679 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
6680 | "") |
6681 | ||
ea112fc4 | 6682 | (define_insn_and_split "*nabsdi2" |
266eb58a | 6683 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 6684 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) |
266eb58a DE |
6685 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
6686 | "TARGET_POWERPC64" | |
ea112fc4 DE |
6687 | "#" |
6688 | "&& reload_completed" | |
a260abc9 | 6689 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6690 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 6691 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
6692 | "") |
6693 | ||
6694 | (define_expand "negdi2" | |
6695 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6696 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
6697 | "" | |
6698 | "") | |
6699 | ||
6700 | (define_insn "" | |
6701 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6702 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6703 | "TARGET_POWERPC64" | |
6704 | "neg %0,%1") | |
6705 | ||
6706 | (define_insn "" | |
9ebbca7d GK |
6707 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6708 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 6709 | (const_int 0))) |
9ebbca7d | 6710 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 6711 | "TARGET_POWERPC64" |
9ebbca7d GK |
6712 | "@ |
6713 | neg. %2,%1 | |
6714 | #" | |
6715 | [(set_attr "type" "compare") | |
6716 | (set_attr "length" "4,8")]) | |
6717 | ||
6718 | (define_split | |
6719 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6720 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6721 | (const_int 0))) | |
6722 | (clobber (match_scratch:DI 2 ""))] | |
6723 | "TARGET_POWERPC64 && reload_completed" | |
6724 | [(set (match_dup 2) | |
6725 | (neg:DI (match_dup 1))) | |
6726 | (set (match_dup 0) | |
6727 | (compare:CC (match_dup 2) | |
6728 | (const_int 0)))] | |
6729 | "") | |
815cdc52 | 6730 | |
29ae5b89 | 6731 | (define_insn "" |
9ebbca7d GK |
6732 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
6733 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 6734 | (const_int 0))) |
9ebbca7d | 6735 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 6736 | (neg:DI (match_dup 1)))] |
29ae5b89 | 6737 | "TARGET_POWERPC64" |
9ebbca7d GK |
6738 | "@ |
6739 | neg. %0,%1 | |
6740 | #" | |
6741 | [(set_attr "type" "compare") | |
6742 | (set_attr "length" "4,8")]) | |
6743 | ||
6744 | (define_split | |
6745 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
6746 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6747 | (const_int 0))) | |
6748 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6749 | (neg:DI (match_dup 1)))] | |
6750 | "TARGET_POWERPC64 && reload_completed" | |
6751 | [(set (match_dup 0) | |
6752 | (neg:DI (match_dup 1))) | |
6753 | (set (match_dup 2) | |
6754 | (compare:CC (match_dup 0) | |
6755 | (const_int 0)))] | |
6756 | "") | |
266eb58a | 6757 | |
1b1edcfa DE |
6758 | (define_insn "clzdi2" |
6759 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6760 | (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6761 | "TARGET_POWERPC64" | |
6762 | "cntlzd %0,%1") | |
6763 | ||
6764 | (define_expand "ctzdi2" | |
4977bab6 | 6765 | [(set (match_dup 2) |
1b1edcfa | 6766 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) |
4977bab6 | 6767 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) |
1b1edcfa DE |
6768 | (match_dup 2))) |
6769 | (clobber (scratch:CC))]) | |
d865b122 | 6770 | (set (match_dup 4) (clz:DI (match_dup 3))) |
4977bab6 | 6771 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 6772 | (minus:DI (const_int 63) (match_dup 4)))] |
266eb58a | 6773 | "TARGET_POWERPC64" |
4977bab6 ZW |
6774 | { |
6775 | operands[2] = gen_reg_rtx (DImode); | |
6776 | operands[3] = gen_reg_rtx (DImode); | |
6777 | operands[4] = gen_reg_rtx (DImode); | |
6778 | }) | |
6779 | ||
1b1edcfa DE |
6780 | (define_expand "ffsdi2" |
6781 | [(set (match_dup 2) | |
6782 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
6783 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) | |
6784 | (match_dup 2))) | |
6785 | (clobber (scratch:CC))]) | |
6786 | (set (match_dup 4) (clz:DI (match_dup 3))) | |
6787 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6788 | (minus:DI (const_int 64) (match_dup 4)))] | |
4977bab6 | 6789 | "TARGET_POWERPC64" |
1b1edcfa DE |
6790 | { |
6791 | operands[2] = gen_reg_rtx (DImode); | |
6792 | operands[3] = gen_reg_rtx (DImode); | |
6793 | operands[4] = gen_reg_rtx (DImode); | |
6794 | }) | |
266eb58a DE |
6795 | |
6796 | (define_insn "muldi3" | |
6797 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6798 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
6799 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6800 | "TARGET_POWERPC64" | |
6801 | "mulld %0,%1,%2" | |
3cb999d8 | 6802 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6803 | |
6804 | (define_insn "smuldi3_highpart" | |
6805 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6806 | (truncate:DI | |
6807 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
6808 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6809 | (sign_extend:TI | |
6810 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6811 | (const_int 64))))] | |
6812 | "TARGET_POWERPC64" | |
6813 | "mulhd %0,%1,%2" | |
3cb999d8 | 6814 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6815 | |
6816 | (define_insn "umuldi3_highpart" | |
6817 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6818 | (truncate:DI | |
6819 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
6820 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6821 | (zero_extend:TI | |
6822 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6823 | (const_int 64))))] | |
6824 | "TARGET_POWERPC64" | |
6825 | "mulhdu %0,%1,%2" | |
3cb999d8 | 6826 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6827 | |
6828 | (define_expand "divdi3" | |
6829 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6830 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6831 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6832 | "TARGET_POWERPC64" | |
6833 | " | |
6834 | { | |
6835 | if (GET_CODE (operands[2]) == CONST_INT | |
2bfcf297 | 6836 | && INTVAL (operands[2]) > 0 |
266eb58a DE |
6837 | && exact_log2 (INTVAL (operands[2])) >= 0) |
6838 | ; | |
6839 | else | |
6840 | operands[2] = force_reg (DImode, operands[2]); | |
6841 | }") | |
6842 | ||
6843 | (define_expand "moddi3" | |
6844 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6845 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6846 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6847 | "TARGET_POWERPC64" | |
6848 | " | |
6849 | { | |
2bfcf297 | 6850 | int i; |
266eb58a DE |
6851 | rtx temp1; |
6852 | rtx temp2; | |
6853 | ||
2bfcf297 DB |
6854 | if (GET_CODE (operands[2]) != CONST_INT |
6855 | || INTVAL (operands[2]) <= 0 | |
6856 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) | |
266eb58a DE |
6857 | FAIL; |
6858 | ||
6859 | temp1 = gen_reg_rtx (DImode); | |
6860 | temp2 = gen_reg_rtx (DImode); | |
6861 | ||
6862 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6863 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6864 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6865 | DONE; | |
6866 | }") | |
6867 | ||
6868 | (define_insn "" | |
6869 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6870 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
6871 | (match_operand:DI 2 "exact_log2_cint_operand" "N")))] |
6872 | "TARGET_POWERPC64" | |
266eb58a DE |
6873 | "sradi %0,%1,%p2\;addze %0,%0" |
6874 | [(set_attr "length" "8")]) | |
6875 | ||
6876 | (define_insn "" | |
9ebbca7d GK |
6877 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6878 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6879 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6880 | (const_int 0))) |
9ebbca7d | 6881 | (clobber (match_scratch:DI 3 "=r,r"))] |
2bfcf297 | 6882 | "TARGET_POWERPC64" |
9ebbca7d GK |
6883 | "@ |
6884 | sradi %3,%1,%p2\;addze. %3,%3 | |
6885 | #" | |
266eb58a | 6886 | [(set_attr "type" "compare") |
9ebbca7d GK |
6887 | (set_attr "length" "8,12")]) |
6888 | ||
6889 | (define_split | |
6890 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6891 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6892 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6893 | (const_int 0))) |
6894 | (clobber (match_scratch:DI 3 ""))] | |
2bfcf297 | 6895 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6896 | [(set (match_dup 3) |
6897 | (div:DI (match_dup 1) (match_dup 2))) | |
6898 | (set (match_dup 0) | |
6899 | (compare:CC (match_dup 3) | |
6900 | (const_int 0)))] | |
6901 | "") | |
266eb58a DE |
6902 | |
6903 | (define_insn "" | |
9ebbca7d GK |
6904 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6905 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6906 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6907 | (const_int 0))) |
9ebbca7d | 6908 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6909 | (div:DI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 6910 | "TARGET_POWERPC64" |
9ebbca7d GK |
6911 | "@ |
6912 | sradi %0,%1,%p2\;addze. %0,%0 | |
6913 | #" | |
266eb58a | 6914 | [(set_attr "type" "compare") |
9ebbca7d | 6915 | (set_attr "length" "8,12")]) |
266eb58a | 6916 | |
9ebbca7d GK |
6917 | (define_split |
6918 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6919 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6920 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6921 | (const_int 0))) |
6922 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6923 | (div:DI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 6924 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6925 | [(set (match_dup 0) |
6926 | (div:DI (match_dup 1) (match_dup 2))) | |
6927 | (set (match_dup 3) | |
6928 | (compare:CC (match_dup 0) | |
6929 | (const_int 0)))] | |
6930 | "") | |
6931 | ||
6932 | (define_insn "" | |
6933 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6934 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6935 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6936 | "TARGET_POWERPC64" |
6937 | "divd %0,%1,%2" | |
3cb999d8 | 6938 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6939 | |
6940 | (define_insn "udivdi3" | |
6941 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6942 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6943 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6944 | "TARGET_POWERPC64" | |
6945 | "divdu %0,%1,%2" | |
3cb999d8 | 6946 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6947 | |
6948 | (define_insn "rotldi3" | |
6949 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6950 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6951 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6952 | "TARGET_POWERPC64" | |
a66078ee | 6953 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6954 | |
a260abc9 | 6955 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6956 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6957 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6958 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6959 | (const_int 0))) |
9ebbca7d | 6960 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6961 | "TARGET_POWERPC64" |
9ebbca7d GK |
6962 | "@ |
6963 | rld%I2cl. %3,%1,%H2,0 | |
6964 | #" | |
6965 | [(set_attr "type" "delayed_compare") | |
6966 | (set_attr "length" "4,8")]) | |
6967 | ||
6968 | (define_split | |
6969 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6970 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6971 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6972 | (const_int 0))) | |
6973 | (clobber (match_scratch:DI 3 ""))] | |
6974 | "TARGET_POWERPC64 && reload_completed" | |
6975 | [(set (match_dup 3) | |
6976 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6977 | (set (match_dup 0) | |
6978 | (compare:CC (match_dup 3) | |
6979 | (const_int 0)))] | |
6980 | "") | |
266eb58a | 6981 | |
a260abc9 | 6982 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6983 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6984 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6985 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6986 | (const_int 0))) |
9ebbca7d | 6987 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6988 | (rotate:DI (match_dup 1) (match_dup 2)))] |
6989 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6990 | "@ |
6991 | rld%I2cl. %0,%1,%H2,0 | |
6992 | #" | |
6993 | [(set_attr "type" "delayed_compare") | |
6994 | (set_attr "length" "4,8")]) | |
6995 | ||
6996 | (define_split | |
6997 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6998 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6999 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
7000 | (const_int 0))) | |
7001 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7002 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
7003 | "TARGET_POWERPC64 && reload_completed" | |
7004 | [(set (match_dup 0) | |
7005 | (rotate:DI (match_dup 1) (match_dup 2))) | |
7006 | (set (match_dup 3) | |
7007 | (compare:CC (match_dup 0) | |
7008 | (const_int 0)))] | |
7009 | "") | |
266eb58a | 7010 | |
a260abc9 DE |
7011 | (define_insn "*rotldi3_internal4" |
7012 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
7013 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7014 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
ce71f754 | 7015 | (match_operand:DI 3 "mask64_operand" "n")))] |
a260abc9 DE |
7016 | "TARGET_POWERPC64" |
7017 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
7018 | ||
7019 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 7020 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 7021 | (compare:CC (and:DI |
9ebbca7d GK |
7022 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
7023 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 7024 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 7025 | (const_int 0))) |
9ebbca7d | 7026 | (clobber (match_scratch:DI 4 "=r,r"))] |
a260abc9 | 7027 | "TARGET_POWERPC64" |
9ebbca7d GK |
7028 | "@ |
7029 | rld%I2c%B3. %4,%1,%H2,%S3 | |
7030 | #" | |
7031 | [(set_attr "type" "delayed_compare") | |
7032 | (set_attr "length" "4,8")]) | |
7033 | ||
7034 | (define_split | |
7035 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7036 | (compare:CC (and:DI | |
7037 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7038 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
7039 | (match_operand:DI 3 "mask64_operand" "")) | |
7040 | (const_int 0))) | |
7041 | (clobber (match_scratch:DI 4 ""))] | |
7042 | "TARGET_POWERPC64 && reload_completed" | |
7043 | [(set (match_dup 4) | |
7044 | (and:DI (rotate:DI (match_dup 1) | |
7045 | (match_dup 2)) | |
7046 | (match_dup 3))) | |
7047 | (set (match_dup 0) | |
7048 | (compare:CC (match_dup 4) | |
7049 | (const_int 0)))] | |
7050 | "") | |
a260abc9 DE |
7051 | |
7052 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 7053 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 7054 | (compare:CC (and:DI |
9ebbca7d GK |
7055 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
7056 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 7057 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 7058 | (const_int 0))) |
9ebbca7d | 7059 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
7060 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
7061 | "TARGET_POWERPC64" | |
9ebbca7d GK |
7062 | "@ |
7063 | rld%I2c%B3. %0,%1,%H2,%S3 | |
7064 | #" | |
7065 | [(set_attr "type" "delayed_compare") | |
7066 | (set_attr "length" "4,8")]) | |
7067 | ||
7068 | (define_split | |
7069 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
7070 | (compare:CC (and:DI | |
7071 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7072 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
7073 | (match_operand:DI 3 "mask64_operand" "")) | |
7074 | (const_int 0))) | |
7075 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7076 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
7077 | "TARGET_POWERPC64 && reload_completed" | |
7078 | [(set (match_dup 0) | |
7079 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
7080 | (set (match_dup 4) | |
7081 | (compare:CC (match_dup 0) | |
7082 | (const_int 0)))] | |
7083 | "") | |
a260abc9 DE |
7084 | |
7085 | (define_insn "*rotldi3_internal7" | |
7086 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
7087 | (zero_extend:DI | |
7088 | (subreg:QI | |
7089 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7090 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
7091 | "TARGET_POWERPC64" | |
7092 | "rld%I2cl %0,%1,%H2,56") | |
7093 | ||
7094 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 7095 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
7096 | (compare:CC (zero_extend:DI |
7097 | (subreg:QI | |
9ebbca7d GK |
7098 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
7099 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 7100 | (const_int 0))) |
9ebbca7d | 7101 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 7102 | "TARGET_POWERPC64" |
9ebbca7d GK |
7103 | "@ |
7104 | rld%I2cl. %3,%1,%H2,56 | |
7105 | #" | |
7106 | [(set_attr "type" "delayed_compare") | |
7107 | (set_attr "length" "4,8")]) | |
7108 | ||
7109 | (define_split | |
7110 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7111 | (compare:CC (zero_extend:DI | |
7112 | (subreg:QI | |
7113 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7114 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
7115 | (const_int 0))) | |
7116 | (clobber (match_scratch:DI 3 ""))] | |
7117 | "TARGET_POWERPC64 && reload_completed" | |
7118 | [(set (match_dup 3) | |
7119 | (zero_extend:DI (subreg:QI | |
7120 | (rotate:DI (match_dup 1) | |
7121 | (match_dup 2)) 0))) | |
7122 | (set (match_dup 0) | |
7123 | (compare:CC (match_dup 3) | |
7124 | (const_int 0)))] | |
7125 | "") | |
a260abc9 DE |
7126 | |
7127 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 7128 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
7129 | (compare:CC (zero_extend:DI |
7130 | (subreg:QI | |
9ebbca7d GK |
7131 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
7132 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 7133 | (const_int 0))) |
9ebbca7d | 7134 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
7135 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
7136 | "TARGET_POWERPC64" | |
9ebbca7d GK |
7137 | "@ |
7138 | rld%I2cl. %0,%1,%H2,56 | |
7139 | #" | |
7140 | [(set_attr "type" "delayed_compare") | |
7141 | (set_attr "length" "4,8")]) | |
7142 | ||
7143 | (define_split | |
7144 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7145 | (compare:CC (zero_extend:DI | |
7146 | (subreg:QI | |
7147 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7148 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
7149 | (const_int 0))) | |
7150 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7151 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
7152 | "TARGET_POWERPC64 && reload_completed" | |
7153 | [(set (match_dup 0) | |
7154 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
7155 | (set (match_dup 3) | |
7156 | (compare:CC (match_dup 0) | |
7157 | (const_int 0)))] | |
7158 | "") | |
a260abc9 DE |
7159 | |
7160 | (define_insn "*rotldi3_internal10" | |
7161 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
7162 | (zero_extend:DI | |
7163 | (subreg:HI | |
7164 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7165 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
7166 | "TARGET_POWERPC64" | |
7167 | "rld%I2cl %0,%1,%H2,48") | |
7168 | ||
7169 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 7170 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
7171 | (compare:CC (zero_extend:DI |
7172 | (subreg:HI | |
9ebbca7d GK |
7173 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
7174 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 7175 | (const_int 0))) |
9ebbca7d | 7176 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 7177 | "TARGET_POWERPC64" |
9ebbca7d GK |
7178 | "@ |
7179 | rld%I2cl. %3,%1,%H2,48 | |
7180 | #" | |
7181 | [(set_attr "type" "delayed_compare") | |
7182 | (set_attr "length" "4,8")]) | |
7183 | ||
7184 | (define_split | |
7185 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7186 | (compare:CC (zero_extend:DI | |
7187 | (subreg:HI | |
7188 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7189 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
7190 | (const_int 0))) | |
7191 | (clobber (match_scratch:DI 3 ""))] | |
7192 | "TARGET_POWERPC64 && reload_completed" | |
7193 | [(set (match_dup 3) | |
7194 | (zero_extend:DI (subreg:HI | |
7195 | (rotate:DI (match_dup 1) | |
7196 | (match_dup 2)) 0))) | |
7197 | (set (match_dup 0) | |
7198 | (compare:CC (match_dup 3) | |
7199 | (const_int 0)))] | |
7200 | "") | |
a260abc9 DE |
7201 | |
7202 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 7203 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
7204 | (compare:CC (zero_extend:DI |
7205 | (subreg:HI | |
9ebbca7d GK |
7206 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
7207 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 7208 | (const_int 0))) |
9ebbca7d | 7209 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
7210 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
7211 | "TARGET_POWERPC64" | |
9ebbca7d GK |
7212 | "@ |
7213 | rld%I2cl. %0,%1,%H2,48 | |
7214 | #" | |
7215 | [(set_attr "type" "delayed_compare") | |
7216 | (set_attr "length" "4,8")]) | |
7217 | ||
7218 | (define_split | |
7219 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7220 | (compare:CC (zero_extend:DI | |
7221 | (subreg:HI | |
7222 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7223 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
7224 | (const_int 0))) | |
7225 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7226 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
7227 | "TARGET_POWERPC64 && reload_completed" | |
7228 | [(set (match_dup 0) | |
7229 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
7230 | (set (match_dup 3) | |
7231 | (compare:CC (match_dup 0) | |
7232 | (const_int 0)))] | |
7233 | "") | |
a260abc9 DE |
7234 | |
7235 | (define_insn "*rotldi3_internal13" | |
7236 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
7237 | (zero_extend:DI | |
7238 | (subreg:SI | |
7239 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7240 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
7241 | "TARGET_POWERPC64" | |
7242 | "rld%I2cl %0,%1,%H2,32") | |
7243 | ||
7244 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 7245 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
7246 | (compare:CC (zero_extend:DI |
7247 | (subreg:SI | |
9ebbca7d GK |
7248 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
7249 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 7250 | (const_int 0))) |
9ebbca7d | 7251 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 7252 | "TARGET_POWERPC64" |
9ebbca7d GK |
7253 | "@ |
7254 | rld%I2cl. %3,%1,%H2,32 | |
7255 | #" | |
7256 | [(set_attr "type" "delayed_compare") | |
7257 | (set_attr "length" "4,8")]) | |
7258 | ||
7259 | (define_split | |
7260 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7261 | (compare:CC (zero_extend:DI | |
7262 | (subreg:SI | |
7263 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7264 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
7265 | (const_int 0))) | |
7266 | (clobber (match_scratch:DI 3 ""))] | |
7267 | "TARGET_POWERPC64 && reload_completed" | |
7268 | [(set (match_dup 3) | |
7269 | (zero_extend:DI (subreg:SI | |
7270 | (rotate:DI (match_dup 1) | |
7271 | (match_dup 2)) 0))) | |
7272 | (set (match_dup 0) | |
7273 | (compare:CC (match_dup 3) | |
7274 | (const_int 0)))] | |
7275 | "") | |
a260abc9 DE |
7276 | |
7277 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 7278 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
7279 | (compare:CC (zero_extend:DI |
7280 | (subreg:SI | |
9ebbca7d GK |
7281 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
7282 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 7283 | (const_int 0))) |
9ebbca7d | 7284 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
7285 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
7286 | "TARGET_POWERPC64" | |
9ebbca7d GK |
7287 | "@ |
7288 | rld%I2cl. %0,%1,%H2,32 | |
7289 | #" | |
7290 | [(set_attr "type" "delayed_compare") | |
7291 | (set_attr "length" "4,8")]) | |
7292 | ||
7293 | (define_split | |
7294 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7295 | (compare:CC (zero_extend:DI | |
7296 | (subreg:SI | |
7297 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7298 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
7299 | (const_int 0))) | |
7300 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7301 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
7302 | "TARGET_POWERPC64 && reload_completed" | |
7303 | [(set (match_dup 0) | |
7304 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
7305 | (set (match_dup 3) | |
7306 | (compare:CC (match_dup 0) | |
7307 | (const_int 0)))] | |
7308 | "") | |
a260abc9 | 7309 | |
266eb58a DE |
7310 | (define_expand "ashldi3" |
7311 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7312 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7313 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
7314 | "TARGET_POWERPC64 || TARGET_POWER" | |
7315 | " | |
7316 | { | |
7317 | if (TARGET_POWERPC64) | |
7318 | ; | |
7319 | else if (TARGET_POWER) | |
7320 | { | |
7321 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
7322 | DONE; | |
7323 | } | |
7324 | else | |
7325 | FAIL; | |
7326 | }") | |
7327 | ||
e2c953b6 | 7328 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
7329 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7330 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7331 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
7332 | "TARGET_POWERPC64" | |
a66078ee | 7333 | "sld%I2 %0,%1,%H2" |
266eb58a DE |
7334 | [(set_attr "length" "8")]) |
7335 | ||
e2c953b6 | 7336 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
7337 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
7338 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7339 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7340 | (const_int 0))) |
9ebbca7d | 7341 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7342 | "TARGET_POWERPC64" |
9ebbca7d GK |
7343 | "@ |
7344 | sld%I2. %3,%1,%H2 | |
7345 | #" | |
7346 | [(set_attr "type" "delayed_compare") | |
7347 | (set_attr "length" "4,8")]) | |
29ae5b89 | 7348 | |
9ebbca7d GK |
7349 | (define_split |
7350 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7351 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7352 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7353 | (const_int 0))) | |
7354 | (clobber (match_scratch:DI 3 ""))] | |
7355 | "TARGET_POWERPC64 && reload_completed" | |
7356 | [(set (match_dup 3) | |
7357 | (ashift:DI (match_dup 1) (match_dup 2))) | |
7358 | (set (match_dup 0) | |
7359 | (compare:CC (match_dup 3) | |
7360 | (const_int 0)))] | |
7361 | "") | |
7362 | ||
e2c953b6 | 7363 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
7364 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7365 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7366 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7367 | (const_int 0))) |
9ebbca7d | 7368 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
7369 | (ashift:DI (match_dup 1) (match_dup 2)))] |
7370 | "TARGET_POWERPC64" | |
9ebbca7d GK |
7371 | "@ |
7372 | sld%I2. %0,%1,%H2 | |
7373 | #" | |
7374 | [(set_attr "type" "delayed_compare") | |
7375 | (set_attr "length" "4,8")]) | |
7376 | ||
7377 | (define_split | |
7378 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7379 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7380 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7381 | (const_int 0))) | |
7382 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7383 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
7384 | "TARGET_POWERPC64 && reload_completed" | |
7385 | [(set (match_dup 0) | |
7386 | (ashift:DI (match_dup 1) (match_dup 2))) | |
7387 | (set (match_dup 3) | |
7388 | (compare:CC (match_dup 0) | |
7389 | (const_int 0)))] | |
7390 | "") | |
266eb58a | 7391 | |
e2c953b6 | 7392 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
7393 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7394 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7395 | (match_operand:SI 2 "const_int_operand" "i")) | |
c5059423 AM |
7396 | (match_operand:DI 3 "const_int_operand" "n")))] |
7397 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" | |
e2c953b6 | 7398 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 7399 | |
e2c953b6 | 7400 | (define_insn "ashldi3_internal5" |
9ebbca7d | 7401 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 7402 | (compare:CC |
9ebbca7d GK |
7403 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
7404 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 7405 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 7406 | (const_int 0))) |
9ebbca7d | 7407 | (clobber (match_scratch:DI 4 "=r,r"))] |
c5059423 | 7408 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 7409 | "@ |
e2c953b6 | 7410 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
7411 | #" |
7412 | [(set_attr "type" "delayed_compare") | |
7413 | (set_attr "length" "4,8")]) | |
7414 | ||
7415 | (define_split | |
7416 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7417 | (compare:CC | |
7418 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7419 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 7420 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
7421 | (const_int 0))) |
7422 | (clobber (match_scratch:DI 4 ""))] | |
c5059423 AM |
7423 | "TARGET_POWERPC64 && reload_completed |
7424 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
9ebbca7d GK |
7425 | [(set (match_dup 4) |
7426 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 7427 | (match_dup 3))) |
9ebbca7d GK |
7428 | (set (match_dup 0) |
7429 | (compare:CC (match_dup 4) | |
7430 | (const_int 0)))] | |
7431 | "") | |
3cb999d8 | 7432 | |
e2c953b6 | 7433 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 7434 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 7435 | (compare:CC |
9ebbca7d GK |
7436 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
7437 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 7438 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 7439 | (const_int 0))) |
9ebbca7d | 7440 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 7441 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
c5059423 | 7442 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 7443 | "@ |
e2c953b6 | 7444 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
7445 | #" |
7446 | [(set_attr "type" "delayed_compare") | |
7447 | (set_attr "length" "4,8")]) | |
7448 | ||
7449 | (define_split | |
7450 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
7451 | (compare:CC | |
7452 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7453 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 7454 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
7455 | (const_int 0))) |
7456 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7457 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
c5059423 AM |
7458 | "TARGET_POWERPC64 && reload_completed |
7459 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
7460 | [(set (match_dup 0) | |
7461 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
7462 | (match_dup 3))) | |
7463 | (set (match_dup 4) | |
7464 | (compare:CC (match_dup 0) | |
7465 | (const_int 0)))] | |
7466 | "") | |
7467 | ||
7468 | (define_insn "*ashldi3_internal7" | |
7469 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
7470 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7471 | (match_operand:SI 2 "const_int_operand" "i")) | |
ce71f754 | 7472 | (match_operand:DI 3 "mask64_operand" "n")))] |
c5059423 AM |
7473 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" |
7474 | "rldicr %0,%1,%H2,%S3") | |
7475 | ||
7476 | (define_insn "ashldi3_internal8" | |
7477 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
7478 | (compare:CC | |
7479 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7480 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 7481 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
7482 | (const_int 0))) |
7483 | (clobber (match_scratch:DI 4 "=r,r"))] | |
7484 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" | |
7485 | "@ | |
7486 | rldicr. %4,%1,%H2,%S3 | |
7487 | #" | |
7488 | [(set_attr "type" "delayed_compare") | |
7489 | (set_attr "length" "4,8")]) | |
7490 | ||
7491 | (define_split | |
7492 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7493 | (compare:CC | |
7494 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7495 | (match_operand:SI 2 "const_int_operand" "")) | |
7496 | (match_operand:DI 3 "mask64_operand" "")) | |
7497 | (const_int 0))) | |
7498 | (clobber (match_scratch:DI 4 ""))] | |
7499 | "TARGET_POWERPC64 && reload_completed | |
7500 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
7501 | [(set (match_dup 4) | |
7502 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
7503 | (match_dup 3))) | |
7504 | (set (match_dup 0) | |
7505 | (compare:CC (match_dup 4) | |
7506 | (const_int 0)))] | |
7507 | "") | |
7508 | ||
7509 | (define_insn "*ashldi3_internal9" | |
7510 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
7511 | (compare:CC | |
7512 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7513 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 7514 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
7515 | (const_int 0))) |
7516 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
7517 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
7518 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" | |
7519 | "@ | |
7520 | rldicr. %0,%1,%H2,%S3 | |
7521 | #" | |
7522 | [(set_attr "type" "delayed_compare") | |
7523 | (set_attr "length" "4,8")]) | |
7524 | ||
7525 | (define_split | |
7526 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
7527 | (compare:CC | |
7528 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7529 | (match_operand:SI 2 "const_int_operand" "")) | |
7530 | (match_operand:DI 3 "mask64_operand" "")) | |
7531 | (const_int 0))) | |
7532 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7533 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
7534 | "TARGET_POWERPC64 && reload_completed | |
7535 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
9ebbca7d | 7536 | [(set (match_dup 0) |
e2c953b6 DE |
7537 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
7538 | (match_dup 3))) | |
9ebbca7d GK |
7539 | (set (match_dup 4) |
7540 | (compare:CC (match_dup 0) | |
7541 | (const_int 0)))] | |
7542 | "") | |
7543 | ||
7544 | (define_expand "lshrdi3" | |
266eb58a DE |
7545 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
7546 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7547 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
7548 | "TARGET_POWERPC64 || TARGET_POWER" | |
7549 | " | |
7550 | { | |
7551 | if (TARGET_POWERPC64) | |
7552 | ; | |
7553 | else if (TARGET_POWER) | |
7554 | { | |
7555 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
7556 | DONE; | |
7557 | } | |
7558 | else | |
7559 | FAIL; | |
7560 | }") | |
7561 | ||
e2c953b6 | 7562 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
7563 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7564 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7565 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
7566 | "TARGET_POWERPC64" | |
a66078ee | 7567 | "srd%I2 %0,%1,%H2") |
266eb58a | 7568 | |
e2c953b6 | 7569 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
7570 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
7571 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7572 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 7573 | (const_int 0))) |
9ebbca7d | 7574 | (clobber (match_scratch:DI 3 "=r,r"))] |
29ae5b89 | 7575 | "TARGET_POWERPC64" |
9ebbca7d GK |
7576 | "@ |
7577 | srd%I2. %3,%1,%H2 | |
7578 | #" | |
7579 | [(set_attr "type" "delayed_compare") | |
7580 | (set_attr "length" "4,8")]) | |
7581 | ||
7582 | (define_split | |
7583 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7584 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7585 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7586 | (const_int 0))) | |
7587 | (clobber (match_scratch:DI 3 ""))] | |
7588 | "TARGET_POWERPC64 && reload_completed" | |
7589 | [(set (match_dup 3) | |
7590 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
7591 | (set (match_dup 0) | |
7592 | (compare:CC (match_dup 3) | |
7593 | (const_int 0)))] | |
7594 | "") | |
266eb58a | 7595 | |
e2c953b6 | 7596 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
7597 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7598 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7599 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7600 | (const_int 0))) |
9ebbca7d | 7601 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 JL |
7602 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
7603 | "TARGET_POWERPC64" | |
9ebbca7d GK |
7604 | "@ |
7605 | srd%I2. %0,%1,%H2 | |
7606 | #" | |
7607 | [(set_attr "type" "delayed_compare") | |
7608 | (set_attr "length" "4,8")]) | |
7609 | ||
7610 | (define_split | |
7611 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7612 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7613 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7614 | (const_int 0))) | |
7615 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7616 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
7617 | "TARGET_POWERPC64 && reload_completed" | |
7618 | [(set (match_dup 0) | |
7619 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
7620 | (set (match_dup 3) | |
7621 | (compare:CC (match_dup 0) | |
7622 | (const_int 0)))] | |
7623 | "") | |
266eb58a DE |
7624 | |
7625 | (define_expand "ashrdi3" | |
7626 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7627 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7628 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4aa74a4f | 7629 | "" |
266eb58a DE |
7630 | " |
7631 | { | |
7632 | if (TARGET_POWERPC64) | |
7633 | ; | |
7634 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
7635 | { | |
7636 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
7637 | DONE; | |
7638 | } | |
4aa74a4f FS |
7639 | else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT) |
7640 | { | |
7641 | emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); | |
7642 | DONE; | |
7643 | } | |
266eb58a DE |
7644 | else |
7645 | FAIL; | |
7646 | }") | |
7647 | ||
e2c953b6 | 7648 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
7649 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7650 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7651 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
7652 | "TARGET_POWERPC64" | |
375490e0 | 7653 | "srad%I2 %0,%1,%H2") |
266eb58a | 7654 | |
e2c953b6 | 7655 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
7656 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
7657 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7658 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7659 | (const_int 0))) |
9ebbca7d | 7660 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7661 | "TARGET_POWERPC64" |
9ebbca7d GK |
7662 | "@ |
7663 | srad%I2. %3,%1,%H2 | |
7664 | #" | |
7665 | [(set_attr "type" "delayed_compare") | |
7666 | (set_attr "length" "4,8")]) | |
7667 | ||
7668 | (define_split | |
7669 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7670 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7671 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7672 | (const_int 0))) | |
7673 | (clobber (match_scratch:DI 3 ""))] | |
7674 | "TARGET_POWERPC64 && reload_completed" | |
7675 | [(set (match_dup 3) | |
7676 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7677 | (set (match_dup 0) | |
7678 | (compare:CC (match_dup 3) | |
7679 | (const_int 0)))] | |
7680 | "") | |
266eb58a | 7681 | |
e2c953b6 | 7682 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
7683 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7684 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7685 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7686 | (const_int 0))) |
9ebbca7d | 7687 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
7688 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
7689 | "TARGET_POWERPC64" | |
9ebbca7d GK |
7690 | "@ |
7691 | srad%I2. %0,%1,%H2 | |
7692 | #" | |
7693 | [(set_attr "type" "delayed_compare") | |
7694 | (set_attr "length" "4,8")]) | |
7695 | ||
7696 | (define_split | |
7697 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7698 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7699 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7700 | (const_int 0))) | |
7701 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7702 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
7703 | "TARGET_POWERPC64 && reload_completed" | |
7704 | [(set (match_dup 0) | |
7705 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7706 | (set (match_dup 3) | |
7707 | (compare:CC (match_dup 0) | |
7708 | (const_int 0)))] | |
7709 | "") | |
815cdc52 | 7710 | |
29ae5b89 | 7711 | (define_insn "anddi3" |
0ba1b2ff AM |
7712 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") |
7713 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
7714 | (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t"))) | |
7715 | (clobber (match_scratch:CC 3 "=X,X,x,x,X"))] | |
6ffc8580 | 7716 | "TARGET_POWERPC64" |
266eb58a DE |
7717 | "@ |
7718 | and %0,%1,%2 | |
29ae5b89 JL |
7719 | rldic%B2 %0,%1,0,%S2 |
7720 | andi. %0,%1,%b2 | |
0ba1b2ff AM |
7721 | andis. %0,%1,%u2 |
7722 | #" | |
7723 | [(set_attr "length" "4,4,4,4,8")]) | |
7724 | ||
7725 | (define_split | |
7726 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7727 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7728 | (match_operand:DI 2 "mask64_2_operand" ""))) | |
7729 | (clobber (match_scratch:CC 3 ""))] | |
7730 | "TARGET_POWERPC64 | |
7731 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7732 | && !mask64_operand (operands[2], DImode)" | |
7733 | [(set (match_dup 0) | |
7734 | (and:DI (rotate:DI (match_dup 1) | |
7735 | (match_dup 4)) | |
7736 | (match_dup 5))) | |
7737 | (set (match_dup 0) | |
7738 | (and:DI (rotate:DI (match_dup 0) | |
7739 | (match_dup 6)) | |
7740 | (match_dup 7)))] | |
7741 | " | |
7742 | { | |
7743 | build_mask64_2_operands (operands[2], &operands[4]); | |
7744 | }") | |
266eb58a | 7745 | |
a260abc9 | 7746 | (define_insn "*anddi3_internal2" |
0ba1b2ff AM |
7747 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7748 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7749 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7750 | (const_int 0))) |
0ba1b2ff AM |
7751 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r")) |
7752 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] | |
6ffc8580 | 7753 | "TARGET_POWERPC64" |
266eb58a DE |
7754 | "@ |
7755 | and. %3,%1,%2 | |
6c873122 | 7756 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
7757 | andi. %3,%1,%b2 |
7758 | andis. %3,%1,%u2 | |
9ebbca7d GK |
7759 | # |
7760 | # | |
7761 | # | |
0ba1b2ff AM |
7762 | # |
7763 | # | |
9ebbca7d | 7764 | #" |
0ba1b2ff AM |
7765 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7766 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7767 | |
7768 | (define_split | |
7769 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7770 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7771 | (match_operand:DI 2 "and64_operand" "")) | |
7772 | (const_int 0))) | |
7773 | (clobber (match_scratch:DI 3 "")) | |
7774 | (clobber (match_scratch:CC 4 ""))] | |
7775 | "TARGET_POWERPC64 && reload_completed" | |
7776 | [(parallel [(set (match_dup 3) | |
7777 | (and:DI (match_dup 1) | |
7778 | (match_dup 2))) | |
7779 | (clobber (match_dup 4))]) | |
7780 | (set (match_dup 0) | |
7781 | (compare:CC (match_dup 3) | |
7782 | (const_int 0)))] | |
7783 | "") | |
266eb58a | 7784 | |
0ba1b2ff AM |
7785 | (define_split |
7786 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
7787 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7788 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7789 | (const_int 0))) | |
7790 | (clobber (match_scratch:DI 3 "")) | |
7791 | (clobber (match_scratch:CC 4 ""))] | |
7792 | "TARGET_POWERPC64 && reload_completed | |
7793 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7794 | && !mask64_operand (operands[2], DImode)" | |
7795 | [(set (match_dup 3) | |
7796 | (and:DI (rotate:DI (match_dup 1) | |
7797 | (match_dup 5)) | |
7798 | (match_dup 6))) | |
7799 | (parallel [(set (match_dup 0) | |
7800 | (compare:CC (and:DI (rotate:DI (match_dup 3) | |
7801 | (match_dup 7)) | |
7802 | (match_dup 8)) | |
7803 | (const_int 0))) | |
7804 | (clobber (match_dup 3))])] | |
7805 | " | |
7806 | { | |
7807 | build_mask64_2_operands (operands[2], &operands[5]); | |
7808 | }") | |
7809 | ||
a260abc9 | 7810 | (define_insn "*anddi3_internal3" |
0ba1b2ff AM |
7811 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7812 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7813 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7814 | (const_int 0))) |
0ba1b2ff | 7815 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
9ebbca7d | 7816 | (and:DI (match_dup 1) (match_dup 2))) |
0ba1b2ff | 7817 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] |
6ffc8580 | 7818 | "TARGET_POWERPC64" |
266eb58a DE |
7819 | "@ |
7820 | and. %0,%1,%2 | |
6c873122 | 7821 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
7822 | andi. %0,%1,%b2 |
7823 | andis. %0,%1,%u2 | |
9ebbca7d GK |
7824 | # |
7825 | # | |
7826 | # | |
0ba1b2ff AM |
7827 | # |
7828 | # | |
9ebbca7d | 7829 | #" |
0ba1b2ff AM |
7830 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7831 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7832 | |
7833 | (define_split | |
7834 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7835 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7836 | (match_operand:DI 2 "and64_operand" "")) | |
7837 | (const_int 0))) | |
7838 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7839 | (and:DI (match_dup 1) (match_dup 2))) | |
7840 | (clobber (match_scratch:CC 4 ""))] | |
7841 | "TARGET_POWERPC64 && reload_completed" | |
7842 | [(parallel [(set (match_dup 0) | |
7843 | (and:DI (match_dup 1) (match_dup 2))) | |
7844 | (clobber (match_dup 4))]) | |
7845 | (set (match_dup 3) | |
7846 | (compare:CC (match_dup 0) | |
7847 | (const_int 0)))] | |
7848 | "") | |
266eb58a | 7849 | |
0ba1b2ff AM |
7850 | (define_split |
7851 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
7852 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7853 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7854 | (const_int 0))) | |
7855 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7856 | (and:DI (match_dup 1) (match_dup 2))) | |
7857 | (clobber (match_scratch:CC 4 ""))] | |
7858 | "TARGET_POWERPC64 && reload_completed | |
7859 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7860 | && !mask64_operand (operands[2], DImode)" | |
7861 | [(set (match_dup 0) | |
7862 | (and:DI (rotate:DI (match_dup 1) | |
7863 | (match_dup 5)) | |
7864 | (match_dup 6))) | |
7865 | (parallel [(set (match_dup 3) | |
7866 | (compare:CC (and:DI (rotate:DI (match_dup 0) | |
7867 | (match_dup 7)) | |
7868 | (match_dup 8)) | |
7869 | (const_int 0))) | |
7870 | (set (match_dup 0) | |
7871 | (and:DI (rotate:DI (match_dup 0) | |
7872 | (match_dup 7)) | |
7873 | (match_dup 8)))])] | |
7874 | " | |
7875 | { | |
7876 | build_mask64_2_operands (operands[2], &operands[5]); | |
7877 | }") | |
7878 | ||
a260abc9 | 7879 | (define_expand "iordi3" |
266eb58a | 7880 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 7881 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 7882 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 7883 | "TARGET_POWERPC64" |
266eb58a DE |
7884 | " |
7885 | { | |
dfbdccdb | 7886 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 7887 | { |
dfbdccdb | 7888 | HOST_WIDE_INT value; |
677a9668 | 7889 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 7890 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 7891 | |
dfbdccdb GK |
7892 | if (GET_CODE (operands[2]) == CONST_INT) |
7893 | { | |
7894 | value = INTVAL (operands[2]); | |
7895 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7896 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7897 | } | |
e2c953b6 | 7898 | else |
dfbdccdb GK |
7899 | { |
7900 | value = CONST_DOUBLE_LOW (operands[2]); | |
7901 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7902 | immed_double_const (value | |
7903 | & (~ (HOST_WIDE_INT) 0xffff), | |
7904 | 0, DImode))); | |
7905 | } | |
e2c953b6 | 7906 | |
9ebbca7d GK |
7907 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7908 | DONE; | |
7909 | } | |
266eb58a DE |
7910 | }") |
7911 | ||
a260abc9 DE |
7912 | (define_expand "xordi3" |
7913 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7914 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 7915 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
7916 | "TARGET_POWERPC64" |
7917 | " | |
7918 | { | |
dfbdccdb | 7919 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 7920 | { |
dfbdccdb | 7921 | HOST_WIDE_INT value; |
677a9668 | 7922 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
7923 | ? operands[0] : gen_reg_rtx (DImode)); |
7924 | ||
dfbdccdb GK |
7925 | if (GET_CODE (operands[2]) == CONST_INT) |
7926 | { | |
7927 | value = INTVAL (operands[2]); | |
7928 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7929 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7930 | } | |
e2c953b6 | 7931 | else |
dfbdccdb GK |
7932 | { |
7933 | value = CONST_DOUBLE_LOW (operands[2]); | |
7934 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7935 | immed_double_const (value | |
7936 | & (~ (HOST_WIDE_INT) 0xffff), | |
7937 | 0, DImode))); | |
7938 | } | |
e2c953b6 | 7939 | |
9ebbca7d GK |
7940 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7941 | DONE; | |
7942 | } | |
a260abc9 DE |
7943 | }") |
7944 | ||
dfbdccdb | 7945 | (define_insn "*booldi3_internal1" |
266eb58a | 7946 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 7947 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7948 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
7949 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 7950 | "TARGET_POWERPC64" |
1fd4e8c1 | 7951 | "@ |
dfbdccdb GK |
7952 | %q3 %0,%1,%2 |
7953 | %q3i %0,%1,%b2 | |
7954 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 7955 | |
dfbdccdb | 7956 | (define_insn "*booldi3_internal2" |
9ebbca7d | 7957 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 7958 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
7959 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
7960 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7961 | (const_int 0))) | |
9ebbca7d | 7962 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7963 | "TARGET_POWERPC64" |
9ebbca7d | 7964 | "@ |
dfbdccdb | 7965 | %q4. %3,%1,%2 |
9ebbca7d GK |
7966 | #" |
7967 | [(set_attr "type" "compare") | |
7968 | (set_attr "length" "4,8")]) | |
7969 | ||
7970 | (define_split | |
7971 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7972 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7973 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7974 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7975 | (const_int 0))) |
9ebbca7d GK |
7976 | (clobber (match_scratch:DI 3 ""))] |
7977 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7978 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7979 | (set (match_dup 0) |
7980 | (compare:CC (match_dup 3) | |
7981 | (const_int 0)))] | |
7982 | "") | |
1fd4e8c1 | 7983 | |
dfbdccdb | 7984 | (define_insn "*booldi3_internal3" |
9ebbca7d | 7985 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7986 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7987 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7988 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7989 | (const_int 0))) | |
9ebbca7d | 7990 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7991 | (match_dup 4))] |
266eb58a | 7992 | "TARGET_POWERPC64" |
9ebbca7d | 7993 | "@ |
dfbdccdb | 7994 | %q4. %0,%1,%2 |
9ebbca7d GK |
7995 | #" |
7996 | [(set_attr "type" "compare") | |
7997 | (set_attr "length" "4,8")]) | |
7998 | ||
7999 | (define_split | |
e72247f4 | 8000 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 8001 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
8002 | [(match_operand:DI 1 "gpc_reg_operand" "") |
8003 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 8004 | (const_int 0))) |
75540af0 | 8005 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 8006 | (match_dup 4))] |
9ebbca7d | 8007 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 8008 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
8009 | (set (match_dup 3) |
8010 | (compare:CC (match_dup 0) | |
8011 | (const_int 0)))] | |
8012 | "") | |
1fd4e8c1 | 8013 | |
5bdc5878 | 8014 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 8015 | ;; each of which does one 16-bit part. This is used by combine. |
266eb58a DE |
8016 | |
8017 | (define_split | |
8018 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 8019 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
8020 | [(match_operand:DI 1 "gpc_reg_operand" "") |
8021 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 8022 | "TARGET_POWERPC64" |
dfbdccdb GK |
8023 | [(set (match_dup 0) (match_dup 4)) |
8024 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
8025 | " |
8026 | { | |
dfbdccdb GK |
8027 | rtx i3,i4; |
8028 | ||
9ebbca7d GK |
8029 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
8030 | { | |
8031 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 8032 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 8033 | 0, DImode); |
dfbdccdb | 8034 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
8035 | } |
8036 | else | |
8037 | { | |
dfbdccdb | 8038 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 8039 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 8040 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 8041 | } |
dfbdccdb GK |
8042 | operands[4] = gen_rtx (GET_CODE (operands[3]), DImode, |
8043 | operands[1], i3); | |
8044 | operands[5] = gen_rtx (GET_CODE (operands[3]), DImode, | |
8045 | operands[0], i4); | |
1fd4e8c1 RK |
8046 | }") |
8047 | ||
dfbdccdb | 8048 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 8049 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
8050 | (match_operator:DI 3 "boolean_operator" |
8051 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 8052 | (match_operand:DI 2 "gpc_reg_operand" "r")]))] |
a473029f | 8053 | "TARGET_POWERPC64" |
1d328b19 | 8054 | "%q3 %0,%2,%1") |
a473029f | 8055 | |
dfbdccdb | 8056 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 8057 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
8058 | (compare:CC (match_operator:DI 4 "boolean_operator" |
8059 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
8060 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
8061 | (const_int 0))) | |
9ebbca7d | 8062 | (clobber (match_scratch:DI 3 "=r,r"))] |
a473029f | 8063 | "TARGET_POWERPC64" |
9ebbca7d | 8064 | "@ |
1d328b19 | 8065 | %q4. %3,%2,%1 |
9ebbca7d GK |
8066 | #" |
8067 | [(set_attr "type" "compare") | |
8068 | (set_attr "length" "4,8")]) | |
8069 | ||
8070 | (define_split | |
8071 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 8072 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
8073 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
8074 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 8075 | (const_int 0))) |
9ebbca7d GK |
8076 | (clobber (match_scratch:DI 3 ""))] |
8077 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 8078 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
8079 | (set (match_dup 0) |
8080 | (compare:CC (match_dup 3) | |
8081 | (const_int 0)))] | |
8082 | "") | |
a473029f | 8083 | |
dfbdccdb | 8084 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 8085 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
8086 | (compare:CC (match_operator:DI 4 "boolean_operator" |
8087 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
8088 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
8089 | (const_int 0))) | |
9ebbca7d | 8090 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 8091 | (match_dup 4))] |
a473029f | 8092 | "TARGET_POWERPC64" |
9ebbca7d | 8093 | "@ |
1d328b19 | 8094 | %q4. %0,%2,%1 |
9ebbca7d GK |
8095 | #" |
8096 | [(set_attr "type" "compare") | |
8097 | (set_attr "length" "4,8")]) | |
8098 | ||
8099 | (define_split | |
e72247f4 | 8100 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 8101 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
8102 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
8103 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 8104 | (const_int 0))) |
75540af0 | 8105 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 8106 | (match_dup 4))] |
9ebbca7d | 8107 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 8108 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
8109 | (set (match_dup 3) |
8110 | (compare:CC (match_dup 0) | |
8111 | (const_int 0)))] | |
8112 | "") | |
266eb58a | 8113 | |
dfbdccdb | 8114 | (define_insn "*boolccdi3_internal1" |
a473029f | 8115 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
8116 | (match_operator:DI 3 "boolean_operator" |
8117 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 8118 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] |
a473029f | 8119 | "TARGET_POWERPC64" |
dfbdccdb | 8120 | "%q3 %0,%1,%2") |
a473029f | 8121 | |
dfbdccdb | 8122 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 8123 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
8124 | (compare:CC (match_operator:DI 4 "boolean_operator" |
8125 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
8126 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
8127 | (const_int 0))) | |
9ebbca7d | 8128 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 8129 | "TARGET_POWERPC64" |
9ebbca7d | 8130 | "@ |
dfbdccdb | 8131 | %q4. %3,%1,%2 |
9ebbca7d GK |
8132 | #" |
8133 | [(set_attr "type" "compare") | |
8134 | (set_attr "length" "4,8")]) | |
8135 | ||
8136 | (define_split | |
8137 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 8138 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
8139 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
8140 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 8141 | (const_int 0))) |
9ebbca7d GK |
8142 | (clobber (match_scratch:DI 3 ""))] |
8143 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 8144 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
8145 | (set (match_dup 0) |
8146 | (compare:CC (match_dup 3) | |
8147 | (const_int 0)))] | |
8148 | "") | |
266eb58a | 8149 | |
dfbdccdb | 8150 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 8151 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
8152 | (compare:CC (match_operator:DI 4 "boolean_operator" |
8153 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
8154 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
8155 | (const_int 0))) | |
9ebbca7d | 8156 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 8157 | (match_dup 4))] |
29ae5b89 | 8158 | "TARGET_POWERPC64" |
9ebbca7d | 8159 | "@ |
dfbdccdb | 8160 | %q4. %0,%1,%2 |
9ebbca7d GK |
8161 | #" |
8162 | [(set_attr "type" "compare") | |
8163 | (set_attr "length" "4,8")]) | |
8164 | ||
8165 | (define_split | |
e72247f4 | 8166 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 8167 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
8168 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
8169 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 8170 | (const_int 0))) |
75540af0 | 8171 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 8172 | (match_dup 4))] |
9ebbca7d | 8173 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 8174 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
8175 | (set (match_dup 3) |
8176 | (compare:CC (match_dup 0) | |
8177 | (const_int 0)))] | |
8178 | "") | |
dfbdccdb | 8179 | \f |
1fd4e8c1 | 8180 | ;; Now define ways of moving data around. |
4697a36c MM |
8181 | |
8182 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
8183 | ;; The output of this could be r0, but we make a very strong |
8184 | ;; preference for a base register because it will usually | |
8185 | ;; be needed there. | |
4697a36c | 8186 | (define_insn "elf_high" |
9ebbca7d | 8187 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 8188 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 8189 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 8190 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
8191 | |
8192 | (define_insn "elf_low" | |
9ebbca7d GK |
8193 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
8194 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 8195 | (match_operand 2 "" "")))] |
0ad91047 | 8196 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
8197 | "@ |
8198 | {cal|la} %0,%2@l(%1) | |
81eace42 | 8199 | {ai|addic} %0,%1,%K2") |
4697a36c | 8200 | |
ee890fe2 SS |
8201 | ;; Mach-O PIC trickery. |
8202 | (define_insn "macho_high" | |
8203 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") | |
8204 | (high:SI (match_operand 1 "" "")))] | |
8205 | "TARGET_MACHO && ! TARGET_64BIT" | |
8206 | "{liu|lis} %0,ha16(%1)") | |
8207 | ||
8208 | (define_insn "macho_low" | |
8209 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
8210 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
8211 | (match_operand 2 "" "")))] | |
8212 | "TARGET_MACHO && ! TARGET_64BIT" | |
8213 | "@ | |
8214 | {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} | |
8215 | {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") | |
8216 | ||
766a866c MM |
8217 | ;; Set up a register with a value from the GOT table |
8218 | ||
8219 | (define_expand "movsi_got" | |
52d3af72 | 8220 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d GK |
8221 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
8222 | (match_dup 2)] 8))] | |
f607bc57 | 8223 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
8224 | " |
8225 | { | |
38c1f2d7 MM |
8226 | if (GET_CODE (operands[1]) == CONST) |
8227 | { | |
8228 | rtx offset = const0_rtx; | |
8229 | HOST_WIDE_INT value; | |
8230 | ||
8231 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
8232 | value = INTVAL (offset); | |
8233 | if (value != 0) | |
8234 | { | |
677a9668 | 8235 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
8236 | emit_insn (gen_movsi_got (tmp, operands[1])); |
8237 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
8238 | DONE; | |
8239 | } | |
8240 | } | |
8241 | ||
c4c40373 | 8242 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
8243 | }") |
8244 | ||
84f414bc | 8245 | (define_insn "*movsi_got_internal" |
52d3af72 | 8246 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d GK |
8247 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
8248 | (match_operand:SI 2 "gpc_reg_operand" "b")] 8))] | |
f607bc57 | 8249 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
8250 | "{l|lwz} %0,%a1@got(%2)" |
8251 | [(set_attr "type" "load")]) | |
8252 | ||
b22b9b3e JL |
8253 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
8254 | ;; didn't get allocated to a hard register. | |
8255 | (define_split | |
75540af0 | 8256 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 8257 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
75540af0 | 8258 | (match_operand:SI 2 "memory_operand" "")] 8))] |
f607bc57 | 8259 | "DEFAULT_ABI == ABI_V4 |
b22b9b3e JL |
8260 | && flag_pic == 1 |
8261 | && (reload_in_progress || reload_completed)" | |
8262 | [(set (match_dup 0) (match_dup 2)) | |
9ebbca7d | 8263 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))] |
b22b9b3e JL |
8264 | "") |
8265 | ||
1fd4e8c1 RK |
8266 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
8267 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
8268 | ;; and this is even supposed to be faster, but it is simpler not to get | |
8269 | ;; integers in the TOC. | |
8270 | (define_expand "movsi" | |
8271 | [(set (match_operand:SI 0 "general_operand" "") | |
8272 | (match_operand:SI 1 "any_operand" ""))] | |
8273 | "" | |
fb4d4348 | 8274 | "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") |
1fd4e8c1 | 8275 | |
ee890fe2 SS |
8276 | (define_insn "movsi_low" |
8277 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
f585a356 | 8278 | (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
ee890fe2 SS |
8279 | (match_operand 2 "" ""))))] |
8280 | "TARGET_MACHO && ! TARGET_64BIT" | |
8281 | "{l|lwz} %0,lo16(%2)(%1)" | |
8282 | [(set_attr "type" "load") | |
8283 | (set_attr "length" "4")]) | |
8284 | ||
c859cda6 | 8285 | (define_insn "movsi_low_st" |
f585a356 | 8286 | [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
c859cda6 DJ |
8287 | (match_operand 2 "" ""))) |
8288 | (match_operand:SI 0 "gpc_reg_operand" "r"))] | |
8289 | "TARGET_MACHO && ! TARGET_64BIT" | |
8290 | "{st|stw} %0,lo16(%2)(%1)" | |
8291 | [(set_attr "type" "store") | |
8292 | (set_attr "length" "4")]) | |
8293 | ||
8294 | (define_insn "movdf_low" | |
234e114c | 8295 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") |
f585a356 | 8296 | (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 8297 | (match_operand 2 "" ""))))] |
a3170dc6 | 8298 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
234e114c DJ |
8299 | "* |
8300 | { | |
8301 | switch (which_alternative) | |
8302 | { | |
8303 | case 0: | |
8304 | return \"lfd %0,lo16(%2)(%1)\"; | |
8305 | case 1: | |
8306 | { | |
8307 | rtx operands2[4]; | |
8308 | operands2[0] = operands[0]; | |
8309 | operands2[1] = operands[1]; | |
8310 | operands2[2] = operands[2]; | |
1db02437 | 8311 | operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
234e114c DJ |
8312 | output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands); |
8313 | /* We cannot rely on ha16(low half)==ha16(high half), alas, | |
8314 | although in practice it almost always is. */ | |
8315 | output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2); | |
8316 | return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\"); | |
8317 | } | |
8318 | default: | |
8319 | abort(); | |
8320 | } | |
8321 | }" | |
c859cda6 | 8322 | [(set_attr "type" "load") |
234e114c | 8323 | (set_attr "length" "4,12")]) |
c859cda6 DJ |
8324 | |
8325 | (define_insn "movdf_low_st" | |
f585a356 | 8326 | [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
c859cda6 DJ |
8327 | (match_operand 2 "" ""))) |
8328 | (match_operand:DF 0 "gpc_reg_operand" "f"))] | |
a3170dc6 | 8329 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
c859cda6 DJ |
8330 | "stfd %0,lo16(%2)(%1)" |
8331 | [(set_attr "type" "store") | |
8332 | (set_attr "length" "4")]) | |
8333 | ||
8334 | (define_insn "movsf_low" | |
fd3b43f2 | 8335 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") |
f585a356 | 8336 | (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 8337 | (match_operand 2 "" ""))))] |
a3170dc6 | 8338 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
fd3b43f2 DJ |
8339 | "@ |
8340 | lfs %0,lo16(%2)(%1) | |
8341 | {l|lwz} %0,lo16(%2)(%1)" | |
c859cda6 DJ |
8342 | [(set_attr "type" "load") |
8343 | (set_attr "length" "4")]) | |
8344 | ||
8345 | (define_insn "movsf_low_st" | |
f585a356 | 8346 | [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 8347 | (match_operand 2 "" ""))) |
fd3b43f2 | 8348 | (match_operand:SF 0 "gpc_reg_operand" "f,!r"))] |
a3170dc6 | 8349 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
fd3b43f2 DJ |
8350 | "@ |
8351 | stfs %0,lo16(%2)(%1) | |
8352 | {st|stw} %0,lo16(%2)(%1)" | |
c859cda6 DJ |
8353 | [(set_attr "type" "store") |
8354 | (set_attr "length" "4")]) | |
8355 | ||
acad7ed3 | 8356 | (define_insn "*movsi_internal1" |
a004eb82 AH |
8357 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") |
8358 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] | |
19d5775a RK |
8359 | "gpc_reg_operand (operands[0], SImode) |
8360 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 8361 | "@ |
deb9225a | 8362 | mr %0,%1 |
b9442c72 | 8363 | {cal|la} %0,%a1 |
ca7f5001 RK |
8364 | {l%U1%X1|lwz%U1%X1} %0,%1 |
8365 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 8366 | {lil|li} %0,%1 |
802a0058 | 8367 | {liu|lis} %0,%v1 |
beaec479 | 8368 | # |
aee86b38 | 8369 | {cal|la} %0,%a1 |
1fd4e8c1 | 8370 | mf%1 %0 |
5c23c401 | 8371 | mt%0 %1 |
e76e75bb | 8372 | mt%0 %1 |
a004eb82 | 8373 | mt%0 %1 |
e34eaae5 | 8374 | {cror 0,0,0|nop}" |
a004eb82 AH |
8375 | [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*,*") |
8376 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) | |
1fd4e8c1 | 8377 | |
77fa0940 RK |
8378 | ;; Split a load of a large constant into the appropriate two-insn |
8379 | ;; sequence. | |
8380 | ||
8381 | (define_split | |
8382 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
8383 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 8384 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
8385 | && (INTVAL (operands[1]) & 0xffff) != 0" |
8386 | [(set (match_dup 0) | |
8387 | (match_dup 2)) | |
8388 | (set (match_dup 0) | |
8389 | (ior:SI (match_dup 0) | |
8390 | (match_dup 3)))] | |
8391 | " | |
af8cb5c5 DE |
8392 | { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2); |
8393 | ||
8394 | if (tem == operands[0]) | |
8395 | DONE; | |
8396 | else | |
8397 | FAIL; | |
77fa0940 RK |
8398 | }") |
8399 | ||
acad7ed3 | 8400 | (define_insn "*movsi_internal2" |
9ebbca7d GK |
8401 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
8402 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 8403 | (const_int 0))) |
9ebbca7d | 8404 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
0ad91047 | 8405 | "! TARGET_POWERPC64" |
9ebbca7d GK |
8406 | "@ |
8407 | mr. %0,%1 | |
8408 | #" | |
8409 | [(set_attr "type" "compare") | |
8410 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 8411 | \f |
9ebbca7d GK |
8412 | (define_split |
8413 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8414 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
8415 | (const_int 0))) | |
8416 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8417 | "! TARGET_POWERPC64 && reload_completed" | |
8418 | [(set (match_dup 0) (match_dup 1)) | |
8419 | (set (match_dup 2) | |
8420 | (compare:CC (match_dup 0) | |
8421 | (const_int 0)))] | |
8422 | "") | |
8423 | ||
1fd4e8c1 RK |
8424 | (define_expand "movhi" |
8425 | [(set (match_operand:HI 0 "general_operand" "") | |
8426 | (match_operand:HI 1 "any_operand" ""))] | |
8427 | "" | |
fb4d4348 | 8428 | "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") |
1fd4e8c1 | 8429 | |
e34eaae5 | 8430 | (define_insn "*movhi_internal" |
fb81d7ce RK |
8431 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
8432 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
8433 | "gpc_reg_operand (operands[0], HImode) |
8434 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 8435 | "@ |
deb9225a | 8436 | mr %0,%1 |
1fd4e8c1 RK |
8437 | lhz%U1%X1 %0,%1 |
8438 | sth%U0%X0 %1,%0 | |
19d5775a | 8439 | {lil|li} %0,%w1 |
1fd4e8c1 | 8440 | mf%1 %0 |
e76e75bb | 8441 | mt%0 %1 |
fb81d7ce | 8442 | mt%0 %1 |
e34eaae5 | 8443 | {cror 0,0,0|nop}" |
b7ff3d82 | 8444 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
8445 | |
8446 | (define_expand "movqi" | |
8447 | [(set (match_operand:QI 0 "general_operand" "") | |
8448 | (match_operand:QI 1 "any_operand" ""))] | |
8449 | "" | |
fb4d4348 | 8450 | "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") |
1fd4e8c1 | 8451 | |
e34eaae5 | 8452 | (define_insn "*movqi_internal" |
fb81d7ce RK |
8453 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
8454 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
8455 | "gpc_reg_operand (operands[0], QImode) |
8456 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 8457 | "@ |
deb9225a | 8458 | mr %0,%1 |
1fd4e8c1 RK |
8459 | lbz%U1%X1 %0,%1 |
8460 | stb%U0%X0 %1,%0 | |
19d5775a | 8461 | {lil|li} %0,%1 |
1fd4e8c1 | 8462 | mf%1 %0 |
e76e75bb | 8463 | mt%0 %1 |
fb81d7ce | 8464 | mt%0 %1 |
e34eaae5 | 8465 | {cror 0,0,0|nop}" |
b7ff3d82 | 8466 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
8467 | \f |
8468 | ;; Here is how to move condition codes around. When we store CC data in | |
8469 | ;; an integer register or memory, we store just the high-order 4 bits. | |
8470 | ;; This lets us not shift in the most common case of CR0. | |
8471 | (define_expand "movcc" | |
8472 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
8473 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
8474 | "" | |
8475 | "") | |
8476 | ||
a65c591c | 8477 | (define_insn "*movcc_internal1" |
b991a865 GK |
8478 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,cl,q,r,r,m") |
8479 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,r,r,h,m,r"))] | |
1fd4e8c1 RK |
8480 | "register_operand (operands[0], CCmode) |
8481 | || register_operand (operands[1], CCmode)" | |
8482 | "@ | |
8483 | mcrf %0,%1 | |
8484 | mtcrf 128,%1 | |
ca7f5001 | 8485 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
1fd4e8c1 | 8486 | mfcr %0 |
ca7f5001 | 8487 | mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 |
deb9225a | 8488 | mr %0,%1 |
b991a865 GK |
8489 | mt%0 %1 |
8490 | mt%0 %1 | |
8491 | mf%1 %0 | |
ca7f5001 RK |
8492 | {l%U1%X1|lwz%U1%X1} %0,%1 |
8493 | {st%U0%U1|stw%U0%U1} %1,%0" | |
b991a865 GK |
8494 | [(set_attr "type" "cr_logical,cr_logical,cr_logical,cr_logical,cr_logical,*,*,mtjmpr,*,load,store") |
8495 | (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")]) | |
1fd4e8c1 | 8496 | \f |
e52e05ca MM |
8497 | ;; For floating-point, we normally deal with the floating-point registers |
8498 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
8499 | ;; can produce floating-point values in fixed-point registers. Unless the | |
8500 | ;; value is a simple constant or already in memory, we deal with this by | |
8501 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
8502 | (define_expand "movsf" |
8503 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
8504 | (match_operand:SF 1 "any_operand" ""))] | |
8505 | "" | |
fb4d4348 | 8506 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 8507 | |
1fd4e8c1 | 8508 | (define_split |
cd2b37d9 | 8509 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 8510 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 8511 | "reload_completed |
5ae4759c MM |
8512 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8513 | || (GET_CODE (operands[0]) == SUBREG | |
8514 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8515 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 8516 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
8517 | " |
8518 | { | |
8519 | long l; | |
8520 | REAL_VALUE_TYPE rv; | |
8521 | ||
8522 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8523 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 8524 | |
f99f88e0 DE |
8525 | if (! TARGET_POWERPC64) |
8526 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
8527 | else | |
8528 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 8529 | |
2496c7bd | 8530 | operands[3] = gen_int_mode (l, SImode); |
a260abc9 DE |
8531 | }") |
8532 | ||
c4c40373 | 8533 | (define_insn "*movsf_hardfloat" |
b991a865 GK |
8534 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!r,!r") |
8535 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,G,Fn"))] | |
d14a6d05 | 8536 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
8537 | || gpc_reg_operand (operands[1], SFmode)) |
8538 | && (TARGET_HARD_FLOAT && TARGET_FPRS)" | |
1fd4e8c1 | 8539 | "@ |
f99f88e0 DE |
8540 | mr %0,%1 |
8541 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
8542 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
8543 | fmr %0,%1 |
8544 | lfs%U1%X1 %0,%1 | |
c4c40373 | 8545 | stfs%U0%X0 %1,%0 |
b991a865 GK |
8546 | mt%0 %1 |
8547 | mt%0 %1 | |
8548 | mf%1 %0 | |
c4c40373 MM |
8549 | # |
8550 | #" | |
b991a865 GK |
8551 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*") |
8552 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 8553 | |
c4c40373 | 8554 | (define_insn "*movsf_softfloat" |
b991a865 GK |
8555 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r") |
8556 | (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn"))] | |
d14a6d05 | 8557 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
8558 | || gpc_reg_operand (operands[1], SFmode)) |
8559 | && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" | |
d14a6d05 MM |
8560 | "@ |
8561 | mr %0,%1 | |
b991a865 GK |
8562 | mt%0 %1 |
8563 | mt%0 %1 | |
8564 | mf%1 %0 | |
d14a6d05 MM |
8565 | {l%U1%X1|lwz%U1%X1} %0,%1 |
8566 | {st%U0%X0|stw%U0%X0} %1,%0 | |
8567 | {lil|li} %0,%1 | |
802a0058 | 8568 | {liu|lis} %0,%v1 |
aee86b38 | 8569 | {cal|la} %0,%a1 |
c4c40373 MM |
8570 | # |
8571 | #" | |
b991a865 GK |
8572 | [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*") |
8573 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 8574 | |
1fd4e8c1 RK |
8575 | \f |
8576 | (define_expand "movdf" | |
8577 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
8578 | (match_operand:DF 1 "any_operand" ""))] | |
8579 | "" | |
fb4d4348 | 8580 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
8581 | |
8582 | (define_split | |
cd2b37d9 | 8583 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 8584 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 8585 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
8586 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8587 | || (GET_CODE (operands[0]) == SUBREG | |
8588 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8589 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
8590 | [(set (match_dup 2) (match_dup 4)) |
8591 | (set (match_dup 3) (match_dup 1))] | |
8592 | " | |
8593 | { | |
5ae4759c | 8594 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
8595 | HOST_WIDE_INT value = INTVAL (operands[1]); |
8596 | ||
5ae4759c MM |
8597 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
8598 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
8599 | #if HOST_BITS_PER_WIDE_INT == 32 |
8600 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
8601 | #else | |
8602 | operands[4] = GEN_INT (value >> 32); | |
a65c591c | 8603 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
5f59ecb7 | 8604 | #endif |
c4c40373 MM |
8605 | }") |
8606 | ||
c4c40373 MM |
8607 | (define_split |
8608 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
8609 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 8610 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
8611 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8612 | || (GET_CODE (operands[0]) == SUBREG | |
8613 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8614 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
8615 | [(set (match_dup 2) (match_dup 4)) |
8616 | (set (match_dup 3) (match_dup 5))] | |
8617 | " | |
8618 | { | |
5ae4759c | 8619 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
8620 | long l[2]; |
8621 | REAL_VALUE_TYPE rv; | |
8622 | ||
8623 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8624 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
8625 | ||
5ae4759c MM |
8626 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
8627 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
2496c7bd LB |
8628 | operands[4] = gen_int_mode (l[endian], SImode); |
8629 | operands[5] = gen_int_mode (l[1 - endian], SImode); | |
c4c40373 MM |
8630 | }") |
8631 | ||
efc08378 DE |
8632 | (define_split |
8633 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 8634 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 8635 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
8636 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8637 | || (GET_CODE (operands[0]) == SUBREG | |
8638 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8639 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 8640 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 8641 | " |
a260abc9 DE |
8642 | { |
8643 | int endian = (WORDS_BIG_ENDIAN == 0); | |
8644 | long l[2]; | |
8645 | REAL_VALUE_TYPE rv; | |
4977bab6 | 8646 | #if HOST_BITS_PER_WIDE_INT >= 64 |
5b029315 | 8647 | HOST_WIDE_INT val; |
4977bab6 | 8648 | #endif |
a260abc9 DE |
8649 | |
8650 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8651 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
8652 | ||
8653 | operands[2] = gen_lowpart (DImode, operands[0]); | |
8654 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
5b029315 | 8655 | #if HOST_BITS_PER_WIDE_INT >= 64 |
a2419b96 DE |
8656 | val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 |
8657 | | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); | |
5b029315 | 8658 | |
f5264b52 | 8659 | operands[3] = gen_int_mode (val, DImode); |
5b029315 | 8660 | #else |
a260abc9 | 8661 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); |
5b029315 | 8662 | #endif |
a260abc9 | 8663 | }") |
efc08378 | 8664 | |
4eae5fe1 | 8665 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 8666 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
8667 | ;; a non-offsettable memref, but also it is less efficient than loading |
8668 | ;; the constant into an FP register, since it will probably be used there. | |
8669 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
8670 | ;; of handling these non-offsettable values. | |
c4c40373 | 8671 | (define_insn "*movdf_hardfloat32" |
914a7297 DE |
8672 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") |
8673 | (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] | |
a3170dc6 | 8674 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
8675 | && (gpc_reg_operand (operands[0], DFmode) |
8676 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
8677 | "* |
8678 | { | |
8679 | switch (which_alternative) | |
8680 | { | |
a260abc9 | 8681 | default: |
a6c2a102 | 8682 | abort (); |
e7113111 RK |
8683 | case 0: |
8684 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
8685 | the first register operand 0 is the same as the second register |
8686 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 8687 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 8688 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 8689 | else |
deb9225a | 8690 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 8691 | case 1: |
2b97222d DE |
8692 | if (offsettable_memref_p (operands[1]) |
8693 | || (GET_CODE (operands[1]) == MEM | |
69f51a21 DE |
8694 | && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM |
8695 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC | |
8696 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))) | |
000034eb DE |
8697 | { |
8698 | /* If the low-address word is used in the address, we must load | |
8699 | it last. Otherwise, load it first. Note that we cannot have | |
8700 | auto-increment in that case since the address register is | |
8701 | known to be dead. */ | |
8702 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8703 | operands[1], 0)) | |
8704 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
8705 | else | |
8706 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8707 | } | |
e7113111 | 8708 | else |
000034eb DE |
8709 | { |
8710 | rtx addreg; | |
8711 | ||
000034eb DE |
8712 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
8713 | if (refers_to_regno_p (REGNO (operands[0]), | |
8714 | REGNO (operands[0]) + 1, | |
8715 | operands[1], 0)) | |
8716 | { | |
8717 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 8718 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 8719 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 8720 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
8721 | } |
8722 | else | |
8723 | { | |
2b97222d | 8724 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 8725 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8726 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
8727 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8728 | return \"\"; | |
8729 | } | |
8730 | } | |
e7113111 | 8731 | case 2: |
2b97222d DE |
8732 | if (offsettable_memref_p (operands[0]) |
8733 | || (GET_CODE (operands[0]) == MEM | |
69f51a21 DE |
8734 | && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM |
8735 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC | |
8736 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))) | |
000034eb DE |
8737 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8738 | else | |
8739 | { | |
8740 | rtx addreg; | |
8741 | ||
000034eb | 8742 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 8743 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 8744 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8745 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
8746 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8747 | return \"\"; | |
8748 | } | |
e7113111 | 8749 | case 3: |
914a7297 | 8750 | return \"fmr %0,%1\"; |
e7113111 | 8751 | case 4: |
914a7297 | 8752 | return \"lfd%U1%X1 %0,%1\"; |
e7113111 | 8753 | case 5: |
914a7297 | 8754 | return \"stfd%U0%X0 %1,%0\"; |
e7113111 | 8755 | case 6: |
c4c40373 | 8756 | case 7: |
c4c40373 | 8757 | case 8: |
914a7297 | 8758 | return \"#\"; |
e7113111 RK |
8759 | } |
8760 | }" | |
914a7297 DE |
8761 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*") |
8762 | (set_attr "length" "8,16,16,4,4,4,8,12,16")]) | |
51b8fc2c | 8763 | |
c4c40373 | 8764 | (define_insn "*movdf_softfloat32" |
1427100a DE |
8765 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
8766 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
a3170dc6 | 8767 | "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
8768 | && (gpc_reg_operand (operands[0], DFmode) |
8769 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8770 | "* |
8771 | { | |
8772 | switch (which_alternative) | |
8773 | { | |
a260abc9 | 8774 | default: |
a6c2a102 | 8775 | abort (); |
dc4f83ca MM |
8776 | case 0: |
8777 | /* We normally copy the low-numbered register first. However, if | |
8778 | the first register operand 0 is the same as the second register of | |
8779 | operand 1, we must copy in the opposite order. */ | |
8780 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8781 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8782 | else | |
8783 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8784 | case 1: | |
3cb999d8 DE |
8785 | /* If the low-address word is used in the address, we must load |
8786 | it last. Otherwise, load it first. Note that we cannot have | |
8787 | auto-increment in that case since the address register is | |
8788 | known to be dead. */ | |
dc4f83ca | 8789 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 8790 | operands[1], 0)) |
dc4f83ca MM |
8791 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
8792 | else | |
8793 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8794 | case 2: | |
8795 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
8796 | case 3: | |
c4c40373 MM |
8797 | case 4: |
8798 | case 5: | |
dc4f83ca MM |
8799 | return \"#\"; |
8800 | } | |
8801 | }" | |
c4c40373 MM |
8802 | [(set_attr "type" "*,load,store,*,*,*") |
8803 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 8804 | |
c4c40373 | 8805 | (define_insn "*movdf_hardfloat64" |
914a7297 DE |
8806 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!cl,!r,!r,!r,!r") |
8807 | (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,r,h,G,H,F"))] | |
a3170dc6 | 8808 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
8809 | && (gpc_reg_operand (operands[0], DFmode) |
8810 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 8811 | "@ |
3d5570cb RK |
8812 | mr %0,%1 |
8813 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8814 | std%U0%X0 %1,%0 |
3d5570cb | 8815 | fmr %0,%1 |
f63184ac | 8816 | lfd%U1%X1 %0,%1 |
914a7297 DE |
8817 | stfd%U0%X0 %1,%0 |
8818 | mt%0 %1 | |
8819 | mf%1 %0 | |
8820 | # | |
8821 | # | |
8822 | #" | |
8823 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*") | |
8824 | (set_attr "length" "4,4,4,4,4,4,4,4,8,12,16")]) | |
dc4f83ca | 8825 | |
c4c40373 | 8826 | (define_insn "*movdf_softfloat64" |
914a7297 DE |
8827 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r") |
8828 | (match_operand:DF 1 "input_operand" "r,r,h,m,r,G,H,F"))] | |
a3170dc6 | 8829 | "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
8830 | && (gpc_reg_operand (operands[0], DFmode) |
8831 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8832 | "@ |
8833 | mr %0,%1 | |
914a7297 DE |
8834 | mt%0 %1 |
8835 | mf%1 %0 | |
dc4f83ca | 8836 | ld%U1%X1 %0,%1 |
96bb8ed3 | 8837 | std%U0%X0 %1,%0 |
c4c40373 MM |
8838 | # |
8839 | # | |
dc4f83ca | 8840 | #" |
914a7297 DE |
8841 | [(set_attr "type" "*,*,*,load,store,*,*,*") |
8842 | (set_attr "length" "4,4,4,4,4,8,12,16")]) | |
1fd4e8c1 | 8843 | \f |
06f4e019 DE |
8844 | (define_expand "movtf" |
8845 | [(set (match_operand:TF 0 "general_operand" "") | |
8846 | (match_operand:TF 1 "any_operand" ""))] | |
a3170dc6 AH |
8847 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8848 | && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8849 | "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") |
8850 | ||
8851 | (define_insn "*movtf_internal" | |
8852 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,m,!r,!r,!r") | |
8853 | (match_operand:TF 1 "input_operand" "f,m,f,G,H,F"))] | |
a3170dc6 AH |
8854 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8855 | && TARGET_LONG_DOUBLE_128 | |
06f4e019 DE |
8856 | && (gpc_reg_operand (operands[0], TFmode) |
8857 | || gpc_reg_operand (operands[1], TFmode))" | |
8858 | "* | |
8859 | { | |
8860 | switch (which_alternative) | |
8861 | { | |
8862 | default: | |
8863 | abort (); | |
8864 | case 0: | |
8865 | /* We normally copy the low-numbered register first. However, if | |
8866 | the first register operand 0 is the same as the second register of | |
8867 | operand 1, we must copy in the opposite order. */ | |
8868 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8869 | return \"fmr %L0,%L1\;fmr %0,%1\"; | |
8870 | else | |
8871 | return \"fmr %0,%1\;fmr %L0,%L1\"; | |
8872 | case 1: | |
f5264b52 | 8873 | return \"lfd %0,%1\;lfd %L0,%Y1\"; |
06f4e019 | 8874 | case 2: |
f5264b52 | 8875 | return \"stfd %1,%0\;stfd %L1,%Y0\"; |
06f4e019 DE |
8876 | case 3: |
8877 | case 4: | |
8878 | case 5: | |
8879 | return \"#\"; | |
8880 | } | |
8881 | }" | |
8882 | [(set_attr "type" "fp,fpload,fpstore,*,*,*") | |
8883 | (set_attr "length" "8,8,8,12,16,20")]) | |
8884 | ||
8885 | (define_split | |
8886 | [(set (match_operand:TF 0 "gpc_reg_operand" "") | |
f5264b52 | 8887 | (match_operand:TF 1 "easy_fp_constant" ""))] |
fcce224d DE |
8888 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8889 | && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_POWERPC64 | |
8890 | && TARGET_LONG_DOUBLE_128 && reload_completed | |
8891 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) | |
8892 | || (GET_CODE (operands[0]) == SUBREG | |
8893 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8894 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
8895 | [(set (match_dup 2) (match_dup 6)) | |
8896 | (set (match_dup 3) (match_dup 7)) | |
8897 | (set (match_dup 4) (match_dup 8)) | |
8898 | (set (match_dup 5) (match_dup 9))] | |
8899 | " | |
8900 | { | |
8901 | long l[4]; | |
8902 | REAL_VALUE_TYPE rv; | |
8903 | ||
8904 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8905 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l); | |
8906 | ||
8907 | operands[2] = operand_subword (operands[0], 0, 0, TFmode); | |
8908 | operands[3] = operand_subword (operands[0], 1, 0, TFmode); | |
8909 | operands[4] = operand_subword (operands[0], 2, 0, TFmode); | |
8910 | operands[5] = operand_subword (operands[0], 3, 0, TFmode); | |
8911 | operands[6] = gen_int_mode (l[0], SImode); | |
8912 | operands[7] = gen_int_mode (l[1], SImode); | |
8913 | operands[8] = gen_int_mode (l[2], SImode); | |
8914 | operands[9] = gen_int_mode (l[3], SImode); | |
8915 | }") | |
8916 | ||
8917 | (define_split | |
8918 | [(set (match_operand:TF 0 "gpc_reg_operand" "") | |
8919 | (match_operand:TF 1 "easy_fp_constant" ""))] | |
8920 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8921 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 | |
8922 | && TARGET_LONG_DOUBLE_128 && reload_completed | |
8923 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) | |
8924 | || (GET_CODE (operands[0]) == SUBREG | |
8925 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8926 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
8927 | [(set (match_dup 2) (match_dup 4)) | |
8928 | (set (match_dup 3) (match_dup 5))] | |
06f4e019 DE |
8929 | " |
8930 | { | |
fcce224d DE |
8931 | long l[4]; |
8932 | REAL_VALUE_TYPE rv; | |
d24652ee | 8933 | #if HOST_BITS_PER_WIDE_INT >= 64 |
f5264b52 | 8934 | HOST_WIDE_INT val; |
d24652ee | 8935 | #endif |
fcce224d DE |
8936 | |
8937 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8938 | REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l); | |
8939 | ||
f5264b52 DE |
8940 | operands[2] = gen_lowpart (DImode, operands[0]); |
8941 | operands[3] = gen_highpart (DImode, operands[0]); | |
8942 | #if HOST_BITS_PER_WIDE_INT >= 64 | |
a2419b96 DE |
8943 | val = ((HOST_WIDE_INT)(unsigned long)l[0] << 32 |
8944 | | ((HOST_WIDE_INT)(unsigned long)l[1])); | |
f5264b52 DE |
8945 | operands[4] = gen_int_mode (val, DImode); |
8946 | ||
a2419b96 DE |
8947 | val = ((HOST_WIDE_INT)(unsigned long)l[2] << 32 |
8948 | | ((HOST_WIDE_INT)(unsigned long)l[3])); | |
f5264b52 DE |
8949 | operands[5] = gen_int_mode (val, DImode); |
8950 | #else | |
8951 | operands[4] = immed_double_const (l[1], l[0], DImode); | |
8952 | operands[5] = immed_double_const (l[3], l[2], DImode); | |
8953 | #endif | |
06f4e019 DE |
8954 | }") |
8955 | ||
a2419b96 | 8956 | (define_insn "extenddftf2" |
06f4e019 DE |
8957 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
8958 | (float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
8959 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8960 | && TARGET_LONG_DOUBLE_128" | |
a2419b96 | 8961 | "* |
06f4e019 | 8962 | { |
a2419b96 DE |
8963 | if (REGNO (operands[0]) == REGNO (operands[1])) |
8964 | return \"fsub %L0,%L0,%L0\"; | |
8965 | else | |
8966 | return \"fmr %0,%1\;fsub %L0,%L0,%L0\"; | |
8967 | }" | |
8968 | [(set_attr "type" "fp")]) | |
06f4e019 | 8969 | |
a2419b96 | 8970 | (define_insn "extendsftf2" |
06f4e019 DE |
8971 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
8972 | (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
8973 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8974 | && TARGET_LONG_DOUBLE_128" | |
a2419b96 | 8975 | "* |
06f4e019 | 8976 | { |
a2419b96 DE |
8977 | if (REGNO (operands[0]) == REGNO (operands[1])) |
8978 | return \"fsub %L0,%L0,%L0\"; | |
8979 | else | |
8980 | return \"fmr %0,%1\;fsub %L0,%L0,%L0\"; | |
8981 | }" | |
8982 | [(set_attr "type" "fp")]) | |
06f4e019 DE |
8983 | |
8984 | (define_insn "trunctfdf2" | |
8985 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8986 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
8987 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
8988 | && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8989 | "fadd %0,%1,%L1" |
8990 | [(set_attr "type" "fp") | |
8991 | (set_attr "length" "8")]) | |
8992 | ||
8993 | (define_insn_and_split "trunctfsf2" | |
8994 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
ea112fc4 DE |
8995 | (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8996 | (clobber (match_scratch:DF 2 "=f"))] | |
a3170dc6 AH |
8997 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT |
8998 | && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8999 | "#" |
ea112fc4 | 9000 | "&& reload_completed" |
06f4e019 DE |
9001 | [(set (match_dup 2) |
9002 | (float_truncate:DF (match_dup 1))) | |
9003 | (set (match_dup 0) | |
9004 | (float_truncate:SF (match_dup 2)))] | |
ea112fc4 | 9005 | "") |
06f4e019 | 9006 | |
ea112fc4 DE |
9007 | (define_insn_and_split "floatditf2" |
9008 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 9009 | (float:TF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 DE |
9010 | (clobber (match_scratch:DF 2 "=f"))] |
9011 | "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 | |
a3170dc6 | 9012 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" |
ea112fc4 DE |
9013 | "#" |
9014 | "&& reload_completed" | |
06f4e019 | 9015 | [(set (match_dup 2) |
a2419b96 DE |
9016 | (float:DF (match_dup 1))) |
9017 | (set (match_dup 0) | |
06f4e019 | 9018 | (float_extend:TF (match_dup 2)))] |
ea112fc4 | 9019 | "") |
06f4e019 | 9020 | |
ea112fc4 DE |
9021 | (define_insn_and_split "floatsitf2" |
9022 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 9023 | (float:TF (match_operand:SI 1 "gpc_reg_operand" "r"))) |
ea112fc4 | 9024 | (clobber (match_scratch:DF 2 "=f"))] |
a3170dc6 AH |
9025 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
9026 | && TARGET_LONG_DOUBLE_128" | |
ea112fc4 DE |
9027 | "#" |
9028 | "&& reload_completed" | |
06f4e019 | 9029 | [(set (match_dup 2) |
a2419b96 DE |
9030 | (float:DF (match_dup 1))) |
9031 | (set (match_dup 0) | |
06f4e019 | 9032 | (float_extend:TF (match_dup 2)))] |
ea112fc4 | 9033 | "") |
06f4e019 | 9034 | |
ea112fc4 | 9035 | (define_insn_and_split "fix_trunctfdi2" |
61c07d3c | 9036 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
a2419b96 DE |
9037 | (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f"))) |
9038 | (clobber (match_scratch:DF 2 "=f"))] | |
ea112fc4 | 9039 | "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 |
a3170dc6 | 9040 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" |
ea112fc4 DE |
9041 | "#" |
9042 | "&& reload_completed" | |
06f4e019 | 9043 | [(set (match_dup 2) |
a2419b96 DE |
9044 | (float_truncate:DF (match_dup 1))) |
9045 | (set (match_dup 0) | |
9046 | (fix:DI (match_dup 2)))] | |
ea112fc4 | 9047 | "") |
06f4e019 | 9048 | |
ea112fc4 | 9049 | (define_insn_and_split "fix_trunctfsi2" |
61c07d3c | 9050 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
a2419b96 DE |
9051 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) |
9052 | (clobber (match_scratch:DF 2 "=f"))] | |
a3170dc6 AH |
9053 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
9054 | && TARGET_LONG_DOUBLE_128" | |
ea112fc4 DE |
9055 | "#" |
9056 | "&& reload_completed" | |
06f4e019 | 9057 | [(set (match_dup 2) |
a2419b96 DE |
9058 | (float_truncate:DF (match_dup 1))) |
9059 | (set (match_dup 0) | |
06f4e019 | 9060 | (fix:SI (match_dup 2)))] |
ea112fc4 | 9061 | "") |
06f4e019 DE |
9062 | |
9063 | (define_insn "negtf2" | |
9064 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
9065 | (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
9066 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
9067 | && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
9068 | "* |
9069 | { | |
9070 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
9071 | return \"fneg %L0,%L1\;fneg %0,%1\"; | |
9072 | else | |
9073 | return \"fneg %0,%1\;fneg %L0,%L1\"; | |
9074 | }" | |
9075 | [(set_attr "type" "fp") | |
9076 | (set_attr "length" "8")]) | |
9077 | ||
9078 | (define_insn "abstf2" | |
9079 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
9080 | (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
9081 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
9082 | && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
9083 | "* |
9084 | { | |
9085 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
9086 | return \"fabs %L0,%L1\;fabs %0,%1\"; | |
9087 | else | |
9088 | return \"fabs %0,%1\;fabs %L0,%L1\"; | |
9089 | }" | |
9090 | [(set_attr "type" "fp") | |
9091 | (set_attr "length" "8")]) | |
9092 | ||
9093 | (define_insn "" | |
9094 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
9095 | (neg:TF (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 AH |
9096 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
9097 | && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
9098 | "* |
9099 | { | |
9100 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
9101 | return \"fnabs %L0,%L1\;fnabs %0,%1\"; | |
9102 | else | |
9103 | return \"fnabs %0,%1\;fnabs %L0,%L1\"; | |
9104 | }" | |
9105 | [(set_attr "type" "fp") | |
9106 | (set_attr "length" "8")]) | |
9107 | \f | |
1fd4e8c1 RK |
9108 | ;; Next come the multi-word integer load and store and the load and store |
9109 | ;; multiple insns. | |
9110 | (define_expand "movdi" | |
9111 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 9112 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 | 9113 | "" |
fb4d4348 | 9114 | "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") |
1fd4e8c1 | 9115 | |
acad7ed3 | 9116 | (define_insn "*movdi_internal32" |
4e74d8ec MM |
9117 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") |
9118 | (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] | |
a260abc9 | 9119 | "! TARGET_POWERPC64 |
4e74d8ec MM |
9120 | && (gpc_reg_operand (operands[0], DImode) |
9121 | || gpc_reg_operand (operands[1], DImode))" | |
1fd4e8c1 RK |
9122 | "* |
9123 | { | |
9124 | switch (which_alternative) | |
9125 | { | |
a260abc9 | 9126 | default: |
a6c2a102 | 9127 | abort (); |
1fd4e8c1 RK |
9128 | case 0: |
9129 | /* We normally copy the low-numbered register first. However, if | |
9130 | the first register operand 0 is the same as the second register of | |
9131 | operand 1, we must copy in the opposite order. */ | |
9132 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 9133 | return \"mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 9134 | else |
deb9225a | 9135 | return \"mr %0,%1\;mr %L0,%L1\"; |
1fd4e8c1 RK |
9136 | case 1: |
9137 | /* If the low-address word is used in the address, we must load it | |
9138 | last. Otherwise, load it first. Note that we cannot have | |
9139 | auto-increment in that case since the address register is known to be | |
9140 | dead. */ | |
9141 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 9142 | operands[1], 0)) |
ca7f5001 | 9143 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
1fd4e8c1 | 9144 | else |
ca7f5001 | 9145 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 | 9146 | case 2: |
ca7f5001 | 9147 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8ffd9c51 RK |
9148 | case 3: |
9149 | return \"fmr %0,%1\"; | |
9150 | case 4: | |
9151 | return \"lfd%U1%X1 %0,%1\"; | |
9152 | case 5: | |
9153 | return \"stfd%U0%X0 %1,%0\"; | |
4e74d8ec MM |
9154 | case 6: |
9155 | case 7: | |
9156 | case 8: | |
9157 | case 9: | |
9158 | case 10: | |
9159 | return \"#\"; | |
1fd4e8c1 RK |
9160 | } |
9161 | }" | |
4e74d8ec | 9162 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*") |
914a7297 | 9163 | (set_attr "length" "8,8,8,4,4,4,8,12,8,12,16")]) |
4e74d8ec MM |
9164 | |
9165 | (define_split | |
9166 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
9167 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 9168 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
9169 | [(set (match_dup 2) (match_dup 4)) |
9170 | (set (match_dup 3) (match_dup 1))] | |
9171 | " | |
9172 | { | |
5f59ecb7 | 9173 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
9174 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
9175 | DImode); | |
9176 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
9177 | DImode); | |
75d39459 | 9178 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 9179 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 9180 | #else |
5f59ecb7 | 9181 | operands[4] = GEN_INT (value >> 32); |
a65c591c | 9182 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
75d39459 | 9183 | #endif |
4e74d8ec MM |
9184 | }") |
9185 | ||
4e74d8ec MM |
9186 | (define_split |
9187 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
9188 | (match_operand:DI 1 "const_double_operand" ""))] | |
75d39459 | 9189 | "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
9190 | [(set (match_dup 2) (match_dup 4)) |
9191 | (set (match_dup 3) (match_dup 5))] | |
9192 | " | |
9193 | { | |
bdaa0181 GK |
9194 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
9195 | DImode); | |
9196 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
9197 | DImode); | |
f6968f59 MM |
9198 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
9199 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
4e74d8ec MM |
9200 | }") |
9201 | ||
acad7ed3 | 9202 | (define_insn "*movdi_internal64" |
5d7e6254 | 9203 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h") |
9615f239 | 9204 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 9205 | "TARGET_POWERPC64 |
4e74d8ec MM |
9206 | && (gpc_reg_operand (operands[0], DImode) |
9207 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 9208 | "@ |
3d5570cb RK |
9209 | mr %0,%1 |
9210 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 9211 | std%U0%X0 %1,%0 |
3d5570cb | 9212 | li %0,%1 |
802a0058 | 9213 | lis %0,%v1 |
e6ca2c17 | 9214 | # |
aee86b38 | 9215 | {cal|la} %0,%a1 |
3d5570cb RK |
9216 | fmr %0,%1 |
9217 | lfd%U1%X1 %0,%1 | |
9218 | stfd%U0%X0 %1,%0 | |
9219 | mf%1 %0 | |
08075ead | 9220 | mt%0 %1 |
e34eaae5 | 9221 | {cror 0,0,0|nop}" |
b7ff3d82 | 9222 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*") |
e6ca2c17 DE |
9223 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
9224 | ||
5f59ecb7 | 9225 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
9226 | (define_insn "" |
9227 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
9228 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
9229 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
9230 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
9231 | && num_insns_constant (operands[1], DImode) == 1" |
9232 | "* | |
9233 | { | |
9234 | return ((unsigned HOST_WIDE_INT) | |
9235 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
9236 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
9237 | }") | |
9238 | ||
a260abc9 DE |
9239 | ;; Generate all one-bits and clear left or right. |
9240 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
9241 | (define_split | |
9242 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
9243 | (match_operand:DI 1 "mask64_operand" ""))] | |
9244 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
9245 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 9246 | (set (match_dup 0) |
a260abc9 DE |
9247 | (and:DI (rotate:DI (match_dup 0) |
9248 | (const_int 0)) | |
9249 | (match_dup 1)))] | |
9250 | "") | |
9251 | ||
9252 | ;; Split a load of a large constant into the appropriate five-instruction | |
9253 | ;; sequence. Handle anything in a constant number of insns. | |
9254 | ;; When non-easy constants can go in the TOC, this should use | |
9255 | ;; easy_fp_constant predicate. | |
9256 | (define_split | |
9257 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
9258 | (match_operand:DI 1 "const_int_operand" ""))] |
9259 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
9260 | [(set (match_dup 0) (match_dup 2)) | |
9261 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
e6ca2c17 | 9262 | " |
2bfcf297 DB |
9263 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
9264 | ||
9265 | if (tem == operands[0]) | |
9266 | DONE; | |
e8d791dd | 9267 | else |
2bfcf297 | 9268 | FAIL; |
5f59ecb7 | 9269 | }") |
e6ca2c17 | 9270 | |
5f59ecb7 DE |
9271 | (define_split |
9272 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
9273 | (match_operand:DI 1 "const_double_operand" ""))] |
9274 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
9275 | [(set (match_dup 0) (match_dup 2)) | |
9276 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
5f59ecb7 | 9277 | " |
2bfcf297 DB |
9278 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
9279 | ||
9280 | if (tem == operands[0]) | |
9281 | DONE; | |
9282 | else | |
9283 | FAIL; | |
e6ca2c17 | 9284 | }") |
08075ead | 9285 | |
2bfcf297 | 9286 | ;; Split a load of a large constant into the appropriate five-instruction |
acad7ed3 | 9287 | (define_insn "*movdi_internal2" |
9ebbca7d GK |
9288 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
9289 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
08075ead | 9290 | (const_int 0))) |
9ebbca7d | 9291 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
08075ead | 9292 | "TARGET_POWERPC64" |
9ebbca7d GK |
9293 | "@ |
9294 | mr. %0,%1 | |
9295 | #" | |
9296 | [(set_attr "type" "compare") | |
9297 | (set_attr "length" "4,8")]) | |
acad7ed3 | 9298 | |
9ebbca7d GK |
9299 | (define_split |
9300 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
9301 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
9302 | (const_int 0))) | |
9303 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
9304 | "TARGET_POWERPC64 && reload_completed" | |
9305 | [(set (match_dup 0) (match_dup 1)) | |
9306 | (set (match_dup 2) | |
9307 | (compare:CC (match_dup 0) | |
9308 | (const_int 0)))] | |
9309 | "") | |
acad7ed3 | 9310 | \f |
1fd4e8c1 RK |
9311 | ;; TImode is similar, except that we usually want to compute the address into |
9312 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 9313 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
9314 | (define_expand "movti" |
9315 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
9316 | (match_operand:TI 1 "general_operand" "")) | |
9317 | (clobber (scratch:SI))])] | |
7e69e155 | 9318 | "TARGET_STRING || TARGET_POWERPC64" |
fb4d4348 | 9319 | "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") |
1fd4e8c1 RK |
9320 | |
9321 | ;; We say that MQ is clobbered in the last alternative because the first | |
9322 | ;; alternative would never get used otherwise since it would need a reload | |
9323 | ;; while the 2nd alternative would not. We put memory cases first so they | |
9324 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
9325 | ;; giving the SCRATCH mq. | |
a260abc9 | 9326 | (define_insn "*movti_power" |
e1469d0d | 9327 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
9328 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
9329 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
7e69e155 | 9330 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 9331 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
9332 | "* |
9333 | { | |
9334 | switch (which_alternative) | |
9335 | { | |
dc4f83ca MM |
9336 | default: |
9337 | abort (); | |
9338 | ||
1fd4e8c1 | 9339 | case 0: |
ca7f5001 | 9340 | return \"{stsi|stswi} %1,%P0,16\"; |
1fd4e8c1 | 9341 | case 1: |
ca7f5001 | 9342 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
1fd4e8c1 RK |
9343 | case 2: |
9344 | /* Normally copy registers with lowest numbered register copied first. | |
9345 | But copy in the other order if the first register of the output | |
9346 | is the second, third, or fourth register in the input. */ | |
9347 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
9348 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
deb9225a | 9349 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 9350 | else |
deb9225a | 9351 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; |
1fd4e8c1 RK |
9352 | case 3: |
9353 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
9354 | fall through to generating four loads. */ | |
9355 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 9356 | return \"{lsi|lswi} %0,%P1,16\"; |
82e41834 | 9357 | /* ... fall through ... */ |
1fd4e8c1 RK |
9358 | case 4: |
9359 | /* If the address register is the same as the register for the lowest- | |
9360 | addressed word, load it last. Similarly for the next two words. | |
9361 | Otherwise load lowest address to highest. */ | |
9362 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
9363 | operands[1], 0)) | |
ca7f5001 | 9364 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; |
1fd4e8c1 RK |
9365 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, |
9366 | REGNO (operands[0]) + 2, operands[1], 0)) | |
ca7f5001 | 9367 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 RK |
9368 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, |
9369 | REGNO (operands[0]) + 3, operands[1], 0)) | |
ca7f5001 | 9370 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; |
1fd4e8c1 | 9371 | else |
ca7f5001 | 9372 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; |
1fd4e8c1 RK |
9373 | } |
9374 | }" | |
b7ff3d82 | 9375 | [(set_attr "type" "store,store,*,load,load") |
914a7297 | 9376 | (set_attr "length" "4,16,16,4,16")]) |
51b8fc2c | 9377 | |
a260abc9 | 9378 | (define_insn "*movti_string" |
cd1d3445 | 9379 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
27dc0551 | 9380 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))] |
0ad91047 | 9381 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
9382 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
9383 | "* | |
9384 | { | |
9385 | switch (which_alternative) | |
9386 | { | |
9387 | default: | |
9388 | abort (); | |
9389 | ||
9390 | case 0: | |
cd1d3445 | 9391 | return \"{stsi|stswi} %1,%P0,16\"; |
dc4f83ca | 9392 | case 1: |
cd1d3445 DE |
9393 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
9394 | case 2: | |
dc4f83ca MM |
9395 | /* Normally copy registers with lowest numbered register copied first. |
9396 | But copy in the other order if the first register of the output | |
9397 | is the second, third, or fourth register in the input. */ | |
9398 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
9399 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
9400 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; | |
9401 | else | |
9402 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; | |
cd1d3445 DE |
9403 | case 3: |
9404 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
9405 | fall through to generating four loads. */ | |
9406 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
9407 | return \"{lsi|lswi} %0,%P1,16\"; | |
9408 | /* ... fall through ... */ | |
9409 | case 4: | |
dc4f83ca MM |
9410 | /* If the address register is the same as the register for the lowest- |
9411 | addressed word, load it last. Similarly for the next two words. | |
9412 | Otherwise load lowest address to highest. */ | |
9413 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
9414 | operands[1], 0)) | |
9415 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; | |
9416 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, | |
9417 | REGNO (operands[0]) + 2, operands[1], 0)) | |
9418 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; | |
9419 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, | |
9420 | REGNO (operands[0]) + 3, operands[1], 0)) | |
9421 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; | |
9422 | else | |
9423 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; | |
9424 | } | |
9425 | }" | |
cd1d3445 DE |
9426 | [(set_attr "type" "store,store,*,load,load") |
9427 | (set_attr "length" "4,16,16,4,16")]) | |
dc4f83ca | 9428 | |
a260abc9 | 9429 | (define_insn "*movti_ppc64" |
51b8fc2c RK |
9430 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") |
9431 | (match_operand:TI 1 "input_operand" "r,m,r"))] | |
9432 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) | |
9433 | || gpc_reg_operand (operands[1], TImode))" | |
9434 | "* | |
9435 | { | |
9436 | switch (which_alternative) | |
9437 | { | |
a260abc9 | 9438 | default: |
a6c2a102 | 9439 | abort (); |
51b8fc2c RK |
9440 | case 0: |
9441 | /* We normally copy the low-numbered register first. However, if | |
9442 | the first register operand 0 is the same as the second register of | |
9443 | operand 1, we must copy in the opposite order. */ | |
9444 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
9445 | return \"mr %L0,%L1\;mr %0,%1\"; | |
9446 | else | |
9447 | return \"mr %0,%1\;mr %L0,%L1\"; | |
9448 | case 1: | |
9449 | /* If the low-address word is used in the address, we must load it | |
9450 | last. Otherwise, load it first. Note that we cannot have | |
9451 | auto-increment in that case since the address register is known to be | |
9452 | dead. */ | |
9453 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 9454 | operands[1], 0)) |
51b8fc2c RK |
9455 | return \"ld %L0,%L1\;ld %0,%1\"; |
9456 | else | |
9457 | return \"ld%U1 %0,%1\;ld %L0,%L1\"; | |
9458 | case 2: | |
9459 | return \"std%U0 %1,%0\;std %L1,%L0\"; | |
9460 | } | |
9461 | }" | |
b7ff3d82 | 9462 | [(set_attr "type" "*,load,store") |
51b8fc2c | 9463 | (set_attr "length" "8,8,8")]) |
1fd4e8c1 RK |
9464 | \f |
9465 | (define_expand "load_multiple" | |
2f622005 RK |
9466 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
9467 | (match_operand:SI 1 "" "")) | |
9468 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 9469 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
9470 | " |
9471 | { | |
9472 | int regno; | |
9473 | int count; | |
792760b9 | 9474 | rtx op1; |
1fd4e8c1 RK |
9475 | int i; |
9476 | ||
9477 | /* Support only loading a constant number of fixed-point registers from | |
9478 | memory and only bother with this if more than two; the machine | |
9479 | doesn't support more than eight. */ | |
9480 | if (GET_CODE (operands[2]) != CONST_INT | |
9481 | || INTVAL (operands[2]) <= 2 | |
9482 | || INTVAL (operands[2]) > 8 | |
9483 | || GET_CODE (operands[1]) != MEM | |
9484 | || GET_CODE (operands[0]) != REG | |
9485 | || REGNO (operands[0]) >= 32) | |
9486 | FAIL; | |
9487 | ||
9488 | count = INTVAL (operands[2]); | |
9489 | regno = REGNO (operands[0]); | |
9490 | ||
39403d82 | 9491 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
9492 | op1 = replace_equiv_address (operands[1], |
9493 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
9494 | |
9495 | for (i = 0; i < count; i++) | |
9496 | XVECEXP (operands[3], 0, i) | |
39403d82 | 9497 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
7ef788f0 | 9498 | adjust_address_nv (op1, SImode, i * 4)); |
1fd4e8c1 RK |
9499 | }") |
9500 | ||
9caa3eb2 | 9501 | (define_insn "*ldmsi8" |
1fd4e8c1 | 9502 | [(match_parallel 0 "load_multiple_operation" |
9caa3eb2 DE |
9503 | [(set (match_operand:SI 2 "gpc_reg_operand" "") |
9504 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
9505 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
9506 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
9507 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
9508 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
9509 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
9510 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
9511 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
9512 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
9513 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
9514 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
9515 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
9516 | (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
9517 | (set (match_operand:SI 9 "gpc_reg_operand" "") | |
9518 | (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] | |
9519 | "TARGET_STRING && XVECLEN (operands[0], 0) == 8" | |
1fd4e8c1 | 9520 | "* |
9caa3eb2 DE |
9521 | { return rs6000_output_load_multiple (operands); }" |
9522 | [(set_attr "type" "load") | |
9523 | (set_attr "length" "32")]) | |
1fd4e8c1 | 9524 | |
9caa3eb2 DE |
9525 | (define_insn "*ldmsi7" |
9526 | [(match_parallel 0 "load_multiple_operation" | |
9527 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
9528 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
9529 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
9530 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
9531 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
9532 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
9533 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
9534 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
9535 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
9536 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
9537 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
9538 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
9539 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
9540 | (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] | |
9541 | "TARGET_STRING && XVECLEN (operands[0], 0) == 7" | |
9542 | "* | |
9543 | { return rs6000_output_load_multiple (operands); }" | |
9544 | [(set_attr "type" "load") | |
9545 | (set_attr "length" "32")]) | |
9546 | ||
9547 | (define_insn "*ldmsi6" | |
9548 | [(match_parallel 0 "load_multiple_operation" | |
9549 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
9550 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
9551 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
9552 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
9553 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
9554 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
9555 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
9556 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
9557 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
9558 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
9559 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
9560 | (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] | |
9561 | "TARGET_STRING && XVECLEN (operands[0], 0) == 6" | |
9562 | "* | |
9563 | { return rs6000_output_load_multiple (operands); }" | |
9564 | [(set_attr "type" "load") | |
9565 | (set_attr "length" "32")]) | |
9566 | ||
9567 | (define_insn "*ldmsi5" | |
9568 | [(match_parallel 0 "load_multiple_operation" | |
9569 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
9570 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
9571 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
9572 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
9573 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
9574 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
9575 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
9576 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
9577 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
9578 | (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] | |
9579 | "TARGET_STRING && XVECLEN (operands[0], 0) == 5" | |
9580 | "* | |
9581 | { return rs6000_output_load_multiple (operands); }" | |
9582 | [(set_attr "type" "load") | |
9583 | (set_attr "length" "32")]) | |
9584 | ||
9585 | (define_insn "*ldmsi4" | |
9586 | [(match_parallel 0 "load_multiple_operation" | |
9587 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
9588 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
9589 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
9590 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
9591 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
9592 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
9593 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
9594 | (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] | |
9595 | "TARGET_STRING && XVECLEN (operands[0], 0) == 4" | |
9596 | "* | |
9597 | { return rs6000_output_load_multiple (operands); }" | |
9598 | [(set_attr "type" "load") | |
9599 | (set_attr "length" "32")]) | |
9600 | ||
9601 | (define_insn "*ldmsi3" | |
9602 | [(match_parallel 0 "load_multiple_operation" | |
9603 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
9604 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
9605 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
9606 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
9607 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
9608 | (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] | |
9609 | "TARGET_STRING && XVECLEN (operands[0], 0) == 3" | |
9610 | "* | |
9611 | { return rs6000_output_load_multiple (operands); }" | |
b19003d8 | 9612 | [(set_attr "type" "load") |
e82ee4cc | 9613 | (set_attr "length" "32")]) |
b19003d8 | 9614 | |
1fd4e8c1 | 9615 | (define_expand "store_multiple" |
2f622005 RK |
9616 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
9617 | (match_operand:SI 1 "" "")) | |
9618 | (clobber (scratch:SI)) | |
9619 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 9620 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
9621 | " |
9622 | { | |
9623 | int regno; | |
9624 | int count; | |
9625 | rtx to; | |
792760b9 | 9626 | rtx op0; |
1fd4e8c1 RK |
9627 | int i; |
9628 | ||
9629 | /* Support only storing a constant number of fixed-point registers to | |
9630 | memory and only bother with this if more than two; the machine | |
9631 | doesn't support more than eight. */ | |
9632 | if (GET_CODE (operands[2]) != CONST_INT | |
9633 | || INTVAL (operands[2]) <= 2 | |
9634 | || INTVAL (operands[2]) > 8 | |
9635 | || GET_CODE (operands[0]) != MEM | |
9636 | || GET_CODE (operands[1]) != REG | |
9637 | || REGNO (operands[1]) >= 32) | |
9638 | FAIL; | |
9639 | ||
9640 | count = INTVAL (operands[2]); | |
9641 | regno = REGNO (operands[1]); | |
9642 | ||
39403d82 | 9643 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 9644 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 9645 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
9646 | |
9647 | XVECEXP (operands[3], 0, 0) | |
7ef788f0 | 9648 | = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]); |
39403d82 | 9649 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 9650 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
9651 | |
9652 | for (i = 1; i < count; i++) | |
9653 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 9654 | = gen_rtx_SET (VOIDmode, |
7ef788f0 | 9655 | adjust_address_nv (op0, SImode, i * 4), |
c5c76735 | 9656 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
9657 | }") |
9658 | ||
9caa3eb2 | 9659 | (define_insn "*store_multiple_power" |
1fd4e8c1 RK |
9660 | [(match_parallel 0 "store_multiple_operation" |
9661 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 9662 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9663 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 9664 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
9665 | "{stsi|stswi} %2,%P1,%O0" |
9666 | [(set_attr "type" "store")]) | |
d14a6d05 | 9667 | |
e46e3130 | 9668 | (define_insn "*stmsi8" |
d14a6d05 | 9669 | [(match_parallel 0 "store_multiple_operation" |
e46e3130 DJ |
9670 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
9671 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9672 | (clobber (match_scratch:SI 3 "X")) | |
9673 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9674 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9675 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9676 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9677 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9678 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9679 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9680 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9681 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9682 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
9683 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
9684 | (match_operand:SI 9 "gpc_reg_operand" "r")) | |
9685 | (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
9686 | (match_operand:SI 10 "gpc_reg_operand" "r"))])] | |
9687 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9" | |
9688 | "{stsi|stswi} %2,%1,%O0" | |
9689 | [(set_attr "type" "store")]) | |
9690 | ||
9691 | (define_insn "*stmsi7" | |
9692 | [(match_parallel 0 "store_multiple_operation" | |
9693 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9694 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9695 | (clobber (match_scratch:SI 3 "X")) | |
9696 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9697 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9698 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9699 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9700 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9701 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9702 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9703 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9704 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9705 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
9706 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
9707 | (match_operand:SI 9 "gpc_reg_operand" "r"))])] | |
9708 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8" | |
9709 | "{stsi|stswi} %2,%1,%O0" | |
9710 | [(set_attr "type" "store")]) | |
9711 | ||
9712 | (define_insn "*stmsi6" | |
9713 | [(match_parallel 0 "store_multiple_operation" | |
9714 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9715 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9716 | (clobber (match_scratch:SI 3 "X")) | |
9717 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9718 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9719 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9720 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9721 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9722 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9723 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9724 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9725 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9726 | (match_operand:SI 8 "gpc_reg_operand" "r"))])] | |
9727 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7" | |
9728 | "{stsi|stswi} %2,%1,%O0" | |
9729 | [(set_attr "type" "store")]) | |
9730 | ||
9731 | (define_insn "*stmsi5" | |
9732 | [(match_parallel 0 "store_multiple_operation" | |
9733 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9734 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9735 | (clobber (match_scratch:SI 3 "X")) | |
9736 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9737 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9738 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9739 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9740 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9741 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9742 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9743 | (match_operand:SI 7 "gpc_reg_operand" "r"))])] | |
9744 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6" | |
9745 | "{stsi|stswi} %2,%1,%O0" | |
9746 | [(set_attr "type" "store")]) | |
9747 | ||
9748 | (define_insn "*stmsi4" | |
9749 | [(match_parallel 0 "store_multiple_operation" | |
9750 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9751 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9752 | (clobber (match_scratch:SI 3 "X")) | |
9753 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9754 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9755 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9756 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9757 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9758 | (match_operand:SI 6 "gpc_reg_operand" "r"))])] | |
9759 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5" | |
b7ff3d82 DE |
9760 | "{stsi|stswi} %2,%1,%O0" |
9761 | [(set_attr "type" "store")]) | |
7e69e155 | 9762 | |
e46e3130 DJ |
9763 | (define_insn "*stmsi3" |
9764 | [(match_parallel 0 "store_multiple_operation" | |
9765 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9766 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9767 | (clobber (match_scratch:SI 3 "X")) | |
9768 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9769 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9770 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9771 | (match_operand:SI 5 "gpc_reg_operand" "r"))])] | |
9772 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4" | |
9773 | "{stsi|stswi} %2,%1,%O0" | |
9774 | [(set_attr "type" "store")]) | |
7e69e155 MM |
9775 | \f |
9776 | ;; String/block move insn. | |
9777 | ;; Argument 0 is the destination | |
9778 | ;; Argument 1 is the source | |
9779 | ;; Argument 2 is the length | |
9780 | ;; Argument 3 is the alignment | |
9781 | ||
9782 | (define_expand "movstrsi" | |
b6c9286a MM |
9783 | [(parallel [(set (match_operand:BLK 0 "" "") |
9784 | (match_operand:BLK 1 "" "")) | |
9785 | (use (match_operand:SI 2 "" "")) | |
9786 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
9787 | "" |
9788 | " | |
9789 | { | |
9790 | if (expand_block_move (operands)) | |
9791 | DONE; | |
9792 | else | |
9793 | FAIL; | |
9794 | }") | |
9795 | ||
9796 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
9797 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
9798 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9799 | (define_expand "movstrsi_8reg" |
b6c9286a MM |
9800 | [(parallel [(set (match_operand 0 "" "") |
9801 | (match_operand 1 "" "")) | |
9802 | (use (match_operand 2 "" "")) | |
9803 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
9804 | (clobber (reg:SI 5)) |
9805 | (clobber (reg:SI 6)) | |
9806 | (clobber (reg:SI 7)) | |
9807 | (clobber (reg:SI 8)) | |
9808 | (clobber (reg:SI 9)) | |
9809 | (clobber (reg:SI 10)) | |
9810 | (clobber (reg:SI 11)) | |
9811 | (clobber (reg:SI 12)) | |
3c67b673 | 9812 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9813 | "TARGET_STRING" |
9814 | "") | |
9815 | ||
9816 | (define_insn "" | |
52d3af72 DE |
9817 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9818 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9819 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9820 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9821 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9822 | (clobber (reg:SI 6)) |
9823 | (clobber (reg:SI 7)) | |
9824 | (clobber (reg:SI 8)) | |
9825 | (clobber (reg:SI 9)) | |
9826 | (clobber (reg:SI 10)) | |
9827 | (clobber (reg:SI 11)) | |
9828 | (clobber (reg:SI 12)) | |
3c67b673 | 9829 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 9830 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
9831 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9832 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9833 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9834 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9835 | && REGNO (operands[4]) == 5" |
9836 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9837 | [(set_attr "type" "load") |
9838 | (set_attr "length" "8")]) | |
7e69e155 MM |
9839 | |
9840 | (define_insn "" | |
52d3af72 DE |
9841 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9842 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9843 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9844 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9845 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9846 | (clobber (reg:SI 6)) |
9847 | (clobber (reg:SI 7)) | |
9848 | (clobber (reg:SI 8)) | |
9849 | (clobber (reg:SI 9)) | |
9850 | (clobber (reg:SI 10)) | |
9851 | (clobber (reg:SI 11)) | |
9852 | (clobber (reg:SI 12)) | |
3c67b673 | 9853 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9854 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
9855 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9856 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9857 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9858 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9859 | && REGNO (operands[4]) == 5" |
9860 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9861 | [(set_attr "type" "load") |
9862 | (set_attr "length" "8")]) | |
7e69e155 | 9863 | |
09a625f7 TR |
9864 | (define_insn "" |
9865 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9866 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9867 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9868 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9869 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9870 | (clobber (reg:SI 6)) | |
9871 | (clobber (reg:SI 7)) | |
9872 | (clobber (reg:SI 8)) | |
9873 | (clobber (reg:SI 9)) | |
9874 | (clobber (reg:SI 10)) | |
9875 | (clobber (reg:SI 11)) | |
9876 | (clobber (reg:SI 12)) | |
9877 | (clobber (match_scratch:SI 5 "X"))] | |
9878 | "TARGET_STRING && TARGET_POWERPC64 | |
9879 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) | |
9880 | || INTVAL (operands[2]) == 0) | |
9881 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
9882 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
9883 | && REGNO (operands[4]) == 5" | |
9884 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9885 | [(set_attr "type" "load") | |
9886 | (set_attr "length" "8")]) | |
9887 | ||
7e69e155 | 9888 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the |
f9562f27 DE |
9889 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
9890 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9891 | (define_expand "movstrsi_6reg" |
b6c9286a MM |
9892 | [(parallel [(set (match_operand 0 "" "") |
9893 | (match_operand 1 "" "")) | |
9894 | (use (match_operand 2 "" "")) | |
9895 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9896 | (clobber (reg:SI 5)) |
9897 | (clobber (reg:SI 6)) | |
7e69e155 MM |
9898 | (clobber (reg:SI 7)) |
9899 | (clobber (reg:SI 8)) | |
9900 | (clobber (reg:SI 9)) | |
9901 | (clobber (reg:SI 10)) | |
3c67b673 | 9902 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9903 | "TARGET_STRING" |
9904 | "") | |
9905 | ||
9906 | (define_insn "" | |
52d3af72 DE |
9907 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9908 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9909 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9910 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9911 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9912 | (clobber (reg:SI 6)) |
9913 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9914 | (clobber (reg:SI 8)) |
9915 | (clobber (reg:SI 9)) | |
9916 | (clobber (reg:SI 10)) | |
3c67b673 | 9917 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9918 | "TARGET_STRING && TARGET_POWER |
9919 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
9920 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9921 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9922 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9923 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9924 | [(set_attr "type" "load") |
9925 | (set_attr "length" "8")]) | |
7e69e155 MM |
9926 | |
9927 | (define_insn "" | |
52d3af72 DE |
9928 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9929 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9930 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9931 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9932 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9933 | (clobber (reg:SI 6)) |
9934 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9935 | (clobber (reg:SI 8)) |
9936 | (clobber (reg:SI 9)) | |
9937 | (clobber (reg:SI 10)) | |
3c67b673 | 9938 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9939 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9940 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
9941 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9942 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9943 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9944 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9945 | [(set_attr "type" "load") |
9946 | (set_attr "length" "8")]) | |
7e69e155 | 9947 | |
09a625f7 TR |
9948 | (define_insn "" |
9949 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9950 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9951 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9952 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9953 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9954 | (clobber (reg:SI 6)) | |
9955 | (clobber (reg:SI 7)) | |
9956 | (clobber (reg:SI 8)) | |
9957 | (clobber (reg:SI 9)) | |
9958 | (clobber (reg:SI 10)) | |
9959 | (clobber (match_scratch:SI 5 "X"))] | |
9960 | "TARGET_STRING && TARGET_POWERPC64 | |
9961 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 | |
9962 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) | |
9963 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9964 | && REGNO (operands[4]) == 5" | |
9965 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9966 | [(set_attr "type" "load") | |
9967 | (set_attr "length" "8")]) | |
9968 | ||
f9562f27 DE |
9969 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
9970 | ;; problems with TImode. | |
9971 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9972 | (define_expand "movstrsi_4reg" |
b6c9286a MM |
9973 | [(parallel [(set (match_operand 0 "" "") |
9974 | (match_operand 1 "" "")) | |
9975 | (use (match_operand 2 "" "")) | |
9976 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9977 | (clobber (reg:SI 5)) |
9978 | (clobber (reg:SI 6)) | |
9979 | (clobber (reg:SI 7)) | |
9980 | (clobber (reg:SI 8)) | |
3c67b673 | 9981 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9982 | "TARGET_STRING" |
9983 | "") | |
9984 | ||
9985 | (define_insn "" | |
52d3af72 DE |
9986 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9987 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9988 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9989 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9990 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9991 | (clobber (reg:SI 6)) |
9992 | (clobber (reg:SI 7)) | |
9993 | (clobber (reg:SI 8)) | |
3c67b673 | 9994 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9995 | "TARGET_STRING && TARGET_POWER |
9996 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
9997 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9998 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9999 | && REGNO (operands[4]) == 5" | |
3c67b673 | 10000 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
10001 | [(set_attr "type" "load") |
10002 | (set_attr "length" "8")]) | |
7e69e155 MM |
10003 | |
10004 | (define_insn "" | |
52d3af72 DE |
10005 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
10006 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
10007 | (use (match_operand:SI 2 "immediate_operand" "i")) |
10008 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 10009 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
10010 | (clobber (reg:SI 6)) |
10011 | (clobber (reg:SI 7)) | |
10012 | (clobber (reg:SI 8)) | |
3c67b673 | 10013 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 10014 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 10015 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
10016 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
10017 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
10018 | && REGNO (operands[4]) == 5" | |
3c67b673 | 10019 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
10020 | [(set_attr "type" "load") |
10021 | (set_attr "length" "8")]) | |
7e69e155 | 10022 | |
09a625f7 TR |
10023 | (define_insn "" |
10024 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
10025 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
10026 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
10027 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
10028 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
10029 | (clobber (reg:SI 6)) | |
10030 | (clobber (reg:SI 7)) | |
10031 | (clobber (reg:SI 8)) | |
10032 | (clobber (match_scratch:SI 5 "X"))] | |
10033 | "TARGET_STRING && TARGET_POWERPC64 | |
10034 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
10035 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) | |
10036 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
10037 | && REGNO (operands[4]) == 5" | |
10038 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
10039 | [(set_attr "type" "load") | |
10040 | (set_attr "length" "8")]) | |
10041 | ||
7e69e155 MM |
10042 | ;; Move up to 8 bytes at a time. |
10043 | (define_expand "movstrsi_2reg" | |
b6c9286a MM |
10044 | [(parallel [(set (match_operand 0 "" "") |
10045 | (match_operand 1 "" "")) | |
10046 | (use (match_operand 2 "" "")) | |
10047 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
10048 | (clobber (match_scratch:DI 4 "")) |
10049 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 10050 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
10051 | "") |
10052 | ||
10053 | (define_insn "" | |
52d3af72 DE |
10054 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
10055 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
10056 | (use (match_operand:SI 2 "immediate_operand" "i")) |
10057 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
10058 | (clobber (match_scratch:DI 4 "=&r")) | |
10059 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 10060 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
10061 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
10062 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
10063 | [(set_attr "type" "load") |
10064 | (set_attr "length" "8")]) | |
7e69e155 MM |
10065 | |
10066 | (define_insn "" | |
52d3af72 DE |
10067 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
10068 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
10069 | (use (match_operand:SI 2 "immediate_operand" "i")) |
10070 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
10071 | (clobber (match_scratch:DI 4 "=&r")) | |
10072 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 10073 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 10074 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 10075 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
10076 | [(set_attr "type" "load") |
10077 | (set_attr "length" "8")]) | |
7e69e155 MM |
10078 | |
10079 | ;; Move up to 4 bytes at a time. | |
10080 | (define_expand "movstrsi_1reg" | |
b6c9286a MM |
10081 | [(parallel [(set (match_operand 0 "" "") |
10082 | (match_operand 1 "" "")) | |
10083 | (use (match_operand 2 "" "")) | |
10084 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
10085 | (clobber (match_scratch:SI 4 "")) |
10086 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
10087 | "TARGET_STRING" |
10088 | "") | |
10089 | ||
10090 | (define_insn "" | |
52d3af72 DE |
10091 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
10092 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
10093 | (use (match_operand:SI 2 "immediate_operand" "i")) |
10094 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
10095 | (clobber (match_scratch:SI 4 "=&r")) | |
10096 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
10097 | "TARGET_STRING && TARGET_POWER |
10098 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 10099 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
10100 | [(set_attr "type" "load") |
10101 | (set_attr "length" "8")]) | |
7e69e155 MM |
10102 | |
10103 | (define_insn "" | |
52d3af72 DE |
10104 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
10105 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
10106 | (use (match_operand:SI 2 "immediate_operand" "i")) |
10107 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
10108 | (clobber (match_scratch:SI 4 "=&r")) | |
10109 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 10110 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 10111 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
09a625f7 TR |
10112 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
10113 | [(set_attr "type" "load") | |
10114 | (set_attr "length" "8")]) | |
10115 | ||
10116 | (define_insn "" | |
10117 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
10118 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
10119 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
10120 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
10121 | (clobber (match_scratch:SI 4 "=&r")) | |
10122 | (clobber (match_scratch:SI 5 "X"))] | |
10123 | "TARGET_STRING && TARGET_POWERPC64 | |
10124 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 10125 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
10126 | [(set_attr "type" "load") |
10127 | (set_attr "length" "8")]) | |
7e69e155 | 10128 | |
1fd4e8c1 | 10129 | \f |
7e69e155 | 10130 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
10131 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
10132 | ;; do cases where the increment is not the size of the object. | |
10133 | ;; | |
10134 | ;; In all these cases, we use operands 0 and 1 for the register being | |
10135 | ;; incremented because those are the operands that local-alloc will | |
10136 | ;; tie and these are the pair most likely to be tieable (and the ones | |
10137 | ;; that will benefit the most). | |
10138 | ||
38c1f2d7 | 10139 | (define_insn "*movdi_update1" |
51b8fc2c | 10140 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 10141 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 10142 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) |
51b8fc2c RK |
10143 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") |
10144 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 10145 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
10146 | "@ |
10147 | ldux %3,%0,%2 | |
10148 | ldu %3,%2(%0)" | |
10149 | [(set_attr "type" "load")]) | |
10150 | ||
38c1f2d7 | 10151 | (define_insn "*movdi_update2" |
287f13ff RK |
10152 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") |
10153 | (sign_extend:DI | |
10154 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
10155 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
10156 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
10157 | (plus:DI (match_dup 1) (match_dup 2)))] | |
10158 | "TARGET_POWERPC64" | |
10159 | "lwaux %3,%0,%2" | |
10160 | [(set_attr "type" "load")]) | |
10161 | ||
4697a36c | 10162 | (define_insn "movdi_update" |
51b8fc2c | 10163 | [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 10164 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))) |
51b8fc2c RK |
10165 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) |
10166 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
10167 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 10168 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
10169 | "@ |
10170 | stdux %3,%0,%2 | |
b7ff3d82 DE |
10171 | stdu %3,%2(%0)" |
10172 | [(set_attr "type" "store")]) | |
51b8fc2c | 10173 | |
38c1f2d7 | 10174 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
10175 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
10176 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 10177 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 10178 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
10179 | (plus:SI (match_dup 1) (match_dup 2)))] |
10180 | "" | |
10181 | "@ | |
ca7f5001 RK |
10182 | {lux|lwzux} %3,%0,%2 |
10183 | {lu|lwzu} %3,%2(%0)" | |
cfb557c4 | 10184 | [(set_attr "type" "load")]) |
1fd4e8c1 | 10185 | |
4697a36c | 10186 | (define_insn "movsi_update" |
cd2b37d9 | 10187 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 10188 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
10189 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
10190 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 10191 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 10192 | "TARGET_UPDATE" |
1fd4e8c1 | 10193 | "@ |
ca7f5001 | 10194 | {stux|stwux} %3,%0,%2 |
b7ff3d82 DE |
10195 | {stu|stwu} %3,%2(%0)" |
10196 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 10197 | |
38c1f2d7 | 10198 | (define_insn "*movhi_update" |
cd2b37d9 RK |
10199 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
10200 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 10201 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 10202 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 10203 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 10204 | "TARGET_UPDATE" |
1fd4e8c1 | 10205 | "@ |
5f243543 RK |
10206 | lhzux %3,%0,%2 |
10207 | lhzu %3,%2(%0)" | |
cfb557c4 | 10208 | [(set_attr "type" "load")]) |
1fd4e8c1 | 10209 | |
38c1f2d7 | 10210 | (define_insn "*movhi_update2" |
cd2b37d9 | 10211 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10212 | (zero_extend:SI |
cd2b37d9 | 10213 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 10214 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 10215 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 10216 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 10217 | "TARGET_UPDATE" |
1fd4e8c1 | 10218 | "@ |
5f243543 RK |
10219 | lhzux %3,%0,%2 |
10220 | lhzu %3,%2(%0)" | |
cfb557c4 | 10221 | [(set_attr "type" "load")]) |
1fd4e8c1 | 10222 | |
38c1f2d7 | 10223 | (define_insn "*movhi_update3" |
cd2b37d9 | 10224 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10225 | (sign_extend:SI |
cd2b37d9 | 10226 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 10227 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 10228 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 10229 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 10230 | "TARGET_UPDATE" |
1fd4e8c1 | 10231 | "@ |
5f243543 RK |
10232 | lhaux %3,%0,%2 |
10233 | lhau %3,%2(%0)" | |
cfb557c4 | 10234 | [(set_attr "type" "load")]) |
1fd4e8c1 | 10235 | |
38c1f2d7 | 10236 | (define_insn "*movhi_update4" |
cd2b37d9 | 10237 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 10238 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
10239 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
10240 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 10241 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 10242 | "TARGET_UPDATE" |
1fd4e8c1 | 10243 | "@ |
5f243543 | 10244 | sthux %3,%0,%2 |
b7ff3d82 DE |
10245 | sthu %3,%2(%0)" |
10246 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 10247 | |
38c1f2d7 | 10248 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
10249 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
10250 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 10251 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 10252 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 10253 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 10254 | "TARGET_UPDATE" |
1fd4e8c1 | 10255 | "@ |
5f243543 RK |
10256 | lbzux %3,%0,%2 |
10257 | lbzu %3,%2(%0)" | |
cfb557c4 | 10258 | [(set_attr "type" "load")]) |
1fd4e8c1 | 10259 | |
38c1f2d7 | 10260 | (define_insn "*movqi_update2" |
cd2b37d9 | 10261 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10262 | (zero_extend:SI |
cd2b37d9 | 10263 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 10264 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 10265 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 10266 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 10267 | "TARGET_UPDATE" |
1fd4e8c1 | 10268 | "@ |
5f243543 RK |
10269 | lbzux %3,%0,%2 |
10270 | lbzu %3,%2(%0)" | |
cfb557c4 | 10271 | [(set_attr "type" "load")]) |
1fd4e8c1 | 10272 | |
38c1f2d7 | 10273 | (define_insn "*movqi_update3" |
cd2b37d9 | 10274 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 10275 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
10276 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
10277 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 10278 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 10279 | "TARGET_UPDATE" |
1fd4e8c1 | 10280 | "@ |
5f243543 | 10281 | stbux %3,%0,%2 |
b7ff3d82 DE |
10282 | stbu %3,%2(%0)" |
10283 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 10284 | |
38c1f2d7 | 10285 | (define_insn "*movsf_update1" |
cd2b37d9 | 10286 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 10287 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 10288 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 10289 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 10290 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 10291 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 10292 | "@ |
5f243543 RK |
10293 | lfsux %3,%0,%2 |
10294 | lfsu %3,%2(%0)" | |
cfb557c4 | 10295 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 10296 | |
38c1f2d7 | 10297 | (define_insn "*movsf_update2" |
cd2b37d9 | 10298 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 10299 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
10300 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
10301 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 10302 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 10303 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 10304 | "@ |
85fff2f3 | 10305 | stfsux %3,%0,%2 |
b7ff3d82 DE |
10306 | stfsu %3,%2(%0)" |
10307 | [(set_attr "type" "fpstore")]) | |
1fd4e8c1 | 10308 | |
38c1f2d7 MM |
10309 | (define_insn "*movsf_update3" |
10310 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
10311 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
10312 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
10313 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
10314 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 10315 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
10316 | "@ |
10317 | {lux|lwzux} %3,%0,%2 | |
10318 | {lu|lwzu} %3,%2(%0)" | |
10319 | [(set_attr "type" "load")]) | |
10320 | ||
10321 | (define_insn "*movsf_update4" | |
10322 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
10323 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
10324 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
10325 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
10326 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 10327 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
10328 | "@ |
10329 | {stux|stwux} %3,%0,%2 | |
10330 | {stu|stwu} %3,%2(%0)" | |
10331 | [(set_attr "type" "store")]) | |
10332 | ||
10333 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
10334 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
10335 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 10336 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 10337 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 10338 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 10339 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 10340 | "@ |
5f243543 RK |
10341 | lfdux %3,%0,%2 |
10342 | lfdu %3,%2(%0)" | |
cfb557c4 | 10343 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 10344 | |
38c1f2d7 | 10345 | (define_insn "*movdf_update2" |
cd2b37d9 | 10346 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 10347 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
10348 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
10349 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 10350 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 10351 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 10352 | "@ |
5f243543 | 10353 | stfdux %3,%0,%2 |
b7ff3d82 DE |
10354 | stfdu %3,%2(%0)" |
10355 | [(set_attr "type" "fpstore")]) | |
4c70a4f3 RK |
10356 | |
10357 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
10358 | ||
10359 | (define_peephole | |
10360 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
10361 | (match_operand:DF 1 "memory_operand" "")) | |
10362 | (set (match_operand:DF 2 "gpc_reg_operand" "=f") | |
10363 | (match_operand:DF 3 "memory_operand" ""))] | |
10364 | "TARGET_POWER2 | |
a3170dc6 | 10365 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 RK |
10366 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
10367 | && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) | |
10368 | && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" | |
10369 | "lfq%U1%X1 %0,%1") | |
10370 | ||
10371 | (define_peephole | |
10372 | [(set (match_operand:DF 0 "memory_operand" "") | |
10373 | (match_operand:DF 1 "gpc_reg_operand" "f")) | |
10374 | (set (match_operand:DF 2 "memory_operand" "") | |
10375 | (match_operand:DF 3 "gpc_reg_operand" "f"))] | |
10376 | "TARGET_POWER2 | |
a3170dc6 | 10377 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 RK |
10378 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
10379 | && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) | |
10380 | && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" | |
10381 | "stfq%U0%X0 %1,%0") | |
1fd4e8c1 RK |
10382 | \f |
10383 | ;; Next come insns related to the calling sequence. | |
10384 | ;; | |
10385 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 10386 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
10387 | |
10388 | (define_expand "allocate_stack" | |
52d3af72 | 10389 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
10390 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
10391 | (set (reg 1) | |
10392 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
10393 | "" |
10394 | " | |
4697a36c | 10395 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 10396 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 10397 | rtx neg_op0; |
1fd4e8c1 RK |
10398 | |
10399 | emit_move_insn (chain, stack_bot); | |
4697a36c | 10400 | |
a157febd GK |
10401 | /* Check stack bounds if necessary. */ |
10402 | if (current_function_limit_stack) | |
10403 | { | |
10404 | rtx available; | |
10405 | available = expand_binop (Pmode, sub_optab, | |
10406 | stack_pointer_rtx, stack_limit_rtx, | |
10407 | NULL_RTX, 1, OPTAB_WIDEN); | |
10408 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
10409 | } | |
10410 | ||
e9a25f70 JL |
10411 | if (GET_CODE (operands[1]) != CONST_INT |
10412 | || INTVAL (operands[1]) < -32767 | |
10413 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
10414 | { |
10415 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 10416 | if (TARGET_32BIT) |
e9a25f70 | 10417 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 10418 | else |
e9a25f70 | 10419 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
10420 | } |
10421 | else | |
e9a25f70 | 10422 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 10423 | |
38c1f2d7 MM |
10424 | if (TARGET_UPDATE) |
10425 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) | |
10426 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); | |
4697a36c | 10427 | |
38c1f2d7 MM |
10428 | else |
10429 | { | |
10430 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
10431 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 10432 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 10433 | } |
e9a25f70 JL |
10434 | |
10435 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
10436 | DONE; |
10437 | }") | |
59257ff7 RK |
10438 | |
10439 | ;; These patterns say how to save and restore the stack pointer. We need not | |
10440 | ;; save the stack pointer at function level since we are careful to | |
10441 | ;; preserve the backchain. At block level, we have to restore the backchain | |
10442 | ;; when we restore the stack pointer. | |
10443 | ;; | |
10444 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
10445 | ;; backchain and restore both. Note that in the nonlocal case, the | |
10446 | ;; save area is a memory location. | |
10447 | ||
10448 | (define_expand "save_stack_function" | |
ff381587 MM |
10449 | [(match_operand 0 "any_operand" "") |
10450 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 10451 | "" |
ff381587 | 10452 | "DONE;") |
59257ff7 RK |
10453 | |
10454 | (define_expand "restore_stack_function" | |
ff381587 MM |
10455 | [(match_operand 0 "any_operand" "") |
10456 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 10457 | "" |
ff381587 | 10458 | "DONE;") |
59257ff7 RK |
10459 | |
10460 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
10461 | [(use (match_operand 0 "register_operand" "")) |
10462 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 10463 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 10464 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
10465 | "" |
10466 | " | |
dfdfa60f DE |
10467 | { |
10468 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 10469 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 10470 | }") |
59257ff7 RK |
10471 | |
10472 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
10473 | [(match_operand 0 "memory_operand" "") |
10474 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
10475 | "" |
10476 | " | |
10477 | { | |
a260abc9 | 10478 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
10479 | |
10480 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 10481 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
c5c76735 JL |
10482 | emit_move_insn (operand_subword (operands[0], 0, 0, |
10483 | (TARGET_32BIT ? DImode : TImode)), | |
a260abc9 DE |
10484 | temp); |
10485 | emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)), | |
10486 | operands[1]); | |
59257ff7 RK |
10487 | DONE; |
10488 | }") | |
7e69e155 | 10489 | |
59257ff7 | 10490 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
10491 | [(match_operand 0 "register_operand" "") |
10492 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
10493 | "" |
10494 | " | |
10495 | { | |
a260abc9 | 10496 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
10497 | |
10498 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 DE |
10499 | emit_move_insn (temp, |
10500 | operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode))); | |
10501 | emit_move_insn (operands[0], | |
c5c76735 JL |
10502 | operand_subword (operands[1], 1, 0, |
10503 | (TARGET_32BIT ? DImode : TImode))); | |
39403d82 | 10504 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
10505 | DONE; |
10506 | }") | |
9ebbca7d GK |
10507 | \f |
10508 | ;; TOC register handling. | |
b6c9286a | 10509 | |
9ebbca7d | 10510 | ;; Code to initialize the TOC register... |
f0f6a223 | 10511 | |
9ebbca7d | 10512 | (define_insn "load_toc_aix_si" |
e72247f4 | 10513 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
46aaf10d DE |
10514 | (unspec:SI [(const_int 0)] 7)) |
10515 | (use (reg:SI 2))])] | |
2bfcf297 | 10516 | "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" |
f0f6a223 RK |
10517 | "* |
10518 | { | |
9ebbca7d GK |
10519 | char buf[30]; |
10520 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 10521 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
10522 | operands[2] = gen_rtx_REG (Pmode, 2); |
10523 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
10524 | }" |
10525 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
10526 | |
10527 | (define_insn "load_toc_aix_di" | |
e72247f4 | 10528 | [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
46aaf10d DE |
10529 | (unspec:DI [(const_int 0)] 7)) |
10530 | (use (reg:DI 2))])] | |
2bfcf297 | 10531 | "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" |
9ebbca7d GK |
10532 | "* |
10533 | { | |
10534 | char buf[30]; | |
f585a356 DE |
10535 | #ifdef TARGET_RELOCATABLE |
10536 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", | |
10537 | !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); | |
10538 | #else | |
9ebbca7d | 10539 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); |
f585a356 | 10540 | #endif |
2bfcf297 DB |
10541 | if (TARGET_ELF) |
10542 | strcat (buf, \"@toc\"); | |
a8a05998 | 10543 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
10544 | operands[2] = gen_rtx_REG (Pmode, 2); |
10545 | return \"ld %0,%1(%2)\"; | |
10546 | }" | |
10547 | [(set_attr "type" "load")]) | |
10548 | ||
10549 | (define_insn "load_toc_v4_pic_si" | |
10550 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10551 | (unspec:SI [(const_int 0)] 7))] | |
f607bc57 | 10552 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" |
9ebbca7d GK |
10553 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
10554 | [(set_attr "type" "branch") | |
10555 | (set_attr "length" "4")]) | |
10556 | ||
9ebbca7d GK |
10557 | (define_insn "load_toc_v4_PIC_1" |
10558 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10559 | (match_operand:SI 1 "immediate_operand" "s")) | |
10560 | (unspec [(match_dup 1)] 7)] | |
20b71b17 | 10561 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
df7a8989 | 10562 | "bcl 20,31,%1\\n%1:" |
9ebbca7d GK |
10563 | [(set_attr "type" "branch") |
10564 | (set_attr "length" "4")]) | |
10565 | ||
10566 | (define_insn "load_toc_v4_PIC_1b" | |
10567 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10568 | (match_operand:SI 1 "immediate_operand" "s")) | |
10569 | (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)] | |
20b71b17 | 10570 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
df7a8989 | 10571 | "bcl 20,31,%1\\n\\t.long %2-%1+4\\n%1:" |
9ebbca7d GK |
10572 | [(set_attr "type" "branch") |
10573 | (set_attr "length" "8")]) | |
10574 | ||
10575 | (define_insn "load_toc_v4_PIC_2" | |
f585a356 | 10576 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
a2900460 | 10577 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
9ebbca7d GK |
10578 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") |
10579 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
20b71b17 | 10580 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
9ebbca7d GK |
10581 | "{l|lwz} %0,%2-%3(%1)" |
10582 | [(set_attr "type" "load")]) | |
10583 | ||
ee890fe2 SS |
10584 | (define_insn "load_macho_picbase" |
10585 | [(set (match_operand:SI 0 "register_operand" "=l") | |
f51eee6a | 10586 | (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] 15))] |
ee890fe2 | 10587 | "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" |
f51eee6a | 10588 | "bcl 20,31,%1\\n%1:" |
ee890fe2 SS |
10589 | [(set_attr "type" "branch") |
10590 | (set_attr "length" "4")]) | |
10591 | ||
f51eee6a GK |
10592 | (define_insn "macho_correct_pic" |
10593 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
10594 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "=r") | |
10595 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "s") | |
10596 | (match_operand:SI 3 "immediate_operand" "s")] | |
10597 | 16)))] | |
10598 | "DEFAULT_ABI == ABI_DARWIN" | |
10599 | "addis %0,%1,ha16(%2-%3)\n\taddi %1,%1,lo16(%2-%3)" | |
10600 | [(set_attr "length" "8")]) | |
10601 | ||
9ebbca7d GK |
10602 | ;; If the TOC is shared over a translation unit, as happens with all |
10603 | ;; the kinds of PIC that we support, we need to restore the TOC | |
10604 | ;; pointer only when jumping over units of translation. | |
f51eee6a | 10605 | ;; On Darwin, we need to reload the picbase. |
9ebbca7d GK |
10606 | |
10607 | (define_expand "builtin_setjmp_receiver" | |
10608 | [(use (label_ref (match_operand 0 "" "")))] | |
f607bc57 | 10609 | "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
f51eee6a GK |
10610 | || (TARGET_TOC && TARGET_MINIMAL_TOC) |
10611 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" | |
9ebbca7d GK |
10612 | " |
10613 | { | |
84d7dd4a | 10614 | #if TARGET_MACHO |
f51eee6a GK |
10615 | if (DEFAULT_ABI == ABI_DARWIN) |
10616 | { | |
d24652ee | 10617 | const char *picbase = machopic_function_base_name (); |
f51eee6a GK |
10618 | rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1)); |
10619 | rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); | |
10620 | rtx tmplabrtx; | |
10621 | char tmplab[20]; | |
10622 | ||
10623 | ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", | |
10624 | CODE_LABEL_NUMBER (operands[0])); | |
10625 | tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (tmplab, -1)); | |
10626 | ||
10627 | emit_insn (gen_load_macho_picbase (picreg, tmplabrtx)); | |
10628 | emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); | |
10629 | } | |
10630 | else | |
84d7dd4a | 10631 | #endif |
f51eee6a | 10632 | rs6000_emit_load_toc_table (FALSE); |
9ebbca7d GK |
10633 | DONE; |
10634 | }") | |
10635 | \f | |
10636 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
10637 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
10638 | ;; pointer to its TOC, and whose third word contains a value to place in the |
10639 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 10640 | ;; "trampoline" need not have any executable code. |
b6c9286a | 10641 | |
cccf3bdc DE |
10642 | (define_expand "call_indirect_aix32" |
10643 | [(set (match_dup 2) | |
10644 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
10645 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10646 | (reg:SI 2)) | |
10647 | (set (reg:SI 2) | |
10648 | (mem:SI (plus:SI (match_dup 0) | |
10649 | (const_int 4)))) | |
10650 | (set (reg:SI 11) | |
10651 | (mem:SI (plus:SI (match_dup 0) | |
10652 | (const_int 8)))) | |
10653 | (parallel [(call (mem:SI (match_dup 2)) | |
10654 | (match_operand 1 "" "")) | |
10655 | (use (reg:SI 2)) | |
10656 | (use (reg:SI 11)) | |
10657 | (set (reg:SI 2) | |
10658 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10659 | (clobber (scratch:SI))])] | |
10660 | "TARGET_32BIT" | |
10661 | " | |
10662 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10663 | |
cccf3bdc DE |
10664 | (define_expand "call_indirect_aix64" |
10665 | [(set (match_dup 2) | |
10666 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
10667 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10668 | (reg:DI 2)) | |
10669 | (set (reg:DI 2) | |
10670 | (mem:DI (plus:DI (match_dup 0) | |
10671 | (const_int 8)))) | |
10672 | (set (reg:DI 11) | |
10673 | (mem:DI (plus:DI (match_dup 0) | |
10674 | (const_int 16)))) | |
10675 | (parallel [(call (mem:SI (match_dup 2)) | |
10676 | (match_operand 1 "" "")) | |
10677 | (use (reg:DI 2)) | |
10678 | (use (reg:DI 11)) | |
10679 | (set (reg:DI 2) | |
10680 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10681 | (clobber (scratch:SI))])] | |
10682 | "TARGET_64BIT" | |
10683 | " | |
10684 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 10685 | |
cccf3bdc DE |
10686 | (define_expand "call_value_indirect_aix32" |
10687 | [(set (match_dup 3) | |
10688 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10689 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10690 | (reg:SI 2)) | |
10691 | (set (reg:SI 2) | |
10692 | (mem:SI (plus:SI (match_dup 1) | |
10693 | (const_int 4)))) | |
10694 | (set (reg:SI 11) | |
10695 | (mem:SI (plus:SI (match_dup 1) | |
10696 | (const_int 8)))) | |
10697 | (parallel [(set (match_operand 0 "" "") | |
10698 | (call (mem:SI (match_dup 3)) | |
10699 | (match_operand 2 "" ""))) | |
10700 | (use (reg:SI 2)) | |
10701 | (use (reg:SI 11)) | |
10702 | (set (reg:SI 2) | |
10703 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10704 | (clobber (scratch:SI))])] | |
10705 | "TARGET_32BIT" | |
10706 | " | |
10707 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10708 | |
cccf3bdc DE |
10709 | (define_expand "call_value_indirect_aix64" |
10710 | [(set (match_dup 3) | |
10711 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10712 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10713 | (reg:DI 2)) | |
10714 | (set (reg:DI 2) | |
10715 | (mem:DI (plus:DI (match_dup 1) | |
10716 | (const_int 8)))) | |
10717 | (set (reg:DI 11) | |
10718 | (mem:DI (plus:DI (match_dup 1) | |
10719 | (const_int 16)))) | |
10720 | (parallel [(set (match_operand 0 "" "") | |
10721 | (call (mem:SI (match_dup 3)) | |
10722 | (match_operand 2 "" ""))) | |
10723 | (use (reg:DI 2)) | |
10724 | (use (reg:DI 11)) | |
10725 | (set (reg:DI 2) | |
10726 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10727 | (clobber (scratch:SI))])] | |
10728 | "TARGET_64BIT" | |
10729 | " | |
10730 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 10731 | |
b6c9286a | 10732 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 10733 | (define_expand "call" |
a260abc9 | 10734 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 10735 | (match_operand 1 "" "")) |
4697a36c | 10736 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
10737 | (clobber (scratch:SI))])] |
10738 | "" | |
10739 | " | |
10740 | { | |
ee890fe2 SS |
10741 | #if TARGET_MACHO |
10742 | if (flag_pic) | |
10743 | operands[0] = machopic_indirect_call_target (operands[0]); | |
10744 | #endif | |
10745 | ||
1fd4e8c1 RK |
10746 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) |
10747 | abort (); | |
10748 | ||
10749 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 10750 | |
6a4cee5f MM |
10751 | if (GET_CODE (operands[0]) != SYMBOL_REF |
10752 | || (INTVAL (operands[2]) & CALL_LONG) != 0) | |
1fd4e8c1 | 10753 | { |
6a4cee5f MM |
10754 | if (INTVAL (operands[2]) & CALL_LONG) |
10755 | operands[0] = rs6000_longcall_ref (operands[0]); | |
10756 | ||
cccf3bdc DE |
10757 | if (DEFAULT_ABI == ABI_V4 |
10758 | || DEFAULT_ABI == ABI_AIX_NODESC | |
f607bc57 | 10759 | || DEFAULT_ABI == ABI_DARWIN) |
cccf3bdc | 10760 | operands[0] = force_reg (Pmode, operands[0]); |
1fd4e8c1 | 10761 | |
cccf3bdc DE |
10762 | else if (DEFAULT_ABI == ABI_AIX) |
10763 | { | |
10764 | /* AIX function pointers are really pointers to a three word | |
10765 | area. */ | |
10766 | emit_call_insn (TARGET_32BIT | |
10767 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
10768 | operands[0]), | |
10769 | operands[1]) | |
10770 | : gen_call_indirect_aix64 (force_reg (DImode, | |
10771 | operands[0]), | |
10772 | operands[1])); | |
10773 | DONE; | |
b6c9286a | 10774 | } |
cccf3bdc DE |
10775 | else |
10776 | abort (); | |
1fd4e8c1 RK |
10777 | } |
10778 | }") | |
10779 | ||
10780 | (define_expand "call_value" | |
10781 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 10782 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 10783 | (match_operand 2 "" ""))) |
4697a36c | 10784 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
10785 | (clobber (scratch:SI))])] |
10786 | "" | |
10787 | " | |
10788 | { | |
ee890fe2 SS |
10789 | #if TARGET_MACHO |
10790 | if (flag_pic) | |
10791 | operands[1] = machopic_indirect_call_target (operands[1]); | |
10792 | #endif | |
10793 | ||
1fd4e8c1 RK |
10794 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) |
10795 | abort (); | |
10796 | ||
10797 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 10798 | |
6a4cee5f MM |
10799 | if (GET_CODE (operands[1]) != SYMBOL_REF |
10800 | || (INTVAL (operands[3]) & CALL_LONG) != 0) | |
1fd4e8c1 | 10801 | { |
6756293c | 10802 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
10803 | operands[1] = rs6000_longcall_ref (operands[1]); |
10804 | ||
cccf3bdc DE |
10805 | if (DEFAULT_ABI == ABI_V4 |
10806 | || DEFAULT_ABI == ABI_AIX_NODESC | |
f607bc57 | 10807 | || DEFAULT_ABI == ABI_DARWIN) |
cccf3bdc | 10808 | operands[0] = force_reg (Pmode, operands[0]); |
1fd4e8c1 | 10809 | |
cccf3bdc DE |
10810 | else if (DEFAULT_ABI == ABI_AIX) |
10811 | { | |
10812 | /* AIX function pointers are really pointers to a three word | |
10813 | area. */ | |
10814 | emit_call_insn (TARGET_32BIT | |
10815 | ? gen_call_value_indirect_aix32 (operands[0], | |
10816 | force_reg (SImode, | |
10817 | operands[1]), | |
10818 | operands[2]) | |
10819 | : gen_call_value_indirect_aix64 (operands[0], | |
10820 | force_reg (DImode, | |
10821 | operands[1]), | |
10822 | operands[2])); | |
10823 | DONE; | |
b6c9286a | 10824 | } |
cccf3bdc DE |
10825 | else |
10826 | abort (); | |
1fd4e8c1 RK |
10827 | } |
10828 | }") | |
10829 | ||
04780ee7 | 10830 | ;; Call to function in current module. No TOC pointer reload needed. |
a0ab749a | 10831 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10832 | ;; either the function was not prototyped, or it was prototyped as a |
10833 | ;; variable argument function. It is > 0 if FP registers were passed | |
10834 | ;; and < 0 if they were not. | |
04780ee7 | 10835 | |
a260abc9 | 10836 | (define_insn "*call_local32" |
4697a36c MM |
10837 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
10838 | (match_operand 1 "" "g,g")) | |
10839 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10840 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 10841 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
10842 | "* |
10843 | { | |
6a4cee5f MM |
10844 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
10845 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10846 | ||
10847 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10848 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 10849 | |
a226df46 | 10850 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 10851 | }" |
b7ff3d82 DE |
10852 | [(set_attr "type" "branch") |
10853 | (set_attr "length" "4,8")]) | |
04780ee7 | 10854 | |
a260abc9 DE |
10855 | (define_insn "*call_local64" |
10856 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10857 | (match_operand 1 "" "g,g")) | |
10858 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10859 | (clobber (match_scratch:SI 3 "=l,l"))] | |
10860 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10861 | "* | |
10862 | { | |
10863 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10864 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10865 | ||
10866 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10867 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10868 | ||
10869 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
10870 | }" | |
10871 | [(set_attr "type" "branch") | |
10872 | (set_attr "length" "4,8")]) | |
10873 | ||
cccf3bdc | 10874 | (define_insn "*call_value_local32" |
d18dba68 | 10875 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10876 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) |
10877 | (match_operand 2 "" "g,g"))) | |
10878 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10879 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10880 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10881 | "* | |
10882 | { | |
10883 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10884 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10885 | ||
10886 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10887 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10888 | ||
10889 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10890 | }" | |
10891 | [(set_attr "type" "branch") | |
10892 | (set_attr "length" "4,8")]) | |
10893 | ||
10894 | ||
cccf3bdc | 10895 | (define_insn "*call_value_local64" |
d18dba68 | 10896 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10897 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) |
10898 | (match_operand 2 "" "g,g"))) | |
10899 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10900 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10901 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10902 | "* | |
10903 | { | |
10904 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10905 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10906 | ||
10907 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10908 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10909 | ||
10910 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10911 | }" | |
10912 | [(set_attr "type" "branch") | |
10913 | (set_attr "length" "4,8")]) | |
10914 | ||
04780ee7 | 10915 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 10916 | ;; pointer (r2) after the call unless this is System V. |
a0ab749a | 10917 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10918 | ;; either the function was not prototyped, or it was prototyped as a |
10919 | ;; variable argument function. It is > 0 if FP registers were passed | |
10920 | ;; and < 0 if they were not. | |
04780ee7 | 10921 | |
cccf3bdc DE |
10922 | (define_insn "*call_indirect_nonlocal_aix32" |
10923 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) | |
10924 | (match_operand 1 "" "g")) | |
10925 | (use (reg:SI 2)) | |
10926 | (use (reg:SI 11)) | |
10927 | (set (reg:SI 2) | |
10928 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
c77e04ae | 10929 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10930 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
10931 | "b%T0l\;{l|lwz} 2,20(1)" | |
10932 | [(set_attr "type" "jmpreg") | |
10933 | (set_attr "length" "8")]) | |
10934 | ||
a260abc9 | 10935 | (define_insn "*call_nonlocal_aix32" |
cc4d5fec | 10936 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10937 | (match_operand 1 "" "g")) |
10938 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10939 | (clobber (match_scratch:SI 3 "=l"))] | |
10940 | "TARGET_32BIT | |
10941 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10942 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10943 | "bl %z0\;%." |
b7ff3d82 | 10944 | [(set_attr "type" "branch") |
cccf3bdc DE |
10945 | (set_attr "length" "8")]) |
10946 | ||
10947 | (define_insn "*call_indirect_nonlocal_aix64" | |
10948 | [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) | |
10949 | (match_operand 1 "" "g")) | |
10950 | (use (reg:DI 2)) | |
10951 | (use (reg:DI 11)) | |
10952 | (set (reg:DI 2) | |
10953 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
c77e04ae | 10954 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10955 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
10956 | "b%T0l\;ld 2,40(1)" | |
10957 | [(set_attr "type" "jmpreg") | |
10958 | (set_attr "length" "8")]) | |
59313e4e | 10959 | |
a260abc9 | 10960 | (define_insn "*call_nonlocal_aix64" |
cc4d5fec | 10961 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10962 | (match_operand 1 "" "g")) |
10963 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10964 | (clobber (match_scratch:SI 3 "=l"))] | |
9ebbca7d GK |
10965 | "TARGET_64BIT |
10966 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10967 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10968 | "bl %z0\;%." |
a260abc9 | 10969 | [(set_attr "type" "branch") |
cccf3bdc | 10970 | (set_attr "length" "8")]) |
7509c759 | 10971 | |
cccf3bdc | 10972 | (define_insn "*call_value_indirect_nonlocal_aix32" |
d18dba68 | 10973 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10974 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) |
10975 | (match_operand 2 "" "g"))) | |
10976 | (use (reg:SI 2)) | |
10977 | (use (reg:SI 11)) | |
10978 | (set (reg:SI 2) | |
10979 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10980 | (clobber (match_scratch:SI 3 "=l"))] | |
10981 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" | |
10982 | "b%T1l\;{l|lwz} 2,20(1)" | |
10983 | [(set_attr "type" "jmpreg") | |
10984 | (set_attr "length" "8")]) | |
1fd4e8c1 | 10985 | |
cccf3bdc | 10986 | (define_insn "*call_value_nonlocal_aix32" |
d18dba68 | 10987 | [(set (match_operand 0 "" "") |
cc4d5fec | 10988 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10989 | (match_operand 2 "" "g"))) |
10990 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10991 | (clobber (match_scratch:SI 4 "=l"))] | |
10992 | "TARGET_32BIT | |
10993 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10994 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 10995 | "bl %z1\;%." |
b7ff3d82 | 10996 | [(set_attr "type" "branch") |
cccf3bdc | 10997 | (set_attr "length" "8")]) |
04780ee7 | 10998 | |
cccf3bdc | 10999 | (define_insn "*call_value_indirect_nonlocal_aix64" |
d18dba68 | 11000 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
11001 | (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) |
11002 | (match_operand 2 "" "g"))) | |
11003 | (use (reg:DI 2)) | |
11004 | (use (reg:DI 11)) | |
11005 | (set (reg:DI 2) | |
11006 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
11007 | (clobber (match_scratch:SI 3 "=l"))] | |
11008 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" | |
11009 | "b%T1l\;ld 2,40(1)" | |
11010 | [(set_attr "type" "jmpreg") | |
11011 | (set_attr "length" "8")]) | |
11012 | ||
11013 | (define_insn "*call_value_nonlocal_aix64" | |
d18dba68 | 11014 | [(set (match_operand 0 "" "") |
cc4d5fec | 11015 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
11016 | (match_operand 2 "" "g"))) |
11017 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
11018 | (clobber (match_scratch:SI 4 "=l"))] | |
9ebbca7d GK |
11019 | "TARGET_64BIT |
11020 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 11021 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
11022 | "bl %z1\;%." |
11023 | [(set_attr "type" "branch") | |
11024 | (set_attr "length" "8")]) | |
11025 | ||
11026 | ;; A function pointer under System V is just a normal pointer | |
11027 | ;; operands[0] is the function pointer | |
11028 | ;; operands[1] is the stack size to clean up | |
11029 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
11030 | ;; which indicates how to set cr1 | |
11031 | ||
a5c76ee6 ZW |
11032 | (define_insn "*call_indirect_nonlocal_sysv" |
11033 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl")) | |
11034 | (match_operand 1 "" "g,g")) | |
11035 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
11036 | (clobber (match_scratch:SI 3 "=l,l"))] | |
cccf3bdc DE |
11037 | "DEFAULT_ABI == ABI_AIX_NODESC |
11038 | || DEFAULT_ABI == ABI_V4 | |
f607bc57 | 11039 | || DEFAULT_ABI == ABI_DARWIN" |
911f679c | 11040 | { |
cccf3bdc | 11041 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 11042 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f | 11043 | |
cccf3bdc | 11044 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
a5c76ee6 | 11045 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 11046 | |
a5c76ee6 ZW |
11047 | return "b%T0l"; |
11048 | } | |
11049 | [(set_attr "type" "jmpreg,jmpreg") | |
11050 | (set_attr "length" "4,8")]) | |
cccf3bdc | 11051 | |
a5c76ee6 ZW |
11052 | (define_insn "*call_nonlocal_sysv" |
11053 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
11054 | (match_operand 1 "" "g,g")) | |
11055 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
11056 | (clobber (match_scratch:SI 3 "=l,l"))] | |
11057 | "(DEFAULT_ABI == ABI_AIX_NODESC | |
11058 | || DEFAULT_ABI == ABI_V4 | |
11059 | || DEFAULT_ABI == ABI_DARWIN) | |
11060 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
11061 | { | |
11062 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
11063 | output_asm_insn ("crxor 6,6,6", operands); | |
11064 | ||
11065 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
11066 | output_asm_insn ("creqv 6,6,6", operands); | |
11067 | ||
11068 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0"; | |
11069 | } | |
11070 | [(set_attr "type" "branch,branch") | |
11071 | (set_attr "length" "4,8")]) | |
11072 | ||
11073 | (define_insn "*call_value_indirect_nonlocal_sysv" | |
d18dba68 | 11074 | [(set (match_operand 0 "" "") |
a5c76ee6 ZW |
11075 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl")) |
11076 | (match_operand 2 "" "g,g"))) | |
11077 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
11078 | (clobber (match_scratch:SI 4 "=l,l"))] | |
cccf3bdc DE |
11079 | "DEFAULT_ABI == ABI_AIX_NODESC |
11080 | || DEFAULT_ABI == ABI_V4 | |
f607bc57 | 11081 | || DEFAULT_ABI == ABI_DARWIN" |
b6c9286a | 11082 | { |
6a4cee5f | 11083 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 11084 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f MM |
11085 | |
11086 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
a5c76ee6 | 11087 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 11088 | |
a5c76ee6 ZW |
11089 | return "b%T1l"; |
11090 | } | |
11091 | [(set_attr "type" "jmpreg,jmpreg") | |
11092 | (set_attr "length" "4,8")]) | |
11093 | ||
11094 | (define_insn "*call_value_nonlocal_sysv" | |
11095 | [(set (match_operand 0 "" "") | |
11096 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
11097 | (match_operand 2 "" "g,g"))) | |
11098 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
11099 | (clobber (match_scratch:SI 4 "=l,l"))] | |
11100 | "(DEFAULT_ABI == ABI_AIX_NODESC | |
11101 | || DEFAULT_ABI == ABI_V4 | |
11102 | || DEFAULT_ABI == ABI_DARWIN) | |
11103 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
11104 | { | |
11105 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
11106 | output_asm_insn ("crxor 6,6,6", operands); | |
11107 | ||
11108 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
11109 | output_asm_insn ("creqv 6,6,6", operands); | |
11110 | ||
11111 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1"; | |
11112 | } | |
11113 | [(set_attr "type" "branch,branch") | |
11114 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
11115 | |
11116 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
11117 | (define_expand "untyped_call" |
11118 | [(parallel [(call (match_operand 0 "" "") | |
11119 | (const_int 0)) | |
11120 | (match_operand 1 "" "") | |
11121 | (match_operand 2 "" "")])] | |
11122 | "" | |
11123 | " | |
11124 | { | |
11125 | int i; | |
11126 | ||
7d70b8b2 | 11127 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
11128 | |
11129 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
11130 | { | |
11131 | rtx set = XVECEXP (operands[2], 0, i); | |
11132 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
11133 | } | |
11134 | ||
11135 | /* The optimizer does not know that the call sets the function value | |
11136 | registers we stored in the result block. We avoid problems by | |
11137 | claiming that all hard registers are used and clobbered at this | |
11138 | point. */ | |
11139 | emit_insn (gen_blockage ()); | |
11140 | ||
11141 | DONE; | |
11142 | }") | |
11143 | ||
5e1bf043 DJ |
11144 | ;; sibling call patterns |
11145 | (define_expand "sibcall" | |
11146 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) | |
11147 | (match_operand 1 "" "")) | |
11148 | (use (match_operand 2 "" "")) | |
fe352c29 | 11149 | (use (match_operand 3 "" "")) |
5e1bf043 DJ |
11150 | (return)])] |
11151 | "" | |
11152 | " | |
11153 | { | |
11154 | #if TARGET_MACHO | |
11155 | if (flag_pic) | |
11156 | operands[0] = machopic_indirect_call_target (operands[0]); | |
11157 | #endif | |
11158 | ||
11159 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) | |
11160 | abort (); | |
11161 | ||
11162 | operands[0] = XEXP (operands[0], 0); | |
fe352c29 | 11163 | operands[3] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
11164 | |
11165 | }") | |
11166 | ||
11167 | ;; this and similar patterns must be marked as using LR, otherwise | |
11168 | ;; dataflow will try to delete the store into it. This is true | |
11169 | ;; even when the actual reg to jump to is in CTR, when LR was | |
11170 | ;; saved and restored around the PIC-setting BCL. | |
11171 | (define_insn "*sibcall_local32" | |
11172 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) | |
11173 | (match_operand 1 "" "g,g")) | |
11174 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 11175 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
11176 | (return)] |
11177 | "(INTVAL (operands[2]) & CALL_LONG) == 0" | |
11178 | "* | |
11179 | { | |
11180 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
11181 | output_asm_insn (\"crxor 6,6,6\", operands); | |
11182 | ||
11183 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
11184 | output_asm_insn (\"creqv 6,6,6\", operands); | |
11185 | ||
11186 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
11187 | }" | |
11188 | [(set_attr "type" "branch") | |
11189 | (set_attr "length" "4,8")]) | |
11190 | ||
11191 | (define_insn "*sibcall_local64" | |
11192 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
11193 | (match_operand 1 "" "g,g")) | |
11194 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 11195 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
11196 | (return)] |
11197 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
11198 | "* | |
11199 | { | |
11200 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
11201 | output_asm_insn (\"crxor 6,6,6\", operands); | |
11202 | ||
11203 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
11204 | output_asm_insn (\"creqv 6,6,6\", operands); | |
11205 | ||
11206 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
11207 | }" | |
11208 | [(set_attr "type" "branch") | |
11209 | (set_attr "length" "4,8")]) | |
11210 | ||
11211 | (define_insn "*sibcall_value_local32" | |
11212 | [(set (match_operand 0 "" "") | |
11213 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
11214 | (match_operand 2 "" "g,g"))) | |
11215 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 11216 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
11217 | (return)] |
11218 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
11219 | "* | |
11220 | { | |
11221 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
11222 | output_asm_insn (\"crxor 6,6,6\", operands); | |
11223 | ||
11224 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
11225 | output_asm_insn (\"creqv 6,6,6\", operands); | |
11226 | ||
11227 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
11228 | }" | |
11229 | [(set_attr "type" "branch") | |
11230 | (set_attr "length" "4,8")]) | |
11231 | ||
11232 | ||
11233 | (define_insn "*sibcall_value_local64" | |
11234 | [(set (match_operand 0 "" "") | |
11235 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
11236 | (match_operand 2 "" "g,g"))) | |
11237 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 11238 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
11239 | (return)] |
11240 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
11241 | "* | |
11242 | { | |
11243 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
11244 | output_asm_insn (\"crxor 6,6,6\", operands); | |
11245 | ||
11246 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
11247 | output_asm_insn (\"creqv 6,6,6\", operands); | |
11248 | ||
11249 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
11250 | }" | |
11251 | [(set_attr "type" "branch") | |
11252 | (set_attr "length" "4,8")]) | |
11253 | ||
11254 | (define_insn "*sibcall_nonlocal_aix32" | |
11255 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) | |
11256 | (match_operand 1 "" "g")) | |
11257 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 11258 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 DJ |
11259 | (return)] |
11260 | "TARGET_32BIT | |
11261 | && DEFAULT_ABI == ABI_AIX | |
11262 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
11263 | "b %z0" | |
11264 | [(set_attr "type" "branch") | |
11265 | (set_attr "length" "4")]) | |
11266 | ||
11267 | (define_insn "*sibcall_nonlocal_aix64" | |
11268 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) | |
11269 | (match_operand 1 "" "g")) | |
11270 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 11271 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 DJ |
11272 | (return)] |
11273 | "TARGET_64BIT | |
11274 | && DEFAULT_ABI == ABI_AIX | |
11275 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
11276 | "b %z0" | |
11277 | [(set_attr "type" "branch") | |
11278 | (set_attr "length" "4")]) | |
11279 | ||
11280 | (define_insn "*sibcall_value_nonlocal_aix32" | |
11281 | [(set (match_operand 0 "" "") | |
11282 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) | |
11283 | (match_operand 2 "" "g"))) | |
11284 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 11285 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 DJ |
11286 | (return)] |
11287 | "TARGET_32BIT | |
11288 | && DEFAULT_ABI == ABI_AIX | |
11289 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
11290 | "b %z1" | |
11291 | [(set_attr "type" "branch") | |
11292 | (set_attr "length" "4")]) | |
11293 | ||
11294 | (define_insn "*sibcall_value_nonlocal_aix64" | |
11295 | [(set (match_operand 0 "" "") | |
11296 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) | |
11297 | (match_operand 2 "" "g"))) | |
11298 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 11299 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 DJ |
11300 | (return)] |
11301 | "TARGET_64BIT | |
11302 | && DEFAULT_ABI == ABI_AIX | |
11303 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
11304 | "b %z1" | |
11305 | [(set_attr "type" "branch") | |
11306 | (set_attr "length" "4")]) | |
11307 | ||
11308 | (define_insn "*sibcall_nonlocal_sysv" | |
11309 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
11310 | (match_operand 1 "" "")) | |
11311 | (use (match_operand 2 "immediate_operand" "O,n")) | |
fe352c29 | 11312 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
11313 | (return)] |
11314 | "(DEFAULT_ABI == ABI_DARWIN | |
11315 | || DEFAULT_ABI == ABI_V4 | |
11316 | || DEFAULT_ABI == ABI_AIX_NODESC) | |
11317 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
11318 | "* | |
11319 | { | |
11320 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
11321 | output_asm_insn (\"crxor 6,6,6\", operands); | |
11322 | ||
11323 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
11324 | output_asm_insn (\"creqv 6,6,6\", operands); | |
11325 | ||
11326 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\"; | |
11327 | }" | |
11328 | [(set_attr "type" "branch,branch") | |
11329 | (set_attr "length" "4,8")]) | |
11330 | ||
11331 | (define_expand "sibcall_value" | |
11332 | [(parallel [(set (match_operand 0 "register_operand" "") | |
11333 | (call (mem:SI (match_operand 1 "address_operand" "")) | |
11334 | (match_operand 2 "" ""))) | |
11335 | (use (match_operand 3 "" "")) | |
fe352c29 | 11336 | (use (match_operand 4 "" "")) |
5e1bf043 DJ |
11337 | (return)])] |
11338 | "" | |
11339 | " | |
11340 | { | |
11341 | #if TARGET_MACHO | |
11342 | if (flag_pic) | |
11343 | operands[1] = machopic_indirect_call_target (operands[1]); | |
11344 | #endif | |
11345 | ||
11346 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) | |
11347 | abort (); | |
11348 | ||
11349 | operands[1] = XEXP (operands[1], 0); | |
fe352c29 | 11350 | operands[4] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
11351 | |
11352 | }") | |
11353 | ||
11354 | (define_insn "*sibcall_value_nonlocal_sysv" | |
11355 | [(set (match_operand 0 "" "") | |
11356 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
11357 | (match_operand 2 "" ""))) | |
11358 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 11359 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
11360 | (return)] |
11361 | "(DEFAULT_ABI == ABI_DARWIN | |
11362 | || DEFAULT_ABI == ABI_V4 | |
11363 | || DEFAULT_ABI == ABI_AIX_NODESC) | |
11364 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
11365 | "* | |
11366 | { | |
11367 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
11368 | output_asm_insn (\"crxor 6,6,6\", operands); | |
11369 | ||
11370 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
11371 | output_asm_insn (\"creqv 6,6,6\", operands); | |
11372 | ||
11373 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\"; | |
11374 | }" | |
11375 | [(set_attr "type" "branch,branch") | |
11376 | (set_attr "length" "4,8")]) | |
11377 | ||
11378 | (define_expand "sibcall_epilogue" | |
11379 | [(use (const_int 0))] | |
11380 | "TARGET_SCHED_PROLOG" | |
11381 | " | |
11382 | { | |
11383 | rs6000_emit_epilogue (TRUE); | |
11384 | DONE; | |
11385 | }") | |
11386 | ||
e6f948e3 RK |
11387 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and |
11388 | ;; all of memory. This blocks insns from being moved across this point. | |
11389 | ||
11390 | (define_insn "blockage" | |
11391 | [(unspec_volatile [(const_int 0)] 0)] | |
11392 | "" | |
11393 | "") | |
1fd4e8c1 RK |
11394 | \f |
11395 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 11396 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
11397 | ;; |
11398 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
11399 | ;; insns, and branches. We store the operands of compares until we see | |
11400 | ;; how it is used. | |
11401 | (define_expand "cmpsi" | |
11402 | [(set (cc0) | |
cd2b37d9 | 11403 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11404 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
11405 | "" | |
11406 | " | |
11407 | { | |
11408 | /* Take care of the possibility that operands[1] might be negative but | |
11409 | this might be a logical operation. That insn doesn't exist. */ | |
11410 | if (GET_CODE (operands[1]) == CONST_INT | |
11411 | && INTVAL (operands[1]) < 0) | |
11412 | operands[1] = force_reg (SImode, operands[1]); | |
11413 | ||
11414 | rs6000_compare_op0 = operands[0]; | |
11415 | rs6000_compare_op1 = operands[1]; | |
11416 | rs6000_compare_fp_p = 0; | |
11417 | DONE; | |
11418 | }") | |
11419 | ||
266eb58a DE |
11420 | (define_expand "cmpdi" |
11421 | [(set (cc0) | |
11422 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
11423 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
11424 | "TARGET_POWERPC64" | |
11425 | " | |
11426 | { | |
11427 | /* Take care of the possibility that operands[1] might be negative but | |
11428 | this might be a logical operation. That insn doesn't exist. */ | |
11429 | if (GET_CODE (operands[1]) == CONST_INT | |
11430 | && INTVAL (operands[1]) < 0) | |
11431 | operands[1] = force_reg (DImode, operands[1]); | |
11432 | ||
11433 | rs6000_compare_op0 = operands[0]; | |
11434 | rs6000_compare_op1 = operands[1]; | |
11435 | rs6000_compare_fp_p = 0; | |
11436 | DONE; | |
11437 | }") | |
11438 | ||
1fd4e8c1 | 11439 | (define_expand "cmpsf" |
cd2b37d9 RK |
11440 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
11441 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 11442 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
11443 | " |
11444 | { | |
11445 | rs6000_compare_op0 = operands[0]; | |
11446 | rs6000_compare_op1 = operands[1]; | |
11447 | rs6000_compare_fp_p = 1; | |
11448 | DONE; | |
11449 | }") | |
11450 | ||
11451 | (define_expand "cmpdf" | |
cd2b37d9 RK |
11452 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
11453 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 11454 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11455 | " |
11456 | { | |
11457 | rs6000_compare_op0 = operands[0]; | |
11458 | rs6000_compare_op1 = operands[1]; | |
11459 | rs6000_compare_fp_p = 1; | |
11460 | DONE; | |
11461 | }") | |
11462 | ||
d6f99ca4 | 11463 | (define_expand "cmptf" |
e7a4130e DE |
11464 | [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "") |
11465 | (match_operand:TF 1 "gpc_reg_operand" "")))] | |
a3170dc6 AH |
11466 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT |
11467 | && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
d6f99ca4 DE |
11468 | " |
11469 | { | |
11470 | rs6000_compare_op0 = operands[0]; | |
11471 | rs6000_compare_op1 = operands[1]; | |
11472 | rs6000_compare_fp_p = 1; | |
11473 | DONE; | |
11474 | }") | |
11475 | ||
1fd4e8c1 | 11476 | (define_expand "beq" |
39a10a29 | 11477 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 11478 | "" |
39a10a29 | 11479 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
11480 | |
11481 | (define_expand "bne" | |
39a10a29 | 11482 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 11483 | "" |
39a10a29 | 11484 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 11485 | |
39a10a29 GK |
11486 | (define_expand "bge" |
11487 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11488 | "" |
39a10a29 | 11489 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
11490 | |
11491 | (define_expand "bgt" | |
39a10a29 | 11492 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 11493 | "" |
39a10a29 | 11494 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
11495 | |
11496 | (define_expand "ble" | |
39a10a29 | 11497 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 11498 | "" |
39a10a29 | 11499 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 11500 | |
39a10a29 GK |
11501 | (define_expand "blt" |
11502 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11503 | "" |
39a10a29 | 11504 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 11505 | |
39a10a29 GK |
11506 | (define_expand "bgeu" |
11507 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11508 | "" |
39a10a29 | 11509 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 11510 | |
39a10a29 GK |
11511 | (define_expand "bgtu" |
11512 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11513 | "" |
39a10a29 | 11514 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 11515 | |
39a10a29 GK |
11516 | (define_expand "bleu" |
11517 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11518 | "" |
39a10a29 | 11519 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 11520 | |
39a10a29 GK |
11521 | (define_expand "bltu" |
11522 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 11523 | "" |
39a10a29 | 11524 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 11525 | |
1c882ea4 | 11526 | (define_expand "bunordered" |
39a10a29 | 11527 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11528 | "" |
39a10a29 | 11529 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
11530 | |
11531 | (define_expand "bordered" | |
39a10a29 | 11532 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11533 | "" |
39a10a29 | 11534 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
11535 | |
11536 | (define_expand "buneq" | |
39a10a29 | 11537 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11538 | "" |
39a10a29 | 11539 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
11540 | |
11541 | (define_expand "bunge" | |
39a10a29 | 11542 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11543 | "" |
39a10a29 | 11544 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
11545 | |
11546 | (define_expand "bungt" | |
39a10a29 | 11547 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11548 | "" |
39a10a29 | 11549 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
11550 | |
11551 | (define_expand "bunle" | |
39a10a29 | 11552 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11553 | "" |
39a10a29 | 11554 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
11555 | |
11556 | (define_expand "bunlt" | |
39a10a29 | 11557 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11558 | "" |
39a10a29 | 11559 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
11560 | |
11561 | (define_expand "bltgt" | |
39a10a29 | 11562 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11563 | "" |
39a10a29 | 11564 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 11565 | |
1fd4e8c1 RK |
11566 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
11567 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
11568 | ;; with an scc insns. However, due to the order that combine see the | |
11569 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
11570 | ;; the cases we don't want to handle. | |
11571 | (define_expand "seq" | |
39a10a29 | 11572 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11573 | "" |
39a10a29 | 11574 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
11575 | |
11576 | (define_expand "sne" | |
39a10a29 | 11577 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11578 | "" |
11579 | " | |
39a10a29 GK |
11580 | { |
11581 | if (! rs6000_compare_fp_p) | |
1fd4e8c1 RK |
11582 | FAIL; |
11583 | ||
39a10a29 GK |
11584 | rs6000_emit_sCOND (NE, operands[0]); |
11585 | DONE; | |
1fd4e8c1 RK |
11586 | }") |
11587 | ||
11588 | ;; A > 0 is best done using the portable sequence, so fail in that case. | |
11589 | (define_expand "sgt" | |
39a10a29 | 11590 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11591 | "" |
11592 | " | |
5638268e DE |
11593 | { |
11594 | if (! rs6000_compare_fp_p | |
11595 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
11596 | FAIL; |
11597 | ||
39a10a29 GK |
11598 | rs6000_emit_sCOND (GT, operands[0]); |
11599 | DONE; | |
1fd4e8c1 RK |
11600 | }") |
11601 | ||
11602 | ;; A < 0 is best done in the portable way for A an integer. | |
11603 | (define_expand "slt" | |
39a10a29 | 11604 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11605 | "" |
11606 | " | |
5638268e DE |
11607 | { |
11608 | if (! rs6000_compare_fp_p | |
11609 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
11610 | FAIL; |
11611 | ||
39a10a29 GK |
11612 | rs6000_emit_sCOND (LT, operands[0]); |
11613 | DONE; | |
1fd4e8c1 RK |
11614 | }") |
11615 | ||
5638268e | 11616 | ;; A >= 0 is best done the portable way for A an integer. |
1fd4e8c1 | 11617 | (define_expand "sge" |
39a10a29 | 11618 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11619 | "" |
5638268e DE |
11620 | " |
11621 | { | |
11622 | if (! rs6000_compare_fp_p | |
11623 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
11624 | FAIL; | |
11625 | ||
11626 | rs6000_emit_sCOND (GE, operands[0]); | |
11627 | DONE; | |
11628 | }") | |
1fd4e8c1 RK |
11629 | |
11630 | ;; A <= 0 is best done the portable way for A an integer. | |
11631 | (define_expand "sle" | |
39a10a29 | 11632 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11633 | "" |
11634 | " | |
5638268e DE |
11635 | { |
11636 | if (! rs6000_compare_fp_p | |
11637 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
11638 | FAIL; |
11639 | ||
39a10a29 GK |
11640 | rs6000_emit_sCOND (LE, operands[0]); |
11641 | DONE; | |
1fd4e8c1 RK |
11642 | }") |
11643 | ||
11644 | (define_expand "sgtu" | |
39a10a29 | 11645 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11646 | "" |
39a10a29 | 11647 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
11648 | |
11649 | (define_expand "sltu" | |
39a10a29 | 11650 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11651 | "" |
39a10a29 | 11652 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
11653 | |
11654 | (define_expand "sgeu" | |
39a10a29 | 11655 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11656 | "" |
39a10a29 | 11657 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
11658 | |
11659 | (define_expand "sleu" | |
39a10a29 | 11660 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11661 | "" |
39a10a29 | 11662 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
11663 | \f |
11664 | ;; Here are the actual compare insns. | |
acad7ed3 | 11665 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 11666 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 11667 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
11668 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
11669 | "" | |
7f340546 | 11670 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
1fd4e8c1 RK |
11671 | [(set_attr "type" "compare")]) |
11672 | ||
acad7ed3 | 11673 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
11674 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
11675 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
11676 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
11677 | "TARGET_POWERPC64" | |
11678 | "cmpd%I2 %0,%1,%2" | |
11679 | [(set_attr "type" "compare")]) | |
11680 | ||
f357808b RK |
11681 | ;; If we are comparing a register for equality with a large constant, |
11682 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
11683 | ;; register for the result of the XOR. | |
11684 | ||
11685 | (define_split | |
11686 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 11687 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 11688 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 11689 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
11690 | "find_single_use (operands[0], insn, 0) |
11691 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
11692 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
11693 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
11694 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
11695 | " | |
11696 | { | |
11697 | /* Get the constant we are comparing against, C, and see what it looks like | |
11698 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
11699 | with C to get the sign-extended value. */ | |
11700 | ||
5f59ecb7 | 11701 | HOST_WIDE_INT c = INTVAL (operands[2]); |
a65c591c | 11702 | HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; |
5f59ecb7 | 11703 | HOST_WIDE_INT xorv = c ^ sextc; |
f357808b | 11704 | |
89e9f3a8 MM |
11705 | operands[4] = GEN_INT (xorv); |
11706 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
11707 | }") |
11708 | ||
acad7ed3 | 11709 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 11710 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 11711 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 11712 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 11713 | "" |
e2c953b6 | 11714 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
1fd4e8c1 RK |
11715 | [(set_attr "type" "compare")]) |
11716 | ||
acad7ed3 | 11717 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
11718 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
11719 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 11720 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 11721 | "" |
e2c953b6 | 11722 | "cmpld%I2 %0,%1,%b2" |
266eb58a DE |
11723 | [(set_attr "type" "compare")]) |
11724 | ||
1fd4e8c1 RK |
11725 | ;; The following two insns don't exist as single insns, but if we provide |
11726 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
11727 | ;; of the required delay between a compare and branch. We generate code for | |
11728 | ;; them by splitting. | |
11729 | ||
11730 | (define_insn "" | |
11731 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11732 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11733 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 11734 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11735 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11736 | "" | |
baf97f86 RK |
11737 | "#" |
11738 | [(set_attr "length" "8")]) | |
7e69e155 | 11739 | |
1fd4e8c1 RK |
11740 | (define_insn "" |
11741 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11742 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11743 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 11744 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11745 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11746 | "" | |
baf97f86 RK |
11747 | "#" |
11748 | [(set_attr "length" "8")]) | |
7e69e155 | 11749 | |
1fd4e8c1 RK |
11750 | (define_split |
11751 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 11752 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11753 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 11754 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11755 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11756 | "" | |
11757 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
11758 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11759 | ||
11760 | (define_split | |
11761 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 11762 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11763 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 11764 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11765 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11766 | "" | |
11767 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
11768 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11769 | ||
acad7ed3 | 11770 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 11771 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11772 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
11773 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11774 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11775 | "fcmpu %0,%1,%2" |
11776 | [(set_attr "type" "fpcompare")]) | |
11777 | ||
acad7ed3 | 11778 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 11779 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11780 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
11781 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11782 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11783 | "fcmpu %0,%1,%2" |
11784 | [(set_attr "type" "fpcompare")]) | |
d6f99ca4 DE |
11785 | |
11786 | ;; Only need to compare second words if first words equal | |
11787 | (define_insn "*cmptf_internal1" | |
11788 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
11789 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
11790 | (match_operand:TF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 AH |
11791 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS |
11792 | && TARGET_LONG_DOUBLE_128" | |
2e7d5318 | 11793 | "fcmpu %0,%1,%2\;bne %0,$+4\;fcmpu %0,%L1,%L2" |
d6f99ca4 DE |
11794 | [(set_attr "type" "fpcompare") |
11795 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
11796 | \f |
11797 | ;; Now we have the scc insns. We can do some combinations because of the | |
11798 | ;; way the machine works. | |
11799 | ;; | |
11800 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
11801 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
11802 | ;; cases the insns below which don't use an intermediate CR field will | |
11803 | ;; be used instead. | |
1fd4e8c1 | 11804 | (define_insn "" |
cd2b37d9 | 11805 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11806 | (match_operator:SI 1 "scc_comparison_operator" |
11807 | [(match_operand 2 "cc_reg_operand" "y") | |
11808 | (const_int 0)]))] | |
11809 | "" | |
ca7f5001 | 11810 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" |
309323c2 DE |
11811 | [(set_attr "type" "cr_logical") |
11812 | (set_attr "length" "12")]) | |
1fd4e8c1 | 11813 | |
a3170dc6 AH |
11814 | ;; Same as above, but get the OV/ORDERED bit. |
11815 | (define_insn "move_from_CR_ov_bit" | |
11816 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
11817 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] 724))] | |
11818 | "TARGET_ISEL" | |
11819 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1" | |
11820 | [(set_attr "length" "12")]) | |
11821 | ||
1fd4e8c1 | 11822 | (define_insn "" |
9ebbca7d GK |
11823 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
11824 | (match_operator:DI 1 "scc_comparison_operator" | |
11825 | [(match_operand 2 "cc_reg_operand" "y") | |
11826 | (const_int 0)]))] | |
11827 | "TARGET_POWERPC64" | |
11828 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" | |
309323c2 DE |
11829 | [(set_attr "type" "cr_logical") |
11830 | (set_attr "length" "12")]) | |
9ebbca7d GK |
11831 | |
11832 | (define_insn "" | |
11833 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 11834 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 11835 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
11836 | (const_int 0)]) |
11837 | (const_int 0))) | |
9ebbca7d | 11838 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11839 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
0ad91047 | 11840 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11841 | "@ |
11842 | %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1 | |
11843 | #" | |
b19003d8 | 11844 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11845 | (set_attr "length" "12,16")]) |
11846 | ||
11847 | (define_split | |
11848 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11849 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
11850 | [(match_operand 2 "cc_reg_operand" "") | |
11851 | (const_int 0)]) | |
11852 | (const_int 0))) | |
11853 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
11854 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
11855 | "! TARGET_POWERPC64 && reload_completed" | |
11856 | [(set (match_dup 3) | |
11857 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
11858 | (set (match_dup 0) | |
11859 | (compare:CC (match_dup 3) | |
11860 | (const_int 0)))] | |
11861 | "") | |
1fd4e8c1 RK |
11862 | |
11863 | (define_insn "" | |
cd2b37d9 | 11864 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11865 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
11866 | [(match_operand 2 "cc_reg_operand" "y") | |
11867 | (const_int 0)]) | |
11868 | (match_operand:SI 3 "const_int_operand" "n")))] | |
11869 | "" | |
11870 | "* | |
11871 | { | |
11872 | int is_bit = ccr_bit (operands[1], 1); | |
11873 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11874 | int count; | |
11875 | ||
11876 | if (is_bit >= put_bit) | |
11877 | count = is_bit - put_bit; | |
11878 | else | |
11879 | count = 32 - (put_bit - is_bit); | |
11880 | ||
89e9f3a8 MM |
11881 | operands[4] = GEN_INT (count); |
11882 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 11883 | |
ca7f5001 | 11884 | return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 | 11885 | }" |
309323c2 DE |
11886 | [(set_attr "type" "cr_logical") |
11887 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
11888 | |
11889 | (define_insn "" | |
9ebbca7d | 11890 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11891 | (compare:CC |
11892 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 11893 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 11894 | (const_int 0)]) |
9ebbca7d | 11895 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 11896 | (const_int 0))) |
9ebbca7d | 11897 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11898 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
11899 | (match_dup 3)))] | |
ce71f754 | 11900 | "" |
1fd4e8c1 RK |
11901 | "* |
11902 | { | |
11903 | int is_bit = ccr_bit (operands[1], 1); | |
11904 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11905 | int count; | |
11906 | ||
9ebbca7d GK |
11907 | /* Force split for non-cc0 compare. */ |
11908 | if (which_alternative == 1) | |
11909 | return \"#\"; | |
11910 | ||
1fd4e8c1 RK |
11911 | if (is_bit >= put_bit) |
11912 | count = is_bit - put_bit; | |
11913 | else | |
11914 | count = 32 - (put_bit - is_bit); | |
11915 | ||
89e9f3a8 MM |
11916 | operands[5] = GEN_INT (count); |
11917 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 11918 | |
ca7f5001 | 11919 | return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 11920 | }" |
b19003d8 | 11921 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11922 | (set_attr "length" "12,16")]) |
11923 | ||
11924 | (define_split | |
11925 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11926 | (compare:CC | |
11927 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
11928 | [(match_operand 2 "cc_reg_operand" "") | |
11929 | (const_int 0)]) | |
11930 | (match_operand:SI 3 "const_int_operand" "")) | |
11931 | (const_int 0))) | |
11932 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
11933 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11934 | (match_dup 3)))] | |
ce71f754 | 11935 | "reload_completed" |
9ebbca7d GK |
11936 | [(set (match_dup 4) |
11937 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11938 | (match_dup 3))) | |
11939 | (set (match_dup 0) | |
11940 | (compare:CC (match_dup 4) | |
11941 | (const_int 0)))] | |
11942 | "") | |
1fd4e8c1 | 11943 | |
c5defebb RK |
11944 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
11945 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
11946 | ||
11947 | (define_peephole | |
cd2b37d9 | 11948 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
11949 | (match_operator:SI 1 "scc_comparison_operator" |
11950 | [(match_operand 2 "cc_reg_operand" "y") | |
11951 | (const_int 0)])) | |
cd2b37d9 | 11952 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
11953 | (match_operator:SI 4 "scc_comparison_operator" |
11954 | [(match_operand 5 "cc_reg_operand" "y") | |
11955 | (const_int 0)]))] | |
309323c2 DE |
11956 | "REGNO (operands[2]) != REGNO (operands[5])" |
11957 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" | |
11958 | [(set_attr "type" "cr_logical") | |
11959 | (set_attr "length" "20")]) | |
c5defebb | 11960 | |
9ebbca7d GK |
11961 | (define_peephole |
11962 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11963 | (match_operator:DI 1 "scc_comparison_operator" | |
11964 | [(match_operand 2 "cc_reg_operand" "y") | |
11965 | (const_int 0)])) | |
11966 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
11967 | (match_operator:DI 4 "scc_comparison_operator" | |
11968 | [(match_operand 5 "cc_reg_operand" "y") | |
11969 | (const_int 0)]))] | |
309323c2 DE |
11970 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" |
11971 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" | |
11972 | [(set_attr "type" "cr_logical") | |
11973 | (set_attr "length" "20")]) | |
9ebbca7d | 11974 | |
1fd4e8c1 RK |
11975 | ;; There are some scc insns that can be done directly, without a compare. |
11976 | ;; These are faster because they don't involve the communications between | |
11977 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
11978 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
11979 | ;; | |
11980 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
11981 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
11982 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
11983 | ;; cases where it is no more expensive than (neg (scc ..)). | |
11984 | ||
11985 | ;; Have reload force a constant into a register for the simple insns that | |
11986 | ;; otherwise won't accept constants. We do this because it is faster than | |
11987 | ;; the cmp/mfcr sequence we would otherwise generate. | |
11988 | ||
11989 | (define_insn "" | |
cd2b37d9 RK |
11990 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
11991 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 11992 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 11993 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
f9562f27 | 11994 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11995 | "@ |
ca7f5001 | 11996 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 11997 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
11998 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
11999 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
12000 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 12001 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 12002 | |
a260abc9 DE |
12003 | (define_insn "" |
12004 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
12005 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
12006 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
12007 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
12008 | "TARGET_POWERPC64" | |
12009 | "@ | |
12010 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
12011 | subfic %3,%1,0\;adde %0,%3,%1 | |
12012 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
12013 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
12014 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
12015 | [(set_attr "length" "12,8,12,12,12")]) | |
12016 | ||
1fd4e8c1 | 12017 | (define_insn "" |
9ebbca7d | 12018 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 12019 | (compare:CC |
9ebbca7d GK |
12020 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
12021 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 12022 | (const_int 0))) |
9ebbca7d | 12023 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 12024 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12025 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
f9562f27 | 12026 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12027 | "@ |
ca7f5001 RK |
12028 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
12029 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
12030 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
12031 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
12032 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
12033 | # | |
12034 | # | |
12035 | # | |
12036 | # | |
12037 | #" | |
b19003d8 | 12038 | [(set_attr "type" "compare") |
9ebbca7d GK |
12039 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
12040 | ||
12041 | (define_split | |
12042 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12043 | (compare:CC | |
12044 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12045 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
12046 | (const_int 0))) | |
12047 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12048 | (eq:SI (match_dup 1) (match_dup 2))) | |
12049 | (clobber (match_scratch:SI 3 ""))] | |
12050 | "! TARGET_POWERPC64 && reload_completed" | |
12051 | [(parallel [(set (match_dup 0) | |
12052 | (eq:SI (match_dup 1) (match_dup 2))) | |
12053 | (clobber (match_dup 3))]) | |
12054 | (set (match_dup 4) | |
12055 | (compare:CC (match_dup 0) | |
12056 | (const_int 0)))] | |
12057 | "") | |
b19003d8 | 12058 | |
a260abc9 | 12059 | (define_insn "" |
9ebbca7d | 12060 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 12061 | (compare:CC |
9ebbca7d GK |
12062 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
12063 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 12064 | (const_int 0))) |
9ebbca7d | 12065 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 12066 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12067 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
a260abc9 DE |
12068 | "TARGET_POWERPC64" |
12069 | "@ | |
12070 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
12071 | subfic %3,%1,0\;adde. %0,%3,%1 | |
12072 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
12073 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
12074 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
12075 | # | |
12076 | # | |
12077 | # | |
12078 | # | |
12079 | #" | |
a260abc9 | 12080 | [(set_attr "type" "compare") |
9ebbca7d GK |
12081 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
12082 | ||
12083 | (define_split | |
12084 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12085 | (compare:CC | |
12086 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12087 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
12088 | (const_int 0))) | |
12089 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12090 | (eq:DI (match_dup 1) (match_dup 2))) | |
12091 | (clobber (match_scratch:DI 3 ""))] | |
12092 | "TARGET_POWERPC64 && reload_completed" | |
12093 | [(parallel [(set (match_dup 0) | |
12094 | (eq:DI (match_dup 1) (match_dup 2))) | |
12095 | (clobber (match_dup 3))]) | |
12096 | (set (match_dup 4) | |
12097 | (compare:CC (match_dup 0) | |
12098 | (const_int 0)))] | |
12099 | "") | |
a260abc9 | 12100 | |
b19003d8 RK |
12101 | ;; We have insns of the form shown by the first define_insn below. If |
12102 | ;; there is something inside the comparison operation, we must split it. | |
12103 | (define_split | |
12104 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
12105 | (plus:SI (match_operator 1 "comparison_operator" | |
12106 | [(match_operand:SI 2 "" "") | |
12107 | (match_operand:SI 3 | |
12108 | "reg_or_cint_operand" "")]) | |
12109 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
12110 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
12111 | "! gpc_reg_operand (operands[2], SImode)" | |
12112 | [(set (match_dup 5) (match_dup 2)) | |
12113 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
12114 | (match_dup 4)))]) | |
1fd4e8c1 RK |
12115 | |
12116 | (define_insn "" | |
5276df18 | 12117 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") |
cd2b37d9 | 12118 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 12119 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
5276df18 | 12120 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] |
f9562f27 | 12121 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12122 | "@ |
5276df18 DE |
12123 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
12124 | {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 | |
12125 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
12126 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
12127 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" | |
b19003d8 | 12128 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
12129 | |
12130 | (define_insn "" | |
9ebbca7d | 12131 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 12132 | (compare:CC |
1fd4e8c1 | 12133 | (plus:SI |
9ebbca7d GK |
12134 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
12135 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
12136 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 12137 | (const_int 0))) |
9ebbca7d | 12138 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 12139 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12140 | "@ |
ca7f5001 | 12141 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 12142 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
12143 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
12144 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
12145 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
12146 | # | |
12147 | # | |
12148 | # | |
12149 | # | |
12150 | #" | |
b19003d8 | 12151 | [(set_attr "type" "compare") |
9ebbca7d GK |
12152 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
12153 | ||
12154 | (define_split | |
12155 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12156 | (compare:CC | |
12157 | (plus:SI | |
12158 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12159 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
12160 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12161 | (const_int 0))) | |
12162 | (clobber (match_scratch:SI 4 ""))] | |
12163 | "! TARGET_POWERPC64 && reload_completed" | |
12164 | [(set (match_dup 4) | |
12165 | (plus:SI (eq:SI (match_dup 1) | |
12166 | (match_dup 2)) | |
12167 | (match_dup 3))) | |
12168 | (set (match_dup 0) | |
12169 | (compare:CC (match_dup 4) | |
12170 | (const_int 0)))] | |
12171 | "") | |
1fd4e8c1 RK |
12172 | |
12173 | (define_insn "" | |
0387639b | 12174 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 12175 | (compare:CC |
1fd4e8c1 | 12176 | (plus:SI |
9ebbca7d GK |
12177 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
12178 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
12179 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 12180 | (const_int 0))) |
0387639b DE |
12181 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") |
12182 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 12183 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12184 | "@ |
0387639b DE |
12185 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
12186 | {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 | |
12187 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
12188 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
12189 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12190 | # |
12191 | # | |
12192 | # | |
12193 | # | |
12194 | #" | |
12195 | [(set_attr "type" "compare") | |
12196 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
12197 | ||
12198 | (define_split | |
0387639b | 12199 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12200 | (compare:CC |
12201 | (plus:SI | |
12202 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12203 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
12204 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12205 | (const_int 0))) | |
12206 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
0387639b | 12207 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12208 | "! TARGET_POWERPC64 && reload_completed" |
0387639b | 12209 | [(set (match_dup 0) |
9ebbca7d | 12210 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
0387639b | 12211 | (set (match_dup 4) |
9ebbca7d GK |
12212 | (compare:CC (match_dup 0) |
12213 | (const_int 0)))] | |
12214 | "") | |
12215 | ||
1fd4e8c1 | 12216 | (define_insn "" |
cd2b37d9 | 12217 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 12218 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 12219 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
f9562f27 | 12220 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12221 | "@ |
ca7f5001 RK |
12222 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
12223 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
12224 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
12225 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
12226 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12227 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 12228 | |
ea9be077 MM |
12229 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
12230 | ;; since it nabs/sr is just as fast. | |
463b558b | 12231 | (define_insn "*ne0" |
b4e95693 | 12232 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
12233 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
12234 | (const_int 31))) | |
12235 | (clobber (match_scratch:SI 2 "=&r"))] | |
a3170dc6 | 12236 | "! TARGET_POWER && ! TARGET_POWERPC64 && !TARGET_ISEL" |
ea9be077 MM |
12237 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
12238 | [(set_attr "length" "8")]) | |
12239 | ||
a260abc9 DE |
12240 | (define_insn "" |
12241 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12242 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
12243 | (const_int 63))) | |
12244 | (clobber (match_scratch:DI 2 "=&r"))] | |
12245 | "TARGET_POWERPC64" | |
12246 | "addic %2,%1,-1\;subfe %0,%2,%1" | |
12247 | [(set_attr "length" "8")]) | |
12248 | ||
1fd4e8c1 RK |
12249 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
12250 | (define_insn "" | |
cd2b37d9 | 12251 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 12252 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 12253 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 12254 | (const_int 31)) |
cd2b37d9 | 12255 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 12256 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 12257 | "! TARGET_POWERPC64" |
ca7f5001 | 12258 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 12259 | [(set_attr "length" "8")]) |
1fd4e8c1 | 12260 | |
a260abc9 DE |
12261 | (define_insn "" |
12262 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12263 | (plus:DI (lshiftrt:DI | |
12264 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
12265 | (const_int 63)) | |
12266 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
12267 | (clobber (match_scratch:DI 3 "=&r"))] | |
12268 | "TARGET_POWERPC64" | |
12269 | "addic %3,%1,-1\;addze %0,%2" | |
12270 | [(set_attr "length" "8")]) | |
12271 | ||
1fd4e8c1 | 12272 | (define_insn "" |
9ebbca7d | 12273 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12274 | (compare:CC |
12275 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 12276 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 12277 | (const_int 31)) |
9ebbca7d | 12278 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 12279 | (const_int 0))) |
889b90a1 GK |
12280 | (clobber (match_scratch:SI 3 "=&r,&r")) |
12281 | (clobber (match_scratch:SI 4 "=X,&r"))] | |
f9562f27 | 12282 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12283 | "@ |
12284 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
12285 | #" | |
b19003d8 | 12286 | [(set_attr "type" "compare") |
9ebbca7d GK |
12287 | (set_attr "length" "8,12")]) |
12288 | ||
12289 | (define_split | |
12290 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12291 | (compare:CC | |
12292 | (plus:SI (lshiftrt:SI | |
12293 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
12294 | (const_int 31)) | |
12295 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
12296 | (const_int 0))) | |
889b90a1 GK |
12297 | (clobber (match_scratch:SI 3 "")) |
12298 | (clobber (match_scratch:SI 4 ""))] | |
9ebbca7d | 12299 | "! TARGET_POWERPC64 && reload_completed" |
889b90a1 | 12300 | [(parallel [(set (match_dup 3) |
ce71f754 AM |
12301 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) |
12302 | (const_int 31)) | |
12303 | (match_dup 2))) | |
889b90a1 | 12304 | (clobber (match_dup 4))]) |
9ebbca7d GK |
12305 | (set (match_dup 0) |
12306 | (compare:CC (match_dup 3) | |
12307 | (const_int 0)))] | |
12308 | "") | |
1fd4e8c1 | 12309 | |
a260abc9 | 12310 | (define_insn "" |
9ebbca7d | 12311 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
12312 | (compare:CC |
12313 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 12314 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 12315 | (const_int 63)) |
9ebbca7d | 12316 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 12317 | (const_int 0))) |
9ebbca7d | 12318 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 12319 | "TARGET_POWERPC64" |
9ebbca7d GK |
12320 | "@ |
12321 | addic %3,%1,-1\;addze. %3,%2 | |
12322 | #" | |
a260abc9 | 12323 | [(set_attr "type" "compare") |
9ebbca7d GK |
12324 | (set_attr "length" "8,12")]) |
12325 | ||
12326 | (define_split | |
12327 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12328 | (compare:CC | |
12329 | (plus:DI (lshiftrt:DI | |
12330 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
12331 | (const_int 63)) | |
12332 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12333 | (const_int 0))) | |
12334 | (clobber (match_scratch:DI 3 ""))] | |
12335 | "TARGET_POWERPC64 && reload_completed" | |
12336 | [(set (match_dup 3) | |
12337 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
12338 | (const_int 63)) | |
12339 | (match_dup 2))) | |
12340 | (set (match_dup 0) | |
12341 | (compare:CC (match_dup 3) | |
12342 | (const_int 0)))] | |
12343 | "") | |
a260abc9 | 12344 | |
1fd4e8c1 | 12345 | (define_insn "" |
9ebbca7d | 12346 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12347 | (compare:CC |
12348 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 12349 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 12350 | (const_int 31)) |
9ebbca7d | 12351 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 12352 | (const_int 0))) |
9ebbca7d | 12353 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
12354 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
12355 | (match_dup 2))) | |
9ebbca7d | 12356 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 12357 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12358 | "@ |
12359 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
12360 | #" | |
b19003d8 | 12361 | [(set_attr "type" "compare") |
9ebbca7d GK |
12362 | (set_attr "length" "8,12")]) |
12363 | ||
12364 | (define_split | |
12365 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12366 | (compare:CC | |
12367 | (plus:SI (lshiftrt:SI | |
12368 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
12369 | (const_int 31)) | |
12370 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
12371 | (const_int 0))) | |
12372 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12373 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
12374 | (match_dup 2))) | |
12375 | (clobber (match_scratch:SI 3 ""))] | |
12376 | "! TARGET_POWERPC64 && reload_completed" | |
12377 | [(parallel [(set (match_dup 0) | |
12378 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
12379 | (match_dup 2))) | |
12380 | (clobber (match_dup 3))]) | |
12381 | (set (match_dup 4) | |
12382 | (compare:CC (match_dup 0) | |
12383 | (const_int 0)))] | |
12384 | "") | |
1fd4e8c1 | 12385 | |
a260abc9 | 12386 | (define_insn "" |
9ebbca7d | 12387 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
12388 | (compare:CC |
12389 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 12390 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 12391 | (const_int 63)) |
9ebbca7d | 12392 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 12393 | (const_int 0))) |
9ebbca7d | 12394 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
12395 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
12396 | (match_dup 2))) | |
9ebbca7d | 12397 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 12398 | "TARGET_POWERPC64" |
9ebbca7d GK |
12399 | "@ |
12400 | addic %3,%1,-1\;addze. %0,%2 | |
12401 | #" | |
a260abc9 | 12402 | [(set_attr "type" "compare") |
9ebbca7d GK |
12403 | (set_attr "length" "8,12")]) |
12404 | ||
12405 | (define_split | |
12406 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12407 | (compare:CC | |
12408 | (plus:DI (lshiftrt:DI | |
12409 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
12410 | (const_int 63)) | |
12411 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12412 | (const_int 0))) | |
12413 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12414 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
12415 | (match_dup 2))) | |
12416 | (clobber (match_scratch:DI 3 ""))] | |
12417 | "TARGET_POWERPC64 && reload_completed" | |
12418 | [(parallel [(set (match_dup 0) | |
12419 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
12420 | (match_dup 2))) | |
12421 | (clobber (match_dup 3))]) | |
12422 | (set (match_dup 4) | |
12423 | (compare:CC (match_dup 0) | |
12424 | (const_int 0)))] | |
12425 | "") | |
a260abc9 | 12426 | |
1fd4e8c1 | 12427 | (define_insn "" |
cd2b37d9 RK |
12428 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12429 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
12430 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
12431 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 12432 | "TARGET_POWER" |
1fd4e8c1 | 12433 | "@ |
ca7f5001 | 12434 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 12435 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12436 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12437 | |
12438 | (define_insn "" | |
9ebbca7d | 12439 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12440 | (compare:CC |
9ebbca7d GK |
12441 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12442 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 12443 | (const_int 0))) |
9ebbca7d | 12444 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12445 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12446 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 12447 | "TARGET_POWER" |
1fd4e8c1 | 12448 | "@ |
ca7f5001 | 12449 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
12450 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
12451 | # | |
12452 | #" | |
12453 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
12454 | (set_attr "length" "12,12,16,16")]) | |
12455 | ||
12456 | (define_split | |
12457 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12458 | (compare:CC | |
12459 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12460 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12461 | (const_int 0))) | |
12462 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12463 | (le:SI (match_dup 1) (match_dup 2))) | |
12464 | (clobber (match_scratch:SI 3 ""))] | |
12465 | "TARGET_POWER && reload_completed" | |
12466 | [(parallel [(set (match_dup 0) | |
12467 | (le:SI (match_dup 1) (match_dup 2))) | |
12468 | (clobber (match_dup 3))]) | |
12469 | (set (match_dup 4) | |
12470 | (compare:CC (match_dup 0) | |
12471 | (const_int 0)))] | |
12472 | "") | |
1fd4e8c1 RK |
12473 | |
12474 | (define_insn "" | |
097657c3 | 12475 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 12476 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12477 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
097657c3 | 12478 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
ca7f5001 | 12479 | "TARGET_POWER" |
1fd4e8c1 | 12480 | "@ |
097657c3 AM |
12481 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
12482 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" | |
b19003d8 | 12483 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12484 | |
12485 | (define_insn "" | |
9ebbca7d | 12486 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12487 | (compare:CC |
9ebbca7d GK |
12488 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12489 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
12490 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12491 | (const_int 0))) |
9ebbca7d | 12492 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 12493 | "TARGET_POWER" |
1fd4e8c1 | 12494 | "@ |
ca7f5001 | 12495 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12496 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
12497 | # | |
12498 | #" | |
b19003d8 | 12499 | [(set_attr "type" "compare") |
9ebbca7d GK |
12500 | (set_attr "length" "12,12,16,16")]) |
12501 | ||
12502 | (define_split | |
12503 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12504 | (compare:CC | |
12505 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12506 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12507 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12508 | (const_int 0))) | |
12509 | (clobber (match_scratch:SI 4 ""))] | |
12510 | "TARGET_POWER && reload_completed" | |
12511 | [(set (match_dup 4) | |
12512 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12513 | (match_dup 3))) |
9ebbca7d GK |
12514 | (set (match_dup 0) |
12515 | (compare:CC (match_dup 4) | |
12516 | (const_int 0)))] | |
12517 | "") | |
1fd4e8c1 RK |
12518 | |
12519 | (define_insn "" | |
097657c3 | 12520 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12521 | (compare:CC |
9ebbca7d GK |
12522 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12523 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
12524 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12525 | (const_int 0))) |
097657c3 AM |
12526 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12527 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12528 | "TARGET_POWER" |
1fd4e8c1 | 12529 | "@ |
097657c3 AM |
12530 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
12531 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12532 | # |
12533 | #" | |
b19003d8 | 12534 | [(set_attr "type" "compare") |
9ebbca7d GK |
12535 | (set_attr "length" "12,12,16,16")]) |
12536 | ||
12537 | (define_split | |
097657c3 | 12538 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12539 | (compare:CC |
12540 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12541 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12542 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12543 | (const_int 0))) | |
12544 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12545 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12546 | "TARGET_POWER && reload_completed" |
097657c3 | 12547 | [(set (match_dup 0) |
9ebbca7d | 12548 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12549 | (set (match_dup 4) |
9ebbca7d GK |
12550 | (compare:CC (match_dup 0) |
12551 | (const_int 0)))] | |
12552 | "") | |
1fd4e8c1 RK |
12553 | |
12554 | (define_insn "" | |
cd2b37d9 RK |
12555 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12556 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12557 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 12558 | "TARGET_POWER" |
1fd4e8c1 | 12559 | "@ |
ca7f5001 RK |
12560 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
12561 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12562 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12563 | |
12564 | (define_insn "" | |
cd2b37d9 RK |
12565 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12566 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12567 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 12568 | "! TARGET_POWERPC64" |
ca7f5001 | 12569 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 12570 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12571 | |
f9562f27 DE |
12572 | (define_insn "" |
12573 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12574 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12575 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
12576 | "TARGET_POWERPC64" | |
12577 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" | |
12578 | [(set_attr "length" "12")]) | |
12579 | ||
12580 | (define_insn "" | |
9ebbca7d | 12581 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12582 | (compare:CC |
9ebbca7d GK |
12583 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12584 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 12585 | (const_int 0))) |
9ebbca7d | 12586 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
12587 | (leu:DI (match_dup 1) (match_dup 2)))] |
12588 | "TARGET_POWERPC64" | |
9ebbca7d GK |
12589 | "@ |
12590 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
12591 | #" | |
f9562f27 | 12592 | [(set_attr "type" "compare") |
9ebbca7d GK |
12593 | (set_attr "length" "12,16")]) |
12594 | ||
12595 | (define_split | |
12596 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12597 | (compare:CC | |
12598 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12599 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12600 | (const_int 0))) | |
12601 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12602 | (leu:DI (match_dup 1) (match_dup 2)))] | |
12603 | "TARGET_POWERPC64 && reload_completed" | |
12604 | [(set (match_dup 0) | |
12605 | (leu:DI (match_dup 1) (match_dup 2))) | |
12606 | (set (match_dup 3) | |
12607 | (compare:CC (match_dup 0) | |
12608 | (const_int 0)))] | |
12609 | "") | |
f9562f27 | 12610 | |
1fd4e8c1 | 12611 | (define_insn "" |
9ebbca7d | 12612 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12613 | (compare:CC |
9ebbca7d GK |
12614 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12615 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12616 | (const_int 0))) |
9ebbca7d | 12617 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12618 | (leu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 12619 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12620 | "@ |
12621 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
12622 | #" | |
b19003d8 | 12623 | [(set_attr "type" "compare") |
9ebbca7d GK |
12624 | (set_attr "length" "12,16")]) |
12625 | ||
12626 | (define_split | |
12627 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12628 | (compare:CC | |
12629 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12630 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12631 | (const_int 0))) | |
12632 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12633 | (leu:SI (match_dup 1) (match_dup 2)))] | |
12634 | "! TARGET_POWERPC64 && reload_completed" | |
12635 | [(set (match_dup 0) | |
12636 | (leu:SI (match_dup 1) (match_dup 2))) | |
12637 | (set (match_dup 3) | |
12638 | (compare:CC (match_dup 0) | |
12639 | (const_int 0)))] | |
12640 | "") | |
1fd4e8c1 | 12641 | |
f9562f27 | 12642 | (define_insn "" |
9ebbca7d | 12643 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12644 | (compare:CC |
9ebbca7d GK |
12645 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12646 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 12647 | (const_int 0))) |
9ebbca7d | 12648 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
12649 | (leu:DI (match_dup 1) (match_dup 2)))] |
12650 | "TARGET_POWERPC64" | |
9ebbca7d GK |
12651 | "@ |
12652 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
12653 | #" | |
f9562f27 | 12654 | [(set_attr "type" "compare") |
9ebbca7d | 12655 | (set_attr "length" "12,16")]) |
f9562f27 | 12656 | |
1fd4e8c1 | 12657 | (define_insn "" |
80103f96 | 12658 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12659 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12660 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
80103f96 | 12661 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
f9562f27 | 12662 | "! TARGET_POWERPC64" |
80103f96 | 12663 | "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 12664 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12665 | |
12666 | (define_insn "" | |
9ebbca7d | 12667 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12668 | (compare:CC |
9ebbca7d GK |
12669 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12670 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12671 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12672 | (const_int 0))) |
9ebbca7d | 12673 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 12674 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12675 | "@ |
12676 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
12677 | #" | |
b19003d8 | 12678 | [(set_attr "type" "compare") |
9ebbca7d GK |
12679 | (set_attr "length" "8,12")]) |
12680 | ||
12681 | (define_split | |
12682 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12683 | (compare:CC | |
12684 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12685 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12686 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12687 | (const_int 0))) | |
12688 | (clobber (match_scratch:SI 4 ""))] | |
12689 | "! TARGET_POWERPC64 && reload_completed" | |
12690 | [(set (match_dup 4) | |
12691 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
12692 | (match_dup 3))) | |
12693 | (set (match_dup 0) | |
12694 | (compare:CC (match_dup 4) | |
12695 | (const_int 0)))] | |
12696 | "") | |
1fd4e8c1 RK |
12697 | |
12698 | (define_insn "" | |
097657c3 | 12699 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12700 | (compare:CC |
9ebbca7d GK |
12701 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12702 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12703 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12704 | (const_int 0))) |
097657c3 AM |
12705 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12706 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 12707 | "! TARGET_POWERPC64" |
9ebbca7d | 12708 | "@ |
097657c3 | 12709 | {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 |
9ebbca7d | 12710 | #" |
b19003d8 | 12711 | [(set_attr "type" "compare") |
9ebbca7d GK |
12712 | (set_attr "length" "8,12")]) |
12713 | ||
12714 | (define_split | |
097657c3 | 12715 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12716 | (compare:CC |
12717 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12718 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12719 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12720 | (const_int 0))) | |
12721 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12722 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12723 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 12724 | [(set (match_dup 0) |
9ebbca7d | 12725 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12726 | (set (match_dup 4) |
9ebbca7d GK |
12727 | (compare:CC (match_dup 0) |
12728 | (const_int 0)))] | |
12729 | "") | |
1fd4e8c1 RK |
12730 | |
12731 | (define_insn "" | |
cd2b37d9 RK |
12732 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12733 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12734 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 12735 | "! TARGET_POWERPC64" |
ca7f5001 | 12736 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 12737 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12738 | |
12739 | (define_insn "" | |
097657c3 | 12740 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
1fd4e8c1 | 12741 | (and:SI (neg:SI |
cd2b37d9 | 12742 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12743 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
097657c3 | 12744 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
f9562f27 | 12745 | "! TARGET_POWERPC64" |
097657c3 | 12746 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" |
b19003d8 | 12747 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12748 | |
12749 | (define_insn "" | |
9ebbca7d | 12750 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12751 | (compare:CC |
12752 | (and:SI (neg:SI | |
9ebbca7d GK |
12753 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12754 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12755 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12756 | (const_int 0))) |
9ebbca7d | 12757 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 12758 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12759 | "@ |
12760 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
12761 | #" | |
12762 | [(set_attr "type" "compare") | |
12763 | (set_attr "length" "12,16")]) | |
12764 | ||
12765 | (define_split | |
12766 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12767 | (compare:CC | |
12768 | (and:SI (neg:SI | |
12769 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12770 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12771 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12772 | (const_int 0))) | |
12773 | (clobber (match_scratch:SI 4 ""))] | |
12774 | "! TARGET_POWERPC64 && reload_completed" | |
12775 | [(set (match_dup 4) | |
097657c3 AM |
12776 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) |
12777 | (match_dup 3))) | |
9ebbca7d GK |
12778 | (set (match_dup 0) |
12779 | (compare:CC (match_dup 4) | |
12780 | (const_int 0)))] | |
12781 | "") | |
1fd4e8c1 RK |
12782 | |
12783 | (define_insn "" | |
097657c3 | 12784 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12785 | (compare:CC |
12786 | (and:SI (neg:SI | |
9ebbca7d GK |
12787 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12788 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12789 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12790 | (const_int 0))) |
097657c3 AM |
12791 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12792 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
f9562f27 | 12793 | "! TARGET_POWERPC64" |
9ebbca7d | 12794 | "@ |
097657c3 | 12795 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
9ebbca7d | 12796 | #" |
b19003d8 | 12797 | [(set_attr "type" "compare") |
9ebbca7d GK |
12798 | (set_attr "length" "12,16")]) |
12799 | ||
12800 | (define_split | |
097657c3 | 12801 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12802 | (compare:CC |
12803 | (and:SI (neg:SI | |
12804 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12805 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12806 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12807 | (const_int 0))) | |
12808 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12809 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
9ebbca7d | 12810 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 AM |
12811 | [(set (match_dup 0) |
12812 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) | |
12813 | (match_dup 3))) | |
12814 | (set (match_dup 4) | |
9ebbca7d GK |
12815 | (compare:CC (match_dup 0) |
12816 | (const_int 0)))] | |
12817 | "") | |
1fd4e8c1 RK |
12818 | |
12819 | (define_insn "" | |
cd2b37d9 RK |
12820 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12821 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12822 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 12823 | "TARGET_POWER" |
7f340546 | 12824 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12825 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12826 | |
12827 | (define_insn "" | |
9ebbca7d | 12828 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12829 | (compare:CC |
9ebbca7d GK |
12830 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12831 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12832 | (const_int 0))) |
9ebbca7d | 12833 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12834 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12835 | "TARGET_POWER" |
9ebbca7d GK |
12836 | "@ |
12837 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12838 | #" | |
29ae5b89 | 12839 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12840 | (set_attr "length" "12,16")]) |
12841 | ||
12842 | (define_split | |
12843 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12844 | (compare:CC | |
12845 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12846 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12847 | (const_int 0))) | |
12848 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12849 | (lt:SI (match_dup 1) (match_dup 2)))] | |
12850 | "TARGET_POWER && reload_completed" | |
12851 | [(set (match_dup 0) | |
12852 | (lt:SI (match_dup 1) (match_dup 2))) | |
12853 | (set (match_dup 3) | |
12854 | (compare:CC (match_dup 0) | |
12855 | (const_int 0)))] | |
12856 | "") | |
1fd4e8c1 RK |
12857 | |
12858 | (define_insn "" | |
097657c3 | 12859 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12860 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12861 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12862 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12863 | "TARGET_POWER" |
097657c3 | 12864 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 12865 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12866 | |
12867 | (define_insn "" | |
9ebbca7d | 12868 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12869 | (compare:CC |
9ebbca7d GK |
12870 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12871 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12872 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12873 | (const_int 0))) |
9ebbca7d | 12874 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12875 | "TARGET_POWER" |
9ebbca7d GK |
12876 | "@ |
12877 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12878 | #" | |
b19003d8 | 12879 | [(set_attr "type" "compare") |
9ebbca7d GK |
12880 | (set_attr "length" "12,16")]) |
12881 | ||
12882 | (define_split | |
12883 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12884 | (compare:CC | |
12885 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12886 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12887 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12888 | (const_int 0))) | |
12889 | (clobber (match_scratch:SI 4 ""))] | |
12890 | "TARGET_POWER && reload_completed" | |
12891 | [(set (match_dup 4) | |
12892 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12893 | (match_dup 3))) |
9ebbca7d GK |
12894 | (set (match_dup 0) |
12895 | (compare:CC (match_dup 4) | |
12896 | (const_int 0)))] | |
12897 | "") | |
1fd4e8c1 RK |
12898 | |
12899 | (define_insn "" | |
097657c3 | 12900 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12901 | (compare:CC |
9ebbca7d GK |
12902 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12903 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12904 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12905 | (const_int 0))) |
097657c3 AM |
12906 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12907 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12908 | "TARGET_POWER" |
9ebbca7d | 12909 | "@ |
097657c3 | 12910 | doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 12911 | #" |
b19003d8 | 12912 | [(set_attr "type" "compare") |
9ebbca7d GK |
12913 | (set_attr "length" "12,16")]) |
12914 | ||
12915 | (define_split | |
097657c3 | 12916 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12917 | (compare:CC |
12918 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12919 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12920 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12921 | (const_int 0))) | |
12922 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12923 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12924 | "TARGET_POWER && reload_completed" |
097657c3 | 12925 | [(set (match_dup 0) |
9ebbca7d | 12926 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12927 | (set (match_dup 4) |
9ebbca7d GK |
12928 | (compare:CC (match_dup 0) |
12929 | (const_int 0)))] | |
12930 | "") | |
1fd4e8c1 RK |
12931 | |
12932 | (define_insn "" | |
cd2b37d9 RK |
12933 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12934 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12935 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12936 | "TARGET_POWER" |
12937 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12938 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12939 | |
12940 | (define_insn "" | |
cd2b37d9 RK |
12941 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12942 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12943 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 12944 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12945 | "@ |
ca7f5001 RK |
12946 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
12947 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 12948 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12949 | |
12950 | (define_insn "" | |
9ebbca7d | 12951 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12952 | (compare:CC |
9ebbca7d GK |
12953 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12954 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12955 | (const_int 0))) |
9ebbca7d | 12956 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12957 | (ltu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 12958 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12959 | "@ |
ca7f5001 | 12960 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
12961 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
12962 | # | |
12963 | #" | |
b19003d8 | 12964 | [(set_attr "type" "compare") |
9ebbca7d GK |
12965 | (set_attr "length" "12,12,16,16")]) |
12966 | ||
12967 | (define_split | |
12968 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12969 | (compare:CC | |
12970 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12971 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12972 | (const_int 0))) | |
12973 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12974 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
12975 | "! TARGET_POWERPC64 && reload_completed" | |
12976 | [(set (match_dup 0) | |
12977 | (ltu:SI (match_dup 1) (match_dup 2))) | |
12978 | (set (match_dup 3) | |
12979 | (compare:CC (match_dup 0) | |
12980 | (const_int 0)))] | |
12981 | "") | |
1fd4e8c1 RK |
12982 | |
12983 | (define_insn "" | |
80103f96 | 12984 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
19378cf8 MM |
12985 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12986 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
80103f96 | 12987 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))] |
f9562f27 | 12988 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12989 | "@ |
80103f96 FS |
12990 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3 |
12991 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" | |
b19003d8 | 12992 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12993 | |
12994 | (define_insn "" | |
9ebbca7d | 12995 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12996 | (compare:CC |
9ebbca7d GK |
12997 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12998 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12999 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13000 | (const_int 0))) |
9ebbca7d | 13001 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 13002 | "! TARGET_POWERPC64" |
1fd4e8c1 | 13003 | "@ |
ca7f5001 | 13004 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
9ebbca7d GK |
13005 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
13006 | # | |
13007 | #" | |
b19003d8 | 13008 | [(set_attr "type" "compare") |
9ebbca7d GK |
13009 | (set_attr "length" "12,12,16,16")]) |
13010 | ||
13011 | (define_split | |
13012 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13013 | (compare:CC | |
13014 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13015 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
13016 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13017 | (const_int 0))) | |
13018 | (clobber (match_scratch:SI 4 ""))] | |
13019 | "! TARGET_POWERPC64 && reload_completed" | |
13020 | [(set (match_dup 4) | |
13021 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 13022 | (match_dup 3))) |
9ebbca7d GK |
13023 | (set (match_dup 0) |
13024 | (compare:CC (match_dup 4) | |
13025 | (const_int 0)))] | |
13026 | "") | |
1fd4e8c1 RK |
13027 | |
13028 | (define_insn "" | |
097657c3 | 13029 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13030 | (compare:CC |
9ebbca7d GK |
13031 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13032 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
13033 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13034 | (const_int 0))) |
097657c3 AM |
13035 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13036 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 13037 | "! TARGET_POWERPC64" |
1fd4e8c1 | 13038 | "@ |
097657c3 AM |
13039 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 |
13040 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 | |
9ebbca7d GK |
13041 | # |
13042 | #" | |
b19003d8 | 13043 | [(set_attr "type" "compare") |
9ebbca7d GK |
13044 | (set_attr "length" "12,12,16,16")]) |
13045 | ||
13046 | (define_split | |
097657c3 | 13047 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13048 | (compare:CC |
13049 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13050 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
13051 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13052 | (const_int 0))) | |
13053 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13054 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13055 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 13056 | [(set (match_dup 0) |
9ebbca7d | 13057 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13058 | (set (match_dup 4) |
9ebbca7d GK |
13059 | (compare:CC (match_dup 0) |
13060 | (const_int 0)))] | |
13061 | "") | |
1fd4e8c1 RK |
13062 | |
13063 | (define_insn "" | |
cd2b37d9 RK |
13064 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
13065 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 13066 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
f9562f27 | 13067 | "! TARGET_POWERPC64" |
1fd4e8c1 | 13068 | "@ |
ca7f5001 RK |
13069 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
13070 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 13071 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
13072 | |
13073 | (define_insn "" | |
cd2b37d9 RK |
13074 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13075 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
13076 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
13077 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
13078 | "TARGET_POWER" |
13079 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 13080 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13081 | |
9ebbca7d GK |
13082 | (define_insn "" |
13083 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 13084 | (compare:CC |
9ebbca7d GK |
13085 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13086 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 13087 | (const_int 0))) |
9ebbca7d | 13088 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13089 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 13090 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 13091 | "TARGET_POWER" |
9ebbca7d GK |
13092 | "@ |
13093 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
13094 | #" | |
13095 | [(set_attr "type" "compare") | |
13096 | (set_attr "length" "12,16")]) | |
13097 | ||
13098 | (define_split | |
13099 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
13100 | (compare:CC | |
13101 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13102 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13103 | (const_int 0))) | |
13104 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13105 | (ge:SI (match_dup 1) (match_dup 2))) | |
13106 | (clobber (match_scratch:SI 3 ""))] | |
13107 | "TARGET_POWER && reload_completed" | |
13108 | [(parallel [(set (match_dup 0) | |
097657c3 AM |
13109 | (ge:SI (match_dup 1) (match_dup 2))) |
13110 | (clobber (match_dup 3))]) | |
9ebbca7d GK |
13111 | (set (match_dup 4) |
13112 | (compare:CC (match_dup 0) | |
13113 | (const_int 0)))] | |
13114 | "") | |
13115 | ||
1fd4e8c1 | 13116 | (define_insn "" |
097657c3 | 13117 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13118 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13119 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 13120 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 13121 | "TARGET_POWER" |
097657c3 | 13122 | "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" |
b19003d8 | 13123 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13124 | |
13125 | (define_insn "" | |
9ebbca7d | 13126 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13127 | (compare:CC |
9ebbca7d GK |
13128 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13129 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
13130 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13131 | (const_int 0))) |
9ebbca7d | 13132 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 13133 | "TARGET_POWER" |
9ebbca7d GK |
13134 | "@ |
13135 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
13136 | #" | |
b19003d8 | 13137 | [(set_attr "type" "compare") |
9ebbca7d GK |
13138 | (set_attr "length" "12,16")]) |
13139 | ||
13140 | (define_split | |
13141 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13142 | (compare:CC | |
13143 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13144 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13145 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13146 | (const_int 0))) | |
13147 | (clobber (match_scratch:SI 4 ""))] | |
13148 | "TARGET_POWER && reload_completed" | |
13149 | [(set (match_dup 4) | |
13150 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 13151 | (match_dup 3))) |
9ebbca7d GK |
13152 | (set (match_dup 0) |
13153 | (compare:CC (match_dup 4) | |
13154 | (const_int 0)))] | |
13155 | "") | |
1fd4e8c1 RK |
13156 | |
13157 | (define_insn "" | |
097657c3 | 13158 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13159 | (compare:CC |
9ebbca7d GK |
13160 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13161 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
13162 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13163 | (const_int 0))) |
097657c3 AM |
13164 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13165 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 13166 | "TARGET_POWER" |
9ebbca7d | 13167 | "@ |
097657c3 | 13168 | doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
9ebbca7d | 13169 | #" |
b19003d8 | 13170 | [(set_attr "type" "compare") |
9ebbca7d GK |
13171 | (set_attr "length" "12,16")]) |
13172 | ||
13173 | (define_split | |
097657c3 | 13174 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13175 | (compare:CC |
13176 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13177 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13178 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13179 | (const_int 0))) | |
13180 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13181 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13182 | "TARGET_POWER && reload_completed" |
097657c3 | 13183 | [(set (match_dup 0) |
9ebbca7d | 13184 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13185 | (set (match_dup 4) |
9ebbca7d GK |
13186 | (compare:CC (match_dup 0) |
13187 | (const_int 0)))] | |
13188 | "") | |
1fd4e8c1 RK |
13189 | |
13190 | (define_insn "" | |
cd2b37d9 RK |
13191 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13192 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13193 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
13194 | "TARGET_POWER" |
13195 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 13196 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13197 | |
1fd4e8c1 | 13198 | (define_insn "" |
cd2b37d9 RK |
13199 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
13200 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 13201 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 13202 | "! TARGET_POWERPC64" |
1fd4e8c1 | 13203 | "@ |
ca7f5001 RK |
13204 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
13205 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 13206 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13207 | |
f9562f27 DE |
13208 | (define_insn "" |
13209 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
13210 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
13211 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
13212 | "TARGET_POWERPC64" | |
13213 | "@ | |
13214 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
13215 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
13216 | [(set_attr "length" "12")]) | |
13217 | ||
1fd4e8c1 | 13218 | (define_insn "" |
9ebbca7d | 13219 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13220 | (compare:CC |
9ebbca7d GK |
13221 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13222 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 13223 | (const_int 0))) |
9ebbca7d | 13224 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 13225 | (geu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 13226 | "! TARGET_POWERPC64" |
1fd4e8c1 | 13227 | "@ |
ca7f5001 | 13228 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
13229 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
13230 | # | |
13231 | #" | |
b19003d8 | 13232 | [(set_attr "type" "compare") |
9ebbca7d GK |
13233 | (set_attr "length" "12,12,16,16")]) |
13234 | ||
13235 | (define_split | |
13236 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13237 | (compare:CC | |
13238 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13239 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
13240 | (const_int 0))) | |
13241 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13242 | (geu:SI (match_dup 1) (match_dup 2)))] | |
13243 | "! TARGET_POWERPC64 && reload_completed" | |
13244 | [(set (match_dup 0) | |
13245 | (geu:SI (match_dup 1) (match_dup 2))) | |
13246 | (set (match_dup 3) | |
13247 | (compare:CC (match_dup 0) | |
13248 | (const_int 0)))] | |
13249 | "") | |
1fd4e8c1 | 13250 | |
f9562f27 | 13251 | (define_insn "" |
9ebbca7d | 13252 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13253 | (compare:CC |
9ebbca7d GK |
13254 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13255 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 13256 | (const_int 0))) |
9ebbca7d | 13257 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 DE |
13258 | (geu:DI (match_dup 1) (match_dup 2)))] |
13259 | "TARGET_POWERPC64" | |
13260 | "@ | |
13261 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
13262 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
13263 | # | |
13264 | #" | |
f9562f27 | 13265 | [(set_attr "type" "compare") |
9ebbca7d GK |
13266 | (set_attr "length" "12,12,16,16")]) |
13267 | ||
13268 | (define_split | |
13269 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13270 | (compare:CC | |
13271 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13272 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
13273 | (const_int 0))) | |
13274 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13275 | (geu:DI (match_dup 1) (match_dup 2)))] | |
13276 | "TARGET_POWERPC64 && reload_completed" | |
13277 | [(set (match_dup 0) | |
13278 | (geu:DI (match_dup 1) (match_dup 2))) | |
13279 | (set (match_dup 3) | |
13280 | (compare:CC (match_dup 0) | |
13281 | (const_int 0)))] | |
13282 | "") | |
f9562f27 | 13283 | |
1fd4e8c1 | 13284 | (define_insn "" |
80103f96 | 13285 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 13286 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 13287 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
80103f96 | 13288 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
f9562f27 | 13289 | "! TARGET_POWERPC64" |
1fd4e8c1 | 13290 | "@ |
80103f96 FS |
13291 | {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 |
13292 | {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 13293 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
13294 | |
13295 | (define_insn "" | |
9ebbca7d | 13296 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13297 | (compare:CC |
9ebbca7d GK |
13298 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13299 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
13300 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13301 | (const_int 0))) |
9ebbca7d | 13302 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 13303 | "! TARGET_POWERPC64" |
1fd4e8c1 | 13304 | "@ |
ca7f5001 | 13305 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
13306 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
13307 | # | |
13308 | #" | |
b19003d8 | 13309 | [(set_attr "type" "compare") |
9ebbca7d GK |
13310 | (set_attr "length" "8,8,12,12")]) |
13311 | ||
13312 | (define_split | |
13313 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13314 | (compare:CC | |
13315 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13316 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
13317 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13318 | (const_int 0))) | |
13319 | (clobber (match_scratch:SI 4 ""))] | |
13320 | "! TARGET_POWERPC64 && reload_completed" | |
13321 | [(set (match_dup 4) | |
13322 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
13323 | (match_dup 3))) | |
13324 | (set (match_dup 0) | |
13325 | (compare:CC (match_dup 4) | |
13326 | (const_int 0)))] | |
13327 | "") | |
1fd4e8c1 RK |
13328 | |
13329 | (define_insn "" | |
097657c3 | 13330 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13331 | (compare:CC |
9ebbca7d GK |
13332 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13333 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
13334 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13335 | (const_int 0))) |
097657c3 AM |
13336 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13337 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 13338 | "! TARGET_POWERPC64" |
1fd4e8c1 | 13339 | "@ |
097657c3 AM |
13340 | {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 |
13341 | {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
13342 | # |
13343 | #" | |
b19003d8 | 13344 | [(set_attr "type" "compare") |
9ebbca7d GK |
13345 | (set_attr "length" "8,8,12,12")]) |
13346 | ||
13347 | (define_split | |
097657c3 | 13348 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13349 | (compare:CC |
13350 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13351 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
13352 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13353 | (const_int 0))) | |
13354 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13355 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13356 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 13357 | [(set (match_dup 0) |
9ebbca7d | 13358 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13359 | (set (match_dup 4) |
9ebbca7d GK |
13360 | (compare:CC (match_dup 0) |
13361 | (const_int 0)))] | |
13362 | "") | |
1fd4e8c1 RK |
13363 | |
13364 | (define_insn "" | |
cd2b37d9 RK |
13365 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
13366 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 13367 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
f9562f27 | 13368 | "! TARGET_POWERPC64" |
1fd4e8c1 | 13369 | "@ |
ca7f5001 | 13370 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 13371 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 13372 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13373 | |
13374 | (define_insn "" | |
097657c3 | 13375 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
1fd4e8c1 | 13376 | (and:SI (neg:SI |
cd2b37d9 | 13377 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 13378 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
097657c3 | 13379 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
f9562f27 | 13380 | "! TARGET_POWERPC64" |
1fd4e8c1 | 13381 | "@ |
097657c3 AM |
13382 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 |
13383 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" | |
b19003d8 | 13384 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13385 | |
13386 | (define_insn "" | |
9ebbca7d | 13387 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
13388 | (compare:CC |
13389 | (and:SI (neg:SI | |
9ebbca7d GK |
13390 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13391 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
13392 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13393 | (const_int 0))) |
9ebbca7d | 13394 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 13395 | "! TARGET_POWERPC64" |
1fd4e8c1 | 13396 | "@ |
ca7f5001 | 13397 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
13398 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
13399 | # | |
13400 | #" | |
b19003d8 | 13401 | [(set_attr "type" "compare") |
9ebbca7d GK |
13402 | (set_attr "length" "12,12,16,16")]) |
13403 | ||
13404 | (define_split | |
13405 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13406 | (compare:CC | |
13407 | (and:SI (neg:SI | |
13408 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13409 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
13410 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13411 | (const_int 0))) | |
13412 | (clobber (match_scratch:SI 4 ""))] | |
13413 | "! TARGET_POWERPC64 && reload_completed" | |
13414 | [(set (match_dup 4) | |
097657c3 AM |
13415 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) |
13416 | (match_dup 3))) | |
9ebbca7d GK |
13417 | (set (match_dup 0) |
13418 | (compare:CC (match_dup 4) | |
13419 | (const_int 0)))] | |
13420 | "") | |
1fd4e8c1 RK |
13421 | |
13422 | (define_insn "" | |
097657c3 | 13423 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
13424 | (compare:CC |
13425 | (and:SI (neg:SI | |
9ebbca7d GK |
13426 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13427 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
13428 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13429 | (const_int 0))) |
097657c3 AM |
13430 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13431 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
f9562f27 | 13432 | "! TARGET_POWERPC64" |
1fd4e8c1 | 13433 | "@ |
097657c3 AM |
13434 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
13435 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 | |
9ebbca7d GK |
13436 | # |
13437 | #" | |
b19003d8 | 13438 | [(set_attr "type" "compare") |
9ebbca7d GK |
13439 | (set_attr "length" "12,12,16,16")]) |
13440 | ||
13441 | (define_split | |
097657c3 | 13442 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13443 | (compare:CC |
13444 | (and:SI (neg:SI | |
13445 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13446 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
13447 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13448 | (const_int 0))) | |
13449 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13450 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
9ebbca7d | 13451 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 13452 | [(set (match_dup 0) |
9ebbca7d | 13453 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
097657c3 | 13454 | (set (match_dup 4) |
9ebbca7d GK |
13455 | (compare:CC (match_dup 0) |
13456 | (const_int 0)))] | |
13457 | "") | |
1fd4e8c1 RK |
13458 | |
13459 | (define_insn "" | |
cd2b37d9 RK |
13460 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13461 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13462 | (const_int 0)))] |
f9562f27 | 13463 | "! TARGET_POWERPC64" |
ca7f5001 | 13464 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 13465 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13466 | |
f9562f27 DE |
13467 | (define_insn "" |
13468 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13469 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13470 | (const_int 0)))] | |
13471 | "TARGET_POWERPC64" | |
13472 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" | |
13473 | [(set_attr "length" "12")]) | |
13474 | ||
1fd4e8c1 | 13475 | (define_insn "" |
9ebbca7d | 13476 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13477 | (compare:CC |
9ebbca7d | 13478 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
13479 | (const_int 0)) |
13480 | (const_int 0))) | |
9ebbca7d | 13481 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13482 | (gt:SI (match_dup 1) (const_int 0)))] |
f9562f27 | 13483 | "! TARGET_POWERPC64" |
9ebbca7d GK |
13484 | "@ |
13485 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
13486 | #" | |
29ae5b89 | 13487 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13488 | (set_attr "length" "12,16")]) |
13489 | ||
13490 | (define_split | |
13491 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
13492 | (compare:CC | |
13493 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13494 | (const_int 0)) | |
13495 | (const_int 0))) | |
13496 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13497 | (gt:SI (match_dup 1) (const_int 0)))] | |
13498 | "! TARGET_POWERPC64 && reload_completed" | |
13499 | [(set (match_dup 0) | |
13500 | (gt:SI (match_dup 1) (const_int 0))) | |
13501 | (set (match_dup 2) | |
13502 | (compare:CC (match_dup 0) | |
13503 | (const_int 0)))] | |
13504 | "") | |
1fd4e8c1 | 13505 | |
f9562f27 | 13506 | (define_insn "" |
9ebbca7d | 13507 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 13508 | (compare:CC |
9ebbca7d | 13509 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
13510 | (const_int 0)) |
13511 | (const_int 0))) | |
9ebbca7d | 13512 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
13513 | (gt:DI (match_dup 1) (const_int 0)))] |
13514 | "TARGET_POWERPC64" | |
9ebbca7d GK |
13515 | "@ |
13516 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
13517 | #" | |
f9562f27 | 13518 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13519 | (set_attr "length" "12,16")]) |
13520 | ||
13521 | (define_split | |
13522 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
13523 | (compare:CC | |
13524 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13525 | (const_int 0)) | |
13526 | (const_int 0))) | |
13527 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13528 | (gt:DI (match_dup 1) (const_int 0)))] | |
13529 | "TARGET_POWERPC64 && reload_completed" | |
13530 | [(set (match_dup 0) | |
13531 | (gt:DI (match_dup 1) (const_int 0))) | |
13532 | (set (match_dup 2) | |
13533 | (compare:CC (match_dup 0) | |
13534 | (const_int 0)))] | |
13535 | "") | |
f9562f27 | 13536 | |
1fd4e8c1 | 13537 | (define_insn "" |
cd2b37d9 RK |
13538 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13539 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13540 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
13541 | "TARGET_POWER" |
13542 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 13543 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13544 | |
13545 | (define_insn "" | |
9ebbca7d | 13546 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13547 | (compare:CC |
9ebbca7d GK |
13548 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13549 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 13550 | (const_int 0))) |
9ebbca7d | 13551 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13552 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 13553 | "TARGET_POWER" |
9ebbca7d GK |
13554 | "@ |
13555 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
13556 | #" | |
29ae5b89 | 13557 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13558 | (set_attr "length" "12,16")]) |
13559 | ||
13560 | (define_split | |
13561 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13562 | (compare:CC | |
13563 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13564 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13565 | (const_int 0))) | |
13566 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13567 | (gt:SI (match_dup 1) (match_dup 2)))] | |
13568 | "TARGET_POWER && reload_completed" | |
13569 | [(set (match_dup 0) | |
13570 | (gt:SI (match_dup 1) (match_dup 2))) | |
13571 | (set (match_dup 3) | |
13572 | (compare:CC (match_dup 0) | |
13573 | (const_int 0)))] | |
13574 | "") | |
1fd4e8c1 RK |
13575 | |
13576 | (define_insn "" | |
80103f96 | 13577 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13578 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13579 | (const_int 0)) |
80103f96 | 13580 | (match_operand:SI 2 "gpc_reg_operand" "r")))] |
f9562f27 | 13581 | "! TARGET_POWERPC64" |
80103f96 | 13582 | "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" |
b19003d8 | 13583 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13584 | |
f9562f27 | 13585 | (define_insn "" |
097657c3 | 13586 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
f9562f27 DE |
13587 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
13588 | (const_int 0)) | |
097657c3 | 13589 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
f9562f27 | 13590 | "TARGET_POWERPC64" |
097657c3 | 13591 | "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" |
f9562f27 DE |
13592 | [(set_attr "length" "12")]) |
13593 | ||
1fd4e8c1 | 13594 | (define_insn "" |
9ebbca7d | 13595 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13596 | (compare:CC |
9ebbca7d | 13597 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 13598 | (const_int 0)) |
9ebbca7d | 13599 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 13600 | (const_int 0))) |
9ebbca7d | 13601 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 13602 | "! TARGET_POWERPC64" |
9ebbca7d GK |
13603 | "@ |
13604 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
13605 | #" | |
b19003d8 | 13606 | [(set_attr "type" "compare") |
9ebbca7d GK |
13607 | (set_attr "length" "12,16")]) |
13608 | ||
13609 | (define_split | |
13610 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13611 | (compare:CC | |
13612 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13613 | (const_int 0)) | |
13614 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
13615 | (const_int 0))) | |
13616 | (clobber (match_scratch:SI 3 ""))] | |
13617 | "! TARGET_POWERPC64 && reload_completed" | |
13618 | [(set (match_dup 3) | |
13619 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
13620 | (match_dup 2))) | |
13621 | (set (match_dup 0) | |
13622 | (compare:CC (match_dup 3) | |
13623 | (const_int 0)))] | |
13624 | "") | |
1fd4e8c1 | 13625 | |
f9562f27 | 13626 | (define_insn "" |
9ebbca7d | 13627 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 13628 | (compare:CC |
9ebbca7d | 13629 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13630 | (const_int 0)) |
9ebbca7d | 13631 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13632 | (const_int 0))) |
9ebbca7d | 13633 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 13634 | "TARGET_POWERPC64" |
9ebbca7d GK |
13635 | "@ |
13636 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
13637 | #" | |
f9562f27 | 13638 | [(set_attr "type" "compare") |
9ebbca7d GK |
13639 | (set_attr "length" "12,16")]) |
13640 | ||
13641 | (define_split | |
13642 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13643 | (compare:CC | |
13644 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13645 | (const_int 0)) | |
13646 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13647 | (const_int 0))) | |
13648 | (clobber (match_scratch:DI 3 ""))] | |
13649 | "TARGET_POWERPC64 && reload_completed" | |
13650 | [(set (match_dup 3) | |
13651 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
097657c3 | 13652 | (match_dup 2))) |
9ebbca7d GK |
13653 | (set (match_dup 0) |
13654 | (compare:CC (match_dup 3) | |
13655 | (const_int 0)))] | |
13656 | "") | |
f9562f27 | 13657 | |
1fd4e8c1 | 13658 | (define_insn "" |
097657c3 | 13659 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
9ebbca7d GK |
13660 | (compare:CC |
13661 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
13662 | (const_int 0)) | |
13663 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
13664 | (const_int 0))) | |
097657c3 AM |
13665 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13666 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
9ebbca7d GK |
13667 | "! TARGET_POWERPC64" |
13668 | "@ | |
097657c3 | 13669 | {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 |
9ebbca7d GK |
13670 | #" |
13671 | [(set_attr "type" "compare") | |
13672 | (set_attr "length" "12,16")]) | |
13673 | ||
13674 | (define_split | |
097657c3 | 13675 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
1fd4e8c1 | 13676 | (compare:CC |
9ebbca7d | 13677 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 13678 | (const_int 0)) |
9ebbca7d | 13679 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 13680 | (const_int 0))) |
9ebbca7d | 13681 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
097657c3 | 13682 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] |
9ebbca7d | 13683 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 13684 | [(set (match_dup 0) |
9ebbca7d | 13685 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13686 | (set (match_dup 3) |
9ebbca7d GK |
13687 | (compare:CC (match_dup 0) |
13688 | (const_int 0)))] | |
13689 | "") | |
1fd4e8c1 | 13690 | |
f9562f27 | 13691 | (define_insn "" |
097657c3 | 13692 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13693 | (compare:CC |
9ebbca7d | 13694 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13695 | (const_int 0)) |
9ebbca7d | 13696 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13697 | (const_int 0))) |
097657c3 AM |
13698 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
13699 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
f9562f27 | 13700 | "TARGET_POWERPC64" |
9ebbca7d | 13701 | "@ |
097657c3 | 13702 | addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 |
9ebbca7d | 13703 | #" |
f9562f27 | 13704 | [(set_attr "type" "compare") |
9ebbca7d GK |
13705 | (set_attr "length" "12,16")]) |
13706 | ||
13707 | (define_split | |
097657c3 | 13708 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13709 | (compare:CC |
13710 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13711 | (const_int 0)) | |
13712 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13713 | (const_int 0))) | |
13714 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13715 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] |
9ebbca7d | 13716 | "TARGET_POWERPC64 && reload_completed" |
097657c3 | 13717 | [(set (match_dup 0) |
9ebbca7d | 13718 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13719 | (set (match_dup 3) |
9ebbca7d GK |
13720 | (compare:CC (match_dup 0) |
13721 | (const_int 0)))] | |
13722 | "") | |
f9562f27 | 13723 | |
1fd4e8c1 | 13724 | (define_insn "" |
097657c3 | 13725 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13726 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13727 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
097657c3 | 13728 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 13729 | "TARGET_POWER" |
097657c3 | 13730 | "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 13731 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13732 | |
13733 | (define_insn "" | |
9ebbca7d | 13734 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13735 | (compare:CC |
9ebbca7d GK |
13736 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13737 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13738 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13739 | (const_int 0))) |
9ebbca7d | 13740 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 13741 | "TARGET_POWER" |
9ebbca7d GK |
13742 | "@ |
13743 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
13744 | #" | |
b19003d8 | 13745 | [(set_attr "type" "compare") |
9ebbca7d GK |
13746 | (set_attr "length" "12,16")]) |
13747 | ||
13748 | (define_split | |
13749 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13750 | (compare:CC | |
13751 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13752 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13753 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13754 | (const_int 0))) | |
13755 | (clobber (match_scratch:SI 4 ""))] | |
13756 | "TARGET_POWER && reload_completed" | |
13757 | [(set (match_dup 4) | |
097657c3 | 13758 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d GK |
13759 | (set (match_dup 0) |
13760 | (compare:CC (match_dup 4) | |
13761 | (const_int 0)))] | |
13762 | "") | |
1fd4e8c1 RK |
13763 | |
13764 | (define_insn "" | |
097657c3 | 13765 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13766 | (compare:CC |
9ebbca7d GK |
13767 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13768 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13769 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13770 | (const_int 0))) |
097657c3 AM |
13771 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13772 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 13773 | "TARGET_POWER" |
9ebbca7d | 13774 | "@ |
097657c3 | 13775 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 13776 | #" |
b19003d8 | 13777 | [(set_attr "type" "compare") |
9ebbca7d GK |
13778 | (set_attr "length" "12,16")]) |
13779 | ||
13780 | (define_split | |
097657c3 | 13781 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13782 | (compare:CC |
13783 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13784 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13785 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13786 | (const_int 0))) | |
13787 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13788 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13789 | "TARGET_POWER && reload_completed" |
097657c3 | 13790 | [(set (match_dup 0) |
9ebbca7d | 13791 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13792 | (set (match_dup 4) |
9ebbca7d GK |
13793 | (compare:CC (match_dup 0) |
13794 | (const_int 0)))] | |
13795 | "") | |
1fd4e8c1 RK |
13796 | |
13797 | (define_insn "" | |
cd2b37d9 RK |
13798 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13799 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13800 | (const_int 0))))] |
f9562f27 | 13801 | "! TARGET_POWERPC64" |
ca7f5001 | 13802 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 13803 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13804 | |
f9562f27 DE |
13805 | (define_insn "" |
13806 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13807 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13808 | (const_int 0))))] | |
13809 | "TARGET_POWERPC64" | |
8377288b | 13810 | "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63" |
f9562f27 DE |
13811 | [(set_attr "length" "12")]) |
13812 | ||
1fd4e8c1 | 13813 | (define_insn "" |
cd2b37d9 RK |
13814 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13815 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13816 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
13817 | "TARGET_POWER" |
13818 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 13819 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13820 | |
13821 | (define_insn "" | |
cd2b37d9 RK |
13822 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13823 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13824 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 13825 | "! TARGET_POWERPC64" |
ca7f5001 | 13826 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 13827 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13828 | |
f9562f27 DE |
13829 | (define_insn "" |
13830 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13831 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13832 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
13833 | "TARGET_POWERPC64" | |
13834 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0" | |
13835 | [(set_attr "length" "12")]) | |
13836 | ||
1fd4e8c1 | 13837 | (define_insn "" |
9ebbca7d | 13838 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13839 | (compare:CC |
9ebbca7d GK |
13840 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13841 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 13842 | (const_int 0))) |
9ebbca7d | 13843 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13844 | (gtu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 13845 | "! TARGET_POWERPC64" |
9ebbca7d GK |
13846 | "@ |
13847 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
13848 | #" | |
b19003d8 | 13849 | [(set_attr "type" "compare") |
9ebbca7d GK |
13850 | (set_attr "length" "12,16")]) |
13851 | ||
13852 | (define_split | |
13853 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13854 | (compare:CC | |
13855 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13856 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13857 | (const_int 0))) | |
13858 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13859 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
13860 | "! TARGET_POWERPC64 && reload_completed" | |
13861 | [(set (match_dup 0) | |
13862 | (gtu:SI (match_dup 1) (match_dup 2))) | |
13863 | (set (match_dup 3) | |
13864 | (compare:CC (match_dup 0) | |
13865 | (const_int 0)))] | |
13866 | "") | |
1fd4e8c1 | 13867 | |
f9562f27 | 13868 | (define_insn "" |
9ebbca7d | 13869 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13870 | (compare:CC |
9ebbca7d GK |
13871 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13872 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 13873 | (const_int 0))) |
9ebbca7d | 13874 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
13875 | (gtu:DI (match_dup 1) (match_dup 2)))] |
13876 | "TARGET_POWERPC64" | |
9ebbca7d GK |
13877 | "@ |
13878 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
13879 | #" | |
f9562f27 | 13880 | [(set_attr "type" "compare") |
9ebbca7d GK |
13881 | (set_attr "length" "12,16")]) |
13882 | ||
13883 | (define_split | |
13884 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13885 | (compare:CC | |
13886 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13887 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13888 | (const_int 0))) | |
13889 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13890 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
13891 | "TARGET_POWERPC64 && reload_completed" | |
13892 | [(set (match_dup 0) | |
13893 | (gtu:DI (match_dup 1) (match_dup 2))) | |
13894 | (set (match_dup 3) | |
13895 | (compare:CC (match_dup 0) | |
13896 | (const_int 0)))] | |
13897 | "") | |
f9562f27 | 13898 | |
1fd4e8c1 | 13899 | (define_insn "" |
80103f96 | 13900 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
19378cf8 MM |
13901 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13902 | (match_operand:SI 2 "reg_or_short_operand" "I,rI")) | |
80103f96 | 13903 | (match_operand:SI 3 "reg_or_short_operand" "r,rI")))] |
f9562f27 | 13904 | "! TARGET_POWERPC64" |
00751805 | 13905 | "@ |
80103f96 FS |
13906 | {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3 |
13907 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" | |
19378cf8 | 13908 | [(set_attr "length" "8,12")]) |
1fd4e8c1 | 13909 | |
f9562f27 | 13910 | (define_insn "" |
097657c3 | 13911 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
f9562f27 DE |
13912 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13913 | (match_operand:DI 2 "reg_or_short_operand" "I,rI")) | |
097657c3 | 13914 | (match_operand:DI 3 "reg_or_short_operand" "r,rI")))] |
f9562f27 DE |
13915 | "TARGET_POWERPC64" |
13916 | "@ | |
097657c3 AM |
13917 | addic %0,%1,%k2\;addze %0,%3 |
13918 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3" | |
f9562f27 DE |
13919 | [(set_attr "length" "8,12")]) |
13920 | ||
1fd4e8c1 | 13921 | (define_insn "" |
9ebbca7d | 13922 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13923 | (compare:CC |
9ebbca7d GK |
13924 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13925 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13926 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13927 | (const_int 0))) |
9ebbca7d | 13928 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 13929 | "! TARGET_POWERPC64" |
00751805 | 13930 | "@ |
19378cf8 | 13931 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
13932 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
13933 | # | |
13934 | #" | |
b19003d8 | 13935 | [(set_attr "type" "compare") |
9ebbca7d GK |
13936 | (set_attr "length" "8,12,12,16")]) |
13937 | ||
13938 | (define_split | |
13939 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13940 | (compare:CC | |
13941 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13942 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13943 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13944 | (const_int 0))) | |
13945 | (clobber (match_scratch:SI 4 ""))] | |
13946 | "! TARGET_POWERPC64 && reload_completed" | |
13947 | [(set (match_dup 4) | |
13948 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 13949 | (match_dup 3))) |
9ebbca7d GK |
13950 | (set (match_dup 0) |
13951 | (compare:CC (match_dup 4) | |
13952 | (const_int 0)))] | |
13953 | "") | |
1fd4e8c1 | 13954 | |
f9562f27 | 13955 | (define_insn "" |
9ebbca7d | 13956 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13957 | (compare:CC |
9ebbca7d GK |
13958 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13959 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13960 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13961 | (const_int 0))) |
9ebbca7d | 13962 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
13963 | "TARGET_POWERPC64" |
13964 | "@ | |
13965 | addic %4,%1,%k2\;addze. %4,%3 | |
9ebbca7d GK |
13966 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3 |
13967 | # | |
13968 | #" | |
f9562f27 | 13969 | [(set_attr "type" "compare") |
9ebbca7d GK |
13970 | (set_attr "length" "8,12,12,16")]) |
13971 | ||
13972 | (define_split | |
13973 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13974 | (compare:CC | |
13975 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13976 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13977 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13978 | (const_int 0))) | |
13979 | (clobber (match_scratch:DI 4 ""))] | |
13980 | "TARGET_POWERPC64 && reload_completed" | |
13981 | [(set (match_dup 4) | |
13982 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
13983 | (match_dup 3))) | |
13984 | (set (match_dup 0) | |
13985 | (compare:CC (match_dup 4) | |
13986 | (const_int 0)))] | |
13987 | "") | |
f9562f27 | 13988 | |
1fd4e8c1 | 13989 | (define_insn "" |
097657c3 | 13990 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13991 | (compare:CC |
9ebbca7d GK |
13992 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13993 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13994 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13995 | (const_int 0))) |
097657c3 AM |
13996 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13997 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 13998 | "! TARGET_POWERPC64" |
00751805 | 13999 | "@ |
097657c3 AM |
14000 | {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 |
14001 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 | |
9ebbca7d GK |
14002 | # |
14003 | #" | |
b19003d8 | 14004 | [(set_attr "type" "compare") |
9ebbca7d GK |
14005 | (set_attr "length" "8,12,12,16")]) |
14006 | ||
14007 | (define_split | |
097657c3 | 14008 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
14009 | (compare:CC |
14010 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
14011 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
14012 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
14013 | (const_int 0))) | |
14014 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 14015 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 14016 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 14017 | [(set (match_dup 0) |
9ebbca7d | 14018 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 14019 | (set (match_dup 4) |
9ebbca7d GK |
14020 | (compare:CC (match_dup 0) |
14021 | (const_int 0)))] | |
14022 | "") | |
1fd4e8c1 | 14023 | |
f9562f27 | 14024 | (define_insn "" |
097657c3 | 14025 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 14026 | (compare:CC |
9ebbca7d GK |
14027 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
14028 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
14029 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 14030 | (const_int 0))) |
097657c3 AM |
14031 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
14032 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 DE |
14033 | "TARGET_POWERPC64" |
14034 | "@ | |
097657c3 AM |
14035 | addic %0,%1,%k2\;addze. %0,%3 |
14036 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3 | |
9ebbca7d GK |
14037 | # |
14038 | #" | |
f9562f27 | 14039 | [(set_attr "type" "compare") |
9ebbca7d GK |
14040 | (set_attr "length" "8,12,12,16")]) |
14041 | ||
14042 | (define_split | |
097657c3 | 14043 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
14044 | (compare:CC |
14045 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
14046 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
14047 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
14048 | (const_int 0))) | |
14049 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 14050 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 14051 | "TARGET_POWERPC64 && reload_completed" |
097657c3 | 14052 | [(set (match_dup 0) |
9ebbca7d | 14053 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 14054 | (set (match_dup 4) |
9ebbca7d GK |
14055 | (compare:CC (match_dup 0) |
14056 | (const_int 0)))] | |
14057 | "") | |
f9562f27 | 14058 | |
1fd4e8c1 | 14059 | (define_insn "" |
cd2b37d9 RK |
14060 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
14061 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 14062 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 14063 | "! TARGET_POWERPC64" |
ca7f5001 | 14064 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 14065 | [(set_attr "length" "8")]) |
f9562f27 DE |
14066 | |
14067 | (define_insn "" | |
14068 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
14069 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
14070 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
14071 | "TARGET_POWERPC64" | |
14072 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" | |
14073 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
14074 | \f |
14075 | ;; Define both directions of branch and return. If we need a reload | |
14076 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
14077 | ;; register CC value to there. | |
14078 | ||
14079 | (define_insn "" | |
14080 | [(set (pc) | |
14081 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
14082 | [(match_operand 2 | |
14083 | "cc_reg_operand" "x,?y") | |
14084 | (const_int 0)]) | |
14085 | (label_ref (match_operand 0 "" "")) | |
14086 | (pc)))] | |
14087 | "" | |
b19003d8 RK |
14088 | "* |
14089 | { | |
12a4e8c5 | 14090 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
14091 | }" |
14092 | [(set_attr "type" "branch")]) | |
14093 | ||
1fd4e8c1 RK |
14094 | (define_insn "" |
14095 | [(set (pc) | |
14096 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
14097 | [(match_operand 1 | |
14098 | "cc_reg_operand" "x,?y") | |
14099 | (const_int 0)]) | |
14100 | (return) | |
14101 | (pc)))] | |
14102 | "direct_return ()" | |
12a4e8c5 GK |
14103 | "* |
14104 | { | |
14105 | return output_cbranch (operands[0], NULL, 0, insn); | |
14106 | }" | |
b7ff3d82 | 14107 | [(set_attr "type" "branch") |
39a10a29 | 14108 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
14109 | |
14110 | (define_insn "" | |
14111 | [(set (pc) | |
14112 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
14113 | [(match_operand 2 | |
14114 | "cc_reg_operand" "x,?y") | |
14115 | (const_int 0)]) | |
14116 | (pc) | |
14117 | (label_ref (match_operand 0 "" ""))))] | |
14118 | "" | |
b19003d8 RK |
14119 | "* |
14120 | { | |
12a4e8c5 | 14121 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
14122 | }" |
14123 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
14124 | |
14125 | (define_insn "" | |
14126 | [(set (pc) | |
14127 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
14128 | [(match_operand 1 | |
14129 | "cc_reg_operand" "x,?y") | |
14130 | (const_int 0)]) | |
14131 | (pc) | |
14132 | (return)))] | |
14133 | "direct_return ()" | |
12a4e8c5 GK |
14134 | "* |
14135 | { | |
14136 | return output_cbranch (operands[0], NULL, 1, insn); | |
14137 | }" | |
b7ff3d82 | 14138 | [(set_attr "type" "branch") |
39a10a29 GK |
14139 | (set_attr "length" "4")]) |
14140 | ||
14141 | ;; Logic on condition register values. | |
14142 | ||
14143 | ; This pattern matches things like | |
14144 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
14145 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
14146 | ; (const_int 1))) | |
14147 | ; which are generated by the branch logic. | |
14148 | ||
14149 | (define_insn "" | |
14150 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
14151 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" | |
14152 | [(match_operator:SI 2 | |
14153 | "branch_positive_comparison_operator" | |
14154 | [(match_operand 3 | |
14155 | "cc_reg_operand" "y") | |
14156 | (const_int 0)]) | |
14157 | (match_operator:SI 4 | |
14158 | "branch_positive_comparison_operator" | |
14159 | [(match_operand 5 | |
14160 | "cc_reg_operand" "y") | |
14161 | (const_int 0)])]) | |
14162 | (const_int 1)))] | |
14163 | "" | |
14164 | "cr%q1 %E0,%j2,%j4" | |
14165 | [(set_attr "type" "cr_logical")]) | |
14166 | ||
14167 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
14168 | ; Because ~1 has all but the low bit set. | |
14169 | (define_insn "" | |
14170 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
14171 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" | |
14172 | [(not:SI (match_operator:SI 2 | |
14173 | "branch_positive_comparison_operator" | |
14174 | [(match_operand 3 | |
14175 | "cc_reg_operand" "y") | |
14176 | (const_int 0)])) | |
14177 | (match_operator:SI 4 | |
14178 | "branch_positive_comparison_operator" | |
14179 | [(match_operand 5 | |
14180 | "cc_reg_operand" "y") | |
14181 | (const_int 0)])]) | |
14182 | (const_int -1)))] | |
14183 | "" | |
14184 | "cr%q1 %E0,%j2,%j4" | |
14185 | [(set_attr "type" "cr_logical")]) | |
14186 | ||
14187 | (define_insn "" | |
14188 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
6c873122 | 14189 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 14190 | "branch_positive_comparison_operator" |
6c873122 | 14191 | [(match_operand 2 |
39a10a29 GK |
14192 | "cc_reg_operand" "y") |
14193 | (const_int 0)]) | |
14194 | (const_int 0)))] | |
fe6b547a | 14195 | "!TARGET_SPE" |
251b3667 | 14196 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
39a10a29 GK |
14197 | [(set_attr "type" "cr_logical")]) |
14198 | ||
14199 | ;; If we are comparing the result of two comparisons, this can be done | |
14200 | ;; using creqv or crxor. | |
14201 | ||
14202 | (define_insn_and_split "" | |
14203 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
14204 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
14205 | [(match_operand 2 "cc_reg_operand" "y") | |
14206 | (const_int 0)]) | |
14207 | (match_operator 3 "branch_comparison_operator" | |
14208 | [(match_operand 4 "cc_reg_operand" "y") | |
14209 | (const_int 0)])))] | |
14210 | "" | |
14211 | "#" | |
14212 | "" | |
14213 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
14214 | (match_dup 5)))] | |
14215 | " | |
14216 | { | |
14217 | int positive_1, positive_2; | |
14218 | ||
14219 | positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode); | |
14220 | positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode); | |
14221 | ||
14222 | if (! positive_1) | |
2d4368e6 | 14223 | operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]), |
39a10a29 | 14224 | GET_CODE (operands[1])), |
2d4368e6 DE |
14225 | SImode, |
14226 | operands[2], const0_rtx); | |
39a10a29 | 14227 | else if (GET_MODE (operands[1]) != SImode) |
2d4368e6 DE |
14228 | operands[1] = gen_rtx (GET_CODE (operands[1]), |
14229 | SImode, | |
14230 | operands[2], const0_rtx); | |
39a10a29 GK |
14231 | |
14232 | if (! positive_2) | |
2d4368e6 | 14233 | operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]), |
39a10a29 | 14234 | GET_CODE (operands[3])), |
2d4368e6 DE |
14235 | SImode, |
14236 | operands[4], const0_rtx); | |
39a10a29 | 14237 | else if (GET_MODE (operands[3]) != SImode) |
2d4368e6 DE |
14238 | operands[3] = gen_rtx (GET_CODE (operands[3]), |
14239 | SImode, | |
14240 | operands[4], const0_rtx); | |
39a10a29 GK |
14241 | |
14242 | if (positive_1 == positive_2) | |
251b3667 DE |
14243 | { |
14244 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
14245 | operands[5] = constm1_rtx; | |
14246 | } | |
14247 | else | |
14248 | { | |
14249 | operands[5] = const1_rtx; | |
14250 | } | |
39a10a29 | 14251 | }") |
1fd4e8c1 RK |
14252 | |
14253 | ;; Unconditional branch and return. | |
14254 | ||
14255 | (define_insn "jump" | |
14256 | [(set (pc) | |
14257 | (label_ref (match_operand 0 "" "")))] | |
14258 | "" | |
b7ff3d82 DE |
14259 | "b %l0" |
14260 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
14261 | |
14262 | (define_insn "return" | |
14263 | [(return)] | |
14264 | "direct_return ()" | |
324e52cc TG |
14265 | "{br|blr}" |
14266 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 14267 | |
0ad91047 DE |
14268 | (define_expand "indirect_jump" |
14269 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 14270 | "" |
0ad91047 DE |
14271 | " |
14272 | { | |
14273 | if (TARGET_32BIT) | |
14274 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
14275 | else | |
14276 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
14277 | DONE; | |
14278 | }") | |
14279 | ||
14280 | (define_insn "indirect_jumpsi" | |
b92b324d | 14281 | [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))] |
0ad91047 | 14282 | "TARGET_32BIT" |
b92b324d DE |
14283 | "@ |
14284 | bctr | |
14285 | {br|blr}" | |
324e52cc | 14286 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 14287 | |
0ad91047 | 14288 | (define_insn "indirect_jumpdi" |
b92b324d | 14289 | [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))] |
0ad91047 | 14290 | "TARGET_64BIT" |
b92b324d DE |
14291 | "@ |
14292 | bctr | |
14293 | blr" | |
266eb58a DE |
14294 | [(set_attr "type" "jmpreg")]) |
14295 | ||
1fd4e8c1 RK |
14296 | ;; Table jump for switch statements: |
14297 | (define_expand "tablejump" | |
e6ca2c17 DE |
14298 | [(use (match_operand 0 "" "")) |
14299 | (use (label_ref (match_operand 1 "" "")))] | |
14300 | "" | |
14301 | " | |
14302 | { | |
14303 | if (TARGET_32BIT) | |
14304 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
14305 | else | |
14306 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
14307 | DONE; | |
14308 | }") | |
14309 | ||
14310 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
14311 | [(set (match_dup 3) |
14312 | (plus:SI (match_operand:SI 0 "" "") | |
14313 | (match_dup 2))) | |
14314 | (parallel [(set (pc) (match_dup 3)) | |
14315 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 14316 | "TARGET_32BIT" |
1fd4e8c1 RK |
14317 | " |
14318 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 14319 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
14320 | operands[3] = gen_reg_rtx (SImode); |
14321 | }") | |
14322 | ||
e6ca2c17 | 14323 | (define_expand "tablejumpdi" |
9ebbca7d GK |
14324 | [(set (match_dup 4) |
14325 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) | |
14326 | (set (match_dup 3) | |
14327 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
14328 | (match_dup 2))) |
14329 | (parallel [(set (pc) (match_dup 3)) | |
14330 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 14331 | "TARGET_64BIT" |
e6ca2c17 | 14332 | " |
9ebbca7d | 14333 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 14334 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 14335 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
14336 | }") |
14337 | ||
1fd4e8c1 RK |
14338 | (define_insn "" |
14339 | [(set (pc) | |
c859cda6 | 14340 | (match_operand:SI 0 "register_operand" "c,*l")) |
1fd4e8c1 | 14341 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 14342 | "TARGET_32BIT" |
c859cda6 DJ |
14343 | "@ |
14344 | bctr | |
14345 | {br|blr}" | |
a6845123 | 14346 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 14347 | |
266eb58a DE |
14348 | (define_insn "" |
14349 | [(set (pc) | |
c859cda6 | 14350 | (match_operand:DI 0 "register_operand" "c,*l")) |
266eb58a | 14351 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 14352 | "TARGET_64BIT" |
c859cda6 DJ |
14353 | "@ |
14354 | bctr | |
14355 | blr" | |
266eb58a DE |
14356 | [(set_attr "type" "jmpreg")]) |
14357 | ||
1fd4e8c1 RK |
14358 | (define_insn "nop" |
14359 | [(const_int 0)] | |
14360 | "" | |
ca7f5001 | 14361 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 14362 | \f |
7e69e155 | 14363 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
14364 | ;; so loop.c knows what to generate. |
14365 | ||
5527bf14 RH |
14366 | (define_expand "doloop_end" |
14367 | [(use (match_operand 0 "" "")) ; loop pseudo | |
14368 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
14369 | (use (match_operand 2 "" "")) ; max iterations | |
14370 | (use (match_operand 3 "" "")) ; loop level | |
14371 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
14372 | "" |
14373 | " | |
14374 | { | |
5527bf14 RH |
14375 | /* Only use this on innermost loops. */ |
14376 | if (INTVAL (operands[3]) > 1) | |
14377 | FAIL; | |
0ad91047 | 14378 | if (TARGET_POWERPC64) |
5527bf14 RH |
14379 | { |
14380 | if (GET_MODE (operands[0]) != DImode) | |
14381 | FAIL; | |
14382 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
14383 | } | |
0ad91047 | 14384 | else |
5527bf14 RH |
14385 | { |
14386 | if (GET_MODE (operands[0]) != SImode) | |
14387 | FAIL; | |
14388 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
14389 | } | |
0ad91047 DE |
14390 | DONE; |
14391 | }") | |
14392 | ||
14393 | (define_expand "ctrsi" | |
3cb999d8 DE |
14394 | [(parallel [(set (pc) |
14395 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
14396 | (const_int 1)) | |
14397 | (label_ref (match_operand 1 "" "")) | |
14398 | (pc))) | |
b6c9286a MM |
14399 | (set (match_dup 0) |
14400 | (plus:SI (match_dup 0) | |
14401 | (const_int -1))) | |
5f81043f RK |
14402 | (clobber (match_scratch:CC 2 "")) |
14403 | (clobber (match_scratch:SI 3 ""))])] | |
0ad91047 DE |
14404 | "! TARGET_POWERPC64" |
14405 | "") | |
14406 | ||
14407 | (define_expand "ctrdi" | |
3cb999d8 DE |
14408 | [(parallel [(set (pc) |
14409 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
14410 | (const_int 1)) | |
14411 | (label_ref (match_operand 1 "" "")) | |
14412 | (pc))) | |
0ad91047 DE |
14413 | (set (match_dup 0) |
14414 | (plus:DI (match_dup 0) | |
14415 | (const_int -1))) | |
14416 | (clobber (match_scratch:CC 2 "")) | |
61c07d3c | 14417 | (clobber (match_scratch:DI 3 ""))])] |
0ad91047 | 14418 | "TARGET_POWERPC64" |
61c07d3c | 14419 | "") |
c225ba7b | 14420 | |
1fd4e8c1 RK |
14421 | ;; We need to be able to do this for any operand, including MEM, or we |
14422 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 14423 | ;; JUMP_INSNs. |
0ad91047 | 14424 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
14425 | ;; label MUST be operand 0. |
14426 | ||
0ad91047 | 14427 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 14428 | [(set (pc) |
5f81043f | 14429 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 14430 | (const_int 1)) |
a6845123 | 14431 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 14432 | (pc))) |
5f81043f RK |
14433 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
14434 | (plus:SI (match_dup 1) | |
14435 | (const_int -1))) | |
1fd4e8c1 RK |
14436 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14437 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 14438 | "! TARGET_POWERPC64" |
b19003d8 RK |
14439 | "* |
14440 | { | |
af87a13e | 14441 | if (which_alternative != 0) |
b19003d8 | 14442 | return \"#\"; |
856a6884 | 14443 | else if (get_attr_length (insn) == 4) |
a6845123 | 14444 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 14445 | else |
f607bc57 | 14446 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 14447 | }" |
baf97f86 | 14448 | [(set_attr "type" "branch") |
914a7297 | 14449 | (set_attr "length" "4,12,16")]) |
7e69e155 | 14450 | |
0ad91047 | 14451 | (define_insn "*ctrsi_internal2" |
5f81043f RK |
14452 | [(set (pc) |
14453 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") | |
14454 | (const_int 1)) | |
14455 | (pc) | |
14456 | (label_ref (match_operand 0 "" "")))) | |
14457 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
14458 | (plus:SI (match_dup 1) | |
14459 | (const_int -1))) | |
14460 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
14461 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
14462 | "! TARGET_POWERPC64" |
14463 | "* | |
14464 | { | |
14465 | if (which_alternative != 0) | |
14466 | return \"#\"; | |
856a6884 | 14467 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14468 | return \"bdz %l0\"; |
14469 | else | |
f607bc57 | 14470 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14471 | }" |
14472 | [(set_attr "type" "branch") | |
914a7297 | 14473 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
14474 | |
14475 | (define_insn "*ctrdi_internal1" | |
14476 | [(set (pc) | |
61c07d3c | 14477 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
14478 | (const_int 1)) |
14479 | (label_ref (match_operand 0 "" "")) | |
14480 | (pc))) | |
61c07d3c | 14481 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
14482 | (plus:DI (match_dup 1) |
14483 | (const_int -1))) | |
61c07d3c DE |
14484 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14485 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
14486 | "TARGET_POWERPC64" |
14487 | "* | |
14488 | { | |
14489 | if (which_alternative != 0) | |
14490 | return \"#\"; | |
856a6884 | 14491 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14492 | return \"{bdn|bdnz} %l0\"; |
14493 | else | |
f607bc57 | 14494 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14495 | }" |
14496 | [(set_attr "type" "branch") | |
914a7297 | 14497 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
14498 | |
14499 | (define_insn "*ctrdi_internal2" | |
14500 | [(set (pc) | |
61c07d3c | 14501 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
14502 | (const_int 1)) |
14503 | (pc) | |
14504 | (label_ref (match_operand 0 "" "")))) | |
61c07d3c | 14505 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
14506 | (plus:DI (match_dup 1) |
14507 | (const_int -1))) | |
61c07d3c DE |
14508 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14509 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 | 14510 | "TARGET_POWERPC64" |
5f81043f RK |
14511 | "* |
14512 | { | |
14513 | if (which_alternative != 0) | |
14514 | return \"#\"; | |
856a6884 | 14515 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14516 | return \"bdz %l0\"; |
14517 | else | |
f607bc57 | 14518 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
14519 | }" |
14520 | [(set_attr "type" "branch") | |
914a7297 | 14521 | (set_attr "length" "4,12,16")]) |
5f81043f | 14522 | |
c225ba7b | 14523 | ;; Similar, but we can use GE since we have a REG_NONNEG. |
0ad91047 DE |
14524 | |
14525 | (define_insn "*ctrsi_internal3" | |
1fd4e8c1 | 14526 | [(set (pc) |
5f81043f | 14527 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 14528 | (const_int 0)) |
a6845123 | 14529 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 14530 | (pc))) |
5f81043f RK |
14531 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
14532 | (plus:SI (match_dup 1) | |
14533 | (const_int -1))) | |
1fd4e8c1 RK |
14534 | (clobber (match_scratch:CC 3 "=X,&x,&X")) |
14535 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 14536 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
b19003d8 RK |
14537 | "* |
14538 | { | |
af87a13e | 14539 | if (which_alternative != 0) |
b19003d8 | 14540 | return \"#\"; |
856a6884 | 14541 | else if (get_attr_length (insn) == 4) |
a6845123 | 14542 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 14543 | else |
f607bc57 | 14544 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 14545 | }" |
baf97f86 | 14546 | [(set_attr "type" "branch") |
914a7297 | 14547 | (set_attr "length" "4,12,16")]) |
7e69e155 | 14548 | |
0ad91047 | 14549 | (define_insn "*ctrsi_internal4" |
1fd4e8c1 | 14550 | [(set (pc) |
5f81043f RK |
14551 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
14552 | (const_int 0)) | |
14553 | (pc) | |
14554 | (label_ref (match_operand 0 "" "")))) | |
14555 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
14556 | (plus:SI (match_dup 1) | |
14557 | (const_int -1))) | |
14558 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
14559 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 14560 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
5f81043f RK |
14561 | "* |
14562 | { | |
14563 | if (which_alternative != 0) | |
14564 | return \"#\"; | |
856a6884 | 14565 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14566 | return \"bdz %l0\"; |
14567 | else | |
f607bc57 | 14568 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
14569 | }" |
14570 | [(set_attr "type" "branch") | |
914a7297 | 14571 | (set_attr "length" "4,12,16")]) |
5f81043f | 14572 | |
0ad91047 DE |
14573 | (define_insn "*ctrdi_internal3" |
14574 | [(set (pc) | |
61c07d3c | 14575 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
14576 | (const_int 0)) |
14577 | (label_ref (match_operand 0 "" "")) | |
14578 | (pc))) | |
61c07d3c | 14579 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
14580 | (plus:DI (match_dup 1) |
14581 | (const_int -1))) | |
61c07d3c DE |
14582 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14583 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
14584 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
14585 | "* | |
14586 | { | |
14587 | if (which_alternative != 0) | |
14588 | return \"#\"; | |
856a6884 | 14589 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14590 | return \"{bdn|bdnz} %l0\"; |
14591 | else | |
f607bc57 | 14592 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14593 | }" |
14594 | [(set_attr "type" "branch") | |
914a7297 | 14595 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
14596 | |
14597 | (define_insn "*ctrdi_internal4" | |
14598 | [(set (pc) | |
61c07d3c | 14599 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
14600 | (const_int 0)) |
14601 | (pc) | |
14602 | (label_ref (match_operand 0 "" "")))) | |
61c07d3c | 14603 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
14604 | (plus:DI (match_dup 1) |
14605 | (const_int -1))) | |
61c07d3c DE |
14606 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14607 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
14608 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
14609 | "* | |
14610 | { | |
14611 | if (which_alternative != 0) | |
14612 | return \"#\"; | |
856a6884 | 14613 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14614 | return \"bdz %l0\"; |
14615 | else | |
f607bc57 | 14616 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14617 | }" |
14618 | [(set_attr "type" "branch") | |
914a7297 | 14619 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
14620 | |
14621 | ;; Similar but use EQ | |
14622 | ||
14623 | (define_insn "*ctrsi_internal5" | |
5f81043f RK |
14624 | [(set (pc) |
14625 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
1fd4e8c1 | 14626 | (const_int 1)) |
a6845123 | 14627 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 14628 | (pc))) |
5f81043f RK |
14629 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
14630 | (plus:SI (match_dup 1) | |
14631 | (const_int -1))) | |
1fd4e8c1 RK |
14632 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14633 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 14634 | "! TARGET_POWERPC64" |
b19003d8 RK |
14635 | "* |
14636 | { | |
af87a13e | 14637 | if (which_alternative != 0) |
b19003d8 | 14638 | return \"#\"; |
856a6884 | 14639 | else if (get_attr_length (insn) == 4) |
a6845123 | 14640 | return \"bdz %l0\"; |
b19003d8 | 14641 | else |
f607bc57 | 14642 | return \"{bdn|bdnz} $+8\;b %l0\"; |
b19003d8 | 14643 | }" |
baf97f86 | 14644 | [(set_attr "type" "branch") |
914a7297 | 14645 | (set_attr "length" "4,12,16")]) |
1fd4e8c1 | 14646 | |
0ad91047 | 14647 | (define_insn "*ctrsi_internal6" |
5f81043f RK |
14648 | [(set (pc) |
14649 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
14650 | (const_int 1)) | |
14651 | (pc) | |
14652 | (label_ref (match_operand 0 "" "")))) | |
14653 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
14654 | (plus:SI (match_dup 1) | |
14655 | (const_int -1))) | |
14656 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
14657 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
14658 | "! TARGET_POWERPC64" |
14659 | "* | |
14660 | { | |
14661 | if (which_alternative != 0) | |
14662 | return \"#\"; | |
856a6884 | 14663 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14664 | return \"{bdn|bdnz} %l0\"; |
14665 | else | |
f607bc57 | 14666 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14667 | }" |
14668 | [(set_attr "type" "branch") | |
914a7297 | 14669 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
14670 | |
14671 | (define_insn "*ctrdi_internal5" | |
14672 | [(set (pc) | |
61c07d3c | 14673 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
14674 | (const_int 1)) |
14675 | (label_ref (match_operand 0 "" "")) | |
14676 | (pc))) | |
61c07d3c | 14677 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
14678 | (plus:DI (match_dup 1) |
14679 | (const_int -1))) | |
61c07d3c DE |
14680 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14681 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
14682 | "TARGET_POWERPC64" |
14683 | "* | |
14684 | { | |
14685 | if (which_alternative != 0) | |
14686 | return \"#\"; | |
856a6884 | 14687 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14688 | return \"bdz %l0\"; |
14689 | else | |
f607bc57 | 14690 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14691 | }" |
14692 | [(set_attr "type" "branch") | |
914a7297 | 14693 | (set_attr "length" "4,12,16")]) |
0ad91047 DE |
14694 | |
14695 | (define_insn "*ctrdi_internal6" | |
14696 | [(set (pc) | |
61c07d3c | 14697 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
14698 | (const_int 1)) |
14699 | (pc) | |
14700 | (label_ref (match_operand 0 "" "")))) | |
61c07d3c | 14701 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
14702 | (plus:DI (match_dup 1) |
14703 | (const_int -1))) | |
61c07d3c DE |
14704 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
14705 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 | 14706 | "TARGET_POWERPC64" |
5f81043f RK |
14707 | "* |
14708 | { | |
14709 | if (which_alternative != 0) | |
14710 | return \"#\"; | |
856a6884 | 14711 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14712 | return \"{bdn|bdnz} %l0\"; |
14713 | else | |
f607bc57 | 14714 | return \"bdz $+8\;b %l0\"; |
5f81043f RK |
14715 | }" |
14716 | [(set_attr "type" "branch") | |
914a7297 | 14717 | (set_attr "length" "4,12,16")]) |
5f81043f | 14718 | |
0ad91047 DE |
14719 | ;; Now the splitters if we could not allocate the CTR register |
14720 | ||
1fd4e8c1 RK |
14721 | (define_split |
14722 | [(set (pc) | |
14723 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14724 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14725 | (const_int 1)]) |
14726 | (match_operand 5 "" "") | |
14727 | (match_operand 6 "" ""))) | |
cd2b37d9 | 14728 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
14729 | (plus:SI (match_dup 1) |
14730 | (const_int -1))) | |
1fd4e8c1 RK |
14731 | (clobber (match_scratch:CC 3 "")) |
14732 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 | 14733 | "! TARGET_POWERPC64 && reload_completed" |
1fd4e8c1 | 14734 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14735 | (compare:CC (plus:SI (match_dup 1) |
14736 | (const_int -1)) | |
1fd4e8c1 | 14737 | (const_int 0))) |
5f81043f RK |
14738 | (set (match_dup 0) |
14739 | (plus:SI (match_dup 1) | |
14740 | (const_int -1)))]) | |
14741 | (set (pc) (if_then_else (match_dup 7) | |
14742 | (match_dup 5) | |
14743 | (match_dup 6)))] | |
1fd4e8c1 RK |
14744 | " |
14745 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
14746 | const0_rtx); }") | |
14747 | ||
14748 | (define_split | |
14749 | [(set (pc) | |
14750 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14751 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14752 | (const_int 1)]) |
14753 | (match_operand 5 "" "") | |
14754 | (match_operand 6 "" ""))) | |
9ebbca7d | 14755 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
14756 | (plus:SI (match_dup 1) (const_int -1))) |
14757 | (clobber (match_scratch:CC 3 "")) | |
14758 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 DE |
14759 | "! TARGET_POWERPC64 && reload_completed |
14760 | && ! gpc_reg_operand (operands[0], SImode)" | |
1fd4e8c1 | 14761 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14762 | (compare:CC (plus:SI (match_dup 1) |
14763 | (const_int -1)) | |
1fd4e8c1 | 14764 | (const_int 0))) |
5f81043f RK |
14765 | (set (match_dup 4) |
14766 | (plus:SI (match_dup 1) | |
14767 | (const_int -1)))]) | |
14768 | (set (match_dup 0) | |
14769 | (match_dup 4)) | |
14770 | (set (pc) (if_then_else (match_dup 7) | |
14771 | (match_dup 5) | |
14772 | (match_dup 6)))] | |
1fd4e8c1 RK |
14773 | " |
14774 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
14775 | const0_rtx); }") | |
0ad91047 DE |
14776 | (define_split |
14777 | [(set (pc) | |
14778 | (if_then_else (match_operator 2 "comparison_operator" | |
14779 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14780 | (const_int 1)]) | |
61c07d3c DE |
14781 | (match_operand 5 "" "") |
14782 | (match_operand 6 "" ""))) | |
0ad91047 DE |
14783 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
14784 | (plus:DI (match_dup 1) | |
14785 | (const_int -1))) | |
14786 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c DE |
14787 | (clobber (match_scratch:DI 4 ""))] |
14788 | "TARGET_POWERPC64 && reload_completed" | |
0ad91047 DE |
14789 | [(parallel [(set (match_dup 3) |
14790 | (compare:CC (plus:DI (match_dup 1) | |
14791 | (const_int -1)) | |
14792 | (const_int 0))) | |
14793 | (set (match_dup 0) | |
14794 | (plus:DI (match_dup 1) | |
14795 | (const_int -1)))]) | |
61c07d3c DE |
14796 | (set (pc) (if_then_else (match_dup 7) |
14797 | (match_dup 5) | |
14798 | (match_dup 6)))] | |
0ad91047 | 14799 | " |
61c07d3c | 14800 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], |
0ad91047 DE |
14801 | const0_rtx); }") |
14802 | ||
14803 | (define_split | |
14804 | [(set (pc) | |
14805 | (if_then_else (match_operator 2 "comparison_operator" | |
14806 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14807 | (const_int 1)]) | |
61c07d3c DE |
14808 | (match_operand 5 "" "") |
14809 | (match_operand 6 "" ""))) | |
9ebbca7d | 14810 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
14811 | (plus:DI (match_dup 1) (const_int -1))) |
14812 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 14813 | (clobber (match_scratch:DI 4 ""))] |
0ad91047 DE |
14814 | "TARGET_POWERPC64 && reload_completed |
14815 | && ! gpc_reg_operand (operands[0], DImode)" | |
14816 | [(parallel [(set (match_dup 3) | |
14817 | (compare:CC (plus:DI (match_dup 1) | |
14818 | (const_int -1)) | |
14819 | (const_int 0))) | |
14820 | (set (match_dup 4) | |
14821 | (plus:DI (match_dup 1) | |
14822 | (const_int -1)))]) | |
14823 | (set (match_dup 0) | |
14824 | (match_dup 4)) | |
61c07d3c DE |
14825 | (set (pc) (if_then_else (match_dup 7) |
14826 | (match_dup 5) | |
14827 | (match_dup 6)))] | |
0ad91047 | 14828 | " |
61c07d3c | 14829 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], |
0ad91047 | 14830 | const0_rtx); }") |
c94ccb87 | 14831 | |
e0cd0770 JC |
14832 | \f |
14833 | (define_insn "trap" | |
14834 | [(trap_if (const_int 1) (const_int 0))] | |
14835 | "" | |
14836 | "{t 31,0,0|trap}") | |
14837 | ||
14838 | (define_expand "conditional_trap" | |
14839 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14840 | [(match_dup 2) (match_dup 3)]) | |
14841 | (match_operand 1 "const_int_operand" ""))] | |
14842 | "" | |
14843 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
14844 | operands[2] = rs6000_compare_op0; | |
14845 | operands[3] = rs6000_compare_op1;") | |
14846 | ||
14847 | (define_insn "" | |
14848 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14849 | [(match_operand:SI 1 "register_operand" "r") | |
14850 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
14851 | (const_int 0))] | |
14852 | "" | |
a157febd GK |
14853 | "{t|tw}%V0%I2 %1,%2") |
14854 | ||
14855 | (define_insn "" | |
14856 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14857 | [(match_operand:DI 1 "register_operand" "r") | |
14858 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
14859 | (const_int 0))] | |
14860 | "TARGET_POWERPC64" | |
14861 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
14862 | \f |
14863 | ;; Insns related to generating the function prologue and epilogue. | |
14864 | ||
14865 | (define_expand "prologue" | |
14866 | [(use (const_int 0))] | |
14867 | "TARGET_SCHED_PROLOG" | |
14868 | " | |
14869 | { | |
14870 | rs6000_emit_prologue (); | |
14871 | DONE; | |
14872 | }") | |
14873 | ||
14874 | (define_insn "movesi_from_cr" | |
14875 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
14876 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) | |
14877 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))] | |
14878 | "" | |
309323c2 DE |
14879 | "mfcr %0" |
14880 | [(set_attr "type" "cr_logical")]) | |
9ebbca7d GK |
14881 | |
14882 | (define_insn "*stmw" | |
14883 | [(match_parallel 0 "stmw_operation" | |
14884 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
14885 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
14886 | "TARGET_MULTIPLE" | |
14887 | "{stm|stmw} %2,%1") | |
14888 | ||
14889 | (define_insn "*save_fpregs_si" | |
14890 | [(match_parallel 0 "any_operand" | |
14891 | [(clobber (match_operand:SI 1 "register_operand" "=l")) | |
14892 | (use (match_operand:SI 2 "call_operand" "s")) | |
14893 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14894 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14895 | "TARGET_32BIT" | |
14896 | "bl %z2") | |
14897 | ||
14898 | (define_insn "*save_fpregs_di" | |
14899 | [(match_parallel 0 "any_operand" | |
14900 | [(clobber (match_operand:DI 1 "register_operand" "=l")) | |
14901 | (use (match_operand:DI 2 "call_operand" "s")) | |
14902 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14903 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14904 | "TARGET_64BIT" | |
14905 | "bl %z2") | |
14906 | ||
14907 | ; These are to explain that changes to the stack pointer should | |
14908 | ; not be moved over stores to stack memory. | |
14909 | (define_insn "stack_tie" | |
14910 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
14911 | (unspec:BLK [(match_dup 0)] 5))] | |
14912 | "" | |
14913 | "" | |
14914 | [(set_attr "length" "0")]) | |
14915 | ||
14916 | ||
14917 | (define_expand "epilogue" | |
14918 | [(use (const_int 0))] | |
14919 | "TARGET_SCHED_PROLOG" | |
14920 | " | |
14921 | { | |
14922 | rs6000_emit_epilogue (FALSE); | |
14923 | DONE; | |
14924 | }") | |
14925 | ||
14926 | ; On some processors, doing the mtcrf one CC register at a time is | |
14927 | ; faster (like on the 604e). On others, doing them all at once is | |
14928 | ; faster; for instance, on the 601 and 750. | |
14929 | ||
14930 | (define_expand "movsi_to_cr_one" | |
35aba846 DE |
14931 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14932 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
14933 | (match_dup 2)] 20))] | |
14934 | "" | |
14935 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
9ebbca7d GK |
14936 | |
14937 | (define_insn "*movsi_to_cr" | |
35aba846 DE |
14938 | [(match_parallel 0 "mtcrf_operation" |
14939 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") | |
14940 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
14941 | (match_operand 3 "immediate_operand" "n")] | |
9ebbca7d GK |
14942 | 20))])] |
14943 | "" | |
e35b9579 GK |
14944 | "* |
14945 | { | |
14946 | int mask = 0; | |
14947 | int i; | |
14948 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14949 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14950 | operands[4] = GEN_INT (mask); | |
14951 | return \"mtcrf %4,%2\"; | |
309323c2 DE |
14952 | }" |
14953 | [(set_attr "type" "cr_logical")]) | |
9ebbca7d GK |
14954 | |
14955 | (define_insn "" | |
309323c2 DE |
14956 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14957 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
14958 | (match_operand 2 "immediate_operand" "n")] 20))] | |
14959 | "GET_CODE (operands[0]) == REG | |
14960 | && CR_REGNO_P (REGNO (operands[0])) | |
14961 | && GET_CODE (operands[2]) == CONST_INT | |
14962 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
14963 | "mtcrf %R0,%1" | |
14964 | [(set_attr "type" "cr_logical")]) | |
9ebbca7d GK |
14965 | |
14966 | ; The load-multiple instructions have similar properties. | |
14967 | ; Note that "load_multiple" is a name known to the machine-independent | |
14968 | ; code that actually corresponds to the powerpc load-string. | |
14969 | ||
14970 | (define_insn "*lmw" | |
35aba846 DE |
14971 | [(match_parallel 0 "lmw_operation" |
14972 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14973 | (match_operand:SI 2 "memory_operand" "m"))])] | |
14974 | "TARGET_MULTIPLE" | |
14975 | "{lm|lmw} %1,%2") | |
9ebbca7d GK |
14976 | |
14977 | (define_insn "*return_internal_si" | |
e35b9579 GK |
14978 | [(return) |
14979 | (use (match_operand:SI 0 "register_operand" "lc"))] | |
9ebbca7d | 14980 | "TARGET_32BIT" |
cccf3bdc | 14981 | "b%T0" |
9ebbca7d GK |
14982 | [(set_attr "type" "jmpreg")]) |
14983 | ||
14984 | (define_insn "*return_internal_di" | |
e35b9579 GK |
14985 | [(return) |
14986 | (use (match_operand:DI 0 "register_operand" "lc"))] | |
9ebbca7d | 14987 | "TARGET_64BIT" |
cccf3bdc | 14988 | "b%T0" |
9ebbca7d GK |
14989 | [(set_attr "type" "jmpreg")]) |
14990 | ||
14991 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
14992 | ; stuff was in GCC. Oh, and "any_operand" is a bit flexible... | |
14993 | ||
14994 | (define_insn "*return_and_restore_fpregs_si" | |
14995 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
14996 | [(return) |
14997 | (use (match_operand:SI 1 "register_operand" "l")) | |
9ebbca7d GK |
14998 | (use (match_operand:SI 2 "call_operand" "s")) |
14999 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
15000 | (match_operand:DF 4 "memory_operand" "m"))])] | |
15001 | "TARGET_32BIT" | |
15002 | "b %z2") | |
15003 | ||
15004 | (define_insn "*return_and_restore_fpregs_di" | |
15005 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
15006 | [(return) |
15007 | (use (match_operand:DI 1 "register_operand" "l")) | |
9ebbca7d GK |
15008 | (use (match_operand:DI 2 "call_operand" "s")) |
15009 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
15010 | (match_operand:DF 4 "memory_operand" "m"))])] | |
15011 | "TARGET_64BIT" | |
15012 | "b %z2") | |
15013 | ||
83720594 RH |
15014 | ; This is used in compiling the unwind routines. |
15015 | (define_expand "eh_return" | |
15016 | [(use (match_operand 0 "general_operand" "")) | |
15017 | (use (match_operand 1 "general_operand" ""))] | |
9ebbca7d GK |
15018 | "" |
15019 | " | |
15020 | { | |
3553b09d | 15021 | #if TARGET_AIX |
83720594 | 15022 | rs6000_emit_eh_toc_restore (operands[0]); |
3553b09d | 15023 | #endif |
83720594 RH |
15024 | if (TARGET_32BIT) |
15025 | emit_insn (gen_eh_set_lr_si (operands[1])); | |
9ebbca7d | 15026 | else |
83720594 RH |
15027 | emit_insn (gen_eh_set_lr_di (operands[1])); |
15028 | emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]); | |
9ebbca7d GK |
15029 | DONE; |
15030 | }") | |
15031 | ||
83720594 RH |
15032 | ; We can't expand this before we know where the link register is stored. |
15033 | (define_insn "eh_set_lr_si" | |
15034 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9) | |
466eb3e0 | 15035 | (clobber (match_scratch:SI 1 "=&b"))] |
83720594 RH |
15036 | "TARGET_32BIT" |
15037 | "#") | |
15038 | ||
15039 | (define_insn "eh_set_lr_di" | |
15040 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9) | |
466eb3e0 | 15041 | (clobber (match_scratch:DI 1 "=&b"))] |
83720594 RH |
15042 | "TARGET_64BIT" |
15043 | "#") | |
9ebbca7d GK |
15044 | |
15045 | (define_split | |
83720594 RH |
15046 | [(unspec_volatile [(match_operand 0 "register_operand" "")] 9) |
15047 | (clobber (match_scratch 1 ""))] | |
15048 | "reload_completed" | |
15049 | [(const_int 0)] | |
9ebbca7d GK |
15050 | " |
15051 | { | |
83720594 | 15052 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d | 15053 | |
83720594 RH |
15054 | if (info->lr_save_p) |
15055 | { | |
15056 | rtx frame_rtx = stack_pointer_rtx; | |
15057 | int sp_offset = 0; | |
15058 | rtx tmp; | |
9ebbca7d | 15059 | |
83720594 RH |
15060 | if (frame_pointer_needed |
15061 | || current_function_calls_alloca | |
15062 | || info->total_size > 32767) | |
15063 | { | |
15064 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
15065 | frame_rtx = operands[1]; | |
15066 | } | |
15067 | else if (info->push_p) | |
15068 | sp_offset = info->total_size; | |
9ebbca7d | 15069 | |
83720594 RH |
15070 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); |
15071 | tmp = gen_rtx_MEM (Pmode, tmp); | |
15072 | emit_move_insn (tmp, operands[0]); | |
15073 | } | |
15074 | else | |
15075 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
15076 | DONE; | |
15077 | }") | |
0ac081f6 | 15078 | |
01a2ccd0 DE |
15079 | (define_insn "prefetch" |
15080 | [(prefetch (match_operand:V4SI 0 "address_operand" "p") | |
6041bf2f DE |
15081 | (match_operand:SI 1 "const_int_operand" "n") |
15082 | (match_operand:SI 2 "const_int_operand" "n"))] | |
01a2ccd0 | 15083 | "TARGET_POWERPC" |
6041bf2f DE |
15084 | "* |
15085 | { | |
01a2ccd0 DE |
15086 | if (GET_CODE (operands[0]) == REG) |
15087 | return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; | |
15088 | return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; | |
6041bf2f DE |
15089 | }" |
15090 | [(set_attr "type" "load")]) | |
a3170dc6 | 15091 | |
10ed84db | 15092 | (include "altivec.md") |
a3170dc6 | 15093 | (include "spe.md") |