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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
d24652ee | 2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
affad9a4 | 3 | ;; 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 | 5 | |
5de601cf | 6 | ;; This file is part of GCC. |
1fd4e8c1 | 7 | |
5de601cf NC |
8 | ;; GCC is free software; you can redistribute it and/or modify it |
9 | ;; under the terms of the GNU General Public License as published | |
10 | ;; by the Free Software Foundation; either version 2, or (at your | |
11 | ;; option) any later version. | |
1fd4e8c1 | 12 | |
5de601cf NC |
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | ;; License for more details. | |
1fd4e8c1 RK |
17 | |
18 | ;; You should have received a copy of the GNU General Public License | |
5de601cf NC |
19 | ;; along with GCC; see the file COPYING. If not, write to the |
20 | ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | ;; MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d | 24 | |
615158e2 JJ |
25 | ;; |
26 | ;; UNSPEC usage | |
27 | ;; | |
28 | ||
29 | (define_constants | |
30 | [(UNSPEC_FRSP 0) ; frsp for POWER machines | |
31 | (UNSPEC_TIE 5) ; tie stack contents and stack pointer | |
32 | (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC | |
33 | (UNSPEC_TOC 7) ; address of the TOC (more-or-less) | |
34 | (UNSPEC_MOVSI_GOT 8) | |
35 | (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit | |
36 | (UNSPEC_FCTIWZ 10) | |
37 | (UNSPEC_LD_MPIC 15) ; load_macho_picbase | |
38 | (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic | |
39 | (UNSPEC_TLSGD 17) | |
40 | (UNSPEC_TLSLD 18) | |
41 | (UNSPEC_MOVESI_FROM_CR 19) | |
42 | (UNSPEC_MOVESI_TO_CR 20) | |
43 | (UNSPEC_TLSDTPREL 21) | |
44 | (UNSPEC_TLSDTPRELHA 22) | |
45 | (UNSPEC_TLSDTPRELLO 23) | |
46 | (UNSPEC_TLSGOTDTPREL 24) | |
47 | (UNSPEC_TLSTPREL 25) | |
48 | (UNSPEC_TLSTPRELHA 26) | |
49 | (UNSPEC_TLSTPRELLO 27) | |
50 | (UNSPEC_TLSGOTTPREL 28) | |
51 | (UNSPEC_TLSTLS 29) | |
ecb62ae7 | 52 | (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero |
423c1189 | 53 | (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit |
615158e2 JJ |
54 | ]) |
55 | ||
56 | ;; | |
57 | ;; UNSPEC_VOLATILE usage | |
58 | ;; | |
59 | ||
60 | (define_constants | |
61 | [(UNSPECV_BLOCK 0) | |
62 | (UNSPECV_EH_RR 9) ; eh_reg_restore | |
63 | ]) | |
1fd4e8c1 RK |
64 | \f |
65 | ;; Define an insn type attribute. This is used in function unit delay | |
66 | ;; computations. | |
2c4a9cff | 67 | (define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv" |
1fd4e8c1 RK |
68 | (const_string "integer")) |
69 | ||
b19003d8 | 70 | ;; Length (in bytes). |
6ae08853 | 71 | ; '(pc)' in the following doesn't include the instruction itself; it is |
6cbadf36 | 72 | ; calculated as if the instruction had zero size. |
b19003d8 RK |
73 | (define_attr "length" "" |
74 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 75 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 76 | (const_int -32768)) |
6cbadf36 GK |
77 | (lt (minus (match_dup 0) (pc)) |
78 | (const_int 32764))) | |
39a10a29 GK |
79 | (const_int 4) |
80 | (const_int 8)) | |
b19003d8 RK |
81 | (const_int 4))) |
82 | ||
cfb557c4 RK |
83 | ;; Processor type -- this attribute must exactly match the processor_type |
84 | ;; enumeration in rs6000.h. | |
85 | ||
ec507f2d | 86 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5" |
cfb557c4 RK |
87 | (const (symbol_ref "rs6000_cpu_attr"))) |
88 | ||
b54cf83a DE |
89 | (automata_option "ndfa") |
90 | ||
91 | (include "rios1.md") | |
92 | (include "rios2.md") | |
93 | (include "rs64.md") | |
94 | (include "mpc.md") | |
95 | (include "40x.md") | |
02ca7595 | 96 | (include "440.md") |
b54cf83a DE |
97 | (include "603.md") |
98 | (include "6xx.md") | |
99 | (include "7xx.md") | |
100 | (include "7450.md") | |
5e8006fa | 101 | (include "8540.md") |
b54cf83a | 102 | (include "power4.md") |
ec507f2d | 103 | (include "power5.md") |
309323c2 | 104 | |
1fd4e8c1 RK |
105 | \f |
106 | ;; Start with fixed-point load and store insns. Here we put only the more | |
107 | ;; complex forms. Basic data transfer is done later. | |
108 | ||
51b8fc2c RK |
109 | (define_expand "zero_extendqidi2" |
110 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
111 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
112 | "TARGET_POWERPC64" | |
113 | "") | |
114 | ||
115 | (define_insn "" | |
116 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
117 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
118 | "TARGET_POWERPC64" | |
119 | "@ | |
120 | lbz%U1%X1 %0,%1 | |
4371f8af | 121 | rldicl %0,%1,0,56" |
51b8fc2c RK |
122 | [(set_attr "type" "load,*")]) |
123 | ||
124 | (define_insn "" | |
9ebbca7d GK |
125 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
126 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 127 | (const_int 0))) |
9ebbca7d | 128 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 129 | "TARGET_64BIT" |
9ebbca7d GK |
130 | "@ |
131 | rldicl. %2,%1,0,56 | |
132 | #" | |
133 | [(set_attr "type" "compare") | |
134 | (set_attr "length" "4,8")]) | |
135 | ||
136 | (define_split | |
137 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
138 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
139 | (const_int 0))) | |
140 | (clobber (match_scratch:DI 2 ""))] | |
141 | "TARGET_POWERPC64 && reload_completed" | |
142 | [(set (match_dup 2) | |
143 | (zero_extend:DI (match_dup 1))) | |
144 | (set (match_dup 0) | |
145 | (compare:CC (match_dup 2) | |
146 | (const_int 0)))] | |
147 | "") | |
51b8fc2c RK |
148 | |
149 | (define_insn "" | |
9ebbca7d GK |
150 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
151 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 152 | (const_int 0))) |
9ebbca7d | 153 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 154 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 155 | "TARGET_64BIT" |
9ebbca7d GK |
156 | "@ |
157 | rldicl. %0,%1,0,56 | |
158 | #" | |
159 | [(set_attr "type" "compare") | |
160 | (set_attr "length" "4,8")]) | |
161 | ||
162 | (define_split | |
163 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
164 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
165 | (const_int 0))) | |
166 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
167 | (zero_extend:DI (match_dup 1)))] | |
168 | "TARGET_POWERPC64 && reload_completed" | |
169 | [(set (match_dup 0) | |
170 | (zero_extend:DI (match_dup 1))) | |
171 | (set (match_dup 2) | |
172 | (compare:CC (match_dup 0) | |
173 | (const_int 0)))] | |
174 | "") | |
51b8fc2c | 175 | |
2bee0449 RK |
176 | (define_insn "extendqidi2" |
177 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
178 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 179 | "TARGET_POWERPC64" |
2bee0449 | 180 | "extsb %0,%1") |
51b8fc2c RK |
181 | |
182 | (define_insn "" | |
9ebbca7d GK |
183 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
184 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 185 | (const_int 0))) |
9ebbca7d | 186 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 187 | "TARGET_64BIT" |
9ebbca7d GK |
188 | "@ |
189 | extsb. %2,%1 | |
190 | #" | |
191 | [(set_attr "type" "compare") | |
192 | (set_attr "length" "4,8")]) | |
193 | ||
194 | (define_split | |
195 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
196 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
197 | (const_int 0))) | |
198 | (clobber (match_scratch:DI 2 ""))] | |
199 | "TARGET_POWERPC64 && reload_completed" | |
200 | [(set (match_dup 2) | |
201 | (sign_extend:DI (match_dup 1))) | |
202 | (set (match_dup 0) | |
203 | (compare:CC (match_dup 2) | |
204 | (const_int 0)))] | |
205 | "") | |
51b8fc2c RK |
206 | |
207 | (define_insn "" | |
9ebbca7d GK |
208 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
209 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 210 | (const_int 0))) |
9ebbca7d | 211 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 212 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 213 | "TARGET_64BIT" |
9ebbca7d GK |
214 | "@ |
215 | extsb. %0,%1 | |
216 | #" | |
217 | [(set_attr "type" "compare") | |
218 | (set_attr "length" "4,8")]) | |
219 | ||
220 | (define_split | |
221 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
222 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
223 | (const_int 0))) | |
224 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
225 | (sign_extend:DI (match_dup 1)))] | |
226 | "TARGET_POWERPC64 && reload_completed" | |
227 | [(set (match_dup 0) | |
228 | (sign_extend:DI (match_dup 1))) | |
229 | (set (match_dup 2) | |
230 | (compare:CC (match_dup 0) | |
231 | (const_int 0)))] | |
232 | "") | |
51b8fc2c RK |
233 | |
234 | (define_expand "zero_extendhidi2" | |
235 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
236 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
237 | "TARGET_POWERPC64" | |
238 | "") | |
239 | ||
240 | (define_insn "" | |
241 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
242 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
243 | "TARGET_POWERPC64" | |
244 | "@ | |
245 | lhz%U1%X1 %0,%1 | |
4371f8af | 246 | rldicl %0,%1,0,48" |
51b8fc2c RK |
247 | [(set_attr "type" "load,*")]) |
248 | ||
249 | (define_insn "" | |
9ebbca7d GK |
250 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
251 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 252 | (const_int 0))) |
9ebbca7d | 253 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 254 | "TARGET_64BIT" |
9ebbca7d GK |
255 | "@ |
256 | rldicl. %2,%1,0,48 | |
257 | #" | |
258 | [(set_attr "type" "compare") | |
259 | (set_attr "length" "4,8")]) | |
260 | ||
261 | (define_split | |
262 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
263 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
264 | (const_int 0))) | |
265 | (clobber (match_scratch:DI 2 ""))] | |
266 | "TARGET_POWERPC64 && reload_completed" | |
267 | [(set (match_dup 2) | |
268 | (zero_extend:DI (match_dup 1))) | |
269 | (set (match_dup 0) | |
270 | (compare:CC (match_dup 2) | |
271 | (const_int 0)))] | |
272 | "") | |
51b8fc2c RK |
273 | |
274 | (define_insn "" | |
9ebbca7d GK |
275 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
276 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 277 | (const_int 0))) |
9ebbca7d | 278 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 279 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 280 | "TARGET_64BIT" |
9ebbca7d GK |
281 | "@ |
282 | rldicl. %0,%1,0,48 | |
283 | #" | |
284 | [(set_attr "type" "compare") | |
285 | (set_attr "length" "4,8")]) | |
286 | ||
287 | (define_split | |
288 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
289 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
290 | (const_int 0))) | |
291 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
292 | (zero_extend:DI (match_dup 1)))] | |
293 | "TARGET_POWERPC64 && reload_completed" | |
294 | [(set (match_dup 0) | |
295 | (zero_extend:DI (match_dup 1))) | |
296 | (set (match_dup 2) | |
297 | (compare:CC (match_dup 0) | |
298 | (const_int 0)))] | |
299 | "") | |
51b8fc2c RK |
300 | |
301 | (define_expand "extendhidi2" | |
302 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
303 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
304 | "TARGET_POWERPC64" | |
305 | "") | |
306 | ||
307 | (define_insn "" | |
308 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
309 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
310 | "TARGET_POWERPC64" | |
311 | "@ | |
312 | lha%U1%X1 %0,%1 | |
313 | extsh %0,%1" | |
b54cf83a | 314 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
315 | |
316 | (define_insn "" | |
9ebbca7d GK |
317 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
318 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 319 | (const_int 0))) |
9ebbca7d | 320 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 321 | "TARGET_64BIT" |
9ebbca7d GK |
322 | "@ |
323 | extsh. %2,%1 | |
324 | #" | |
325 | [(set_attr "type" "compare") | |
326 | (set_attr "length" "4,8")]) | |
327 | ||
328 | (define_split | |
329 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
330 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
331 | (const_int 0))) | |
332 | (clobber (match_scratch:DI 2 ""))] | |
333 | "TARGET_POWERPC64 && reload_completed" | |
334 | [(set (match_dup 2) | |
335 | (sign_extend:DI (match_dup 1))) | |
336 | (set (match_dup 0) | |
337 | (compare:CC (match_dup 2) | |
338 | (const_int 0)))] | |
339 | "") | |
51b8fc2c RK |
340 | |
341 | (define_insn "" | |
9ebbca7d GK |
342 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
343 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 344 | (const_int 0))) |
9ebbca7d | 345 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 346 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 347 | "TARGET_64BIT" |
9ebbca7d GK |
348 | "@ |
349 | extsh. %0,%1 | |
350 | #" | |
351 | [(set_attr "type" "compare") | |
352 | (set_attr "length" "4,8")]) | |
353 | ||
354 | (define_split | |
355 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
356 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
357 | (const_int 0))) | |
358 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
359 | (sign_extend:DI (match_dup 1)))] | |
360 | "TARGET_POWERPC64 && reload_completed" | |
361 | [(set (match_dup 0) | |
362 | (sign_extend:DI (match_dup 1))) | |
363 | (set (match_dup 2) | |
364 | (compare:CC (match_dup 0) | |
365 | (const_int 0)))] | |
366 | "") | |
51b8fc2c RK |
367 | |
368 | (define_expand "zero_extendsidi2" | |
369 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
370 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
371 | "TARGET_POWERPC64" | |
372 | "") | |
373 | ||
374 | (define_insn "" | |
375 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
376 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
377 | "TARGET_POWERPC64" | |
378 | "@ | |
379 | lwz%U1%X1 %0,%1 | |
380 | rldicl %0,%1,0,32" | |
381 | [(set_attr "type" "load,*")]) | |
382 | ||
383 | (define_insn "" | |
9ebbca7d GK |
384 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
385 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 386 | (const_int 0))) |
9ebbca7d | 387 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 388 | "TARGET_64BIT" |
9ebbca7d GK |
389 | "@ |
390 | rldicl. %2,%1,0,32 | |
391 | #" | |
392 | [(set_attr "type" "compare") | |
393 | (set_attr "length" "4,8")]) | |
394 | ||
395 | (define_split | |
396 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
397 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
398 | (const_int 0))) | |
399 | (clobber (match_scratch:DI 2 ""))] | |
400 | "TARGET_POWERPC64 && reload_completed" | |
401 | [(set (match_dup 2) | |
402 | (zero_extend:DI (match_dup 1))) | |
403 | (set (match_dup 0) | |
404 | (compare:CC (match_dup 2) | |
405 | (const_int 0)))] | |
406 | "") | |
51b8fc2c RK |
407 | |
408 | (define_insn "" | |
9ebbca7d GK |
409 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
410 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 411 | (const_int 0))) |
9ebbca7d | 412 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 413 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 414 | "TARGET_64BIT" |
9ebbca7d GK |
415 | "@ |
416 | rldicl. %0,%1,0,32 | |
417 | #" | |
418 | [(set_attr "type" "compare") | |
419 | (set_attr "length" "4,8")]) | |
420 | ||
421 | (define_split | |
422 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
423 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
424 | (const_int 0))) | |
425 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
426 | (zero_extend:DI (match_dup 1)))] | |
427 | "TARGET_POWERPC64 && reload_completed" | |
428 | [(set (match_dup 0) | |
429 | (zero_extend:DI (match_dup 1))) | |
430 | (set (match_dup 2) | |
431 | (compare:CC (match_dup 0) | |
432 | (const_int 0)))] | |
433 | "") | |
51b8fc2c RK |
434 | |
435 | (define_expand "extendsidi2" | |
436 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
437 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
438 | "TARGET_POWERPC64" | |
439 | "") | |
440 | ||
441 | (define_insn "" | |
442 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 443 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
444 | "TARGET_POWERPC64" |
445 | "@ | |
446 | lwa%U1%X1 %0,%1 | |
447 | extsw %0,%1" | |
b54cf83a | 448 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
449 | |
450 | (define_insn "" | |
9ebbca7d GK |
451 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
452 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 453 | (const_int 0))) |
9ebbca7d | 454 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 455 | "TARGET_64BIT" |
9ebbca7d GK |
456 | "@ |
457 | extsw. %2,%1 | |
458 | #" | |
459 | [(set_attr "type" "compare") | |
460 | (set_attr "length" "4,8")]) | |
461 | ||
462 | (define_split | |
463 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
464 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
465 | (const_int 0))) | |
466 | (clobber (match_scratch:DI 2 ""))] | |
467 | "TARGET_POWERPC64 && reload_completed" | |
468 | [(set (match_dup 2) | |
469 | (sign_extend:DI (match_dup 1))) | |
470 | (set (match_dup 0) | |
471 | (compare:CC (match_dup 2) | |
472 | (const_int 0)))] | |
473 | "") | |
51b8fc2c RK |
474 | |
475 | (define_insn "" | |
9ebbca7d GK |
476 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
477 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 478 | (const_int 0))) |
9ebbca7d | 479 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 480 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 481 | "TARGET_64BIT" |
9ebbca7d GK |
482 | "@ |
483 | extsw. %0,%1 | |
484 | #" | |
485 | [(set_attr "type" "compare") | |
486 | (set_attr "length" "4,8")]) | |
487 | ||
488 | (define_split | |
489 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
490 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
491 | (const_int 0))) | |
492 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
493 | (sign_extend:DI (match_dup 1)))] | |
494 | "TARGET_POWERPC64 && reload_completed" | |
495 | [(set (match_dup 0) | |
496 | (sign_extend:DI (match_dup 1))) | |
497 | (set (match_dup 2) | |
498 | (compare:CC (match_dup 0) | |
499 | (const_int 0)))] | |
500 | "") | |
51b8fc2c | 501 | |
1fd4e8c1 | 502 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
503 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
504 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
505 | "" |
506 | "") | |
507 | ||
508 | (define_insn "" | |
cd2b37d9 | 509 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
510 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
511 | "" | |
512 | "@ | |
513 | lbz%U1%X1 %0,%1 | |
005a35b9 | 514 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
515 | [(set_attr "type" "load,*")]) |
516 | ||
517 | (define_insn "" | |
9ebbca7d GK |
518 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
519 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 520 | (const_int 0))) |
9ebbca7d | 521 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 522 | "" |
9ebbca7d GK |
523 | "@ |
524 | {andil.|andi.} %2,%1,0xff | |
525 | #" | |
526 | [(set_attr "type" "compare") | |
527 | (set_attr "length" "4,8")]) | |
528 | ||
529 | (define_split | |
530 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
531 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
532 | (const_int 0))) | |
533 | (clobber (match_scratch:SI 2 ""))] | |
534 | "reload_completed" | |
535 | [(set (match_dup 2) | |
536 | (zero_extend:SI (match_dup 1))) | |
537 | (set (match_dup 0) | |
538 | (compare:CC (match_dup 2) | |
539 | (const_int 0)))] | |
540 | "") | |
1fd4e8c1 RK |
541 | |
542 | (define_insn "" | |
9ebbca7d GK |
543 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
544 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 545 | (const_int 0))) |
9ebbca7d | 546 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
547 | (zero_extend:SI (match_dup 1)))] |
548 | "" | |
9ebbca7d GK |
549 | "@ |
550 | {andil.|andi.} %0,%1,0xff | |
551 | #" | |
552 | [(set_attr "type" "compare") | |
553 | (set_attr "length" "4,8")]) | |
554 | ||
555 | (define_split | |
556 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
557 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
558 | (const_int 0))) | |
559 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
560 | (zero_extend:SI (match_dup 1)))] | |
561 | "reload_completed" | |
562 | [(set (match_dup 0) | |
563 | (zero_extend:SI (match_dup 1))) | |
564 | (set (match_dup 2) | |
565 | (compare:CC (match_dup 0) | |
566 | (const_int 0)))] | |
567 | "") | |
1fd4e8c1 | 568 | |
51b8fc2c RK |
569 | (define_expand "extendqisi2" |
570 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
571 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
572 | "" | |
573 | " | |
574 | { | |
575 | if (TARGET_POWERPC) | |
576 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
577 | else if (TARGET_POWER) | |
578 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
579 | else | |
580 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
581 | DONE; | |
582 | }") | |
583 | ||
584 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
585 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
586 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 587 | "TARGET_POWERPC" |
2bee0449 | 588 | "extsb %0,%1") |
51b8fc2c RK |
589 | |
590 | (define_insn "" | |
9ebbca7d GK |
591 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
592 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 593 | (const_int 0))) |
9ebbca7d | 594 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 595 | "TARGET_POWERPC" |
9ebbca7d GK |
596 | "@ |
597 | extsb. %2,%1 | |
598 | #" | |
599 | [(set_attr "type" "compare") | |
600 | (set_attr "length" "4,8")]) | |
601 | ||
602 | (define_split | |
603 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
604 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
605 | (const_int 0))) | |
606 | (clobber (match_scratch:SI 2 ""))] | |
607 | "TARGET_POWERPC && reload_completed" | |
608 | [(set (match_dup 2) | |
609 | (sign_extend:SI (match_dup 1))) | |
610 | (set (match_dup 0) | |
611 | (compare:CC (match_dup 2) | |
612 | (const_int 0)))] | |
613 | "") | |
51b8fc2c RK |
614 | |
615 | (define_insn "" | |
9ebbca7d GK |
616 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
617 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 618 | (const_int 0))) |
9ebbca7d | 619 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
620 | (sign_extend:SI (match_dup 1)))] |
621 | "TARGET_POWERPC" | |
9ebbca7d GK |
622 | "@ |
623 | extsb. %0,%1 | |
624 | #" | |
625 | [(set_attr "type" "compare") | |
626 | (set_attr "length" "4,8")]) | |
627 | ||
628 | (define_split | |
629 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
630 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
631 | (const_int 0))) | |
632 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
633 | (sign_extend:SI (match_dup 1)))] | |
634 | "TARGET_POWERPC && reload_completed" | |
635 | [(set (match_dup 0) | |
636 | (sign_extend:SI (match_dup 1))) | |
637 | (set (match_dup 2) | |
638 | (compare:CC (match_dup 0) | |
639 | (const_int 0)))] | |
640 | "") | |
51b8fc2c RK |
641 | |
642 | (define_expand "extendqisi2_power" | |
643 | [(parallel [(set (match_dup 2) | |
644 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
645 | (const_int 24))) | |
646 | (clobber (scratch:SI))]) | |
647 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
648 | (ashiftrt:SI (match_dup 2) | |
649 | (const_int 24))) | |
650 | (clobber (scratch:SI))])] | |
651 | "TARGET_POWER" | |
652 | " | |
653 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
654 | operands[2] = gen_reg_rtx (SImode); }") | |
655 | ||
656 | (define_expand "extendqisi2_no_power" | |
657 | [(set (match_dup 2) | |
658 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
659 | (const_int 24))) | |
660 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
661 | (ashiftrt:SI (match_dup 2) | |
662 | (const_int 24)))] | |
663 | "! TARGET_POWER && ! TARGET_POWERPC" | |
664 | " | |
665 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
666 | operands[2] = gen_reg_rtx (SImode); }") | |
667 | ||
1fd4e8c1 | 668 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
669 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
670 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
671 | "" |
672 | "") | |
673 | ||
674 | (define_insn "" | |
cd2b37d9 | 675 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
676 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
677 | "" | |
678 | "@ | |
679 | lbz%U1%X1 %0,%1 | |
005a35b9 | 680 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
681 | [(set_attr "type" "load,*")]) |
682 | ||
683 | (define_insn "" | |
9ebbca7d GK |
684 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
685 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 686 | (const_int 0))) |
9ebbca7d | 687 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 688 | "" |
9ebbca7d GK |
689 | "@ |
690 | {andil.|andi.} %2,%1,0xff | |
691 | #" | |
692 | [(set_attr "type" "compare") | |
693 | (set_attr "length" "4,8")]) | |
694 | ||
695 | (define_split | |
696 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
697 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
698 | (const_int 0))) | |
699 | (clobber (match_scratch:HI 2 ""))] | |
700 | "reload_completed" | |
701 | [(set (match_dup 2) | |
702 | (zero_extend:HI (match_dup 1))) | |
703 | (set (match_dup 0) | |
704 | (compare:CC (match_dup 2) | |
705 | (const_int 0)))] | |
706 | "") | |
1fd4e8c1 | 707 | |
51b8fc2c | 708 | (define_insn "" |
9ebbca7d GK |
709 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
710 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 711 | (const_int 0))) |
9ebbca7d | 712 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
713 | (zero_extend:HI (match_dup 1)))] |
714 | "" | |
9ebbca7d GK |
715 | "@ |
716 | {andil.|andi.} %0,%1,0xff | |
717 | #" | |
718 | [(set_attr "type" "compare") | |
719 | (set_attr "length" "4,8")]) | |
720 | ||
721 | (define_split | |
722 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
723 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
724 | (const_int 0))) | |
725 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
726 | (zero_extend:HI (match_dup 1)))] | |
727 | "reload_completed" | |
728 | [(set (match_dup 0) | |
729 | (zero_extend:HI (match_dup 1))) | |
730 | (set (match_dup 2) | |
731 | (compare:CC (match_dup 0) | |
732 | (const_int 0)))] | |
733 | "") | |
815cdc52 MM |
734 | |
735 | (define_expand "extendqihi2" | |
736 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
737 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
738 | "" | |
739 | " | |
740 | { | |
741 | if (TARGET_POWERPC) | |
742 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
743 | else if (TARGET_POWER) | |
744 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
745 | else | |
746 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
747 | DONE; | |
748 | }") | |
749 | ||
750 | (define_insn "extendqihi2_ppc" | |
751 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
752 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
753 | "TARGET_POWERPC" | |
754 | "extsb %0,%1") | |
755 | ||
756 | (define_insn "" | |
9ebbca7d GK |
757 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
758 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 759 | (const_int 0))) |
9ebbca7d | 760 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 761 | "TARGET_POWERPC" |
9ebbca7d GK |
762 | "@ |
763 | extsb. %2,%1 | |
764 | #" | |
765 | [(set_attr "type" "compare") | |
766 | (set_attr "length" "4,8")]) | |
767 | ||
768 | (define_split | |
769 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
770 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
771 | (const_int 0))) | |
772 | (clobber (match_scratch:HI 2 ""))] | |
773 | "TARGET_POWERPC && reload_completed" | |
774 | [(set (match_dup 2) | |
775 | (sign_extend:HI (match_dup 1))) | |
776 | (set (match_dup 0) | |
777 | (compare:CC (match_dup 2) | |
778 | (const_int 0)))] | |
779 | "") | |
815cdc52 MM |
780 | |
781 | (define_insn "" | |
9ebbca7d GK |
782 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
783 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 784 | (const_int 0))) |
9ebbca7d | 785 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
786 | (sign_extend:HI (match_dup 1)))] |
787 | "TARGET_POWERPC" | |
9ebbca7d GK |
788 | "@ |
789 | extsb. %0,%1 | |
790 | #" | |
791 | [(set_attr "type" "compare") | |
792 | (set_attr "length" "4,8")]) | |
793 | ||
794 | (define_split | |
795 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
796 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
797 | (const_int 0))) | |
798 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
799 | (sign_extend:HI (match_dup 1)))] | |
800 | "TARGET_POWERPC && reload_completed" | |
801 | [(set (match_dup 0) | |
802 | (sign_extend:HI (match_dup 1))) | |
803 | (set (match_dup 2) | |
804 | (compare:CC (match_dup 0) | |
805 | (const_int 0)))] | |
806 | "") | |
51b8fc2c RK |
807 | |
808 | (define_expand "extendqihi2_power" | |
809 | [(parallel [(set (match_dup 2) | |
810 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
811 | (const_int 24))) | |
812 | (clobber (scratch:SI))]) | |
813 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
814 | (ashiftrt:SI (match_dup 2) | |
815 | (const_int 24))) | |
816 | (clobber (scratch:SI))])] | |
817 | "TARGET_POWER" | |
818 | " | |
819 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
820 | operands[1] = gen_lowpart (SImode, operands[1]); | |
821 | operands[2] = gen_reg_rtx (SImode); }") | |
822 | ||
823 | (define_expand "extendqihi2_no_power" | |
824 | [(set (match_dup 2) | |
825 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
826 | (const_int 24))) | |
827 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
828 | (ashiftrt:SI (match_dup 2) | |
829 | (const_int 24)))] | |
830 | "! TARGET_POWER && ! TARGET_POWERPC" | |
831 | " | |
832 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
833 | operands[1] = gen_lowpart (SImode, operands[1]); | |
834 | operands[2] = gen_reg_rtx (SImode); }") | |
835 | ||
1fd4e8c1 | 836 | (define_expand "zero_extendhisi2" |
5f243543 | 837 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 838 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
839 | "" |
840 | "") | |
841 | ||
842 | (define_insn "" | |
cd2b37d9 | 843 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
844 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
845 | "" | |
846 | "@ | |
847 | lhz%U1%X1 %0,%1 | |
005a35b9 | 848 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
849 | [(set_attr "type" "load,*")]) |
850 | ||
851 | (define_insn "" | |
9ebbca7d GK |
852 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
853 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 854 | (const_int 0))) |
9ebbca7d | 855 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 856 | "" |
9ebbca7d GK |
857 | "@ |
858 | {andil.|andi.} %2,%1,0xffff | |
859 | #" | |
860 | [(set_attr "type" "compare") | |
861 | (set_attr "length" "4,8")]) | |
862 | ||
863 | (define_split | |
864 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
865 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
866 | (const_int 0))) | |
867 | (clobber (match_scratch:SI 2 ""))] | |
868 | "reload_completed" | |
869 | [(set (match_dup 2) | |
870 | (zero_extend:SI (match_dup 1))) | |
871 | (set (match_dup 0) | |
872 | (compare:CC (match_dup 2) | |
873 | (const_int 0)))] | |
874 | "") | |
1fd4e8c1 RK |
875 | |
876 | (define_insn "" | |
9ebbca7d GK |
877 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
878 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 879 | (const_int 0))) |
9ebbca7d | 880 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
881 | (zero_extend:SI (match_dup 1)))] |
882 | "" | |
9ebbca7d GK |
883 | "@ |
884 | {andil.|andi.} %0,%1,0xffff | |
885 | #" | |
886 | [(set_attr "type" "compare") | |
887 | (set_attr "length" "4,8")]) | |
888 | ||
889 | (define_split | |
890 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
891 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
892 | (const_int 0))) | |
893 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
894 | (zero_extend:SI (match_dup 1)))] | |
895 | "reload_completed" | |
896 | [(set (match_dup 0) | |
897 | (zero_extend:SI (match_dup 1))) | |
898 | (set (match_dup 2) | |
899 | (compare:CC (match_dup 0) | |
900 | (const_int 0)))] | |
901 | "") | |
1fd4e8c1 RK |
902 | |
903 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
904 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
905 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
906 | "" |
907 | "") | |
908 | ||
909 | (define_insn "" | |
cd2b37d9 | 910 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
911 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
912 | "" | |
913 | "@ | |
914 | lha%U1%X1 %0,%1 | |
ca7f5001 | 915 | {exts|extsh} %0,%1" |
b54cf83a | 916 | [(set_attr "type" "load_ext,*")]) |
1fd4e8c1 RK |
917 | |
918 | (define_insn "" | |
9ebbca7d GK |
919 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
920 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 921 | (const_int 0))) |
9ebbca7d | 922 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 923 | "" |
9ebbca7d GK |
924 | "@ |
925 | {exts.|extsh.} %2,%1 | |
926 | #" | |
927 | [(set_attr "type" "compare") | |
928 | (set_attr "length" "4,8")]) | |
929 | ||
930 | (define_split | |
931 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
932 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
933 | (const_int 0))) | |
934 | (clobber (match_scratch:SI 2 ""))] | |
935 | "reload_completed" | |
936 | [(set (match_dup 2) | |
937 | (sign_extend:SI (match_dup 1))) | |
938 | (set (match_dup 0) | |
939 | (compare:CC (match_dup 2) | |
940 | (const_int 0)))] | |
941 | "") | |
1fd4e8c1 RK |
942 | |
943 | (define_insn "" | |
9ebbca7d GK |
944 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
945 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 946 | (const_int 0))) |
9ebbca7d | 947 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
948 | (sign_extend:SI (match_dup 1)))] |
949 | "" | |
9ebbca7d GK |
950 | "@ |
951 | {exts.|extsh.} %0,%1 | |
952 | #" | |
953 | [(set_attr "type" "compare") | |
954 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 955 | \f |
9ebbca7d GK |
956 | (define_split |
957 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
958 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
959 | (const_int 0))) | |
960 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
961 | (sign_extend:SI (match_dup 1)))] | |
962 | "reload_completed" | |
963 | [(set (match_dup 0) | |
964 | (sign_extend:SI (match_dup 1))) | |
965 | (set (match_dup 2) | |
966 | (compare:CC (match_dup 0) | |
967 | (const_int 0)))] | |
968 | "") | |
969 | ||
1fd4e8c1 | 970 | ;; Fixed-point arithmetic insns. |
deb9225a RK |
971 | |
972 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
973 | ;; allowing register zero as source. | |
7cd5235b MM |
974 | (define_expand "addsi3" |
975 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
976 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 977 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
7cd5235b MM |
978 | "" |
979 | " | |
980 | { | |
677a9668 DE |
981 | if (GET_CODE (operands[2]) == CONST_INT |
982 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 983 | { |
677a9668 | 984 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
985 | ? operands[0] : gen_reg_rtx (SImode)); |
986 | ||
2bfcf297 | 987 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 988 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 989 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
7cd5235b | 990 | |
9ebbca7d GK |
991 | /* The ordering here is important for the prolog expander. |
992 | When space is allocated from the stack, adding 'low' first may | |
993 | produce a temporary deallocation (which would be bad). */ | |
2bfcf297 | 994 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest))); |
7cd5235b MM |
995 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); |
996 | DONE; | |
997 | } | |
998 | }") | |
999 | ||
1000 | (define_insn "*addsi3_internal1" | |
1001 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
1002 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 1003 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1004 | "" |
1005 | "@ | |
deb9225a RK |
1006 | {cax|add} %0,%1,%2 |
1007 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1008 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1009 | {cau|addis} %0,%1,%v2" |
1010 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1011 | |
ee890fe2 SS |
1012 | (define_insn "addsi3_high" |
1013 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1014 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1015 | (high:SI (match_operand 2 "" ""))))] | |
1016 | "TARGET_MACHO && !TARGET_64BIT" | |
1017 | "{cau|addis} %0,%1,ha16(%2)" | |
1018 | [(set_attr "length" "4")]) | |
1019 | ||
7cd5235b | 1020 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1021 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1022 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1023 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1024 | (const_int 0))) |
cb8cc086 | 1025 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
4b8a63d6 | 1026 | "TARGET_32BIT" |
deb9225a RK |
1027 | "@ |
1028 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1029 | {ai.|addic.} %3,%1,%2 |
1030 | # | |
1031 | #" | |
a62bfff2 | 1032 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1033 | (set_attr "length" "4,4,8,8")]) |
1034 | ||
1035 | (define_split | |
1036 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1037 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1038 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1039 | (const_int 0))) | |
1040 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 1041 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1042 | [(set (match_dup 3) |
1043 | (plus:SI (match_dup 1) | |
1044 | (match_dup 2))) | |
1045 | (set (match_dup 0) | |
1046 | (compare:CC (match_dup 3) | |
1047 | (const_int 0)))] | |
1048 | "") | |
7e69e155 | 1049 | |
7cd5235b | 1050 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1051 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1052 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1053 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1054 | (const_int 0))) |
cb8cc086 MM |
1055 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1056 | (plus:SI (match_dup 1) | |
1057 | (match_dup 2)))] | |
4b8a63d6 | 1058 | "TARGET_32BIT" |
deb9225a RK |
1059 | "@ |
1060 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1061 | {ai.|addic.} %0,%1,%2 |
1062 | # | |
1063 | #" | |
a62bfff2 | 1064 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1065 | (set_attr "length" "4,4,8,8")]) |
1066 | ||
1067 | (define_split | |
1068 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1069 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1070 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1071 | (const_int 0))) | |
1072 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1073 | (plus:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 1074 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1075 | [(set (match_dup 0) |
1076 | (plus:SI (match_dup 1) | |
1077 | (match_dup 2))) | |
1078 | (set (match_dup 3) | |
1079 | (compare:CC (match_dup 0) | |
1080 | (const_int 0)))] | |
1081 | "") | |
7e69e155 | 1082 | |
f357808b RK |
1083 | ;; Split an add that we can't do in one insn into two insns, each of which |
1084 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1085 | ;; add should be last in case the result gets used in an address. | |
1086 | ||
1087 | (define_split | |
cd2b37d9 RK |
1088 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1089 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1090 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1091 | "" |
f357808b RK |
1092 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1093 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1094 | " | |
1fd4e8c1 | 1095 | { |
2bfcf297 | 1096 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1097 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 1098 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
1fd4e8c1 | 1099 | |
2bfcf297 | 1100 | operands[3] = GEN_INT (rest); |
e6ca2c17 | 1101 | operands[4] = GEN_INT (low); |
1fd4e8c1 RK |
1102 | }") |
1103 | ||
8de2a197 | 1104 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1105 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1106 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1107 | "" |
ca7f5001 RK |
1108 | "nor %0,%1,%1") |
1109 | ||
1110 | (define_insn "" | |
52d3af72 DE |
1111 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1112 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1113 | (const_int 0))) |
52d3af72 | 1114 | (clobber (match_scratch:SI 2 "=r,r"))] |
4b8a63d6 | 1115 | "TARGET_32BIT" |
52d3af72 DE |
1116 | "@ |
1117 | nor. %2,%1,%1 | |
1118 | #" | |
1119 | [(set_attr "type" "compare") | |
1120 | (set_attr "length" "4,8")]) | |
1121 | ||
1122 | (define_split | |
1123 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1124 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1125 | (const_int 0))) | |
1126 | (clobber (match_scratch:SI 2 ""))] | |
4b8a63d6 | 1127 | "TARGET_32BIT && reload_completed" |
52d3af72 DE |
1128 | [(set (match_dup 2) |
1129 | (not:SI (match_dup 1))) | |
1130 | (set (match_dup 0) | |
1131 | (compare:CC (match_dup 2) | |
1132 | (const_int 0)))] | |
1133 | "") | |
ca7f5001 RK |
1134 | |
1135 | (define_insn "" | |
52d3af72 DE |
1136 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1137 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1138 | (const_int 0))) |
52d3af72 | 1139 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1140 | (not:SI (match_dup 1)))] |
4b8a63d6 | 1141 | "TARGET_32BIT" |
52d3af72 DE |
1142 | "@ |
1143 | nor. %0,%1,%1 | |
1144 | #" | |
1145 | [(set_attr "type" "compare") | |
1146 | (set_attr "length" "4,8")]) | |
1147 | ||
1148 | (define_split | |
1149 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1150 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1151 | (const_int 0))) | |
1cb18e3c | 1152 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
52d3af72 | 1153 | (not:SI (match_dup 1)))] |
4b8a63d6 | 1154 | "TARGET_32BIT && reload_completed" |
52d3af72 DE |
1155 | [(set (match_dup 0) |
1156 | (not:SI (match_dup 1))) | |
1157 | (set (match_dup 2) | |
1158 | (compare:CC (match_dup 0) | |
1159 | (const_int 0)))] | |
1160 | "") | |
1fd4e8c1 RK |
1161 | |
1162 | (define_insn "" | |
3d91674b RK |
1163 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1164 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1165 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1166 | "! TARGET_POWERPC" |
ca7f5001 | 1167 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1168 | |
deb9225a RK |
1169 | (define_insn "" |
1170 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1171 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1172 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1173 | "TARGET_POWERPC" | |
1174 | "@ | |
1175 | subf %0,%2,%1 | |
1176 | subfic %0,%2,%1") | |
1177 | ||
1fd4e8c1 | 1178 | (define_insn "" |
cb8cc086 MM |
1179 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1180 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1181 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1182 | (const_int 0))) |
cb8cc086 | 1183 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1184 | "! TARGET_POWERPC" |
cb8cc086 MM |
1185 | "@ |
1186 | {sf.|subfc.} %3,%2,%1 | |
1187 | #" | |
1188 | [(set_attr "type" "compare") | |
1189 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1190 | |
deb9225a | 1191 | (define_insn "" |
cb8cc086 MM |
1192 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1193 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1194 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1195 | (const_int 0))) |
cb8cc086 | 1196 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 1197 | "TARGET_POWERPC && TARGET_32BIT" |
cb8cc086 MM |
1198 | "@ |
1199 | subf. %3,%2,%1 | |
1200 | #" | |
a62bfff2 | 1201 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1202 | (set_attr "length" "4,8")]) |
1203 | ||
1204 | (define_split | |
1205 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1206 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1207 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1208 | (const_int 0))) | |
1209 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 1210 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1211 | [(set (match_dup 3) |
1212 | (minus:SI (match_dup 1) | |
1213 | (match_dup 2))) | |
1214 | (set (match_dup 0) | |
1215 | (compare:CC (match_dup 3) | |
1216 | (const_int 0)))] | |
1217 | "") | |
deb9225a | 1218 | |
1fd4e8c1 | 1219 | (define_insn "" |
cb8cc086 MM |
1220 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1221 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1222 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1223 | (const_int 0))) |
cb8cc086 | 1224 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1225 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1226 | "! TARGET_POWERPC" |
cb8cc086 MM |
1227 | "@ |
1228 | {sf.|subfc.} %0,%2,%1 | |
1229 | #" | |
1230 | [(set_attr "type" "compare") | |
1231 | (set_attr "length" "4,8")]) | |
815cdc52 | 1232 | |
29ae5b89 | 1233 | (define_insn "" |
cb8cc086 MM |
1234 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1235 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1236 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1237 | (const_int 0))) |
cb8cc086 MM |
1238 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1239 | (minus:SI (match_dup 1) | |
1240 | (match_dup 2)))] | |
4b8a63d6 | 1241 | "TARGET_POWERPC && TARGET_32BIT" |
90612787 DE |
1242 | "@ |
1243 | subf. %0,%2,%1 | |
1244 | #" | |
a62bfff2 | 1245 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1246 | (set_attr "length" "4,8")]) |
1247 | ||
1248 | (define_split | |
1249 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1250 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1251 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1252 | (const_int 0))) | |
1253 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1254 | (minus:SI (match_dup 1) | |
1255 | (match_dup 2)))] | |
4b8a63d6 | 1256 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1257 | [(set (match_dup 0) |
1258 | (minus:SI (match_dup 1) | |
1259 | (match_dup 2))) | |
1260 | (set (match_dup 3) | |
1261 | (compare:CC (match_dup 0) | |
1262 | (const_int 0)))] | |
1263 | "") | |
deb9225a | 1264 | |
1fd4e8c1 | 1265 | (define_expand "subsi3" |
cd2b37d9 | 1266 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1267 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
f6bf7de2 | 1268 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
1fd4e8c1 | 1269 | "" |
a0044fb1 RK |
1270 | " |
1271 | { | |
1272 | if (GET_CODE (operands[2]) == CONST_INT) | |
1273 | { | |
1274 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1275 | negate_rtx (SImode, operands[2]))); | |
1276 | DONE; | |
1277 | } | |
1278 | }") | |
1fd4e8c1 RK |
1279 | |
1280 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1281 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1282 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1283 | ;; combine. | |
1fd4e8c1 RK |
1284 | |
1285 | (define_expand "sminsi3" | |
1286 | [(set (match_dup 3) | |
cd2b37d9 | 1287 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1288 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1289 | (const_int 0) | |
1290 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1291 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1292 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1293 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1294 | " |
a3170dc6 AH |
1295 | { |
1296 | if (TARGET_ISEL) | |
1297 | { | |
1298 | operands[2] = force_reg (SImode, operands[2]); | |
1299 | rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); | |
1300 | DONE; | |
1301 | } | |
1302 | ||
1303 | operands[3] = gen_reg_rtx (SImode); | |
1304 | }") | |
1fd4e8c1 | 1305 | |
95ac8e67 RK |
1306 | (define_split |
1307 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1308 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1309 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1310 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1311 | "TARGET_POWER" |
95ac8e67 RK |
1312 | [(set (match_dup 3) |
1313 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1314 | (const_int 0) | |
1315 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1316 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1317 | "") | |
1318 | ||
1fd4e8c1 RK |
1319 | (define_expand "smaxsi3" |
1320 | [(set (match_dup 3) | |
cd2b37d9 | 1321 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1322 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1323 | (const_int 0) | |
1324 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1325 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1326 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1327 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1328 | " |
a3170dc6 AH |
1329 | { |
1330 | if (TARGET_ISEL) | |
1331 | { | |
1332 | operands[2] = force_reg (SImode, operands[2]); | |
1333 | rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); | |
1334 | DONE; | |
1335 | } | |
1336 | operands[3] = gen_reg_rtx (SImode); | |
1337 | }") | |
1fd4e8c1 | 1338 | |
95ac8e67 RK |
1339 | (define_split |
1340 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1341 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1342 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1343 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1344 | "TARGET_POWER" |
95ac8e67 RK |
1345 | [(set (match_dup 3) |
1346 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1347 | (const_int 0) | |
1348 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1349 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1350 | "") | |
1351 | ||
1fd4e8c1 | 1352 | (define_expand "uminsi3" |
cd2b37d9 | 1353 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1354 | (match_dup 5))) |
cd2b37d9 | 1355 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1356 | (match_dup 5))) |
1fd4e8c1 RK |
1357 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1358 | (const_int 0) | |
1359 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1360 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1361 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1362 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1363 | " |
bb68ff55 | 1364 | { |
a3170dc6 AH |
1365 | if (TARGET_ISEL) |
1366 | { | |
1367 | rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]); | |
1368 | DONE; | |
1369 | } | |
bb68ff55 MM |
1370 | operands[3] = gen_reg_rtx (SImode); |
1371 | operands[4] = gen_reg_rtx (SImode); | |
1372 | operands[5] = GEN_INT (-2147483647 - 1); | |
1373 | }") | |
1fd4e8c1 RK |
1374 | |
1375 | (define_expand "umaxsi3" | |
cd2b37d9 | 1376 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1377 | (match_dup 5))) |
cd2b37d9 | 1378 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1379 | (match_dup 5))) |
1fd4e8c1 RK |
1380 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1381 | (const_int 0) | |
1382 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1383 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1384 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1385 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1386 | " |
bb68ff55 | 1387 | { |
a3170dc6 AH |
1388 | if (TARGET_ISEL) |
1389 | { | |
1390 | rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]); | |
1391 | DONE; | |
1392 | } | |
bb68ff55 MM |
1393 | operands[3] = gen_reg_rtx (SImode); |
1394 | operands[4] = gen_reg_rtx (SImode); | |
1395 | operands[5] = GEN_INT (-2147483647 - 1); | |
1396 | }") | |
1fd4e8c1 RK |
1397 | |
1398 | (define_insn "" | |
cd2b37d9 RK |
1399 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1400 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1401 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1402 | (const_int 0) |
1403 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1404 | "TARGET_POWER" |
1fd4e8c1 RK |
1405 | "doz%I2 %0,%1,%2") |
1406 | ||
1407 | (define_insn "" | |
9ebbca7d | 1408 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1409 | (compare:CC |
9ebbca7d GK |
1410 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1411 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1412 | (const_int 0) |
1413 | (minus:SI (match_dup 2) (match_dup 1))) | |
1414 | (const_int 0))) | |
9ebbca7d | 1415 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 1416 | "TARGET_POWER" |
9ebbca7d GK |
1417 | "@ |
1418 | doz%I2. %3,%1,%2 | |
1419 | #" | |
1420 | [(set_attr "type" "delayed_compare") | |
1421 | (set_attr "length" "4,8")]) | |
1422 | ||
1423 | (define_split | |
1424 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1425 | (compare:CC | |
1426 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1427 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1428 | (const_int 0) | |
1429 | (minus:SI (match_dup 2) (match_dup 1))) | |
1430 | (const_int 0))) | |
1431 | (clobber (match_scratch:SI 3 ""))] | |
1432 | "TARGET_POWER && reload_completed" | |
1433 | [(set (match_dup 3) | |
1434 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1435 | (const_int 0) | |
1436 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1437 | (set (match_dup 0) | |
1438 | (compare:CC (match_dup 3) | |
1439 | (const_int 0)))] | |
1440 | "") | |
1fd4e8c1 RK |
1441 | |
1442 | (define_insn "" | |
9ebbca7d | 1443 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1444 | (compare:CC |
9ebbca7d GK |
1445 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1446 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1447 | (const_int 0) |
1448 | (minus:SI (match_dup 2) (match_dup 1))) | |
1449 | (const_int 0))) | |
9ebbca7d | 1450 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1451 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1452 | (const_int 0) | |
1453 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1454 | "TARGET_POWER" |
9ebbca7d GK |
1455 | "@ |
1456 | doz%I2. %0,%1,%2 | |
1457 | #" | |
1458 | [(set_attr "type" "delayed_compare") | |
1459 | (set_attr "length" "4,8")]) | |
1460 | ||
1461 | (define_split | |
1462 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1463 | (compare:CC | |
1464 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1465 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1466 | (const_int 0) | |
1467 | (minus:SI (match_dup 2) (match_dup 1))) | |
1468 | (const_int 0))) | |
1469 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1470 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1471 | (const_int 0) | |
1472 | (minus:SI (match_dup 2) (match_dup 1))))] | |
1473 | "TARGET_POWER && reload_completed" | |
1474 | [(set (match_dup 0) | |
1475 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1476 | (const_int 0) | |
1477 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1478 | (set (match_dup 3) | |
1479 | (compare:CC (match_dup 0) | |
1480 | (const_int 0)))] | |
1481 | "") | |
1fd4e8c1 RK |
1482 | |
1483 | ;; We don't need abs with condition code because such comparisons should | |
1484 | ;; never be done. | |
ea9be077 MM |
1485 | (define_expand "abssi2" |
1486 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1487 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1488 | "" | |
1489 | " | |
1490 | { | |
a3170dc6 AH |
1491 | if (TARGET_ISEL) |
1492 | { | |
1493 | emit_insn (gen_abssi2_isel (operands[0], operands[1])); | |
1494 | DONE; | |
1495 | } | |
1496 | else if (! TARGET_POWER) | |
ea9be077 MM |
1497 | { |
1498 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1499 | DONE; | |
1500 | } | |
1501 | }") | |
1502 | ||
ea112fc4 | 1503 | (define_insn "*abssi2_power" |
cd2b37d9 RK |
1504 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1505 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1506 | "TARGET_POWER" |
1fd4e8c1 RK |
1507 | "abs %0,%1") |
1508 | ||
a3170dc6 AH |
1509 | (define_insn_and_split "abssi2_isel" |
1510 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1511 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8c48b6f5 | 1512 | (clobber (match_scratch:SI 2 "=&b")) |
a3170dc6 AH |
1513 | (clobber (match_scratch:CC 3 "=y"))] |
1514 | "TARGET_ISEL" | |
1515 | "#" | |
1516 | "&& reload_completed" | |
1517 | [(set (match_dup 2) (neg:SI (match_dup 1))) | |
1518 | (set (match_dup 3) | |
1519 | (compare:CC (match_dup 1) | |
1520 | (const_int 0))) | |
1521 | (set (match_dup 0) | |
1522 | (if_then_else:SI (ge (match_dup 3) | |
1523 | (const_int 0)) | |
1524 | (match_dup 1) | |
1525 | (match_dup 2)))] | |
1526 | "") | |
1527 | ||
ea112fc4 | 1528 | (define_insn_and_split "abssi2_nopower" |
ea9be077 | 1529 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1530 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) |
ea9be077 | 1531 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
a3170dc6 | 1532 | "! TARGET_POWER && ! TARGET_ISEL" |
ea112fc4 DE |
1533 | "#" |
1534 | "&& reload_completed" | |
ea9be077 MM |
1535 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1536 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1537 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1538 | "") |
1539 | ||
463b558b | 1540 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1541 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1542 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1543 | "TARGET_POWER" |
1fd4e8c1 RK |
1544 | "nabs %0,%1") |
1545 | ||
ea112fc4 | 1546 | (define_insn_and_split "*nabs_nopower" |
ea9be077 | 1547 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1548 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) |
ea9be077 | 1549 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
0ad91047 | 1550 | "! TARGET_POWER" |
ea112fc4 DE |
1551 | "#" |
1552 | "&& reload_completed" | |
ea9be077 MM |
1553 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1554 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1555 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1556 | "") |
1557 | ||
1fd4e8c1 | 1558 | (define_insn "negsi2" |
cd2b37d9 RK |
1559 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1560 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1561 | "" |
1562 | "neg %0,%1") | |
1563 | ||
1564 | (define_insn "" | |
9ebbca7d GK |
1565 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1566 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1567 | (const_int 0))) |
9ebbca7d | 1568 | (clobber (match_scratch:SI 2 "=r,r"))] |
4b8a63d6 | 1569 | "TARGET_32BIT" |
9ebbca7d GK |
1570 | "@ |
1571 | neg. %2,%1 | |
1572 | #" | |
a62bfff2 | 1573 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1574 | (set_attr "length" "4,8")]) |
1575 | ||
1576 | (define_split | |
1577 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1578 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1579 | (const_int 0))) | |
1580 | (clobber (match_scratch:SI 2 ""))] | |
4b8a63d6 | 1581 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
1582 | [(set (match_dup 2) |
1583 | (neg:SI (match_dup 1))) | |
1584 | (set (match_dup 0) | |
1585 | (compare:CC (match_dup 2) | |
1586 | (const_int 0)))] | |
1587 | "") | |
1fd4e8c1 RK |
1588 | |
1589 | (define_insn "" | |
9ebbca7d GK |
1590 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1591 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1592 | (const_int 0))) |
9ebbca7d | 1593 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1594 | (neg:SI (match_dup 1)))] |
4b8a63d6 | 1595 | "TARGET_32BIT" |
9ebbca7d GK |
1596 | "@ |
1597 | neg. %0,%1 | |
1598 | #" | |
a62bfff2 | 1599 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1600 | (set_attr "length" "4,8")]) |
1601 | ||
1602 | (define_split | |
1603 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1604 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1605 | (const_int 0))) | |
1606 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1607 | (neg:SI (match_dup 1)))] | |
4b8a63d6 | 1608 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
1609 | [(set (match_dup 0) |
1610 | (neg:SI (match_dup 1))) | |
1611 | (set (match_dup 2) | |
1612 | (compare:CC (match_dup 0) | |
1613 | (const_int 0)))] | |
1614 | "") | |
1fd4e8c1 | 1615 | |
1b1edcfa DE |
1616 | (define_insn "clzsi2" |
1617 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1618 | (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1619 | "" | |
1620 | "{cntlz|cntlzw} %0,%1") | |
1621 | ||
1622 | (define_expand "ctzsi2" | |
4977bab6 | 1623 | [(set (match_dup 2) |
1b1edcfa | 1624 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
4977bab6 | 1625 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) |
1b1edcfa DE |
1626 | (match_dup 2))) |
1627 | (clobber (scratch:CC))]) | |
d865b122 | 1628 | (set (match_dup 4) (clz:SI (match_dup 3))) |
4977bab6 | 1629 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 1630 | (minus:SI (const_int 31) (match_dup 4)))] |
1fd4e8c1 | 1631 | "" |
4977bab6 ZW |
1632 | { |
1633 | operands[2] = gen_reg_rtx (SImode); | |
1634 | operands[3] = gen_reg_rtx (SImode); | |
1635 | operands[4] = gen_reg_rtx (SImode); | |
1636 | }) | |
6ae08853 | 1637 | |
1b1edcfa DE |
1638 | (define_expand "ffssi2" |
1639 | [(set (match_dup 2) | |
1640 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
1641 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) | |
1642 | (match_dup 2))) | |
1643 | (clobber (scratch:CC))]) | |
1644 | (set (match_dup 4) (clz:SI (match_dup 3))) | |
1645 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1646 | (minus:SI (const_int 32) (match_dup 4)))] | |
4977bab6 | 1647 | "" |
1b1edcfa DE |
1648 | { |
1649 | operands[2] = gen_reg_rtx (SImode); | |
1650 | operands[3] = gen_reg_rtx (SImode); | |
1651 | operands[4] = gen_reg_rtx (SImode); | |
1652 | }) | |
6ae08853 | 1653 | |
ca7f5001 RK |
1654 | (define_expand "mulsi3" |
1655 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1656 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
1657 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
1658 | "" | |
1659 | " | |
1660 | { | |
1661 | if (TARGET_POWER) | |
68b40e7e | 1662 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 1663 | else |
68b40e7e | 1664 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
1665 | DONE; |
1666 | }") | |
1667 | ||
68b40e7e | 1668 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
1669 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1670 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
1671 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
1672 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
1673 | "TARGET_POWER" |
1674 | "@ | |
1675 | {muls|mullw} %0,%1,%2 | |
1676 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1677 | [(set (attr "type") |
c859cda6 DJ |
1678 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1679 | (const_string "imul3") | |
6ae08853 | 1680 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1681 | (const_string "imul2")] |
1682 | (const_string "imul")))]) | |
ca7f5001 | 1683 | |
68b40e7e | 1684 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
1685 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1686 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1687 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 1688 | "! TARGET_POWER" |
1fd4e8c1 | 1689 | "@ |
d904e9ed RK |
1690 | {muls|mullw} %0,%1,%2 |
1691 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1692 | [(set (attr "type") |
c859cda6 DJ |
1693 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1694 | (const_string "imul3") | |
6ae08853 | 1695 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1696 | (const_string "imul2")] |
1697 | (const_string "imul")))]) | |
1fd4e8c1 | 1698 | |
9259f3b0 | 1699 | (define_insn "*mulsi3_mq_internal1" |
9ebbca7d GK |
1700 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1701 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1702 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1703 | (const_int 0))) |
9ebbca7d GK |
1704 | (clobber (match_scratch:SI 3 "=r,r")) |
1705 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 1706 | "TARGET_POWER" |
9ebbca7d GK |
1707 | "@ |
1708 | {muls.|mullw.} %3,%1,%2 | |
1709 | #" | |
9259f3b0 | 1710 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1711 | (set_attr "length" "4,8")]) |
1712 | ||
1713 | (define_split | |
1714 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1715 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1716 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1717 | (const_int 0))) | |
1718 | (clobber (match_scratch:SI 3 "")) | |
1719 | (clobber (match_scratch:SI 4 ""))] | |
1720 | "TARGET_POWER && reload_completed" | |
1721 | [(parallel [(set (match_dup 3) | |
1722 | (mult:SI (match_dup 1) (match_dup 2))) | |
1723 | (clobber (match_dup 4))]) | |
1724 | (set (match_dup 0) | |
1725 | (compare:CC (match_dup 3) | |
1726 | (const_int 0)))] | |
1727 | "") | |
ca7f5001 | 1728 | |
9259f3b0 | 1729 | (define_insn "*mulsi3_no_mq_internal1" |
9ebbca7d GK |
1730 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1731 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1732 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1733 | (const_int 0))) |
9ebbca7d | 1734 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 1735 | "! TARGET_POWER" |
9ebbca7d GK |
1736 | "@ |
1737 | {muls.|mullw.} %3,%1,%2 | |
1738 | #" | |
9259f3b0 | 1739 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1740 | (set_attr "length" "4,8")]) |
1741 | ||
1742 | (define_split | |
1743 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1744 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1745 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1746 | (const_int 0))) | |
1747 | (clobber (match_scratch:SI 3 ""))] | |
1748 | "! TARGET_POWER && reload_completed" | |
1749 | [(set (match_dup 3) | |
1750 | (mult:SI (match_dup 1) (match_dup 2))) | |
1751 | (set (match_dup 0) | |
1752 | (compare:CC (match_dup 3) | |
1753 | (const_int 0)))] | |
1754 | "") | |
1fd4e8c1 | 1755 | |
9259f3b0 | 1756 | (define_insn "*mulsi3_mq_internal2" |
9ebbca7d GK |
1757 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1758 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1759 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1760 | (const_int 0))) |
9ebbca7d | 1761 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 1762 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 1763 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 1764 | "TARGET_POWER" |
9ebbca7d GK |
1765 | "@ |
1766 | {muls.|mullw.} %0,%1,%2 | |
1767 | #" | |
9259f3b0 | 1768 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1769 | (set_attr "length" "4,8")]) |
1770 | ||
1771 | (define_split | |
1772 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1773 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1774 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1775 | (const_int 0))) | |
1776 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1777 | (mult:SI (match_dup 1) (match_dup 2))) | |
1778 | (clobber (match_scratch:SI 4 ""))] | |
1779 | "TARGET_POWER && reload_completed" | |
1780 | [(parallel [(set (match_dup 0) | |
1781 | (mult:SI (match_dup 1) (match_dup 2))) | |
1782 | (clobber (match_dup 4))]) | |
1783 | (set (match_dup 3) | |
1784 | (compare:CC (match_dup 0) | |
1785 | (const_int 0)))] | |
1786 | "") | |
ca7f5001 | 1787 | |
9259f3b0 | 1788 | (define_insn "*mulsi3_no_mq_internal2" |
9ebbca7d GK |
1789 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1790 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1791 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1792 | (const_int 0))) |
9ebbca7d | 1793 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 1794 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 1795 | "! TARGET_POWER" |
9ebbca7d GK |
1796 | "@ |
1797 | {muls.|mullw.} %0,%1,%2 | |
1798 | #" | |
9259f3b0 | 1799 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1800 | (set_attr "length" "4,8")]) |
1801 | ||
1802 | (define_split | |
1803 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1804 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1805 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1806 | (const_int 0))) | |
1807 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1808 | (mult:SI (match_dup 1) (match_dup 2)))] | |
1809 | "! TARGET_POWER && reload_completed" | |
1810 | [(set (match_dup 0) | |
1811 | (mult:SI (match_dup 1) (match_dup 2))) | |
1812 | (set (match_dup 3) | |
1813 | (compare:CC (match_dup 0) | |
1814 | (const_int 0)))] | |
1815 | "") | |
1fd4e8c1 RK |
1816 | |
1817 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
1818 | ;; 0 and remainder to operand 3. | |
1819 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
1820 | ||
8ffd9c51 RK |
1821 | (define_expand "divmodsi4" |
1822 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1823 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1824 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
bb157ff4 | 1825 | (set (match_operand:SI 3 "register_operand" "") |
8ffd9c51 RK |
1826 | (mod:SI (match_dup 1) (match_dup 2)))])] |
1827 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1828 | " | |
1829 | { | |
1830 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1831 | { | |
39403d82 DE |
1832 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1833 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1834 | emit_insn (gen_divss_call ()); |
39403d82 DE |
1835 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1836 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
1837 | DONE; |
1838 | } | |
1839 | }") | |
deb9225a | 1840 | |
bb157ff4 | 1841 | (define_insn "*divmodsi4_internal" |
cd2b37d9 RK |
1842 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1843 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1844 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
bb157ff4 | 1845 | (set (match_operand:SI 3 "register_operand" "=q") |
1fd4e8c1 | 1846 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 1847 | "TARGET_POWER" |
cfb557c4 RK |
1848 | "divs %0,%1,%2" |
1849 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 1850 | |
8ffd9c51 RK |
1851 | (define_expand "udivsi3" |
1852 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1853 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1854 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
1855 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1856 | " | |
1857 | { | |
1858 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1859 | { | |
39403d82 DE |
1860 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1861 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1862 | emit_insn (gen_quous_call ()); |
39403d82 | 1863 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1864 | DONE; |
1865 | } | |
f192bf8b DE |
1866 | else if (TARGET_POWER) |
1867 | { | |
1868 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
1869 | DONE; | |
1870 | } | |
8ffd9c51 | 1871 | }") |
deb9225a | 1872 | |
f192bf8b DE |
1873 | (define_insn "udivsi3_mq" |
1874 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1875 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1876 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1877 | (clobber (match_scratch:SI 3 "=q"))] | |
1878 | "TARGET_POWERPC && TARGET_POWER" | |
1879 | "divwu %0,%1,%2" | |
1880 | [(set_attr "type" "idiv")]) | |
1881 | ||
1882 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
1883 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1884 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1885 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 1886 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 1887 | "divwu %0,%1,%2" |
ca7f5001 RK |
1888 | [(set_attr "type" "idiv")]) |
1889 | ||
1fd4e8c1 | 1890 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 1891 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
1892 | ;; used; for PowerPC, force operands into register and do a normal divide; |
1893 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 1894 | (define_expand "divsi3" |
cd2b37d9 RK |
1895 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1896 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
1897 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
1898 | "" | |
1899 | " | |
1900 | { | |
ca7f5001 | 1901 | if (GET_CODE (operands[2]) == CONST_INT |
2bfcf297 | 1902 | && INTVAL (operands[2]) > 0 |
ca7f5001 RK |
1903 | && exact_log2 (INTVAL (operands[2])) >= 0) |
1904 | ; | |
b6c9286a | 1905 | else if (TARGET_POWERPC) |
f192bf8b DE |
1906 | { |
1907 | operands[2] = force_reg (SImode, operands[2]); | |
1908 | if (TARGET_POWER) | |
1909 | { | |
1910 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
1911 | DONE; | |
1912 | } | |
1913 | } | |
b6c9286a | 1914 | else if (TARGET_POWER) |
1fd4e8c1 | 1915 | FAIL; |
405c5495 | 1916 | else |
8ffd9c51 | 1917 | { |
39403d82 DE |
1918 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1919 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1920 | emit_insn (gen_quoss_call ()); |
39403d82 | 1921 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1922 | DONE; |
1923 | } | |
1fd4e8c1 RK |
1924 | }") |
1925 | ||
f192bf8b DE |
1926 | (define_insn "divsi3_mq" |
1927 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1928 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1929 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1930 | (clobber (match_scratch:SI 3 "=q"))] | |
1931 | "TARGET_POWERPC && TARGET_POWER" | |
1932 | "divw %0,%1,%2" | |
1933 | [(set_attr "type" "idiv")]) | |
1934 | ||
1935 | (define_insn "*divsi3_no_mq" | |
1936 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1937 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1938 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1939 | "TARGET_POWERPC && ! TARGET_POWER" | |
1940 | "divw %0,%1,%2" | |
1941 | [(set_attr "type" "idiv")]) | |
1942 | ||
1fd4e8c1 | 1943 | (define_expand "modsi3" |
85644414 RK |
1944 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
1945 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 1946 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 1947 | "" |
1fd4e8c1 RK |
1948 | " |
1949 | { | |
481c7efa | 1950 | int i; |
39b52ba2 RK |
1951 | rtx temp1; |
1952 | rtx temp2; | |
1953 | ||
2bfcf297 | 1954 | if (GET_CODE (operands[2]) != CONST_INT |
a65c591c | 1955 | || INTVAL (operands[2]) <= 0 |
2bfcf297 | 1956 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) |
39b52ba2 RK |
1957 | FAIL; |
1958 | ||
1959 | temp1 = gen_reg_rtx (SImode); | |
1960 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 1961 | |
85644414 | 1962 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 1963 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
1964 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
1965 | DONE; | |
1fd4e8c1 RK |
1966 | }") |
1967 | ||
1968 | (define_insn "" | |
cd2b37d9 RK |
1969 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1970 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
1971 | (match_operand:SI 2 "exact_log2_cint_operand" "N")))] |
1972 | "" | |
ca7f5001 | 1973 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 1974 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
1975 | |
1976 | (define_insn "" | |
9ebbca7d GK |
1977 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1978 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 1979 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 1980 | (const_int 0))) |
9ebbca7d | 1981 | (clobber (match_scratch:SI 3 "=r,r"))] |
2bfcf297 | 1982 | "" |
9ebbca7d GK |
1983 | "@ |
1984 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
1985 | #" | |
b19003d8 | 1986 | [(set_attr "type" "compare") |
9ebbca7d GK |
1987 | (set_attr "length" "8,12")]) |
1988 | ||
1989 | (define_split | |
1990 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1991 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 1992 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
1993 | (const_int 0))) |
1994 | (clobber (match_scratch:SI 3 ""))] | |
2bfcf297 | 1995 | "reload_completed" |
9ebbca7d GK |
1996 | [(set (match_dup 3) |
1997 | (div:SI (match_dup 1) (match_dup 2))) | |
1998 | (set (match_dup 0) | |
1999 | (compare:CC (match_dup 3) | |
2000 | (const_int 0)))] | |
2001 | "") | |
1fd4e8c1 RK |
2002 | |
2003 | (define_insn "" | |
9ebbca7d GK |
2004 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2005 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2006 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2007 | (const_int 0))) |
9ebbca7d | 2008 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2009 | (div:SI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 2010 | "" |
9ebbca7d GK |
2011 | "@ |
2012 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2013 | #" | |
b19003d8 | 2014 | [(set_attr "type" "compare") |
9ebbca7d GK |
2015 | (set_attr "length" "8,12")]) |
2016 | ||
2017 | (define_split | |
2018 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2019 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2020 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2021 | (const_int 0))) |
2022 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2023 | (div:SI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2024 | "reload_completed" |
9ebbca7d GK |
2025 | [(set (match_dup 0) |
2026 | (div:SI (match_dup 1) (match_dup 2))) | |
2027 | (set (match_dup 3) | |
2028 | (compare:CC (match_dup 0) | |
2029 | (const_int 0)))] | |
2030 | "") | |
1fd4e8c1 RK |
2031 | |
2032 | (define_insn "" | |
cd2b37d9 | 2033 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2034 | (udiv:SI |
996a5f59 | 2035 | (plus:DI (ashift:DI |
cd2b37d9 | 2036 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2037 | (const_int 32)) |
23a900dc | 2038 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2039 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2040 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2041 | (umod:SI |
996a5f59 | 2042 | (plus:DI (ashift:DI |
1fd4e8c1 | 2043 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2044 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2045 | (match_dup 3)))] |
ca7f5001 | 2046 | "TARGET_POWER" |
cfb557c4 RK |
2047 | "div %0,%1,%3" |
2048 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2049 | |
2050 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2051 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2052 | ;; have to worry about the branches. So make a few subroutines here. | |
2053 | ;; | |
2054 | ;; First comes the normal case. | |
2055 | (define_expand "udivmodsi4_normal" | |
2056 | [(set (match_dup 4) (const_int 0)) | |
2057 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2058 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2059 | (const_int 32)) |
2060 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2061 | (match_operand:SI 2 "" ""))) | |
2062 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2063 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2064 | (const_int 32)) |
2065 | (zero_extend:DI (match_dup 1))) | |
2066 | (match_dup 2)))])] | |
ca7f5001 | 2067 | "TARGET_POWER" |
1fd4e8c1 RK |
2068 | " |
2069 | { operands[4] = gen_reg_rtx (SImode); }") | |
2070 | ||
2071 | ;; This handles the branches. | |
2072 | (define_expand "udivmodsi4_tests" | |
2073 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2074 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2075 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2076 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2077 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2078 | (set (match_dup 0) (const_int 1)) | |
2079 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2080 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2081 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2082 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2083 | "TARGET_POWER" |
1fd4e8c1 RK |
2084 | " |
2085 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2086 | operands[6] = gen_reg_rtx (CCmode); | |
2087 | }") | |
2088 | ||
2089 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2090 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2091 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2092 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2093 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2094 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2095 | "" |
1fd4e8c1 RK |
2096 | " |
2097 | { | |
2098 | rtx label = 0; | |
2099 | ||
8ffd9c51 | 2100 | if (! TARGET_POWER) |
c4d38ccb MM |
2101 | { |
2102 | if (! TARGET_POWERPC) | |
2103 | { | |
39403d82 DE |
2104 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2105 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2106 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2107 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2108 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2109 | DONE; |
2110 | } | |
2111 | else | |
2112 | FAIL; | |
2113 | } | |
0081a354 | 2114 | |
1fd4e8c1 RK |
2115 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2116 | { | |
2117 | operands[2] = force_reg (SImode, operands[2]); | |
2118 | label = gen_label_rtx (); | |
2119 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2120 | operands[3], label)); | |
2121 | } | |
2122 | else | |
2123 | operands[2] = force_reg (SImode, operands[2]); | |
2124 | ||
2125 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2126 | operands[3])); | |
2127 | if (label) | |
2128 | emit_label (label); | |
2129 | ||
2130 | DONE; | |
2131 | }") | |
0081a354 | 2132 | |
fada905b MM |
2133 | ;; AIX architecture-independent common-mode multiply (DImode), |
2134 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2135 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2136 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2137 | ;; assumed unused if generating common-mode, so ignore. | |
2138 | (define_insn "mulh_call" | |
2139 | [(set (reg:SI 3) | |
2140 | (truncate:SI | |
2141 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2142 | (sign_extend:DI (reg:SI 4))) | |
2143 | (const_int 32)))) | |
cf27b467 | 2144 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2145 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2146 | "bla __mulh" |
2147 | [(set_attr "type" "imul")]) | |
fada905b MM |
2148 | |
2149 | (define_insn "mull_call" | |
2150 | [(set (reg:DI 3) | |
2151 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2152 | (sign_extend:DI (reg:SI 4)))) | |
2153 | (clobber (match_scratch:SI 0 "=l")) | |
2154 | (clobber (reg:SI 0))] | |
2155 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2156 | "bla __mull" |
2157 | [(set_attr "type" "imul")]) | |
fada905b MM |
2158 | |
2159 | (define_insn "divss_call" | |
2160 | [(set (reg:SI 3) | |
2161 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2162 | (set (reg:SI 4) | |
2163 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2164 | (clobber (match_scratch:SI 0 "=l")) | |
2165 | (clobber (reg:SI 0))] | |
2166 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2167 | "bla __divss" |
2168 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2169 | |
2170 | (define_insn "divus_call" | |
8ffd9c51 RK |
2171 | [(set (reg:SI 3) |
2172 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2173 | (set (reg:SI 4) | |
2174 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2175 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2176 | (clobber (reg:SI 0)) |
2177 | (clobber (match_scratch:CC 1 "=x")) | |
2178 | (clobber (reg:CC 69))] | |
2179 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2180 | "bla __divus" |
2181 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2182 | |
2183 | (define_insn "quoss_call" | |
2184 | [(set (reg:SI 3) | |
2185 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2186 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2187 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2188 | "bla __quoss" |
2189 | [(set_attr "type" "idiv")]) | |
0081a354 | 2190 | |
fada905b MM |
2191 | (define_insn "quous_call" |
2192 | [(set (reg:SI 3) | |
2193 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2194 | (clobber (match_scratch:SI 0 "=l")) | |
2195 | (clobber (reg:SI 0)) | |
2196 | (clobber (match_scratch:CC 1 "=x")) | |
2197 | (clobber (reg:CC 69))] | |
2198 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2199 | "bla __quous" |
2200 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2201 | \f |
bb21487f | 2202 | ;; Logical instructions |
dfbdccdb GK |
2203 | ;; The logical instructions are mostly combined by using match_operator, |
2204 | ;; but the plain AND insns are somewhat different because there is no | |
2205 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2206 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2207 | ||
29ae5b89 JL |
2208 | (define_insn "andsi3" |
2209 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2210 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2211 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2212 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2213 | "" |
2214 | "@ | |
2215 | and %0,%1,%2 | |
ca7f5001 RK |
2216 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2217 | {andil.|andi.} %0,%1,%b2 | |
9ebbca7d | 2218 | {andiu.|andis.} %0,%1,%u2") |
52d3af72 DE |
2219 | |
2220 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
0ba1b2ff | 2221 | ;; the test again -- this avoids a mfcr which on the higher end |
52d3af72 | 2222 | ;; machines causes an execution serialization |
1fd4e8c1 | 2223 | |
7cd5235b | 2224 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2225 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2226 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2227 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2228 | (const_int 0))) |
52d3af72 DE |
2229 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2230 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2231 | "TARGET_32BIT" |
1fd4e8c1 RK |
2232 | "@ |
2233 | and. %3,%1,%2 | |
ca7f5001 RK |
2234 | {andil.|andi.} %3,%1,%b2 |
2235 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2236 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2237 | # | |
2238 | # | |
2239 | # | |
2240 | #" | |
2241 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2242 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2243 | |
0ba1b2ff AM |
2244 | (define_insn "*andsi3_internal3" |
2245 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2246 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2247 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2248 | (const_int 0))) | |
2249 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) | |
2250 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2251 | "TARGET_64BIT" |
0ba1b2ff AM |
2252 | "@ |
2253 | # | |
2254 | {andil.|andi.} %3,%1,%b2 | |
2255 | {andiu.|andis.} %3,%1,%u2 | |
2256 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 | |
2257 | # | |
2258 | # | |
2259 | # | |
2260 | #" | |
2261 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2262 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2263 | ||
52d3af72 DE |
2264 | (define_split |
2265 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2266 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2267 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 2268 | (const_int 0))) |
52d3af72 DE |
2269 | (clobber (match_scratch:SI 3 "")) |
2270 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2271 | "reload_completed" |
52d3af72 DE |
2272 | [(parallel [(set (match_dup 3) |
2273 | (and:SI (match_dup 1) | |
2274 | (match_dup 2))) | |
2275 | (clobber (match_dup 4))]) | |
2276 | (set (match_dup 0) | |
2277 | (compare:CC (match_dup 3) | |
2278 | (const_int 0)))] | |
2279 | "") | |
2280 | ||
0ba1b2ff AM |
2281 | ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the |
2282 | ;; whole 64 bit reg, and we don't know what is in the high 32 bits. | |
2283 | ||
2284 | (define_split | |
2285 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
2286 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2287 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2288 | (const_int 0))) | |
2289 | (clobber (match_scratch:SI 3 "")) | |
2290 | (clobber (match_scratch:CC 4 ""))] | |
2291 | "TARGET_POWERPC64 && reload_completed" | |
2292 | [(parallel [(set (match_dup 3) | |
2293 | (and:SI (match_dup 1) | |
2294 | (match_dup 2))) | |
2295 | (clobber (match_dup 4))]) | |
2296 | (set (match_dup 0) | |
2297 | (compare:CC (match_dup 3) | |
2298 | (const_int 0)))] | |
2299 | "") | |
2300 | ||
2301 | (define_insn "*andsi3_internal4" | |
52d3af72 DE |
2302 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2303 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2304 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2305 | (const_int 0))) |
2306 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2307 | (and:SI (match_dup 1) | |
2308 | (match_dup 2))) | |
2309 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2310 | "TARGET_32BIT" |
1fd4e8c1 RK |
2311 | "@ |
2312 | and. %0,%1,%2 | |
ca7f5001 RK |
2313 | {andil.|andi.} %0,%1,%b2 |
2314 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2315 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2316 | # | |
2317 | # | |
2318 | # | |
2319 | #" | |
2320 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2321 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2322 | ||
0ba1b2ff AM |
2323 | (define_insn "*andsi3_internal5" |
2324 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2325 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2326 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2327 | (const_int 0))) | |
2328 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2329 | (and:SI (match_dup 1) | |
2330 | (match_dup 2))) | |
2331 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2332 | "TARGET_64BIT" |
0ba1b2ff AM |
2333 | "@ |
2334 | # | |
2335 | {andil.|andi.} %0,%1,%b2 | |
2336 | {andiu.|andis.} %0,%1,%u2 | |
2337 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 | |
2338 | # | |
2339 | # | |
2340 | # | |
2341 | #" | |
2342 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2343 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2344 | ||
52d3af72 DE |
2345 | (define_split |
2346 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2347 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2348 | (match_operand:SI 2 "and_operand" "")) | |
2349 | (const_int 0))) | |
2350 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2351 | (and:SI (match_dup 1) | |
2352 | (match_dup 2))) | |
2353 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2354 | "reload_completed" |
52d3af72 DE |
2355 | [(parallel [(set (match_dup 0) |
2356 | (and:SI (match_dup 1) | |
2357 | (match_dup 2))) | |
2358 | (clobber (match_dup 4))]) | |
2359 | (set (match_dup 3) | |
2360 | (compare:CC (match_dup 0) | |
2361 | (const_int 0)))] | |
2362 | "") | |
1fd4e8c1 | 2363 | |
0ba1b2ff AM |
2364 | (define_split |
2365 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
2366 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2367 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2368 | (const_int 0))) | |
2369 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2370 | (and:SI (match_dup 1) | |
2371 | (match_dup 2))) | |
2372 | (clobber (match_scratch:CC 4 ""))] | |
2373 | "TARGET_POWERPC64 && reload_completed" | |
2374 | [(parallel [(set (match_dup 0) | |
2375 | (and:SI (match_dup 1) | |
2376 | (match_dup 2))) | |
2377 | (clobber (match_dup 4))]) | |
2378 | (set (match_dup 3) | |
2379 | (compare:CC (match_dup 0) | |
2380 | (const_int 0)))] | |
2381 | "") | |
2382 | ||
2383 | ;; Handle the PowerPC64 rlwinm corner case | |
2384 | ||
2385 | (define_insn_and_split "*andsi3_internal6" | |
2386 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2387 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2388 | (match_operand:SI 2 "mask_operand_wrap" "i")))] | |
2389 | "TARGET_POWERPC64" | |
2390 | "#" | |
2391 | "TARGET_POWERPC64" | |
2392 | [(set (match_dup 0) | |
2393 | (and:SI (rotate:SI (match_dup 1) (match_dup 3)) | |
2394 | (match_dup 4))) | |
2395 | (set (match_dup 0) | |
2396 | (rotate:SI (match_dup 0) (match_dup 5)))] | |
2397 | " | |
2398 | { | |
2399 | int mb = extract_MB (operands[2]); | |
2400 | int me = extract_ME (operands[2]); | |
2401 | operands[3] = GEN_INT (me + 1); | |
2402 | operands[5] = GEN_INT (32 - (me + 1)); | |
2403 | operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2404 | }" | |
2405 | [(set_attr "length" "8")]) | |
2406 | ||
2407 | (define_insn_and_split "*andsi3_internal7" | |
2408 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") | |
2409 | (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r") | |
2410 | (match_operand:SI 1 "mask_operand_wrap" "i,i")) | |
2411 | (const_int 0))) | |
2412 | (clobber (match_scratch:SI 3 "=r,r"))] | |
2413 | "TARGET_POWERPC64" | |
2414 | "#" | |
2415 | "TARGET_POWERPC64" | |
2416 | [(parallel [(set (match_dup 2) | |
2417 | (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4)) | |
2418 | (match_dup 5)) | |
2419 | (const_int 0))) | |
2420 | (clobber (match_dup 3))])] | |
2421 | " | |
2422 | { | |
2423 | int mb = extract_MB (operands[1]); | |
2424 | int me = extract_ME (operands[1]); | |
2425 | operands[4] = GEN_INT (me + 1); | |
2426 | operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2427 | }" | |
2428 | [(set_attr "type" "delayed_compare,compare") | |
2429 | (set_attr "length" "4,8")]) | |
2430 | ||
2431 | (define_insn_and_split "*andsi3_internal8" | |
2432 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y") | |
2433 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2434 | (match_operand:SI 2 "mask_operand_wrap" "i,i")) | |
2435 | (const_int 0))) | |
2436 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
2437 | (and:SI (match_dup 1) | |
2438 | (match_dup 2)))] | |
2439 | "TARGET_POWERPC64" | |
2440 | "#" | |
2441 | "TARGET_POWERPC64" | |
2442 | [(parallel [(set (match_dup 3) | |
2443 | (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4)) | |
2444 | (match_dup 5)) | |
2445 | (const_int 0))) | |
2446 | (set (match_dup 0) | |
2447 | (and:SI (rotate:SI (match_dup 1) (match_dup 4)) | |
2448 | (match_dup 5)))]) | |
2449 | (set (match_dup 0) | |
2450 | (rotate:SI (match_dup 0) (match_dup 6)))] | |
2451 | " | |
2452 | { | |
2453 | int mb = extract_MB (operands[2]); | |
2454 | int me = extract_ME (operands[2]); | |
2455 | operands[4] = GEN_INT (me + 1); | |
2456 | operands[6] = GEN_INT (32 - (me + 1)); | |
2457 | operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2458 | }" | |
2459 | [(set_attr "type" "delayed_compare,compare") | |
2460 | (set_attr "length" "8,12")]) | |
2461 | ||
7cd5235b | 2462 | (define_expand "iorsi3" |
cd2b37d9 | 2463 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2464 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2465 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 2466 | "" |
f357808b RK |
2467 | " |
2468 | { | |
7cd5235b | 2469 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2470 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2471 | { |
2472 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2473 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2474 | ? operands[0] : gen_reg_rtx (SImode)); |
2475 | ||
a260abc9 DE |
2476 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2477 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2478 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2479 | DONE; |
2480 | } | |
f357808b RK |
2481 | }") |
2482 | ||
7cd5235b | 2483 | (define_expand "xorsi3" |
cd2b37d9 | 2484 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2485 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2486 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 2487 | "" |
7cd5235b | 2488 | " |
1fd4e8c1 | 2489 | { |
7cd5235b | 2490 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2491 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2492 | { |
2493 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2494 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2495 | ? operands[0] : gen_reg_rtx (SImode)); |
2496 | ||
a260abc9 DE |
2497 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2498 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2499 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2500 | DONE; |
2501 | } | |
1fd4e8c1 RK |
2502 | }") |
2503 | ||
dfbdccdb | 2504 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2505 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 2506 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2507 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
2508 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2509 | "" |
2510 | "@ | |
dfbdccdb GK |
2511 | %q3 %0,%1,%2 |
2512 | {%q3il|%q3i} %0,%1,%b2 | |
2513 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2514 | |
dfbdccdb | 2515 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2516 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 2517 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
2518 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
2519 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2520 | (const_int 0))) | |
52d3af72 | 2521 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2522 | "TARGET_32BIT" |
52d3af72 | 2523 | "@ |
dfbdccdb | 2524 | %q4. %3,%1,%2 |
52d3af72 DE |
2525 | #" |
2526 | [(set_attr "type" "compare") | |
2527 | (set_attr "length" "4,8")]) | |
2528 | ||
2529 | (define_split | |
2530 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2531 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2532 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2533 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2534 | (const_int 0))) |
52d3af72 | 2535 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2536 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2537 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2538 | (set (match_dup 0) |
2539 | (compare:CC (match_dup 3) | |
2540 | (const_int 0)))] | |
2541 | "") | |
815cdc52 | 2542 | |
dfbdccdb | 2543 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2544 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2545 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2546 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2547 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2548 | (const_int 0))) | |
52d3af72 | 2549 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2550 | (match_dup 4))] |
4b8a63d6 | 2551 | "TARGET_32BIT" |
52d3af72 | 2552 | "@ |
dfbdccdb | 2553 | %q4. %0,%1,%2 |
52d3af72 DE |
2554 | #" |
2555 | [(set_attr "type" "compare") | |
2556 | (set_attr "length" "4,8")]) | |
2557 | ||
2558 | (define_split | |
e72247f4 | 2559 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2560 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2561 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2562 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2563 | (const_int 0))) |
75540af0 | 2564 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2565 | (match_dup 4))] |
4b8a63d6 | 2566 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2567 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2568 | (set (match_dup 3) |
2569 | (compare:CC (match_dup 0) | |
2570 | (const_int 0)))] | |
2571 | "") | |
1fd4e8c1 | 2572 | |
6ae08853 | 2573 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 2574 | ;; each of which does one 16-bit part. This is used by combine. |
a260abc9 DE |
2575 | |
2576 | (define_split | |
2577 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 2578 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2579 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2580 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 2581 | "" |
dfbdccdb GK |
2582 | [(set (match_dup 0) (match_dup 4)) |
2583 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
2584 | " |
2585 | { | |
dfbdccdb GK |
2586 | rtx i; |
2587 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
1c563bed | 2588 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2589 | operands[1], i); |
dfbdccdb | 2590 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); |
1c563bed | 2591 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2592 | operands[0], i); |
a260abc9 DE |
2593 | }") |
2594 | ||
dfbdccdb | 2595 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 2596 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2597 | (match_operator:SI 3 "boolean_operator" |
2598 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2599 | (match_operand:SI 2 "gpc_reg_operand" "r")]))] |
1fd4e8c1 | 2600 | "" |
dfbdccdb | 2601 | "%q3 %0,%2,%1") |
1fd4e8c1 | 2602 | |
dfbdccdb | 2603 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 2604 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2605 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2606 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2607 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2608 | (const_int 0))) | |
52d3af72 | 2609 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2610 | "TARGET_32BIT" |
52d3af72 | 2611 | "@ |
dfbdccdb | 2612 | %q4. %3,%2,%1 |
52d3af72 DE |
2613 | #" |
2614 | [(set_attr "type" "compare") | |
2615 | (set_attr "length" "4,8")]) | |
2616 | ||
2617 | (define_split | |
2618 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2619 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2620 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2621 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2622 | (const_int 0))) |
52d3af72 | 2623 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2624 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2625 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2626 | (set (match_dup 0) |
2627 | (compare:CC (match_dup 3) | |
2628 | (const_int 0)))] | |
2629 | "") | |
1fd4e8c1 | 2630 | |
dfbdccdb | 2631 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 2632 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2633 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2634 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2635 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2636 | (const_int 0))) | |
52d3af72 | 2637 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2638 | (match_dup 4))] |
4b8a63d6 | 2639 | "TARGET_32BIT" |
52d3af72 | 2640 | "@ |
dfbdccdb | 2641 | %q4. %0,%2,%1 |
52d3af72 DE |
2642 | #" |
2643 | [(set_attr "type" "compare") | |
2644 | (set_attr "length" "4,8")]) | |
2645 | ||
2646 | (define_split | |
e72247f4 | 2647 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2648 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2649 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2650 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2651 | (const_int 0))) |
75540af0 | 2652 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2653 | (match_dup 4))] |
4b8a63d6 | 2654 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2655 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2656 | (set (match_dup 3) |
2657 | (compare:CC (match_dup 0) | |
2658 | (const_int 0)))] | |
2659 | "") | |
2660 | ||
dfbdccdb | 2661 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 2662 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2663 | (match_operator:SI 3 "boolean_operator" |
2664 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2665 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] |
1fd4e8c1 | 2666 | "" |
dfbdccdb | 2667 | "%q3 %0,%1,%2") |
1fd4e8c1 | 2668 | |
dfbdccdb | 2669 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 2670 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2671 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2672 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2673 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2674 | (const_int 0))) | |
52d3af72 | 2675 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2676 | "TARGET_32BIT" |
52d3af72 | 2677 | "@ |
dfbdccdb | 2678 | %q4. %3,%1,%2 |
52d3af72 DE |
2679 | #" |
2680 | [(set_attr "type" "compare") | |
2681 | (set_attr "length" "4,8")]) | |
2682 | ||
2683 | (define_split | |
2684 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2685 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2686 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2687 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2688 | (const_int 0))) |
52d3af72 | 2689 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2690 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2691 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2692 | (set (match_dup 0) |
2693 | (compare:CC (match_dup 3) | |
2694 | (const_int 0)))] | |
2695 | "") | |
1fd4e8c1 | 2696 | |
dfbdccdb | 2697 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 2698 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2699 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2700 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2701 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2702 | (const_int 0))) | |
52d3af72 | 2703 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2704 | (match_dup 4))] |
4b8a63d6 | 2705 | "TARGET_32BIT" |
52d3af72 | 2706 | "@ |
dfbdccdb | 2707 | %q4. %0,%1,%2 |
52d3af72 DE |
2708 | #" |
2709 | [(set_attr "type" "compare") | |
2710 | (set_attr "length" "4,8")]) | |
2711 | ||
2712 | (define_split | |
e72247f4 | 2713 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2714 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2715 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2716 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2717 | (const_int 0))) |
75540af0 | 2718 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2719 | (match_dup 4))] |
4b8a63d6 | 2720 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2721 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2722 | (set (match_dup 3) |
2723 | (compare:CC (match_dup 0) | |
2724 | (const_int 0)))] | |
2725 | "") | |
1fd4e8c1 RK |
2726 | |
2727 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2728 | ;; orders. Don't define forms that only set CR fields because these | |
2729 | ;; would modify an input register. | |
2730 | ||
7cd5235b | 2731 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2732 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2733 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2734 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2735 | (and:SI (match_dup 2) | |
cd2b37d9 | 2736 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2737 | "TARGET_POWER" |
01def764 | 2738 | "maskir %0,%3,%2") |
1fd4e8c1 | 2739 | |
7cd5235b | 2740 | (define_insn "*maskir_internal2" |
242e8072 | 2741 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2742 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2743 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2744 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2745 | (match_dup 2))))] |
ca7f5001 | 2746 | "TARGET_POWER" |
01def764 | 2747 | "maskir %0,%3,%2") |
1fd4e8c1 | 2748 | |
7cd5235b | 2749 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2750 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2751 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2752 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2753 | (and:SI (not:SI (match_dup 2)) |
2754 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2755 | "TARGET_POWER" |
01def764 | 2756 | "maskir %0,%3,%2") |
1fd4e8c1 | 2757 | |
7cd5235b | 2758 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2759 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2760 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2761 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2762 | (and:SI (not:SI (match_dup 2)) | |
2763 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2764 | "TARGET_POWER" |
01def764 | 2765 | "maskir %0,%3,%2") |
1fd4e8c1 | 2766 | |
7cd5235b | 2767 | (define_insn "*maskir_internal5" |
9ebbca7d | 2768 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2769 | (compare:CC |
9ebbca7d GK |
2770 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2771 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 2772 | (and:SI (match_dup 2) |
9ebbca7d | 2773 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 2774 | (const_int 0))) |
9ebbca7d | 2775 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2776 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2777 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2778 | "TARGET_POWER" |
9ebbca7d GK |
2779 | "@ |
2780 | maskir. %0,%3,%2 | |
2781 | #" | |
2782 | [(set_attr "type" "compare") | |
2783 | (set_attr "length" "4,8")]) | |
2784 | ||
2785 | (define_split | |
2786 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2787 | (compare:CC | |
2788 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2789 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2790 | (and:SI (match_dup 2) | |
2791 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
2792 | (const_int 0))) | |
2793 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2794 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2795 | (and:SI (match_dup 2) (match_dup 3))))] | |
2796 | "TARGET_POWER && reload_completed" | |
2797 | [(set (match_dup 0) | |
2798 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2799 | (and:SI (match_dup 2) (match_dup 3)))) | |
2800 | (set (match_dup 4) | |
2801 | (compare:CC (match_dup 0) | |
2802 | (const_int 0)))] | |
2803 | "") | |
1fd4e8c1 | 2804 | |
7cd5235b | 2805 | (define_insn "*maskir_internal6" |
9ebbca7d | 2806 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2807 | (compare:CC |
9ebbca7d GK |
2808 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2809 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
2810 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 2811 | (match_dup 2))) |
1fd4e8c1 | 2812 | (const_int 0))) |
9ebbca7d | 2813 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2814 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2815 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 2816 | "TARGET_POWER" |
9ebbca7d GK |
2817 | "@ |
2818 | maskir. %0,%3,%2 | |
2819 | #" | |
2820 | [(set_attr "type" "compare") | |
2821 | (set_attr "length" "4,8")]) | |
2822 | ||
2823 | (define_split | |
2824 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2825 | (compare:CC | |
2826 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2827 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2828 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2829 | (match_dup 2))) | |
2830 | (const_int 0))) | |
2831 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2832 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2833 | (and:SI (match_dup 3) (match_dup 2))))] | |
2834 | "TARGET_POWER && reload_completed" | |
2835 | [(set (match_dup 0) | |
2836 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2837 | (and:SI (match_dup 3) (match_dup 2)))) | |
2838 | (set (match_dup 4) | |
2839 | (compare:CC (match_dup 0) | |
2840 | (const_int 0)))] | |
2841 | "") | |
1fd4e8c1 | 2842 | |
7cd5235b | 2843 | (define_insn "*maskir_internal7" |
9ebbca7d | 2844 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 2845 | (compare:CC |
9ebbca7d GK |
2846 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
2847 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2848 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2849 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 2850 | (const_int 0))) |
9ebbca7d | 2851 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
2852 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
2853 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2854 | "TARGET_POWER" | |
9ebbca7d GK |
2855 | "@ |
2856 | maskir. %0,%3,%2 | |
2857 | #" | |
2858 | [(set_attr "type" "compare") | |
2859 | (set_attr "length" "4,8")]) | |
2860 | ||
2861 | (define_split | |
2862 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2863 | (compare:CC | |
2864 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
2865 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
2866 | (and:SI (not:SI (match_dup 2)) | |
2867 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2868 | (const_int 0))) | |
2869 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2870 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2871 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2872 | "TARGET_POWER && reload_completed" | |
2873 | [(set (match_dup 0) | |
2874 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2875 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2876 | (set (match_dup 4) | |
2877 | (compare:CC (match_dup 0) | |
2878 | (const_int 0)))] | |
2879 | "") | |
1fd4e8c1 | 2880 | |
7cd5235b | 2881 | (define_insn "*maskir_internal8" |
9ebbca7d | 2882 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2883 | (compare:CC |
9ebbca7d GK |
2884 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
2885 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 2886 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2887 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 2888 | (const_int 0))) |
9ebbca7d | 2889 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2890 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
2891 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 2892 | "TARGET_POWER" |
9ebbca7d GK |
2893 | "@ |
2894 | maskir. %0,%3,%2 | |
2895 | #" | |
2896 | [(set_attr "type" "compare") | |
2897 | (set_attr "length" "4,8")]) | |
fcce224d | 2898 | |
9ebbca7d GK |
2899 | (define_split |
2900 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2901 | (compare:CC | |
2902 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2903 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2904 | (and:SI (not:SI (match_dup 2)) | |
2905 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2906 | (const_int 0))) | |
2907 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2908 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2909 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2910 | "TARGET_POWER && reload_completed" | |
2911 | [(set (match_dup 0) | |
2912 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2913 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2914 | (set (match_dup 4) | |
2915 | (compare:CC (match_dup 0) | |
2916 | (const_int 0)))] | |
2917 | "") | |
fcce224d | 2918 | \f |
1fd4e8c1 RK |
2919 | ;; Rotate and shift insns, in all their variants. These support shifts, |
2920 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 2921 | (define_expand "insv" |
0ad91047 DE |
2922 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
2923 | (match_operand:SI 1 "const_int_operand" "") | |
2924 | (match_operand:SI 2 "const_int_operand" "")) | |
2925 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
2926 | "" |
2927 | " | |
2928 | { | |
2929 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2930 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2931 | compiler if the address of the structure is taken later. */ | |
2932 | if (GET_CODE (operands[0]) == SUBREG | |
2933 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2934 | FAIL; | |
a78e33fc DE |
2935 | |
2936 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
2937 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
2938 | else | |
2939 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
2940 | DONE; | |
034c1be0 MM |
2941 | }") |
2942 | ||
a78e33fc | 2943 | (define_insn "insvsi" |
cd2b37d9 | 2944 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
2945 | (match_operand:SI 1 "const_int_operand" "i") |
2946 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 2947 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
2948 | "" |
2949 | "* | |
2950 | { | |
2951 | int start = INTVAL (operands[2]) & 31; | |
2952 | int size = INTVAL (operands[1]) & 31; | |
2953 | ||
89e9f3a8 MM |
2954 | operands[4] = GEN_INT (32 - start - size); |
2955 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2956 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2957 | }" |
2958 | [(set_attr "type" "insert_word")]) | |
1fd4e8c1 | 2959 | |
a78e33fc | 2960 | (define_insn "*insvsi_internal1" |
d56d506a RK |
2961 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2962 | (match_operand:SI 1 "const_int_operand" "i") | |
2963 | (match_operand:SI 2 "const_int_operand" "i")) | |
2964 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2965 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2966 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2967 | "* |
2968 | { | |
2969 | int shift = INTVAL (operands[4]) & 31; | |
2970 | int start = INTVAL (operands[2]) & 31; | |
2971 | int size = INTVAL (operands[1]) & 31; | |
2972 | ||
89e9f3a8 MM |
2973 | operands[4] = GEN_INT (shift - start - size); |
2974 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2975 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2976 | }" |
2977 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2978 | |
a78e33fc | 2979 | (define_insn "*insvsi_internal2" |
d56d506a RK |
2980 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2981 | (match_operand:SI 1 "const_int_operand" "i") | |
2982 | (match_operand:SI 2 "const_int_operand" "i")) | |
2983 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2984 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2985 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2986 | "* |
2987 | { | |
2988 | int shift = INTVAL (operands[4]) & 31; | |
2989 | int start = INTVAL (operands[2]) & 31; | |
2990 | int size = INTVAL (operands[1]) & 31; | |
2991 | ||
89e9f3a8 MM |
2992 | operands[4] = GEN_INT (32 - shift - start - size); |
2993 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2994 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2995 | }" |
2996 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2997 | |
a78e33fc | 2998 | (define_insn "*insvsi_internal3" |
d56d506a RK |
2999 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3000 | (match_operand:SI 1 "const_int_operand" "i") | |
3001 | (match_operand:SI 2 "const_int_operand" "i")) | |
3002 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3003 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 3004 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3005 | "* |
3006 | { | |
3007 | int shift = INTVAL (operands[4]) & 31; | |
3008 | int start = INTVAL (operands[2]) & 31; | |
3009 | int size = INTVAL (operands[1]) & 31; | |
3010 | ||
89e9f3a8 MM |
3011 | operands[4] = GEN_INT (32 - shift - start - size); |
3012 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3013 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
3014 | }" |
3015 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3016 | |
a78e33fc | 3017 | (define_insn "*insvsi_internal4" |
d56d506a RK |
3018 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3019 | (match_operand:SI 1 "const_int_operand" "i") | |
3020 | (match_operand:SI 2 "const_int_operand" "i")) | |
3021 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3022 | (match_operand:SI 4 "const_int_operand" "i") | |
3023 | (match_operand:SI 5 "const_int_operand" "i")))] | |
3024 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
3025 | "* | |
3026 | { | |
3027 | int extract_start = INTVAL (operands[5]) & 31; | |
3028 | int extract_size = INTVAL (operands[4]) & 31; | |
3029 | int insert_start = INTVAL (operands[2]) & 31; | |
3030 | int insert_size = INTVAL (operands[1]) & 31; | |
3031 | ||
3032 | /* Align extract field with insert field */ | |
3a598fbe | 3033 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 3034 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 3035 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
8e8238f1 DE |
3036 | }" |
3037 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3038 | |
a78e33fc | 3039 | (define_insn "insvdi" |
685f3906 | 3040 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3041 | (match_operand:SI 1 "const_int_operand" "i") |
3042 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3043 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3044 | "TARGET_POWERPC64" | |
3045 | "* | |
3046 | { | |
3047 | int start = INTVAL (operands[2]) & 63; | |
3048 | int size = INTVAL (operands[1]) & 63; | |
3049 | ||
a78e33fc DE |
3050 | operands[1] = GEN_INT (64 - start - size); |
3051 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3052 | }") |
3053 | ||
034c1be0 | 3054 | (define_expand "extzv" |
0ad91047 DE |
3055 | [(set (match_operand 0 "gpc_reg_operand" "") |
3056 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3057 | (match_operand:SI 2 "const_int_operand" "") | |
3058 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3059 | "" |
3060 | " | |
3061 | { | |
3062 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3063 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3064 | compiler if the address of the structure is taken later. */ | |
3065 | if (GET_CODE (operands[0]) == SUBREG | |
3066 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3067 | FAIL; | |
a78e33fc DE |
3068 | |
3069 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3070 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3071 | else | |
3072 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3073 | DONE; | |
034c1be0 MM |
3074 | }") |
3075 | ||
a78e33fc | 3076 | (define_insn "extzvsi" |
cd2b37d9 RK |
3077 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3078 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3079 | (match_operand:SI 2 "const_int_operand" "i") |
3080 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3081 | "" | |
3082 | "* | |
3083 | { | |
3084 | int start = INTVAL (operands[3]) & 31; | |
3085 | int size = INTVAL (operands[2]) & 31; | |
3086 | ||
3087 | if (start + size >= 32) | |
3088 | operands[3] = const0_rtx; | |
3089 | else | |
89e9f3a8 | 3090 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3091 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3092 | }") |
3093 | ||
a78e33fc | 3094 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3095 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3096 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3097 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3098 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3099 | (const_int 0))) |
9ebbca7d | 3100 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3101 | "" |
1fd4e8c1 RK |
3102 | "* |
3103 | { | |
3104 | int start = INTVAL (operands[3]) & 31; | |
3105 | int size = INTVAL (operands[2]) & 31; | |
3106 | ||
9ebbca7d GK |
3107 | /* Force split for non-cc0 compare. */ |
3108 | if (which_alternative == 1) | |
3109 | return \"#\"; | |
3110 | ||
43a88a8c | 3111 | /* If the bit-field being tested fits in the upper or lower half of a |
a7a975e1 RK |
3112 | word, it is possible to use andiu. or andil. to test it. This is |
3113 | useful because the condition register set-use delay is smaller for | |
3114 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3115 | position is 0 because the LT and GT bits may be set wrong. */ | |
3116 | ||
3117 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3118 | { |
3a598fbe | 3119 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3120 | - (1 << (16 - (start & 15) - size)))); |
3121 | if (start < 16) | |
ca7f5001 | 3122 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3123 | else |
ca7f5001 | 3124 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3125 | } |
7e69e155 | 3126 | |
1fd4e8c1 RK |
3127 | if (start + size >= 32) |
3128 | operands[3] = const0_rtx; | |
3129 | else | |
89e9f3a8 | 3130 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3131 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3132 | }" |
9ebbca7d GK |
3133 | [(set_attr "type" "compare") |
3134 | (set_attr "length" "4,8")]) | |
3135 | ||
3136 | (define_split | |
3137 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3138 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3139 | (match_operand:SI 2 "const_int_operand" "") | |
3140 | (match_operand:SI 3 "const_int_operand" "")) | |
3141 | (const_int 0))) | |
3142 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3143 | "reload_completed" |
9ebbca7d GK |
3144 | [(set (match_dup 4) |
3145 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3146 | (match_dup 3))) | |
3147 | (set (match_dup 0) | |
3148 | (compare:CC (match_dup 4) | |
3149 | (const_int 0)))] | |
3150 | "") | |
1fd4e8c1 | 3151 | |
a78e33fc | 3152 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3153 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3154 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3155 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3156 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3157 | (const_int 0))) |
9ebbca7d | 3158 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3159 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
ce71f754 | 3160 | "" |
1fd4e8c1 RK |
3161 | "* |
3162 | { | |
3163 | int start = INTVAL (operands[3]) & 31; | |
3164 | int size = INTVAL (operands[2]) & 31; | |
3165 | ||
9ebbca7d GK |
3166 | /* Force split for non-cc0 compare. */ |
3167 | if (which_alternative == 1) | |
3168 | return \"#\"; | |
3169 | ||
bc401279 | 3170 | /* Since we are using the output value, we can't ignore any need for |
43a88a8c | 3171 | a shift. The bit-field must end at the LSB. */ |
bc401279 | 3172 | if (start >= 16 && start + size == 32) |
df031c43 | 3173 | { |
bc401279 AM |
3174 | operands[3] = GEN_INT ((1 << size) - 1); |
3175 | return \"{andil.|andi.} %0,%1,%3\"; | |
df031c43 | 3176 | } |
7e69e155 | 3177 | |
1fd4e8c1 RK |
3178 | if (start + size >= 32) |
3179 | operands[3] = const0_rtx; | |
3180 | else | |
89e9f3a8 | 3181 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3182 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3183 | }" |
ce71f754 | 3184 | [(set_attr "type" "compare") |
9ebbca7d GK |
3185 | (set_attr "length" "4,8")]) |
3186 | ||
3187 | (define_split | |
3188 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3189 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3190 | (match_operand:SI 2 "const_int_operand" "") | |
3191 | (match_operand:SI 3 "const_int_operand" "")) | |
3192 | (const_int 0))) | |
3193 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3194 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
ce71f754 | 3195 | "reload_completed" |
9ebbca7d GK |
3196 | [(set (match_dup 0) |
3197 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3198 | (set (match_dup 4) | |
3199 | (compare:CC (match_dup 0) | |
3200 | (const_int 0)))] | |
3201 | "") | |
1fd4e8c1 | 3202 | |
a78e33fc | 3203 | (define_insn "extzvdi" |
685f3906 DE |
3204 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3205 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3206 | (match_operand:SI 2 "const_int_operand" "i") |
3207 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3208 | "TARGET_POWERPC64" |
3209 | "* | |
3210 | { | |
3211 | int start = INTVAL (operands[3]) & 63; | |
3212 | int size = INTVAL (operands[2]) & 63; | |
3213 | ||
3214 | if (start + size >= 64) | |
3215 | operands[3] = const0_rtx; | |
3216 | else | |
89e9f3a8 MM |
3217 | operands[3] = GEN_INT (start + size); |
3218 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3219 | return \"rldicl %0,%1,%3,%2\"; |
3220 | }") | |
3221 | ||
a78e33fc | 3222 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3223 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3224 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3225 | (match_operand:SI 2 "const_int_operand" "i") |
3226 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3227 | (const_int 0))) |
29ae5b89 | 3228 | (clobber (match_scratch:DI 4 "=r"))] |
683bdff7 | 3229 | "TARGET_64BIT" |
685f3906 DE |
3230 | "* |
3231 | { | |
3232 | int start = INTVAL (operands[3]) & 63; | |
3233 | int size = INTVAL (operands[2]) & 63; | |
3234 | ||
3235 | if (start + size >= 64) | |
3236 | operands[3] = const0_rtx; | |
3237 | else | |
89e9f3a8 MM |
3238 | operands[3] = GEN_INT (start + size); |
3239 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3240 | return \"rldicl. %4,%1,%3,%2\"; |
3241 | }") | |
3242 | ||
a78e33fc | 3243 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3244 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3245 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3246 | (match_operand:SI 2 "const_int_operand" "i") |
3247 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3248 | (const_int 0))) |
29ae5b89 | 3249 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 | 3250 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
683bdff7 | 3251 | "TARGET_64BIT" |
685f3906 DE |
3252 | "* |
3253 | { | |
3254 | int start = INTVAL (operands[3]) & 63; | |
3255 | int size = INTVAL (operands[2]) & 63; | |
3256 | ||
3257 | if (start + size >= 64) | |
3258 | operands[3] = const0_rtx; | |
3259 | else | |
89e9f3a8 MM |
3260 | operands[3] = GEN_INT (start + size); |
3261 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3262 | return \"rldicl. %0,%1,%3,%2\"; |
3263 | }") | |
3264 | ||
1fd4e8c1 | 3265 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3266 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3267 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3268 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3269 | "" | |
ca7f5001 | 3270 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3271 | |
a260abc9 | 3272 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3273 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3274 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3275 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3276 | (const_int 0))) |
9ebbca7d | 3277 | (clobber (match_scratch:SI 3 "=r,r"))] |
ce71f754 | 3278 | "" |
9ebbca7d GK |
3279 | "@ |
3280 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3281 | #" | |
3282 | [(set_attr "type" "delayed_compare") | |
3283 | (set_attr "length" "4,8")]) | |
3284 | ||
3285 | (define_split | |
3286 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3287 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3288 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3289 | (const_int 0))) | |
3290 | (clobber (match_scratch:SI 3 ""))] | |
ce71f754 | 3291 | "reload_completed" |
9ebbca7d GK |
3292 | [(set (match_dup 3) |
3293 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3294 | (set (match_dup 0) | |
3295 | (compare:CC (match_dup 3) | |
3296 | (const_int 0)))] | |
3297 | "") | |
1fd4e8c1 | 3298 | |
a260abc9 | 3299 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3300 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3301 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3302 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3303 | (const_int 0))) |
9ebbca7d | 3304 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3305 | (rotate:SI (match_dup 1) (match_dup 2)))] |
ce71f754 | 3306 | "" |
9ebbca7d GK |
3307 | "@ |
3308 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3309 | #" | |
3310 | [(set_attr "type" "delayed_compare") | |
3311 | (set_attr "length" "4,8")]) | |
3312 | ||
3313 | (define_split | |
3314 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3315 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3316 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3317 | (const_int 0))) | |
3318 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3319 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
ce71f754 | 3320 | "reload_completed" |
9ebbca7d GK |
3321 | [(set (match_dup 0) |
3322 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3323 | (set (match_dup 3) | |
3324 | (compare:CC (match_dup 0) | |
3325 | (const_int 0)))] | |
3326 | "") | |
1fd4e8c1 | 3327 | |
a260abc9 | 3328 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3329 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3330 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3331 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
ce71f754 | 3332 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3333 | "" |
ca7f5001 | 3334 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3335 | |
a260abc9 | 3336 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3337 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3338 | (compare:CC (and:SI |
9ebbca7d GK |
3339 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3340 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3341 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3342 | (const_int 0))) |
9ebbca7d | 3343 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3344 | "" |
9ebbca7d GK |
3345 | "@ |
3346 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3347 | #" | |
3348 | [(set_attr "type" "delayed_compare") | |
3349 | (set_attr "length" "4,8")]) | |
3350 | ||
3351 | (define_split | |
3352 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3353 | (compare:CC (and:SI | |
3354 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3355 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3356 | (match_operand:SI 3 "mask_operand" "")) | |
3357 | (const_int 0))) | |
3358 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3359 | "reload_completed" |
9ebbca7d GK |
3360 | [(set (match_dup 4) |
3361 | (and:SI (rotate:SI (match_dup 1) | |
3362 | (match_dup 2)) | |
3363 | (match_dup 3))) | |
3364 | (set (match_dup 0) | |
3365 | (compare:CC (match_dup 4) | |
3366 | (const_int 0)))] | |
3367 | "") | |
1fd4e8c1 | 3368 | |
a260abc9 | 3369 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3370 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3371 | (compare:CC (and:SI |
9ebbca7d GK |
3372 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3373 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3374 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3375 | (const_int 0))) |
9ebbca7d | 3376 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3377 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3378 | "" |
9ebbca7d GK |
3379 | "@ |
3380 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3381 | #" | |
3382 | [(set_attr "type" "delayed_compare") | |
3383 | (set_attr "length" "4,8")]) | |
3384 | ||
3385 | (define_split | |
3386 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3387 | (compare:CC (and:SI | |
3388 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3389 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3390 | (match_operand:SI 3 "mask_operand" "")) | |
3391 | (const_int 0))) | |
3392 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3393 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3394 | "reload_completed" |
9ebbca7d GK |
3395 | [(set (match_dup 0) |
3396 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3397 | (set (match_dup 4) | |
3398 | (compare:CC (match_dup 0) | |
3399 | (const_int 0)))] | |
3400 | "") | |
1fd4e8c1 | 3401 | |
a260abc9 | 3402 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3403 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3404 | (zero_extend:SI |
3405 | (subreg:QI | |
cd2b37d9 | 3406 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3407 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3408 | "" | |
ca7f5001 | 3409 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3410 | |
a260abc9 | 3411 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3412 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3413 | (compare:CC (zero_extend:SI |
3414 | (subreg:QI | |
9ebbca7d GK |
3415 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3416 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3417 | (const_int 0))) |
9ebbca7d | 3418 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3419 | "" |
9ebbca7d GK |
3420 | "@ |
3421 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3422 | #" | |
3423 | [(set_attr "type" "delayed_compare") | |
3424 | (set_attr "length" "4,8")]) | |
3425 | ||
3426 | (define_split | |
3427 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3428 | (compare:CC (zero_extend:SI | |
3429 | (subreg:QI | |
3430 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3431 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3432 | (const_int 0))) | |
3433 | (clobber (match_scratch:SI 3 ""))] | |
3434 | "reload_completed" | |
3435 | [(set (match_dup 3) | |
3436 | (zero_extend:SI (subreg:QI | |
3437 | (rotate:SI (match_dup 1) | |
3438 | (match_dup 2)) 0))) | |
3439 | (set (match_dup 0) | |
3440 | (compare:CC (match_dup 3) | |
3441 | (const_int 0)))] | |
3442 | "") | |
1fd4e8c1 | 3443 | |
a260abc9 | 3444 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3445 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3446 | (compare:CC (zero_extend:SI |
3447 | (subreg:QI | |
9ebbca7d GK |
3448 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3449 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3450 | (const_int 0))) |
9ebbca7d | 3451 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3452 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3453 | "" | |
9ebbca7d GK |
3454 | "@ |
3455 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3456 | #" | |
3457 | [(set_attr "type" "delayed_compare") | |
3458 | (set_attr "length" "4,8")]) | |
3459 | ||
3460 | (define_split | |
3461 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3462 | (compare:CC (zero_extend:SI | |
3463 | (subreg:QI | |
3464 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3465 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3466 | (const_int 0))) | |
3467 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3468 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3469 | "reload_completed" | |
3470 | [(set (match_dup 0) | |
3471 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3472 | (set (match_dup 3) | |
3473 | (compare:CC (match_dup 0) | |
3474 | (const_int 0)))] | |
3475 | "") | |
1fd4e8c1 | 3476 | |
a260abc9 | 3477 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3478 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3479 | (zero_extend:SI |
3480 | (subreg:HI | |
cd2b37d9 | 3481 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3482 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3483 | "" | |
ca7f5001 | 3484 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3485 | |
a260abc9 | 3486 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3487 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3488 | (compare:CC (zero_extend:SI |
3489 | (subreg:HI | |
9ebbca7d GK |
3490 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3491 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3492 | (const_int 0))) |
9ebbca7d | 3493 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3494 | "" |
9ebbca7d GK |
3495 | "@ |
3496 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3497 | #" | |
3498 | [(set_attr "type" "delayed_compare") | |
3499 | (set_attr "length" "4,8")]) | |
3500 | ||
3501 | (define_split | |
3502 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3503 | (compare:CC (zero_extend:SI | |
3504 | (subreg:HI | |
3505 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3506 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3507 | (const_int 0))) | |
3508 | (clobber (match_scratch:SI 3 ""))] | |
3509 | "reload_completed" | |
3510 | [(set (match_dup 3) | |
3511 | (zero_extend:SI (subreg:HI | |
3512 | (rotate:SI (match_dup 1) | |
3513 | (match_dup 2)) 0))) | |
3514 | (set (match_dup 0) | |
3515 | (compare:CC (match_dup 3) | |
3516 | (const_int 0)))] | |
3517 | "") | |
1fd4e8c1 | 3518 | |
a260abc9 | 3519 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3520 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3521 | (compare:CC (zero_extend:SI |
3522 | (subreg:HI | |
9ebbca7d GK |
3523 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3524 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3525 | (const_int 0))) |
9ebbca7d | 3526 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3527 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3528 | "" | |
9ebbca7d GK |
3529 | "@ |
3530 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3531 | #" | |
3532 | [(set_attr "type" "delayed_compare") | |
3533 | (set_attr "length" "4,8")]) | |
3534 | ||
3535 | (define_split | |
3536 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3537 | (compare:CC (zero_extend:SI | |
3538 | (subreg:HI | |
3539 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3540 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3541 | (const_int 0))) | |
3542 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3543 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3544 | "reload_completed" | |
3545 | [(set (match_dup 0) | |
3546 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3547 | (set (match_dup 3) | |
3548 | (compare:CC (match_dup 0) | |
3549 | (const_int 0)))] | |
3550 | "") | |
1fd4e8c1 RK |
3551 | |
3552 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3553 | ;; SHIFT_COUNT_TRUNCATED. | |
3554 | ||
ca7f5001 RK |
3555 | (define_expand "ashlsi3" |
3556 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3557 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3558 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3559 | "" | |
3560 | " | |
3561 | { | |
3562 | if (TARGET_POWER) | |
3563 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3564 | else | |
25c341fa | 3565 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3566 | DONE; |
3567 | }") | |
3568 | ||
3569 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3570 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3571 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3572 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3573 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3574 | "TARGET_POWER" |
1fd4e8c1 RK |
3575 | "@ |
3576 | sle %0,%1,%2 | |
9ebbca7d | 3577 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3578 | |
25c341fa | 3579 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3580 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3581 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3582 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3583 | "! TARGET_POWER" |
9ebbca7d | 3584 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3585 | |
3586 | (define_insn "" | |
9ebbca7d GK |
3587 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3588 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3589 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3590 | (const_int 0))) |
9ebbca7d GK |
3591 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
3592 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 3593 | "TARGET_POWER" |
1fd4e8c1 RK |
3594 | "@ |
3595 | sle. %3,%1,%2 | |
9ebbca7d GK |
3596 | {sli.|slwi.} %3,%1,%h2 |
3597 | # | |
3598 | #" | |
3599 | [(set_attr "type" "delayed_compare") | |
3600 | (set_attr "length" "4,4,8,8")]) | |
3601 | ||
3602 | (define_split | |
3603 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3604 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3605 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3606 | (const_int 0))) | |
3607 | (clobber (match_scratch:SI 3 "")) | |
3608 | (clobber (match_scratch:SI 4 ""))] | |
3609 | "TARGET_POWER && reload_completed" | |
3610 | [(parallel [(set (match_dup 3) | |
3611 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3612 | (clobber (match_dup 4))]) | |
3613 | (set (match_dup 0) | |
3614 | (compare:CC (match_dup 3) | |
3615 | (const_int 0)))] | |
3616 | "") | |
25c341fa | 3617 | |
ca7f5001 | 3618 | (define_insn "" |
9ebbca7d GK |
3619 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3620 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3621 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3622 | (const_int 0))) |
9ebbca7d | 3623 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 3624 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3625 | "@ |
3626 | {sl|slw}%I2. %3,%1,%h2 | |
3627 | #" | |
3628 | [(set_attr "type" "delayed_compare") | |
3629 | (set_attr "length" "4,8")]) | |
3630 | ||
3631 | (define_split | |
3632 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3633 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3634 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3635 | (const_int 0))) | |
3636 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3637 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3638 | [(set (match_dup 3) |
3639 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3640 | (set (match_dup 0) | |
3641 | (compare:CC (match_dup 3) | |
3642 | (const_int 0)))] | |
3643 | "") | |
1fd4e8c1 RK |
3644 | |
3645 | (define_insn "" | |
9ebbca7d GK |
3646 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3647 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3648 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3649 | (const_int 0))) |
9ebbca7d | 3650 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 3651 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3652 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 3653 | "TARGET_POWER" |
1fd4e8c1 RK |
3654 | "@ |
3655 | sle. %0,%1,%2 | |
9ebbca7d GK |
3656 | {sli.|slwi.} %0,%1,%h2 |
3657 | # | |
3658 | #" | |
3659 | [(set_attr "type" "delayed_compare") | |
3660 | (set_attr "length" "4,4,8,8")]) | |
3661 | ||
3662 | (define_split | |
3663 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3664 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3665 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3666 | (const_int 0))) | |
3667 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3668 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3669 | (clobber (match_scratch:SI 4 ""))] | |
3670 | "TARGET_POWER && reload_completed" | |
3671 | [(parallel [(set (match_dup 0) | |
3672 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3673 | (clobber (match_dup 4))]) | |
3674 | (set (match_dup 3) | |
3675 | (compare:CC (match_dup 0) | |
3676 | (const_int 0)))] | |
3677 | "") | |
25c341fa | 3678 | |
ca7f5001 | 3679 | (define_insn "" |
9ebbca7d GK |
3680 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3681 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3682 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3683 | (const_int 0))) |
9ebbca7d | 3684 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 3685 | (ashift:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 3686 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3687 | "@ |
3688 | {sl|slw}%I2. %0,%1,%h2 | |
3689 | #" | |
3690 | [(set_attr "type" "delayed_compare") | |
3691 | (set_attr "length" "4,8")]) | |
3692 | ||
3693 | (define_split | |
3694 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3695 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3696 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3697 | (const_int 0))) | |
3698 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3699 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 3700 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3701 | [(set (match_dup 0) |
3702 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3703 | (set (match_dup 3) | |
3704 | (compare:CC (match_dup 0) | |
3705 | (const_int 0)))] | |
3706 | "") | |
1fd4e8c1 RK |
3707 | |
3708 | (define_insn "" | |
cd2b37d9 RK |
3709 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3710 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3711 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3712 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3713 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 3714 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3715 | |
3716 | (define_insn "" | |
9ebbca7d | 3717 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3718 | (compare:CC |
9ebbca7d GK |
3719 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3720 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3721 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3722 | (const_int 0))) |
9ebbca7d | 3723 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3724 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3725 | "@ |
3726 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
3727 | #" | |
3728 | [(set_attr "type" "delayed_compare") | |
3729 | (set_attr "length" "4,8")]) | |
3730 | ||
3731 | (define_split | |
3732 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3733 | (compare:CC | |
3734 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3735 | (match_operand:SI 2 "const_int_operand" "")) | |
3736 | (match_operand:SI 3 "mask_operand" "")) | |
3737 | (const_int 0))) | |
3738 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3739 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3740 | [(set (match_dup 4) |
3741 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
3742 | (match_dup 3))) | |
3743 | (set (match_dup 0) | |
3744 | (compare:CC (match_dup 4) | |
3745 | (const_int 0)))] | |
3746 | "") | |
1fd4e8c1 RK |
3747 | |
3748 | (define_insn "" | |
9ebbca7d | 3749 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3750 | (compare:CC |
9ebbca7d GK |
3751 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3752 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3753 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3754 | (const_int 0))) |
9ebbca7d | 3755 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3756 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3757 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3758 | "@ |
3759 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
3760 | #" | |
3761 | [(set_attr "type" "delayed_compare") | |
3762 | (set_attr "length" "4,8")]) | |
3763 | ||
3764 | (define_split | |
3765 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3766 | (compare:CC | |
3767 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3768 | (match_operand:SI 2 "const_int_operand" "")) | |
3769 | (match_operand:SI 3 "mask_operand" "")) | |
3770 | (const_int 0))) | |
3771 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3772 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3773 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3774 | [(set (match_dup 0) |
3775 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3776 | (set (match_dup 4) | |
3777 | (compare:CC (match_dup 0) | |
3778 | (const_int 0)))] | |
3779 | "") | |
1fd4e8c1 | 3780 | |
ca7f5001 | 3781 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3782 | ;; "sli x,x,0". |
ca7f5001 RK |
3783 | (define_expand "lshrsi3" |
3784 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3785 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3786 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3787 | "" | |
3788 | " | |
3789 | { | |
3790 | if (TARGET_POWER) | |
3791 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
3792 | else | |
25c341fa | 3793 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3794 | DONE; |
3795 | }") | |
3796 | ||
3797 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
3798 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
3799 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3800 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
3801 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 3802 | "TARGET_POWER" |
1fd4e8c1 RK |
3803 | "@ |
3804 | sre %0,%1,%2 | |
bdf423cb | 3805 | mr %0,%1 |
ca7f5001 RK |
3806 | {s%A2i|s%A2wi} %0,%1,%h2") |
3807 | ||
25c341fa | 3808 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
3809 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3810 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3811 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 3812 | "! TARGET_POWER" |
bdf423cb MM |
3813 | "@ |
3814 | mr %0,%1 | |
3815 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
3816 | |
3817 | (define_insn "" | |
9ebbca7d GK |
3818 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
3819 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3820 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3821 | (const_int 0))) |
9ebbca7d GK |
3822 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
3823 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 3824 | "TARGET_POWER" |
1fd4e8c1 | 3825 | "@ |
29ae5b89 JL |
3826 | sre. %3,%1,%2 |
3827 | mr. %1,%1 | |
9ebbca7d GK |
3828 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
3829 | # | |
3830 | # | |
3831 | #" | |
3832 | [(set_attr "type" "delayed_compare") | |
3833 | (set_attr "length" "4,4,4,8,8,8")]) | |
3834 | ||
3835 | (define_split | |
3836 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3837 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3838 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3839 | (const_int 0))) | |
3840 | (clobber (match_scratch:SI 3 "")) | |
3841 | (clobber (match_scratch:SI 4 ""))] | |
3842 | "TARGET_POWER && reload_completed" | |
3843 | [(parallel [(set (match_dup 3) | |
3844 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3845 | (clobber (match_dup 4))]) | |
3846 | (set (match_dup 0) | |
3847 | (compare:CC (match_dup 3) | |
3848 | (const_int 0)))] | |
3849 | "") | |
ca7f5001 RK |
3850 | |
3851 | (define_insn "" | |
9ebbca7d GK |
3852 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3853 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3854 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 3855 | (const_int 0))) |
9ebbca7d | 3856 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
4b8a63d6 | 3857 | "! TARGET_POWER && TARGET_32BIT" |
bdf423cb MM |
3858 | "@ |
3859 | mr. %1,%1 | |
9ebbca7d GK |
3860 | {sr|srw}%I2. %3,%1,%h2 |
3861 | # | |
3862 | #" | |
3863 | [(set_attr "type" "delayed_compare") | |
3864 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 3865 | |
9ebbca7d GK |
3866 | (define_split |
3867 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3868 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3869 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3870 | (const_int 0))) | |
3871 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3872 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3873 | [(set (match_dup 3) |
3874 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3875 | (set (match_dup 0) | |
3876 | (compare:CC (match_dup 3) | |
3877 | (const_int 0)))] | |
3878 | "") | |
3879 | ||
3880 | (define_insn "" | |
3881 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
3882 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3883 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3884 | (const_int 0))) |
9ebbca7d | 3885 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 3886 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3887 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 3888 | "TARGET_POWER" |
1fd4e8c1 | 3889 | "@ |
29ae5b89 JL |
3890 | sre. %0,%1,%2 |
3891 | mr. %0,%1 | |
9ebbca7d GK |
3892 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
3893 | # | |
3894 | # | |
3895 | #" | |
3896 | [(set_attr "type" "delayed_compare") | |
3897 | (set_attr "length" "4,4,4,8,8,8")]) | |
3898 | ||
3899 | (define_split | |
3900 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3901 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3902 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3903 | (const_int 0))) | |
3904 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3905 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3906 | (clobber (match_scratch:SI 4 ""))] | |
3907 | "TARGET_POWER && reload_completed" | |
3908 | [(parallel [(set (match_dup 0) | |
3909 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3910 | (clobber (match_dup 4))]) | |
3911 | (set (match_dup 3) | |
3912 | (compare:CC (match_dup 0) | |
3913 | (const_int 0)))] | |
3914 | "") | |
ca7f5001 RK |
3915 | |
3916 | (define_insn "" | |
9ebbca7d GK |
3917 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3918 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3919 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 3920 | (const_int 0))) |
9ebbca7d | 3921 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 3922 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 3923 | "! TARGET_POWER && TARGET_32BIT" |
29ae5b89 JL |
3924 | "@ |
3925 | mr. %0,%1 | |
9ebbca7d GK |
3926 | {sr|srw}%I2. %0,%1,%h2 |
3927 | # | |
3928 | #" | |
3929 | [(set_attr "type" "delayed_compare") | |
3930 | (set_attr "length" "4,4,8,8")]) | |
3931 | ||
3932 | (define_split | |
3933 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3934 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3935 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3936 | (const_int 0))) | |
3937 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3938 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 3939 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3940 | [(set (match_dup 0) |
3941 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3942 | (set (match_dup 3) | |
3943 | (compare:CC (match_dup 0) | |
3944 | (const_int 0)))] | |
3945 | "") | |
1fd4e8c1 RK |
3946 | |
3947 | (define_insn "" | |
cd2b37d9 RK |
3948 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3949 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3950 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3951 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3952 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 3953 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
3954 | |
3955 | (define_insn "" | |
9ebbca7d | 3956 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3957 | (compare:CC |
9ebbca7d GK |
3958 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3959 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3960 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3961 | (const_int 0))) |
9ebbca7d | 3962 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3963 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3964 | "@ |
3965 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
3966 | #" | |
3967 | [(set_attr "type" "delayed_compare") | |
3968 | (set_attr "length" "4,8")]) | |
3969 | ||
3970 | (define_split | |
3971 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3972 | (compare:CC | |
3973 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3974 | (match_operand:SI 2 "const_int_operand" "")) | |
3975 | (match_operand:SI 3 "mask_operand" "")) | |
3976 | (const_int 0))) | |
3977 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3978 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3979 | [(set (match_dup 4) |
3980 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
3981 | (match_dup 3))) | |
3982 | (set (match_dup 0) | |
3983 | (compare:CC (match_dup 4) | |
3984 | (const_int 0)))] | |
3985 | "") | |
1fd4e8c1 RK |
3986 | |
3987 | (define_insn "" | |
9ebbca7d | 3988 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3989 | (compare:CC |
9ebbca7d GK |
3990 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3991 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3992 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3993 | (const_int 0))) |
9ebbca7d | 3994 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3995 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3996 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3997 | "@ |
3998 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
3999 | #" | |
4000 | [(set_attr "type" "delayed_compare") | |
4001 | (set_attr "length" "4,8")]) | |
4002 | ||
4003 | (define_split | |
4004 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4005 | (compare:CC | |
4006 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4007 | (match_operand:SI 2 "const_int_operand" "")) | |
4008 | (match_operand:SI 3 "mask_operand" "")) | |
4009 | (const_int 0))) | |
4010 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4011 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 4012 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4013 | [(set (match_dup 0) |
4014 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4015 | (set (match_dup 4) | |
4016 | (compare:CC (match_dup 0) | |
4017 | (const_int 0)))] | |
4018 | "") | |
1fd4e8c1 RK |
4019 | |
4020 | (define_insn "" | |
cd2b37d9 | 4021 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4022 | (zero_extend:SI |
4023 | (subreg:QI | |
cd2b37d9 | 4024 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4025 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4026 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4027 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4028 | |
4029 | (define_insn "" | |
9ebbca7d | 4030 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4031 | (compare:CC |
4032 | (zero_extend:SI | |
4033 | (subreg:QI | |
9ebbca7d GK |
4034 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4035 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4036 | (const_int 0))) |
9ebbca7d | 4037 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4038 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4039 | "@ |
4040 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4041 | #" | |
4042 | [(set_attr "type" "delayed_compare") | |
4043 | (set_attr "length" "4,8")]) | |
4044 | ||
4045 | (define_split | |
4046 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4047 | (compare:CC | |
4048 | (zero_extend:SI | |
4049 | (subreg:QI | |
4050 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4051 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4052 | (const_int 0))) | |
4053 | (clobber (match_scratch:SI 3 ""))] | |
4054 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4055 | [(set (match_dup 3) | |
4056 | (zero_extend:SI (subreg:QI | |
4057 | (lshiftrt:SI (match_dup 1) | |
4058 | (match_dup 2)) 0))) | |
4059 | (set (match_dup 0) | |
4060 | (compare:CC (match_dup 3) | |
4061 | (const_int 0)))] | |
4062 | "") | |
1fd4e8c1 RK |
4063 | |
4064 | (define_insn "" | |
9ebbca7d | 4065 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4066 | (compare:CC |
4067 | (zero_extend:SI | |
4068 | (subreg:QI | |
9ebbca7d GK |
4069 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4070 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4071 | (const_int 0))) |
9ebbca7d | 4072 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4073 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4074 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4075 | "@ |
4076 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4077 | #" | |
4078 | [(set_attr "type" "delayed_compare") | |
4079 | (set_attr "length" "4,8")]) | |
4080 | ||
4081 | (define_split | |
4082 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4083 | (compare:CC | |
4084 | (zero_extend:SI | |
4085 | (subreg:QI | |
4086 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4087 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4088 | (const_int 0))) | |
4089 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4090 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4091 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4092 | [(set (match_dup 0) | |
4093 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4094 | (set (match_dup 3) | |
4095 | (compare:CC (match_dup 0) | |
4096 | (const_int 0)))] | |
4097 | "") | |
1fd4e8c1 RK |
4098 | |
4099 | (define_insn "" | |
cd2b37d9 | 4100 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4101 | (zero_extend:SI |
4102 | (subreg:HI | |
cd2b37d9 | 4103 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4104 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4105 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4106 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4107 | |
4108 | (define_insn "" | |
9ebbca7d | 4109 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4110 | (compare:CC |
4111 | (zero_extend:SI | |
4112 | (subreg:HI | |
9ebbca7d GK |
4113 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4114 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4115 | (const_int 0))) |
9ebbca7d | 4116 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4117 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4118 | "@ |
4119 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4120 | #" | |
4121 | [(set_attr "type" "delayed_compare") | |
4122 | (set_attr "length" "4,8")]) | |
4123 | ||
4124 | (define_split | |
4125 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4126 | (compare:CC | |
4127 | (zero_extend:SI | |
4128 | (subreg:HI | |
4129 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4130 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4131 | (const_int 0))) | |
4132 | (clobber (match_scratch:SI 3 ""))] | |
4133 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4134 | [(set (match_dup 3) | |
4135 | (zero_extend:SI (subreg:HI | |
4136 | (lshiftrt:SI (match_dup 1) | |
4137 | (match_dup 2)) 0))) | |
4138 | (set (match_dup 0) | |
4139 | (compare:CC (match_dup 3) | |
4140 | (const_int 0)))] | |
4141 | "") | |
1fd4e8c1 RK |
4142 | |
4143 | (define_insn "" | |
9ebbca7d | 4144 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4145 | (compare:CC |
4146 | (zero_extend:SI | |
4147 | (subreg:HI | |
9ebbca7d GK |
4148 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4149 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4150 | (const_int 0))) |
9ebbca7d | 4151 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4152 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4153 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4154 | "@ |
4155 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4156 | #" | |
4157 | [(set_attr "type" "delayed_compare") | |
4158 | (set_attr "length" "4,8")]) | |
4159 | ||
4160 | (define_split | |
4161 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4162 | (compare:CC | |
4163 | (zero_extend:SI | |
4164 | (subreg:HI | |
4165 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4166 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4167 | (const_int 0))) | |
4168 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4169 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4170 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4171 | [(set (match_dup 0) | |
4172 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4173 | (set (match_dup 3) | |
4174 | (compare:CC (match_dup 0) | |
4175 | (const_int 0)))] | |
4176 | "") | |
1fd4e8c1 RK |
4177 | |
4178 | (define_insn "" | |
cd2b37d9 | 4179 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4180 | (const_int 1) |
cd2b37d9 RK |
4181 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4182 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4183 | (const_int 31)))] |
ca7f5001 | 4184 | "TARGET_POWER" |
1fd4e8c1 RK |
4185 | "rrib %0,%1,%2") |
4186 | ||
4187 | (define_insn "" | |
cd2b37d9 | 4188 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4189 | (const_int 1) |
cd2b37d9 RK |
4190 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4191 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4192 | (const_int 31)))] |
ca7f5001 | 4193 | "TARGET_POWER" |
1fd4e8c1 RK |
4194 | "rrib %0,%1,%2") |
4195 | ||
4196 | (define_insn "" | |
cd2b37d9 | 4197 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4198 | (const_int 1) |
cd2b37d9 RK |
4199 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4200 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4201 | (const_int 1) |
4202 | (const_int 0)))] | |
ca7f5001 | 4203 | "TARGET_POWER" |
1fd4e8c1 RK |
4204 | "rrib %0,%1,%2") |
4205 | ||
ca7f5001 RK |
4206 | (define_expand "ashrsi3" |
4207 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4208 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4209 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4210 | "" | |
4211 | " | |
4212 | { | |
4213 | if (TARGET_POWER) | |
4214 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4215 | else | |
25c341fa | 4216 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4217 | DONE; |
4218 | }") | |
4219 | ||
4220 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4221 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4222 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4223 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4224 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4225 | "TARGET_POWER" |
1fd4e8c1 RK |
4226 | "@ |
4227 | srea %0,%1,%2 | |
ca7f5001 RK |
4228 | {srai|srawi} %0,%1,%h2") |
4229 | ||
25c341fa | 4230 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4231 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4232 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4233 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4234 | "! TARGET_POWER" |
d904e9ed | 4235 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4236 | |
4237 | (define_insn "" | |
9ebbca7d GK |
4238 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4239 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4240 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4241 | (const_int 0))) |
9ebbca7d GK |
4242 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4243 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4244 | "TARGET_POWER" |
1fd4e8c1 RK |
4245 | "@ |
4246 | srea. %3,%1,%2 | |
9ebbca7d GK |
4247 | {srai.|srawi.} %3,%1,%h2 |
4248 | # | |
4249 | #" | |
4250 | [(set_attr "type" "delayed_compare") | |
4251 | (set_attr "length" "4,4,8,8")]) | |
4252 | ||
4253 | (define_split | |
4254 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4255 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4256 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4257 | (const_int 0))) | |
4258 | (clobber (match_scratch:SI 3 "")) | |
4259 | (clobber (match_scratch:SI 4 ""))] | |
4260 | "TARGET_POWER && reload_completed" | |
4261 | [(parallel [(set (match_dup 3) | |
4262 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4263 | (clobber (match_dup 4))]) | |
4264 | (set (match_dup 0) | |
4265 | (compare:CC (match_dup 3) | |
4266 | (const_int 0)))] | |
4267 | "") | |
ca7f5001 RK |
4268 | |
4269 | (define_insn "" | |
9ebbca7d GK |
4270 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4271 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4272 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4273 | (const_int 0))) |
9ebbca7d | 4274 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4275 | "! TARGET_POWER" |
9ebbca7d GK |
4276 | "@ |
4277 | {sra|sraw}%I2. %3,%1,%h2 | |
4278 | #" | |
4279 | [(set_attr "type" "delayed_compare") | |
4280 | (set_attr "length" "4,8")]) | |
4281 | ||
4282 | (define_split | |
4283 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4284 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4285 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4286 | (const_int 0))) | |
4287 | (clobber (match_scratch:SI 3 ""))] | |
4288 | "! TARGET_POWER && reload_completed" | |
4289 | [(set (match_dup 3) | |
4290 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4291 | (set (match_dup 0) | |
4292 | (compare:CC (match_dup 3) | |
4293 | (const_int 0)))] | |
4294 | "") | |
1fd4e8c1 RK |
4295 | |
4296 | (define_insn "" | |
9ebbca7d GK |
4297 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4298 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4299 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4300 | (const_int 0))) |
9ebbca7d | 4301 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4302 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4303 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4304 | "TARGET_POWER" |
1fd4e8c1 RK |
4305 | "@ |
4306 | srea. %0,%1,%2 | |
9ebbca7d GK |
4307 | {srai.|srawi.} %0,%1,%h2 |
4308 | # | |
4309 | #" | |
4310 | [(set_attr "type" "delayed_compare") | |
4311 | (set_attr "length" "4,4,8,8")]) | |
4312 | ||
4313 | (define_split | |
4314 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4315 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4316 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4317 | (const_int 0))) | |
4318 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4319 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4320 | (clobber (match_scratch:SI 4 ""))] | |
4321 | "TARGET_POWER && reload_completed" | |
4322 | [(parallel [(set (match_dup 0) | |
4323 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4324 | (clobber (match_dup 4))]) | |
4325 | (set (match_dup 3) | |
4326 | (compare:CC (match_dup 0) | |
4327 | (const_int 0)))] | |
4328 | "") | |
1fd4e8c1 | 4329 | |
ca7f5001 | 4330 | (define_insn "" |
9ebbca7d GK |
4331 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4332 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4333 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4334 | (const_int 0))) |
9ebbca7d | 4335 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4336 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4337 | "! TARGET_POWER" |
9ebbca7d GK |
4338 | "@ |
4339 | {sra|sraw}%I2. %0,%1,%h2 | |
4340 | #" | |
4341 | [(set_attr "type" "delayed_compare") | |
4342 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4343 | \f |
9ebbca7d GK |
4344 | (define_split |
4345 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4346 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4347 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4348 | (const_int 0))) | |
4349 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4350 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4351 | "! TARGET_POWER && reload_completed" | |
4352 | [(set (match_dup 0) | |
4353 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4354 | (set (match_dup 3) | |
4355 | (compare:CC (match_dup 0) | |
4356 | (const_int 0)))] | |
4357 | "") | |
4358 | ||
1fd4e8c1 RK |
4359 | ;; Floating-point insns, excluding normal data motion. |
4360 | ;; | |
ca7f5001 RK |
4361 | ;; PowerPC has a full set of single-precision floating point instructions. |
4362 | ;; | |
4363 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4364 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4365 | ;; The only conversions we will do will be when storing to memory. In that | |
4366 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4367 | ;; |
4368 | ;; Note that when we store into a single-precision memory location, we need to | |
4369 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4370 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4371 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4372 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4373 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4374 | ||
e8112008 | 4375 | (define_insn "extendsfdf2" |
cd2b37d9 | 4376 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
e8112008 | 4377 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] |
a3170dc6 | 4378 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
e8112008 | 4379 | "* |
5c30aff8 | 4380 | { |
e8112008 RK |
4381 | if (REGNO (operands[0]) == REGNO (operands[1])) |
4382 | return \"\"; | |
4383 | else | |
4384 | return \"fmr %0,%1\"; | |
4385 | }" | |
4386 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4387 | |
4388 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
4389 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4390 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4391 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
dcac138d | 4392 | "frsp %0,%1" |
1fd4e8c1 RK |
4393 | [(set_attr "type" "fp")]) |
4394 | ||
455350f4 RK |
4395 | (define_insn "aux_truncdfsf2" |
4396 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
615158e2 | 4397 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))] |
a3170dc6 | 4398 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
455350f4 RK |
4399 | "frsp %0,%1" |
4400 | [(set_attr "type" "fp")]) | |
4401 | ||
a3170dc6 AH |
4402 | (define_expand "negsf2" |
4403 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4404 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4405 | "TARGET_HARD_FLOAT" | |
4406 | "") | |
4407 | ||
4408 | (define_insn "*negsf2" | |
cd2b37d9 RK |
4409 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4410 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4411 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4412 | "fneg %0,%1" |
4413 | [(set_attr "type" "fp")]) | |
4414 | ||
a3170dc6 AH |
4415 | (define_expand "abssf2" |
4416 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4417 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4418 | "TARGET_HARD_FLOAT" | |
4419 | "") | |
4420 | ||
4421 | (define_insn "*abssf2" | |
cd2b37d9 RK |
4422 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4423 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4424 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4425 | "fabs %0,%1" |
4426 | [(set_attr "type" "fp")]) | |
4427 | ||
4428 | (define_insn "" | |
cd2b37d9 RK |
4429 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4430 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4431 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4432 | "fnabs %0,%1" |
4433 | [(set_attr "type" "fp")]) | |
4434 | ||
ca7f5001 RK |
4435 | (define_expand "addsf3" |
4436 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4437 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4438 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4439 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4440 | "") |
4441 | ||
4442 | (define_insn "" | |
cd2b37d9 RK |
4443 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4444 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4445 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4446 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4447 | "fadds %0,%1,%2" |
ca7f5001 RK |
4448 | [(set_attr "type" "fp")]) |
4449 | ||
4450 | (define_insn "" | |
4451 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4452 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4453 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4454 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4455 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4456 | [(set_attr "type" "fp")]) |
4457 | ||
4458 | (define_expand "subsf3" | |
4459 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4460 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4461 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4462 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4463 | "") |
4464 | ||
4465 | (define_insn "" | |
4466 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4467 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4468 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4469 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4470 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4471 | [(set_attr "type" "fp")]) |
4472 | ||
ca7f5001 | 4473 | (define_insn "" |
cd2b37d9 RK |
4474 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4475 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4476 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4477 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4478 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4479 | [(set_attr "type" "fp")]) |
4480 | ||
4481 | (define_expand "mulsf3" | |
4482 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4483 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4484 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4485 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4486 | "") |
4487 | ||
4488 | (define_insn "" | |
4489 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4490 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4491 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4492 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4493 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4494 | [(set_attr "type" "fp")]) |
4495 | ||
ca7f5001 | 4496 | (define_insn "" |
cd2b37d9 RK |
4497 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4498 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4499 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4500 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4501 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4502 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4503 | |
ca7f5001 RK |
4504 | (define_expand "divsf3" |
4505 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4506 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4507 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4508 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4509 | "") |
4510 | ||
4511 | (define_insn "" | |
cd2b37d9 RK |
4512 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4513 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4514 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4515 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4516 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4517 | [(set_attr "type" "sdiv")]) |
4518 | ||
4519 | (define_insn "" | |
4520 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4521 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4522 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4523 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4524 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4525 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4526 | |
4527 | (define_insn "" | |
cd2b37d9 RK |
4528 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4529 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4530 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4531 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4532 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4533 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4534 | [(set_attr "type" "fp")]) |
4535 | ||
4536 | (define_insn "" | |
4537 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4538 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4539 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4540 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4541 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4542 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4543 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4544 | |
4545 | (define_insn "" | |
cd2b37d9 RK |
4546 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4547 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4548 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4549 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4550 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4551 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4552 | [(set_attr "type" "fp")]) |
4553 | ||
4554 | (define_insn "" | |
4555 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4556 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4557 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4558 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4559 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4560 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4561 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4562 | |
4563 | (define_insn "" | |
cd2b37d9 RK |
4564 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4565 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4566 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4567 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4568 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4569 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4570 | "fnmadds %0,%1,%2,%3" | |
4571 | [(set_attr "type" "fp")]) | |
4572 | ||
4573 | (define_insn "" | |
4574 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4575 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4576 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4577 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4578 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4579 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4580 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4581 | [(set_attr "type" "fp")]) |
4582 | ||
4583 | (define_insn "" | |
4584 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4585 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4586 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4587 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4588 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4589 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4590 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4591 | |
16823694 GK |
4592 | (define_insn "" |
4593 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4594 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4595 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4596 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4597 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4598 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4599 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4600 | [(set_attr "type" "dmul")]) | |
4601 | ||
1fd4e8c1 | 4602 | (define_insn "" |
cd2b37d9 RK |
4603 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4604 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4605 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4606 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4607 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4608 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4609 | "fnmsubs %0,%1,%2,%3" | |
4610 | [(set_attr "type" "fp")]) | |
4611 | ||
4612 | (define_insn "" | |
4613 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4614 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4615 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4616 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4617 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4618 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4619 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4620 | [(set_attr "type" "fp")]) |
4621 | ||
4622 | (define_insn "" | |
4623 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4624 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4625 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4626 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4627 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4628 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 4629 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4630 | |
16823694 GK |
4631 | (define_insn "" |
4632 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4633 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4634 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4635 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4636 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4637 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4638 | "{fnms|fnmsub} %0,%1,%2,%3" | |
4639 | [(set_attr "type" "fp")]) | |
4640 | ||
ca7f5001 RK |
4641 | (define_expand "sqrtsf2" |
4642 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4643 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 4644 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4645 | "") |
4646 | ||
4647 | (define_insn "" | |
4648 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4649 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4650 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4651 | "fsqrts %0,%1" |
4652 | [(set_attr "type" "ssqrt")]) | |
4653 | ||
4654 | (define_insn "" | |
4655 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4656 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4657 | "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4658 | "fsqrt %0,%1" |
4659 | [(set_attr "type" "dsqrt")]) | |
4660 | ||
94d7001a RK |
4661 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4662 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4663 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
4664 | ;; combine. |
4665 | (define_expand "maxsf3" | |
8e871c05 | 4666 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4667 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
4668 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4669 | (match_dup 1) |
4670 | (match_dup 2)))] | |
a3170dc6 | 4671 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 4672 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
2f607b94 | 4673 | |
8e871c05 | 4674 | (define_expand "minsf3" |
50a0b056 GK |
4675 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
4676 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
4677 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
4678 | (match_dup 2) | |
4679 | (match_dup 1)))] | |
a3170dc6 | 4680 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 4681 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 4682 | |
8e871c05 RK |
4683 | (define_split |
4684 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4685 | (match_operator:SF 3 "min_max_operator" |
4686 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
4687 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
a3170dc6 | 4688 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 GK |
4689 | [(const_int 0)] |
4690 | " | |
6ae08853 | 4691 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
4692 | operands[1], operands[2]); |
4693 | DONE; | |
4694 | }") | |
2f607b94 | 4695 | |
a3170dc6 AH |
4696 | (define_expand "movsicc" |
4697 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4698 | (if_then_else:SI (match_operand 1 "comparison_operator" "") | |
4699 | (match_operand:SI 2 "gpc_reg_operand" "") | |
4700 | (match_operand:SI 3 "gpc_reg_operand" "")))] | |
4701 | "TARGET_ISEL" | |
4702 | " | |
4703 | { | |
4704 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) | |
4705 | DONE; | |
4706 | else | |
4707 | FAIL; | |
4708 | }") | |
4709 | ||
4710 | ;; We use the BASE_REGS for the isel input operands because, if rA is | |
4711 | ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB | |
4712 | ;; because we may switch the operands and rB may end up being rA. | |
4713 | ;; | |
4714 | ;; We need 2 patterns: an unsigned and a signed pattern. We could | |
4715 | ;; leave out the mode in operand 4 and use one pattern, but reload can | |
4716 | ;; change the mode underneath our feet and then gets confused trying | |
4717 | ;; to reload the value. | |
4718 | (define_insn "isel_signed" | |
4719 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4720 | (if_then_else:SI | |
4721 | (match_operator 1 "comparison_operator" | |
4722 | [(match_operand:CC 4 "cc_reg_operand" "y") | |
4723 | (const_int 0)]) | |
4724 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4725 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4726 | "TARGET_ISEL" | |
4727 | "* | |
4728 | { return output_isel (operands); }" | |
4729 | [(set_attr "length" "4")]) | |
4730 | ||
4731 | (define_insn "isel_unsigned" | |
4732 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4733 | (if_then_else:SI | |
4734 | (match_operator 1 "comparison_operator" | |
4735 | [(match_operand:CCUNS 4 "cc_reg_operand" "y") | |
4736 | (const_int 0)]) | |
4737 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4738 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4739 | "TARGET_ISEL" | |
4740 | "* | |
4741 | { return output_isel (operands); }" | |
4742 | [(set_attr "length" "4")]) | |
4743 | ||
94d7001a | 4744 | (define_expand "movsfcc" |
0ad91047 | 4745 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 4746 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4747 | (match_operand:SF 2 "gpc_reg_operand" "") |
4748 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 4749 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4750 | " |
4751 | { | |
50a0b056 GK |
4752 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4753 | DONE; | |
94d7001a | 4754 | else |
50a0b056 | 4755 | FAIL; |
94d7001a | 4756 | }") |
d56d506a | 4757 | |
50a0b056 | 4758 | (define_insn "*fselsfsf4" |
8e871c05 RK |
4759 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4760 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4761 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4762 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4763 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4764 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
4765 | "fsel %0,%1,%2,%3" |
4766 | [(set_attr "type" "fp")]) | |
2f607b94 | 4767 | |
50a0b056 | 4768 | (define_insn "*fseldfsf4" |
94d7001a RK |
4769 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4770 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 4771 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4772 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4773 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4774 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4775 | "fsel %0,%1,%2,%3" |
4776 | [(set_attr "type" "fp")]) | |
d56d506a | 4777 | |
1fd4e8c1 | 4778 | (define_insn "negdf2" |
cd2b37d9 RK |
4779 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4780 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4781 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4782 | "fneg %0,%1" |
4783 | [(set_attr "type" "fp")]) | |
4784 | ||
4785 | (define_insn "absdf2" | |
cd2b37d9 RK |
4786 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4787 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4788 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4789 | "fabs %0,%1" |
4790 | [(set_attr "type" "fp")]) | |
4791 | ||
4792 | (define_insn "" | |
cd2b37d9 RK |
4793 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4794 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4795 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4796 | "fnabs %0,%1" |
4797 | [(set_attr "type" "fp")]) | |
4798 | ||
4799 | (define_insn "adddf3" | |
cd2b37d9 RK |
4800 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4801 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4802 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4803 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4804 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
4805 | [(set_attr "type" "fp")]) |
4806 | ||
4807 | (define_insn "subdf3" | |
cd2b37d9 RK |
4808 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4809 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4810 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4811 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4812 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
4813 | [(set_attr "type" "fp")]) |
4814 | ||
4815 | (define_insn "muldf3" | |
cd2b37d9 RK |
4816 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4817 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4818 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4819 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4820 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 4821 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4822 | |
4823 | (define_insn "divdf3" | |
cd2b37d9 RK |
4824 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4825 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4826 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4827 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4828 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 4829 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4830 | |
4831 | (define_insn "" | |
cd2b37d9 RK |
4832 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4833 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4834 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4835 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4836 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4837 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 4838 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4839 | |
4840 | (define_insn "" | |
cd2b37d9 RK |
4841 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4842 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4843 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4844 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4845 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4846 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 4847 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4848 | |
4849 | (define_insn "" | |
cd2b37d9 RK |
4850 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4851 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4852 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4853 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4854 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4855 | && HONOR_SIGNED_ZEROS (DFmode)" | |
4856 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4857 | [(set_attr "type" "dmul")]) | |
4858 | ||
4859 | (define_insn "" | |
4860 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4861 | (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) | |
4862 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4863 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
4864 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4865 | && ! HONOR_SIGNED_ZEROS (DFmode)" | |
ca7f5001 | 4866 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 4867 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4868 | |
4869 | (define_insn "" | |
cd2b37d9 RK |
4870 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4871 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4872 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4873 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4874 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4875 | && HONOR_SIGNED_ZEROS (DFmode)" | |
4876 | "{fnms|fnmsub} %0,%1,%2,%3" | |
4877 | [(set_attr "type" "dmul")]) | |
4878 | ||
4879 | (define_insn "" | |
4880 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4881 | (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") | |
4882 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4883 | (match_operand:DF 2 "gpc_reg_operand" "f"))))] | |
6ae08853 | 4884 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
16823694 | 4885 | && ! HONOR_SIGNED_ZEROS (DFmode)" |
ca7f5001 | 4886 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 4887 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
4888 | |
4889 | (define_insn "sqrtdf2" | |
4890 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4891 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4892 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4893 | "fsqrt %0,%1" |
4894 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 4895 | |
50a0b056 | 4896 | ;; The conditional move instructions allow us to perform max and min |
6ae08853 | 4897 | ;; operations even when |
b77dfefc | 4898 | |
8e871c05 | 4899 | (define_expand "maxdf3" |
8e871c05 | 4900 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4901 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
4902 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4903 | (match_dup 1) |
4904 | (match_dup 2)))] | |
a3170dc6 | 4905 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 4906 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
b77dfefc | 4907 | |
8e871c05 | 4908 | (define_expand "mindf3" |
50a0b056 GK |
4909 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
4910 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
4911 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
4912 | (match_dup 2) | |
4913 | (match_dup 1)))] | |
a3170dc6 | 4914 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 | 4915 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 4916 | |
8e871c05 RK |
4917 | (define_split |
4918 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4919 | (match_operator:DF 3 "min_max_operator" |
4920 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
4921 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
a3170dc6 | 4922 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
50a0b056 GK |
4923 | [(const_int 0)] |
4924 | " | |
6ae08853 | 4925 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
4926 | operands[1], operands[2]); |
4927 | DONE; | |
4928 | }") | |
b77dfefc | 4929 | |
94d7001a | 4930 | (define_expand "movdfcc" |
0ad91047 | 4931 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 4932 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4933 | (match_operand:DF 2 "gpc_reg_operand" "") |
4934 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 4935 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4936 | " |
4937 | { | |
50a0b056 GK |
4938 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4939 | DONE; | |
94d7001a | 4940 | else |
50a0b056 | 4941 | FAIL; |
94d7001a | 4942 | }") |
d56d506a | 4943 | |
50a0b056 | 4944 | (define_insn "*fseldfdf4" |
8e871c05 RK |
4945 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4946 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4947 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4948 | (match_operand:DF 2 "gpc_reg_operand" "f") |
4949 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4950 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
4951 | "fsel %0,%1,%2,%3" |
4952 | [(set_attr "type" "fp")]) | |
d56d506a | 4953 | |
50a0b056 | 4954 | (define_insn "*fselsfdf4" |
94d7001a RK |
4955 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4956 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4957 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4958 | (match_operand:DF 2 "gpc_reg_operand" "f") |
4959 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
4960 | "TARGET_PPC_GFXOPT" | |
4961 | "fsel %0,%1,%2,%3" | |
4962 | [(set_attr "type" "fp")]) | |
1fd4e8c1 | 4963 | \f |
d095928f AH |
4964 | ;; Conversions to and from floating-point. |
4965 | ||
4966 | (define_expand "fixuns_truncsfsi2" | |
4967 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4968 | (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4969 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
4970 | "") | |
4971 | ||
4972 | (define_expand "fix_truncsfsi2" | |
4973 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4974 | (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4975 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
4976 | "") | |
4977 | ||
9ebbca7d GK |
4978 | ; For each of these conversions, there is a define_expand, a define_insn |
4979 | ; with a '#' template, and a define_split (with C code). The idea is | |
4980 | ; to allow constant folding with the template of the define_insn, | |
4981 | ; then to have the insns split later (between sched1 and final). | |
4982 | ||
1fd4e8c1 | 4983 | (define_expand "floatsidf2" |
802a0058 MM |
4984 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
4985 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
4986 | (use (match_dup 2)) | |
4987 | (use (match_dup 3)) | |
208c89ce | 4988 | (clobber (match_dup 4)) |
a7df97e6 | 4989 | (clobber (match_dup 5)) |
9ebbca7d | 4990 | (clobber (match_dup 6))])] |
a3170dc6 | 4991 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4992 | " |
4993 | { | |
05d49501 AM |
4994 | if (TARGET_POWERPC64) |
4995 | { | |
4996 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
4997 | rtx t1 = gen_reg_rtx (DImode); | |
4998 | rtx t2 = gen_reg_rtx (DImode); | |
4999 | emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); | |
5000 | DONE; | |
5001 | } | |
5002 | ||
802a0058 | 5003 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5004 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); |
9ebbca7d GK |
5005 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5006 | operands[5] = gen_reg_rtx (DFmode); | |
5007 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5008 | }") |
5009 | ||
802a0058 MM |
5010 | (define_insn "*floatsidf2_internal" |
5011 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5012 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5013 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5014 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5015 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 DJ |
5016 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) |
5017 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] | |
a3170dc6 | 5018 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5019 | "#" |
a7df97e6 | 5020 | [(set_attr "length" "24")]) |
802a0058 MM |
5021 | |
5022 | (define_split | |
dbe3df29 | 5023 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
5024 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
5025 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5026 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5027 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5028 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5029 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
a3170dc6 | 5030 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5031 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5032 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5033 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5034 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5035 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5036 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5037 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
208c89ce MM |
5038 | " |
5039 | { | |
9ebbca7d GK |
5040 | rtx lowword, highword; |
5041 | if (GET_CODE (operands[4]) != MEM) | |
5042 | abort(); | |
5043 | highword = XEXP (operands[4], 0); | |
5044 | lowword = plus_constant (highword, 4); | |
5045 | if (! WORDS_BIG_ENDIAN) | |
5046 | { | |
5047 | rtx tmp; | |
5048 | tmp = highword; highword = lowword; lowword = tmp; | |
5049 | } | |
5050 | ||
6ae08853 | 5051 | emit_insn (gen_xorsi3 (operands[6], operands[1], |
9ebbca7d GK |
5052 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); |
5053 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); | |
5054 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5055 | emit_move_insn (operands[5], operands[4]); | |
5056 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5057 | DONE; | |
208c89ce | 5058 | }") |
802a0058 | 5059 | |
a3170dc6 AH |
5060 | (define_expand "floatunssisf2" |
5061 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5062 | (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5063 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5064 | "") | |
5065 | ||
802a0058 MM |
5066 | (define_expand "floatunssidf2" |
5067 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5068 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5069 | (use (match_dup 2)) | |
5070 | (use (match_dup 3)) | |
a7df97e6 | 5071 | (clobber (match_dup 4)) |
9ebbca7d | 5072 | (clobber (match_dup 5))])] |
a3170dc6 | 5073 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5074 | " |
5075 | { | |
05d49501 AM |
5076 | if (TARGET_POWERPC64) |
5077 | { | |
5078 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5079 | rtx t1 = gen_reg_rtx (DImode); | |
5080 | rtx t2 = gen_reg_rtx (DImode); | |
5081 | emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, | |
5082 | t1, t2)); | |
5083 | DONE; | |
5084 | } | |
5085 | ||
802a0058 | 5086 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5087 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); |
9ebbca7d GK |
5088 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5089 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5090 | }") |
5091 | ||
802a0058 MM |
5092 | (define_insn "*floatunssidf2_internal" |
5093 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5094 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5095 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5096 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5097 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 | 5098 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] |
a3170dc6 | 5099 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5100 | "#" |
a7df97e6 | 5101 | [(set_attr "length" "20")]) |
802a0058 MM |
5102 | |
5103 | (define_split | |
5104 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5105 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5106 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5107 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5108 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5109 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
a3170dc6 | 5110 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5111 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5112 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5113 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5114 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5115 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5116 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
5117 | " | |
802a0058 | 5118 | { |
9ebbca7d GK |
5119 | rtx lowword, highword; |
5120 | if (GET_CODE (operands[4]) != MEM) | |
5121 | abort(); | |
5122 | highword = XEXP (operands[4], 0); | |
5123 | lowword = plus_constant (highword, 4); | |
5124 | if (! WORDS_BIG_ENDIAN) | |
f6968f59 | 5125 | { |
9ebbca7d GK |
5126 | rtx tmp; |
5127 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5128 | } |
802a0058 | 5129 | |
9ebbca7d GK |
5130 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); |
5131 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5132 | emit_move_insn (operands[5], operands[4]); | |
5133 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5134 | DONE; | |
5135 | }") | |
1fd4e8c1 | 5136 | |
1fd4e8c1 | 5137 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
5138 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5139 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5140 | (clobber (match_dup 2)) | |
9ebbca7d | 5141 | (clobber (match_dup 3))])] |
a3170dc6 | 5142 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5143 | " |
5144 | { | |
802a0058 | 5145 | operands[2] = gen_reg_rtx (DImode); |
9ebbca7d | 5146 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5147 | }") |
5148 | ||
802a0058 MM |
5149 | (define_insn "*fix_truncdfsi2_internal" |
5150 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5151 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
e3485bbc | 5152 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) |
9ebbca7d | 5153 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
a3170dc6 | 5154 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5155 | "#" |
9ebbca7d | 5156 | [(set_attr "length" "16")]) |
802a0058 MM |
5157 | |
5158 | (define_split | |
5159 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
75540af0 | 5160 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
802a0058 | 5161 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
9ebbca7d | 5162 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] |
a3170dc6 | 5163 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d | 5164 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
75540af0 | 5165 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
9ebbca7d GK |
5166 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
5167 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] | |
5168 | " | |
802a0058 | 5169 | { |
9ebbca7d GK |
5170 | rtx lowword; |
5171 | if (GET_CODE (operands[3]) != MEM) | |
5172 | abort(); | |
5173 | lowword = XEXP (operands[3], 0); | |
5174 | if (WORDS_BIG_ENDIAN) | |
5175 | lowword = plus_constant (lowword, 4); | |
802a0058 | 5176 | |
9ebbca7d GK |
5177 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5178 | emit_move_insn (operands[3], operands[2]); | |
5179 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
5180 | DONE; | |
5181 | }") | |
802a0058 | 5182 | |
615158e2 | 5183 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) |
9ebbca7d GK |
5184 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) |
5185 | ; because the first makes it clear that operand 0 is not live | |
5186 | ; before the instruction. | |
5187 | (define_insn "fctiwz" | |
61c07d3c | 5188 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
615158e2 JJ |
5189 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] |
5190 | UNSPEC_FCTIWZ))] | |
a3170dc6 | 5191 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
a260abc9 DE |
5192 | "{fcirz|fctiwz} %0,%1" |
5193 | [(set_attr "type" "fp")]) | |
5194 | ||
a3170dc6 AH |
5195 | (define_expand "floatsisf2" |
5196 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5197 | (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5198 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5199 | "") | |
5200 | ||
a473029f RK |
5201 | (define_insn "floatdidf2" |
5202 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 5203 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] |
a3170dc6 | 5204 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5205 | "fcfid %0,%1" |
5206 | [(set_attr "type" "fp")]) | |
5207 | ||
05d49501 AM |
5208 | (define_insn_and_split "floatsidf_ppc64" |
5209 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5210 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5211 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5212 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5213 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5214 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5215 | "#" |
ecb62ae7 | 5216 | "&& 1" |
05d49501 AM |
5217 | [(set (match_dup 3) (sign_extend:DI (match_dup 1))) |
5218 | (set (match_dup 2) (match_dup 3)) | |
5219 | (set (match_dup 4) (match_dup 2)) | |
5220 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5221 | "") | |
5222 | ||
5223 | (define_insn_and_split "floatunssidf_ppc64" | |
5224 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5225 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5226 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5227 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5228 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5229 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5230 | "#" |
ecb62ae7 | 5231 | "&& 1" |
05d49501 AM |
5232 | [(set (match_dup 3) (zero_extend:DI (match_dup 1))) |
5233 | (set (match_dup 2) (match_dup 3)) | |
5234 | (set (match_dup 4) (match_dup 2)) | |
5235 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5236 | "") | |
5237 | ||
a473029f | 5238 | (define_insn "fix_truncdfdi2" |
61c07d3c | 5239 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
a473029f | 5240 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] |
a3170dc6 | 5241 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5242 | "fctidz %0,%1" |
5243 | [(set_attr "type" "fp")]) | |
ea112fc4 | 5244 | |
678b7733 AM |
5245 | (define_expand "floatdisf2" |
5246 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5247 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] | |
683bdff7 | 5248 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS" |
678b7733 AM |
5249 | " |
5250 | { | |
5251 | if (!flag_unsafe_math_optimizations) | |
5252 | { | |
5253 | rtx label = gen_label_rtx (); | |
5254 | emit_insn (gen_floatdisf2_internal2 (operands[1], label)); | |
5255 | emit_label (label); | |
5256 | } | |
5257 | emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1])); | |
5258 | DONE; | |
5259 | }") | |
5260 | ||
5261 | ;; This is not IEEE compliant if rounding mode is "round to nearest". | |
5262 | ;; If the DI->DF conversion is inexact, then it's possible to suffer | |
5263 | ;; from double rounding. | |
5264 | (define_insn_and_split "floatdisf2_internal1" | |
ea112fc4 | 5265 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
61c07d3c | 5266 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 | 5267 | (clobber (match_scratch:DF 2 "=f"))] |
678b7733 | 5268 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ea112fc4 DE |
5269 | "#" |
5270 | "&& reload_completed" | |
5271 | [(set (match_dup 2) | |
5272 | (float:DF (match_dup 1))) | |
5273 | (set (match_dup 0) | |
5274 | (float_truncate:SF (match_dup 2)))] | |
5275 | "") | |
678b7733 AM |
5276 | |
5277 | ;; Twiddles bits to avoid double rounding. | |
b6d08ca1 | 5278 | ;; Bits that might be truncated when converting to DFmode are replaced |
678b7733 AM |
5279 | ;; by a bit that won't be lost at that stage, but is below the SFmode |
5280 | ;; rounding position. | |
5281 | (define_expand "floatdisf2_internal2" | |
42a6388c AM |
5282 | [(parallel [(set (match_dup 4) |
5283 | (compare:CC (and:DI (match_operand:DI 0 "" "") | |
5284 | (const_int 2047)) | |
5285 | (const_int 0))) | |
5286 | (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047))) | |
5287 | (clobber (match_scratch:CC 7 ""))]) | |
678b7733 AM |
5288 | (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53))) |
5289 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1))) | |
5290 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
5291 | (label_ref (match_operand:DI 1 "" "")) | |
5292 | (pc))) | |
5293 | (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2))) | |
5294 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
5295 | (label_ref (match_dup 1)) | |
5296 | (pc))) | |
5297 | (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2))) | |
5298 | (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))] | |
683bdff7 | 5299 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS" |
678b7733 AM |
5300 | " |
5301 | { | |
5302 | operands[2] = gen_reg_rtx (DImode); | |
5303 | operands[3] = gen_reg_rtx (DImode); | |
5304 | operands[4] = gen_reg_rtx (CCmode); | |
5305 | operands[5] = gen_reg_rtx (CCUNSmode); | |
5306 | }") | |
1fd4e8c1 RK |
5307 | \f |
5308 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5309 | ;; of instructions. The & constraints are to prevent the register |
5310 | ;; allocator from allocating registers that overlap with the inputs | |
5311 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5312 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5313 | |
266eb58a | 5314 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5315 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5316 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5317 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5318 | "! TARGET_POWERPC64" |
0f645302 MM |
5319 | "* |
5320 | { | |
5321 | if (WORDS_BIG_ENDIAN) | |
5322 | return (GET_CODE (operands[2])) != CONST_INT | |
5323 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5324 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5325 | else | |
5326 | return (GET_CODE (operands[2])) != CONST_INT | |
5327 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5328 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5329 | }" | |
b19003d8 | 5330 | [(set_attr "length" "8")]) |
1fd4e8c1 | 5331 | |
266eb58a | 5332 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5333 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5334 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5335 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5336 | "! TARGET_POWERPC64" |
5502823b RK |
5337 | "* |
5338 | { | |
0f645302 MM |
5339 | if (WORDS_BIG_ENDIAN) |
5340 | return (GET_CODE (operands[1]) != CONST_INT) | |
5341 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5342 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5343 | else | |
5344 | return (GET_CODE (operands[1]) != CONST_INT) | |
5345 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5346 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5347 | }" |
ca7f5001 RK |
5348 | [(set_attr "length" "8")]) |
5349 | ||
266eb58a | 5350 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5351 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5352 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5353 | "! TARGET_POWERPC64" |
5502823b RK |
5354 | "* |
5355 | { | |
5356 | return (WORDS_BIG_ENDIAN) | |
5357 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5358 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5359 | }" | |
ca7f5001 RK |
5360 | [(set_attr "length" "8")]) |
5361 | ||
8ffd9c51 RK |
5362 | (define_expand "mulsidi3" |
5363 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5364 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5365 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5366 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5367 | " |
5368 | { | |
5369 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5370 | { | |
39403d82 DE |
5371 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5372 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5373 | emit_insn (gen_mull_call ()); |
cf27b467 | 5374 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5375 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5376 | else |
5377 | { | |
5378 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5379 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5380 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5381 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5382 | } |
8ffd9c51 RK |
5383 | DONE; |
5384 | } | |
5385 | else if (TARGET_POWER) | |
5386 | { | |
5387 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5388 | DONE; | |
5389 | } | |
5390 | }") | |
deb9225a | 5391 | |
8ffd9c51 | 5392 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5393 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5394 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5395 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5396 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5397 | "TARGET_POWER" |
b19003d8 | 5398 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5399 | [(set_attr "type" "imul") |
5400 | (set_attr "length" "8")]) | |
deb9225a | 5401 | |
f192bf8b | 5402 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5403 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5404 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5405 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5406 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5407 | "* |
5408 | { | |
5409 | return (WORDS_BIG_ENDIAN) | |
5410 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5411 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5412 | }" | |
8ffd9c51 RK |
5413 | [(set_attr "type" "imul") |
5414 | (set_attr "length" "8")]) | |
deb9225a | 5415 | |
ebedb4dd MM |
5416 | (define_split |
5417 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5418 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5419 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5420 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5421 | [(set (match_dup 3) |
5422 | (truncate:SI | |
5423 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5424 | (sign_extend:DI (match_dup 2))) | |
5425 | (const_int 32)))) | |
5426 | (set (match_dup 4) | |
5427 | (mult:SI (match_dup 1) | |
5428 | (match_dup 2)))] | |
5429 | " | |
5430 | { | |
5431 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5432 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5433 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5434 | }") | |
5435 | ||
f192bf8b DE |
5436 | (define_expand "umulsidi3" |
5437 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5438 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5439 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5440 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5441 | " | |
5442 | { | |
5443 | if (TARGET_POWER) | |
5444 | { | |
5445 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5446 | DONE; | |
5447 | } | |
5448 | }") | |
5449 | ||
5450 | (define_insn "umulsidi3_mq" | |
5451 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5452 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5453 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5454 | (clobber (match_scratch:SI 3 "=q"))] | |
5455 | "TARGET_POWERPC && TARGET_POWER" | |
5456 | "* | |
5457 | { | |
5458 | return (WORDS_BIG_ENDIAN) | |
5459 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5460 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5461 | }" | |
5462 | [(set_attr "type" "imul") | |
5463 | (set_attr "length" "8")]) | |
5464 | ||
5465 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5466 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5467 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5468 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5469 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5470 | "* |
5471 | { | |
5472 | return (WORDS_BIG_ENDIAN) | |
5473 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5474 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5475 | }" | |
5476 | [(set_attr "type" "imul") | |
5477 | (set_attr "length" "8")]) | |
5478 | ||
ebedb4dd MM |
5479 | (define_split |
5480 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5481 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5482 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5483 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5484 | [(set (match_dup 3) |
5485 | (truncate:SI | |
5486 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5487 | (zero_extend:DI (match_dup 2))) | |
5488 | (const_int 32)))) | |
5489 | (set (match_dup 4) | |
5490 | (mult:SI (match_dup 1) | |
5491 | (match_dup 2)))] | |
5492 | " | |
5493 | { | |
5494 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5495 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5496 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5497 | }") | |
5498 | ||
8ffd9c51 RK |
5499 | (define_expand "smulsi3_highpart" |
5500 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5501 | (truncate:SI | |
5502 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5503 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5504 | (sign_extend:DI | |
5505 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5506 | (const_int 32))))] | |
5507 | "" | |
5508 | " | |
5509 | { | |
5510 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5511 | { | |
39403d82 DE |
5512 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5513 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5514 | emit_insn (gen_mulh_call ()); |
39403d82 | 5515 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5516 | DONE; |
5517 | } | |
5518 | else if (TARGET_POWER) | |
5519 | { | |
5520 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5521 | DONE; | |
5522 | } | |
5523 | }") | |
deb9225a | 5524 | |
8ffd9c51 RK |
5525 | (define_insn "smulsi3_highpart_mq" |
5526 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5527 | (truncate:SI | |
fada905b MM |
5528 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5529 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5530 | (sign_extend:DI | |
5531 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5532 | (const_int 32)))) |
5533 | (clobber (match_scratch:SI 3 "=q"))] | |
5534 | "TARGET_POWER" | |
5535 | "mul %0,%1,%2" | |
5536 | [(set_attr "type" "imul")]) | |
deb9225a | 5537 | |
f192bf8b | 5538 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5539 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5540 | (truncate:SI | |
fada905b MM |
5541 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5542 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5543 | (sign_extend:DI | |
5544 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5545 | (const_int 32))))] |
f192bf8b | 5546 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5547 | "mulhw %0,%1,%2" |
5548 | [(set_attr "type" "imul")]) | |
deb9225a | 5549 | |
f192bf8b DE |
5550 | (define_expand "umulsi3_highpart" |
5551 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5552 | (truncate:SI | |
5553 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5554 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5555 | (zero_extend:DI | |
5556 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5557 | (const_int 32))))] | |
5558 | "TARGET_POWERPC" | |
5559 | " | |
5560 | { | |
5561 | if (TARGET_POWER) | |
5562 | { | |
5563 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5564 | DONE; | |
5565 | } | |
5566 | }") | |
5567 | ||
5568 | (define_insn "umulsi3_highpart_mq" | |
5569 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5570 | (truncate:SI | |
5571 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5572 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5573 | (zero_extend:DI | |
5574 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5575 | (const_int 32)))) | |
5576 | (clobber (match_scratch:SI 3 "=q"))] | |
5577 | "TARGET_POWERPC && TARGET_POWER" | |
5578 | "mulhwu %0,%1,%2" | |
5579 | [(set_attr "type" "imul")]) | |
5580 | ||
5581 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5582 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5583 | (truncate:SI | |
5584 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5585 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5586 | (zero_extend:DI | |
5587 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5588 | (const_int 32))))] | |
f192bf8b | 5589 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5590 | "mulhwu %0,%1,%2" |
5591 | [(set_attr "type" "imul")]) | |
5592 | ||
5593 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5594 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5595 | ;; why we have the strange constraints below. | |
5596 | (define_insn "ashldi3_power" | |
5597 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5598 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5599 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5600 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5601 | "TARGET_POWER" | |
5602 | "@ | |
5603 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5604 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5605 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5606 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5607 | [(set_attr "length" "8")]) | |
5608 | ||
5609 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5610 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5611 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5612 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5613 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5614 | "TARGET_POWER" | |
5615 | "@ | |
47ad8c61 | 5616 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5617 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5618 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5619 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5620 | [(set_attr "length" "8")]) | |
5621 | ||
5622 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5623 | ;; just handle shifts by constants. | |
5624 | (define_insn "ashrdi3_power" | |
7093ddee | 5625 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5626 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5627 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5628 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5629 | "TARGET_POWER" | |
5630 | "@ | |
5631 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5632 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5633 | [(set_attr "length" "8")]) | |
4aa74a4f FS |
5634 | |
5635 | (define_insn "ashrdi3_no_power" | |
5636 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") | |
5637 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5638 | (match_operand:SI 2 "const_int_operand" "M,i")))] | |
97727e85 | 5639 | "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN" |
4aa74a4f FS |
5640 | "@ |
5641 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5642 | {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" | |
5643 | [(set_attr "length" "8,12")]) | |
683bdff7 FJ |
5644 | |
5645 | (define_insn "*ashrdisi3_noppc64" | |
5646 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 5647 | (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
683bdff7 FJ |
5648 | (const_int 32)) 4))] |
5649 | "TARGET_32BIT && !TARGET_POWERPC64" | |
5650 | "* | |
5651 | { | |
5652 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
5653 | return \"\"; | |
5654 | else | |
5655 | return \"mr %0,%1\"; | |
5656 | }" | |
6ae08853 | 5657 | [(set_attr "length" "4")]) |
683bdff7 | 5658 | |
266eb58a DE |
5659 | \f |
5660 | ;; PowerPC64 DImode operations. | |
5661 | ||
5662 | (define_expand "adddi3" | |
5663 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5664 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 5665 | (match_operand:DI 2 "reg_or_add_cint64_operand" "")))] |
266eb58a DE |
5666 | "" |
5667 | " | |
5668 | { | |
a260abc9 DE |
5669 | if (! TARGET_POWERPC64) |
5670 | { | |
5671 | if (non_short_cint_operand (operands[2], DImode)) | |
5672 | FAIL; | |
5673 | } | |
5674 | else | |
5675 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 5676 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 5677 | { |
677a9668 | 5678 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
5679 | ? operands[0] : gen_reg_rtx (DImode)); |
5680 | ||
2bfcf297 | 5681 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5682 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5683 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
a260abc9 | 5684 | |
2bfcf297 DB |
5685 | if (!CONST_OK_FOR_LETTER_P (rest, 'L')) |
5686 | FAIL; | |
a260abc9 | 5687 | |
2bfcf297 DB |
5688 | /* The ordering here is important for the prolog expander. |
5689 | When space is allocated from the stack, adding 'low' first may | |
5690 | produce a temporary deallocation (which would be bad). */ | |
5691 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest))); | |
a260abc9 DE |
5692 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); |
5693 | DONE; | |
5694 | } | |
266eb58a DE |
5695 | }") |
5696 | ||
5697 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
5698 | ;; allowing register zero as source. | |
5699 | ||
a260abc9 | 5700 | (define_insn "*adddi3_internal1" |
266eb58a DE |
5701 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
5702 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 5703 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
5704 | "TARGET_POWERPC64" |
5705 | "@ | |
5706 | add %0,%1,%2 | |
5707 | addi %0,%1,%2 | |
5708 | addic %0,%1,%2 | |
802a0058 | 5709 | addis %0,%1,%v2") |
266eb58a | 5710 | |
a260abc9 | 5711 | (define_insn "*adddi3_internal2" |
9ebbca7d GK |
5712 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
5713 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5714 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5715 | (const_int 0))) |
9ebbca7d | 5716 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
683bdff7 | 5717 | "TARGET_64BIT" |
266eb58a DE |
5718 | "@ |
5719 | add. %3,%1,%2 | |
9ebbca7d GK |
5720 | addic. %3,%1,%2 |
5721 | # | |
5722 | #" | |
a62bfff2 | 5723 | [(set_attr "type" "fast_compare,compare,compare,compare") |
9ebbca7d GK |
5724 | (set_attr "length" "4,4,8,8")]) |
5725 | ||
5726 | (define_split | |
5727 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5728 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5729 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5730 | (const_int 0))) | |
5731 | (clobber (match_scratch:DI 3 ""))] | |
5732 | "TARGET_POWERPC64 && reload_completed" | |
5733 | [(set (match_dup 3) | |
5734 | (plus:DI (match_dup 1) (match_dup 2))) | |
5735 | (set (match_dup 0) | |
5736 | (compare:CC (match_dup 3) | |
5737 | (const_int 0)))] | |
5738 | "") | |
266eb58a | 5739 | |
a260abc9 | 5740 | (define_insn "*adddi3_internal3" |
9ebbca7d GK |
5741 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
5742 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5743 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5744 | (const_int 0))) |
9ebbca7d | 5745 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
266eb58a | 5746 | (plus:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 5747 | "TARGET_64BIT" |
266eb58a DE |
5748 | "@ |
5749 | add. %0,%1,%2 | |
9ebbca7d GK |
5750 | addic. %0,%1,%2 |
5751 | # | |
5752 | #" | |
a62bfff2 | 5753 | [(set_attr "type" "fast_compare,compare,compare,compare") |
9ebbca7d GK |
5754 | (set_attr "length" "4,4,8,8")]) |
5755 | ||
5756 | (define_split | |
5757 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5758 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5759 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5760 | (const_int 0))) | |
5761 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5762 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5763 | "TARGET_POWERPC64 && reload_completed" | |
5764 | [(set (match_dup 0) | |
5765 | (plus:DI (match_dup 1) (match_dup 2))) | |
5766 | (set (match_dup 3) | |
5767 | (compare:CC (match_dup 0) | |
5768 | (const_int 0)))] | |
5769 | "") | |
266eb58a DE |
5770 | |
5771 | ;; Split an add that we can't do in one insn into two insns, each of which | |
5772 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
5773 | ;; add should be last in case the result gets used in an address. | |
5774 | ||
5775 | (define_split | |
5776 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5777 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5778 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
5779 | "TARGET_POWERPC64" | |
5780 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
5781 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
5782 | " | |
5783 | { | |
2bfcf297 | 5784 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5785 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5786 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
266eb58a | 5787 | |
2bfcf297 DB |
5788 | operands[4] = GEN_INT (low); |
5789 | if (CONST_OK_FOR_LETTER_P (rest, 'L')) | |
5790 | operands[3] = GEN_INT (rest); | |
5791 | else if (! no_new_pseudos) | |
38886f37 | 5792 | { |
2bfcf297 DB |
5793 | operands[3] = gen_reg_rtx (DImode); |
5794 | emit_move_insn (operands[3], operands[2]); | |
5795 | emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); | |
5796 | DONE; | |
38886f37 | 5797 | } |
2bfcf297 DB |
5798 | else |
5799 | FAIL; | |
266eb58a DE |
5800 | }") |
5801 | ||
5802 | (define_insn "one_cmpldi2" | |
5803 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5804 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5805 | "TARGET_POWERPC64" | |
5806 | "nor %0,%1,%1") | |
5807 | ||
5808 | (define_insn "" | |
9ebbca7d GK |
5809 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5810 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5811 | (const_int 0))) |
9ebbca7d | 5812 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 5813 | "TARGET_64BIT" |
9ebbca7d GK |
5814 | "@ |
5815 | nor. %2,%1,%1 | |
5816 | #" | |
5817 | [(set_attr "type" "compare") | |
5818 | (set_attr "length" "4,8")]) | |
5819 | ||
5820 | (define_split | |
5821 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5822 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5823 | (const_int 0))) | |
5824 | (clobber (match_scratch:DI 2 ""))] | |
5825 | "TARGET_POWERPC64 && reload_completed" | |
5826 | [(set (match_dup 2) | |
5827 | (not:DI (match_dup 1))) | |
5828 | (set (match_dup 0) | |
5829 | (compare:CC (match_dup 2) | |
5830 | (const_int 0)))] | |
5831 | "") | |
266eb58a DE |
5832 | |
5833 | (define_insn "" | |
9ebbca7d GK |
5834 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5835 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5836 | (const_int 0))) |
9ebbca7d | 5837 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 5838 | (not:DI (match_dup 1)))] |
683bdff7 | 5839 | "TARGET_64BIT" |
9ebbca7d GK |
5840 | "@ |
5841 | nor. %0,%1,%1 | |
5842 | #" | |
5843 | [(set_attr "type" "compare") | |
5844 | (set_attr "length" "4,8")]) | |
5845 | ||
5846 | (define_split | |
5847 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5848 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5849 | (const_int 0))) | |
5850 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5851 | (not:DI (match_dup 1)))] | |
5852 | "TARGET_POWERPC64 && reload_completed" | |
5853 | [(set (match_dup 0) | |
5854 | (not:DI (match_dup 1))) | |
5855 | (set (match_dup 2) | |
5856 | (compare:CC (match_dup 0) | |
5857 | (const_int 0)))] | |
5858 | "") | |
266eb58a DE |
5859 | |
5860 | (define_insn "" | |
5861 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5862 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
5863 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
5864 | "TARGET_POWERPC64" | |
5865 | "@ | |
5866 | subf %0,%2,%1 | |
5867 | subfic %0,%2,%1") | |
5868 | ||
5869 | (define_insn "" | |
9ebbca7d GK |
5870 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5871 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5872 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5873 | (const_int 0))) |
9ebbca7d | 5874 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 5875 | "TARGET_64BIT" |
9ebbca7d GK |
5876 | "@ |
5877 | subf. %3,%2,%1 | |
5878 | #" | |
a62bfff2 | 5879 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
5880 | (set_attr "length" "4,8")]) |
5881 | ||
5882 | (define_split | |
5883 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5884 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5885 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5886 | (const_int 0))) | |
5887 | (clobber (match_scratch:DI 3 ""))] | |
5888 | "TARGET_POWERPC64 && reload_completed" | |
5889 | [(set (match_dup 3) | |
5890 | (minus:DI (match_dup 1) (match_dup 2))) | |
5891 | (set (match_dup 0) | |
5892 | (compare:CC (match_dup 3) | |
5893 | (const_int 0)))] | |
5894 | "") | |
266eb58a DE |
5895 | |
5896 | (define_insn "" | |
9ebbca7d GK |
5897 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
5898 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5899 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5900 | (const_int 0))) |
9ebbca7d | 5901 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 5902 | (minus:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 5903 | "TARGET_64BIT" |
9ebbca7d GK |
5904 | "@ |
5905 | subf. %0,%2,%1 | |
5906 | #" | |
a62bfff2 | 5907 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
5908 | (set_attr "length" "4,8")]) |
5909 | ||
5910 | (define_split | |
5911 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5912 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5913 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5914 | (const_int 0))) | |
5915 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5916 | (minus:DI (match_dup 1) (match_dup 2)))] | |
5917 | "TARGET_POWERPC64 && reload_completed" | |
5918 | [(set (match_dup 0) | |
5919 | (minus:DI (match_dup 1) (match_dup 2))) | |
5920 | (set (match_dup 3) | |
5921 | (compare:CC (match_dup 0) | |
5922 | (const_int 0)))] | |
5923 | "") | |
266eb58a DE |
5924 | |
5925 | (define_expand "subdi3" | |
5926 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5927 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
2bfcf297 | 5928 | (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))] |
266eb58a DE |
5929 | "" |
5930 | " | |
5931 | { | |
5932 | if (GET_CODE (operands[2]) == CONST_INT) | |
5933 | { | |
5934 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
5935 | negate_rtx (DImode, operands[2]))); | |
5936 | DONE; | |
5937 | } | |
5938 | }") | |
5939 | ||
ea112fc4 | 5940 | (define_insn_and_split "absdi2" |
266eb58a | 5941 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 5942 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) |
266eb58a DE |
5943 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
5944 | "TARGET_POWERPC64" | |
ea112fc4 DE |
5945 | "#" |
5946 | "&& reload_completed" | |
a260abc9 | 5947 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5948 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 5949 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
5950 | "") |
5951 | ||
ea112fc4 | 5952 | (define_insn_and_split "*nabsdi2" |
266eb58a | 5953 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 5954 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) |
266eb58a DE |
5955 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
5956 | "TARGET_POWERPC64" | |
ea112fc4 DE |
5957 | "#" |
5958 | "&& reload_completed" | |
a260abc9 | 5959 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5960 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 5961 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
5962 | "") |
5963 | ||
5964 | (define_expand "negdi2" | |
5965 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5966 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
5967 | "" | |
5968 | "") | |
5969 | ||
5970 | (define_insn "" | |
5971 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5972 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5973 | "TARGET_POWERPC64" | |
5974 | "neg %0,%1") | |
5975 | ||
5976 | (define_insn "" | |
9ebbca7d GK |
5977 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5978 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5979 | (const_int 0))) |
9ebbca7d | 5980 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 5981 | "TARGET_64BIT" |
9ebbca7d GK |
5982 | "@ |
5983 | neg. %2,%1 | |
5984 | #" | |
a62bfff2 | 5985 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
5986 | (set_attr "length" "4,8")]) |
5987 | ||
5988 | (define_split | |
5989 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5990 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5991 | (const_int 0))) | |
5992 | (clobber (match_scratch:DI 2 ""))] | |
5993 | "TARGET_POWERPC64 && reload_completed" | |
5994 | [(set (match_dup 2) | |
5995 | (neg:DI (match_dup 1))) | |
5996 | (set (match_dup 0) | |
5997 | (compare:CC (match_dup 2) | |
5998 | (const_int 0)))] | |
5999 | "") | |
815cdc52 | 6000 | |
29ae5b89 | 6001 | (define_insn "" |
9ebbca7d GK |
6002 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
6003 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 6004 | (const_int 0))) |
9ebbca7d | 6005 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 6006 | (neg:DI (match_dup 1)))] |
683bdff7 | 6007 | "TARGET_64BIT" |
9ebbca7d GK |
6008 | "@ |
6009 | neg. %0,%1 | |
6010 | #" | |
a62bfff2 | 6011 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
6012 | (set_attr "length" "4,8")]) |
6013 | ||
6014 | (define_split | |
6015 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
6016 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6017 | (const_int 0))) | |
6018 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6019 | (neg:DI (match_dup 1)))] | |
6020 | "TARGET_POWERPC64 && reload_completed" | |
6021 | [(set (match_dup 0) | |
6022 | (neg:DI (match_dup 1))) | |
6023 | (set (match_dup 2) | |
6024 | (compare:CC (match_dup 0) | |
6025 | (const_int 0)))] | |
6026 | "") | |
266eb58a | 6027 | |
1b1edcfa DE |
6028 | (define_insn "clzdi2" |
6029 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6030 | (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6031 | "TARGET_POWERPC64" | |
6032 | "cntlzd %0,%1") | |
6033 | ||
6034 | (define_expand "ctzdi2" | |
4977bab6 | 6035 | [(set (match_dup 2) |
1b1edcfa | 6036 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) |
6ae08853 AM |
6037 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) |
6038 | (match_dup 2))) | |
1b1edcfa | 6039 | (clobber (scratch:CC))]) |
d865b122 | 6040 | (set (match_dup 4) (clz:DI (match_dup 3))) |
4977bab6 | 6041 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 6042 | (minus:DI (const_int 63) (match_dup 4)))] |
266eb58a | 6043 | "TARGET_POWERPC64" |
4977bab6 | 6044 | { |
6ae08853 | 6045 | operands[2] = gen_reg_rtx (DImode); |
4977bab6 ZW |
6046 | operands[3] = gen_reg_rtx (DImode); |
6047 | operands[4] = gen_reg_rtx (DImode); | |
6048 | }) | |
6049 | ||
1b1edcfa DE |
6050 | (define_expand "ffsdi2" |
6051 | [(set (match_dup 2) | |
6052 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
6ae08853 AM |
6053 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) |
6054 | (match_dup 2))) | |
1b1edcfa DE |
6055 | (clobber (scratch:CC))]) |
6056 | (set (match_dup 4) (clz:DI (match_dup 3))) | |
6057 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6058 | (minus:DI (const_int 64) (match_dup 4)))] | |
4977bab6 | 6059 | "TARGET_POWERPC64" |
1b1edcfa | 6060 | { |
6ae08853 | 6061 | operands[2] = gen_reg_rtx (DImode); |
1b1edcfa DE |
6062 | operands[3] = gen_reg_rtx (DImode); |
6063 | operands[4] = gen_reg_rtx (DImode); | |
6064 | }) | |
266eb58a DE |
6065 | |
6066 | (define_insn "muldi3" | |
6067 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6068 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
6069 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6070 | "TARGET_POWERPC64" | |
6071 | "mulld %0,%1,%2" | |
3cb999d8 | 6072 | [(set_attr "type" "lmul")]) |
266eb58a | 6073 | |
9259f3b0 DE |
6074 | (define_insn "*muldi3_internal1" |
6075 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6076 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6077 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
6078 | (const_int 0))) | |
6079 | (clobber (match_scratch:DI 3 "=r,r"))] | |
6080 | "TARGET_POWERPC64" | |
6081 | "@ | |
6082 | mulld. %3,%1,%2 | |
6083 | #" | |
6084 | [(set_attr "type" "lmul_compare") | |
6085 | (set_attr "length" "4,8")]) | |
6086 | ||
6087 | (define_split | |
6088 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6089 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6090 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6091 | (const_int 0))) | |
6092 | (clobber (match_scratch:DI 3 ""))] | |
6093 | "TARGET_POWERPC64 && reload_completed" | |
6094 | [(set (match_dup 3) | |
6095 | (mult:DI (match_dup 1) (match_dup 2))) | |
6096 | (set (match_dup 0) | |
6097 | (compare:CC (match_dup 3) | |
6098 | (const_int 0)))] | |
6099 | "") | |
6100 | ||
6101 | (define_insn "*muldi3_internal2" | |
6102 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") | |
6103 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6104 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
6105 | (const_int 0))) | |
6106 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6107 | (mult:DI (match_dup 1) (match_dup 2)))] | |
6108 | "TARGET_POWERPC64" | |
6109 | "@ | |
6110 | mulld. %0,%1,%2 | |
6111 | #" | |
6112 | [(set_attr "type" "lmul_compare") | |
6113 | (set_attr "length" "4,8")]) | |
6114 | ||
6115 | (define_split | |
6116 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6117 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6118 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6119 | (const_int 0))) | |
6120 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6121 | (mult:DI (match_dup 1) (match_dup 2)))] | |
6122 | "TARGET_POWERPC64 && reload_completed" | |
6123 | [(set (match_dup 0) | |
6124 | (mult:DI (match_dup 1) (match_dup 2))) | |
6125 | (set (match_dup 3) | |
6126 | (compare:CC (match_dup 0) | |
6127 | (const_int 0)))] | |
6128 | "") | |
6129 | ||
266eb58a DE |
6130 | (define_insn "smuldi3_highpart" |
6131 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6132 | (truncate:DI | |
6133 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
6134 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6135 | (sign_extend:TI | |
6136 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6137 | (const_int 64))))] | |
6138 | "TARGET_POWERPC64" | |
6139 | "mulhd %0,%1,%2" | |
3cb999d8 | 6140 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6141 | |
6142 | (define_insn "umuldi3_highpart" | |
6143 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6144 | (truncate:DI | |
6145 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
6146 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6147 | (zero_extend:TI | |
6148 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6149 | (const_int 64))))] | |
6150 | "TARGET_POWERPC64" | |
6151 | "mulhdu %0,%1,%2" | |
3cb999d8 | 6152 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6153 | |
6154 | (define_expand "divdi3" | |
6155 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6156 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6157 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6158 | "TARGET_POWERPC64" | |
6159 | " | |
6160 | { | |
6161 | if (GET_CODE (operands[2]) == CONST_INT | |
2bfcf297 | 6162 | && INTVAL (operands[2]) > 0 |
266eb58a DE |
6163 | && exact_log2 (INTVAL (operands[2])) >= 0) |
6164 | ; | |
6165 | else | |
6166 | operands[2] = force_reg (DImode, operands[2]); | |
6167 | }") | |
6168 | ||
6169 | (define_expand "moddi3" | |
6170 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6171 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6172 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6173 | "TARGET_POWERPC64" | |
6174 | " | |
6175 | { | |
2bfcf297 | 6176 | int i; |
266eb58a DE |
6177 | rtx temp1; |
6178 | rtx temp2; | |
6179 | ||
2bfcf297 DB |
6180 | if (GET_CODE (operands[2]) != CONST_INT |
6181 | || INTVAL (operands[2]) <= 0 | |
6182 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) | |
266eb58a DE |
6183 | FAIL; |
6184 | ||
6185 | temp1 = gen_reg_rtx (DImode); | |
6186 | temp2 = gen_reg_rtx (DImode); | |
6187 | ||
6188 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6189 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6190 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6191 | DONE; | |
6192 | }") | |
6193 | ||
6194 | (define_insn "" | |
6195 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6196 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
6197 | (match_operand:DI 2 "exact_log2_cint_operand" "N")))] |
6198 | "TARGET_POWERPC64" | |
266eb58a DE |
6199 | "sradi %0,%1,%p2\;addze %0,%0" |
6200 | [(set_attr "length" "8")]) | |
6201 | ||
6202 | (define_insn "" | |
9ebbca7d GK |
6203 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6204 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6205 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6206 | (const_int 0))) |
9ebbca7d | 6207 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6208 | "TARGET_64BIT" |
9ebbca7d GK |
6209 | "@ |
6210 | sradi %3,%1,%p2\;addze. %3,%3 | |
6211 | #" | |
266eb58a | 6212 | [(set_attr "type" "compare") |
9ebbca7d GK |
6213 | (set_attr "length" "8,12")]) |
6214 | ||
6215 | (define_split | |
6216 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6217 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6218 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6219 | (const_int 0))) |
6220 | (clobber (match_scratch:DI 3 ""))] | |
2bfcf297 | 6221 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6222 | [(set (match_dup 3) |
6223 | (div:DI (match_dup 1) (match_dup 2))) | |
6224 | (set (match_dup 0) | |
6225 | (compare:CC (match_dup 3) | |
6226 | (const_int 0)))] | |
6227 | "") | |
266eb58a DE |
6228 | |
6229 | (define_insn "" | |
9ebbca7d GK |
6230 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6231 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6232 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6233 | (const_int 0))) |
9ebbca7d | 6234 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6235 | (div:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6236 | "TARGET_64BIT" |
9ebbca7d GK |
6237 | "@ |
6238 | sradi %0,%1,%p2\;addze. %0,%0 | |
6239 | #" | |
266eb58a | 6240 | [(set_attr "type" "compare") |
9ebbca7d | 6241 | (set_attr "length" "8,12")]) |
266eb58a | 6242 | |
9ebbca7d GK |
6243 | (define_split |
6244 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6245 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6246 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6247 | (const_int 0))) |
6248 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6249 | (div:DI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 6250 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6251 | [(set (match_dup 0) |
6252 | (div:DI (match_dup 1) (match_dup 2))) | |
6253 | (set (match_dup 3) | |
6254 | (compare:CC (match_dup 0) | |
6255 | (const_int 0)))] | |
6256 | "") | |
6257 | ||
6258 | (define_insn "" | |
6259 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6260 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6261 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6262 | "TARGET_POWERPC64" |
6263 | "divd %0,%1,%2" | |
3cb999d8 | 6264 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6265 | |
6266 | (define_insn "udivdi3" | |
6267 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6268 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6269 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6270 | "TARGET_POWERPC64" | |
6271 | "divdu %0,%1,%2" | |
3cb999d8 | 6272 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6273 | |
6274 | (define_insn "rotldi3" | |
6275 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6276 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6277 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6278 | "TARGET_POWERPC64" | |
a66078ee | 6279 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6280 | |
a260abc9 | 6281 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6282 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6283 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6284 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6285 | (const_int 0))) |
9ebbca7d | 6286 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6287 | "TARGET_64BIT" |
9ebbca7d GK |
6288 | "@ |
6289 | rld%I2cl. %3,%1,%H2,0 | |
6290 | #" | |
6291 | [(set_attr "type" "delayed_compare") | |
6292 | (set_attr "length" "4,8")]) | |
6293 | ||
6294 | (define_split | |
6295 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6296 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6297 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6298 | (const_int 0))) | |
6299 | (clobber (match_scratch:DI 3 ""))] | |
6300 | "TARGET_POWERPC64 && reload_completed" | |
6301 | [(set (match_dup 3) | |
6302 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6303 | (set (match_dup 0) | |
6304 | (compare:CC (match_dup 3) | |
6305 | (const_int 0)))] | |
6306 | "") | |
266eb58a | 6307 | |
a260abc9 | 6308 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6309 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6310 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6311 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6312 | (const_int 0))) |
9ebbca7d | 6313 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6314 | (rotate:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6315 | "TARGET_64BIT" |
9ebbca7d GK |
6316 | "@ |
6317 | rld%I2cl. %0,%1,%H2,0 | |
6318 | #" | |
6319 | [(set_attr "type" "delayed_compare") | |
6320 | (set_attr "length" "4,8")]) | |
6321 | ||
6322 | (define_split | |
6323 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6324 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6325 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6326 | (const_int 0))) | |
6327 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6328 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6329 | "TARGET_POWERPC64 && reload_completed" | |
6330 | [(set (match_dup 0) | |
6331 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6332 | (set (match_dup 3) | |
6333 | (compare:CC (match_dup 0) | |
6334 | (const_int 0)))] | |
6335 | "") | |
266eb58a | 6336 | |
a260abc9 DE |
6337 | (define_insn "*rotldi3_internal4" |
6338 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6339 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6340 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
ce71f754 | 6341 | (match_operand:DI 3 "mask64_operand" "n")))] |
a260abc9 DE |
6342 | "TARGET_POWERPC64" |
6343 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6344 | ||
6345 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6346 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6347 | (compare:CC (and:DI |
9ebbca7d GK |
6348 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6349 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6350 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6351 | (const_int 0))) |
9ebbca7d | 6352 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6353 | "TARGET_64BIT" |
9ebbca7d GK |
6354 | "@ |
6355 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6356 | #" | |
6357 | [(set_attr "type" "delayed_compare") | |
6358 | (set_attr "length" "4,8")]) | |
6359 | ||
6360 | (define_split | |
6361 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6362 | (compare:CC (and:DI | |
6363 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6364 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6365 | (match_operand:DI 3 "mask64_operand" "")) | |
6366 | (const_int 0))) | |
6367 | (clobber (match_scratch:DI 4 ""))] | |
6368 | "TARGET_POWERPC64 && reload_completed" | |
6369 | [(set (match_dup 4) | |
6370 | (and:DI (rotate:DI (match_dup 1) | |
6371 | (match_dup 2)) | |
6372 | (match_dup 3))) | |
6373 | (set (match_dup 0) | |
6374 | (compare:CC (match_dup 4) | |
6375 | (const_int 0)))] | |
6376 | "") | |
a260abc9 DE |
6377 | |
6378 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6379 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6380 | (compare:CC (and:DI |
9ebbca7d GK |
6381 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6382 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6383 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6384 | (const_int 0))) |
9ebbca7d | 6385 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6386 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6387 | "TARGET_64BIT" |
9ebbca7d GK |
6388 | "@ |
6389 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6390 | #" | |
6391 | [(set_attr "type" "delayed_compare") | |
6392 | (set_attr "length" "4,8")]) | |
6393 | ||
6394 | (define_split | |
6395 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6396 | (compare:CC (and:DI | |
6397 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6398 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6399 | (match_operand:DI 3 "mask64_operand" "")) | |
6400 | (const_int 0))) | |
6401 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6402 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6403 | "TARGET_POWERPC64 && reload_completed" | |
6404 | [(set (match_dup 0) | |
6405 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6406 | (set (match_dup 4) | |
6407 | (compare:CC (match_dup 0) | |
6408 | (const_int 0)))] | |
6409 | "") | |
a260abc9 DE |
6410 | |
6411 | (define_insn "*rotldi3_internal7" | |
6412 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6413 | (zero_extend:DI | |
6414 | (subreg:QI | |
6415 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6416 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6417 | "TARGET_POWERPC64" | |
6418 | "rld%I2cl %0,%1,%H2,56") | |
6419 | ||
6420 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6421 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6422 | (compare:CC (zero_extend:DI |
6423 | (subreg:QI | |
9ebbca7d GK |
6424 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6425 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6426 | (const_int 0))) |
9ebbca7d | 6427 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6428 | "TARGET_64BIT" |
9ebbca7d GK |
6429 | "@ |
6430 | rld%I2cl. %3,%1,%H2,56 | |
6431 | #" | |
6432 | [(set_attr "type" "delayed_compare") | |
6433 | (set_attr "length" "4,8")]) | |
6434 | ||
6435 | (define_split | |
6436 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6437 | (compare:CC (zero_extend:DI | |
6438 | (subreg:QI | |
6439 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6440 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6441 | (const_int 0))) | |
6442 | (clobber (match_scratch:DI 3 ""))] | |
6443 | "TARGET_POWERPC64 && reload_completed" | |
6444 | [(set (match_dup 3) | |
6445 | (zero_extend:DI (subreg:QI | |
6446 | (rotate:DI (match_dup 1) | |
6447 | (match_dup 2)) 0))) | |
6448 | (set (match_dup 0) | |
6449 | (compare:CC (match_dup 3) | |
6450 | (const_int 0)))] | |
6451 | "") | |
a260abc9 DE |
6452 | |
6453 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6454 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6455 | (compare:CC (zero_extend:DI |
6456 | (subreg:QI | |
9ebbca7d GK |
6457 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6458 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6459 | (const_int 0))) |
9ebbca7d | 6460 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6461 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6462 | "TARGET_64BIT" |
9ebbca7d GK |
6463 | "@ |
6464 | rld%I2cl. %0,%1,%H2,56 | |
6465 | #" | |
6466 | [(set_attr "type" "delayed_compare") | |
6467 | (set_attr "length" "4,8")]) | |
6468 | ||
6469 | (define_split | |
6470 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6471 | (compare:CC (zero_extend:DI | |
6472 | (subreg:QI | |
6473 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6474 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6475 | (const_int 0))) | |
6476 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6477 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6478 | "TARGET_POWERPC64 && reload_completed" | |
6479 | [(set (match_dup 0) | |
6480 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6481 | (set (match_dup 3) | |
6482 | (compare:CC (match_dup 0) | |
6483 | (const_int 0)))] | |
6484 | "") | |
a260abc9 DE |
6485 | |
6486 | (define_insn "*rotldi3_internal10" | |
6487 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6488 | (zero_extend:DI | |
6489 | (subreg:HI | |
6490 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6491 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6492 | "TARGET_POWERPC64" | |
6493 | "rld%I2cl %0,%1,%H2,48") | |
6494 | ||
6495 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6496 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6497 | (compare:CC (zero_extend:DI |
6498 | (subreg:HI | |
9ebbca7d GK |
6499 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6500 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6501 | (const_int 0))) |
9ebbca7d | 6502 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6503 | "TARGET_64BIT" |
9ebbca7d GK |
6504 | "@ |
6505 | rld%I2cl. %3,%1,%H2,48 | |
6506 | #" | |
6507 | [(set_attr "type" "delayed_compare") | |
6508 | (set_attr "length" "4,8")]) | |
6509 | ||
6510 | (define_split | |
6511 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6512 | (compare:CC (zero_extend:DI | |
6513 | (subreg:HI | |
6514 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6515 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6516 | (const_int 0))) | |
6517 | (clobber (match_scratch:DI 3 ""))] | |
6518 | "TARGET_POWERPC64 && reload_completed" | |
6519 | [(set (match_dup 3) | |
6520 | (zero_extend:DI (subreg:HI | |
6521 | (rotate:DI (match_dup 1) | |
6522 | (match_dup 2)) 0))) | |
6523 | (set (match_dup 0) | |
6524 | (compare:CC (match_dup 3) | |
6525 | (const_int 0)))] | |
6526 | "") | |
a260abc9 DE |
6527 | |
6528 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6529 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6530 | (compare:CC (zero_extend:DI |
6531 | (subreg:HI | |
9ebbca7d GK |
6532 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6533 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6534 | (const_int 0))) |
9ebbca7d | 6535 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6536 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6537 | "TARGET_64BIT" |
9ebbca7d GK |
6538 | "@ |
6539 | rld%I2cl. %0,%1,%H2,48 | |
6540 | #" | |
6541 | [(set_attr "type" "delayed_compare") | |
6542 | (set_attr "length" "4,8")]) | |
6543 | ||
6544 | (define_split | |
6545 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6546 | (compare:CC (zero_extend:DI | |
6547 | (subreg:HI | |
6548 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6549 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6550 | (const_int 0))) | |
6551 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6552 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6553 | "TARGET_POWERPC64 && reload_completed" | |
6554 | [(set (match_dup 0) | |
6555 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6556 | (set (match_dup 3) | |
6557 | (compare:CC (match_dup 0) | |
6558 | (const_int 0)))] | |
6559 | "") | |
a260abc9 DE |
6560 | |
6561 | (define_insn "*rotldi3_internal13" | |
6562 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6563 | (zero_extend:DI | |
6564 | (subreg:SI | |
6565 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6566 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6567 | "TARGET_POWERPC64" | |
6568 | "rld%I2cl %0,%1,%H2,32") | |
6569 | ||
6570 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6571 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6572 | (compare:CC (zero_extend:DI |
6573 | (subreg:SI | |
9ebbca7d GK |
6574 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6575 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6576 | (const_int 0))) |
9ebbca7d | 6577 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6578 | "TARGET_64BIT" |
9ebbca7d GK |
6579 | "@ |
6580 | rld%I2cl. %3,%1,%H2,32 | |
6581 | #" | |
6582 | [(set_attr "type" "delayed_compare") | |
6583 | (set_attr "length" "4,8")]) | |
6584 | ||
6585 | (define_split | |
6586 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6587 | (compare:CC (zero_extend:DI | |
6588 | (subreg:SI | |
6589 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6590 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6591 | (const_int 0))) | |
6592 | (clobber (match_scratch:DI 3 ""))] | |
6593 | "TARGET_POWERPC64 && reload_completed" | |
6594 | [(set (match_dup 3) | |
6595 | (zero_extend:DI (subreg:SI | |
6596 | (rotate:DI (match_dup 1) | |
6597 | (match_dup 2)) 0))) | |
6598 | (set (match_dup 0) | |
6599 | (compare:CC (match_dup 3) | |
6600 | (const_int 0)))] | |
6601 | "") | |
a260abc9 DE |
6602 | |
6603 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6604 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6605 | (compare:CC (zero_extend:DI |
6606 | (subreg:SI | |
9ebbca7d GK |
6607 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6608 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6609 | (const_int 0))) |
9ebbca7d | 6610 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6611 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6612 | "TARGET_64BIT" |
9ebbca7d GK |
6613 | "@ |
6614 | rld%I2cl. %0,%1,%H2,32 | |
6615 | #" | |
6616 | [(set_attr "type" "delayed_compare") | |
6617 | (set_attr "length" "4,8")]) | |
6618 | ||
6619 | (define_split | |
6620 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6621 | (compare:CC (zero_extend:DI | |
6622 | (subreg:SI | |
6623 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6624 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6625 | (const_int 0))) | |
6626 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6627 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6628 | "TARGET_POWERPC64 && reload_completed" | |
6629 | [(set (match_dup 0) | |
6630 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6631 | (set (match_dup 3) | |
6632 | (compare:CC (match_dup 0) | |
6633 | (const_int 0)))] | |
6634 | "") | |
a260abc9 | 6635 | |
266eb58a DE |
6636 | (define_expand "ashldi3" |
6637 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6638 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6639 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6640 | "TARGET_POWERPC64 || TARGET_POWER" | |
6641 | " | |
6642 | { | |
6643 | if (TARGET_POWERPC64) | |
6644 | ; | |
6645 | else if (TARGET_POWER) | |
6646 | { | |
6647 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6648 | DONE; | |
6649 | } | |
6650 | else | |
6651 | FAIL; | |
6652 | }") | |
6653 | ||
e2c953b6 | 6654 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
6655 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6656 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6657 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6658 | "TARGET_POWERPC64" | |
a66078ee | 6659 | "sld%I2 %0,%1,%H2" |
266eb58a | 6660 | [(set_attr "length" "8")]) |
6ae08853 | 6661 | |
e2c953b6 | 6662 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
6663 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6664 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6665 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6666 | (const_int 0))) |
9ebbca7d | 6667 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6668 | "TARGET_64BIT" |
9ebbca7d GK |
6669 | "@ |
6670 | sld%I2. %3,%1,%H2 | |
6671 | #" | |
6672 | [(set_attr "type" "delayed_compare") | |
6673 | (set_attr "length" "4,8")]) | |
6ae08853 | 6674 | |
9ebbca7d GK |
6675 | (define_split |
6676 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6677 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6678 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6679 | (const_int 0))) | |
6680 | (clobber (match_scratch:DI 3 ""))] | |
6681 | "TARGET_POWERPC64 && reload_completed" | |
6682 | [(set (match_dup 3) | |
6683 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6684 | (set (match_dup 0) | |
6685 | (compare:CC (match_dup 3) | |
6686 | (const_int 0)))] | |
6687 | "") | |
6688 | ||
e2c953b6 | 6689 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
6690 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6691 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6692 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6693 | (const_int 0))) |
9ebbca7d | 6694 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6695 | (ashift:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6696 | "TARGET_64BIT" |
9ebbca7d GK |
6697 | "@ |
6698 | sld%I2. %0,%1,%H2 | |
6699 | #" | |
6700 | [(set_attr "type" "delayed_compare") | |
6701 | (set_attr "length" "4,8")]) | |
6702 | ||
6703 | (define_split | |
6704 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6705 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6706 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6707 | (const_int 0))) | |
6708 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6709 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6710 | "TARGET_POWERPC64 && reload_completed" | |
6711 | [(set (match_dup 0) | |
6712 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6713 | (set (match_dup 3) | |
6714 | (compare:CC (match_dup 0) | |
6715 | (const_int 0)))] | |
6716 | "") | |
266eb58a | 6717 | |
e2c953b6 | 6718 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
6719 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6720 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6721 | (match_operand:SI 2 "const_int_operand" "i")) | |
c5059423 AM |
6722 | (match_operand:DI 3 "const_int_operand" "n")))] |
6723 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" | |
e2c953b6 | 6724 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 6725 | |
e2c953b6 | 6726 | (define_insn "ashldi3_internal5" |
9ebbca7d | 6727 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6728 | (compare:CC |
9ebbca7d GK |
6729 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6730 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6731 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6732 | (const_int 0))) |
9ebbca7d | 6733 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6734 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6735 | "@ |
e2c953b6 | 6736 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
6737 | #" |
6738 | [(set_attr "type" "delayed_compare") | |
6739 | (set_attr "length" "4,8")]) | |
6740 | ||
6741 | (define_split | |
6742 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6743 | (compare:CC | |
6744 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6745 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6746 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6747 | (const_int 0))) |
6748 | (clobber (match_scratch:DI 4 ""))] | |
c5059423 AM |
6749 | "TARGET_POWERPC64 && reload_completed |
6750 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
9ebbca7d GK |
6751 | [(set (match_dup 4) |
6752 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 6753 | (match_dup 3))) |
9ebbca7d GK |
6754 | (set (match_dup 0) |
6755 | (compare:CC (match_dup 4) | |
6756 | (const_int 0)))] | |
6757 | "") | |
3cb999d8 | 6758 | |
e2c953b6 | 6759 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 6760 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6761 | (compare:CC |
9ebbca7d GK |
6762 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6763 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6764 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6765 | (const_int 0))) |
9ebbca7d | 6766 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 6767 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6768 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6769 | "@ |
e2c953b6 | 6770 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
6771 | #" |
6772 | [(set_attr "type" "delayed_compare") | |
6773 | (set_attr "length" "4,8")]) | |
6774 | ||
6775 | (define_split | |
6776 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6777 | (compare:CC | |
6778 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6779 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6780 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6781 | (const_int 0))) |
6782 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6783 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
c5059423 AM |
6784 | "TARGET_POWERPC64 && reload_completed |
6785 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
6786 | [(set (match_dup 0) | |
6787 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6788 | (match_dup 3))) | |
6789 | (set (match_dup 4) | |
6790 | (compare:CC (match_dup 0) | |
6791 | (const_int 0)))] | |
6792 | "") | |
6793 | ||
6794 | (define_insn "*ashldi3_internal7" | |
6795 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6796 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6797 | (match_operand:SI 2 "const_int_operand" "i")) | |
ce71f754 | 6798 | (match_operand:DI 3 "mask64_operand" "n")))] |
c5059423 AM |
6799 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" |
6800 | "rldicr %0,%1,%H2,%S3") | |
6801 | ||
6802 | (define_insn "ashldi3_internal8" | |
6803 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6804 | (compare:CC | |
6805 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6806 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6807 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6808 | (const_int 0))) |
6809 | (clobber (match_scratch:DI 4 "=r,r"))] | |
683bdff7 | 6810 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6811 | "@ |
6812 | rldicr. %4,%1,%H2,%S3 | |
6813 | #" | |
6814 | [(set_attr "type" "delayed_compare") | |
6815 | (set_attr "length" "4,8")]) | |
6816 | ||
6817 | (define_split | |
6818 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6819 | (compare:CC | |
6820 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6821 | (match_operand:SI 2 "const_int_operand" "")) | |
6822 | (match_operand:DI 3 "mask64_operand" "")) | |
6823 | (const_int 0))) | |
6824 | (clobber (match_scratch:DI 4 ""))] | |
6825 | "TARGET_POWERPC64 && reload_completed | |
6826 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6827 | [(set (match_dup 4) | |
6828 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6829 | (match_dup 3))) | |
6830 | (set (match_dup 0) | |
6831 | (compare:CC (match_dup 4) | |
6832 | (const_int 0)))] | |
6833 | "") | |
6834 | ||
6835 | (define_insn "*ashldi3_internal9" | |
6836 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
6837 | (compare:CC | |
6838 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6839 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6840 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6841 | (const_int 0))) |
6842 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6843 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 6844 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6845 | "@ |
6846 | rldicr. %0,%1,%H2,%S3 | |
6847 | #" | |
6848 | [(set_attr "type" "delayed_compare") | |
6849 | (set_attr "length" "4,8")]) | |
6850 | ||
6851 | (define_split | |
6852 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6853 | (compare:CC | |
6854 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6855 | (match_operand:SI 2 "const_int_operand" "")) | |
6856 | (match_operand:DI 3 "mask64_operand" "")) | |
6857 | (const_int 0))) | |
6858 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6859 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6860 | "TARGET_POWERPC64 && reload_completed | |
6861 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
9ebbca7d | 6862 | [(set (match_dup 0) |
e2c953b6 DE |
6863 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
6864 | (match_dup 3))) | |
9ebbca7d GK |
6865 | (set (match_dup 4) |
6866 | (compare:CC (match_dup 0) | |
6867 | (const_int 0)))] | |
6868 | "") | |
6869 | ||
6870 | (define_expand "lshrdi3" | |
266eb58a DE |
6871 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6872 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6873 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6874 | "TARGET_POWERPC64 || TARGET_POWER" | |
6875 | " | |
6876 | { | |
6877 | if (TARGET_POWERPC64) | |
6878 | ; | |
6879 | else if (TARGET_POWER) | |
6880 | { | |
6881 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
6882 | DONE; | |
6883 | } | |
6884 | else | |
6885 | FAIL; | |
6886 | }") | |
6887 | ||
e2c953b6 | 6888 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
6889 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6890 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6891 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6892 | "TARGET_POWERPC64" | |
a66078ee | 6893 | "srd%I2 %0,%1,%H2") |
266eb58a | 6894 | |
e2c953b6 | 6895 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
6896 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6897 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6898 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 6899 | (const_int 0))) |
9ebbca7d | 6900 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6901 | "TARGET_64BIT " |
9ebbca7d GK |
6902 | "@ |
6903 | srd%I2. %3,%1,%H2 | |
6904 | #" | |
6905 | [(set_attr "type" "delayed_compare") | |
6906 | (set_attr "length" "4,8")]) | |
6907 | ||
6908 | (define_split | |
6909 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6910 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6911 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6912 | (const_int 0))) | |
6913 | (clobber (match_scratch:DI 3 ""))] | |
6914 | "TARGET_POWERPC64 && reload_completed" | |
6915 | [(set (match_dup 3) | |
6916 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6917 | (set (match_dup 0) | |
6918 | (compare:CC (match_dup 3) | |
6919 | (const_int 0)))] | |
6920 | "") | |
266eb58a | 6921 | |
e2c953b6 | 6922 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
6923 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6924 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6925 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6926 | (const_int 0))) |
9ebbca7d | 6927 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 6928 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6929 | "TARGET_64BIT" |
9ebbca7d GK |
6930 | "@ |
6931 | srd%I2. %0,%1,%H2 | |
6932 | #" | |
6933 | [(set_attr "type" "delayed_compare") | |
6934 | (set_attr "length" "4,8")]) | |
6935 | ||
6936 | (define_split | |
6937 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6938 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6939 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6940 | (const_int 0))) | |
6941 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6942 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
6943 | "TARGET_POWERPC64 && reload_completed" | |
6944 | [(set (match_dup 0) | |
6945 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6946 | (set (match_dup 3) | |
6947 | (compare:CC (match_dup 0) | |
6948 | (const_int 0)))] | |
6949 | "") | |
266eb58a DE |
6950 | |
6951 | (define_expand "ashrdi3" | |
6952 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6953 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6954 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
97727e85 | 6955 | "WORDS_BIG_ENDIAN" |
266eb58a DE |
6956 | " |
6957 | { | |
6958 | if (TARGET_POWERPC64) | |
6959 | ; | |
6960 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
6961 | { | |
6962 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
6963 | DONE; | |
6964 | } | |
97727e85 AH |
6965 | else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT |
6966 | && WORDS_BIG_ENDIAN) | |
4aa74a4f FS |
6967 | { |
6968 | emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); | |
6969 | DONE; | |
6970 | } | |
266eb58a DE |
6971 | else |
6972 | FAIL; | |
6973 | }") | |
6974 | ||
e2c953b6 | 6975 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
6976 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6977 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6978 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6979 | "TARGET_POWERPC64" | |
375490e0 | 6980 | "srad%I2 %0,%1,%H2") |
266eb58a | 6981 | |
e2c953b6 | 6982 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
6983 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6984 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6985 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6986 | (const_int 0))) |
9ebbca7d | 6987 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6988 | "TARGET_64BIT" |
9ebbca7d GK |
6989 | "@ |
6990 | srad%I2. %3,%1,%H2 | |
6991 | #" | |
6992 | [(set_attr "type" "delayed_compare") | |
6993 | (set_attr "length" "4,8")]) | |
6994 | ||
6995 | (define_split | |
6996 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6997 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6998 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6999 | (const_int 0))) | |
7000 | (clobber (match_scratch:DI 3 ""))] | |
7001 | "TARGET_POWERPC64 && reload_completed" | |
7002 | [(set (match_dup 3) | |
7003 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7004 | (set (match_dup 0) | |
7005 | (compare:CC (match_dup 3) | |
7006 | (const_int 0)))] | |
7007 | "") | |
266eb58a | 7008 | |
e2c953b6 | 7009 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
7010 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7011 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7012 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7013 | (const_int 0))) |
9ebbca7d | 7014 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 7015 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 7016 | "TARGET_64BIT" |
9ebbca7d GK |
7017 | "@ |
7018 | srad%I2. %0,%1,%H2 | |
7019 | #" | |
7020 | [(set_attr "type" "delayed_compare") | |
7021 | (set_attr "length" "4,8")]) | |
7022 | ||
7023 | (define_split | |
7024 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7025 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7026 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7027 | (const_int 0))) | |
7028 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7029 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
7030 | "TARGET_POWERPC64 && reload_completed" | |
7031 | [(set (match_dup 0) | |
7032 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7033 | (set (match_dup 3) | |
7034 | (compare:CC (match_dup 0) | |
7035 | (const_int 0)))] | |
7036 | "") | |
815cdc52 | 7037 | |
29ae5b89 | 7038 | (define_insn "anddi3" |
0ba1b2ff AM |
7039 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") |
7040 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
7041 | (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t"))) | |
7042 | (clobber (match_scratch:CC 3 "=X,X,x,x,X"))] | |
6ffc8580 | 7043 | "TARGET_POWERPC64" |
266eb58a DE |
7044 | "@ |
7045 | and %0,%1,%2 | |
29ae5b89 JL |
7046 | rldic%B2 %0,%1,0,%S2 |
7047 | andi. %0,%1,%b2 | |
0ba1b2ff AM |
7048 | andis. %0,%1,%u2 |
7049 | #" | |
7050 | [(set_attr "length" "4,4,4,4,8")]) | |
7051 | ||
7052 | (define_split | |
7053 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7054 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7055 | (match_operand:DI 2 "mask64_2_operand" ""))) | |
7056 | (clobber (match_scratch:CC 3 ""))] | |
7057 | "TARGET_POWERPC64 | |
7058 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7059 | && !mask64_operand (operands[2], DImode)" | |
7060 | [(set (match_dup 0) | |
7061 | (and:DI (rotate:DI (match_dup 1) | |
7062 | (match_dup 4)) | |
7063 | (match_dup 5))) | |
7064 | (set (match_dup 0) | |
7065 | (and:DI (rotate:DI (match_dup 0) | |
7066 | (match_dup 6)) | |
7067 | (match_dup 7)))] | |
7068 | " | |
7069 | { | |
7070 | build_mask64_2_operands (operands[2], &operands[4]); | |
7071 | }") | |
266eb58a | 7072 | |
a260abc9 | 7073 | (define_insn "*anddi3_internal2" |
0ba1b2ff AM |
7074 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7075 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7076 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7077 | (const_int 0))) |
0ba1b2ff AM |
7078 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r")) |
7079 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] | |
683bdff7 | 7080 | "TARGET_64BIT" |
266eb58a DE |
7081 | "@ |
7082 | and. %3,%1,%2 | |
6c873122 | 7083 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
7084 | andi. %3,%1,%b2 |
7085 | andis. %3,%1,%u2 | |
9ebbca7d GK |
7086 | # |
7087 | # | |
7088 | # | |
0ba1b2ff AM |
7089 | # |
7090 | # | |
9ebbca7d | 7091 | #" |
0ba1b2ff AM |
7092 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7093 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7094 | |
7095 | (define_split | |
7096 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7097 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7098 | (match_operand:DI 2 "and64_operand" "")) | |
7099 | (const_int 0))) | |
7100 | (clobber (match_scratch:DI 3 "")) | |
7101 | (clobber (match_scratch:CC 4 ""))] | |
7102 | "TARGET_POWERPC64 && reload_completed" | |
7103 | [(parallel [(set (match_dup 3) | |
7104 | (and:DI (match_dup 1) | |
7105 | (match_dup 2))) | |
7106 | (clobber (match_dup 4))]) | |
7107 | (set (match_dup 0) | |
7108 | (compare:CC (match_dup 3) | |
7109 | (const_int 0)))] | |
7110 | "") | |
266eb58a | 7111 | |
0ba1b2ff AM |
7112 | (define_split |
7113 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
7114 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7115 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7116 | (const_int 0))) | |
7117 | (clobber (match_scratch:DI 3 "")) | |
7118 | (clobber (match_scratch:CC 4 ""))] | |
7119 | "TARGET_POWERPC64 && reload_completed | |
7120 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7121 | && !mask64_operand (operands[2], DImode)" | |
7122 | [(set (match_dup 3) | |
7123 | (and:DI (rotate:DI (match_dup 1) | |
7124 | (match_dup 5)) | |
7125 | (match_dup 6))) | |
7126 | (parallel [(set (match_dup 0) | |
7127 | (compare:CC (and:DI (rotate:DI (match_dup 3) | |
7128 | (match_dup 7)) | |
7129 | (match_dup 8)) | |
7130 | (const_int 0))) | |
7131 | (clobber (match_dup 3))])] | |
7132 | " | |
7133 | { | |
7134 | build_mask64_2_operands (operands[2], &operands[5]); | |
7135 | }") | |
7136 | ||
a260abc9 | 7137 | (define_insn "*anddi3_internal3" |
0ba1b2ff AM |
7138 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7139 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7140 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7141 | (const_int 0))) |
0ba1b2ff | 7142 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
9ebbca7d | 7143 | (and:DI (match_dup 1) (match_dup 2))) |
0ba1b2ff | 7144 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] |
683bdff7 | 7145 | "TARGET_64BIT" |
266eb58a DE |
7146 | "@ |
7147 | and. %0,%1,%2 | |
6c873122 | 7148 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
7149 | andi. %0,%1,%b2 |
7150 | andis. %0,%1,%u2 | |
9ebbca7d GK |
7151 | # |
7152 | # | |
7153 | # | |
0ba1b2ff AM |
7154 | # |
7155 | # | |
9ebbca7d | 7156 | #" |
0ba1b2ff AM |
7157 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7158 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7159 | |
7160 | (define_split | |
7161 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7162 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7163 | (match_operand:DI 2 "and64_operand" "")) | |
7164 | (const_int 0))) | |
7165 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7166 | (and:DI (match_dup 1) (match_dup 2))) | |
7167 | (clobber (match_scratch:CC 4 ""))] | |
7168 | "TARGET_POWERPC64 && reload_completed" | |
7169 | [(parallel [(set (match_dup 0) | |
7170 | (and:DI (match_dup 1) (match_dup 2))) | |
7171 | (clobber (match_dup 4))]) | |
7172 | (set (match_dup 3) | |
7173 | (compare:CC (match_dup 0) | |
7174 | (const_int 0)))] | |
7175 | "") | |
266eb58a | 7176 | |
0ba1b2ff AM |
7177 | (define_split |
7178 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
7179 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7180 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7181 | (const_int 0))) | |
7182 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7183 | (and:DI (match_dup 1) (match_dup 2))) | |
7184 | (clobber (match_scratch:CC 4 ""))] | |
7185 | "TARGET_POWERPC64 && reload_completed | |
7186 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7187 | && !mask64_operand (operands[2], DImode)" | |
7188 | [(set (match_dup 0) | |
7189 | (and:DI (rotate:DI (match_dup 1) | |
7190 | (match_dup 5)) | |
7191 | (match_dup 6))) | |
7192 | (parallel [(set (match_dup 3) | |
7193 | (compare:CC (and:DI (rotate:DI (match_dup 0) | |
7194 | (match_dup 7)) | |
7195 | (match_dup 8)) | |
7196 | (const_int 0))) | |
7197 | (set (match_dup 0) | |
7198 | (and:DI (rotate:DI (match_dup 0) | |
7199 | (match_dup 7)) | |
7200 | (match_dup 8)))])] | |
7201 | " | |
7202 | { | |
7203 | build_mask64_2_operands (operands[2], &operands[5]); | |
7204 | }") | |
7205 | ||
a260abc9 | 7206 | (define_expand "iordi3" |
266eb58a | 7207 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 7208 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 7209 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 7210 | "TARGET_POWERPC64" |
266eb58a DE |
7211 | " |
7212 | { | |
dfbdccdb | 7213 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 7214 | { |
dfbdccdb | 7215 | HOST_WIDE_INT value; |
677a9668 | 7216 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 7217 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 7218 | |
dfbdccdb GK |
7219 | if (GET_CODE (operands[2]) == CONST_INT) |
7220 | { | |
7221 | value = INTVAL (operands[2]); | |
7222 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7223 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7224 | } | |
e2c953b6 | 7225 | else |
dfbdccdb GK |
7226 | { |
7227 | value = CONST_DOUBLE_LOW (operands[2]); | |
7228 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7229 | immed_double_const (value | |
7230 | & (~ (HOST_WIDE_INT) 0xffff), | |
7231 | 0, DImode))); | |
7232 | } | |
e2c953b6 | 7233 | |
9ebbca7d GK |
7234 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7235 | DONE; | |
7236 | } | |
266eb58a DE |
7237 | }") |
7238 | ||
a260abc9 DE |
7239 | (define_expand "xordi3" |
7240 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7241 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 7242 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
7243 | "TARGET_POWERPC64" |
7244 | " | |
7245 | { | |
dfbdccdb | 7246 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 7247 | { |
dfbdccdb | 7248 | HOST_WIDE_INT value; |
677a9668 | 7249 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
7250 | ? operands[0] : gen_reg_rtx (DImode)); |
7251 | ||
dfbdccdb GK |
7252 | if (GET_CODE (operands[2]) == CONST_INT) |
7253 | { | |
7254 | value = INTVAL (operands[2]); | |
7255 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7256 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7257 | } | |
e2c953b6 | 7258 | else |
dfbdccdb GK |
7259 | { |
7260 | value = CONST_DOUBLE_LOW (operands[2]); | |
7261 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7262 | immed_double_const (value | |
7263 | & (~ (HOST_WIDE_INT) 0xffff), | |
7264 | 0, DImode))); | |
7265 | } | |
e2c953b6 | 7266 | |
9ebbca7d GK |
7267 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7268 | DONE; | |
7269 | } | |
a260abc9 DE |
7270 | }") |
7271 | ||
dfbdccdb | 7272 | (define_insn "*booldi3_internal1" |
266eb58a | 7273 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 7274 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7275 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
7276 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 7277 | "TARGET_POWERPC64" |
1fd4e8c1 | 7278 | "@ |
dfbdccdb GK |
7279 | %q3 %0,%1,%2 |
7280 | %q3i %0,%1,%b2 | |
7281 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 7282 | |
dfbdccdb | 7283 | (define_insn "*booldi3_internal2" |
9ebbca7d | 7284 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 7285 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
7286 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
7287 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7288 | (const_int 0))) | |
9ebbca7d | 7289 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7290 | "TARGET_64BIT" |
9ebbca7d | 7291 | "@ |
dfbdccdb | 7292 | %q4. %3,%1,%2 |
9ebbca7d GK |
7293 | #" |
7294 | [(set_attr "type" "compare") | |
7295 | (set_attr "length" "4,8")]) | |
7296 | ||
7297 | (define_split | |
7298 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7299 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7300 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7301 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7302 | (const_int 0))) |
9ebbca7d GK |
7303 | (clobber (match_scratch:DI 3 ""))] |
7304 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7305 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7306 | (set (match_dup 0) |
7307 | (compare:CC (match_dup 3) | |
7308 | (const_int 0)))] | |
7309 | "") | |
1fd4e8c1 | 7310 | |
dfbdccdb | 7311 | (define_insn "*booldi3_internal3" |
9ebbca7d | 7312 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7313 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7314 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7315 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7316 | (const_int 0))) | |
9ebbca7d | 7317 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7318 | (match_dup 4))] |
683bdff7 | 7319 | "TARGET_64BIT" |
9ebbca7d | 7320 | "@ |
dfbdccdb | 7321 | %q4. %0,%1,%2 |
9ebbca7d GK |
7322 | #" |
7323 | [(set_attr "type" "compare") | |
7324 | (set_attr "length" "4,8")]) | |
7325 | ||
7326 | (define_split | |
e72247f4 | 7327 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7328 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7329 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7330 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7331 | (const_int 0))) |
75540af0 | 7332 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7333 | (match_dup 4))] |
9ebbca7d | 7334 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7335 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7336 | (set (match_dup 3) |
7337 | (compare:CC (match_dup 0) | |
7338 | (const_int 0)))] | |
7339 | "") | |
1fd4e8c1 | 7340 | |
6ae08853 | 7341 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 7342 | ;; each of which does one 16-bit part. This is used by combine. |
266eb58a DE |
7343 | |
7344 | (define_split | |
7345 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 7346 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7347 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7348 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7349 | "TARGET_POWERPC64" |
dfbdccdb GK |
7350 | [(set (match_dup 0) (match_dup 4)) |
7351 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7352 | " |
7353 | { | |
dfbdccdb | 7354 | rtx i3,i4; |
6ae08853 | 7355 | |
9ebbca7d GK |
7356 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7357 | { | |
7358 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7359 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7360 | 0, DImode); |
dfbdccdb | 7361 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7362 | } |
7363 | else | |
7364 | { | |
dfbdccdb | 7365 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7366 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7367 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7368 | } |
1c563bed | 7369 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7370 | operands[1], i3); |
1c563bed | 7371 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7372 | operands[0], i4); |
1fd4e8c1 RK |
7373 | }") |
7374 | ||
dfbdccdb | 7375 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7376 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7377 | (match_operator:DI 3 "boolean_operator" |
7378 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7379 | (match_operand:DI 2 "gpc_reg_operand" "r")]))] |
a473029f | 7380 | "TARGET_POWERPC64" |
1d328b19 | 7381 | "%q3 %0,%2,%1") |
a473029f | 7382 | |
dfbdccdb | 7383 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7384 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7385 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7386 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7387 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7388 | (const_int 0))) | |
9ebbca7d | 7389 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7390 | "TARGET_64BIT" |
9ebbca7d | 7391 | "@ |
1d328b19 | 7392 | %q4. %3,%2,%1 |
9ebbca7d GK |
7393 | #" |
7394 | [(set_attr "type" "compare") | |
7395 | (set_attr "length" "4,8")]) | |
7396 | ||
7397 | (define_split | |
7398 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7399 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7400 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7401 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7402 | (const_int 0))) |
9ebbca7d GK |
7403 | (clobber (match_scratch:DI 3 ""))] |
7404 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7405 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7406 | (set (match_dup 0) |
7407 | (compare:CC (match_dup 3) | |
7408 | (const_int 0)))] | |
7409 | "") | |
a473029f | 7410 | |
dfbdccdb | 7411 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7412 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7413 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7414 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7415 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7416 | (const_int 0))) | |
9ebbca7d | 7417 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7418 | (match_dup 4))] |
683bdff7 | 7419 | "TARGET_64BIT" |
9ebbca7d | 7420 | "@ |
1d328b19 | 7421 | %q4. %0,%2,%1 |
9ebbca7d GK |
7422 | #" |
7423 | [(set_attr "type" "compare") | |
7424 | (set_attr "length" "4,8")]) | |
7425 | ||
7426 | (define_split | |
e72247f4 | 7427 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7428 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7429 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7430 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7431 | (const_int 0))) |
75540af0 | 7432 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7433 | (match_dup 4))] |
9ebbca7d | 7434 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7435 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7436 | (set (match_dup 3) |
7437 | (compare:CC (match_dup 0) | |
7438 | (const_int 0)))] | |
7439 | "") | |
266eb58a | 7440 | |
dfbdccdb | 7441 | (define_insn "*boolccdi3_internal1" |
a473029f | 7442 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7443 | (match_operator:DI 3 "boolean_operator" |
7444 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7445 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] |
a473029f | 7446 | "TARGET_POWERPC64" |
dfbdccdb | 7447 | "%q3 %0,%1,%2") |
a473029f | 7448 | |
dfbdccdb | 7449 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7450 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7451 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7452 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7453 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7454 | (const_int 0))) | |
9ebbca7d | 7455 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7456 | "TARGET_64BIT" |
9ebbca7d | 7457 | "@ |
dfbdccdb | 7458 | %q4. %3,%1,%2 |
9ebbca7d GK |
7459 | #" |
7460 | [(set_attr "type" "compare") | |
7461 | (set_attr "length" "4,8")]) | |
7462 | ||
7463 | (define_split | |
7464 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7465 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7466 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7467 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7468 | (const_int 0))) |
9ebbca7d GK |
7469 | (clobber (match_scratch:DI 3 ""))] |
7470 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7471 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7472 | (set (match_dup 0) |
7473 | (compare:CC (match_dup 3) | |
7474 | (const_int 0)))] | |
7475 | "") | |
266eb58a | 7476 | |
dfbdccdb | 7477 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7478 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7479 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7480 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7481 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7482 | (const_int 0))) | |
9ebbca7d | 7483 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7484 | (match_dup 4))] |
683bdff7 | 7485 | "TARGET_64BIT" |
9ebbca7d | 7486 | "@ |
dfbdccdb | 7487 | %q4. %0,%1,%2 |
9ebbca7d GK |
7488 | #" |
7489 | [(set_attr "type" "compare") | |
7490 | (set_attr "length" "4,8")]) | |
7491 | ||
7492 | (define_split | |
e72247f4 | 7493 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7494 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7495 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7496 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7497 | (const_int 0))) |
75540af0 | 7498 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7499 | (match_dup 4))] |
9ebbca7d | 7500 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7501 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7502 | (set (match_dup 3) |
7503 | (compare:CC (match_dup 0) | |
7504 | (const_int 0)))] | |
7505 | "") | |
dfbdccdb | 7506 | \f |
1fd4e8c1 | 7507 | ;; Now define ways of moving data around. |
4697a36c MM |
7508 | |
7509 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
7510 | ;; The output of this could be r0, but we make a very strong |
7511 | ;; preference for a base register because it will usually | |
7512 | ;; be needed there. | |
4697a36c | 7513 | (define_insn "elf_high" |
9ebbca7d | 7514 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 7515 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 7516 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 7517 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
7518 | |
7519 | (define_insn "elf_low" | |
9ebbca7d GK |
7520 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
7521 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 7522 | (match_operand 2 "" "")))] |
0ad91047 | 7523 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
7524 | "@ |
7525 | {cal|la} %0,%2@l(%1) | |
81eace42 | 7526 | {ai|addic} %0,%1,%K2") |
4697a36c | 7527 | |
ee890fe2 SS |
7528 | ;; Mach-O PIC trickery. |
7529 | (define_insn "macho_high" | |
7530 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") | |
7531 | (high:SI (match_operand 1 "" "")))] | |
7532 | "TARGET_MACHO && ! TARGET_64BIT" | |
7533 | "{liu|lis} %0,ha16(%1)") | |
7534 | ||
7535 | (define_insn "macho_low" | |
7536 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
7537 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
7538 | (match_operand 2 "" "")))] | |
7539 | "TARGET_MACHO && ! TARGET_64BIT" | |
7540 | "@ | |
7541 | {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} | |
7542 | {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") | |
7543 | ||
766a866c MM |
7544 | ;; Set up a register with a value from the GOT table |
7545 | ||
7546 | (define_expand "movsi_got" | |
52d3af72 | 7547 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7548 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
615158e2 | 7549 | (match_dup 2)] UNSPEC_MOVSI_GOT))] |
f607bc57 | 7550 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7551 | " |
7552 | { | |
38c1f2d7 MM |
7553 | if (GET_CODE (operands[1]) == CONST) |
7554 | { | |
7555 | rtx offset = const0_rtx; | |
7556 | HOST_WIDE_INT value; | |
7557 | ||
7558 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7559 | value = INTVAL (offset); | |
7560 | if (value != 0) | |
7561 | { | |
677a9668 | 7562 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7563 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7564 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7565 | DONE; | |
7566 | } | |
7567 | } | |
7568 | ||
c4c40373 | 7569 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7570 | }") |
7571 | ||
84f414bc | 7572 | (define_insn "*movsi_got_internal" |
52d3af72 | 7573 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d | 7574 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7575 | (match_operand:SI 2 "gpc_reg_operand" "b")] |
7576 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7577 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7578 | "{l|lwz} %0,%a1@got(%2)" |
7579 | [(set_attr "type" "load")]) | |
7580 | ||
b22b9b3e JL |
7581 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7582 | ;; didn't get allocated to a hard register. | |
6ae08853 | 7583 | (define_split |
75540af0 | 7584 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7585 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7586 | (match_operand:SI 2 "memory_operand" "")] |
7587 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7588 | "DEFAULT_ABI == ABI_V4 |
b22b9b3e JL |
7589 | && flag_pic == 1 |
7590 | && (reload_in_progress || reload_completed)" | |
7591 | [(set (match_dup 0) (match_dup 2)) | |
615158e2 JJ |
7592 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] |
7593 | UNSPEC_MOVSI_GOT))] | |
b22b9b3e JL |
7594 | "") |
7595 | ||
1fd4e8c1 RK |
7596 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7597 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7598 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7599 | ;; integers in the TOC. | |
7600 | (define_expand "movsi" | |
7601 | [(set (match_operand:SI 0 "general_operand" "") | |
7602 | (match_operand:SI 1 "any_operand" ""))] | |
7603 | "" | |
fb4d4348 | 7604 | "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") |
1fd4e8c1 | 7605 | |
ee890fe2 SS |
7606 | (define_insn "movsi_low" |
7607 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
f585a356 | 7608 | (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
ee890fe2 SS |
7609 | (match_operand 2 "" ""))))] |
7610 | "TARGET_MACHO && ! TARGET_64BIT" | |
7611 | "{l|lwz} %0,lo16(%2)(%1)" | |
7612 | [(set_attr "type" "load") | |
7613 | (set_attr "length" "4")]) | |
7614 | ||
c859cda6 | 7615 | (define_insn "movsi_low_st" |
f585a356 | 7616 | [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
c859cda6 DJ |
7617 | (match_operand 2 "" ""))) |
7618 | (match_operand:SI 0 "gpc_reg_operand" "r"))] | |
7619 | "TARGET_MACHO && ! TARGET_64BIT" | |
7620 | "{st|stw} %0,lo16(%2)(%1)" | |
7621 | [(set_attr "type" "store") | |
7622 | (set_attr "length" "4")]) | |
7623 | ||
7624 | (define_insn "movdf_low" | |
234e114c | 7625 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") |
f585a356 | 7626 | (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 7627 | (match_operand 2 "" ""))))] |
a3170dc6 | 7628 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
234e114c DJ |
7629 | "* |
7630 | { | |
7631 | switch (which_alternative) | |
7632 | { | |
7633 | case 0: | |
7634 | return \"lfd %0,lo16(%2)(%1)\"; | |
7635 | case 1: | |
7636 | { | |
7637 | rtx operands2[4]; | |
7638 | operands2[0] = operands[0]; | |
7639 | operands2[1] = operands[1]; | |
7640 | operands2[2] = operands[2]; | |
683bdff7 | 7641 | if (TARGET_POWERPC64 && TARGET_32BIT) |
a3c9585f | 7642 | /* Note, old assemblers didn't support relocation here. */ |
683bdff7 | 7643 | return \"ld %0,lo16(%2)(%1)\"; |
ab82a49f | 7644 | else |
683bdff7 | 7645 | { |
6ae08853 | 7646 | operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
683bdff7 FJ |
7647 | output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands); |
7648 | #if TARGET_MACHO | |
7649 | if (MACHO_DYNAMIC_NO_PIC_P) | |
7650 | output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands); | |
6ae08853 | 7651 | else |
683bdff7 FJ |
7652 | /* We cannot rely on ha16(low half)==ha16(high half), alas, |
7653 | although in practice it almost always is. */ | |
7654 | output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2); | |
ab82a49f | 7655 | #endif |
683bdff7 FJ |
7656 | return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\"); |
7657 | } | |
234e114c DJ |
7658 | } |
7659 | default: | |
7660 | abort(); | |
7661 | } | |
7662 | }" | |
c859cda6 | 7663 | [(set_attr "type" "load") |
234e114c | 7664 | (set_attr "length" "4,12")]) |
c859cda6 DJ |
7665 | |
7666 | (define_insn "movdf_low_st" | |
f585a356 | 7667 | [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
c859cda6 DJ |
7668 | (match_operand 2 "" ""))) |
7669 | (match_operand:DF 0 "gpc_reg_operand" "f"))] | |
a3170dc6 | 7670 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
c859cda6 DJ |
7671 | "stfd %0,lo16(%2)(%1)" |
7672 | [(set_attr "type" "store") | |
7673 | (set_attr "length" "4")]) | |
7674 | ||
7675 | (define_insn "movsf_low" | |
fd3b43f2 | 7676 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") |
f585a356 | 7677 | (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 7678 | (match_operand 2 "" ""))))] |
a3170dc6 | 7679 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
fd3b43f2 DJ |
7680 | "@ |
7681 | lfs %0,lo16(%2)(%1) | |
7682 | {l|lwz} %0,lo16(%2)(%1)" | |
c859cda6 DJ |
7683 | [(set_attr "type" "load") |
7684 | (set_attr "length" "4")]) | |
7685 | ||
7686 | (define_insn "movsf_low_st" | |
f585a356 | 7687 | [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 7688 | (match_operand 2 "" ""))) |
fd3b43f2 | 7689 | (match_operand:SF 0 "gpc_reg_operand" "f,!r"))] |
a3170dc6 | 7690 | "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" |
fd3b43f2 DJ |
7691 | "@ |
7692 | stfs %0,lo16(%2)(%1) | |
7693 | {st|stw} %0,lo16(%2)(%1)" | |
c859cda6 DJ |
7694 | [(set_attr "type" "store") |
7695 | (set_attr "length" "4")]) | |
7696 | ||
acad7ed3 | 7697 | (define_insn "*movsi_internal1" |
a004eb82 AH |
7698 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") |
7699 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] | |
19d5775a RK |
7700 | "gpc_reg_operand (operands[0], SImode) |
7701 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7702 | "@ |
deb9225a | 7703 | mr %0,%1 |
b9442c72 | 7704 | {cal|la} %0,%a1 |
ca7f5001 RK |
7705 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7706 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7707 | {lil|li} %0,%1 |
802a0058 | 7708 | {liu|lis} %0,%v1 |
beaec479 | 7709 | # |
aee86b38 | 7710 | {cal|la} %0,%a1 |
1fd4e8c1 | 7711 | mf%1 %0 |
5c23c401 | 7712 | mt%0 %1 |
e76e75bb | 7713 | mt%0 %1 |
a004eb82 | 7714 | mt%0 %1 |
e34eaae5 | 7715 | {cror 0,0,0|nop}" |
02ca7595 | 7716 | [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*") |
a004eb82 | 7717 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7718 | |
77fa0940 RK |
7719 | ;; Split a load of a large constant into the appropriate two-insn |
7720 | ;; sequence. | |
7721 | ||
7722 | (define_split | |
7723 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7724 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7725 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7726 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7727 | [(set (match_dup 0) | |
7728 | (match_dup 2)) | |
7729 | (set (match_dup 0) | |
7730 | (ior:SI (match_dup 0) | |
7731 | (match_dup 3)))] | |
7732 | " | |
af8cb5c5 DE |
7733 | { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2); |
7734 | ||
7735 | if (tem == operands[0]) | |
7736 | DONE; | |
7737 | else | |
7738 | FAIL; | |
77fa0940 RK |
7739 | }") |
7740 | ||
acad7ed3 | 7741 | (define_insn "*movsi_internal2" |
bb84cb12 DE |
7742 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
7743 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r") | |
1fd4e8c1 | 7744 | (const_int 0))) |
bb84cb12 | 7745 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
4b8a63d6 | 7746 | "TARGET_32BIT" |
9ebbca7d | 7747 | "@ |
bb84cb12 | 7748 | {cmpi|cmpwi} %2,%0,0 |
9ebbca7d GK |
7749 | mr. %0,%1 |
7750 | #" | |
bb84cb12 DE |
7751 | [(set_attr "type" "cmp,compare,cmp") |
7752 | (set_attr "length" "4,4,8")]) | |
7753 | ||
9ebbca7d GK |
7754 | (define_split |
7755 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
7756 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
7757 | (const_int 0))) | |
7758 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
4b8a63d6 | 7759 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
7760 | [(set (match_dup 0) (match_dup 1)) |
7761 | (set (match_dup 2) | |
7762 | (compare:CC (match_dup 0) | |
7763 | (const_int 0)))] | |
7764 | "") | |
bb84cb12 | 7765 | \f |
1fd4e8c1 RK |
7766 | (define_expand "movhi" |
7767 | [(set (match_operand:HI 0 "general_operand" "") | |
7768 | (match_operand:HI 1 "any_operand" ""))] | |
7769 | "" | |
fb4d4348 | 7770 | "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") |
1fd4e8c1 | 7771 | |
e34eaae5 | 7772 | (define_insn "*movhi_internal" |
fb81d7ce RK |
7773 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7774 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7775 | "gpc_reg_operand (operands[0], HImode) |
7776 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7777 | "@ |
deb9225a | 7778 | mr %0,%1 |
1fd4e8c1 RK |
7779 | lhz%U1%X1 %0,%1 |
7780 | sth%U0%X0 %1,%0 | |
19d5775a | 7781 | {lil|li} %0,%w1 |
1fd4e8c1 | 7782 | mf%1 %0 |
e76e75bb | 7783 | mt%0 %1 |
fb81d7ce | 7784 | mt%0 %1 |
e34eaae5 | 7785 | {cror 0,0,0|nop}" |
02ca7595 | 7786 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7787 | |
7788 | (define_expand "movqi" | |
7789 | [(set (match_operand:QI 0 "general_operand" "") | |
7790 | (match_operand:QI 1 "any_operand" ""))] | |
7791 | "" | |
fb4d4348 | 7792 | "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") |
1fd4e8c1 | 7793 | |
e34eaae5 | 7794 | (define_insn "*movqi_internal" |
fb81d7ce RK |
7795 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7796 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7797 | "gpc_reg_operand (operands[0], QImode) |
7798 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7799 | "@ |
deb9225a | 7800 | mr %0,%1 |
1fd4e8c1 RK |
7801 | lbz%U1%X1 %0,%1 |
7802 | stb%U0%X0 %1,%0 | |
19d5775a | 7803 | {lil|li} %0,%1 |
1fd4e8c1 | 7804 | mf%1 %0 |
e76e75bb | 7805 | mt%0 %1 |
fb81d7ce | 7806 | mt%0 %1 |
e34eaae5 | 7807 | {cror 0,0,0|nop}" |
02ca7595 | 7808 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7809 | \f |
7810 | ;; Here is how to move condition codes around. When we store CC data in | |
7811 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7812 | ;; This lets us not shift in the most common case of CR0. | |
7813 | (define_expand "movcc" | |
7814 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7815 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7816 | "" | |
7817 | "") | |
7818 | ||
a65c591c | 7819 | (define_insn "*movcc_internal1" |
b54cf83a DE |
7820 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m") |
7821 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))] | |
1fd4e8c1 RK |
7822 | "register_operand (operands[0], CCmode) |
7823 | || register_operand (operands[1], CCmode)" | |
7824 | "@ | |
7825 | mcrf %0,%1 | |
7826 | mtcrf 128,%1 | |
ca7f5001 | 7827 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
2c4a9cff DE |
7828 | mfcr %0%Q1 |
7829 | mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 | |
deb9225a | 7830 | mr %0,%1 |
b54cf83a | 7831 | mf%1 %0 |
b991a865 GK |
7832 | mt%0 %1 |
7833 | mt%0 %1 | |
ca7f5001 RK |
7834 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7835 | {st%U0%U1|stw%U0%U1} %1,%0" | |
2c4a9cff DE |
7836 | [(set (attr "type") |
7837 | (cond [(eq_attr "alternative" "0") | |
7838 | (const_string "cr_logical") | |
7839 | (eq_attr "alternative" "1,2") | |
7840 | (const_string "mtcr") | |
7841 | (eq_attr "alternative" "5,7") | |
7842 | (const_string "integer") | |
7843 | (eq_attr "alternative" "6") | |
7844 | (const_string "mfjmpr") | |
7845 | (eq_attr "alternative" "8") | |
7846 | (const_string "mtjmpr") | |
7847 | (eq_attr "alternative" "9") | |
7848 | (const_string "load") | |
7849 | (eq_attr "alternative" "10") | |
7850 | (const_string "store") | |
7851 | (ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
7852 | (const_string "mfcrf") | |
7853 | ] | |
7854 | (const_string "mfcr"))) | |
b991a865 | 7855 | (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7856 | \f |
e52e05ca MM |
7857 | ;; For floating-point, we normally deal with the floating-point registers |
7858 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7859 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7860 | ;; value is a simple constant or already in memory, we deal with this by | |
7861 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7862 | (define_expand "movsf" |
7863 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7864 | (match_operand:SF 1 "any_operand" ""))] | |
7865 | "" | |
fb4d4348 | 7866 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 7867 | |
1fd4e8c1 | 7868 | (define_split |
cd2b37d9 | 7869 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7870 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7871 | "reload_completed |
5ae4759c MM |
7872 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7873 | || (GET_CODE (operands[0]) == SUBREG | |
7874 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7875 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7876 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7877 | " |
7878 | { | |
7879 | long l; | |
7880 | REAL_VALUE_TYPE rv; | |
7881 | ||
7882 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7883 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7884 | |
f99f88e0 DE |
7885 | if (! TARGET_POWERPC64) |
7886 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7887 | else | |
7888 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7889 | |
2496c7bd | 7890 | operands[3] = gen_int_mode (l, SImode); |
a260abc9 DE |
7891 | }") |
7892 | ||
c4c40373 | 7893 | (define_insn "*movsf_hardfloat" |
ae6669e7 DJ |
7894 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r") |
7895 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))] | |
d14a6d05 | 7896 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7897 | || gpc_reg_operand (operands[1], SFmode)) |
7898 | && (TARGET_HARD_FLOAT && TARGET_FPRS)" | |
1fd4e8c1 | 7899 | "@ |
f99f88e0 DE |
7900 | mr %0,%1 |
7901 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7902 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7903 | fmr %0,%1 |
7904 | lfs%U1%X1 %0,%1 | |
c4c40373 | 7905 | stfs%U0%X0 %1,%0 |
b991a865 GK |
7906 | mt%0 %1 |
7907 | mt%0 %1 | |
7908 | mf%1 %0 | |
e0740893 | 7909 | {cror 0,0,0|nop} |
c4c40373 MM |
7910 | # |
7911 | #" | |
ae6669e7 DJ |
7912 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*") |
7913 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7914 | |
c4c40373 | 7915 | (define_insn "*movsf_softfloat" |
dd0fbae2 MK |
7916 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h") |
7917 | (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))] | |
d14a6d05 | 7918 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7919 | || gpc_reg_operand (operands[1], SFmode)) |
7920 | && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" | |
d14a6d05 MM |
7921 | "@ |
7922 | mr %0,%1 | |
b991a865 GK |
7923 | mt%0 %1 |
7924 | mt%0 %1 | |
7925 | mf%1 %0 | |
d14a6d05 MM |
7926 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7927 | {st%U0%X0|stw%U0%X0} %1,%0 | |
7928 | {lil|li} %0,%1 | |
802a0058 | 7929 | {liu|lis} %0,%v1 |
aee86b38 | 7930 | {cal|la} %0,%a1 |
c4c40373 | 7931 | # |
dd0fbae2 MK |
7932 | # |
7933 | {cror 0,0,0|nop}" | |
7934 | [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*") | |
7935 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")]) | |
d14a6d05 | 7936 | |
1fd4e8c1 RK |
7937 | \f |
7938 | (define_expand "movdf" | |
7939 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
7940 | (match_operand:DF 1 "any_operand" ""))] | |
7941 | "" | |
fb4d4348 | 7942 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
7943 | |
7944 | (define_split | |
cd2b37d9 | 7945 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 7946 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 7947 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7948 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7949 | || (GET_CODE (operands[0]) == SUBREG | |
7950 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7951 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7952 | [(set (match_dup 2) (match_dup 4)) |
7953 | (set (match_dup 3) (match_dup 1))] | |
7954 | " | |
7955 | { | |
5ae4759c | 7956 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
7957 | HOST_WIDE_INT value = INTVAL (operands[1]); |
7958 | ||
5ae4759c MM |
7959 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7960 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
7961 | #if HOST_BITS_PER_WIDE_INT == 32 |
7962 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
7963 | #else | |
7964 | operands[4] = GEN_INT (value >> 32); | |
a65c591c | 7965 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
5f59ecb7 | 7966 | #endif |
c4c40373 MM |
7967 | }") |
7968 | ||
c4c40373 MM |
7969 | (define_split |
7970 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
7971 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 7972 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7973 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7974 | || (GET_CODE (operands[0]) == SUBREG | |
7975 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7976 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7977 | [(set (match_dup 2) (match_dup 4)) |
7978 | (set (match_dup 3) (match_dup 5))] | |
7979 | " | |
7980 | { | |
5ae4759c | 7981 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
7982 | long l[2]; |
7983 | REAL_VALUE_TYPE rv; | |
7984 | ||
7985 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7986 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7987 | ||
5ae4759c MM |
7988 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7989 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
2496c7bd LB |
7990 | operands[4] = gen_int_mode (l[endian], SImode); |
7991 | operands[5] = gen_int_mode (l[1 - endian], SImode); | |
c4c40373 MM |
7992 | }") |
7993 | ||
efc08378 DE |
7994 | (define_split |
7995 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 7996 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 7997 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7998 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7999 | || (GET_CODE (operands[0]) == SUBREG | |
8000 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8001 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 8002 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 8003 | " |
a260abc9 DE |
8004 | { |
8005 | int endian = (WORDS_BIG_ENDIAN == 0); | |
8006 | long l[2]; | |
8007 | REAL_VALUE_TYPE rv; | |
4977bab6 | 8008 | #if HOST_BITS_PER_WIDE_INT >= 64 |
5b029315 | 8009 | HOST_WIDE_INT val; |
4977bab6 | 8010 | #endif |
a260abc9 DE |
8011 | |
8012 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8013 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
8014 | ||
8015 | operands[2] = gen_lowpart (DImode, operands[0]); | |
8016 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
5b029315 | 8017 | #if HOST_BITS_PER_WIDE_INT >= 64 |
a2419b96 DE |
8018 | val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 |
8019 | | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); | |
5b029315 | 8020 | |
f5264b52 | 8021 | operands[3] = gen_int_mode (val, DImode); |
5b029315 | 8022 | #else |
a260abc9 | 8023 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); |
5b029315 | 8024 | #endif |
a260abc9 | 8025 | }") |
efc08378 | 8026 | |
4eae5fe1 | 8027 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 8028 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
8029 | ;; a non-offsettable memref, but also it is less efficient than loading |
8030 | ;; the constant into an FP register, since it will probably be used there. | |
8031 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
8032 | ;; of handling these non-offsettable values. | |
c4c40373 | 8033 | (define_insn "*movdf_hardfloat32" |
914a7297 DE |
8034 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") |
8035 | (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] | |
a3170dc6 | 8036 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
8037 | && (gpc_reg_operand (operands[0], DFmode) |
8038 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
8039 | "* |
8040 | { | |
8041 | switch (which_alternative) | |
8042 | { | |
a260abc9 | 8043 | default: |
a6c2a102 | 8044 | abort (); |
e7113111 RK |
8045 | case 0: |
8046 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
8047 | the first register operand 0 is the same as the second register |
8048 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 8049 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 8050 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 8051 | else |
deb9225a | 8052 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 8053 | case 1: |
76d2b81d DJ |
8054 | if (GET_CODE (operands[1]) == MEM |
8055 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0), | |
8056 | reload_completed || reload_in_progress) | |
8057 | || GET_CODE (XEXP (operands[1], 0)) == REG | |
8058 | || GET_CODE (XEXP (operands[1], 0)) == LO_SUM | |
69f51a21 | 8059 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC |
76d2b81d | 8060 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)) |
000034eb DE |
8061 | { |
8062 | /* If the low-address word is used in the address, we must load | |
8063 | it last. Otherwise, load it first. Note that we cannot have | |
8064 | auto-increment in that case since the address register is | |
8065 | known to be dead. */ | |
8066 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8067 | operands[1], 0)) | |
8068 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
8069 | else | |
8070 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8071 | } | |
e7113111 | 8072 | else |
000034eb DE |
8073 | { |
8074 | rtx addreg; | |
8075 | ||
000034eb DE |
8076 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
8077 | if (refers_to_regno_p (REGNO (operands[0]), | |
8078 | REGNO (operands[0]) + 1, | |
8079 | operands[1], 0)) | |
8080 | { | |
8081 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 8082 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 8083 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 8084 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
8085 | } |
8086 | else | |
8087 | { | |
2b97222d | 8088 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 8089 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8090 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
8091 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8092 | return \"\"; | |
8093 | } | |
8094 | } | |
e7113111 | 8095 | case 2: |
76d2b81d DJ |
8096 | if (GET_CODE (operands[0]) == MEM |
8097 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0), | |
8098 | reload_completed || reload_in_progress) | |
8099 | || GET_CODE (XEXP (operands[0], 0)) == REG | |
8100 | || GET_CODE (XEXP (operands[0], 0)) == LO_SUM | |
69f51a21 | 8101 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC |
76d2b81d | 8102 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)) |
000034eb DE |
8103 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8104 | else | |
8105 | { | |
8106 | rtx addreg; | |
8107 | ||
000034eb | 8108 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 8109 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 8110 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8111 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
8112 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8113 | return \"\"; | |
8114 | } | |
e7113111 | 8115 | case 3: |
914a7297 | 8116 | return \"fmr %0,%1\"; |
e7113111 | 8117 | case 4: |
914a7297 | 8118 | return \"lfd%U1%X1 %0,%1\"; |
e7113111 | 8119 | case 5: |
914a7297 | 8120 | return \"stfd%U0%X0 %1,%0\"; |
e7113111 | 8121 | case 6: |
c4c40373 | 8122 | case 7: |
c4c40373 | 8123 | case 8: |
914a7297 | 8124 | return \"#\"; |
e7113111 RK |
8125 | } |
8126 | }" | |
914a7297 DE |
8127 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*") |
8128 | (set_attr "length" "8,16,16,4,4,4,8,12,16")]) | |
51b8fc2c | 8129 | |
c4c40373 | 8130 | (define_insn "*movdf_softfloat32" |
1427100a DE |
8131 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
8132 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
a3170dc6 | 8133 | "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
8134 | && (gpc_reg_operand (operands[0], DFmode) |
8135 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8136 | "* |
8137 | { | |
8138 | switch (which_alternative) | |
8139 | { | |
a260abc9 | 8140 | default: |
a6c2a102 | 8141 | abort (); |
dc4f83ca MM |
8142 | case 0: |
8143 | /* We normally copy the low-numbered register first. However, if | |
8144 | the first register operand 0 is the same as the second register of | |
8145 | operand 1, we must copy in the opposite order. */ | |
8146 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8147 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8148 | else | |
8149 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8150 | case 1: | |
3cb999d8 DE |
8151 | /* If the low-address word is used in the address, we must load |
8152 | it last. Otherwise, load it first. Note that we cannot have | |
8153 | auto-increment in that case since the address register is | |
8154 | known to be dead. */ | |
dc4f83ca | 8155 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 8156 | operands[1], 0)) |
dc4f83ca MM |
8157 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
8158 | else | |
8159 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8160 | case 2: | |
8161 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
8162 | case 3: | |
c4c40373 MM |
8163 | case 4: |
8164 | case 5: | |
dc4f83ca MM |
8165 | return \"#\"; |
8166 | } | |
8167 | }" | |
c4c40373 MM |
8168 | [(set_attr "type" "*,load,store,*,*,*") |
8169 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 8170 | |
d2288d5d HP |
8171 | ; ld/std require word-aligned displacements -> 'Y' constraint. |
8172 | ; List Y->r and r->Y before r->r for reload. | |
c4c40373 | 8173 | (define_insn "*movdf_hardfloat64" |
ae6669e7 DJ |
8174 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r") |
8175 | (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] | |
a3170dc6 | 8176 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
8177 | && (gpc_reg_operand (operands[0], DFmode) |
8178 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 8179 | "@ |
96bb8ed3 | 8180 | std%U0%X0 %1,%0 |
3364872d FJ |
8181 | ld%U1%X1 %0,%1 |
8182 | mr %0,%1 | |
3d5570cb | 8183 | fmr %0,%1 |
f63184ac | 8184 | lfd%U1%X1 %0,%1 |
914a7297 DE |
8185 | stfd%U0%X0 %1,%0 |
8186 | mt%0 %1 | |
8187 | mf%1 %0 | |
e0740893 | 8188 | {cror 0,0,0|nop} |
914a7297 DE |
8189 | # |
8190 | # | |
8191 | #" | |
ae6669e7 DJ |
8192 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*") |
8193 | (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")]) | |
dc4f83ca | 8194 | |
c4c40373 | 8195 | (define_insn "*movdf_softfloat64" |
d2288d5d HP |
8196 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h") |
8197 | (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))] | |
a3170dc6 | 8198 | "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
8199 | && (gpc_reg_operand (operands[0], DFmode) |
8200 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca | 8201 | "@ |
d2288d5d HP |
8202 | ld%U1%X1 %0,%1 |
8203 | std%U0%X0 %1,%0 | |
dc4f83ca | 8204 | mr %0,%1 |
914a7297 DE |
8205 | mt%0 %1 |
8206 | mf%1 %0 | |
c4c40373 MM |
8207 | # |
8208 | # | |
e2d0915c | 8209 | # |
e0740893 | 8210 | {cror 0,0,0|nop}" |
d2288d5d | 8211 | [(set_attr "type" "load,store,*,*,*,*,*,*,*") |
e2d0915c | 8212 | (set_attr "length" "4,4,4,4,4,8,12,16,4")]) |
1fd4e8c1 | 8213 | \f |
06f4e019 DE |
8214 | (define_expand "movtf" |
8215 | [(set (match_operand:TF 0 "general_operand" "") | |
8216 | (match_operand:TF 1 "any_operand" ""))] | |
39e63627 GK |
8217 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8218 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8219 | "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") |
8220 | ||
a9baceb1 GK |
8221 | ; It's important to list the o->f and f->o moves before f->f because |
8222 | ; otherwise reload, given m->f, will try to pick f->f and reload it, | |
8223 | ; which doesn't make progress. | |
8224 | (define_insn_and_split "*movtf_internal" | |
8225 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,rm,r") | |
8226 | (match_operand:TF 1 "input_operand" "f,o,f,r,mGHF"))] | |
39e63627 GK |
8227 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8228 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
06f4e019 DE |
8229 | && (gpc_reg_operand (operands[0], TFmode) |
8230 | || gpc_reg_operand (operands[1], TFmode))" | |
a9baceb1 | 8231 | "#" |
ecb62ae7 | 8232 | "&& reload_completed" |
a9baceb1 GK |
8233 | [(pc)] |
8234 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } | |
8235 | [(set_attr "length" "8,8,8,20,20")]) | |
06f4e019 | 8236 | |
ecb62ae7 GK |
8237 | (define_expand "extenddftf2" |
8238 | [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
8239 | (float_extend:TF (match_operand:DF 1 "input_operand" ""))) | |
8240 | (use (match_dup 2))])] | |
39e63627 GK |
8241 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8242 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8243 | { |
ecb62ae7 GK |
8244 | operands[2] = CONST0_RTX (DFmode); |
8245 | }) | |
06f4e019 | 8246 | |
ecb62ae7 GK |
8247 | (define_insn_and_split "*extenddftf2_internal" |
8248 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r") | |
8249 | (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF"))) | |
8250 | (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))] | |
39e63627 GK |
8251 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8252 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 GK |
8253 | "#" |
8254 | "&& reload_completed" | |
8255 | [(pc)] | |
06f4e019 | 8256 | { |
ecb62ae7 GK |
8257 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; |
8258 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); | |
8259 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word), | |
8260 | operands[1]); | |
8261 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word), | |
8262 | operands[2]); | |
8263 | DONE; | |
6ae08853 | 8264 | }) |
ecb62ae7 GK |
8265 | |
8266 | (define_expand "extendsftf2" | |
8267 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
8268 | (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
8269 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8270 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
8271 | { | |
8272 | rtx tmp = gen_reg_rtx (DFmode); | |
8273 | emit_insn (gen_extendsfdf2 (tmp, operands[1])); | |
8274 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
8275 | DONE; | |
8276 | }) | |
06f4e019 DE |
8277 | |
8278 | (define_insn "trunctfdf2" | |
8279 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8280 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8281 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8282 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8283 | "fadd %0,%1,%L1" |
8284 | [(set_attr "type" "fp") | |
ecb62ae7 | 8285 | (set_attr "length" "4")]) |
06f4e019 DE |
8286 | |
8287 | (define_insn_and_split "trunctfsf2" | |
8288 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
ea112fc4 DE |
8289 | (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8290 | (clobber (match_scratch:DF 2 "=f"))] | |
39e63627 GK |
8291 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8292 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8293 | "#" |
ea112fc4 | 8294 | "&& reload_completed" |
06f4e019 DE |
8295 | [(set (match_dup 2) |
8296 | (float_truncate:DF (match_dup 1))) | |
8297 | (set (match_dup 0) | |
8298 | (float_truncate:SF (match_dup 2)))] | |
ea112fc4 | 8299 | "") |
06f4e019 | 8300 | |
0c90aa3c | 8301 | (define_expand "floatsitf2" |
ea112fc4 | 8302 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
0c90aa3c | 8303 | (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))] |
39e63627 GK |
8304 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8305 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
0c90aa3c GK |
8306 | { |
8307 | rtx tmp = gen_reg_rtx (DFmode); | |
8308 | expand_float (tmp, operands[1], false); | |
8309 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
8310 | DONE; | |
8311 | }) | |
06f4e019 | 8312 | |
ecb62ae7 GK |
8313 | ; fadd, but rounding towards zero. |
8314 | ; This is probably not the optimal code sequence. | |
8315 | (define_insn "fix_trunc_helper" | |
8316 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8317 | (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")] | |
8318 | UNSPEC_FIX_TRUNC_TF)) | |
8319 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))] | |
8320 | "TARGET_HARD_FLOAT && TARGET_FPRS" | |
8321 | "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" | |
8322 | [(set_attr "type" "fp") | |
8323 | (set_attr "length" "20")]) | |
8324 | ||
0c90aa3c | 8325 | (define_expand "fix_trunctfsi2" |
ecb62ae7 GK |
8326 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
8327 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" ""))) | |
8328 | (clobber (match_dup 2)) | |
8329 | (clobber (match_dup 3)) | |
8330 | (clobber (match_dup 4)) | |
8331 | (clobber (match_dup 5))])] | |
8332 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8333 | && (TARGET_POWER2 || TARGET_POWERPC) | |
8334 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
8335 | { | |
8336 | operands[2] = gen_reg_rtx (DFmode); | |
8337 | operands[3] = gen_reg_rtx (DFmode); | |
8338 | operands[4] = gen_reg_rtx (DImode); | |
8339 | operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
8340 | }) | |
8341 | ||
8342 | (define_insn_and_split "*fix_trunctfsi2_internal" | |
61c07d3c | 8343 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ecb62ae7 GK |
8344 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8345 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=f")) | |
8346 | (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f")) | |
8347 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f")) | |
8348 | (clobber (match_operand:DI 5 "memory_operand" "=o"))] | |
39e63627 GK |
8349 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8350 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 GK |
8351 | "#" |
8352 | "&& reload_completed" | |
8353 | [(pc)] | |
0c90aa3c | 8354 | { |
ecb62ae7 GK |
8355 | rtx lowword; |
8356 | emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3])); | |
8357 | ||
8358 | if (GET_CODE (operands[5]) != MEM) | |
8359 | abort(); | |
8360 | lowword = XEXP (operands[5], 0); | |
8361 | if (WORDS_BIG_ENDIAN) | |
8362 | lowword = plus_constant (lowword, 4); | |
8363 | ||
8364 | emit_insn (gen_fctiwz (operands[4], operands[2])); | |
8365 | emit_move_insn (operands[5], operands[4]); | |
8366 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
0c90aa3c GK |
8367 | DONE; |
8368 | }) | |
06f4e019 DE |
8369 | |
8370 | (define_insn "negtf2" | |
8371 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8372 | (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8373 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8374 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8375 | "* |
8376 | { | |
8377 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8378 | return \"fneg %L0,%L1\;fneg %0,%1\"; | |
8379 | else | |
8380 | return \"fneg %0,%1\;fneg %L0,%L1\"; | |
8381 | }" | |
8382 | [(set_attr "type" "fp") | |
8383 | (set_attr "length" "8")]) | |
8384 | ||
1a402dc1 | 8385 | (define_expand "abstf2" |
06f4e019 DE |
8386 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
8387 | (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8388 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8389 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 8390 | " |
06f4e019 | 8391 | { |
1a402dc1 AM |
8392 | rtx label = gen_label_rtx (); |
8393 | emit_insn (gen_abstf2_internal (operands[0], operands[1], label)); | |
8394 | emit_label (label); | |
8395 | DONE; | |
8396 | }") | |
06f4e019 | 8397 | |
1a402dc1 | 8398 | (define_expand "abstf2_internal" |
06f4e019 | 8399 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
1a402dc1 AM |
8400 | (match_operand:TF 1 "gpc_reg_operand" "f")) |
8401 | (set (match_dup 3) (match_dup 5)) | |
8402 | (set (match_dup 5) (abs:DF (match_dup 5))) | |
8403 | (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5))) | |
8404 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
8405 | (label_ref (match_operand 2 "" "")) | |
8406 | (pc))) | |
8407 | (set (match_dup 6) (neg:DF (match_dup 6)))] | |
39e63627 GK |
8408 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8409 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 8410 | " |
06f4e019 | 8411 | { |
1a402dc1 AM |
8412 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); |
8413 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; | |
8414 | operands[3] = gen_reg_rtx (DFmode); | |
8415 | operands[4] = gen_reg_rtx (CCFPmode); | |
8416 | operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); | |
8417 | operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); | |
8418 | }") | |
06f4e019 | 8419 | \f |
1fd4e8c1 RK |
8420 | ;; Next come the multi-word integer load and store and the load and store |
8421 | ;; multiple insns. | |
8422 | (define_expand "movdi" | |
8423 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 8424 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 | 8425 | "" |
fb4d4348 | 8426 | "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") |
1fd4e8c1 | 8427 | |
acad7ed3 | 8428 | (define_insn "*movdi_internal32" |
4e74d8ec MM |
8429 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") |
8430 | (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] | |
a260abc9 | 8431 | "! TARGET_POWERPC64 |
4e74d8ec MM |
8432 | && (gpc_reg_operand (operands[0], DImode) |
8433 | || gpc_reg_operand (operands[1], DImode))" | |
1fd4e8c1 RK |
8434 | "* |
8435 | { | |
8436 | switch (which_alternative) | |
8437 | { | |
a260abc9 | 8438 | default: |
a6c2a102 | 8439 | abort (); |
1fd4e8c1 | 8440 | case 0: |
1fd4e8c1 | 8441 | case 1: |
1fd4e8c1 | 8442 | case 2: |
3a1f863f | 8443 | return \"#\"; |
8ffd9c51 RK |
8444 | case 3: |
8445 | return \"fmr %0,%1\"; | |
8446 | case 4: | |
8447 | return \"lfd%U1%X1 %0,%1\"; | |
8448 | case 5: | |
8449 | return \"stfd%U0%X0 %1,%0\"; | |
4e74d8ec MM |
8450 | case 6: |
8451 | case 7: | |
8452 | case 8: | |
8453 | case 9: | |
8454 | case 10: | |
8455 | return \"#\"; | |
1fd4e8c1 RK |
8456 | } |
8457 | }" | |
3a1f863f | 8458 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")]) |
4e74d8ec MM |
8459 | |
8460 | (define_split | |
8461 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8462 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 8463 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8464 | [(set (match_dup 2) (match_dup 4)) |
8465 | (set (match_dup 3) (match_dup 1))] | |
8466 | " | |
8467 | { | |
5f59ecb7 | 8468 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
8469 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8470 | DImode); | |
8471 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8472 | DImode); | |
75d39459 | 8473 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 8474 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 8475 | #else |
5f59ecb7 | 8476 | operands[4] = GEN_INT (value >> 32); |
a65c591c | 8477 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
75d39459 | 8478 | #endif |
4e74d8ec MM |
8479 | }") |
8480 | ||
3a1f863f DE |
8481 | (define_split |
8482 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
8483 | (match_operand:DI 1 "input_operand" ""))] | |
6ae08853 | 8484 | "reload_completed && !TARGET_POWERPC64 |
3a1f863f | 8485 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
8486 | [(pc)] |
8487 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
3a1f863f | 8488 | |
6fc19dc9 AM |
8489 | (define_split |
8490 | [(set (match_operand:TI 0 "gpc_reg_operand" "") | |
8491 | (match_operand:TI 1 "const_double_operand" ""))] | |
8492 | "TARGET_POWERPC64" | |
8493 | [(set (match_dup 2) (match_dup 4)) | |
8494 | (set (match_dup 3) (match_dup 5))] | |
8495 | " | |
8496 | { | |
8497 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, | |
8498 | TImode); | |
8499 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8500 | TImode); | |
8501 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
8502 | { | |
8503 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
8504 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
8505 | } | |
8506 | else if (GET_CODE (operands[1]) == CONST_INT) | |
8507 | { | |
8508 | operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0)); | |
8509 | operands[5] = operands[1]; | |
8510 | } | |
8511 | else | |
8512 | FAIL; | |
8513 | }") | |
8514 | ||
acad7ed3 | 8515 | (define_insn "*movdi_internal64" |
5d7e6254 | 8516 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h") |
9615f239 | 8517 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 8518 | "TARGET_POWERPC64 |
4e74d8ec MM |
8519 | && (gpc_reg_operand (operands[0], DImode) |
8520 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 8521 | "@ |
3d5570cb RK |
8522 | mr %0,%1 |
8523 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8524 | std%U0%X0 %1,%0 |
3d5570cb | 8525 | li %0,%1 |
802a0058 | 8526 | lis %0,%v1 |
e6ca2c17 | 8527 | # |
aee86b38 | 8528 | {cal|la} %0,%a1 |
3d5570cb RK |
8529 | fmr %0,%1 |
8530 | lfd%U1%X1 %0,%1 | |
8531 | stfd%U0%X0 %1,%0 | |
8532 | mf%1 %0 | |
08075ead | 8533 | mt%0 %1 |
e34eaae5 | 8534 | {cror 0,0,0|nop}" |
02ca7595 | 8535 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*") |
e6ca2c17 DE |
8536 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
8537 | ||
5f59ecb7 | 8538 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
8539 | (define_insn "" |
8540 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8541 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
8542 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8543 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
8544 | && num_insns_constant (operands[1], DImode) == 1" |
8545 | "* | |
8546 | { | |
8547 | return ((unsigned HOST_WIDE_INT) | |
8548 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
8549 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
8550 | }") | |
8551 | ||
a260abc9 DE |
8552 | ;; Generate all one-bits and clear left or right. |
8553 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8554 | (define_split | |
8555 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8556 | (match_operand:DI 1 "mask64_operand" ""))] | |
8557 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8558 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8559 | (set (match_dup 0) |
a260abc9 DE |
8560 | (and:DI (rotate:DI (match_dup 0) |
8561 | (const_int 0)) | |
8562 | (match_dup 1)))] | |
8563 | "") | |
8564 | ||
8565 | ;; Split a load of a large constant into the appropriate five-instruction | |
8566 | ;; sequence. Handle anything in a constant number of insns. | |
8567 | ;; When non-easy constants can go in the TOC, this should use | |
8568 | ;; easy_fp_constant predicate. | |
8569 | (define_split | |
8570 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8571 | (match_operand:DI 1 "const_int_operand" ""))] |
8572 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8573 | [(set (match_dup 0) (match_dup 2)) | |
8574 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
e6ca2c17 | 8575 | " |
2bfcf297 DB |
8576 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8577 | ||
8578 | if (tem == operands[0]) | |
8579 | DONE; | |
e8d791dd | 8580 | else |
2bfcf297 | 8581 | FAIL; |
5f59ecb7 | 8582 | }") |
e6ca2c17 | 8583 | |
5f59ecb7 DE |
8584 | (define_split |
8585 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8586 | (match_operand:DI 1 "const_double_operand" ""))] |
8587 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8588 | [(set (match_dup 0) (match_dup 2)) | |
8589 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
5f59ecb7 | 8590 | " |
2bfcf297 DB |
8591 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8592 | ||
8593 | if (tem == operands[0]) | |
8594 | DONE; | |
8595 | else | |
8596 | FAIL; | |
e6ca2c17 | 8597 | }") |
08075ead | 8598 | |
acad7ed3 | 8599 | (define_insn "*movdi_internal2" |
bb84cb12 DE |
8600 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
8601 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r") | |
08075ead | 8602 | (const_int 0))) |
bb84cb12 | 8603 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
683bdff7 | 8604 | "TARGET_64BIT" |
9ebbca7d | 8605 | "@ |
bb84cb12 | 8606 | cmpdi %2,%0,0 |
9ebbca7d GK |
8607 | mr. %0,%1 |
8608 | #" | |
bb84cb12 DE |
8609 | [(set_attr "type" "cmp,compare,cmp") |
8610 | (set_attr "length" "4,4,8")]) | |
acad7ed3 | 8611 | |
9ebbca7d GK |
8612 | (define_split |
8613 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8614 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
8615 | (const_int 0))) | |
8616 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8617 | "TARGET_POWERPC64 && reload_completed" | |
8618 | [(set (match_dup 0) (match_dup 1)) | |
8619 | (set (match_dup 2) | |
8620 | (compare:CC (match_dup 0) | |
8621 | (const_int 0)))] | |
8622 | "") | |
acad7ed3 | 8623 | \f |
1fd4e8c1 RK |
8624 | ;; TImode is similar, except that we usually want to compute the address into |
8625 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8626 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8627 | (define_expand "movti" |
8628 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
8629 | (match_operand:TI 1 "general_operand" "")) | |
8630 | (clobber (scratch:SI))])] | |
3a1f863f | 8631 | "" |
fb4d4348 | 8632 | "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") |
1fd4e8c1 RK |
8633 | |
8634 | ;; We say that MQ is clobbered in the last alternative because the first | |
8635 | ;; alternative would never get used otherwise since it would need a reload | |
8636 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8637 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8638 | ;; giving the SCRATCH mq. | |
3a1f863f | 8639 | |
a260abc9 | 8640 | (define_insn "*movti_power" |
e1469d0d | 8641 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
8642 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
8643 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
6ae08853 | 8644 | "TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8645 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8646 | "* |
8647 | { | |
8648 | switch (which_alternative) | |
8649 | { | |
dc4f83ca MM |
8650 | default: |
8651 | abort (); | |
8652 | ||
1fd4e8c1 | 8653 | case 0: |
3a1f863f DE |
8654 | if (TARGET_STRING) |
8655 | return \"{stsi|stswi} %1,%P0,16\"; | |
1fd4e8c1 | 8656 | case 1: |
1fd4e8c1 | 8657 | case 2: |
3a1f863f | 8658 | return \"#\"; |
1fd4e8c1 RK |
8659 | case 3: |
8660 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8661 | fall through to generating four loads. */ | |
e876481c DE |
8662 | if (TARGET_STRING |
8663 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8664 | return \"{lsi|lswi} %0,%P1,16\"; |
82e41834 | 8665 | /* ... fall through ... */ |
1fd4e8c1 | 8666 | case 4: |
3a1f863f | 8667 | return \"#\"; |
1fd4e8c1 RK |
8668 | } |
8669 | }" | |
3a1f863f | 8670 | [(set_attr "type" "store,store,*,load,load")]) |
51b8fc2c | 8671 | |
a260abc9 | 8672 | (define_insn "*movti_string" |
cd1d3445 | 8673 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
27dc0551 | 8674 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))] |
3a1f863f | 8675 | "! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8676 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8677 | "* | |
8678 | { | |
8679 | switch (which_alternative) | |
8680 | { | |
8681 | default: | |
8682 | abort (); | |
dc4f83ca | 8683 | case 0: |
3a1f863f DE |
8684 | if (TARGET_STRING) |
8685 | return \"{stsi|stswi} %1,%P0,16\"; | |
dc4f83ca | 8686 | case 1: |
cd1d3445 | 8687 | case 2: |
3a1f863f | 8688 | return \"#\"; |
cd1d3445 DE |
8689 | case 3: |
8690 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8691 | fall through to generating four loads. */ | |
6ae08853 | 8692 | if (TARGET_STRING |
3a1f863f | 8693 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) |
cd1d3445 DE |
8694 | return \"{lsi|lswi} %0,%P1,16\"; |
8695 | /* ... fall through ... */ | |
8696 | case 4: | |
3a1f863f | 8697 | return \"#\"; |
dc4f83ca MM |
8698 | } |
8699 | }" | |
3a1f863f | 8700 | [(set_attr "type" "store,store,*,load,load")]) |
dc4f83ca | 8701 | |
a260abc9 | 8702 | (define_insn "*movti_ppc64" |
3a1f863f DE |
8703 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,m,r") |
8704 | (match_operand:TI 1 "input_operand" "r,r,o"))] | |
51b8fc2c RK |
8705 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) |
8706 | || gpc_reg_operand (operands[1], TImode))" | |
3a1f863f | 8707 | "@ |
6ae08853 AM |
8708 | # |
8709 | # | |
3a1f863f DE |
8710 | #" |
8711 | [(set_attr "type" "*,load,store")]) | |
8712 | ||
8713 | (define_split | |
8714 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
8715 | (match_operand:TI 1 "input_operand" ""))] | |
a9baceb1 | 8716 | "reload_completed |
3a1f863f | 8717 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
8718 | [(pc)] |
8719 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
1fd4e8c1 RK |
8720 | \f |
8721 | (define_expand "load_multiple" | |
2f622005 RK |
8722 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8723 | (match_operand:SI 1 "" "")) | |
8724 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8725 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8726 | " |
8727 | { | |
8728 | int regno; | |
8729 | int count; | |
792760b9 | 8730 | rtx op1; |
1fd4e8c1 RK |
8731 | int i; |
8732 | ||
8733 | /* Support only loading a constant number of fixed-point registers from | |
8734 | memory and only bother with this if more than two; the machine | |
8735 | doesn't support more than eight. */ | |
8736 | if (GET_CODE (operands[2]) != CONST_INT | |
8737 | || INTVAL (operands[2]) <= 2 | |
8738 | || INTVAL (operands[2]) > 8 | |
8739 | || GET_CODE (operands[1]) != MEM | |
8740 | || GET_CODE (operands[0]) != REG | |
8741 | || REGNO (operands[0]) >= 32) | |
8742 | FAIL; | |
8743 | ||
8744 | count = INTVAL (operands[2]); | |
8745 | regno = REGNO (operands[0]); | |
8746 | ||
39403d82 | 8747 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
8748 | op1 = replace_equiv_address (operands[1], |
8749 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
8750 | |
8751 | for (i = 0; i < count; i++) | |
8752 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8753 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
7ef788f0 | 8754 | adjust_address_nv (op1, SImode, i * 4)); |
1fd4e8c1 RK |
8755 | }") |
8756 | ||
9caa3eb2 | 8757 | (define_insn "*ldmsi8" |
1fd4e8c1 | 8758 | [(match_parallel 0 "load_multiple_operation" |
9caa3eb2 DE |
8759 | [(set (match_operand:SI 2 "gpc_reg_operand" "") |
8760 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8761 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8762 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8763 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8764 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8765 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8766 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8767 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8768 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8769 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8770 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8771 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8772 | (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
8773 | (set (match_operand:SI 9 "gpc_reg_operand" "") | |
8774 | (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] | |
8775 | "TARGET_STRING && XVECLEN (operands[0], 0) == 8" | |
1fd4e8c1 | 8776 | "* |
9caa3eb2 DE |
8777 | { return rs6000_output_load_multiple (operands); }" |
8778 | [(set_attr "type" "load") | |
8779 | (set_attr "length" "32")]) | |
1fd4e8c1 | 8780 | |
9caa3eb2 DE |
8781 | (define_insn "*ldmsi7" |
8782 | [(match_parallel 0 "load_multiple_operation" | |
8783 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8784 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8785 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8786 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8787 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8788 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8789 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8790 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8791 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8792 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8793 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8794 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8795 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8796 | (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] | |
8797 | "TARGET_STRING && XVECLEN (operands[0], 0) == 7" | |
8798 | "* | |
8799 | { return rs6000_output_load_multiple (operands); }" | |
8800 | [(set_attr "type" "load") | |
8801 | (set_attr "length" "32")]) | |
8802 | ||
8803 | (define_insn "*ldmsi6" | |
8804 | [(match_parallel 0 "load_multiple_operation" | |
8805 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8806 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8807 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8808 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8809 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8810 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8811 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8812 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8813 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8814 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8815 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8816 | (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] | |
8817 | "TARGET_STRING && XVECLEN (operands[0], 0) == 6" | |
8818 | "* | |
8819 | { return rs6000_output_load_multiple (operands); }" | |
8820 | [(set_attr "type" "load") | |
8821 | (set_attr "length" "32")]) | |
8822 | ||
8823 | (define_insn "*ldmsi5" | |
8824 | [(match_parallel 0 "load_multiple_operation" | |
8825 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8826 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8827 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8828 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8829 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8830 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8831 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8832 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8833 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8834 | (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] | |
8835 | "TARGET_STRING && XVECLEN (operands[0], 0) == 5" | |
8836 | "* | |
8837 | { return rs6000_output_load_multiple (operands); }" | |
8838 | [(set_attr "type" "load") | |
8839 | (set_attr "length" "32")]) | |
8840 | ||
8841 | (define_insn "*ldmsi4" | |
8842 | [(match_parallel 0 "load_multiple_operation" | |
8843 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8844 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8845 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8846 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8847 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8848 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8849 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8850 | (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] | |
8851 | "TARGET_STRING && XVECLEN (operands[0], 0) == 4" | |
8852 | "* | |
8853 | { return rs6000_output_load_multiple (operands); }" | |
8854 | [(set_attr "type" "load") | |
8855 | (set_attr "length" "32")]) | |
8856 | ||
8857 | (define_insn "*ldmsi3" | |
8858 | [(match_parallel 0 "load_multiple_operation" | |
8859 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8860 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8861 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8862 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8863 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8864 | (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] | |
8865 | "TARGET_STRING && XVECLEN (operands[0], 0) == 3" | |
8866 | "* | |
8867 | { return rs6000_output_load_multiple (operands); }" | |
b19003d8 | 8868 | [(set_attr "type" "load") |
e82ee4cc | 8869 | (set_attr "length" "32")]) |
b19003d8 | 8870 | |
1fd4e8c1 | 8871 | (define_expand "store_multiple" |
2f622005 RK |
8872 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8873 | (match_operand:SI 1 "" "")) | |
8874 | (clobber (scratch:SI)) | |
8875 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8876 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8877 | " |
8878 | { | |
8879 | int regno; | |
8880 | int count; | |
8881 | rtx to; | |
792760b9 | 8882 | rtx op0; |
1fd4e8c1 RK |
8883 | int i; |
8884 | ||
8885 | /* Support only storing a constant number of fixed-point registers to | |
8886 | memory and only bother with this if more than two; the machine | |
8887 | doesn't support more than eight. */ | |
8888 | if (GET_CODE (operands[2]) != CONST_INT | |
8889 | || INTVAL (operands[2]) <= 2 | |
8890 | || INTVAL (operands[2]) > 8 | |
8891 | || GET_CODE (operands[0]) != MEM | |
8892 | || GET_CODE (operands[1]) != REG | |
8893 | || REGNO (operands[1]) >= 32) | |
8894 | FAIL; | |
8895 | ||
8896 | count = INTVAL (operands[2]); | |
8897 | regno = REGNO (operands[1]); | |
8898 | ||
39403d82 | 8899 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 8900 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 8901 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
8902 | |
8903 | XVECEXP (operands[3], 0, 0) | |
7ef788f0 | 8904 | = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]); |
39403d82 | 8905 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8906 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8907 | |
8908 | for (i = 1; i < count; i++) | |
8909 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8910 | = gen_rtx_SET (VOIDmode, |
7ef788f0 | 8911 | adjust_address_nv (op0, SImode, i * 4), |
c5c76735 | 8912 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
8913 | }") |
8914 | ||
9caa3eb2 | 8915 | (define_insn "*store_multiple_power" |
1fd4e8c1 RK |
8916 | [(match_parallel 0 "store_multiple_operation" |
8917 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 8918 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 8919 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 8920 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
8921 | "{stsi|stswi} %2,%P1,%O0" |
8922 | [(set_attr "type" "store")]) | |
d14a6d05 | 8923 | |
e46e3130 | 8924 | (define_insn "*stmsi8" |
d14a6d05 | 8925 | [(match_parallel 0 "store_multiple_operation" |
e46e3130 DJ |
8926 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
8927 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8928 | (clobber (match_scratch:SI 3 "X")) | |
8929 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8930 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8931 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8932 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8933 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8934 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8935 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8936 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8937 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8938 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
8939 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
8940 | (match_operand:SI 9 "gpc_reg_operand" "r")) | |
8941 | (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
8942 | (match_operand:SI 10 "gpc_reg_operand" "r"))])] | |
8943 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9" | |
8944 | "{stsi|stswi} %2,%1,%O0" | |
8945 | [(set_attr "type" "store")]) | |
8946 | ||
8947 | (define_insn "*stmsi7" | |
8948 | [(match_parallel 0 "store_multiple_operation" | |
8949 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8950 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8951 | (clobber (match_scratch:SI 3 "X")) | |
8952 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8953 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8954 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8955 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8956 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8957 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8958 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8959 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8960 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8961 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
8962 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
8963 | (match_operand:SI 9 "gpc_reg_operand" "r"))])] | |
8964 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8" | |
8965 | "{stsi|stswi} %2,%1,%O0" | |
8966 | [(set_attr "type" "store")]) | |
8967 | ||
8968 | (define_insn "*stmsi6" | |
8969 | [(match_parallel 0 "store_multiple_operation" | |
8970 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8971 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8972 | (clobber (match_scratch:SI 3 "X")) | |
8973 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8974 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8975 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8976 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8977 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8978 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8979 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8980 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8981 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8982 | (match_operand:SI 8 "gpc_reg_operand" "r"))])] | |
8983 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7" | |
8984 | "{stsi|stswi} %2,%1,%O0" | |
8985 | [(set_attr "type" "store")]) | |
8986 | ||
8987 | (define_insn "*stmsi5" | |
8988 | [(match_parallel 0 "store_multiple_operation" | |
8989 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8990 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8991 | (clobber (match_scratch:SI 3 "X")) | |
8992 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8993 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8994 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8995 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8996 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8997 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8998 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8999 | (match_operand:SI 7 "gpc_reg_operand" "r"))])] | |
9000 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6" | |
9001 | "{stsi|stswi} %2,%1,%O0" | |
9002 | [(set_attr "type" "store")]) | |
9003 | ||
9004 | (define_insn "*stmsi4" | |
9005 | [(match_parallel 0 "store_multiple_operation" | |
9006 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9007 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9008 | (clobber (match_scratch:SI 3 "X")) | |
9009 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9010 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9011 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9012 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9013 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9014 | (match_operand:SI 6 "gpc_reg_operand" "r"))])] | |
9015 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5" | |
b7ff3d82 DE |
9016 | "{stsi|stswi} %2,%1,%O0" |
9017 | [(set_attr "type" "store")]) | |
7e69e155 | 9018 | |
e46e3130 DJ |
9019 | (define_insn "*stmsi3" |
9020 | [(match_parallel 0 "store_multiple_operation" | |
9021 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9022 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9023 | (clobber (match_scratch:SI 3 "X")) | |
9024 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9025 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9026 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9027 | (match_operand:SI 5 "gpc_reg_operand" "r"))])] | |
9028 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4" | |
9029 | "{stsi|stswi} %2,%1,%O0" | |
9030 | [(set_attr "type" "store")]) | |
7e69e155 MM |
9031 | \f |
9032 | ;; String/block move insn. | |
9033 | ;; Argument 0 is the destination | |
9034 | ;; Argument 1 is the source | |
9035 | ;; Argument 2 is the length | |
9036 | ;; Argument 3 is the alignment | |
9037 | ||
9038 | (define_expand "movstrsi" | |
b6c9286a MM |
9039 | [(parallel [(set (match_operand:BLK 0 "" "") |
9040 | (match_operand:BLK 1 "" "")) | |
9041 | (use (match_operand:SI 2 "" "")) | |
9042 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
9043 | "" |
9044 | " | |
9045 | { | |
9046 | if (expand_block_move (operands)) | |
9047 | DONE; | |
9048 | else | |
9049 | FAIL; | |
9050 | }") | |
9051 | ||
9052 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
9053 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
9054 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9055 | (define_expand "movstrsi_8reg" |
b6c9286a MM |
9056 | [(parallel [(set (match_operand 0 "" "") |
9057 | (match_operand 1 "" "")) | |
9058 | (use (match_operand 2 "" "")) | |
9059 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
9060 | (clobber (reg:SI 5)) |
9061 | (clobber (reg:SI 6)) | |
9062 | (clobber (reg:SI 7)) | |
9063 | (clobber (reg:SI 8)) | |
9064 | (clobber (reg:SI 9)) | |
9065 | (clobber (reg:SI 10)) | |
9066 | (clobber (reg:SI 11)) | |
9067 | (clobber (reg:SI 12)) | |
3c67b673 | 9068 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9069 | "TARGET_STRING" |
9070 | "") | |
9071 | ||
9072 | (define_insn "" | |
52d3af72 DE |
9073 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9074 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9075 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9076 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9077 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9078 | (clobber (reg:SI 6)) |
9079 | (clobber (reg:SI 7)) | |
9080 | (clobber (reg:SI 8)) | |
9081 | (clobber (reg:SI 9)) | |
9082 | (clobber (reg:SI 10)) | |
9083 | (clobber (reg:SI 11)) | |
9084 | (clobber (reg:SI 12)) | |
3c67b673 | 9085 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 9086 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
9087 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9088 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9089 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9090 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9091 | && REGNO (operands[4]) == 5" |
9092 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9093 | [(set_attr "type" "load") |
9094 | (set_attr "length" "8")]) | |
7e69e155 MM |
9095 | |
9096 | (define_insn "" | |
52d3af72 DE |
9097 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9098 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9099 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9100 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9101 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9102 | (clobber (reg:SI 6)) |
9103 | (clobber (reg:SI 7)) | |
9104 | (clobber (reg:SI 8)) | |
9105 | (clobber (reg:SI 9)) | |
9106 | (clobber (reg:SI 10)) | |
9107 | (clobber (reg:SI 11)) | |
9108 | (clobber (reg:SI 12)) | |
3c67b673 | 9109 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9110 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
9111 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9112 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9113 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9114 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9115 | && REGNO (operands[4]) == 5" |
9116 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9117 | [(set_attr "type" "load") |
9118 | (set_attr "length" "8")]) | |
7e69e155 | 9119 | |
09a625f7 TR |
9120 | (define_insn "" |
9121 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9122 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9123 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9124 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9125 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9126 | (clobber (reg:SI 6)) | |
9127 | (clobber (reg:SI 7)) | |
9128 | (clobber (reg:SI 8)) | |
9129 | (clobber (reg:SI 9)) | |
9130 | (clobber (reg:SI 10)) | |
9131 | (clobber (reg:SI 11)) | |
9132 | (clobber (reg:SI 12)) | |
9133 | (clobber (match_scratch:SI 5 "X"))] | |
9134 | "TARGET_STRING && TARGET_POWERPC64 | |
9135 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) | |
9136 | || INTVAL (operands[2]) == 0) | |
9137 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
9138 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
9139 | && REGNO (operands[4]) == 5" | |
9140 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9141 | [(set_attr "type" "load") | |
9142 | (set_attr "length" "8")]) | |
9143 | ||
7e69e155 | 9144 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the |
f9562f27 DE |
9145 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
9146 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9147 | (define_expand "movstrsi_6reg" |
b6c9286a MM |
9148 | [(parallel [(set (match_operand 0 "" "") |
9149 | (match_operand 1 "" "")) | |
9150 | (use (match_operand 2 "" "")) | |
9151 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9152 | (clobber (reg:SI 5)) |
9153 | (clobber (reg:SI 6)) | |
7e69e155 MM |
9154 | (clobber (reg:SI 7)) |
9155 | (clobber (reg:SI 8)) | |
9156 | (clobber (reg:SI 9)) | |
9157 | (clobber (reg:SI 10)) | |
3c67b673 | 9158 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9159 | "TARGET_STRING" |
9160 | "") | |
9161 | ||
9162 | (define_insn "" | |
52d3af72 DE |
9163 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9164 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9165 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9166 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9167 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9168 | (clobber (reg:SI 6)) |
9169 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9170 | (clobber (reg:SI 8)) |
9171 | (clobber (reg:SI 9)) | |
9172 | (clobber (reg:SI 10)) | |
3c67b673 | 9173 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9174 | "TARGET_STRING && TARGET_POWER |
9175 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
9176 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9177 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9178 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9179 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9180 | [(set_attr "type" "load") |
9181 | (set_attr "length" "8")]) | |
7e69e155 MM |
9182 | |
9183 | (define_insn "" | |
52d3af72 DE |
9184 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9185 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9186 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9187 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9188 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9189 | (clobber (reg:SI 6)) |
9190 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9191 | (clobber (reg:SI 8)) |
9192 | (clobber (reg:SI 9)) | |
9193 | (clobber (reg:SI 10)) | |
3c67b673 | 9194 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9195 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9196 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
9197 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9198 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9199 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9200 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9201 | [(set_attr "type" "load") |
9202 | (set_attr "length" "8")]) | |
7e69e155 | 9203 | |
09a625f7 TR |
9204 | (define_insn "" |
9205 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9206 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9207 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9208 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9209 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9210 | (clobber (reg:SI 6)) | |
9211 | (clobber (reg:SI 7)) | |
9212 | (clobber (reg:SI 8)) | |
9213 | (clobber (reg:SI 9)) | |
9214 | (clobber (reg:SI 10)) | |
9215 | (clobber (match_scratch:SI 5 "X"))] | |
9216 | "TARGET_STRING && TARGET_POWERPC64 | |
9217 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 | |
9218 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) | |
9219 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9220 | && REGNO (operands[4]) == 5" | |
9221 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9222 | [(set_attr "type" "load") | |
9223 | (set_attr "length" "8")]) | |
9224 | ||
f9562f27 DE |
9225 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
9226 | ;; problems with TImode. | |
9227 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9228 | (define_expand "movstrsi_4reg" |
b6c9286a MM |
9229 | [(parallel [(set (match_operand 0 "" "") |
9230 | (match_operand 1 "" "")) | |
9231 | (use (match_operand 2 "" "")) | |
9232 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9233 | (clobber (reg:SI 5)) |
9234 | (clobber (reg:SI 6)) | |
9235 | (clobber (reg:SI 7)) | |
9236 | (clobber (reg:SI 8)) | |
3c67b673 | 9237 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9238 | "TARGET_STRING" |
9239 | "") | |
9240 | ||
9241 | (define_insn "" | |
52d3af72 DE |
9242 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9243 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9244 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9245 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9246 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9247 | (clobber (reg:SI 6)) |
9248 | (clobber (reg:SI 7)) | |
9249 | (clobber (reg:SI 8)) | |
3c67b673 | 9250 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9251 | "TARGET_STRING && TARGET_POWER |
9252 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
9253 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9254 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9255 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9256 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9257 | [(set_attr "type" "load") |
9258 | (set_attr "length" "8")]) | |
7e69e155 MM |
9259 | |
9260 | (define_insn "" | |
52d3af72 DE |
9261 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9262 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9263 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9264 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9265 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9266 | (clobber (reg:SI 6)) |
9267 | (clobber (reg:SI 7)) | |
9268 | (clobber (reg:SI 8)) | |
3c67b673 | 9269 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9270 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9271 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
9272 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9273 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9274 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9275 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9276 | [(set_attr "type" "load") |
9277 | (set_attr "length" "8")]) | |
7e69e155 | 9278 | |
09a625f7 TR |
9279 | (define_insn "" |
9280 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9281 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9282 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9283 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9284 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9285 | (clobber (reg:SI 6)) | |
9286 | (clobber (reg:SI 7)) | |
9287 | (clobber (reg:SI 8)) | |
9288 | (clobber (match_scratch:SI 5 "X"))] | |
9289 | "TARGET_STRING && TARGET_POWERPC64 | |
9290 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
9291 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) | |
9292 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9293 | && REGNO (operands[4]) == 5" | |
9294 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9295 | [(set_attr "type" "load") | |
9296 | (set_attr "length" "8")]) | |
9297 | ||
7e69e155 MM |
9298 | ;; Move up to 8 bytes at a time. |
9299 | (define_expand "movstrsi_2reg" | |
b6c9286a MM |
9300 | [(parallel [(set (match_operand 0 "" "") |
9301 | (match_operand 1 "" "")) | |
9302 | (use (match_operand 2 "" "")) | |
9303 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9304 | (clobber (match_scratch:DI 4 "")) |
9305 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 9306 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
9307 | "") |
9308 | ||
9309 | (define_insn "" | |
52d3af72 DE |
9310 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9311 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9312 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9313 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9314 | (clobber (match_scratch:DI 4 "=&r")) | |
9315 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 9316 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
9317 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
9318 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9319 | [(set_attr "type" "load") |
9320 | (set_attr "length" "8")]) | |
7e69e155 MM |
9321 | |
9322 | (define_insn "" | |
52d3af72 DE |
9323 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9324 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9325 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9326 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9327 | (clobber (match_scratch:DI 4 "=&r")) | |
9328 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 9329 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 9330 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 9331 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9332 | [(set_attr "type" "load") |
9333 | (set_attr "length" "8")]) | |
7e69e155 MM |
9334 | |
9335 | ;; Move up to 4 bytes at a time. | |
9336 | (define_expand "movstrsi_1reg" | |
b6c9286a MM |
9337 | [(parallel [(set (match_operand 0 "" "") |
9338 | (match_operand 1 "" "")) | |
9339 | (use (match_operand 2 "" "")) | |
9340 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9341 | (clobber (match_scratch:SI 4 "")) |
9342 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
9343 | "TARGET_STRING" |
9344 | "") | |
9345 | ||
9346 | (define_insn "" | |
52d3af72 DE |
9347 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9348 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9349 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9350 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9351 | (clobber (match_scratch:SI 4 "=&r")) | |
9352 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
9353 | "TARGET_STRING && TARGET_POWER |
9354 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9355 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9356 | [(set_attr "type" "load") |
9357 | (set_attr "length" "8")]) | |
7e69e155 MM |
9358 | |
9359 | (define_insn "" | |
52d3af72 DE |
9360 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9361 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9362 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9363 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9364 | (clobber (match_scratch:SI 4 "=&r")) | |
9365 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 9366 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9367 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
09a625f7 TR |
9368 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
9369 | [(set_attr "type" "load") | |
9370 | (set_attr "length" "8")]) | |
9371 | ||
9372 | (define_insn "" | |
9373 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9374 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9375 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9376 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9377 | (clobber (match_scratch:SI 4 "=&r")) | |
9378 | (clobber (match_scratch:SI 5 "X"))] | |
9379 | "TARGET_STRING && TARGET_POWERPC64 | |
9380 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9381 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9382 | [(set_attr "type" "load") |
9383 | (set_attr "length" "8")]) | |
7e69e155 | 9384 | |
1fd4e8c1 | 9385 | \f |
7e69e155 | 9386 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
9387 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
9388 | ;; do cases where the increment is not the size of the object. | |
9389 | ;; | |
9390 | ;; In all these cases, we use operands 0 and 1 for the register being | |
9391 | ;; incremented because those are the operands that local-alloc will | |
9392 | ;; tie and these are the pair most likely to be tieable (and the ones | |
9393 | ;; that will benefit the most). | |
9394 | ||
38c1f2d7 | 9395 | (define_insn "*movdi_update1" |
51b8fc2c | 9396 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 9397 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 9398 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) |
51b8fc2c RK |
9399 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") |
9400 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9401 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9402 | "@ |
9403 | ldux %3,%0,%2 | |
9404 | ldu %3,%2(%0)" | |
b54cf83a | 9405 | [(set_attr "type" "load_ux,load_u")]) |
287f13ff | 9406 | |
4697a36c | 9407 | (define_insn "movdi_update" |
51b8fc2c | 9408 | [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 9409 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))) |
51b8fc2c RK |
9410 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) |
9411 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
9412 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9413 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9414 | "@ |
9415 | stdux %3,%0,%2 | |
b7ff3d82 | 9416 | stdu %3,%2(%0)" |
b54cf83a | 9417 | [(set_attr "type" "store_ux,store_u")]) |
51b8fc2c | 9418 | |
38c1f2d7 | 9419 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
9420 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
9421 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9422 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9423 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9424 | (plus:SI (match_dup 1) (match_dup 2)))] |
f7b3ab8a | 9425 | "TARGET_UPDATE" |
1fd4e8c1 | 9426 | "@ |
ca7f5001 RK |
9427 | {lux|lwzux} %3,%0,%2 |
9428 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a DE |
9429 | [(set_attr "type" "load_ux,load_u")]) |
9430 | ||
9431 | (define_insn "*movsi_update2" | |
9432 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
9433 | (sign_extend:DI | |
9434 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
9435 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
9436 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
9437 | (plus:DI (match_dup 1) (match_dup 2)))] | |
9438 | "TARGET_POWERPC64" | |
9439 | "lwaux %3,%0,%2" | |
9440 | [(set_attr "type" "load_ext_ux")]) | |
1fd4e8c1 | 9441 | |
4697a36c | 9442 | (define_insn "movsi_update" |
cd2b37d9 | 9443 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9444 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9445 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
9446 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9447 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9448 | "TARGET_UPDATE" |
1fd4e8c1 | 9449 | "@ |
ca7f5001 | 9450 | {stux|stwux} %3,%0,%2 |
b7ff3d82 | 9451 | {stu|stwu} %3,%2(%0)" |
b54cf83a | 9452 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9453 | |
b54cf83a | 9454 | (define_insn "*movhi_update1" |
cd2b37d9 RK |
9455 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
9456 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9457 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9458 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9459 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9460 | "TARGET_UPDATE" |
1fd4e8c1 | 9461 | "@ |
5f243543 RK |
9462 | lhzux %3,%0,%2 |
9463 | lhzu %3,%2(%0)" | |
b54cf83a | 9464 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9465 | |
38c1f2d7 | 9466 | (define_insn "*movhi_update2" |
cd2b37d9 | 9467 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9468 | (zero_extend:SI |
cd2b37d9 | 9469 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9470 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9471 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9472 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9473 | "TARGET_UPDATE" |
1fd4e8c1 | 9474 | "@ |
5f243543 RK |
9475 | lhzux %3,%0,%2 |
9476 | lhzu %3,%2(%0)" | |
b54cf83a | 9477 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9478 | |
38c1f2d7 | 9479 | (define_insn "*movhi_update3" |
cd2b37d9 | 9480 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9481 | (sign_extend:SI |
cd2b37d9 | 9482 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9483 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9484 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9485 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9486 | "TARGET_UPDATE" |
1fd4e8c1 | 9487 | "@ |
5f243543 RK |
9488 | lhaux %3,%0,%2 |
9489 | lhau %3,%2(%0)" | |
b54cf83a | 9490 | [(set_attr "type" "load_ext_ux,load_ext_u")]) |
1fd4e8c1 | 9491 | |
38c1f2d7 | 9492 | (define_insn "*movhi_update4" |
cd2b37d9 | 9493 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9494 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9495 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
9496 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9497 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9498 | "TARGET_UPDATE" |
1fd4e8c1 | 9499 | "@ |
5f243543 | 9500 | sthux %3,%0,%2 |
b7ff3d82 | 9501 | sthu %3,%2(%0)" |
b54cf83a | 9502 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9503 | |
38c1f2d7 | 9504 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
9505 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
9506 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9507 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9508 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9509 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9510 | "TARGET_UPDATE" |
1fd4e8c1 | 9511 | "@ |
5f243543 RK |
9512 | lbzux %3,%0,%2 |
9513 | lbzu %3,%2(%0)" | |
b54cf83a | 9514 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9515 | |
38c1f2d7 | 9516 | (define_insn "*movqi_update2" |
cd2b37d9 | 9517 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9518 | (zero_extend:SI |
cd2b37d9 | 9519 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9520 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9521 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9522 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9523 | "TARGET_UPDATE" |
1fd4e8c1 | 9524 | "@ |
5f243543 RK |
9525 | lbzux %3,%0,%2 |
9526 | lbzu %3,%2(%0)" | |
b54cf83a | 9527 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9528 | |
38c1f2d7 | 9529 | (define_insn "*movqi_update3" |
cd2b37d9 | 9530 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9531 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9532 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
9533 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9534 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9535 | "TARGET_UPDATE" |
1fd4e8c1 | 9536 | "@ |
5f243543 | 9537 | stbux %3,%0,%2 |
b7ff3d82 | 9538 | stbu %3,%2(%0)" |
b54cf83a | 9539 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9540 | |
38c1f2d7 | 9541 | (define_insn "*movsf_update1" |
cd2b37d9 | 9542 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 9543 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9544 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9545 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9546 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9547 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9548 | "@ |
5f243543 RK |
9549 | lfsux %3,%0,%2 |
9550 | lfsu %3,%2(%0)" | |
b54cf83a | 9551 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9552 | |
38c1f2d7 | 9553 | (define_insn "*movsf_update2" |
cd2b37d9 | 9554 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9555 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9556 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
9557 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9558 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9559 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9560 | "@ |
85fff2f3 | 9561 | stfsux %3,%0,%2 |
b7ff3d82 | 9562 | stfsu %3,%2(%0)" |
b54cf83a | 9563 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
1fd4e8c1 | 9564 | |
38c1f2d7 MM |
9565 | (define_insn "*movsf_update3" |
9566 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
9567 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9568 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
9569 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9570 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9571 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9572 | "@ |
9573 | {lux|lwzux} %3,%0,%2 | |
9574 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a | 9575 | [(set_attr "type" "load_ux,load_u")]) |
38c1f2d7 MM |
9576 | |
9577 | (define_insn "*movsf_update4" | |
9578 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9579 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
9580 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
9581 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9582 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9583 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9584 | "@ |
9585 | {stux|stwux} %3,%0,%2 | |
9586 | {stu|stwu} %3,%2(%0)" | |
b54cf83a | 9587 | [(set_attr "type" "store_ux,store_u")]) |
38c1f2d7 MM |
9588 | |
9589 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
9590 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
9591 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9592 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9593 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9594 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9595 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9596 | "@ |
5f243543 RK |
9597 | lfdux %3,%0,%2 |
9598 | lfdu %3,%2(%0)" | |
b54cf83a | 9599 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9600 | |
38c1f2d7 | 9601 | (define_insn "*movdf_update2" |
cd2b37d9 | 9602 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9603 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9604 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
9605 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9606 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9607 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9608 | "@ |
5f243543 | 9609 | stfdux %3,%0,%2 |
b7ff3d82 | 9610 | stfdu %3,%2(%0)" |
b54cf83a | 9611 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
4c70a4f3 RK |
9612 | |
9613 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
9614 | ||
90f81f99 AP |
9615 | (define_insn "*lfq_power2" |
9616 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
9617 | (match_operand:TF 1 "memory_operand" ""))] | |
9618 | "TARGET_POWER2 | |
9619 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
9620 | "lfq%U1%X1 %0,%1") | |
9621 | ||
9622 | (define_peephole2 | |
9623 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4c70a4f3 | 9624 | (match_operand:DF 1 "memory_operand" "")) |
90f81f99 | 9625 | (set (match_operand:DF 2 "gpc_reg_operand" "") |
4c70a4f3 RK |
9626 | (match_operand:DF 3 "memory_operand" ""))] |
9627 | "TARGET_POWER2 | |
a3170dc6 | 9628 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9629 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
90f81f99 AP |
9630 | && mems_ok_for_quad_peep (operands[1], operands[3])" |
9631 | [(set (match_dup 0) | |
9632 | (match_dup 1))] | |
9633 | "operands[1] = widen_memory_access (operands[1], TFmode, 0); | |
9634 | operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));") | |
4c70a4f3 | 9635 | |
90f81f99 AP |
9636 | (define_insn "*stfq_power2" |
9637 | [(set (match_operand:TF 0 "memory_operand" "") | |
9638 | (match_operand:TF 1 "gpc_reg_operand" "f"))] | |
9639 | "TARGET_POWER2 | |
9640 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
9641 | "stfq%U0%X0 %1,%0") | |
9642 | ||
9643 | ||
9644 | (define_peephole2 | |
4c70a4f3 | 9645 | [(set (match_operand:DF 0 "memory_operand" "") |
90f81f99 | 9646 | (match_operand:DF 1 "gpc_reg_operand" "")) |
4c70a4f3 | 9647 | (set (match_operand:DF 2 "memory_operand" "") |
90f81f99 | 9648 | (match_operand:DF 3 "gpc_reg_operand" ""))] |
4c70a4f3 | 9649 | "TARGET_POWER2 |
a3170dc6 | 9650 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9651 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
90f81f99 AP |
9652 | && mems_ok_for_quad_peep (operands[0], operands[2])" |
9653 | [(set (match_dup 0) | |
9654 | (match_dup 1))] | |
9655 | "operands[0] = widen_memory_access (operands[0], TFmode, 0); | |
9656 | operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));") | |
1fd4e8c1 | 9657 | \f |
c4501e62 JJ |
9658 | ;; TLS support. |
9659 | ||
9660 | ;; "b" output constraint here and on tls_ld to support tls linker optimization. | |
9661 | (define_insn "tls_gd_32" | |
b150f4f3 DE |
9662 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9663 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9664 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9665 | UNSPEC_TLSGD))] | |
9666 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9667 | "addi %0,%1,%2@got@tlsgd") | |
9668 | ||
9669 | (define_insn "tls_gd_64" | |
b150f4f3 DE |
9670 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9671 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9672 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9673 | UNSPEC_TLSGD))] | |
9674 | "HAVE_AS_TLS && TARGET_64BIT" | |
9675 | "addi %0,%1,%2@got@tlsgd") | |
9676 | ||
9677 | (define_insn "tls_ld_32" | |
b150f4f3 DE |
9678 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9679 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9680 | UNSPEC_TLSLD))] |
9681 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9682 | "addi %0,%1,%&@got@tlsld") | |
9683 | ||
9684 | (define_insn "tls_ld_64" | |
b150f4f3 DE |
9685 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9686 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9687 | UNSPEC_TLSLD))] |
9688 | "HAVE_AS_TLS && TARGET_64BIT" | |
9689 | "addi %0,%1,%&@got@tlsld") | |
9690 | ||
9691 | (define_insn "tls_dtprel_32" | |
b150f4f3 DE |
9692 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9693 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9694 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9695 | UNSPEC_TLSDTPREL))] | |
9696 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9697 | "addi %0,%1,%2@dtprel") | |
9698 | ||
9699 | (define_insn "tls_dtprel_64" | |
b150f4f3 DE |
9700 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9701 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9702 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9703 | UNSPEC_TLSDTPREL))] | |
9704 | "HAVE_AS_TLS && TARGET_64BIT" | |
9705 | "addi %0,%1,%2@dtprel") | |
9706 | ||
9707 | (define_insn "tls_dtprel_ha_32" | |
b150f4f3 DE |
9708 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9709 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9710 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9711 | UNSPEC_TLSDTPRELHA))] | |
9712 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9713 | "addis %0,%1,%2@dtprel@ha") | |
9714 | ||
9715 | (define_insn "tls_dtprel_ha_64" | |
b150f4f3 DE |
9716 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9717 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9718 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9719 | UNSPEC_TLSDTPRELHA))] | |
9720 | "HAVE_AS_TLS && TARGET_64BIT" | |
9721 | "addis %0,%1,%2@dtprel@ha") | |
9722 | ||
9723 | (define_insn "tls_dtprel_lo_32" | |
b150f4f3 DE |
9724 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9725 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9726 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9727 | UNSPEC_TLSDTPRELLO))] | |
9728 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9729 | "addi %0,%1,%2@dtprel@l") | |
9730 | ||
9731 | (define_insn "tls_dtprel_lo_64" | |
b150f4f3 DE |
9732 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9733 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9734 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9735 | UNSPEC_TLSDTPRELLO))] | |
9736 | "HAVE_AS_TLS && TARGET_64BIT" | |
9737 | "addi %0,%1,%2@dtprel@l") | |
9738 | ||
9739 | (define_insn "tls_got_dtprel_32" | |
b150f4f3 DE |
9740 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9741 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9742 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9743 | UNSPEC_TLSGOTDTPREL))] | |
9744 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9745 | "lwz %0,%2@got@dtprel(%1)") | |
9746 | ||
9747 | (define_insn "tls_got_dtprel_64" | |
b150f4f3 DE |
9748 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9749 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9750 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9751 | UNSPEC_TLSGOTDTPREL))] | |
9752 | "HAVE_AS_TLS && TARGET_64BIT" | |
9753 | "ld %0,%2@got@dtprel(%1)") | |
9754 | ||
9755 | (define_insn "tls_tprel_32" | |
b150f4f3 DE |
9756 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9757 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9758 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9759 | UNSPEC_TLSTPREL))] | |
9760 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9761 | "addi %0,%1,%2@tprel") | |
9762 | ||
9763 | (define_insn "tls_tprel_64" | |
b150f4f3 DE |
9764 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9765 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9766 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9767 | UNSPEC_TLSTPREL))] | |
9768 | "HAVE_AS_TLS && TARGET_64BIT" | |
9769 | "addi %0,%1,%2@tprel") | |
9770 | ||
9771 | (define_insn "tls_tprel_ha_32" | |
b150f4f3 DE |
9772 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9773 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9774 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9775 | UNSPEC_TLSTPRELHA))] | |
9776 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9777 | "addis %0,%1,%2@tprel@ha") | |
9778 | ||
9779 | (define_insn "tls_tprel_ha_64" | |
b150f4f3 DE |
9780 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9781 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9782 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9783 | UNSPEC_TLSTPRELHA))] | |
9784 | "HAVE_AS_TLS && TARGET_64BIT" | |
9785 | "addis %0,%1,%2@tprel@ha") | |
9786 | ||
9787 | (define_insn "tls_tprel_lo_32" | |
b150f4f3 DE |
9788 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9789 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9790 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9791 | UNSPEC_TLSTPRELLO))] | |
9792 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9793 | "addi %0,%1,%2@tprel@l") | |
9794 | ||
9795 | (define_insn "tls_tprel_lo_64" | |
b150f4f3 DE |
9796 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9797 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9798 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9799 | UNSPEC_TLSTPRELLO))] | |
9800 | "HAVE_AS_TLS && TARGET_64BIT" | |
9801 | "addi %0,%1,%2@tprel@l") | |
9802 | ||
c1207243 | 9803 | ;; "b" output constraint here and on tls_tls input to support linker tls |
c4501e62 JJ |
9804 | ;; optimization. The linker may edit the instructions emitted by a |
9805 | ;; tls_got_tprel/tls_tls pair to addis,addi. | |
9806 | (define_insn "tls_got_tprel_32" | |
b150f4f3 DE |
9807 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9808 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9809 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9810 | UNSPEC_TLSGOTTPREL))] | |
9811 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9812 | "lwz %0,%2@got@tprel(%1)") | |
9813 | ||
9814 | (define_insn "tls_got_tprel_64" | |
b150f4f3 DE |
9815 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9816 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9817 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9818 | UNSPEC_TLSGOTTPREL))] | |
9819 | "HAVE_AS_TLS && TARGET_64BIT" | |
9820 | "ld %0,%2@got@tprel(%1)") | |
9821 | ||
9822 | (define_insn "tls_tls_32" | |
b150f4f3 DE |
9823 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9824 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9825 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9826 | UNSPEC_TLSTLS))] | |
9827 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9828 | "add %0,%1,%2@tls") | |
9829 | ||
9830 | (define_insn "tls_tls_64" | |
b150f4f3 DE |
9831 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9832 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9833 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9834 | UNSPEC_TLSTLS))] | |
9835 | "HAVE_AS_TLS && TARGET_64BIT" | |
9836 | "add %0,%1,%2@tls") | |
9837 | \f | |
1fd4e8c1 RK |
9838 | ;; Next come insns related to the calling sequence. |
9839 | ;; | |
9840 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 9841 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
9842 | |
9843 | (define_expand "allocate_stack" | |
52d3af72 | 9844 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9845 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
9846 | (set (reg 1) | |
9847 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
9848 | "" |
9849 | " | |
4697a36c | 9850 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 9851 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 9852 | rtx neg_op0; |
1fd4e8c1 RK |
9853 | |
9854 | emit_move_insn (chain, stack_bot); | |
4697a36c | 9855 | |
a157febd GK |
9856 | /* Check stack bounds if necessary. */ |
9857 | if (current_function_limit_stack) | |
9858 | { | |
9859 | rtx available; | |
6ae08853 | 9860 | available = expand_binop (Pmode, sub_optab, |
a157febd GK |
9861 | stack_pointer_rtx, stack_limit_rtx, |
9862 | NULL_RTX, 1, OPTAB_WIDEN); | |
9863 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
9864 | } | |
9865 | ||
e9a25f70 JL |
9866 | if (GET_CODE (operands[1]) != CONST_INT |
9867 | || INTVAL (operands[1]) < -32767 | |
9868 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
9869 | { |
9870 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 9871 | if (TARGET_32BIT) |
e9a25f70 | 9872 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 9873 | else |
e9a25f70 | 9874 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
9875 | } |
9876 | else | |
e9a25f70 | 9877 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 9878 | |
38c1f2d7 MM |
9879 | if (TARGET_UPDATE) |
9880 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) | |
9881 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); | |
4697a36c | 9882 | |
38c1f2d7 MM |
9883 | else |
9884 | { | |
9885 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
9886 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 9887 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 9888 | } |
e9a25f70 JL |
9889 | |
9890 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
9891 | DONE; |
9892 | }") | |
59257ff7 RK |
9893 | |
9894 | ;; These patterns say how to save and restore the stack pointer. We need not | |
9895 | ;; save the stack pointer at function level since we are careful to | |
9896 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9897 | ;; when we restore the stack pointer. | |
9898 | ;; | |
9899 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9900 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9901 | ;; save area is a memory location. | |
9902 | ||
9903 | (define_expand "save_stack_function" | |
ff381587 MM |
9904 | [(match_operand 0 "any_operand" "") |
9905 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9906 | "" |
ff381587 | 9907 | "DONE;") |
59257ff7 RK |
9908 | |
9909 | (define_expand "restore_stack_function" | |
ff381587 MM |
9910 | [(match_operand 0 "any_operand" "") |
9911 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9912 | "" |
ff381587 | 9913 | "DONE;") |
59257ff7 RK |
9914 | |
9915 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
9916 | [(use (match_operand 0 "register_operand" "")) |
9917 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 9918 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 9919 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
9920 | "" |
9921 | " | |
dfdfa60f DE |
9922 | { |
9923 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 9924 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 9925 | }") |
59257ff7 RK |
9926 | |
9927 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
9928 | [(match_operand 0 "memory_operand" "") |
9929 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
9930 | "" |
9931 | " | |
9932 | { | |
a260abc9 | 9933 | rtx temp = gen_reg_rtx (Pmode); |
11b25716 | 9934 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
9935 | |
9936 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 9937 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
39e453d7 DE |
9938 | emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp); |
9939 | emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word), | |
a260abc9 | 9940 | operands[1]); |
59257ff7 RK |
9941 | DONE; |
9942 | }") | |
7e69e155 | 9943 | |
59257ff7 | 9944 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
9945 | [(match_operand 0 "register_operand" "") |
9946 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
9947 | "" |
9948 | " | |
9949 | { | |
a260abc9 | 9950 | rtx temp = gen_reg_rtx (Pmode); |
11b25716 | 9951 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
9952 | |
9953 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 | 9954 | emit_move_insn (temp, |
39e453d7 | 9955 | adjust_address_nv (operands[1], Pmode, 0)); |
a260abc9 | 9956 | emit_move_insn (operands[0], |
39e453d7 | 9957 | adjust_address_nv (operands[1], Pmode, units_per_word)); |
39403d82 | 9958 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
9959 | DONE; |
9960 | }") | |
9ebbca7d GK |
9961 | \f |
9962 | ;; TOC register handling. | |
b6c9286a | 9963 | |
9ebbca7d | 9964 | ;; Code to initialize the TOC register... |
f0f6a223 | 9965 | |
9ebbca7d | 9966 | (define_insn "load_toc_aix_si" |
e72247f4 | 9967 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
615158e2 | 9968 | (unspec:SI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 9969 | (use (reg:SI 2))])] |
2bfcf297 | 9970 | "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" |
f0f6a223 RK |
9971 | "* |
9972 | { | |
9ebbca7d GK |
9973 | char buf[30]; |
9974 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 9975 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9976 | operands[2] = gen_rtx_REG (Pmode, 2); |
9977 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
9978 | }" |
9979 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
9980 | |
9981 | (define_insn "load_toc_aix_di" | |
e72247f4 | 9982 | [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
615158e2 | 9983 | (unspec:DI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 9984 | (use (reg:DI 2))])] |
2bfcf297 | 9985 | "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" |
9ebbca7d GK |
9986 | "* |
9987 | { | |
9988 | char buf[30]; | |
f585a356 DE |
9989 | #ifdef TARGET_RELOCATABLE |
9990 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", | |
9991 | !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); | |
9992 | #else | |
9ebbca7d | 9993 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); |
f585a356 | 9994 | #endif |
2bfcf297 DB |
9995 | if (TARGET_ELF) |
9996 | strcat (buf, \"@toc\"); | |
a8a05998 | 9997 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9998 | operands[2] = gen_rtx_REG (Pmode, 2); |
9999 | return \"ld %0,%1(%2)\"; | |
10000 | }" | |
10001 | [(set_attr "type" "load")]) | |
10002 | ||
10003 | (define_insn "load_toc_v4_pic_si" | |
10004 | [(set (match_operand:SI 0 "register_operand" "=l") | |
615158e2 | 10005 | (unspec:SI [(const_int 0)] UNSPEC_TOC))] |
f607bc57 | 10006 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" |
9ebbca7d GK |
10007 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
10008 | [(set_attr "type" "branch") | |
10009 | (set_attr "length" "4")]) | |
10010 | ||
9ebbca7d GK |
10011 | (define_insn "load_toc_v4_PIC_1" |
10012 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10013 | (match_operand:SI 1 "immediate_operand" "s")) | |
c4501e62 | 10014 | (use (unspec [(match_dup 1)] UNSPEC_TOC))] |
20b71b17 | 10015 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
df7a8989 | 10016 | "bcl 20,31,%1\\n%1:" |
9ebbca7d GK |
10017 | [(set_attr "type" "branch") |
10018 | (set_attr "length" "4")]) | |
10019 | ||
10020 | (define_insn "load_toc_v4_PIC_1b" | |
10021 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10022 | (match_operand:SI 1 "immediate_operand" "s")) | |
c4501e62 JJ |
10023 | (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] |
10024 | UNSPEC_TOCPTR))] | |
20b71b17 | 10025 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
c4501e62 | 10026 | "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1" |
9ebbca7d GK |
10027 | [(set_attr "type" "branch") |
10028 | (set_attr "length" "8")]) | |
10029 | ||
10030 | (define_insn "load_toc_v4_PIC_2" | |
f585a356 | 10031 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
a2900460 | 10032 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
9ebbca7d GK |
10033 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") |
10034 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
20b71b17 | 10035 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
9ebbca7d GK |
10036 | "{l|lwz} %0,%2-%3(%1)" |
10037 | [(set_attr "type" "load")]) | |
10038 | ||
ee890fe2 SS |
10039 | (define_insn "load_macho_picbase" |
10040 | [(set (match_operand:SI 0 "register_operand" "=l") | |
615158e2 JJ |
10041 | (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] |
10042 | UNSPEC_LD_MPIC))] | |
ee890fe2 | 10043 | "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" |
f51eee6a | 10044 | "bcl 20,31,%1\\n%1:" |
ee890fe2 SS |
10045 | [(set_attr "type" "branch") |
10046 | (set_attr "length" "4")]) | |
10047 | ||
f51eee6a GK |
10048 | (define_insn "macho_correct_pic" |
10049 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
8291cc0e | 10050 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
f51eee6a GK |
10051 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "s") |
10052 | (match_operand:SI 3 "immediate_operand" "s")] | |
615158e2 | 10053 | UNSPEC_MPIC_CORRECT)))] |
f51eee6a | 10054 | "DEFAULT_ABI == ABI_DARWIN" |
8291cc0e | 10055 | "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)" |
f51eee6a GK |
10056 | [(set_attr "length" "8")]) |
10057 | ||
9ebbca7d GK |
10058 | ;; If the TOC is shared over a translation unit, as happens with all |
10059 | ;; the kinds of PIC that we support, we need to restore the TOC | |
10060 | ;; pointer only when jumping over units of translation. | |
f51eee6a | 10061 | ;; On Darwin, we need to reload the picbase. |
9ebbca7d GK |
10062 | |
10063 | (define_expand "builtin_setjmp_receiver" | |
10064 | [(use (label_ref (match_operand 0 "" "")))] | |
f607bc57 | 10065 | "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
f51eee6a GK |
10066 | || (TARGET_TOC && TARGET_MINIMAL_TOC) |
10067 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" | |
9ebbca7d GK |
10068 | " |
10069 | { | |
84d7dd4a | 10070 | #if TARGET_MACHO |
f51eee6a GK |
10071 | if (DEFAULT_ABI == ABI_DARWIN) |
10072 | { | |
d24652ee | 10073 | const char *picbase = machopic_function_base_name (); |
485bad26 | 10074 | rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase)); |
f51eee6a GK |
10075 | rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
10076 | rtx tmplabrtx; | |
10077 | char tmplab[20]; | |
10078 | ||
10079 | ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", | |
10080 | CODE_LABEL_NUMBER (operands[0])); | |
485bad26 | 10081 | tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); |
f51eee6a GK |
10082 | |
10083 | emit_insn (gen_load_macho_picbase (picreg, tmplabrtx)); | |
10084 | emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); | |
10085 | } | |
10086 | else | |
84d7dd4a | 10087 | #endif |
f51eee6a | 10088 | rs6000_emit_load_toc_table (FALSE); |
9ebbca7d GK |
10089 | DONE; |
10090 | }") | |
10091 | \f | |
10092 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
10093 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
10094 | ;; pointer to its TOC, and whose third word contains a value to place in the |
10095 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 10096 | ;; "trampoline" need not have any executable code. |
b6c9286a | 10097 | |
cccf3bdc DE |
10098 | (define_expand "call_indirect_aix32" |
10099 | [(set (match_dup 2) | |
10100 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
10101 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10102 | (reg:SI 2)) | |
10103 | (set (reg:SI 2) | |
10104 | (mem:SI (plus:SI (match_dup 0) | |
10105 | (const_int 4)))) | |
10106 | (set (reg:SI 11) | |
10107 | (mem:SI (plus:SI (match_dup 0) | |
10108 | (const_int 8)))) | |
10109 | (parallel [(call (mem:SI (match_dup 2)) | |
10110 | (match_operand 1 "" "")) | |
10111 | (use (reg:SI 2)) | |
10112 | (use (reg:SI 11)) | |
10113 | (set (reg:SI 2) | |
10114 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10115 | (clobber (scratch:SI))])] | |
10116 | "TARGET_32BIT" | |
10117 | " | |
10118 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10119 | |
cccf3bdc DE |
10120 | (define_expand "call_indirect_aix64" |
10121 | [(set (match_dup 2) | |
10122 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
10123 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10124 | (reg:DI 2)) | |
10125 | (set (reg:DI 2) | |
10126 | (mem:DI (plus:DI (match_dup 0) | |
10127 | (const_int 8)))) | |
10128 | (set (reg:DI 11) | |
10129 | (mem:DI (plus:DI (match_dup 0) | |
10130 | (const_int 16)))) | |
10131 | (parallel [(call (mem:SI (match_dup 2)) | |
10132 | (match_operand 1 "" "")) | |
10133 | (use (reg:DI 2)) | |
10134 | (use (reg:DI 11)) | |
10135 | (set (reg:DI 2) | |
10136 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10137 | (clobber (scratch:SI))])] | |
10138 | "TARGET_64BIT" | |
10139 | " | |
10140 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 10141 | |
cccf3bdc DE |
10142 | (define_expand "call_value_indirect_aix32" |
10143 | [(set (match_dup 3) | |
10144 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10145 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10146 | (reg:SI 2)) | |
10147 | (set (reg:SI 2) | |
10148 | (mem:SI (plus:SI (match_dup 1) | |
10149 | (const_int 4)))) | |
10150 | (set (reg:SI 11) | |
10151 | (mem:SI (plus:SI (match_dup 1) | |
10152 | (const_int 8)))) | |
10153 | (parallel [(set (match_operand 0 "" "") | |
10154 | (call (mem:SI (match_dup 3)) | |
10155 | (match_operand 2 "" ""))) | |
10156 | (use (reg:SI 2)) | |
10157 | (use (reg:SI 11)) | |
10158 | (set (reg:SI 2) | |
10159 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10160 | (clobber (scratch:SI))])] | |
10161 | "TARGET_32BIT" | |
10162 | " | |
10163 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10164 | |
cccf3bdc DE |
10165 | (define_expand "call_value_indirect_aix64" |
10166 | [(set (match_dup 3) | |
10167 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10168 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10169 | (reg:DI 2)) | |
10170 | (set (reg:DI 2) | |
10171 | (mem:DI (plus:DI (match_dup 1) | |
10172 | (const_int 8)))) | |
10173 | (set (reg:DI 11) | |
10174 | (mem:DI (plus:DI (match_dup 1) | |
10175 | (const_int 16)))) | |
10176 | (parallel [(set (match_operand 0 "" "") | |
10177 | (call (mem:SI (match_dup 3)) | |
10178 | (match_operand 2 "" ""))) | |
10179 | (use (reg:DI 2)) | |
10180 | (use (reg:DI 11)) | |
10181 | (set (reg:DI 2) | |
10182 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10183 | (clobber (scratch:SI))])] | |
10184 | "TARGET_64BIT" | |
10185 | " | |
10186 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 10187 | |
b6c9286a | 10188 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 10189 | (define_expand "call" |
a260abc9 | 10190 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 10191 | (match_operand 1 "" "")) |
4697a36c | 10192 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
10193 | (clobber (scratch:SI))])] |
10194 | "" | |
10195 | " | |
10196 | { | |
ee890fe2 | 10197 | #if TARGET_MACHO |
ab82a49f | 10198 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
10199 | operands[0] = machopic_indirect_call_target (operands[0]); |
10200 | #endif | |
10201 | ||
1fd4e8c1 RK |
10202 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) |
10203 | abort (); | |
10204 | ||
10205 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 10206 | |
6a4cee5f | 10207 | if (GET_CODE (operands[0]) != SYMBOL_REF |
473f51b6 | 10208 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0])) |
efdba735 | 10209 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0)) |
1fd4e8c1 | 10210 | { |
6a4cee5f MM |
10211 | if (INTVAL (operands[2]) & CALL_LONG) |
10212 | operands[0] = rs6000_longcall_ref (operands[0]); | |
10213 | ||
cccf3bdc | 10214 | if (DEFAULT_ABI == ABI_V4 |
f607bc57 | 10215 | || DEFAULT_ABI == ABI_DARWIN) |
bbf294a5 | 10216 | operands[0] = force_reg (Pmode, operands[0]); |
1fd4e8c1 | 10217 | |
cccf3bdc DE |
10218 | else if (DEFAULT_ABI == ABI_AIX) |
10219 | { | |
10220 | /* AIX function pointers are really pointers to a three word | |
10221 | area. */ | |
10222 | emit_call_insn (TARGET_32BIT | |
10223 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
10224 | operands[0]), | |
10225 | operands[1]) | |
10226 | : gen_call_indirect_aix64 (force_reg (DImode, | |
10227 | operands[0]), | |
10228 | operands[1])); | |
10229 | DONE; | |
b6c9286a | 10230 | } |
cccf3bdc DE |
10231 | else |
10232 | abort (); | |
1fd4e8c1 RK |
10233 | } |
10234 | }") | |
10235 | ||
10236 | (define_expand "call_value" | |
10237 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 10238 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 10239 | (match_operand 2 "" ""))) |
4697a36c | 10240 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
10241 | (clobber (scratch:SI))])] |
10242 | "" | |
10243 | " | |
10244 | { | |
ee890fe2 | 10245 | #if TARGET_MACHO |
ab82a49f | 10246 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
10247 | operands[1] = machopic_indirect_call_target (operands[1]); |
10248 | #endif | |
10249 | ||
1fd4e8c1 RK |
10250 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) |
10251 | abort (); | |
10252 | ||
10253 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 10254 | |
6a4cee5f | 10255 | if (GET_CODE (operands[1]) != SYMBOL_REF |
473f51b6 | 10256 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1])) |
efdba735 | 10257 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0)) |
1fd4e8c1 | 10258 | { |
6756293c | 10259 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
10260 | operands[1] = rs6000_longcall_ref (operands[1]); |
10261 | ||
cccf3bdc | 10262 | if (DEFAULT_ABI == ABI_V4 |
f607bc57 | 10263 | || DEFAULT_ABI == ABI_DARWIN) |
bbf294a5 | 10264 | operands[1] = force_reg (Pmode, operands[1]); |
1fd4e8c1 | 10265 | |
cccf3bdc DE |
10266 | else if (DEFAULT_ABI == ABI_AIX) |
10267 | { | |
10268 | /* AIX function pointers are really pointers to a three word | |
10269 | area. */ | |
10270 | emit_call_insn (TARGET_32BIT | |
10271 | ? gen_call_value_indirect_aix32 (operands[0], | |
10272 | force_reg (SImode, | |
10273 | operands[1]), | |
10274 | operands[2]) | |
10275 | : gen_call_value_indirect_aix64 (operands[0], | |
10276 | force_reg (DImode, | |
10277 | operands[1]), | |
10278 | operands[2])); | |
10279 | DONE; | |
b6c9286a | 10280 | } |
cccf3bdc DE |
10281 | else |
10282 | abort (); | |
1fd4e8c1 RK |
10283 | } |
10284 | }") | |
10285 | ||
04780ee7 | 10286 | ;; Call to function in current module. No TOC pointer reload needed. |
a0ab749a | 10287 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10288 | ;; either the function was not prototyped, or it was prototyped as a |
10289 | ;; variable argument function. It is > 0 if FP registers were passed | |
10290 | ;; and < 0 if they were not. | |
04780ee7 | 10291 | |
a260abc9 | 10292 | (define_insn "*call_local32" |
4697a36c MM |
10293 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
10294 | (match_operand 1 "" "g,g")) | |
10295 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10296 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 10297 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
10298 | "* |
10299 | { | |
6a4cee5f MM |
10300 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
10301 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10302 | ||
10303 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10304 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 10305 | |
a226df46 | 10306 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 10307 | }" |
b7ff3d82 DE |
10308 | [(set_attr "type" "branch") |
10309 | (set_attr "length" "4,8")]) | |
04780ee7 | 10310 | |
a260abc9 DE |
10311 | (define_insn "*call_local64" |
10312 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10313 | (match_operand 1 "" "g,g")) | |
10314 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10315 | (clobber (match_scratch:SI 3 "=l,l"))] | |
10316 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10317 | "* | |
10318 | { | |
10319 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10320 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10321 | ||
10322 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10323 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10324 | ||
10325 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
10326 | }" | |
10327 | [(set_attr "type" "branch") | |
10328 | (set_attr "length" "4,8")]) | |
10329 | ||
cccf3bdc | 10330 | (define_insn "*call_value_local32" |
d18dba68 | 10331 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10332 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) |
10333 | (match_operand 2 "" "g,g"))) | |
10334 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10335 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10336 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10337 | "* | |
10338 | { | |
10339 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10340 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10341 | ||
10342 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10343 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10344 | ||
10345 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10346 | }" | |
10347 | [(set_attr "type" "branch") | |
10348 | (set_attr "length" "4,8")]) | |
10349 | ||
10350 | ||
cccf3bdc | 10351 | (define_insn "*call_value_local64" |
d18dba68 | 10352 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10353 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) |
10354 | (match_operand 2 "" "g,g"))) | |
10355 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10356 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10357 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10358 | "* | |
10359 | { | |
10360 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10361 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10362 | ||
10363 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10364 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10365 | ||
10366 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10367 | }" | |
10368 | [(set_attr "type" "branch") | |
10369 | (set_attr "length" "4,8")]) | |
10370 | ||
04780ee7 | 10371 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 10372 | ;; pointer (r2) after the call unless this is System V. |
a0ab749a | 10373 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10374 | ;; either the function was not prototyped, or it was prototyped as a |
10375 | ;; variable argument function. It is > 0 if FP registers were passed | |
10376 | ;; and < 0 if they were not. | |
04780ee7 | 10377 | |
cccf3bdc DE |
10378 | (define_insn "*call_indirect_nonlocal_aix32" |
10379 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) | |
10380 | (match_operand 1 "" "g")) | |
10381 | (use (reg:SI 2)) | |
10382 | (use (reg:SI 11)) | |
10383 | (set (reg:SI 2) | |
10384 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
c77e04ae | 10385 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10386 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
10387 | "b%T0l\;{l|lwz} 2,20(1)" | |
10388 | [(set_attr "type" "jmpreg") | |
10389 | (set_attr "length" "8")]) | |
10390 | ||
a260abc9 | 10391 | (define_insn "*call_nonlocal_aix32" |
cc4d5fec | 10392 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10393 | (match_operand 1 "" "g")) |
10394 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10395 | (clobber (match_scratch:SI 3 "=l"))] | |
10396 | "TARGET_32BIT | |
10397 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10398 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10399 | "bl %z0\;%." |
b7ff3d82 | 10400 | [(set_attr "type" "branch") |
cccf3bdc DE |
10401 | (set_attr "length" "8")]) |
10402 | ||
10403 | (define_insn "*call_indirect_nonlocal_aix64" | |
10404 | [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) | |
10405 | (match_operand 1 "" "g")) | |
10406 | (use (reg:DI 2)) | |
10407 | (use (reg:DI 11)) | |
10408 | (set (reg:DI 2) | |
10409 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
c77e04ae | 10410 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10411 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
10412 | "b%T0l\;ld 2,40(1)" | |
10413 | [(set_attr "type" "jmpreg") | |
10414 | (set_attr "length" "8")]) | |
59313e4e | 10415 | |
a260abc9 | 10416 | (define_insn "*call_nonlocal_aix64" |
cc4d5fec | 10417 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10418 | (match_operand 1 "" "g")) |
10419 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10420 | (clobber (match_scratch:SI 3 "=l"))] | |
6ae08853 | 10421 | "TARGET_64BIT |
9ebbca7d | 10422 | && DEFAULT_ABI == ABI_AIX |
a260abc9 | 10423 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10424 | "bl %z0\;%." |
a260abc9 | 10425 | [(set_attr "type" "branch") |
cccf3bdc | 10426 | (set_attr "length" "8")]) |
7509c759 | 10427 | |
cccf3bdc | 10428 | (define_insn "*call_value_indirect_nonlocal_aix32" |
d18dba68 | 10429 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10430 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) |
10431 | (match_operand 2 "" "g"))) | |
10432 | (use (reg:SI 2)) | |
10433 | (use (reg:SI 11)) | |
10434 | (set (reg:SI 2) | |
10435 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10436 | (clobber (match_scratch:SI 3 "=l"))] | |
10437 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" | |
10438 | "b%T1l\;{l|lwz} 2,20(1)" | |
10439 | [(set_attr "type" "jmpreg") | |
10440 | (set_attr "length" "8")]) | |
1fd4e8c1 | 10441 | |
cccf3bdc | 10442 | (define_insn "*call_value_nonlocal_aix32" |
d18dba68 | 10443 | [(set (match_operand 0 "" "") |
cc4d5fec | 10444 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10445 | (match_operand 2 "" "g"))) |
10446 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10447 | (clobber (match_scratch:SI 4 "=l"))] | |
10448 | "TARGET_32BIT | |
10449 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10450 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 10451 | "bl %z1\;%." |
b7ff3d82 | 10452 | [(set_attr "type" "branch") |
cccf3bdc | 10453 | (set_attr "length" "8")]) |
04780ee7 | 10454 | |
cccf3bdc | 10455 | (define_insn "*call_value_indirect_nonlocal_aix64" |
d18dba68 | 10456 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10457 | (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) |
10458 | (match_operand 2 "" "g"))) | |
10459 | (use (reg:DI 2)) | |
10460 | (use (reg:DI 11)) | |
10461 | (set (reg:DI 2) | |
10462 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10463 | (clobber (match_scratch:SI 3 "=l"))] | |
10464 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" | |
10465 | "b%T1l\;ld 2,40(1)" | |
10466 | [(set_attr "type" "jmpreg") | |
10467 | (set_attr "length" "8")]) | |
10468 | ||
10469 | (define_insn "*call_value_nonlocal_aix64" | |
d18dba68 | 10470 | [(set (match_operand 0 "" "") |
cc4d5fec | 10471 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10472 | (match_operand 2 "" "g"))) |
10473 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10474 | (clobber (match_scratch:SI 4 "=l"))] | |
6ae08853 | 10475 | "TARGET_64BIT |
9ebbca7d | 10476 | && DEFAULT_ABI == ABI_AIX |
5a19791c | 10477 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
10478 | "bl %z1\;%." |
10479 | [(set_attr "type" "branch") | |
10480 | (set_attr "length" "8")]) | |
10481 | ||
10482 | ;; A function pointer under System V is just a normal pointer | |
10483 | ;; operands[0] is the function pointer | |
10484 | ;; operands[1] is the stack size to clean up | |
10485 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
10486 | ;; which indicates how to set cr1 | |
10487 | ||
a5c76ee6 ZW |
10488 | (define_insn "*call_indirect_nonlocal_sysv" |
10489 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl")) | |
10490 | (match_operand 1 "" "g,g")) | |
10491 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10492 | (clobber (match_scratch:SI 3 "=l,l"))] | |
50d440bc | 10493 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10494 | || DEFAULT_ABI == ABI_DARWIN" |
911f679c | 10495 | { |
cccf3bdc | 10496 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10497 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f | 10498 | |
cccf3bdc | 10499 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
a5c76ee6 | 10500 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10501 | |
a5c76ee6 ZW |
10502 | return "b%T0l"; |
10503 | } | |
10504 | [(set_attr "type" "jmpreg,jmpreg") | |
10505 | (set_attr "length" "4,8")]) | |
cccf3bdc | 10506 | |
a5c76ee6 ZW |
10507 | (define_insn "*call_nonlocal_sysv" |
10508 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10509 | (match_operand 1 "" "g,g")) | |
10510 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10511 | (clobber (match_scratch:SI 3 "=l,l"))] | |
efdba735 SH |
10512 | "(DEFAULT_ABI == ABI_DARWIN |
10513 | || (DEFAULT_ABI == ABI_V4 | |
10514 | && (INTVAL (operands[2]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10515 | { |
10516 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10517 | output_asm_insn ("crxor 6,6,6", operands); | |
10518 | ||
10519 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10520 | output_asm_insn ("creqv 6,6,6", operands); | |
10521 | ||
c989f2f7 | 10522 | #if TARGET_MACHO |
efdba735 SH |
10523 | return output_call(insn, operands, 0, 2); |
10524 | #else | |
a5c76ee6 | 10525 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0"; |
6ae08853 | 10526 | #endif |
a5c76ee6 ZW |
10527 | } |
10528 | [(set_attr "type" "branch,branch") | |
10529 | (set_attr "length" "4,8")]) | |
10530 | ||
10531 | (define_insn "*call_value_indirect_nonlocal_sysv" | |
d18dba68 | 10532 | [(set (match_operand 0 "" "") |
a5c76ee6 ZW |
10533 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl")) |
10534 | (match_operand 2 "" "g,g"))) | |
10535 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10536 | (clobber (match_scratch:SI 4 "=l,l"))] | |
50d440bc | 10537 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10538 | || DEFAULT_ABI == ABI_DARWIN" |
b6c9286a | 10539 | { |
6a4cee5f | 10540 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10541 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f MM |
10542 | |
10543 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
a5c76ee6 | 10544 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10545 | |
a5c76ee6 ZW |
10546 | return "b%T1l"; |
10547 | } | |
10548 | [(set_attr "type" "jmpreg,jmpreg") | |
10549 | (set_attr "length" "4,8")]) | |
10550 | ||
10551 | (define_insn "*call_value_nonlocal_sysv" | |
10552 | [(set (match_operand 0 "" "") | |
10553 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10554 | (match_operand 2 "" "g,g"))) | |
10555 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10556 | (clobber (match_scratch:SI 4 "=l,l"))] | |
efdba735 SH |
10557 | "(DEFAULT_ABI == ABI_DARWIN |
10558 | || (DEFAULT_ABI == ABI_V4 | |
10559 | && (INTVAL (operands[3]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10560 | { |
10561 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10562 | output_asm_insn ("crxor 6,6,6", operands); | |
10563 | ||
10564 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10565 | output_asm_insn ("creqv 6,6,6", operands); | |
10566 | ||
c989f2f7 | 10567 | #if TARGET_MACHO |
efdba735 SH |
10568 | return output_call(insn, operands, 1, 3); |
10569 | #else | |
a5c76ee6 | 10570 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1"; |
6ae08853 | 10571 | #endif |
a5c76ee6 ZW |
10572 | } |
10573 | [(set_attr "type" "branch,branch") | |
10574 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
10575 | |
10576 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
10577 | (define_expand "untyped_call" |
10578 | [(parallel [(call (match_operand 0 "" "") | |
10579 | (const_int 0)) | |
10580 | (match_operand 1 "" "") | |
10581 | (match_operand 2 "" "")])] | |
10582 | "" | |
10583 | " | |
10584 | { | |
10585 | int i; | |
10586 | ||
7d70b8b2 | 10587 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
10588 | |
10589 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10590 | { | |
10591 | rtx set = XVECEXP (operands[2], 0, i); | |
10592 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10593 | } | |
10594 | ||
10595 | /* The optimizer does not know that the call sets the function value | |
10596 | registers we stored in the result block. We avoid problems by | |
10597 | claiming that all hard registers are used and clobbered at this | |
10598 | point. */ | |
10599 | emit_insn (gen_blockage ()); | |
10600 | ||
10601 | DONE; | |
10602 | }") | |
10603 | ||
5e1bf043 DJ |
10604 | ;; sibling call patterns |
10605 | (define_expand "sibcall" | |
10606 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) | |
10607 | (match_operand 1 "" "")) | |
10608 | (use (match_operand 2 "" "")) | |
fe352c29 | 10609 | (use (match_operand 3 "" "")) |
5e1bf043 DJ |
10610 | (return)])] |
10611 | "" | |
10612 | " | |
10613 | { | |
10614 | #if TARGET_MACHO | |
ab82a49f | 10615 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10616 | operands[0] = machopic_indirect_call_target (operands[0]); |
10617 | #endif | |
10618 | ||
10619 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) | |
10620 | abort (); | |
10621 | ||
10622 | operands[0] = XEXP (operands[0], 0); | |
fe352c29 | 10623 | operands[3] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10624 | |
10625 | }") | |
10626 | ||
10627 | ;; this and similar patterns must be marked as using LR, otherwise | |
10628 | ;; dataflow will try to delete the store into it. This is true | |
10629 | ;; even when the actual reg to jump to is in CTR, when LR was | |
10630 | ;; saved and restored around the PIC-setting BCL. | |
10631 | (define_insn "*sibcall_local32" | |
10632 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) | |
10633 | (match_operand 1 "" "g,g")) | |
10634 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10635 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10636 | (return)] |
10637 | "(INTVAL (operands[2]) & CALL_LONG) == 0" | |
10638 | "* | |
10639 | { | |
10640 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10641 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10642 | ||
10643 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10644 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10645 | ||
10646 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10647 | }" | |
10648 | [(set_attr "type" "branch") | |
10649 | (set_attr "length" "4,8")]) | |
10650 | ||
10651 | (define_insn "*sibcall_local64" | |
10652 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10653 | (match_operand 1 "" "g,g")) | |
10654 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10655 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10656 | (return)] |
10657 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10658 | "* | |
10659 | { | |
10660 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10661 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10662 | ||
10663 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10664 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10665 | ||
10666 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10667 | }" | |
10668 | [(set_attr "type" "branch") | |
10669 | (set_attr "length" "4,8")]) | |
10670 | ||
10671 | (define_insn "*sibcall_value_local32" | |
10672 | [(set (match_operand 0 "" "") | |
10673 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
10674 | (match_operand 2 "" "g,g"))) | |
10675 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10676 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10677 | (return)] |
10678 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10679 | "* | |
10680 | { | |
10681 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10682 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10683 | ||
10684 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10685 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10686 | ||
10687 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10688 | }" | |
10689 | [(set_attr "type" "branch") | |
10690 | (set_attr "length" "4,8")]) | |
10691 | ||
10692 | ||
10693 | (define_insn "*sibcall_value_local64" | |
10694 | [(set (match_operand 0 "" "") | |
10695 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
10696 | (match_operand 2 "" "g,g"))) | |
10697 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10698 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10699 | (return)] |
10700 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10701 | "* | |
10702 | { | |
10703 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10704 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10705 | ||
10706 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10707 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10708 | ||
10709 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10710 | }" | |
10711 | [(set_attr "type" "branch") | |
10712 | (set_attr "length" "4,8")]) | |
10713 | ||
10714 | (define_insn "*sibcall_nonlocal_aix32" | |
10715 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) | |
10716 | (match_operand 1 "" "g")) | |
10717 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10718 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 DJ |
10719 | (return)] |
10720 | "TARGET_32BIT | |
10721 | && DEFAULT_ABI == ABI_AIX | |
10722 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10723 | "b %z0" | |
10724 | [(set_attr "type" "branch") | |
10725 | (set_attr "length" "4")]) | |
10726 | ||
10727 | (define_insn "*sibcall_nonlocal_aix64" | |
10728 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) | |
10729 | (match_operand 1 "" "g")) | |
10730 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10731 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 | 10732 | (return)] |
6ae08853 | 10733 | "TARGET_64BIT |
5e1bf043 DJ |
10734 | && DEFAULT_ABI == ABI_AIX |
10735 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10736 | "b %z0" | |
10737 | [(set_attr "type" "branch") | |
10738 | (set_attr "length" "4")]) | |
10739 | ||
10740 | (define_insn "*sibcall_value_nonlocal_aix32" | |
10741 | [(set (match_operand 0 "" "") | |
10742 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) | |
10743 | (match_operand 2 "" "g"))) | |
10744 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10745 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 DJ |
10746 | (return)] |
10747 | "TARGET_32BIT | |
10748 | && DEFAULT_ABI == ABI_AIX | |
10749 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10750 | "b %z1" | |
10751 | [(set_attr "type" "branch") | |
10752 | (set_attr "length" "4")]) | |
10753 | ||
10754 | (define_insn "*sibcall_value_nonlocal_aix64" | |
10755 | [(set (match_operand 0 "" "") | |
10756 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) | |
10757 | (match_operand 2 "" "g"))) | |
10758 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10759 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 | 10760 | (return)] |
6ae08853 | 10761 | "TARGET_64BIT |
5e1bf043 DJ |
10762 | && DEFAULT_ABI == ABI_AIX |
10763 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10764 | "b %z1" | |
10765 | [(set_attr "type" "branch") | |
10766 | (set_attr "length" "4")]) | |
10767 | ||
10768 | (define_insn "*sibcall_nonlocal_sysv" | |
10769 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10770 | (match_operand 1 "" "")) | |
10771 | (use (match_operand 2 "immediate_operand" "O,n")) | |
fe352c29 | 10772 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10773 | (return)] |
10774 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10775 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10776 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
10777 | "* | |
10778 | { | |
10779 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10780 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10781 | ||
10782 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10783 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10784 | ||
10785 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\"; | |
10786 | }" | |
10787 | [(set_attr "type" "branch,branch") | |
10788 | (set_attr "length" "4,8")]) | |
10789 | ||
10790 | (define_expand "sibcall_value" | |
10791 | [(parallel [(set (match_operand 0 "register_operand" "") | |
10792 | (call (mem:SI (match_operand 1 "address_operand" "")) | |
10793 | (match_operand 2 "" ""))) | |
10794 | (use (match_operand 3 "" "")) | |
fe352c29 | 10795 | (use (match_operand 4 "" "")) |
5e1bf043 DJ |
10796 | (return)])] |
10797 | "" | |
10798 | " | |
10799 | { | |
10800 | #if TARGET_MACHO | |
ab82a49f | 10801 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10802 | operands[1] = machopic_indirect_call_target (operands[1]); |
10803 | #endif | |
10804 | ||
10805 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) | |
10806 | abort (); | |
10807 | ||
10808 | operands[1] = XEXP (operands[1], 0); | |
fe352c29 | 10809 | operands[4] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10810 | |
10811 | }") | |
10812 | ||
10813 | (define_insn "*sibcall_value_nonlocal_sysv" | |
10814 | [(set (match_operand 0 "" "") | |
10815 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10816 | (match_operand 2 "" ""))) | |
10817 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10818 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10819 | (return)] |
10820 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10821 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10822 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
10823 | "* | |
10824 | { | |
10825 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10826 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10827 | ||
10828 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10829 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10830 | ||
10831 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\"; | |
10832 | }" | |
10833 | [(set_attr "type" "branch,branch") | |
10834 | (set_attr "length" "4,8")]) | |
10835 | ||
10836 | (define_expand "sibcall_epilogue" | |
10837 | [(use (const_int 0))] | |
10838 | "TARGET_SCHED_PROLOG" | |
10839 | " | |
10840 | { | |
10841 | rs6000_emit_epilogue (TRUE); | |
10842 | DONE; | |
10843 | }") | |
10844 | ||
e6f948e3 RK |
10845 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and |
10846 | ;; all of memory. This blocks insns from being moved across this point. | |
10847 | ||
10848 | (define_insn "blockage" | |
615158e2 | 10849 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)] |
e6f948e3 RK |
10850 | "" |
10851 | "") | |
1fd4e8c1 RK |
10852 | \f |
10853 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 10854 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
10855 | ;; |
10856 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
10857 | ;; insns, and branches. We store the operands of compares until we see | |
10858 | ;; how it is used. | |
10859 | (define_expand "cmpsi" | |
10860 | [(set (cc0) | |
cd2b37d9 | 10861 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10862 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
10863 | "" | |
10864 | " | |
10865 | { | |
10866 | /* Take care of the possibility that operands[1] might be negative but | |
10867 | this might be a logical operation. That insn doesn't exist. */ | |
10868 | if (GET_CODE (operands[1]) == CONST_INT | |
10869 | && INTVAL (operands[1]) < 0) | |
10870 | operands[1] = force_reg (SImode, operands[1]); | |
10871 | ||
10872 | rs6000_compare_op0 = operands[0]; | |
10873 | rs6000_compare_op1 = operands[1]; | |
10874 | rs6000_compare_fp_p = 0; | |
10875 | DONE; | |
10876 | }") | |
10877 | ||
266eb58a DE |
10878 | (define_expand "cmpdi" |
10879 | [(set (cc0) | |
10880 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
10881 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
10882 | "TARGET_POWERPC64" | |
10883 | " | |
10884 | { | |
10885 | /* Take care of the possibility that operands[1] might be negative but | |
10886 | this might be a logical operation. That insn doesn't exist. */ | |
10887 | if (GET_CODE (operands[1]) == CONST_INT | |
10888 | && INTVAL (operands[1]) < 0) | |
10889 | operands[1] = force_reg (DImode, operands[1]); | |
10890 | ||
10891 | rs6000_compare_op0 = operands[0]; | |
10892 | rs6000_compare_op1 = operands[1]; | |
10893 | rs6000_compare_fp_p = 0; | |
10894 | DONE; | |
10895 | }") | |
10896 | ||
1fd4e8c1 | 10897 | (define_expand "cmpsf" |
cd2b37d9 RK |
10898 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
10899 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 10900 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10901 | " |
10902 | { | |
10903 | rs6000_compare_op0 = operands[0]; | |
10904 | rs6000_compare_op1 = operands[1]; | |
10905 | rs6000_compare_fp_p = 1; | |
10906 | DONE; | |
10907 | }") | |
10908 | ||
10909 | (define_expand "cmpdf" | |
cd2b37d9 RK |
10910 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
10911 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 10912 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
10913 | " |
10914 | { | |
10915 | rs6000_compare_op0 = operands[0]; | |
10916 | rs6000_compare_op1 = operands[1]; | |
10917 | rs6000_compare_fp_p = 1; | |
10918 | DONE; | |
10919 | }") | |
10920 | ||
d6f99ca4 | 10921 | (define_expand "cmptf" |
e7a4130e DE |
10922 | [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "") |
10923 | (match_operand:TF 1 "gpc_reg_operand" "")))] | |
39e63627 GK |
10924 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
10925 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
d6f99ca4 DE |
10926 | " |
10927 | { | |
10928 | rs6000_compare_op0 = operands[0]; | |
10929 | rs6000_compare_op1 = operands[1]; | |
10930 | rs6000_compare_fp_p = 1; | |
10931 | DONE; | |
10932 | }") | |
10933 | ||
1fd4e8c1 | 10934 | (define_expand "beq" |
39a10a29 | 10935 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10936 | "" |
39a10a29 | 10937 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10938 | |
10939 | (define_expand "bne" | |
39a10a29 | 10940 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10941 | "" |
39a10a29 | 10942 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 10943 | |
39a10a29 GK |
10944 | (define_expand "bge" |
10945 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10946 | "" |
39a10a29 | 10947 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
10948 | |
10949 | (define_expand "bgt" | |
39a10a29 | 10950 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10951 | "" |
39a10a29 | 10952 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
10953 | |
10954 | (define_expand "ble" | |
39a10a29 | 10955 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10956 | "" |
39a10a29 | 10957 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 10958 | |
39a10a29 GK |
10959 | (define_expand "blt" |
10960 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10961 | "" |
39a10a29 | 10962 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 10963 | |
39a10a29 GK |
10964 | (define_expand "bgeu" |
10965 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10966 | "" |
39a10a29 | 10967 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 10968 | |
39a10a29 GK |
10969 | (define_expand "bgtu" |
10970 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10971 | "" |
39a10a29 | 10972 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 10973 | |
39a10a29 GK |
10974 | (define_expand "bleu" |
10975 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10976 | "" |
39a10a29 | 10977 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 10978 | |
39a10a29 GK |
10979 | (define_expand "bltu" |
10980 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10981 | "" |
39a10a29 | 10982 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 10983 | |
1c882ea4 | 10984 | (define_expand "bunordered" |
39a10a29 | 10985 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10986 | "" |
39a10a29 | 10987 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
10988 | |
10989 | (define_expand "bordered" | |
39a10a29 | 10990 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10991 | "" |
39a10a29 | 10992 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
10993 | |
10994 | (define_expand "buneq" | |
39a10a29 | 10995 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10996 | "" |
39a10a29 | 10997 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
10998 | |
10999 | (define_expand "bunge" | |
39a10a29 | 11000 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11001 | "" |
39a10a29 | 11002 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
11003 | |
11004 | (define_expand "bungt" | |
39a10a29 | 11005 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11006 | "" |
39a10a29 | 11007 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
11008 | |
11009 | (define_expand "bunle" | |
39a10a29 | 11010 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11011 | "" |
39a10a29 | 11012 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
11013 | |
11014 | (define_expand "bunlt" | |
39a10a29 | 11015 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11016 | "" |
39a10a29 | 11017 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
11018 | |
11019 | (define_expand "bltgt" | |
39a10a29 | 11020 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11021 | "" |
39a10a29 | 11022 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 11023 | |
1fd4e8c1 RK |
11024 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
11025 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
11026 | ;; with an scc insns. However, due to the order that combine see the | |
11027 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
11028 | ;; the cases we don't want to handle. | |
11029 | (define_expand "seq" | |
39a10a29 | 11030 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11031 | "" |
39a10a29 | 11032 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
11033 | |
11034 | (define_expand "sne" | |
39a10a29 | 11035 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11036 | "" |
11037 | " | |
6ae08853 | 11038 | { |
39a10a29 | 11039 | if (! rs6000_compare_fp_p) |
1fd4e8c1 RK |
11040 | FAIL; |
11041 | ||
6ae08853 | 11042 | rs6000_emit_sCOND (NE, operands[0]); |
39a10a29 | 11043 | DONE; |
1fd4e8c1 RK |
11044 | }") |
11045 | ||
b7053a3f GK |
11046 | ;; A >= 0 is best done the portable way for A an integer. |
11047 | (define_expand "sge" | |
39a10a29 | 11048 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11049 | "" |
11050 | " | |
5638268e DE |
11051 | { |
11052 | if (! rs6000_compare_fp_p | |
11053 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
11054 | FAIL; |
11055 | ||
b7053a3f | 11056 | rs6000_emit_sCOND (GE, operands[0]); |
39a10a29 | 11057 | DONE; |
1fd4e8c1 RK |
11058 | }") |
11059 | ||
b7053a3f GK |
11060 | ;; A > 0 is best done using the portable sequence, so fail in that case. |
11061 | (define_expand "sgt" | |
39a10a29 | 11062 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11063 | "" |
11064 | " | |
5638268e | 11065 | { |
b7053a3f | 11066 | if (! rs6000_compare_fp_p |
5638268e | 11067 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) |
1fd4e8c1 RK |
11068 | FAIL; |
11069 | ||
6ae08853 | 11070 | rs6000_emit_sCOND (GT, operands[0]); |
39a10a29 | 11071 | DONE; |
1fd4e8c1 RK |
11072 | }") |
11073 | ||
b7053a3f GK |
11074 | ;; A <= 0 is best done the portable way for A an integer. |
11075 | (define_expand "sle" | |
39a10a29 | 11076 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11077 | "" |
5638268e DE |
11078 | " |
11079 | { | |
11080 | if (! rs6000_compare_fp_p | |
11081 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
11082 | FAIL; | |
11083 | ||
6ae08853 | 11084 | rs6000_emit_sCOND (LE, operands[0]); |
5638268e DE |
11085 | DONE; |
11086 | }") | |
1fd4e8c1 | 11087 | |
b7053a3f GK |
11088 | ;; A < 0 is best done in the portable way for A an integer. |
11089 | (define_expand "slt" | |
39a10a29 | 11090 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11091 | "" |
11092 | " | |
5638268e | 11093 | { |
6ae08853 | 11094 | if (! rs6000_compare_fp_p |
5638268e | 11095 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) |
1fd4e8c1 RK |
11096 | FAIL; |
11097 | ||
6ae08853 | 11098 | rs6000_emit_sCOND (LT, operands[0]); |
39a10a29 | 11099 | DONE; |
1fd4e8c1 RK |
11100 | }") |
11101 | ||
b7053a3f GK |
11102 | (define_expand "sgeu" |
11103 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11104 | "" | |
11105 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") | |
11106 | ||
1fd4e8c1 | 11107 | (define_expand "sgtu" |
39a10a29 | 11108 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11109 | "" |
39a10a29 | 11110 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 11111 | |
b7053a3f GK |
11112 | (define_expand "sleu" |
11113 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11114 | "" | |
11115 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") | |
11116 | ||
1fd4e8c1 | 11117 | (define_expand "sltu" |
39a10a29 | 11118 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11119 | "" |
39a10a29 | 11120 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 11121 | |
b7053a3f | 11122 | (define_expand "sunordered" |
39a10a29 | 11123 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11124 | "" |
b7053a3f | 11125 | "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }") |
1fd4e8c1 | 11126 | |
b7053a3f | 11127 | (define_expand "sordered" |
39a10a29 | 11128 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11129 | "" |
b7053a3f GK |
11130 | "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }") |
11131 | ||
11132 | (define_expand "suneq" | |
11133 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11134 | "" | |
11135 | "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }") | |
11136 | ||
11137 | (define_expand "sunge" | |
11138 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11139 | "" | |
11140 | "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }") | |
11141 | ||
11142 | (define_expand "sungt" | |
11143 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11144 | "" | |
11145 | "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }") | |
11146 | ||
11147 | (define_expand "sunle" | |
11148 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11149 | "" | |
11150 | "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }") | |
11151 | ||
11152 | (define_expand "sunlt" | |
11153 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11154 | "" | |
11155 | "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }") | |
11156 | ||
11157 | (define_expand "sltgt" | |
11158 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11159 | "" | |
11160 | "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }") | |
11161 | ||
1fd4e8c1 RK |
11162 | \f |
11163 | ;; Here are the actual compare insns. | |
acad7ed3 | 11164 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 11165 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 11166 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
11167 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
11168 | "" | |
7f340546 | 11169 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
b54cf83a | 11170 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 11171 | |
acad7ed3 | 11172 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
11173 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
11174 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
11175 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
11176 | "TARGET_POWERPC64" | |
11177 | "cmpd%I2 %0,%1,%2" | |
b54cf83a | 11178 | [(set_attr "type" "cmp")]) |
266eb58a | 11179 | |
f357808b RK |
11180 | ;; If we are comparing a register for equality with a large constant, |
11181 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
11182 | ;; register for the result of the XOR. | |
11183 | ||
11184 | (define_split | |
11185 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 11186 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 11187 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 11188 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
11189 | "find_single_use (operands[0], insn, 0) |
11190 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
11191 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
11192 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
11193 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
11194 | " | |
11195 | { | |
11196 | /* Get the constant we are comparing against, C, and see what it looks like | |
11197 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
11198 | with C to get the sign-extended value. */ | |
11199 | ||
5f59ecb7 | 11200 | HOST_WIDE_INT c = INTVAL (operands[2]); |
a65c591c | 11201 | HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; |
5f59ecb7 | 11202 | HOST_WIDE_INT xorv = c ^ sextc; |
f357808b | 11203 | |
89e9f3a8 MM |
11204 | operands[4] = GEN_INT (xorv); |
11205 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
11206 | }") |
11207 | ||
acad7ed3 | 11208 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 11209 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 11210 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 11211 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 11212 | "" |
e2c953b6 | 11213 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
b54cf83a | 11214 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 11215 | |
acad7ed3 | 11216 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
11217 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
11218 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 11219 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 11220 | "" |
e2c953b6 | 11221 | "cmpld%I2 %0,%1,%b2" |
b54cf83a | 11222 | [(set_attr "type" "cmp")]) |
266eb58a | 11223 | |
1fd4e8c1 RK |
11224 | ;; The following two insns don't exist as single insns, but if we provide |
11225 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
11226 | ;; of the required delay between a compare and branch. We generate code for | |
11227 | ;; them by splitting. | |
11228 | ||
11229 | (define_insn "" | |
11230 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11231 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11232 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 11233 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11234 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11235 | "" | |
baf97f86 RK |
11236 | "#" |
11237 | [(set_attr "length" "8")]) | |
7e69e155 | 11238 | |
1fd4e8c1 RK |
11239 | (define_insn "" |
11240 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11241 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11242 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 11243 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11244 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11245 | "" | |
baf97f86 RK |
11246 | "#" |
11247 | [(set_attr "length" "8")]) | |
7e69e155 | 11248 | |
1fd4e8c1 RK |
11249 | (define_split |
11250 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 11251 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11252 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 11253 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11254 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11255 | "" | |
11256 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
11257 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11258 | ||
11259 | (define_split | |
11260 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 11261 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11262 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 11263 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11264 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11265 | "" | |
11266 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
11267 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11268 | ||
acad7ed3 | 11269 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 11270 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11271 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
11272 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11273 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11274 | "fcmpu %0,%1,%2" |
11275 | [(set_attr "type" "fpcompare")]) | |
11276 | ||
acad7ed3 | 11277 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 11278 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11279 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
11280 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11281 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11282 | "fcmpu %0,%1,%2" |
11283 | [(set_attr "type" "fpcompare")]) | |
d6f99ca4 DE |
11284 | |
11285 | ;; Only need to compare second words if first words equal | |
11286 | (define_insn "*cmptf_internal1" | |
11287 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
11288 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
11289 | (match_operand:TF 2 "gpc_reg_operand" "f")))] | |
39e63627 GK |
11290 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
11291 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 | 11292 | "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" |
d6f99ca4 DE |
11293 | [(set_attr "type" "fpcompare") |
11294 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
11295 | \f |
11296 | ;; Now we have the scc insns. We can do some combinations because of the | |
11297 | ;; way the machine works. | |
11298 | ;; | |
11299 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
11300 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
11301 | ;; cases the insns below which don't use an intermediate CR field will | |
11302 | ;; be used instead. | |
1fd4e8c1 | 11303 | (define_insn "" |
cd2b37d9 | 11304 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11305 | (match_operator:SI 1 "scc_comparison_operator" |
11306 | [(match_operand 2 "cc_reg_operand" "y") | |
11307 | (const_int 0)]))] | |
11308 | "" | |
2c4a9cff DE |
11309 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
11310 | [(set (attr "type") | |
11311 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11312 | (const_string "mfcrf") | |
11313 | ] | |
11314 | (const_string "mfcr"))) | |
309323c2 | 11315 | (set_attr "length" "12")]) |
1fd4e8c1 | 11316 | |
423c1189 AH |
11317 | ;; Same as above, but get the GT bit. |
11318 | (define_insn "move_from_CR_gt_bit" | |
11319 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
11320 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))] | |
11321 | "TARGET_E500" | |
11322 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1" | |
11323 | [(set_attr "type" "mfcr") | |
11324 | (set_attr "length" "12")]) | |
11325 | ||
a3170dc6 AH |
11326 | ;; Same as above, but get the OV/ORDERED bit. |
11327 | (define_insn "move_from_CR_ov_bit" | |
11328 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
615158e2 | 11329 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))] |
a3170dc6 | 11330 | "TARGET_ISEL" |
b7053a3f | 11331 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1" |
b54cf83a DE |
11332 | [(set_attr "type" "mfcr") |
11333 | (set_attr "length" "12")]) | |
a3170dc6 | 11334 | |
1fd4e8c1 | 11335 | (define_insn "" |
9ebbca7d GK |
11336 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
11337 | (match_operator:DI 1 "scc_comparison_operator" | |
11338 | [(match_operand 2 "cc_reg_operand" "y") | |
11339 | (const_int 0)]))] | |
11340 | "TARGET_POWERPC64" | |
2c4a9cff DE |
11341 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
11342 | [(set (attr "type") | |
11343 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11344 | (const_string "mfcrf") | |
11345 | ] | |
11346 | (const_string "mfcr"))) | |
309323c2 | 11347 | (set_attr "length" "12")]) |
9ebbca7d GK |
11348 | |
11349 | (define_insn "" | |
11350 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 11351 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 11352 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
11353 | (const_int 0)]) |
11354 | (const_int 0))) | |
9ebbca7d | 11355 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11356 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
4b8a63d6 | 11357 | "TARGET_32BIT" |
9ebbca7d | 11358 | "@ |
2c4a9cff | 11359 | mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1 |
9ebbca7d | 11360 | #" |
b19003d8 | 11361 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11362 | (set_attr "length" "12,16")]) |
11363 | ||
11364 | (define_split | |
11365 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11366 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
11367 | [(match_operand 2 "cc_reg_operand" "") | |
11368 | (const_int 0)]) | |
11369 | (const_int 0))) | |
11370 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
11371 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
4b8a63d6 | 11372 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11373 | [(set (match_dup 3) |
11374 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
11375 | (set (match_dup 0) | |
11376 | (compare:CC (match_dup 3) | |
11377 | (const_int 0)))] | |
11378 | "") | |
1fd4e8c1 RK |
11379 | |
11380 | (define_insn "" | |
cd2b37d9 | 11381 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11382 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
11383 | [(match_operand 2 "cc_reg_operand" "y") | |
11384 | (const_int 0)]) | |
11385 | (match_operand:SI 3 "const_int_operand" "n")))] | |
11386 | "" | |
11387 | "* | |
11388 | { | |
11389 | int is_bit = ccr_bit (operands[1], 1); | |
11390 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11391 | int count; | |
11392 | ||
11393 | if (is_bit >= put_bit) | |
11394 | count = is_bit - put_bit; | |
11395 | else | |
11396 | count = 32 - (put_bit - is_bit); | |
11397 | ||
89e9f3a8 MM |
11398 | operands[4] = GEN_INT (count); |
11399 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 11400 | |
2c4a9cff | 11401 | return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 | 11402 | }" |
2c4a9cff DE |
11403 | [(set (attr "type") |
11404 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11405 | (const_string "mfcrf") | |
11406 | ] | |
11407 | (const_string "mfcr"))) | |
309323c2 | 11408 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
11409 | |
11410 | (define_insn "" | |
9ebbca7d | 11411 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11412 | (compare:CC |
11413 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 11414 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 11415 | (const_int 0)]) |
9ebbca7d | 11416 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 11417 | (const_int 0))) |
9ebbca7d | 11418 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11419 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
11420 | (match_dup 3)))] | |
ce71f754 | 11421 | "" |
1fd4e8c1 RK |
11422 | "* |
11423 | { | |
11424 | int is_bit = ccr_bit (operands[1], 1); | |
11425 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11426 | int count; | |
11427 | ||
9ebbca7d GK |
11428 | /* Force split for non-cc0 compare. */ |
11429 | if (which_alternative == 1) | |
11430 | return \"#\"; | |
11431 | ||
1fd4e8c1 RK |
11432 | if (is_bit >= put_bit) |
11433 | count = is_bit - put_bit; | |
11434 | else | |
11435 | count = 32 - (put_bit - is_bit); | |
11436 | ||
89e9f3a8 MM |
11437 | operands[5] = GEN_INT (count); |
11438 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 11439 | |
2c4a9cff | 11440 | return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 11441 | }" |
b19003d8 | 11442 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11443 | (set_attr "length" "12,16")]) |
11444 | ||
11445 | (define_split | |
11446 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11447 | (compare:CC | |
11448 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
11449 | [(match_operand 2 "cc_reg_operand" "") | |
11450 | (const_int 0)]) | |
11451 | (match_operand:SI 3 "const_int_operand" "")) | |
11452 | (const_int 0))) | |
11453 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
11454 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11455 | (match_dup 3)))] | |
ce71f754 | 11456 | "reload_completed" |
9ebbca7d GK |
11457 | [(set (match_dup 4) |
11458 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11459 | (match_dup 3))) | |
11460 | (set (match_dup 0) | |
11461 | (compare:CC (match_dup 4) | |
11462 | (const_int 0)))] | |
11463 | "") | |
1fd4e8c1 | 11464 | |
c5defebb RK |
11465 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
11466 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
11467 | ||
11468 | (define_peephole | |
cd2b37d9 | 11469 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
11470 | (match_operator:SI 1 "scc_comparison_operator" |
11471 | [(match_operand 2 "cc_reg_operand" "y") | |
11472 | (const_int 0)])) | |
cd2b37d9 | 11473 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
11474 | (match_operator:SI 4 "scc_comparison_operator" |
11475 | [(match_operand 5 "cc_reg_operand" "y") | |
11476 | (const_int 0)]))] | |
309323c2 | 11477 | "REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11478 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11479 | [(set_attr "type" "mfcr") |
309323c2 | 11480 | (set_attr "length" "20")]) |
c5defebb | 11481 | |
9ebbca7d GK |
11482 | (define_peephole |
11483 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11484 | (match_operator:DI 1 "scc_comparison_operator" | |
11485 | [(match_operand 2 "cc_reg_operand" "y") | |
11486 | (const_int 0)])) | |
11487 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
11488 | (match_operator:DI 4 "scc_comparison_operator" | |
11489 | [(match_operand 5 "cc_reg_operand" "y") | |
11490 | (const_int 0)]))] | |
309323c2 | 11491 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11492 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11493 | [(set_attr "type" "mfcr") |
309323c2 | 11494 | (set_attr "length" "20")]) |
9ebbca7d | 11495 | |
1fd4e8c1 RK |
11496 | ;; There are some scc insns that can be done directly, without a compare. |
11497 | ;; These are faster because they don't involve the communications between | |
11498 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
11499 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
11500 | ;; | |
11501 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
11502 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
11503 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
11504 | ;; cases where it is no more expensive than (neg (scc ..)). | |
11505 | ||
11506 | ;; Have reload force a constant into a register for the simple insns that | |
11507 | ;; otherwise won't accept constants. We do this because it is faster than | |
11508 | ;; the cmp/mfcr sequence we would otherwise generate. | |
11509 | ||
11510 | (define_insn "" | |
cd2b37d9 RK |
11511 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
11512 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 11513 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 11514 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
683bdff7 | 11515 | "TARGET_32BIT" |
1fd4e8c1 | 11516 | "@ |
ca7f5001 | 11517 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 11518 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
11519 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
11520 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
11521 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 11522 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 11523 | |
a260abc9 DE |
11524 | (define_insn "" |
11525 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
11526 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
11527 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
11528 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
683bdff7 | 11529 | "TARGET_64BIT" |
a260abc9 DE |
11530 | "@ |
11531 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11532 | subfic %3,%1,0\;adde %0,%3,%1 | |
11533 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11534 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11535 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
11536 | [(set_attr "length" "12,8,12,12,12")]) | |
11537 | ||
1fd4e8c1 | 11538 | (define_insn "" |
9ebbca7d | 11539 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11540 | (compare:CC |
9ebbca7d GK |
11541 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11542 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 11543 | (const_int 0))) |
9ebbca7d | 11544 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 11545 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11546 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
683bdff7 | 11547 | "TARGET_32BIT" |
1fd4e8c1 | 11548 | "@ |
ca7f5001 RK |
11549 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11550 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
11551 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
11552 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
11553 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11554 | # | |
11555 | # | |
11556 | # | |
11557 | # | |
11558 | #" | |
b19003d8 | 11559 | [(set_attr "type" "compare") |
9ebbca7d GK |
11560 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11561 | ||
11562 | (define_split | |
11563 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11564 | (compare:CC | |
11565 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11566 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11567 | (const_int 0))) | |
11568 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11569 | (eq:SI (match_dup 1) (match_dup 2))) | |
11570 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 11571 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11572 | [(parallel [(set (match_dup 0) |
11573 | (eq:SI (match_dup 1) (match_dup 2))) | |
11574 | (clobber (match_dup 3))]) | |
11575 | (set (match_dup 4) | |
11576 | (compare:CC (match_dup 0) | |
11577 | (const_int 0)))] | |
11578 | "") | |
b19003d8 | 11579 | |
a260abc9 | 11580 | (define_insn "" |
9ebbca7d | 11581 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 11582 | (compare:CC |
9ebbca7d GK |
11583 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11584 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 11585 | (const_int 0))) |
9ebbca7d | 11586 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 11587 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11588 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
683bdff7 | 11589 | "TARGET_64BIT" |
a260abc9 DE |
11590 | "@ |
11591 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11592 | subfic %3,%1,0\;adde. %0,%3,%1 | |
11593 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11594 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
11595 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
11596 | # | |
11597 | # | |
11598 | # | |
11599 | # | |
11600 | #" | |
a260abc9 | 11601 | [(set_attr "type" "compare") |
9ebbca7d GK |
11602 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11603 | ||
11604 | (define_split | |
11605 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11606 | (compare:CC | |
11607 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11608 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
11609 | (const_int 0))) | |
11610 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11611 | (eq:DI (match_dup 1) (match_dup 2))) | |
11612 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11613 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11614 | [(parallel [(set (match_dup 0) |
11615 | (eq:DI (match_dup 1) (match_dup 2))) | |
11616 | (clobber (match_dup 3))]) | |
11617 | (set (match_dup 4) | |
11618 | (compare:CC (match_dup 0) | |
11619 | (const_int 0)))] | |
11620 | "") | |
a260abc9 | 11621 | |
b19003d8 RK |
11622 | ;; We have insns of the form shown by the first define_insn below. If |
11623 | ;; there is something inside the comparison operation, we must split it. | |
11624 | (define_split | |
11625 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
11626 | (plus:SI (match_operator 1 "comparison_operator" | |
11627 | [(match_operand:SI 2 "" "") | |
11628 | (match_operand:SI 3 | |
11629 | "reg_or_cint_operand" "")]) | |
11630 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
11631 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
11632 | "! gpc_reg_operand (operands[2], SImode)" | |
11633 | [(set (match_dup 5) (match_dup 2)) | |
11634 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
11635 | (match_dup 4)))]) | |
1fd4e8c1 RK |
11636 | |
11637 | (define_insn "" | |
5276df18 | 11638 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") |
cd2b37d9 | 11639 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11640 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
5276df18 | 11641 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] |
683bdff7 | 11642 | "TARGET_32BIT" |
1fd4e8c1 | 11643 | "@ |
5276df18 DE |
11644 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11645 | {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 | |
11646 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11647 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11648 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" | |
b19003d8 | 11649 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
11650 | |
11651 | (define_insn "" | |
9ebbca7d | 11652 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11653 | (compare:CC |
1fd4e8c1 | 11654 | (plus:SI |
9ebbca7d GK |
11655 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11656 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11657 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11658 | (const_int 0))) |
9ebbca7d | 11659 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
683bdff7 | 11660 | "TARGET_32BIT" |
1fd4e8c1 | 11661 | "@ |
ca7f5001 | 11662 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 11663 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
11664 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11665 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
11666 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11667 | # | |
11668 | # | |
11669 | # | |
11670 | # | |
11671 | #" | |
b19003d8 | 11672 | [(set_attr "type" "compare") |
9ebbca7d GK |
11673 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11674 | ||
11675 | (define_split | |
11676 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11677 | (compare:CC | |
11678 | (plus:SI | |
11679 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11680 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11681 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11682 | (const_int 0))) | |
11683 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11684 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11685 | [(set (match_dup 4) |
11686 | (plus:SI (eq:SI (match_dup 1) | |
11687 | (match_dup 2)) | |
11688 | (match_dup 3))) | |
11689 | (set (match_dup 0) | |
11690 | (compare:CC (match_dup 4) | |
11691 | (const_int 0)))] | |
11692 | "") | |
1fd4e8c1 RK |
11693 | |
11694 | (define_insn "" | |
0387639b | 11695 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11696 | (compare:CC |
1fd4e8c1 | 11697 | (plus:SI |
9ebbca7d GK |
11698 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11699 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11700 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11701 | (const_int 0))) |
0387639b DE |
11702 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") |
11703 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 11704 | "TARGET_32BIT" |
1fd4e8c1 | 11705 | "@ |
0387639b DE |
11706 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11707 | {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 | |
11708 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11709 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11710 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11711 | # |
11712 | # | |
11713 | # | |
11714 | # | |
11715 | #" | |
11716 | [(set_attr "type" "compare") | |
11717 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
11718 | ||
11719 | (define_split | |
0387639b | 11720 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11721 | (compare:CC |
11722 | (plus:SI | |
11723 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11724 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11725 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11726 | (const_int 0))) | |
11727 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
0387639b | 11728 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 11729 | "TARGET_32BIT && reload_completed" |
0387639b | 11730 | [(set (match_dup 0) |
9ebbca7d | 11731 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
0387639b | 11732 | (set (match_dup 4) |
9ebbca7d GK |
11733 | (compare:CC (match_dup 0) |
11734 | (const_int 0)))] | |
11735 | "") | |
11736 | ||
1fd4e8c1 | 11737 | (define_insn "" |
cd2b37d9 | 11738 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 11739 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11740 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
683bdff7 | 11741 | "TARGET_32BIT" |
1fd4e8c1 | 11742 | "@ |
ca7f5001 RK |
11743 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11744 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
11745 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11746 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11747 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11748 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 11749 | |
ea9be077 MM |
11750 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
11751 | ;; since it nabs/sr is just as fast. | |
463b558b | 11752 | (define_insn "*ne0" |
b4e95693 | 11753 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
11754 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
11755 | (const_int 31))) | |
11756 | (clobber (match_scratch:SI 2 "=&r"))] | |
683bdff7 | 11757 | "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL" |
ea9be077 MM |
11758 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
11759 | [(set_attr "length" "8")]) | |
11760 | ||
a260abc9 DE |
11761 | (define_insn "" |
11762 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11763 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11764 | (const_int 63))) | |
11765 | (clobber (match_scratch:DI 2 "=&r"))] | |
683bdff7 | 11766 | "TARGET_64BIT" |
a260abc9 DE |
11767 | "addic %2,%1,-1\;subfe %0,%2,%1" |
11768 | [(set_attr "length" "8")]) | |
11769 | ||
1fd4e8c1 RK |
11770 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
11771 | (define_insn "" | |
cd2b37d9 | 11772 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 11773 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 11774 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11775 | (const_int 31)) |
cd2b37d9 | 11776 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11777 | (clobber (match_scratch:SI 3 "=&r"))] |
683bdff7 | 11778 | "TARGET_32BIT" |
ca7f5001 | 11779 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 11780 | [(set_attr "length" "8")]) |
1fd4e8c1 | 11781 | |
a260abc9 DE |
11782 | (define_insn "" |
11783 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11784 | (plus:DI (lshiftrt:DI | |
11785 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11786 | (const_int 63)) | |
11787 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11788 | (clobber (match_scratch:DI 3 "=&r"))] | |
683bdff7 | 11789 | "TARGET_64BIT" |
a260abc9 DE |
11790 | "addic %3,%1,-1\;addze %0,%2" |
11791 | [(set_attr "length" "8")]) | |
11792 | ||
1fd4e8c1 | 11793 | (define_insn "" |
9ebbca7d | 11794 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11795 | (compare:CC |
11796 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11797 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11798 | (const_int 31)) |
9ebbca7d | 11799 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11800 | (const_int 0))) |
889b90a1 GK |
11801 | (clobber (match_scratch:SI 3 "=&r,&r")) |
11802 | (clobber (match_scratch:SI 4 "=X,&r"))] | |
683bdff7 | 11803 | "TARGET_32BIT" |
9ebbca7d GK |
11804 | "@ |
11805 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
11806 | #" | |
b19003d8 | 11807 | [(set_attr "type" "compare") |
9ebbca7d GK |
11808 | (set_attr "length" "8,12")]) |
11809 | ||
11810 | (define_split | |
11811 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11812 | (compare:CC | |
11813 | (plus:SI (lshiftrt:SI | |
11814 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11815 | (const_int 31)) | |
11816 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11817 | (const_int 0))) | |
889b90a1 GK |
11818 | (clobber (match_scratch:SI 3 "")) |
11819 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11820 | "TARGET_32BIT && reload_completed" |
889b90a1 | 11821 | [(parallel [(set (match_dup 3) |
ce71f754 AM |
11822 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) |
11823 | (const_int 31)) | |
11824 | (match_dup 2))) | |
889b90a1 | 11825 | (clobber (match_dup 4))]) |
9ebbca7d GK |
11826 | (set (match_dup 0) |
11827 | (compare:CC (match_dup 3) | |
11828 | (const_int 0)))] | |
11829 | "") | |
1fd4e8c1 | 11830 | |
a260abc9 | 11831 | (define_insn "" |
9ebbca7d | 11832 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11833 | (compare:CC |
11834 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11835 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11836 | (const_int 63)) |
9ebbca7d | 11837 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11838 | (const_int 0))) |
9ebbca7d | 11839 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 11840 | "TARGET_64BIT" |
9ebbca7d GK |
11841 | "@ |
11842 | addic %3,%1,-1\;addze. %3,%2 | |
11843 | #" | |
a260abc9 | 11844 | [(set_attr "type" "compare") |
9ebbca7d GK |
11845 | (set_attr "length" "8,12")]) |
11846 | ||
11847 | (define_split | |
11848 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11849 | (compare:CC | |
11850 | (plus:DI (lshiftrt:DI | |
11851 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11852 | (const_int 63)) | |
11853 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11854 | (const_int 0))) | |
11855 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11856 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11857 | [(set (match_dup 3) |
11858 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
11859 | (const_int 63)) | |
11860 | (match_dup 2))) | |
11861 | (set (match_dup 0) | |
11862 | (compare:CC (match_dup 3) | |
11863 | (const_int 0)))] | |
11864 | "") | |
a260abc9 | 11865 | |
1fd4e8c1 | 11866 | (define_insn "" |
9ebbca7d | 11867 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11868 | (compare:CC |
11869 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11870 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11871 | (const_int 31)) |
9ebbca7d | 11872 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11873 | (const_int 0))) |
9ebbca7d | 11874 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11875 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
11876 | (match_dup 2))) | |
9ebbca7d | 11877 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 11878 | "TARGET_32BIT" |
9ebbca7d GK |
11879 | "@ |
11880 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
11881 | #" | |
b19003d8 | 11882 | [(set_attr "type" "compare") |
9ebbca7d GK |
11883 | (set_attr "length" "8,12")]) |
11884 | ||
11885 | (define_split | |
11886 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11887 | (compare:CC | |
11888 | (plus:SI (lshiftrt:SI | |
11889 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11890 | (const_int 31)) | |
11891 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11892 | (const_int 0))) | |
11893 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11894 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11895 | (match_dup 2))) | |
11896 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 11897 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11898 | [(parallel [(set (match_dup 0) |
11899 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11900 | (match_dup 2))) | |
11901 | (clobber (match_dup 3))]) | |
11902 | (set (match_dup 4) | |
11903 | (compare:CC (match_dup 0) | |
11904 | (const_int 0)))] | |
11905 | "") | |
1fd4e8c1 | 11906 | |
a260abc9 | 11907 | (define_insn "" |
9ebbca7d | 11908 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11909 | (compare:CC |
11910 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11911 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11912 | (const_int 63)) |
9ebbca7d | 11913 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11914 | (const_int 0))) |
9ebbca7d | 11915 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
11916 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
11917 | (match_dup 2))) | |
9ebbca7d | 11918 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 11919 | "TARGET_64BIT" |
9ebbca7d GK |
11920 | "@ |
11921 | addic %3,%1,-1\;addze. %0,%2 | |
11922 | #" | |
a260abc9 | 11923 | [(set_attr "type" "compare") |
9ebbca7d GK |
11924 | (set_attr "length" "8,12")]) |
11925 | ||
11926 | (define_split | |
11927 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11928 | (compare:CC | |
11929 | (plus:DI (lshiftrt:DI | |
11930 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11931 | (const_int 63)) | |
11932 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11933 | (const_int 0))) | |
11934 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11935 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11936 | (match_dup 2))) | |
11937 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11938 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11939 | [(parallel [(set (match_dup 0) |
11940 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11941 | (match_dup 2))) | |
11942 | (clobber (match_dup 3))]) | |
11943 | (set (match_dup 4) | |
11944 | (compare:CC (match_dup 0) | |
11945 | (const_int 0)))] | |
11946 | "") | |
a260abc9 | 11947 | |
1fd4e8c1 | 11948 | (define_insn "" |
cd2b37d9 RK |
11949 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11950 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
11951 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
11952 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 11953 | "TARGET_POWER" |
1fd4e8c1 | 11954 | "@ |
ca7f5001 | 11955 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 11956 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11957 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11958 | |
11959 | (define_insn "" | |
9ebbca7d | 11960 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11961 | (compare:CC |
9ebbca7d GK |
11962 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11963 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 11964 | (const_int 0))) |
9ebbca7d | 11965 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11966 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11967 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 11968 | "TARGET_POWER" |
1fd4e8c1 | 11969 | "@ |
ca7f5001 | 11970 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
11971 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
11972 | # | |
11973 | #" | |
11974 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
11975 | (set_attr "length" "12,12,16,16")]) | |
11976 | ||
11977 | (define_split | |
11978 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11979 | (compare:CC | |
11980 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11981 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11982 | (const_int 0))) | |
11983 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11984 | (le:SI (match_dup 1) (match_dup 2))) | |
11985 | (clobber (match_scratch:SI 3 ""))] | |
11986 | "TARGET_POWER && reload_completed" | |
11987 | [(parallel [(set (match_dup 0) | |
11988 | (le:SI (match_dup 1) (match_dup 2))) | |
11989 | (clobber (match_dup 3))]) | |
11990 | (set (match_dup 4) | |
11991 | (compare:CC (match_dup 0) | |
11992 | (const_int 0)))] | |
11993 | "") | |
1fd4e8c1 RK |
11994 | |
11995 | (define_insn "" | |
097657c3 | 11996 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 11997 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 11998 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
097657c3 | 11999 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
ca7f5001 | 12000 | "TARGET_POWER" |
1fd4e8c1 | 12001 | "@ |
097657c3 AM |
12002 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
12003 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" | |
b19003d8 | 12004 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12005 | |
12006 | (define_insn "" | |
9ebbca7d | 12007 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12008 | (compare:CC |
9ebbca7d GK |
12009 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12010 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
12011 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12012 | (const_int 0))) |
9ebbca7d | 12013 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 12014 | "TARGET_POWER" |
1fd4e8c1 | 12015 | "@ |
ca7f5001 | 12016 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12017 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
12018 | # | |
12019 | #" | |
b19003d8 | 12020 | [(set_attr "type" "compare") |
9ebbca7d GK |
12021 | (set_attr "length" "12,12,16,16")]) |
12022 | ||
12023 | (define_split | |
12024 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12025 | (compare:CC | |
12026 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12027 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12028 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12029 | (const_int 0))) | |
12030 | (clobber (match_scratch:SI 4 ""))] | |
12031 | "TARGET_POWER && reload_completed" | |
12032 | [(set (match_dup 4) | |
12033 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12034 | (match_dup 3))) |
9ebbca7d GK |
12035 | (set (match_dup 0) |
12036 | (compare:CC (match_dup 4) | |
12037 | (const_int 0)))] | |
12038 | "") | |
1fd4e8c1 RK |
12039 | |
12040 | (define_insn "" | |
097657c3 | 12041 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12042 | (compare:CC |
9ebbca7d GK |
12043 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12044 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
12045 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12046 | (const_int 0))) |
097657c3 AM |
12047 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12048 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12049 | "TARGET_POWER" |
1fd4e8c1 | 12050 | "@ |
097657c3 AM |
12051 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
12052 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12053 | # |
12054 | #" | |
b19003d8 | 12055 | [(set_attr "type" "compare") |
9ebbca7d GK |
12056 | (set_attr "length" "12,12,16,16")]) |
12057 | ||
12058 | (define_split | |
097657c3 | 12059 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12060 | (compare:CC |
12061 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12062 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12063 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12064 | (const_int 0))) | |
12065 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12066 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12067 | "TARGET_POWER && reload_completed" |
097657c3 | 12068 | [(set (match_dup 0) |
9ebbca7d | 12069 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12070 | (set (match_dup 4) |
9ebbca7d GK |
12071 | (compare:CC (match_dup 0) |
12072 | (const_int 0)))] | |
12073 | "") | |
1fd4e8c1 RK |
12074 | |
12075 | (define_insn "" | |
cd2b37d9 RK |
12076 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12077 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12078 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 12079 | "TARGET_POWER" |
1fd4e8c1 | 12080 | "@ |
ca7f5001 RK |
12081 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
12082 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12083 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12084 | |
12085 | (define_insn "" | |
cd2b37d9 RK |
12086 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12087 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12088 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
4b8a63d6 | 12089 | "TARGET_32BIT" |
ca7f5001 | 12090 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 12091 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12092 | |
f9562f27 DE |
12093 | (define_insn "" |
12094 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12095 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12096 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 12097 | "TARGET_64BIT" |
f9562f27 DE |
12098 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" |
12099 | [(set_attr "length" "12")]) | |
12100 | ||
12101 | (define_insn "" | |
9ebbca7d | 12102 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12103 | (compare:CC |
9ebbca7d GK |
12104 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12105 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 12106 | (const_int 0))) |
9ebbca7d | 12107 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 12108 | (leu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12109 | "TARGET_64BIT" |
9ebbca7d GK |
12110 | "@ |
12111 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
12112 | #" | |
f9562f27 | 12113 | [(set_attr "type" "compare") |
9ebbca7d GK |
12114 | (set_attr "length" "12,16")]) |
12115 | ||
12116 | (define_split | |
12117 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12118 | (compare:CC | |
12119 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12120 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12121 | (const_int 0))) | |
12122 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12123 | (leu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12124 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12125 | [(set (match_dup 0) |
12126 | (leu:DI (match_dup 1) (match_dup 2))) | |
12127 | (set (match_dup 3) | |
12128 | (compare:CC (match_dup 0) | |
12129 | (const_int 0)))] | |
12130 | "") | |
f9562f27 | 12131 | |
1fd4e8c1 | 12132 | (define_insn "" |
9ebbca7d | 12133 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12134 | (compare:CC |
9ebbca7d GK |
12135 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12136 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12137 | (const_int 0))) |
9ebbca7d | 12138 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12139 | (leu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12140 | "TARGET_32BIT" |
9ebbca7d GK |
12141 | "@ |
12142 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
12143 | #" | |
b19003d8 | 12144 | [(set_attr "type" "compare") |
9ebbca7d GK |
12145 | (set_attr "length" "12,16")]) |
12146 | ||
12147 | (define_split | |
12148 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12149 | (compare:CC | |
12150 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12151 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12152 | (const_int 0))) | |
12153 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12154 | (leu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12155 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12156 | [(set (match_dup 0) |
12157 | (leu:SI (match_dup 1) (match_dup 2))) | |
12158 | (set (match_dup 3) | |
12159 | (compare:CC (match_dup 0) | |
12160 | (const_int 0)))] | |
12161 | "") | |
1fd4e8c1 RK |
12162 | |
12163 | (define_insn "" | |
80103f96 | 12164 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12165 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12166 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
80103f96 | 12167 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
683bdff7 | 12168 | "TARGET_32BIT" |
80103f96 | 12169 | "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 12170 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12171 | |
12172 | (define_insn "" | |
9ebbca7d | 12173 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12174 | (compare:CC |
9ebbca7d GK |
12175 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12176 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12177 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12178 | (const_int 0))) |
9ebbca7d | 12179 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 12180 | "TARGET_32BIT" |
9ebbca7d GK |
12181 | "@ |
12182 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
12183 | #" | |
b19003d8 | 12184 | [(set_attr "type" "compare") |
9ebbca7d GK |
12185 | (set_attr "length" "8,12")]) |
12186 | ||
12187 | (define_split | |
12188 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12189 | (compare:CC | |
12190 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12191 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12192 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12193 | (const_int 0))) | |
12194 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12195 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12196 | [(set (match_dup 4) |
12197 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
12198 | (match_dup 3))) | |
12199 | (set (match_dup 0) | |
12200 | (compare:CC (match_dup 4) | |
12201 | (const_int 0)))] | |
12202 | "") | |
1fd4e8c1 RK |
12203 | |
12204 | (define_insn "" | |
097657c3 | 12205 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12206 | (compare:CC |
9ebbca7d GK |
12207 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12208 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12209 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12210 | (const_int 0))) |
097657c3 AM |
12211 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12212 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12213 | "TARGET_32BIT" |
9ebbca7d | 12214 | "@ |
097657c3 | 12215 | {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 |
9ebbca7d | 12216 | #" |
b19003d8 | 12217 | [(set_attr "type" "compare") |
9ebbca7d GK |
12218 | (set_attr "length" "8,12")]) |
12219 | ||
12220 | (define_split | |
097657c3 | 12221 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12222 | (compare:CC |
12223 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12224 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12225 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12226 | (const_int 0))) | |
12227 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12228 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12229 | "TARGET_32BIT && reload_completed" |
097657c3 | 12230 | [(set (match_dup 0) |
9ebbca7d | 12231 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12232 | (set (match_dup 4) |
9ebbca7d GK |
12233 | (compare:CC (match_dup 0) |
12234 | (const_int 0)))] | |
12235 | "") | |
1fd4e8c1 RK |
12236 | |
12237 | (define_insn "" | |
cd2b37d9 RK |
12238 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12239 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12240 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
683bdff7 | 12241 | "TARGET_32BIT" |
ca7f5001 | 12242 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 12243 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12244 | |
12245 | (define_insn "" | |
097657c3 | 12246 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
1fd4e8c1 | 12247 | (and:SI (neg:SI |
cd2b37d9 | 12248 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12249 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
097657c3 | 12250 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
683bdff7 | 12251 | "TARGET_32BIT" |
097657c3 | 12252 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" |
b19003d8 | 12253 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12254 | |
12255 | (define_insn "" | |
9ebbca7d | 12256 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12257 | (compare:CC |
12258 | (and:SI (neg:SI | |
9ebbca7d GK |
12259 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12260 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12261 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12262 | (const_int 0))) |
9ebbca7d | 12263 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 12264 | "TARGET_32BIT" |
9ebbca7d GK |
12265 | "@ |
12266 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
12267 | #" | |
12268 | [(set_attr "type" "compare") | |
12269 | (set_attr "length" "12,16")]) | |
12270 | ||
12271 | (define_split | |
12272 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12273 | (compare:CC | |
12274 | (and:SI (neg:SI | |
12275 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12276 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12277 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12278 | (const_int 0))) | |
12279 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12280 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 12281 | [(set (match_dup 4) |
097657c3 AM |
12282 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) |
12283 | (match_dup 3))) | |
9ebbca7d GK |
12284 | (set (match_dup 0) |
12285 | (compare:CC (match_dup 4) | |
12286 | (const_int 0)))] | |
12287 | "") | |
1fd4e8c1 RK |
12288 | |
12289 | (define_insn "" | |
097657c3 | 12290 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12291 | (compare:CC |
12292 | (and:SI (neg:SI | |
9ebbca7d GK |
12293 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12294 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12295 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12296 | (const_int 0))) |
097657c3 AM |
12297 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12298 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 12299 | "TARGET_32BIT" |
9ebbca7d | 12300 | "@ |
097657c3 | 12301 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
9ebbca7d | 12302 | #" |
b19003d8 | 12303 | [(set_attr "type" "compare") |
9ebbca7d GK |
12304 | (set_attr "length" "12,16")]) |
12305 | ||
12306 | (define_split | |
097657c3 | 12307 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12308 | (compare:CC |
12309 | (and:SI (neg:SI | |
12310 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12311 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12312 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12313 | (const_int 0))) | |
12314 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12315 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 12316 | "TARGET_32BIT && reload_completed" |
097657c3 AM |
12317 | [(set (match_dup 0) |
12318 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) | |
12319 | (match_dup 3))) | |
12320 | (set (match_dup 4) | |
9ebbca7d GK |
12321 | (compare:CC (match_dup 0) |
12322 | (const_int 0)))] | |
12323 | "") | |
1fd4e8c1 RK |
12324 | |
12325 | (define_insn "" | |
cd2b37d9 RK |
12326 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12327 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12328 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 12329 | "TARGET_POWER" |
7f340546 | 12330 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12331 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12332 | |
12333 | (define_insn "" | |
9ebbca7d | 12334 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12335 | (compare:CC |
9ebbca7d GK |
12336 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12337 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12338 | (const_int 0))) |
9ebbca7d | 12339 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12340 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12341 | "TARGET_POWER" |
9ebbca7d GK |
12342 | "@ |
12343 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12344 | #" | |
29ae5b89 | 12345 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12346 | (set_attr "length" "12,16")]) |
12347 | ||
12348 | (define_split | |
12349 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12350 | (compare:CC | |
12351 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12352 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12353 | (const_int 0))) | |
12354 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12355 | (lt:SI (match_dup 1) (match_dup 2)))] | |
12356 | "TARGET_POWER && reload_completed" | |
12357 | [(set (match_dup 0) | |
12358 | (lt:SI (match_dup 1) (match_dup 2))) | |
12359 | (set (match_dup 3) | |
12360 | (compare:CC (match_dup 0) | |
12361 | (const_int 0)))] | |
12362 | "") | |
1fd4e8c1 RK |
12363 | |
12364 | (define_insn "" | |
097657c3 | 12365 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12366 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12367 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12368 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12369 | "TARGET_POWER" |
097657c3 | 12370 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 12371 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12372 | |
12373 | (define_insn "" | |
9ebbca7d | 12374 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12375 | (compare:CC |
9ebbca7d GK |
12376 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12377 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12378 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12379 | (const_int 0))) |
9ebbca7d | 12380 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12381 | "TARGET_POWER" |
9ebbca7d GK |
12382 | "@ |
12383 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12384 | #" | |
b19003d8 | 12385 | [(set_attr "type" "compare") |
9ebbca7d GK |
12386 | (set_attr "length" "12,16")]) |
12387 | ||
12388 | (define_split | |
12389 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12390 | (compare:CC | |
12391 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12392 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12393 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12394 | (const_int 0))) | |
12395 | (clobber (match_scratch:SI 4 ""))] | |
12396 | "TARGET_POWER && reload_completed" | |
12397 | [(set (match_dup 4) | |
12398 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12399 | (match_dup 3))) |
9ebbca7d GK |
12400 | (set (match_dup 0) |
12401 | (compare:CC (match_dup 4) | |
12402 | (const_int 0)))] | |
12403 | "") | |
1fd4e8c1 RK |
12404 | |
12405 | (define_insn "" | |
097657c3 | 12406 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12407 | (compare:CC |
9ebbca7d GK |
12408 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12409 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12410 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12411 | (const_int 0))) |
097657c3 AM |
12412 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12413 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12414 | "TARGET_POWER" |
9ebbca7d | 12415 | "@ |
097657c3 | 12416 | doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 12417 | #" |
b19003d8 | 12418 | [(set_attr "type" "compare") |
9ebbca7d GK |
12419 | (set_attr "length" "12,16")]) |
12420 | ||
12421 | (define_split | |
097657c3 | 12422 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12423 | (compare:CC |
12424 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12425 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12426 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12427 | (const_int 0))) | |
12428 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12429 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12430 | "TARGET_POWER && reload_completed" |
097657c3 | 12431 | [(set (match_dup 0) |
9ebbca7d | 12432 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12433 | (set (match_dup 4) |
9ebbca7d GK |
12434 | (compare:CC (match_dup 0) |
12435 | (const_int 0)))] | |
12436 | "") | |
1fd4e8c1 RK |
12437 | |
12438 | (define_insn "" | |
cd2b37d9 RK |
12439 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12440 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12441 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12442 | "TARGET_POWER" |
12443 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12444 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12445 | |
12446 | (define_insn "" | |
cd2b37d9 RK |
12447 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12448 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12449 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
683bdff7 | 12450 | "TARGET_32BIT" |
1fd4e8c1 | 12451 | "@ |
ca7f5001 RK |
12452 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
12453 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 12454 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12455 | |
12456 | (define_insn "" | |
9ebbca7d | 12457 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12458 | (compare:CC |
9ebbca7d GK |
12459 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12460 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12461 | (const_int 0))) |
9ebbca7d | 12462 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12463 | (ltu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12464 | "TARGET_32BIT" |
1fd4e8c1 | 12465 | "@ |
ca7f5001 | 12466 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
12467 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
12468 | # | |
12469 | #" | |
b19003d8 | 12470 | [(set_attr "type" "compare") |
9ebbca7d GK |
12471 | (set_attr "length" "12,12,16,16")]) |
12472 | ||
12473 | (define_split | |
12474 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12475 | (compare:CC | |
12476 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12477 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12478 | (const_int 0))) | |
12479 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12480 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12481 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12482 | [(set (match_dup 0) |
12483 | (ltu:SI (match_dup 1) (match_dup 2))) | |
12484 | (set (match_dup 3) | |
12485 | (compare:CC (match_dup 0) | |
12486 | (const_int 0)))] | |
12487 | "") | |
1fd4e8c1 RK |
12488 | |
12489 | (define_insn "" | |
80103f96 | 12490 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
19378cf8 MM |
12491 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12492 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
80103f96 | 12493 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))] |
683bdff7 | 12494 | "TARGET_32BIT" |
1fd4e8c1 | 12495 | "@ |
80103f96 FS |
12496 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3 |
12497 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" | |
b19003d8 | 12498 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12499 | |
12500 | (define_insn "" | |
9ebbca7d | 12501 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12502 | (compare:CC |
9ebbca7d GK |
12503 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12504 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12505 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12506 | (const_int 0))) |
9ebbca7d | 12507 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12508 | "TARGET_32BIT" |
1fd4e8c1 | 12509 | "@ |
ca7f5001 | 12510 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
9ebbca7d GK |
12511 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
12512 | # | |
12513 | #" | |
b19003d8 | 12514 | [(set_attr "type" "compare") |
9ebbca7d GK |
12515 | (set_attr "length" "12,12,16,16")]) |
12516 | ||
12517 | (define_split | |
12518 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12519 | (compare:CC | |
12520 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12521 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12522 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12523 | (const_int 0))) | |
12524 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12525 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12526 | [(set (match_dup 4) |
12527 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12528 | (match_dup 3))) |
9ebbca7d GK |
12529 | (set (match_dup 0) |
12530 | (compare:CC (match_dup 4) | |
12531 | (const_int 0)))] | |
12532 | "") | |
1fd4e8c1 RK |
12533 | |
12534 | (define_insn "" | |
097657c3 | 12535 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12536 | (compare:CC |
9ebbca7d GK |
12537 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12538 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12539 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12540 | (const_int 0))) |
097657c3 AM |
12541 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12542 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12543 | "TARGET_32BIT" |
1fd4e8c1 | 12544 | "@ |
097657c3 AM |
12545 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 |
12546 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 | |
9ebbca7d GK |
12547 | # |
12548 | #" | |
b19003d8 | 12549 | [(set_attr "type" "compare") |
9ebbca7d GK |
12550 | (set_attr "length" "12,12,16,16")]) |
12551 | ||
12552 | (define_split | |
097657c3 | 12553 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12554 | (compare:CC |
12555 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12556 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12557 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12558 | (const_int 0))) | |
12559 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12560 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12561 | "TARGET_32BIT && reload_completed" |
097657c3 | 12562 | [(set (match_dup 0) |
9ebbca7d | 12563 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12564 | (set (match_dup 4) |
9ebbca7d GK |
12565 | (compare:CC (match_dup 0) |
12566 | (const_int 0)))] | |
12567 | "") | |
1fd4e8c1 RK |
12568 | |
12569 | (define_insn "" | |
cd2b37d9 RK |
12570 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12571 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12572 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
683bdff7 | 12573 | "TARGET_32BIT" |
1fd4e8c1 | 12574 | "@ |
ca7f5001 RK |
12575 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
12576 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12577 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12578 | |
12579 | (define_insn "" | |
cd2b37d9 RK |
12580 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12581 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
12582 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
12583 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
12584 | "TARGET_POWER" |
12585 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 12586 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12587 | |
9ebbca7d GK |
12588 | (define_insn "" |
12589 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 12590 | (compare:CC |
9ebbca7d GK |
12591 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12592 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12593 | (const_int 0))) |
9ebbca7d | 12594 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12595 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12596 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 12597 | "TARGET_POWER" |
9ebbca7d GK |
12598 | "@ |
12599 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
12600 | #" | |
12601 | [(set_attr "type" "compare") | |
12602 | (set_attr "length" "12,16")]) | |
12603 | ||
12604 | (define_split | |
12605 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12606 | (compare:CC | |
12607 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12608 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12609 | (const_int 0))) | |
12610 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12611 | (ge:SI (match_dup 1) (match_dup 2))) | |
12612 | (clobber (match_scratch:SI 3 ""))] | |
12613 | "TARGET_POWER && reload_completed" | |
12614 | [(parallel [(set (match_dup 0) | |
097657c3 AM |
12615 | (ge:SI (match_dup 1) (match_dup 2))) |
12616 | (clobber (match_dup 3))]) | |
9ebbca7d GK |
12617 | (set (match_dup 4) |
12618 | (compare:CC (match_dup 0) | |
12619 | (const_int 0)))] | |
12620 | "") | |
12621 | ||
1fd4e8c1 | 12622 | (define_insn "" |
097657c3 | 12623 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12624 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12625 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12626 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12627 | "TARGET_POWER" |
097657c3 | 12628 | "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" |
b19003d8 | 12629 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12630 | |
12631 | (define_insn "" | |
9ebbca7d | 12632 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12633 | (compare:CC |
9ebbca7d GK |
12634 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12635 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12636 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12637 | (const_int 0))) |
9ebbca7d | 12638 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12639 | "TARGET_POWER" |
9ebbca7d GK |
12640 | "@ |
12641 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
12642 | #" | |
b19003d8 | 12643 | [(set_attr "type" "compare") |
9ebbca7d GK |
12644 | (set_attr "length" "12,16")]) |
12645 | ||
12646 | (define_split | |
12647 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12648 | (compare:CC | |
12649 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12650 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12651 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12652 | (const_int 0))) | |
12653 | (clobber (match_scratch:SI 4 ""))] | |
12654 | "TARGET_POWER && reload_completed" | |
12655 | [(set (match_dup 4) | |
12656 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12657 | (match_dup 3))) |
9ebbca7d GK |
12658 | (set (match_dup 0) |
12659 | (compare:CC (match_dup 4) | |
12660 | (const_int 0)))] | |
12661 | "") | |
1fd4e8c1 RK |
12662 | |
12663 | (define_insn "" | |
097657c3 | 12664 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12665 | (compare:CC |
9ebbca7d GK |
12666 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12667 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12668 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12669 | (const_int 0))) |
097657c3 AM |
12670 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12671 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12672 | "TARGET_POWER" |
9ebbca7d | 12673 | "@ |
097657c3 | 12674 | doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
9ebbca7d | 12675 | #" |
b19003d8 | 12676 | [(set_attr "type" "compare") |
9ebbca7d GK |
12677 | (set_attr "length" "12,16")]) |
12678 | ||
12679 | (define_split | |
097657c3 | 12680 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12681 | (compare:CC |
12682 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12683 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12684 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12685 | (const_int 0))) | |
12686 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12687 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12688 | "TARGET_POWER && reload_completed" |
097657c3 | 12689 | [(set (match_dup 0) |
9ebbca7d | 12690 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12691 | (set (match_dup 4) |
9ebbca7d GK |
12692 | (compare:CC (match_dup 0) |
12693 | (const_int 0)))] | |
12694 | "") | |
1fd4e8c1 RK |
12695 | |
12696 | (define_insn "" | |
cd2b37d9 RK |
12697 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12698 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12699 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12700 | "TARGET_POWER" |
12701 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12702 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12703 | |
1fd4e8c1 | 12704 | (define_insn "" |
cd2b37d9 RK |
12705 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12706 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12707 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
683bdff7 | 12708 | "TARGET_32BIT" |
1fd4e8c1 | 12709 | "@ |
ca7f5001 RK |
12710 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
12711 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 12712 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12713 | |
f9562f27 DE |
12714 | (define_insn "" |
12715 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12716 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12717 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
683bdff7 | 12718 | "TARGET_64BIT" |
f9562f27 DE |
12719 | "@ |
12720 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
12721 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
12722 | [(set_attr "length" "12")]) | |
12723 | ||
1fd4e8c1 | 12724 | (define_insn "" |
9ebbca7d | 12725 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12726 | (compare:CC |
9ebbca7d GK |
12727 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12728 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12729 | (const_int 0))) |
9ebbca7d | 12730 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12731 | (geu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12732 | "TARGET_32BIT" |
1fd4e8c1 | 12733 | "@ |
ca7f5001 | 12734 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
12735 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
12736 | # | |
12737 | #" | |
b19003d8 | 12738 | [(set_attr "type" "compare") |
9ebbca7d GK |
12739 | (set_attr "length" "12,12,16,16")]) |
12740 | ||
12741 | (define_split | |
12742 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12743 | (compare:CC | |
12744 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12745 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12746 | (const_int 0))) | |
12747 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12748 | (geu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12749 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12750 | [(set (match_dup 0) |
12751 | (geu:SI (match_dup 1) (match_dup 2))) | |
12752 | (set (match_dup 3) | |
12753 | (compare:CC (match_dup 0) | |
12754 | (const_int 0)))] | |
12755 | "") | |
1fd4e8c1 | 12756 | |
f9562f27 | 12757 | (define_insn "" |
9ebbca7d | 12758 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12759 | (compare:CC |
9ebbca7d GK |
12760 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12761 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 12762 | (const_int 0))) |
9ebbca7d | 12763 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 | 12764 | (geu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12765 | "TARGET_64BIT" |
f9562f27 DE |
12766 | "@ |
12767 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
12768 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
12769 | # | |
12770 | #" | |
f9562f27 | 12771 | [(set_attr "type" "compare") |
9ebbca7d GK |
12772 | (set_attr "length" "12,12,16,16")]) |
12773 | ||
12774 | (define_split | |
12775 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12776 | (compare:CC | |
12777 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12778 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
12779 | (const_int 0))) | |
12780 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12781 | (geu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12782 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12783 | [(set (match_dup 0) |
12784 | (geu:DI (match_dup 1) (match_dup 2))) | |
12785 | (set (match_dup 3) | |
12786 | (compare:CC (match_dup 0) | |
12787 | (const_int 0)))] | |
12788 | "") | |
f9562f27 | 12789 | |
1fd4e8c1 | 12790 | (define_insn "" |
80103f96 | 12791 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 12792 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12793 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
80103f96 | 12794 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
683bdff7 | 12795 | "TARGET_32BIT" |
1fd4e8c1 | 12796 | "@ |
80103f96 FS |
12797 | {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 |
12798 | {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 12799 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12800 | |
12801 | (define_insn "" | |
9ebbca7d | 12802 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12803 | (compare:CC |
9ebbca7d GK |
12804 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12805 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12806 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12807 | (const_int 0))) |
9ebbca7d | 12808 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12809 | "TARGET_32BIT" |
1fd4e8c1 | 12810 | "@ |
ca7f5001 | 12811 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12812 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
12813 | # | |
12814 | #" | |
b19003d8 | 12815 | [(set_attr "type" "compare") |
9ebbca7d GK |
12816 | (set_attr "length" "8,8,12,12")]) |
12817 | ||
12818 | (define_split | |
12819 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12820 | (compare:CC | |
12821 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12822 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12823 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12824 | (const_int 0))) | |
12825 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12826 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12827 | [(set (match_dup 4) |
12828 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
12829 | (match_dup 3))) | |
12830 | (set (match_dup 0) | |
12831 | (compare:CC (match_dup 4) | |
12832 | (const_int 0)))] | |
12833 | "") | |
1fd4e8c1 RK |
12834 | |
12835 | (define_insn "" | |
097657c3 | 12836 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12837 | (compare:CC |
9ebbca7d GK |
12838 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12839 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12840 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12841 | (const_int 0))) |
097657c3 AM |
12842 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12843 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12844 | "TARGET_32BIT" |
1fd4e8c1 | 12845 | "@ |
097657c3 AM |
12846 | {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 |
12847 | {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12848 | # |
12849 | #" | |
b19003d8 | 12850 | [(set_attr "type" "compare") |
9ebbca7d GK |
12851 | (set_attr "length" "8,8,12,12")]) |
12852 | ||
12853 | (define_split | |
097657c3 | 12854 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12855 | (compare:CC |
12856 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12857 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12858 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12859 | (const_int 0))) | |
12860 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12861 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12862 | "TARGET_32BIT && reload_completed" |
097657c3 | 12863 | [(set (match_dup 0) |
9ebbca7d | 12864 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12865 | (set (match_dup 4) |
9ebbca7d GK |
12866 | (compare:CC (match_dup 0) |
12867 | (const_int 0)))] | |
12868 | "") | |
1fd4e8c1 RK |
12869 | |
12870 | (define_insn "" | |
cd2b37d9 RK |
12871 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12872 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12873 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
683bdff7 | 12874 | "TARGET_32BIT" |
1fd4e8c1 | 12875 | "@ |
ca7f5001 | 12876 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 12877 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 12878 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12879 | |
12880 | (define_insn "" | |
097657c3 | 12881 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
1fd4e8c1 | 12882 | (and:SI (neg:SI |
cd2b37d9 | 12883 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12884 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
097657c3 | 12885 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
683bdff7 | 12886 | "TARGET_32BIT" |
1fd4e8c1 | 12887 | "@ |
097657c3 AM |
12888 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 |
12889 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" | |
b19003d8 | 12890 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12891 | |
12892 | (define_insn "" | |
9ebbca7d | 12893 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12894 | (compare:CC |
12895 | (and:SI (neg:SI | |
9ebbca7d GK |
12896 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12897 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12898 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12899 | (const_int 0))) |
9ebbca7d | 12900 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12901 | "TARGET_32BIT" |
1fd4e8c1 | 12902 | "@ |
ca7f5001 | 12903 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
12904 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
12905 | # | |
12906 | #" | |
b19003d8 | 12907 | [(set_attr "type" "compare") |
9ebbca7d GK |
12908 | (set_attr "length" "12,12,16,16")]) |
12909 | ||
12910 | (define_split | |
12911 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12912 | (compare:CC | |
12913 | (and:SI (neg:SI | |
12914 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12915 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12916 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12917 | (const_int 0))) | |
12918 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12919 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 12920 | [(set (match_dup 4) |
097657c3 AM |
12921 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) |
12922 | (match_dup 3))) | |
9ebbca7d GK |
12923 | (set (match_dup 0) |
12924 | (compare:CC (match_dup 4) | |
12925 | (const_int 0)))] | |
12926 | "") | |
1fd4e8c1 RK |
12927 | |
12928 | (define_insn "" | |
097657c3 | 12929 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12930 | (compare:CC |
12931 | (and:SI (neg:SI | |
9ebbca7d GK |
12932 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12933 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12934 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12935 | (const_int 0))) |
097657c3 AM |
12936 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12937 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 12938 | "TARGET_32BIT" |
1fd4e8c1 | 12939 | "@ |
097657c3 AM |
12940 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
12941 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 | |
9ebbca7d GK |
12942 | # |
12943 | #" | |
b19003d8 | 12944 | [(set_attr "type" "compare") |
9ebbca7d GK |
12945 | (set_attr "length" "12,12,16,16")]) |
12946 | ||
12947 | (define_split | |
097657c3 | 12948 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12949 | (compare:CC |
12950 | (and:SI (neg:SI | |
12951 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12952 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12953 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12954 | (const_int 0))) | |
12955 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12956 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 12957 | "TARGET_32BIT && reload_completed" |
097657c3 | 12958 | [(set (match_dup 0) |
9ebbca7d | 12959 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
097657c3 | 12960 | (set (match_dup 4) |
9ebbca7d GK |
12961 | (compare:CC (match_dup 0) |
12962 | (const_int 0)))] | |
12963 | "") | |
1fd4e8c1 RK |
12964 | |
12965 | (define_insn "" | |
cd2b37d9 RK |
12966 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12967 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12968 | (const_int 0)))] |
683bdff7 | 12969 | "TARGET_32BIT" |
ca7f5001 | 12970 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12971 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12972 | |
f9562f27 DE |
12973 | (define_insn "" |
12974 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12975 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12976 | (const_int 0)))] | |
683bdff7 | 12977 | "TARGET_64BIT" |
f9562f27 DE |
12978 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" |
12979 | [(set_attr "length" "12")]) | |
12980 | ||
1fd4e8c1 | 12981 | (define_insn "" |
9ebbca7d | 12982 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12983 | (compare:CC |
9ebbca7d | 12984 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
12985 | (const_int 0)) |
12986 | (const_int 0))) | |
9ebbca7d | 12987 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12988 | (gt:SI (match_dup 1) (const_int 0)))] |
683bdff7 | 12989 | "TARGET_32BIT" |
9ebbca7d GK |
12990 | "@ |
12991 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
12992 | #" | |
29ae5b89 | 12993 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12994 | (set_attr "length" "12,16")]) |
12995 | ||
12996 | (define_split | |
12997 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
12998 | (compare:CC | |
12999 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13000 | (const_int 0)) | |
13001 | (const_int 0))) | |
13002 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13003 | (gt:SI (match_dup 1) (const_int 0)))] | |
683bdff7 | 13004 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13005 | [(set (match_dup 0) |
13006 | (gt:SI (match_dup 1) (const_int 0))) | |
13007 | (set (match_dup 2) | |
13008 | (compare:CC (match_dup 0) | |
13009 | (const_int 0)))] | |
13010 | "") | |
1fd4e8c1 | 13011 | |
f9562f27 | 13012 | (define_insn "" |
9ebbca7d | 13013 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 13014 | (compare:CC |
9ebbca7d | 13015 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
13016 | (const_int 0)) |
13017 | (const_int 0))) | |
9ebbca7d | 13018 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 13019 | (gt:DI (match_dup 1) (const_int 0)))] |
683bdff7 | 13020 | "TARGET_64BIT" |
9ebbca7d GK |
13021 | "@ |
13022 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
13023 | #" | |
f9562f27 | 13024 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13025 | (set_attr "length" "12,16")]) |
13026 | ||
13027 | (define_split | |
13028 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
13029 | (compare:CC | |
13030 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13031 | (const_int 0)) | |
13032 | (const_int 0))) | |
13033 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13034 | (gt:DI (match_dup 1) (const_int 0)))] | |
683bdff7 | 13035 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13036 | [(set (match_dup 0) |
13037 | (gt:DI (match_dup 1) (const_int 0))) | |
13038 | (set (match_dup 2) | |
13039 | (compare:CC (match_dup 0) | |
13040 | (const_int 0)))] | |
13041 | "") | |
f9562f27 | 13042 | |
1fd4e8c1 | 13043 | (define_insn "" |
cd2b37d9 RK |
13044 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13045 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13046 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
13047 | "TARGET_POWER" |
13048 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 13049 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13050 | |
13051 | (define_insn "" | |
9ebbca7d | 13052 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13053 | (compare:CC |
9ebbca7d GK |
13054 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13055 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 13056 | (const_int 0))) |
9ebbca7d | 13057 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13058 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 13059 | "TARGET_POWER" |
9ebbca7d GK |
13060 | "@ |
13061 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
13062 | #" | |
29ae5b89 | 13063 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13064 | (set_attr "length" "12,16")]) |
13065 | ||
13066 | (define_split | |
13067 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13068 | (compare:CC | |
13069 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13070 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13071 | (const_int 0))) | |
13072 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13073 | (gt:SI (match_dup 1) (match_dup 2)))] | |
13074 | "TARGET_POWER && reload_completed" | |
13075 | [(set (match_dup 0) | |
13076 | (gt:SI (match_dup 1) (match_dup 2))) | |
13077 | (set (match_dup 3) | |
13078 | (compare:CC (match_dup 0) | |
13079 | (const_int 0)))] | |
13080 | "") | |
1fd4e8c1 RK |
13081 | |
13082 | (define_insn "" | |
80103f96 | 13083 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13084 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13085 | (const_int 0)) |
80103f96 | 13086 | (match_operand:SI 2 "gpc_reg_operand" "r")))] |
683bdff7 | 13087 | "TARGET_32BIT" |
80103f96 | 13088 | "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" |
b19003d8 | 13089 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13090 | |
f9562f27 | 13091 | (define_insn "" |
097657c3 | 13092 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
f9562f27 DE |
13093 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
13094 | (const_int 0)) | |
097657c3 | 13095 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
683bdff7 | 13096 | "TARGET_64BIT" |
097657c3 | 13097 | "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" |
f9562f27 DE |
13098 | [(set_attr "length" "12")]) |
13099 | ||
1fd4e8c1 | 13100 | (define_insn "" |
9ebbca7d | 13101 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13102 | (compare:CC |
9ebbca7d | 13103 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 13104 | (const_int 0)) |
9ebbca7d | 13105 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 13106 | (const_int 0))) |
9ebbca7d | 13107 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 13108 | "TARGET_32BIT" |
9ebbca7d GK |
13109 | "@ |
13110 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
13111 | #" | |
b19003d8 | 13112 | [(set_attr "type" "compare") |
9ebbca7d GK |
13113 | (set_attr "length" "12,16")]) |
13114 | ||
13115 | (define_split | |
13116 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13117 | (compare:CC | |
13118 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13119 | (const_int 0)) | |
13120 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
13121 | (const_int 0))) | |
13122 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 13123 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13124 | [(set (match_dup 3) |
13125 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
13126 | (match_dup 2))) | |
13127 | (set (match_dup 0) | |
13128 | (compare:CC (match_dup 3) | |
13129 | (const_int 0)))] | |
13130 | "") | |
1fd4e8c1 | 13131 | |
f9562f27 | 13132 | (define_insn "" |
9ebbca7d | 13133 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 13134 | (compare:CC |
9ebbca7d | 13135 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13136 | (const_int 0)) |
9ebbca7d | 13137 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13138 | (const_int 0))) |
9ebbca7d | 13139 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 13140 | "TARGET_64BIT" |
9ebbca7d GK |
13141 | "@ |
13142 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
13143 | #" | |
f9562f27 | 13144 | [(set_attr "type" "compare") |
9ebbca7d GK |
13145 | (set_attr "length" "12,16")]) |
13146 | ||
13147 | (define_split | |
13148 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13149 | (compare:CC | |
13150 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13151 | (const_int 0)) | |
13152 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13153 | (const_int 0))) | |
13154 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 13155 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13156 | [(set (match_dup 3) |
13157 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
097657c3 | 13158 | (match_dup 2))) |
9ebbca7d GK |
13159 | (set (match_dup 0) |
13160 | (compare:CC (match_dup 3) | |
13161 | (const_int 0)))] | |
13162 | "") | |
f9562f27 | 13163 | |
1fd4e8c1 | 13164 | (define_insn "" |
097657c3 | 13165 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
9ebbca7d GK |
13166 | (compare:CC |
13167 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
13168 | (const_int 0)) | |
13169 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
13170 | (const_int 0))) | |
097657c3 AM |
13171 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13172 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 13173 | "TARGET_32BIT" |
9ebbca7d | 13174 | "@ |
097657c3 | 13175 | {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 |
9ebbca7d GK |
13176 | #" |
13177 | [(set_attr "type" "compare") | |
13178 | (set_attr "length" "12,16")]) | |
13179 | ||
13180 | (define_split | |
097657c3 | 13181 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
1fd4e8c1 | 13182 | (compare:CC |
9ebbca7d | 13183 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 13184 | (const_int 0)) |
9ebbca7d | 13185 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 13186 | (const_int 0))) |
9ebbca7d | 13187 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
097657c3 | 13188 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 13189 | "TARGET_32BIT && reload_completed" |
097657c3 | 13190 | [(set (match_dup 0) |
9ebbca7d | 13191 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13192 | (set (match_dup 3) |
9ebbca7d GK |
13193 | (compare:CC (match_dup 0) |
13194 | (const_int 0)))] | |
13195 | "") | |
1fd4e8c1 | 13196 | |
f9562f27 | 13197 | (define_insn "" |
097657c3 | 13198 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13199 | (compare:CC |
9ebbca7d | 13200 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13201 | (const_int 0)) |
9ebbca7d | 13202 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13203 | (const_int 0))) |
097657c3 AM |
13204 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
13205 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 13206 | "TARGET_64BIT" |
9ebbca7d | 13207 | "@ |
097657c3 | 13208 | addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 |
9ebbca7d | 13209 | #" |
f9562f27 | 13210 | [(set_attr "type" "compare") |
9ebbca7d GK |
13211 | (set_attr "length" "12,16")]) |
13212 | ||
13213 | (define_split | |
097657c3 | 13214 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13215 | (compare:CC |
13216 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13217 | (const_int 0)) | |
13218 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13219 | (const_int 0))) | |
13220 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13221 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 13222 | "TARGET_64BIT && reload_completed" |
097657c3 | 13223 | [(set (match_dup 0) |
9ebbca7d | 13224 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13225 | (set (match_dup 3) |
9ebbca7d GK |
13226 | (compare:CC (match_dup 0) |
13227 | (const_int 0)))] | |
13228 | "") | |
f9562f27 | 13229 | |
1fd4e8c1 | 13230 | (define_insn "" |
097657c3 | 13231 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13232 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13233 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
097657c3 | 13234 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 13235 | "TARGET_POWER" |
097657c3 | 13236 | "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 13237 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13238 | |
13239 | (define_insn "" | |
9ebbca7d | 13240 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13241 | (compare:CC |
9ebbca7d GK |
13242 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13243 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13244 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13245 | (const_int 0))) |
9ebbca7d | 13246 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 13247 | "TARGET_POWER" |
9ebbca7d GK |
13248 | "@ |
13249 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
13250 | #" | |
b19003d8 | 13251 | [(set_attr "type" "compare") |
9ebbca7d GK |
13252 | (set_attr "length" "12,16")]) |
13253 | ||
13254 | (define_split | |
13255 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13256 | (compare:CC | |
13257 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13258 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13259 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13260 | (const_int 0))) | |
13261 | (clobber (match_scratch:SI 4 ""))] | |
13262 | "TARGET_POWER && reload_completed" | |
13263 | [(set (match_dup 4) | |
097657c3 | 13264 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d GK |
13265 | (set (match_dup 0) |
13266 | (compare:CC (match_dup 4) | |
13267 | (const_int 0)))] | |
13268 | "") | |
1fd4e8c1 RK |
13269 | |
13270 | (define_insn "" | |
097657c3 | 13271 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13272 | (compare:CC |
9ebbca7d GK |
13273 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13274 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13275 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13276 | (const_int 0))) |
097657c3 AM |
13277 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13278 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 13279 | "TARGET_POWER" |
9ebbca7d | 13280 | "@ |
097657c3 | 13281 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 13282 | #" |
b19003d8 | 13283 | [(set_attr "type" "compare") |
9ebbca7d GK |
13284 | (set_attr "length" "12,16")]) |
13285 | ||
13286 | (define_split | |
097657c3 | 13287 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13288 | (compare:CC |
13289 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13290 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13291 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13292 | (const_int 0))) | |
13293 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13294 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13295 | "TARGET_POWER && reload_completed" |
097657c3 | 13296 | [(set (match_dup 0) |
9ebbca7d | 13297 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13298 | (set (match_dup 4) |
9ebbca7d GK |
13299 | (compare:CC (match_dup 0) |
13300 | (const_int 0)))] | |
13301 | "") | |
1fd4e8c1 RK |
13302 | |
13303 | (define_insn "" | |
cd2b37d9 RK |
13304 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13305 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13306 | (const_int 0))))] |
683bdff7 | 13307 | "TARGET_32BIT" |
ca7f5001 | 13308 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 13309 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13310 | |
f9562f27 DE |
13311 | (define_insn "" |
13312 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13313 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13314 | (const_int 0))))] | |
683bdff7 | 13315 | "TARGET_64BIT" |
8377288b | 13316 | "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63" |
f9562f27 DE |
13317 | [(set_attr "length" "12")]) |
13318 | ||
1fd4e8c1 | 13319 | (define_insn "" |
cd2b37d9 RK |
13320 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13321 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13322 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
13323 | "TARGET_POWER" |
13324 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 13325 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13326 | |
13327 | (define_insn "" | |
cd2b37d9 RK |
13328 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13329 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13330 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
683bdff7 | 13331 | "TARGET_32BIT" |
ca7f5001 | 13332 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 13333 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13334 | |
f9562f27 DE |
13335 | (define_insn "" |
13336 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13337 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13338 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13339 | "TARGET_64BIT" |
f9562f27 DE |
13340 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0" |
13341 | [(set_attr "length" "12")]) | |
13342 | ||
1fd4e8c1 | 13343 | (define_insn "" |
9ebbca7d | 13344 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13345 | (compare:CC |
9ebbca7d GK |
13346 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13347 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 13348 | (const_int 0))) |
9ebbca7d | 13349 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13350 | (gtu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 13351 | "TARGET_32BIT" |
9ebbca7d GK |
13352 | "@ |
13353 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
13354 | #" | |
b19003d8 | 13355 | [(set_attr "type" "compare") |
9ebbca7d GK |
13356 | (set_attr "length" "12,16")]) |
13357 | ||
13358 | (define_split | |
13359 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13360 | (compare:CC | |
13361 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13362 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13363 | (const_int 0))) | |
13364 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13365 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 13366 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13367 | [(set (match_dup 0) |
13368 | (gtu:SI (match_dup 1) (match_dup 2))) | |
13369 | (set (match_dup 3) | |
13370 | (compare:CC (match_dup 0) | |
13371 | (const_int 0)))] | |
13372 | "") | |
1fd4e8c1 | 13373 | |
f9562f27 | 13374 | (define_insn "" |
9ebbca7d | 13375 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13376 | (compare:CC |
9ebbca7d GK |
13377 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13378 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 13379 | (const_int 0))) |
9ebbca7d | 13380 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 13381 | (gtu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 13382 | "TARGET_64BIT" |
9ebbca7d GK |
13383 | "@ |
13384 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
13385 | #" | |
f9562f27 | 13386 | [(set_attr "type" "compare") |
9ebbca7d GK |
13387 | (set_attr "length" "12,16")]) |
13388 | ||
13389 | (define_split | |
13390 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13391 | (compare:CC | |
13392 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13393 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13394 | (const_int 0))) | |
13395 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13396 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 13397 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13398 | [(set (match_dup 0) |
13399 | (gtu:DI (match_dup 1) (match_dup 2))) | |
13400 | (set (match_dup 3) | |
13401 | (compare:CC (match_dup 0) | |
13402 | (const_int 0)))] | |
13403 | "") | |
f9562f27 | 13404 | |
1fd4e8c1 | 13405 | (define_insn "" |
80103f96 | 13406 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
19378cf8 MM |
13407 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13408 | (match_operand:SI 2 "reg_or_short_operand" "I,rI")) | |
80103f96 | 13409 | (match_operand:SI 3 "reg_or_short_operand" "r,rI")))] |
683bdff7 | 13410 | "TARGET_32BIT" |
00751805 | 13411 | "@ |
80103f96 FS |
13412 | {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3 |
13413 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" | |
19378cf8 | 13414 | [(set_attr "length" "8,12")]) |
1fd4e8c1 | 13415 | |
f9562f27 | 13416 | (define_insn "" |
097657c3 | 13417 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
f9562f27 DE |
13418 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13419 | (match_operand:DI 2 "reg_or_short_operand" "I,rI")) | |
097657c3 | 13420 | (match_operand:DI 3 "reg_or_short_operand" "r,rI")))] |
683bdff7 | 13421 | "TARGET_64BIT" |
f9562f27 | 13422 | "@ |
097657c3 AM |
13423 | addic %0,%1,%k2\;addze %0,%3 |
13424 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3" | |
f9562f27 DE |
13425 | [(set_attr "length" "8,12")]) |
13426 | ||
1fd4e8c1 | 13427 | (define_insn "" |
9ebbca7d | 13428 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13429 | (compare:CC |
9ebbca7d GK |
13430 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13431 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13432 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13433 | (const_int 0))) |
9ebbca7d | 13434 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13435 | "TARGET_32BIT" |
00751805 | 13436 | "@ |
19378cf8 | 13437 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
13438 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
13439 | # | |
13440 | #" | |
b19003d8 | 13441 | [(set_attr "type" "compare") |
9ebbca7d GK |
13442 | (set_attr "length" "8,12,12,16")]) |
13443 | ||
13444 | (define_split | |
13445 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13446 | (compare:CC | |
13447 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13448 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13449 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13450 | (const_int 0))) | |
13451 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 13452 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13453 | [(set (match_dup 4) |
13454 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 13455 | (match_dup 3))) |
9ebbca7d GK |
13456 | (set (match_dup 0) |
13457 | (compare:CC (match_dup 4) | |
13458 | (const_int 0)))] | |
13459 | "") | |
1fd4e8c1 | 13460 | |
f9562f27 | 13461 | (define_insn "" |
9ebbca7d | 13462 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13463 | (compare:CC |
9ebbca7d GK |
13464 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13465 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13466 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13467 | (const_int 0))) |
9ebbca7d | 13468 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13469 | "TARGET_64BIT" |
f9562f27 DE |
13470 | "@ |
13471 | addic %4,%1,%k2\;addze. %4,%3 | |
9ebbca7d GK |
13472 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3 |
13473 | # | |
13474 | #" | |
f9562f27 | 13475 | [(set_attr "type" "compare") |
9ebbca7d GK |
13476 | (set_attr "length" "8,12,12,16")]) |
13477 | ||
13478 | (define_split | |
13479 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13480 | (compare:CC | |
13481 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13482 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13483 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13484 | (const_int 0))) | |
13485 | (clobber (match_scratch:DI 4 ""))] | |
683bdff7 | 13486 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13487 | [(set (match_dup 4) |
13488 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
13489 | (match_dup 3))) | |
13490 | (set (match_dup 0) | |
13491 | (compare:CC (match_dup 4) | |
13492 | (const_int 0)))] | |
13493 | "") | |
f9562f27 | 13494 | |
1fd4e8c1 | 13495 | (define_insn "" |
097657c3 | 13496 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13497 | (compare:CC |
9ebbca7d GK |
13498 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13499 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13500 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13501 | (const_int 0))) |
097657c3 AM |
13502 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13503 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 13504 | "TARGET_32BIT" |
00751805 | 13505 | "@ |
097657c3 AM |
13506 | {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 |
13507 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 | |
9ebbca7d GK |
13508 | # |
13509 | #" | |
b19003d8 | 13510 | [(set_attr "type" "compare") |
9ebbca7d GK |
13511 | (set_attr "length" "8,12,12,16")]) |
13512 | ||
13513 | (define_split | |
097657c3 | 13514 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13515 | (compare:CC |
13516 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13517 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13518 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13519 | (const_int 0))) | |
13520 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13521 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 13522 | "TARGET_32BIT && reload_completed" |
097657c3 | 13523 | [(set (match_dup 0) |
9ebbca7d | 13524 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13525 | (set (match_dup 4) |
9ebbca7d GK |
13526 | (compare:CC (match_dup 0) |
13527 | (const_int 0)))] | |
13528 | "") | |
1fd4e8c1 | 13529 | |
f9562f27 | 13530 | (define_insn "" |
097657c3 | 13531 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13532 | (compare:CC |
9ebbca7d GK |
13533 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13534 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13535 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13536 | (const_int 0))) |
097657c3 AM |
13537 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13538 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 13539 | "TARGET_64BIT" |
f9562f27 | 13540 | "@ |
097657c3 AM |
13541 | addic %0,%1,%k2\;addze. %0,%3 |
13542 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3 | |
9ebbca7d GK |
13543 | # |
13544 | #" | |
f9562f27 | 13545 | [(set_attr "type" "compare") |
9ebbca7d GK |
13546 | (set_attr "length" "8,12,12,16")]) |
13547 | ||
13548 | (define_split | |
097657c3 | 13549 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13550 | (compare:CC |
13551 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13552 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13553 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13554 | (const_int 0))) | |
13555 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13556 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 13557 | "TARGET_64BIT && reload_completed" |
097657c3 | 13558 | [(set (match_dup 0) |
9ebbca7d | 13559 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13560 | (set (match_dup 4) |
9ebbca7d GK |
13561 | (compare:CC (match_dup 0) |
13562 | (const_int 0)))] | |
13563 | "") | |
f9562f27 | 13564 | |
1fd4e8c1 | 13565 | (define_insn "" |
cd2b37d9 RK |
13566 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13567 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13568 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
683bdff7 | 13569 | "TARGET_32BIT" |
ca7f5001 | 13570 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 13571 | [(set_attr "length" "8")]) |
f9562f27 DE |
13572 | |
13573 | (define_insn "" | |
13574 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13575 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13576 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
683bdff7 | 13577 | "TARGET_64BIT" |
f9562f27 DE |
13578 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" |
13579 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
13580 | \f |
13581 | ;; Define both directions of branch and return. If we need a reload | |
13582 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
13583 | ;; register CC value to there. | |
13584 | ||
13585 | (define_insn "" | |
13586 | [(set (pc) | |
13587 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13588 | [(match_operand 2 | |
b54cf83a | 13589 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13590 | (const_int 0)]) |
13591 | (label_ref (match_operand 0 "" "")) | |
13592 | (pc)))] | |
13593 | "" | |
b19003d8 RK |
13594 | "* |
13595 | { | |
12a4e8c5 | 13596 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
13597 | }" |
13598 | [(set_attr "type" "branch")]) | |
13599 | ||
1fd4e8c1 RK |
13600 | (define_insn "" |
13601 | [(set (pc) | |
13602 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13603 | [(match_operand 1 | |
b54cf83a | 13604 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13605 | (const_int 0)]) |
13606 | (return) | |
13607 | (pc)))] | |
13608 | "direct_return ()" | |
12a4e8c5 GK |
13609 | "* |
13610 | { | |
13611 | return output_cbranch (operands[0], NULL, 0, insn); | |
13612 | }" | |
b7ff3d82 | 13613 | [(set_attr "type" "branch") |
39a10a29 | 13614 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
13615 | |
13616 | (define_insn "" | |
13617 | [(set (pc) | |
13618 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13619 | [(match_operand 2 | |
b54cf83a | 13620 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13621 | (const_int 0)]) |
13622 | (pc) | |
13623 | (label_ref (match_operand 0 "" ""))))] | |
13624 | "" | |
b19003d8 RK |
13625 | "* |
13626 | { | |
12a4e8c5 | 13627 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
13628 | }" |
13629 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13630 | |
13631 | (define_insn "" | |
13632 | [(set (pc) | |
13633 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13634 | [(match_operand 1 | |
b54cf83a | 13635 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13636 | (const_int 0)]) |
13637 | (pc) | |
13638 | (return)))] | |
13639 | "direct_return ()" | |
12a4e8c5 GK |
13640 | "* |
13641 | { | |
13642 | return output_cbranch (operands[0], NULL, 1, insn); | |
13643 | }" | |
b7ff3d82 | 13644 | [(set_attr "type" "branch") |
39a10a29 GK |
13645 | (set_attr "length" "4")]) |
13646 | ||
13647 | ;; Logic on condition register values. | |
13648 | ||
13649 | ; This pattern matches things like | |
13650 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
13651 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
13652 | ; (const_int 1))) | |
13653 | ; which are generated by the branch logic. | |
b54cf83a | 13654 | ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB) |
39a10a29 | 13655 | |
423c1189 | 13656 | (define_insn "*cceq_ior_compare" |
b54cf83a | 13657 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13658 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" |
b54cf83a | 13659 | [(match_operator:SI 2 |
39a10a29 GK |
13660 | "branch_positive_comparison_operator" |
13661 | [(match_operand 3 | |
b54cf83a | 13662 | "cc_reg_operand" "y,y") |
39a10a29 | 13663 | (const_int 0)]) |
b54cf83a | 13664 | (match_operator:SI 4 |
39a10a29 GK |
13665 | "branch_positive_comparison_operator" |
13666 | [(match_operand 5 | |
b54cf83a | 13667 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13668 | (const_int 0)])]) |
13669 | (const_int 1)))] | |
423c1189 | 13670 | "!(TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS)" |
39a10a29 | 13671 | "cr%q1 %E0,%j2,%j4" |
b54cf83a | 13672 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13673 | |
13674 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
13675 | ; Because ~1 has all but the low bit set. | |
13676 | (define_insn "" | |
b54cf83a | 13677 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13678 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" |
b54cf83a | 13679 | [(not:SI (match_operator:SI 2 |
39a10a29 GK |
13680 | "branch_positive_comparison_operator" |
13681 | [(match_operand 3 | |
b54cf83a | 13682 | "cc_reg_operand" "y,y") |
39a10a29 GK |
13683 | (const_int 0)])) |
13684 | (match_operator:SI 4 | |
13685 | "branch_positive_comparison_operator" | |
13686 | [(match_operand 5 | |
b54cf83a | 13687 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13688 | (const_int 0)])]) |
13689 | (const_int -1)))] | |
13690 | "" | |
13691 | "cr%q1 %E0,%j2,%j4" | |
b54cf83a | 13692 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 | 13693 | |
423c1189 | 13694 | (define_insn "*cceq_rev_compare" |
b54cf83a | 13695 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
6c873122 | 13696 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 13697 | "branch_positive_comparison_operator" |
6c873122 | 13698 | [(match_operand 2 |
b54cf83a | 13699 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13700 | (const_int 0)]) |
13701 | (const_int 0)))] | |
423c1189 | 13702 | "" |
251b3667 | 13703 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
b54cf83a | 13704 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13705 | |
13706 | ;; If we are comparing the result of two comparisons, this can be done | |
13707 | ;; using creqv or crxor. | |
13708 | ||
13709 | (define_insn_and_split "" | |
13710 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
13711 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
13712 | [(match_operand 2 "cc_reg_operand" "y") | |
13713 | (const_int 0)]) | |
13714 | (match_operator 3 "branch_comparison_operator" | |
13715 | [(match_operand 4 "cc_reg_operand" "y") | |
13716 | (const_int 0)])))] | |
13717 | "" | |
13718 | "#" | |
13719 | "" | |
13720 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
13721 | (match_dup 5)))] | |
13722 | " | |
13723 | { | |
13724 | int positive_1, positive_2; | |
13725 | ||
13726 | positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode); | |
13727 | positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode); | |
13728 | ||
13729 | if (! positive_1) | |
1c563bed | 13730 | operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]), |
0f4c242b KH |
13731 | GET_CODE (operands[1])), |
13732 | SImode, | |
13733 | operands[2], const0_rtx); | |
39a10a29 | 13734 | else if (GET_MODE (operands[1]) != SImode) |
0f4c242b KH |
13735 | operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, |
13736 | operands[2], const0_rtx); | |
39a10a29 GK |
13737 | |
13738 | if (! positive_2) | |
1c563bed | 13739 | operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]), |
0f4c242b KH |
13740 | GET_CODE (operands[3])), |
13741 | SImode, | |
13742 | operands[4], const0_rtx); | |
39a10a29 | 13743 | else if (GET_MODE (operands[3]) != SImode) |
0f4c242b KH |
13744 | operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
13745 | operands[4], const0_rtx); | |
39a10a29 GK |
13746 | |
13747 | if (positive_1 == positive_2) | |
251b3667 DE |
13748 | { |
13749 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
13750 | operands[5] = constm1_rtx; | |
13751 | } | |
13752 | else | |
13753 | { | |
13754 | operands[5] = const1_rtx; | |
13755 | } | |
39a10a29 | 13756 | }") |
1fd4e8c1 RK |
13757 | |
13758 | ;; Unconditional branch and return. | |
13759 | ||
13760 | (define_insn "jump" | |
13761 | [(set (pc) | |
13762 | (label_ref (match_operand 0 "" "")))] | |
13763 | "" | |
b7ff3d82 DE |
13764 | "b %l0" |
13765 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13766 | |
13767 | (define_insn "return" | |
13768 | [(return)] | |
13769 | "direct_return ()" | |
324e52cc TG |
13770 | "{br|blr}" |
13771 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 13772 | |
0ad91047 DE |
13773 | (define_expand "indirect_jump" |
13774 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 13775 | "" |
0ad91047 DE |
13776 | " |
13777 | { | |
13778 | if (TARGET_32BIT) | |
13779 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
13780 | else | |
13781 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
13782 | DONE; | |
13783 | }") | |
13784 | ||
13785 | (define_insn "indirect_jumpsi" | |
b92b324d | 13786 | [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))] |
0ad91047 | 13787 | "TARGET_32BIT" |
b92b324d DE |
13788 | "@ |
13789 | bctr | |
13790 | {br|blr}" | |
324e52cc | 13791 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13792 | |
0ad91047 | 13793 | (define_insn "indirect_jumpdi" |
b92b324d | 13794 | [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))] |
0ad91047 | 13795 | "TARGET_64BIT" |
b92b324d DE |
13796 | "@ |
13797 | bctr | |
13798 | blr" | |
266eb58a DE |
13799 | [(set_attr "type" "jmpreg")]) |
13800 | ||
1fd4e8c1 RK |
13801 | ;; Table jump for switch statements: |
13802 | (define_expand "tablejump" | |
e6ca2c17 DE |
13803 | [(use (match_operand 0 "" "")) |
13804 | (use (label_ref (match_operand 1 "" "")))] | |
13805 | "" | |
13806 | " | |
13807 | { | |
13808 | if (TARGET_32BIT) | |
13809 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
13810 | else | |
13811 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
13812 | DONE; | |
13813 | }") | |
13814 | ||
13815 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
13816 | [(set (match_dup 3) |
13817 | (plus:SI (match_operand:SI 0 "" "") | |
13818 | (match_dup 2))) | |
13819 | (parallel [(set (pc) (match_dup 3)) | |
13820 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13821 | "TARGET_32BIT" |
1fd4e8c1 RK |
13822 | " |
13823 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 13824 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
13825 | operands[3] = gen_reg_rtx (SImode); |
13826 | }") | |
13827 | ||
e6ca2c17 | 13828 | (define_expand "tablejumpdi" |
6ae08853 | 13829 | [(set (match_dup 4) |
9ebbca7d GK |
13830 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) |
13831 | (set (match_dup 3) | |
13832 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
13833 | (match_dup 2))) |
13834 | (parallel [(set (pc) (match_dup 3)) | |
13835 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13836 | "TARGET_64BIT" |
e6ca2c17 | 13837 | " |
9ebbca7d | 13838 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 13839 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 13840 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
13841 | }") |
13842 | ||
1fd4e8c1 RK |
13843 | (define_insn "" |
13844 | [(set (pc) | |
c859cda6 | 13845 | (match_operand:SI 0 "register_operand" "c,*l")) |
1fd4e8c1 | 13846 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13847 | "TARGET_32BIT" |
c859cda6 DJ |
13848 | "@ |
13849 | bctr | |
13850 | {br|blr}" | |
a6845123 | 13851 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13852 | |
266eb58a DE |
13853 | (define_insn "" |
13854 | [(set (pc) | |
c859cda6 | 13855 | (match_operand:DI 0 "register_operand" "c,*l")) |
266eb58a | 13856 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13857 | "TARGET_64BIT" |
c859cda6 DJ |
13858 | "@ |
13859 | bctr | |
13860 | blr" | |
266eb58a DE |
13861 | [(set_attr "type" "jmpreg")]) |
13862 | ||
1fd4e8c1 RK |
13863 | (define_insn "nop" |
13864 | [(const_int 0)] | |
13865 | "" | |
ca7f5001 | 13866 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 13867 | \f |
7e69e155 | 13868 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
13869 | ;; so loop.c knows what to generate. |
13870 | ||
5527bf14 RH |
13871 | (define_expand "doloop_end" |
13872 | [(use (match_operand 0 "" "")) ; loop pseudo | |
13873 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
13874 | (use (match_operand 2 "" "")) ; max iterations | |
13875 | (use (match_operand 3 "" "")) ; loop level | |
13876 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
13877 | "" |
13878 | " | |
13879 | { | |
5527bf14 RH |
13880 | /* Only use this on innermost loops. */ |
13881 | if (INTVAL (operands[3]) > 1) | |
13882 | FAIL; | |
683bdff7 | 13883 | if (TARGET_64BIT) |
5527bf14 RH |
13884 | { |
13885 | if (GET_MODE (operands[0]) != DImode) | |
13886 | FAIL; | |
13887 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
13888 | } | |
0ad91047 | 13889 | else |
5527bf14 RH |
13890 | { |
13891 | if (GET_MODE (operands[0]) != SImode) | |
13892 | FAIL; | |
13893 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
13894 | } | |
0ad91047 DE |
13895 | DONE; |
13896 | }") | |
13897 | ||
13898 | (define_expand "ctrsi" | |
3cb999d8 DE |
13899 | [(parallel [(set (pc) |
13900 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
13901 | (const_int 1)) | |
13902 | (label_ref (match_operand 1 "" "")) | |
13903 | (pc))) | |
b6c9286a MM |
13904 | (set (match_dup 0) |
13905 | (plus:SI (match_dup 0) | |
13906 | (const_int -1))) | |
5f81043f RK |
13907 | (clobber (match_scratch:CC 2 "")) |
13908 | (clobber (match_scratch:SI 3 ""))])] | |
683bdff7 | 13909 | "TARGET_32BIT" |
0ad91047 DE |
13910 | "") |
13911 | ||
13912 | (define_expand "ctrdi" | |
3cb999d8 DE |
13913 | [(parallel [(set (pc) |
13914 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
13915 | (const_int 1)) | |
13916 | (label_ref (match_operand 1 "" "")) | |
13917 | (pc))) | |
0ad91047 DE |
13918 | (set (match_dup 0) |
13919 | (plus:DI (match_dup 0) | |
13920 | (const_int -1))) | |
13921 | (clobber (match_scratch:CC 2 "")) | |
61c07d3c | 13922 | (clobber (match_scratch:DI 3 ""))])] |
683bdff7 | 13923 | "TARGET_64BIT" |
61c07d3c | 13924 | "") |
c225ba7b | 13925 | |
1fd4e8c1 RK |
13926 | ;; We need to be able to do this for any operand, including MEM, or we |
13927 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 13928 | ;; JUMP_INSNs. |
0ad91047 | 13929 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
13930 | ;; label MUST be operand 0. |
13931 | ||
0ad91047 | 13932 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 13933 | [(set (pc) |
43b68ce5 | 13934 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
1fd4e8c1 | 13935 | (const_int 1)) |
a6845123 | 13936 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13937 | (pc))) |
b150f4f3 | 13938 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
13939 | (plus:SI (match_dup 1) |
13940 | (const_int -1))) | |
43b68ce5 DE |
13941 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
13942 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 13943 | "TARGET_32BIT" |
b19003d8 RK |
13944 | "* |
13945 | { | |
af87a13e | 13946 | if (which_alternative != 0) |
b19003d8 | 13947 | return \"#\"; |
856a6884 | 13948 | else if (get_attr_length (insn) == 4) |
a6845123 | 13949 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 13950 | else |
f607bc57 | 13951 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 13952 | }" |
baf97f86 | 13953 | [(set_attr "type" "branch") |
5a195cb5 | 13954 | (set_attr "length" "*,12,16,16")]) |
7e69e155 | 13955 | |
0ad91047 | 13956 | (define_insn "*ctrsi_internal2" |
5f81043f | 13957 | [(set (pc) |
43b68ce5 | 13958 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
5f81043f RK |
13959 | (const_int 1)) |
13960 | (pc) | |
13961 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 13962 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
13963 | (plus:SI (match_dup 1) |
13964 | (const_int -1))) | |
43b68ce5 DE |
13965 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
13966 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 13967 | "TARGET_32BIT" |
0ad91047 DE |
13968 | "* |
13969 | { | |
13970 | if (which_alternative != 0) | |
13971 | return \"#\"; | |
856a6884 | 13972 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13973 | return \"bdz %l0\"; |
13974 | else | |
f607bc57 | 13975 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
13976 | }" |
13977 | [(set_attr "type" "branch") | |
5a195cb5 | 13978 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
13979 | |
13980 | (define_insn "*ctrdi_internal1" | |
13981 | [(set (pc) | |
43b68ce5 | 13982 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
13983 | (const_int 1)) |
13984 | (label_ref (match_operand 0 "" "")) | |
13985 | (pc))) | |
b150f4f3 | 13986 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
13987 | (plus:DI (match_dup 1) |
13988 | (const_int -1))) | |
43b68ce5 DE |
13989 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
13990 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 13991 | "TARGET_64BIT" |
0ad91047 DE |
13992 | "* |
13993 | { | |
13994 | if (which_alternative != 0) | |
13995 | return \"#\"; | |
856a6884 | 13996 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13997 | return \"{bdn|bdnz} %l0\"; |
13998 | else | |
f607bc57 | 13999 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14000 | }" |
14001 | [(set_attr "type" "branch") | |
5a195cb5 | 14002 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14003 | |
14004 | (define_insn "*ctrdi_internal2" | |
14005 | [(set (pc) | |
43b68ce5 | 14006 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14007 | (const_int 1)) |
14008 | (pc) | |
14009 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14010 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14011 | (plus:DI (match_dup 1) |
14012 | (const_int -1))) | |
43b68ce5 DE |
14013 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14014 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14015 | "TARGET_64BIT" |
5f81043f RK |
14016 | "* |
14017 | { | |
14018 | if (which_alternative != 0) | |
14019 | return \"#\"; | |
856a6884 | 14020 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14021 | return \"bdz %l0\"; |
14022 | else | |
f607bc57 | 14023 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
14024 | }" |
14025 | [(set_attr "type" "branch") | |
5a195cb5 | 14026 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 14027 | |
0ad91047 DE |
14028 | ;; Similar but use EQ |
14029 | ||
14030 | (define_insn "*ctrsi_internal5" | |
5f81043f | 14031 | [(set (pc) |
43b68ce5 | 14032 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
1fd4e8c1 | 14033 | (const_int 1)) |
a6845123 | 14034 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 14035 | (pc))) |
b150f4f3 | 14036 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14037 | (plus:SI (match_dup 1) |
14038 | (const_int -1))) | |
43b68ce5 DE |
14039 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14040 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14041 | "TARGET_32BIT" |
b19003d8 RK |
14042 | "* |
14043 | { | |
af87a13e | 14044 | if (which_alternative != 0) |
b19003d8 | 14045 | return \"#\"; |
856a6884 | 14046 | else if (get_attr_length (insn) == 4) |
a6845123 | 14047 | return \"bdz %l0\"; |
b19003d8 | 14048 | else |
f607bc57 | 14049 | return \"{bdn|bdnz} $+8\;b %l0\"; |
b19003d8 | 14050 | }" |
baf97f86 | 14051 | [(set_attr "type" "branch") |
5a195cb5 | 14052 | (set_attr "length" "*,12,16,16")]) |
1fd4e8c1 | 14053 | |
0ad91047 | 14054 | (define_insn "*ctrsi_internal6" |
5f81043f | 14055 | [(set (pc) |
43b68ce5 | 14056 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
5f81043f RK |
14057 | (const_int 1)) |
14058 | (pc) | |
14059 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14060 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14061 | (plus:SI (match_dup 1) |
14062 | (const_int -1))) | |
43b68ce5 DE |
14063 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14064 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14065 | "TARGET_32BIT" |
0ad91047 DE |
14066 | "* |
14067 | { | |
14068 | if (which_alternative != 0) | |
14069 | return \"#\"; | |
856a6884 | 14070 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14071 | return \"{bdn|bdnz} %l0\"; |
14072 | else | |
f607bc57 | 14073 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14074 | }" |
14075 | [(set_attr "type" "branch") | |
5a195cb5 | 14076 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14077 | |
14078 | (define_insn "*ctrdi_internal5" | |
14079 | [(set (pc) | |
43b68ce5 | 14080 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14081 | (const_int 1)) |
14082 | (label_ref (match_operand 0 "" "")) | |
14083 | (pc))) | |
b150f4f3 | 14084 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14085 | (plus:DI (match_dup 1) |
14086 | (const_int -1))) | |
43b68ce5 DE |
14087 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14088 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14089 | "TARGET_64BIT" |
0ad91047 DE |
14090 | "* |
14091 | { | |
14092 | if (which_alternative != 0) | |
14093 | return \"#\"; | |
856a6884 | 14094 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14095 | return \"bdz %l0\"; |
14096 | else | |
f607bc57 | 14097 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14098 | }" |
14099 | [(set_attr "type" "branch") | |
5a195cb5 | 14100 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14101 | |
14102 | (define_insn "*ctrdi_internal6" | |
14103 | [(set (pc) | |
43b68ce5 | 14104 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14105 | (const_int 1)) |
14106 | (pc) | |
14107 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14108 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14109 | (plus:DI (match_dup 1) |
14110 | (const_int -1))) | |
43b68ce5 DE |
14111 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14112 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14113 | "TARGET_64BIT" |
5f81043f RK |
14114 | "* |
14115 | { | |
14116 | if (which_alternative != 0) | |
14117 | return \"#\"; | |
856a6884 | 14118 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14119 | return \"{bdn|bdnz} %l0\"; |
14120 | else | |
f607bc57 | 14121 | return \"bdz $+8\;b %l0\"; |
5f81043f RK |
14122 | }" |
14123 | [(set_attr "type" "branch") | |
5a195cb5 | 14124 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 14125 | |
0ad91047 DE |
14126 | ;; Now the splitters if we could not allocate the CTR register |
14127 | ||
1fd4e8c1 RK |
14128 | (define_split |
14129 | [(set (pc) | |
14130 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14131 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14132 | (const_int 1)]) |
14133 | (match_operand 5 "" "") | |
14134 | (match_operand 6 "" ""))) | |
cd2b37d9 | 14135 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
14136 | (plus:SI (match_dup 1) |
14137 | (const_int -1))) | |
1fd4e8c1 RK |
14138 | (clobber (match_scratch:CC 3 "")) |
14139 | (clobber (match_scratch:SI 4 ""))] | |
4b8a63d6 | 14140 | "TARGET_32BIT && reload_completed" |
1fd4e8c1 | 14141 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14142 | (compare:CC (plus:SI (match_dup 1) |
14143 | (const_int -1)) | |
1fd4e8c1 | 14144 | (const_int 0))) |
5f81043f RK |
14145 | (set (match_dup 0) |
14146 | (plus:SI (match_dup 1) | |
14147 | (const_int -1)))]) | |
14148 | (set (pc) (if_then_else (match_dup 7) | |
14149 | (match_dup 5) | |
14150 | (match_dup 6)))] | |
1fd4e8c1 | 14151 | " |
0f4c242b KH |
14152 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14153 | operands[3], const0_rtx); }") | |
1fd4e8c1 RK |
14154 | |
14155 | (define_split | |
14156 | [(set (pc) | |
14157 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14158 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14159 | (const_int 1)]) |
14160 | (match_operand 5 "" "") | |
14161 | (match_operand 6 "" ""))) | |
9ebbca7d | 14162 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
14163 | (plus:SI (match_dup 1) (const_int -1))) |
14164 | (clobber (match_scratch:CC 3 "")) | |
14165 | (clobber (match_scratch:SI 4 ""))] | |
4b8a63d6 | 14166 | "TARGET_32BIT && reload_completed |
0ad91047 | 14167 | && ! gpc_reg_operand (operands[0], SImode)" |
1fd4e8c1 | 14168 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14169 | (compare:CC (plus:SI (match_dup 1) |
14170 | (const_int -1)) | |
1fd4e8c1 | 14171 | (const_int 0))) |
5f81043f RK |
14172 | (set (match_dup 4) |
14173 | (plus:SI (match_dup 1) | |
14174 | (const_int -1)))]) | |
14175 | (set (match_dup 0) | |
14176 | (match_dup 4)) | |
14177 | (set (pc) (if_then_else (match_dup 7) | |
14178 | (match_dup 5) | |
14179 | (match_dup 6)))] | |
1fd4e8c1 | 14180 | " |
0f4c242b KH |
14181 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14182 | operands[3], const0_rtx); }") | |
0ad91047 DE |
14183 | (define_split |
14184 | [(set (pc) | |
14185 | (if_then_else (match_operator 2 "comparison_operator" | |
14186 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14187 | (const_int 1)]) | |
61c07d3c DE |
14188 | (match_operand 5 "" "") |
14189 | (match_operand 6 "" ""))) | |
0ad91047 DE |
14190 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
14191 | (plus:DI (match_dup 1) | |
14192 | (const_int -1))) | |
14193 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 14194 | (clobber (match_scratch:DI 4 ""))] |
683bdff7 | 14195 | "TARGET_64BIT && reload_completed" |
0ad91047 DE |
14196 | [(parallel [(set (match_dup 3) |
14197 | (compare:CC (plus:DI (match_dup 1) | |
14198 | (const_int -1)) | |
14199 | (const_int 0))) | |
14200 | (set (match_dup 0) | |
14201 | (plus:DI (match_dup 1) | |
14202 | (const_int -1)))]) | |
61c07d3c DE |
14203 | (set (pc) (if_then_else (match_dup 7) |
14204 | (match_dup 5) | |
14205 | (match_dup 6)))] | |
0ad91047 | 14206 | " |
0f4c242b KH |
14207 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14208 | operands[3], const0_rtx); }") | |
0ad91047 DE |
14209 | |
14210 | (define_split | |
14211 | [(set (pc) | |
14212 | (if_then_else (match_operator 2 "comparison_operator" | |
14213 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14214 | (const_int 1)]) | |
61c07d3c DE |
14215 | (match_operand 5 "" "") |
14216 | (match_operand 6 "" ""))) | |
9ebbca7d | 14217 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
14218 | (plus:DI (match_dup 1) (const_int -1))) |
14219 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 14220 | (clobber (match_scratch:DI 4 ""))] |
683bdff7 | 14221 | "TARGET_64BIT && reload_completed |
0ad91047 DE |
14222 | && ! gpc_reg_operand (operands[0], DImode)" |
14223 | [(parallel [(set (match_dup 3) | |
14224 | (compare:CC (plus:DI (match_dup 1) | |
14225 | (const_int -1)) | |
14226 | (const_int 0))) | |
14227 | (set (match_dup 4) | |
14228 | (plus:DI (match_dup 1) | |
14229 | (const_int -1)))]) | |
14230 | (set (match_dup 0) | |
14231 | (match_dup 4)) | |
61c07d3c DE |
14232 | (set (pc) (if_then_else (match_dup 7) |
14233 | (match_dup 5) | |
14234 | (match_dup 6)))] | |
0ad91047 | 14235 | " |
0f4c242b KH |
14236 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14237 | operands[3], const0_rtx); }") | |
e0cd0770 JC |
14238 | \f |
14239 | (define_insn "trap" | |
14240 | [(trap_if (const_int 1) (const_int 0))] | |
14241 | "" | |
14242 | "{t 31,0,0|trap}") | |
14243 | ||
14244 | (define_expand "conditional_trap" | |
14245 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14246 | [(match_dup 2) (match_dup 3)]) | |
14247 | (match_operand 1 "const_int_operand" ""))] | |
14248 | "" | |
14249 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
14250 | operands[2] = rs6000_compare_op0; | |
14251 | operands[3] = rs6000_compare_op1;") | |
14252 | ||
14253 | (define_insn "" | |
14254 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14255 | [(match_operand:SI 1 "register_operand" "r") | |
14256 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
14257 | (const_int 0))] | |
14258 | "" | |
a157febd GK |
14259 | "{t|tw}%V0%I2 %1,%2") |
14260 | ||
14261 | (define_insn "" | |
14262 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14263 | [(match_operand:DI 1 "register_operand" "r") | |
14264 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
14265 | (const_int 0))] | |
14266 | "TARGET_POWERPC64" | |
14267 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
14268 | \f |
14269 | ;; Insns related to generating the function prologue and epilogue. | |
14270 | ||
14271 | (define_expand "prologue" | |
14272 | [(use (const_int 0))] | |
14273 | "TARGET_SCHED_PROLOG" | |
14274 | " | |
14275 | { | |
14276 | rs6000_emit_prologue (); | |
14277 | DONE; | |
14278 | }") | |
14279 | ||
2c4a9cff DE |
14280 | (define_insn "*movesi_from_cr_one" |
14281 | [(match_parallel 0 "mfcr_operation" | |
14282 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14283 | (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y") | |
14284 | (match_operand 3 "immediate_operand" "n")] | |
14285 | UNSPEC_MOVESI_FROM_CR))])] | |
14286 | "TARGET_MFCRF" | |
14287 | "* | |
14288 | { | |
14289 | int mask = 0; | |
14290 | int i; | |
14291 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14292 | { | |
14293 | mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14294 | operands[4] = GEN_INT (mask); | |
14295 | output_asm_insn (\"mfcr %1,%4\", operands); | |
14296 | } | |
14297 | return \"\"; | |
14298 | }" | |
14299 | [(set_attr "type" "mfcrf")]) | |
14300 | ||
9ebbca7d GK |
14301 | (define_insn "movesi_from_cr" |
14302 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 14303 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) |
615158e2 JJ |
14304 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] |
14305 | UNSPEC_MOVESI_FROM_CR))] | |
9ebbca7d | 14306 | "" |
309323c2 | 14307 | "mfcr %0" |
b54cf83a | 14308 | [(set_attr "type" "mfcr")]) |
9ebbca7d GK |
14309 | |
14310 | (define_insn "*stmw" | |
e033a023 DE |
14311 | [(match_parallel 0 "stmw_operation" |
14312 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
14313 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
14314 | "TARGET_MULTIPLE" | |
14315 | "{stm|stmw} %2,%1") | |
6ae08853 | 14316 | |
9ebbca7d | 14317 | (define_insn "*save_fpregs_si" |
e033a023 DE |
14318 | [(match_parallel 0 "any_operand" |
14319 | [(clobber (match_operand:SI 1 "register_operand" "=l")) | |
14320 | (use (match_operand:SI 2 "call_operand" "s")) | |
14321 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14322 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14323 | "TARGET_32BIT" | |
14324 | "bl %z2" | |
14325 | [(set_attr "type" "branch") | |
14326 | (set_attr "length" "4")]) | |
9ebbca7d GK |
14327 | |
14328 | (define_insn "*save_fpregs_di" | |
e033a023 DE |
14329 | [(match_parallel 0 "any_operand" |
14330 | [(clobber (match_operand:DI 1 "register_operand" "=l")) | |
14331 | (use (match_operand:DI 2 "call_operand" "s")) | |
14332 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14333 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14334 | "TARGET_64BIT" | |
14335 | "bl %z2" | |
14336 | [(set_attr "type" "branch") | |
14337 | (set_attr "length" "4")]) | |
9ebbca7d GK |
14338 | |
14339 | ; These are to explain that changes to the stack pointer should | |
14340 | ; not be moved over stores to stack memory. | |
14341 | (define_insn "stack_tie" | |
14342 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
615158e2 | 14343 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] |
9ebbca7d GK |
14344 | "" |
14345 | "" | |
14346 | [(set_attr "length" "0")]) | |
14347 | ||
14348 | ||
14349 | (define_expand "epilogue" | |
14350 | [(use (const_int 0))] | |
14351 | "TARGET_SCHED_PROLOG" | |
14352 | " | |
14353 | { | |
14354 | rs6000_emit_epilogue (FALSE); | |
14355 | DONE; | |
14356 | }") | |
14357 | ||
14358 | ; On some processors, doing the mtcrf one CC register at a time is | |
14359 | ; faster (like on the 604e). On others, doing them all at once is | |
14360 | ; faster; for instance, on the 601 and 750. | |
14361 | ||
14362 | (define_expand "movsi_to_cr_one" | |
35aba846 DE |
14363 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14364 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 | 14365 | (match_dup 2)] UNSPEC_MOVESI_TO_CR))] |
35aba846 DE |
14366 | "" |
14367 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
9ebbca7d GK |
14368 | |
14369 | (define_insn "*movsi_to_cr" | |
35aba846 DE |
14370 | [(match_parallel 0 "mtcrf_operation" |
14371 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") | |
14372 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
14373 | (match_operand 3 "immediate_operand" "n")] | |
615158e2 | 14374 | UNSPEC_MOVESI_TO_CR))])] |
9ebbca7d | 14375 | "" |
e35b9579 GK |
14376 | "* |
14377 | { | |
14378 | int mask = 0; | |
14379 | int i; | |
14380 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14381 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14382 | operands[4] = GEN_INT (mask); | |
14383 | return \"mtcrf %4,%2\"; | |
309323c2 | 14384 | }" |
b54cf83a | 14385 | [(set_attr "type" "mtcr")]) |
9ebbca7d | 14386 | |
b54cf83a | 14387 | (define_insn "*mtcrfsi" |
309323c2 DE |
14388 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14389 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 JJ |
14390 | (match_operand 2 "immediate_operand" "n")] |
14391 | UNSPEC_MOVESI_TO_CR))] | |
6ae08853 | 14392 | "GET_CODE (operands[0]) == REG |
309323c2 DE |
14393 | && CR_REGNO_P (REGNO (operands[0])) |
14394 | && GET_CODE (operands[2]) == CONST_INT | |
14395 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
14396 | "mtcrf %R0,%1" | |
b54cf83a | 14397 | [(set_attr "type" "mtcr")]) |
9ebbca7d GK |
14398 | |
14399 | ; The load-multiple instructions have similar properties. | |
14400 | ; Note that "load_multiple" is a name known to the machine-independent | |
14401 | ; code that actually corresponds to the powerpc load-string. | |
14402 | ||
14403 | (define_insn "*lmw" | |
35aba846 DE |
14404 | [(match_parallel 0 "lmw_operation" |
14405 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14406 | (match_operand:SI 2 "memory_operand" "m"))])] | |
14407 | "TARGET_MULTIPLE" | |
14408 | "{lm|lmw} %1,%2") | |
6ae08853 | 14409 | |
9ebbca7d | 14410 | (define_insn "*return_internal_si" |
e35b9579 GK |
14411 | [(return) |
14412 | (use (match_operand:SI 0 "register_operand" "lc"))] | |
9ebbca7d | 14413 | "TARGET_32BIT" |
cccf3bdc | 14414 | "b%T0" |
9ebbca7d GK |
14415 | [(set_attr "type" "jmpreg")]) |
14416 | ||
14417 | (define_insn "*return_internal_di" | |
e35b9579 GK |
14418 | [(return) |
14419 | (use (match_operand:DI 0 "register_operand" "lc"))] | |
9ebbca7d | 14420 | "TARGET_64BIT" |
cccf3bdc | 14421 | "b%T0" |
9ebbca7d GK |
14422 | [(set_attr "type" "jmpreg")]) |
14423 | ||
14424 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
14425 | ; stuff was in GCC. Oh, and "any_operand" is a bit flexible... | |
14426 | ||
14427 | (define_insn "*return_and_restore_fpregs_si" | |
14428 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
14429 | [(return) |
14430 | (use (match_operand:SI 1 "register_operand" "l")) | |
9ebbca7d GK |
14431 | (use (match_operand:SI 2 "call_operand" "s")) |
14432 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14433 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14434 | "TARGET_32BIT" | |
14435 | "b %z2") | |
14436 | ||
14437 | (define_insn "*return_and_restore_fpregs_di" | |
14438 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
14439 | [(return) |
14440 | (use (match_operand:DI 1 "register_operand" "l")) | |
9ebbca7d GK |
14441 | (use (match_operand:DI 2 "call_operand" "s")) |
14442 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14443 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14444 | "TARGET_64BIT" | |
14445 | "b %z2") | |
14446 | ||
83720594 RH |
14447 | ; This is used in compiling the unwind routines. |
14448 | (define_expand "eh_return" | |
34dc173c | 14449 | [(use (match_operand 0 "general_operand" ""))] |
9ebbca7d GK |
14450 | "" |
14451 | " | |
14452 | { | |
83720594 | 14453 | if (TARGET_32BIT) |
34dc173c | 14454 | emit_insn (gen_eh_set_lr_si (operands[0])); |
9ebbca7d | 14455 | else |
34dc173c | 14456 | emit_insn (gen_eh_set_lr_di (operands[0])); |
9ebbca7d GK |
14457 | DONE; |
14458 | }") | |
14459 | ||
83720594 RH |
14460 | ; We can't expand this before we know where the link register is stored. |
14461 | (define_insn "eh_set_lr_si" | |
615158e2 JJ |
14462 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] |
14463 | UNSPECV_EH_RR) | |
466eb3e0 | 14464 | (clobber (match_scratch:SI 1 "=&b"))] |
83720594 RH |
14465 | "TARGET_32BIT" |
14466 | "#") | |
14467 | ||
14468 | (define_insn "eh_set_lr_di" | |
615158e2 JJ |
14469 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
14470 | UNSPECV_EH_RR) | |
466eb3e0 | 14471 | (clobber (match_scratch:DI 1 "=&b"))] |
83720594 RH |
14472 | "TARGET_64BIT" |
14473 | "#") | |
9ebbca7d GK |
14474 | |
14475 | (define_split | |
615158e2 | 14476 | [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) |
83720594 RH |
14477 | (clobber (match_scratch 1 ""))] |
14478 | "reload_completed" | |
14479 | [(const_int 0)] | |
9ebbca7d GK |
14480 | " |
14481 | { | |
d1d0c603 | 14482 | rs6000_emit_eh_reg_restore (operands[0], operands[1]); |
83720594 RH |
14483 | DONE; |
14484 | }") | |
0ac081f6 | 14485 | |
01a2ccd0 DE |
14486 | (define_insn "prefetch" |
14487 | [(prefetch (match_operand:V4SI 0 "address_operand" "p") | |
6041bf2f DE |
14488 | (match_operand:SI 1 "const_int_operand" "n") |
14489 | (match_operand:SI 2 "const_int_operand" "n"))] | |
01a2ccd0 | 14490 | "TARGET_POWERPC" |
6041bf2f DE |
14491 | "* |
14492 | { | |
01a2ccd0 DE |
14493 | if (GET_CODE (operands[0]) == REG) |
14494 | return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; | |
14495 | return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; | |
6041bf2f DE |
14496 | }" |
14497 | [(set_attr "type" "load")]) | |
a3170dc6 | 14498 | |
10ed84db | 14499 | (include "altivec.md") |
a3170dc6 | 14500 | (include "spe.md") |