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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
d24652ee | 2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
409f61cd | 3 | ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 | 5 | |
5de601cf | 6 | ;; This file is part of GCC. |
1fd4e8c1 | 7 | |
5de601cf NC |
8 | ;; GCC is free software; you can redistribute it and/or modify it |
9 | ;; under the terms of the GNU General Public License as published | |
10 | ;; by the Free Software Foundation; either version 2, or (at your | |
11 | ;; option) any later version. | |
1fd4e8c1 | 12 | |
5de601cf NC |
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | ;; License for more details. | |
1fd4e8c1 RK |
17 | |
18 | ;; You should have received a copy of the GNU General Public License | |
5de601cf | 19 | ;; along with GCC; see the file COPYING. If not, write to the |
39d14dda KC |
20 | ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, |
21 | ;; MA 02110-1301, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d | 24 | |
615158e2 JJ |
25 | ;; |
26 | ;; UNSPEC usage | |
27 | ;; | |
28 | ||
29 | (define_constants | |
30 | [(UNSPEC_FRSP 0) ; frsp for POWER machines | |
31 | (UNSPEC_TIE 5) ; tie stack contents and stack pointer | |
32 | (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC | |
33 | (UNSPEC_TOC 7) ; address of the TOC (more-or-less) | |
34 | (UNSPEC_MOVSI_GOT 8) | |
35 | (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit | |
36 | (UNSPEC_FCTIWZ 10) | |
37 | (UNSPEC_LD_MPIC 15) ; load_macho_picbase | |
38 | (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic | |
39 | (UNSPEC_TLSGD 17) | |
40 | (UNSPEC_TLSLD 18) | |
41 | (UNSPEC_MOVESI_FROM_CR 19) | |
42 | (UNSPEC_MOVESI_TO_CR 20) | |
43 | (UNSPEC_TLSDTPREL 21) | |
44 | (UNSPEC_TLSDTPRELHA 22) | |
45 | (UNSPEC_TLSDTPRELLO 23) | |
46 | (UNSPEC_TLSGOTDTPREL 24) | |
47 | (UNSPEC_TLSTPREL 25) | |
48 | (UNSPEC_TLSTPRELHA 26) | |
49 | (UNSPEC_TLSTPRELLO 27) | |
50 | (UNSPEC_TLSGOTTPREL 28) | |
51 | (UNSPEC_TLSTLS 29) | |
ecb62ae7 | 52 | (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero |
64022b5d | 53 | (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit |
da4c340c | 54 | (UNSPEC_STFIWX 32) |
9f0076e5 DE |
55 | (UNSPEC_POPCNTB 33) |
56 | (UNSPEC_FRES 34) | |
57 | (UNSPEC_SP_SET 35) | |
58 | (UNSPEC_SP_TEST 36) | |
59 | (UNSPEC_SYNC 37) | |
60 | (UNSPEC_LWSYNC 38) | |
61 | (UNSPEC_ISYNC 39) | |
62 | (UNSPEC_SYNC_OP 40) | |
63 | (UNSPEC_ATOMIC 41) | |
64 | (UNSPEC_CMPXCHG 42) | |
65 | (UNSPEC_XCHG 43) | |
66 | (UNSPEC_AND 44) | |
615158e2 JJ |
67 | ]) |
68 | ||
69 | ;; | |
70 | ;; UNSPEC_VOLATILE usage | |
71 | ;; | |
72 | ||
73 | (define_constants | |
74 | [(UNSPECV_BLOCK 0) | |
b52110d4 DE |
75 | (UNSPECV_LL 1) ; load-locked |
76 | (UNSPECV_SC 2) ; store-conditional | |
615158e2 JJ |
77 | (UNSPECV_EH_RR 9) ; eh_reg_restore |
78 | ]) | |
1fd4e8c1 RK |
79 | \f |
80 | ;; Define an insn type attribute. This is used in function unit delay | |
81 | ;; computations. | |
b52110d4 | 82 | (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c" |
1fd4e8c1 RK |
83 | (const_string "integer")) |
84 | ||
b19003d8 | 85 | ;; Length (in bytes). |
6ae08853 | 86 | ; '(pc)' in the following doesn't include the instruction itself; it is |
6cbadf36 | 87 | ; calculated as if the instruction had zero size. |
b19003d8 RK |
88 | (define_attr "length" "" |
89 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 90 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 91 | (const_int -32768)) |
6cbadf36 GK |
92 | (lt (minus (match_dup 0) (pc)) |
93 | (const_int 32764))) | |
39a10a29 GK |
94 | (const_int 4) |
95 | (const_int 8)) | |
b19003d8 RK |
96 | (const_int 4))) |
97 | ||
cfb557c4 RK |
98 | ;; Processor type -- this attribute must exactly match the processor_type |
99 | ;; enumeration in rs6000.h. | |
100 | ||
ec507f2d | 101 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5" |
cfb557c4 RK |
102 | (const (symbol_ref "rs6000_cpu_attr"))) |
103 | ||
b54cf83a DE |
104 | (automata_option "ndfa") |
105 | ||
106 | (include "rios1.md") | |
107 | (include "rios2.md") | |
108 | (include "rs64.md") | |
109 | (include "mpc.md") | |
110 | (include "40x.md") | |
02ca7595 | 111 | (include "440.md") |
b54cf83a DE |
112 | (include "603.md") |
113 | (include "6xx.md") | |
114 | (include "7xx.md") | |
115 | (include "7450.md") | |
5e8006fa | 116 | (include "8540.md") |
b54cf83a | 117 | (include "power4.md") |
ec507f2d | 118 | (include "power5.md") |
48d72335 DE |
119 | |
120 | (include "predicates.md") | |
121 | ||
ac9e2cff | 122 | (include "darwin.md") |
309323c2 | 123 | |
1fd4e8c1 | 124 | \f |
915167f5 GK |
125 | ;; Mode macros |
126 | ||
127 | ; This mode macro allows :GPR to be used to indicate the allowable size | |
128 | ; of whole values in GPRs. | |
129 | (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")]) | |
130 | ||
0354e5d8 | 131 | ; Any supported integer mode. |
915167f5 GK |
132 | (define_mode_macro INT [QI HI SI DI TI]) |
133 | ||
0354e5d8 | 134 | ; Any supported integer mode that fits in one register. |
915167f5 GK |
135 | (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")]) |
136 | ||
b5568f07 DE |
137 | ; extend modes for DImode |
138 | (define_mode_macro QHSI [QI HI SI]) | |
139 | ||
0354e5d8 GK |
140 | ; SImode or DImode, even if DImode doesn't fit in GPRs. |
141 | (define_mode_macro SDI [SI DI]) | |
142 | ||
143 | ; The size of a pointer. Also, the size of the value that a record-condition | |
144 | ; (one with a '.') will compare. | |
145 | (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")]) | |
2e6c9641 | 146 | |
4ae234b0 GK |
147 | ; Any hardware-supported floating-point mode |
148 | (define_mode_macro FP [(SF "TARGET_HARD_FLOAT") | |
149 | (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)") | |
150 | (TF "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
151 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")]) | |
152 | ||
915167f5 | 153 | ; Various instructions that come in SI and DI forms. |
0354e5d8 | 154 | ; A generic w/d attribute, for things like cmpw/cmpd. |
b5568f07 DE |
155 | (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")]) |
156 | ||
157 | ; DImode bits | |
158 | (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")]) | |
915167f5 GK |
159 | |
160 | \f | |
1fd4e8c1 RK |
161 | ;; Start with fixed-point load and store insns. Here we put only the more |
162 | ;; complex forms. Basic data transfer is done later. | |
163 | ||
b5568f07 | 164 | (define_expand "zero_extend<mode>di2" |
51b8fc2c | 165 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
b5568f07 | 166 | (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))] |
51b8fc2c RK |
167 | "TARGET_POWERPC64" |
168 | "") | |
169 | ||
b5568f07 | 170 | (define_insn "*zero_extend<mode>di2_internal1" |
51b8fc2c | 171 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
b5568f07 | 172 | (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))] |
51b8fc2c RK |
173 | "TARGET_POWERPC64" |
174 | "@ | |
b5568f07 DE |
175 | l<wd>z%U1%X1 %0,%1 |
176 | rldicl %0,%1,0,<dbits>" | |
51b8fc2c RK |
177 | [(set_attr "type" "load,*")]) |
178 | ||
b5568f07 | 179 | (define_insn "*zero_extend<mode>di2_internal2" |
9ebbca7d | 180 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
b5568f07 | 181 | (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r")) |
815cdc52 | 182 | (const_int 0))) |
9ebbca7d | 183 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 184 | "TARGET_64BIT" |
9ebbca7d | 185 | "@ |
b5568f07 | 186 | rldicl. %2,%1,0,<dbits> |
9ebbca7d GK |
187 | #" |
188 | [(set_attr "type" "compare") | |
189 | (set_attr "length" "4,8")]) | |
190 | ||
191 | (define_split | |
192 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
b5568f07 | 193 | (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")) |
9ebbca7d GK |
194 | (const_int 0))) |
195 | (clobber (match_scratch:DI 2 ""))] | |
196 | "TARGET_POWERPC64 && reload_completed" | |
197 | [(set (match_dup 2) | |
198 | (zero_extend:DI (match_dup 1))) | |
199 | (set (match_dup 0) | |
200 | (compare:CC (match_dup 2) | |
201 | (const_int 0)))] | |
202 | "") | |
51b8fc2c | 203 | |
b5568f07 | 204 | (define_insn "*zero_extend<mode>di2_internal3" |
9ebbca7d | 205 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
b5568f07 | 206 | (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r")) |
51b8fc2c | 207 | (const_int 0))) |
9ebbca7d | 208 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 209 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 210 | "TARGET_64BIT" |
9ebbca7d | 211 | "@ |
b5568f07 | 212 | rldicl. %0,%1,0,<dbits> |
9ebbca7d GK |
213 | #" |
214 | [(set_attr "type" "compare") | |
215 | (set_attr "length" "4,8")]) | |
216 | ||
217 | (define_split | |
218 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
b5568f07 | 219 | (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")) |
9ebbca7d GK |
220 | (const_int 0))) |
221 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
222 | (zero_extend:DI (match_dup 1)))] | |
223 | "TARGET_POWERPC64 && reload_completed" | |
224 | [(set (match_dup 0) | |
225 | (zero_extend:DI (match_dup 1))) | |
226 | (set (match_dup 2) | |
227 | (compare:CC (match_dup 0) | |
228 | (const_int 0)))] | |
229 | "") | |
51b8fc2c | 230 | |
2bee0449 RK |
231 | (define_insn "extendqidi2" |
232 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
233 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 234 | "TARGET_POWERPC64" |
2bee0449 | 235 | "extsb %0,%1") |
51b8fc2c RK |
236 | |
237 | (define_insn "" | |
9ebbca7d GK |
238 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
239 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 240 | (const_int 0))) |
9ebbca7d | 241 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 242 | "TARGET_64BIT" |
9ebbca7d GK |
243 | "@ |
244 | extsb. %2,%1 | |
245 | #" | |
246 | [(set_attr "type" "compare") | |
247 | (set_attr "length" "4,8")]) | |
248 | ||
249 | (define_split | |
250 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
251 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
252 | (const_int 0))) | |
253 | (clobber (match_scratch:DI 2 ""))] | |
254 | "TARGET_POWERPC64 && reload_completed" | |
255 | [(set (match_dup 2) | |
256 | (sign_extend:DI (match_dup 1))) | |
257 | (set (match_dup 0) | |
258 | (compare:CC (match_dup 2) | |
259 | (const_int 0)))] | |
260 | "") | |
51b8fc2c RK |
261 | |
262 | (define_insn "" | |
9ebbca7d GK |
263 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
264 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 265 | (const_int 0))) |
9ebbca7d | 266 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 267 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 268 | "TARGET_64BIT" |
9ebbca7d GK |
269 | "@ |
270 | extsb. %0,%1 | |
271 | #" | |
272 | [(set_attr "type" "compare") | |
273 | (set_attr "length" "4,8")]) | |
274 | ||
275 | (define_split | |
276 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
277 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
278 | (const_int 0))) | |
279 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
280 | (sign_extend:DI (match_dup 1)))] | |
281 | "TARGET_POWERPC64 && reload_completed" | |
282 | [(set (match_dup 0) | |
283 | (sign_extend:DI (match_dup 1))) | |
284 | (set (match_dup 2) | |
285 | (compare:CC (match_dup 0) | |
286 | (const_int 0)))] | |
287 | "") | |
51b8fc2c | 288 | |
51b8fc2c RK |
289 | (define_expand "extendhidi2" |
290 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
291 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
292 | "TARGET_POWERPC64" | |
293 | "") | |
294 | ||
295 | (define_insn "" | |
296 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
297 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
298 | "TARGET_POWERPC64" | |
299 | "@ | |
300 | lha%U1%X1 %0,%1 | |
301 | extsh %0,%1" | |
b54cf83a | 302 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
303 | |
304 | (define_insn "" | |
9ebbca7d GK |
305 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
306 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 307 | (const_int 0))) |
9ebbca7d | 308 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 309 | "TARGET_64BIT" |
9ebbca7d GK |
310 | "@ |
311 | extsh. %2,%1 | |
312 | #" | |
313 | [(set_attr "type" "compare") | |
314 | (set_attr "length" "4,8")]) | |
315 | ||
316 | (define_split | |
317 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
318 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
319 | (const_int 0))) | |
320 | (clobber (match_scratch:DI 2 ""))] | |
321 | "TARGET_POWERPC64 && reload_completed" | |
322 | [(set (match_dup 2) | |
323 | (sign_extend:DI (match_dup 1))) | |
324 | (set (match_dup 0) | |
325 | (compare:CC (match_dup 2) | |
326 | (const_int 0)))] | |
327 | "") | |
51b8fc2c RK |
328 | |
329 | (define_insn "" | |
9ebbca7d GK |
330 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
331 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 332 | (const_int 0))) |
9ebbca7d | 333 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 334 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 335 | "TARGET_64BIT" |
9ebbca7d GK |
336 | "@ |
337 | extsh. %0,%1 | |
338 | #" | |
339 | [(set_attr "type" "compare") | |
340 | (set_attr "length" "4,8")]) | |
341 | ||
342 | (define_split | |
343 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
344 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
345 | (const_int 0))) | |
346 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
347 | (sign_extend:DI (match_dup 1)))] | |
348 | "TARGET_POWERPC64 && reload_completed" | |
349 | [(set (match_dup 0) | |
350 | (sign_extend:DI (match_dup 1))) | |
351 | (set (match_dup 2) | |
352 | (compare:CC (match_dup 0) | |
353 | (const_int 0)))] | |
354 | "") | |
51b8fc2c | 355 | |
51b8fc2c RK |
356 | (define_expand "extendsidi2" |
357 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
358 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
359 | "TARGET_POWERPC64" | |
360 | "") | |
361 | ||
362 | (define_insn "" | |
363 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 364 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
365 | "TARGET_POWERPC64" |
366 | "@ | |
367 | lwa%U1%X1 %0,%1 | |
368 | extsw %0,%1" | |
b54cf83a | 369 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
370 | |
371 | (define_insn "" | |
9ebbca7d GK |
372 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
373 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 374 | (const_int 0))) |
9ebbca7d | 375 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 376 | "TARGET_64BIT" |
9ebbca7d GK |
377 | "@ |
378 | extsw. %2,%1 | |
379 | #" | |
380 | [(set_attr "type" "compare") | |
381 | (set_attr "length" "4,8")]) | |
382 | ||
383 | (define_split | |
384 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
385 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
386 | (const_int 0))) | |
387 | (clobber (match_scratch:DI 2 ""))] | |
388 | "TARGET_POWERPC64 && reload_completed" | |
389 | [(set (match_dup 2) | |
390 | (sign_extend:DI (match_dup 1))) | |
391 | (set (match_dup 0) | |
392 | (compare:CC (match_dup 2) | |
393 | (const_int 0)))] | |
394 | "") | |
51b8fc2c RK |
395 | |
396 | (define_insn "" | |
9ebbca7d GK |
397 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
398 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 399 | (const_int 0))) |
9ebbca7d | 400 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 401 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 402 | "TARGET_64BIT" |
9ebbca7d GK |
403 | "@ |
404 | extsw. %0,%1 | |
405 | #" | |
406 | [(set_attr "type" "compare") | |
407 | (set_attr "length" "4,8")]) | |
408 | ||
409 | (define_split | |
410 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
411 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
412 | (const_int 0))) | |
413 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
414 | (sign_extend:DI (match_dup 1)))] | |
415 | "TARGET_POWERPC64 && reload_completed" | |
416 | [(set (match_dup 0) | |
417 | (sign_extend:DI (match_dup 1))) | |
418 | (set (match_dup 2) | |
419 | (compare:CC (match_dup 0) | |
420 | (const_int 0)))] | |
421 | "") | |
51b8fc2c | 422 | |
1fd4e8c1 | 423 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
424 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
425 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
426 | "" |
427 | "") | |
428 | ||
429 | (define_insn "" | |
cd2b37d9 | 430 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
431 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
432 | "" | |
433 | "@ | |
434 | lbz%U1%X1 %0,%1 | |
005a35b9 | 435 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
436 | [(set_attr "type" "load,*")]) |
437 | ||
438 | (define_insn "" | |
9ebbca7d GK |
439 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
440 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 441 | (const_int 0))) |
9ebbca7d | 442 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 443 | "" |
9ebbca7d GK |
444 | "@ |
445 | {andil.|andi.} %2,%1,0xff | |
446 | #" | |
447 | [(set_attr "type" "compare") | |
448 | (set_attr "length" "4,8")]) | |
449 | ||
450 | (define_split | |
451 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
452 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
453 | (const_int 0))) | |
454 | (clobber (match_scratch:SI 2 ""))] | |
455 | "reload_completed" | |
456 | [(set (match_dup 2) | |
457 | (zero_extend:SI (match_dup 1))) | |
458 | (set (match_dup 0) | |
459 | (compare:CC (match_dup 2) | |
460 | (const_int 0)))] | |
461 | "") | |
1fd4e8c1 RK |
462 | |
463 | (define_insn "" | |
9ebbca7d GK |
464 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
465 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 466 | (const_int 0))) |
9ebbca7d | 467 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
468 | (zero_extend:SI (match_dup 1)))] |
469 | "" | |
9ebbca7d GK |
470 | "@ |
471 | {andil.|andi.} %0,%1,0xff | |
472 | #" | |
473 | [(set_attr "type" "compare") | |
474 | (set_attr "length" "4,8")]) | |
475 | ||
476 | (define_split | |
477 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
478 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
479 | (const_int 0))) | |
480 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
481 | (zero_extend:SI (match_dup 1)))] | |
482 | "reload_completed" | |
483 | [(set (match_dup 0) | |
484 | (zero_extend:SI (match_dup 1))) | |
485 | (set (match_dup 2) | |
486 | (compare:CC (match_dup 0) | |
487 | (const_int 0)))] | |
488 | "") | |
1fd4e8c1 | 489 | |
51b8fc2c RK |
490 | (define_expand "extendqisi2" |
491 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
492 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
493 | "" | |
494 | " | |
495 | { | |
496 | if (TARGET_POWERPC) | |
497 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
498 | else if (TARGET_POWER) | |
499 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
500 | else | |
501 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
502 | DONE; | |
503 | }") | |
504 | ||
505 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
506 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
507 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 508 | "TARGET_POWERPC" |
2bee0449 | 509 | "extsb %0,%1") |
51b8fc2c RK |
510 | |
511 | (define_insn "" | |
9ebbca7d GK |
512 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
513 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 514 | (const_int 0))) |
9ebbca7d | 515 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 516 | "TARGET_POWERPC" |
9ebbca7d GK |
517 | "@ |
518 | extsb. %2,%1 | |
519 | #" | |
520 | [(set_attr "type" "compare") | |
521 | (set_attr "length" "4,8")]) | |
522 | ||
523 | (define_split | |
524 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
525 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
526 | (const_int 0))) | |
527 | (clobber (match_scratch:SI 2 ""))] | |
528 | "TARGET_POWERPC && reload_completed" | |
529 | [(set (match_dup 2) | |
530 | (sign_extend:SI (match_dup 1))) | |
531 | (set (match_dup 0) | |
532 | (compare:CC (match_dup 2) | |
533 | (const_int 0)))] | |
534 | "") | |
51b8fc2c RK |
535 | |
536 | (define_insn "" | |
9ebbca7d GK |
537 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
538 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 539 | (const_int 0))) |
9ebbca7d | 540 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
541 | (sign_extend:SI (match_dup 1)))] |
542 | "TARGET_POWERPC" | |
9ebbca7d GK |
543 | "@ |
544 | extsb. %0,%1 | |
545 | #" | |
546 | [(set_attr "type" "compare") | |
547 | (set_attr "length" "4,8")]) | |
548 | ||
549 | (define_split | |
550 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
551 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
552 | (const_int 0))) | |
553 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
554 | (sign_extend:SI (match_dup 1)))] | |
555 | "TARGET_POWERPC && reload_completed" | |
556 | [(set (match_dup 0) | |
557 | (sign_extend:SI (match_dup 1))) | |
558 | (set (match_dup 2) | |
559 | (compare:CC (match_dup 0) | |
560 | (const_int 0)))] | |
561 | "") | |
51b8fc2c RK |
562 | |
563 | (define_expand "extendqisi2_power" | |
564 | [(parallel [(set (match_dup 2) | |
565 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
566 | (const_int 24))) | |
567 | (clobber (scratch:SI))]) | |
568 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
569 | (ashiftrt:SI (match_dup 2) | |
570 | (const_int 24))) | |
571 | (clobber (scratch:SI))])] | |
572 | "TARGET_POWER" | |
573 | " | |
574 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
575 | operands[2] = gen_reg_rtx (SImode); }") | |
576 | ||
577 | (define_expand "extendqisi2_no_power" | |
578 | [(set (match_dup 2) | |
579 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
580 | (const_int 24))) | |
581 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
582 | (ashiftrt:SI (match_dup 2) | |
583 | (const_int 24)))] | |
584 | "! TARGET_POWER && ! TARGET_POWERPC" | |
585 | " | |
586 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
587 | operands[2] = gen_reg_rtx (SImode); }") | |
588 | ||
1fd4e8c1 | 589 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
590 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
591 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
592 | "" |
593 | "") | |
594 | ||
595 | (define_insn "" | |
cd2b37d9 | 596 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
597 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
598 | "" | |
599 | "@ | |
600 | lbz%U1%X1 %0,%1 | |
005a35b9 | 601 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
602 | [(set_attr "type" "load,*")]) |
603 | ||
604 | (define_insn "" | |
9ebbca7d GK |
605 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
606 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 607 | (const_int 0))) |
9ebbca7d | 608 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 609 | "" |
9ebbca7d GK |
610 | "@ |
611 | {andil.|andi.} %2,%1,0xff | |
612 | #" | |
613 | [(set_attr "type" "compare") | |
614 | (set_attr "length" "4,8")]) | |
615 | ||
616 | (define_split | |
617 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
618 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
619 | (const_int 0))) | |
620 | (clobber (match_scratch:HI 2 ""))] | |
621 | "reload_completed" | |
622 | [(set (match_dup 2) | |
623 | (zero_extend:HI (match_dup 1))) | |
624 | (set (match_dup 0) | |
625 | (compare:CC (match_dup 2) | |
626 | (const_int 0)))] | |
627 | "") | |
1fd4e8c1 | 628 | |
51b8fc2c | 629 | (define_insn "" |
9ebbca7d GK |
630 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
631 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 632 | (const_int 0))) |
9ebbca7d | 633 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
634 | (zero_extend:HI (match_dup 1)))] |
635 | "" | |
9ebbca7d GK |
636 | "@ |
637 | {andil.|andi.} %0,%1,0xff | |
638 | #" | |
639 | [(set_attr "type" "compare") | |
640 | (set_attr "length" "4,8")]) | |
641 | ||
642 | (define_split | |
643 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
644 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
645 | (const_int 0))) | |
646 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
647 | (zero_extend:HI (match_dup 1)))] | |
648 | "reload_completed" | |
649 | [(set (match_dup 0) | |
650 | (zero_extend:HI (match_dup 1))) | |
651 | (set (match_dup 2) | |
652 | (compare:CC (match_dup 0) | |
653 | (const_int 0)))] | |
654 | "") | |
815cdc52 MM |
655 | |
656 | (define_expand "extendqihi2" | |
657 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
658 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
659 | "" | |
660 | " | |
661 | { | |
662 | if (TARGET_POWERPC) | |
663 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
664 | else if (TARGET_POWER) | |
665 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
666 | else | |
667 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
668 | DONE; | |
669 | }") | |
670 | ||
671 | (define_insn "extendqihi2_ppc" | |
672 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
673 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
674 | "TARGET_POWERPC" | |
675 | "extsb %0,%1") | |
676 | ||
677 | (define_insn "" | |
9ebbca7d GK |
678 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
679 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 680 | (const_int 0))) |
9ebbca7d | 681 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 682 | "TARGET_POWERPC" |
9ebbca7d GK |
683 | "@ |
684 | extsb. %2,%1 | |
685 | #" | |
686 | [(set_attr "type" "compare") | |
687 | (set_attr "length" "4,8")]) | |
688 | ||
689 | (define_split | |
690 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
691 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
692 | (const_int 0))) | |
693 | (clobber (match_scratch:HI 2 ""))] | |
694 | "TARGET_POWERPC && reload_completed" | |
695 | [(set (match_dup 2) | |
696 | (sign_extend:HI (match_dup 1))) | |
697 | (set (match_dup 0) | |
698 | (compare:CC (match_dup 2) | |
699 | (const_int 0)))] | |
700 | "") | |
815cdc52 MM |
701 | |
702 | (define_insn "" | |
9ebbca7d GK |
703 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
704 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 705 | (const_int 0))) |
9ebbca7d | 706 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
707 | (sign_extend:HI (match_dup 1)))] |
708 | "TARGET_POWERPC" | |
9ebbca7d GK |
709 | "@ |
710 | extsb. %0,%1 | |
711 | #" | |
712 | [(set_attr "type" "compare") | |
713 | (set_attr "length" "4,8")]) | |
714 | ||
715 | (define_split | |
716 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
717 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
718 | (const_int 0))) | |
719 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
720 | (sign_extend:HI (match_dup 1)))] | |
721 | "TARGET_POWERPC && reload_completed" | |
722 | [(set (match_dup 0) | |
723 | (sign_extend:HI (match_dup 1))) | |
724 | (set (match_dup 2) | |
725 | (compare:CC (match_dup 0) | |
726 | (const_int 0)))] | |
727 | "") | |
51b8fc2c RK |
728 | |
729 | (define_expand "extendqihi2_power" | |
730 | [(parallel [(set (match_dup 2) | |
731 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
732 | (const_int 24))) | |
733 | (clobber (scratch:SI))]) | |
734 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
735 | (ashiftrt:SI (match_dup 2) | |
736 | (const_int 24))) | |
737 | (clobber (scratch:SI))])] | |
738 | "TARGET_POWER" | |
739 | " | |
740 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
741 | operands[1] = gen_lowpart (SImode, operands[1]); | |
742 | operands[2] = gen_reg_rtx (SImode); }") | |
743 | ||
744 | (define_expand "extendqihi2_no_power" | |
745 | [(set (match_dup 2) | |
746 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
747 | (const_int 24))) | |
748 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
749 | (ashiftrt:SI (match_dup 2) | |
750 | (const_int 24)))] | |
751 | "! TARGET_POWER && ! TARGET_POWERPC" | |
752 | " | |
753 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
754 | operands[1] = gen_lowpart (SImode, operands[1]); | |
755 | operands[2] = gen_reg_rtx (SImode); }") | |
756 | ||
1fd4e8c1 | 757 | (define_expand "zero_extendhisi2" |
5f243543 | 758 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 759 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
760 | "" |
761 | "") | |
762 | ||
763 | (define_insn "" | |
cd2b37d9 | 764 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
765 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
766 | "" | |
767 | "@ | |
768 | lhz%U1%X1 %0,%1 | |
005a35b9 | 769 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
770 | [(set_attr "type" "load,*")]) |
771 | ||
772 | (define_insn "" | |
9ebbca7d GK |
773 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
774 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 775 | (const_int 0))) |
9ebbca7d | 776 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 777 | "" |
9ebbca7d GK |
778 | "@ |
779 | {andil.|andi.} %2,%1,0xffff | |
780 | #" | |
781 | [(set_attr "type" "compare") | |
782 | (set_attr "length" "4,8")]) | |
783 | ||
784 | (define_split | |
785 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
786 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
787 | (const_int 0))) | |
788 | (clobber (match_scratch:SI 2 ""))] | |
789 | "reload_completed" | |
790 | [(set (match_dup 2) | |
791 | (zero_extend:SI (match_dup 1))) | |
792 | (set (match_dup 0) | |
793 | (compare:CC (match_dup 2) | |
794 | (const_int 0)))] | |
795 | "") | |
1fd4e8c1 RK |
796 | |
797 | (define_insn "" | |
9ebbca7d GK |
798 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
799 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 800 | (const_int 0))) |
9ebbca7d | 801 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
802 | (zero_extend:SI (match_dup 1)))] |
803 | "" | |
9ebbca7d GK |
804 | "@ |
805 | {andil.|andi.} %0,%1,0xffff | |
806 | #" | |
807 | [(set_attr "type" "compare") | |
808 | (set_attr "length" "4,8")]) | |
809 | ||
810 | (define_split | |
811 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
812 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
813 | (const_int 0))) | |
814 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
815 | (zero_extend:SI (match_dup 1)))] | |
816 | "reload_completed" | |
817 | [(set (match_dup 0) | |
818 | (zero_extend:SI (match_dup 1))) | |
819 | (set (match_dup 2) | |
820 | (compare:CC (match_dup 0) | |
821 | (const_int 0)))] | |
822 | "") | |
1fd4e8c1 RK |
823 | |
824 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
825 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
826 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
827 | "" |
828 | "") | |
829 | ||
830 | (define_insn "" | |
cd2b37d9 | 831 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
832 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
833 | "" | |
834 | "@ | |
835 | lha%U1%X1 %0,%1 | |
ca7f5001 | 836 | {exts|extsh} %0,%1" |
b54cf83a | 837 | [(set_attr "type" "load_ext,*")]) |
1fd4e8c1 RK |
838 | |
839 | (define_insn "" | |
9ebbca7d GK |
840 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
841 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 842 | (const_int 0))) |
9ebbca7d | 843 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 844 | "" |
9ebbca7d GK |
845 | "@ |
846 | {exts.|extsh.} %2,%1 | |
847 | #" | |
848 | [(set_attr "type" "compare") | |
849 | (set_attr "length" "4,8")]) | |
850 | ||
851 | (define_split | |
852 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
853 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
854 | (const_int 0))) | |
855 | (clobber (match_scratch:SI 2 ""))] | |
856 | "reload_completed" | |
857 | [(set (match_dup 2) | |
858 | (sign_extend:SI (match_dup 1))) | |
859 | (set (match_dup 0) | |
860 | (compare:CC (match_dup 2) | |
861 | (const_int 0)))] | |
862 | "") | |
1fd4e8c1 RK |
863 | |
864 | (define_insn "" | |
9ebbca7d GK |
865 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
866 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 867 | (const_int 0))) |
9ebbca7d | 868 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
869 | (sign_extend:SI (match_dup 1)))] |
870 | "" | |
9ebbca7d GK |
871 | "@ |
872 | {exts.|extsh.} %0,%1 | |
873 | #" | |
874 | [(set_attr "type" "compare") | |
875 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 876 | \f |
9ebbca7d GK |
877 | (define_split |
878 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
879 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
880 | (const_int 0))) | |
881 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
882 | (sign_extend:SI (match_dup 1)))] | |
883 | "reload_completed" | |
884 | [(set (match_dup 0) | |
885 | (sign_extend:SI (match_dup 1))) | |
886 | (set (match_dup 2) | |
887 | (compare:CC (match_dup 0) | |
888 | (const_int 0)))] | |
889 | "") | |
890 | ||
1fd4e8c1 | 891 | ;; Fixed-point arithmetic insns. |
deb9225a | 892 | |
0354e5d8 GK |
893 | (define_expand "add<mode>3" |
894 | [(set (match_operand:SDI 0 "gpc_reg_operand" "") | |
895 | (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "") | |
4ae234b0 | 896 | (match_operand:SDI 2 "reg_or_add_cint_operand" "")))] |
7cd5235b MM |
897 | "" |
898 | " | |
899 | { | |
0354e5d8 GK |
900 | if (<MODE>mode == DImode && ! TARGET_POWERPC64) |
901 | { | |
902 | if (non_short_cint_operand (operands[2], DImode)) | |
903 | FAIL; | |
904 | } | |
905 | else if (GET_CODE (operands[2]) == CONST_INT | |
906 | && ! add_operand (operands[2], <MODE>mode)) | |
7cd5235b | 907 | { |
677a9668 | 908 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
0354e5d8 | 909 | ? operands[0] : gen_reg_rtx (<MODE>mode)); |
7cd5235b | 910 | |
2bfcf297 | 911 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 912 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
0354e5d8 GK |
913 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode); |
914 | ||
915 | if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L')) | |
916 | FAIL; | |
7cd5235b | 917 | |
9ebbca7d GK |
918 | /* The ordering here is important for the prolog expander. |
919 | When space is allocated from the stack, adding 'low' first may | |
920 | produce a temporary deallocation (which would be bad). */ | |
0354e5d8 GK |
921 | emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest))); |
922 | emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low))); | |
7cd5235b MM |
923 | DONE; |
924 | } | |
925 | }") | |
926 | ||
0354e5d8 GK |
927 | ;; Discourage ai/addic because of carry but provide it in an alternative |
928 | ;; allowing register zero as source. | |
929 | (define_insn "*add<mode>3_internal1" | |
930 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r") | |
931 | (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b") | |
932 | (match_operand:GPR 2 "add_operand" "r,I,I,L")))] | |
1fd4e8c1 RK |
933 | "" |
934 | "@ | |
deb9225a RK |
935 | {cax|add} %0,%1,%2 |
936 | {cal %0,%2(%1)|addi %0,%1,%2} | |
937 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
938 | {cau|addis} %0,%1,%v2" |
939 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 940 | |
ee890fe2 SS |
941 | (define_insn "addsi3_high" |
942 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
943 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
944 | (high:SI (match_operand 2 "" ""))))] | |
945 | "TARGET_MACHO && !TARGET_64BIT" | |
946 | "{cau|addis} %0,%1,ha16(%2)" | |
947 | [(set_attr "length" "4")]) | |
948 | ||
0354e5d8 | 949 | (define_insn "*add<mode>3_internal2" |
cb8cc086 | 950 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
0354e5d8 GK |
951 | (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r") |
952 | (match_operand:P 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 953 | (const_int 0))) |
0354e5d8 GK |
954 | (clobber (match_scratch:P 3 "=r,r,r,r"))] |
955 | "" | |
deb9225a RK |
956 | "@ |
957 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
958 | {ai.|addic.} %3,%1,%2 |
959 | # | |
960 | #" | |
a62bfff2 | 961 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
962 | (set_attr "length" "4,4,8,8")]) |
963 | ||
964 | (define_split | |
965 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
0354e5d8 GK |
966 | (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "") |
967 | (match_operand:GPR 2 "reg_or_short_operand" "")) | |
cb8cc086 | 968 | (const_int 0))) |
0354e5d8 GK |
969 | (clobber (match_scratch:GPR 3 ""))] |
970 | "reload_completed" | |
cb8cc086 | 971 | [(set (match_dup 3) |
0354e5d8 | 972 | (plus:GPR (match_dup 1) |
cb8cc086 MM |
973 | (match_dup 2))) |
974 | (set (match_dup 0) | |
975 | (compare:CC (match_dup 3) | |
976 | (const_int 0)))] | |
977 | "") | |
7e69e155 | 978 | |
0354e5d8 | 979 | (define_insn "*add<mode>3_internal3" |
cb8cc086 | 980 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
0354e5d8 GK |
981 | (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r") |
982 | (match_operand:P 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 983 | (const_int 0))) |
0354e5d8 GK |
984 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r") |
985 | (plus:P (match_dup 1) | |
986 | (match_dup 2)))] | |
987 | "" | |
deb9225a RK |
988 | "@ |
989 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
990 | {ai.|addic.} %0,%1,%2 |
991 | # | |
992 | #" | |
a62bfff2 | 993 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
994 | (set_attr "length" "4,4,8,8")]) |
995 | ||
996 | (define_split | |
997 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
0354e5d8 GK |
998 | (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "") |
999 | (match_operand:P 2 "reg_or_short_operand" "")) | |
cb8cc086 | 1000 | (const_int 0))) |
0354e5d8 GK |
1001 | (set (match_operand:P 0 "gpc_reg_operand" "") |
1002 | (plus:P (match_dup 1) (match_dup 2)))] | |
1003 | "reload_completed" | |
cb8cc086 | 1004 | [(set (match_dup 0) |
0354e5d8 GK |
1005 | (plus:P (match_dup 1) |
1006 | (match_dup 2))) | |
cb8cc086 MM |
1007 | (set (match_dup 3) |
1008 | (compare:CC (match_dup 0) | |
1009 | (const_int 0)))] | |
1010 | "") | |
7e69e155 | 1011 | |
f357808b RK |
1012 | ;; Split an add that we can't do in one insn into two insns, each of which |
1013 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1014 | ;; add should be last in case the result gets used in an address. | |
1015 | ||
1016 | (define_split | |
0354e5d8 GK |
1017 | [(set (match_operand:GPR 0 "gpc_reg_operand" "") |
1018 | (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "") | |
1019 | (match_operand:GPR 2 "non_add_cint_operand" "")))] | |
1fd4e8c1 | 1020 | "" |
0354e5d8 GK |
1021 | [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3))) |
1022 | (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))] | |
f357808b | 1023 | " |
1fd4e8c1 | 1024 | { |
2bfcf297 | 1025 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1026 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
0354e5d8 | 1027 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode); |
1fd4e8c1 | 1028 | |
e6ca2c17 | 1029 | operands[4] = GEN_INT (low); |
0354e5d8 GK |
1030 | if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L')) |
1031 | operands[3] = GEN_INT (rest); | |
1032 | else if (! no_new_pseudos) | |
1033 | { | |
1034 | operands[3] = gen_reg_rtx (DImode); | |
1035 | emit_move_insn (operands[3], operands[2]); | |
1036 | emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); | |
1037 | DONE; | |
1038 | } | |
1039 | else | |
1040 | FAIL; | |
1fd4e8c1 RK |
1041 | }") |
1042 | ||
0354e5d8 GK |
1043 | (define_insn "one_cmpl<mode>2" |
1044 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1045 | (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1046 | "" |
ca7f5001 RK |
1047 | "nor %0,%1,%1") |
1048 | ||
1049 | (define_insn "" | |
52d3af72 | 1050 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
0354e5d8 | 1051 | (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r")) |
ca7f5001 | 1052 | (const_int 0))) |
0354e5d8 GK |
1053 | (clobber (match_scratch:P 2 "=r,r"))] |
1054 | "" | |
52d3af72 DE |
1055 | "@ |
1056 | nor. %2,%1,%1 | |
1057 | #" | |
1058 | [(set_attr "type" "compare") | |
1059 | (set_attr "length" "4,8")]) | |
1060 | ||
1061 | (define_split | |
1062 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
0354e5d8 | 1063 | (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "")) |
52d3af72 | 1064 | (const_int 0))) |
0354e5d8 GK |
1065 | (clobber (match_scratch:P 2 ""))] |
1066 | "reload_completed" | |
52d3af72 | 1067 | [(set (match_dup 2) |
0354e5d8 | 1068 | (not:P (match_dup 1))) |
52d3af72 DE |
1069 | (set (match_dup 0) |
1070 | (compare:CC (match_dup 2) | |
1071 | (const_int 0)))] | |
1072 | "") | |
ca7f5001 RK |
1073 | |
1074 | (define_insn "" | |
52d3af72 | 1075 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
0354e5d8 | 1076 | (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r")) |
815cdc52 | 1077 | (const_int 0))) |
0354e5d8 GK |
1078 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r") |
1079 | (not:P (match_dup 1)))] | |
1080 | "" | |
52d3af72 DE |
1081 | "@ |
1082 | nor. %0,%1,%1 | |
1083 | #" | |
1084 | [(set_attr "type" "compare") | |
1085 | (set_attr "length" "4,8")]) | |
1086 | ||
1087 | (define_split | |
1088 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
0354e5d8 | 1089 | (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "")) |
52d3af72 | 1090 | (const_int 0))) |
0354e5d8 GK |
1091 | (set (match_operand:P 0 "gpc_reg_operand" "") |
1092 | (not:P (match_dup 1)))] | |
1093 | "reload_completed" | |
52d3af72 | 1094 | [(set (match_dup 0) |
0354e5d8 | 1095 | (not:P (match_dup 1))) |
52d3af72 DE |
1096 | (set (match_dup 2) |
1097 | (compare:CC (match_dup 0) | |
1098 | (const_int 0)))] | |
1099 | "") | |
1fd4e8c1 RK |
1100 | |
1101 | (define_insn "" | |
3d91674b RK |
1102 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1103 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1104 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1105 | "! TARGET_POWERPC" |
ca7f5001 | 1106 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1107 | |
deb9225a | 1108 | (define_insn "" |
0354e5d8 GK |
1109 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") |
1110 | (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I") | |
1111 | (match_operand:GPR 2 "gpc_reg_operand" "r,r")))] | |
deb9225a RK |
1112 | "TARGET_POWERPC" |
1113 | "@ | |
1114 | subf %0,%2,%1 | |
1115 | subfic %0,%2,%1") | |
1116 | ||
1fd4e8c1 | 1117 | (define_insn "" |
cb8cc086 MM |
1118 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1119 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1120 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1121 | (const_int 0))) |
cb8cc086 | 1122 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1123 | "! TARGET_POWERPC" |
cb8cc086 MM |
1124 | "@ |
1125 | {sf.|subfc.} %3,%2,%1 | |
1126 | #" | |
1127 | [(set_attr "type" "compare") | |
1128 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1129 | |
deb9225a | 1130 | (define_insn "" |
cb8cc086 | 1131 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
0354e5d8 GK |
1132 | (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r") |
1133 | (match_operand:P 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1134 | (const_int 0))) |
0354e5d8 GK |
1135 | (clobber (match_scratch:P 3 "=r,r"))] |
1136 | "TARGET_POWERPC" | |
cb8cc086 MM |
1137 | "@ |
1138 | subf. %3,%2,%1 | |
1139 | #" | |
a62bfff2 | 1140 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1141 | (set_attr "length" "4,8")]) |
1142 | ||
1143 | (define_split | |
1144 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
0354e5d8 GK |
1145 | (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "") |
1146 | (match_operand:P 2 "gpc_reg_operand" "")) | |
cb8cc086 | 1147 | (const_int 0))) |
0354e5d8 GK |
1148 | (clobber (match_scratch:P 3 ""))] |
1149 | "reload_completed" | |
cb8cc086 | 1150 | [(set (match_dup 3) |
0354e5d8 | 1151 | (minus:P (match_dup 1) |
cb8cc086 MM |
1152 | (match_dup 2))) |
1153 | (set (match_dup 0) | |
1154 | (compare:CC (match_dup 3) | |
1155 | (const_int 0)))] | |
1156 | "") | |
deb9225a | 1157 | |
1fd4e8c1 | 1158 | (define_insn "" |
cb8cc086 MM |
1159 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1160 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1161 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1162 | (const_int 0))) |
cb8cc086 | 1163 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1164 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1165 | "! TARGET_POWERPC" |
cb8cc086 MM |
1166 | "@ |
1167 | {sf.|subfc.} %0,%2,%1 | |
1168 | #" | |
1169 | [(set_attr "type" "compare") | |
1170 | (set_attr "length" "4,8")]) | |
815cdc52 | 1171 | |
29ae5b89 | 1172 | (define_insn "" |
cb8cc086 | 1173 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
0354e5d8 GK |
1174 | (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r") |
1175 | (match_operand:P 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1176 | (const_int 0))) |
0354e5d8 GK |
1177 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r") |
1178 | (minus:P (match_dup 1) | |
cb8cc086 | 1179 | (match_dup 2)))] |
0354e5d8 | 1180 | "TARGET_POWERPC" |
90612787 DE |
1181 | "@ |
1182 | subf. %0,%2,%1 | |
1183 | #" | |
a62bfff2 | 1184 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1185 | (set_attr "length" "4,8")]) |
1186 | ||
1187 | (define_split | |
1188 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
0354e5d8 GK |
1189 | (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "") |
1190 | (match_operand:P 2 "gpc_reg_operand" "")) | |
cb8cc086 | 1191 | (const_int 0))) |
0354e5d8 GK |
1192 | (set (match_operand:P 0 "gpc_reg_operand" "") |
1193 | (minus:P (match_dup 1) | |
cb8cc086 | 1194 | (match_dup 2)))] |
0354e5d8 | 1195 | "reload_completed" |
cb8cc086 | 1196 | [(set (match_dup 0) |
0354e5d8 | 1197 | (minus:P (match_dup 1) |
cb8cc086 MM |
1198 | (match_dup 2))) |
1199 | (set (match_dup 3) | |
1200 | (compare:CC (match_dup 0) | |
1201 | (const_int 0)))] | |
1202 | "") | |
deb9225a | 1203 | |
0354e5d8 GK |
1204 | (define_expand "sub<mode>3" |
1205 | [(set (match_operand:SDI 0 "gpc_reg_operand" "") | |
1206 | (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "") | |
4ae234b0 | 1207 | (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))] |
1fd4e8c1 | 1208 | "" |
a0044fb1 RK |
1209 | " |
1210 | { | |
1211 | if (GET_CODE (operands[2]) == CONST_INT) | |
1212 | { | |
0354e5d8 GK |
1213 | emit_insn (gen_add<mode>3 (operands[0], operands[1], |
1214 | negate_rtx (<MODE>mode, operands[2]))); | |
a0044fb1 RK |
1215 | DONE; |
1216 | } | |
1217 | }") | |
1fd4e8c1 RK |
1218 | |
1219 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1220 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1221 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1222 | ;; combine. | |
1fd4e8c1 RK |
1223 | |
1224 | (define_expand "sminsi3" | |
1225 | [(set (match_dup 3) | |
cd2b37d9 | 1226 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1227 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1228 | (const_int 0) | |
1229 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1230 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1231 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1232 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1233 | " |
a3170dc6 AH |
1234 | { |
1235 | if (TARGET_ISEL) | |
1236 | { | |
1237 | operands[2] = force_reg (SImode, operands[2]); | |
1238 | rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); | |
1239 | DONE; | |
1240 | } | |
1241 | ||
1242 | operands[3] = gen_reg_rtx (SImode); | |
1243 | }") | |
1fd4e8c1 | 1244 | |
95ac8e67 RK |
1245 | (define_split |
1246 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1247 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1248 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1249 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1250 | "TARGET_POWER" |
95ac8e67 RK |
1251 | [(set (match_dup 3) |
1252 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1253 | (const_int 0) | |
1254 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1255 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1256 | "") | |
1257 | ||
1fd4e8c1 RK |
1258 | (define_expand "smaxsi3" |
1259 | [(set (match_dup 3) | |
cd2b37d9 | 1260 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1261 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1262 | (const_int 0) | |
1263 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1264 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1265 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1266 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1267 | " |
a3170dc6 AH |
1268 | { |
1269 | if (TARGET_ISEL) | |
1270 | { | |
1271 | operands[2] = force_reg (SImode, operands[2]); | |
1272 | rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); | |
1273 | DONE; | |
1274 | } | |
1275 | operands[3] = gen_reg_rtx (SImode); | |
1276 | }") | |
1fd4e8c1 | 1277 | |
95ac8e67 RK |
1278 | (define_split |
1279 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1280 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1281 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1282 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1283 | "TARGET_POWER" |
95ac8e67 RK |
1284 | [(set (match_dup 3) |
1285 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1286 | (const_int 0) | |
1287 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1288 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1289 | "") | |
1290 | ||
1fd4e8c1 | 1291 | (define_expand "uminsi3" |
cd2b37d9 | 1292 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1293 | (match_dup 5))) |
cd2b37d9 | 1294 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1295 | (match_dup 5))) |
1fd4e8c1 RK |
1296 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1297 | (const_int 0) | |
1298 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1299 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1300 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1301 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1302 | " |
bb68ff55 | 1303 | { |
a3170dc6 AH |
1304 | if (TARGET_ISEL) |
1305 | { | |
1306 | rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]); | |
1307 | DONE; | |
1308 | } | |
bb68ff55 MM |
1309 | operands[3] = gen_reg_rtx (SImode); |
1310 | operands[4] = gen_reg_rtx (SImode); | |
1311 | operands[5] = GEN_INT (-2147483647 - 1); | |
1312 | }") | |
1fd4e8c1 RK |
1313 | |
1314 | (define_expand "umaxsi3" | |
cd2b37d9 | 1315 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1316 | (match_dup 5))) |
cd2b37d9 | 1317 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1318 | (match_dup 5))) |
1fd4e8c1 RK |
1319 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1320 | (const_int 0) | |
1321 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1322 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1323 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1324 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1325 | " |
bb68ff55 | 1326 | { |
a3170dc6 AH |
1327 | if (TARGET_ISEL) |
1328 | { | |
1329 | rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]); | |
1330 | DONE; | |
1331 | } | |
bb68ff55 MM |
1332 | operands[3] = gen_reg_rtx (SImode); |
1333 | operands[4] = gen_reg_rtx (SImode); | |
1334 | operands[5] = GEN_INT (-2147483647 - 1); | |
1335 | }") | |
1fd4e8c1 RK |
1336 | |
1337 | (define_insn "" | |
cd2b37d9 RK |
1338 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1339 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1340 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1341 | (const_int 0) |
1342 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1343 | "TARGET_POWER" |
1fd4e8c1 RK |
1344 | "doz%I2 %0,%1,%2") |
1345 | ||
1346 | (define_insn "" | |
9ebbca7d | 1347 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1348 | (compare:CC |
9ebbca7d GK |
1349 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1350 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1351 | (const_int 0) |
1352 | (minus:SI (match_dup 2) (match_dup 1))) | |
1353 | (const_int 0))) | |
9ebbca7d | 1354 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 1355 | "TARGET_POWER" |
9ebbca7d GK |
1356 | "@ |
1357 | doz%I2. %3,%1,%2 | |
1358 | #" | |
1359 | [(set_attr "type" "delayed_compare") | |
1360 | (set_attr "length" "4,8")]) | |
1361 | ||
1362 | (define_split | |
1363 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1364 | (compare:CC | |
1365 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1366 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1367 | (const_int 0) | |
1368 | (minus:SI (match_dup 2) (match_dup 1))) | |
1369 | (const_int 0))) | |
1370 | (clobber (match_scratch:SI 3 ""))] | |
1371 | "TARGET_POWER && reload_completed" | |
1372 | [(set (match_dup 3) | |
1373 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1374 | (const_int 0) | |
1375 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1376 | (set (match_dup 0) | |
1377 | (compare:CC (match_dup 3) | |
1378 | (const_int 0)))] | |
1379 | "") | |
1fd4e8c1 RK |
1380 | |
1381 | (define_insn "" | |
9ebbca7d | 1382 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1383 | (compare:CC |
9ebbca7d GK |
1384 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1385 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1386 | (const_int 0) |
1387 | (minus:SI (match_dup 2) (match_dup 1))) | |
1388 | (const_int 0))) | |
9ebbca7d | 1389 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1390 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1391 | (const_int 0) | |
1392 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1393 | "TARGET_POWER" |
9ebbca7d GK |
1394 | "@ |
1395 | doz%I2. %0,%1,%2 | |
1396 | #" | |
1397 | [(set_attr "type" "delayed_compare") | |
1398 | (set_attr "length" "4,8")]) | |
1399 | ||
1400 | (define_split | |
1401 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1402 | (compare:CC | |
1403 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1404 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1405 | (const_int 0) | |
1406 | (minus:SI (match_dup 2) (match_dup 1))) | |
1407 | (const_int 0))) | |
1408 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1409 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1410 | (const_int 0) | |
1411 | (minus:SI (match_dup 2) (match_dup 1))))] | |
1412 | "TARGET_POWER && reload_completed" | |
1413 | [(set (match_dup 0) | |
1414 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1415 | (const_int 0) | |
1416 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1417 | (set (match_dup 3) | |
1418 | (compare:CC (match_dup 0) | |
1419 | (const_int 0)))] | |
1420 | "") | |
1fd4e8c1 RK |
1421 | |
1422 | ;; We don't need abs with condition code because such comparisons should | |
1423 | ;; never be done. | |
ea9be077 MM |
1424 | (define_expand "abssi2" |
1425 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1426 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1427 | "" | |
1428 | " | |
1429 | { | |
a3170dc6 AH |
1430 | if (TARGET_ISEL) |
1431 | { | |
1432 | emit_insn (gen_abssi2_isel (operands[0], operands[1])); | |
1433 | DONE; | |
1434 | } | |
1435 | else if (! TARGET_POWER) | |
ea9be077 MM |
1436 | { |
1437 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1438 | DONE; | |
1439 | } | |
1440 | }") | |
1441 | ||
ea112fc4 | 1442 | (define_insn "*abssi2_power" |
cd2b37d9 RK |
1443 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1444 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1445 | "TARGET_POWER" |
1fd4e8c1 RK |
1446 | "abs %0,%1") |
1447 | ||
a3170dc6 AH |
1448 | (define_insn_and_split "abssi2_isel" |
1449 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1450 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8c48b6f5 | 1451 | (clobber (match_scratch:SI 2 "=&b")) |
a3170dc6 AH |
1452 | (clobber (match_scratch:CC 3 "=y"))] |
1453 | "TARGET_ISEL" | |
1454 | "#" | |
1455 | "&& reload_completed" | |
1456 | [(set (match_dup 2) (neg:SI (match_dup 1))) | |
1457 | (set (match_dup 3) | |
1458 | (compare:CC (match_dup 1) | |
1459 | (const_int 0))) | |
1460 | (set (match_dup 0) | |
1461 | (if_then_else:SI (ge (match_dup 3) | |
1462 | (const_int 0)) | |
1463 | (match_dup 1) | |
1464 | (match_dup 2)))] | |
1465 | "") | |
1466 | ||
ea112fc4 | 1467 | (define_insn_and_split "abssi2_nopower" |
ea9be077 | 1468 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1469 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) |
ea9be077 | 1470 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
a3170dc6 | 1471 | "! TARGET_POWER && ! TARGET_ISEL" |
ea112fc4 DE |
1472 | "#" |
1473 | "&& reload_completed" | |
ea9be077 MM |
1474 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1475 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1476 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1477 | "") |
1478 | ||
463b558b | 1479 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1480 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1481 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1482 | "TARGET_POWER" |
1fd4e8c1 RK |
1483 | "nabs %0,%1") |
1484 | ||
ea112fc4 | 1485 | (define_insn_and_split "*nabs_nopower" |
ea9be077 | 1486 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1487 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) |
ea9be077 | 1488 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
0ad91047 | 1489 | "! TARGET_POWER" |
ea112fc4 DE |
1490 | "#" |
1491 | "&& reload_completed" | |
ea9be077 MM |
1492 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1493 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1494 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1495 | "") |
1496 | ||
0354e5d8 GK |
1497 | (define_expand "neg<mode>2" |
1498 | [(set (match_operand:SDI 0 "gpc_reg_operand" "") | |
1499 | (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))] | |
1500 | "" | |
1501 | "") | |
1502 | ||
1503 | (define_insn "*neg<mode>2_internal" | |
1504 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1505 | (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1506 | "" |
1507 | "neg %0,%1") | |
1508 | ||
1509 | (define_insn "" | |
9ebbca7d | 1510 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
0354e5d8 | 1511 | (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 1512 | (const_int 0))) |
0354e5d8 GK |
1513 | (clobber (match_scratch:P 2 "=r,r"))] |
1514 | "" | |
9ebbca7d GK |
1515 | "@ |
1516 | neg. %2,%1 | |
1517 | #" | |
a62bfff2 | 1518 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1519 | (set_attr "length" "4,8")]) |
1520 | ||
1521 | (define_split | |
1522 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
0354e5d8 | 1523 | (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "")) |
9ebbca7d | 1524 | (const_int 0))) |
0354e5d8 GK |
1525 | (clobber (match_scratch:P 2 ""))] |
1526 | "reload_completed" | |
9ebbca7d | 1527 | [(set (match_dup 2) |
0354e5d8 | 1528 | (neg:P (match_dup 1))) |
9ebbca7d GK |
1529 | (set (match_dup 0) |
1530 | (compare:CC (match_dup 2) | |
1531 | (const_int 0)))] | |
1532 | "") | |
1fd4e8c1 RK |
1533 | |
1534 | (define_insn "" | |
9ebbca7d | 1535 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
0354e5d8 | 1536 | (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r")) |
815cdc52 | 1537 | (const_int 0))) |
0354e5d8 GK |
1538 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r") |
1539 | (neg:P (match_dup 1)))] | |
1540 | "" | |
9ebbca7d GK |
1541 | "@ |
1542 | neg. %0,%1 | |
1543 | #" | |
a62bfff2 | 1544 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1545 | (set_attr "length" "4,8")]) |
1546 | ||
1547 | (define_split | |
1548 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
0354e5d8 | 1549 | (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "")) |
9ebbca7d | 1550 | (const_int 0))) |
0354e5d8 GK |
1551 | (set (match_operand:P 0 "gpc_reg_operand" "") |
1552 | (neg:P (match_dup 1)))] | |
66859ace | 1553 | "reload_completed" |
9ebbca7d | 1554 | [(set (match_dup 0) |
0354e5d8 | 1555 | (neg:P (match_dup 1))) |
9ebbca7d GK |
1556 | (set (match_dup 2) |
1557 | (compare:CC (match_dup 0) | |
1558 | (const_int 0)))] | |
1559 | "") | |
1fd4e8c1 | 1560 | |
0354e5d8 GK |
1561 | (define_insn "clz<mode>2" |
1562 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1563 | (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] | |
1b1edcfa | 1564 | "" |
0354e5d8 | 1565 | "{cntlz|cntlz<wd>} %0,%1") |
1b1edcfa | 1566 | |
0354e5d8 | 1567 | (define_expand "ctz<mode>2" |
4977bab6 | 1568 | [(set (match_dup 2) |
0354e5d8 GK |
1569 | (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) |
1570 | (parallel [(set (match_dup 3) (and:GPR (match_dup 1) | |
1571 | (match_dup 2))) | |
1b1edcfa | 1572 | (clobber (scratch:CC))]) |
0354e5d8 GK |
1573 | (set (match_dup 4) (clz:GPR (match_dup 3))) |
1574 | (set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1575 | (minus:GPR (match_dup 5) (match_dup 4)))] | |
1fd4e8c1 | 1576 | "" |
4977bab6 | 1577 | { |
0354e5d8 GK |
1578 | operands[2] = gen_reg_rtx (<MODE>mode); |
1579 | operands[3] = gen_reg_rtx (<MODE>mode); | |
1580 | operands[4] = gen_reg_rtx (<MODE>mode); | |
1581 | operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1); | |
4977bab6 | 1582 | }) |
6ae08853 | 1583 | |
0354e5d8 | 1584 | (define_expand "ffs<mode>2" |
1b1edcfa | 1585 | [(set (match_dup 2) |
0354e5d8 GK |
1586 | (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) |
1587 | (parallel [(set (match_dup 3) (and:GPR (match_dup 1) | |
1588 | (match_dup 2))) | |
1b1edcfa | 1589 | (clobber (scratch:CC))]) |
0354e5d8 GK |
1590 | (set (match_dup 4) (clz:GPR (match_dup 3))) |
1591 | (set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1592 | (minus:GPR (match_dup 5) (match_dup 4)))] | |
4977bab6 | 1593 | "" |
1b1edcfa | 1594 | { |
0354e5d8 GK |
1595 | operands[2] = gen_reg_rtx (<MODE>mode); |
1596 | operands[3] = gen_reg_rtx (<MODE>mode); | |
1597 | operands[4] = gen_reg_rtx (<MODE>mode); | |
1598 | operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)); | |
1b1edcfa | 1599 | }) |
6ae08853 | 1600 | |
432218ba DE |
1601 | (define_expand "popcount<mode>2" |
1602 | [(set (match_dup 2) | |
1603 | (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] | |
1604 | UNSPEC_POPCNTB)) | |
1605 | (set (match_dup 3) | |
1606 | (mult:GPR (match_dup 2) (match_dup 4))) | |
1607 | (set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1608 | (lshiftrt:GPR (match_dup 3) (match_dup 5)))] | |
1609 | "TARGET_POPCNTB" | |
1610 | { | |
1611 | operands[2] = gen_reg_rtx (<MODE>mode); | |
1612 | operands[3] = gen_reg_rtx (<MODE>mode); | |
1e0aa44a DE |
1613 | operands[4] = force_reg (<MODE>mode, |
1614 | <MODE>mode == SImode | |
1615 | ? GEN_INT (0x01010101) | |
1616 | : GEN_INT ((HOST_WIDE_INT) | |
1617 | 0x01010101 << 32 | 0x01010101)); | |
432218ba DE |
1618 | operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8); |
1619 | }) | |
1620 | ||
1621 | (define_insn "popcntb<mode>2" | |
1622 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1623 | (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] | |
1624 | UNSPEC_POPCNTB))] | |
1625 | "TARGET_POPCNTB" | |
1626 | "popcntb %0,%1") | |
1627 | ||
ca7f5001 RK |
1628 | (define_expand "mulsi3" |
1629 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1630 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
1631 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
1632 | "" | |
1633 | " | |
1634 | { | |
1635 | if (TARGET_POWER) | |
68b40e7e | 1636 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 1637 | else |
68b40e7e | 1638 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
1639 | DONE; |
1640 | }") | |
1641 | ||
68b40e7e | 1642 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
1643 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1644 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
1645 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
1646 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
1647 | "TARGET_POWER" |
1648 | "@ | |
1649 | {muls|mullw} %0,%1,%2 | |
1650 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1651 | [(set (attr "type") |
c859cda6 DJ |
1652 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1653 | (const_string "imul3") | |
6ae08853 | 1654 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1655 | (const_string "imul2")] |
1656 | (const_string "imul")))]) | |
ca7f5001 | 1657 | |
68b40e7e | 1658 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
1659 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1660 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1661 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 1662 | "! TARGET_POWER" |
1fd4e8c1 | 1663 | "@ |
d904e9ed RK |
1664 | {muls|mullw} %0,%1,%2 |
1665 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1666 | [(set (attr "type") |
c859cda6 DJ |
1667 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1668 | (const_string "imul3") | |
6ae08853 | 1669 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1670 | (const_string "imul2")] |
1671 | (const_string "imul")))]) | |
1fd4e8c1 | 1672 | |
9259f3b0 | 1673 | (define_insn "*mulsi3_mq_internal1" |
9ebbca7d GK |
1674 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1675 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1676 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1677 | (const_int 0))) |
9ebbca7d GK |
1678 | (clobber (match_scratch:SI 3 "=r,r")) |
1679 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 1680 | "TARGET_POWER" |
9ebbca7d GK |
1681 | "@ |
1682 | {muls.|mullw.} %3,%1,%2 | |
1683 | #" | |
9259f3b0 | 1684 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1685 | (set_attr "length" "4,8")]) |
1686 | ||
1687 | (define_split | |
1688 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1689 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1690 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1691 | (const_int 0))) | |
1692 | (clobber (match_scratch:SI 3 "")) | |
1693 | (clobber (match_scratch:SI 4 ""))] | |
1694 | "TARGET_POWER && reload_completed" | |
1695 | [(parallel [(set (match_dup 3) | |
1696 | (mult:SI (match_dup 1) (match_dup 2))) | |
1697 | (clobber (match_dup 4))]) | |
1698 | (set (match_dup 0) | |
1699 | (compare:CC (match_dup 3) | |
1700 | (const_int 0)))] | |
1701 | "") | |
ca7f5001 | 1702 | |
9259f3b0 | 1703 | (define_insn "*mulsi3_no_mq_internal1" |
9ebbca7d GK |
1704 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1705 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1706 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1707 | (const_int 0))) |
9ebbca7d | 1708 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 1709 | "! TARGET_POWER" |
9ebbca7d GK |
1710 | "@ |
1711 | {muls.|mullw.} %3,%1,%2 | |
1712 | #" | |
9259f3b0 | 1713 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1714 | (set_attr "length" "4,8")]) |
1715 | ||
1716 | (define_split | |
1717 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1718 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1719 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1720 | (const_int 0))) | |
1721 | (clobber (match_scratch:SI 3 ""))] | |
1722 | "! TARGET_POWER && reload_completed" | |
1723 | [(set (match_dup 3) | |
1724 | (mult:SI (match_dup 1) (match_dup 2))) | |
1725 | (set (match_dup 0) | |
1726 | (compare:CC (match_dup 3) | |
1727 | (const_int 0)))] | |
1728 | "") | |
1fd4e8c1 | 1729 | |
9259f3b0 | 1730 | (define_insn "*mulsi3_mq_internal2" |
9ebbca7d GK |
1731 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1732 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1733 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1734 | (const_int 0))) |
9ebbca7d | 1735 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 1736 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 1737 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 1738 | "TARGET_POWER" |
9ebbca7d GK |
1739 | "@ |
1740 | {muls.|mullw.} %0,%1,%2 | |
1741 | #" | |
9259f3b0 | 1742 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1743 | (set_attr "length" "4,8")]) |
1744 | ||
1745 | (define_split | |
1746 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1747 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1748 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1749 | (const_int 0))) | |
1750 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1751 | (mult:SI (match_dup 1) (match_dup 2))) | |
1752 | (clobber (match_scratch:SI 4 ""))] | |
1753 | "TARGET_POWER && reload_completed" | |
1754 | [(parallel [(set (match_dup 0) | |
1755 | (mult:SI (match_dup 1) (match_dup 2))) | |
1756 | (clobber (match_dup 4))]) | |
1757 | (set (match_dup 3) | |
1758 | (compare:CC (match_dup 0) | |
1759 | (const_int 0)))] | |
1760 | "") | |
ca7f5001 | 1761 | |
9259f3b0 | 1762 | (define_insn "*mulsi3_no_mq_internal2" |
9ebbca7d GK |
1763 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1764 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1765 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1766 | (const_int 0))) |
9ebbca7d | 1767 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 1768 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 1769 | "! TARGET_POWER" |
9ebbca7d GK |
1770 | "@ |
1771 | {muls.|mullw.} %0,%1,%2 | |
1772 | #" | |
9259f3b0 | 1773 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1774 | (set_attr "length" "4,8")]) |
1775 | ||
1776 | (define_split | |
1777 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1778 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1779 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1780 | (const_int 0))) | |
1781 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1782 | (mult:SI (match_dup 1) (match_dup 2)))] | |
1783 | "! TARGET_POWER && reload_completed" | |
1784 | [(set (match_dup 0) | |
1785 | (mult:SI (match_dup 1) (match_dup 2))) | |
1786 | (set (match_dup 3) | |
1787 | (compare:CC (match_dup 0) | |
1788 | (const_int 0)))] | |
1789 | "") | |
1fd4e8c1 RK |
1790 | |
1791 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
1792 | ;; 0 and remainder to operand 3. | |
1793 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
1794 | ||
8ffd9c51 RK |
1795 | (define_expand "divmodsi4" |
1796 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1797 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1798 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
bb157ff4 | 1799 | (set (match_operand:SI 3 "register_operand" "") |
8ffd9c51 RK |
1800 | (mod:SI (match_dup 1) (match_dup 2)))])] |
1801 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1802 | " | |
1803 | { | |
1804 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1805 | { | |
39403d82 DE |
1806 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1807 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1808 | emit_insn (gen_divss_call ()); |
39403d82 DE |
1809 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1810 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
1811 | DONE; |
1812 | } | |
1813 | }") | |
deb9225a | 1814 | |
bb157ff4 | 1815 | (define_insn "*divmodsi4_internal" |
cd2b37d9 RK |
1816 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1817 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1818 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
bb157ff4 | 1819 | (set (match_operand:SI 3 "register_operand" "=q") |
1fd4e8c1 | 1820 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 1821 | "TARGET_POWER" |
cfb557c4 RK |
1822 | "divs %0,%1,%2" |
1823 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 1824 | |
4ae234b0 GK |
1825 | (define_expand "udiv<mode>3" |
1826 | [(set (match_operand:GPR 0 "gpc_reg_operand" "") | |
1827 | (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "") | |
1828 | (match_operand:GPR 2 "gpc_reg_operand" "")))] | |
8ffd9c51 RK |
1829 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" |
1830 | " | |
1831 | { | |
1832 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1833 | { | |
39403d82 DE |
1834 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1835 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1836 | emit_insn (gen_quous_call ()); |
39403d82 | 1837 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1838 | DONE; |
1839 | } | |
f192bf8b DE |
1840 | else if (TARGET_POWER) |
1841 | { | |
1842 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
1843 | DONE; | |
1844 | } | |
8ffd9c51 | 1845 | }") |
deb9225a | 1846 | |
f192bf8b DE |
1847 | (define_insn "udivsi3_mq" |
1848 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1849 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1850 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1851 | (clobber (match_scratch:SI 3 "=q"))] | |
1852 | "TARGET_POWERPC && TARGET_POWER" | |
1853 | "divwu %0,%1,%2" | |
1854 | [(set_attr "type" "idiv")]) | |
1855 | ||
1856 | (define_insn "*udivsi3_no_mq" | |
4ae234b0 GK |
1857 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") |
1858 | (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") | |
1859 | (match_operand:GPR 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 1860 | "TARGET_POWERPC && ! TARGET_POWER" |
4ae234b0 | 1861 | "div<wd>u %0,%1,%2" |
ca7f5001 RK |
1862 | [(set_attr "type" "idiv")]) |
1863 | ||
1fd4e8c1 | 1864 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 1865 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
1866 | ;; used; for PowerPC, force operands into register and do a normal divide; |
1867 | ;; for AIX common-mode, use quoss call on register operands. | |
4ae234b0 GK |
1868 | (define_expand "div<mode>3" |
1869 | [(set (match_operand:GPR 0 "gpc_reg_operand" "") | |
1870 | (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") | |
1871 | (match_operand:GPR 2 "reg_or_cint_operand" "")))] | |
1fd4e8c1 RK |
1872 | "" |
1873 | " | |
1874 | { | |
ca7f5001 | 1875 | if (GET_CODE (operands[2]) == CONST_INT |
2bfcf297 | 1876 | && INTVAL (operands[2]) > 0 |
ca7f5001 RK |
1877 | && exact_log2 (INTVAL (operands[2])) >= 0) |
1878 | ; | |
b6c9286a | 1879 | else if (TARGET_POWERPC) |
f192bf8b DE |
1880 | { |
1881 | operands[2] = force_reg (SImode, operands[2]); | |
1882 | if (TARGET_POWER) | |
1883 | { | |
1884 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
1885 | DONE; | |
1886 | } | |
1887 | } | |
b6c9286a | 1888 | else if (TARGET_POWER) |
1fd4e8c1 | 1889 | FAIL; |
405c5495 | 1890 | else |
8ffd9c51 | 1891 | { |
39403d82 DE |
1892 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1893 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1894 | emit_insn (gen_quoss_call ()); |
39403d82 | 1895 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1896 | DONE; |
1897 | } | |
1fd4e8c1 RK |
1898 | }") |
1899 | ||
f192bf8b DE |
1900 | (define_insn "divsi3_mq" |
1901 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1902 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1903 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1904 | (clobber (match_scratch:SI 3 "=q"))] | |
1905 | "TARGET_POWERPC && TARGET_POWER" | |
1906 | "divw %0,%1,%2" | |
1907 | [(set_attr "type" "idiv")]) | |
1908 | ||
4ae234b0 GK |
1909 | (define_insn "*div<mode>3_no_mq" |
1910 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1911 | (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") | |
1912 | (match_operand:GPR 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 1913 | "TARGET_POWERPC && ! TARGET_POWER" |
4ae234b0 | 1914 | "div<wd> %0,%1,%2" |
f192bf8b DE |
1915 | [(set_attr "type" "idiv")]) |
1916 | ||
4ae234b0 GK |
1917 | (define_expand "mod<mode>3" |
1918 | [(use (match_operand:GPR 0 "gpc_reg_operand" "")) | |
1919 | (use (match_operand:GPR 1 "gpc_reg_operand" "")) | |
1920 | (use (match_operand:GPR 2 "reg_or_cint_operand" ""))] | |
39b52ba2 | 1921 | "" |
1fd4e8c1 RK |
1922 | " |
1923 | { | |
481c7efa | 1924 | int i; |
39b52ba2 RK |
1925 | rtx temp1; |
1926 | rtx temp2; | |
1927 | ||
2bfcf297 | 1928 | if (GET_CODE (operands[2]) != CONST_INT |
a65c591c | 1929 | || INTVAL (operands[2]) <= 0 |
2bfcf297 | 1930 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) |
39b52ba2 RK |
1931 | FAIL; |
1932 | ||
4ae234b0 GK |
1933 | temp1 = gen_reg_rtx (<MODE>mode); |
1934 | temp2 = gen_reg_rtx (<MODE>mode); | |
1fd4e8c1 | 1935 | |
4ae234b0 GK |
1936 | emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2])); |
1937 | emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i))); | |
1938 | emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2)); | |
85644414 | 1939 | DONE; |
1fd4e8c1 RK |
1940 | }") |
1941 | ||
1942 | (define_insn "" | |
4ae234b0 GK |
1943 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") |
1944 | (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") | |
1945 | (match_operand:GPR 2 "exact_log2_cint_operand" "N")))] | |
2bfcf297 | 1946 | "" |
4ae234b0 | 1947 | "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0" |
943c15ed DE |
1948 | [(set_attr "type" "two") |
1949 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
1950 | |
1951 | (define_insn "" | |
9ebbca7d | 1952 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4ae234b0 GK |
1953 | (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r") |
1954 | (match_operand:P 2 "exact_log2_cint_operand" "N,N")) | |
b6b12107 | 1955 | (const_int 0))) |
4ae234b0 | 1956 | (clobber (match_scratch:P 3 "=r,r"))] |
2bfcf297 | 1957 | "" |
9ebbca7d | 1958 | "@ |
4ae234b0 | 1959 | {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3 |
9ebbca7d | 1960 | #" |
b19003d8 | 1961 | [(set_attr "type" "compare") |
9ebbca7d GK |
1962 | (set_attr "length" "8,12")]) |
1963 | ||
1964 | (define_split | |
1965 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4ae234b0 GK |
1966 | (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") |
1967 | (match_operand:GPR 2 "exact_log2_cint_operand" | |
1968 | "")) | |
9ebbca7d | 1969 | (const_int 0))) |
4ae234b0 | 1970 | (clobber (match_scratch:GPR 3 ""))] |
2bfcf297 | 1971 | "reload_completed" |
9ebbca7d | 1972 | [(set (match_dup 3) |
4ae234b0 | 1973 | (div:<MODE> (match_dup 1) (match_dup 2))) |
9ebbca7d GK |
1974 | (set (match_dup 0) |
1975 | (compare:CC (match_dup 3) | |
1976 | (const_int 0)))] | |
1977 | "") | |
1fd4e8c1 RK |
1978 | |
1979 | (define_insn "" | |
9ebbca7d | 1980 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4ae234b0 GK |
1981 | (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r") |
1982 | (match_operand:P 2 "exact_log2_cint_operand" "N,N")) | |
b6b12107 | 1983 | (const_int 0))) |
4ae234b0 GK |
1984 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r") |
1985 | (div:P (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 1986 | "" |
9ebbca7d | 1987 | "@ |
4ae234b0 | 1988 | {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0 |
9ebbca7d | 1989 | #" |
b19003d8 | 1990 | [(set_attr "type" "compare") |
9ebbca7d GK |
1991 | (set_attr "length" "8,12")]) |
1992 | ||
1993 | (define_split | |
1994 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4ae234b0 GK |
1995 | (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") |
1996 | (match_operand:GPR 2 "exact_log2_cint_operand" | |
1997 | "")) | |
9ebbca7d | 1998 | (const_int 0))) |
4ae234b0 GK |
1999 | (set (match_operand:GPR 0 "gpc_reg_operand" "") |
2000 | (div:GPR (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2001 | "reload_completed" |
9ebbca7d | 2002 | [(set (match_dup 0) |
4ae234b0 | 2003 | (div:<MODE> (match_dup 1) (match_dup 2))) |
9ebbca7d GK |
2004 | (set (match_dup 3) |
2005 | (compare:CC (match_dup 0) | |
2006 | (const_int 0)))] | |
2007 | "") | |
1fd4e8c1 RK |
2008 | |
2009 | (define_insn "" | |
cd2b37d9 | 2010 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2011 | (udiv:SI |
996a5f59 | 2012 | (plus:DI (ashift:DI |
cd2b37d9 | 2013 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2014 | (const_int 32)) |
23a900dc | 2015 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2016 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2017 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2018 | (umod:SI |
996a5f59 | 2019 | (plus:DI (ashift:DI |
1fd4e8c1 | 2020 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2021 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2022 | (match_dup 3)))] |
ca7f5001 | 2023 | "TARGET_POWER" |
cfb557c4 RK |
2024 | "div %0,%1,%3" |
2025 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2026 | |
2027 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2028 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2029 | ;; have to worry about the branches. So make a few subroutines here. | |
2030 | ;; | |
2031 | ;; First comes the normal case. | |
2032 | (define_expand "udivmodsi4_normal" | |
2033 | [(set (match_dup 4) (const_int 0)) | |
2034 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2035 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2036 | (const_int 32)) |
2037 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2038 | (match_operand:SI 2 "" ""))) | |
2039 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2040 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2041 | (const_int 32)) |
2042 | (zero_extend:DI (match_dup 1))) | |
2043 | (match_dup 2)))])] | |
ca7f5001 | 2044 | "TARGET_POWER" |
1fd4e8c1 RK |
2045 | " |
2046 | { operands[4] = gen_reg_rtx (SImode); }") | |
2047 | ||
2048 | ;; This handles the branches. | |
2049 | (define_expand "udivmodsi4_tests" | |
2050 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2051 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2052 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2053 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2054 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2055 | (set (match_dup 0) (const_int 1)) | |
2056 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2057 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2058 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2059 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2060 | "TARGET_POWER" |
1fd4e8c1 RK |
2061 | " |
2062 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2063 | operands[6] = gen_reg_rtx (CCmode); | |
2064 | }") | |
2065 | ||
2066 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2067 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2068 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2069 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2070 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2071 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2072 | "" |
1fd4e8c1 RK |
2073 | " |
2074 | { | |
2075 | rtx label = 0; | |
2076 | ||
8ffd9c51 | 2077 | if (! TARGET_POWER) |
c4d38ccb MM |
2078 | { |
2079 | if (! TARGET_POWERPC) | |
2080 | { | |
39403d82 DE |
2081 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2082 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2083 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2084 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2085 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2086 | DONE; |
2087 | } | |
2088 | else | |
2089 | FAIL; | |
2090 | } | |
0081a354 | 2091 | |
1fd4e8c1 RK |
2092 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2093 | { | |
2094 | operands[2] = force_reg (SImode, operands[2]); | |
2095 | label = gen_label_rtx (); | |
2096 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2097 | operands[3], label)); | |
2098 | } | |
2099 | else | |
2100 | operands[2] = force_reg (SImode, operands[2]); | |
2101 | ||
2102 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2103 | operands[3])); | |
2104 | if (label) | |
2105 | emit_label (label); | |
2106 | ||
2107 | DONE; | |
2108 | }") | |
0081a354 | 2109 | |
fada905b MM |
2110 | ;; AIX architecture-independent common-mode multiply (DImode), |
2111 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2112 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2113 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2114 | ;; assumed unused if generating common-mode, so ignore. | |
2115 | (define_insn "mulh_call" | |
2116 | [(set (reg:SI 3) | |
2117 | (truncate:SI | |
2118 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2119 | (sign_extend:DI (reg:SI 4))) | |
2120 | (const_int 32)))) | |
cf27b467 | 2121 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2122 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2123 | "bla __mulh" |
2124 | [(set_attr "type" "imul")]) | |
fada905b MM |
2125 | |
2126 | (define_insn "mull_call" | |
2127 | [(set (reg:DI 3) | |
2128 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2129 | (sign_extend:DI (reg:SI 4)))) | |
2130 | (clobber (match_scratch:SI 0 "=l")) | |
2131 | (clobber (reg:SI 0))] | |
2132 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2133 | "bla __mull" |
2134 | [(set_attr "type" "imul")]) | |
fada905b MM |
2135 | |
2136 | (define_insn "divss_call" | |
2137 | [(set (reg:SI 3) | |
2138 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2139 | (set (reg:SI 4) | |
2140 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2141 | (clobber (match_scratch:SI 0 "=l")) | |
2142 | (clobber (reg:SI 0))] | |
2143 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2144 | "bla __divss" |
2145 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2146 | |
2147 | (define_insn "divus_call" | |
8ffd9c51 RK |
2148 | [(set (reg:SI 3) |
2149 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2150 | (set (reg:SI 4) | |
2151 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2152 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2153 | (clobber (reg:SI 0)) |
2154 | (clobber (match_scratch:CC 1 "=x")) | |
2155 | (clobber (reg:CC 69))] | |
2156 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2157 | "bla __divus" |
2158 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2159 | |
2160 | (define_insn "quoss_call" | |
2161 | [(set (reg:SI 3) | |
2162 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2163 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2164 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2165 | "bla __quoss" |
2166 | [(set_attr "type" "idiv")]) | |
0081a354 | 2167 | |
fada905b MM |
2168 | (define_insn "quous_call" |
2169 | [(set (reg:SI 3) | |
2170 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2171 | (clobber (match_scratch:SI 0 "=l")) | |
2172 | (clobber (reg:SI 0)) | |
2173 | (clobber (match_scratch:CC 1 "=x")) | |
2174 | (clobber (reg:CC 69))] | |
2175 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2176 | "bla __quous" |
2177 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2178 | \f |
bb21487f | 2179 | ;; Logical instructions |
dfbdccdb GK |
2180 | ;; The logical instructions are mostly combined by using match_operator, |
2181 | ;; but the plain AND insns are somewhat different because there is no | |
2182 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2183 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2184 | ||
29ae5b89 JL |
2185 | (define_insn "andsi3" |
2186 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2187 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2188 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2189 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2190 | "" |
2191 | "@ | |
2192 | and %0,%1,%2 | |
ca7f5001 RK |
2193 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2194 | {andil.|andi.} %0,%1,%b2 | |
520308bc DE |
2195 | {andiu.|andis.} %0,%1,%u2" |
2196 | [(set_attr "type" "*,*,compare,compare")]) | |
52d3af72 DE |
2197 | |
2198 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
0ba1b2ff | 2199 | ;; the test again -- this avoids a mfcr which on the higher end |
52d3af72 | 2200 | ;; machines causes an execution serialization |
1fd4e8c1 | 2201 | |
7cd5235b | 2202 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2203 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2204 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2205 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2206 | (const_int 0))) |
52d3af72 DE |
2207 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2208 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2209 | "TARGET_32BIT" |
1fd4e8c1 RK |
2210 | "@ |
2211 | and. %3,%1,%2 | |
ca7f5001 RK |
2212 | {andil.|andi.} %3,%1,%b2 |
2213 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2214 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2215 | # | |
2216 | # | |
2217 | # | |
2218 | #" | |
2219 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2220 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2221 | |
0ba1b2ff AM |
2222 | (define_insn "*andsi3_internal3" |
2223 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2224 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2225 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2226 | (const_int 0))) | |
2227 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) | |
2228 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2229 | "TARGET_64BIT" |
0ba1b2ff AM |
2230 | "@ |
2231 | # | |
2232 | {andil.|andi.} %3,%1,%b2 | |
2233 | {andiu.|andis.} %3,%1,%u2 | |
2234 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 | |
2235 | # | |
2236 | # | |
2237 | # | |
2238 | #" | |
2239 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2240 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2241 | ||
52d3af72 DE |
2242 | (define_split |
2243 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4ae234b0 GK |
2244 | (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "") |
2245 | (match_operand:GPR 2 "and_operand" "")) | |
1fd4e8c1 | 2246 | (const_int 0))) |
4ae234b0 | 2247 | (clobber (match_scratch:GPR 3 "")) |
52d3af72 | 2248 | (clobber (match_scratch:CC 4 ""))] |
0ba1b2ff | 2249 | "reload_completed" |
52d3af72 | 2250 | [(parallel [(set (match_dup 3) |
4ae234b0 GK |
2251 | (and:<MODE> (match_dup 1) |
2252 | (match_dup 2))) | |
52d3af72 DE |
2253 | (clobber (match_dup 4))]) |
2254 | (set (match_dup 0) | |
2255 | (compare:CC (match_dup 3) | |
2256 | (const_int 0)))] | |
2257 | "") | |
2258 | ||
0ba1b2ff AM |
2259 | ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the |
2260 | ;; whole 64 bit reg, and we don't know what is in the high 32 bits. | |
2261 | ||
2262 | (define_split | |
2263 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
2264 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2265 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2266 | (const_int 0))) | |
2267 | (clobber (match_scratch:SI 3 "")) | |
2268 | (clobber (match_scratch:CC 4 ""))] | |
2269 | "TARGET_POWERPC64 && reload_completed" | |
2270 | [(parallel [(set (match_dup 3) | |
2271 | (and:SI (match_dup 1) | |
2272 | (match_dup 2))) | |
2273 | (clobber (match_dup 4))]) | |
2274 | (set (match_dup 0) | |
2275 | (compare:CC (match_dup 3) | |
2276 | (const_int 0)))] | |
2277 | "") | |
2278 | ||
2279 | (define_insn "*andsi3_internal4" | |
52d3af72 DE |
2280 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2281 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2282 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2283 | (const_int 0))) |
2284 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2285 | (and:SI (match_dup 1) | |
2286 | (match_dup 2))) | |
2287 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2288 | "TARGET_32BIT" |
1fd4e8c1 RK |
2289 | "@ |
2290 | and. %0,%1,%2 | |
ca7f5001 RK |
2291 | {andil.|andi.} %0,%1,%b2 |
2292 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2293 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2294 | # | |
2295 | # | |
2296 | # | |
2297 | #" | |
2298 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2299 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2300 | ||
0ba1b2ff AM |
2301 | (define_insn "*andsi3_internal5" |
2302 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2303 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2304 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2305 | (const_int 0))) | |
2306 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2307 | (and:SI (match_dup 1) | |
2308 | (match_dup 2))) | |
2309 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2310 | "TARGET_64BIT" |
0ba1b2ff AM |
2311 | "@ |
2312 | # | |
2313 | {andil.|andi.} %0,%1,%b2 | |
2314 | {andiu.|andis.} %0,%1,%u2 | |
2315 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 | |
2316 | # | |
2317 | # | |
2318 | # | |
2319 | #" | |
2320 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2321 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2322 | ||
52d3af72 DE |
2323 | (define_split |
2324 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2325 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2326 | (match_operand:SI 2 "and_operand" "")) | |
2327 | (const_int 0))) | |
2328 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2329 | (and:SI (match_dup 1) | |
2330 | (match_dup 2))) | |
2331 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2332 | "reload_completed" |
52d3af72 DE |
2333 | [(parallel [(set (match_dup 0) |
2334 | (and:SI (match_dup 1) | |
2335 | (match_dup 2))) | |
2336 | (clobber (match_dup 4))]) | |
2337 | (set (match_dup 3) | |
2338 | (compare:CC (match_dup 0) | |
2339 | (const_int 0)))] | |
2340 | "") | |
1fd4e8c1 | 2341 | |
0ba1b2ff AM |
2342 | (define_split |
2343 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
2344 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2345 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2346 | (const_int 0))) | |
2347 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2348 | (and:SI (match_dup 1) | |
2349 | (match_dup 2))) | |
2350 | (clobber (match_scratch:CC 4 ""))] | |
2351 | "TARGET_POWERPC64 && reload_completed" | |
2352 | [(parallel [(set (match_dup 0) | |
2353 | (and:SI (match_dup 1) | |
2354 | (match_dup 2))) | |
2355 | (clobber (match_dup 4))]) | |
2356 | (set (match_dup 3) | |
2357 | (compare:CC (match_dup 0) | |
2358 | (const_int 0)))] | |
2359 | "") | |
2360 | ||
2361 | ;; Handle the PowerPC64 rlwinm corner case | |
2362 | ||
2363 | (define_insn_and_split "*andsi3_internal6" | |
2364 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2365 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2366 | (match_operand:SI 2 "mask_operand_wrap" "i")))] | |
2367 | "TARGET_POWERPC64" | |
2368 | "#" | |
2369 | "TARGET_POWERPC64" | |
2370 | [(set (match_dup 0) | |
2371 | (and:SI (rotate:SI (match_dup 1) (match_dup 3)) | |
2372 | (match_dup 4))) | |
2373 | (set (match_dup 0) | |
2374 | (rotate:SI (match_dup 0) (match_dup 5)))] | |
2375 | " | |
2376 | { | |
2377 | int mb = extract_MB (operands[2]); | |
2378 | int me = extract_ME (operands[2]); | |
2379 | operands[3] = GEN_INT (me + 1); | |
2380 | operands[5] = GEN_INT (32 - (me + 1)); | |
2381 | operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2382 | }" | |
2383 | [(set_attr "length" "8")]) | |
2384 | ||
7cd5235b | 2385 | (define_expand "iorsi3" |
cd2b37d9 | 2386 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2387 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2388 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 2389 | "" |
f357808b RK |
2390 | " |
2391 | { | |
7cd5235b | 2392 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2393 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2394 | { |
2395 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2396 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2397 | ? operands[0] : gen_reg_rtx (SImode)); |
2398 | ||
a260abc9 DE |
2399 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2400 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2401 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2402 | DONE; |
2403 | } | |
f357808b RK |
2404 | }") |
2405 | ||
7cd5235b | 2406 | (define_expand "xorsi3" |
cd2b37d9 | 2407 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2408 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2409 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 2410 | "" |
7cd5235b | 2411 | " |
1fd4e8c1 | 2412 | { |
7cd5235b | 2413 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2414 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2415 | { |
2416 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2417 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2418 | ? operands[0] : gen_reg_rtx (SImode)); |
2419 | ||
a260abc9 DE |
2420 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2421 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2422 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2423 | DONE; |
2424 | } | |
1fd4e8c1 RK |
2425 | }") |
2426 | ||
dfbdccdb | 2427 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2428 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 2429 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2430 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
2431 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2432 | "" |
2433 | "@ | |
dfbdccdb GK |
2434 | %q3 %0,%1,%2 |
2435 | {%q3il|%q3i} %0,%1,%b2 | |
2436 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2437 | |
dfbdccdb | 2438 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2439 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 2440 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
2441 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
2442 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2443 | (const_int 0))) | |
52d3af72 | 2444 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2445 | "TARGET_32BIT" |
52d3af72 | 2446 | "@ |
dfbdccdb | 2447 | %q4. %3,%1,%2 |
52d3af72 DE |
2448 | #" |
2449 | [(set_attr "type" "compare") | |
2450 | (set_attr "length" "4,8")]) | |
2451 | ||
2452 | (define_split | |
2453 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2454 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2455 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2456 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2457 | (const_int 0))) |
52d3af72 | 2458 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2459 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2460 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2461 | (set (match_dup 0) |
2462 | (compare:CC (match_dup 3) | |
2463 | (const_int 0)))] | |
2464 | "") | |
815cdc52 | 2465 | |
dfbdccdb | 2466 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2467 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2468 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2469 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2470 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2471 | (const_int 0))) | |
52d3af72 | 2472 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2473 | (match_dup 4))] |
4b8a63d6 | 2474 | "TARGET_32BIT" |
52d3af72 | 2475 | "@ |
dfbdccdb | 2476 | %q4. %0,%1,%2 |
52d3af72 DE |
2477 | #" |
2478 | [(set_attr "type" "compare") | |
2479 | (set_attr "length" "4,8")]) | |
2480 | ||
2481 | (define_split | |
e72247f4 | 2482 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2483 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2484 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2485 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2486 | (const_int 0))) |
75540af0 | 2487 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2488 | (match_dup 4))] |
4b8a63d6 | 2489 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2490 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2491 | (set (match_dup 3) |
2492 | (compare:CC (match_dup 0) | |
2493 | (const_int 0)))] | |
2494 | "") | |
1fd4e8c1 | 2495 | |
6ae08853 | 2496 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 2497 | ;; each of which does one 16-bit part. This is used by combine. |
a260abc9 DE |
2498 | |
2499 | (define_split | |
2500 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 2501 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2502 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2503 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 2504 | "" |
dfbdccdb GK |
2505 | [(set (match_dup 0) (match_dup 4)) |
2506 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
2507 | " |
2508 | { | |
dfbdccdb GK |
2509 | rtx i; |
2510 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
1c563bed | 2511 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2512 | operands[1], i); |
dfbdccdb | 2513 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); |
1c563bed | 2514 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2515 | operands[0], i); |
a260abc9 DE |
2516 | }") |
2517 | ||
dfbdccdb | 2518 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 2519 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2520 | (match_operator:SI 3 "boolean_operator" |
2521 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2522 | (match_operand:SI 2 "gpc_reg_operand" "r")]))] |
1fd4e8c1 | 2523 | "" |
dfbdccdb | 2524 | "%q3 %0,%2,%1") |
1fd4e8c1 | 2525 | |
dfbdccdb | 2526 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 2527 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2528 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2529 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2530 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2531 | (const_int 0))) | |
52d3af72 | 2532 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2533 | "TARGET_32BIT" |
52d3af72 | 2534 | "@ |
dfbdccdb | 2535 | %q4. %3,%2,%1 |
52d3af72 DE |
2536 | #" |
2537 | [(set_attr "type" "compare") | |
2538 | (set_attr "length" "4,8")]) | |
2539 | ||
2540 | (define_split | |
2541 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2542 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2543 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2544 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2545 | (const_int 0))) |
52d3af72 | 2546 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2547 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2548 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2549 | (set (match_dup 0) |
2550 | (compare:CC (match_dup 3) | |
2551 | (const_int 0)))] | |
2552 | "") | |
1fd4e8c1 | 2553 | |
dfbdccdb | 2554 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 2555 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2556 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2557 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2558 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2559 | (const_int 0))) | |
52d3af72 | 2560 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2561 | (match_dup 4))] |
4b8a63d6 | 2562 | "TARGET_32BIT" |
52d3af72 | 2563 | "@ |
dfbdccdb | 2564 | %q4. %0,%2,%1 |
52d3af72 DE |
2565 | #" |
2566 | [(set_attr "type" "compare") | |
2567 | (set_attr "length" "4,8")]) | |
2568 | ||
2569 | (define_split | |
e72247f4 | 2570 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2571 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2572 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2573 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2574 | (const_int 0))) |
75540af0 | 2575 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2576 | (match_dup 4))] |
4b8a63d6 | 2577 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2578 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2579 | (set (match_dup 3) |
2580 | (compare:CC (match_dup 0) | |
2581 | (const_int 0)))] | |
2582 | "") | |
2583 | ||
dfbdccdb | 2584 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 2585 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2586 | (match_operator:SI 3 "boolean_operator" |
2587 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2588 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] |
1fd4e8c1 | 2589 | "" |
dfbdccdb | 2590 | "%q3 %0,%1,%2") |
1fd4e8c1 | 2591 | |
dfbdccdb | 2592 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 2593 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2594 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2595 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2596 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2597 | (const_int 0))) | |
52d3af72 | 2598 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2599 | "TARGET_32BIT" |
52d3af72 | 2600 | "@ |
dfbdccdb | 2601 | %q4. %3,%1,%2 |
52d3af72 DE |
2602 | #" |
2603 | [(set_attr "type" "compare") | |
2604 | (set_attr "length" "4,8")]) | |
2605 | ||
2606 | (define_split | |
2607 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2608 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2609 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2610 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2611 | (const_int 0))) |
52d3af72 | 2612 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2613 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2614 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2615 | (set (match_dup 0) |
2616 | (compare:CC (match_dup 3) | |
2617 | (const_int 0)))] | |
2618 | "") | |
1fd4e8c1 | 2619 | |
dfbdccdb | 2620 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 2621 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2622 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2623 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2624 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2625 | (const_int 0))) | |
52d3af72 | 2626 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2627 | (match_dup 4))] |
4b8a63d6 | 2628 | "TARGET_32BIT" |
52d3af72 | 2629 | "@ |
dfbdccdb | 2630 | %q4. %0,%1,%2 |
52d3af72 DE |
2631 | #" |
2632 | [(set_attr "type" "compare") | |
2633 | (set_attr "length" "4,8")]) | |
2634 | ||
2635 | (define_split | |
e72247f4 | 2636 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2637 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2638 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2639 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2640 | (const_int 0))) |
75540af0 | 2641 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2642 | (match_dup 4))] |
4b8a63d6 | 2643 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2644 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2645 | (set (match_dup 3) |
2646 | (compare:CC (match_dup 0) | |
2647 | (const_int 0)))] | |
2648 | "") | |
1fd4e8c1 RK |
2649 | |
2650 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2651 | ;; orders. Don't define forms that only set CR fields because these | |
2652 | ;; would modify an input register. | |
2653 | ||
7cd5235b | 2654 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2655 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2656 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2657 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2658 | (and:SI (match_dup 2) | |
cd2b37d9 | 2659 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2660 | "TARGET_POWER" |
01def764 | 2661 | "maskir %0,%3,%2") |
1fd4e8c1 | 2662 | |
7cd5235b | 2663 | (define_insn "*maskir_internal2" |
242e8072 | 2664 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2665 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2666 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2667 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2668 | (match_dup 2))))] |
ca7f5001 | 2669 | "TARGET_POWER" |
01def764 | 2670 | "maskir %0,%3,%2") |
1fd4e8c1 | 2671 | |
7cd5235b | 2672 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2673 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2674 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2675 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2676 | (and:SI (not:SI (match_dup 2)) |
2677 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2678 | "TARGET_POWER" |
01def764 | 2679 | "maskir %0,%3,%2") |
1fd4e8c1 | 2680 | |
7cd5235b | 2681 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2682 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2683 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2684 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2685 | (and:SI (not:SI (match_dup 2)) | |
2686 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2687 | "TARGET_POWER" |
01def764 | 2688 | "maskir %0,%3,%2") |
1fd4e8c1 | 2689 | |
7cd5235b | 2690 | (define_insn "*maskir_internal5" |
9ebbca7d | 2691 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2692 | (compare:CC |
9ebbca7d GK |
2693 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2694 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 2695 | (and:SI (match_dup 2) |
9ebbca7d | 2696 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 2697 | (const_int 0))) |
9ebbca7d | 2698 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2699 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2700 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2701 | "TARGET_POWER" |
9ebbca7d GK |
2702 | "@ |
2703 | maskir. %0,%3,%2 | |
2704 | #" | |
2705 | [(set_attr "type" "compare") | |
2706 | (set_attr "length" "4,8")]) | |
2707 | ||
2708 | (define_split | |
2709 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2710 | (compare:CC | |
2711 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2712 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2713 | (and:SI (match_dup 2) | |
2714 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
2715 | (const_int 0))) | |
2716 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2717 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2718 | (and:SI (match_dup 2) (match_dup 3))))] | |
2719 | "TARGET_POWER && reload_completed" | |
2720 | [(set (match_dup 0) | |
2721 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2722 | (and:SI (match_dup 2) (match_dup 3)))) | |
2723 | (set (match_dup 4) | |
2724 | (compare:CC (match_dup 0) | |
2725 | (const_int 0)))] | |
2726 | "") | |
1fd4e8c1 | 2727 | |
7cd5235b | 2728 | (define_insn "*maskir_internal6" |
9ebbca7d | 2729 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2730 | (compare:CC |
9ebbca7d GK |
2731 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2732 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
2733 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 2734 | (match_dup 2))) |
1fd4e8c1 | 2735 | (const_int 0))) |
9ebbca7d | 2736 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2737 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2738 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 2739 | "TARGET_POWER" |
9ebbca7d GK |
2740 | "@ |
2741 | maskir. %0,%3,%2 | |
2742 | #" | |
2743 | [(set_attr "type" "compare") | |
2744 | (set_attr "length" "4,8")]) | |
2745 | ||
2746 | (define_split | |
2747 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2748 | (compare:CC | |
2749 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2750 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2751 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2752 | (match_dup 2))) | |
2753 | (const_int 0))) | |
2754 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2755 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2756 | (and:SI (match_dup 3) (match_dup 2))))] | |
2757 | "TARGET_POWER && reload_completed" | |
2758 | [(set (match_dup 0) | |
2759 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2760 | (and:SI (match_dup 3) (match_dup 2)))) | |
2761 | (set (match_dup 4) | |
2762 | (compare:CC (match_dup 0) | |
2763 | (const_int 0)))] | |
2764 | "") | |
1fd4e8c1 | 2765 | |
7cd5235b | 2766 | (define_insn "*maskir_internal7" |
9ebbca7d | 2767 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 2768 | (compare:CC |
9ebbca7d GK |
2769 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
2770 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2771 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2772 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 2773 | (const_int 0))) |
9ebbca7d | 2774 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
2775 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
2776 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2777 | "TARGET_POWER" | |
9ebbca7d GK |
2778 | "@ |
2779 | maskir. %0,%3,%2 | |
2780 | #" | |
2781 | [(set_attr "type" "compare") | |
2782 | (set_attr "length" "4,8")]) | |
2783 | ||
2784 | (define_split | |
2785 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2786 | (compare:CC | |
2787 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
2788 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
2789 | (and:SI (not:SI (match_dup 2)) | |
2790 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2791 | (const_int 0))) | |
2792 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2793 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2794 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2795 | "TARGET_POWER && reload_completed" | |
2796 | [(set (match_dup 0) | |
2797 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2798 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2799 | (set (match_dup 4) | |
2800 | (compare:CC (match_dup 0) | |
2801 | (const_int 0)))] | |
2802 | "") | |
1fd4e8c1 | 2803 | |
7cd5235b | 2804 | (define_insn "*maskir_internal8" |
9ebbca7d | 2805 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2806 | (compare:CC |
9ebbca7d GK |
2807 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
2808 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 2809 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2810 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 2811 | (const_int 0))) |
9ebbca7d | 2812 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2813 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
2814 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 2815 | "TARGET_POWER" |
9ebbca7d GK |
2816 | "@ |
2817 | maskir. %0,%3,%2 | |
2818 | #" | |
2819 | [(set_attr "type" "compare") | |
2820 | (set_attr "length" "4,8")]) | |
fcce224d | 2821 | |
9ebbca7d GK |
2822 | (define_split |
2823 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2824 | (compare:CC | |
2825 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2826 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2827 | (and:SI (not:SI (match_dup 2)) | |
2828 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2829 | (const_int 0))) | |
2830 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2831 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2832 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2833 | "TARGET_POWER && reload_completed" | |
2834 | [(set (match_dup 0) | |
2835 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2836 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2837 | (set (match_dup 4) | |
2838 | (compare:CC (match_dup 0) | |
2839 | (const_int 0)))] | |
2840 | "") | |
fcce224d | 2841 | \f |
1fd4e8c1 RK |
2842 | ;; Rotate and shift insns, in all their variants. These support shifts, |
2843 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 2844 | (define_expand "insv" |
0ad91047 DE |
2845 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
2846 | (match_operand:SI 1 "const_int_operand" "") | |
2847 | (match_operand:SI 2 "const_int_operand" "")) | |
2848 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
2849 | "" |
2850 | " | |
2851 | { | |
2852 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2853 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2854 | compiler if the address of the structure is taken later. */ | |
2855 | if (GET_CODE (operands[0]) == SUBREG | |
2856 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2857 | FAIL; | |
a78e33fc DE |
2858 | |
2859 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
2860 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
2861 | else | |
2862 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
2863 | DONE; | |
034c1be0 MM |
2864 | }") |
2865 | ||
a78e33fc | 2866 | (define_insn "insvsi" |
cd2b37d9 | 2867 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
2868 | (match_operand:SI 1 "const_int_operand" "i") |
2869 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 2870 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
2871 | "" |
2872 | "* | |
2873 | { | |
2874 | int start = INTVAL (operands[2]) & 31; | |
2875 | int size = INTVAL (operands[1]) & 31; | |
2876 | ||
89e9f3a8 MM |
2877 | operands[4] = GEN_INT (32 - start - size); |
2878 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2879 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2880 | }" |
2881 | [(set_attr "type" "insert_word")]) | |
1fd4e8c1 | 2882 | |
a78e33fc | 2883 | (define_insn "*insvsi_internal1" |
d56d506a RK |
2884 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2885 | (match_operand:SI 1 "const_int_operand" "i") | |
2886 | (match_operand:SI 2 "const_int_operand" "i")) | |
6d0a8091 | 2887 | (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
d56d506a | 2888 | (match_operand:SI 4 "const_int_operand" "i")))] |
f0dc3f49 | 2889 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2890 | "* |
2891 | { | |
2892 | int shift = INTVAL (operands[4]) & 31; | |
2893 | int start = INTVAL (operands[2]) & 31; | |
2894 | int size = INTVAL (operands[1]) & 31; | |
2895 | ||
89e9f3a8 | 2896 | operands[4] = GEN_INT (shift - start - size); |
6d0a8091 | 2897 | operands[1] = GEN_INT (start + size - 1); |
a66078ee | 2898 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2899 | }" |
2900 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2901 | |
a78e33fc | 2902 | (define_insn "*insvsi_internal2" |
d56d506a RK |
2903 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2904 | (match_operand:SI 1 "const_int_operand" "i") | |
2905 | (match_operand:SI 2 "const_int_operand" "i")) | |
2906 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2907 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2908 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2909 | "* |
2910 | { | |
2911 | int shift = INTVAL (operands[4]) & 31; | |
2912 | int start = INTVAL (operands[2]) & 31; | |
2913 | int size = INTVAL (operands[1]) & 31; | |
2914 | ||
89e9f3a8 MM |
2915 | operands[4] = GEN_INT (32 - shift - start - size); |
2916 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2917 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2918 | }" |
2919 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2920 | |
a78e33fc | 2921 | (define_insn "*insvsi_internal3" |
d56d506a RK |
2922 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2923 | (match_operand:SI 1 "const_int_operand" "i") | |
2924 | (match_operand:SI 2 "const_int_operand" "i")) | |
2925 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2926 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 2927 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2928 | "* |
2929 | { | |
2930 | int shift = INTVAL (operands[4]) & 31; | |
2931 | int start = INTVAL (operands[2]) & 31; | |
2932 | int size = INTVAL (operands[1]) & 31; | |
2933 | ||
89e9f3a8 MM |
2934 | operands[4] = GEN_INT (32 - shift - start - size); |
2935 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2936 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2937 | }" |
2938 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2939 | |
a78e33fc | 2940 | (define_insn "*insvsi_internal4" |
d56d506a RK |
2941 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2942 | (match_operand:SI 1 "const_int_operand" "i") | |
2943 | (match_operand:SI 2 "const_int_operand" "i")) | |
2944 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2945 | (match_operand:SI 4 "const_int_operand" "i") | |
2946 | (match_operand:SI 5 "const_int_operand" "i")))] | |
2947 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
2948 | "* | |
2949 | { | |
2950 | int extract_start = INTVAL (operands[5]) & 31; | |
2951 | int extract_size = INTVAL (operands[4]) & 31; | |
2952 | int insert_start = INTVAL (operands[2]) & 31; | |
2953 | int insert_size = INTVAL (operands[1]) & 31; | |
2954 | ||
2955 | /* Align extract field with insert field */ | |
3a598fbe | 2956 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 2957 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 2958 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
8e8238f1 DE |
2959 | }" |
2960 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2961 | |
f241bf89 EC |
2962 | ;; combine patterns for rlwimi |
2963 | (define_insn "*insvsi_internal5" | |
2964 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2965 | (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") | |
2966 | (match_operand:SI 1 "mask_operand" "i")) | |
2967 | (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2968 | (match_operand:SI 2 "const_int_operand" "i")) | |
2969 | (match_operand:SI 5 "mask_operand" "i"))))] | |
2970 | "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" | |
2971 | "* | |
2972 | { | |
2973 | int me = extract_ME(operands[5]); | |
2974 | int mb = extract_MB(operands[5]); | |
2975 | operands[4] = GEN_INT(32 - INTVAL(operands[2])); | |
2976 | operands[2] = GEN_INT(mb); | |
2977 | operands[1] = GEN_INT(me); | |
2978 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; | |
2979 | }" | |
2980 | [(set_attr "type" "insert_word")]) | |
2981 | ||
2982 | (define_insn "*insvsi_internal6" | |
2983 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2984 | (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2985 | (match_operand:SI 2 "const_int_operand" "i")) | |
2986 | (match_operand:SI 5 "mask_operand" "i")) | |
2987 | (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") | |
2988 | (match_operand:SI 1 "mask_operand" "i"))))] | |
2989 | "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" | |
2990 | "* | |
2991 | { | |
2992 | int me = extract_ME(operands[5]); | |
2993 | int mb = extract_MB(operands[5]); | |
2994 | operands[4] = GEN_INT(32 - INTVAL(operands[2])); | |
2995 | operands[2] = GEN_INT(mb); | |
2996 | operands[1] = GEN_INT(me); | |
2997 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; | |
2998 | }" | |
2999 | [(set_attr "type" "insert_word")]) | |
3000 | ||
a78e33fc | 3001 | (define_insn "insvdi" |
685f3906 | 3002 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3003 | (match_operand:SI 1 "const_int_operand" "i") |
3004 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3005 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3006 | "TARGET_POWERPC64" | |
3007 | "* | |
3008 | { | |
3009 | int start = INTVAL (operands[2]) & 63; | |
3010 | int size = INTVAL (operands[1]) & 63; | |
3011 | ||
a78e33fc DE |
3012 | operands[1] = GEN_INT (64 - start - size); |
3013 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3014 | }") |
3015 | ||
11ac38b2 DE |
3016 | (define_insn "*insvdi_internal2" |
3017 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
3018 | (match_operand:SI 1 "const_int_operand" "i") | |
3019 | (match_operand:SI 2 "const_int_operand" "i")) | |
3020 | (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") | |
3021 | (match_operand:SI 4 "const_int_operand" "i")))] | |
3022 | "TARGET_POWERPC64 | |
3023 | && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" | |
3024 | "* | |
3025 | { | |
3026 | int shift = INTVAL (operands[4]) & 63; | |
3027 | int start = (INTVAL (operands[2]) & 63) - 32; | |
3028 | int size = INTVAL (operands[1]) & 63; | |
3029 | ||
3030 | operands[4] = GEN_INT (64 - shift - start - size); | |
3031 | operands[2] = GEN_INT (start); | |
3032 | operands[1] = GEN_INT (start + size - 1); | |
3033 | return \"rlwimi %0,%3,%h4,%h2,%h1\"; | |
3034 | }") | |
3035 | ||
3036 | (define_insn "*insvdi_internal3" | |
3037 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
3038 | (match_operand:SI 1 "const_int_operand" "i") | |
3039 | (match_operand:SI 2 "const_int_operand" "i")) | |
3040 | (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") | |
3041 | (match_operand:SI 4 "const_int_operand" "i")))] | |
3042 | "TARGET_POWERPC64 | |
3043 | && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" | |
3044 | "* | |
3045 | { | |
3046 | int shift = INTVAL (operands[4]) & 63; | |
3047 | int start = (INTVAL (operands[2]) & 63) - 32; | |
3048 | int size = INTVAL (operands[1]) & 63; | |
3049 | ||
3050 | operands[4] = GEN_INT (64 - shift - start - size); | |
3051 | operands[2] = GEN_INT (start); | |
3052 | operands[1] = GEN_INT (start + size - 1); | |
3053 | return \"rlwimi %0,%3,%h4,%h2,%h1\"; | |
3054 | }") | |
3055 | ||
034c1be0 | 3056 | (define_expand "extzv" |
0ad91047 DE |
3057 | [(set (match_operand 0 "gpc_reg_operand" "") |
3058 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3059 | (match_operand:SI 2 "const_int_operand" "") | |
3060 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3061 | "" |
3062 | " | |
3063 | { | |
3064 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3065 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3066 | compiler if the address of the structure is taken later. */ | |
3067 | if (GET_CODE (operands[0]) == SUBREG | |
3068 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3069 | FAIL; | |
a78e33fc DE |
3070 | |
3071 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3072 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3073 | else | |
3074 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3075 | DONE; | |
034c1be0 MM |
3076 | }") |
3077 | ||
a78e33fc | 3078 | (define_insn "extzvsi" |
cd2b37d9 RK |
3079 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3080 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3081 | (match_operand:SI 2 "const_int_operand" "i") |
3082 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3083 | "" | |
3084 | "* | |
3085 | { | |
3086 | int start = INTVAL (operands[3]) & 31; | |
3087 | int size = INTVAL (operands[2]) & 31; | |
3088 | ||
3089 | if (start + size >= 32) | |
3090 | operands[3] = const0_rtx; | |
3091 | else | |
89e9f3a8 | 3092 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3093 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3094 | }") |
3095 | ||
a78e33fc | 3096 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3097 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3098 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3099 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3100 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3101 | (const_int 0))) |
9ebbca7d | 3102 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3103 | "" |
1fd4e8c1 RK |
3104 | "* |
3105 | { | |
3106 | int start = INTVAL (operands[3]) & 31; | |
3107 | int size = INTVAL (operands[2]) & 31; | |
3108 | ||
9ebbca7d GK |
3109 | /* Force split for non-cc0 compare. */ |
3110 | if (which_alternative == 1) | |
3111 | return \"#\"; | |
3112 | ||
43a88a8c | 3113 | /* If the bit-field being tested fits in the upper or lower half of a |
a7a975e1 RK |
3114 | word, it is possible to use andiu. or andil. to test it. This is |
3115 | useful because the condition register set-use delay is smaller for | |
3116 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3117 | position is 0 because the LT and GT bits may be set wrong. */ | |
3118 | ||
3119 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3120 | { |
3a598fbe | 3121 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3122 | - (1 << (16 - (start & 15) - size)))); |
3123 | if (start < 16) | |
ca7f5001 | 3124 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3125 | else |
ca7f5001 | 3126 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3127 | } |
7e69e155 | 3128 | |
1fd4e8c1 RK |
3129 | if (start + size >= 32) |
3130 | operands[3] = const0_rtx; | |
3131 | else | |
89e9f3a8 | 3132 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3133 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3134 | }" |
9ebbca7d GK |
3135 | [(set_attr "type" "compare") |
3136 | (set_attr "length" "4,8")]) | |
3137 | ||
3138 | (define_split | |
3139 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3140 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3141 | (match_operand:SI 2 "const_int_operand" "") | |
3142 | (match_operand:SI 3 "const_int_operand" "")) | |
3143 | (const_int 0))) | |
3144 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3145 | "reload_completed" |
9ebbca7d GK |
3146 | [(set (match_dup 4) |
3147 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3148 | (match_dup 3))) | |
3149 | (set (match_dup 0) | |
3150 | (compare:CC (match_dup 4) | |
3151 | (const_int 0)))] | |
3152 | "") | |
1fd4e8c1 | 3153 | |
a78e33fc | 3154 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3155 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3156 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3157 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3158 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3159 | (const_int 0))) |
9ebbca7d | 3160 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3161 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
ce71f754 | 3162 | "" |
1fd4e8c1 RK |
3163 | "* |
3164 | { | |
3165 | int start = INTVAL (operands[3]) & 31; | |
3166 | int size = INTVAL (operands[2]) & 31; | |
3167 | ||
9ebbca7d GK |
3168 | /* Force split for non-cc0 compare. */ |
3169 | if (which_alternative == 1) | |
3170 | return \"#\"; | |
3171 | ||
bc401279 | 3172 | /* Since we are using the output value, we can't ignore any need for |
43a88a8c | 3173 | a shift. The bit-field must end at the LSB. */ |
bc401279 | 3174 | if (start >= 16 && start + size == 32) |
df031c43 | 3175 | { |
bc401279 AM |
3176 | operands[3] = GEN_INT ((1 << size) - 1); |
3177 | return \"{andil.|andi.} %0,%1,%3\"; | |
df031c43 | 3178 | } |
7e69e155 | 3179 | |
1fd4e8c1 RK |
3180 | if (start + size >= 32) |
3181 | operands[3] = const0_rtx; | |
3182 | else | |
89e9f3a8 | 3183 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3184 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3185 | }" |
ce71f754 | 3186 | [(set_attr "type" "compare") |
9ebbca7d GK |
3187 | (set_attr "length" "4,8")]) |
3188 | ||
3189 | (define_split | |
3190 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3191 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3192 | (match_operand:SI 2 "const_int_operand" "") | |
3193 | (match_operand:SI 3 "const_int_operand" "")) | |
3194 | (const_int 0))) | |
3195 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3196 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
ce71f754 | 3197 | "reload_completed" |
9ebbca7d GK |
3198 | [(set (match_dup 0) |
3199 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3200 | (set (match_dup 4) | |
3201 | (compare:CC (match_dup 0) | |
3202 | (const_int 0)))] | |
3203 | "") | |
1fd4e8c1 | 3204 | |
a78e33fc | 3205 | (define_insn "extzvdi" |
685f3906 DE |
3206 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3207 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3208 | (match_operand:SI 2 "const_int_operand" "i") |
3209 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3210 | "TARGET_POWERPC64" |
3211 | "* | |
3212 | { | |
3213 | int start = INTVAL (operands[3]) & 63; | |
3214 | int size = INTVAL (operands[2]) & 63; | |
3215 | ||
3216 | if (start + size >= 64) | |
3217 | operands[3] = const0_rtx; | |
3218 | else | |
89e9f3a8 MM |
3219 | operands[3] = GEN_INT (start + size); |
3220 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3221 | return \"rldicl %0,%1,%3,%2\"; |
3222 | }") | |
3223 | ||
a78e33fc | 3224 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3225 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3226 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3227 | (match_operand:SI 2 "const_int_operand" "i") |
3228 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3229 | (const_int 0))) |
29ae5b89 | 3230 | (clobber (match_scratch:DI 4 "=r"))] |
683bdff7 | 3231 | "TARGET_64BIT" |
685f3906 DE |
3232 | "* |
3233 | { | |
3234 | int start = INTVAL (operands[3]) & 63; | |
3235 | int size = INTVAL (operands[2]) & 63; | |
3236 | ||
3237 | if (start + size >= 64) | |
3238 | operands[3] = const0_rtx; | |
3239 | else | |
89e9f3a8 MM |
3240 | operands[3] = GEN_INT (start + size); |
3241 | operands[2] = GEN_INT (64 - size); | |
685f3906 | 3242 | return \"rldicl. %4,%1,%3,%2\"; |
9a3c428b DE |
3243 | }" |
3244 | [(set_attr "type" "compare")]) | |
685f3906 | 3245 | |
a78e33fc | 3246 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3247 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3248 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3249 | (match_operand:SI 2 "const_int_operand" "i") |
3250 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3251 | (const_int 0))) |
29ae5b89 | 3252 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 | 3253 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
683bdff7 | 3254 | "TARGET_64BIT" |
685f3906 DE |
3255 | "* |
3256 | { | |
3257 | int start = INTVAL (operands[3]) & 63; | |
3258 | int size = INTVAL (operands[2]) & 63; | |
3259 | ||
3260 | if (start + size >= 64) | |
3261 | operands[3] = const0_rtx; | |
3262 | else | |
89e9f3a8 MM |
3263 | operands[3] = GEN_INT (start + size); |
3264 | operands[2] = GEN_INT (64 - size); | |
685f3906 | 3265 | return \"rldicl. %0,%1,%3,%2\"; |
9a3c428b DE |
3266 | }" |
3267 | [(set_attr "type" "compare")]) | |
685f3906 | 3268 | |
1fd4e8c1 | 3269 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3270 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3271 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3272 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3273 | "" | |
ca7f5001 | 3274 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3275 | |
a260abc9 | 3276 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3277 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3278 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3279 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3280 | (const_int 0))) |
9ebbca7d | 3281 | (clobber (match_scratch:SI 3 "=r,r"))] |
ce71f754 | 3282 | "" |
9ebbca7d GK |
3283 | "@ |
3284 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3285 | #" | |
3286 | [(set_attr "type" "delayed_compare") | |
3287 | (set_attr "length" "4,8")]) | |
3288 | ||
3289 | (define_split | |
3290 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3291 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3292 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3293 | (const_int 0))) | |
3294 | (clobber (match_scratch:SI 3 ""))] | |
ce71f754 | 3295 | "reload_completed" |
9ebbca7d GK |
3296 | [(set (match_dup 3) |
3297 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3298 | (set (match_dup 0) | |
3299 | (compare:CC (match_dup 3) | |
3300 | (const_int 0)))] | |
3301 | "") | |
1fd4e8c1 | 3302 | |
a260abc9 | 3303 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3304 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3305 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3306 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3307 | (const_int 0))) |
9ebbca7d | 3308 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3309 | (rotate:SI (match_dup 1) (match_dup 2)))] |
ce71f754 | 3310 | "" |
9ebbca7d GK |
3311 | "@ |
3312 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3313 | #" | |
3314 | [(set_attr "type" "delayed_compare") | |
3315 | (set_attr "length" "4,8")]) | |
3316 | ||
3317 | (define_split | |
3318 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3319 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3320 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3321 | (const_int 0))) | |
3322 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3323 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
ce71f754 | 3324 | "reload_completed" |
9ebbca7d GK |
3325 | [(set (match_dup 0) |
3326 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3327 | (set (match_dup 3) | |
3328 | (compare:CC (match_dup 0) | |
3329 | (const_int 0)))] | |
3330 | "") | |
1fd4e8c1 | 3331 | |
a260abc9 | 3332 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3333 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3334 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3335 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
ce71f754 | 3336 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3337 | "" |
ca7f5001 | 3338 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3339 | |
a260abc9 | 3340 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3341 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3342 | (compare:CC (and:SI |
9ebbca7d GK |
3343 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3344 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3345 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3346 | (const_int 0))) |
9ebbca7d | 3347 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3348 | "" |
9ebbca7d GK |
3349 | "@ |
3350 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3351 | #" | |
3352 | [(set_attr "type" "delayed_compare") | |
3353 | (set_attr "length" "4,8")]) | |
3354 | ||
3355 | (define_split | |
3356 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3357 | (compare:CC (and:SI | |
3358 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3359 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3360 | (match_operand:SI 3 "mask_operand" "")) | |
3361 | (const_int 0))) | |
3362 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3363 | "reload_completed" |
9ebbca7d GK |
3364 | [(set (match_dup 4) |
3365 | (and:SI (rotate:SI (match_dup 1) | |
3366 | (match_dup 2)) | |
3367 | (match_dup 3))) | |
3368 | (set (match_dup 0) | |
3369 | (compare:CC (match_dup 4) | |
3370 | (const_int 0)))] | |
3371 | "") | |
1fd4e8c1 | 3372 | |
a260abc9 | 3373 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3374 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3375 | (compare:CC (and:SI |
9ebbca7d GK |
3376 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3377 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3378 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3379 | (const_int 0))) |
9ebbca7d | 3380 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3381 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3382 | "" |
9ebbca7d GK |
3383 | "@ |
3384 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3385 | #" | |
3386 | [(set_attr "type" "delayed_compare") | |
3387 | (set_attr "length" "4,8")]) | |
3388 | ||
3389 | (define_split | |
3390 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3391 | (compare:CC (and:SI | |
3392 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3393 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3394 | (match_operand:SI 3 "mask_operand" "")) | |
3395 | (const_int 0))) | |
3396 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3397 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3398 | "reload_completed" |
9ebbca7d GK |
3399 | [(set (match_dup 0) |
3400 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3401 | (set (match_dup 4) | |
3402 | (compare:CC (match_dup 0) | |
3403 | (const_int 0)))] | |
3404 | "") | |
1fd4e8c1 | 3405 | |
a260abc9 | 3406 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3407 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3408 | (zero_extend:SI |
3409 | (subreg:QI | |
cd2b37d9 | 3410 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3411 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3412 | "" | |
ca7f5001 | 3413 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3414 | |
a260abc9 | 3415 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3416 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3417 | (compare:CC (zero_extend:SI |
3418 | (subreg:QI | |
9ebbca7d GK |
3419 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3420 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3421 | (const_int 0))) |
9ebbca7d | 3422 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3423 | "" |
9ebbca7d GK |
3424 | "@ |
3425 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3426 | #" | |
3427 | [(set_attr "type" "delayed_compare") | |
3428 | (set_attr "length" "4,8")]) | |
3429 | ||
3430 | (define_split | |
3431 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3432 | (compare:CC (zero_extend:SI | |
3433 | (subreg:QI | |
3434 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3435 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3436 | (const_int 0))) | |
3437 | (clobber (match_scratch:SI 3 ""))] | |
3438 | "reload_completed" | |
3439 | [(set (match_dup 3) | |
3440 | (zero_extend:SI (subreg:QI | |
3441 | (rotate:SI (match_dup 1) | |
3442 | (match_dup 2)) 0))) | |
3443 | (set (match_dup 0) | |
3444 | (compare:CC (match_dup 3) | |
3445 | (const_int 0)))] | |
3446 | "") | |
1fd4e8c1 | 3447 | |
a260abc9 | 3448 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3449 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3450 | (compare:CC (zero_extend:SI |
3451 | (subreg:QI | |
9ebbca7d GK |
3452 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3453 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3454 | (const_int 0))) |
9ebbca7d | 3455 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3456 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3457 | "" | |
9ebbca7d GK |
3458 | "@ |
3459 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3460 | #" | |
3461 | [(set_attr "type" "delayed_compare") | |
3462 | (set_attr "length" "4,8")]) | |
3463 | ||
3464 | (define_split | |
3465 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3466 | (compare:CC (zero_extend:SI | |
3467 | (subreg:QI | |
3468 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3469 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3470 | (const_int 0))) | |
3471 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3472 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3473 | "reload_completed" | |
3474 | [(set (match_dup 0) | |
3475 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3476 | (set (match_dup 3) | |
3477 | (compare:CC (match_dup 0) | |
3478 | (const_int 0)))] | |
3479 | "") | |
1fd4e8c1 | 3480 | |
a260abc9 | 3481 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3482 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3483 | (zero_extend:SI |
3484 | (subreg:HI | |
cd2b37d9 | 3485 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3486 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3487 | "" | |
ca7f5001 | 3488 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3489 | |
a260abc9 | 3490 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3491 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3492 | (compare:CC (zero_extend:SI |
3493 | (subreg:HI | |
9ebbca7d GK |
3494 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3495 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3496 | (const_int 0))) |
9ebbca7d | 3497 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3498 | "" |
9ebbca7d GK |
3499 | "@ |
3500 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3501 | #" | |
3502 | [(set_attr "type" "delayed_compare") | |
3503 | (set_attr "length" "4,8")]) | |
3504 | ||
3505 | (define_split | |
3506 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3507 | (compare:CC (zero_extend:SI | |
3508 | (subreg:HI | |
3509 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3510 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3511 | (const_int 0))) | |
3512 | (clobber (match_scratch:SI 3 ""))] | |
3513 | "reload_completed" | |
3514 | [(set (match_dup 3) | |
3515 | (zero_extend:SI (subreg:HI | |
3516 | (rotate:SI (match_dup 1) | |
3517 | (match_dup 2)) 0))) | |
3518 | (set (match_dup 0) | |
3519 | (compare:CC (match_dup 3) | |
3520 | (const_int 0)))] | |
3521 | "") | |
1fd4e8c1 | 3522 | |
a260abc9 | 3523 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3524 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3525 | (compare:CC (zero_extend:SI |
3526 | (subreg:HI | |
9ebbca7d GK |
3527 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3528 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3529 | (const_int 0))) |
9ebbca7d | 3530 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3531 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3532 | "" | |
9ebbca7d GK |
3533 | "@ |
3534 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3535 | #" | |
3536 | [(set_attr "type" "delayed_compare") | |
3537 | (set_attr "length" "4,8")]) | |
3538 | ||
3539 | (define_split | |
3540 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3541 | (compare:CC (zero_extend:SI | |
3542 | (subreg:HI | |
3543 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3544 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3545 | (const_int 0))) | |
3546 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3547 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3548 | "reload_completed" | |
3549 | [(set (match_dup 0) | |
3550 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3551 | (set (match_dup 3) | |
3552 | (compare:CC (match_dup 0) | |
3553 | (const_int 0)))] | |
3554 | "") | |
1fd4e8c1 RK |
3555 | |
3556 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3557 | ;; SHIFT_COUNT_TRUNCATED. | |
3558 | ||
ca7f5001 RK |
3559 | (define_expand "ashlsi3" |
3560 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3561 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3562 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3563 | "" | |
3564 | " | |
3565 | { | |
3566 | if (TARGET_POWER) | |
3567 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3568 | else | |
25c341fa | 3569 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3570 | DONE; |
3571 | }") | |
3572 | ||
3573 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3574 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3575 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3576 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3577 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3578 | "TARGET_POWER" |
1fd4e8c1 RK |
3579 | "@ |
3580 | sle %0,%1,%2 | |
9ebbca7d | 3581 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3582 | |
25c341fa | 3583 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3584 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3585 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3586 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3587 | "! TARGET_POWER" |
9ebbca7d | 3588 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3589 | |
3590 | (define_insn "" | |
9ebbca7d GK |
3591 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3592 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3593 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3594 | (const_int 0))) |
9ebbca7d GK |
3595 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
3596 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 3597 | "TARGET_POWER" |
1fd4e8c1 RK |
3598 | "@ |
3599 | sle. %3,%1,%2 | |
9ebbca7d GK |
3600 | {sli.|slwi.} %3,%1,%h2 |
3601 | # | |
3602 | #" | |
3603 | [(set_attr "type" "delayed_compare") | |
3604 | (set_attr "length" "4,4,8,8")]) | |
3605 | ||
3606 | (define_split | |
3607 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3608 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3609 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3610 | (const_int 0))) | |
3611 | (clobber (match_scratch:SI 3 "")) | |
3612 | (clobber (match_scratch:SI 4 ""))] | |
3613 | "TARGET_POWER && reload_completed" | |
3614 | [(parallel [(set (match_dup 3) | |
3615 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3616 | (clobber (match_dup 4))]) | |
3617 | (set (match_dup 0) | |
3618 | (compare:CC (match_dup 3) | |
3619 | (const_int 0)))] | |
3620 | "") | |
25c341fa | 3621 | |
ca7f5001 | 3622 | (define_insn "" |
9ebbca7d GK |
3623 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3624 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3625 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3626 | (const_int 0))) |
9ebbca7d | 3627 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 3628 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3629 | "@ |
3630 | {sl|slw}%I2. %3,%1,%h2 | |
3631 | #" | |
3632 | [(set_attr "type" "delayed_compare") | |
3633 | (set_attr "length" "4,8")]) | |
3634 | ||
3635 | (define_split | |
3636 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3637 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3638 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3639 | (const_int 0))) | |
3640 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3641 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3642 | [(set (match_dup 3) |
3643 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3644 | (set (match_dup 0) | |
3645 | (compare:CC (match_dup 3) | |
3646 | (const_int 0)))] | |
3647 | "") | |
1fd4e8c1 RK |
3648 | |
3649 | (define_insn "" | |
9ebbca7d GK |
3650 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3651 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3652 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3653 | (const_int 0))) |
9ebbca7d | 3654 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 3655 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3656 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 3657 | "TARGET_POWER" |
1fd4e8c1 RK |
3658 | "@ |
3659 | sle. %0,%1,%2 | |
9ebbca7d GK |
3660 | {sli.|slwi.} %0,%1,%h2 |
3661 | # | |
3662 | #" | |
3663 | [(set_attr "type" "delayed_compare") | |
3664 | (set_attr "length" "4,4,8,8")]) | |
3665 | ||
3666 | (define_split | |
3667 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3668 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3669 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3670 | (const_int 0))) | |
3671 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3672 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3673 | (clobber (match_scratch:SI 4 ""))] | |
3674 | "TARGET_POWER && reload_completed" | |
3675 | [(parallel [(set (match_dup 0) | |
3676 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3677 | (clobber (match_dup 4))]) | |
3678 | (set (match_dup 3) | |
3679 | (compare:CC (match_dup 0) | |
3680 | (const_int 0)))] | |
3681 | "") | |
25c341fa | 3682 | |
ca7f5001 | 3683 | (define_insn "" |
9ebbca7d GK |
3684 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3685 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3686 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3687 | (const_int 0))) |
9ebbca7d | 3688 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 3689 | (ashift:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 3690 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3691 | "@ |
3692 | {sl|slw}%I2. %0,%1,%h2 | |
3693 | #" | |
3694 | [(set_attr "type" "delayed_compare") | |
3695 | (set_attr "length" "4,8")]) | |
3696 | ||
3697 | (define_split | |
3698 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3699 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3700 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3701 | (const_int 0))) | |
3702 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3703 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 3704 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3705 | [(set (match_dup 0) |
3706 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3707 | (set (match_dup 3) | |
3708 | (compare:CC (match_dup 0) | |
3709 | (const_int 0)))] | |
3710 | "") | |
1fd4e8c1 | 3711 | |
915167f5 | 3712 | (define_insn "rlwinm" |
cd2b37d9 RK |
3713 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3714 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3715 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3716 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3717 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 3718 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3719 | |
3720 | (define_insn "" | |
9ebbca7d | 3721 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3722 | (compare:CC |
9ebbca7d GK |
3723 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3724 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3725 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3726 | (const_int 0))) |
9ebbca7d | 3727 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3728 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3729 | "@ |
3730 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
3731 | #" | |
3732 | [(set_attr "type" "delayed_compare") | |
3733 | (set_attr "length" "4,8")]) | |
3734 | ||
3735 | (define_split | |
3736 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3737 | (compare:CC | |
3738 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3739 | (match_operand:SI 2 "const_int_operand" "")) | |
3740 | (match_operand:SI 3 "mask_operand" "")) | |
3741 | (const_int 0))) | |
3742 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3743 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3744 | [(set (match_dup 4) |
3745 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
3746 | (match_dup 3))) | |
3747 | (set (match_dup 0) | |
3748 | (compare:CC (match_dup 4) | |
3749 | (const_int 0)))] | |
3750 | "") | |
1fd4e8c1 RK |
3751 | |
3752 | (define_insn "" | |
9ebbca7d | 3753 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3754 | (compare:CC |
9ebbca7d GK |
3755 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3756 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3757 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3758 | (const_int 0))) |
9ebbca7d | 3759 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3760 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3761 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3762 | "@ |
3763 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
3764 | #" | |
3765 | [(set_attr "type" "delayed_compare") | |
3766 | (set_attr "length" "4,8")]) | |
3767 | ||
3768 | (define_split | |
3769 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3770 | (compare:CC | |
3771 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3772 | (match_operand:SI 2 "const_int_operand" "")) | |
3773 | (match_operand:SI 3 "mask_operand" "")) | |
3774 | (const_int 0))) | |
3775 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3776 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3777 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3778 | [(set (match_dup 0) |
3779 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3780 | (set (match_dup 4) | |
3781 | (compare:CC (match_dup 0) | |
3782 | (const_int 0)))] | |
3783 | "") | |
1fd4e8c1 | 3784 | |
ca7f5001 | 3785 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3786 | ;; "sli x,x,0". |
ca7f5001 RK |
3787 | (define_expand "lshrsi3" |
3788 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3789 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3790 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3791 | "" | |
3792 | " | |
3793 | { | |
3794 | if (TARGET_POWER) | |
3795 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
3796 | else | |
25c341fa | 3797 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3798 | DONE; |
3799 | }") | |
3800 | ||
3801 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
3802 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
3803 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3804 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
3805 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 3806 | "TARGET_POWER" |
1fd4e8c1 RK |
3807 | "@ |
3808 | sre %0,%1,%2 | |
bdf423cb | 3809 | mr %0,%1 |
ca7f5001 RK |
3810 | {s%A2i|s%A2wi} %0,%1,%h2") |
3811 | ||
25c341fa | 3812 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
3813 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3814 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3815 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 3816 | "! TARGET_POWER" |
bdf423cb MM |
3817 | "@ |
3818 | mr %0,%1 | |
3819 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
3820 | |
3821 | (define_insn "" | |
9ebbca7d GK |
3822 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
3823 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3824 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3825 | (const_int 0))) |
9ebbca7d GK |
3826 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
3827 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 3828 | "TARGET_POWER" |
1fd4e8c1 | 3829 | "@ |
29ae5b89 JL |
3830 | sre. %3,%1,%2 |
3831 | mr. %1,%1 | |
9ebbca7d GK |
3832 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
3833 | # | |
3834 | # | |
3835 | #" | |
3836 | [(set_attr "type" "delayed_compare") | |
3837 | (set_attr "length" "4,4,4,8,8,8")]) | |
3838 | ||
3839 | (define_split | |
3840 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3841 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3842 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3843 | (const_int 0))) | |
3844 | (clobber (match_scratch:SI 3 "")) | |
3845 | (clobber (match_scratch:SI 4 ""))] | |
3846 | "TARGET_POWER && reload_completed" | |
3847 | [(parallel [(set (match_dup 3) | |
3848 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3849 | (clobber (match_dup 4))]) | |
3850 | (set (match_dup 0) | |
3851 | (compare:CC (match_dup 3) | |
3852 | (const_int 0)))] | |
3853 | "") | |
ca7f5001 RK |
3854 | |
3855 | (define_insn "" | |
9ebbca7d GK |
3856 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3857 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3858 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 3859 | (const_int 0))) |
9ebbca7d | 3860 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
4b8a63d6 | 3861 | "! TARGET_POWER && TARGET_32BIT" |
bdf423cb MM |
3862 | "@ |
3863 | mr. %1,%1 | |
9ebbca7d GK |
3864 | {sr|srw}%I2. %3,%1,%h2 |
3865 | # | |
3866 | #" | |
3867 | [(set_attr "type" "delayed_compare") | |
3868 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 3869 | |
9ebbca7d GK |
3870 | (define_split |
3871 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3872 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3873 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3874 | (const_int 0))) | |
3875 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3876 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3877 | [(set (match_dup 3) |
3878 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3879 | (set (match_dup 0) | |
3880 | (compare:CC (match_dup 3) | |
3881 | (const_int 0)))] | |
3882 | "") | |
3883 | ||
3884 | (define_insn "" | |
3885 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
3886 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3887 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3888 | (const_int 0))) |
9ebbca7d | 3889 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 3890 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3891 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 3892 | "TARGET_POWER" |
1fd4e8c1 | 3893 | "@ |
29ae5b89 JL |
3894 | sre. %0,%1,%2 |
3895 | mr. %0,%1 | |
9ebbca7d GK |
3896 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
3897 | # | |
3898 | # | |
3899 | #" | |
3900 | [(set_attr "type" "delayed_compare") | |
3901 | (set_attr "length" "4,4,4,8,8,8")]) | |
3902 | ||
3903 | (define_split | |
3904 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3905 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3906 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3907 | (const_int 0))) | |
3908 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3909 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3910 | (clobber (match_scratch:SI 4 ""))] | |
3911 | "TARGET_POWER && reload_completed" | |
3912 | [(parallel [(set (match_dup 0) | |
3913 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3914 | (clobber (match_dup 4))]) | |
3915 | (set (match_dup 3) | |
3916 | (compare:CC (match_dup 0) | |
3917 | (const_int 0)))] | |
3918 | "") | |
ca7f5001 RK |
3919 | |
3920 | (define_insn "" | |
9ebbca7d GK |
3921 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3922 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3923 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 3924 | (const_int 0))) |
9ebbca7d | 3925 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 3926 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 3927 | "! TARGET_POWER && TARGET_32BIT" |
29ae5b89 JL |
3928 | "@ |
3929 | mr. %0,%1 | |
9ebbca7d GK |
3930 | {sr|srw}%I2. %0,%1,%h2 |
3931 | # | |
3932 | #" | |
3933 | [(set_attr "type" "delayed_compare") | |
3934 | (set_attr "length" "4,4,8,8")]) | |
3935 | ||
3936 | (define_split | |
3937 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3938 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3939 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3940 | (const_int 0))) | |
3941 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3942 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 3943 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3944 | [(set (match_dup 0) |
3945 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3946 | (set (match_dup 3) | |
3947 | (compare:CC (match_dup 0) | |
3948 | (const_int 0)))] | |
3949 | "") | |
1fd4e8c1 RK |
3950 | |
3951 | (define_insn "" | |
cd2b37d9 RK |
3952 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3953 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3954 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3955 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3956 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 3957 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
3958 | |
3959 | (define_insn "" | |
9ebbca7d | 3960 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3961 | (compare:CC |
9ebbca7d GK |
3962 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3963 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3964 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3965 | (const_int 0))) |
9ebbca7d | 3966 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3967 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3968 | "@ |
3969 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
3970 | #" | |
3971 | [(set_attr "type" "delayed_compare") | |
3972 | (set_attr "length" "4,8")]) | |
3973 | ||
3974 | (define_split | |
3975 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3976 | (compare:CC | |
3977 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3978 | (match_operand:SI 2 "const_int_operand" "")) | |
3979 | (match_operand:SI 3 "mask_operand" "")) | |
3980 | (const_int 0))) | |
3981 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3982 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3983 | [(set (match_dup 4) |
3984 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
3985 | (match_dup 3))) | |
3986 | (set (match_dup 0) | |
3987 | (compare:CC (match_dup 4) | |
3988 | (const_int 0)))] | |
3989 | "") | |
1fd4e8c1 RK |
3990 | |
3991 | (define_insn "" | |
9ebbca7d | 3992 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3993 | (compare:CC |
9ebbca7d GK |
3994 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3995 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3996 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3997 | (const_int 0))) |
9ebbca7d | 3998 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3999 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 4000 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4001 | "@ |
4002 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
4003 | #" | |
4004 | [(set_attr "type" "delayed_compare") | |
4005 | (set_attr "length" "4,8")]) | |
4006 | ||
4007 | (define_split | |
4008 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4009 | (compare:CC | |
4010 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4011 | (match_operand:SI 2 "const_int_operand" "")) | |
4012 | (match_operand:SI 3 "mask_operand" "")) | |
4013 | (const_int 0))) | |
4014 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4015 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 4016 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4017 | [(set (match_dup 0) |
4018 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4019 | (set (match_dup 4) | |
4020 | (compare:CC (match_dup 0) | |
4021 | (const_int 0)))] | |
4022 | "") | |
1fd4e8c1 RK |
4023 | |
4024 | (define_insn "" | |
cd2b37d9 | 4025 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4026 | (zero_extend:SI |
4027 | (subreg:QI | |
cd2b37d9 | 4028 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4029 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4030 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4031 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4032 | |
4033 | (define_insn "" | |
9ebbca7d | 4034 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4035 | (compare:CC |
4036 | (zero_extend:SI | |
4037 | (subreg:QI | |
9ebbca7d GK |
4038 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4039 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4040 | (const_int 0))) |
9ebbca7d | 4041 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4042 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4043 | "@ |
4044 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4045 | #" | |
4046 | [(set_attr "type" "delayed_compare") | |
4047 | (set_attr "length" "4,8")]) | |
4048 | ||
4049 | (define_split | |
4050 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4051 | (compare:CC | |
4052 | (zero_extend:SI | |
4053 | (subreg:QI | |
4054 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4055 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4056 | (const_int 0))) | |
4057 | (clobber (match_scratch:SI 3 ""))] | |
4058 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4059 | [(set (match_dup 3) | |
4060 | (zero_extend:SI (subreg:QI | |
4061 | (lshiftrt:SI (match_dup 1) | |
4062 | (match_dup 2)) 0))) | |
4063 | (set (match_dup 0) | |
4064 | (compare:CC (match_dup 3) | |
4065 | (const_int 0)))] | |
4066 | "") | |
1fd4e8c1 RK |
4067 | |
4068 | (define_insn "" | |
9ebbca7d | 4069 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4070 | (compare:CC |
4071 | (zero_extend:SI | |
4072 | (subreg:QI | |
9ebbca7d GK |
4073 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4074 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4075 | (const_int 0))) |
9ebbca7d | 4076 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4077 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4078 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4079 | "@ |
4080 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4081 | #" | |
4082 | [(set_attr "type" "delayed_compare") | |
4083 | (set_attr "length" "4,8")]) | |
4084 | ||
4085 | (define_split | |
4086 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4087 | (compare:CC | |
4088 | (zero_extend:SI | |
4089 | (subreg:QI | |
4090 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4091 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4092 | (const_int 0))) | |
4093 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4094 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4095 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4096 | [(set (match_dup 0) | |
4097 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4098 | (set (match_dup 3) | |
4099 | (compare:CC (match_dup 0) | |
4100 | (const_int 0)))] | |
4101 | "") | |
1fd4e8c1 RK |
4102 | |
4103 | (define_insn "" | |
cd2b37d9 | 4104 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4105 | (zero_extend:SI |
4106 | (subreg:HI | |
cd2b37d9 | 4107 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4108 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4109 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4110 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4111 | |
4112 | (define_insn "" | |
9ebbca7d | 4113 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4114 | (compare:CC |
4115 | (zero_extend:SI | |
4116 | (subreg:HI | |
9ebbca7d GK |
4117 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4118 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4119 | (const_int 0))) |
9ebbca7d | 4120 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4121 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4122 | "@ |
4123 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4124 | #" | |
4125 | [(set_attr "type" "delayed_compare") | |
4126 | (set_attr "length" "4,8")]) | |
4127 | ||
4128 | (define_split | |
4129 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4130 | (compare:CC | |
4131 | (zero_extend:SI | |
4132 | (subreg:HI | |
4133 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4134 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4135 | (const_int 0))) | |
4136 | (clobber (match_scratch:SI 3 ""))] | |
4137 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4138 | [(set (match_dup 3) | |
4139 | (zero_extend:SI (subreg:HI | |
4140 | (lshiftrt:SI (match_dup 1) | |
4141 | (match_dup 2)) 0))) | |
4142 | (set (match_dup 0) | |
4143 | (compare:CC (match_dup 3) | |
4144 | (const_int 0)))] | |
4145 | "") | |
1fd4e8c1 RK |
4146 | |
4147 | (define_insn "" | |
9ebbca7d | 4148 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4149 | (compare:CC |
4150 | (zero_extend:SI | |
4151 | (subreg:HI | |
9ebbca7d GK |
4152 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4153 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4154 | (const_int 0))) |
9ebbca7d | 4155 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4156 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4157 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4158 | "@ |
4159 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4160 | #" | |
4161 | [(set_attr "type" "delayed_compare") | |
4162 | (set_attr "length" "4,8")]) | |
4163 | ||
4164 | (define_split | |
4165 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4166 | (compare:CC | |
4167 | (zero_extend:SI | |
4168 | (subreg:HI | |
4169 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4170 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4171 | (const_int 0))) | |
4172 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4173 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4174 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4175 | [(set (match_dup 0) | |
4176 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4177 | (set (match_dup 3) | |
4178 | (compare:CC (match_dup 0) | |
4179 | (const_int 0)))] | |
4180 | "") | |
1fd4e8c1 RK |
4181 | |
4182 | (define_insn "" | |
cd2b37d9 | 4183 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4184 | (const_int 1) |
cd2b37d9 RK |
4185 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4186 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4187 | (const_int 31)))] |
ca7f5001 | 4188 | "TARGET_POWER" |
1fd4e8c1 RK |
4189 | "rrib %0,%1,%2") |
4190 | ||
4191 | (define_insn "" | |
cd2b37d9 | 4192 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4193 | (const_int 1) |
cd2b37d9 RK |
4194 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4195 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4196 | (const_int 31)))] |
ca7f5001 | 4197 | "TARGET_POWER" |
1fd4e8c1 RK |
4198 | "rrib %0,%1,%2") |
4199 | ||
4200 | (define_insn "" | |
cd2b37d9 | 4201 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4202 | (const_int 1) |
cd2b37d9 RK |
4203 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4204 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4205 | (const_int 1) |
4206 | (const_int 0)))] | |
ca7f5001 | 4207 | "TARGET_POWER" |
1fd4e8c1 RK |
4208 | "rrib %0,%1,%2") |
4209 | ||
ca7f5001 RK |
4210 | (define_expand "ashrsi3" |
4211 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4212 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4213 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4214 | "" | |
4215 | " | |
4216 | { | |
4217 | if (TARGET_POWER) | |
4218 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4219 | else | |
25c341fa | 4220 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4221 | DONE; |
4222 | }") | |
4223 | ||
4224 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4225 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4226 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4227 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4228 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4229 | "TARGET_POWER" |
1fd4e8c1 RK |
4230 | "@ |
4231 | srea %0,%1,%2 | |
ca7f5001 RK |
4232 | {srai|srawi} %0,%1,%h2") |
4233 | ||
25c341fa | 4234 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4235 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4236 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4237 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4238 | "! TARGET_POWER" |
d904e9ed | 4239 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4240 | |
4241 | (define_insn "" | |
9ebbca7d GK |
4242 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4243 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4244 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4245 | (const_int 0))) |
9ebbca7d GK |
4246 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4247 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4248 | "TARGET_POWER" |
1fd4e8c1 RK |
4249 | "@ |
4250 | srea. %3,%1,%2 | |
9ebbca7d GK |
4251 | {srai.|srawi.} %3,%1,%h2 |
4252 | # | |
4253 | #" | |
4254 | [(set_attr "type" "delayed_compare") | |
4255 | (set_attr "length" "4,4,8,8")]) | |
4256 | ||
4257 | (define_split | |
4258 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4259 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4260 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4261 | (const_int 0))) | |
4262 | (clobber (match_scratch:SI 3 "")) | |
4263 | (clobber (match_scratch:SI 4 ""))] | |
4264 | "TARGET_POWER && reload_completed" | |
4265 | [(parallel [(set (match_dup 3) | |
4266 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4267 | (clobber (match_dup 4))]) | |
4268 | (set (match_dup 0) | |
4269 | (compare:CC (match_dup 3) | |
4270 | (const_int 0)))] | |
4271 | "") | |
ca7f5001 RK |
4272 | |
4273 | (define_insn "" | |
9ebbca7d GK |
4274 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4275 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4276 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4277 | (const_int 0))) |
9ebbca7d | 4278 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4279 | "! TARGET_POWER" |
9ebbca7d GK |
4280 | "@ |
4281 | {sra|sraw}%I2. %3,%1,%h2 | |
4282 | #" | |
4283 | [(set_attr "type" "delayed_compare") | |
4284 | (set_attr "length" "4,8")]) | |
4285 | ||
4286 | (define_split | |
4287 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4288 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4289 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4290 | (const_int 0))) | |
4291 | (clobber (match_scratch:SI 3 ""))] | |
4292 | "! TARGET_POWER && reload_completed" | |
4293 | [(set (match_dup 3) | |
4294 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4295 | (set (match_dup 0) | |
4296 | (compare:CC (match_dup 3) | |
4297 | (const_int 0)))] | |
4298 | "") | |
1fd4e8c1 RK |
4299 | |
4300 | (define_insn "" | |
9ebbca7d GK |
4301 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4302 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4303 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4304 | (const_int 0))) |
9ebbca7d | 4305 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4306 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4307 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4308 | "TARGET_POWER" |
1fd4e8c1 RK |
4309 | "@ |
4310 | srea. %0,%1,%2 | |
9ebbca7d GK |
4311 | {srai.|srawi.} %0,%1,%h2 |
4312 | # | |
4313 | #" | |
4314 | [(set_attr "type" "delayed_compare") | |
4315 | (set_attr "length" "4,4,8,8")]) | |
4316 | ||
4317 | (define_split | |
4318 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4319 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4320 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4321 | (const_int 0))) | |
4322 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4323 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4324 | (clobber (match_scratch:SI 4 ""))] | |
4325 | "TARGET_POWER && reload_completed" | |
4326 | [(parallel [(set (match_dup 0) | |
4327 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4328 | (clobber (match_dup 4))]) | |
4329 | (set (match_dup 3) | |
4330 | (compare:CC (match_dup 0) | |
4331 | (const_int 0)))] | |
4332 | "") | |
1fd4e8c1 | 4333 | |
ca7f5001 | 4334 | (define_insn "" |
9ebbca7d GK |
4335 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4336 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4337 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4338 | (const_int 0))) |
9ebbca7d | 4339 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4340 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4341 | "! TARGET_POWER" |
9ebbca7d GK |
4342 | "@ |
4343 | {sra|sraw}%I2. %0,%1,%h2 | |
4344 | #" | |
4345 | [(set_attr "type" "delayed_compare") | |
4346 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4347 | \f |
9ebbca7d GK |
4348 | (define_split |
4349 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4350 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4351 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4352 | (const_int 0))) | |
4353 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4354 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4355 | "! TARGET_POWER && reload_completed" | |
4356 | [(set (match_dup 0) | |
4357 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4358 | (set (match_dup 3) | |
4359 | (compare:CC (match_dup 0) | |
4360 | (const_int 0)))] | |
4361 | "") | |
4362 | ||
1fd4e8c1 RK |
4363 | ;; Floating-point insns, excluding normal data motion. |
4364 | ;; | |
ca7f5001 RK |
4365 | ;; PowerPC has a full set of single-precision floating point instructions. |
4366 | ;; | |
4367 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4368 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4369 | ;; The only conversions we will do will be when storing to memory. In that | |
4370 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4371 | ;; |
4372 | ;; Note that when we store into a single-precision memory location, we need to | |
4373 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4374 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4375 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4376 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4377 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4378 | ||
99176a91 AH |
4379 | (define_expand "extendsfdf2" |
4380 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
97c54d9a | 4381 | (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))] |
99176a91 AH |
4382 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" |
4383 | "") | |
4384 | ||
4385 | (define_insn_and_split "*extendsfdf2_fpr" | |
97c54d9a DE |
4386 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f") |
4387 | (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))] | |
a3170dc6 | 4388 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
11ac38b2 DE |
4389 | "@ |
4390 | # | |
97c54d9a DE |
4391 | fmr %0,%1 |
4392 | lfs%U1%X1 %0,%1" | |
d7b1468b | 4393 | "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])" |
11ac38b2 | 4394 | [(const_int 0)] |
5c30aff8 | 4395 | { |
11ac38b2 DE |
4396 | emit_note (NOTE_INSN_DELETED); |
4397 | DONE; | |
4398 | } | |
97c54d9a | 4399 | [(set_attr "type" "fp,fp,fpload")]) |
1fd4e8c1 | 4400 | |
7a2f7870 AH |
4401 | (define_expand "truncdfsf2" |
4402 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4403 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4404 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4405 | "") | |
4406 | ||
99176a91 | 4407 | (define_insn "*truncdfsf2_fpr" |
cd2b37d9 RK |
4408 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4409 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4410 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
dcac138d | 4411 | "frsp %0,%1" |
1fd4e8c1 RK |
4412 | [(set_attr "type" "fp")]) |
4413 | ||
455350f4 RK |
4414 | (define_insn "aux_truncdfsf2" |
4415 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
615158e2 | 4416 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))] |
a3170dc6 | 4417 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
455350f4 RK |
4418 | "frsp %0,%1" |
4419 | [(set_attr "type" "fp")]) | |
4420 | ||
a3170dc6 AH |
4421 | (define_expand "negsf2" |
4422 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4423 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4424 | "TARGET_HARD_FLOAT" | |
4425 | "") | |
4426 | ||
4427 | (define_insn "*negsf2" | |
cd2b37d9 RK |
4428 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4429 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4430 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4431 | "fneg %0,%1" |
4432 | [(set_attr "type" "fp")]) | |
4433 | ||
a3170dc6 AH |
4434 | (define_expand "abssf2" |
4435 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4436 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4437 | "TARGET_HARD_FLOAT" | |
4438 | "") | |
4439 | ||
4440 | (define_insn "*abssf2" | |
cd2b37d9 RK |
4441 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4442 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4443 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4444 | "fabs %0,%1" |
4445 | [(set_attr "type" "fp")]) | |
4446 | ||
4447 | (define_insn "" | |
cd2b37d9 RK |
4448 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4449 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4450 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4451 | "fnabs %0,%1" |
4452 | [(set_attr "type" "fp")]) | |
4453 | ||
ca7f5001 RK |
4454 | (define_expand "addsf3" |
4455 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4456 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4457 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4458 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4459 | "") |
4460 | ||
4461 | (define_insn "" | |
cd2b37d9 RK |
4462 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4463 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4464 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4465 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4466 | "fadds %0,%1,%2" |
ca7f5001 RK |
4467 | [(set_attr "type" "fp")]) |
4468 | ||
4469 | (define_insn "" | |
4470 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4471 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4472 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4473 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4474 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4475 | [(set_attr "type" "fp")]) |
4476 | ||
4477 | (define_expand "subsf3" | |
4478 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4479 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4480 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4481 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4482 | "") |
4483 | ||
4484 | (define_insn "" | |
4485 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4486 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4487 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4488 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4489 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4490 | [(set_attr "type" "fp")]) |
4491 | ||
ca7f5001 | 4492 | (define_insn "" |
cd2b37d9 RK |
4493 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4494 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4495 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4496 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4497 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4498 | [(set_attr "type" "fp")]) |
4499 | ||
4500 | (define_expand "mulsf3" | |
4501 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4502 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4503 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4504 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4505 | "") |
4506 | ||
4507 | (define_insn "" | |
4508 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4509 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4510 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4511 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4512 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4513 | [(set_attr "type" "fp")]) |
4514 | ||
ca7f5001 | 4515 | (define_insn "" |
cd2b37d9 RK |
4516 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4517 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4518 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4519 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4520 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4521 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4522 | |
ef765ea9 DE |
4523 | (define_insn "fres" |
4524 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4525 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))] | |
4526 | "TARGET_PPC_GFXOPT && flag_finite_math_only" | |
4527 | "fres %0,%1" | |
4528 | [(set_attr "type" "fp")]) | |
4529 | ||
ca7f5001 RK |
4530 | (define_expand "divsf3" |
4531 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4532 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4533 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4534 | "TARGET_HARD_FLOAT" |
ef765ea9 DE |
4535 | { |
4536 | if (swdiv && !optimize_size && TARGET_PPC_GFXOPT | |
4537 | && flag_finite_math_only && !flag_trapping_math) | |
4538 | { | |
4539 | rs6000_emit_swdivsf (operands[0], operands[1], operands[2]); | |
4540 | DONE; | |
4541 | } | |
4542 | }) | |
ca7f5001 RK |
4543 | |
4544 | (define_insn "" | |
cd2b37d9 RK |
4545 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4546 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4547 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4548 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4549 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4550 | [(set_attr "type" "sdiv")]) |
4551 | ||
4552 | (define_insn "" | |
4553 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4554 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4555 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4556 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4557 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4558 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4559 | |
4560 | (define_insn "" | |
cd2b37d9 RK |
4561 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4562 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4563 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4564 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4565 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4566 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4567 | [(set_attr "type" "fp")]) |
4568 | ||
4569 | (define_insn "" | |
4570 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4571 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4572 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4573 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4574 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4575 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4576 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4577 | |
4578 | (define_insn "" | |
cd2b37d9 RK |
4579 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4580 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4581 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4582 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4583 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4584 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4585 | [(set_attr "type" "fp")]) |
4586 | ||
4587 | (define_insn "" | |
4588 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4589 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4590 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4591 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4592 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4593 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4594 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4595 | |
4596 | (define_insn "" | |
cd2b37d9 RK |
4597 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4598 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4599 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4600 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4601 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4602 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4603 | "fnmadds %0,%1,%2,%3" | |
4604 | [(set_attr "type" "fp")]) | |
4605 | ||
4606 | (define_insn "" | |
4607 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4608 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4609 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4610 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4611 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4612 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4613 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4614 | [(set_attr "type" "fp")]) |
4615 | ||
4616 | (define_insn "" | |
4617 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4618 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4619 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4620 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4621 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4622 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4623 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4624 | |
16823694 GK |
4625 | (define_insn "" |
4626 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4627 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4628 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4629 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4630 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4631 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4632 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4633 | [(set_attr "type" "dmul")]) | |
4634 | ||
1fd4e8c1 | 4635 | (define_insn "" |
cd2b37d9 RK |
4636 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4637 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4638 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4639 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4640 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4641 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4642 | "fnmsubs %0,%1,%2,%3" | |
4643 | [(set_attr "type" "fp")]) | |
4644 | ||
4645 | (define_insn "" | |
4646 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4647 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4648 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4649 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4650 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4651 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4652 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4653 | [(set_attr "type" "fp")]) |
4654 | ||
4655 | (define_insn "" | |
4656 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4657 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4658 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4659 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4660 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4661 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 4662 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4663 | |
16823694 GK |
4664 | (define_insn "" |
4665 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4666 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4667 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4668 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4669 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4670 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4671 | "{fnms|fnmsub} %0,%1,%2,%3" | |
4672 | [(set_attr "type" "fp")]) | |
4673 | ||
ca7f5001 RK |
4674 | (define_expand "sqrtsf2" |
4675 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4676 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 4677 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4678 | "") |
4679 | ||
4680 | (define_insn "" | |
4681 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4682 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4683 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4684 | "fsqrts %0,%1" |
4685 | [(set_attr "type" "ssqrt")]) | |
4686 | ||
4687 | (define_insn "" | |
4688 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4689 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4690 | "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4691 | "fsqrt %0,%1" |
4692 | [(set_attr "type" "dsqrt")]) | |
4693 | ||
0530bc70 AP |
4694 | (define_expand "copysignsf3" |
4695 | [(set (match_dup 3) | |
4696 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" ""))) | |
4697 | (set (match_dup 4) | |
4698 | (neg:SF (abs:SF (match_dup 1)))) | |
4699 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
4700 | (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "") | |
4701 | (match_dup 5)) | |
4702 | (match_dup 3) | |
4703 | (match_dup 4)))] | |
4704 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS | |
bb8df8a6 | 4705 | && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)" |
0530bc70 AP |
4706 | { |
4707 | operands[3] = gen_reg_rtx (SFmode); | |
4708 | operands[4] = gen_reg_rtx (SFmode); | |
4709 | operands[5] = CONST0_RTX (SFmode); | |
4710 | }) | |
4711 | ||
4712 | (define_expand "copysigndf3" | |
4713 | [(set (match_dup 3) | |
4714 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" ""))) | |
4715 | (set (match_dup 4) | |
4716 | (neg:DF (abs:DF (match_dup 1)))) | |
4717 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
4718 | (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "") | |
4719 | (match_dup 5)) | |
4720 | (match_dup 3) | |
4721 | (match_dup 4)))] | |
4722 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS | |
4723 | && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)" | |
4724 | { | |
4725 | operands[3] = gen_reg_rtx (DFmode); | |
4726 | operands[4] = gen_reg_rtx (DFmode); | |
4727 | operands[5] = CONST0_RTX (DFmode); | |
4728 | }) | |
4729 | ||
94d7001a RK |
4730 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4731 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4732 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 | 4733 | ;; combine. |
7ae4d8d4 | 4734 | (define_expand "smaxsf3" |
8e871c05 | 4735 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4736 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
4737 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4738 | (match_dup 1) |
4739 | (match_dup 2)))] | |
89e73849 | 4740 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 4741 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
2f607b94 | 4742 | |
7ae4d8d4 | 4743 | (define_expand "sminsf3" |
50a0b056 GK |
4744 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
4745 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
4746 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
4747 | (match_dup 2) | |
4748 | (match_dup 1)))] | |
89e73849 | 4749 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 4750 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 4751 | |
8e871c05 RK |
4752 | (define_split |
4753 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4754 | (match_operator:SF 3 "min_max_operator" |
4755 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
4756 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
89e73849 | 4757 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 GK |
4758 | [(const_int 0)] |
4759 | " | |
6ae08853 | 4760 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
4761 | operands[1], operands[2]); |
4762 | DONE; | |
4763 | }") | |
2f607b94 | 4764 | |
a3170dc6 AH |
4765 | (define_expand "movsicc" |
4766 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4767 | (if_then_else:SI (match_operand 1 "comparison_operator" "") | |
4768 | (match_operand:SI 2 "gpc_reg_operand" "") | |
4769 | (match_operand:SI 3 "gpc_reg_operand" "")))] | |
4770 | "TARGET_ISEL" | |
4771 | " | |
4772 | { | |
4773 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) | |
4774 | DONE; | |
4775 | else | |
4776 | FAIL; | |
4777 | }") | |
4778 | ||
4779 | ;; We use the BASE_REGS for the isel input operands because, if rA is | |
4780 | ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB | |
4781 | ;; because we may switch the operands and rB may end up being rA. | |
4782 | ;; | |
4783 | ;; We need 2 patterns: an unsigned and a signed pattern. We could | |
4784 | ;; leave out the mode in operand 4 and use one pattern, but reload can | |
4785 | ;; change the mode underneath our feet and then gets confused trying | |
4786 | ;; to reload the value. | |
4787 | (define_insn "isel_signed" | |
4788 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4789 | (if_then_else:SI | |
4790 | (match_operator 1 "comparison_operator" | |
4791 | [(match_operand:CC 4 "cc_reg_operand" "y") | |
4792 | (const_int 0)]) | |
4793 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4794 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4795 | "TARGET_ISEL" | |
4796 | "* | |
4797 | { return output_isel (operands); }" | |
4798 | [(set_attr "length" "4")]) | |
4799 | ||
4800 | (define_insn "isel_unsigned" | |
4801 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4802 | (if_then_else:SI | |
4803 | (match_operator 1 "comparison_operator" | |
4804 | [(match_operand:CCUNS 4 "cc_reg_operand" "y") | |
4805 | (const_int 0)]) | |
4806 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4807 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4808 | "TARGET_ISEL" | |
4809 | "* | |
4810 | { return output_isel (operands); }" | |
4811 | [(set_attr "length" "4")]) | |
4812 | ||
94d7001a | 4813 | (define_expand "movsfcc" |
0ad91047 | 4814 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 4815 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4816 | (match_operand:SF 2 "gpc_reg_operand" "") |
4817 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 4818 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4819 | " |
4820 | { | |
50a0b056 GK |
4821 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4822 | DONE; | |
94d7001a | 4823 | else |
50a0b056 | 4824 | FAIL; |
94d7001a | 4825 | }") |
d56d506a | 4826 | |
50a0b056 | 4827 | (define_insn "*fselsfsf4" |
8e871c05 RK |
4828 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4829 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4830 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4831 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4832 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4833 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
4834 | "fsel %0,%1,%2,%3" |
4835 | [(set_attr "type" "fp")]) | |
2f607b94 | 4836 | |
50a0b056 | 4837 | (define_insn "*fseldfsf4" |
94d7001a RK |
4838 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4839 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 4840 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4841 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4842 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4843 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4844 | "fsel %0,%1,%2,%3" |
4845 | [(set_attr "type" "fp")]) | |
d56d506a | 4846 | |
7a2f7870 AH |
4847 | (define_expand "negdf2" |
4848 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4849 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4850 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4851 | "") | |
4852 | ||
99176a91 | 4853 | (define_insn "*negdf2_fpr" |
cd2b37d9 RK |
4854 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4855 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4856 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4857 | "fneg %0,%1" |
4858 | [(set_attr "type" "fp")]) | |
4859 | ||
7a2f7870 AH |
4860 | (define_expand "absdf2" |
4861 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4862 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4863 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4864 | "") | |
4865 | ||
99176a91 | 4866 | (define_insn "*absdf2_fpr" |
cd2b37d9 RK |
4867 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4868 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4869 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4870 | "fabs %0,%1" |
4871 | [(set_attr "type" "fp")]) | |
4872 | ||
99176a91 | 4873 | (define_insn "*nabsdf2_fpr" |
cd2b37d9 RK |
4874 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4875 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4876 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4877 | "fnabs %0,%1" |
4878 | [(set_attr "type" "fp")]) | |
4879 | ||
7a2f7870 AH |
4880 | (define_expand "adddf3" |
4881 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4882 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4883 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4884 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4885 | "") | |
4886 | ||
99176a91 | 4887 | (define_insn "*adddf3_fpr" |
cd2b37d9 RK |
4888 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4889 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4890 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4891 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4892 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
4893 | [(set_attr "type" "fp")]) |
4894 | ||
7a2f7870 AH |
4895 | (define_expand "subdf3" |
4896 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4897 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4898 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4899 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4900 | "") | |
4901 | ||
99176a91 | 4902 | (define_insn "*subdf3_fpr" |
cd2b37d9 RK |
4903 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4904 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4905 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4906 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4907 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
4908 | [(set_attr "type" "fp")]) |
4909 | ||
7a2f7870 AH |
4910 | (define_expand "muldf3" |
4911 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4912 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4913 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4914 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4915 | "") | |
4916 | ||
99176a91 | 4917 | (define_insn "*muldf3_fpr" |
cd2b37d9 RK |
4918 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4919 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4920 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4921 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4922 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 4923 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4924 | |
ef765ea9 DE |
4925 | (define_insn "fred" |
4926 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4927 | (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))] | |
4928 | "TARGET_POPCNTB && flag_finite_math_only" | |
4929 | "fre %0,%1" | |
4930 | [(set_attr "type" "fp")]) | |
4931 | ||
7a2f7870 AH |
4932 | (define_expand "divdf3" |
4933 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4934 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4935 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4936 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
ef765ea9 DE |
4937 | { |
4938 | if (swdiv && !optimize_size && TARGET_POPCNTB | |
4939 | && flag_finite_math_only && !flag_trapping_math) | |
4940 | { | |
4941 | rs6000_emit_swdivdf (operands[0], operands[1], operands[2]); | |
4942 | DONE; | |
4943 | } | |
4944 | }) | |
7a2f7870 | 4945 | |
99176a91 | 4946 | (define_insn "*divdf3_fpr" |
cd2b37d9 RK |
4947 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4948 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4949 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4950 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4951 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 4952 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4953 | |
4954 | (define_insn "" | |
cd2b37d9 RK |
4955 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4956 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4957 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4958 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4959 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4960 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 4961 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4962 | |
4963 | (define_insn "" | |
cd2b37d9 RK |
4964 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4965 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4966 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4967 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4968 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4969 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 4970 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4971 | |
4972 | (define_insn "" | |
cd2b37d9 RK |
4973 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4974 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4975 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4976 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4977 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4978 | && HONOR_SIGNED_ZEROS (DFmode)" | |
4979 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4980 | [(set_attr "type" "dmul")]) | |
4981 | ||
4982 | (define_insn "" | |
4983 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4984 | (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) | |
4985 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4986 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
4987 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4988 | && ! HONOR_SIGNED_ZEROS (DFmode)" | |
ca7f5001 | 4989 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 4990 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4991 | |
4992 | (define_insn "" | |
cd2b37d9 RK |
4993 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4994 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4995 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4996 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4997 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4998 | && HONOR_SIGNED_ZEROS (DFmode)" | |
4999 | "{fnms|fnmsub} %0,%1,%2,%3" | |
5000 | [(set_attr "type" "dmul")]) | |
5001 | ||
5002 | (define_insn "" | |
5003 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5004 | (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") | |
5005 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5006 | (match_operand:DF 2 "gpc_reg_operand" "f"))))] | |
6ae08853 | 5007 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
16823694 | 5008 | && ! HONOR_SIGNED_ZEROS (DFmode)" |
ca7f5001 | 5009 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 5010 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
5011 | |
5012 | (define_insn "sqrtdf2" | |
5013 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5014 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5015 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
5016 | "fsqrt %0,%1" |
5017 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 5018 | |
50a0b056 | 5019 | ;; The conditional move instructions allow us to perform max and min |
6ae08853 | 5020 | ;; operations even when |
b77dfefc | 5021 | |
7ae4d8d4 | 5022 | (define_expand "smaxdf3" |
8e871c05 | 5023 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
5024 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
5025 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
5026 | (match_dup 1) |
5027 | (match_dup 2)))] | |
89e73849 | 5028 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 5029 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
b77dfefc | 5030 | |
7ae4d8d4 | 5031 | (define_expand "smindf3" |
50a0b056 GK |
5032 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5033 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
5034 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
5035 | (match_dup 2) | |
5036 | (match_dup 1)))] | |
89e73849 | 5037 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 5038 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 5039 | |
8e871c05 RK |
5040 | (define_split |
5041 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
5042 | (match_operator:DF 3 "min_max_operator" |
5043 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
5044 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
89e73849 | 5045 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 GK |
5046 | [(const_int 0)] |
5047 | " | |
6ae08853 | 5048 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
5049 | operands[1], operands[2]); |
5050 | DONE; | |
5051 | }") | |
b77dfefc | 5052 | |
94d7001a | 5053 | (define_expand "movdfcc" |
0ad91047 | 5054 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 5055 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5056 | (match_operand:DF 2 "gpc_reg_operand" "") |
5057 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 5058 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
5059 | " |
5060 | { | |
50a0b056 GK |
5061 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5062 | DONE; | |
94d7001a | 5063 | else |
50a0b056 | 5064 | FAIL; |
94d7001a | 5065 | }") |
d56d506a | 5066 | |
50a0b056 | 5067 | (define_insn "*fseldfdf4" |
8e871c05 RK |
5068 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5069 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5070 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5071 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5072 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5073 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
5074 | "fsel %0,%1,%2,%3" |
5075 | [(set_attr "type" "fp")]) | |
d56d506a | 5076 | |
50a0b056 | 5077 | (define_insn "*fselsfdf4" |
94d7001a RK |
5078 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5079 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5080 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5081 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5082 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5083 | "TARGET_PPC_GFXOPT" | |
5084 | "fsel %0,%1,%2,%3" | |
5085 | [(set_attr "type" "fp")]) | |
1fd4e8c1 | 5086 | \f |
d095928f AH |
5087 | ;; Conversions to and from floating-point. |
5088 | ||
5089 | (define_expand "fixuns_truncsfsi2" | |
5090 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5091 | (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5092 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5093 | "") | |
5094 | ||
5095 | (define_expand "fix_truncsfsi2" | |
5096 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5097 | (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5098 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5099 | "") | |
5100 | ||
9ebbca7d GK |
5101 | ; For each of these conversions, there is a define_expand, a define_insn |
5102 | ; with a '#' template, and a define_split (with C code). The idea is | |
5103 | ; to allow constant folding with the template of the define_insn, | |
5104 | ; then to have the insns split later (between sched1 and final). | |
5105 | ||
1fd4e8c1 | 5106 | (define_expand "floatsidf2" |
802a0058 MM |
5107 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5108 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5109 | (use (match_dup 2)) | |
5110 | (use (match_dup 3)) | |
208c89ce | 5111 | (clobber (match_dup 4)) |
a7df97e6 | 5112 | (clobber (match_dup 5)) |
9ebbca7d | 5113 | (clobber (match_dup 6))])] |
a3170dc6 | 5114 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5115 | " |
5116 | { | |
99176a91 AH |
5117 | if (TARGET_E500_DOUBLE) |
5118 | { | |
5119 | emit_insn (gen_spe_floatsidf2 (operands[0], operands[1])); | |
5120 | DONE; | |
5121 | } | |
05d49501 AM |
5122 | if (TARGET_POWERPC64) |
5123 | { | |
5124 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5125 | rtx t1 = gen_reg_rtx (DImode); | |
5126 | rtx t2 = gen_reg_rtx (DImode); | |
5127 | emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); | |
5128 | DONE; | |
5129 | } | |
5130 | ||
802a0058 | 5131 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5132 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); |
9ebbca7d GK |
5133 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5134 | operands[5] = gen_reg_rtx (DFmode); | |
5135 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5136 | }") |
5137 | ||
230215f5 | 5138 | (define_insn_and_split "*floatsidf2_internal" |
802a0058 MM |
5139 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") |
5140 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5141 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5142 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5143 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 DJ |
5144 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) |
5145 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] | |
a3170dc6 | 5146 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5147 | "#" |
230215f5 GK |
5148 | "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))" |
5149 | [(pc)] | |
208c89ce MM |
5150 | " |
5151 | { | |
9ebbca7d | 5152 | rtx lowword, highword; |
230215f5 GK |
5153 | gcc_assert (MEM_P (operands[4])); |
5154 | highword = adjust_address (operands[4], SImode, 0); | |
5155 | lowword = adjust_address (operands[4], SImode, 4); | |
9ebbca7d GK |
5156 | if (! WORDS_BIG_ENDIAN) |
5157 | { | |
5158 | rtx tmp; | |
5159 | tmp = highword; highword = lowword; lowword = tmp; | |
5160 | } | |
5161 | ||
6ae08853 | 5162 | emit_insn (gen_xorsi3 (operands[6], operands[1], |
9ebbca7d | 5163 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); |
230215f5 GK |
5164 | emit_move_insn (lowword, operands[6]); |
5165 | emit_move_insn (highword, operands[2]); | |
9ebbca7d GK |
5166 | emit_move_insn (operands[5], operands[4]); |
5167 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5168 | DONE; | |
230215f5 GK |
5169 | }" |
5170 | [(set_attr "length" "24")]) | |
802a0058 | 5171 | |
a3170dc6 AH |
5172 | (define_expand "floatunssisf2" |
5173 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5174 | (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5175 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5176 | "") | |
5177 | ||
802a0058 MM |
5178 | (define_expand "floatunssidf2" |
5179 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5180 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5181 | (use (match_dup 2)) | |
5182 | (use (match_dup 3)) | |
a7df97e6 | 5183 | (clobber (match_dup 4)) |
9ebbca7d | 5184 | (clobber (match_dup 5))])] |
99176a91 | 5185 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" |
1fd4e8c1 RK |
5186 | " |
5187 | { | |
99176a91 AH |
5188 | if (TARGET_E500_DOUBLE) |
5189 | { | |
5190 | emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1])); | |
5191 | DONE; | |
5192 | } | |
05d49501 AM |
5193 | if (TARGET_POWERPC64) |
5194 | { | |
5195 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5196 | rtx t1 = gen_reg_rtx (DImode); | |
5197 | rtx t2 = gen_reg_rtx (DImode); | |
5198 | emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, | |
5199 | t1, t2)); | |
5200 | DONE; | |
5201 | } | |
5202 | ||
802a0058 | 5203 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5204 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); |
9ebbca7d GK |
5205 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5206 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5207 | }") |
5208 | ||
230215f5 | 5209 | (define_insn_and_split "*floatunssidf2_internal" |
802a0058 MM |
5210 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") |
5211 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5212 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5213 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5214 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 | 5215 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] |
a3170dc6 | 5216 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5217 | "#" |
230215f5 GK |
5218 | "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))" |
5219 | [(pc)] | |
9ebbca7d | 5220 | " |
802a0058 | 5221 | { |
9ebbca7d | 5222 | rtx lowword, highword; |
230215f5 GK |
5223 | gcc_assert (MEM_P (operands[4])); |
5224 | highword = adjust_address (operands[4], SImode, 0); | |
5225 | lowword = adjust_address (operands[4], SImode, 4); | |
9ebbca7d | 5226 | if (! WORDS_BIG_ENDIAN) |
f6968f59 | 5227 | { |
9ebbca7d GK |
5228 | rtx tmp; |
5229 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5230 | } |
802a0058 | 5231 | |
230215f5 GK |
5232 | emit_move_insn (lowword, operands[1]); |
5233 | emit_move_insn (highword, operands[2]); | |
9ebbca7d GK |
5234 | emit_move_insn (operands[5], operands[4]); |
5235 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5236 | DONE; | |
230215f5 GK |
5237 | }" |
5238 | [(set_attr "length" "20")]) | |
1fd4e8c1 | 5239 | |
1fd4e8c1 | 5240 | (define_expand "fix_truncdfsi2" |
045a8eb3 | 5241 | [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "") |
802a0058 MM |
5242 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
5243 | (clobber (match_dup 2)) | |
9ebbca7d | 5244 | (clobber (match_dup 3))])] |
99176a91 AH |
5245 | "(TARGET_POWER2 || TARGET_POWERPC) |
5246 | && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
1fd4e8c1 RK |
5247 | " |
5248 | { | |
99176a91 AH |
5249 | if (TARGET_E500_DOUBLE) |
5250 | { | |
5251 | emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1])); | |
5252 | DONE; | |
5253 | } | |
802a0058 | 5254 | operands[2] = gen_reg_rtx (DImode); |
da4c340c GK |
5255 | if (TARGET_PPC_GFXOPT) |
5256 | { | |
5257 | rtx orig_dest = operands[0]; | |
045a8eb3 | 5258 | if (! memory_operand (orig_dest, GET_MODE (orig_dest))) |
da4c340c GK |
5259 | operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0); |
5260 | emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1], | |
5261 | operands[2])); | |
5262 | if (operands[0] != orig_dest) | |
5263 | emit_move_insn (orig_dest, operands[0]); | |
5264 | DONE; | |
5265 | } | |
9ebbca7d | 5266 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5267 | }") |
5268 | ||
da4c340c | 5269 | (define_insn_and_split "*fix_truncdfsi2_internal" |
802a0058 MM |
5270 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5271 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
e3485bbc | 5272 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) |
9ebbca7d | 5273 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
a3170dc6 | 5274 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5275 | "#" |
230215f5 | 5276 | "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))" |
da4c340c | 5277 | [(pc)] |
9ebbca7d | 5278 | " |
802a0058 | 5279 | { |
9ebbca7d | 5280 | rtx lowword; |
230215f5 GK |
5281 | gcc_assert (MEM_P (operands[3])); |
5282 | lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0); | |
802a0058 | 5283 | |
9ebbca7d GK |
5284 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5285 | emit_move_insn (operands[3], operands[2]); | |
230215f5 | 5286 | emit_move_insn (operands[0], lowword); |
9ebbca7d | 5287 | DONE; |
da4c340c GK |
5288 | }" |
5289 | [(set_attr "length" "16")]) | |
5290 | ||
5291 | (define_insn_and_split "fix_truncdfsi2_internal_gfxopt" | |
5292 | [(set (match_operand:SI 0 "memory_operand" "=Z") | |
5293 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5294 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))] | |
5295 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS | |
5296 | && TARGET_PPC_GFXOPT" | |
5297 | "#" | |
5298 | "&& 1" | |
5299 | [(pc)] | |
5300 | " | |
5301 | { | |
5302 | emit_insn (gen_fctiwz (operands[2], operands[1])); | |
5303 | emit_insn (gen_stfiwx (operands[0], operands[2])); | |
5304 | DONE; | |
5305 | }" | |
5306 | [(set_attr "length" "16")]) | |
802a0058 | 5307 | |
615158e2 | 5308 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) |
9ebbca7d GK |
5309 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) |
5310 | ; because the first makes it clear that operand 0 is not live | |
5311 | ; before the instruction. | |
5312 | (define_insn "fctiwz" | |
da4c340c | 5313 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") |
615158e2 JJ |
5314 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] |
5315 | UNSPEC_FCTIWZ))] | |
a3170dc6 | 5316 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
a260abc9 DE |
5317 | "{fcirz|fctiwz} %0,%1" |
5318 | [(set_attr "type" "fp")]) | |
5319 | ||
da4c340c GK |
5320 | ; An UNSPEC is used so we don't have to support SImode in FP registers. |
5321 | (define_insn "stfiwx" | |
5322 | [(set (match_operand:SI 0 "memory_operand" "=Z") | |
5323 | (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")] | |
5324 | UNSPEC_STFIWX))] | |
5325 | "TARGET_PPC_GFXOPT" | |
5326 | "stfiwx %1,%y0" | |
5327 | [(set_attr "type" "fpstore")]) | |
5328 | ||
a3170dc6 AH |
5329 | (define_expand "floatsisf2" |
5330 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5331 | (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5332 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5333 | "") | |
5334 | ||
a473029f RK |
5335 | (define_insn "floatdidf2" |
5336 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 5337 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] |
a3170dc6 | 5338 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5339 | "fcfid %0,%1" |
5340 | [(set_attr "type" "fp")]) | |
5341 | ||
05d49501 AM |
5342 | (define_insn_and_split "floatsidf_ppc64" |
5343 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5344 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5345 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5346 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5347 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5348 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5349 | "#" |
ecb62ae7 | 5350 | "&& 1" |
05d49501 AM |
5351 | [(set (match_dup 3) (sign_extend:DI (match_dup 1))) |
5352 | (set (match_dup 2) (match_dup 3)) | |
5353 | (set (match_dup 4) (match_dup 2)) | |
5354 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5355 | "") | |
5356 | ||
5357 | (define_insn_and_split "floatunssidf_ppc64" | |
5358 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5359 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5360 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5361 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5362 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5363 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5364 | "#" |
ecb62ae7 | 5365 | "&& 1" |
05d49501 AM |
5366 | [(set (match_dup 3) (zero_extend:DI (match_dup 1))) |
5367 | (set (match_dup 2) (match_dup 3)) | |
5368 | (set (match_dup 4) (match_dup 2)) | |
5369 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5370 | "") | |
5371 | ||
a473029f | 5372 | (define_insn "fix_truncdfdi2" |
61c07d3c | 5373 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
a473029f | 5374 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] |
a3170dc6 | 5375 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5376 | "fctidz %0,%1" |
5377 | [(set_attr "type" "fp")]) | |
ea112fc4 | 5378 | |
678b7733 AM |
5379 | (define_expand "floatdisf2" |
5380 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5381 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] | |
994cf173 | 5382 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
678b7733 AM |
5383 | " |
5384 | { | |
994cf173 | 5385 | rtx val = operands[1]; |
678b7733 AM |
5386 | if (!flag_unsafe_math_optimizations) |
5387 | { | |
5388 | rtx label = gen_label_rtx (); | |
994cf173 AM |
5389 | val = gen_reg_rtx (DImode); |
5390 | emit_insn (gen_floatdisf2_internal2 (val, operands[1], label)); | |
678b7733 AM |
5391 | emit_label (label); |
5392 | } | |
994cf173 | 5393 | emit_insn (gen_floatdisf2_internal1 (operands[0], val)); |
678b7733 AM |
5394 | DONE; |
5395 | }") | |
5396 | ||
5397 | ;; This is not IEEE compliant if rounding mode is "round to nearest". | |
5398 | ;; If the DI->DF conversion is inexact, then it's possible to suffer | |
5399 | ;; from double rounding. | |
5400 | (define_insn_and_split "floatdisf2_internal1" | |
ea112fc4 | 5401 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
61c07d3c | 5402 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 | 5403 | (clobber (match_scratch:DF 2 "=f"))] |
678b7733 | 5404 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ea112fc4 DE |
5405 | "#" |
5406 | "&& reload_completed" | |
5407 | [(set (match_dup 2) | |
5408 | (float:DF (match_dup 1))) | |
5409 | (set (match_dup 0) | |
5410 | (float_truncate:SF (match_dup 2)))] | |
5411 | "") | |
678b7733 AM |
5412 | |
5413 | ;; Twiddles bits to avoid double rounding. | |
b6d08ca1 | 5414 | ;; Bits that might be truncated when converting to DFmode are replaced |
678b7733 AM |
5415 | ;; by a bit that won't be lost at that stage, but is below the SFmode |
5416 | ;; rounding position. | |
5417 | (define_expand "floatdisf2_internal2" | |
994cf173 AM |
5418 | [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "") |
5419 | (const_int 53))) | |
5420 | (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1) | |
5421 | (const_int 2047))) | |
5422 | (clobber (scratch:CC))]) | |
5423 | (set (match_dup 3) (plus:DI (match_dup 3) | |
5424 | (const_int 1))) | |
5425 | (set (match_dup 0) (plus:DI (match_dup 0) | |
5426 | (const_int 2047))) | |
5427 | (set (match_dup 4) (compare:CCUNS (match_dup 3) | |
5428 | (const_int 3))) | |
5429 | (set (match_dup 0) (ior:DI (match_dup 0) | |
5430 | (match_dup 1))) | |
5431 | (parallel [(set (match_dup 0) (and:DI (match_dup 0) | |
5432 | (const_int -2048))) | |
5433 | (clobber (scratch:CC))]) | |
5434 | (set (pc) (if_then_else (geu (match_dup 4) (const_int 0)) | |
5435 | (label_ref (match_operand:DI 2 "" "")) | |
678b7733 | 5436 | (pc))) |
994cf173 AM |
5437 | (set (match_dup 0) (match_dup 1))] |
5438 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" | |
678b7733 AM |
5439 | " |
5440 | { | |
678b7733 | 5441 | operands[3] = gen_reg_rtx (DImode); |
994cf173 | 5442 | operands[4] = gen_reg_rtx (CCUNSmode); |
678b7733 | 5443 | }") |
1fd4e8c1 RK |
5444 | \f |
5445 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5446 | ;; of instructions. The & constraints are to prevent the register |
5447 | ;; allocator from allocating registers that overlap with the inputs | |
5448 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5449 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5450 | |
266eb58a | 5451 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5452 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5453 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5454 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5455 | "! TARGET_POWERPC64" |
0f645302 MM |
5456 | "* |
5457 | { | |
5458 | if (WORDS_BIG_ENDIAN) | |
5459 | return (GET_CODE (operands[2])) != CONST_INT | |
5460 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5461 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5462 | else | |
5463 | return (GET_CODE (operands[2])) != CONST_INT | |
5464 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5465 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5466 | }" | |
943c15ed DE |
5467 | [(set_attr "type" "two") |
5468 | (set_attr "length" "8")]) | |
1fd4e8c1 | 5469 | |
266eb58a | 5470 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5471 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5472 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5473 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5474 | "! TARGET_POWERPC64" |
5502823b RK |
5475 | "* |
5476 | { | |
0f645302 MM |
5477 | if (WORDS_BIG_ENDIAN) |
5478 | return (GET_CODE (operands[1]) != CONST_INT) | |
5479 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5480 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5481 | else | |
5482 | return (GET_CODE (operands[1]) != CONST_INT) | |
5483 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5484 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5485 | }" |
943c15ed DE |
5486 | [(set_attr "type" "two") |
5487 | (set_attr "length" "8")]) | |
ca7f5001 | 5488 | |
266eb58a | 5489 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5490 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5491 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5492 | "! TARGET_POWERPC64" |
5502823b RK |
5493 | "* |
5494 | { | |
5495 | return (WORDS_BIG_ENDIAN) | |
5496 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5497 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5498 | }" | |
943c15ed DE |
5499 | [(set_attr "type" "two") |
5500 | (set_attr "length" "8")]) | |
ca7f5001 | 5501 | |
8ffd9c51 RK |
5502 | (define_expand "mulsidi3" |
5503 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5504 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5505 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5506 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5507 | " |
5508 | { | |
5509 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5510 | { | |
39403d82 DE |
5511 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5512 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5513 | emit_insn (gen_mull_call ()); |
cf27b467 | 5514 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5515 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5516 | else |
5517 | { | |
5518 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5519 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5520 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5521 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5522 | } |
8ffd9c51 RK |
5523 | DONE; |
5524 | } | |
5525 | else if (TARGET_POWER) | |
5526 | { | |
5527 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5528 | DONE; | |
5529 | } | |
5530 | }") | |
deb9225a | 5531 | |
8ffd9c51 | 5532 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5533 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5534 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5535 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5536 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5537 | "TARGET_POWER" |
b19003d8 | 5538 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5539 | [(set_attr "type" "imul") |
5540 | (set_attr "length" "8")]) | |
deb9225a | 5541 | |
f192bf8b | 5542 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5543 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5544 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5545 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5546 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5547 | "* |
5548 | { | |
5549 | return (WORDS_BIG_ENDIAN) | |
5550 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5551 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5552 | }" | |
8ffd9c51 RK |
5553 | [(set_attr "type" "imul") |
5554 | (set_attr "length" "8")]) | |
deb9225a | 5555 | |
ebedb4dd MM |
5556 | (define_split |
5557 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5558 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5559 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5560 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5561 | [(set (match_dup 3) |
5562 | (truncate:SI | |
5563 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5564 | (sign_extend:DI (match_dup 2))) | |
5565 | (const_int 32)))) | |
5566 | (set (match_dup 4) | |
5567 | (mult:SI (match_dup 1) | |
5568 | (match_dup 2)))] | |
5569 | " | |
5570 | { | |
5571 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5572 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5573 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5574 | }") | |
5575 | ||
f192bf8b DE |
5576 | (define_expand "umulsidi3" |
5577 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5578 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5579 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5580 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5581 | " | |
5582 | { | |
5583 | if (TARGET_POWER) | |
5584 | { | |
5585 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5586 | DONE; | |
5587 | } | |
5588 | }") | |
5589 | ||
5590 | (define_insn "umulsidi3_mq" | |
5591 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5592 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5593 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5594 | (clobber (match_scratch:SI 3 "=q"))] | |
5595 | "TARGET_POWERPC && TARGET_POWER" | |
5596 | "* | |
5597 | { | |
5598 | return (WORDS_BIG_ENDIAN) | |
5599 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5600 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5601 | }" | |
5602 | [(set_attr "type" "imul") | |
5603 | (set_attr "length" "8")]) | |
5604 | ||
5605 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5606 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5607 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5608 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5609 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5610 | "* |
5611 | { | |
5612 | return (WORDS_BIG_ENDIAN) | |
5613 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5614 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5615 | }" | |
5616 | [(set_attr "type" "imul") | |
5617 | (set_attr "length" "8")]) | |
5618 | ||
ebedb4dd MM |
5619 | (define_split |
5620 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5621 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5622 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5623 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5624 | [(set (match_dup 3) |
5625 | (truncate:SI | |
5626 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5627 | (zero_extend:DI (match_dup 2))) | |
5628 | (const_int 32)))) | |
5629 | (set (match_dup 4) | |
5630 | (mult:SI (match_dup 1) | |
5631 | (match_dup 2)))] | |
5632 | " | |
5633 | { | |
5634 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5635 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5636 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5637 | }") | |
5638 | ||
8ffd9c51 RK |
5639 | (define_expand "smulsi3_highpart" |
5640 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5641 | (truncate:SI | |
5642 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5643 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5644 | (sign_extend:DI | |
5645 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5646 | (const_int 32))))] | |
5647 | "" | |
5648 | " | |
5649 | { | |
5650 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5651 | { | |
39403d82 DE |
5652 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5653 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5654 | emit_insn (gen_mulh_call ()); |
39403d82 | 5655 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5656 | DONE; |
5657 | } | |
5658 | else if (TARGET_POWER) | |
5659 | { | |
5660 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5661 | DONE; | |
5662 | } | |
5663 | }") | |
deb9225a | 5664 | |
8ffd9c51 RK |
5665 | (define_insn "smulsi3_highpart_mq" |
5666 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5667 | (truncate:SI | |
fada905b MM |
5668 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5669 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5670 | (sign_extend:DI | |
5671 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5672 | (const_int 32)))) |
5673 | (clobber (match_scratch:SI 3 "=q"))] | |
5674 | "TARGET_POWER" | |
5675 | "mul %0,%1,%2" | |
5676 | [(set_attr "type" "imul")]) | |
deb9225a | 5677 | |
f192bf8b | 5678 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5679 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5680 | (truncate:SI | |
fada905b MM |
5681 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5682 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5683 | (sign_extend:DI | |
5684 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5685 | (const_int 32))))] |
f192bf8b | 5686 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5687 | "mulhw %0,%1,%2" |
5688 | [(set_attr "type" "imul")]) | |
deb9225a | 5689 | |
f192bf8b DE |
5690 | (define_expand "umulsi3_highpart" |
5691 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5692 | (truncate:SI | |
5693 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5694 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5695 | (zero_extend:DI | |
5696 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5697 | (const_int 32))))] | |
5698 | "TARGET_POWERPC" | |
5699 | " | |
5700 | { | |
5701 | if (TARGET_POWER) | |
5702 | { | |
5703 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5704 | DONE; | |
5705 | } | |
5706 | }") | |
5707 | ||
5708 | (define_insn "umulsi3_highpart_mq" | |
5709 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5710 | (truncate:SI | |
5711 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5712 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5713 | (zero_extend:DI | |
5714 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5715 | (const_int 32)))) | |
5716 | (clobber (match_scratch:SI 3 "=q"))] | |
5717 | "TARGET_POWERPC && TARGET_POWER" | |
5718 | "mulhwu %0,%1,%2" | |
5719 | [(set_attr "type" "imul")]) | |
5720 | ||
5721 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5722 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5723 | (truncate:SI | |
5724 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5725 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5726 | (zero_extend:DI | |
5727 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5728 | (const_int 32))))] | |
f192bf8b | 5729 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5730 | "mulhwu %0,%1,%2" |
5731 | [(set_attr "type" "imul")]) | |
5732 | ||
5733 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5734 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5735 | ;; why we have the strange constraints below. | |
5736 | (define_insn "ashldi3_power" | |
5737 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5738 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5739 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5740 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5741 | "TARGET_POWER" | |
5742 | "@ | |
5743 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5744 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5745 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5746 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5747 | [(set_attr "length" "8")]) | |
5748 | ||
5749 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5750 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5751 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5752 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5753 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5754 | "TARGET_POWER" | |
5755 | "@ | |
47ad8c61 | 5756 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5757 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5758 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5759 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5760 | [(set_attr "length" "8")]) | |
5761 | ||
5762 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5763 | ;; just handle shifts by constants. | |
5764 | (define_insn "ashrdi3_power" | |
7093ddee | 5765 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5766 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5767 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5768 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5769 | "TARGET_POWER" | |
5770 | "@ | |
5771 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5772 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5773 | [(set_attr "length" "8")]) | |
4aa74a4f FS |
5774 | |
5775 | (define_insn "ashrdi3_no_power" | |
5776 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") | |
5777 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5778 | (match_operand:SI 2 "const_int_operand" "M,i")))] | |
97727e85 | 5779 | "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN" |
4aa74a4f FS |
5780 | "@ |
5781 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5782 | {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" | |
943c15ed DE |
5783 | [(set_attr "type" "two,three") |
5784 | (set_attr "length" "8,12")]) | |
683bdff7 FJ |
5785 | |
5786 | (define_insn "*ashrdisi3_noppc64" | |
5787 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 5788 | (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
683bdff7 FJ |
5789 | (const_int 32)) 4))] |
5790 | "TARGET_32BIT && !TARGET_POWERPC64" | |
5791 | "* | |
5792 | { | |
5793 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
5794 | return \"\"; | |
5795 | else | |
5796 | return \"mr %0,%1\"; | |
5797 | }" | |
6ae08853 | 5798 | [(set_attr "length" "4")]) |
683bdff7 | 5799 | |
266eb58a DE |
5800 | \f |
5801 | ;; PowerPC64 DImode operations. | |
5802 | ||
ea112fc4 | 5803 | (define_insn_and_split "absdi2" |
266eb58a | 5804 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 5805 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) |
266eb58a DE |
5806 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
5807 | "TARGET_POWERPC64" | |
ea112fc4 DE |
5808 | "#" |
5809 | "&& reload_completed" | |
a260abc9 | 5810 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5811 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 5812 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
5813 | "") |
5814 | ||
ea112fc4 | 5815 | (define_insn_and_split "*nabsdi2" |
266eb58a | 5816 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 5817 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) |
266eb58a DE |
5818 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
5819 | "TARGET_POWERPC64" | |
ea112fc4 DE |
5820 | "#" |
5821 | "&& reload_completed" | |
a260abc9 | 5822 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5823 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 5824 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
5825 | "") |
5826 | ||
266eb58a | 5827 | (define_insn "muldi3" |
c9692532 DE |
5828 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
5829 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
5830 | (match_operand:DI 2 "reg_or_short_operand" "r,I")))] | |
266eb58a | 5831 | "TARGET_POWERPC64" |
c9692532 DE |
5832 | "@ |
5833 | mulld %0,%1,%2 | |
5834 | mulli %0,%1,%2" | |
5835 | [(set (attr "type") | |
5836 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") | |
5837 | (const_string "imul3") | |
5838 | (match_operand:SI 2 "short_cint_operand" "") | |
5839 | (const_string "imul2")] | |
5840 | (const_string "lmul")))]) | |
266eb58a | 5841 | |
9259f3b0 DE |
5842 | (define_insn "*muldi3_internal1" |
5843 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
5844 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
5845 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
5846 | (const_int 0))) | |
5847 | (clobber (match_scratch:DI 3 "=r,r"))] | |
5848 | "TARGET_POWERPC64" | |
5849 | "@ | |
5850 | mulld. %3,%1,%2 | |
5851 | #" | |
5852 | [(set_attr "type" "lmul_compare") | |
5853 | (set_attr "length" "4,8")]) | |
5854 | ||
5855 | (define_split | |
5856 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5857 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5858 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5859 | (const_int 0))) | |
5860 | (clobber (match_scratch:DI 3 ""))] | |
5861 | "TARGET_POWERPC64 && reload_completed" | |
5862 | [(set (match_dup 3) | |
5863 | (mult:DI (match_dup 1) (match_dup 2))) | |
5864 | (set (match_dup 0) | |
5865 | (compare:CC (match_dup 3) | |
5866 | (const_int 0)))] | |
5867 | "") | |
5868 | ||
5869 | (define_insn "*muldi3_internal2" | |
5870 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") | |
5871 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
5872 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
5873 | (const_int 0))) | |
5874 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5875 | (mult:DI (match_dup 1) (match_dup 2)))] | |
5876 | "TARGET_POWERPC64" | |
5877 | "@ | |
5878 | mulld. %0,%1,%2 | |
5879 | #" | |
5880 | [(set_attr "type" "lmul_compare") | |
5881 | (set_attr "length" "4,8")]) | |
5882 | ||
5883 | (define_split | |
5884 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5885 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5886 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5887 | (const_int 0))) | |
5888 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5889 | (mult:DI (match_dup 1) (match_dup 2)))] | |
5890 | "TARGET_POWERPC64 && reload_completed" | |
5891 | [(set (match_dup 0) | |
5892 | (mult:DI (match_dup 1) (match_dup 2))) | |
5893 | (set (match_dup 3) | |
5894 | (compare:CC (match_dup 0) | |
5895 | (const_int 0)))] | |
5896 | "") | |
5897 | ||
266eb58a DE |
5898 | (define_insn "smuldi3_highpart" |
5899 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5900 | (truncate:DI | |
5901 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
5902 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5903 | (sign_extend:TI | |
5904 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
5905 | (const_int 64))))] | |
5906 | "TARGET_POWERPC64" | |
5907 | "mulhd %0,%1,%2" | |
3cb999d8 | 5908 | [(set_attr "type" "lmul")]) |
266eb58a DE |
5909 | |
5910 | (define_insn "umuldi3_highpart" | |
5911 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5912 | (truncate:DI | |
5913 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
5914 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5915 | (zero_extend:TI | |
5916 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
5917 | (const_int 64))))] | |
5918 | "TARGET_POWERPC64" | |
5919 | "mulhdu %0,%1,%2" | |
3cb999d8 | 5920 | [(set_attr "type" "lmul")]) |
266eb58a | 5921 | |
266eb58a DE |
5922 | (define_insn "rotldi3" |
5923 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5924 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5925 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
5926 | "TARGET_POWERPC64" | |
a66078ee | 5927 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 5928 | |
a260abc9 | 5929 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
5930 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5931 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5932 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 5933 | (const_int 0))) |
9ebbca7d | 5934 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 5935 | "TARGET_64BIT" |
9ebbca7d GK |
5936 | "@ |
5937 | rld%I2cl. %3,%1,%H2,0 | |
5938 | #" | |
5939 | [(set_attr "type" "delayed_compare") | |
5940 | (set_attr "length" "4,8")]) | |
5941 | ||
5942 | (define_split | |
5943 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5944 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5945 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
5946 | (const_int 0))) | |
5947 | (clobber (match_scratch:DI 3 ""))] | |
5948 | "TARGET_POWERPC64 && reload_completed" | |
5949 | [(set (match_dup 3) | |
5950 | (rotate:DI (match_dup 1) (match_dup 2))) | |
5951 | (set (match_dup 0) | |
5952 | (compare:CC (match_dup 3) | |
5953 | (const_int 0)))] | |
5954 | "") | |
266eb58a | 5955 | |
a260abc9 | 5956 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
5957 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
5958 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5959 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 5960 | (const_int 0))) |
9ebbca7d | 5961 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 5962 | (rotate:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 5963 | "TARGET_64BIT" |
9ebbca7d GK |
5964 | "@ |
5965 | rld%I2cl. %0,%1,%H2,0 | |
5966 | #" | |
5967 | [(set_attr "type" "delayed_compare") | |
5968 | (set_attr "length" "4,8")]) | |
5969 | ||
5970 | (define_split | |
5971 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5972 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5973 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
5974 | (const_int 0))) | |
5975 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5976 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
5977 | "TARGET_POWERPC64 && reload_completed" | |
5978 | [(set (match_dup 0) | |
5979 | (rotate:DI (match_dup 1) (match_dup 2))) | |
5980 | (set (match_dup 3) | |
5981 | (compare:CC (match_dup 0) | |
5982 | (const_int 0)))] | |
5983 | "") | |
266eb58a | 5984 | |
a260abc9 DE |
5985 | (define_insn "*rotldi3_internal4" |
5986 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5987 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5988 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
1990cd79 | 5989 | (match_operand:DI 3 "mask64_operand" "n")))] |
a260abc9 DE |
5990 | "TARGET_POWERPC64" |
5991 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
5992 | ||
5993 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 5994 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 5995 | (compare:CC (and:DI |
9ebbca7d GK |
5996 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5997 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
1990cd79 | 5998 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 5999 | (const_int 0))) |
9ebbca7d | 6000 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6001 | "TARGET_64BIT" |
9ebbca7d GK |
6002 | "@ |
6003 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6004 | #" | |
6005 | [(set_attr "type" "delayed_compare") | |
6006 | (set_attr "length" "4,8")]) | |
6007 | ||
6008 | (define_split | |
6009 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6010 | (compare:CC (and:DI | |
6011 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6012 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
1990cd79 | 6013 | (match_operand:DI 3 "mask64_operand" "")) |
9ebbca7d GK |
6014 | (const_int 0))) |
6015 | (clobber (match_scratch:DI 4 ""))] | |
6016 | "TARGET_POWERPC64 && reload_completed" | |
6017 | [(set (match_dup 4) | |
6018 | (and:DI (rotate:DI (match_dup 1) | |
6019 | (match_dup 2)) | |
6020 | (match_dup 3))) | |
6021 | (set (match_dup 0) | |
6022 | (compare:CC (match_dup 4) | |
6023 | (const_int 0)))] | |
6024 | "") | |
a260abc9 DE |
6025 | |
6026 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6027 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6028 | (compare:CC (and:DI |
9ebbca7d GK |
6029 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6030 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
1990cd79 | 6031 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6032 | (const_int 0))) |
9ebbca7d | 6033 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6034 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6035 | "TARGET_64BIT" |
9ebbca7d GK |
6036 | "@ |
6037 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6038 | #" | |
6039 | [(set_attr "type" "delayed_compare") | |
6040 | (set_attr "length" "4,8")]) | |
6041 | ||
6042 | (define_split | |
6043 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6044 | (compare:CC (and:DI | |
6045 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6046 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
1990cd79 | 6047 | (match_operand:DI 3 "mask64_operand" "")) |
9ebbca7d GK |
6048 | (const_int 0))) |
6049 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6050 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6051 | "TARGET_POWERPC64 && reload_completed" | |
6052 | [(set (match_dup 0) | |
6053 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6054 | (set (match_dup 4) | |
6055 | (compare:CC (match_dup 0) | |
6056 | (const_int 0)))] | |
6057 | "") | |
a260abc9 DE |
6058 | |
6059 | (define_insn "*rotldi3_internal7" | |
6060 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6061 | (zero_extend:DI | |
6062 | (subreg:QI | |
6063 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6064 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6065 | "TARGET_POWERPC64" | |
6066 | "rld%I2cl %0,%1,%H2,56") | |
6067 | ||
6068 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6069 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6070 | (compare:CC (zero_extend:DI |
6071 | (subreg:QI | |
9ebbca7d GK |
6072 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6073 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6074 | (const_int 0))) |
9ebbca7d | 6075 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6076 | "TARGET_64BIT" |
9ebbca7d GK |
6077 | "@ |
6078 | rld%I2cl. %3,%1,%H2,56 | |
6079 | #" | |
6080 | [(set_attr "type" "delayed_compare") | |
6081 | (set_attr "length" "4,8")]) | |
6082 | ||
6083 | (define_split | |
6084 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6085 | (compare:CC (zero_extend:DI | |
6086 | (subreg:QI | |
6087 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6088 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6089 | (const_int 0))) | |
6090 | (clobber (match_scratch:DI 3 ""))] | |
6091 | "TARGET_POWERPC64 && reload_completed" | |
6092 | [(set (match_dup 3) | |
6093 | (zero_extend:DI (subreg:QI | |
6094 | (rotate:DI (match_dup 1) | |
6095 | (match_dup 2)) 0))) | |
6096 | (set (match_dup 0) | |
6097 | (compare:CC (match_dup 3) | |
6098 | (const_int 0)))] | |
6099 | "") | |
a260abc9 DE |
6100 | |
6101 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6102 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6103 | (compare:CC (zero_extend:DI |
6104 | (subreg:QI | |
9ebbca7d GK |
6105 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6106 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6107 | (const_int 0))) |
9ebbca7d | 6108 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6109 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6110 | "TARGET_64BIT" |
9ebbca7d GK |
6111 | "@ |
6112 | rld%I2cl. %0,%1,%H2,56 | |
6113 | #" | |
6114 | [(set_attr "type" "delayed_compare") | |
6115 | (set_attr "length" "4,8")]) | |
6116 | ||
6117 | (define_split | |
6118 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6119 | (compare:CC (zero_extend:DI | |
6120 | (subreg:QI | |
6121 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6122 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6123 | (const_int 0))) | |
6124 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6125 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6126 | "TARGET_POWERPC64 && reload_completed" | |
6127 | [(set (match_dup 0) | |
6128 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6129 | (set (match_dup 3) | |
6130 | (compare:CC (match_dup 0) | |
6131 | (const_int 0)))] | |
6132 | "") | |
a260abc9 DE |
6133 | |
6134 | (define_insn "*rotldi3_internal10" | |
6135 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6136 | (zero_extend:DI | |
6137 | (subreg:HI | |
6138 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6139 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6140 | "TARGET_POWERPC64" | |
6141 | "rld%I2cl %0,%1,%H2,48") | |
6142 | ||
6143 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6144 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6145 | (compare:CC (zero_extend:DI |
6146 | (subreg:HI | |
9ebbca7d GK |
6147 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6148 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6149 | (const_int 0))) |
9ebbca7d | 6150 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6151 | "TARGET_64BIT" |
9ebbca7d GK |
6152 | "@ |
6153 | rld%I2cl. %3,%1,%H2,48 | |
6154 | #" | |
6155 | [(set_attr "type" "delayed_compare") | |
6156 | (set_attr "length" "4,8")]) | |
6157 | ||
6158 | (define_split | |
6159 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6160 | (compare:CC (zero_extend:DI | |
6161 | (subreg:HI | |
6162 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6163 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6164 | (const_int 0))) | |
6165 | (clobber (match_scratch:DI 3 ""))] | |
6166 | "TARGET_POWERPC64 && reload_completed" | |
6167 | [(set (match_dup 3) | |
6168 | (zero_extend:DI (subreg:HI | |
6169 | (rotate:DI (match_dup 1) | |
6170 | (match_dup 2)) 0))) | |
6171 | (set (match_dup 0) | |
6172 | (compare:CC (match_dup 3) | |
6173 | (const_int 0)))] | |
6174 | "") | |
a260abc9 DE |
6175 | |
6176 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6177 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6178 | (compare:CC (zero_extend:DI |
6179 | (subreg:HI | |
9ebbca7d GK |
6180 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6181 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6182 | (const_int 0))) |
9ebbca7d | 6183 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6184 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6185 | "TARGET_64BIT" |
9ebbca7d GK |
6186 | "@ |
6187 | rld%I2cl. %0,%1,%H2,48 | |
6188 | #" | |
6189 | [(set_attr "type" "delayed_compare") | |
6190 | (set_attr "length" "4,8")]) | |
6191 | ||
6192 | (define_split | |
6193 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6194 | (compare:CC (zero_extend:DI | |
6195 | (subreg:HI | |
6196 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6197 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6198 | (const_int 0))) | |
6199 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6200 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6201 | "TARGET_POWERPC64 && reload_completed" | |
6202 | [(set (match_dup 0) | |
6203 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6204 | (set (match_dup 3) | |
6205 | (compare:CC (match_dup 0) | |
6206 | (const_int 0)))] | |
6207 | "") | |
a260abc9 DE |
6208 | |
6209 | (define_insn "*rotldi3_internal13" | |
6210 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6211 | (zero_extend:DI | |
6212 | (subreg:SI | |
6213 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6214 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6215 | "TARGET_POWERPC64" | |
6216 | "rld%I2cl %0,%1,%H2,32") | |
6217 | ||
6218 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6219 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6220 | (compare:CC (zero_extend:DI |
6221 | (subreg:SI | |
9ebbca7d GK |
6222 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6223 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6224 | (const_int 0))) |
9ebbca7d | 6225 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6226 | "TARGET_64BIT" |
9ebbca7d GK |
6227 | "@ |
6228 | rld%I2cl. %3,%1,%H2,32 | |
6229 | #" | |
6230 | [(set_attr "type" "delayed_compare") | |
6231 | (set_attr "length" "4,8")]) | |
6232 | ||
6233 | (define_split | |
6234 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6235 | (compare:CC (zero_extend:DI | |
6236 | (subreg:SI | |
6237 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6238 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6239 | (const_int 0))) | |
6240 | (clobber (match_scratch:DI 3 ""))] | |
6241 | "TARGET_POWERPC64 && reload_completed" | |
6242 | [(set (match_dup 3) | |
6243 | (zero_extend:DI (subreg:SI | |
6244 | (rotate:DI (match_dup 1) | |
6245 | (match_dup 2)) 0))) | |
6246 | (set (match_dup 0) | |
6247 | (compare:CC (match_dup 3) | |
6248 | (const_int 0)))] | |
6249 | "") | |
a260abc9 DE |
6250 | |
6251 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6252 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6253 | (compare:CC (zero_extend:DI |
6254 | (subreg:SI | |
9ebbca7d GK |
6255 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6256 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6257 | (const_int 0))) |
9ebbca7d | 6258 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6259 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6260 | "TARGET_64BIT" |
9ebbca7d GK |
6261 | "@ |
6262 | rld%I2cl. %0,%1,%H2,32 | |
6263 | #" | |
6264 | [(set_attr "type" "delayed_compare") | |
6265 | (set_attr "length" "4,8")]) | |
6266 | ||
6267 | (define_split | |
6268 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6269 | (compare:CC (zero_extend:DI | |
6270 | (subreg:SI | |
6271 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6272 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6273 | (const_int 0))) | |
6274 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6275 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6276 | "TARGET_POWERPC64 && reload_completed" | |
6277 | [(set (match_dup 0) | |
6278 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6279 | (set (match_dup 3) | |
6280 | (compare:CC (match_dup 0) | |
6281 | (const_int 0)))] | |
6282 | "") | |
a260abc9 | 6283 | |
266eb58a DE |
6284 | (define_expand "ashldi3" |
6285 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6286 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6287 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6288 | "TARGET_POWERPC64 || TARGET_POWER" | |
6289 | " | |
6290 | { | |
6291 | if (TARGET_POWERPC64) | |
6292 | ; | |
6293 | else if (TARGET_POWER) | |
6294 | { | |
6295 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6296 | DONE; | |
6297 | } | |
6298 | else | |
6299 | FAIL; | |
6300 | }") | |
6301 | ||
e2c953b6 | 6302 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
6303 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6304 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6305 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6306 | "TARGET_POWERPC64" | |
943c15ed | 6307 | "sld%I2 %0,%1,%H2") |
6ae08853 | 6308 | |
e2c953b6 | 6309 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
6310 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6311 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6312 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6313 | (const_int 0))) |
9ebbca7d | 6314 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6315 | "TARGET_64BIT" |
9ebbca7d GK |
6316 | "@ |
6317 | sld%I2. %3,%1,%H2 | |
6318 | #" | |
6319 | [(set_attr "type" "delayed_compare") | |
6320 | (set_attr "length" "4,8")]) | |
6ae08853 | 6321 | |
9ebbca7d GK |
6322 | (define_split |
6323 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6324 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6325 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6326 | (const_int 0))) | |
6327 | (clobber (match_scratch:DI 3 ""))] | |
6328 | "TARGET_POWERPC64 && reload_completed" | |
6329 | [(set (match_dup 3) | |
6330 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6331 | (set (match_dup 0) | |
6332 | (compare:CC (match_dup 3) | |
6333 | (const_int 0)))] | |
6334 | "") | |
6335 | ||
e2c953b6 | 6336 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
6337 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6338 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6339 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6340 | (const_int 0))) |
9ebbca7d | 6341 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6342 | (ashift:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6343 | "TARGET_64BIT" |
9ebbca7d GK |
6344 | "@ |
6345 | sld%I2. %0,%1,%H2 | |
6346 | #" | |
6347 | [(set_attr "type" "delayed_compare") | |
6348 | (set_attr "length" "4,8")]) | |
6349 | ||
6350 | (define_split | |
6351 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6352 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6353 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6354 | (const_int 0))) | |
6355 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6356 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6357 | "TARGET_POWERPC64 && reload_completed" | |
6358 | [(set (match_dup 0) | |
6359 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6360 | (set (match_dup 3) | |
6361 | (compare:CC (match_dup 0) | |
6362 | (const_int 0)))] | |
6363 | "") | |
266eb58a | 6364 | |
e2c953b6 | 6365 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
6366 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6367 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6368 | (match_operand:SI 2 "const_int_operand" "i")) | |
c5059423 AM |
6369 | (match_operand:DI 3 "const_int_operand" "n")))] |
6370 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" | |
e2c953b6 | 6371 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 6372 | |
e2c953b6 | 6373 | (define_insn "ashldi3_internal5" |
9ebbca7d | 6374 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6375 | (compare:CC |
9ebbca7d GK |
6376 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6377 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6378 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6379 | (const_int 0))) |
9ebbca7d | 6380 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6381 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6382 | "@ |
e2c953b6 | 6383 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
6384 | #" |
6385 | [(set_attr "type" "delayed_compare") | |
6386 | (set_attr "length" "4,8")]) | |
6387 | ||
6388 | (define_split | |
6389 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6390 | (compare:CC | |
6391 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6392 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6393 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6394 | (const_int 0))) |
6395 | (clobber (match_scratch:DI 4 ""))] | |
c5059423 AM |
6396 | "TARGET_POWERPC64 && reload_completed |
6397 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
9ebbca7d GK |
6398 | [(set (match_dup 4) |
6399 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 6400 | (match_dup 3))) |
9ebbca7d GK |
6401 | (set (match_dup 0) |
6402 | (compare:CC (match_dup 4) | |
6403 | (const_int 0)))] | |
6404 | "") | |
3cb999d8 | 6405 | |
e2c953b6 | 6406 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 6407 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6408 | (compare:CC |
9ebbca7d GK |
6409 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6410 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6411 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6412 | (const_int 0))) |
9ebbca7d | 6413 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 6414 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6415 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6416 | "@ |
e2c953b6 | 6417 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
6418 | #" |
6419 | [(set_attr "type" "delayed_compare") | |
6420 | (set_attr "length" "4,8")]) | |
6421 | ||
6422 | (define_split | |
6423 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6424 | (compare:CC | |
6425 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6426 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6427 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6428 | (const_int 0))) |
6429 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6430 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
c5059423 AM |
6431 | "TARGET_POWERPC64 && reload_completed |
6432 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
6433 | [(set (match_dup 0) | |
6434 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6435 | (match_dup 3))) | |
6436 | (set (match_dup 4) | |
6437 | (compare:CC (match_dup 0) | |
6438 | (const_int 0)))] | |
6439 | "") | |
6440 | ||
6441 | (define_insn "*ashldi3_internal7" | |
6442 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6443 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6444 | (match_operand:SI 2 "const_int_operand" "i")) | |
1990cd79 | 6445 | (match_operand:DI 3 "mask64_operand" "n")))] |
c5059423 AM |
6446 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" |
6447 | "rldicr %0,%1,%H2,%S3") | |
6448 | ||
6449 | (define_insn "ashldi3_internal8" | |
6450 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6451 | (compare:CC | |
6452 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6453 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
1990cd79 | 6454 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6455 | (const_int 0))) |
6456 | (clobber (match_scratch:DI 4 "=r,r"))] | |
683bdff7 | 6457 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6458 | "@ |
6459 | rldicr. %4,%1,%H2,%S3 | |
6460 | #" | |
6461 | [(set_attr "type" "delayed_compare") | |
6462 | (set_attr "length" "4,8")]) | |
6463 | ||
6464 | (define_split | |
6465 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6466 | (compare:CC | |
6467 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6468 | (match_operand:SI 2 "const_int_operand" "")) | |
1990cd79 | 6469 | (match_operand:DI 3 "mask64_operand" "")) |
c5059423 AM |
6470 | (const_int 0))) |
6471 | (clobber (match_scratch:DI 4 ""))] | |
6472 | "TARGET_POWERPC64 && reload_completed | |
6473 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6474 | [(set (match_dup 4) | |
6475 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6476 | (match_dup 3))) | |
6477 | (set (match_dup 0) | |
6478 | (compare:CC (match_dup 4) | |
6479 | (const_int 0)))] | |
6480 | "") | |
6481 | ||
6482 | (define_insn "*ashldi3_internal9" | |
6483 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
6484 | (compare:CC | |
6485 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6486 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
1990cd79 | 6487 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6488 | (const_int 0))) |
6489 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6490 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 6491 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6492 | "@ |
6493 | rldicr. %0,%1,%H2,%S3 | |
6494 | #" | |
6495 | [(set_attr "type" "delayed_compare") | |
6496 | (set_attr "length" "4,8")]) | |
6497 | ||
6498 | (define_split | |
6499 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6500 | (compare:CC | |
6501 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6502 | (match_operand:SI 2 "const_int_operand" "")) | |
1990cd79 | 6503 | (match_operand:DI 3 "mask64_operand" "")) |
c5059423 AM |
6504 | (const_int 0))) |
6505 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6506 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6507 | "TARGET_POWERPC64 && reload_completed | |
6508 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
9ebbca7d | 6509 | [(set (match_dup 0) |
e2c953b6 DE |
6510 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
6511 | (match_dup 3))) | |
9ebbca7d GK |
6512 | (set (match_dup 4) |
6513 | (compare:CC (match_dup 0) | |
6514 | (const_int 0)))] | |
6515 | "") | |
6516 | ||
6517 | (define_expand "lshrdi3" | |
266eb58a DE |
6518 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6519 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6520 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6521 | "TARGET_POWERPC64 || TARGET_POWER" | |
6522 | " | |
6523 | { | |
6524 | if (TARGET_POWERPC64) | |
6525 | ; | |
6526 | else if (TARGET_POWER) | |
6527 | { | |
6528 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
6529 | DONE; | |
6530 | } | |
6531 | else | |
6532 | FAIL; | |
6533 | }") | |
6534 | ||
e2c953b6 | 6535 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
6536 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6537 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6538 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6539 | "TARGET_POWERPC64" | |
a66078ee | 6540 | "srd%I2 %0,%1,%H2") |
266eb58a | 6541 | |
e2c953b6 | 6542 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
6543 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6544 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6545 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 6546 | (const_int 0))) |
9ebbca7d | 6547 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6548 | "TARGET_64BIT " |
9ebbca7d GK |
6549 | "@ |
6550 | srd%I2. %3,%1,%H2 | |
6551 | #" | |
6552 | [(set_attr "type" "delayed_compare") | |
6553 | (set_attr "length" "4,8")]) | |
6554 | ||
6555 | (define_split | |
6556 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6557 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6558 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6559 | (const_int 0))) | |
6560 | (clobber (match_scratch:DI 3 ""))] | |
6561 | "TARGET_POWERPC64 && reload_completed" | |
6562 | [(set (match_dup 3) | |
6563 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6564 | (set (match_dup 0) | |
6565 | (compare:CC (match_dup 3) | |
6566 | (const_int 0)))] | |
6567 | "") | |
266eb58a | 6568 | |
e2c953b6 | 6569 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
6570 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6571 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6572 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6573 | (const_int 0))) |
9ebbca7d | 6574 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 6575 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6576 | "TARGET_64BIT" |
9ebbca7d GK |
6577 | "@ |
6578 | srd%I2. %0,%1,%H2 | |
6579 | #" | |
6580 | [(set_attr "type" "delayed_compare") | |
6581 | (set_attr "length" "4,8")]) | |
6582 | ||
6583 | (define_split | |
6584 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6585 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6586 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6587 | (const_int 0))) | |
6588 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6589 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
6590 | "TARGET_POWERPC64 && reload_completed" | |
6591 | [(set (match_dup 0) | |
6592 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6593 | (set (match_dup 3) | |
6594 | (compare:CC (match_dup 0) | |
6595 | (const_int 0)))] | |
6596 | "") | |
266eb58a DE |
6597 | |
6598 | (define_expand "ashrdi3" | |
6599 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6600 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6601 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
97727e85 | 6602 | "WORDS_BIG_ENDIAN" |
266eb58a DE |
6603 | " |
6604 | { | |
6605 | if (TARGET_POWERPC64) | |
6606 | ; | |
6607 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
6608 | { | |
6609 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
6610 | DONE; | |
6611 | } | |
97727e85 AH |
6612 | else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT |
6613 | && WORDS_BIG_ENDIAN) | |
4aa74a4f FS |
6614 | { |
6615 | emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); | |
6616 | DONE; | |
6617 | } | |
266eb58a DE |
6618 | else |
6619 | FAIL; | |
6620 | }") | |
6621 | ||
e2c953b6 | 6622 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
6623 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6624 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6625 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6626 | "TARGET_POWERPC64" | |
375490e0 | 6627 | "srad%I2 %0,%1,%H2") |
266eb58a | 6628 | |
e2c953b6 | 6629 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
6630 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6631 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6632 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6633 | (const_int 0))) |
9ebbca7d | 6634 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6635 | "TARGET_64BIT" |
9ebbca7d GK |
6636 | "@ |
6637 | srad%I2. %3,%1,%H2 | |
6638 | #" | |
6639 | [(set_attr "type" "delayed_compare") | |
6640 | (set_attr "length" "4,8")]) | |
6641 | ||
6642 | (define_split | |
6643 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6644 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6645 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6646 | (const_int 0))) | |
6647 | (clobber (match_scratch:DI 3 ""))] | |
6648 | "TARGET_POWERPC64 && reload_completed" | |
6649 | [(set (match_dup 3) | |
6650 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6651 | (set (match_dup 0) | |
6652 | (compare:CC (match_dup 3) | |
6653 | (const_int 0)))] | |
6654 | "") | |
266eb58a | 6655 | |
e2c953b6 | 6656 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
6657 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6658 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6659 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6660 | (const_int 0))) |
9ebbca7d | 6661 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6662 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6663 | "TARGET_64BIT" |
9ebbca7d GK |
6664 | "@ |
6665 | srad%I2. %0,%1,%H2 | |
6666 | #" | |
6667 | [(set_attr "type" "delayed_compare") | |
6668 | (set_attr "length" "4,8")]) | |
6669 | ||
6670 | (define_split | |
6671 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6672 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6673 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6674 | (const_int 0))) | |
6675 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6676 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
6677 | "TARGET_POWERPC64 && reload_completed" | |
6678 | [(set (match_dup 0) | |
6679 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6680 | (set (match_dup 3) | |
6681 | (compare:CC (match_dup 0) | |
6682 | (const_int 0)))] | |
6683 | "") | |
815cdc52 | 6684 | |
29ae5b89 | 6685 | (define_insn "anddi3" |
e1e2e653 NS |
6686 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
6687 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r") | |
6688 | (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t"))) | |
6689 | (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))] | |
6ffc8580 | 6690 | "TARGET_POWERPC64" |
266eb58a DE |
6691 | "@ |
6692 | and %0,%1,%2 | |
29ae5b89 | 6693 | rldic%B2 %0,%1,0,%S2 |
e1e2e653 | 6694 | rlwinm %0,%1,0,%m2,%M2 |
29ae5b89 | 6695 | andi. %0,%1,%b2 |
0ba1b2ff AM |
6696 | andis. %0,%1,%u2 |
6697 | #" | |
e1e2e653 NS |
6698 | [(set_attr "type" "*,*,*,compare,compare,*") |
6699 | (set_attr "length" "4,4,4,4,4,8")]) | |
0ba1b2ff AM |
6700 | |
6701 | (define_split | |
6702 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6703 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6704 | (match_operand:DI 2 "mask64_2_operand" ""))) | |
6705 | (clobber (match_scratch:CC 3 ""))] | |
6706 | "TARGET_POWERPC64 | |
6707 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
1990cd79 AM |
6708 | && !mask_operand (operands[2], DImode) |
6709 | && !mask64_operand (operands[2], DImode)" | |
0ba1b2ff AM |
6710 | [(set (match_dup 0) |
6711 | (and:DI (rotate:DI (match_dup 1) | |
6712 | (match_dup 4)) | |
6713 | (match_dup 5))) | |
6714 | (set (match_dup 0) | |
6715 | (and:DI (rotate:DI (match_dup 0) | |
6716 | (match_dup 6)) | |
6717 | (match_dup 7)))] | |
0ba1b2ff AM |
6718 | { |
6719 | build_mask64_2_operands (operands[2], &operands[4]); | |
e1e2e653 | 6720 | }) |
266eb58a | 6721 | |
a260abc9 | 6722 | (define_insn "*anddi3_internal2" |
1990cd79 AM |
6723 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y") |
6724 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r") | |
6725 | (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t")) | |
266eb58a | 6726 | (const_int 0))) |
1990cd79 AM |
6727 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r")) |
6728 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))] | |
683bdff7 | 6729 | "TARGET_64BIT" |
266eb58a DE |
6730 | "@ |
6731 | and. %3,%1,%2 | |
6c873122 | 6732 | rldic%B2. %3,%1,0,%S2 |
1990cd79 | 6733 | rlwinm. %3,%1,0,%m2,%M2 |
6ffc8580 MM |
6734 | andi. %3,%1,%b2 |
6735 | andis. %3,%1,%u2 | |
9ebbca7d GK |
6736 | # |
6737 | # | |
6738 | # | |
0ba1b2ff AM |
6739 | # |
6740 | # | |
1990cd79 | 6741 | # |
9ebbca7d | 6742 | #" |
1990cd79 AM |
6743 | [(set_attr "type" "compare,delayed_compare,delayed_compare,compare,compare,delayed_compare,delayed_compare,compare,compare,compare,compare,compare") |
6744 | (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")]) | |
9ebbca7d | 6745 | |
0ba1b2ff AM |
6746 | (define_split |
6747 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
6748 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6749 | (match_operand:DI 2 "mask64_2_operand" "")) | |
6750 | (const_int 0))) | |
6751 | (clobber (match_scratch:DI 3 "")) | |
6752 | (clobber (match_scratch:CC 4 ""))] | |
1990cd79 | 6753 | "TARGET_64BIT && reload_completed |
0ba1b2ff | 6754 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) |
1990cd79 AM |
6755 | && !mask_operand (operands[2], DImode) |
6756 | && !mask64_operand (operands[2], DImode)" | |
0ba1b2ff AM |
6757 | [(set (match_dup 3) |
6758 | (and:DI (rotate:DI (match_dup 1) | |
6759 | (match_dup 5)) | |
6760 | (match_dup 6))) | |
6761 | (parallel [(set (match_dup 0) | |
6762 | (compare:CC (and:DI (rotate:DI (match_dup 3) | |
6763 | (match_dup 7)) | |
6764 | (match_dup 8)) | |
6765 | (const_int 0))) | |
6766 | (clobber (match_dup 3))])] | |
6767 | " | |
6768 | { | |
6769 | build_mask64_2_operands (operands[2], &operands[5]); | |
6770 | }") | |
6771 | ||
a260abc9 | 6772 | (define_insn "*anddi3_internal3" |
1990cd79 AM |
6773 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y") |
6774 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r") | |
6775 | (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t")) | |
266eb58a | 6776 | (const_int 0))) |
1990cd79 | 6777 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r") |
9ebbca7d | 6778 | (and:DI (match_dup 1) (match_dup 2))) |
1990cd79 | 6779 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))] |
683bdff7 | 6780 | "TARGET_64BIT" |
266eb58a DE |
6781 | "@ |
6782 | and. %0,%1,%2 | |
6c873122 | 6783 | rldic%B2. %0,%1,0,%S2 |
1990cd79 | 6784 | rlwinm. %0,%1,0,%m2,%M2 |
6ffc8580 MM |
6785 | andi. %0,%1,%b2 |
6786 | andis. %0,%1,%u2 | |
9ebbca7d GK |
6787 | # |
6788 | # | |
6789 | # | |
0ba1b2ff AM |
6790 | # |
6791 | # | |
1990cd79 | 6792 | # |
9ebbca7d | 6793 | #" |
1990cd79 AM |
6794 | [(set_attr "type" "compare,delayed_compare,delayed_compare,compare,compare,delayed_compare,delayed_compare,compare,compare,compare,compare,compare") |
6795 | (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")]) | |
9ebbca7d GK |
6796 | |
6797 | (define_split | |
6798 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6799 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1990cd79 | 6800 | (match_operand:DI 2 "and64_2_operand" "")) |
9ebbca7d GK |
6801 | (const_int 0))) |
6802 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6803 | (and:DI (match_dup 1) (match_dup 2))) | |
6804 | (clobber (match_scratch:CC 4 ""))] | |
1990cd79 | 6805 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
6806 | [(parallel [(set (match_dup 0) |
6807 | (and:DI (match_dup 1) (match_dup 2))) | |
6808 | (clobber (match_dup 4))]) | |
6809 | (set (match_dup 3) | |
6810 | (compare:CC (match_dup 0) | |
6811 | (const_int 0)))] | |
6812 | "") | |
266eb58a | 6813 | |
0ba1b2ff AM |
6814 | (define_split |
6815 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
6816 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6817 | (match_operand:DI 2 "mask64_2_operand" "")) | |
6818 | (const_int 0))) | |
6819 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6820 | (and:DI (match_dup 1) (match_dup 2))) | |
6821 | (clobber (match_scratch:CC 4 ""))] | |
1990cd79 | 6822 | "TARGET_64BIT && reload_completed |
0ba1b2ff | 6823 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) |
1990cd79 AM |
6824 | && !mask_operand (operands[2], DImode) |
6825 | && !mask64_operand (operands[2], DImode)" | |
0ba1b2ff AM |
6826 | [(set (match_dup 0) |
6827 | (and:DI (rotate:DI (match_dup 1) | |
6828 | (match_dup 5)) | |
6829 | (match_dup 6))) | |
6830 | (parallel [(set (match_dup 3) | |
6831 | (compare:CC (and:DI (rotate:DI (match_dup 0) | |
6832 | (match_dup 7)) | |
6833 | (match_dup 8)) | |
6834 | (const_int 0))) | |
6835 | (set (match_dup 0) | |
6836 | (and:DI (rotate:DI (match_dup 0) | |
6837 | (match_dup 7)) | |
6838 | (match_dup 8)))])] | |
6839 | " | |
6840 | { | |
6841 | build_mask64_2_operands (operands[2], &operands[5]); | |
6842 | }") | |
6843 | ||
a260abc9 | 6844 | (define_expand "iordi3" |
266eb58a | 6845 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 6846 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 6847 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 6848 | "TARGET_POWERPC64" |
266eb58a DE |
6849 | " |
6850 | { | |
dfbdccdb | 6851 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 6852 | { |
dfbdccdb | 6853 | HOST_WIDE_INT value; |
677a9668 | 6854 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 6855 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 6856 | |
dfbdccdb GK |
6857 | if (GET_CODE (operands[2]) == CONST_INT) |
6858 | { | |
6859 | value = INTVAL (operands[2]); | |
6860 | emit_insn (gen_iordi3 (tmp, operands[1], | |
6861 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
6862 | } | |
e2c953b6 | 6863 | else |
dfbdccdb GK |
6864 | { |
6865 | value = CONST_DOUBLE_LOW (operands[2]); | |
6866 | emit_insn (gen_iordi3 (tmp, operands[1], | |
6867 | immed_double_const (value | |
6868 | & (~ (HOST_WIDE_INT) 0xffff), | |
6869 | 0, DImode))); | |
6870 | } | |
e2c953b6 | 6871 | |
9ebbca7d GK |
6872 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
6873 | DONE; | |
6874 | } | |
266eb58a DE |
6875 | }") |
6876 | ||
a260abc9 DE |
6877 | (define_expand "xordi3" |
6878 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6879 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 6880 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
6881 | "TARGET_POWERPC64" |
6882 | " | |
6883 | { | |
dfbdccdb | 6884 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 6885 | { |
dfbdccdb | 6886 | HOST_WIDE_INT value; |
677a9668 | 6887 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
6888 | ? operands[0] : gen_reg_rtx (DImode)); |
6889 | ||
dfbdccdb GK |
6890 | if (GET_CODE (operands[2]) == CONST_INT) |
6891 | { | |
6892 | value = INTVAL (operands[2]); | |
6893 | emit_insn (gen_xordi3 (tmp, operands[1], | |
6894 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
6895 | } | |
e2c953b6 | 6896 | else |
dfbdccdb GK |
6897 | { |
6898 | value = CONST_DOUBLE_LOW (operands[2]); | |
6899 | emit_insn (gen_xordi3 (tmp, operands[1], | |
6900 | immed_double_const (value | |
6901 | & (~ (HOST_WIDE_INT) 0xffff), | |
6902 | 0, DImode))); | |
6903 | } | |
e2c953b6 | 6904 | |
9ebbca7d GK |
6905 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
6906 | DONE; | |
6907 | } | |
a260abc9 DE |
6908 | }") |
6909 | ||
dfbdccdb | 6910 | (define_insn "*booldi3_internal1" |
266eb58a | 6911 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 6912 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
6913 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
6914 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 6915 | "TARGET_POWERPC64" |
1fd4e8c1 | 6916 | "@ |
dfbdccdb GK |
6917 | %q3 %0,%1,%2 |
6918 | %q3i %0,%1,%b2 | |
6919 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 6920 | |
dfbdccdb | 6921 | (define_insn "*booldi3_internal2" |
9ebbca7d | 6922 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 6923 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
6924 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
6925 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
6926 | (const_int 0))) | |
9ebbca7d | 6927 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6928 | "TARGET_64BIT" |
9ebbca7d | 6929 | "@ |
dfbdccdb | 6930 | %q4. %3,%1,%2 |
9ebbca7d GK |
6931 | #" |
6932 | [(set_attr "type" "compare") | |
6933 | (set_attr "length" "4,8")]) | |
6934 | ||
6935 | (define_split | |
6936 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 6937 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
6938 | [(match_operand:DI 1 "gpc_reg_operand" "") |
6939 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 6940 | (const_int 0))) |
9ebbca7d GK |
6941 | (clobber (match_scratch:DI 3 ""))] |
6942 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 6943 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
6944 | (set (match_dup 0) |
6945 | (compare:CC (match_dup 3) | |
6946 | (const_int 0)))] | |
6947 | "") | |
1fd4e8c1 | 6948 | |
dfbdccdb | 6949 | (define_insn "*booldi3_internal3" |
9ebbca7d | 6950 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
6951 | (compare:CC (match_operator:DI 4 "boolean_operator" |
6952 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6953 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
6954 | (const_int 0))) | |
9ebbca7d | 6955 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 6956 | (match_dup 4))] |
683bdff7 | 6957 | "TARGET_64BIT" |
9ebbca7d | 6958 | "@ |
dfbdccdb | 6959 | %q4. %0,%1,%2 |
9ebbca7d GK |
6960 | #" |
6961 | [(set_attr "type" "compare") | |
6962 | (set_attr "length" "4,8")]) | |
6963 | ||
6964 | (define_split | |
e72247f4 | 6965 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 6966 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
6967 | [(match_operand:DI 1 "gpc_reg_operand" "") |
6968 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 6969 | (const_int 0))) |
75540af0 | 6970 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 6971 | (match_dup 4))] |
9ebbca7d | 6972 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 6973 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
6974 | (set (match_dup 3) |
6975 | (compare:CC (match_dup 0) | |
6976 | (const_int 0)))] | |
6977 | "") | |
1fd4e8c1 | 6978 | |
6ae08853 | 6979 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 6980 | ;; each of which does one 16-bit part. This is used by combine. |
266eb58a DE |
6981 | |
6982 | (define_split | |
6983 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 6984 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
6985 | [(match_operand:DI 1 "gpc_reg_operand" "") |
6986 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 6987 | "TARGET_POWERPC64" |
dfbdccdb GK |
6988 | [(set (match_dup 0) (match_dup 4)) |
6989 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
6990 | " |
6991 | { | |
dfbdccdb | 6992 | rtx i3,i4; |
6ae08853 | 6993 | |
9ebbca7d GK |
6994 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
6995 | { | |
6996 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 6997 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 6998 | 0, DImode); |
dfbdccdb | 6999 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7000 | } |
7001 | else | |
7002 | { | |
dfbdccdb | 7003 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7004 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7005 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7006 | } |
1c563bed | 7007 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7008 | operands[1], i3); |
1c563bed | 7009 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7010 | operands[0], i4); |
1fd4e8c1 RK |
7011 | }") |
7012 | ||
dfbdccdb | 7013 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7014 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7015 | (match_operator:DI 3 "boolean_operator" |
7016 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7017 | (match_operand:DI 2 "gpc_reg_operand" "r")]))] |
a473029f | 7018 | "TARGET_POWERPC64" |
1d328b19 | 7019 | "%q3 %0,%2,%1") |
a473029f | 7020 | |
dfbdccdb | 7021 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7022 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7023 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7024 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7025 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7026 | (const_int 0))) | |
9ebbca7d | 7027 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7028 | "TARGET_64BIT" |
9ebbca7d | 7029 | "@ |
1d328b19 | 7030 | %q4. %3,%2,%1 |
9ebbca7d GK |
7031 | #" |
7032 | [(set_attr "type" "compare") | |
7033 | (set_attr "length" "4,8")]) | |
7034 | ||
7035 | (define_split | |
7036 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7037 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7038 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7039 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7040 | (const_int 0))) |
9ebbca7d GK |
7041 | (clobber (match_scratch:DI 3 ""))] |
7042 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7043 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7044 | (set (match_dup 0) |
7045 | (compare:CC (match_dup 3) | |
7046 | (const_int 0)))] | |
7047 | "") | |
a473029f | 7048 | |
dfbdccdb | 7049 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7050 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7051 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7052 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7053 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7054 | (const_int 0))) | |
9ebbca7d | 7055 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7056 | (match_dup 4))] |
683bdff7 | 7057 | "TARGET_64BIT" |
9ebbca7d | 7058 | "@ |
1d328b19 | 7059 | %q4. %0,%2,%1 |
9ebbca7d GK |
7060 | #" |
7061 | [(set_attr "type" "compare") | |
7062 | (set_attr "length" "4,8")]) | |
7063 | ||
7064 | (define_split | |
e72247f4 | 7065 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7066 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7067 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7068 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7069 | (const_int 0))) |
75540af0 | 7070 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7071 | (match_dup 4))] |
9ebbca7d | 7072 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7073 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7074 | (set (match_dup 3) |
7075 | (compare:CC (match_dup 0) | |
7076 | (const_int 0)))] | |
7077 | "") | |
266eb58a | 7078 | |
dfbdccdb | 7079 | (define_insn "*boolccdi3_internal1" |
a473029f | 7080 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7081 | (match_operator:DI 3 "boolean_operator" |
7082 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7083 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] |
a473029f | 7084 | "TARGET_POWERPC64" |
dfbdccdb | 7085 | "%q3 %0,%1,%2") |
a473029f | 7086 | |
dfbdccdb | 7087 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7088 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7089 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7090 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7091 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7092 | (const_int 0))) | |
9ebbca7d | 7093 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7094 | "TARGET_64BIT" |
9ebbca7d | 7095 | "@ |
dfbdccdb | 7096 | %q4. %3,%1,%2 |
9ebbca7d GK |
7097 | #" |
7098 | [(set_attr "type" "compare") | |
7099 | (set_attr "length" "4,8")]) | |
7100 | ||
7101 | (define_split | |
7102 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7103 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7104 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7105 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7106 | (const_int 0))) |
9ebbca7d GK |
7107 | (clobber (match_scratch:DI 3 ""))] |
7108 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7109 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7110 | (set (match_dup 0) |
7111 | (compare:CC (match_dup 3) | |
7112 | (const_int 0)))] | |
7113 | "") | |
266eb58a | 7114 | |
dfbdccdb | 7115 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7116 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7117 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7118 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7119 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7120 | (const_int 0))) | |
9ebbca7d | 7121 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7122 | (match_dup 4))] |
683bdff7 | 7123 | "TARGET_64BIT" |
9ebbca7d | 7124 | "@ |
dfbdccdb | 7125 | %q4. %0,%1,%2 |
9ebbca7d GK |
7126 | #" |
7127 | [(set_attr "type" "compare") | |
7128 | (set_attr "length" "4,8")]) | |
7129 | ||
7130 | (define_split | |
e72247f4 | 7131 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7132 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7133 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7134 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7135 | (const_int 0))) |
75540af0 | 7136 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7137 | (match_dup 4))] |
9ebbca7d | 7138 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7139 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7140 | (set (match_dup 3) |
7141 | (compare:CC (match_dup 0) | |
7142 | (const_int 0)))] | |
7143 | "") | |
dfbdccdb | 7144 | \f |
1fd4e8c1 | 7145 | ;; Now define ways of moving data around. |
4697a36c | 7146 | |
766a866c MM |
7147 | ;; Set up a register with a value from the GOT table |
7148 | ||
7149 | (define_expand "movsi_got" | |
52d3af72 | 7150 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7151 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
615158e2 | 7152 | (match_dup 2)] UNSPEC_MOVSI_GOT))] |
f607bc57 | 7153 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7154 | " |
7155 | { | |
38c1f2d7 MM |
7156 | if (GET_CODE (operands[1]) == CONST) |
7157 | { | |
7158 | rtx offset = const0_rtx; | |
7159 | HOST_WIDE_INT value; | |
7160 | ||
7161 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7162 | value = INTVAL (offset); | |
7163 | if (value != 0) | |
7164 | { | |
677a9668 | 7165 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7166 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7167 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7168 | DONE; | |
7169 | } | |
7170 | } | |
7171 | ||
c4c40373 | 7172 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7173 | }") |
7174 | ||
84f414bc | 7175 | (define_insn "*movsi_got_internal" |
52d3af72 | 7176 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d | 7177 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7178 | (match_operand:SI 2 "gpc_reg_operand" "b")] |
7179 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7180 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7181 | "{l|lwz} %0,%a1@got(%2)" |
7182 | [(set_attr "type" "load")]) | |
7183 | ||
b22b9b3e JL |
7184 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7185 | ;; didn't get allocated to a hard register. | |
6ae08853 | 7186 | (define_split |
75540af0 | 7187 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7188 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7189 | (match_operand:SI 2 "memory_operand" "")] |
7190 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7191 | "DEFAULT_ABI == ABI_V4 |
b22b9b3e JL |
7192 | && flag_pic == 1 |
7193 | && (reload_in_progress || reload_completed)" | |
7194 | [(set (match_dup 0) (match_dup 2)) | |
615158e2 JJ |
7195 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] |
7196 | UNSPEC_MOVSI_GOT))] | |
b22b9b3e JL |
7197 | "") |
7198 | ||
1fd4e8c1 RK |
7199 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7200 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7201 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7202 | ;; integers in the TOC. | |
ee890fe2 SS |
7203 | (define_insn "movsi_low" |
7204 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
f585a356 | 7205 | (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
ee890fe2 SS |
7206 | (match_operand 2 "" ""))))] |
7207 | "TARGET_MACHO && ! TARGET_64BIT" | |
7208 | "{l|lwz} %0,lo16(%2)(%1)" | |
7209 | [(set_attr "type" "load") | |
7210 | (set_attr "length" "4")]) | |
7211 | ||
acad7ed3 | 7212 | (define_insn "*movsi_internal1" |
165a5bad | 7213 | [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") |
a004eb82 | 7214 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] |
19d5775a RK |
7215 | "gpc_reg_operand (operands[0], SImode) |
7216 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7217 | "@ |
deb9225a | 7218 | mr %0,%1 |
b9442c72 | 7219 | {cal|la} %0,%a1 |
ca7f5001 RK |
7220 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7221 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7222 | {lil|li} %0,%1 |
802a0058 | 7223 | {liu|lis} %0,%v1 |
beaec479 | 7224 | # |
aee86b38 | 7225 | {cal|la} %0,%a1 |
1fd4e8c1 | 7226 | mf%1 %0 |
5c23c401 | 7227 | mt%0 %1 |
e76e75bb | 7228 | mt%0 %1 |
a004eb82 | 7229 | mt%0 %1 |
e34eaae5 | 7230 | {cror 0,0,0|nop}" |
02ca7595 | 7231 | [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*") |
a004eb82 | 7232 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7233 | |
77fa0940 RK |
7234 | ;; Split a load of a large constant into the appropriate two-insn |
7235 | ;; sequence. | |
7236 | ||
7237 | (define_split | |
7238 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7239 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7240 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7241 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7242 | [(set (match_dup 0) | |
7243 | (match_dup 2)) | |
7244 | (set (match_dup 0) | |
7245 | (ior:SI (match_dup 0) | |
7246 | (match_dup 3)))] | |
7247 | " | |
af8cb5c5 DE |
7248 | { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2); |
7249 | ||
7250 | if (tem == operands[0]) | |
7251 | DONE; | |
7252 | else | |
7253 | FAIL; | |
77fa0940 RK |
7254 | }") |
7255 | ||
4ae234b0 | 7256 | (define_insn "*mov<mode>_internal2" |
bb84cb12 | 7257 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
4ae234b0 | 7258 | (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r") |
1fd4e8c1 | 7259 | (const_int 0))) |
4ae234b0 GK |
7260 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
7261 | "" | |
9ebbca7d | 7262 | "@ |
4ae234b0 | 7263 | {cmpi|cmp<wd>i} %2,%0,0 |
9ebbca7d GK |
7264 | mr. %0,%1 |
7265 | #" | |
bb84cb12 DE |
7266 | [(set_attr "type" "cmp,compare,cmp") |
7267 | (set_attr "length" "4,4,8")]) | |
7268 | ||
9ebbca7d GK |
7269 | (define_split |
7270 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
4ae234b0 | 7271 | (compare:CC (match_operand:P 1 "gpc_reg_operand" "") |
9ebbca7d | 7272 | (const_int 0))) |
4ae234b0 GK |
7273 | (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))] |
7274 | "reload_completed" | |
9ebbca7d GK |
7275 | [(set (match_dup 0) (match_dup 1)) |
7276 | (set (match_dup 2) | |
7277 | (compare:CC (match_dup 0) | |
7278 | (const_int 0)))] | |
7279 | "") | |
bb84cb12 | 7280 | \f |
e34eaae5 | 7281 | (define_insn "*movhi_internal" |
fb81d7ce RK |
7282 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7283 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7284 | "gpc_reg_operand (operands[0], HImode) |
7285 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7286 | "@ |
deb9225a | 7287 | mr %0,%1 |
1fd4e8c1 RK |
7288 | lhz%U1%X1 %0,%1 |
7289 | sth%U0%X0 %1,%0 | |
19d5775a | 7290 | {lil|li} %0,%w1 |
1fd4e8c1 | 7291 | mf%1 %0 |
e76e75bb | 7292 | mt%0 %1 |
fb81d7ce | 7293 | mt%0 %1 |
e34eaae5 | 7294 | {cror 0,0,0|nop}" |
02ca7595 | 7295 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 | 7296 | |
4ae234b0 GK |
7297 | (define_expand "mov<mode>" |
7298 | [(set (match_operand:INT 0 "general_operand" "") | |
7299 | (match_operand:INT 1 "any_operand" ""))] | |
1fd4e8c1 | 7300 | "" |
4ae234b0 | 7301 | "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") |
1fd4e8c1 | 7302 | |
e34eaae5 | 7303 | (define_insn "*movqi_internal" |
fb81d7ce RK |
7304 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7305 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7306 | "gpc_reg_operand (operands[0], QImode) |
7307 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7308 | "@ |
deb9225a | 7309 | mr %0,%1 |
1fd4e8c1 RK |
7310 | lbz%U1%X1 %0,%1 |
7311 | stb%U0%X0 %1,%0 | |
19d5775a | 7312 | {lil|li} %0,%1 |
1fd4e8c1 | 7313 | mf%1 %0 |
e76e75bb | 7314 | mt%0 %1 |
fb81d7ce | 7315 | mt%0 %1 |
e34eaae5 | 7316 | {cror 0,0,0|nop}" |
02ca7595 | 7317 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7318 | \f |
7319 | ;; Here is how to move condition codes around. When we store CC data in | |
7320 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7321 | ;; This lets us not shift in the most common case of CR0. | |
7322 | (define_expand "movcc" | |
7323 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7324 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7325 | "" | |
7326 | "") | |
7327 | ||
a65c591c | 7328 | (define_insn "*movcc_internal1" |
b54cf83a DE |
7329 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m") |
7330 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))] | |
1fd4e8c1 RK |
7331 | "register_operand (operands[0], CCmode) |
7332 | || register_operand (operands[1], CCmode)" | |
7333 | "@ | |
7334 | mcrf %0,%1 | |
7335 | mtcrf 128,%1 | |
ca7f5001 | 7336 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
2c4a9cff DE |
7337 | mfcr %0%Q1 |
7338 | mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 | |
deb9225a | 7339 | mr %0,%1 |
b54cf83a | 7340 | mf%1 %0 |
b991a865 GK |
7341 | mt%0 %1 |
7342 | mt%0 %1 | |
ca7f5001 RK |
7343 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7344 | {st%U0%U1|stw%U0%U1} %1,%0" | |
2c4a9cff DE |
7345 | [(set (attr "type") |
7346 | (cond [(eq_attr "alternative" "0") | |
7347 | (const_string "cr_logical") | |
7348 | (eq_attr "alternative" "1,2") | |
7349 | (const_string "mtcr") | |
7350 | (eq_attr "alternative" "5,7") | |
7351 | (const_string "integer") | |
7352 | (eq_attr "alternative" "6") | |
7353 | (const_string "mfjmpr") | |
7354 | (eq_attr "alternative" "8") | |
7355 | (const_string "mtjmpr") | |
7356 | (eq_attr "alternative" "9") | |
7357 | (const_string "load") | |
7358 | (eq_attr "alternative" "10") | |
7359 | (const_string "store") | |
7360 | (ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
7361 | (const_string "mfcrf") | |
7362 | ] | |
7363 | (const_string "mfcr"))) | |
b991a865 | 7364 | (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7365 | \f |
e52e05ca MM |
7366 | ;; For floating-point, we normally deal with the floating-point registers |
7367 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7368 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7369 | ;; value is a simple constant or already in memory, we deal with this by | |
7370 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7371 | (define_expand "movsf" |
7372 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7373 | (match_operand:SF 1 "any_operand" ""))] | |
7374 | "" | |
fb4d4348 | 7375 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 7376 | |
1fd4e8c1 | 7377 | (define_split |
cd2b37d9 | 7378 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7379 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7380 | "reload_completed |
5ae4759c MM |
7381 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7382 | || (GET_CODE (operands[0]) == SUBREG | |
7383 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7384 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7385 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7386 | " |
7387 | { | |
7388 | long l; | |
7389 | REAL_VALUE_TYPE rv; | |
7390 | ||
7391 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7392 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7393 | |
f99f88e0 DE |
7394 | if (! TARGET_POWERPC64) |
7395 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7396 | else | |
7397 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7398 | |
2496c7bd | 7399 | operands[3] = gen_int_mode (l, SImode); |
a260abc9 DE |
7400 | }") |
7401 | ||
c4c40373 | 7402 | (define_insn "*movsf_hardfloat" |
fb3249ef | 7403 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r") |
ae6669e7 | 7404 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))] |
d14a6d05 | 7405 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7406 | || gpc_reg_operand (operands[1], SFmode)) |
7407 | && (TARGET_HARD_FLOAT && TARGET_FPRS)" | |
1fd4e8c1 | 7408 | "@ |
f99f88e0 DE |
7409 | mr %0,%1 |
7410 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7411 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7412 | fmr %0,%1 |
7413 | lfs%U1%X1 %0,%1 | |
c4c40373 | 7414 | stfs%U0%X0 %1,%0 |
b991a865 GK |
7415 | mt%0 %1 |
7416 | mt%0 %1 | |
7417 | mf%1 %0 | |
e0740893 | 7418 | {cror 0,0,0|nop} |
c4c40373 MM |
7419 | # |
7420 | #" | |
ae6669e7 DJ |
7421 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*") |
7422 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7423 | |
c4c40373 | 7424 | (define_insn "*movsf_softfloat" |
dd0fbae2 MK |
7425 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h") |
7426 | (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))] | |
d14a6d05 | 7427 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7428 | || gpc_reg_operand (operands[1], SFmode)) |
7429 | && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" | |
d14a6d05 MM |
7430 | "@ |
7431 | mr %0,%1 | |
b991a865 GK |
7432 | mt%0 %1 |
7433 | mt%0 %1 | |
7434 | mf%1 %0 | |
d14a6d05 MM |
7435 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7436 | {st%U0%X0|stw%U0%X0} %1,%0 | |
7437 | {lil|li} %0,%1 | |
802a0058 | 7438 | {liu|lis} %0,%v1 |
aee86b38 | 7439 | {cal|la} %0,%a1 |
c4c40373 | 7440 | # |
dd0fbae2 MK |
7441 | # |
7442 | {cror 0,0,0|nop}" | |
7443 | [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*") | |
7444 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")]) | |
d14a6d05 | 7445 | |
1fd4e8c1 RK |
7446 | \f |
7447 | (define_expand "movdf" | |
7448 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
7449 | (match_operand:DF 1 "any_operand" ""))] | |
7450 | "" | |
fb4d4348 | 7451 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
7452 | |
7453 | (define_split | |
cd2b37d9 | 7454 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 7455 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 7456 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7457 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7458 | || (GET_CODE (operands[0]) == SUBREG | |
7459 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7460 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7461 | [(set (match_dup 2) (match_dup 4)) |
7462 | (set (match_dup 3) (match_dup 1))] | |
7463 | " | |
7464 | { | |
5ae4759c | 7465 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
7466 | HOST_WIDE_INT value = INTVAL (operands[1]); |
7467 | ||
5ae4759c MM |
7468 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7469 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
7470 | #if HOST_BITS_PER_WIDE_INT == 32 |
7471 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
7472 | #else | |
7473 | operands[4] = GEN_INT (value >> 32); | |
a65c591c | 7474 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
5f59ecb7 | 7475 | #endif |
c4c40373 MM |
7476 | }") |
7477 | ||
c4c40373 MM |
7478 | (define_split |
7479 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
7480 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 7481 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7482 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7483 | || (GET_CODE (operands[0]) == SUBREG | |
7484 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7485 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7486 | [(set (match_dup 2) (match_dup 4)) |
7487 | (set (match_dup 3) (match_dup 5))] | |
7488 | " | |
7489 | { | |
5ae4759c | 7490 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
7491 | long l[2]; |
7492 | REAL_VALUE_TYPE rv; | |
7493 | ||
7494 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7495 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7496 | ||
5ae4759c MM |
7497 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7498 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
2496c7bd LB |
7499 | operands[4] = gen_int_mode (l[endian], SImode); |
7500 | operands[5] = gen_int_mode (l[1 - endian], SImode); | |
c4c40373 MM |
7501 | }") |
7502 | ||
efc08378 DE |
7503 | (define_split |
7504 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
8308679f | 7505 | (match_operand:DF 1 "const_double_operand" ""))] |
a260abc9 | 7506 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7507 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7508 | || (GET_CODE (operands[0]) == SUBREG | |
7509 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7510 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 7511 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 7512 | " |
a260abc9 DE |
7513 | { |
7514 | int endian = (WORDS_BIG_ENDIAN == 0); | |
7515 | long l[2]; | |
7516 | REAL_VALUE_TYPE rv; | |
4977bab6 | 7517 | #if HOST_BITS_PER_WIDE_INT >= 64 |
5b029315 | 7518 | HOST_WIDE_INT val; |
4977bab6 | 7519 | #endif |
a260abc9 DE |
7520 | |
7521 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7522 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7523 | ||
7524 | operands[2] = gen_lowpart (DImode, operands[0]); | |
7525 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
5b029315 | 7526 | #if HOST_BITS_PER_WIDE_INT >= 64 |
a2419b96 DE |
7527 | val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 |
7528 | | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); | |
5b029315 | 7529 | |
f5264b52 | 7530 | operands[3] = gen_int_mode (val, DImode); |
5b029315 | 7531 | #else |
a260abc9 | 7532 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); |
5b029315 | 7533 | #endif |
a260abc9 | 7534 | }") |
efc08378 | 7535 | |
4eae5fe1 | 7536 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 7537 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
7538 | ;; a non-offsettable memref, but also it is less efficient than loading |
7539 | ;; the constant into an FP register, since it will probably be used there. | |
7540 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
7541 | ;; of handling these non-offsettable values. | |
c4c40373 | 7542 | (define_insn "*movdf_hardfloat32" |
914a7297 DE |
7543 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") |
7544 | (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] | |
a3170dc6 | 7545 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
7546 | && (gpc_reg_operand (operands[0], DFmode) |
7547 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
7548 | "* |
7549 | { | |
7550 | switch (which_alternative) | |
7551 | { | |
a260abc9 | 7552 | default: |
37409796 | 7553 | gcc_unreachable (); |
e7113111 RK |
7554 | case 0: |
7555 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
7556 | the first register operand 0 is the same as the second register |
7557 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 7558 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 7559 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 7560 | else |
deb9225a | 7561 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 7562 | case 1: |
819e019c EC |
7563 | if (GET_CODE (operands[1]) == MEM |
7564 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0), | |
7565 | reload_completed || reload_in_progress) | |
0c380712 | 7566 | || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[1], 0)) |
819e019c EC |
7567 | || GET_CODE (XEXP (operands[1], 0)) == REG |
7568 | || GET_CODE (XEXP (operands[1], 0)) == LO_SUM | |
0c380712 | 7569 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC |
819e019c | 7570 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)) |
000034eb DE |
7571 | { |
7572 | /* If the low-address word is used in the address, we must load | |
7573 | it last. Otherwise, load it first. Note that we cannot have | |
7574 | auto-increment in that case since the address register is | |
7575 | known to be dead. */ | |
7576 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
7577 | operands[1], 0)) | |
7578 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
7579 | else | |
7580 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7581 | } | |
e7113111 | 7582 | else |
000034eb DE |
7583 | { |
7584 | rtx addreg; | |
7585 | ||
000034eb DE |
7586 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
7587 | if (refers_to_regno_p (REGNO (operands[0]), | |
7588 | REGNO (operands[0]) + 1, | |
7589 | operands[1], 0)) | |
7590 | { | |
7591 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 7592 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 7593 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 7594 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
7595 | } |
7596 | else | |
7597 | { | |
2b97222d | 7598 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 7599 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 7600 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
7601 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
7602 | return \"\"; | |
7603 | } | |
7604 | } | |
e7113111 | 7605 | case 2: |
819e019c EC |
7606 | if (GET_CODE (operands[0]) == MEM |
7607 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0), | |
7608 | reload_completed || reload_in_progress) | |
0c380712 | 7609 | || rs6000_legitimate_small_data_p (DFmode, XEXP (operands[0], 0)) |
819e019c EC |
7610 | || GET_CODE (XEXP (operands[0], 0)) == REG |
7611 | || GET_CODE (XEXP (operands[0], 0)) == LO_SUM | |
0c380712 | 7612 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC |
819e019c | 7613 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)) |
000034eb DE |
7614 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
7615 | else | |
7616 | { | |
7617 | rtx addreg; | |
7618 | ||
000034eb | 7619 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 7620 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 7621 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 7622 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
7623 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
7624 | return \"\"; | |
7625 | } | |
e7113111 | 7626 | case 3: |
914a7297 | 7627 | return \"fmr %0,%1\"; |
e7113111 | 7628 | case 4: |
914a7297 | 7629 | return \"lfd%U1%X1 %0,%1\"; |
e7113111 | 7630 | case 5: |
914a7297 | 7631 | return \"stfd%U0%X0 %1,%0\"; |
e7113111 | 7632 | case 6: |
c4c40373 | 7633 | case 7: |
c4c40373 | 7634 | case 8: |
914a7297 | 7635 | return \"#\"; |
e7113111 RK |
7636 | } |
7637 | }" | |
943c15ed | 7638 | [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*") |
914a7297 | 7639 | (set_attr "length" "8,16,16,4,4,4,8,12,16")]) |
51b8fc2c | 7640 | |
c4c40373 | 7641 | (define_insn "*movdf_softfloat32" |
1427100a DE |
7642 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
7643 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
7a2f7870 | 7644 | "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) |
52d3af72 DE |
7645 | && (gpc_reg_operand (operands[0], DFmode) |
7646 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
7647 | "* |
7648 | { | |
7649 | switch (which_alternative) | |
7650 | { | |
a260abc9 | 7651 | default: |
37409796 | 7652 | gcc_unreachable (); |
dc4f83ca MM |
7653 | case 0: |
7654 | /* We normally copy the low-numbered register first. However, if | |
7655 | the first register operand 0 is the same as the second register of | |
7656 | operand 1, we must copy in the opposite order. */ | |
7657 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
7658 | return \"mr %L0,%L1\;mr %0,%1\"; | |
7659 | else | |
7660 | return \"mr %0,%1\;mr %L0,%L1\"; | |
7661 | case 1: | |
3cb999d8 DE |
7662 | /* If the low-address word is used in the address, we must load |
7663 | it last. Otherwise, load it first. Note that we cannot have | |
7664 | auto-increment in that case since the address register is | |
7665 | known to be dead. */ | |
dc4f83ca | 7666 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 7667 | operands[1], 0)) |
dc4f83ca MM |
7668 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
7669 | else | |
7670 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7671 | case 2: | |
7672 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
7673 | case 3: | |
c4c40373 MM |
7674 | case 4: |
7675 | case 5: | |
dc4f83ca MM |
7676 | return \"#\"; |
7677 | } | |
7678 | }" | |
943c15ed | 7679 | [(set_attr "type" "two,load,store,*,*,*") |
c4c40373 | 7680 | (set_attr "length" "8,8,8,8,12,16")]) |
dc4f83ca | 7681 | |
d2288d5d HP |
7682 | ; ld/std require word-aligned displacements -> 'Y' constraint. |
7683 | ; List Y->r and r->Y before r->r for reload. | |
c4c40373 | 7684 | (define_insn "*movdf_hardfloat64" |
fb3249ef | 7685 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r") |
ae6669e7 | 7686 | (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] |
a3170dc6 | 7687 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
7688 | && (gpc_reg_operand (operands[0], DFmode) |
7689 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 7690 | "@ |
96bb8ed3 | 7691 | std%U0%X0 %1,%0 |
3364872d FJ |
7692 | ld%U1%X1 %0,%1 |
7693 | mr %0,%1 | |
3d5570cb | 7694 | fmr %0,%1 |
f63184ac | 7695 | lfd%U1%X1 %0,%1 |
914a7297 DE |
7696 | stfd%U0%X0 %1,%0 |
7697 | mt%0 %1 | |
7698 | mf%1 %0 | |
e0740893 | 7699 | {cror 0,0,0|nop} |
914a7297 DE |
7700 | # |
7701 | # | |
7702 | #" | |
ae6669e7 DJ |
7703 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*") |
7704 | (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")]) | |
dc4f83ca | 7705 | |
c4c40373 | 7706 | (define_insn "*movdf_softfloat64" |
d2288d5d HP |
7707 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h") |
7708 | (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))] | |
a3170dc6 | 7709 | "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
7710 | && (gpc_reg_operand (operands[0], DFmode) |
7711 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca | 7712 | "@ |
d2288d5d HP |
7713 | ld%U1%X1 %0,%1 |
7714 | std%U0%X0 %1,%0 | |
dc4f83ca | 7715 | mr %0,%1 |
914a7297 DE |
7716 | mt%0 %1 |
7717 | mf%1 %0 | |
c4c40373 MM |
7718 | # |
7719 | # | |
e2d0915c | 7720 | # |
e0740893 | 7721 | {cror 0,0,0|nop}" |
d2288d5d | 7722 | [(set_attr "type" "load,store,*,*,*,*,*,*,*") |
e2d0915c | 7723 | (set_attr "length" "4,4,4,4,4,8,12,16,4")]) |
1fd4e8c1 | 7724 | \f |
06f4e019 DE |
7725 | (define_expand "movtf" |
7726 | [(set (match_operand:TF 0 "general_operand" "") | |
7727 | (match_operand:TF 1 "any_operand" ""))] | |
39e63627 GK |
7728 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7729 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
7730 | "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") |
7731 | ||
a9baceb1 GK |
7732 | ; It's important to list the o->f and f->o moves before f->f because |
7733 | ; otherwise reload, given m->f, will try to pick f->f and reload it, | |
409f61cd | 7734 | ; which doesn't make progress. Likewise r->Y must be before r->r. |
a9baceb1 | 7735 | (define_insn_and_split "*movtf_internal" |
409f61cd AM |
7736 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r") |
7737 | (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))] | |
39e63627 GK |
7738 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7739 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
06f4e019 DE |
7740 | && (gpc_reg_operand (operands[0], TFmode) |
7741 | || gpc_reg_operand (operands[1], TFmode))" | |
a9baceb1 | 7742 | "#" |
ecb62ae7 | 7743 | "&& reload_completed" |
a9baceb1 GK |
7744 | [(pc)] |
7745 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } | |
112ccb83 | 7746 | [(set_attr "length" "8,8,8,20,20,16")]) |
06f4e019 | 7747 | |
ecb62ae7 GK |
7748 | (define_expand "extenddftf2" |
7749 | [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
7750 | (float_extend:TF (match_operand:DF 1 "input_operand" ""))) | |
7751 | (use (match_dup 2))])] | |
39e63627 GK |
7752 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7753 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 7754 | { |
ecb62ae7 GK |
7755 | operands[2] = CONST0_RTX (DFmode); |
7756 | }) | |
06f4e019 | 7757 | |
ecb62ae7 GK |
7758 | (define_insn_and_split "*extenddftf2_internal" |
7759 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r") | |
7760 | (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF"))) | |
97c54d9a | 7761 | (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))] |
39e63627 GK |
7762 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7763 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 GK |
7764 | "#" |
7765 | "&& reload_completed" | |
7766 | [(pc)] | |
06f4e019 | 7767 | { |
ecb62ae7 GK |
7768 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; |
7769 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); | |
7770 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word), | |
7771 | operands[1]); | |
7772 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word), | |
7773 | operands[2]); | |
7774 | DONE; | |
6ae08853 | 7775 | }) |
ecb62ae7 GK |
7776 | |
7777 | (define_expand "extendsftf2" | |
7778 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
7779 | (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
7780 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
7781 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
7782 | { | |
7783 | rtx tmp = gen_reg_rtx (DFmode); | |
7784 | emit_insn (gen_extendsfdf2 (tmp, operands[1])); | |
7785 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
7786 | DONE; | |
7787 | }) | |
06f4e019 | 7788 | |
8cb320b8 | 7789 | (define_expand "trunctfdf2" |
589b3fda DE |
7790 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
7791 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))] | |
39e63627 GK |
7792 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7793 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
589b3fda | 7794 | "") |
8cb320b8 DE |
7795 | |
7796 | (define_insn_and_split "trunctfdf2_internal1" | |
7797 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f") | |
7798 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))] | |
7799 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT | |
7800 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
7801 | "@ | |
7802 | # | |
7803 | fmr %0,%1" | |
7804 | "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" | |
7805 | [(const_int 0)] | |
7806 | { | |
7807 | emit_note (NOTE_INSN_DELETED); | |
7808 | DONE; | |
7809 | } | |
7810 | [(set_attr "type" "fp")]) | |
7811 | ||
7812 | (define_insn "trunctfdf2_internal2" | |
7813 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
7814 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
7815 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT | |
7816 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 7817 | "fadd %0,%1,%L1" |
8cb320b8 | 7818 | [(set_attr "type" "fp")]) |
06f4e019 DE |
7819 | |
7820 | (define_insn_and_split "trunctfsf2" | |
7821 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
ea112fc4 DE |
7822 | (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) |
7823 | (clobber (match_scratch:DF 2 "=f"))] | |
39e63627 GK |
7824 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7825 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 7826 | "#" |
ea112fc4 | 7827 | "&& reload_completed" |
06f4e019 DE |
7828 | [(set (match_dup 2) |
7829 | (float_truncate:DF (match_dup 1))) | |
7830 | (set (match_dup 0) | |
7831 | (float_truncate:SF (match_dup 2)))] | |
ea112fc4 | 7832 | "") |
06f4e019 | 7833 | |
0c90aa3c | 7834 | (define_expand "floatsitf2" |
ea112fc4 | 7835 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
0c90aa3c | 7836 | (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))] |
39e63627 GK |
7837 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7838 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
0c90aa3c GK |
7839 | { |
7840 | rtx tmp = gen_reg_rtx (DFmode); | |
7841 | expand_float (tmp, operands[1], false); | |
7842 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
7843 | DONE; | |
7844 | }) | |
06f4e019 | 7845 | |
ecb62ae7 GK |
7846 | ; fadd, but rounding towards zero. |
7847 | ; This is probably not the optimal code sequence. | |
7848 | (define_insn "fix_trunc_helper" | |
7849 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
7850 | (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")] | |
7851 | UNSPEC_FIX_TRUNC_TF)) | |
7852 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))] | |
7853 | "TARGET_HARD_FLOAT && TARGET_FPRS" | |
7854 | "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" | |
7855 | [(set_attr "type" "fp") | |
7856 | (set_attr "length" "20")]) | |
7857 | ||
0c90aa3c | 7858 | (define_expand "fix_trunctfsi2" |
ecb62ae7 GK |
7859 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7860 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" ""))) | |
7861 | (clobber (match_dup 2)) | |
7862 | (clobber (match_dup 3)) | |
7863 | (clobber (match_dup 4)) | |
7864 | (clobber (match_dup 5))])] | |
7865 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
7866 | && (TARGET_POWER2 || TARGET_POWERPC) | |
7867 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
7868 | { | |
7869 | operands[2] = gen_reg_rtx (DFmode); | |
7870 | operands[3] = gen_reg_rtx (DFmode); | |
7871 | operands[4] = gen_reg_rtx (DImode); | |
7872 | operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
7873 | }) | |
7874 | ||
7875 | (define_insn_and_split "*fix_trunctfsi2_internal" | |
61c07d3c | 7876 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ecb62ae7 GK |
7877 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) |
7878 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=f")) | |
7879 | (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f")) | |
7880 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f")) | |
7881 | (clobber (match_operand:DI 5 "memory_operand" "=o"))] | |
39e63627 GK |
7882 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7883 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 | 7884 | "#" |
230215f5 | 7885 | "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))" |
ecb62ae7 | 7886 | [(pc)] |
0c90aa3c | 7887 | { |
ecb62ae7 GK |
7888 | rtx lowword; |
7889 | emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3])); | |
7890 | ||
230215f5 GK |
7891 | gcc_assert (MEM_P (operands[5])); |
7892 | lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0); | |
ecb62ae7 GK |
7893 | |
7894 | emit_insn (gen_fctiwz (operands[4], operands[2])); | |
7895 | emit_move_insn (operands[5], operands[4]); | |
230215f5 | 7896 | emit_move_insn (operands[0], lowword); |
0c90aa3c GK |
7897 | DONE; |
7898 | }) | |
06f4e019 DE |
7899 | |
7900 | (define_insn "negtf2" | |
7901 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
7902 | (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
7903 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7904 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
7905 | "* |
7906 | { | |
7907 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
7908 | return \"fneg %L0,%L1\;fneg %0,%1\"; | |
7909 | else | |
7910 | return \"fneg %0,%1\;fneg %L0,%L1\"; | |
7911 | }" | |
7912 | [(set_attr "type" "fp") | |
7913 | (set_attr "length" "8")]) | |
7914 | ||
1a402dc1 | 7915 | (define_expand "abstf2" |
06f4e019 DE |
7916 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
7917 | (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
7918 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7919 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 7920 | " |
06f4e019 | 7921 | { |
1a402dc1 AM |
7922 | rtx label = gen_label_rtx (); |
7923 | emit_insn (gen_abstf2_internal (operands[0], operands[1], label)); | |
7924 | emit_label (label); | |
7925 | DONE; | |
7926 | }") | |
06f4e019 | 7927 | |
1a402dc1 | 7928 | (define_expand "abstf2_internal" |
06f4e019 | 7929 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
1a402dc1 AM |
7930 | (match_operand:TF 1 "gpc_reg_operand" "f")) |
7931 | (set (match_dup 3) (match_dup 5)) | |
7932 | (set (match_dup 5) (abs:DF (match_dup 5))) | |
7933 | (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5))) | |
7934 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
7935 | (label_ref (match_operand 2 "" "")) | |
7936 | (pc))) | |
7937 | (set (match_dup 6) (neg:DF (match_dup 6)))] | |
39e63627 GK |
7938 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7939 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 7940 | " |
06f4e019 | 7941 | { |
1a402dc1 AM |
7942 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); |
7943 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; | |
7944 | operands[3] = gen_reg_rtx (DFmode); | |
7945 | operands[4] = gen_reg_rtx (CCFPmode); | |
7946 | operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); | |
7947 | operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); | |
7948 | }") | |
06f4e019 | 7949 | \f |
1fd4e8c1 RK |
7950 | ;; Next come the multi-word integer load and store and the load and store |
7951 | ;; multiple insns. | |
1fd4e8c1 | 7952 | |
112ccb83 GK |
7953 | ; List r->r after r->"o<>", otherwise reload will try to reload a |
7954 | ; non-offsettable address by using r->r which won't make progress. | |
acad7ed3 | 7955 | (define_insn "*movdi_internal32" |
343f6bbf | 7956 | [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r") |
112ccb83 | 7957 | (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))] |
a260abc9 | 7958 | "! TARGET_POWERPC64 |
4e74d8ec MM |
7959 | && (gpc_reg_operand (operands[0], DImode) |
7960 | || gpc_reg_operand (operands[1], DImode))" | |
112ccb83 GK |
7961 | "@ |
7962 | # | |
7963 | # | |
7964 | # | |
7965 | fmr %0,%1 | |
7966 | lfd%U1%X1 %0,%1 | |
7967 | stfd%U0%X0 %1,%0 | |
7968 | #" | |
7969 | [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")]) | |
4e74d8ec MM |
7970 | |
7971 | (define_split | |
7972 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7973 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 7974 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
7975 | [(set (match_dup 2) (match_dup 4)) |
7976 | (set (match_dup 3) (match_dup 1))] | |
7977 | " | |
7978 | { | |
5f59ecb7 | 7979 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
7980 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
7981 | DImode); | |
7982 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
7983 | DImode); | |
75d39459 | 7984 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 7985 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 7986 | #else |
5f59ecb7 | 7987 | operands[4] = GEN_INT (value >> 32); |
a65c591c | 7988 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
75d39459 | 7989 | #endif |
4e74d8ec MM |
7990 | }") |
7991 | ||
3a1f863f DE |
7992 | (define_split |
7993 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
7994 | (match_operand:DI 1 "input_operand" ""))] | |
6ae08853 | 7995 | "reload_completed && !TARGET_POWERPC64 |
3a1f863f | 7996 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
7997 | [(pc)] |
7998 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
3a1f863f | 7999 | |
acad7ed3 | 8000 | (define_insn "*movdi_internal64" |
343f6bbf | 8001 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h") |
9615f239 | 8002 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 8003 | "TARGET_POWERPC64 |
4e74d8ec MM |
8004 | && (gpc_reg_operand (operands[0], DImode) |
8005 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 8006 | "@ |
3d5570cb RK |
8007 | mr %0,%1 |
8008 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8009 | std%U0%X0 %1,%0 |
3d5570cb | 8010 | li %0,%1 |
802a0058 | 8011 | lis %0,%v1 |
e6ca2c17 | 8012 | # |
aee86b38 | 8013 | {cal|la} %0,%a1 |
3d5570cb RK |
8014 | fmr %0,%1 |
8015 | lfd%U1%X1 %0,%1 | |
8016 | stfd%U0%X0 %1,%0 | |
8017 | mf%1 %0 | |
08075ead | 8018 | mt%0 %1 |
e34eaae5 | 8019 | {cror 0,0,0|nop}" |
02ca7595 | 8020 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*") |
e6ca2c17 DE |
8021 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
8022 | ||
5f59ecb7 | 8023 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
8024 | (define_insn "" |
8025 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8026 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
8027 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8028 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
8029 | && num_insns_constant (operands[1], DImode) == 1" |
8030 | "* | |
8031 | { | |
8032 | return ((unsigned HOST_WIDE_INT) | |
8033 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
8034 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
8035 | }") | |
8036 | ||
a260abc9 DE |
8037 | ;; Generate all one-bits and clear left or right. |
8038 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8039 | (define_split | |
8040 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1990cd79 | 8041 | (match_operand:DI 1 "mask64_operand" ""))] |
a260abc9 DE |
8042 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" |
8043 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8044 | (set (match_dup 0) |
a260abc9 DE |
8045 | (and:DI (rotate:DI (match_dup 0) |
8046 | (const_int 0)) | |
8047 | (match_dup 1)))] | |
8048 | "") | |
8049 | ||
8050 | ;; Split a load of a large constant into the appropriate five-instruction | |
8051 | ;; sequence. Handle anything in a constant number of insns. | |
8052 | ;; When non-easy constants can go in the TOC, this should use | |
8053 | ;; easy_fp_constant predicate. | |
8054 | (define_split | |
8055 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8056 | (match_operand:DI 1 "const_int_operand" ""))] |
8057 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8058 | [(set (match_dup 0) (match_dup 2)) | |
8059 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
e6ca2c17 | 8060 | " |
2bfcf297 DB |
8061 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8062 | ||
8063 | if (tem == operands[0]) | |
8064 | DONE; | |
e8d791dd | 8065 | else |
2bfcf297 | 8066 | FAIL; |
5f59ecb7 | 8067 | }") |
e6ca2c17 | 8068 | |
5f59ecb7 DE |
8069 | (define_split |
8070 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8071 | (match_operand:DI 1 "const_double_operand" ""))] |
8072 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8073 | [(set (match_dup 0) (match_dup 2)) | |
8074 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
5f59ecb7 | 8075 | " |
2bfcf297 DB |
8076 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8077 | ||
8078 | if (tem == operands[0]) | |
8079 | DONE; | |
8080 | else | |
8081 | FAIL; | |
e6ca2c17 | 8082 | }") |
acad7ed3 | 8083 | \f |
1fd4e8c1 RK |
8084 | ;; TImode is similar, except that we usually want to compute the address into |
8085 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8086 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8087 | |
8088 | ;; We say that MQ is clobbered in the last alternative because the first | |
8089 | ;; alternative would never get used otherwise since it would need a reload | |
8090 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8091 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8092 | ;; giving the SCRATCH mq. | |
3a1f863f | 8093 | |
a260abc9 | 8094 | (define_insn "*movti_power" |
7f514158 AM |
8095 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r") |
8096 | (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n")) | |
8097 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))] | |
6ae08853 | 8098 | "TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8099 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8100 | "* |
8101 | { | |
8102 | switch (which_alternative) | |
8103 | { | |
dc4f83ca | 8104 | default: |
37409796 | 8105 | gcc_unreachable (); |
dc4f83ca | 8106 | |
1fd4e8c1 | 8107 | case 0: |
3a1f863f DE |
8108 | if (TARGET_STRING) |
8109 | return \"{stsi|stswi} %1,%P0,16\"; | |
1fd4e8c1 | 8110 | case 1: |
1fd4e8c1 | 8111 | case 2: |
3a1f863f | 8112 | return \"#\"; |
1fd4e8c1 RK |
8113 | case 3: |
8114 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8115 | fall through to generating four loads. */ | |
e876481c DE |
8116 | if (TARGET_STRING |
8117 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8118 | return \"{lsi|lswi} %0,%P1,16\"; |
82e41834 | 8119 | /* ... fall through ... */ |
1fd4e8c1 | 8120 | case 4: |
7f514158 | 8121 | case 5: |
3a1f863f | 8122 | return \"#\"; |
1fd4e8c1 RK |
8123 | } |
8124 | }" | |
7f514158 | 8125 | [(set_attr "type" "store,store,*,load,load,*")]) |
51b8fc2c | 8126 | |
a260abc9 | 8127 | (define_insn "*movti_string" |
7f514158 AM |
8128 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r") |
8129 | (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))] | |
3a1f863f | 8130 | "! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8131 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8132 | "* | |
8133 | { | |
8134 | switch (which_alternative) | |
8135 | { | |
8136 | default: | |
37409796 | 8137 | gcc_unreachable (); |
dc4f83ca | 8138 | case 0: |
3a1f863f DE |
8139 | if (TARGET_STRING) |
8140 | return \"{stsi|stswi} %1,%P0,16\"; | |
dc4f83ca | 8141 | case 1: |
cd1d3445 | 8142 | case 2: |
3a1f863f | 8143 | return \"#\"; |
cd1d3445 DE |
8144 | case 3: |
8145 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8146 | fall through to generating four loads. */ | |
6ae08853 | 8147 | if (TARGET_STRING |
3a1f863f | 8148 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) |
cd1d3445 DE |
8149 | return \"{lsi|lswi} %0,%P1,16\"; |
8150 | /* ... fall through ... */ | |
8151 | case 4: | |
7f514158 | 8152 | case 5: |
3a1f863f | 8153 | return \"#\"; |
dc4f83ca MM |
8154 | } |
8155 | }" | |
7f514158 | 8156 | [(set_attr "type" "store,store,*,load,load,*")]) |
dc4f83ca | 8157 | |
a260abc9 | 8158 | (define_insn "*movti_ppc64" |
112ccb83 GK |
8159 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r") |
8160 | (match_operand:TI 1 "input_operand" "r,r,m"))] | |
51b8fc2c RK |
8161 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) |
8162 | || gpc_reg_operand (operands[1], TImode))" | |
112ccb83 | 8163 | "#" |
3a1f863f DE |
8164 | [(set_attr "type" "*,load,store")]) |
8165 | ||
7f514158 AM |
8166 | (define_split |
8167 | [(set (match_operand:TI 0 "gpc_reg_operand" "") | |
8168 | (match_operand:TI 1 "const_double_operand" ""))] | |
8169 | "TARGET_POWERPC64" | |
8170 | [(set (match_dup 2) (match_dup 4)) | |
8171 | (set (match_dup 3) (match_dup 5))] | |
8172 | " | |
8173 | { | |
8174 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, | |
8175 | TImode); | |
8176 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8177 | TImode); | |
8178 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
8179 | { | |
8180 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
8181 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
8182 | } | |
8183 | else if (GET_CODE (operands[1]) == CONST_INT) | |
8184 | { | |
8185 | operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0)); | |
8186 | operands[5] = operands[1]; | |
8187 | } | |
8188 | else | |
8189 | FAIL; | |
8190 | }") | |
8191 | ||
3a1f863f DE |
8192 | (define_split |
8193 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
8194 | (match_operand:TI 1 "input_operand" ""))] | |
a9baceb1 | 8195 | "reload_completed |
3a1f863f | 8196 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
8197 | [(pc)] |
8198 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
1fd4e8c1 RK |
8199 | \f |
8200 | (define_expand "load_multiple" | |
2f622005 RK |
8201 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8202 | (match_operand:SI 1 "" "")) | |
8203 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8204 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8205 | " |
8206 | { | |
8207 | int regno; | |
8208 | int count; | |
792760b9 | 8209 | rtx op1; |
1fd4e8c1 RK |
8210 | int i; |
8211 | ||
8212 | /* Support only loading a constant number of fixed-point registers from | |
8213 | memory and only bother with this if more than two; the machine | |
8214 | doesn't support more than eight. */ | |
8215 | if (GET_CODE (operands[2]) != CONST_INT | |
8216 | || INTVAL (operands[2]) <= 2 | |
8217 | || INTVAL (operands[2]) > 8 | |
8218 | || GET_CODE (operands[1]) != MEM | |
8219 | || GET_CODE (operands[0]) != REG | |
8220 | || REGNO (operands[0]) >= 32) | |
8221 | FAIL; | |
8222 | ||
8223 | count = INTVAL (operands[2]); | |
8224 | regno = REGNO (operands[0]); | |
8225 | ||
39403d82 | 8226 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
8227 | op1 = replace_equiv_address (operands[1], |
8228 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
8229 | |
8230 | for (i = 0; i < count; i++) | |
8231 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8232 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
7ef788f0 | 8233 | adjust_address_nv (op1, SImode, i * 4)); |
1fd4e8c1 RK |
8234 | }") |
8235 | ||
9caa3eb2 | 8236 | (define_insn "*ldmsi8" |
1fd4e8c1 | 8237 | [(match_parallel 0 "load_multiple_operation" |
9caa3eb2 DE |
8238 | [(set (match_operand:SI 2 "gpc_reg_operand" "") |
8239 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8240 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8241 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8242 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8243 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8244 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8245 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8246 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8247 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8248 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8249 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8250 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8251 | (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
8252 | (set (match_operand:SI 9 "gpc_reg_operand" "") | |
8253 | (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] | |
8254 | "TARGET_STRING && XVECLEN (operands[0], 0) == 8" | |
1fd4e8c1 | 8255 | "* |
9caa3eb2 DE |
8256 | { return rs6000_output_load_multiple (operands); }" |
8257 | [(set_attr "type" "load") | |
8258 | (set_attr "length" "32")]) | |
1fd4e8c1 | 8259 | |
9caa3eb2 DE |
8260 | (define_insn "*ldmsi7" |
8261 | [(match_parallel 0 "load_multiple_operation" | |
8262 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8263 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8264 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8265 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8266 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8267 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8268 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8269 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8270 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8271 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8272 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8273 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8274 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8275 | (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] | |
8276 | "TARGET_STRING && XVECLEN (operands[0], 0) == 7" | |
8277 | "* | |
8278 | { return rs6000_output_load_multiple (operands); }" | |
8279 | [(set_attr "type" "load") | |
8280 | (set_attr "length" "32")]) | |
8281 | ||
8282 | (define_insn "*ldmsi6" | |
8283 | [(match_parallel 0 "load_multiple_operation" | |
8284 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8285 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8286 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8287 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8288 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8289 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8290 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8291 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8292 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8293 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8294 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8295 | (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] | |
8296 | "TARGET_STRING && XVECLEN (operands[0], 0) == 6" | |
8297 | "* | |
8298 | { return rs6000_output_load_multiple (operands); }" | |
8299 | [(set_attr "type" "load") | |
8300 | (set_attr "length" "32")]) | |
8301 | ||
8302 | (define_insn "*ldmsi5" | |
8303 | [(match_parallel 0 "load_multiple_operation" | |
8304 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8305 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8306 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8307 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8308 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8309 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8310 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8311 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8312 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8313 | (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] | |
8314 | "TARGET_STRING && XVECLEN (operands[0], 0) == 5" | |
8315 | "* | |
8316 | { return rs6000_output_load_multiple (operands); }" | |
8317 | [(set_attr "type" "load") | |
8318 | (set_attr "length" "32")]) | |
8319 | ||
8320 | (define_insn "*ldmsi4" | |
8321 | [(match_parallel 0 "load_multiple_operation" | |
8322 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8323 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8324 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8325 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8326 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8327 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8328 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8329 | (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] | |
8330 | "TARGET_STRING && XVECLEN (operands[0], 0) == 4" | |
8331 | "* | |
8332 | { return rs6000_output_load_multiple (operands); }" | |
8333 | [(set_attr "type" "load") | |
8334 | (set_attr "length" "32")]) | |
8335 | ||
8336 | (define_insn "*ldmsi3" | |
8337 | [(match_parallel 0 "load_multiple_operation" | |
8338 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8339 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8340 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8341 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8342 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8343 | (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] | |
8344 | "TARGET_STRING && XVECLEN (operands[0], 0) == 3" | |
8345 | "* | |
8346 | { return rs6000_output_load_multiple (operands); }" | |
b19003d8 | 8347 | [(set_attr "type" "load") |
e82ee4cc | 8348 | (set_attr "length" "32")]) |
b19003d8 | 8349 | |
1fd4e8c1 | 8350 | (define_expand "store_multiple" |
2f622005 RK |
8351 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8352 | (match_operand:SI 1 "" "")) | |
8353 | (clobber (scratch:SI)) | |
8354 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8355 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8356 | " |
8357 | { | |
8358 | int regno; | |
8359 | int count; | |
8360 | rtx to; | |
792760b9 | 8361 | rtx op0; |
1fd4e8c1 RK |
8362 | int i; |
8363 | ||
8364 | /* Support only storing a constant number of fixed-point registers to | |
8365 | memory and only bother with this if more than two; the machine | |
8366 | doesn't support more than eight. */ | |
8367 | if (GET_CODE (operands[2]) != CONST_INT | |
8368 | || INTVAL (operands[2]) <= 2 | |
8369 | || INTVAL (operands[2]) > 8 | |
8370 | || GET_CODE (operands[0]) != MEM | |
8371 | || GET_CODE (operands[1]) != REG | |
8372 | || REGNO (operands[1]) >= 32) | |
8373 | FAIL; | |
8374 | ||
8375 | count = INTVAL (operands[2]); | |
8376 | regno = REGNO (operands[1]); | |
8377 | ||
39403d82 | 8378 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 8379 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 8380 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
8381 | |
8382 | XVECEXP (operands[3], 0, 0) | |
7ef788f0 | 8383 | = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]); |
39403d82 | 8384 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8385 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8386 | |
8387 | for (i = 1; i < count; i++) | |
8388 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8389 | = gen_rtx_SET (VOIDmode, |
7ef788f0 | 8390 | adjust_address_nv (op0, SImode, i * 4), |
c5c76735 | 8391 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
8392 | }") |
8393 | ||
9caa3eb2 | 8394 | (define_insn "*store_multiple_power" |
1fd4e8c1 RK |
8395 | [(match_parallel 0 "store_multiple_operation" |
8396 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 8397 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 8398 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 8399 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
8400 | "{stsi|stswi} %2,%P1,%O0" |
8401 | [(set_attr "type" "store")]) | |
d14a6d05 | 8402 | |
e46e3130 | 8403 | (define_insn "*stmsi8" |
d14a6d05 | 8404 | [(match_parallel 0 "store_multiple_operation" |
e46e3130 DJ |
8405 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
8406 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8407 | (clobber (match_scratch:SI 3 "X")) | |
8408 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8409 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8410 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8411 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8412 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8413 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8414 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8415 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8416 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8417 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
8418 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
8419 | (match_operand:SI 9 "gpc_reg_operand" "r")) | |
8420 | (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
8421 | (match_operand:SI 10 "gpc_reg_operand" "r"))])] | |
8422 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9" | |
8423 | "{stsi|stswi} %2,%1,%O0" | |
8424 | [(set_attr "type" "store")]) | |
8425 | ||
8426 | (define_insn "*stmsi7" | |
8427 | [(match_parallel 0 "store_multiple_operation" | |
8428 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8429 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8430 | (clobber (match_scratch:SI 3 "X")) | |
8431 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8432 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8433 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8434 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8435 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8436 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8437 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8438 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8439 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8440 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
8441 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
8442 | (match_operand:SI 9 "gpc_reg_operand" "r"))])] | |
8443 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8" | |
8444 | "{stsi|stswi} %2,%1,%O0" | |
8445 | [(set_attr "type" "store")]) | |
8446 | ||
8447 | (define_insn "*stmsi6" | |
8448 | [(match_parallel 0 "store_multiple_operation" | |
8449 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8450 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8451 | (clobber (match_scratch:SI 3 "X")) | |
8452 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8453 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8454 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8455 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8456 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8457 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8458 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8459 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8460 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8461 | (match_operand:SI 8 "gpc_reg_operand" "r"))])] | |
8462 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7" | |
8463 | "{stsi|stswi} %2,%1,%O0" | |
8464 | [(set_attr "type" "store")]) | |
8465 | ||
8466 | (define_insn "*stmsi5" | |
8467 | [(match_parallel 0 "store_multiple_operation" | |
8468 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8469 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8470 | (clobber (match_scratch:SI 3 "X")) | |
8471 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8472 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8473 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8474 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8475 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8476 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8477 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8478 | (match_operand:SI 7 "gpc_reg_operand" "r"))])] | |
8479 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6" | |
8480 | "{stsi|stswi} %2,%1,%O0" | |
8481 | [(set_attr "type" "store")]) | |
8482 | ||
8483 | (define_insn "*stmsi4" | |
8484 | [(match_parallel 0 "store_multiple_operation" | |
8485 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8486 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8487 | (clobber (match_scratch:SI 3 "X")) | |
8488 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8489 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8490 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8491 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8492 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8493 | (match_operand:SI 6 "gpc_reg_operand" "r"))])] | |
8494 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5" | |
b7ff3d82 DE |
8495 | "{stsi|stswi} %2,%1,%O0" |
8496 | [(set_attr "type" "store")]) | |
7e69e155 | 8497 | |
e46e3130 DJ |
8498 | (define_insn "*stmsi3" |
8499 | [(match_parallel 0 "store_multiple_operation" | |
8500 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8501 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8502 | (clobber (match_scratch:SI 3 "X")) | |
8503 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8504 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8505 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8506 | (match_operand:SI 5 "gpc_reg_operand" "r"))])] | |
8507 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4" | |
8508 | "{stsi|stswi} %2,%1,%O0" | |
8509 | [(set_attr "type" "store")]) | |
7e69e155 | 8510 | \f |
57e84f18 | 8511 | (define_expand "setmemsi" |
fba73eb1 | 8512 | [(parallel [(set (match_operand:BLK 0 "" "") |
98843c92 | 8513 | (match_operand 2 "const_int_operand" "")) |
fba73eb1 | 8514 | (use (match_operand:SI 1 "" "")) |
57e84f18 | 8515 | (use (match_operand:SI 3 "" ""))])] |
fba73eb1 DE |
8516 | "" |
8517 | " | |
8518 | { | |
57e84f18 | 8519 | /* If value to set is not zero, use the library routine. */ |
a05be2e0 | 8520 | if (operands[2] != const0_rtx) |
57e84f18 AS |
8521 | FAIL; |
8522 | ||
fba73eb1 DE |
8523 | if (expand_block_clear (operands)) |
8524 | DONE; | |
8525 | else | |
8526 | FAIL; | |
8527 | }") | |
8528 | ||
7e69e155 MM |
8529 | ;; String/block move insn. |
8530 | ;; Argument 0 is the destination | |
8531 | ;; Argument 1 is the source | |
8532 | ;; Argument 2 is the length | |
8533 | ;; Argument 3 is the alignment | |
8534 | ||
70128ad9 | 8535 | (define_expand "movmemsi" |
b6c9286a MM |
8536 | [(parallel [(set (match_operand:BLK 0 "" "") |
8537 | (match_operand:BLK 1 "" "")) | |
8538 | (use (match_operand:SI 2 "" "")) | |
8539 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
8540 | "" |
8541 | " | |
8542 | { | |
8543 | if (expand_block_move (operands)) | |
8544 | DONE; | |
8545 | else | |
8546 | FAIL; | |
8547 | }") | |
8548 | ||
8549 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8550 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
8551 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 8552 | (define_expand "movmemsi_8reg" |
b6c9286a MM |
8553 | [(parallel [(set (match_operand 0 "" "") |
8554 | (match_operand 1 "" "")) | |
8555 | (use (match_operand 2 "" "")) | |
8556 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
8557 | (clobber (reg:SI 5)) |
8558 | (clobber (reg:SI 6)) | |
8559 | (clobber (reg:SI 7)) | |
8560 | (clobber (reg:SI 8)) | |
8561 | (clobber (reg:SI 9)) | |
8562 | (clobber (reg:SI 10)) | |
8563 | (clobber (reg:SI 11)) | |
8564 | (clobber (reg:SI 12)) | |
3c67b673 | 8565 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8566 | "TARGET_STRING" |
8567 | "") | |
8568 | ||
8569 | (define_insn "" | |
52d3af72 DE |
8570 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8571 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8572 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8573 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8574 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8575 | (clobber (reg:SI 6)) |
8576 | (clobber (reg:SI 7)) | |
8577 | (clobber (reg:SI 8)) | |
8578 | (clobber (reg:SI 9)) | |
8579 | (clobber (reg:SI 10)) | |
8580 | (clobber (reg:SI 11)) | |
8581 | (clobber (reg:SI 12)) | |
3c67b673 | 8582 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 8583 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
8584 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8585 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8586 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8587 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8588 | && REGNO (operands[4]) == 5" |
8589 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8590 | [(set_attr "type" "load") |
8591 | (set_attr "length" "8")]) | |
7e69e155 MM |
8592 | |
8593 | (define_insn "" | |
4ae234b0 GK |
8594 | [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) |
8595 | (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8596 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8597 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8598 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8599 | (clobber (reg:SI 6)) |
8600 | (clobber (reg:SI 7)) | |
8601 | (clobber (reg:SI 8)) | |
8602 | (clobber (reg:SI 9)) | |
8603 | (clobber (reg:SI 10)) | |
8604 | (clobber (reg:SI 11)) | |
8605 | (clobber (reg:SI 12)) | |
3c67b673 | 8606 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8607 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
8608 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8609 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8610 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8611 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8612 | && REGNO (operands[4]) == 5" |
8613 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8614 | [(set_attr "type" "load") |
8615 | (set_attr "length" "8")]) | |
7e69e155 MM |
8616 | |
8617 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8618 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
8619 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 8620 | (define_expand "movmemsi_6reg" |
b6c9286a MM |
8621 | [(parallel [(set (match_operand 0 "" "") |
8622 | (match_operand 1 "" "")) | |
8623 | (use (match_operand 2 "" "")) | |
8624 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
8625 | (clobber (reg:SI 5)) |
8626 | (clobber (reg:SI 6)) | |
7e69e155 MM |
8627 | (clobber (reg:SI 7)) |
8628 | (clobber (reg:SI 8)) | |
8629 | (clobber (reg:SI 9)) | |
8630 | (clobber (reg:SI 10)) | |
3c67b673 | 8631 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8632 | "TARGET_STRING" |
8633 | "") | |
8634 | ||
8635 | (define_insn "" | |
52d3af72 DE |
8636 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8637 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8638 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8639 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8640 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8641 | (clobber (reg:SI 6)) |
8642 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8643 | (clobber (reg:SI 8)) |
8644 | (clobber (reg:SI 9)) | |
8645 | (clobber (reg:SI 10)) | |
3c67b673 | 8646 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
8647 | "TARGET_STRING && TARGET_POWER |
8648 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
8649 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8650 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8651 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8652 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8653 | [(set_attr "type" "load") |
8654 | (set_attr "length" "8")]) | |
7e69e155 MM |
8655 | |
8656 | (define_insn "" | |
4ae234b0 GK |
8657 | [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) |
8658 | (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8659 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8660 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8661 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8662 | (clobber (reg:SI 6)) |
8663 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8664 | (clobber (reg:SI 8)) |
8665 | (clobber (reg:SI 9)) | |
8666 | (clobber (reg:SI 10)) | |
3c67b673 | 8667 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8668 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8669 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
8670 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8671 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8672 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8673 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8674 | [(set_attr "type" "load") |
8675 | (set_attr "length" "8")]) | |
7e69e155 | 8676 | |
f9562f27 DE |
8677 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
8678 | ;; problems with TImode. | |
8679 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 8680 | (define_expand "movmemsi_4reg" |
b6c9286a MM |
8681 | [(parallel [(set (match_operand 0 "" "") |
8682 | (match_operand 1 "" "")) | |
8683 | (use (match_operand 2 "" "")) | |
8684 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
8685 | (clobber (reg:SI 5)) |
8686 | (clobber (reg:SI 6)) | |
8687 | (clobber (reg:SI 7)) | |
8688 | (clobber (reg:SI 8)) | |
3c67b673 | 8689 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8690 | "TARGET_STRING" |
8691 | "") | |
8692 | ||
8693 | (define_insn "" | |
52d3af72 DE |
8694 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8695 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8696 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8697 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8698 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8699 | (clobber (reg:SI 6)) |
8700 | (clobber (reg:SI 7)) | |
8701 | (clobber (reg:SI 8)) | |
3c67b673 | 8702 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
8703 | "TARGET_STRING && TARGET_POWER |
8704 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
8705 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
8706 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
8707 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8708 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8709 | [(set_attr "type" "load") |
8710 | (set_attr "length" "8")]) | |
7e69e155 MM |
8711 | |
8712 | (define_insn "" | |
4ae234b0 GK |
8713 | [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) |
8714 | (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8715 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8716 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8717 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8718 | (clobber (reg:SI 6)) |
8719 | (clobber (reg:SI 7)) | |
8720 | (clobber (reg:SI 8)) | |
3c67b673 | 8721 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8722 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8723 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
8724 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
8725 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
8726 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8727 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8728 | [(set_attr "type" "load") |
8729 | (set_attr "length" "8")]) | |
7e69e155 MM |
8730 | |
8731 | ;; Move up to 8 bytes at a time. | |
70128ad9 | 8732 | (define_expand "movmemsi_2reg" |
b6c9286a MM |
8733 | [(parallel [(set (match_operand 0 "" "") |
8734 | (match_operand 1 "" "")) | |
8735 | (use (match_operand 2 "" "")) | |
8736 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
8737 | (clobber (match_scratch:DI 4 "")) |
8738 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 8739 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
8740 | "") |
8741 | ||
8742 | (define_insn "" | |
52d3af72 DE |
8743 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8744 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8745 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8746 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8747 | (clobber (match_scratch:DI 4 "=&r")) | |
8748 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 8749 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
8750 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
8751 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8752 | [(set_attr "type" "load") |
8753 | (set_attr "length" "8")]) | |
7e69e155 MM |
8754 | |
8755 | (define_insn "" | |
52d3af72 DE |
8756 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8757 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8758 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8759 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8760 | (clobber (match_scratch:DI 4 "=&r")) | |
8761 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 8762 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 8763 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 8764 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8765 | [(set_attr "type" "load") |
8766 | (set_attr "length" "8")]) | |
7e69e155 MM |
8767 | |
8768 | ;; Move up to 4 bytes at a time. | |
70128ad9 | 8769 | (define_expand "movmemsi_1reg" |
b6c9286a MM |
8770 | [(parallel [(set (match_operand 0 "" "") |
8771 | (match_operand 1 "" "")) | |
8772 | (use (match_operand 2 "" "")) | |
8773 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
8774 | (clobber (match_scratch:SI 4 "")) |
8775 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
8776 | "TARGET_STRING" |
8777 | "") | |
8778 | ||
8779 | (define_insn "" | |
52d3af72 DE |
8780 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8781 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8782 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8783 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8784 | (clobber (match_scratch:SI 4 "=&r")) | |
8785 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
8786 | "TARGET_STRING && TARGET_POWER |
8787 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 8788 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8789 | [(set_attr "type" "load") |
8790 | (set_attr "length" "8")]) | |
7e69e155 MM |
8791 | |
8792 | (define_insn "" | |
4ae234b0 GK |
8793 | [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) |
8794 | (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8795 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8796 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8797 | (clobber (match_scratch:SI 4 "=&r")) | |
8798 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 8799 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8800 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
09a625f7 TR |
8801 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
8802 | [(set_attr "type" "load") | |
8803 | (set_attr "length" "8")]) | |
1fd4e8c1 | 8804 | \f |
7e69e155 | 8805 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
8806 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
8807 | ;; do cases where the increment is not the size of the object. | |
8808 | ;; | |
8809 | ;; In all these cases, we use operands 0 and 1 for the register being | |
8810 | ;; incremented because those are the operands that local-alloc will | |
8811 | ;; tie and these are the pair most likely to be tieable (and the ones | |
8812 | ;; that will benefit the most). | |
8813 | ||
38c1f2d7 | 8814 | (define_insn "*movdi_update1" |
51b8fc2c | 8815 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 8816 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 8817 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) |
51b8fc2c RK |
8818 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") |
8819 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 8820 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
8821 | "@ |
8822 | ldux %3,%0,%2 | |
8823 | ldu %3,%2(%0)" | |
b54cf83a | 8824 | [(set_attr "type" "load_ux,load_u")]) |
287f13ff | 8825 | |
2e6c9641 FJ |
8826 | (define_insn "movdi_<mode>_update" |
8827 | [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") | |
8828 | (match_operand:P 2 "reg_or_aligned_short_operand" "r,I"))) | |
51b8fc2c | 8829 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) |
2e6c9641 FJ |
8830 | (set (match_operand:P 0 "gpc_reg_operand" "=b,b") |
8831 | (plus:P (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 8832 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
8833 | "@ |
8834 | stdux %3,%0,%2 | |
b7ff3d82 | 8835 | stdu %3,%2(%0)" |
b54cf83a | 8836 | [(set_attr "type" "store_ux,store_u")]) |
51b8fc2c | 8837 | |
38c1f2d7 | 8838 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
8839 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
8840 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8841 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8842 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8843 | (plus:SI (match_dup 1) (match_dup 2)))] |
f7b3ab8a | 8844 | "TARGET_UPDATE" |
1fd4e8c1 | 8845 | "@ |
ca7f5001 RK |
8846 | {lux|lwzux} %3,%0,%2 |
8847 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a DE |
8848 | [(set_attr "type" "load_ux,load_u")]) |
8849 | ||
8850 | (define_insn "*movsi_update2" | |
8851 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
8852 | (sign_extend:DI | |
8853 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
8854 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
8855 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
8856 | (plus:DI (match_dup 1) (match_dup 2)))] | |
8857 | "TARGET_POWERPC64" | |
8858 | "lwaux %3,%0,%2" | |
8859 | [(set_attr "type" "load_ext_ux")]) | |
1fd4e8c1 | 8860 | |
4697a36c | 8861 | (define_insn "movsi_update" |
cd2b37d9 | 8862 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8863 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8864 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
8865 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8866 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8867 | "TARGET_UPDATE" |
1fd4e8c1 | 8868 | "@ |
ca7f5001 | 8869 | {stux|stwux} %3,%0,%2 |
b7ff3d82 | 8870 | {stu|stwu} %3,%2(%0)" |
b54cf83a | 8871 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 8872 | |
b54cf83a | 8873 | (define_insn "*movhi_update1" |
cd2b37d9 RK |
8874 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
8875 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8876 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8877 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8878 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8879 | "TARGET_UPDATE" |
1fd4e8c1 | 8880 | "@ |
5f243543 RK |
8881 | lhzux %3,%0,%2 |
8882 | lhzu %3,%2(%0)" | |
b54cf83a | 8883 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 8884 | |
38c1f2d7 | 8885 | (define_insn "*movhi_update2" |
cd2b37d9 | 8886 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8887 | (zero_extend:SI |
cd2b37d9 | 8888 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8889 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8890 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8891 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8892 | "TARGET_UPDATE" |
1fd4e8c1 | 8893 | "@ |
5f243543 RK |
8894 | lhzux %3,%0,%2 |
8895 | lhzu %3,%2(%0)" | |
b54cf83a | 8896 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 8897 | |
38c1f2d7 | 8898 | (define_insn "*movhi_update3" |
cd2b37d9 | 8899 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8900 | (sign_extend:SI |
cd2b37d9 | 8901 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8902 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8903 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8904 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8905 | "TARGET_UPDATE" |
1fd4e8c1 | 8906 | "@ |
5f243543 RK |
8907 | lhaux %3,%0,%2 |
8908 | lhau %3,%2(%0)" | |
b54cf83a | 8909 | [(set_attr "type" "load_ext_ux,load_ext_u")]) |
1fd4e8c1 | 8910 | |
38c1f2d7 | 8911 | (define_insn "*movhi_update4" |
cd2b37d9 | 8912 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8913 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8914 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
8915 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8916 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8917 | "TARGET_UPDATE" |
1fd4e8c1 | 8918 | "@ |
5f243543 | 8919 | sthux %3,%0,%2 |
b7ff3d82 | 8920 | sthu %3,%2(%0)" |
b54cf83a | 8921 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 8922 | |
38c1f2d7 | 8923 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
8924 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
8925 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8926 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8927 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8928 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8929 | "TARGET_UPDATE" |
1fd4e8c1 | 8930 | "@ |
5f243543 RK |
8931 | lbzux %3,%0,%2 |
8932 | lbzu %3,%2(%0)" | |
b54cf83a | 8933 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 8934 | |
38c1f2d7 | 8935 | (define_insn "*movqi_update2" |
cd2b37d9 | 8936 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8937 | (zero_extend:SI |
cd2b37d9 | 8938 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8939 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8940 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8941 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8942 | "TARGET_UPDATE" |
1fd4e8c1 | 8943 | "@ |
5f243543 RK |
8944 | lbzux %3,%0,%2 |
8945 | lbzu %3,%2(%0)" | |
b54cf83a | 8946 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 8947 | |
38c1f2d7 | 8948 | (define_insn "*movqi_update3" |
cd2b37d9 | 8949 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8950 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8951 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
8952 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8953 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8954 | "TARGET_UPDATE" |
1fd4e8c1 | 8955 | "@ |
5f243543 | 8956 | stbux %3,%0,%2 |
b7ff3d82 | 8957 | stbu %3,%2(%0)" |
b54cf83a | 8958 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 8959 | |
38c1f2d7 | 8960 | (define_insn "*movsf_update1" |
cd2b37d9 | 8961 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 8962 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8963 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8964 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8965 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 8966 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 8967 | "@ |
5f243543 RK |
8968 | lfsux %3,%0,%2 |
8969 | lfsu %3,%2(%0)" | |
b54cf83a | 8970 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 8971 | |
38c1f2d7 | 8972 | (define_insn "*movsf_update2" |
cd2b37d9 | 8973 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8974 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8975 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
8976 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8977 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 8978 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 8979 | "@ |
85fff2f3 | 8980 | stfsux %3,%0,%2 |
b7ff3d82 | 8981 | stfsu %3,%2(%0)" |
b54cf83a | 8982 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
1fd4e8c1 | 8983 | |
38c1f2d7 MM |
8984 | (define_insn "*movsf_update3" |
8985 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
8986 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
8987 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
8988 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
8989 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 8990 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
8991 | "@ |
8992 | {lux|lwzux} %3,%0,%2 | |
8993 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a | 8994 | [(set_attr "type" "load_ux,load_u")]) |
38c1f2d7 MM |
8995 | |
8996 | (define_insn "*movsf_update4" | |
8997 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
8998 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
8999 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
9000 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9001 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9002 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9003 | "@ |
9004 | {stux|stwux} %3,%0,%2 | |
9005 | {stu|stwu} %3,%2(%0)" | |
b54cf83a | 9006 | [(set_attr "type" "store_ux,store_u")]) |
38c1f2d7 MM |
9007 | |
9008 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
9009 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
9010 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9011 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9012 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9013 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9014 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9015 | "@ |
5f243543 RK |
9016 | lfdux %3,%0,%2 |
9017 | lfdu %3,%2(%0)" | |
b54cf83a | 9018 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9019 | |
38c1f2d7 | 9020 | (define_insn "*movdf_update2" |
cd2b37d9 | 9021 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9022 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9023 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
9024 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9025 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9026 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9027 | "@ |
5f243543 | 9028 | stfdux %3,%0,%2 |
b7ff3d82 | 9029 | stfdu %3,%2(%0)" |
b54cf83a | 9030 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
4c70a4f3 RK |
9031 | |
9032 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
9033 | ||
90f81f99 | 9034 | (define_insn "*lfq_power2" |
bb8df8a6 EC |
9035 | [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f") |
9036 | (match_operand:V2DF 1 "memory_operand" ""))] | |
90f81f99 AP |
9037 | "TARGET_POWER2 |
9038 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
bb8df8a6 | 9039 | "lfq%U1%X1 %0,%1") |
90f81f99 AP |
9040 | |
9041 | (define_peephole2 | |
9042 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4c70a4f3 | 9043 | (match_operand:DF 1 "memory_operand" "")) |
90f81f99 | 9044 | (set (match_operand:DF 2 "gpc_reg_operand" "") |
4c70a4f3 RK |
9045 | (match_operand:DF 3 "memory_operand" ""))] |
9046 | "TARGET_POWER2 | |
a3170dc6 | 9047 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9048 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
90f81f99 AP |
9049 | && mems_ok_for_quad_peep (operands[1], operands[3])" |
9050 | [(set (match_dup 0) | |
bb8df8a6 EC |
9051 | (match_dup 1))] |
9052 | "operands[1] = widen_memory_access (operands[1], V2DFmode, 0); | |
9053 | operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));") | |
4c70a4f3 | 9054 | |
90f81f99 | 9055 | (define_insn "*stfq_power2" |
bb8df8a6 EC |
9056 | [(set (match_operand:V2DF 0 "memory_operand" "") |
9057 | (match_operand:V2DF 1 "gpc_reg_operand" "f"))] | |
90f81f99 AP |
9058 | "TARGET_POWER2 |
9059 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
9060 | "stfq%U0%X0 %1,%0") | |
9061 | ||
9062 | ||
9063 | (define_peephole2 | |
4c70a4f3 | 9064 | [(set (match_operand:DF 0 "memory_operand" "") |
90f81f99 | 9065 | (match_operand:DF 1 "gpc_reg_operand" "")) |
4c70a4f3 | 9066 | (set (match_operand:DF 2 "memory_operand" "") |
90f81f99 | 9067 | (match_operand:DF 3 "gpc_reg_operand" ""))] |
4c70a4f3 | 9068 | "TARGET_POWER2 |
a3170dc6 | 9069 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9070 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
90f81f99 AP |
9071 | && mems_ok_for_quad_peep (operands[0], operands[2])" |
9072 | [(set (match_dup 0) | |
9073 | (match_dup 1))] | |
bb8df8a6 EC |
9074 | "operands[0] = widen_memory_access (operands[0], V2DFmode, 0); |
9075 | operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));") | |
2f4d9502 NS |
9076 | |
9077 | ;; after inserting conditional returns we can sometimes have | |
9078 | ;; unnecessary register moves. Unfortunately we cannot have a | |
9079 | ;; modeless peephole here, because some single SImode sets have early | |
9080 | ;; clobber outputs. Although those sets expand to multi-ppc-insn | |
9081 | ;; sequences, using get_attr_length here will smash the operands | |
9082 | ;; array. Neither is there an early_cobbler_p predicate. | |
9083 | (define_peephole2 | |
9084 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
9085 | (match_operand:DF 1 "any_operand" "")) | |
9086 | (set (match_operand:DF 2 "gpc_reg_operand" "") | |
9087 | (match_dup 0))] | |
9088 | "peep2_reg_dead_p (2, operands[0])" | |
9089 | [(set (match_dup 2) (match_dup 1))]) | |
9090 | ||
9091 | (define_peephole2 | |
9092 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
9093 | (match_operand:SF 1 "any_operand" "")) | |
9094 | (set (match_operand:SF 2 "gpc_reg_operand" "") | |
9095 | (match_dup 0))] | |
9096 | "peep2_reg_dead_p (2, operands[0])" | |
9097 | [(set (match_dup 2) (match_dup 1))]) | |
9098 | ||
1fd4e8c1 | 9099 | \f |
c4501e62 JJ |
9100 | ;; TLS support. |
9101 | ||
9102 | ;; "b" output constraint here and on tls_ld to support tls linker optimization. | |
9103 | (define_insn "tls_gd_32" | |
b150f4f3 DE |
9104 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9105 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9106 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9107 | UNSPEC_TLSGD))] | |
9108 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9109 | "addi %0,%1,%2@got@tlsgd") | |
9110 | ||
9111 | (define_insn "tls_gd_64" | |
b150f4f3 DE |
9112 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9113 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9114 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9115 | UNSPEC_TLSGD))] | |
9116 | "HAVE_AS_TLS && TARGET_64BIT" | |
9117 | "addi %0,%1,%2@got@tlsgd") | |
9118 | ||
9119 | (define_insn "tls_ld_32" | |
b150f4f3 DE |
9120 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9121 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9122 | UNSPEC_TLSLD))] |
9123 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9124 | "addi %0,%1,%&@got@tlsld") | |
9125 | ||
9126 | (define_insn "tls_ld_64" | |
b150f4f3 DE |
9127 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9128 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9129 | UNSPEC_TLSLD))] |
9130 | "HAVE_AS_TLS && TARGET_64BIT" | |
9131 | "addi %0,%1,%&@got@tlsld") | |
9132 | ||
9133 | (define_insn "tls_dtprel_32" | |
b150f4f3 DE |
9134 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9135 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9136 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9137 | UNSPEC_TLSDTPREL))] | |
9138 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9139 | "addi %0,%1,%2@dtprel") | |
9140 | ||
9141 | (define_insn "tls_dtprel_64" | |
b150f4f3 DE |
9142 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9143 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9144 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9145 | UNSPEC_TLSDTPREL))] | |
9146 | "HAVE_AS_TLS && TARGET_64BIT" | |
9147 | "addi %0,%1,%2@dtprel") | |
9148 | ||
9149 | (define_insn "tls_dtprel_ha_32" | |
b150f4f3 DE |
9150 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9151 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9152 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9153 | UNSPEC_TLSDTPRELHA))] | |
9154 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9155 | "addis %0,%1,%2@dtprel@ha") | |
9156 | ||
9157 | (define_insn "tls_dtprel_ha_64" | |
b150f4f3 DE |
9158 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9159 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9160 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9161 | UNSPEC_TLSDTPRELHA))] | |
9162 | "HAVE_AS_TLS && TARGET_64BIT" | |
9163 | "addis %0,%1,%2@dtprel@ha") | |
9164 | ||
9165 | (define_insn "tls_dtprel_lo_32" | |
b150f4f3 DE |
9166 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9167 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9168 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9169 | UNSPEC_TLSDTPRELLO))] | |
9170 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9171 | "addi %0,%1,%2@dtprel@l") | |
9172 | ||
9173 | (define_insn "tls_dtprel_lo_64" | |
b150f4f3 DE |
9174 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9175 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9176 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9177 | UNSPEC_TLSDTPRELLO))] | |
9178 | "HAVE_AS_TLS && TARGET_64BIT" | |
9179 | "addi %0,%1,%2@dtprel@l") | |
9180 | ||
9181 | (define_insn "tls_got_dtprel_32" | |
b150f4f3 DE |
9182 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9183 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9184 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9185 | UNSPEC_TLSGOTDTPREL))] | |
9186 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9187 | "lwz %0,%2@got@dtprel(%1)") | |
9188 | ||
9189 | (define_insn "tls_got_dtprel_64" | |
b150f4f3 DE |
9190 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9191 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9192 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9193 | UNSPEC_TLSGOTDTPREL))] | |
9194 | "HAVE_AS_TLS && TARGET_64BIT" | |
9195 | "ld %0,%2@got@dtprel(%1)") | |
9196 | ||
9197 | (define_insn "tls_tprel_32" | |
b150f4f3 DE |
9198 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9199 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9200 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9201 | UNSPEC_TLSTPREL))] | |
9202 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9203 | "addi %0,%1,%2@tprel") | |
9204 | ||
9205 | (define_insn "tls_tprel_64" | |
b150f4f3 DE |
9206 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9207 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9208 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9209 | UNSPEC_TLSTPREL))] | |
9210 | "HAVE_AS_TLS && TARGET_64BIT" | |
9211 | "addi %0,%1,%2@tprel") | |
9212 | ||
9213 | (define_insn "tls_tprel_ha_32" | |
b150f4f3 DE |
9214 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9215 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9216 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9217 | UNSPEC_TLSTPRELHA))] | |
9218 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9219 | "addis %0,%1,%2@tprel@ha") | |
9220 | ||
9221 | (define_insn "tls_tprel_ha_64" | |
b150f4f3 DE |
9222 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9223 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9224 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9225 | UNSPEC_TLSTPRELHA))] | |
9226 | "HAVE_AS_TLS && TARGET_64BIT" | |
9227 | "addis %0,%1,%2@tprel@ha") | |
9228 | ||
9229 | (define_insn "tls_tprel_lo_32" | |
b150f4f3 DE |
9230 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9231 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9232 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9233 | UNSPEC_TLSTPRELLO))] | |
9234 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9235 | "addi %0,%1,%2@tprel@l") | |
9236 | ||
9237 | (define_insn "tls_tprel_lo_64" | |
b150f4f3 DE |
9238 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9239 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9240 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9241 | UNSPEC_TLSTPRELLO))] | |
9242 | "HAVE_AS_TLS && TARGET_64BIT" | |
9243 | "addi %0,%1,%2@tprel@l") | |
9244 | ||
c1207243 | 9245 | ;; "b" output constraint here and on tls_tls input to support linker tls |
c4501e62 JJ |
9246 | ;; optimization. The linker may edit the instructions emitted by a |
9247 | ;; tls_got_tprel/tls_tls pair to addis,addi. | |
9248 | (define_insn "tls_got_tprel_32" | |
b150f4f3 DE |
9249 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9250 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9251 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9252 | UNSPEC_TLSGOTTPREL))] | |
9253 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9254 | "lwz %0,%2@got@tprel(%1)") | |
9255 | ||
9256 | (define_insn "tls_got_tprel_64" | |
b150f4f3 DE |
9257 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9258 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9259 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9260 | UNSPEC_TLSGOTTPREL))] | |
9261 | "HAVE_AS_TLS && TARGET_64BIT" | |
9262 | "ld %0,%2@got@tprel(%1)") | |
9263 | ||
9264 | (define_insn "tls_tls_32" | |
b150f4f3 DE |
9265 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9266 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9267 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9268 | UNSPEC_TLSTLS))] | |
9269 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9270 | "add %0,%1,%2@tls") | |
9271 | ||
9272 | (define_insn "tls_tls_64" | |
b150f4f3 DE |
9273 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9274 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9275 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9276 | UNSPEC_TLSTLS))] | |
9277 | "HAVE_AS_TLS && TARGET_64BIT" | |
9278 | "add %0,%1,%2@tls") | |
9279 | \f | |
1fd4e8c1 RK |
9280 | ;; Next come insns related to the calling sequence. |
9281 | ;; | |
9282 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 9283 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
9284 | |
9285 | (define_expand "allocate_stack" | |
52d3af72 | 9286 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9287 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
9288 | (set (reg 1) | |
9289 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
9290 | "" |
9291 | " | |
4697a36c | 9292 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 9293 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 9294 | rtx neg_op0; |
1fd4e8c1 RK |
9295 | |
9296 | emit_move_insn (chain, stack_bot); | |
4697a36c | 9297 | |
a157febd GK |
9298 | /* Check stack bounds if necessary. */ |
9299 | if (current_function_limit_stack) | |
9300 | { | |
9301 | rtx available; | |
6ae08853 | 9302 | available = expand_binop (Pmode, sub_optab, |
a157febd GK |
9303 | stack_pointer_rtx, stack_limit_rtx, |
9304 | NULL_RTX, 1, OPTAB_WIDEN); | |
9305 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
9306 | } | |
9307 | ||
e9a25f70 JL |
9308 | if (GET_CODE (operands[1]) != CONST_INT |
9309 | || INTVAL (operands[1]) < -32767 | |
9310 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
9311 | { |
9312 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 9313 | if (TARGET_32BIT) |
e9a25f70 | 9314 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 9315 | else |
e9a25f70 | 9316 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
9317 | } |
9318 | else | |
e9a25f70 | 9319 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 9320 | |
38c1f2d7 | 9321 | if (TARGET_UPDATE) |
2e6c9641 | 9322 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update)) |
38c1f2d7 | 9323 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); |
4697a36c | 9324 | |
38c1f2d7 MM |
9325 | else |
9326 | { | |
9327 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
9328 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 9329 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 9330 | } |
e9a25f70 JL |
9331 | |
9332 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
9333 | DONE; |
9334 | }") | |
59257ff7 RK |
9335 | |
9336 | ;; These patterns say how to save and restore the stack pointer. We need not | |
9337 | ;; save the stack pointer at function level since we are careful to | |
9338 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9339 | ;; when we restore the stack pointer. | |
9340 | ;; | |
9341 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9342 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9343 | ;; save area is a memory location. | |
9344 | ||
9345 | (define_expand "save_stack_function" | |
ff381587 MM |
9346 | [(match_operand 0 "any_operand" "") |
9347 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9348 | "" |
ff381587 | 9349 | "DONE;") |
59257ff7 RK |
9350 | |
9351 | (define_expand "restore_stack_function" | |
ff381587 MM |
9352 | [(match_operand 0 "any_operand" "") |
9353 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9354 | "" |
ff381587 | 9355 | "DONE;") |
59257ff7 | 9356 | |
2eef28ec AM |
9357 | ;; Adjust stack pointer (op0) to a new value (op1). |
9358 | ;; First copy old stack backchain to new location, and ensure that the | |
9359 | ;; scheduler won't reorder the sp assignment before the backchain write. | |
59257ff7 | 9360 | (define_expand "restore_stack_block" |
2eef28ec AM |
9361 | [(set (match_dup 2) (match_dup 3)) |
9362 | (set (match_dup 4) (match_dup 2)) | |
9363 | (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE)) | |
9364 | (set (match_operand 0 "register_operand" "") | |
9365 | (match_operand 1 "register_operand" ""))] | |
59257ff7 RK |
9366 | "" |
9367 | " | |
dfdfa60f DE |
9368 | { |
9369 | operands[2] = gen_reg_rtx (Pmode); | |
2eef28ec AM |
9370 | operands[3] = gen_frame_mem (Pmode, operands[0]); |
9371 | operands[4] = gen_frame_mem (Pmode, operands[1]); | |
9372 | operands[5] = gen_frame_mem (BLKmode, operands[0]); | |
dfdfa60f | 9373 | }") |
59257ff7 RK |
9374 | |
9375 | (define_expand "save_stack_nonlocal" | |
2eef28ec AM |
9376 | [(set (match_dup 3) (match_dup 4)) |
9377 | (set (match_operand 0 "memory_operand" "") (match_dup 3)) | |
9378 | (set (match_dup 2) (match_operand 1 "register_operand" ""))] | |
59257ff7 RK |
9379 | "" |
9380 | " | |
9381 | { | |
11b25716 | 9382 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
9383 | |
9384 | /* Copy the backchain to the first word, sp to the second. */ | |
2eef28ec AM |
9385 | operands[0] = adjust_address_nv (operands[0], Pmode, 0); |
9386 | operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word); | |
9387 | operands[3] = gen_reg_rtx (Pmode); | |
9388 | operands[4] = gen_frame_mem (Pmode, operands[1]); | |
59257ff7 | 9389 | }") |
7e69e155 | 9390 | |
59257ff7 | 9391 | (define_expand "restore_stack_nonlocal" |
2eef28ec AM |
9392 | [(set (match_dup 2) (match_operand 1 "memory_operand" "")) |
9393 | (set (match_dup 3) (match_dup 4)) | |
9394 | (set (match_dup 5) (match_dup 2)) | |
9395 | (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE)) | |
9396 | (set (match_operand 0 "register_operand" "") (match_dup 3))] | |
59257ff7 RK |
9397 | "" |
9398 | " | |
9399 | { | |
11b25716 | 9400 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
9401 | |
9402 | /* Restore the backchain from the first word, sp from the second. */ | |
2eef28ec AM |
9403 | operands[2] = gen_reg_rtx (Pmode); |
9404 | operands[3] = gen_reg_rtx (Pmode); | |
9405 | operands[1] = adjust_address_nv (operands[1], Pmode, 0); | |
9406 | operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word); | |
9407 | operands[5] = gen_frame_mem (Pmode, operands[3]); | |
9408 | operands[6] = gen_frame_mem (BLKmode, operands[0]); | |
59257ff7 | 9409 | }") |
9ebbca7d GK |
9410 | \f |
9411 | ;; TOC register handling. | |
b6c9286a | 9412 | |
9ebbca7d | 9413 | ;; Code to initialize the TOC register... |
f0f6a223 | 9414 | |
9ebbca7d | 9415 | (define_insn "load_toc_aix_si" |
e72247f4 | 9416 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
615158e2 | 9417 | (unspec:SI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 9418 | (use (reg:SI 2))])] |
2bfcf297 | 9419 | "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" |
f0f6a223 RK |
9420 | "* |
9421 | { | |
9ebbca7d GK |
9422 | char buf[30]; |
9423 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 9424 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9425 | operands[2] = gen_rtx_REG (Pmode, 2); |
9426 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
9427 | }" |
9428 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
9429 | |
9430 | (define_insn "load_toc_aix_di" | |
e72247f4 | 9431 | [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
615158e2 | 9432 | (unspec:DI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 9433 | (use (reg:DI 2))])] |
2bfcf297 | 9434 | "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" |
9ebbca7d GK |
9435 | "* |
9436 | { | |
9437 | char buf[30]; | |
f585a356 DE |
9438 | #ifdef TARGET_RELOCATABLE |
9439 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", | |
9440 | !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); | |
9441 | #else | |
9ebbca7d | 9442 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); |
f585a356 | 9443 | #endif |
2bfcf297 DB |
9444 | if (TARGET_ELF) |
9445 | strcat (buf, \"@toc\"); | |
a8a05998 | 9446 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9447 | operands[2] = gen_rtx_REG (Pmode, 2); |
9448 | return \"ld %0,%1(%2)\"; | |
9449 | }" | |
9450 | [(set_attr "type" "load")]) | |
9451 | ||
9452 | (define_insn "load_toc_v4_pic_si" | |
9453 | [(set (match_operand:SI 0 "register_operand" "=l") | |
615158e2 | 9454 | (unspec:SI [(const_int 0)] UNSPEC_TOC))] |
f607bc57 | 9455 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" |
9ebbca7d GK |
9456 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
9457 | [(set_attr "type" "branch") | |
9458 | (set_attr "length" "4")]) | |
9459 | ||
9ebbca7d GK |
9460 | (define_insn "load_toc_v4_PIC_1" |
9461 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9462 | (match_operand:SI 1 "immediate_operand" "s")) | |
c4501e62 | 9463 | (use (unspec [(match_dup 1)] UNSPEC_TOC))] |
7f970b70 AM |
9464 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX |
9465 | && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" | |
df7a8989 | 9466 | "bcl 20,31,%1\\n%1:" |
9ebbca7d GK |
9467 | [(set_attr "type" "branch") |
9468 | (set_attr "length" "4")]) | |
9469 | ||
9470 | (define_insn "load_toc_v4_PIC_1b" | |
9471 | [(set (match_operand:SI 0 "register_operand" "=l") | |
0e5be35b | 9472 | (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] |
c4501e62 | 9473 | UNSPEC_TOCPTR))] |
20b71b17 | 9474 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
0e5be35b | 9475 | "bcl 20,31,$+8\\n\\t.long %1-$" |
9ebbca7d GK |
9476 | [(set_attr "type" "branch") |
9477 | (set_attr "length" "8")]) | |
9478 | ||
9479 | (define_insn "load_toc_v4_PIC_2" | |
f585a356 | 9480 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
a2900460 | 9481 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
9ebbca7d GK |
9482 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") |
9483 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
20b71b17 | 9484 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
9ebbca7d GK |
9485 | "{l|lwz} %0,%2-%3(%1)" |
9486 | [(set_attr "type" "load")]) | |
9487 | ||
7f970b70 AM |
9488 | (define_insn "load_toc_v4_PIC_3b" |
9489 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
9490 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
9491 | (high:SI | |
9492 | (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s") | |
9493 | (match_operand:SI 3 "symbol_ref_operand" "s")))))] | |
9494 | "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic" | |
9495 | "{cau|addis} %0,%1,%2-%3@ha") | |
9496 | ||
9497 | (define_insn "load_toc_v4_PIC_3c" | |
9498 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
9499 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
9500 | (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s") | |
9501 | (match_operand:SI 3 "symbol_ref_operand" "s"))))] | |
9502 | "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic" | |
9503 | "{cal|addi} %0,%1,%2-%3@l") | |
f51eee6a | 9504 | |
9ebbca7d GK |
9505 | ;; If the TOC is shared over a translation unit, as happens with all |
9506 | ;; the kinds of PIC that we support, we need to restore the TOC | |
9507 | ;; pointer only when jumping over units of translation. | |
f51eee6a | 9508 | ;; On Darwin, we need to reload the picbase. |
9ebbca7d GK |
9509 | |
9510 | (define_expand "builtin_setjmp_receiver" | |
9511 | [(use (label_ref (match_operand 0 "" "")))] | |
f607bc57 | 9512 | "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
f51eee6a GK |
9513 | || (TARGET_TOC && TARGET_MINIMAL_TOC) |
9514 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" | |
9ebbca7d GK |
9515 | " |
9516 | { | |
84d7dd4a | 9517 | #if TARGET_MACHO |
f51eee6a GK |
9518 | if (DEFAULT_ABI == ABI_DARWIN) |
9519 | { | |
d24652ee | 9520 | const char *picbase = machopic_function_base_name (); |
485bad26 | 9521 | rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase)); |
f51eee6a GK |
9522 | rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
9523 | rtx tmplabrtx; | |
9524 | char tmplab[20]; | |
9525 | ||
9526 | ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", | |
9527 | CODE_LABEL_NUMBER (operands[0])); | |
485bad26 | 9528 | tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); |
f51eee6a | 9529 | |
b8a55285 AP |
9530 | emit_insn (gen_load_macho_picbase (picreg, tmplabrtx)); |
9531 | emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); | |
f51eee6a GK |
9532 | } |
9533 | else | |
84d7dd4a | 9534 | #endif |
f51eee6a | 9535 | rs6000_emit_load_toc_table (FALSE); |
9ebbca7d GK |
9536 | DONE; |
9537 | }") | |
7f970b70 AM |
9538 | |
9539 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9540 | ;; The output of this could be r0, but we make a very strong | |
9541 | ;; preference for a base register because it will usually | |
9542 | ;; be needed there. | |
9543 | (define_insn "elf_high" | |
9544 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") | |
9545 | (high:SI (match_operand 1 "" "")))] | |
9546 | "TARGET_ELF && ! TARGET_64BIT" | |
9547 | "{liu|lis} %0,%1@ha") | |
9548 | ||
9549 | (define_insn "elf_low" | |
9550 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
9551 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
9552 | (match_operand 2 "" "")))] | |
9553 | "TARGET_ELF && ! TARGET_64BIT" | |
9554 | "@ | |
9555 | {cal|la} %0,%2@l(%1) | |
9556 | {ai|addic} %0,%1,%K2") | |
9ebbca7d GK |
9557 | \f |
9558 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
9559 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
9560 | ;; pointer to its TOC, and whose third word contains a value to place in the |
9561 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 9562 | ;; "trampoline" need not have any executable code. |
b6c9286a | 9563 | |
cccf3bdc DE |
9564 | (define_expand "call_indirect_aix32" |
9565 | [(set (match_dup 2) | |
9566 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
9567 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9568 | (reg:SI 2)) | |
9569 | (set (reg:SI 2) | |
9570 | (mem:SI (plus:SI (match_dup 0) | |
9571 | (const_int 4)))) | |
9572 | (set (reg:SI 11) | |
9573 | (mem:SI (plus:SI (match_dup 0) | |
9574 | (const_int 8)))) | |
9575 | (parallel [(call (mem:SI (match_dup 2)) | |
9576 | (match_operand 1 "" "")) | |
9577 | (use (reg:SI 2)) | |
9578 | (use (reg:SI 11)) | |
9579 | (set (reg:SI 2) | |
9580 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9581 | (clobber (scratch:SI))])] | |
9582 | "TARGET_32BIT" | |
9583 | " | |
9584 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9585 | |
cccf3bdc DE |
9586 | (define_expand "call_indirect_aix64" |
9587 | [(set (match_dup 2) | |
9588 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
9589 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9590 | (reg:DI 2)) | |
9591 | (set (reg:DI 2) | |
9592 | (mem:DI (plus:DI (match_dup 0) | |
9593 | (const_int 8)))) | |
9594 | (set (reg:DI 11) | |
9595 | (mem:DI (plus:DI (match_dup 0) | |
9596 | (const_int 16)))) | |
9597 | (parallel [(call (mem:SI (match_dup 2)) | |
9598 | (match_operand 1 "" "")) | |
9599 | (use (reg:DI 2)) | |
9600 | (use (reg:DI 11)) | |
9601 | (set (reg:DI 2) | |
9602 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9603 | (clobber (scratch:SI))])] | |
9604 | "TARGET_64BIT" | |
9605 | " | |
9606 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 9607 | |
cccf3bdc DE |
9608 | (define_expand "call_value_indirect_aix32" |
9609 | [(set (match_dup 3) | |
9610 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
9611 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9612 | (reg:SI 2)) | |
9613 | (set (reg:SI 2) | |
9614 | (mem:SI (plus:SI (match_dup 1) | |
9615 | (const_int 4)))) | |
9616 | (set (reg:SI 11) | |
9617 | (mem:SI (plus:SI (match_dup 1) | |
9618 | (const_int 8)))) | |
9619 | (parallel [(set (match_operand 0 "" "") | |
9620 | (call (mem:SI (match_dup 3)) | |
9621 | (match_operand 2 "" ""))) | |
9622 | (use (reg:SI 2)) | |
9623 | (use (reg:SI 11)) | |
9624 | (set (reg:SI 2) | |
9625 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9626 | (clobber (scratch:SI))])] | |
9627 | "TARGET_32BIT" | |
9628 | " | |
9629 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9630 | |
cccf3bdc DE |
9631 | (define_expand "call_value_indirect_aix64" |
9632 | [(set (match_dup 3) | |
9633 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
9634 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9635 | (reg:DI 2)) | |
9636 | (set (reg:DI 2) | |
9637 | (mem:DI (plus:DI (match_dup 1) | |
9638 | (const_int 8)))) | |
9639 | (set (reg:DI 11) | |
9640 | (mem:DI (plus:DI (match_dup 1) | |
9641 | (const_int 16)))) | |
9642 | (parallel [(set (match_operand 0 "" "") | |
9643 | (call (mem:SI (match_dup 3)) | |
9644 | (match_operand 2 "" ""))) | |
9645 | (use (reg:DI 2)) | |
9646 | (use (reg:DI 11)) | |
9647 | (set (reg:DI 2) | |
9648 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9649 | (clobber (scratch:SI))])] | |
9650 | "TARGET_64BIT" | |
9651 | " | |
9652 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 9653 | |
b6c9286a | 9654 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 9655 | (define_expand "call" |
a260abc9 | 9656 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 9657 | (match_operand 1 "" "")) |
4697a36c | 9658 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
9659 | (clobber (scratch:SI))])] |
9660 | "" | |
9661 | " | |
9662 | { | |
ee890fe2 | 9663 | #if TARGET_MACHO |
ab82a49f | 9664 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
9665 | operands[0] = machopic_indirect_call_target (operands[0]); |
9666 | #endif | |
9667 | ||
37409796 NS |
9668 | gcc_assert (GET_CODE (operands[0]) == MEM); |
9669 | gcc_assert (GET_CODE (operands[1]) == CONST_INT); | |
1fd4e8c1 RK |
9670 | |
9671 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 9672 | |
7f970b70 AM |
9673 | if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT |
9674 | && flag_pic | |
9675 | && GET_CODE (operands[0]) == SYMBOL_REF | |
9676 | && !SYMBOL_REF_LOCAL_P (operands[0])) | |
9677 | { | |
9678 | rtx call; | |
9679 | rtvec tmp; | |
9680 | ||
9681 | tmp = gen_rtvec (3, | |
9682 | gen_rtx_CALL (VOIDmode, | |
9683 | gen_rtx_MEM (SImode, operands[0]), | |
9684 | operands[1]), | |
9685 | gen_rtx_USE (VOIDmode, operands[2]), | |
9686 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode))); | |
9687 | call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp)); | |
9688 | use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx); | |
9689 | DONE; | |
9690 | } | |
9691 | ||
6a4cee5f | 9692 | if (GET_CODE (operands[0]) != SYMBOL_REF |
473f51b6 | 9693 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0])) |
efdba735 | 9694 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0)) |
1fd4e8c1 | 9695 | { |
6a4cee5f MM |
9696 | if (INTVAL (operands[2]) & CALL_LONG) |
9697 | operands[0] = rs6000_longcall_ref (operands[0]); | |
9698 | ||
37409796 NS |
9699 | switch (DEFAULT_ABI) |
9700 | { | |
9701 | case ABI_V4: | |
9702 | case ABI_DARWIN: | |
9703 | operands[0] = force_reg (Pmode, operands[0]); | |
9704 | break; | |
1fd4e8c1 | 9705 | |
37409796 | 9706 | case ABI_AIX: |
cccf3bdc DE |
9707 | /* AIX function pointers are really pointers to a three word |
9708 | area. */ | |
9709 | emit_call_insn (TARGET_32BIT | |
9710 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
9711 | operands[0]), | |
9712 | operands[1]) | |
9713 | : gen_call_indirect_aix64 (force_reg (DImode, | |
9714 | operands[0]), | |
9715 | operands[1])); | |
9716 | DONE; | |
37409796 NS |
9717 | |
9718 | default: | |
9719 | gcc_unreachable (); | |
b6c9286a | 9720 | } |
1fd4e8c1 RK |
9721 | } |
9722 | }") | |
9723 | ||
9724 | (define_expand "call_value" | |
9725 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 9726 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 9727 | (match_operand 2 "" ""))) |
4697a36c | 9728 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
9729 | (clobber (scratch:SI))])] |
9730 | "" | |
9731 | " | |
9732 | { | |
ee890fe2 | 9733 | #if TARGET_MACHO |
ab82a49f | 9734 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
9735 | operands[1] = machopic_indirect_call_target (operands[1]); |
9736 | #endif | |
9737 | ||
37409796 NS |
9738 | gcc_assert (GET_CODE (operands[1]) == MEM); |
9739 | gcc_assert (GET_CODE (operands[2]) == CONST_INT); | |
1fd4e8c1 RK |
9740 | |
9741 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 9742 | |
7f970b70 AM |
9743 | if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT |
9744 | && flag_pic | |
9745 | && GET_CODE (operands[1]) == SYMBOL_REF | |
9746 | && !SYMBOL_REF_LOCAL_P (operands[1])) | |
9747 | { | |
9748 | rtx call; | |
9749 | rtvec tmp; | |
9750 | ||
9751 | tmp = gen_rtvec (3, | |
9752 | gen_rtx_SET (VOIDmode, | |
9753 | operands[0], | |
9754 | gen_rtx_CALL (VOIDmode, | |
9755 | gen_rtx_MEM (SImode, | |
9756 | operands[1]), | |
9757 | operands[2])), | |
9758 | gen_rtx_USE (VOIDmode, operands[3]), | |
9759 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode))); | |
9760 | call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp)); | |
9761 | use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx); | |
9762 | DONE; | |
9763 | } | |
9764 | ||
6a4cee5f | 9765 | if (GET_CODE (operands[1]) != SYMBOL_REF |
473f51b6 | 9766 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1])) |
efdba735 | 9767 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0)) |
1fd4e8c1 | 9768 | { |
6756293c | 9769 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
9770 | operands[1] = rs6000_longcall_ref (operands[1]); |
9771 | ||
37409796 NS |
9772 | switch (DEFAULT_ABI) |
9773 | { | |
9774 | case ABI_V4: | |
9775 | case ABI_DARWIN: | |
9776 | operands[1] = force_reg (Pmode, operands[1]); | |
9777 | break; | |
1fd4e8c1 | 9778 | |
37409796 | 9779 | case ABI_AIX: |
cccf3bdc DE |
9780 | /* AIX function pointers are really pointers to a three word |
9781 | area. */ | |
9782 | emit_call_insn (TARGET_32BIT | |
9783 | ? gen_call_value_indirect_aix32 (operands[0], | |
9784 | force_reg (SImode, | |
9785 | operands[1]), | |
9786 | operands[2]) | |
9787 | : gen_call_value_indirect_aix64 (operands[0], | |
9788 | force_reg (DImode, | |
9789 | operands[1]), | |
9790 | operands[2])); | |
9791 | DONE; | |
37409796 NS |
9792 | |
9793 | default: | |
9794 | gcc_unreachable (); | |
b6c9286a | 9795 | } |
1fd4e8c1 RK |
9796 | } |
9797 | }") | |
9798 | ||
04780ee7 | 9799 | ;; Call to function in current module. No TOC pointer reload needed. |
a0ab749a | 9800 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
9801 | ;; either the function was not prototyped, or it was prototyped as a |
9802 | ;; variable argument function. It is > 0 if FP registers were passed | |
9803 | ;; and < 0 if they were not. | |
04780ee7 | 9804 | |
a260abc9 | 9805 | (define_insn "*call_local32" |
4697a36c MM |
9806 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
9807 | (match_operand 1 "" "g,g")) | |
9808 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9809 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 9810 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
9811 | "* |
9812 | { | |
6a4cee5f MM |
9813 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
9814 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9815 | ||
9816 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9817 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 9818 | |
a226df46 | 9819 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 9820 | }" |
b7ff3d82 DE |
9821 | [(set_attr "type" "branch") |
9822 | (set_attr "length" "4,8")]) | |
04780ee7 | 9823 | |
a260abc9 DE |
9824 | (define_insn "*call_local64" |
9825 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
9826 | (match_operand 1 "" "g,g")) | |
9827 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9828 | (clobber (match_scratch:SI 3 "=l,l"))] | |
9829 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
9830 | "* | |
9831 | { | |
9832 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
9833 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9834 | ||
9835 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9836 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9837 | ||
9838 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
9839 | }" | |
9840 | [(set_attr "type" "branch") | |
9841 | (set_attr "length" "4,8")]) | |
9842 | ||
cccf3bdc | 9843 | (define_insn "*call_value_local32" |
d18dba68 | 9844 | [(set (match_operand 0 "" "") |
a260abc9 DE |
9845 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) |
9846 | (match_operand 2 "" "g,g"))) | |
9847 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9848 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9849 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
9850 | "* | |
9851 | { | |
9852 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9853 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9854 | ||
9855 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9856 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9857 | ||
9858 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9859 | }" | |
9860 | [(set_attr "type" "branch") | |
9861 | (set_attr "length" "4,8")]) | |
9862 | ||
9863 | ||
cccf3bdc | 9864 | (define_insn "*call_value_local64" |
d18dba68 | 9865 | [(set (match_operand 0 "" "") |
a260abc9 DE |
9866 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) |
9867 | (match_operand 2 "" "g,g"))) | |
9868 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9869 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9870 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
9871 | "* | |
9872 | { | |
9873 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9874 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9875 | ||
9876 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9877 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9878 | ||
9879 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9880 | }" | |
9881 | [(set_attr "type" "branch") | |
9882 | (set_attr "length" "4,8")]) | |
9883 | ||
04780ee7 | 9884 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 9885 | ;; pointer (r2) after the call unless this is System V. |
a0ab749a | 9886 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
9887 | ;; either the function was not prototyped, or it was prototyped as a |
9888 | ;; variable argument function. It is > 0 if FP registers were passed | |
9889 | ;; and < 0 if they were not. | |
04780ee7 | 9890 | |
cccf3bdc | 9891 | (define_insn "*call_indirect_nonlocal_aix32" |
70ae0191 DE |
9892 | [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l")) |
9893 | (match_operand 1 "" "g,g")) | |
cccf3bdc DE |
9894 | (use (reg:SI 2)) |
9895 | (use (reg:SI 11)) | |
9896 | (set (reg:SI 2) | |
9897 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
70ae0191 | 9898 | (clobber (match_scratch:SI 2 "=l,l"))] |
cccf3bdc DE |
9899 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
9900 | "b%T0l\;{l|lwz} 2,20(1)" | |
9901 | [(set_attr "type" "jmpreg") | |
9902 | (set_attr "length" "8")]) | |
9903 | ||
a260abc9 | 9904 | (define_insn "*call_nonlocal_aix32" |
cc4d5fec | 9905 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
9906 | (match_operand 1 "" "g")) |
9907 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
9908 | (clobber (match_scratch:SI 3 "=l"))] | |
9909 | "TARGET_32BIT | |
9910 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 9911 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 9912 | "bl %z0\;%." |
b7ff3d82 | 9913 | [(set_attr "type" "branch") |
cccf3bdc DE |
9914 | (set_attr "length" "8")]) |
9915 | ||
9916 | (define_insn "*call_indirect_nonlocal_aix64" | |
70ae0191 DE |
9917 | [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l")) |
9918 | (match_operand 1 "" "g,g")) | |
cccf3bdc DE |
9919 | (use (reg:DI 2)) |
9920 | (use (reg:DI 11)) | |
9921 | (set (reg:DI 2) | |
9922 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
70ae0191 | 9923 | (clobber (match_scratch:SI 2 "=l,l"))] |
cccf3bdc DE |
9924 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
9925 | "b%T0l\;ld 2,40(1)" | |
9926 | [(set_attr "type" "jmpreg") | |
9927 | (set_attr "length" "8")]) | |
59313e4e | 9928 | |
a260abc9 | 9929 | (define_insn "*call_nonlocal_aix64" |
cc4d5fec | 9930 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
9931 | (match_operand 1 "" "g")) |
9932 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
9933 | (clobber (match_scratch:SI 3 "=l"))] | |
6ae08853 | 9934 | "TARGET_64BIT |
9ebbca7d | 9935 | && DEFAULT_ABI == ABI_AIX |
a260abc9 | 9936 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 9937 | "bl %z0\;%." |
a260abc9 | 9938 | [(set_attr "type" "branch") |
cccf3bdc | 9939 | (set_attr "length" "8")]) |
7509c759 | 9940 | |
cccf3bdc | 9941 | (define_insn "*call_value_indirect_nonlocal_aix32" |
d18dba68 | 9942 | [(set (match_operand 0 "" "") |
70ae0191 DE |
9943 | (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l")) |
9944 | (match_operand 2 "" "g,g"))) | |
cccf3bdc DE |
9945 | (use (reg:SI 2)) |
9946 | (use (reg:SI 11)) | |
9947 | (set (reg:SI 2) | |
9948 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
70ae0191 | 9949 | (clobber (match_scratch:SI 3 "=l,l"))] |
cccf3bdc DE |
9950 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
9951 | "b%T1l\;{l|lwz} 2,20(1)" | |
9952 | [(set_attr "type" "jmpreg") | |
9953 | (set_attr "length" "8")]) | |
1fd4e8c1 | 9954 | |
cccf3bdc | 9955 | (define_insn "*call_value_nonlocal_aix32" |
d18dba68 | 9956 | [(set (match_operand 0 "" "") |
cc4d5fec | 9957 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
9958 | (match_operand 2 "" "g"))) |
9959 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
9960 | (clobber (match_scratch:SI 4 "=l"))] | |
9961 | "TARGET_32BIT | |
9962 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 9963 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 9964 | "bl %z1\;%." |
b7ff3d82 | 9965 | [(set_attr "type" "branch") |
cccf3bdc | 9966 | (set_attr "length" "8")]) |
04780ee7 | 9967 | |
cccf3bdc | 9968 | (define_insn "*call_value_indirect_nonlocal_aix64" |
d18dba68 | 9969 | [(set (match_operand 0 "" "") |
70ae0191 DE |
9970 | (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l")) |
9971 | (match_operand 2 "" "g,g"))) | |
cccf3bdc DE |
9972 | (use (reg:DI 2)) |
9973 | (use (reg:DI 11)) | |
9974 | (set (reg:DI 2) | |
9975 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
70ae0191 | 9976 | (clobber (match_scratch:SI 3 "=l,l"))] |
cccf3bdc DE |
9977 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
9978 | "b%T1l\;ld 2,40(1)" | |
9979 | [(set_attr "type" "jmpreg") | |
9980 | (set_attr "length" "8")]) | |
9981 | ||
9982 | (define_insn "*call_value_nonlocal_aix64" | |
d18dba68 | 9983 | [(set (match_operand 0 "" "") |
cc4d5fec | 9984 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
9985 | (match_operand 2 "" "g"))) |
9986 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
9987 | (clobber (match_scratch:SI 4 "=l"))] | |
6ae08853 | 9988 | "TARGET_64BIT |
9ebbca7d | 9989 | && DEFAULT_ABI == ABI_AIX |
5a19791c | 9990 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
9991 | "bl %z1\;%." |
9992 | [(set_attr "type" "branch") | |
9993 | (set_attr "length" "8")]) | |
9994 | ||
9995 | ;; A function pointer under System V is just a normal pointer | |
9996 | ;; operands[0] is the function pointer | |
9997 | ;; operands[1] is the stack size to clean up | |
9998 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
9999 | ;; which indicates how to set cr1 | |
10000 | ||
a5c76ee6 | 10001 | (define_insn "*call_indirect_nonlocal_sysv" |
6d0a8091 DJ |
10002 | [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l")) |
10003 | (match_operand 1 "" "g,g,g,g")) | |
10004 | (use (match_operand:SI 2 "immediate_operand" "O,O,n,n")) | |
10005 | (clobber (match_scratch:SI 3 "=l,l,l,l"))] | |
50d440bc | 10006 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10007 | || DEFAULT_ABI == ABI_DARWIN" |
911f679c | 10008 | { |
cccf3bdc | 10009 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10010 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f | 10011 | |
cccf3bdc | 10012 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
a5c76ee6 | 10013 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10014 | |
a5c76ee6 ZW |
10015 | return "b%T0l"; |
10016 | } | |
6d0a8091 DJ |
10017 | [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg") |
10018 | (set_attr "length" "4,4,8,8")]) | |
cccf3bdc | 10019 | |
a5c76ee6 ZW |
10020 | (define_insn "*call_nonlocal_sysv" |
10021 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10022 | (match_operand 1 "" "g,g")) | |
10023 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10024 | (clobber (match_scratch:SI 3 "=l,l"))] | |
efdba735 SH |
10025 | "(DEFAULT_ABI == ABI_DARWIN |
10026 | || (DEFAULT_ABI == ABI_V4 | |
10027 | && (INTVAL (operands[2]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10028 | { |
10029 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10030 | output_asm_insn ("crxor 6,6,6", operands); | |
10031 | ||
10032 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10033 | output_asm_insn ("creqv 6,6,6", operands); | |
10034 | ||
c989f2f7 | 10035 | #if TARGET_MACHO |
efdba735 SH |
10036 | return output_call(insn, operands, 0, 2); |
10037 | #else | |
7f970b70 AM |
10038 | if (DEFAULT_ABI == ABI_V4 && flag_pic) |
10039 | { | |
10040 | if (TARGET_SECURE_PLT && flag_pic == 2) | |
10041 | /* The magic 32768 offset here and in the other sysv call insns | |
10042 | corresponds to the offset of r30 in .got2, as given by LCTOC1. | |
10043 | See sysv4.h:toc_section. */ | |
10044 | return "bl %z0+32768@plt"; | |
10045 | else | |
10046 | return "bl %z0@plt"; | |
10047 | } | |
10048 | else | |
10049 | return "bl %z0"; | |
6ae08853 | 10050 | #endif |
a5c76ee6 ZW |
10051 | } |
10052 | [(set_attr "type" "branch,branch") | |
10053 | (set_attr "length" "4,8")]) | |
10054 | ||
10055 | (define_insn "*call_value_indirect_nonlocal_sysv" | |
d18dba68 | 10056 | [(set (match_operand 0 "" "") |
6d0a8091 DJ |
10057 | (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l")) |
10058 | (match_operand 2 "" "g,g,g,g"))) | |
10059 | (use (match_operand:SI 3 "immediate_operand" "O,O,n,n")) | |
10060 | (clobber (match_scratch:SI 4 "=l,l,l,l"))] | |
50d440bc | 10061 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10062 | || DEFAULT_ABI == ABI_DARWIN" |
b6c9286a | 10063 | { |
6a4cee5f | 10064 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10065 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f MM |
10066 | |
10067 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
a5c76ee6 | 10068 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10069 | |
a5c76ee6 ZW |
10070 | return "b%T1l"; |
10071 | } | |
6d0a8091 DJ |
10072 | [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg") |
10073 | (set_attr "length" "4,4,8,8")]) | |
a5c76ee6 ZW |
10074 | |
10075 | (define_insn "*call_value_nonlocal_sysv" | |
10076 | [(set (match_operand 0 "" "") | |
10077 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10078 | (match_operand 2 "" "g,g"))) | |
10079 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10080 | (clobber (match_scratch:SI 4 "=l,l"))] | |
efdba735 SH |
10081 | "(DEFAULT_ABI == ABI_DARWIN |
10082 | || (DEFAULT_ABI == ABI_V4 | |
10083 | && (INTVAL (operands[3]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10084 | { |
10085 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10086 | output_asm_insn ("crxor 6,6,6", operands); | |
10087 | ||
10088 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10089 | output_asm_insn ("creqv 6,6,6", operands); | |
10090 | ||
c989f2f7 | 10091 | #if TARGET_MACHO |
efdba735 SH |
10092 | return output_call(insn, operands, 1, 3); |
10093 | #else | |
7f970b70 AM |
10094 | if (DEFAULT_ABI == ABI_V4 && flag_pic) |
10095 | { | |
10096 | if (TARGET_SECURE_PLT && flag_pic == 2) | |
10097 | return "bl %z1+32768@plt"; | |
10098 | else | |
10099 | return "bl %z1@plt"; | |
10100 | } | |
10101 | else | |
10102 | return "bl %z1"; | |
6ae08853 | 10103 | #endif |
a5c76ee6 ZW |
10104 | } |
10105 | [(set_attr "type" "branch,branch") | |
10106 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
10107 | |
10108 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
10109 | (define_expand "untyped_call" |
10110 | [(parallel [(call (match_operand 0 "" "") | |
10111 | (const_int 0)) | |
10112 | (match_operand 1 "" "") | |
10113 | (match_operand 2 "" "")])] | |
10114 | "" | |
10115 | " | |
10116 | { | |
10117 | int i; | |
10118 | ||
7d70b8b2 | 10119 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
10120 | |
10121 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10122 | { | |
10123 | rtx set = XVECEXP (operands[2], 0, i); | |
10124 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10125 | } | |
10126 | ||
10127 | /* The optimizer does not know that the call sets the function value | |
10128 | registers we stored in the result block. We avoid problems by | |
10129 | claiming that all hard registers are used and clobbered at this | |
10130 | point. */ | |
10131 | emit_insn (gen_blockage ()); | |
10132 | ||
10133 | DONE; | |
10134 | }") | |
10135 | ||
5e1bf043 DJ |
10136 | ;; sibling call patterns |
10137 | (define_expand "sibcall" | |
10138 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) | |
10139 | (match_operand 1 "" "")) | |
10140 | (use (match_operand 2 "" "")) | |
fe352c29 | 10141 | (use (match_operand 3 "" "")) |
5e1bf043 DJ |
10142 | (return)])] |
10143 | "" | |
10144 | " | |
10145 | { | |
10146 | #if TARGET_MACHO | |
ab82a49f | 10147 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10148 | operands[0] = machopic_indirect_call_target (operands[0]); |
10149 | #endif | |
10150 | ||
37409796 NS |
10151 | gcc_assert (GET_CODE (operands[0]) == MEM); |
10152 | gcc_assert (GET_CODE (operands[1]) == CONST_INT); | |
5e1bf043 DJ |
10153 | |
10154 | operands[0] = XEXP (operands[0], 0); | |
fe352c29 | 10155 | operands[3] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10156 | |
10157 | }") | |
10158 | ||
10159 | ;; this and similar patterns must be marked as using LR, otherwise | |
10160 | ;; dataflow will try to delete the store into it. This is true | |
10161 | ;; even when the actual reg to jump to is in CTR, when LR was | |
10162 | ;; saved and restored around the PIC-setting BCL. | |
10163 | (define_insn "*sibcall_local32" | |
10164 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) | |
10165 | (match_operand 1 "" "g,g")) | |
10166 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10167 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10168 | (return)] |
10169 | "(INTVAL (operands[2]) & CALL_LONG) == 0" | |
10170 | "* | |
10171 | { | |
10172 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10173 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10174 | ||
10175 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10176 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10177 | ||
10178 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10179 | }" | |
10180 | [(set_attr "type" "branch") | |
10181 | (set_attr "length" "4,8")]) | |
10182 | ||
10183 | (define_insn "*sibcall_local64" | |
10184 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10185 | (match_operand 1 "" "g,g")) | |
10186 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10187 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10188 | (return)] |
10189 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10190 | "* | |
10191 | { | |
10192 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10193 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10194 | ||
10195 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10196 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10197 | ||
10198 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10199 | }" | |
10200 | [(set_attr "type" "branch") | |
10201 | (set_attr "length" "4,8")]) | |
10202 | ||
10203 | (define_insn "*sibcall_value_local32" | |
10204 | [(set (match_operand 0 "" "") | |
10205 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
10206 | (match_operand 2 "" "g,g"))) | |
10207 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10208 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10209 | (return)] |
10210 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10211 | "* | |
10212 | { | |
10213 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10214 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10215 | ||
10216 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10217 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10218 | ||
10219 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10220 | }" | |
10221 | [(set_attr "type" "branch") | |
10222 | (set_attr "length" "4,8")]) | |
10223 | ||
10224 | ||
10225 | (define_insn "*sibcall_value_local64" | |
10226 | [(set (match_operand 0 "" "") | |
10227 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
10228 | (match_operand 2 "" "g,g"))) | |
10229 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10230 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10231 | (return)] |
10232 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10233 | "* | |
10234 | { | |
10235 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10236 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10237 | ||
10238 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10239 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10240 | ||
10241 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10242 | }" | |
10243 | [(set_attr "type" "branch") | |
10244 | (set_attr "length" "4,8")]) | |
10245 | ||
10246 | (define_insn "*sibcall_nonlocal_aix32" | |
10247 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) | |
10248 | (match_operand 1 "" "g")) | |
10249 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10250 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 DJ |
10251 | (return)] |
10252 | "TARGET_32BIT | |
10253 | && DEFAULT_ABI == ABI_AIX | |
10254 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10255 | "b %z0" | |
10256 | [(set_attr "type" "branch") | |
10257 | (set_attr "length" "4")]) | |
10258 | ||
10259 | (define_insn "*sibcall_nonlocal_aix64" | |
10260 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) | |
10261 | (match_operand 1 "" "g")) | |
10262 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10263 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 | 10264 | (return)] |
6ae08853 | 10265 | "TARGET_64BIT |
5e1bf043 DJ |
10266 | && DEFAULT_ABI == ABI_AIX |
10267 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10268 | "b %z0" | |
10269 | [(set_attr "type" "branch") | |
10270 | (set_attr "length" "4")]) | |
10271 | ||
10272 | (define_insn "*sibcall_value_nonlocal_aix32" | |
10273 | [(set (match_operand 0 "" "") | |
10274 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) | |
10275 | (match_operand 2 "" "g"))) | |
10276 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10277 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 DJ |
10278 | (return)] |
10279 | "TARGET_32BIT | |
10280 | && DEFAULT_ABI == ABI_AIX | |
10281 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10282 | "b %z1" | |
10283 | [(set_attr "type" "branch") | |
10284 | (set_attr "length" "4")]) | |
10285 | ||
10286 | (define_insn "*sibcall_value_nonlocal_aix64" | |
10287 | [(set (match_operand 0 "" "") | |
10288 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) | |
10289 | (match_operand 2 "" "g"))) | |
10290 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10291 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 | 10292 | (return)] |
6ae08853 | 10293 | "TARGET_64BIT |
5e1bf043 DJ |
10294 | && DEFAULT_ABI == ABI_AIX |
10295 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10296 | "b %z1" | |
10297 | [(set_attr "type" "branch") | |
10298 | (set_attr "length" "4")]) | |
10299 | ||
10300 | (define_insn "*sibcall_nonlocal_sysv" | |
10301 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10302 | (match_operand 1 "" "")) | |
10303 | (use (match_operand 2 "immediate_operand" "O,n")) | |
fe352c29 | 10304 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10305 | (return)] |
10306 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10307 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10308 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
10309 | "* | |
10310 | { | |
10311 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10312 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10313 | ||
10314 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10315 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10316 | ||
7f970b70 AM |
10317 | if (DEFAULT_ABI == ABI_V4 && flag_pic) |
10318 | { | |
10319 | if (TARGET_SECURE_PLT && flag_pic == 2) | |
10320 | return \"b %z0+32768@plt\"; | |
10321 | else | |
10322 | return \"b %z0@plt\"; | |
10323 | } | |
10324 | else | |
10325 | return \"b %z0\"; | |
5e1bf043 DJ |
10326 | }" |
10327 | [(set_attr "type" "branch,branch") | |
10328 | (set_attr "length" "4,8")]) | |
10329 | ||
10330 | (define_expand "sibcall_value" | |
10331 | [(parallel [(set (match_operand 0 "register_operand" "") | |
10332 | (call (mem:SI (match_operand 1 "address_operand" "")) | |
10333 | (match_operand 2 "" ""))) | |
10334 | (use (match_operand 3 "" "")) | |
fe352c29 | 10335 | (use (match_operand 4 "" "")) |
5e1bf043 DJ |
10336 | (return)])] |
10337 | "" | |
10338 | " | |
10339 | { | |
10340 | #if TARGET_MACHO | |
ab82a49f | 10341 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10342 | operands[1] = machopic_indirect_call_target (operands[1]); |
10343 | #endif | |
10344 | ||
37409796 NS |
10345 | gcc_assert (GET_CODE (operands[1]) == MEM); |
10346 | gcc_assert (GET_CODE (operands[2]) == CONST_INT); | |
5e1bf043 DJ |
10347 | |
10348 | operands[1] = XEXP (operands[1], 0); | |
fe352c29 | 10349 | operands[4] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10350 | |
10351 | }") | |
10352 | ||
10353 | (define_insn "*sibcall_value_nonlocal_sysv" | |
10354 | [(set (match_operand 0 "" "") | |
10355 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10356 | (match_operand 2 "" ""))) | |
10357 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10358 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10359 | (return)] |
10360 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10361 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10362 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
10363 | "* | |
10364 | { | |
10365 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10366 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10367 | ||
10368 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10369 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10370 | ||
7f970b70 AM |
10371 | if (DEFAULT_ABI == ABI_V4 && flag_pic) |
10372 | { | |
10373 | if (TARGET_SECURE_PLT && flag_pic == 2) | |
10374 | return \"b %z1+32768@plt\"; | |
10375 | else | |
10376 | return \"b %z1@plt\"; | |
10377 | } | |
10378 | else | |
10379 | return \"b %z1\"; | |
5e1bf043 DJ |
10380 | }" |
10381 | [(set_attr "type" "branch,branch") | |
10382 | (set_attr "length" "4,8")]) | |
10383 | ||
10384 | (define_expand "sibcall_epilogue" | |
10385 | [(use (const_int 0))] | |
10386 | "TARGET_SCHED_PROLOG" | |
10387 | " | |
10388 | { | |
10389 | rs6000_emit_epilogue (TRUE); | |
10390 | DONE; | |
10391 | }") | |
10392 | ||
e6f948e3 RK |
10393 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and |
10394 | ;; all of memory. This blocks insns from being moved across this point. | |
10395 | ||
10396 | (define_insn "blockage" | |
615158e2 | 10397 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)] |
e6f948e3 RK |
10398 | "" |
10399 | "") | |
1fd4e8c1 RK |
10400 | \f |
10401 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 10402 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
10403 | ;; |
10404 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
10405 | ;; insns, and branches. We store the operands of compares until we see | |
10406 | ;; how it is used. | |
4ae234b0 | 10407 | (define_expand "cmp<mode>" |
1fd4e8c1 | 10408 | [(set (cc0) |
4ae234b0 GK |
10409 | (compare (match_operand:GPR 0 "gpc_reg_operand" "") |
10410 | (match_operand:GPR 1 "reg_or_short_operand" "")))] | |
1fd4e8c1 RK |
10411 | "" |
10412 | " | |
10413 | { | |
10414 | /* Take care of the possibility that operands[1] might be negative but | |
10415 | this might be a logical operation. That insn doesn't exist. */ | |
10416 | if (GET_CODE (operands[1]) == CONST_INT | |
10417 | && INTVAL (operands[1]) < 0) | |
4ae234b0 | 10418 | operands[1] = force_reg (<MODE>mode, operands[1]); |
1fd4e8c1 RK |
10419 | |
10420 | rs6000_compare_op0 = operands[0]; | |
10421 | rs6000_compare_op1 = operands[1]; | |
10422 | rs6000_compare_fp_p = 0; | |
10423 | DONE; | |
10424 | }") | |
10425 | ||
4ae234b0 GK |
10426 | (define_expand "cmp<mode>" |
10427 | [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "") | |
10428 | (match_operand:FP 1 "gpc_reg_operand" "")))] | |
10429 | "" | |
d6f99ca4 DE |
10430 | " |
10431 | { | |
10432 | rs6000_compare_op0 = operands[0]; | |
10433 | rs6000_compare_op1 = operands[1]; | |
10434 | rs6000_compare_fp_p = 1; | |
10435 | DONE; | |
10436 | }") | |
10437 | ||
1fd4e8c1 | 10438 | (define_expand "beq" |
39a10a29 | 10439 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10440 | "" |
39a10a29 | 10441 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10442 | |
10443 | (define_expand "bne" | |
39a10a29 | 10444 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10445 | "" |
39a10a29 | 10446 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 10447 | |
39a10a29 GK |
10448 | (define_expand "bge" |
10449 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10450 | "" |
39a10a29 | 10451 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
10452 | |
10453 | (define_expand "bgt" | |
39a10a29 | 10454 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10455 | "" |
39a10a29 | 10456 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
10457 | |
10458 | (define_expand "ble" | |
39a10a29 | 10459 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10460 | "" |
39a10a29 | 10461 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 10462 | |
39a10a29 GK |
10463 | (define_expand "blt" |
10464 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10465 | "" |
39a10a29 | 10466 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 10467 | |
39a10a29 GK |
10468 | (define_expand "bgeu" |
10469 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10470 | "" |
39a10a29 | 10471 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 10472 | |
39a10a29 GK |
10473 | (define_expand "bgtu" |
10474 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10475 | "" |
39a10a29 | 10476 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 10477 | |
39a10a29 GK |
10478 | (define_expand "bleu" |
10479 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10480 | "" |
39a10a29 | 10481 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 10482 | |
39a10a29 GK |
10483 | (define_expand "bltu" |
10484 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10485 | "" |
39a10a29 | 10486 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 10487 | |
1c882ea4 | 10488 | (define_expand "bunordered" |
39a10a29 | 10489 | [(use (match_operand 0 "" ""))] |
7a1bf2f9 | 10490 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
39a10a29 | 10491 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
10492 | |
10493 | (define_expand "bordered" | |
39a10a29 | 10494 | [(use (match_operand 0 "" ""))] |
7a1bf2f9 | 10495 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
39a10a29 | 10496 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
10497 | |
10498 | (define_expand "buneq" | |
39a10a29 | 10499 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10500 | "" |
39a10a29 | 10501 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
10502 | |
10503 | (define_expand "bunge" | |
39a10a29 | 10504 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10505 | "" |
39a10a29 | 10506 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
10507 | |
10508 | (define_expand "bungt" | |
39a10a29 | 10509 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10510 | "" |
39a10a29 | 10511 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
10512 | |
10513 | (define_expand "bunle" | |
39a10a29 | 10514 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10515 | "" |
39a10a29 | 10516 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
10517 | |
10518 | (define_expand "bunlt" | |
39a10a29 | 10519 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10520 | "" |
39a10a29 | 10521 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
10522 | |
10523 | (define_expand "bltgt" | |
39a10a29 | 10524 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10525 | "" |
39a10a29 | 10526 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 10527 | |
1fd4e8c1 RK |
10528 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
10529 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
10530 | ;; with an scc insns. However, due to the order that combine see the | |
10531 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
10532 | ;; the cases we don't want to handle. | |
10533 | (define_expand "seq" | |
39a10a29 | 10534 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10535 | "" |
39a10a29 | 10536 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10537 | |
10538 | (define_expand "sne" | |
39a10a29 | 10539 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10540 | "" |
10541 | " | |
6ae08853 | 10542 | { |
39a10a29 | 10543 | if (! rs6000_compare_fp_p) |
1fd4e8c1 RK |
10544 | FAIL; |
10545 | ||
6ae08853 | 10546 | rs6000_emit_sCOND (NE, operands[0]); |
39a10a29 | 10547 | DONE; |
1fd4e8c1 RK |
10548 | }") |
10549 | ||
b7053a3f GK |
10550 | ;; A >= 0 is best done the portable way for A an integer. |
10551 | (define_expand "sge" | |
39a10a29 | 10552 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10553 | "" |
10554 | " | |
5638268e | 10555 | { |
e56d7409 | 10556 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
1fd4e8c1 RK |
10557 | FAIL; |
10558 | ||
b7053a3f | 10559 | rs6000_emit_sCOND (GE, operands[0]); |
39a10a29 | 10560 | DONE; |
1fd4e8c1 RK |
10561 | }") |
10562 | ||
b7053a3f GK |
10563 | ;; A > 0 is best done using the portable sequence, so fail in that case. |
10564 | (define_expand "sgt" | |
39a10a29 | 10565 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10566 | "" |
10567 | " | |
5638268e | 10568 | { |
e56d7409 | 10569 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
1fd4e8c1 RK |
10570 | FAIL; |
10571 | ||
6ae08853 | 10572 | rs6000_emit_sCOND (GT, operands[0]); |
39a10a29 | 10573 | DONE; |
1fd4e8c1 RK |
10574 | }") |
10575 | ||
b7053a3f GK |
10576 | ;; A <= 0 is best done the portable way for A an integer. |
10577 | (define_expand "sle" | |
39a10a29 | 10578 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10579 | "" |
5638268e DE |
10580 | " |
10581 | { | |
e56d7409 | 10582 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
5638268e DE |
10583 | FAIL; |
10584 | ||
6ae08853 | 10585 | rs6000_emit_sCOND (LE, operands[0]); |
5638268e DE |
10586 | DONE; |
10587 | }") | |
1fd4e8c1 | 10588 | |
b7053a3f GK |
10589 | ;; A < 0 is best done in the portable way for A an integer. |
10590 | (define_expand "slt" | |
39a10a29 | 10591 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10592 | "" |
10593 | " | |
5638268e | 10594 | { |
e56d7409 | 10595 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
1fd4e8c1 RK |
10596 | FAIL; |
10597 | ||
6ae08853 | 10598 | rs6000_emit_sCOND (LT, operands[0]); |
39a10a29 | 10599 | DONE; |
1fd4e8c1 RK |
10600 | }") |
10601 | ||
b7053a3f GK |
10602 | (define_expand "sgeu" |
10603 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10604 | "" | |
10605 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") | |
10606 | ||
1fd4e8c1 | 10607 | (define_expand "sgtu" |
39a10a29 | 10608 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10609 | "" |
39a10a29 | 10610 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 10611 | |
b7053a3f GK |
10612 | (define_expand "sleu" |
10613 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10614 | "" | |
10615 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") | |
10616 | ||
1fd4e8c1 | 10617 | (define_expand "sltu" |
39a10a29 | 10618 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10619 | "" |
39a10a29 | 10620 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 10621 | |
b7053a3f | 10622 | (define_expand "sunordered" |
39a10a29 | 10623 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
7836a61f | 10624 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
b7053a3f | 10625 | "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }") |
1fd4e8c1 | 10626 | |
b7053a3f | 10627 | (define_expand "sordered" |
39a10a29 | 10628 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
7836a61f | 10629 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
b7053a3f GK |
10630 | "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }") |
10631 | ||
10632 | (define_expand "suneq" | |
10633 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10634 | "" | |
10635 | "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }") | |
10636 | ||
10637 | (define_expand "sunge" | |
10638 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10639 | "" | |
10640 | "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }") | |
10641 | ||
10642 | (define_expand "sungt" | |
10643 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10644 | "" | |
10645 | "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }") | |
10646 | ||
10647 | (define_expand "sunle" | |
10648 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10649 | "" | |
10650 | "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }") | |
10651 | ||
10652 | (define_expand "sunlt" | |
10653 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10654 | "" | |
10655 | "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }") | |
10656 | ||
10657 | (define_expand "sltgt" | |
10658 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10659 | "" | |
10660 | "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }") | |
10661 | ||
3aebbe5f JJ |
10662 | (define_expand "stack_protect_set" |
10663 | [(match_operand 0 "memory_operand" "") | |
10664 | (match_operand 1 "memory_operand" "")] | |
10665 | "" | |
10666 | { | |
77008252 JJ |
10667 | #ifdef TARGET_THREAD_SSP_OFFSET |
10668 | rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2); | |
10669 | rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET)); | |
10670 | operands[1] = gen_rtx_MEM (Pmode, addr); | |
10671 | #endif | |
3aebbe5f JJ |
10672 | if (TARGET_64BIT) |
10673 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
10674 | else | |
10675 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
10676 | DONE; | |
10677 | }) | |
10678 | ||
10679 | (define_insn "stack_protect_setsi" | |
10680 | [(set (match_operand:SI 0 "memory_operand" "=m") | |
10681 | (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET)) | |
10682 | (set (match_scratch:SI 2 "=&r") (const_int 0))] | |
10683 | "TARGET_32BIT" | |
10684 | "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0" | |
10685 | [(set_attr "type" "three") | |
10686 | (set_attr "length" "12")]) | |
10687 | ||
10688 | (define_insn "stack_protect_setdi" | |
10689 | [(set (match_operand:DI 0 "memory_operand" "=m") | |
10690 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET)) | |
10691 | (set (match_scratch:DI 2 "=&r") (const_int 0))] | |
10692 | "TARGET_64BIT" | |
10693 | "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0" | |
10694 | [(set_attr "type" "three") | |
10695 | (set_attr "length" "12")]) | |
10696 | ||
10697 | (define_expand "stack_protect_test" | |
10698 | [(match_operand 0 "memory_operand" "") | |
10699 | (match_operand 1 "memory_operand" "") | |
10700 | (match_operand 2 "" "")] | |
10701 | "" | |
10702 | { | |
77008252 JJ |
10703 | #ifdef TARGET_THREAD_SSP_OFFSET |
10704 | rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2); | |
10705 | rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET)); | |
10706 | operands[1] = gen_rtx_MEM (Pmode, addr); | |
10707 | #endif | |
3aebbe5f JJ |
10708 | rs6000_compare_op0 = operands[0]; |
10709 | rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), | |
10710 | UNSPEC_SP_TEST); | |
10711 | rs6000_compare_fp_p = 0; | |
10712 | emit_jump_insn (gen_beq (operands[2])); | |
10713 | DONE; | |
10714 | }) | |
10715 | ||
10716 | (define_insn "stack_protect_testsi" | |
10717 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y") | |
10718 | (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m") | |
10719 | (match_operand:SI 2 "memory_operand" "m,m")] | |
10720 | UNSPEC_SP_TEST)) | |
41f12ed0 JJ |
10721 | (set (match_scratch:SI 4 "=r,r") (const_int 0)) |
10722 | (clobber (match_scratch:SI 3 "=&r,&r"))] | |
3aebbe5f JJ |
10723 | "TARGET_32BIT" |
10724 | "@ | |
10725 | {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0 | |
10726 | {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0" | |
10727 | [(set_attr "length" "16,20")]) | |
10728 | ||
10729 | (define_insn "stack_protect_testdi" | |
10730 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y") | |
10731 | (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m") | |
10732 | (match_operand:DI 2 "memory_operand" "m,m")] | |
10733 | UNSPEC_SP_TEST)) | |
41f12ed0 JJ |
10734 | (set (match_scratch:DI 4 "=r,r") (const_int 0)) |
10735 | (clobber (match_scratch:DI 3 "=&r,&r"))] | |
3aebbe5f JJ |
10736 | "TARGET_64BIT" |
10737 | "@ | |
10738 | ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0 | |
10739 | ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0" | |
10740 | [(set_attr "length" "16,20")]) | |
10741 | ||
1fd4e8c1 RK |
10742 | \f |
10743 | ;; Here are the actual compare insns. | |
4ae234b0 | 10744 | (define_insn "*cmp<mode>_internal1" |
1fd4e8c1 | 10745 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
4ae234b0 GK |
10746 | (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r") |
10747 | (match_operand:GPR 2 "reg_or_short_operand" "rI")))] | |
1fd4e8c1 | 10748 | "" |
4ae234b0 | 10749 | "{cmp%I2|cmp<wd>%I2} %0,%1,%2" |
b54cf83a | 10750 | [(set_attr "type" "cmp")]) |
266eb58a | 10751 | |
f357808b | 10752 | ;; If we are comparing a register for equality with a large constant, |
28d0e143 PB |
10753 | ;; we can do this with an XOR followed by a compare. But this is profitable |
10754 | ;; only if the large constant is only used for the comparison (and in this | |
10755 | ;; case we already have a register to reuse as scratch). | |
130869aa PB |
10756 | ;; |
10757 | ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear: | |
10758 | ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available. | |
f357808b | 10759 | |
28d0e143 | 10760 | (define_peephole2 |
130869aa PB |
10761 | [(set (match_operand:SI 0 "register_operand") |
10762 | (match_operand:SI 1 "logical_operand" "")) | |
10763 | (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator" | |
28d0e143 | 10764 | [(match_dup 0) |
130869aa | 10765 | (match_operand:SI 2 "logical_operand" "")])) |
28d0e143 | 10766 | (set (match_operand:CC 4 "cc_reg_operand" "") |
130869aa | 10767 | (compare:CC (match_operand:SI 5 "gpc_reg_operand" "") |
28d0e143 PB |
10768 | (match_dup 0))) |
10769 | (set (pc) | |
10770 | (if_then_else (match_operator 6 "equality_operator" | |
10771 | [(match_dup 4) (const_int 0)]) | |
10772 | (match_operand 7 "" "") | |
10773 | (match_operand 8 "" "")))] | |
130869aa PB |
10774 | "peep2_reg_dead_p (3, operands[0]) |
10775 | && peep2_reg_dead_p (4, operands[4])" | |
10776 | [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9))) | |
28d0e143 PB |
10777 | (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10))) |
10778 | (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))] | |
10779 | ||
10780 | { | |
10781 | /* Get the constant we are comparing against, and see what it looks like | |
10782 | when sign-extended from 16 to 32 bits. Then see what constant we could | |
10783 | XOR with SEXTC to get the sign-extended value. */ | |
10784 | rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]), | |
130869aa | 10785 | SImode, |
28d0e143 PB |
10786 | operands[1], operands[2]); |
10787 | HOST_WIDE_INT c = INTVAL (cnst); | |
a65c591c | 10788 | HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; |
5f59ecb7 | 10789 | HOST_WIDE_INT xorv = c ^ sextc; |
f357808b | 10790 | |
28d0e143 PB |
10791 | operands[9] = GEN_INT (xorv); |
10792 | operands[10] = GEN_INT (sextc); | |
10793 | }) | |
f357808b | 10794 | |
acad7ed3 | 10795 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 10796 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 10797 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 10798 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 10799 | "" |
e2c953b6 | 10800 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
b54cf83a | 10801 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 10802 | |
acad7ed3 | 10803 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
10804 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
10805 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 10806 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 10807 | "" |
e2c953b6 | 10808 | "cmpld%I2 %0,%1,%b2" |
b54cf83a | 10809 | [(set_attr "type" "cmp")]) |
266eb58a | 10810 | |
1fd4e8c1 RK |
10811 | ;; The following two insns don't exist as single insns, but if we provide |
10812 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
10813 | ;; of the required delay between a compare and branch. We generate code for | |
10814 | ;; them by splitting. | |
10815 | ||
10816 | (define_insn "" | |
10817 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 10818 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10819 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 10820 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10821 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
10822 | "" | |
baf97f86 RK |
10823 | "#" |
10824 | [(set_attr "length" "8")]) | |
7e69e155 | 10825 | |
1fd4e8c1 RK |
10826 | (define_insn "" |
10827 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 10828 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10829 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 10830 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10831 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
10832 | "" | |
baf97f86 RK |
10833 | "#" |
10834 | [(set_attr "length" "8")]) | |
7e69e155 | 10835 | |
1fd4e8c1 RK |
10836 | (define_split |
10837 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 10838 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10839 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 10840 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10841 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10842 | "" | |
10843 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
10844 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10845 | ||
10846 | (define_split | |
10847 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 10848 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10849 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 10850 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10851 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10852 | "" | |
10853 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
10854 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10855 | ||
acad7ed3 | 10856 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 10857 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10858 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
10859 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 10860 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
10861 | "fcmpu %0,%1,%2" |
10862 | [(set_attr "type" "fpcompare")]) | |
10863 | ||
acad7ed3 | 10864 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 10865 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10866 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
10867 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 10868 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
10869 | "fcmpu %0,%1,%2" |
10870 | [(set_attr "type" "fpcompare")]) | |
d6f99ca4 DE |
10871 | |
10872 | ;; Only need to compare second words if first words equal | |
10873 | (define_insn "*cmptf_internal1" | |
10874 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
10875 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
10876 | (match_operand:TF 2 "gpc_reg_operand" "f")))] | |
de17c25f | 10877 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT |
39e63627 | 10878 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" |
ecb62ae7 | 10879 | "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" |
d6f99ca4 DE |
10880 | [(set_attr "type" "fpcompare") |
10881 | (set_attr "length" "12")]) | |
de17c25f DE |
10882 | |
10883 | (define_insn_and_split "*cmptf_internal2" | |
10884 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
10885 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
10886 | (match_operand:TF 2 "gpc_reg_operand" "f"))) | |
10887 | (clobber (match_scratch:DF 3 "=f")) | |
10888 | (clobber (match_scratch:DF 4 "=f")) | |
10889 | (clobber (match_scratch:DF 5 "=f")) | |
10890 | (clobber (match_scratch:DF 6 "=f")) | |
10891 | (clobber (match_scratch:DF 7 "=f")) | |
10892 | (clobber (match_scratch:DF 8 "=f")) | |
10893 | (clobber (match_scratch:DF 9 "=f")) | |
10894 | (clobber (match_scratch:DF 10 "=f"))] | |
10895 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT | |
10896 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
10897 | "#" | |
10898 | "&& reload_completed" | |
10899 | [(set (match_dup 3) (match_dup 13)) | |
10900 | (set (match_dup 4) (match_dup 14)) | |
10901 | (set (match_dup 9) (abs:DF (match_dup 5))) | |
10902 | (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3))) | |
10903 | (set (pc) (if_then_else (ne (match_dup 0) (const_int 0)) | |
10904 | (label_ref (match_dup 11)) | |
10905 | (pc))) | |
10906 | (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7))) | |
10907 | (set (pc) (label_ref (match_dup 12))) | |
10908 | (match_dup 11) | |
10909 | (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7))) | |
10910 | (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8))) | |
10911 | (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9))) | |
10912 | (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4))) | |
10913 | (match_dup 12)] | |
10914 | { | |
10915 | REAL_VALUE_TYPE rv; | |
10916 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; | |
10917 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); | |
10918 | ||
10919 | operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word); | |
10920 | operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word); | |
10921 | operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word); | |
10922 | operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word); | |
10923 | operands[11] = gen_label_rtx (); | |
10924 | operands[12] = gen_label_rtx (); | |
10925 | real_inf (&rv); | |
10926 | operands[13] = force_const_mem (DFmode, | |
10927 | CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode)); | |
10928 | operands[14] = force_const_mem (DFmode, | |
10929 | CONST_DOUBLE_FROM_REAL_VALUE (dconst0, | |
10930 | DFmode)); | |
10931 | if (TARGET_TOC) | |
10932 | { | |
10933 | operands[13] = gen_const_mem (DFmode, | |
10934 | create_TOC_reference (XEXP (operands[13], 0))); | |
10935 | operands[14] = gen_const_mem (DFmode, | |
10936 | create_TOC_reference (XEXP (operands[14], 0))); | |
10937 | set_mem_alias_set (operands[13], get_TOC_alias_set ()); | |
10938 | set_mem_alias_set (operands[14], get_TOC_alias_set ()); | |
10939 | } | |
10940 | }) | |
1fd4e8c1 RK |
10941 | \f |
10942 | ;; Now we have the scc insns. We can do some combinations because of the | |
10943 | ;; way the machine works. | |
10944 | ;; | |
10945 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
10946 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
10947 | ;; cases the insns below which don't use an intermediate CR field will | |
10948 | ;; be used instead. | |
1fd4e8c1 | 10949 | (define_insn "" |
cd2b37d9 | 10950 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10951 | (match_operator:SI 1 "scc_comparison_operator" |
10952 | [(match_operand 2 "cc_reg_operand" "y") | |
10953 | (const_int 0)]))] | |
10954 | "" | |
2c4a9cff DE |
10955 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
10956 | [(set (attr "type") | |
10957 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
10958 | (const_string "mfcrf") | |
10959 | ] | |
10960 | (const_string "mfcr"))) | |
c1618c0c | 10961 | (set_attr "length" "8")]) |
1fd4e8c1 | 10962 | |
423c1189 | 10963 | ;; Same as above, but get the GT bit. |
64022b5d | 10964 | (define_insn "move_from_CR_gt_bit" |
423c1189 | 10965 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
64022b5d | 10966 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))] |
423c1189 | 10967 | "TARGET_E500" |
64022b5d | 10968 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31" |
423c1189 | 10969 | [(set_attr "type" "mfcr") |
c1618c0c | 10970 | (set_attr "length" "8")]) |
423c1189 | 10971 | |
a3170dc6 AH |
10972 | ;; Same as above, but get the OV/ORDERED bit. |
10973 | (define_insn "move_from_CR_ov_bit" | |
10974 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
615158e2 | 10975 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))] |
a3170dc6 | 10976 | "TARGET_ISEL" |
b7053a3f | 10977 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1" |
b54cf83a | 10978 | [(set_attr "type" "mfcr") |
c1618c0c | 10979 | (set_attr "length" "8")]) |
a3170dc6 | 10980 | |
1fd4e8c1 | 10981 | (define_insn "" |
9ebbca7d GK |
10982 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
10983 | (match_operator:DI 1 "scc_comparison_operator" | |
10984 | [(match_operand 2 "cc_reg_operand" "y") | |
10985 | (const_int 0)]))] | |
10986 | "TARGET_POWERPC64" | |
2c4a9cff DE |
10987 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
10988 | [(set (attr "type") | |
10989 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
10990 | (const_string "mfcrf") | |
10991 | ] | |
10992 | (const_string "mfcr"))) | |
c1618c0c | 10993 | (set_attr "length" "8")]) |
9ebbca7d GK |
10994 | |
10995 | (define_insn "" | |
10996 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 10997 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 10998 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
10999 | (const_int 0)]) |
11000 | (const_int 0))) | |
9ebbca7d | 11001 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11002 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
4b8a63d6 | 11003 | "TARGET_32BIT" |
9ebbca7d | 11004 | "@ |
2c4a9cff | 11005 | mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1 |
9ebbca7d | 11006 | #" |
b19003d8 | 11007 | [(set_attr "type" "delayed_compare") |
c1618c0c | 11008 | (set_attr "length" "8,16")]) |
9ebbca7d GK |
11009 | |
11010 | (define_split | |
11011 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11012 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
11013 | [(match_operand 2 "cc_reg_operand" "") | |
11014 | (const_int 0)]) | |
11015 | (const_int 0))) | |
11016 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
11017 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
4b8a63d6 | 11018 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11019 | [(set (match_dup 3) |
11020 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
11021 | (set (match_dup 0) | |
11022 | (compare:CC (match_dup 3) | |
11023 | (const_int 0)))] | |
11024 | "") | |
1fd4e8c1 RK |
11025 | |
11026 | (define_insn "" | |
cd2b37d9 | 11027 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11028 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
11029 | [(match_operand 2 "cc_reg_operand" "y") | |
11030 | (const_int 0)]) | |
11031 | (match_operand:SI 3 "const_int_operand" "n")))] | |
11032 | "" | |
11033 | "* | |
11034 | { | |
11035 | int is_bit = ccr_bit (operands[1], 1); | |
11036 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11037 | int count; | |
11038 | ||
11039 | if (is_bit >= put_bit) | |
11040 | count = is_bit - put_bit; | |
11041 | else | |
11042 | count = 32 - (put_bit - is_bit); | |
11043 | ||
89e9f3a8 MM |
11044 | operands[4] = GEN_INT (count); |
11045 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 11046 | |
2c4a9cff | 11047 | return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 | 11048 | }" |
2c4a9cff DE |
11049 | [(set (attr "type") |
11050 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11051 | (const_string "mfcrf") | |
11052 | ] | |
11053 | (const_string "mfcr"))) | |
c1618c0c | 11054 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
11055 | |
11056 | (define_insn "" | |
9ebbca7d | 11057 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11058 | (compare:CC |
11059 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 11060 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 11061 | (const_int 0)]) |
9ebbca7d | 11062 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 11063 | (const_int 0))) |
9ebbca7d | 11064 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11065 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
11066 | (match_dup 3)))] | |
ce71f754 | 11067 | "" |
1fd4e8c1 RK |
11068 | "* |
11069 | { | |
11070 | int is_bit = ccr_bit (operands[1], 1); | |
11071 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11072 | int count; | |
11073 | ||
9ebbca7d GK |
11074 | /* Force split for non-cc0 compare. */ |
11075 | if (which_alternative == 1) | |
11076 | return \"#\"; | |
11077 | ||
1fd4e8c1 RK |
11078 | if (is_bit >= put_bit) |
11079 | count = is_bit - put_bit; | |
11080 | else | |
11081 | count = 32 - (put_bit - is_bit); | |
11082 | ||
89e9f3a8 MM |
11083 | operands[5] = GEN_INT (count); |
11084 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 11085 | |
2c4a9cff | 11086 | return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 11087 | }" |
b19003d8 | 11088 | [(set_attr "type" "delayed_compare") |
c1618c0c | 11089 | (set_attr "length" "8,16")]) |
9ebbca7d GK |
11090 | |
11091 | (define_split | |
11092 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11093 | (compare:CC | |
11094 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
11095 | [(match_operand 2 "cc_reg_operand" "") | |
11096 | (const_int 0)]) | |
11097 | (match_operand:SI 3 "const_int_operand" "")) | |
11098 | (const_int 0))) | |
11099 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
11100 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11101 | (match_dup 3)))] | |
ce71f754 | 11102 | "reload_completed" |
9ebbca7d GK |
11103 | [(set (match_dup 4) |
11104 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11105 | (match_dup 3))) | |
11106 | (set (match_dup 0) | |
11107 | (compare:CC (match_dup 4) | |
11108 | (const_int 0)))] | |
11109 | "") | |
1fd4e8c1 | 11110 | |
c5defebb RK |
11111 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
11112 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
11113 | ||
11114 | (define_peephole | |
cd2b37d9 | 11115 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
11116 | (match_operator:SI 1 "scc_comparison_operator" |
11117 | [(match_operand 2 "cc_reg_operand" "y") | |
11118 | (const_int 0)])) | |
cd2b37d9 | 11119 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
11120 | (match_operator:SI 4 "scc_comparison_operator" |
11121 | [(match_operand 5 "cc_reg_operand" "y") | |
11122 | (const_int 0)]))] | |
309323c2 | 11123 | "REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11124 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11125 | [(set_attr "type" "mfcr") |
c1618c0c | 11126 | (set_attr "length" "12")]) |
c5defebb | 11127 | |
9ebbca7d GK |
11128 | (define_peephole |
11129 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11130 | (match_operator:DI 1 "scc_comparison_operator" | |
11131 | [(match_operand 2 "cc_reg_operand" "y") | |
11132 | (const_int 0)])) | |
11133 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
11134 | (match_operator:DI 4 "scc_comparison_operator" | |
11135 | [(match_operand 5 "cc_reg_operand" "y") | |
11136 | (const_int 0)]))] | |
309323c2 | 11137 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11138 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11139 | [(set_attr "type" "mfcr") |
c1618c0c | 11140 | (set_attr "length" "12")]) |
9ebbca7d | 11141 | |
1fd4e8c1 RK |
11142 | ;; There are some scc insns that can be done directly, without a compare. |
11143 | ;; These are faster because they don't involve the communications between | |
11144 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
11145 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
11146 | ;; | |
11147 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
11148 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
11149 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
11150 | ;; cases where it is no more expensive than (neg (scc ..)). | |
11151 | ||
11152 | ;; Have reload force a constant into a register for the simple insns that | |
11153 | ;; otherwise won't accept constants. We do this because it is faster than | |
11154 | ;; the cmp/mfcr sequence we would otherwise generate. | |
11155 | ||
e9441276 DE |
11156 | (define_mode_attr scc_eq_op2 [(SI "rKLI") |
11157 | (DI "rKJI")]) | |
a260abc9 | 11158 | |
e9441276 DE |
11159 | (define_insn_and_split "*eq<mode>" |
11160 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
11161 | (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") | |
d0515b39 | 11162 | (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))] |
70ae0191 | 11163 | "" |
e9441276 | 11164 | "#" |
d0515b39 DE |
11165 | "" |
11166 | [(set (match_dup 0) | |
11167 | (clz:GPR (match_dup 3))) | |
70ae0191 | 11168 | (set (match_dup 0) |
d0515b39 | 11169 | (lshiftrt:GPR (match_dup 0) (match_dup 4)))] |
70ae0191 | 11170 | { |
e9441276 DE |
11171 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0) |
11172 | { | |
d0515b39 DE |
11173 | /* Use output operand as intermediate. */ |
11174 | operands[3] = operands[0]; | |
11175 | ||
e9441276 | 11176 | if (logical_operand (operands[2], <MODE>mode)) |
d0515b39 | 11177 | emit_insn (gen_rtx_SET (VOIDmode, operands[3], |
e9441276 DE |
11178 | gen_rtx_XOR (<MODE>mode, |
11179 | operands[1], operands[2]))); | |
11180 | else | |
d0515b39 | 11181 | emit_insn (gen_rtx_SET (VOIDmode, operands[3], |
e9441276 DE |
11182 | gen_rtx_PLUS (<MODE>mode, operands[1], |
11183 | negate_rtx (<MODE>mode, | |
11184 | operands[2])))); | |
11185 | } | |
11186 | else | |
d0515b39 | 11187 | operands[3] = operands[1]; |
9ebbca7d | 11188 | |
d0515b39 | 11189 | operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode))); |
e9441276 | 11190 | }) |
a260abc9 | 11191 | |
e9441276 | 11192 | (define_insn_and_split "*eq<mode>_compare" |
d0515b39 | 11193 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") |
70ae0191 | 11194 | (compare:CC |
1fa5c709 DE |
11195 | (eq:P (match_operand:P 1 "gpc_reg_operand" "=r") |
11196 | (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>")) | |
70ae0191 | 11197 | (const_int 0))) |
1fa5c709 | 11198 | (set (match_operand:P 0 "gpc_reg_operand" "=r") |
d0515b39 | 11199 | (eq:P (match_dup 1) (match_dup 2)))] |
297abd0d | 11200 | "optimize_size" |
e9441276 | 11201 | "#" |
297abd0d | 11202 | "optimize_size" |
d0515b39 | 11203 | [(set (match_dup 0) |
1fa5c709 | 11204 | (clz:P (match_dup 4))) |
d0515b39 DE |
11205 | (parallel [(set (match_dup 3) |
11206 | (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5)) | |
70ae0191 DE |
11207 | (const_int 0))) |
11208 | (set (match_dup 0) | |
d0515b39 | 11209 | (lshiftrt:P (match_dup 0) (match_dup 5)))])] |
70ae0191 | 11210 | { |
e9441276 DE |
11211 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0) |
11212 | { | |
d0515b39 DE |
11213 | /* Use output operand as intermediate. */ |
11214 | operands[4] = operands[0]; | |
11215 | ||
e9441276 DE |
11216 | if (logical_operand (operands[2], <MODE>mode)) |
11217 | emit_insn (gen_rtx_SET (VOIDmode, operands[4], | |
11218 | gen_rtx_XOR (<MODE>mode, | |
11219 | operands[1], operands[2]))); | |
11220 | else | |
11221 | emit_insn (gen_rtx_SET (VOIDmode, operands[4], | |
11222 | gen_rtx_PLUS (<MODE>mode, operands[1], | |
11223 | negate_rtx (<MODE>mode, | |
11224 | operands[2])))); | |
11225 | } | |
11226 | else | |
11227 | operands[4] = operands[1]; | |
11228 | ||
d0515b39 | 11229 | operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode))); |
70ae0191 DE |
11230 | }) |
11231 | ||
b19003d8 RK |
11232 | ;; We have insns of the form shown by the first define_insn below. If |
11233 | ;; there is something inside the comparison operation, we must split it. | |
11234 | (define_split | |
11235 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
11236 | (plus:SI (match_operator 1 "comparison_operator" | |
11237 | [(match_operand:SI 2 "" "") | |
11238 | (match_operand:SI 3 | |
11239 | "reg_or_cint_operand" "")]) | |
11240 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
11241 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
11242 | "! gpc_reg_operand (operands[2], SImode)" | |
11243 | [(set (match_dup 5) (match_dup 2)) | |
11244 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
11245 | (match_dup 4)))]) | |
1fd4e8c1 | 11246 | |
297abd0d | 11247 | (define_insn "*plus_eqsi" |
5276df18 | 11248 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") |
cd2b37d9 | 11249 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
56fc483e | 11250 | (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I")) |
5276df18 | 11251 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] |
297abd0d | 11252 | "TARGET_32BIT && optimize_size" |
1fd4e8c1 | 11253 | "@ |
5276df18 DE |
11254 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11255 | {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 | |
11256 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11257 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11258 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" | |
943c15ed DE |
11259 | [(set_attr "type" "three,two,three,three,three") |
11260 | (set_attr "length" "12,8,12,12,12")]) | |
1fd4e8c1 | 11261 | |
297abd0d | 11262 | (define_insn "*compare_plus_eqsi" |
9ebbca7d | 11263 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11264 | (compare:CC |
1fd4e8c1 | 11265 | (plus:SI |
9ebbca7d | 11266 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
56fc483e | 11267 | (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I")) |
9ebbca7d | 11268 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) |
1fd4e8c1 | 11269 | (const_int 0))) |
9ebbca7d | 11270 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
297abd0d | 11271 | "TARGET_32BIT && optimize_size" |
1fd4e8c1 | 11272 | "@ |
ca7f5001 | 11273 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 11274 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
11275 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11276 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
11277 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11278 | # | |
11279 | # | |
11280 | # | |
11281 | # | |
11282 | #" | |
b19003d8 | 11283 | [(set_attr "type" "compare") |
9ebbca7d GK |
11284 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11285 | ||
11286 | (define_split | |
11287 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11288 | (compare:CC | |
11289 | (plus:SI | |
11290 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
56fc483e | 11291 | (match_operand:SI 2 "scc_eq_operand" "")) |
9ebbca7d GK |
11292 | (match_operand:SI 3 "gpc_reg_operand" "")) |
11293 | (const_int 0))) | |
11294 | (clobber (match_scratch:SI 4 ""))] | |
297abd0d | 11295 | "TARGET_32BIT && optimize_size && reload_completed" |
9ebbca7d GK |
11296 | [(set (match_dup 4) |
11297 | (plus:SI (eq:SI (match_dup 1) | |
11298 | (match_dup 2)) | |
11299 | (match_dup 3))) | |
11300 | (set (match_dup 0) | |
11301 | (compare:CC (match_dup 4) | |
11302 | (const_int 0)))] | |
11303 | "") | |
1fd4e8c1 | 11304 | |
297abd0d | 11305 | (define_insn "*plus_eqsi_compare" |
0387639b | 11306 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11307 | (compare:CC |
1fd4e8c1 | 11308 | (plus:SI |
9ebbca7d | 11309 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
56fc483e | 11310 | (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I")) |
9ebbca7d | 11311 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) |
1fd4e8c1 | 11312 | (const_int 0))) |
0387639b DE |
11313 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") |
11314 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
297abd0d | 11315 | "TARGET_32BIT && optimize_size" |
1fd4e8c1 | 11316 | "@ |
0387639b DE |
11317 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11318 | {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 | |
11319 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11320 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11321 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11322 | # |
11323 | # | |
11324 | # | |
11325 | # | |
11326 | #" | |
11327 | [(set_attr "type" "compare") | |
11328 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
11329 | ||
11330 | (define_split | |
0387639b | 11331 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11332 | (compare:CC |
11333 | (plus:SI | |
11334 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
56fc483e | 11335 | (match_operand:SI 2 "scc_eq_operand" "")) |
9ebbca7d GK |
11336 | (match_operand:SI 3 "gpc_reg_operand" "")) |
11337 | (const_int 0))) | |
11338 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
0387639b | 11339 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
297abd0d | 11340 | "TARGET_32BIT && optimize_size && reload_completed" |
0387639b | 11341 | [(set (match_dup 0) |
9ebbca7d | 11342 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
0387639b | 11343 | (set (match_dup 4) |
9ebbca7d GK |
11344 | (compare:CC (match_dup 0) |
11345 | (const_int 0)))] | |
11346 | "") | |
11347 | ||
d0515b39 DE |
11348 | (define_insn "*neg_eq0<mode>" |
11349 | [(set (match_operand:P 0 "gpc_reg_operand" "=r") | |
11350 | (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r") | |
11351 | (const_int 0))))] | |
297abd0d | 11352 | "optimize_size" |
d0515b39 DE |
11353 | "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0" |
11354 | [(set_attr "type" "two") | |
11355 | (set_attr "length" "8")]) | |
11356 | ||
11357 | (define_insn_and_split "*neg_eq<mode>" | |
11358 | [(set (match_operand:P 0 "gpc_reg_operand" "=r") | |
11359 | (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r") | |
11360 | (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))] | |
297abd0d | 11361 | "optimize_size" |
d0515b39 | 11362 | "#" |
297abd0d | 11363 | "optimize_size" |
d0515b39 DE |
11364 | [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))] |
11365 | { | |
11366 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0) | |
11367 | { | |
11368 | /* Use output operand as intermediate. */ | |
11369 | operands[3] = operands[0]; | |
11370 | ||
11371 | if (logical_operand (operands[2], <MODE>mode)) | |
11372 | emit_insn (gen_rtx_SET (VOIDmode, operands[3], | |
11373 | gen_rtx_XOR (<MODE>mode, | |
11374 | operands[1], operands[2]))); | |
11375 | else | |
11376 | emit_insn (gen_rtx_SET (VOIDmode, operands[3], | |
11377 | gen_rtx_PLUS (<MODE>mode, operands[1], | |
11378 | negate_rtx (<MODE>mode, | |
11379 | operands[2])))); | |
11380 | } | |
11381 | else | |
11382 | operands[3] = operands[1]; | |
11383 | }) | |
1fd4e8c1 | 11384 | |
ea9be077 MM |
11385 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
11386 | ;; since it nabs/sr is just as fast. | |
ce45ef46 | 11387 | (define_insn "*ne0si" |
b4e95693 | 11388 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
11389 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
11390 | (const_int 31))) | |
11391 | (clobber (match_scratch:SI 2 "=&r"))] | |
683bdff7 | 11392 | "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL" |
ea9be077 | 11393 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
943c15ed DE |
11394 | [(set_attr "type" "two") |
11395 | (set_attr "length" "8")]) | |
ea9be077 | 11396 | |
ce45ef46 | 11397 | (define_insn "*ne0di" |
a260abc9 DE |
11398 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
11399 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11400 | (const_int 63))) | |
11401 | (clobber (match_scratch:DI 2 "=&r"))] | |
683bdff7 | 11402 | "TARGET_64BIT" |
a260abc9 | 11403 | "addic %2,%1,-1\;subfe %0,%2,%1" |
943c15ed DE |
11404 | [(set_attr "type" "two") |
11405 | (set_attr "length" "8")]) | |
a260abc9 | 11406 | |
1fd4e8c1 | 11407 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
297abd0d | 11408 | (define_insn "*plus_ne0si" |
cd2b37d9 | 11409 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 11410 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 11411 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11412 | (const_int 31)) |
cd2b37d9 | 11413 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11414 | (clobber (match_scratch:SI 3 "=&r"))] |
683bdff7 | 11415 | "TARGET_32BIT" |
ca7f5001 | 11416 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
943c15ed DE |
11417 | [(set_attr "type" "two") |
11418 | (set_attr "length" "8")]) | |
1fd4e8c1 | 11419 | |
297abd0d | 11420 | (define_insn "*plus_ne0di" |
a260abc9 DE |
11421 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
11422 | (plus:DI (lshiftrt:DI | |
11423 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11424 | (const_int 63)) | |
11425 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11426 | (clobber (match_scratch:DI 3 "=&r"))] | |
683bdff7 | 11427 | "TARGET_64BIT" |
a260abc9 | 11428 | "addic %3,%1,-1\;addze %0,%2" |
943c15ed DE |
11429 | [(set_attr "type" "two") |
11430 | (set_attr "length" "8")]) | |
a260abc9 | 11431 | |
297abd0d | 11432 | (define_insn "*compare_plus_ne0si" |
9ebbca7d | 11433 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11434 | (compare:CC |
11435 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11436 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11437 | (const_int 31)) |
9ebbca7d | 11438 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11439 | (const_int 0))) |
889b90a1 GK |
11440 | (clobber (match_scratch:SI 3 "=&r,&r")) |
11441 | (clobber (match_scratch:SI 4 "=X,&r"))] | |
683bdff7 | 11442 | "TARGET_32BIT" |
9ebbca7d GK |
11443 | "@ |
11444 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
11445 | #" | |
b19003d8 | 11446 | [(set_attr "type" "compare") |
9ebbca7d GK |
11447 | (set_attr "length" "8,12")]) |
11448 | ||
11449 | (define_split | |
11450 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11451 | (compare:CC | |
11452 | (plus:SI (lshiftrt:SI | |
11453 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11454 | (const_int 31)) | |
11455 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11456 | (const_int 0))) | |
889b90a1 GK |
11457 | (clobber (match_scratch:SI 3 "")) |
11458 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11459 | "TARGET_32BIT && reload_completed" |
889b90a1 | 11460 | [(parallel [(set (match_dup 3) |
ce71f754 AM |
11461 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) |
11462 | (const_int 31)) | |
11463 | (match_dup 2))) | |
889b90a1 | 11464 | (clobber (match_dup 4))]) |
9ebbca7d GK |
11465 | (set (match_dup 0) |
11466 | (compare:CC (match_dup 3) | |
11467 | (const_int 0)))] | |
11468 | "") | |
1fd4e8c1 | 11469 | |
297abd0d | 11470 | (define_insn "*compare_plus_ne0di" |
9ebbca7d | 11471 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11472 | (compare:CC |
11473 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11474 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11475 | (const_int 63)) |
9ebbca7d | 11476 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11477 | (const_int 0))) |
9ebbca7d | 11478 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 11479 | "TARGET_64BIT" |
9ebbca7d GK |
11480 | "@ |
11481 | addic %3,%1,-1\;addze. %3,%2 | |
11482 | #" | |
a260abc9 | 11483 | [(set_attr "type" "compare") |
9ebbca7d GK |
11484 | (set_attr "length" "8,12")]) |
11485 | ||
11486 | (define_split | |
11487 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11488 | (compare:CC | |
11489 | (plus:DI (lshiftrt:DI | |
11490 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11491 | (const_int 63)) | |
11492 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11493 | (const_int 0))) | |
11494 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11495 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11496 | [(set (match_dup 3) |
11497 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
11498 | (const_int 63)) | |
11499 | (match_dup 2))) | |
11500 | (set (match_dup 0) | |
11501 | (compare:CC (match_dup 3) | |
11502 | (const_int 0)))] | |
11503 | "") | |
a260abc9 | 11504 | |
297abd0d | 11505 | (define_insn "*plus_ne0si_compare" |
9ebbca7d | 11506 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11507 | (compare:CC |
11508 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11509 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11510 | (const_int 31)) |
9ebbca7d | 11511 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11512 | (const_int 0))) |
9ebbca7d | 11513 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11514 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
11515 | (match_dup 2))) | |
9ebbca7d | 11516 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 11517 | "TARGET_32BIT" |
9ebbca7d GK |
11518 | "@ |
11519 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
11520 | #" | |
b19003d8 | 11521 | [(set_attr "type" "compare") |
9ebbca7d GK |
11522 | (set_attr "length" "8,12")]) |
11523 | ||
11524 | (define_split | |
11525 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11526 | (compare:CC | |
11527 | (plus:SI (lshiftrt:SI | |
11528 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11529 | (const_int 31)) | |
11530 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11531 | (const_int 0))) | |
11532 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11533 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11534 | (match_dup 2))) | |
11535 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 11536 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11537 | [(parallel [(set (match_dup 0) |
11538 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11539 | (match_dup 2))) | |
11540 | (clobber (match_dup 3))]) | |
11541 | (set (match_dup 4) | |
11542 | (compare:CC (match_dup 0) | |
11543 | (const_int 0)))] | |
11544 | "") | |
1fd4e8c1 | 11545 | |
297abd0d | 11546 | (define_insn "*plus_ne0di_compare" |
9ebbca7d | 11547 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11548 | (compare:CC |
11549 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11550 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11551 | (const_int 63)) |
9ebbca7d | 11552 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11553 | (const_int 0))) |
9ebbca7d | 11554 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
11555 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
11556 | (match_dup 2))) | |
9ebbca7d | 11557 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 11558 | "TARGET_64BIT" |
9ebbca7d GK |
11559 | "@ |
11560 | addic %3,%1,-1\;addze. %0,%2 | |
11561 | #" | |
a260abc9 | 11562 | [(set_attr "type" "compare") |
9ebbca7d GK |
11563 | (set_attr "length" "8,12")]) |
11564 | ||
11565 | (define_split | |
11566 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11567 | (compare:CC | |
11568 | (plus:DI (lshiftrt:DI | |
11569 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11570 | (const_int 63)) | |
11571 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11572 | (const_int 0))) | |
11573 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11574 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11575 | (match_dup 2))) | |
11576 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11577 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11578 | [(parallel [(set (match_dup 0) |
11579 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11580 | (match_dup 2))) | |
11581 | (clobber (match_dup 3))]) | |
11582 | (set (match_dup 4) | |
11583 | (compare:CC (match_dup 0) | |
11584 | (const_int 0)))] | |
11585 | "") | |
a260abc9 | 11586 | |
1fd4e8c1 | 11587 | (define_insn "" |
cd2b37d9 RK |
11588 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11589 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
11590 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
11591 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 11592 | "TARGET_POWER" |
1fd4e8c1 | 11593 | "@ |
ca7f5001 | 11594 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 11595 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11596 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11597 | |
11598 | (define_insn "" | |
9ebbca7d | 11599 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11600 | (compare:CC |
9ebbca7d GK |
11601 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11602 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 11603 | (const_int 0))) |
9ebbca7d | 11604 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11605 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11606 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 11607 | "TARGET_POWER" |
1fd4e8c1 | 11608 | "@ |
ca7f5001 | 11609 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
11610 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
11611 | # | |
11612 | #" | |
11613 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
11614 | (set_attr "length" "12,12,16,16")]) | |
11615 | ||
11616 | (define_split | |
11617 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11618 | (compare:CC | |
11619 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11620 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11621 | (const_int 0))) | |
11622 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11623 | (le:SI (match_dup 1) (match_dup 2))) | |
11624 | (clobber (match_scratch:SI 3 ""))] | |
11625 | "TARGET_POWER && reload_completed" | |
11626 | [(parallel [(set (match_dup 0) | |
11627 | (le:SI (match_dup 1) (match_dup 2))) | |
11628 | (clobber (match_dup 3))]) | |
11629 | (set (match_dup 4) | |
11630 | (compare:CC (match_dup 0) | |
11631 | (const_int 0)))] | |
11632 | "") | |
1fd4e8c1 RK |
11633 | |
11634 | (define_insn "" | |
097657c3 | 11635 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 11636 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 11637 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
097657c3 | 11638 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
ca7f5001 | 11639 | "TARGET_POWER" |
1fd4e8c1 | 11640 | "@ |
097657c3 AM |
11641 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11642 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" | |
b19003d8 | 11643 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11644 | |
11645 | (define_insn "" | |
9ebbca7d | 11646 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11647 | (compare:CC |
9ebbca7d GK |
11648 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11649 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
11650 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11651 | (const_int 0))) |
9ebbca7d | 11652 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 11653 | "TARGET_POWER" |
1fd4e8c1 | 11654 | "@ |
ca7f5001 | 11655 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
11656 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
11657 | # | |
11658 | #" | |
b19003d8 | 11659 | [(set_attr "type" "compare") |
9ebbca7d GK |
11660 | (set_attr "length" "12,12,16,16")]) |
11661 | ||
11662 | (define_split | |
11663 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11664 | (compare:CC | |
11665 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11666 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11667 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11668 | (const_int 0))) | |
11669 | (clobber (match_scratch:SI 4 ""))] | |
11670 | "TARGET_POWER && reload_completed" | |
11671 | [(set (match_dup 4) | |
11672 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 11673 | (match_dup 3))) |
9ebbca7d GK |
11674 | (set (match_dup 0) |
11675 | (compare:CC (match_dup 4) | |
11676 | (const_int 0)))] | |
11677 | "") | |
1fd4e8c1 RK |
11678 | |
11679 | (define_insn "" | |
097657c3 | 11680 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11681 | (compare:CC |
9ebbca7d GK |
11682 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11683 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
11684 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11685 | (const_int 0))) |
097657c3 AM |
11686 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
11687 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 11688 | "TARGET_POWER" |
1fd4e8c1 | 11689 | "@ |
097657c3 AM |
11690 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11691 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11692 | # |
11693 | #" | |
b19003d8 | 11694 | [(set_attr "type" "compare") |
9ebbca7d GK |
11695 | (set_attr "length" "12,12,16,16")]) |
11696 | ||
11697 | (define_split | |
097657c3 | 11698 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11699 | (compare:CC |
11700 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11701 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11702 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11703 | (const_int 0))) | |
11704 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 11705 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 11706 | "TARGET_POWER && reload_completed" |
097657c3 | 11707 | [(set (match_dup 0) |
9ebbca7d | 11708 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 11709 | (set (match_dup 4) |
9ebbca7d GK |
11710 | (compare:CC (match_dup 0) |
11711 | (const_int 0)))] | |
11712 | "") | |
1fd4e8c1 RK |
11713 | |
11714 | (define_insn "" | |
cd2b37d9 RK |
11715 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11716 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11717 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 11718 | "TARGET_POWER" |
1fd4e8c1 | 11719 | "@ |
ca7f5001 RK |
11720 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11721 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 11722 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11723 | |
a2dba291 DE |
11724 | (define_insn "*leu<mode>" |
11725 | [(set (match_operand:P 0 "gpc_reg_operand" "=r") | |
11726 | (leu:P (match_operand:P 1 "gpc_reg_operand" "r") | |
11727 | (match_operand:P 2 "reg_or_short_operand" "rI")))] | |
11728 | "" | |
ca7f5001 | 11729 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
943c15ed DE |
11730 | [(set_attr "type" "three") |
11731 | (set_attr "length" "12")]) | |
1fd4e8c1 | 11732 | |
a2dba291 | 11733 | (define_insn "*leu<mode>_compare" |
9ebbca7d | 11734 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11735 | (compare:CC |
a2dba291 DE |
11736 | (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r") |
11737 | (match_operand:P 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11738 | (const_int 0))) |
a2dba291 DE |
11739 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r") |
11740 | (leu:P (match_dup 1) (match_dup 2)))] | |
11741 | "" | |
9ebbca7d GK |
11742 | "@ |
11743 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
11744 | #" | |
b19003d8 | 11745 | [(set_attr "type" "compare") |
9ebbca7d GK |
11746 | (set_attr "length" "12,16")]) |
11747 | ||
11748 | (define_split | |
11749 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11750 | (compare:CC | |
a2dba291 DE |
11751 | (leu:P (match_operand:P 1 "gpc_reg_operand" "") |
11752 | (match_operand:P 2 "reg_or_short_operand" "")) | |
9ebbca7d | 11753 | (const_int 0))) |
a2dba291 DE |
11754 | (set (match_operand:P 0 "gpc_reg_operand" "") |
11755 | (leu:P (match_dup 1) (match_dup 2)))] | |
11756 | "reload_completed" | |
9ebbca7d | 11757 | [(set (match_dup 0) |
a2dba291 | 11758 | (leu:P (match_dup 1) (match_dup 2))) |
9ebbca7d GK |
11759 | (set (match_dup 3) |
11760 | (compare:CC (match_dup 0) | |
11761 | (const_int 0)))] | |
11762 | "") | |
1fd4e8c1 | 11763 | |
a2dba291 DE |
11764 | (define_insn "*plus_leu<mode>" |
11765 | [(set (match_operand:P 0 "gpc_reg_operand" "=&r") | |
11766 | (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r") | |
11767 | (match_operand:P 2 "reg_or_short_operand" "rI")) | |
11768 | (match_operand:P 3 "gpc_reg_operand" "r")))] | |
11769 | "" | |
80103f96 | 11770 | "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" |
943c15ed DE |
11771 | [(set_attr "type" "two") |
11772 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
11773 | |
11774 | (define_insn "" | |
9ebbca7d | 11775 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11776 | (compare:CC |
9ebbca7d GK |
11777 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11778 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11779 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11780 | (const_int 0))) |
9ebbca7d | 11781 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 11782 | "TARGET_32BIT" |
9ebbca7d GK |
11783 | "@ |
11784 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
11785 | #" | |
b19003d8 | 11786 | [(set_attr "type" "compare") |
9ebbca7d GK |
11787 | (set_attr "length" "8,12")]) |
11788 | ||
11789 | (define_split | |
11790 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11791 | (compare:CC | |
11792 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11793 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11794 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11795 | (const_int 0))) | |
11796 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11797 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11798 | [(set (match_dup 4) |
11799 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
11800 | (match_dup 3))) | |
11801 | (set (match_dup 0) | |
11802 | (compare:CC (match_dup 4) | |
11803 | (const_int 0)))] | |
11804 | "") | |
1fd4e8c1 RK |
11805 | |
11806 | (define_insn "" | |
097657c3 | 11807 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11808 | (compare:CC |
9ebbca7d GK |
11809 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11810 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11811 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11812 | (const_int 0))) |
097657c3 AM |
11813 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
11814 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 11815 | "TARGET_32BIT" |
9ebbca7d | 11816 | "@ |
097657c3 | 11817 | {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 |
9ebbca7d | 11818 | #" |
b19003d8 | 11819 | [(set_attr "type" "compare") |
9ebbca7d GK |
11820 | (set_attr "length" "8,12")]) |
11821 | ||
11822 | (define_split | |
097657c3 | 11823 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11824 | (compare:CC |
11825 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11826 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11827 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11828 | (const_int 0))) | |
11829 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 11830 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 11831 | "TARGET_32BIT && reload_completed" |
097657c3 | 11832 | [(set (match_dup 0) |
9ebbca7d | 11833 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 11834 | (set (match_dup 4) |
9ebbca7d GK |
11835 | (compare:CC (match_dup 0) |
11836 | (const_int 0)))] | |
11837 | "") | |
1fd4e8c1 | 11838 | |
a2dba291 DE |
11839 | (define_insn "*neg_leu<mode>" |
11840 | [(set (match_operand:P 0 "gpc_reg_operand" "=r") | |
11841 | (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r") | |
11842 | (match_operand:P 2 "reg_or_short_operand" "rI"))))] | |
11843 | "" | |
ca7f5001 | 11844 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
943c15ed DE |
11845 | [(set_attr "type" "three") |
11846 | (set_attr "length" "12")]) | |
1fd4e8c1 | 11847 | |
a2dba291 DE |
11848 | (define_insn "*and_neg_leu<mode>" |
11849 | [(set (match_operand:P 0 "gpc_reg_operand" "=&r") | |
11850 | (and:P (neg:P | |
11851 | (leu:P (match_operand:P 1 "gpc_reg_operand" "r") | |
11852 | (match_operand:P 2 "reg_or_short_operand" "rI"))) | |
11853 | (match_operand:P 3 "gpc_reg_operand" "r")))] | |
11854 | "" | |
097657c3 | 11855 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" |
943c15ed DE |
11856 | [(set_attr "type" "three") |
11857 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
11858 | |
11859 | (define_insn "" | |
9ebbca7d | 11860 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11861 | (compare:CC |
11862 | (and:SI (neg:SI | |
9ebbca7d GK |
11863 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11864 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11865 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11866 | (const_int 0))) |
9ebbca7d | 11867 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 11868 | "TARGET_32BIT" |
9ebbca7d GK |
11869 | "@ |
11870 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
11871 | #" | |
11872 | [(set_attr "type" "compare") | |
11873 | (set_attr "length" "12,16")]) | |
11874 | ||
11875 | (define_split | |
11876 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11877 | (compare:CC | |
11878 | (and:SI (neg:SI | |
11879 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11880 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11881 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11882 | (const_int 0))) | |
11883 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11884 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 11885 | [(set (match_dup 4) |
097657c3 AM |
11886 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) |
11887 | (match_dup 3))) | |
9ebbca7d GK |
11888 | (set (match_dup 0) |
11889 | (compare:CC (match_dup 4) | |
11890 | (const_int 0)))] | |
11891 | "") | |
1fd4e8c1 RK |
11892 | |
11893 | (define_insn "" | |
097657c3 | 11894 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11895 | (compare:CC |
11896 | (and:SI (neg:SI | |
9ebbca7d GK |
11897 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11898 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11899 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11900 | (const_int 0))) |
097657c3 AM |
11901 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
11902 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 11903 | "TARGET_32BIT" |
9ebbca7d | 11904 | "@ |
097657c3 | 11905 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
9ebbca7d | 11906 | #" |
b19003d8 | 11907 | [(set_attr "type" "compare") |
9ebbca7d GK |
11908 | (set_attr "length" "12,16")]) |
11909 | ||
11910 | (define_split | |
097657c3 | 11911 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11912 | (compare:CC |
11913 | (and:SI (neg:SI | |
11914 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11915 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11916 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11917 | (const_int 0))) | |
11918 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 11919 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 11920 | "TARGET_32BIT && reload_completed" |
097657c3 AM |
11921 | [(set (match_dup 0) |
11922 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) | |
11923 | (match_dup 3))) | |
11924 | (set (match_dup 4) | |
9ebbca7d GK |
11925 | (compare:CC (match_dup 0) |
11926 | (const_int 0)))] | |
11927 | "") | |
1fd4e8c1 RK |
11928 | |
11929 | (define_insn "" | |
cd2b37d9 RK |
11930 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11931 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11932 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 11933 | "TARGET_POWER" |
7f340546 | 11934 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11935 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11936 | |
11937 | (define_insn "" | |
9ebbca7d | 11938 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11939 | (compare:CC |
9ebbca7d GK |
11940 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11941 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11942 | (const_int 0))) |
9ebbca7d | 11943 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11944 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 11945 | "TARGET_POWER" |
9ebbca7d GK |
11946 | "@ |
11947 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
11948 | #" | |
29ae5b89 | 11949 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11950 | (set_attr "length" "12,16")]) |
11951 | ||
11952 | (define_split | |
11953 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11954 | (compare:CC | |
11955 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11956 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11957 | (const_int 0))) | |
11958 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11959 | (lt:SI (match_dup 1) (match_dup 2)))] | |
11960 | "TARGET_POWER && reload_completed" | |
11961 | [(set (match_dup 0) | |
11962 | (lt:SI (match_dup 1) (match_dup 2))) | |
11963 | (set (match_dup 3) | |
11964 | (compare:CC (match_dup 0) | |
11965 | (const_int 0)))] | |
11966 | "") | |
1fd4e8c1 RK |
11967 | |
11968 | (define_insn "" | |
097657c3 | 11969 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 11970 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11971 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 11972 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 11973 | "TARGET_POWER" |
097657c3 | 11974 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 11975 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11976 | |
11977 | (define_insn "" | |
9ebbca7d | 11978 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11979 | (compare:CC |
9ebbca7d GK |
11980 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11981 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11982 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11983 | (const_int 0))) |
9ebbca7d | 11984 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11985 | "TARGET_POWER" |
9ebbca7d GK |
11986 | "@ |
11987 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
11988 | #" | |
b19003d8 | 11989 | [(set_attr "type" "compare") |
9ebbca7d GK |
11990 | (set_attr "length" "12,16")]) |
11991 | ||
11992 | (define_split | |
11993 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11994 | (compare:CC | |
11995 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11996 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11997 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11998 | (const_int 0))) | |
11999 | (clobber (match_scratch:SI 4 ""))] | |
12000 | "TARGET_POWER && reload_completed" | |
12001 | [(set (match_dup 4) | |
12002 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12003 | (match_dup 3))) |
9ebbca7d GK |
12004 | (set (match_dup 0) |
12005 | (compare:CC (match_dup 4) | |
12006 | (const_int 0)))] | |
12007 | "") | |
1fd4e8c1 RK |
12008 | |
12009 | (define_insn "" | |
097657c3 | 12010 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12011 | (compare:CC |
9ebbca7d GK |
12012 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12013 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12014 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12015 | (const_int 0))) |
097657c3 AM |
12016 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12017 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12018 | "TARGET_POWER" |
9ebbca7d | 12019 | "@ |
097657c3 | 12020 | doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 12021 | #" |
b19003d8 | 12022 | [(set_attr "type" "compare") |
9ebbca7d GK |
12023 | (set_attr "length" "12,16")]) |
12024 | ||
12025 | (define_split | |
097657c3 | 12026 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12027 | (compare:CC |
12028 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12029 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12030 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12031 | (const_int 0))) | |
12032 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12033 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12034 | "TARGET_POWER && reload_completed" |
097657c3 | 12035 | [(set (match_dup 0) |
9ebbca7d | 12036 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12037 | (set (match_dup 4) |
9ebbca7d GK |
12038 | (compare:CC (match_dup 0) |
12039 | (const_int 0)))] | |
12040 | "") | |
1fd4e8c1 RK |
12041 | |
12042 | (define_insn "" | |
cd2b37d9 RK |
12043 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12044 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12045 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12046 | "TARGET_POWER" |
12047 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12048 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12049 | |
ce45ef46 DE |
12050 | (define_insn_and_split "*ltu<mode>" |
12051 | [(set (match_operand:P 0 "gpc_reg_operand" "=r,r") | |
12052 | (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r") | |
12053 | (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))] | |
12054 | "" | |
c0600ecd | 12055 | "#" |
ce45ef46 DE |
12056 | "" |
12057 | [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2)))) | |
12058 | (set (match_dup 0) (neg:P (match_dup 0)))] | |
c0600ecd | 12059 | "") |
1fd4e8c1 | 12060 | |
1e24ce83 | 12061 | (define_insn_and_split "*ltu<mode>_compare" |
9ebbca7d | 12062 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12063 | (compare:CC |
a2dba291 DE |
12064 | (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r") |
12065 | (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12066 | (const_int 0))) |
a2dba291 DE |
12067 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r") |
12068 | (ltu:P (match_dup 1) (match_dup 2)))] | |
12069 | "" | |
1e24ce83 DE |
12070 | "#" |
12071 | "" | |
12072 | [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2)))) | |
12073 | (parallel [(set (match_dup 3) | |
12074 | (compare:CC (neg:P (match_dup 0)) (const_int 0))) | |
12075 | (set (match_dup 0) (neg:P (match_dup 0)))])] | |
9ebbca7d | 12076 | "") |
1fd4e8c1 | 12077 | |
a2dba291 DE |
12078 | (define_insn_and_split "*plus_ltu<mode>" |
12079 | [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r") | |
12080 | (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r") | |
12081 | (match_operand:P 2 "reg_or_neg_short_operand" "r,P")) | |
1e24ce83 | 12082 | (match_operand:P 3 "reg_or_short_operand" "rI,rI")))] |
a2dba291 | 12083 | "" |
c0600ecd | 12084 | "#" |
04fa46cf | 12085 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" |
a2dba291 DE |
12086 | [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2)))) |
12087 | (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))] | |
c0600ecd | 12088 | "") |
1fd4e8c1 | 12089 | |
1e24ce83 | 12090 | (define_insn_and_split "*plus_ltu<mode>_compare" |
097657c3 | 12091 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12092 | (compare:CC |
1e24ce83 DE |
12093 | (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r") |
12094 | (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12095 | (match_operand:P 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12096 | (const_int 0))) |
1e24ce83 DE |
12097 | (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12098 | (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
12099 | "" | |
12100 | "#" | |
12101 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" | |
12102 | [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2)))) | |
12103 | (parallel [(set (match_dup 4) | |
12104 | (compare:CC (minus:P (match_dup 3) (match_dup 0)) | |
12105 | (const_int 0))) | |
12106 | (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])] | |
9ebbca7d | 12107 | "") |
1fd4e8c1 | 12108 | |
ce45ef46 DE |
12109 | (define_insn "*neg_ltu<mode>" |
12110 | [(set (match_operand:P 0 "gpc_reg_operand" "=r,r") | |
12111 | (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r") | |
12112 | (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))] | |
12113 | "" | |
c0600ecd DE |
12114 | "@ |
12115 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 | |
12116 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
943c15ed | 12117 | [(set_attr "type" "two") |
c0600ecd | 12118 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
12119 | |
12120 | (define_insn "" | |
cd2b37d9 RK |
12121 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12122 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
12123 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
12124 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
12125 | "TARGET_POWER" |
12126 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 12127 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12128 | |
9ebbca7d GK |
12129 | (define_insn "" |
12130 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 12131 | (compare:CC |
9ebbca7d GK |
12132 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12133 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12134 | (const_int 0))) |
9ebbca7d | 12135 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12136 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12137 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 12138 | "TARGET_POWER" |
9ebbca7d GK |
12139 | "@ |
12140 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
12141 | #" | |
12142 | [(set_attr "type" "compare") | |
12143 | (set_attr "length" "12,16")]) | |
12144 | ||
12145 | (define_split | |
12146 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12147 | (compare:CC | |
12148 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12149 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12150 | (const_int 0))) | |
12151 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12152 | (ge:SI (match_dup 1) (match_dup 2))) | |
12153 | (clobber (match_scratch:SI 3 ""))] | |
12154 | "TARGET_POWER && reload_completed" | |
12155 | [(parallel [(set (match_dup 0) | |
097657c3 AM |
12156 | (ge:SI (match_dup 1) (match_dup 2))) |
12157 | (clobber (match_dup 3))]) | |
9ebbca7d GK |
12158 | (set (match_dup 4) |
12159 | (compare:CC (match_dup 0) | |
12160 | (const_int 0)))] | |
12161 | "") | |
12162 | ||
1fd4e8c1 | 12163 | (define_insn "" |
097657c3 | 12164 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12165 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12166 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12167 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12168 | "TARGET_POWER" |
097657c3 | 12169 | "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" |
b19003d8 | 12170 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12171 | |
12172 | (define_insn "" | |
9ebbca7d | 12173 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12174 | (compare:CC |
9ebbca7d GK |
12175 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12176 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12177 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12178 | (const_int 0))) |
9ebbca7d | 12179 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12180 | "TARGET_POWER" |
9ebbca7d GK |
12181 | "@ |
12182 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
12183 | #" | |
b19003d8 | 12184 | [(set_attr "type" "compare") |
9ebbca7d GK |
12185 | (set_attr "length" "12,16")]) |
12186 | ||
12187 | (define_split | |
12188 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12189 | (compare:CC | |
12190 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12191 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12192 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12193 | (const_int 0))) | |
12194 | (clobber (match_scratch:SI 4 ""))] | |
12195 | "TARGET_POWER && reload_completed" | |
12196 | [(set (match_dup 4) | |
12197 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12198 | (match_dup 3))) |
9ebbca7d GK |
12199 | (set (match_dup 0) |
12200 | (compare:CC (match_dup 4) | |
12201 | (const_int 0)))] | |
12202 | "") | |
1fd4e8c1 RK |
12203 | |
12204 | (define_insn "" | |
097657c3 | 12205 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12206 | (compare:CC |
9ebbca7d GK |
12207 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12208 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12209 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12210 | (const_int 0))) |
097657c3 AM |
12211 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12212 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12213 | "TARGET_POWER" |
9ebbca7d | 12214 | "@ |
097657c3 | 12215 | doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
9ebbca7d | 12216 | #" |
b19003d8 | 12217 | [(set_attr "type" "compare") |
9ebbca7d GK |
12218 | (set_attr "length" "12,16")]) |
12219 | ||
12220 | (define_split | |
097657c3 | 12221 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12222 | (compare:CC |
12223 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12224 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12225 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12226 | (const_int 0))) | |
12227 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12228 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12229 | "TARGET_POWER && reload_completed" |
097657c3 | 12230 | [(set (match_dup 0) |
9ebbca7d | 12231 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12232 | (set (match_dup 4) |
9ebbca7d GK |
12233 | (compare:CC (match_dup 0) |
12234 | (const_int 0)))] | |
12235 | "") | |
1fd4e8c1 RK |
12236 | |
12237 | (define_insn "" | |
cd2b37d9 RK |
12238 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12239 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12240 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12241 | "TARGET_POWER" |
12242 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12243 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12244 | |
a2dba291 DE |
12245 | (define_insn "*geu<mode>" |
12246 | [(set (match_operand:P 0 "gpc_reg_operand" "=r,r") | |
12247 | (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") | |
12248 | (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))] | |
12249 | "" | |
1fd4e8c1 | 12250 | "@ |
ca7f5001 RK |
12251 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
12252 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
943c15ed DE |
12253 | [(set_attr "type" "three") |
12254 | (set_attr "length" "12")]) | |
1fd4e8c1 | 12255 | |
a2dba291 | 12256 | (define_insn "*geu<mode>_compare" |
9ebbca7d | 12257 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12258 | (compare:CC |
a2dba291 DE |
12259 | (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r") |
12260 | (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12261 | (const_int 0))) |
a2dba291 DE |
12262 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r") |
12263 | (geu:P (match_dup 1) (match_dup 2)))] | |
12264 | "" | |
1fd4e8c1 | 12265 | "@ |
ca7f5001 | 12266 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
12267 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
12268 | # | |
12269 | #" | |
b19003d8 | 12270 | [(set_attr "type" "compare") |
9ebbca7d GK |
12271 | (set_attr "length" "12,12,16,16")]) |
12272 | ||
12273 | (define_split | |
12274 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12275 | (compare:CC | |
a2dba291 DE |
12276 | (geu:P (match_operand:P 1 "gpc_reg_operand" "") |
12277 | (match_operand:P 2 "reg_or_neg_short_operand" "")) | |
9ebbca7d | 12278 | (const_int 0))) |
a2dba291 DE |
12279 | (set (match_operand:P 0 "gpc_reg_operand" "") |
12280 | (geu:P (match_dup 1) (match_dup 2)))] | |
12281 | "reload_completed" | |
9ebbca7d | 12282 | [(set (match_dup 0) |
a2dba291 | 12283 | (geu:P (match_dup 1) (match_dup 2))) |
9ebbca7d GK |
12284 | (set (match_dup 3) |
12285 | (compare:CC (match_dup 0) | |
12286 | (const_int 0)))] | |
12287 | "") | |
f9562f27 | 12288 | |
a2dba291 DE |
12289 | (define_insn "*plus_geu<mode>" |
12290 | [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r") | |
12291 | (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") | |
12292 | (match_operand:P 2 "reg_or_neg_short_operand" "r,P")) | |
12293 | (match_operand:P 3 "gpc_reg_operand" "r,r")))] | |
12294 | "" | |
1fd4e8c1 | 12295 | "@ |
80103f96 FS |
12296 | {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 |
12297 | {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" | |
943c15ed DE |
12298 | [(set_attr "type" "two") |
12299 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
12300 | |
12301 | (define_insn "" | |
9ebbca7d | 12302 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12303 | (compare:CC |
9ebbca7d GK |
12304 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12305 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12306 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12307 | (const_int 0))) |
9ebbca7d | 12308 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12309 | "TARGET_32BIT" |
1fd4e8c1 | 12310 | "@ |
ca7f5001 | 12311 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12312 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
12313 | # | |
12314 | #" | |
b19003d8 | 12315 | [(set_attr "type" "compare") |
9ebbca7d GK |
12316 | (set_attr "length" "8,8,12,12")]) |
12317 | ||
12318 | (define_split | |
12319 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12320 | (compare:CC | |
12321 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12322 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12323 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12324 | (const_int 0))) | |
12325 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12326 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12327 | [(set (match_dup 4) |
12328 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
12329 | (match_dup 3))) | |
12330 | (set (match_dup 0) | |
12331 | (compare:CC (match_dup 4) | |
12332 | (const_int 0)))] | |
12333 | "") | |
1fd4e8c1 RK |
12334 | |
12335 | (define_insn "" | |
097657c3 | 12336 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12337 | (compare:CC |
9ebbca7d GK |
12338 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12339 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12340 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12341 | (const_int 0))) |
097657c3 AM |
12342 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12343 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12344 | "TARGET_32BIT" |
1fd4e8c1 | 12345 | "@ |
097657c3 AM |
12346 | {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 |
12347 | {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12348 | # |
12349 | #" | |
b19003d8 | 12350 | [(set_attr "type" "compare") |
9ebbca7d GK |
12351 | (set_attr "length" "8,8,12,12")]) |
12352 | ||
12353 | (define_split | |
097657c3 | 12354 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12355 | (compare:CC |
12356 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12357 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12358 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12359 | (const_int 0))) | |
12360 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12361 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12362 | "TARGET_32BIT && reload_completed" |
097657c3 | 12363 | [(set (match_dup 0) |
9ebbca7d | 12364 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12365 | (set (match_dup 4) |
9ebbca7d GK |
12366 | (compare:CC (match_dup 0) |
12367 | (const_int 0)))] | |
12368 | "") | |
1fd4e8c1 | 12369 | |
a2dba291 DE |
12370 | (define_insn "*neg_geu<mode>" |
12371 | [(set (match_operand:P 0 "gpc_reg_operand" "=r,r") | |
12372 | (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") | |
12373 | (match_operand:P 2 "reg_or_short_operand" "r,I"))))] | |
12374 | "" | |
1fd4e8c1 | 12375 | "@ |
ca7f5001 | 12376 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 12377 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
943c15ed DE |
12378 | [(set_attr "type" "three") |
12379 | (set_attr "length" "12")]) | |
1fd4e8c1 | 12380 | |
a2dba291 DE |
12381 | (define_insn "*and_neg_geu<mode>" |
12382 | [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r") | |
12383 | (and:P (neg:P | |
12384 | (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") | |
12385 | (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))) | |
12386 | (match_operand:P 3 "gpc_reg_operand" "r,r")))] | |
12387 | "" | |
1fd4e8c1 | 12388 | "@ |
097657c3 AM |
12389 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 |
12390 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" | |
943c15ed DE |
12391 | [(set_attr "type" "three") |
12392 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
12393 | |
12394 | (define_insn "" | |
9ebbca7d | 12395 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12396 | (compare:CC |
12397 | (and:SI (neg:SI | |
9ebbca7d GK |
12398 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12399 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12400 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12401 | (const_int 0))) |
9ebbca7d | 12402 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12403 | "TARGET_32BIT" |
1fd4e8c1 | 12404 | "@ |
ca7f5001 | 12405 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
12406 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
12407 | # | |
12408 | #" | |
b19003d8 | 12409 | [(set_attr "type" "compare") |
9ebbca7d GK |
12410 | (set_attr "length" "12,12,16,16")]) |
12411 | ||
12412 | (define_split | |
12413 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12414 | (compare:CC | |
12415 | (and:SI (neg:SI | |
12416 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12417 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12418 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12419 | (const_int 0))) | |
12420 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12421 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 12422 | [(set (match_dup 4) |
097657c3 AM |
12423 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) |
12424 | (match_dup 3))) | |
9ebbca7d GK |
12425 | (set (match_dup 0) |
12426 | (compare:CC (match_dup 4) | |
12427 | (const_int 0)))] | |
12428 | "") | |
1fd4e8c1 RK |
12429 | |
12430 | (define_insn "" | |
097657c3 | 12431 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12432 | (compare:CC |
12433 | (and:SI (neg:SI | |
9ebbca7d GK |
12434 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12435 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12436 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12437 | (const_int 0))) |
097657c3 AM |
12438 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12439 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 12440 | "TARGET_32BIT" |
1fd4e8c1 | 12441 | "@ |
097657c3 AM |
12442 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
12443 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 | |
9ebbca7d GK |
12444 | # |
12445 | #" | |
b19003d8 | 12446 | [(set_attr "type" "compare") |
9ebbca7d GK |
12447 | (set_attr "length" "12,12,16,16")]) |
12448 | ||
12449 | (define_split | |
097657c3 | 12450 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12451 | (compare:CC |
12452 | (and:SI (neg:SI | |
12453 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12454 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12455 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12456 | (const_int 0))) | |
12457 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12458 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 12459 | "TARGET_32BIT && reload_completed" |
097657c3 | 12460 | [(set (match_dup 0) |
9ebbca7d | 12461 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
097657c3 | 12462 | (set (match_dup 4) |
9ebbca7d GK |
12463 | (compare:CC (match_dup 0) |
12464 | (const_int 0)))] | |
12465 | "") | |
1fd4e8c1 | 12466 | |
1fd4e8c1 | 12467 | (define_insn "" |
cd2b37d9 RK |
12468 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12469 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12470 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
12471 | "TARGET_POWER" |
12472 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 12473 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12474 | |
12475 | (define_insn "" | |
9ebbca7d | 12476 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12477 | (compare:CC |
9ebbca7d GK |
12478 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12479 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 12480 | (const_int 0))) |
9ebbca7d | 12481 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12482 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12483 | "TARGET_POWER" |
9ebbca7d GK |
12484 | "@ |
12485 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12486 | #" | |
29ae5b89 | 12487 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12488 | (set_attr "length" "12,16")]) |
12489 | ||
12490 | (define_split | |
12491 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12492 | (compare:CC | |
12493 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12494 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12495 | (const_int 0))) | |
12496 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12497 | (gt:SI (match_dup 1) (match_dup 2)))] | |
12498 | "TARGET_POWER && reload_completed" | |
12499 | [(set (match_dup 0) | |
12500 | (gt:SI (match_dup 1) (match_dup 2))) | |
12501 | (set (match_dup 3) | |
12502 | (compare:CC (match_dup 0) | |
12503 | (const_int 0)))] | |
12504 | "") | |
1fd4e8c1 | 12505 | |
d0515b39 | 12506 | (define_insn "*plus_gt0<mode>" |
a2dba291 DE |
12507 | [(set (match_operand:P 0 "gpc_reg_operand" "=&r") |
12508 | (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r") | |
12509 | (const_int 0)) | |
12510 | (match_operand:P 2 "gpc_reg_operand" "r")))] | |
12511 | "" | |
80103f96 | 12512 | "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" |
943c15ed DE |
12513 | [(set_attr "type" "three") |
12514 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
12515 | |
12516 | (define_insn "" | |
9ebbca7d | 12517 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12518 | (compare:CC |
9ebbca7d | 12519 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12520 | (const_int 0)) |
9ebbca7d | 12521 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 12522 | (const_int 0))) |
9ebbca7d | 12523 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 12524 | "TARGET_32BIT" |
9ebbca7d GK |
12525 | "@ |
12526 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
12527 | #" | |
b19003d8 | 12528 | [(set_attr "type" "compare") |
9ebbca7d GK |
12529 | (set_attr "length" "12,16")]) |
12530 | ||
12531 | (define_split | |
12532 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12533 | (compare:CC | |
12534 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12535 | (const_int 0)) | |
12536 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
12537 | (const_int 0))) | |
12538 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 12539 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12540 | [(set (match_dup 3) |
12541 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
12542 | (match_dup 2))) | |
12543 | (set (match_dup 0) | |
12544 | (compare:CC (match_dup 3) | |
12545 | (const_int 0)))] | |
12546 | "") | |
1fd4e8c1 | 12547 | |
f9562f27 | 12548 | (define_insn "" |
9ebbca7d | 12549 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 12550 | (compare:CC |
9ebbca7d | 12551 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 12552 | (const_int 0)) |
9ebbca7d | 12553 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 12554 | (const_int 0))) |
9ebbca7d | 12555 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 12556 | "TARGET_64BIT" |
9ebbca7d GK |
12557 | "@ |
12558 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
12559 | #" | |
f9562f27 | 12560 | [(set_attr "type" "compare") |
9ebbca7d GK |
12561 | (set_attr "length" "12,16")]) |
12562 | ||
12563 | (define_split | |
12564 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12565 | (compare:CC | |
12566 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12567 | (const_int 0)) | |
12568 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12569 | (const_int 0))) | |
12570 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 12571 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12572 | [(set (match_dup 3) |
12573 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
097657c3 | 12574 | (match_dup 2))) |
9ebbca7d GK |
12575 | (set (match_dup 0) |
12576 | (compare:CC (match_dup 3) | |
12577 | (const_int 0)))] | |
12578 | "") | |
f9562f27 | 12579 | |
1fd4e8c1 | 12580 | (define_insn "" |
097657c3 | 12581 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
9ebbca7d GK |
12582 | (compare:CC |
12583 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12584 | (const_int 0)) | |
12585 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
12586 | (const_int 0))) | |
097657c3 AM |
12587 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12588 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 12589 | "TARGET_32BIT" |
9ebbca7d | 12590 | "@ |
097657c3 | 12591 | {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 |
9ebbca7d GK |
12592 | #" |
12593 | [(set_attr "type" "compare") | |
12594 | (set_attr "length" "12,16")]) | |
12595 | ||
12596 | (define_split | |
097657c3 | 12597 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
1fd4e8c1 | 12598 | (compare:CC |
9ebbca7d | 12599 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 12600 | (const_int 0)) |
9ebbca7d | 12601 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 12602 | (const_int 0))) |
9ebbca7d | 12603 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
097657c3 | 12604 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 12605 | "TARGET_32BIT && reload_completed" |
097657c3 | 12606 | [(set (match_dup 0) |
9ebbca7d | 12607 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 12608 | (set (match_dup 3) |
9ebbca7d GK |
12609 | (compare:CC (match_dup 0) |
12610 | (const_int 0)))] | |
12611 | "") | |
1fd4e8c1 | 12612 | |
f9562f27 | 12613 | (define_insn "" |
097657c3 | 12614 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12615 | (compare:CC |
9ebbca7d | 12616 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 12617 | (const_int 0)) |
9ebbca7d | 12618 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 12619 | (const_int 0))) |
097657c3 AM |
12620 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
12621 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 12622 | "TARGET_64BIT" |
9ebbca7d | 12623 | "@ |
097657c3 | 12624 | addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 |
9ebbca7d | 12625 | #" |
f9562f27 | 12626 | [(set_attr "type" "compare") |
9ebbca7d GK |
12627 | (set_attr "length" "12,16")]) |
12628 | ||
12629 | (define_split | |
097657c3 | 12630 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12631 | (compare:CC |
12632 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12633 | (const_int 0)) | |
12634 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12635 | (const_int 0))) | |
12636 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 12637 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 12638 | "TARGET_64BIT && reload_completed" |
097657c3 | 12639 | [(set (match_dup 0) |
9ebbca7d | 12640 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 12641 | (set (match_dup 3) |
9ebbca7d GK |
12642 | (compare:CC (match_dup 0) |
12643 | (const_int 0)))] | |
12644 | "") | |
f9562f27 | 12645 | |
1fd4e8c1 | 12646 | (define_insn "" |
097657c3 | 12647 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12648 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12649 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
097657c3 | 12650 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12651 | "TARGET_POWER" |
097657c3 | 12652 | "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 12653 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12654 | |
12655 | (define_insn "" | |
9ebbca7d | 12656 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12657 | (compare:CC |
9ebbca7d GK |
12658 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12659 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
12660 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12661 | (const_int 0))) |
9ebbca7d | 12662 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12663 | "TARGET_POWER" |
9ebbca7d GK |
12664 | "@ |
12665 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12666 | #" | |
b19003d8 | 12667 | [(set_attr "type" "compare") |
9ebbca7d GK |
12668 | (set_attr "length" "12,16")]) |
12669 | ||
12670 | (define_split | |
12671 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12672 | (compare:CC | |
12673 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12674 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12675 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12676 | (const_int 0))) | |
12677 | (clobber (match_scratch:SI 4 ""))] | |
12678 | "TARGET_POWER && reload_completed" | |
12679 | [(set (match_dup 4) | |
097657c3 | 12680 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d GK |
12681 | (set (match_dup 0) |
12682 | (compare:CC (match_dup 4) | |
12683 | (const_int 0)))] | |
12684 | "") | |
1fd4e8c1 RK |
12685 | |
12686 | (define_insn "" | |
097657c3 | 12687 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12688 | (compare:CC |
9ebbca7d GK |
12689 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12690 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
12691 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12692 | (const_int 0))) |
097657c3 AM |
12693 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12694 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12695 | "TARGET_POWER" |
9ebbca7d | 12696 | "@ |
097657c3 | 12697 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 12698 | #" |
b19003d8 | 12699 | [(set_attr "type" "compare") |
9ebbca7d GK |
12700 | (set_attr "length" "12,16")]) |
12701 | ||
12702 | (define_split | |
097657c3 | 12703 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12704 | (compare:CC |
12705 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12706 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12707 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12708 | (const_int 0))) | |
12709 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12710 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12711 | "TARGET_POWER && reload_completed" |
097657c3 | 12712 | [(set (match_dup 0) |
9ebbca7d | 12713 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12714 | (set (match_dup 4) |
9ebbca7d GK |
12715 | (compare:CC (match_dup 0) |
12716 | (const_int 0)))] | |
12717 | "") | |
1fd4e8c1 | 12718 | |
1fd4e8c1 | 12719 | (define_insn "" |
cd2b37d9 RK |
12720 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12721 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12722 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
12723 | "TARGET_POWER" |
12724 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12725 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12726 | |
ce45ef46 DE |
12727 | (define_insn_and_split "*gtu<mode>" |
12728 | [(set (match_operand:P 0 "gpc_reg_operand" "=r") | |
12729 | (gtu:P (match_operand:P 1 "gpc_reg_operand" "r") | |
12730 | (match_operand:P 2 "reg_or_short_operand" "rI")))] | |
12731 | "" | |
c0600ecd | 12732 | "#" |
ce45ef46 DE |
12733 | "" |
12734 | [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2)))) | |
12735 | (set (match_dup 0) (neg:P (match_dup 0)))] | |
c0600ecd | 12736 | "") |
f9562f27 | 12737 | |
1e24ce83 | 12738 | (define_insn_and_split "*gtu<mode>_compare" |
9ebbca7d | 12739 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12740 | (compare:CC |
a2dba291 DE |
12741 | (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r") |
12742 | (match_operand:P 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12743 | (const_int 0))) |
a2dba291 DE |
12744 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r") |
12745 | (gtu:P (match_dup 1) (match_dup 2)))] | |
12746 | "" | |
1e24ce83 DE |
12747 | "#" |
12748 | "" | |
12749 | [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2)))) | |
12750 | (parallel [(set (match_dup 3) | |
12751 | (compare:CC (neg:P (match_dup 0)) (const_int 0))) | |
12752 | (set (match_dup 0) (neg:P (match_dup 0)))])] | |
9ebbca7d | 12753 | "") |
f9562f27 | 12754 | |
1e24ce83 | 12755 | (define_insn_and_split "*plus_gtu<mode>" |
a2dba291 DE |
12756 | [(set (match_operand:P 0 "gpc_reg_operand" "=&r") |
12757 | (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r") | |
12758 | (match_operand:P 2 "reg_or_short_operand" "rI")) | |
12759 | (match_operand:P 3 "reg_or_short_operand" "rI")))] | |
12760 | "" | |
c0600ecd | 12761 | "#" |
04fa46cf | 12762 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" |
a2dba291 DE |
12763 | [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2)))) |
12764 | (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))] | |
c0600ecd | 12765 | "") |
f9562f27 | 12766 | |
1e24ce83 | 12767 | (define_insn_and_split "*plus_gtu<mode>_compare" |
097657c3 | 12768 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12769 | (compare:CC |
1e24ce83 DE |
12770 | (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r") |
12771 | (match_operand:P 2 "reg_or_short_operand" "I,r,I,r")) | |
12772 | (match_operand:P 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 12773 | (const_int 0))) |
1e24ce83 DE |
12774 | (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12775 | (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
12776 | "" | |
12777 | "#" | |
12778 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" | |
12779 | [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2)))) | |
12780 | (parallel [(set (match_dup 4) | |
12781 | (compare:CC (minus:P (match_dup 3) (match_dup 0)) | |
12782 | (const_int 0))) | |
12783 | (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])] | |
9ebbca7d | 12784 | "") |
f9562f27 | 12785 | |
ce45ef46 DE |
12786 | (define_insn "*neg_gtu<mode>" |
12787 | [(set (match_operand:P 0 "gpc_reg_operand" "=r") | |
12788 | (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r") | |
12789 | (match_operand:P 2 "reg_or_short_operand" "rI"))))] | |
12790 | "" | |
ca7f5001 | 12791 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
943c15ed | 12792 | [(set_attr "type" "two") |
c0600ecd | 12793 | (set_attr "length" "8")]) |
f9562f27 | 12794 | |
1fd4e8c1 RK |
12795 | \f |
12796 | ;; Define both directions of branch and return. If we need a reload | |
12797 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
12798 | ;; register CC value to there. | |
12799 | ||
12800 | (define_insn "" | |
12801 | [(set (pc) | |
12802 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
12803 | [(match_operand 2 | |
b54cf83a | 12804 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
12805 | (const_int 0)]) |
12806 | (label_ref (match_operand 0 "" "")) | |
12807 | (pc)))] | |
12808 | "" | |
b19003d8 RK |
12809 | "* |
12810 | { | |
12a4e8c5 | 12811 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
12812 | }" |
12813 | [(set_attr "type" "branch")]) | |
12814 | ||
1fd4e8c1 RK |
12815 | (define_insn "" |
12816 | [(set (pc) | |
12817 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
12818 | [(match_operand 1 | |
b54cf83a | 12819 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
12820 | (const_int 0)]) |
12821 | (return) | |
12822 | (pc)))] | |
12823 | "direct_return ()" | |
12a4e8c5 GK |
12824 | "* |
12825 | { | |
12826 | return output_cbranch (operands[0], NULL, 0, insn); | |
12827 | }" | |
b7ff3d82 | 12828 | [(set_attr "type" "branch") |
39a10a29 | 12829 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
12830 | |
12831 | (define_insn "" | |
12832 | [(set (pc) | |
12833 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
12834 | [(match_operand 2 | |
b54cf83a | 12835 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
12836 | (const_int 0)]) |
12837 | (pc) | |
12838 | (label_ref (match_operand 0 "" ""))))] | |
12839 | "" | |
b19003d8 RK |
12840 | "* |
12841 | { | |
12a4e8c5 | 12842 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
12843 | }" |
12844 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
12845 | |
12846 | (define_insn "" | |
12847 | [(set (pc) | |
12848 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
12849 | [(match_operand 1 | |
b54cf83a | 12850 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
12851 | (const_int 0)]) |
12852 | (pc) | |
12853 | (return)))] | |
12854 | "direct_return ()" | |
12a4e8c5 GK |
12855 | "* |
12856 | { | |
12857 | return output_cbranch (operands[0], NULL, 1, insn); | |
12858 | }" | |
b7ff3d82 | 12859 | [(set_attr "type" "branch") |
39a10a29 GK |
12860 | (set_attr "length" "4")]) |
12861 | ||
12862 | ;; Logic on condition register values. | |
12863 | ||
12864 | ; This pattern matches things like | |
12865 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
12866 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
12867 | ; (const_int 1))) | |
12868 | ; which are generated by the branch logic. | |
b54cf83a | 12869 | ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB) |
39a10a29 | 12870 | |
423c1189 | 12871 | (define_insn "*cceq_ior_compare" |
b54cf83a | 12872 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 12873 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" |
b54cf83a | 12874 | [(match_operator:SI 2 |
39a10a29 GK |
12875 | "branch_positive_comparison_operator" |
12876 | [(match_operand 3 | |
b54cf83a | 12877 | "cc_reg_operand" "y,y") |
39a10a29 | 12878 | (const_int 0)]) |
b54cf83a | 12879 | (match_operator:SI 4 |
39a10a29 GK |
12880 | "branch_positive_comparison_operator" |
12881 | [(match_operand 5 | |
b54cf83a | 12882 | "cc_reg_operand" "0,y") |
39a10a29 GK |
12883 | (const_int 0)])]) |
12884 | (const_int 1)))] | |
24fab1d3 | 12885 | "" |
39a10a29 | 12886 | "cr%q1 %E0,%j2,%j4" |
b54cf83a | 12887 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
12888 | |
12889 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
12890 | ; Because ~1 has all but the low bit set. | |
12891 | (define_insn "" | |
b54cf83a | 12892 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 12893 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" |
b54cf83a | 12894 | [(not:SI (match_operator:SI 2 |
39a10a29 GK |
12895 | "branch_positive_comparison_operator" |
12896 | [(match_operand 3 | |
b54cf83a | 12897 | "cc_reg_operand" "y,y") |
39a10a29 GK |
12898 | (const_int 0)])) |
12899 | (match_operator:SI 4 | |
12900 | "branch_positive_comparison_operator" | |
12901 | [(match_operand 5 | |
b54cf83a | 12902 | "cc_reg_operand" "0,y") |
39a10a29 GK |
12903 | (const_int 0)])]) |
12904 | (const_int -1)))] | |
12905 | "" | |
12906 | "cr%q1 %E0,%j2,%j4" | |
b54cf83a | 12907 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 | 12908 | |
423c1189 | 12909 | (define_insn "*cceq_rev_compare" |
b54cf83a | 12910 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
6c873122 | 12911 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 12912 | "branch_positive_comparison_operator" |
6c873122 | 12913 | [(match_operand 2 |
b54cf83a | 12914 | "cc_reg_operand" "0,y") |
39a10a29 GK |
12915 | (const_int 0)]) |
12916 | (const_int 0)))] | |
423c1189 | 12917 | "" |
251b3667 | 12918 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
b54cf83a | 12919 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
12920 | |
12921 | ;; If we are comparing the result of two comparisons, this can be done | |
12922 | ;; using creqv or crxor. | |
12923 | ||
12924 | (define_insn_and_split "" | |
12925 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12926 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
12927 | [(match_operand 2 "cc_reg_operand" "y") | |
12928 | (const_int 0)]) | |
12929 | (match_operator 3 "branch_comparison_operator" | |
12930 | [(match_operand 4 "cc_reg_operand" "y") | |
12931 | (const_int 0)])))] | |
12932 | "" | |
12933 | "#" | |
12934 | "" | |
12935 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
12936 | (match_dup 5)))] | |
12937 | " | |
12938 | { | |
12939 | int positive_1, positive_2; | |
12940 | ||
364849ee DE |
12941 | positive_1 = branch_positive_comparison_operator (operands[1], |
12942 | GET_MODE (operands[1])); | |
12943 | positive_2 = branch_positive_comparison_operator (operands[3], | |
12944 | GET_MODE (operands[3])); | |
39a10a29 GK |
12945 | |
12946 | if (! positive_1) | |
1c563bed | 12947 | operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]), |
0f4c242b KH |
12948 | GET_CODE (operands[1])), |
12949 | SImode, | |
12950 | operands[2], const0_rtx); | |
39a10a29 | 12951 | else if (GET_MODE (operands[1]) != SImode) |
0f4c242b KH |
12952 | operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, |
12953 | operands[2], const0_rtx); | |
39a10a29 GK |
12954 | |
12955 | if (! positive_2) | |
1c563bed | 12956 | operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]), |
0f4c242b KH |
12957 | GET_CODE (operands[3])), |
12958 | SImode, | |
12959 | operands[4], const0_rtx); | |
39a10a29 | 12960 | else if (GET_MODE (operands[3]) != SImode) |
0f4c242b KH |
12961 | operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
12962 | operands[4], const0_rtx); | |
39a10a29 GK |
12963 | |
12964 | if (positive_1 == positive_2) | |
251b3667 DE |
12965 | { |
12966 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
12967 | operands[5] = constm1_rtx; | |
12968 | } | |
12969 | else | |
12970 | { | |
12971 | operands[5] = const1_rtx; | |
12972 | } | |
39a10a29 | 12973 | }") |
1fd4e8c1 RK |
12974 | |
12975 | ;; Unconditional branch and return. | |
12976 | ||
12977 | (define_insn "jump" | |
12978 | [(set (pc) | |
12979 | (label_ref (match_operand 0 "" "")))] | |
12980 | "" | |
b7ff3d82 DE |
12981 | "b %l0" |
12982 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
12983 | |
12984 | (define_insn "return" | |
12985 | [(return)] | |
12986 | "direct_return ()" | |
324e52cc TG |
12987 | "{br|blr}" |
12988 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 12989 | |
0ad91047 | 12990 | (define_expand "indirect_jump" |
4ae234b0 | 12991 | [(set (pc) (match_operand 0 "register_operand" ""))]) |
0ad91047 | 12992 | |
4ae234b0 GK |
12993 | (define_insn "*indirect_jump<mode>" |
12994 | [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))] | |
12995 | "" | |
b92b324d DE |
12996 | "@ |
12997 | bctr | |
12998 | {br|blr}" | |
324e52cc | 12999 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 RK |
13000 | |
13001 | ;; Table jump for switch statements: | |
13002 | (define_expand "tablejump" | |
e6ca2c17 DE |
13003 | [(use (match_operand 0 "" "")) |
13004 | (use (label_ref (match_operand 1 "" "")))] | |
13005 | "" | |
13006 | " | |
13007 | { | |
13008 | if (TARGET_32BIT) | |
13009 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
13010 | else | |
13011 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
13012 | DONE; | |
13013 | }") | |
13014 | ||
13015 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
13016 | [(set (match_dup 3) |
13017 | (plus:SI (match_operand:SI 0 "" "") | |
13018 | (match_dup 2))) | |
13019 | (parallel [(set (pc) (match_dup 3)) | |
13020 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13021 | "TARGET_32BIT" |
1fd4e8c1 RK |
13022 | " |
13023 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 13024 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
13025 | operands[3] = gen_reg_rtx (SImode); |
13026 | }") | |
13027 | ||
e6ca2c17 | 13028 | (define_expand "tablejumpdi" |
6ae08853 | 13029 | [(set (match_dup 4) |
9ebbca7d GK |
13030 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) |
13031 | (set (match_dup 3) | |
13032 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
13033 | (match_dup 2))) |
13034 | (parallel [(set (pc) (match_dup 3)) | |
13035 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13036 | "TARGET_64BIT" |
e6ca2c17 | 13037 | " |
9ebbca7d | 13038 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 13039 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 13040 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
13041 | }") |
13042 | ||
ce45ef46 | 13043 | (define_insn "*tablejump<mode>_internal1" |
1fd4e8c1 | 13044 | [(set (pc) |
4ae234b0 | 13045 | (match_operand:P 0 "register_operand" "c,*l")) |
1fd4e8c1 | 13046 | (use (label_ref (match_operand 1 "" "")))] |
4ae234b0 | 13047 | "" |
c859cda6 DJ |
13048 | "@ |
13049 | bctr | |
13050 | {br|blr}" | |
a6845123 | 13051 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 RK |
13052 | |
13053 | (define_insn "nop" | |
13054 | [(const_int 0)] | |
13055 | "" | |
ca7f5001 | 13056 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 13057 | \f |
7e69e155 | 13058 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
13059 | ;; so loop.c knows what to generate. |
13060 | ||
5527bf14 RH |
13061 | (define_expand "doloop_end" |
13062 | [(use (match_operand 0 "" "")) ; loop pseudo | |
13063 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
13064 | (use (match_operand 2 "" "")) ; max iterations | |
13065 | (use (match_operand 3 "" "")) ; loop level | |
13066 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
13067 | "" |
13068 | " | |
13069 | { | |
5527bf14 RH |
13070 | /* Only use this on innermost loops. */ |
13071 | if (INTVAL (operands[3]) > 1) | |
13072 | FAIL; | |
683bdff7 | 13073 | if (TARGET_64BIT) |
5527bf14 RH |
13074 | { |
13075 | if (GET_MODE (operands[0]) != DImode) | |
13076 | FAIL; | |
13077 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
13078 | } | |
0ad91047 | 13079 | else |
5527bf14 RH |
13080 | { |
13081 | if (GET_MODE (operands[0]) != SImode) | |
13082 | FAIL; | |
13083 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
13084 | } | |
0ad91047 DE |
13085 | DONE; |
13086 | }") | |
13087 | ||
4ae234b0 | 13088 | (define_expand "ctr<mode>" |
3cb999d8 | 13089 | [(parallel [(set (pc) |
4ae234b0 | 13090 | (if_then_else (ne (match_operand:P 0 "register_operand" "") |
3cb999d8 DE |
13091 | (const_int 1)) |
13092 | (label_ref (match_operand 1 "" "")) | |
13093 | (pc))) | |
b6c9286a | 13094 | (set (match_dup 0) |
4ae234b0 | 13095 | (plus:P (match_dup 0) |
b6c9286a | 13096 | (const_int -1))) |
5f81043f | 13097 | (clobber (match_scratch:CC 2 "")) |
4ae234b0 GK |
13098 | (clobber (match_scratch:P 3 ""))])] |
13099 | "" | |
61c07d3c | 13100 | "") |
c225ba7b | 13101 | |
1fd4e8c1 RK |
13102 | ;; We need to be able to do this for any operand, including MEM, or we |
13103 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 13104 | ;; JUMP_INSNs. |
0ad91047 | 13105 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
13106 | ;; label MUST be operand 0. |
13107 | ||
4ae234b0 | 13108 | (define_insn "*ctr<mode>_internal1" |
0ad91047 | 13109 | [(set (pc) |
4ae234b0 | 13110 | (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
13111 | (const_int 1)) |
13112 | (label_ref (match_operand 0 "" "")) | |
13113 | (pc))) | |
4ae234b0 GK |
13114 | (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
13115 | (plus:P (match_dup 1) | |
0ad91047 | 13116 | (const_int -1))) |
43b68ce5 | 13117 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
4ae234b0 GK |
13118 | (clobber (match_scratch:P 4 "=X,X,&r,r"))] |
13119 | "" | |
0ad91047 DE |
13120 | "* |
13121 | { | |
13122 | if (which_alternative != 0) | |
13123 | return \"#\"; | |
856a6884 | 13124 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13125 | return \"{bdn|bdnz} %l0\"; |
13126 | else | |
f607bc57 | 13127 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
13128 | }" |
13129 | [(set_attr "type" "branch") | |
5a195cb5 | 13130 | (set_attr "length" "*,12,16,16")]) |
0ad91047 | 13131 | |
4ae234b0 | 13132 | (define_insn "*ctr<mode>_internal2" |
0ad91047 | 13133 | [(set (pc) |
4ae234b0 | 13134 | (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
13135 | (const_int 1)) |
13136 | (pc) | |
13137 | (label_ref (match_operand 0 "" "")))) | |
4ae234b0 GK |
13138 | (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
13139 | (plus:P (match_dup 1) | |
0ad91047 | 13140 | (const_int -1))) |
43b68ce5 | 13141 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
4ae234b0 GK |
13142 | (clobber (match_scratch:P 4 "=X,X,&r,r"))] |
13143 | "" | |
5f81043f RK |
13144 | "* |
13145 | { | |
13146 | if (which_alternative != 0) | |
13147 | return \"#\"; | |
856a6884 | 13148 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
13149 | return \"bdz %l0\"; |
13150 | else | |
f607bc57 | 13151 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
13152 | }" |
13153 | [(set_attr "type" "branch") | |
5a195cb5 | 13154 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 13155 | |
0ad91047 DE |
13156 | ;; Similar but use EQ |
13157 | ||
4ae234b0 | 13158 | (define_insn "*ctr<mode>_internal5" |
5f81043f | 13159 | [(set (pc) |
4ae234b0 | 13160 | (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r") |
1fd4e8c1 | 13161 | (const_int 1)) |
a6845123 | 13162 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13163 | (pc))) |
4ae234b0 GK |
13164 | (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
13165 | (plus:P (match_dup 1) | |
0ad91047 | 13166 | (const_int -1))) |
43b68ce5 | 13167 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
4ae234b0 GK |
13168 | (clobber (match_scratch:P 4 "=X,X,&r,r"))] |
13169 | "" | |
0ad91047 DE |
13170 | "* |
13171 | { | |
13172 | if (which_alternative != 0) | |
13173 | return \"#\"; | |
856a6884 | 13174 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13175 | return \"bdz %l0\"; |
13176 | else | |
f607bc57 | 13177 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
13178 | }" |
13179 | [(set_attr "type" "branch") | |
5a195cb5 | 13180 | (set_attr "length" "*,12,16,16")]) |
0ad91047 | 13181 | |
4ae234b0 | 13182 | (define_insn "*ctr<mode>_internal6" |
0ad91047 | 13183 | [(set (pc) |
4ae234b0 | 13184 | (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
13185 | (const_int 1)) |
13186 | (pc) | |
13187 | (label_ref (match_operand 0 "" "")))) | |
4ae234b0 GK |
13188 | (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
13189 | (plus:P (match_dup 1) | |
0ad91047 | 13190 | (const_int -1))) |
43b68ce5 | 13191 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
4ae234b0 GK |
13192 | (clobber (match_scratch:P 4 "=X,X,&r,r"))] |
13193 | "" | |
5f81043f RK |
13194 | "* |
13195 | { | |
13196 | if (which_alternative != 0) | |
13197 | return \"#\"; | |
856a6884 | 13198 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
13199 | return \"{bdn|bdnz} %l0\"; |
13200 | else | |
f607bc57 | 13201 | return \"bdz $+8\;b %l0\"; |
5f81043f RK |
13202 | }" |
13203 | [(set_attr "type" "branch") | |
5a195cb5 | 13204 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 13205 | |
0ad91047 DE |
13206 | ;; Now the splitters if we could not allocate the CTR register |
13207 | ||
1fd4e8c1 RK |
13208 | (define_split |
13209 | [(set (pc) | |
13210 | (if_then_else (match_operator 2 "comparison_operator" | |
4ae234b0 | 13211 | [(match_operand:P 1 "gpc_reg_operand" "") |
0ad91047 | 13212 | (const_int 1)]) |
61c07d3c DE |
13213 | (match_operand 5 "" "") |
13214 | (match_operand 6 "" ""))) | |
4ae234b0 GK |
13215 | (set (match_operand:P 0 "gpc_reg_operand" "") |
13216 | (plus:P (match_dup 1) (const_int -1))) | |
0ad91047 | 13217 | (clobber (match_scratch:CC 3 "")) |
4ae234b0 GK |
13218 | (clobber (match_scratch:P 4 ""))] |
13219 | "reload_completed" | |
0ad91047 | 13220 | [(parallel [(set (match_dup 3) |
4ae234b0 | 13221 | (compare:CC (plus:P (match_dup 1) |
0ad91047 DE |
13222 | (const_int -1)) |
13223 | (const_int 0))) | |
13224 | (set (match_dup 0) | |
4ae234b0 | 13225 | (plus:P (match_dup 1) |
0ad91047 | 13226 | (const_int -1)))]) |
61c07d3c DE |
13227 | (set (pc) (if_then_else (match_dup 7) |
13228 | (match_dup 5) | |
13229 | (match_dup 6)))] | |
0ad91047 | 13230 | " |
0f4c242b KH |
13231 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
13232 | operands[3], const0_rtx); }") | |
0ad91047 DE |
13233 | |
13234 | (define_split | |
13235 | [(set (pc) | |
13236 | (if_then_else (match_operator 2 "comparison_operator" | |
4ae234b0 | 13237 | [(match_operand:P 1 "gpc_reg_operand" "") |
0ad91047 | 13238 | (const_int 1)]) |
61c07d3c DE |
13239 | (match_operand 5 "" "") |
13240 | (match_operand 6 "" ""))) | |
4ae234b0 GK |
13241 | (set (match_operand:P 0 "nonimmediate_operand" "") |
13242 | (plus:P (match_dup 1) (const_int -1))) | |
0ad91047 | 13243 | (clobber (match_scratch:CC 3 "")) |
4ae234b0 GK |
13244 | (clobber (match_scratch:P 4 ""))] |
13245 | "reload_completed && ! gpc_reg_operand (operands[0], SImode)" | |
0ad91047 | 13246 | [(parallel [(set (match_dup 3) |
4ae234b0 | 13247 | (compare:CC (plus:P (match_dup 1) |
0ad91047 DE |
13248 | (const_int -1)) |
13249 | (const_int 0))) | |
13250 | (set (match_dup 4) | |
4ae234b0 | 13251 | (plus:P (match_dup 1) |
0ad91047 DE |
13252 | (const_int -1)))]) |
13253 | (set (match_dup 0) | |
13254 | (match_dup 4)) | |
61c07d3c DE |
13255 | (set (pc) (if_then_else (match_dup 7) |
13256 | (match_dup 5) | |
13257 | (match_dup 6)))] | |
0ad91047 | 13258 | " |
0f4c242b KH |
13259 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
13260 | operands[3], const0_rtx); }") | |
e0cd0770 JC |
13261 | \f |
13262 | (define_insn "trap" | |
13263 | [(trap_if (const_int 1) (const_int 0))] | |
13264 | "" | |
13265 | "{t 31,0,0|trap}") | |
13266 | ||
13267 | (define_expand "conditional_trap" | |
13268 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
13269 | [(match_dup 2) (match_dup 3)]) | |
13270 | (match_operand 1 "const_int_operand" ""))] | |
13271 | "" | |
13272 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
13273 | operands[2] = rs6000_compare_op0; | |
13274 | operands[3] = rs6000_compare_op1;") | |
13275 | ||
13276 | (define_insn "" | |
13277 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
4ae234b0 GK |
13278 | [(match_operand:GPR 1 "register_operand" "r") |
13279 | (match_operand:GPR 2 "reg_or_short_operand" "rI")]) | |
e0cd0770 JC |
13280 | (const_int 0))] |
13281 | "" | |
4ae234b0 | 13282 | "{t|t<wd>}%V0%I2 %1,%2") |
9ebbca7d GK |
13283 | \f |
13284 | ;; Insns related to generating the function prologue and epilogue. | |
13285 | ||
13286 | (define_expand "prologue" | |
13287 | [(use (const_int 0))] | |
13288 | "TARGET_SCHED_PROLOG" | |
13289 | " | |
13290 | { | |
13291 | rs6000_emit_prologue (); | |
13292 | DONE; | |
13293 | }") | |
13294 | ||
2c4a9cff DE |
13295 | (define_insn "*movesi_from_cr_one" |
13296 | [(match_parallel 0 "mfcr_operation" | |
13297 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
13298 | (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y") | |
13299 | (match_operand 3 "immediate_operand" "n")] | |
13300 | UNSPEC_MOVESI_FROM_CR))])] | |
13301 | "TARGET_MFCRF" | |
13302 | "* | |
13303 | { | |
13304 | int mask = 0; | |
13305 | int i; | |
13306 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
13307 | { | |
13308 | mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
13309 | operands[4] = GEN_INT (mask); | |
13310 | output_asm_insn (\"mfcr %1,%4\", operands); | |
13311 | } | |
13312 | return \"\"; | |
13313 | }" | |
13314 | [(set_attr "type" "mfcrf")]) | |
13315 | ||
9ebbca7d GK |
13316 | (define_insn "movesi_from_cr" |
13317 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 13318 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) |
615158e2 JJ |
13319 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] |
13320 | UNSPEC_MOVESI_FROM_CR))] | |
9ebbca7d | 13321 | "" |
309323c2 | 13322 | "mfcr %0" |
b54cf83a | 13323 | [(set_attr "type" "mfcr")]) |
9ebbca7d GK |
13324 | |
13325 | (define_insn "*stmw" | |
e033a023 DE |
13326 | [(match_parallel 0 "stmw_operation" |
13327 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
13328 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
13329 | "TARGET_MULTIPLE" | |
13330 | "{stm|stmw} %2,%1") | |
6ae08853 | 13331 | |
4ae234b0 | 13332 | (define_insn "*save_fpregs_<mode>" |
85d346f1 | 13333 | [(match_parallel 0 "any_parallel_operand" |
4ae234b0 GK |
13334 | [(clobber (match_operand:P 1 "register_operand" "=l")) |
13335 | (use (match_operand:P 2 "call_operand" "s")) | |
e033a023 DE |
13336 | (set (match_operand:DF 3 "memory_operand" "=m") |
13337 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
4ae234b0 | 13338 | "" |
e033a023 DE |
13339 | "bl %z2" |
13340 | [(set_attr "type" "branch") | |
13341 | (set_attr "length" "4")]) | |
9ebbca7d GK |
13342 | |
13343 | ; These are to explain that changes to the stack pointer should | |
13344 | ; not be moved over stores to stack memory. | |
13345 | (define_insn "stack_tie" | |
13346 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
615158e2 | 13347 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] |
9ebbca7d GK |
13348 | "" |
13349 | "" | |
13350 | [(set_attr "length" "0")]) | |
13351 | ||
13352 | ||
13353 | (define_expand "epilogue" | |
13354 | [(use (const_int 0))] | |
13355 | "TARGET_SCHED_PROLOG" | |
13356 | " | |
13357 | { | |
13358 | rs6000_emit_epilogue (FALSE); | |
13359 | DONE; | |
13360 | }") | |
13361 | ||
13362 | ; On some processors, doing the mtcrf one CC register at a time is | |
13363 | ; faster (like on the 604e). On others, doing them all at once is | |
13364 | ; faster; for instance, on the 601 and 750. | |
13365 | ||
13366 | (define_expand "movsi_to_cr_one" | |
35aba846 DE |
13367 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
13368 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 | 13369 | (match_dup 2)] UNSPEC_MOVESI_TO_CR))] |
35aba846 DE |
13370 | "" |
13371 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
9ebbca7d GK |
13372 | |
13373 | (define_insn "*movsi_to_cr" | |
35aba846 DE |
13374 | [(match_parallel 0 "mtcrf_operation" |
13375 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") | |
13376 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
13377 | (match_operand 3 "immediate_operand" "n")] | |
615158e2 | 13378 | UNSPEC_MOVESI_TO_CR))])] |
9ebbca7d | 13379 | "" |
e35b9579 GK |
13380 | "* |
13381 | { | |
13382 | int mask = 0; | |
13383 | int i; | |
13384 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
13385 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
13386 | operands[4] = GEN_INT (mask); | |
13387 | return \"mtcrf %4,%2\"; | |
309323c2 | 13388 | }" |
b54cf83a | 13389 | [(set_attr "type" "mtcr")]) |
9ebbca7d | 13390 | |
b54cf83a | 13391 | (define_insn "*mtcrfsi" |
309323c2 DE |
13392 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
13393 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 JJ |
13394 | (match_operand 2 "immediate_operand" "n")] |
13395 | UNSPEC_MOVESI_TO_CR))] | |
6ae08853 | 13396 | "GET_CODE (operands[0]) == REG |
309323c2 DE |
13397 | && CR_REGNO_P (REGNO (operands[0])) |
13398 | && GET_CODE (operands[2]) == CONST_INT | |
13399 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
13400 | "mtcrf %R0,%1" | |
b54cf83a | 13401 | [(set_attr "type" "mtcr")]) |
9ebbca7d GK |
13402 | |
13403 | ; The load-multiple instructions have similar properties. | |
13404 | ; Note that "load_multiple" is a name known to the machine-independent | |
13405 | ; code that actually corresponds to the powerpc load-string. | |
13406 | ||
13407 | (define_insn "*lmw" | |
35aba846 DE |
13408 | [(match_parallel 0 "lmw_operation" |
13409 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
13410 | (match_operand:SI 2 "memory_operand" "m"))])] | |
13411 | "TARGET_MULTIPLE" | |
13412 | "{lm|lmw} %1,%2") | |
6ae08853 | 13413 | |
4ae234b0 | 13414 | (define_insn "*return_internal_<mode>" |
e35b9579 | 13415 | [(return) |
4ae234b0 GK |
13416 | (use (match_operand:P 0 "register_operand" "lc"))] |
13417 | "" | |
cccf3bdc | 13418 | "b%T0" |
9ebbca7d GK |
13419 | [(set_attr "type" "jmpreg")]) |
13420 | ||
13421 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
85d346f1 | 13422 | ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible... |
9ebbca7d | 13423 | |
4ae234b0 | 13424 | (define_insn "*return_and_restore_fpregs_<mode>" |
85d346f1 | 13425 | [(match_parallel 0 "any_parallel_operand" |
e35b9579 | 13426 | [(return) |
4ae234b0 GK |
13427 | (use (match_operand:P 1 "register_operand" "l")) |
13428 | (use (match_operand:P 2 "call_operand" "s")) | |
9ebbca7d GK |
13429 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") |
13430 | (match_operand:DF 4 "memory_operand" "m"))])] | |
4ae234b0 | 13431 | "" |
9ebbca7d GK |
13432 | "b %z2") |
13433 | ||
83720594 RH |
13434 | ; This is used in compiling the unwind routines. |
13435 | (define_expand "eh_return" | |
34dc173c | 13436 | [(use (match_operand 0 "general_operand" ""))] |
9ebbca7d GK |
13437 | "" |
13438 | " | |
13439 | { | |
83720594 | 13440 | if (TARGET_32BIT) |
34dc173c | 13441 | emit_insn (gen_eh_set_lr_si (operands[0])); |
9ebbca7d | 13442 | else |
34dc173c | 13443 | emit_insn (gen_eh_set_lr_di (operands[0])); |
9ebbca7d GK |
13444 | DONE; |
13445 | }") | |
13446 | ||
83720594 | 13447 | ; We can't expand this before we know where the link register is stored. |
4ae234b0 GK |
13448 | (define_insn "eh_set_lr_<mode>" |
13449 | [(unspec_volatile [(match_operand:P 0 "register_operand" "r")] | |
615158e2 | 13450 | UNSPECV_EH_RR) |
4ae234b0 GK |
13451 | (clobber (match_scratch:P 1 "=&b"))] |
13452 | "" | |
83720594 | 13453 | "#") |
9ebbca7d GK |
13454 | |
13455 | (define_split | |
615158e2 | 13456 | [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) |
83720594 RH |
13457 | (clobber (match_scratch 1 ""))] |
13458 | "reload_completed" | |
13459 | [(const_int 0)] | |
9ebbca7d GK |
13460 | " |
13461 | { | |
d1d0c603 | 13462 | rs6000_emit_eh_reg_restore (operands[0], operands[1]); |
83720594 RH |
13463 | DONE; |
13464 | }") | |
0ac081f6 | 13465 | |
01a2ccd0 | 13466 | (define_insn "prefetch" |
3256a76e | 13467 | [(prefetch (match_operand 0 "indexed_or_indirect_address" "a") |
6041bf2f DE |
13468 | (match_operand:SI 1 "const_int_operand" "n") |
13469 | (match_operand:SI 2 "const_int_operand" "n"))] | |
01a2ccd0 | 13470 | "TARGET_POWERPC" |
6041bf2f DE |
13471 | "* |
13472 | { | |
01a2ccd0 DE |
13473 | if (GET_CODE (operands[0]) == REG) |
13474 | return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; | |
13475 | return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; | |
6041bf2f DE |
13476 | }" |
13477 | [(set_attr "type" "load")]) | |
915167f5 | 13478 | \f |
a3170dc6 | 13479 | |
f565b0a1 | 13480 | (include "sync.md") |
10ed84db | 13481 | (include "altivec.md") |
a3170dc6 | 13482 | (include "spe.md") |