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1fd4e8c1 RK |
1 | ;;- Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
2 | ;; Copyright (C) 1990, 1991 Free Software Foundation, Inc. | |
3 | ;; Contributed by Richard Kenner (kenner@nyu.edu) | |
4 | ||
5 | ;; This file is part of GNU CC. | |
6 | ||
7 | ;; GNU CC is free software; you can redistribute it and/or modify | |
8 | ;; it under the terms of the GNU General Public License as published by | |
9 | ;; the Free Software Foundation; either version 2, or (at your option) | |
10 | ;; any later version. | |
11 | ||
12 | ;; GNU CC is distributed in the hope that it will be useful, | |
13 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ;; GNU General Public License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GNU CC; see the file COPYING. If not, write to | |
19 | ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | ||
21 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
22 | \f | |
23 | ;; Define an insn type attribute. This is used in function unit delay | |
24 | ;; computations. | |
5c23c401 | 25 | (define_attr "type" "load,integer,fp,compare,delayed_compare,fpcompare,mtlr" |
1fd4e8c1 RK |
26 | (const_string "integer")) |
27 | ||
28 | ;; Memory delivers its result in two cycles. | |
29 | (define_function_unit "memory" 1 0 (eq_attr "type" "load") 2 0) | |
30 | ||
31 | ;; We consider floating-point insns to deliver their result in two cycles | |
32 | ;; to try to intersperse integer and FP operations. | |
33 | (define_function_unit "fp" 1 0 (eq_attr "type" "fp,fpcompare") 2 0) | |
34 | ||
35 | ;; Most integer comparisons are ready in four cycles (a stall of three). | |
36 | (define_function_unit "compare" 1 0 (eq_attr "type" "compare") 4 0) | |
37 | ||
38 | ;; Some integer comparisons aren't ready for five cycles (a stall of four). | |
39 | (define_function_unit "compare" 1 0 (eq_attr "type" "delayed_compare") 5 0) | |
40 | ||
41 | ;; Floating-point comparisons take eight cycles. | |
42 | (define_function_unit "compare" 1 0 (eq_attr "type" "fpcompare") 8 0) | |
5c23c401 RK |
43 | |
44 | ;; Branches on LR cannot be done until five cycles after LR is set. | |
45 | (define_function_unit "branch" 1 0 (eq_attr "type" "mtlr") 5 0) | |
1fd4e8c1 RK |
46 | \f |
47 | ;; Start with fixed-point load and store insns. Here we put only the more | |
48 | ;; complex forms. Basic data transfer is done later. | |
49 | ||
50 | (define_expand "zero_extendqisi2" | |
cd2b37d9 RK |
51 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
52 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
53 | "" |
54 | "") | |
55 | ||
56 | (define_insn "" | |
cd2b37d9 | 57 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
58 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
59 | "" | |
60 | "@ | |
61 | lbz%U1%X1 %0,%1 | |
62 | rlinm %0,%1,0,24,31" | |
63 | [(set_attr "type" "load,*")]) | |
64 | ||
65 | (define_insn "" | |
66 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 | 67 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
68 | (const_int 0))) |
69 | (clobber (match_scratch:SI 2 "=r"))] | |
70 | "" | |
71 | "andil. %2,%1,255" | |
72 | [(set_attr "type" "compare")]) | |
73 | ||
74 | (define_insn "" | |
75 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
cd2b37d9 | 76 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 77 | (const_int 0))) |
cd2b37d9 | 78 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
79 | (zero_extend:SI (match_dup 1)))] |
80 | "" | |
81 | "andil. %0,%1,255" | |
82 | [(set_attr "type" "compare")]) | |
83 | ||
84 | (define_expand "zero_extendqihi2" | |
cd2b37d9 RK |
85 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
86 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
87 | "" |
88 | "") | |
89 | ||
90 | (define_insn "" | |
cd2b37d9 | 91 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
92 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
93 | "" | |
94 | "@ | |
95 | lbz%U1%X1 %0,%1 | |
96 | rlinm %0,%1,0,24,31" | |
97 | [(set_attr "type" "load,*")]) | |
98 | ||
99 | (define_expand "zero_extendhisi2" | |
cd2b37d9 RK |
100 | [(set (match_operand:SI 0 "gpc_reg_operand" "r") |
101 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
102 | "" |
103 | "") | |
104 | ||
105 | (define_insn "" | |
cd2b37d9 | 106 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
107 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
108 | "" | |
109 | "@ | |
110 | lhz%U1%X1 %0,%1 | |
111 | rlinm %0,%1,0,16,31" | |
112 | [(set_attr "type" "load,*")]) | |
113 | ||
114 | (define_insn "" | |
115 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 | 116 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
117 | (const_int 0))) |
118 | (clobber (match_scratch:SI 2 "=r"))] | |
119 | "" | |
120 | "andil. %2,%1,65535" | |
121 | [(set_attr "type" "compare")]) | |
122 | ||
123 | (define_insn "" | |
124 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
cd2b37d9 | 125 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 126 | (const_int 0))) |
cd2b37d9 | 127 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
128 | (zero_extend:SI (match_dup 1)))] |
129 | "" | |
130 | "andil. %0,%1,65535" | |
131 | [(set_attr "type" "compare")]) | |
132 | ||
133 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
134 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
135 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
136 | "" |
137 | "") | |
138 | ||
139 | (define_insn "" | |
cd2b37d9 | 140 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
141 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
142 | "" | |
143 | "@ | |
144 | lha%U1%X1 %0,%1 | |
145 | exts %0,%1" | |
146 | [(set_attr "type" "load,*")]) | |
147 | ||
148 | (define_insn "" | |
149 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 | 150 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
151 | (const_int 0))) |
152 | (clobber (match_scratch:SI 2 "=r"))] | |
153 | "" | |
154 | "exts. %2,%1" | |
155 | [(set_attr "type" "compare")]) | |
156 | ||
157 | (define_insn "" | |
158 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
cd2b37d9 | 159 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 160 | (const_int 0))) |
cd2b37d9 | 161 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
162 | (sign_extend:SI (match_dup 1)))] |
163 | "" | |
164 | "exts. %0,%1" | |
165 | [(set_attr "type" "compare")]) | |
166 | \f | |
167 | ;; Fixed-point arithmetic insns. | |
f357808b | 168 | (define_insn "addsi3" |
cd2b37d9 RK |
169 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
170 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b") | |
1fd4e8c1 RK |
171 | (match_operand:SI 2 "add_operand" "rI,J")))] |
172 | "" | |
173 | "@ | |
174 | a%I2 %0,%1,%2 | |
175 | cau %0,%1,%u2") | |
176 | ||
177 | (define_insn "" | |
178 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 | 179 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
180 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
181 | (const_int 0))) | |
182 | (clobber (match_scratch:SI 3 "=r"))] | |
183 | "" | |
184 | "a%I2. %3,%1,%2" | |
185 | [(set_attr "type" "compare")]) | |
186 | ||
187 | (define_insn "" | |
188 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 | 189 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
190 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
191 | (const_int 0))) | |
cd2b37d9 | 192 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
193 | (plus:SI (match_dup 1) (match_dup 2)))] |
194 | "" | |
195 | "a%I2. %0,%1,%2" | |
196 | [(set_attr "type" "compare")]) | |
197 | ||
f357808b RK |
198 | ;; Split an add that we can't do in one insn into two insns, each of which |
199 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
200 | ;; add should be last in case the result gets used in an address. | |
201 | ||
202 | (define_split | |
cd2b37d9 RK |
203 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
204 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 205 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 206 | "" |
f357808b RK |
207 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
208 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
209 | " | |
1fd4e8c1 | 210 | { |
f357808b RK |
211 | int low = INTVAL (operands[2]) & 0xffff; |
212 | int high = (unsigned) INTVAL (operands[2]) >> 16; | |
1fd4e8c1 | 213 | |
f357808b RK |
214 | if (low & 0x8000) |
215 | high++, low |= 0xffff0000; | |
1fd4e8c1 | 216 | |
f357808b RK |
217 | operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16); |
218 | operands[4] = gen_rtx (CONST_INT, VOIDmode, low); | |
1fd4e8c1 RK |
219 | }") |
220 | ||
221 | (define_insn "one_cmplsi2" | |
cd2b37d9 RK |
222 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
223 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
224 | "" |
225 | "sfi %0,%1,-1") | |
226 | ||
227 | (define_insn "" | |
cd2b37d9 | 228 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 229 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") |
cd2b37d9 | 230 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] |
1fd4e8c1 RK |
231 | "" |
232 | "@ | |
233 | sf %0,%2,%1 | |
234 | sfi %0,%2,%1") | |
235 | ||
236 | (define_insn "" | |
237 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
238 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
239 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 RK |
240 | (const_int 0))) |
241 | (clobber (match_scratch:SI 3 "=r"))] | |
242 | "" | |
243 | "sf. %3,%2,%1" | |
244 | [(set_attr "type" "compare")]) | |
245 | ||
246 | (define_insn "" | |
247 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
248 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
249 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 250 | (const_int 0))) |
cd2b37d9 | 251 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
252 | (minus:SI (match_dup 1) (match_dup 2)))] |
253 | "" | |
254 | "sf. %0,%2,%1" | |
255 | [(set_attr "type" "compare")]) | |
256 | ||
257 | (define_expand "subsi3" | |
cd2b37d9 | 258 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
259 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
260 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
261 | "" | |
262 | " | |
263 | { | |
264 | if (GET_CODE (operands[2]) == CONST_INT) | |
265 | { | |
266 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
267 | negate_rtx (SImode, operands[2]))); | |
268 | DONE; | |
269 | } | |
1fd4e8c1 RK |
270 | }") |
271 | ||
272 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
273 | ;; instruction and some auxiliary computations. Then we just have a single | |
274 | ;; DEFINE_INSN for doz[i]. | |
275 | ||
276 | (define_expand "sminsi3" | |
277 | [(set (match_dup 3) | |
cd2b37d9 | 278 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
279 | (match_operand:SI 2 "reg_or_short_operand" "")) |
280 | (const_int 0) | |
281 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 282 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
283 | (minus:SI (match_dup 2) (match_dup 3)))] |
284 | "" | |
285 | " | |
286 | { operands[3] = gen_reg_rtx (SImode); }") | |
287 | ||
288 | (define_expand "smaxsi3" | |
289 | [(set (match_dup 3) | |
cd2b37d9 | 290 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
291 | (match_operand:SI 2 "reg_or_short_operand" "")) |
292 | (const_int 0) | |
293 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 294 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
295 | (plus:SI (match_dup 3) (match_dup 1)))] |
296 | "" | |
297 | " | |
298 | { operands[3] = gen_reg_rtx (SImode); }") | |
299 | ||
300 | (define_expand "uminsi3" | |
cd2b37d9 | 301 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 302 | (const_int -2147483648))) |
cd2b37d9 | 303 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
1fd4e8c1 RK |
304 | (const_int -2147483648))) |
305 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) | |
306 | (const_int 0) | |
307 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 308 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
309 | (minus:SI (match_dup 2) (match_dup 3)))] |
310 | "" | |
311 | " | |
312 | { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") | |
313 | ||
314 | (define_expand "umaxsi3" | |
cd2b37d9 | 315 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 316 | (const_int -2147483648))) |
cd2b37d9 | 317 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
1fd4e8c1 RK |
318 | (const_int -2147483648))) |
319 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) | |
320 | (const_int 0) | |
321 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 322 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
323 | (plus:SI (match_dup 3) (match_dup 1)))] |
324 | "" | |
325 | " | |
326 | { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") | |
327 | ||
328 | (define_insn "" | |
cd2b37d9 RK |
329 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
330 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 331 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
332 | (const_int 0) |
333 | (minus:SI (match_dup 2) (match_dup 1))))] | |
334 | "" | |
335 | "doz%I2 %0,%1,%2") | |
336 | ||
337 | (define_insn "" | |
338 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
339 | (compare:CC | |
cd2b37d9 | 340 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") |
5c23c401 | 341 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
342 | (const_int 0) |
343 | (minus:SI (match_dup 2) (match_dup 1))) | |
344 | (const_int 0))) | |
345 | (clobber (match_scratch:SI 3 "=r"))] | |
346 | "" | |
347 | "doz%I2. %3,%1,%2" | |
348 | [(set_attr "type" "delayed_compare")]) | |
349 | ||
350 | (define_insn "" | |
351 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
352 | (compare:CC | |
cd2b37d9 | 353 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") |
5c23c401 | 354 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
355 | (const_int 0) |
356 | (minus:SI (match_dup 2) (match_dup 1))) | |
357 | (const_int 0))) | |
cd2b37d9 | 358 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
359 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
360 | (const_int 0) | |
361 | (minus:SI (match_dup 2) (match_dup 1))))] | |
362 | "" | |
363 | "doz%I2. %0,%1,%2" | |
364 | [(set_attr "type" "delayed_compare")]) | |
365 | ||
366 | ;; We don't need abs with condition code because such comparisons should | |
367 | ;; never be done. | |
368 | (define_insn "abssi2" | |
cd2b37d9 RK |
369 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
370 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
371 | "" |
372 | "abs %0,%1") | |
373 | ||
374 | (define_insn "" | |
cd2b37d9 RK |
375 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
376 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
1fd4e8c1 RK |
377 | "" |
378 | "nabs %0,%1") | |
379 | ||
380 | (define_insn "negsi2" | |
cd2b37d9 RK |
381 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
382 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
383 | "" |
384 | "neg %0,%1") | |
385 | ||
386 | (define_insn "" | |
387 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 | 388 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
389 | (const_int 0))) |
390 | (clobber (match_scratch:SI 2 "=r"))] | |
391 | "" | |
392 | "neg. %2,%1" | |
393 | [(set_attr "type" "compare")]) | |
394 | ||
395 | (define_insn "" | |
396 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
cd2b37d9 | 397 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 398 | (const_int 0))) |
cd2b37d9 | 399 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
400 | (neg:SI (match_dup 1)))] |
401 | "" | |
402 | "neg. %0,%1" | |
403 | [(set_attr "type" "compare")]) | |
404 | ||
405 | (define_insn "ffssi2" | |
406 | [(set (match_operand:SI 0 "register_operand" "=&r") | |
407 | (ffs:SI (match_operand:SI 1 "register_operand" "r")))] | |
408 | "" | |
409 | "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi %0,%0,32") | |
410 | ||
411 | ;; There is no need for (set (condition) (compare (ffs) 0)) because that | |
412 | ;; can be simplified to an ordinary comparison. A parallel set and compare | |
413 | ;; might be used, so include it. | |
414 | ||
415 | (define_insn "" | |
416 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
417 | (compare:CC (ffs:SI (match_operand:SI 1 "register_operand" "r")) | |
418 | (const_int 0))) | |
419 | (set (match_operand:SI 0 "register_operand" "=&r") | |
420 | (ffs:SI (match_dup 1)))] | |
421 | "" | |
422 | "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi. %0,%0,32" | |
423 | [(set_attr "type" "compare")]) | |
424 | ||
425 | (define_insn "mulsi3" | |
cd2b37d9 RK |
426 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
427 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
428 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
429 | (clobber (match_scratch:SI 3 "=q,q"))] | |
430 | "" | |
431 | "@ | |
432 | muls %0,%1,%2 | |
433 | muli %0,%1,%2") | |
434 | ||
435 | (define_insn "" | |
436 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
437 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
438 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 RK |
439 | (const_int 0))) |
440 | (clobber (match_scratch:SI 3 "=r")) | |
441 | (clobber (match_scratch:SI 4 "=q"))] | |
442 | "" | |
443 | "muls. %3,%1,%2" | |
444 | [(set_attr "type" "delayed_compare")]) | |
445 | ||
446 | (define_insn "" | |
447 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
448 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
449 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 450 | (const_int 0))) |
cd2b37d9 | 451 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
452 | (mult:SI (match_dup 1) (match_dup 2))) |
453 | (clobber (match_scratch:SI 4 "=q"))] | |
454 | "" | |
455 | "muls. %0,%1,%2" | |
456 | [(set_attr "type" "delayed_compare")]) | |
457 | ||
458 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
459 | ;; 0 and remainder to operand 3. | |
460 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
461 | ||
462 | (define_insn "divmodsi4" | |
cd2b37d9 RK |
463 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
464 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
465 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
466 | (set (match_operand:SI 3 "gpc_reg_operand" "=q") | |
1fd4e8c1 RK |
467 | (mod:SI (match_dup 1) (match_dup 2)))] |
468 | "" | |
469 | "divs %0,%1,%2") | |
470 | ||
471 | ;; For powers of two we can do srai/aze for divide and then adjust for | |
472 | ;; modulus. If it isn't a power of two, FAIL so divmodsi4 will be used. | |
473 | (define_expand "divsi3" | |
cd2b37d9 RK |
474 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
475 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
476 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
477 | "" | |
478 | " | |
479 | { | |
480 | if (GET_CODE (operands[2]) != CONST_INT | |
481 | || exact_log2 (INTVAL (operands[2])) < 0) | |
482 | FAIL; | |
483 | }") | |
484 | ||
485 | (define_expand "modsi3" | |
486 | [(set (match_dup 3) | |
cd2b37d9 | 487 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
488 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
489 | (parallel [(set (match_dup 4) (ashift:SI (match_dup 3) (match_dup 5))) | |
490 | (clobber (scratch:SI))]) | |
cd2b37d9 | 491 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
492 | (minus:SI (match_dup 1) (match_dup 4)))] |
493 | "" | |
494 | " | |
495 | { | |
496 | int i = exact_log2 (INTVAL (operands[2])); | |
497 | ||
498 | if (GET_CODE (operands[2]) != CONST_INT || i < 0) | |
499 | FAIL; | |
500 | ||
501 | operands[3] = gen_reg_rtx (SImode); | |
502 | operands[4] = gen_reg_rtx (SImode); | |
503 | operands[5] = gen_rtx (CONST_INT, VOIDmode, i); | |
504 | }") | |
505 | ||
506 | (define_insn "" | |
cd2b37d9 RK |
507 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
508 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
509 | (match_operand:SI 2 "const_int_operand" "N")))] |
510 | "exact_log2 (INTVAL (operands[2])) >= 0" | |
511 | "srai %0,%1,%p2\;aze %0,%0") | |
512 | ||
513 | (define_insn "" | |
514 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 | 515 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
516 | (match_operand:SI 2 "const_int_operand" "N"))) |
517 | (clobber (match_scratch:SI 3 "=r"))] | |
518 | "exact_log2 (INTVAL (operands[2])) >= 0" | |
519 | "srai %3,%1,%p2\;aze. %3,%3" | |
520 | [(set_attr "type" "compare")]) | |
521 | ||
522 | (define_insn "" | |
523 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 | 524 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 525 | (match_operand:SI 2 "const_int_operand" "N"))) |
cd2b37d9 | 526 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
527 | (div:SI (match_dup 1) (match_dup 2)))] |
528 | "exact_log2 (INTVAL (operands[2])) >= 0" | |
529 | "srai %0,%1,%p2\;aze. %0,%0" | |
530 | [(set_attr "type" "compare")]) | |
531 | ||
532 | (define_insn "" | |
cd2b37d9 | 533 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
534 | (udiv:SI |
535 | (plus:DI (lshift:DI | |
cd2b37d9 | 536 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 537 | (const_int 32)) |
740ab4a2 | 538 | (zero_extend:DI (match_operand:SI 4 "register_operand" "0"))) |
cd2b37d9 | 539 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 540 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 RK |
541 | (umod:SI |
542 | (plus:DI (lshift:DI | |
543 | (zero_extend:DI (match_dup 1)) (const_int 32)) | |
740ab4a2 | 544 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 RK |
545 | (match_dup 3)))] |
546 | ||
547 | "" | |
548 | "div %0,%1,%3") | |
549 | ||
550 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
551 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
552 | ;; have to worry about the branches. So make a few subroutines here. | |
553 | ;; | |
554 | ;; First comes the normal case. | |
555 | (define_expand "udivmodsi4_normal" | |
556 | [(set (match_dup 4) (const_int 0)) | |
557 | (parallel [(set (match_operand:SI 0 "" "") | |
558 | (udiv:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4)) | |
559 | (const_int 32)) | |
560 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
561 | (match_operand:SI 2 "" ""))) | |
562 | (set (match_operand:SI 3 "" "") | |
563 | (umod:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4)) | |
564 | (const_int 32)) | |
565 | (zero_extend:DI (match_dup 1))) | |
566 | (match_dup 2)))])] | |
567 | "" | |
568 | " | |
569 | { operands[4] = gen_reg_rtx (SImode); }") | |
570 | ||
571 | ;; This handles the branches. | |
572 | (define_expand "udivmodsi4_tests" | |
573 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
574 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
575 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
576 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
577 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
578 | (set (match_dup 0) (const_int 1)) | |
579 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
580 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
581 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
582 | (label_ref (match_dup 4)) (pc)))] | |
583 | "" | |
584 | " | |
585 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
586 | operands[6] = gen_reg_rtx (CCmode); | |
587 | }") | |
588 | ||
589 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
590 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
591 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 592 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 593 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 RK |
594 | (umod:SI (match_dup 1) (match_dup 2)))])] |
595 | "" | |
596 | " | |
597 | { | |
598 | rtx label = 0; | |
599 | ||
600 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) | |
601 | { | |
602 | operands[2] = force_reg (SImode, operands[2]); | |
603 | label = gen_label_rtx (); | |
604 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
605 | operands[3], label)); | |
606 | } | |
607 | else | |
608 | operands[2] = force_reg (SImode, operands[2]); | |
609 | ||
610 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
611 | operands[3])); | |
612 | if (label) | |
613 | emit_label (label); | |
614 | ||
615 | DONE; | |
616 | }") | |
617 | ||
618 | (define_insn "andsi3" | |
cd2b37d9 RK |
619 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
620 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1fd4e8c1 RK |
621 | (match_operand:SI 2 "and_operand" "?r,L,K,J"))) |
622 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] | |
623 | "" | |
624 | "@ | |
625 | and %0,%1,%2 | |
626 | rlinm %0,%1,0,%m2,%M2 | |
627 | andil. %0,%1,%b2 | |
628 | andiu. %0,%1,%u2") | |
629 | ||
630 | (define_insn "" | |
631 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") | |
cd2b37d9 | 632 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") |
1fd4e8c1 RK |
633 | (match_operand:SI 2 "and_operand" "r,K,J,L")) |
634 | (const_int 0))) | |
635 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] | |
636 | "" | |
637 | "@ | |
638 | and. %3,%1,%2 | |
639 | andil. %3,%1,%b2 | |
640 | andiu. %3,%1,%u2 | |
641 | rlinm. %3,%1,0,%m2,%M2" | |
642 | [(set_attr "type" "compare,compare,compare,delayed_compare")]) | |
643 | ||
644 | (define_insn "" | |
645 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") | |
cd2b37d9 | 646 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") |
1fd4e8c1 RK |
647 | (match_operand:SI 2 "and_operand" "r,K,J,L")) |
648 | (const_int 0))) | |
cd2b37d9 | 649 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 RK |
650 | (and:SI (match_dup 1) (match_dup 2)))] |
651 | "" | |
652 | "@ | |
653 | and. %0,%1,%2 | |
654 | andil. %0,%1,%b2 | |
655 | andiu. %0,%1,%u2 | |
656 | rlinm. %0,%1,0,%m2,%M2" | |
657 | [(set_attr "type" "compare,compare,compare,delayed_compare")]) | |
658 | ||
f357808b RK |
659 | ;; Take a AND with a constant that cannot be done in a single insn and try to |
660 | ;; split it into two insns. This does not verify that the insns are valid | |
661 | ;; since this need not be done as combine will do it. | |
662 | ||
663 | (define_split | |
cd2b37d9 RK |
664 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
665 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b RK |
666 | (match_operand:SI 2 "non_and_cint_operand" "")))] |
667 | "" | |
668 | [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3))) | |
669 | (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))] | |
670 | " | |
671 | { | |
672 | int maskval = INTVAL (operands[2]); | |
673 | int i, transitions, last_bit_value; | |
674 | int orig = maskval, first_c = maskval, second_c; | |
675 | ||
676 | /* We know that MASKVAL must have more than 2 bit-transitions. Start at | |
677 | the low-order bit and count for the third transition. When we get there, | |
678 | make a first mask that has everything to the left of that position | |
679 | a one. Then make the second mask to turn off whatever else is needed. */ | |
680 | ||
681 | for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++) | |
682 | { | |
683 | if (((maskval >>= 1) & 1) != last_bit_value) | |
684 | last_bit_value ^= 1, transitions++; | |
685 | ||
686 | if (transitions > 2) | |
687 | { | |
688 | first_c |= (~0) << i; | |
689 | break; | |
690 | } | |
691 | } | |
692 | ||
693 | second_c = orig | ~ first_c; | |
694 | ||
695 | operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c); | |
696 | operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c); | |
697 | }") | |
698 | ||
699 | (define_insn "iorsi3" | |
cd2b37d9 RK |
700 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
701 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") | |
1fd4e8c1 RK |
702 | (match_operand:SI 2 "logical_operand" "r,K,J")))] |
703 | "" | |
704 | "@ | |
705 | or %0,%1,%2 | |
706 | oril %0,%1,%b2 | |
707 | oriu %0,%1,%u2") | |
708 | ||
709 | (define_insn "" | |
710 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
711 | (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
712 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 RK |
713 | (const_int 0))) |
714 | (clobber (match_scratch:SI 3 "=r"))] | |
715 | "" | |
716 | "or. %3,%1,%2" | |
717 | [(set_attr "type" "compare")]) | |
718 | ||
719 | (define_insn "" | |
720 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
721 | (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
722 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 723 | (const_int 0))) |
cd2b37d9 | 724 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
725 | (ior:SI (match_dup 1) (match_dup 2)))] |
726 | "" | |
727 | "or. %0,%1,%2" | |
728 | [(set_attr "type" "compare")]) | |
729 | ||
f357808b RK |
730 | ;; Split an IOR that we can't do in one insn into two insns, each of which |
731 | ;; does one 16-bit part. This is used by combine. | |
732 | ||
733 | (define_split | |
cd2b37d9 RK |
734 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
735 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 736 | (match_operand:SI 2 "non_logical_cint_operand" "")))] |
1fd4e8c1 | 737 | "" |
f357808b RK |
738 | [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3))) |
739 | (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))] | |
740 | " | |
1fd4e8c1 | 741 | { |
f357808b RK |
742 | operands[3] = gen_rtx (CONST_INT, VOIDmode, |
743 | INTVAL (operands[2]) & 0xffff0000); | |
744 | operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); | |
1fd4e8c1 RK |
745 | }") |
746 | ||
f357808b | 747 | (define_insn "xorsi3" |
cd2b37d9 RK |
748 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
749 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") | |
1fd4e8c1 RK |
750 | (match_operand:SI 2 "logical_operand" "r,K,J")))] |
751 | "" | |
752 | "@ | |
753 | xor %0,%1,%2 | |
754 | xoril %0,%1,%b2 | |
755 | xoriu %0,%1,%u2") | |
756 | ||
757 | (define_insn "" | |
758 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
759 | (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
760 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 RK |
761 | (const_int 0))) |
762 | (clobber (match_scratch:SI 3 "=r"))] | |
763 | "" | |
764 | "xor. %3,%1,%2" | |
765 | [(set_attr "type" "compare")]) | |
766 | ||
767 | (define_insn "" | |
768 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
769 | (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
770 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 771 | (const_int 0))) |
cd2b37d9 | 772 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
773 | (xor:SI (match_dup 1) (match_dup 2)))] |
774 | "" | |
775 | "xor. %0,%1,%2" | |
776 | [(set_attr "type" "compare")]) | |
777 | ||
f357808b RK |
778 | ;; Split an XOR that we can't do in one insn into two insns, each of which |
779 | ;; does one 16-bit part. This is used by combine. | |
780 | ||
781 | (define_split | |
cd2b37d9 RK |
782 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
783 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 784 | (match_operand:SI 2 "non_logical_cint_operand" "")))] |
1fd4e8c1 | 785 | "" |
f357808b RK |
786 | [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3))) |
787 | (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))] | |
788 | " | |
1fd4e8c1 | 789 | { |
f357808b RK |
790 | operands[3] = gen_rtx (CONST_INT, VOIDmode, |
791 | INTVAL (operands[2]) & 0xffff0000); | |
792 | operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); | |
1fd4e8c1 RK |
793 | }") |
794 | ||
795 | (define_insn "" | |
cd2b37d9 RK |
796 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
797 | (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
798 | (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
1fd4e8c1 RK |
799 | "" |
800 | "eqv %0,%1,%2") | |
801 | ||
802 | (define_insn "" | |
803 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
804 | (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") |
805 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1fd4e8c1 RK |
806 | (const_int 0))) |
807 | (clobber (match_scratch:SI 3 "=r"))] | |
808 | "" | |
809 | "eqv. %3,%1,%2" | |
810 | [(set_attr "type" "compare")]) | |
811 | ||
812 | (define_insn "" | |
813 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
814 | (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") |
815 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1fd4e8c1 | 816 | (const_int 0))) |
cd2b37d9 | 817 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
818 | (not:SI (xor:SI (match_dup 1) (match_dup 2))))] |
819 | "" | |
820 | "eqv. %0,%1,%2" | |
821 | [(set_attr "type" "compare")]) | |
822 | ||
823 | (define_insn "" | |
cd2b37d9 RK |
824 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
825 | (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
826 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
827 | "" |
828 | "andc %0,%2,%1") | |
829 | ||
830 | (define_insn "" | |
831 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
832 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
833 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 RK |
834 | (const_int 0))) |
835 | (clobber (match_scratch:SI 3 "=r"))] | |
836 | "" | |
837 | "andc. %3,%2,%1" | |
838 | [(set_attr "type" "compare")]) | |
839 | ||
840 | (define_insn "" | |
841 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
842 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
843 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 844 | (const_int 0))) |
cd2b37d9 | 845 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
846 | (and:SI (not:SI (match_dup 1)) (match_dup 2)))] |
847 | "" | |
848 | "andc. %0,%2,%1" | |
849 | [(set_attr "type" "compare")]) | |
850 | ||
851 | (define_insn "" | |
cd2b37d9 RK |
852 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
853 | (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
854 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
855 | "" |
856 | "orc %0,%2,%1") | |
857 | ||
858 | (define_insn "" | |
859 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
860 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
861 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 RK |
862 | (const_int 0))) |
863 | (clobber (match_scratch:SI 3 "=r"))] | |
864 | "" | |
865 | "orc. %3,%2,%1" | |
866 | [(set_attr "type" "compare")]) | |
867 | ||
868 | (define_insn "" | |
869 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
870 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
871 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 872 | (const_int 0))) |
cd2b37d9 | 873 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
874 | (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] |
875 | "" | |
876 | "orc. %0,%2,%1" | |
877 | [(set_attr "type" "compare")]) | |
878 | ||
879 | (define_insn "" | |
cd2b37d9 RK |
880 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
881 | (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
882 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
1fd4e8c1 RK |
883 | "" |
884 | "nand %0,%1,%2") | |
885 | ||
886 | (define_insn "" | |
887 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
888 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
889 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1fd4e8c1 RK |
890 | (const_int 0))) |
891 | (clobber (match_scratch:SI 3 "=r"))] | |
892 | "" | |
893 | "nand. %3,%1,%2" | |
894 | [(set_attr "type" "compare")]) | |
895 | ||
896 | (define_insn "" | |
897 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
898 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
899 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1fd4e8c1 | 900 | (const_int 0))) |
cd2b37d9 | 901 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
902 | (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] |
903 | "" | |
904 | "nand. %0,%1,%2" | |
905 | [(set_attr "type" "compare")]) | |
906 | ||
907 | (define_insn "" | |
cd2b37d9 RK |
908 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
909 | (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
910 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
1fd4e8c1 RK |
911 | "" |
912 | "nor %0,%1,%2") | |
913 | ||
914 | (define_insn "" | |
915 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
916 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
917 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1fd4e8c1 RK |
918 | (const_int 0))) |
919 | (clobber (match_scratch:SI 3 "=r"))] | |
920 | "" | |
921 | "nor. %3,%1,%2" | |
922 | [(set_attr "type" "compare")]) | |
923 | ||
924 | (define_insn "" | |
925 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 RK |
926 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
927 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1fd4e8c1 | 928 | (const_int 0))) |
cd2b37d9 | 929 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
930 | (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] |
931 | "" | |
932 | "nor. %0,%1,%2" | |
933 | [(set_attr "type" "compare")]) | |
934 | ||
935 | ;; maskir insn. We need four forms because things might be in arbitrary | |
936 | ;; orders. Don't define forms that only set CR fields because these | |
937 | ;; would modify an input register. | |
938 | ||
939 | (define_insn "" | |
cd2b37d9 RK |
940 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
941 | (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
942 | (match_operand:SI 2 "gpc_reg_operand" "0")) | |
1fd4e8c1 | 943 | (and:SI (match_dup 1) |
cd2b37d9 | 944 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
1fd4e8c1 RK |
945 | "" |
946 | "maskir %0,%3,%1") | |
947 | ||
948 | (define_insn "" | |
949 | [(set (match_operand:SI 0 "register_operand" "=r") | |
cd2b37d9 RK |
950 | (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
951 | (match_operand:SI 2 "gpc_reg_operand" "0")) | |
952 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
953 | (match_dup 1))))] |
954 | "" | |
955 | "maskir %0,%3,%1") | |
956 | ||
957 | (define_insn "" | |
cd2b37d9 | 958 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 959 | (ior:SI (and:SI (match_dup 1) |
cd2b37d9 RK |
960 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
961 | (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
962 | (match_operand:SI 2 "gpc_reg_operand" "0"))))] | |
1fd4e8c1 RK |
963 | "" |
964 | "maskir %0,%3,%1") | |
965 | ||
966 | (define_insn "" | |
cd2b37d9 RK |
967 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
968 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
1fd4e8c1 | 969 | (match_dup 1)) |
cd2b37d9 RK |
970 | (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
971 | (match_operand:SI 2 "gpc_reg_operand" "0"))))] | |
1fd4e8c1 RK |
972 | "" |
973 | "maskir %0,%3,%1") | |
974 | ||
975 | (define_insn "" | |
976 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
977 | (compare:CC | |
cd2b37d9 RK |
978 | (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
979 | (match_operand:SI 2 "gpc_reg_operand" "0")) | |
1fd4e8c1 | 980 | (and:SI (match_dup 1) |
cd2b37d9 | 981 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 982 | (const_int 0))) |
cd2b37d9 | 983 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
984 | (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2)) |
985 | (and:SI (match_dup 1) (match_dup 3))))] | |
986 | "" | |
987 | "maskir. %0,%3,%1" | |
988 | [(set_attr "type" "compare")]) | |
989 | ||
990 | (define_insn "" | |
991 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
992 | (compare:CC | |
cd2b37d9 RK |
993 | (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
994 | (match_operand:SI 2 "gpc_reg_operand" "0")) | |
995 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
996 | (match_dup 1))) |
997 | (const_int 0))) | |
998 | (set (match_operand:SI 0 "register_operand" "=r") | |
999 | (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2)) | |
1000 | (and:SI (match_dup 3) (match_dup 1))))] | |
1001 | "" | |
1002 | "maskir. %0,%3,%1" | |
1003 | [(set_attr "type" "compare")]) | |
1004 | ||
1005 | (define_insn "" | |
1006 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
1007 | (compare:CC | |
1008 | (ior:SI (and:SI (match_dup 1) | |
cd2b37d9 RK |
1009 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1010 | (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
1011 | (match_operand:SI 2 "gpc_reg_operand" "0"))) | |
1fd4e8c1 | 1012 | (const_int 0))) |
cd2b37d9 | 1013 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1014 | (ior:SI (and:SI (match_dup 1) (match_dup 3)) |
1015 | (and:SI (not:SI (match_dup 1)) (match_dup 2))))] | |
1016 | "" | |
1017 | "maskir. %0,%3,%1" | |
1018 | [(set_attr "type" "compare")]) | |
1019 | ||
1020 | (define_insn "" | |
1021 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
1022 | (compare:CC | |
cd2b37d9 | 1023 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
1fd4e8c1 | 1024 | (match_dup 1)) |
cd2b37d9 RK |
1025 | (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1026 | (match_operand:SI 2 "gpc_reg_operand" "0"))) | |
1fd4e8c1 | 1027 | (const_int 0))) |
cd2b37d9 | 1028 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1029 | (ior:SI (and:SI (match_dup 3) (match_dup 1)) |
1030 | (and:SI (not:SI (match_dup 1)) (match_dup 2))))] | |
1031 | "" | |
1032 | "maskir. %0,%3,%1" | |
1033 | [(set_attr "type" "compare")]) | |
1034 | \f | |
1035 | ;; Rotate and shift insns, in all their variants. These support shifts, | |
1036 | ;; field inserts and extracts, and various combinations thereof. | |
1037 | (define_insn "insv" | |
cd2b37d9 | 1038 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
1039 | (match_operand:SI 1 "const_int_operand" "i") |
1040 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 1041 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
1042 | "" |
1043 | "* | |
1044 | { | |
1045 | int start = INTVAL (operands[2]) & 31; | |
1046 | int size = INTVAL (operands[1]) & 31; | |
1047 | ||
1048 | operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size); | |
1049 | operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1); | |
1050 | return \"rlimi %0,%3,%4,%h2,%h1\"; | |
1051 | }") | |
1052 | ||
1053 | (define_insn "extzv" | |
cd2b37d9 RK |
1054 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1055 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
1056 | (match_operand:SI 2 "const_int_operand" "i") |
1057 | (match_operand:SI 3 "const_int_operand" "i")))] | |
1058 | "" | |
1059 | "* | |
1060 | { | |
1061 | int start = INTVAL (operands[3]) & 31; | |
1062 | int size = INTVAL (operands[2]) & 31; | |
1063 | ||
1064 | if (start + size >= 32) | |
1065 | operands[3] = const0_rtx; | |
1066 | else | |
1067 | operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); | |
1068 | return \"rlinm %0,%1,%3,%s2,31\"; | |
1069 | }") | |
1070 | ||
1071 | (define_insn "" | |
1072 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 | 1073 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1074 | (match_operand:SI 2 "const_int_operand" "i") |
1075 | (match_operand:SI 3 "const_int_operand" "i")) | |
1076 | (const_int 0))) | |
1077 | (clobber (match_scratch:SI 4 "=r"))] | |
1078 | "" | |
1079 | "* | |
1080 | { | |
1081 | int start = INTVAL (operands[3]) & 31; | |
1082 | int size = INTVAL (operands[2]) & 31; | |
1083 | ||
a7a975e1 RK |
1084 | /* If the bitfield being tested fits in the upper or lower half of a |
1085 | word, it is possible to use andiu. or andil. to test it. This is | |
1086 | useful because the condition register set-use delay is smaller for | |
1087 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
1088 | position is 0 because the LT and GT bits may be set wrong. */ | |
1089 | ||
1090 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 RK |
1091 | { |
1092 | operands[3] = gen_rtx (CONST_INT, VOIDmode, | |
1093 | ((1 << (16 - (start & 15))) | |
1094 | - (1 << (16 - (start & 15) - size)))); | |
1095 | if (start < 16) | |
1096 | return \"andiu. %4,%1,%3\"; | |
1097 | else | |
1098 | return \"andil. %4,%1,%3\"; | |
1099 | } | |
1100 | ||
1fd4e8c1 RK |
1101 | if (start + size >= 32) |
1102 | operands[3] = const0_rtx; | |
1103 | else | |
1104 | operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); | |
1105 | return \"rlinm. %4,%1,%3,%s2,31\"; | |
1106 | }" | |
1107 | [(set_attr "type" "compare")]) | |
1108 | ||
1109 | (define_insn "" | |
1110 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
cd2b37d9 | 1111 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1112 | (match_operand:SI 2 "const_int_operand" "i") |
1113 | (match_operand:SI 3 "const_int_operand" "i")) | |
1114 | (const_int 0))) | |
cd2b37d9 | 1115 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1116 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
1117 | "" | |
1118 | "* | |
1119 | { | |
1120 | int start = INTVAL (operands[3]) & 31; | |
1121 | int size = INTVAL (operands[2]) & 31; | |
1122 | ||
a7a975e1 | 1123 | if (start >= 16 && start + size == 32) |
df031c43 | 1124 | { |
a7a975e1 RK |
1125 | operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1); |
1126 | return \"andil. %0,%1,%3\"; | |
df031c43 RK |
1127 | } |
1128 | ||
1fd4e8c1 RK |
1129 | if (start + size >= 32) |
1130 | operands[3] = const0_rtx; | |
1131 | else | |
1132 | operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size); | |
1133 | return \"rlinm. %0,%1,%3,%s2,31\"; | |
1134 | }" | |
1135 | [(set_attr "type" "delayed_compare")]) | |
1136 | ||
1137 | (define_insn "rotlsi3" | |
cd2b37d9 RK |
1138 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1139 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
1140 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
1141 | "" | |
1142 | "rl%I2nm %0,%1,%h2,0,31") | |
1143 | ||
1144 | (define_insn "" | |
1145 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
cd2b37d9 | 1146 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1147 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
1148 | (const_int 0))) | |
1149 | (clobber (match_scratch:SI 3 "=r"))] | |
1150 | "" | |
1151 | "rl%I2nm. %3,%1,%h2,0,31" | |
1152 | [(set_attr "type" "delayed_compare")]) | |
1153 | ||
1154 | (define_insn "" | |
1155 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
cd2b37d9 | 1156 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1157 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
1158 | (const_int 0))) | |
cd2b37d9 | 1159 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1160 | (rotate:SI (match_dup 1) (match_dup 2)))] |
1161 | "" | |
1162 | "rl%I2nm. %0,%1,%h2,0,31" | |
1163 | [(set_attr "type" "delayed_compare")]) | |
1164 | ||
1165 | (define_insn "" | |
cd2b37d9 RK |
1166 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1167 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
1168 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
1169 | (match_operand:SI 3 "mask_operand" "L")))] | |
1170 | "" | |
1171 | "rl%I2nm %0,%1,%h2,%m3,%M3") | |
1172 | ||
1173 | (define_insn "" | |
1174 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
1175 | (compare:CC (and:SI | |
cd2b37d9 | 1176 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1177 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
1178 | (match_operand:SI 3 "mask_operand" "L")) | |
1179 | (const_int 0))) | |
1180 | (clobber (match_scratch:SI 4 "=r"))] | |
1181 | "" | |
1182 | "rl%I2nm. %4,%1,%h2,%m3,%M3" | |
1183 | [(set_attr "type" "delayed_compare")]) | |
1184 | ||
1185 | (define_insn "" | |
1186 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
1187 | (compare:CC (and:SI | |
cd2b37d9 | 1188 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1189 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
1190 | (match_operand:SI 3 "mask_operand" "L")) | |
1191 | (const_int 0))) | |
cd2b37d9 | 1192 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1193 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
1194 | "" | |
1195 | "rl%I2nm. %0,%1,%h2,%m3,%M3" | |
1196 | [(set_attr "type" "delayed_compare")]) | |
1197 | ||
1198 | (define_insn "" | |
cd2b37d9 | 1199 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1200 | (zero_extend:SI |
1201 | (subreg:QI | |
cd2b37d9 | 1202 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1203 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
1204 | "" | |
1205 | "rl%I2nm %0,%1,%h2,24,31") | |
1206 | ||
1207 | (define_insn "" | |
1208 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
1209 | (compare:CC (zero_extend:SI | |
1210 | (subreg:QI | |
cd2b37d9 | 1211 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1212 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) |
1213 | (const_int 0))) | |
1214 | (clobber (match_scratch:SI 3 "=r"))] | |
1215 | "" | |
1216 | "rl%I2nm. %3,%1,%h2,24,31" | |
1217 | [(set_attr "type" "delayed_compare")]) | |
1218 | ||
1219 | (define_insn "" | |
1220 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
1221 | (compare:CC (zero_extend:SI | |
1222 | (subreg:QI | |
cd2b37d9 | 1223 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1224 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) |
1225 | (const_int 0))) | |
cd2b37d9 | 1226 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1227 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
1228 | "" | |
1229 | "rl%I2nm. %0,%1,%h2,24,31" | |
1230 | [(set_attr "type" "delayed_compare")]) | |
1231 | ||
1232 | (define_insn "" | |
cd2b37d9 | 1233 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1234 | (zero_extend:SI |
1235 | (subreg:HI | |
cd2b37d9 | 1236 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1237 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
1238 | "" | |
1239 | "rl%I2nm %0,%1,%h2,16,31") | |
1240 | ||
1241 | (define_insn "" | |
1242 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
1243 | (compare:CC (zero_extend:SI | |
1244 | (subreg:HI | |
cd2b37d9 | 1245 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1246 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) |
1247 | (const_int 0))) | |
1248 | (clobber (match_scratch:SI 3 "=r"))] | |
1249 | "" | |
1250 | "rl%I2nm. %3,%1,%h2,16,31" | |
1251 | [(set_attr "type" "delayed_compare")]) | |
1252 | ||
1253 | (define_insn "" | |
1254 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
1255 | (compare:CC (zero_extend:SI | |
1256 | (subreg:HI | |
cd2b37d9 | 1257 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1258 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) |
1259 | (const_int 0))) | |
cd2b37d9 | 1260 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1261 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
1262 | "" | |
1263 | "rl%I2nm. %0,%1,%h2,16,31" | |
1264 | [(set_attr "type" "delayed_compare")]) | |
1265 | ||
1266 | ;; Note that we use "sle." instead of "sl." so that we can set | |
1267 | ;; SHIFT_COUNT_TRUNCATED. | |
1268 | ||
1269 | (define_insn "ashlsi3" | |
cd2b37d9 RK |
1270 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1271 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
1272 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
1273 | (clobber (match_scratch:SI 3 "=q,X"))] | |
1274 | "" | |
1275 | "@ | |
1276 | sle %0,%1,%2 | |
1277 | sli %0,%1,%h2") | |
1278 | ||
1279 | (define_insn "" | |
1280 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") | |
cd2b37d9 | 1281 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
1282 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) |
1283 | (const_int 0))) | |
1284 | (clobber (match_scratch:SI 3 "=r,r")) | |
1285 | (clobber (match_scratch:SI 4 "=q,X"))] | |
1286 | "" | |
1287 | "@ | |
1288 | sle. %3,%1,%2 | |
1289 | sli. %3,%1,%h2" | |
1290 | [(set_attr "type" "delayed_compare")]) | |
1291 | ||
1292 | (define_insn "" | |
1293 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") | |
cd2b37d9 | 1294 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
1295 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) |
1296 | (const_int 0))) | |
cd2b37d9 | 1297 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1298 | (ashift:SI (match_dup 1) (match_dup 2))) |
1299 | (clobber (match_scratch:SI 4 "=q,X"))] | |
1300 | "" | |
1301 | "@ | |
1302 | sle. %0,%1,%2 | |
1303 | sli. %0,%1,%h2" | |
1304 | [(set_attr "type" "delayed_compare")]) | |
1305 | ||
1306 | (define_insn "" | |
cd2b37d9 RK |
1307 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1308 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
1309 | (match_operand:SI 2 "const_int_operand" "i")) |
1310 | (match_operand:SI 3 "mask_operand" "L")))] | |
1311 | "includes_lshift_p (operands[2], operands[3])" | |
1312 | "rlinm %0,%h1,%h2,%m3,%M3") | |
1313 | ||
1314 | (define_insn "" | |
1315 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
1316 | (compare:CC | |
cd2b37d9 | 1317 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1318 | (match_operand:SI 2 "const_int_operand" "i")) |
1319 | (match_operand:SI 3 "mask_operand" "L")) | |
1320 | (const_int 0))) | |
1321 | (clobber (match_scratch:SI 4 "=r"))] | |
1322 | "includes_lshift_p (operands[2], operands[3])" | |
1323 | "rlinm. %4,%h1,%h2,%m3,%M3" | |
1324 | [(set_attr "type" "delayed_compare")]) | |
1325 | ||
1326 | (define_insn "" | |
1327 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
1328 | (compare:CC | |
cd2b37d9 | 1329 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1330 | (match_operand:SI 2 "const_int_operand" "i")) |
1331 | (match_operand:SI 3 "mask_operand" "L")) | |
1332 | (const_int 0))) | |
cd2b37d9 | 1333 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1334 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
1335 | "includes_lshift_p (operands[2], operands[3])" | |
1336 | "rlinm. %0,%h1,%h2,%m3,%M3" | |
1337 | [(set_attr "type" "delayed_compare")]) | |
1338 | ||
5c23c401 RK |
1339 | ;; The RS/6000 assembler mis-handles "sri x,x,0", so write that case as |
1340 | ;; "sli x,x,0". | |
1fd4e8c1 | 1341 | (define_insn "lshrsi3" |
cd2b37d9 RK |
1342 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1343 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
1344 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
1345 | (clobber (match_scratch:SI 3 "=q,X"))] | |
1346 | "" | |
1347 | "@ | |
1348 | sre %0,%1,%2 | |
5c23c401 | 1349 | s%A2i %0,%1,%h2") |
1fd4e8c1 RK |
1350 | |
1351 | (define_insn "" | |
1352 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") | |
cd2b37d9 | 1353 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
1354 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) |
1355 | (const_int 0))) | |
1356 | (clobber (match_scratch:SI 3 "=r,r")) | |
1357 | (clobber (match_scratch:SI 4 "=q,X"))] | |
1358 | "" | |
1359 | "@ | |
1360 | sre. %3,%1,%2 | |
5c23c401 | 1361 | s%A2i. %3,%1,%h2" |
1fd4e8c1 RK |
1362 | [(set_attr "type" "delayed_compare")]) |
1363 | ||
1364 | (define_insn "" | |
1365 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") | |
cd2b37d9 | 1366 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
1367 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) |
1368 | (const_int 0))) | |
cd2b37d9 | 1369 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1370 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
1371 | (clobber (match_scratch:SI 4 "=q,X"))] | |
1372 | "" | |
1373 | "@ | |
1374 | sre. %0,%1,%2 | |
5c23c401 | 1375 | s%A2i. %0,%1,%h2" |
1fd4e8c1 RK |
1376 | [(set_attr "type" "delayed_compare")]) |
1377 | ||
1378 | (define_insn "" | |
cd2b37d9 RK |
1379 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1380 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
1381 | (match_operand:SI 2 "const_int_operand" "i")) |
1382 | (match_operand:SI 3 "mask_operand" "L")))] | |
1383 | "includes_rshift_p (operands[2], operands[3])" | |
1384 | "rlinm %0,%1,%s2,%m3,%M3") | |
1385 | ||
1386 | (define_insn "" | |
1387 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
1388 | (compare:CC | |
cd2b37d9 | 1389 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1390 | (match_operand:SI 2 "const_int_operand" "i")) |
1391 | (match_operand:SI 3 "mask_operand" "L")) | |
1392 | (const_int 0))) | |
1393 | (clobber (match_scratch:SI 4 "=r"))] | |
1394 | "includes_rshift_p (operands[2], operands[3])" | |
1395 | "rlinm. %4,%1,%s2,%m3,%M3" | |
1396 | [(set_attr "type" "delayed_compare")]) | |
1397 | ||
1398 | (define_insn "" | |
1399 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
1400 | (compare:CC | |
cd2b37d9 | 1401 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1402 | (match_operand:SI 2 "const_int_operand" "i")) |
1403 | (match_operand:SI 3 "mask_operand" "L")) | |
1404 | (const_int 0))) | |
cd2b37d9 | 1405 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1406 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
1407 | "includes_rshift_p (operands[2], operands[3])" | |
1408 | "rlinm. %0,%1,%s2,%m3,%M3" | |
1409 | [(set_attr "type" "delayed_compare")]) | |
1410 | ||
1411 | (define_insn "" | |
cd2b37d9 | 1412 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1413 | (zero_extend:SI |
1414 | (subreg:QI | |
cd2b37d9 | 1415 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1416 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
1417 | "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" | |
1418 | "rlinm %0,%1,%s2,24,31") | |
1419 | ||
1420 | (define_insn "" | |
1421 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
1422 | (compare:CC | |
1423 | (zero_extend:SI | |
1424 | (subreg:QI | |
cd2b37d9 | 1425 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1426 | (match_operand:SI 2 "const_int_operand" "i")) 0)) |
1427 | (const_int 0))) | |
1428 | (clobber (match_scratch:SI 3 "=r"))] | |
1429 | "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" | |
1430 | "rlinm. %3,%1,%s2,24,31" | |
1431 | [(set_attr "type" "delayed_compare")]) | |
1432 | ||
1433 | (define_insn "" | |
1434 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
1435 | (compare:CC | |
1436 | (zero_extend:SI | |
1437 | (subreg:QI | |
cd2b37d9 | 1438 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1439 | (match_operand:SI 2 "const_int_operand" "i")) 0)) |
1440 | (const_int 0))) | |
cd2b37d9 | 1441 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1442 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
1443 | "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" | |
1444 | "rlinm. %0,%1,%s2,24,31" | |
1445 | [(set_attr "type" "delayed_compare")]) | |
1446 | ||
1447 | (define_insn "" | |
cd2b37d9 | 1448 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1449 | (zero_extend:SI |
1450 | (subreg:HI | |
cd2b37d9 | 1451 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1452 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
1453 | "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" | |
1454 | "rlinm %0,%1,%s2,16,31") | |
1455 | ||
1456 | (define_insn "" | |
1457 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
1458 | (compare:CC | |
1459 | (zero_extend:SI | |
1460 | (subreg:HI | |
cd2b37d9 | 1461 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1462 | (match_operand:SI 2 "const_int_operand" "i")) 0)) |
1463 | (const_int 0))) | |
1464 | (clobber (match_scratch:SI 3 "=r"))] | |
1465 | "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" | |
1466 | "rlinm. %3,%1,%s2,16,31" | |
1467 | [(set_attr "type" "delayed_compare")]) | |
1468 | ||
1469 | (define_insn "" | |
1470 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
1471 | (compare:CC | |
1472 | (zero_extend:SI | |
1473 | (subreg:HI | |
cd2b37d9 | 1474 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
1475 | (match_operand:SI 2 "const_int_operand" "i")) 0)) |
1476 | (const_int 0))) | |
cd2b37d9 | 1477 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1478 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
1479 | "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" | |
1480 | "rlinm. %0,%1,%s2,16,31" | |
1481 | [(set_attr "type" "delayed_compare")]) | |
1482 | ||
1483 | (define_insn "" | |
cd2b37d9 | 1484 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 1485 | (const_int 1) |
cd2b37d9 RK |
1486 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
1487 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
1488 | (const_int 31)))] |
1489 | "" | |
1490 | "rrib %0,%1,%2") | |
1491 | ||
1492 | (define_insn "" | |
cd2b37d9 | 1493 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 1494 | (const_int 1) |
cd2b37d9 RK |
1495 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
1496 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
1497 | (const_int 31)))] |
1498 | "" | |
1499 | "rrib %0,%1,%2") | |
1500 | ||
1501 | (define_insn "" | |
cd2b37d9 | 1502 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 1503 | (const_int 1) |
cd2b37d9 RK |
1504 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
1505 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
1506 | (const_int 1) |
1507 | (const_int 0)))] | |
1508 | "" | |
1509 | "rrib %0,%1,%2") | |
1510 | ||
1511 | (define_insn "ashrsi3" | |
cd2b37d9 RK |
1512 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1513 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
1514 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
1515 | (clobber (match_scratch:SI 3 "=q,X"))] | |
1516 | "" | |
1517 | "@ | |
1518 | srea %0,%1,%2 | |
1519 | srai %0,%1,%h2") | |
1520 | ||
1521 | (define_insn "" | |
1522 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") | |
cd2b37d9 | 1523 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
1524 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) |
1525 | (const_int 0))) | |
1526 | (clobber (match_scratch:SI 3 "=r,r")) | |
1527 | (clobber (match_scratch:SI 4 "=q,X"))] | |
1528 | "" | |
1529 | "@ | |
1530 | srea. %3,%1,%2 | |
1531 | srai. %3,%1,%h2" | |
1532 | [(set_attr "type" "delayed_compare")]) | |
1533 | ||
1534 | (define_insn "" | |
1535 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") | |
cd2b37d9 | 1536 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
1537 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) |
1538 | (const_int 0))) | |
cd2b37d9 | 1539 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1540 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
1541 | (clobber (match_scratch:SI 4 "=q,X"))] | |
1542 | "" | |
1543 | "@ | |
1544 | srea. %0,%1,%2 | |
1545 | srai. %0,%1,%h2" | |
1546 | [(set_attr "type" "delayed_compare")]) | |
1547 | ||
1548 | (define_expand "extendqisi2" | |
1549 | [(parallel [(set (match_dup 2) | |
cd2b37d9 | 1550 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1551 | (const_int 24))) |
1552 | (clobber (scratch:SI))]) | |
cd2b37d9 | 1553 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1554 | (ashiftrt:SI (match_dup 2) |
1555 | (const_int 24))) | |
1556 | (clobber (scratch:SI))])] | |
1557 | "" | |
1558 | " | |
1559 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1560 | operands[2] = gen_reg_rtx (SImode); }") | |
1561 | ||
1562 | (define_expand "extendqihi2" | |
1563 | [(parallel [(set (match_dup 2) | |
cd2b37d9 | 1564 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1565 | (const_int 24))) |
1566 | (clobber (scratch:SI))]) | |
cd2b37d9 | 1567 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1568 | (ashiftrt:SI (match_dup 2) |
1569 | (const_int 24))) | |
1570 | (clobber (scratch:SI))])] | |
1571 | "" | |
1572 | " | |
1573 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1574 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1575 | operands[2] = gen_reg_rtx (SImode); }") | |
1576 | \f | |
1577 | ;; Floating-point insns, excluding normal data motion. | |
1578 | ;; | |
1579 | ;; We pretend that we have both SFmode and DFmode insns, while, in fact, | |
1580 | ;; all fp insns are actually done in double. The only conversions we will | |
1581 | ;; do will be when storing to memory. In that case, we will use the "frsp" | |
1582 | ;; instruction before storing. | |
1583 | ;; | |
1584 | ;; Note that when we store into a single-precision memory location, we need to | |
1585 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
1586 | ;; need a scratch register for the frsp. But this is difficult when the store | |
1587 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
1588 | ;; this case, we just lose precision that we would have otherwise gotten but | |
1589 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
1590 | ||
1591 | (define_insn "extendsfdf2" | |
cd2b37d9 RK |
1592 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
1593 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1594 | "" |
1595 | "* | |
1596 | { | |
1597 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
1598 | return \"\"; | |
1599 | else | |
1600 | return \"fmr %0,%1\"; | |
1601 | }" | |
1602 | [(set_attr "type" "fp")]) | |
1603 | ||
1604 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
1605 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
1606 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1607 | "" |
1608 | "* | |
1609 | { | |
1610 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
1611 | return \"\"; | |
1612 | else | |
1613 | return \"fmr %0,%1\"; | |
1614 | }" | |
1615 | [(set_attr "type" "fp")]) | |
1616 | ||
1617 | (define_insn "negsf2" | |
cd2b37d9 RK |
1618 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
1619 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1620 | "" |
1621 | "fneg %0,%1" | |
1622 | [(set_attr "type" "fp")]) | |
1623 | ||
1624 | (define_insn "abssf2" | |
cd2b37d9 RK |
1625 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
1626 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1627 | "" |
1628 | "fabs %0,%1" | |
1629 | [(set_attr "type" "fp")]) | |
1630 | ||
1631 | (define_insn "" | |
cd2b37d9 RK |
1632 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
1633 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
1fd4e8c1 RK |
1634 | "" |
1635 | "fnabs %0,%1" | |
1636 | [(set_attr "type" "fp")]) | |
1637 | ||
1638 | (define_insn "addsf3" | |
cd2b37d9 RK |
1639 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
1640 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
1641 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1642 | "" |
1643 | "fa %0,%1,%2" | |
1644 | [(set_attr "type" "fp")]) | |
1645 | ||
1646 | (define_insn "subsf3" | |
cd2b37d9 RK |
1647 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
1648 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
1649 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1650 | "" |
1651 | "fs %0,%1,%2" | |
1652 | [(set_attr "type" "fp")]) | |
1653 | ||
1654 | (define_insn "mulsf3" | |
cd2b37d9 RK |
1655 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
1656 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
1657 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1658 | "" |
1659 | "fm %0,%1,%2" | |
1660 | [(set_attr "type" "fp")]) | |
1661 | ||
1662 | (define_insn "divsf3" | |
cd2b37d9 RK |
1663 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
1664 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
1665 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1666 | "" |
1667 | "fd %0,%1,%2" | |
1668 | [(set_attr "type" "fp")]) | |
1669 | ||
1670 | (define_insn "" | |
cd2b37d9 RK |
1671 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
1672 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
1673 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
1674 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1675 | "" |
1676 | "fma %0,%1,%2,%3" | |
1677 | [(set_attr "type" "fp")]) | |
1678 | ||
1679 | (define_insn "" | |
cd2b37d9 RK |
1680 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
1681 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
1682 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
1683 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1684 | "" |
1685 | "fms %0,%1,%2,%3" | |
1686 | [(set_attr "type" "fp")]) | |
1687 | ||
1688 | (define_insn "" | |
cd2b37d9 RK |
1689 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
1690 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
1691 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
1692 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
1fd4e8c1 RK |
1693 | "" |
1694 | "fnma %0,%1,%2,%3" | |
1695 | [(set_attr "type" "fp")]) | |
1696 | ||
1697 | (define_insn "" | |
cd2b37d9 RK |
1698 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
1699 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
1700 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
1701 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
1fd4e8c1 RK |
1702 | "" |
1703 | "fnms %0,%1,%2,%3" | |
1704 | [(set_attr "type" "fp")]) | |
1705 | ||
1706 | (define_insn "negdf2" | |
cd2b37d9 RK |
1707 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
1708 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1709 | "" |
1710 | "fneg %0,%1" | |
1711 | [(set_attr "type" "fp")]) | |
1712 | ||
1713 | (define_insn "absdf2" | |
cd2b37d9 RK |
1714 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
1715 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1716 | "" |
1717 | "fabs %0,%1" | |
1718 | [(set_attr "type" "fp")]) | |
1719 | ||
1720 | (define_insn "" | |
cd2b37d9 RK |
1721 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
1722 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
1fd4e8c1 RK |
1723 | "" |
1724 | "fnabs %0,%1" | |
1725 | [(set_attr "type" "fp")]) | |
1726 | ||
1727 | (define_insn "adddf3" | |
cd2b37d9 RK |
1728 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
1729 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
1730 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1731 | "" |
1732 | "fa %0,%1,%2" | |
1733 | [(set_attr "type" "fp")]) | |
1734 | ||
1735 | (define_insn "subdf3" | |
cd2b37d9 RK |
1736 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
1737 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
1738 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1739 | "" |
1740 | "fs %0,%1,%2" | |
1741 | [(set_attr "type" "fp")]) | |
1742 | ||
1743 | (define_insn "muldf3" | |
cd2b37d9 RK |
1744 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
1745 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
1746 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1747 | "" |
1748 | "fm %0,%1,%2" | |
1749 | [(set_attr "type" "fp")]) | |
1750 | ||
1751 | (define_insn "divdf3" | |
cd2b37d9 RK |
1752 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
1753 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
1754 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1755 | "" |
1756 | "fd %0,%1,%2" | |
1757 | [(set_attr "type" "fp")]) | |
1758 | ||
1759 | (define_insn "" | |
cd2b37d9 RK |
1760 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
1761 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
1762 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
1763 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1764 | "" |
1765 | "fma %0,%1,%2,%3" | |
1766 | [(set_attr "type" "fp")]) | |
1767 | ||
1768 | (define_insn "" | |
cd2b37d9 RK |
1769 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
1770 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
1771 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
1772 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
1773 | "" |
1774 | "fms %0,%1,%2,%3" | |
1775 | [(set_attr "type" "fp")]) | |
1776 | ||
1777 | (define_insn "" | |
cd2b37d9 RK |
1778 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
1779 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
1780 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
1781 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
1fd4e8c1 RK |
1782 | "" |
1783 | "fnma %0,%1,%2,%3" | |
1784 | [(set_attr "type" "fp")]) | |
1785 | ||
1786 | (define_insn "" | |
cd2b37d9 RK |
1787 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
1788 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
1789 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
1790 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
1fd4e8c1 RK |
1791 | "" |
1792 | "fnms %0,%1,%2,%3" | |
1793 | [(set_attr "type" "fp")]) | |
1794 | \f | |
1795 | ;; Conversions to and from floating-point. | |
1796 | (define_expand "floatsidf2" | |
1797 | [(set (match_dup 2) | |
1798 | (plus:DI (zero_extend:DI | |
cd2b37d9 | 1799 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1800 | (match_dup 3))) |
1801 | (match_dup 4))) | |
cd2b37d9 | 1802 | (set (match_operand:DF 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1803 | (minus:DF (subreg:DF (match_dup 2) 0) |
1804 | (match_dup 5)))] | |
1805 | "" | |
1806 | " | |
1807 | { | |
1808 | #if HOST_BITS_PER_INT != BITS_PER_WORD | |
1809 | /* Maybe someone can figure out how to do this in that case. I don't | |
1810 | want to right now. */ | |
1811 | abort (); | |
1812 | #endif | |
1813 | ||
1814 | operands[2] = gen_reg_rtx (DImode); | |
1815 | operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000); | |
1816 | operands[4] = immed_double_const (0, 0x43300000, DImode); | |
1817 | operands[5] = force_reg (DFmode, immed_double_const (0x43300000, | |
1818 | 0x80000000, DFmode)); | |
1819 | }") | |
1820 | ||
1821 | (define_expand "floatunssidf2" | |
1822 | [(set (match_dup 2) | |
cd2b37d9 | 1823 | (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) |
1fd4e8c1 | 1824 | (match_dup 3))) |
cd2b37d9 | 1825 | (set (match_operand:DF 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1826 | (minus:DF (subreg:DF (match_dup 2) 0) |
1827 | (match_dup 4)))] | |
1828 | "" | |
1829 | " | |
1830 | { | |
1831 | #if HOST_BITS_PER_INT != BITS_PER_WORD | |
1832 | /* Maybe someone can figure out how to do this in that case. I don't | |
1833 | want to right now. */ | |
1834 | abort (); | |
1835 | #endif | |
1836 | ||
1837 | operands[2] = gen_reg_rtx (DImode); | |
1838 | operands[3] = immed_double_const (0, 0x43300000, DImode); | |
1839 | operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode)); | |
1840 | }") | |
1841 | ||
1842 | ;; For the above two cases, we always split. | |
1843 | (define_split | |
cd2b37d9 | 1844 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1845 | (plus:DI (zero_extend:DI |
cd2b37d9 | 1846 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1847 | (match_operand:SI 2 "logical_operand" ""))) |
1848 | (match_operand:DI 3 "immediate_operand" "")))] | |
1849 | "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD | |
1850 | && GET_CODE (operands[3]) == CONST_DOUBLE | |
1851 | && CONST_DOUBLE_LOW (operands[3]) == 0" | |
1852 | [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2))) | |
1853 | (set (match_dup 4) (match_dup 5))] | |
1854 | " | |
1855 | { operands[4] = operand_subword (operands[0], 0, 0, DImode); | |
1856 | operands[5] = operand_subword (operands[3], 0, 0, DImode); | |
1857 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
1858 | }") | |
1859 | ||
1860 | (define_insn "" | |
cd2b37d9 | 1861 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 1862 | (plus:DI (zero_extend:DI |
cd2b37d9 | 1863 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") |
1fd4e8c1 RK |
1864 | (match_operand:SI 2 "logical_operand" "rKJ"))) |
1865 | (match_operand:DI 3 "immediate_operand" "n")))] | |
1866 | "HOST_BITS_PER_INT == BITS_PER_WORD | |
1867 | && GET_CODE (operands[3]) == CONST_DOUBLE | |
1868 | && CONST_DOUBLE_LOW (operands[3]) == 0" | |
1869 | "#") | |
1870 | ||
1871 | (define_split | |
cd2b37d9 RK |
1872 | [(set (match_operand:DI 0 "gpc_reg_operand" "=") |
1873 | (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1fd4e8c1 RK |
1874 | (match_operand:DI 2 "immediate_operand" "")))] |
1875 | "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD | |
1876 | && GET_CODE (operands[2]) == CONST_DOUBLE | |
1877 | && CONST_DOUBLE_LOW (operands[2]) == 0" | |
1878 | [(set (match_dup 3) (match_dup 4)) | |
1879 | (set (match_dup 5) (match_dup 1))] | |
1880 | " | |
1881 | { operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1882 | operands[4] = operand_subword (operands[2], 0, 0, DImode); | |
1883 | operands[5] = operand_subword (operands[0], 1, 0, DImode); | |
1884 | ||
1885 | if (rtx_equal_p (operands[1], operands[5])) | |
1886 | { | |
1887 | emit_move_insn (operands[3], operands[4]); | |
1888 | DONE; | |
1889 | } | |
1890 | }") | |
1891 | ||
1892 | (define_insn "" | |
cd2b37d9 RK |
1893 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
1894 | (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 RK |
1895 | (match_operand:DI 2 "immediate_operand" "n")))] |
1896 | "HOST_BITS_PER_INT == BITS_PER_WORD | |
1897 | && GET_CODE (operands[2]) == CONST_DOUBLE | |
1898 | && CONST_DOUBLE_LOW (operands[2]) == 0" | |
1899 | "#") | |
1900 | ||
1901 | (define_expand "fix_truncdfsi2" | |
cd2b37d9 RK |
1902 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1903 | (fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1904 | "" |
1905 | " | |
1906 | { | |
1907 | emit_insn (gen_trunc_call (operands[0], operands[1], | |
1908 | gen_rtx (SYMBOL_REF, Pmode, \"itrunc\"))); | |
1909 | DONE; | |
1910 | }") | |
1911 | ||
1912 | (define_expand "fixuns_truncdfsi2" | |
cd2b37d9 RK |
1913 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1914 | (unsigned_fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1915 | "" |
1916 | " | |
1917 | { | |
1918 | emit_insn (gen_trunc_call (operands[0], operands[1], | |
1919 | gen_rtx (SYMBOL_REF, Pmode, \"uitrunc\"))); | |
1920 | DONE; | |
1921 | }") | |
1922 | ||
1923 | ||
1924 | (define_expand "trunc_call" | |
1925 | [(parallel [(set (match_operand:SI 0 "" "") | |
1926 | (fix:DF (match_operand:DF 1 "" ""))) | |
1927 | (use (match_operand:SI 2 "" ""))])] | |
1928 | "" | |
1929 | " | |
1930 | { | |
1931 | rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]); | |
1932 | rtx first = XVECEXP (insns, 0, 0); | |
1933 | rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1); | |
1934 | ||
1935 | REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last, | |
1936 | REG_NOTES (first)); | |
1937 | REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last)); | |
1938 | ||
1939 | emit_insn (insns); | |
1940 | DONE; | |
1941 | }") | |
1942 | ||
1943 | (define_expand "trunc_call_rtl" | |
cd2b37d9 | 1944 | [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" "")) |
1fd4e8c1 RK |
1945 | (use (reg:DF 33)) |
1946 | (parallel [(set (reg:SI 3) | |
1947 | (call (mem:SI (match_operand 2 "" "")) (const_int 0))) | |
1948 | (clobber (scratch:SI))]) | |
cd2b37d9 | 1949 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1950 | (reg:SI 3))] |
1951 | "" | |
1952 | " | |
1953 | { | |
1954 | rs6000_trunc_used = 1; | |
1955 | }") | |
1956 | \f | |
1957 | ;; Define the DImode operations that can be done in a small number | |
1958 | ;; of instructions. | |
1959 | (define_insn "adddi3" | |
cd2b37d9 RK |
1960 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
1961 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
1962 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1963 | "" |
1964 | "a %L0,%L1,%L2\;ae %0,%1,%2") | |
1965 | ||
1966 | (define_insn "subdi3" | |
cd2b37d9 RK |
1967 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
1968 | (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
1969 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1970 | "" |
1971 | "sf %L0,%L2,%L1\;sfe %0,%2,%1") | |
1972 | ||
1973 | (define_insn "negdi3" | |
cd2b37d9 RK |
1974 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
1975 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1976 | "" |
1977 | "sfi %L0,%L1,0\;sfze %0,%1") | |
1978 | ||
1979 | (define_insn "mulsidi3" | |
cd2b37d9 RK |
1980 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
1981 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
1982 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
1fd4e8c1 RK |
1983 | (clobber (match_scratch:SI 3 "=q"))] |
1984 | "" | |
1985 | "mul %0,%1,%2\;mfmq %L0") | |
1986 | ||
1987 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
1988 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
1989 | ;; why we have the strange constraints below. | |
1990 | (define_insn "ashldi3" | |
cd2b37d9 RK |
1991 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
1992 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
1fd4e8c1 RK |
1993 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) |
1994 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
1995 | "" | |
1996 | "@ | |
1997 | sli %0,%L1,%h2\;cal %L0,0(0) | |
1998 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
1999 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5c23c401 | 2000 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2") |
1fd4e8c1 RK |
2001 | |
2002 | (define_insn "lshrdi3" | |
cd2b37d9 RK |
2003 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r") |
2004 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
1fd4e8c1 RK |
2005 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) |
2006 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
2007 | "" | |
2008 | "@ | |
5c23c401 | 2009 | cal %0,0(0)\;s%A2i %L0,%1,%h2 |
46a48c7f RK |
2010 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
2011 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
2012 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2") | |
1fd4e8c1 RK |
2013 | |
2014 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
2015 | ;; just handle shifts by constants. | |
2016 | ||
2017 | (define_expand "ashrdi3" | |
cd2b37d9 RK |
2018 | [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=") |
2019 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
2020 | (match_operand:SI 2 "general_operand" ""))) |
2021 | (clobber (match_scratch:SI 3 ""))])] | |
2022 | "" | |
2023 | " | |
2024 | { if (GET_CODE (operands[2]) != CONST_INT) | |
2025 | FAIL; | |
2026 | }") | |
2027 | ||
2028 | (define_insn "" | |
cd2b37d9 RK |
2029 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
2030 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
2031 | (match_operand:SI 2 "const_int_operand" "M,i"))) |
2032 | (clobber (match_scratch:SI 3 "=X,q"))] | |
2033 | "" | |
2034 | "@ | |
2035 | srai %0,%1,31\;srai %L0,%1,%h2 | |
46a48c7f | 2036 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2") |
1fd4e8c1 RK |
2037 | \f |
2038 | ;; Now define ways of moving data around. | |
2039 | ;; | |
2040 | ;; For SI, we special-case integers that can't be loaded in one insn. We | |
2041 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
2042 | ;; and this is even supposed to be faster, but it is simpler not to get | |
2043 | ;; integers in the TOC. | |
2044 | (define_expand "movsi" | |
2045 | [(set (match_operand:SI 0 "general_operand" "") | |
2046 | (match_operand:SI 1 "any_operand" ""))] | |
2047 | "" | |
2048 | " | |
2049 | { | |
2050 | if (GET_CODE (operands[0]) != REG) | |
2051 | operands[1] = force_reg (SImode, operands[1]); | |
2052 | ||
2053 | if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) | |
2054 | operands[1] = force_const_mem (SImode, operands[1]); | |
2055 | ||
2056 | if (GET_CODE (operands[1]) == CONST_INT | |
2057 | && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000 | |
2058 | && (INTVAL (operands[1]) & 0xffff) != 0) | |
2059 | { | |
2060 | emit_move_insn (operands[0], | |
2061 | gen_rtx (CONST_INT, VOIDmode, | |
2062 | INTVAL (operands[1]) & 0xffff0000)); | |
2063 | emit_insn (gen_iorsi3 (operands[0], operands[0], | |
2064 | gen_rtx (CONST_INT, VOIDmode, | |
2065 | INTVAL (operands[1]) & 0xffff))); | |
2066 | DONE; | |
2067 | } | |
2068 | }") | |
2069 | ||
2070 | (define_insn "" | |
5c23c401 RK |
2071 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l") |
2072 | (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r"))] | |
cd2b37d9 RK |
2073 | "gpc_reg_operand (operands[0], SImode) |
2074 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 RK |
2075 | "@ |
2076 | ai %0,%1,0 | |
2077 | l%U1%X1 %0,%1 | |
2078 | st%U0%X0 %1,%0 | |
2079 | cal %0,%1(0) | |
2080 | cau %0,0,%u1 | |
2081 | mf%1 %0 | |
5c23c401 | 2082 | mt%0 %1 |
1fd4e8c1 | 2083 | mt%0 %1" |
5c23c401 | 2084 | [(set_attr "type" "*,load,*,*,*,*,*,mtlr")]) |
1fd4e8c1 | 2085 | |
77fa0940 RK |
2086 | ;; Split a load of a large constant into the appropriate two-insn |
2087 | ;; sequence. | |
2088 | ||
2089 | (define_split | |
2090 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2091 | (match_operand:SI 1 "const_int_operand" ""))] | |
2092 | "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000 | |
2093 | && (INTVAL (operands[1]) & 0xffff) != 0" | |
2094 | [(set (match_dup 0) | |
2095 | (match_dup 2)) | |
2096 | (set (match_dup 0) | |
2097 | (ior:SI (match_dup 0) | |
2098 | (match_dup 3)))] | |
2099 | " | |
2100 | { | |
2101 | operands[2] = gen_rtx (CONST_INT, VOIDmode, | |
2102 | INTVAL (operands[1]) & 0xffff0000); | |
2103 | operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff); | |
2104 | }") | |
2105 | ||
1fd4e8c1 RK |
2106 | (define_insn "" |
2107 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
cd2b37d9 | 2108 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 2109 | (const_int 0))) |
cd2b37d9 | 2110 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] |
1fd4e8c1 RK |
2111 | "" |
2112 | "ai. %0,%1,0" | |
2113 | [(set_attr "type" "compare")]) | |
2114 | \f | |
2115 | (define_expand "movhi" | |
2116 | [(set (match_operand:HI 0 "general_operand" "") | |
2117 | (match_operand:HI 1 "any_operand" ""))] | |
2118 | "" | |
2119 | " | |
2120 | { | |
2121 | if (GET_CODE (operands[0]) != REG) | |
2122 | operands[1] = force_reg (HImode, operands[1]); | |
2123 | ||
2124 | if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) | |
2125 | operands[1] = force_const_mem (HImode, operands[1]); | |
2126 | }") | |
2127 | ||
2128 | (define_insn "" | |
2129 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h") | |
2130 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))] | |
cd2b37d9 RK |
2131 | "gpc_reg_operand (operands[0], HImode) |
2132 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 RK |
2133 | "@ |
2134 | oril %0,%1,0 | |
2135 | lhz%U1%X1 %0,%1 | |
2136 | sth%U0%X0 %1,%0 | |
2137 | cal %0,%w1(0) | |
2138 | mf%1 %0 | |
2139 | mt%0 %1" | |
2140 | [(set_attr "type" "*,load,*,*,*,*")]) | |
2141 | ||
2142 | (define_expand "movqi" | |
2143 | [(set (match_operand:QI 0 "general_operand" "") | |
2144 | (match_operand:QI 1 "any_operand" ""))] | |
2145 | "" | |
2146 | " | |
2147 | { | |
2148 | if (GET_CODE (operands[0]) != REG) | |
2149 | operands[1] = force_reg (QImode, operands[1]); | |
2150 | ||
2151 | if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT) | |
2152 | operands[1] = force_const_mem (QImode, operands[1]); | |
2153 | }") | |
2154 | ||
2155 | (define_insn "" | |
2156 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h") | |
2157 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))] | |
cd2b37d9 RK |
2158 | "gpc_reg_operand (operands[0], QImode) |
2159 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 RK |
2160 | "@ |
2161 | oril %0,%1,0 | |
2162 | lbz%U1%X1 %0,%1 | |
2163 | stb%U0%X0 %1,%0 | |
2164 | cal %0,%1(0) | |
2165 | mf%1 %0 | |
2166 | mt%0 %1" | |
2167 | [(set_attr "type" "*,load,*,*,*,*")]) | |
2168 | \f | |
2169 | ;; Here is how to move condition codes around. When we store CC data in | |
2170 | ;; an integer register or memory, we store just the high-order 4 bits. | |
2171 | ;; This lets us not shift in the most common case of CR0. | |
2172 | (define_expand "movcc" | |
2173 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
2174 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
2175 | "" | |
2176 | "") | |
2177 | ||
2178 | (define_insn "" | |
2179 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") | |
2180 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] | |
2181 | "register_operand (operands[0], CCmode) | |
2182 | || register_operand (operands[1], CCmode)" | |
2183 | "@ | |
2184 | mcrf %0,%1 | |
2185 | mtcrf 128,%1 | |
2186 | rlinm %1,%1,%F0,0,31\;mtcrf %R0,%1\;rlinm %1,%1,%f0,0,31 | |
2187 | mfcr %0 | |
2188 | mfcr %0\;rlinm %0,%0,%f1,0,3 | |
2189 | ai %0,%1,0 | |
2190 | l%U1%X1 %0,%1 | |
2191 | st%U0%U1 %1,%0" | |
2192 | [(set_attr "type" "*,*,*,compare,*,*,load,*")]) | |
2193 | \f | |
2194 | ;; For floating-point, we normally deal with the floating-point registers. | |
2195 | ;; The sole exception is that parameter passing can produce floating-point | |
2196 | ;; values in fixed-point registers. Unless the value is a simple constant | |
2197 | ;; or already in memory, we deal with this by allocating memory and copying | |
2198 | ;; the value explicitly via that memory location. | |
2199 | (define_expand "movsf" | |
2200 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
2201 | (match_operand:SF 1 "any_operand" ""))] | |
2202 | "" | |
2203 | " | |
2204 | { | |
2205 | /* If we are called from reload, we might be getting a SUBREG of a hard | |
2206 | reg. So expand it. */ | |
2207 | if (GET_CODE (operands[0]) == SUBREG | |
2208 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
2209 | && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER) | |
2210 | operands[0] = alter_subreg (operands[0]); | |
2211 | if (GET_CODE (operands[1]) == SUBREG | |
2212 | && GET_CODE (SUBREG_REG (operands[1])) == REG | |
2213 | && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER) | |
2214 | operands[1] = alter_subreg (operands[1]); | |
2215 | ||
2216 | /* If we are being called from reload, it is possible that operands[1] | |
2217 | is a hard non-fp register. So handle those cases. */ | |
2218 | if (reload_in_progress && GET_CODE (operands[1]) == REG | |
2219 | && REGNO (operands[1]) < 32) | |
2220 | { | |
2221 | rtx stack_slot; | |
2222 | ||
2223 | /* Remember that we only see a pseudo here if it didn't get a hard | |
2224 | register, so it is memory. */ | |
2225 | if (GET_CODE (operands[0]) == MEM | |
2226 | || (GET_CODE (operands[0]) == REG | |
2227 | && (REGNO (operands[0]) < 32 | |
2228 | || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)) | |
2229 | || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)) | |
2230 | { | |
2231 | emit_move_insn (operand_subword (operands[0], 0, 0, SFmode), | |
2232 | operand_subword (operands[1], 0, 0, SFmode)); | |
2233 | DONE; | |
2234 | } | |
2235 | ||
2236 | stack_slot = gen_rtx (MEM, SFmode, plus_constant (stack_pointer_rtx, 4)); | |
2237 | emit_move_insn (stack_slot, operands[1]); | |
2238 | emit_move_insn (operands[0], stack_slot); | |
2239 | DONE; | |
2240 | } | |
2241 | ||
2242 | if (GET_CODE (operands[0]) == MEM) | |
2243 | operands[1] = force_reg (SFmode, operands[1]); | |
2244 | ||
2245 | if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) | |
2246 | { | |
2247 | rtx stack_slot; | |
2248 | ||
2249 | if (GET_CODE (operands[1]) == MEM | |
2250 | #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE) | |
2251 | || GET_CODE (operands[1]) == CONST_DOUBLE | |
2252 | #endif | |
2253 | || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32) | |
2254 | || (reload_in_progress && GET_CODE (operands[1]) == REG | |
2255 | && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)) | |
2256 | { | |
2257 | emit_move_insn (operand_subword (operands[0], 0, 0, SFmode), | |
2258 | operand_subword (operands[1], 0, 0, SFmode)); | |
2259 | DONE; | |
2260 | } | |
2261 | ||
2262 | if (reload_in_progress) | |
2263 | stack_slot = gen_rtx (MEM, SFmode, | |
2264 | plus_constant (stack_pointer_rtx, 4)); | |
2265 | else | |
2266 | stack_slot = assign_stack_temp (SFmode, 4, 0); | |
2267 | emit_move_insn (stack_slot, operands[1]); | |
2268 | emit_move_insn (operands[0], stack_slot); | |
2269 | DONE; | |
2270 | } | |
2271 | ||
2272 | if (CONSTANT_P (operands[1])) | |
2273 | { | |
2274 | operands[1] = force_const_mem (SFmode, operands[1]); | |
2275 | if (! memory_address_p (SFmode, XEXP (operands[1], 0)) | |
2276 | && ! reload_in_progress) | |
2277 | operands[1] = change_address (operands[1], SFmode, | |
2278 | XEXP (operands[1], 0)); | |
2279 | } | |
2280 | }") | |
2281 | ||
2282 | (define_insn "" | |
cd2b37d9 | 2283 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
2284 | (match_operand:SF 1 "mem_or_easy_const_operand" "G,m"))] |
2285 | "REGNO (operands[0]) <= 31" | |
2286 | "@ | |
2287 | # | |
2288 | l%U1%X1 %0,%1" | |
2289 | [(set_attr "type" "*,load")]) | |
2290 | ||
2291 | (define_split | |
cd2b37d9 | 2292 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
2293 | (match_operand:SF 1 "easy_fp_constant" ""))] |
2294 | "reload_completed && REGNO (operands[0]) <= 31" | |
2295 | [(set (match_dup 2) (match_dup 3))] | |
2296 | " | |
2297 | { operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
2298 | operands[3] = operand_subword (operands[1], 0, 0, SFmode); }") | |
2299 | ||
2300 | (define_insn "" | |
2301 | [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m") | |
2302 | (match_operand:SF 1 "input_operand" "f,m,f"))] | |
cd2b37d9 RK |
2303 | "gpc_reg_operand (operands[0], SFmode) |
2304 | || gpc_reg_operand (operands[1], SFmode)" | |
1fd4e8c1 RK |
2305 | "@ |
2306 | fmr %0,%1 | |
2307 | lfs%U1%X1 %0,%1 | |
2308 | frsp %1,%1\;stfs%U0%X0 %1,%0" | |
2309 | [(set_attr "type" "fp,load,*")]) | |
2310 | \f | |
2311 | (define_expand "movdf" | |
2312 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
2313 | (match_operand:DF 1 "any_operand" ""))] | |
2314 | "" | |
2315 | " | |
2316 | { | |
2317 | /* If we are called from reload, we might be getting a SUBREG of a hard | |
2318 | reg. So expand it. */ | |
2319 | if (GET_CODE (operands[0]) == SUBREG | |
2320 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
2321 | && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER) | |
2322 | operands[0] = alter_subreg (operands[0]); | |
2323 | if (GET_CODE (operands[1]) == SUBREG | |
2324 | && GET_CODE (SUBREG_REG (operands[1])) == REG | |
2325 | && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER) | |
2326 | operands[1] = alter_subreg (operands[1]); | |
2327 | ||
2328 | /* If we are being called from reload, it is possible that operands[1] | |
2329 | is a hard non-fp register. So handle those cases. */ | |
2330 | if (reload_in_progress && GET_CODE (operands[1]) == REG | |
2331 | && REGNO (operands[1]) < 32) | |
2332 | { | |
2333 | rtx stack_slot; | |
2334 | ||
2335 | /* Remember that we only see a pseudo here if it didn't get a hard | |
2336 | register, so it is memory. */ | |
2337 | if (GET_CODE (operands[0]) == MEM | |
2338 | || (GET_CODE (operands[0]) == REG | |
2339 | && (REGNO (operands[0]) < 32 | |
2340 | || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))) | |
2341 | { | |
2342 | emit_move_insn (operand_subword (operands[0], 0, 0, DFmode), | |
2343 | operand_subword (operands[1], 0, 0, DFmode)); | |
2344 | emit_move_insn (operand_subword (operands[0], 1, 0, DFmode), | |
2345 | operand_subword (operands[1], 1, 0, DFmode)); | |
2346 | DONE; | |
2347 | } | |
2348 | ||
2349 | stack_slot = gen_rtx (MEM, DFmode, plus_constant (stack_pointer_rtx, 8)); | |
2350 | emit_move_insn (stack_slot, operands[1]); | |
2351 | emit_move_insn (operands[0], stack_slot); | |
2352 | DONE; | |
2353 | } | |
2354 | ||
2355 | if (GET_CODE (operands[0]) == MEM) | |
2356 | { | |
2357 | if (GET_CODE (operands[1]) == MEM) | |
2358 | { | |
2359 | emit_move_insn (operand_subword (operands[0], 0, 0, DFmode), | |
2360 | operand_subword (operands[1], 0, 0, DFmode)); | |
2361 | emit_move_insn (operand_subword (operands[0], 1, 0, DFmode), | |
2362 | operand_subword (operands[1], 1, 0, DFmode)); | |
2363 | DONE; | |
2364 | } | |
2365 | ||
2366 | operands[1] = force_reg (DFmode, operands[1]); | |
2367 | } | |
2368 | ||
2369 | if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) | |
2370 | { | |
2371 | rtx stack_slot; | |
2372 | ||
2373 | if (GET_CODE (operands[1]) == MEM | |
2374 | #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE) | |
2375 | || GET_CODE (operands[1]) == CONST_DOUBLE | |
2376 | #endif | |
2377 | || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32) | |
2378 | || (reload_in_progress && GET_CODE (operands[1]) == REG | |
2379 | && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)) | |
2380 | { | |
2381 | emit_move_insn (operand_subword (operands[0], 0, 0, DFmode), | |
2382 | operand_subword (operands[1], 0, 0, DFmode)); | |
2383 | emit_move_insn (operand_subword (operands[0], 1, 0, DFmode), | |
2384 | operand_subword (operands[1], 1, 0, DFmode)); | |
2385 | DONE; | |
2386 | } | |
2387 | ||
2388 | if (reload_in_progress) | |
2389 | stack_slot = gen_rtx (MEM, DFmode, | |
2390 | plus_constant (stack_pointer_rtx, 8)); | |
2391 | else | |
2392 | stack_slot = assign_stack_temp (DFmode, 8, 0); | |
2393 | emit_move_insn (stack_slot, operands[1]); | |
2394 | emit_move_insn (operands[0], stack_slot); | |
2395 | DONE; | |
2396 | } | |
2397 | ||
2398 | if (CONSTANT_P (operands[1])) | |
2399 | { | |
2400 | operands[1] = force_const_mem (DFmode, operands[1]); | |
2401 | if (! memory_address_p (DFmode, XEXP (operands[1], 0)) | |
2402 | && ! reload_in_progress) | |
2403 | operands[1] = change_address (operands[1], DFmode, | |
2404 | XEXP (operands[1], 0)); | |
2405 | } | |
2406 | }") | |
2407 | ||
2408 | (define_insn "" | |
cd2b37d9 | 2409 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
2410 | (match_operand:DF 1 "mem_or_easy_const_operand" "G,m"))] |
2411 | "REGNO (operands[0]) <= 31" | |
2412 | "@ | |
2413 | # | |
2414 | l %0,%1\;l %L0,%L1" | |
2415 | [(set_attr "type" "*,load")]) | |
2416 | ||
2417 | (define_split | |
cd2b37d9 | 2418 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
2419 | (match_operand:DF 1 "easy_fp_constant" ""))] |
2420 | "reload_completed && REGNO (operands[0]) <= 31" | |
2421 | [(set (match_dup 2) (match_dup 3)) | |
2422 | (set (match_dup 4) (match_dup 5))] | |
2423 | " | |
2424 | { operands[2] = operand_subword (operands[0], 0, 0, DFmode); | |
2425 | operands[3] = operand_subword (operands[1], 0, 0, DFmode); | |
2426 | operands[4] = operand_subword (operands[0], 1, 0, DFmode); | |
2427 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); }") | |
2428 | ||
2429 | (define_insn "" | |
2430 | [(set (match_operand:DF 0 "fp_reg_or_mem_operand" "=f,f,m") | |
2431 | (match_operand:DF 1 "fp_reg_or_mem_operand" "f,m,f"))] | |
cd2b37d9 RK |
2432 | "gpc_reg_operand (operands[0], DFmode) |
2433 | || gpc_reg_operand (operands[1], DFmode)" | |
1fd4e8c1 RK |
2434 | "@ |
2435 | fmr %0,%1 | |
2436 | lfd%U1%X1 %0,%1 | |
2437 | stfd%U0%X0 %1,%0" | |
2438 | [(set_attr "type" "fp,load,*")]) | |
2439 | \f | |
2440 | ;; Next come the multi-word integer load and store and the load and store | |
2441 | ;; multiple insns. | |
2442 | (define_expand "movdi" | |
2443 | [(set (match_operand:DI 0 "general_operand" "") | |
2444 | (match_operand:DI 1 "general_operand" ""))] | |
2445 | "" | |
2446 | " | |
2447 | { | |
2448 | if (GET_CODE (operands[0]) == MEM) | |
2449 | operands[1] = force_reg (DImode, operands[1]); | |
2450 | ||
2451 | else if (GET_CODE (operands[1]) == CONST_DOUBLE | |
2452 | || GET_CODE (operands[1]) == CONST_INT) | |
2453 | { | |
2454 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
2455 | operand_subword (operands[1], 0, 0, DImode)); | |
2456 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), | |
2457 | operand_subword (operands[1], 1, 0, DImode)); | |
2458 | DONE; | |
2459 | } | |
2460 | }") | |
2461 | ||
2462 | (define_insn "" | |
2463 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m") | |
2464 | (match_operand:DI 1 "input_operand" "r,m,r"))] | |
cd2b37d9 RK |
2465 | "gpc_reg_operand (operands[0], DImode) |
2466 | || gpc_reg_operand (operands[1], DImode)" | |
1fd4e8c1 RK |
2467 | "* |
2468 | { | |
2469 | switch (which_alternative) | |
2470 | { | |
2471 | case 0: | |
2472 | /* We normally copy the low-numbered register first. However, if | |
2473 | the first register operand 0 is the same as the second register of | |
2474 | operand 1, we must copy in the opposite order. */ | |
2475 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
2476 | return \"oril %L0,%L1,0\;oril %0,%1,0\"; | |
2477 | else | |
2478 | return \"oril %0,%1,0\;oril %L0,%L1,0\"; | |
2479 | case 1: | |
2480 | /* If the low-address word is used in the address, we must load it | |
2481 | last. Otherwise, load it first. Note that we cannot have | |
2482 | auto-increment in that case since the address register is known to be | |
2483 | dead. */ | |
2484 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
2485 | operands [1], 0)) | |
2486 | return \"l %L0,%L1\;l %0,%1\"; | |
2487 | else | |
2488 | return \"l%U1 %0,%1\;l %L0,%L1\"; | |
2489 | case 2: | |
2490 | return \"st%U0 %1,%0\;st %L1,%L0\"; | |
2491 | } | |
2492 | }" | |
2493 | [(set_attr "type" "*,load,*")]) | |
2494 | \f | |
2495 | ;; TImode is similar, except that we usually want to compute the address into | |
2496 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
2497 | ;; clobbered in stsi, so we need a SCRATCH for it. | |
2498 | (define_expand "movti" | |
2499 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
2500 | (match_operand:TI 1 "general_operand" "")) | |
2501 | (clobber (scratch:SI))])] | |
2502 | "" | |
2503 | " | |
2504 | { | |
2505 | if (GET_CODE (operands[0]) == MEM) | |
2506 | operands[1] = force_reg (TImode, operands[1]); | |
2507 | ||
2508 | if (GET_CODE (operands[0]) == MEM | |
2509 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
2510 | && ! reload_in_progress) | |
2511 | operands[0] = change_address (operands[0], TImode, | |
2512 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
2513 | ||
2514 | if (GET_CODE (operands[1]) == MEM | |
2515 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
2516 | && ! reload_in_progress) | |
2517 | operands[1] = change_address (operands[1], TImode, | |
2518 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
2519 | }") | |
2520 | ||
2521 | ;; We say that MQ is clobbered in the last alternative because the first | |
2522 | ;; alternative would never get used otherwise since it would need a reload | |
2523 | ;; while the 2nd alternative would not. We put memory cases first so they | |
2524 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
2525 | ;; giving the SCRATCH mq. | |
2526 | (define_insn "" | |
2527 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r") | |
2528 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) | |
2529 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
cd2b37d9 RK |
2530 | "gpc_reg_operand (operands[0], TImode) |
2531 | || gpc_reg_operand (operands[1], TImode)" | |
1fd4e8c1 RK |
2532 | "* |
2533 | { | |
2534 | switch (which_alternative) | |
2535 | { | |
2536 | case 0: | |
2537 | return \"stsi %1,%P0,16\"; | |
2538 | ||
2539 | case 1: | |
2540 | return \"st%U0 %1,%0\;st %L1,%L0\;st %Y1,%Y0\;st %Z1,%Z0\"; | |
2541 | ||
2542 | case 2: | |
2543 | /* Normally copy registers with lowest numbered register copied first. | |
2544 | But copy in the other order if the first register of the output | |
2545 | is the second, third, or fourth register in the input. */ | |
2546 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
2547 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
2548 | return \"oril %Z0,%Z1,0\;oril %Y0,%Y1,0\;oril %L0,%L1,0\;oril %0,%1,0\"; | |
2549 | else | |
2550 | return \"oril %0,%1,0\;oril %L0,%L1,0\;oril %Y0,%Y1,0\;oril %Z0,%Z1,0\"; | |
2551 | case 3: | |
2552 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
2553 | fall through to generating four loads. */ | |
2554 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
2555 | return \"lsi %0,%P1,16\"; | |
2556 | /* ... fall through ... */ | |
2557 | case 4: | |
2558 | /* If the address register is the same as the register for the lowest- | |
2559 | addressed word, load it last. Similarly for the next two words. | |
2560 | Otherwise load lowest address to highest. */ | |
2561 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
2562 | operands[1], 0)) | |
2563 | return \"l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\;l %0,%1\"; | |
2564 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, | |
2565 | REGNO (operands[0]) + 2, operands[1], 0)) | |
2566 | return \"l %0,%1\;l %Y0,%Y1\;l %Z0,%Z1\;l %L0,%L1\"; | |
2567 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, | |
2568 | REGNO (operands[0]) + 3, operands[1], 0)) | |
2569 | return \"l %0,%1\;l %L0,%L1\;l %Z0,%Z1\;l %Y0,%Y1\"; | |
2570 | else | |
2571 | return \"l%U1 %0,%1\;l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\"; | |
2572 | } | |
2573 | }" | |
2574 | [(set_attr "type" "*,load,load,*,*")]) | |
2575 | \f | |
2576 | (define_expand "load_multiple" | |
2577 | [(match_parallel 3 "" [(set (match_operand:SI 0 "" "") | |
2578 | (match_operand:SI 1 "" "")) | |
2579 | (use (match_operand:SI 2 "" ""))])] | |
2580 | "" | |
2581 | " | |
2582 | { | |
2583 | int regno; | |
2584 | int count; | |
2585 | rtx from; | |
2586 | int i; | |
2587 | ||
2588 | /* Support only loading a constant number of fixed-point registers from | |
2589 | memory and only bother with this if more than two; the machine | |
2590 | doesn't support more than eight. */ | |
2591 | if (GET_CODE (operands[2]) != CONST_INT | |
2592 | || INTVAL (operands[2]) <= 2 | |
2593 | || INTVAL (operands[2]) > 8 | |
2594 | || GET_CODE (operands[1]) != MEM | |
2595 | || GET_CODE (operands[0]) != REG | |
2596 | || REGNO (operands[0]) >= 32) | |
2597 | FAIL; | |
2598 | ||
2599 | count = INTVAL (operands[2]); | |
2600 | regno = REGNO (operands[0]); | |
2601 | ||
2602 | operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count)); | |
2603 | from = force_reg (SImode, XEXP (operands[1], 0)); | |
2604 | ||
2605 | for (i = 0; i < count; i++) | |
2606 | XVECEXP (operands[3], 0, i) | |
2607 | = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i), | |
2608 | gen_rtx (MEM, SImode, plus_constant (from, i * 4))); | |
2609 | }") | |
2610 | ||
2611 | (define_insn "" | |
2612 | [(match_parallel 0 "load_multiple_operation" | |
cd2b37d9 | 2613 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2614 | (match_operand:SI 2 "indirect_operand" "Q"))])] |
2615 | "" | |
2616 | "* | |
2617 | { | |
2618 | /* We have to handle the case where the pseudo used to contain the address | |
2619 | is assigned to one of the output registers. In that case, do the | |
2620 | lsi, but then load the correct value. This is a bit of a mess, but is | |
2621 | the best we can do. */ | |
2622 | static char result[100]; | |
2623 | char newload[40]; | |
2624 | int i; | |
2625 | ||
2626 | strcpy (result, \"lsi %1,%P2,%N0\"); | |
2627 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
2628 | if (refers_to_regno_p (REGNO (operands[1]) + i, | |
2629 | REGNO (operands[1]) + i + 1, operands[2], 0)) | |
2630 | { | |
2631 | sprintf (newload, \"\;l %d,%d(%d)\", | |
2632 | REGNO (operands[1]) + i, | |
2633 | i * 4, REGNO (XEXP (operands[2], 0))); | |
2634 | strcat (result, newload); | |
2635 | } | |
2636 | ||
2637 | return result; | |
2638 | }" | |
2639 | [(set_attr "type" "load")]) | |
2640 | \f | |
2641 | (define_expand "store_multiple" | |
2642 | [(match_parallel 3 "" [(set (match_operand:SI 0 "" "") | |
2643 | (match_operand:SI 1 "" "")) | |
2644 | (clobber (scratch:SI)) | |
2645 | (use (match_operand:SI 2 "" ""))])] | |
2646 | "" | |
2647 | " | |
2648 | { | |
2649 | int regno; | |
2650 | int count; | |
2651 | rtx to; | |
2652 | int i; | |
2653 | ||
2654 | /* Support only storing a constant number of fixed-point registers to | |
2655 | memory and only bother with this if more than two; the machine | |
2656 | doesn't support more than eight. */ | |
2657 | if (GET_CODE (operands[2]) != CONST_INT | |
2658 | || INTVAL (operands[2]) <= 2 | |
2659 | || INTVAL (operands[2]) > 8 | |
2660 | || GET_CODE (operands[0]) != MEM | |
2661 | || GET_CODE (operands[1]) != REG | |
2662 | || REGNO (operands[1]) >= 32) | |
2663 | FAIL; | |
2664 | ||
2665 | count = INTVAL (operands[2]); | |
2666 | regno = REGNO (operands[1]); | |
2667 | ||
2668 | operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1)); | |
2669 | to = force_reg (SImode, XEXP (operands[0], 0)); | |
2670 | ||
2671 | XVECEXP (operands[3], 0, 0) | |
2672 | = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]); | |
2673 | XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode, | |
2674 | gen_rtx (SCRATCH, SImode)); | |
2675 | ||
2676 | for (i = 1; i < count; i++) | |
2677 | XVECEXP (operands[3], 0, i + 1) | |
2678 | = gen_rtx (SET, VOIDmode, | |
2679 | gen_rtx (MEM, SImode, plus_constant (to, i * 4)), | |
2680 | gen_rtx (REG, SImode, regno + i)); | |
2681 | }") | |
2682 | ||
2683 | (define_insn "" | |
2684 | [(match_parallel 0 "store_multiple_operation" | |
2685 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 2686 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
2687 | (clobber (match_scratch:SI 3 "=q"))])] |
2688 | "" | |
2689 | "stsi %2,%P1,%O0") | |
2690 | \f | |
2691 | ;; Define insns that do load or store with update. Some of these we can | |
2692 | ;; get by using pre-decrement or pre-increment, but the hardware can also | |
2693 | ;; do cases where the increment is not the size of the object. | |
2694 | ;; | |
2695 | ;; In all these cases, we use operands 0 and 1 for the register being | |
2696 | ;; incremented because those are the operands that local-alloc will | |
2697 | ;; tie and these are the pair most likely to be tieable (and the ones | |
2698 | ;; that will benefit the most). | |
2699 | ||
2700 | (define_insn "" | |
cd2b37d9 RK |
2701 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
2702 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 2703 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 2704 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
2705 | (plus:SI (match_dup 1) (match_dup 2)))] |
2706 | "" | |
2707 | "@ | |
2708 | lux %3,%1,%2 | |
2709 | lu %3,%2(%1)" | |
2710 | [(set_attr "type" "load,load")]) | |
2711 | ||
2712 | (define_insn "" | |
cd2b37d9 | 2713 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 2714 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
2715 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
2716 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 RK |
2717 | (plus:SI (match_dup 1) (match_dup 2)))] |
2718 | "" | |
2719 | "@ | |
2720 | stux %3,%1,%2 | |
2721 | stu %3,%2(%1)") | |
2722 | ||
2723 | (define_insn "" | |
cd2b37d9 RK |
2724 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
2725 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 2726 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 2727 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
2728 | (plus:SI (match_dup 1) (match_dup 2)))] |
2729 | "" | |
2730 | "@ | |
2731 | lhzux %3,%1,%2 | |
2732 | lhzu %3,%2(%1)" | |
2733 | [(set_attr "type" "load,load")]) | |
2734 | ||
2735 | (define_insn "" | |
cd2b37d9 | 2736 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 2737 | (zero_extend:SI |
cd2b37d9 | 2738 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 2739 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 2740 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
2741 | (plus:SI (match_dup 1) (match_dup 2)))] |
2742 | "" | |
2743 | "@ | |
2744 | lhzux %3,%1,%2 | |
2745 | lhzu %3,%2(%1)" | |
2746 | [(set_attr "type" "load,load")]) | |
2747 | ||
2748 | (define_insn "" | |
cd2b37d9 | 2749 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 2750 | (sign_extend:SI |
cd2b37d9 | 2751 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 2752 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 2753 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
2754 | (plus:SI (match_dup 1) (match_dup 2)))] |
2755 | "" | |
2756 | "@ | |
2757 | lhaux %3,%1,%2 | |
2758 | lhau %3,%2(%1)" | |
2759 | [(set_attr "type" "load,load")]) | |
2760 | ||
2761 | (define_insn "" | |
cd2b37d9 | 2762 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 2763 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
2764 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
2765 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 RK |
2766 | (plus:SI (match_dup 1) (match_dup 2)))] |
2767 | "" | |
2768 | "@ | |
2769 | sthux %3,%1,%2 | |
2770 | sthu %3,%2(%1)" | |
2771 | [(set_attr "type" "load,load")]) | |
2772 | ||
2773 | (define_insn "" | |
cd2b37d9 RK |
2774 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
2775 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 2776 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 2777 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
2778 | (plus:SI (match_dup 1) (match_dup 2)))] |
2779 | "" | |
2780 | "@ | |
2781 | lbzux %3,%1,%2 | |
2782 | lbzu %3,%2(%1)" | |
2783 | [(set_attr "type" "load,load")]) | |
2784 | ||
2785 | (define_insn "" | |
cd2b37d9 | 2786 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 2787 | (zero_extend:SI |
cd2b37d9 | 2788 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 2789 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 2790 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
2791 | (plus:SI (match_dup 1) (match_dup 2)))] |
2792 | "" | |
2793 | "@ | |
2794 | lbzux %3,%1,%2 | |
2795 | lbzu %3,%2(%1)" | |
2796 | [(set_attr "type" "load,load")]) | |
2797 | ||
2798 | (define_insn "" | |
cd2b37d9 | 2799 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 2800 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
2801 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
2802 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 RK |
2803 | (plus:SI (match_dup 1) (match_dup 2)))] |
2804 | "" | |
2805 | "@ | |
2806 | stbux %3,%1,%2 | |
2807 | stbu %3,%2(%1)") | |
2808 | ||
2809 | (define_insn "" | |
cd2b37d9 RK |
2810 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
2811 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 2812 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 2813 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
2814 | (plus:SI (match_dup 1) (match_dup 2)))] |
2815 | "" | |
2816 | "@ | |
2817 | lfsux %3,%1,%2 | |
2818 | lfsu %3,%2(%1)" | |
2819 | [(set_attr "type" "load,load")]) | |
2820 | ||
2821 | (define_insn "" | |
cd2b37d9 | 2822 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 2823 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
2824 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
2825 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 RK |
2826 | (plus:SI (match_dup 1) (match_dup 2)))] |
2827 | "" | |
2828 | "@ | |
2829 | frsp %3,%3\;stfsux %3,%1,%2 | |
2830 | frsp %3,%3\;stfsu %3,%2(%1)") | |
2831 | ||
2832 | (define_insn "" | |
cd2b37d9 RK |
2833 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
2834 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 2835 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 2836 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
2837 | (plus:SI (match_dup 1) (match_dup 2)))] |
2838 | "" | |
2839 | "@ | |
2840 | lfdux %3,%1,%2 | |
2841 | lfdu %3,%2(%1)" | |
2842 | [(set_attr "type" "load,load")]) | |
2843 | ||
2844 | (define_insn "" | |
cd2b37d9 | 2845 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 2846 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
2847 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
2848 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 RK |
2849 | (plus:SI (match_dup 1) (match_dup 2)))] |
2850 | "" | |
2851 | "@ | |
2852 | stfdux %3,%1,%2 | |
2853 | stfdu %3,%2(%1)") | |
2854 | \f | |
2855 | ;; Next come insns related to the calling sequence. | |
2856 | ;; | |
2857 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
59257ff7 | 2858 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
2859 | |
2860 | (define_expand "allocate_stack" | |
2861 | [(set (reg:SI 1) | |
2862 | (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_cint_operand" "")))] | |
2863 | "" | |
2864 | " | |
2865 | { rtx chain = gen_reg_rtx (SImode); | |
2866 | rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx); | |
2867 | ||
2868 | emit_move_insn (chain, stack_bot); | |
2869 | emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0])); | |
2870 | emit_move_insn (stack_bot, chain); | |
2871 | DONE; | |
2872 | }") | |
59257ff7 RK |
2873 | |
2874 | ;; These patterns say how to save and restore the stack pointer. We need not | |
2875 | ;; save the stack pointer at function level since we are careful to | |
2876 | ;; preserve the backchain. At block level, we have to restore the backchain | |
2877 | ;; when we restore the stack pointer. | |
2878 | ;; | |
2879 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
2880 | ;; backchain and restore both. Note that in the nonlocal case, the | |
2881 | ;; save area is a memory location. | |
2882 | ||
2883 | (define_expand "save_stack_function" | |
2884 | [(use (const_int 0))] | |
2885 | "" | |
2886 | "") | |
2887 | ||
2888 | (define_expand "restore_stack_function" | |
2889 | [(use (const_int 0))] | |
2890 | "" | |
2891 | "") | |
2892 | ||
2893 | (define_expand "restore_stack_block" | |
2894 | [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" ""))) | |
2895 | (set (match_dup 0) (match_operand:SI 1 "register_operand" "")) | |
2896 | (set (mem:SI (match_dup 0)) (match_dup 2))] | |
2897 | "" | |
2898 | " | |
2899 | { operands[2] = gen_reg_rtx (SImode); }") | |
2900 | ||
2901 | (define_expand "save_stack_nonlocal" | |
2902 | [(match_operand:DI 0 "memory_operand" "") | |
2903 | (match_operand:SI 1 "register_operand" "")] | |
2904 | "" | |
2905 | " | |
2906 | { | |
2907 | rtx temp = gen_reg_rtx (SImode); | |
2908 | ||
2909 | /* Copy the backchain to the first word, sp to the second. */ | |
2910 | emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1])); | |
2911 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp); | |
2912 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]); | |
2913 | DONE; | |
2914 | }") | |
2915 | ||
2916 | (define_expand "restore_stack_nonlocal" | |
2917 | [(match_operand:SI 0 "register_operand" "") | |
2918 | (match_operand:DI 1 "memory_operand" "")] | |
2919 | "" | |
2920 | " | |
2921 | { | |
2922 | rtx temp = gen_reg_rtx (SImode); | |
2923 | ||
2924 | /* Restore the backchain from the first word, sp from the second. */ | |
2925 | emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode)); | |
2926 | emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode)); | |
2927 | emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp); | |
2928 | DONE; | |
2929 | }") | |
1fd4e8c1 RK |
2930 | \f |
2931 | ;; A function pointer is a pointer to a data area whose first word contains | |
2932 | ;; the actual address of the function, whose second word contains a pointer | |
2933 | ;; to its TOC, and whose third word contains a value to place in the static | |
2934 | ;; chain register (r11). Note that if we load the static chain, our | |
2935 | ;; "trampoline" need not have any executable code. | |
2936 | ;; | |
2937 | ;; operands[0] is an SImode pseudo in which we place the address of the | |
2938 | ;; function. | |
2939 | ;; operands[1] is the address of data area of the function to call | |
2940 | ||
2941 | (define_expand "call_via_ptr" | |
cd2b37d9 RK |
2942 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2943 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
1fd4e8c1 RK |
2944 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) |
2945 | (reg:SI 2)) | |
2946 | (set (reg:SI 2) | |
2947 | (mem:SI (plus:SI (match_dup 1) | |
2948 | (const_int 4)))) | |
2949 | (set (reg:SI 11) | |
2950 | (mem:SI (plus:SI (match_dup 1) | |
2951 | (const_int 8)))) | |
2952 | (use (reg:SI 2)) | |
2953 | (use (reg:SI 11))] | |
2954 | "" | |
2955 | "") | |
2956 | ||
2957 | (define_expand "call" | |
2958 | [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" "")) | |
2959 | (match_operand 1 "" "")) | |
2960 | (clobber (scratch:SI))])] | |
2961 | "" | |
2962 | " | |
2963 | { | |
2964 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) | |
2965 | abort (); | |
2966 | ||
2967 | operands[0] = XEXP (operands[0], 0); | |
2968 | if (GET_CODE (operands[0]) != SYMBOL_REF) | |
2969 | { | |
2970 | rtx temp = gen_reg_rtx (SImode); | |
2971 | ||
2972 | emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0]))); | |
2973 | operands[0] = temp; | |
2974 | } | |
2975 | }") | |
2976 | ||
2977 | (define_expand "call_value" | |
2978 | [(parallel [(set (match_operand 0 "" "") | |
2979 | (call (mem:SI (match_operand:SI 1 "address_operand" "")) | |
2980 | (match_operand 2 "" ""))) | |
2981 | (clobber (scratch:SI))])] | |
2982 | "" | |
2983 | " | |
2984 | { | |
2985 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) | |
2986 | abort (); | |
2987 | ||
2988 | operands[1] = XEXP (operands[1], 0); | |
2989 | if (GET_CODE (operands[1]) != SYMBOL_REF) | |
2990 | { | |
2991 | rtx temp = gen_reg_rtx (SImode); | |
2992 | ||
2993 | emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1]))); | |
2994 | operands[1] = temp; | |
2995 | } | |
2996 | }") | |
2997 | ||
2998 | (define_insn "" | |
2999 | [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s")) | |
3000 | (match_operand 1 "" "fg,fg")) | |
9482d6de | 3001 | (clobber (match_scratch:SI 2 "=l,l"))] |
1fd4e8c1 RK |
3002 | "" |
3003 | "@ | |
3004 | brl\;l 2,20(1) | |
3005 | bl %z0\;cror 15,15,15") | |
3006 | ||
3007 | (define_insn "" | |
3008 | [(set (match_operand 0 "" "fg,fg") | |
3009 | (call (mem:SI (match_operand:SI 1 "call_operand" "l,s")) | |
3010 | (match_operand 2 "" "fg,fg"))) | |
3011 | (clobber (match_scratch:SI 3 "=l,l"))] | |
3012 | "" | |
3013 | "@ | |
3014 | brl\;l 2,20(1) | |
3015 | bl %z1\;cror 15,15,15") | |
3016 | \f | |
3017 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
3018 | ;; signed & unsigned, and one type of branch. | |
3019 | ;; | |
3020 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
3021 | ;; insns, and branches. We store the operands of compares until we see | |
3022 | ;; how it is used. | |
3023 | (define_expand "cmpsi" | |
3024 | [(set (cc0) | |
cd2b37d9 | 3025 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3026 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
3027 | "" | |
3028 | " | |
3029 | { | |
3030 | /* Take care of the possibility that operands[1] might be negative but | |
3031 | this might be a logical operation. That insn doesn't exist. */ | |
3032 | if (GET_CODE (operands[1]) == CONST_INT | |
3033 | && INTVAL (operands[1]) < 0) | |
3034 | operands[1] = force_reg (SImode, operands[1]); | |
3035 | ||
3036 | rs6000_compare_op0 = operands[0]; | |
3037 | rs6000_compare_op1 = operands[1]; | |
3038 | rs6000_compare_fp_p = 0; | |
3039 | DONE; | |
3040 | }") | |
3041 | ||
3042 | (define_expand "cmpsf" | |
cd2b37d9 RK |
3043 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
3044 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
3045 | "" |
3046 | " | |
3047 | { | |
3048 | rs6000_compare_op0 = operands[0]; | |
3049 | rs6000_compare_op1 = operands[1]; | |
3050 | rs6000_compare_fp_p = 1; | |
3051 | DONE; | |
3052 | }") | |
3053 | ||
3054 | (define_expand "cmpdf" | |
cd2b37d9 RK |
3055 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
3056 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
3057 | "" |
3058 | " | |
3059 | { | |
3060 | rs6000_compare_op0 = operands[0]; | |
3061 | rs6000_compare_op1 = operands[1]; | |
3062 | rs6000_compare_fp_p = 1; | |
3063 | DONE; | |
3064 | }") | |
3065 | ||
3066 | (define_expand "beq" | |
3067 | [(set (match_dup 2) (match_dup 1)) | |
3068 | (set (pc) | |
3069 | (if_then_else (eq (match_dup 2) | |
3070 | (const_int 0)) | |
3071 | (label_ref (match_operand 0 "" "")) | |
3072 | (pc)))] | |
3073 | "" | |
3074 | " | |
3075 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
3076 | operands[1] = gen_rtx (COMPARE, mode, | |
3077 | rs6000_compare_op0, rs6000_compare_op1); | |
3078 | operands[2] = gen_reg_rtx (mode); | |
3079 | }") | |
3080 | ||
3081 | (define_expand "bne" | |
3082 | [(set (match_dup 2) (match_dup 1)) | |
3083 | (set (pc) | |
3084 | (if_then_else (ne (match_dup 2) | |
3085 | (const_int 0)) | |
3086 | (label_ref (match_operand 0 "" "")) | |
3087 | (pc)))] | |
3088 | "" | |
3089 | " | |
3090 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
3091 | operands[1] = gen_rtx (COMPARE, mode, | |
3092 | rs6000_compare_op0, rs6000_compare_op1); | |
3093 | operands[2] = gen_reg_rtx (mode); | |
3094 | }") | |
3095 | ||
3096 | (define_expand "blt" | |
3097 | [(set (match_dup 2) (match_dup 1)) | |
3098 | (set (pc) | |
3099 | (if_then_else (lt (match_dup 2) | |
3100 | (const_int 0)) | |
3101 | (label_ref (match_operand 0 "" "")) | |
3102 | (pc)))] | |
3103 | "" | |
3104 | " | |
3105 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
3106 | operands[1] = gen_rtx (COMPARE, mode, | |
3107 | rs6000_compare_op0, rs6000_compare_op1); | |
3108 | operands[2] = gen_reg_rtx (mode); | |
3109 | }") | |
3110 | ||
3111 | (define_expand "bgt" | |
3112 | [(set (match_dup 2) (match_dup 1)) | |
3113 | (set (pc) | |
3114 | (if_then_else (gt (match_dup 2) | |
3115 | (const_int 0)) | |
3116 | (label_ref (match_operand 0 "" "")) | |
3117 | (pc)))] | |
3118 | "" | |
3119 | " | |
3120 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
3121 | operands[1] = gen_rtx (COMPARE, mode, | |
3122 | rs6000_compare_op0, rs6000_compare_op1); | |
3123 | operands[2] = gen_reg_rtx (mode); | |
3124 | }") | |
3125 | ||
3126 | (define_expand "ble" | |
3127 | [(set (match_dup 2) (match_dup 1)) | |
3128 | (set (pc) | |
3129 | (if_then_else (le (match_dup 2) | |
3130 | (const_int 0)) | |
3131 | (label_ref (match_operand 0 "" "")) | |
3132 | (pc)))] | |
3133 | "" | |
3134 | " | |
3135 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
3136 | operands[1] = gen_rtx (COMPARE, mode, | |
3137 | rs6000_compare_op0, rs6000_compare_op1); | |
3138 | operands[2] = gen_reg_rtx (mode); | |
3139 | }") | |
3140 | ||
3141 | (define_expand "bge" | |
3142 | [(set (match_dup 2) (match_dup 1)) | |
3143 | (set (pc) | |
3144 | (if_then_else (ge (match_dup 2) | |
3145 | (const_int 0)) | |
3146 | (label_ref (match_operand 0 "" "")) | |
3147 | (pc)))] | |
3148 | "" | |
3149 | " | |
3150 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
3151 | operands[1] = gen_rtx (COMPARE, mode, | |
3152 | rs6000_compare_op0, rs6000_compare_op1); | |
3153 | operands[2] = gen_reg_rtx (mode); | |
3154 | }") | |
3155 | ||
3156 | (define_expand "bgtu" | |
3157 | [(set (match_dup 2) (match_dup 1)) | |
3158 | (set (pc) | |
3159 | (if_then_else (gtu (match_dup 2) | |
3160 | (const_int 0)) | |
3161 | (label_ref (match_operand 0 "" "")) | |
3162 | (pc)))] | |
3163 | "" | |
3164 | " | |
3165 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
3166 | rs6000_compare_op0, rs6000_compare_op1); | |
3167 | operands[2] = gen_reg_rtx (CCUNSmode); | |
3168 | }") | |
3169 | ||
3170 | (define_expand "bltu" | |
3171 | [(set (match_dup 2) (match_dup 1)) | |
3172 | (set (pc) | |
3173 | (if_then_else (ltu (match_dup 2) | |
3174 | (const_int 0)) | |
3175 | (label_ref (match_operand 0 "" "")) | |
3176 | (pc)))] | |
3177 | "" | |
3178 | " | |
3179 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
3180 | rs6000_compare_op0, rs6000_compare_op1); | |
3181 | operands[2] = gen_reg_rtx (CCUNSmode); | |
3182 | }") | |
3183 | ||
3184 | (define_expand "bgeu" | |
3185 | [(set (match_dup 2) (match_dup 1)) | |
3186 | (set (pc) | |
3187 | (if_then_else (geu (match_dup 2) | |
3188 | (const_int 0)) | |
3189 | (label_ref (match_operand 0 "" "")) | |
3190 | (pc)))] | |
3191 | "" | |
3192 | " | |
3193 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
3194 | rs6000_compare_op0, rs6000_compare_op1); | |
3195 | operands[2] = gen_reg_rtx (CCUNSmode); | |
3196 | }") | |
3197 | ||
3198 | (define_expand "bleu" | |
3199 | [(set (match_dup 2) (match_dup 1)) | |
3200 | (set (pc) | |
3201 | (if_then_else (leu (match_dup 2) | |
3202 | (const_int 0)) | |
3203 | (label_ref (match_operand 0 "" "")) | |
3204 | (pc)))] | |
3205 | "" | |
3206 | " | |
3207 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
3208 | rs6000_compare_op0, rs6000_compare_op1); | |
3209 | operands[2] = gen_reg_rtx (CCUNSmode); | |
3210 | }") | |
3211 | ||
3212 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. | |
3213 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
3214 | ;; with an scc insns. However, due to the order that combine see the | |
3215 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
3216 | ;; the cases we don't want to handle. | |
3217 | (define_expand "seq" | |
3218 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 3219 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3220 | (eq:SI (match_dup 2) (const_int 0)))] |
3221 | "" | |
3222 | " | |
3223 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
3224 | operands[1] = gen_rtx (COMPARE, mode, | |
3225 | rs6000_compare_op0, rs6000_compare_op1); | |
3226 | operands[2] = gen_reg_rtx (mode); | |
3227 | }") | |
3228 | ||
3229 | (define_expand "sne" | |
3230 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 3231 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3232 | (ne:SI (match_dup 2) (const_int 0)))] |
3233 | "" | |
3234 | " | |
3235 | { if (! rs6000_compare_fp_p) | |
3236 | FAIL; | |
3237 | ||
3238 | operands[1] = gen_rtx (COMPARE, CCFPmode, | |
3239 | rs6000_compare_op0, rs6000_compare_op1); | |
3240 | operands[2] = gen_reg_rtx (CCFPmode); | |
3241 | }") | |
3242 | ||
3243 | ;; A > 0 is best done using the portable sequence, so fail in that case. | |
3244 | (define_expand "sgt" | |
3245 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 3246 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3247 | (gt:SI (match_dup 2) (const_int 0)))] |
3248 | "" | |
3249 | " | |
3250 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
3251 | ||
3252 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
3253 | FAIL; | |
3254 | ||
3255 | operands[1] = gen_rtx (COMPARE, mode, | |
3256 | rs6000_compare_op0, rs6000_compare_op1); | |
3257 | operands[2] = gen_reg_rtx (mode); | |
3258 | }") | |
3259 | ||
3260 | ;; A < 0 is best done in the portable way for A an integer. | |
3261 | (define_expand "slt" | |
3262 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 3263 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3264 | (lt:SI (match_dup 2) (const_int 0)))] |
3265 | "" | |
3266 | " | |
3267 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
3268 | ||
3269 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
3270 | FAIL; | |
3271 | ||
3272 | operands[1] = gen_rtx (COMPARE, mode, | |
3273 | rs6000_compare_op0, rs6000_compare_op1); | |
3274 | operands[2] = gen_reg_rtx (mode); | |
3275 | }") | |
3276 | ||
3277 | (define_expand "sge" | |
3278 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 3279 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3280 | (ge:SI (match_dup 2) (const_int 0)))] |
3281 | "" | |
3282 | " | |
3283 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
3284 | operands[1] = gen_rtx (COMPARE, mode, | |
3285 | rs6000_compare_op0, rs6000_compare_op1); | |
3286 | operands[2] = gen_reg_rtx (mode); | |
3287 | }") | |
3288 | ||
3289 | ;; A <= 0 is best done the portable way for A an integer. | |
3290 | (define_expand "sle" | |
3291 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 3292 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3293 | (le:SI (match_dup 2) (const_int 0)))] |
3294 | "" | |
3295 | " | |
3296 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
3297 | ||
3298 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
3299 | FAIL; | |
3300 | ||
3301 | operands[1] = gen_rtx (COMPARE, mode, | |
3302 | rs6000_compare_op0, rs6000_compare_op1); | |
3303 | operands[2] = gen_reg_rtx (mode); | |
3304 | }") | |
3305 | ||
3306 | (define_expand "sgtu" | |
3307 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 3308 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3309 | (gtu:SI (match_dup 2) (const_int 0)))] |
3310 | "" | |
3311 | " | |
3312 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
3313 | rs6000_compare_op0, rs6000_compare_op1); | |
3314 | operands[2] = gen_reg_rtx (CCUNSmode); | |
3315 | }") | |
3316 | ||
3317 | (define_expand "sltu" | |
3318 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 3319 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3320 | (ltu:SI (match_dup 2) (const_int 0)))] |
3321 | "" | |
3322 | " | |
3323 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
3324 | rs6000_compare_op0, rs6000_compare_op1); | |
3325 | operands[2] = gen_reg_rtx (CCUNSmode); | |
3326 | }") | |
3327 | ||
3328 | (define_expand "sgeu" | |
3329 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 3330 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3331 | (geu:SI (match_dup 2) (const_int 0)))] |
3332 | "" | |
3333 | " | |
3334 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
3335 | rs6000_compare_op0, rs6000_compare_op1); | |
3336 | operands[2] = gen_reg_rtx (CCUNSmode); | |
3337 | }") | |
3338 | ||
3339 | (define_expand "sleu" | |
3340 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 3341 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3342 | (leu:SI (match_dup 2) (const_int 0)))] |
3343 | "" | |
3344 | " | |
3345 | { operands[1] = gen_rtx (COMPARE, CCUNSmode, | |
3346 | rs6000_compare_op0, rs6000_compare_op1); | |
3347 | operands[2] = gen_reg_rtx (CCUNSmode); | |
3348 | }") | |
3349 | \f | |
3350 | ;; Here are the actual compare insns. | |
3351 | (define_insn "" | |
3352 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
cd2b37d9 | 3353 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3354 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
3355 | "" | |
3356 | "cmp%I2 %0,%1,%2" | |
3357 | [(set_attr "type" "compare")]) | |
3358 | ||
f357808b RK |
3359 | ;; If we are comparing a register for equality with a large constant, |
3360 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
3361 | ;; register for the result of the XOR. | |
3362 | ||
3363 | (define_split | |
3364 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 3365 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 3366 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 3367 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
3368 | "find_single_use (operands[0], insn, 0) |
3369 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
3370 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
3371 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
3372 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
3373 | " | |
3374 | { | |
3375 | /* Get the constant we are comparing against, C, and see what it looks like | |
3376 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
3377 | with C to get the sign-extended value. */ | |
3378 | ||
3379 | int c = INTVAL (operands[2]); | |
3380 | int sextc = (c << 16) >> 16; | |
3381 | int xorv = c ^ sextc; | |
3382 | ||
3383 | operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv); | |
3384 | operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc); | |
3385 | }") | |
3386 | ||
1fd4e8c1 RK |
3387 | (define_insn "" |
3388 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") | |
cd2b37d9 | 3389 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3390 | (match_operand:SI 2 "reg_or_u_short_operand" "rI")))] |
3391 | "" | |
3392 | "cmpl%I2 %0,%1,%W2" | |
3393 | [(set_attr "type" "compare")]) | |
3394 | ||
3395 | ;; The following two insns don't exist as single insns, but if we provide | |
3396 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
3397 | ;; of the required delay between a compare and branch. We generate code for | |
3398 | ;; them by splitting. | |
3399 | ||
3400 | (define_insn "" | |
3401 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 3402 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 3403 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 3404 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3405 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
3406 | "" | |
3407 | "#") | |
3408 | ||
3409 | (define_insn "" | |
3410 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 3411 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 3412 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 3413 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3414 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
3415 | "" | |
3416 | "#") | |
3417 | ||
3418 | (define_split | |
3419 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 3420 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 3421 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 3422 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3423 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
3424 | "" | |
3425 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
3426 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
3427 | ||
3428 | (define_split | |
3429 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 3430 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 3431 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 3432 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
3433 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
3434 | "" | |
3435 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
3436 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
3437 | ||
3438 | (define_insn "" | |
3439 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
cd2b37d9 RK |
3440 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
3441 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
3442 | "" |
3443 | "fcmpu %0,%1,%2" | |
3444 | [(set_attr "type" "fpcompare")]) | |
3445 | ||
3446 | (define_insn "" | |
3447 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
cd2b37d9 RK |
3448 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
3449 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
1fd4e8c1 RK |
3450 | "" |
3451 | "fcmpu %0,%1,%2" | |
3452 | [(set_attr "type" "fpcompare")]) | |
3453 | \f | |
3454 | ;; Now we have the scc insns. We can do some combinations because of the | |
3455 | ;; way the machine works. | |
3456 | ;; | |
3457 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
3458 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
3459 | ;; cases the insns below which don't use an intermediate CR field will | |
3460 | ;; be used instead. | |
1fd4e8c1 | 3461 | (define_insn "" |
cd2b37d9 | 3462 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3463 | (match_operator:SI 1 "scc_comparison_operator" |
3464 | [(match_operand 2 "cc_reg_operand" "y") | |
3465 | (const_int 0)]))] | |
3466 | "" | |
3467 | "%D1mfcr %0\;rlinm %0,%0,%J1,31,31") | |
3468 | ||
3469 | (define_insn "" | |
3470 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
3471 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
3472 | [(match_operand 2 "cc_reg_operand" "y") | |
3473 | (const_int 0)]) | |
3474 | (const_int 0))) | |
cd2b37d9 | 3475 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3476 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
3477 | "" | |
3478 | "%D1mfcr %3\;rlinm. %3,%3,%J1,30,31" | |
3479 | [(set_attr "type" "delayed_compare")]) | |
3480 | ||
3481 | (define_insn "" | |
cd2b37d9 | 3482 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3483 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
3484 | [(match_operand 2 "cc_reg_operand" "y") | |
3485 | (const_int 0)]) | |
3486 | (match_operand:SI 3 "const_int_operand" "n")))] | |
3487 | "" | |
3488 | "* | |
3489 | { | |
3490 | int is_bit = ccr_bit (operands[1], 1); | |
3491 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
3492 | int count; | |
3493 | ||
3494 | if (is_bit >= put_bit) | |
3495 | count = is_bit - put_bit; | |
3496 | else | |
3497 | count = 32 - (put_bit - is_bit); | |
3498 | ||
3499 | operands[4] = gen_rtx (CONST_INT, VOIDmode, count); | |
3500 | operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit); | |
3501 | ||
3502 | return \"%D1mfcr %0\;rlinm %0,%0,%4,%5,%5\"; | |
3503 | }") | |
3504 | ||
3505 | (define_insn "" | |
3506 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
3507 | (compare:CC | |
3508 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
3509 | [(match_operand 2 "cc_reg_operand" "y") | |
3510 | (const_int 0)]) | |
3511 | (match_operand:SI 3 "const_int_operand" "n")) | |
3512 | (const_int 0))) | |
cd2b37d9 | 3513 | (set (match_operand:SI 4 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3514 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
3515 | (match_dup 3)))] | |
3516 | "" | |
3517 | "* | |
3518 | { | |
3519 | int is_bit = ccr_bit (operands[1], 1); | |
3520 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
3521 | int count; | |
3522 | ||
3523 | if (is_bit >= put_bit) | |
3524 | count = is_bit - put_bit; | |
3525 | else | |
3526 | count = 32 - (put_bit - is_bit); | |
3527 | ||
3528 | operands[5] = gen_rtx (CONST_INT, VOIDmode, count); | |
3529 | operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit); | |
3530 | ||
3531 | return \"%D1mfcr %4\;rlinm. %4,%4,%5,%6,%6\"; | |
3532 | }" | |
3533 | [(set_attr "type" "delayed_compare")]) | |
3534 | ||
c5defebb RK |
3535 | ;; If we are comparing the result of two comparisons, this can be done |
3536 | ;; using creqv or crxor. | |
3537 | ||
3538 | (define_insn "" | |
3539 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
3540 | (compare:CCEQ (match_operator 1 "scc_comparison_operator" | |
3541 | [(match_operand 2 "cc_reg_operand" "y") | |
3542 | (const_int 0)]) | |
3543 | (match_operator 3 "scc_comparison_operator" | |
3544 | [(match_operand 4 "cc_reg_operand" "y") | |
3545 | (const_int 0)])))] | |
3546 | "REGNO (operands[2]) != REGNO (operands[4])" | |
3547 | "* | |
3548 | { | |
3549 | enum rtx_code code1, code2; | |
3550 | ||
3551 | code1 = GET_CODE (operands[1]); | |
3552 | code2 = GET_CODE (operands[3]); | |
3553 | ||
3554 | if ((code1 == EQ || code1 == LT || code1 == GT | |
3555 | || code1 == LTU || code1 == GTU | |
3556 | || (code1 != NE && GET_MODE (operands[2]) == CCFPmode)) | |
3557 | != | |
3558 | (code2 == EQ || code2 == LT || code2 == GT | |
3559 | || code2 == LTU || code2 == GTU | |
3560 | || (code2 != NE && GET_MODE (operands[4]) == CCFPmode))) | |
3561 | return \"%C1%C3crxor %E0,%j1,%j3\"; | |
3562 | else | |
3563 | return \"%C1%C3creqv %E0,%j1,%j3\"; | |
3564 | }") | |
3565 | ||
3566 | ;; There is a 3 cycle delay between consecutive mfcr instructions | |
3567 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
3568 | ||
3569 | (define_peephole | |
cd2b37d9 | 3570 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
3571 | (match_operator:SI 1 "scc_comparison_operator" |
3572 | [(match_operand 2 "cc_reg_operand" "y") | |
3573 | (const_int 0)])) | |
cd2b37d9 | 3574 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
3575 | (match_operator:SI 4 "scc_comparison_operator" |
3576 | [(match_operand 5 "cc_reg_operand" "y") | |
3577 | (const_int 0)]))] | |
3578 | "REGNO (operands[2]) != REGNO (operands[5])" | |
3579 | "%D1%D4mfcr %3\;rlinm %0,%3,%J1,31,31\;rlinm %3,%3,%J4,31,31") | |
3580 | ||
1fd4e8c1 RK |
3581 | ;; There are some scc insns that can be done directly, without a compare. |
3582 | ;; These are faster because they don't involve the communications between | |
3583 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
3584 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
3585 | ;; | |
3586 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
3587 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
3588 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
3589 | ;; cases where it is no more expensive than (neg (scc ..)). | |
3590 | ||
3591 | ;; Have reload force a constant into a register for the simple insns that | |
3592 | ;; otherwise won't accept constants. We do this because it is faster than | |
3593 | ;; the cmp/mfcr sequence we would otherwise generate. | |
3594 | ||
3595 | (define_insn "" | |
cd2b37d9 RK |
3596 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
3597 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
1fd4e8c1 RK |
3598 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))) |
3599 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] | |
3600 | "" | |
3601 | "@ | |
3602 | xor %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0 | |
3603 | sfi %3,%1,0\;ae %0,%3,%1 | |
3604 | xoril %0,%1,%b2\;sfi %3,%0,0\;ae %0,%3,%0 | |
3605 | xoriu %0,%1,%u2\;sfi %3,%0,0\;ae %0,%3,%0 | |
3606 | sfi %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0") | |
3607 | ||
3608 | (define_insn "" | |
3609 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") | |
3610 | (compare:CC | |
cd2b37d9 | 3611 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
1fd4e8c1 RK |
3612 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) |
3613 | (const_int 0))) | |
cd2b37d9 | 3614 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
1fd4e8c1 RK |
3615 | (eq:SI (match_dup 1) (match_dup 2))) |
3616 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] | |
3617 | "" | |
3618 | "@ | |
3619 | xor %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0 | |
3620 | sfi %3,%1,0\;ae. %0,%3,%1 | |
3621 | xoril %0,%1,%b2\;sfi %3,%0,0\;ae. %0,%3,%0 | |
3622 | xoriu %0,%1,%u2\;sfi %3,%0,0\;ae. %0,%3,%0 | |
3623 | sfi %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0" | |
3624 | [(set_attr "type" "compare")]) | |
3625 | ||
3626 | (define_insn "" | |
cd2b37d9 RK |
3627 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
3628 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
1fd4e8c1 | 3629 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) |
cd2b37d9 | 3630 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) |
1fd4e8c1 RK |
3631 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
3632 | "" | |
3633 | "@ | |
3634 | xor %4,%1,%2\;sfi %4,%4,0\;aze %0,%3 | |
3635 | sfi %4,%1,0\;aze %0,%3 | |
3636 | xoril %4,%1,%b2\;sfi %4,%4,0\;aze %0,%3 | |
3637 | xoriu %4,%1,%u2\;sfi %4,%4,0\;aze %0,%3 | |
3638 | sfi %4,%1,%2\;sfi %4,%4,0\;aze %0,%3") | |
3639 | ||
3640 | (define_insn "" | |
3641 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x") | |
3642 | (compare:CC | |
3643 | (plus:SI | |
cd2b37d9 | 3644 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
1fd4e8c1 | 3645 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) |
cd2b37d9 | 3646 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) |
1fd4e8c1 RK |
3647 | (const_int 0))) |
3648 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] | |
3649 | "" | |
3650 | "@ | |
3651 | xor %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3 | |
3652 | sfi %4,%1,0\;aze. %0,%3 | |
3653 | xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %4,%3 | |
3654 | xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %4,%3 | |
3655 | sfi %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3" | |
3656 | [(set_attr "type" "compare")]) | |
3657 | ||
3658 | (define_insn "" | |
3659 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x") | |
3660 | (compare:CC | |
3661 | (plus:SI | |
cd2b37d9 | 3662 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
1fd4e8c1 | 3663 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) |
cd2b37d9 | 3664 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) |
1fd4e8c1 | 3665 | (const_int 0))) |
cd2b37d9 | 3666 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
1fd4e8c1 RK |
3667 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
3668 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] | |
3669 | "" | |
3670 | "@ | |
3671 | xor %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3 | |
3672 | sfi %4,%1,0\;aze. %4,%3 | |
3673 | xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %0,%3 | |
3674 | xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %0,%3 | |
3675 | sfi %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3" | |
3676 | [(set_attr "type" "compare")]) | |
3677 | ||
3678 | (define_insn "" | |
cd2b37d9 RK |
3679 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
3680 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r") | |
1fd4e8c1 RK |
3681 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))] |
3682 | "" | |
3683 | "@ | |
3684 | xor %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0 | |
3685 | ai %0,%1,-1\;sfe %0,%0,%0 | |
3686 | xoril %0,%1,%b2\;ai %0,%0,-1\;sfe %0,%0,%0 | |
3687 | xoriu %0,%1,%u2\;ai %0,%0,-1\;sfe %0,%0,%0 | |
3688 | sfi %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0") | |
3689 | ||
3690 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. | |
3691 | (define_insn "" | |
cd2b37d9 | 3692 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 3693 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 3694 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 3695 | (const_int 31)) |
cd2b37d9 | 3696 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
3697 | (clobber (match_scratch:SI 3 "=&r"))] |
3698 | "" | |
3699 | "ai %3,%1,-1\;aze %0,%2") | |
3700 | ||
3701 | (define_insn "" | |
3702 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
3703 | (compare:CC | |
3704 | (plus:SI (lshiftrt:SI | |
cd2b37d9 | 3705 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 3706 | (const_int 31)) |
cd2b37d9 | 3707 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
3708 | (const_int 0))) |
3709 | (clobber (match_scratch:SI 3 "=&r"))] | |
3710 | "" | |
3711 | "ai %3,%1,-1\;aze. %3,%2" | |
3712 | [(set_attr "type" "compare")]) | |
3713 | ||
3714 | (define_insn "" | |
3715 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
3716 | (compare:CC | |
3717 | (plus:SI (lshiftrt:SI | |
cd2b37d9 | 3718 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 3719 | (const_int 31)) |
cd2b37d9 | 3720 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 3721 | (const_int 0))) |
cd2b37d9 | 3722 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3723 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
3724 | (match_dup 2))) | |
3725 | (clobber (match_scratch:SI 3 "=&r"))] | |
3726 | "" | |
3727 | "ai %3,%1,-1\;aze. %0,%2" | |
3728 | [(set_attr "type" "compare")]) | |
3729 | ||
3730 | (define_insn "" | |
cd2b37d9 RK |
3731 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3732 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3733 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
3734 | (clobber (match_scratch:SI 3 "=r,X"))] | |
3735 | "" | |
3736 | "@ | |
3737 | doz %3,%2,%1\;sfi %0,%3,0\;ae %0,%0,%3 | |
3738 | ai %0,%1,-1\;aze %0,%0\;sri %0,%0,31") | |
3739 | ||
3740 | (define_insn "" | |
3741 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x") | |
3742 | (compare:CC | |
cd2b37d9 | 3743 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
3744 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
3745 | (const_int 0))) | |
cd2b37d9 | 3746 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3747 | (le:SI (match_dup 1) (match_dup 2))) |
3748 | (clobber (match_scratch:SI 3 "=r,X"))] | |
3749 | "" | |
3750 | "@ | |
3751 | doz %3,%2,%1\;sfi %0,%3,0\;ae. %0,%0,%3 | |
3752 | ai %0,%1,-1\;aze %0,%0\;sri. %0,%0,31" | |
3753 | [(set_attr "type" "delayed_compare,compare")]) | |
3754 | ||
3755 | (define_insn "" | |
cd2b37d9 RK |
3756 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3757 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 3758 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
cd2b37d9 | 3759 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 RK |
3760 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
3761 | "" | |
3762 | "@ | |
3763 | doz %4,%2,%1\;sfi %4,%4,0\;aze %0,%3 | |
3764 | srai %4,%1,31\;sf %4,%1,%4\;aze %0,%3") | |
3765 | ||
3766 | (define_insn "" | |
3767 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") | |
3768 | (compare:CC | |
cd2b37d9 | 3769 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 3770 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
cd2b37d9 | 3771 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
1fd4e8c1 RK |
3772 | (const_int 0))) |
3773 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
3774 | "" | |
3775 | "@ | |
3776 | doz %4,%2,%1\;sfi %4,%4,0\;aze. %4,%3 | |
3777 | srai %4,%1,31\;sf %4,%1,%4\;aze. %4,%3" | |
3778 | [(set_attr "type" "compare")]) | |
3779 | ||
3780 | (define_insn "" | |
3781 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") | |
3782 | (compare:CC | |
cd2b37d9 | 3783 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 3784 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
cd2b37d9 | 3785 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 3786 | (const_int 0))) |
cd2b37d9 | 3787 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3788 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
3789 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
3790 | "" | |
3791 | "@ | |
3792 | doz %4,%2,%1\;sfi %4,%4,0\;aze. %0,%3 | |
3793 | srai %4,%1,31\;sf %4,%1,%4\;aze. %0,%3" | |
3794 | [(set_attr "type" "compare")]) | |
3795 | ||
3796 | (define_insn "" | |
cd2b37d9 RK |
3797 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3798 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3799 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
3800 | "" | |
3801 | "@ | |
3802 | doz %0,%2,%1\;ai %0,%0,-1\;sfe %0,%0,%0 | |
3803 | ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31") | |
3804 | ||
3805 | (define_insn "" | |
cd2b37d9 RK |
3806 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3807 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3808 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
3809 | "" | |
3810 | "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0") | |
3811 | ||
3812 | (define_insn "" | |
3813 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
3814 | (compare:CC | |
cd2b37d9 | 3815 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3816 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
3817 | (const_int 0))) | |
cd2b37d9 | 3818 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3819 | (leu:SI (match_dup 1) (match_dup 2)))] |
3820 | "" | |
3821 | "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae. %0,%0,%0" | |
3822 | [(set_attr "type" "compare")]) | |
3823 | ||
3824 | (define_insn "" | |
cd2b37d9 RK |
3825 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3826 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3827 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 3828 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
3829 | (clobber (match_scratch:SI 4 "=&r"))] |
3830 | "" | |
3831 | "sf%I2 %4,%1,%2\;aze %0,%3") | |
3832 | ||
3833 | (define_insn "" | |
3834 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
3835 | (compare:CC | |
cd2b37d9 | 3836 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 3837 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 3838 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
3839 | (const_int 0))) |
3840 | (clobber (match_scratch:SI 4 "=&r"))] | |
3841 | "" | |
3842 | "sf%I2 %4,%1,%2\;aze. %4,%3" | |
3843 | [(set_attr "type" "compare")]) | |
3844 | ||
3845 | (define_insn "" | |
3846 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") | |
3847 | (compare:CC | |
cd2b37d9 | 3848 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 3849 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 3850 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 | 3851 | (const_int 0))) |
cd2b37d9 | 3852 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3853 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
3854 | (clobber (match_scratch:SI 4 "=&r"))] | |
3855 | "" | |
3856 | "sf%I2 %4,%1,%2\;aze. %0,%3" | |
3857 | [(set_attr "type" "compare")]) | |
3858 | ||
3859 | (define_insn "" | |
cd2b37d9 RK |
3860 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3861 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3862 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
3863 | "" | |
3864 | "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0") | |
3865 | ||
3866 | (define_insn "" | |
cd2b37d9 | 3867 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 3868 | (and:SI (neg:SI |
cd2b37d9 | 3869 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 3870 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
cd2b37d9 | 3871 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
3872 | (clobber (match_scratch:SI 4 "=&r"))] |
3873 | "" | |
3874 | "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4") | |
3875 | ||
3876 | (define_insn "" | |
3877 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
3878 | (compare:CC | |
3879 | (and:SI (neg:SI | |
cd2b37d9 | 3880 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 3881 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
cd2b37d9 | 3882 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
3883 | (const_int 0))) |
3884 | (clobber (match_scratch:SI 4 "=&r"))] | |
3885 | "" | |
3886 | "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %4,%3,%4" | |
3887 | [(set_attr "type" "compare")]) | |
3888 | ||
3889 | (define_insn "" | |
3890 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") | |
3891 | (compare:CC | |
3892 | (and:SI (neg:SI | |
cd2b37d9 | 3893 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 3894 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
cd2b37d9 | 3895 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 | 3896 | (const_int 0))) |
cd2b37d9 | 3897 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3898 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
3899 | (clobber (match_scratch:SI 4 "=&r"))] | |
3900 | "" | |
3901 | "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %0,%3,%4" | |
3902 | [(set_attr "type" "compare")]) | |
3903 | ||
3904 | (define_insn "" | |
cd2b37d9 RK |
3905 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3906 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3907 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
3908 | "" | |
3909 | "doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31") | |
3910 | ||
3911 | (define_insn "" | |
3912 | [(set (match_operand:SI 3 "cc_reg_operand" "=x") | |
3913 | (compare:CC | |
cd2b37d9 | 3914 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3915 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
3916 | (const_int 0))) | |
cd2b37d9 | 3917 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3918 | (lt:SI (match_dup 1) (match_dup 2)))] |
3919 | "" | |
3920 | "doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31" | |
3921 | [(set_attr "type" "delayed_compare")]) | |
3922 | ||
3923 | (define_insn "" | |
cd2b37d9 RK |
3924 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3925 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3926 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 3927 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
3928 | (clobber (match_scratch:SI 4 "=&r"))] |
3929 | "" | |
3930 | "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3") | |
3931 | ||
3932 | (define_insn "" | |
3933 | [(set (match_operand:SI 0 "cc_reg_operand" "=x") | |
3934 | (compare:CC | |
cd2b37d9 | 3935 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 3936 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 3937 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
3938 | (const_int 0))) |
3939 | (clobber (match_scratch:SI 4 "=&r"))] | |
3940 | "" | |
3941 | "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %4,%3" | |
3942 | [(set_attr "type" "compare")]) | |
3943 | ||
3944 | (define_insn "" | |
3945 | [(set (match_operand:SI 5 "cc_reg_operand" "=x") | |
3946 | (compare:CC | |
cd2b37d9 | 3947 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 3948 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 3949 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 | 3950 | (const_int 0))) |
cd2b37d9 | 3951 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3952 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
3953 | (clobber (match_scratch:SI 4 "=&r"))] | |
3954 | "" | |
3955 | "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %0,%3" | |
3956 | [(set_attr "type" "compare")]) | |
3957 | ||
3958 | (define_insn "" | |
cd2b37d9 RK |
3959 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3960 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3961 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
3962 | "" | |
3963 | "doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31") | |
3964 | ||
3965 | (define_insn "" | |
cd2b37d9 RK |
3966 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3967 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3968 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
3969 | "" | |
3970 | "@ | |
3971 | sf %0,%2,%1\;sfe %0,%0,%0\;neg %0,%0 | |
3972 | ai %0,%1,%n2\;sfe %0,%0,%0\;neg %0,%0") | |
3973 | ||
3974 | (define_insn "" | |
3975 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") | |
3976 | (compare:CC | |
cd2b37d9 | 3977 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
3978 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
3979 | (const_int 0))) | |
cd2b37d9 | 3980 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3981 | (ltu:SI (match_dup 1) (match_dup 2)))] |
3982 | "" | |
3983 | "@ | |
3984 | sf %0,%2,%1\;sfe %0,%0,%0\;neg. %0,%0 | |
3985 | ai %0,%1,%n2\;sfe %0,%0,%0\;neg. %0,%0" | |
3986 | [(set_attr "type" "compare")]) | |
3987 | ||
3988 | (define_insn "" | |
cd2b37d9 RK |
3989 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
3990 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
1fd4e8c1 RK |
3991 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) |
3992 | (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))) | |
3993 | (clobber (match_scratch:SI 4 "=&r,r,&r,r"))] | |
3994 | "" | |
3995 | "@ | |
3996 | sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3 | |
3997 | sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3 | |
3998 | ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3 | |
3999 | ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3") | |
4000 | ||
4001 | (define_insn "" | |
4002 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") | |
4003 | (compare:CC | |
cd2b37d9 | 4004 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
1fd4e8c1 RK |
4005 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) |
4006 | (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")) | |
4007 | (const_int 0))) | |
4008 | (clobber (match_scratch:SI 4 "=&r,r,&r,r"))] | |
4009 | "" | |
4010 | "@ | |
4011 | sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3 | |
4012 | sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3 | |
4013 | ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3 | |
4014 | ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3" | |
4015 | [(set_attr "type" "compare")]) | |
4016 | ||
4017 | (define_insn "" | |
4018 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x") | |
4019 | (compare:CC | |
cd2b37d9 | 4020 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
1fd4e8c1 RK |
4021 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) |
4022 | (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")) | |
4023 | (const_int 0))) | |
cd2b37d9 | 4024 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 RK |
4025 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
4026 | (clobber (match_scratch:SI 4 "=&r,r,&r,r"))] | |
4027 | "" | |
4028 | "@ | |
4029 | sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3 | |
4030 | sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3 | |
4031 | ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3 | |
4032 | ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3" | |
4033 | [(set_attr "type" "compare")]) | |
4034 | ||
4035 | (define_insn "" | |
cd2b37d9 RK |
4036 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4037 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4038 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
4039 | "" | |
4040 | "@ | |
4041 | sf %0,%2,%1\;sfe %0,%0,%0 | |
4042 | ai %0,%1,%n2\;sfe %0,%0,%0") | |
4043 | ||
4044 | (define_insn "" | |
cd2b37d9 RK |
4045 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4046 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4047 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
4048 | (clobber (match_scratch:SI 3 "=r"))] | |
4049 | "" | |
4050 | "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae %0,%0,%3") | |
4051 | ||
4052 | (define_insn "" | |
4053 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
4054 | (compare:CC | |
cd2b37d9 | 4055 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
4056 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
4057 | (const_int 0))) | |
cd2b37d9 | 4058 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4059 | (ge:SI (match_dup 1) (match_dup 2))) |
4060 | (clobber (match_scratch:SI 3 "=r"))] | |
4061 | "" | |
4062 | "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae. %0,%0,%3" | |
4063 | [(set_attr "type" "compare")]) | |
4064 | ||
4065 | (define_insn "" | |
cd2b37d9 RK |
4066 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4067 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4068 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 4069 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
4070 | (clobber (match_scratch:SI 4 "=&r"))] |
4071 | "" | |
4072 | "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3") | |
4073 | ||
4074 | (define_insn "" | |
4075 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
4076 | (compare:CC | |
cd2b37d9 | 4077 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4078 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 4079 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
4080 | (const_int 0))) |
4081 | (clobber (match_scratch:SI 4 "=&r"))] | |
4082 | "" | |
4083 | "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3" | |
4084 | [(set_attr "type" "compare")]) | |
4085 | ||
4086 | (define_insn "" | |
4087 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") | |
4088 | (compare:CC | |
cd2b37d9 | 4089 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4090 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 4091 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 | 4092 | (const_int 0))) |
cd2b37d9 | 4093 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4094 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
4095 | (clobber (match_scratch:SI 4 "=&r"))] | |
4096 | "" | |
4097 | "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3" | |
4098 | [(set_attr "type" "compare")]) | |
4099 | ||
4100 | (define_insn "" | |
cd2b37d9 RK |
4101 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4102 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4103 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
4104 | "" | |
4105 | "doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0") | |
4106 | ||
4107 | ;; This is (and (neg (ge X (const_int 0))) Y). | |
4108 | (define_insn "" | |
cd2b37d9 | 4109 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4110 | (and:SI (neg:SI |
4111 | (lshiftrt:SI | |
cd2b37d9 | 4112 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 4113 | (const_int 31))) |
cd2b37d9 | 4114 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
4115 | (clobber (match_scratch:SI 3 "=&r"))] |
4116 | "" | |
4117 | "srai %3,%1,31\;andc %0,%2,%3") | |
4118 | ||
4119 | (define_insn "" | |
4120 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
4121 | (compare:CC | |
4122 | (and:SI (neg:SI | |
4123 | (lshiftrt:SI | |
cd2b37d9 | 4124 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 4125 | (const_int 31))) |
cd2b37d9 | 4126 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
4127 | (const_int 0))) |
4128 | (clobber (match_scratch:SI 3 "=&r"))] | |
4129 | "" | |
4130 | "srai %3,%1,31\;andc. %3,%2,%3" | |
4131 | [(set_attr "type" "compare")]) | |
4132 | ||
4133 | (define_insn "" | |
4134 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
4135 | (compare:CC | |
4136 | (and:SI (neg:SI | |
4137 | (lshiftrt:SI | |
cd2b37d9 | 4138 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 4139 | (const_int 31))) |
cd2b37d9 | 4140 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 4141 | (const_int 0))) |
cd2b37d9 | 4142 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4143 | (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) |
4144 | (const_int 31))) | |
4145 | (match_dup 2))) | |
4146 | (clobber (match_scratch:SI 3 "=&r"))] | |
4147 | "" | |
4148 | "srai %3,%1,31\;andc. %0,%2,%3" | |
4149 | [(set_attr "type" "compare")]) | |
4150 | ||
4151 | (define_insn "" | |
cd2b37d9 RK |
4152 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4153 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4154 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
4155 | "" | |
4156 | "@ | |
4157 | sf %0,%2,%1\;cal %0,0(0)\;ae %0,%0,%0 | |
4158 | ai %0,%1,%n2\;cal %0,0(0)\;ae %0,%0,%0") | |
4159 | ||
4160 | (define_insn "" | |
4161 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") | |
4162 | (compare:CC | |
cd2b37d9 | 4163 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
4164 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
4165 | (const_int 0))) | |
cd2b37d9 | 4166 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
4167 | (geu:SI (match_dup 1) (match_dup 2)))] |
4168 | "" | |
4169 | "@ | |
4170 | sf %0,%2,%1\;cal %0,0(0)\;ae. %0,%0,%0 | |
4171 | ai %0,%1,%n2\;cal %0,0(0)\;ae. %0,%0,%0" | |
4172 | [(set_attr "type" "compare")]) | |
4173 | ||
4174 | (define_insn "" | |
cd2b37d9 RK |
4175 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4176 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 4177 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
cd2b37d9 | 4178 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 RK |
4179 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
4180 | "" | |
4181 | "@ | |
4182 | sf %4,%2,%1\;aze %0,%3 | |
4183 | ai %4,%1,%n2\;aze %0,%3") | |
4184 | ||
4185 | (define_insn "" | |
4186 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") | |
4187 | (compare:CC | |
cd2b37d9 | 4188 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 4189 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
cd2b37d9 | 4190 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
1fd4e8c1 RK |
4191 | (const_int 0))) |
4192 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
4193 | "" | |
4194 | "@ | |
4195 | sf %4,%2,%1\;aze. %4,%3 | |
4196 | ai %4,%1,%n2\;aze. %4,%3" | |
4197 | [(set_attr "type" "compare")]) | |
4198 | ||
4199 | (define_insn "" | |
4200 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") | |
4201 | (compare:CC | |
cd2b37d9 | 4202 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 4203 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
cd2b37d9 | 4204 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 4205 | (const_int 0))) |
cd2b37d9 | 4206 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
4207 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
4208 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
4209 | "" | |
4210 | "@ | |
4211 | sf %4,%2,%1\;aze. %0,%3 | |
4212 | ai %4,%1,%n2\;aze. %4,%3" | |
4213 | [(set_attr "type" "compare")]) | |
4214 | ||
4215 | (define_insn "" | |
cd2b37d9 RK |
4216 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4217 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4218 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
4219 | "" | |
4220 | "@ | |
4221 | sf %0,%2,%1\;sfe %0,%0,%0\;nand %0,%0,%0 | |
4222 | sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0") | |
4223 | ||
4224 | (define_insn "" | |
cd2b37d9 | 4225 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4226 | (and:SI (neg:SI |
cd2b37d9 | 4227 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 4228 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
cd2b37d9 | 4229 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 RK |
4230 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
4231 | "" | |
4232 | "@ | |
4233 | sf %4,%2,%1\;sfe %4,%4,%4\;andc %0,%3,%4 | |
4234 | ai %4,%1,%n2\;sfe %4,%4,%4\;andc %0,%3,%4") | |
4235 | ||
4236 | (define_insn "" | |
4237 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") | |
4238 | (compare:CC | |
4239 | (and:SI (neg:SI | |
cd2b37d9 | 4240 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 4241 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
cd2b37d9 | 4242 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
1fd4e8c1 RK |
4243 | (const_int 0))) |
4244 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
4245 | "" | |
4246 | "@ | |
4247 | sf %4,%2,%1\;sfe %4,%4,%4\;andc. %4,%3,%4 | |
4248 | ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %4,%3,%4" | |
4249 | [(set_attr "type" "compare")]) | |
4250 | ||
4251 | (define_insn "" | |
4252 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") | |
4253 | (compare:CC | |
4254 | (and:SI (neg:SI | |
cd2b37d9 | 4255 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 4256 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
cd2b37d9 | 4257 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 4258 | (const_int 0))) |
cd2b37d9 | 4259 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
4260 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
4261 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
4262 | "" | |
4263 | "@ | |
4264 | sf %4,%2,%1\;sfe %4,%4,%4\;andc. %0,%3,%4 | |
4265 | ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %0,%3,%4" | |
4266 | [(set_attr "type" "compare")]) | |
4267 | ||
4268 | (define_insn "" | |
cd2b37d9 RK |
4269 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4270 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4271 | (const_int 0)))] |
4272 | "" | |
4273 | "sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31") | |
4274 | ||
4275 | (define_insn "" | |
4276 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
4277 | (compare:CC | |
cd2b37d9 | 4278 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
4279 | (const_int 0)) |
4280 | (const_int 0))) | |
cd2b37d9 | 4281 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4282 | (gt:SI (match_dup 1) (const_int 0)))] |
4283 | "" | |
4284 | "sfi %0,%1,0\;ame %0,%0\;sri. %0,%0,31" | |
4285 | [(set_attr "type" "delayed_compare")]) | |
4286 | ||
4287 | (define_insn "" | |
cd2b37d9 RK |
4288 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4289 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4290 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
4291 | "" | |
4292 | "doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31") | |
4293 | ||
4294 | (define_insn "" | |
4295 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
4296 | (compare:CC | |
cd2b37d9 | 4297 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
4298 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
4299 | (const_int 0))) | |
cd2b37d9 | 4300 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4301 | (gt:SI (match_dup 1) (match_dup 2)))] |
4302 | "" | |
4303 | "doz %0,%2,%1\;nabs %0,%0\;sri. %0,%0,31" | |
4304 | [(set_attr "type" "delayed_compare")]) | |
4305 | ||
4306 | (define_insn "" | |
cd2b37d9 RK |
4307 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4308 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4309 | (const_int 0)) |
cd2b37d9 | 4310 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
4311 | (clobber (match_scratch:SI 3 "=&r"))] |
4312 | "" | |
4313 | "a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2") | |
4314 | ||
4315 | (define_insn "" | |
4316 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
4317 | (compare:CC | |
cd2b37d9 | 4318 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4319 | (const_int 0)) |
cd2b37d9 | 4320 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
4321 | (const_int 0))) |
4322 | (clobber (match_scratch:SI 3 "=&r"))] | |
4323 | "" | |
4324 | "a %3,%1,%1\;sfe %3,%1,%3\;aze. %0,%2" | |
4325 | [(set_attr "type" "compare")]) | |
4326 | ||
4327 | (define_insn "" | |
4328 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
4329 | (compare:CC | |
cd2b37d9 | 4330 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4331 | (const_int 0)) |
cd2b37d9 | 4332 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 4333 | (const_int 0))) |
cd2b37d9 | 4334 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4335 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
4336 | (clobber (match_scratch:SI 3 "=&r"))] | |
4337 | "" | |
4338 | "a %3,%1,%1\;sfe %3,%1,%3\;aze. %3,%2" | |
4339 | [(set_attr "type" "compare")]) | |
4340 | ||
4341 | (define_insn "" | |
cd2b37d9 RK |
4342 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4343 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4344 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
cd2b37d9 | 4345 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
4346 | (clobber (match_scratch:SI 4 "=&r"))] |
4347 | "" | |
4348 | "doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3") | |
4349 | ||
4350 | (define_insn "" | |
4351 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
4352 | (compare:CC | |
cd2b37d9 | 4353 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4354 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
cd2b37d9 | 4355 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 RK |
4356 | (const_int 0))) |
4357 | (clobber (match_scratch:SI 4 "=&r"))] | |
4358 | "" | |
4359 | "doz %4,%2,%1\;ai %4,%4,-1\;aze. %4,%3" | |
4360 | [(set_attr "type" "compare")]) | |
4361 | ||
4362 | (define_insn "" | |
4363 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") | |
4364 | (compare:CC | |
cd2b37d9 | 4365 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4366 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
cd2b37d9 | 4367 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
1fd4e8c1 | 4368 | (const_int 0))) |
cd2b37d9 | 4369 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4370 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
4371 | (clobber (match_scratch:SI 4 "=&r"))] | |
4372 | "" | |
4373 | "doz %4,%2,%1\;ai %4,%4,-1\;aze. %0,%3" | |
4374 | [(set_attr "type" "compare")]) | |
4375 | ||
4376 | (define_insn "" | |
cd2b37d9 RK |
4377 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4378 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4379 | (const_int 0))))] |
4380 | "" | |
4381 | "sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31") | |
4382 | ||
4383 | (define_insn "" | |
cd2b37d9 RK |
4384 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4385 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4386 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
4387 | "" | |
4388 | "doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31") | |
4389 | ||
4390 | (define_insn "" | |
cd2b37d9 RK |
4391 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4392 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4393 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
4394 | "" | |
4395 | "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0") | |
4396 | ||
4397 | (define_insn "" | |
4398 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
4399 | (compare:CC | |
cd2b37d9 | 4400 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
4401 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
4402 | (const_int 0))) | |
cd2b37d9 | 4403 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4404 | (gtu:SI (match_dup 1) (match_dup 2)))] |
4405 | "" | |
4406 | "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg. %0,%0" | |
4407 | [(set_attr "type" "compare")]) | |
4408 | ||
4409 | (define_insn "" | |
cd2b37d9 RK |
4410 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4411 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4412 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) |
4413 | (match_operand:SI 3 "reg_or_short_operand" "r,I"))) | |
4414 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
4415 | "" | |
4416 | "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3") | |
4417 | ||
4418 | (define_insn "" | |
4419 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") | |
4420 | (compare:CC | |
cd2b37d9 | 4421 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
4422 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) |
4423 | (match_operand:SI 3 "reg_or_short_operand" "r,I")) | |
4424 | (const_int 0))) | |
4425 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
4426 | "" | |
4427 | "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3" | |
4428 | [(set_attr "type" "compare")]) | |
4429 | ||
4430 | (define_insn "" | |
4431 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") | |
4432 | (compare:CC | |
cd2b37d9 | 4433 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
4434 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) |
4435 | (match_operand:SI 3 "reg_or_short_operand" "r,I")) | |
4436 | (const_int 0))) | |
cd2b37d9 | 4437 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
4438 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
4439 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
4440 | "" | |
4441 | "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3" | |
4442 | [(set_attr "type" "compare")]) | |
4443 | ||
4444 | (define_insn "" | |
cd2b37d9 RK |
4445 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4446 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4447 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
4448 | "" | |
4449 | "sf%I2 %0,%1,%2\;sfe %0,%0,%0") | |
4450 | \f | |
4451 | ;; Define both directions of branch and return. If we need a reload | |
4452 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
4453 | ;; register CC value to there. | |
4454 | ||
4455 | (define_insn "" | |
4456 | [(set (pc) | |
4457 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
4458 | [(match_operand 2 | |
4459 | "cc_reg_operand" "x,?y") | |
4460 | (const_int 0)]) | |
4461 | (label_ref (match_operand 0 "" "")) | |
4462 | (pc)))] | |
4463 | "" | |
4464 | "%C1bc %t1,%j1,%0") | |
4465 | ||
4466 | (define_insn "" | |
4467 | [(set (pc) | |
4468 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
4469 | [(match_operand 1 | |
4470 | "cc_reg_operand" "x,?y") | |
4471 | (const_int 0)]) | |
4472 | (return) | |
4473 | (pc)))] | |
4474 | "direct_return ()" | |
4475 | "%C0bcr %t0,%j0") | |
4476 | ||
4477 | (define_insn "" | |
4478 | [(set (pc) | |
4479 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
4480 | [(match_operand 2 | |
4481 | "cc_reg_operand" "x,?y") | |
4482 | (const_int 0)]) | |
4483 | (pc) | |
4484 | (label_ref (match_operand 0 "" ""))))] | |
4485 | "" | |
4486 | "%C1bc %T1,%j1,%0") | |
4487 | ||
4488 | (define_insn "" | |
4489 | [(set (pc) | |
4490 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
4491 | [(match_operand 1 | |
4492 | "cc_reg_operand" "x,?y") | |
4493 | (const_int 0)]) | |
4494 | (pc) | |
4495 | (return)))] | |
4496 | "direct_return ()" | |
4497 | "%C0bcr %T0,%j0") | |
4498 | ||
4499 | ;; Unconditional branch and return. | |
4500 | ||
4501 | (define_insn "jump" | |
4502 | [(set (pc) | |
4503 | (label_ref (match_operand 0 "" "")))] | |
4504 | "" | |
4505 | "b %l0") | |
4506 | ||
4507 | (define_insn "return" | |
4508 | [(return)] | |
4509 | "direct_return ()" | |
4510 | "br") | |
4511 | ||
4512 | (define_insn "indirect_jump" | |
4513 | [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))] | |
4514 | "" | |
4515 | "@ | |
4516 | bctr | |
4517 | br") | |
4518 | ||
4519 | ;; Table jump for switch statements: | |
4520 | (define_expand "tablejump" | |
4521 | [(set (match_dup 3) | |
4522 | (plus:SI (match_operand:SI 0 "" "") | |
4523 | (match_dup 2))) | |
4524 | (parallel [(set (pc) (match_dup 3)) | |
4525 | (use (label_ref (match_operand 1 "" "")))])] | |
4526 | "" | |
4527 | " | |
4528 | { operands[0] = force_reg (SImode, operands[0]); | |
4529 | operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1])); | |
4530 | operands[3] = gen_reg_rtx (SImode); | |
4531 | }") | |
4532 | ||
4533 | (define_insn "" | |
4534 | [(set (pc) | |
740ab4a2 | 4535 | (match_operand:SI 0 "register_operand" "c,l")) |
1fd4e8c1 RK |
4536 | (use (label_ref (match_operand 1 "" "")))] |
4537 | "" | |
4538 | "@ | |
4539 | bctr | |
4540 | br") | |
4541 | ||
4542 | (define_insn "nop" | |
4543 | [(const_int 0)] | |
4544 | "" | |
4545 | "cror 0,0,0") | |
4546 | \f | |
4547 | ;; Define the subtract-one-and-jump insns. | |
4548 | ;; We need to be able to do this for any operand, including MEM, or we | |
4549 | ;; will cause reload to blow up since we don't allow output reloads on | |
4550 | ;; JUMP_INSNs. | |
4551 | (define_insn "" | |
4552 | [(set (pc) | |
4553 | (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r") | |
4554 | (const_int 1)) | |
4555 | (label_ref (match_operand 2 "" "")) | |
4556 | (pc))) | |
4557 | (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l") | |
4558 | (plus:SI (match_dup 1) (const_int -1))) | |
4559 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
4560 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
4561 | "" | |
4562 | "@ | |
4563 | bdn %l2 | |
4564 | # | |
4565 | #") | |
4566 | ||
4567 | ;; Similar, but we can use GE since we have a REG_NOTES. | |
4568 | (define_insn "" | |
4569 | [(set (pc) | |
4570 | (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r") | |
4571 | (const_int 0)) | |
4572 | (label_ref (match_operand 2 "" "")) | |
4573 | (pc))) | |
4574 | (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l") | |
4575 | (plus:SI (match_dup 1) (const_int -1))) | |
4576 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
4577 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
4578 | "find_reg_note (insn, REG_NONNEG, 0)" | |
4579 | "@ | |
4580 | bdn %l2 | |
4581 | # | |
4582 | #") | |
4583 | ||
4584 | (define_insn "" | |
4585 | [(set (pc) | |
4586 | (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r") | |
4587 | (const_int 1)) | |
4588 | (label_ref (match_operand 2 "" "")) | |
4589 | (pc))) | |
4590 | (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l") | |
4591 | (plus:SI (match_dup 1) (const_int -1))) | |
4592 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
4593 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
4594 | "" | |
4595 | "@ | |
4596 | bdz %l2 | |
4597 | # | |
4598 | #") | |
4599 | ||
4600 | (define_split | |
4601 | [(set (pc) | |
4602 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 4603 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
4604 | (const_int 1)]) |
4605 | (match_operand 5 "" "") | |
4606 | (match_operand 6 "" ""))) | |
cd2b37d9 | 4607 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
4608 | (plus:SI (match_dup 1) (const_int -1))) |
4609 | (clobber (match_scratch:CC 3 "")) | |
4610 | (clobber (match_scratch:SI 4 ""))] | |
4611 | "reload_completed" | |
4612 | [(parallel [(set (match_dup 3) | |
4613 | (compare:CC (plus:SI (match_dup 1) (const_int -1)) | |
4614 | (const_int 0))) | |
4615 | (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))]) | |
4616 | (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))] | |
4617 | " | |
4618 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
4619 | const0_rtx); }") | |
4620 | ||
4621 | (define_split | |
4622 | [(set (pc) | |
4623 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 4624 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
4625 | (const_int 1)]) |
4626 | (match_operand 5 "" "") | |
4627 | (match_operand 6 "" ""))) | |
4628 | (set (match_operand:SI 0 "general_operand" "") | |
4629 | (plus:SI (match_dup 1) (const_int -1))) | |
4630 | (clobber (match_scratch:CC 3 "")) | |
4631 | (clobber (match_scratch:SI 4 ""))] | |
cd2b37d9 | 4632 | "reload_completed && ! gpc_reg_operand (operands[0], SImode)" |
1fd4e8c1 RK |
4633 | [(parallel [(set (match_dup 3) |
4634 | (compare:CC (plus:SI (match_dup 1) (const_int -1)) | |
4635 | (const_int 0))) | |
4636 | (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))]) | |
4637 | (set (match_dup 0) (match_dup 4)) | |
4638 | (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))] | |
4639 | " | |
4640 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
4641 | const0_rtx); }") | |
4642 | \f | |
4643 | ;;- Local variables: | |
4644 | ;;- mode:emacs-lisp | |
4645 | ;;- comment-start: ";;- " | |
4646 | ;;- eval: (set-syntax-table (copy-sequence (syntax-table))) | |
4647 | ;;- eval: (modify-syntax-entry ?[ "(]") | |
4648 | ;;- eval: (modify-syntax-entry ?] ")[") | |
4649 | ;;- eval: (modify-syntax-entry ?{ "(}") | |
4650 | ;;- eval: (modify-syntax-entry ?} "){") | |
4651 | ;;- End: |