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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
34792e82 | 2 | ;; Copyright (C) 1990, 91-98, 1999 Free Software Foundation, Inc. |
996a5f59 | 3 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 RK |
4 | |
5 | ;; This file is part of GNU CC. | |
6 | ||
7 | ;; GNU CC is free software; you can redistribute it and/or modify | |
8 | ;; it under the terms of the GNU General Public License as published by | |
9 | ;; the Free Software Foundation; either version 2, or (at your option) | |
10 | ;; any later version. | |
11 | ||
12 | ;; GNU CC is distributed in the hope that it will be useful, | |
13 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ;; GNU General Public License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GNU CC; see the file COPYING. If not, write to | |
3f63df56 RK |
19 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | ;; Boston, MA 02111-1307, USA. | |
1fd4e8c1 RK |
21 | |
22 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
23 | \f | |
24 | ;; Define an insn type attribute. This is used in function unit delay | |
25 | ;; computations. | |
b7ff3d82 | 26 | (define_attr "type" "integer,load,store,fpload,fpstore,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg" |
1fd4e8c1 RK |
27 | (const_string "integer")) |
28 | ||
b19003d8 RK |
29 | ;; Length (in bytes). |
30 | (define_attr "length" "" | |
31 | (if_then_else (eq_attr "type" "branch") | |
32 | (if_then_else (and (ge (minus (pc) (match_dup 0)) | |
33 | (const_int -32768)) | |
34 | (lt (minus (pc) (match_dup 0)) | |
35 | (const_int 32767))) | |
36 | (const_int 8) | |
37 | (const_int 12)) | |
38 | (const_int 4))) | |
39 | ||
cfb557c4 RK |
40 | ;; Processor type -- this attribute must exactly match the processor_type |
41 | ;; enumeration in rs6000.h. | |
42 | ||
bef84347 | 43 | (define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750" |
cfb557c4 RK |
44 | (const (symbol_ref "rs6000_cpu_attr"))) |
45 | ||
46 | ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY | |
47 | ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) | |
48 | ||
b7ff3d82 | 49 | ; Load/Store Unit -- pure PowerPC only |
51b8fc2c | 50 | ; (POWER and 601 use Integer Unit) |
cfb557c4 RK |
51 | (define_function_unit "lsu" 1 0 |
52 | (and (eq_attr "type" "load") | |
bef84347 | 53 | (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b6c9286a | 54 | 2 1) |
cfb557c4 RK |
55 | |
56 | (define_function_unit "lsu" 1 0 | |
b7ff3d82 | 57 | (and (eq_attr "type" "store,fpstore") |
bef84347 | 58 | (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b7ff3d82 | 59 | 1 1) |
b6c9286a MM |
60 | |
61 | (define_function_unit "lsu" 1 0 | |
62 | (and (eq_attr "type" "fpload") | |
bef84347 | 63 | (eq_attr "cpu" "mpccore,ppc603,ppc750")) |
b6c9286a | 64 | 2 1) |
cfb557c4 | 65 | |
b7ff3d82 DE |
66 | (define_function_unit "lsu" 1 0 |
67 | (and (eq_attr "type" "fpload") | |
cac8ce95 | 68 | (eq_attr "cpu" "ppc604,ppc604e,ppc620")) |
b7ff3d82 DE |
69 | 3 1) |
70 | ||
cfb557c4 RK |
71 | (define_function_unit "iu" 1 0 |
72 | (and (eq_attr "type" "load") | |
b7ff3d82 | 73 | (eq_attr "cpu" "rios1,ppc403,ppc601")) |
b6c9286a | 74 | 2 1) |
cfb557c4 RK |
75 | |
76 | (define_function_unit "iu" 1 0 | |
b7ff3d82 DE |
77 | (and (eq_attr "type" "store,fpstore") |
78 | (eq_attr "cpu" "rios1,ppc403,ppc601")) | |
79 | 1 1) | |
80 | ||
81 | (define_function_unit "fpu" 1 0 | |
82 | (and (eq_attr "type" "fpstore") | |
3624a679 | 83 | (eq_attr "cpu" "rios1,ppc601")) |
b7ff3d82 | 84 | 0 1) |
cfb557c4 | 85 | |
49a0b204 | 86 | (define_function_unit "iu" 1 0 |
b7ff3d82 | 87 | (and (eq_attr "type" "fpload") |
b6c9286a | 88 | (eq_attr "cpu" "rios1")) |
b7ff3d82 DE |
89 | 2 1) |
90 | ||
91 | (define_function_unit "iu" 1 0 | |
92 | (and (eq_attr "type" "fpload") | |
93 | (eq_attr "cpu" "ppc601")) | |
94 | 3 1) | |
95 | ||
96 | (define_function_unit "iu2" 2 0 | |
97 | (and (eq_attr "type" "load,fpload") | |
98 | (eq_attr "cpu" "rios2")) | |
99 | 2 1) | |
100 | ||
101 | (define_function_unit "iu2" 2 0 | |
102 | (and (eq_attr "type" "store,fpstore") | |
103 | (eq_attr "cpu" "rios2")) | |
104 | 1 1) | |
105 | ||
106 | ; Integer Unit (RIOS1, PPC601, PPC603) | |
107 | (define_function_unit "iu" 1 0 | |
108 | (and (eq_attr "type" "integer") | |
109 | (eq_attr "cpu" "rios1,mpccore,ppc403,ppc601,ppc603")) | |
110 | 1 1) | |
49a0b204 | 111 | |
da0ae67f MM |
112 | (define_function_unit "iu" 1 0 |
113 | (and (eq_attr "type" "imul") | |
114 | (eq_attr "cpu" "ppc403")) | |
115 | 4 4) | |
116 | ||
cfb557c4 RK |
117 | (define_function_unit "iu" 1 0 |
118 | (and (eq_attr "type" "imul") | |
b7ff3d82 | 119 | (eq_attr "cpu" "rios1,ppc601,ppc603")) |
51b8fc2c | 120 | 5 5) |
cfb557c4 RK |
121 | |
122 | (define_function_unit "iu" 1 0 | |
123 | (and (eq_attr "type" "idiv") | |
ca7f5001 | 124 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 125 | 19 19) |
cfb557c4 RK |
126 | |
127 | (define_function_unit "iu" 1 0 | |
128 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
129 | (eq_attr "cpu" "ppc403")) |
130 | 33 33) | |
51b8fc2c | 131 | |
da0ae67f MM |
132 | (define_function_unit "iu" 1 0 |
133 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
134 | (eq_attr "cpu" "ppc601")) |
135 | 36 36) | |
da0ae67f | 136 | |
51b8fc2c RK |
137 | (define_function_unit "iu" 1 0 |
138 | (and (eq_attr "type" "idiv") | |
b7ff3d82 | 139 | (eq_attr "cpu" "ppc603")) |
51b8fc2c RK |
140 | 37 36) |
141 | ||
142 | ; RIOS2 has two integer units: a primary one which can perform all | |
143 | ; operations and a secondary one which is fed in lock step with the first | |
b6c9286a MM |
144 | ; and can perform "simple" integer operations. |
145 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
146 | ; for the complex insns. | |
51b8fc2c RK |
147 | (define_function_unit "iu2" 2 0 |
148 | (and (eq_attr "type" "integer") | |
149 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 150 | 1 1) |
b6c9286a MM |
151 | |
152 | (define_function_unit "iu2" 2 0 | |
153 | (and (eq_attr "type" "imul") | |
154 | (eq_attr "cpu" "rios2")) | |
155 | 2 2) | |
156 | ||
157 | (define_function_unit "iu2" 2 0 | |
158 | (and (eq_attr "type" "idiv") | |
159 | (eq_attr "cpu" "rios2")) | |
160 | 13 13) | |
51b8fc2c RK |
161 | |
162 | (define_function_unit "imuldiv" 1 0 | |
163 | (and (eq_attr "type" "imul") | |
164 | (eq_attr "cpu" "rios2")) | |
b6c9286a MM |
165 | 2 2) |
166 | ||
51b8fc2c RK |
167 | (define_function_unit "imuldiv" 1 0 |
168 | (and (eq_attr "type" "idiv") | |
169 | (eq_attr "cpu" "rios2")) | |
b6c9286a | 170 | 13 13) |
51b8fc2c | 171 | |
cf27b467 MM |
172 | ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions |
173 | ; Divide latency varies greatly from 2-11, use 6 as average | |
174 | (define_function_unit "imuldiv" 1 0 | |
175 | (and (eq_attr "type" "imul") | |
176 | (eq_attr "cpu" "mpccore")) | |
177 | 2 1) | |
178 | ||
179 | (define_function_unit "imuldiv" 1 0 | |
180 | (and (eq_attr "type" "idiv") | |
181 | (eq_attr "cpu" "mpccore")) | |
182 | 6 6) | |
183 | ||
cac8ce95 | 184 | ; PPC604{,e} has two units that perform integer operations |
b6c9286a MM |
185 | ; and one unit for divide/multiply operations (and move |
186 | ; from/to spr). | |
187 | (define_function_unit "iu2" 2 0 | |
51b8fc2c | 188 | (and (eq_attr "type" "integer") |
cac8ce95 | 189 | (eq_attr "cpu" "ppc604,ppc604e,ppc620")) |
b7ff3d82 | 190 | 1 1) |
51b8fc2c RK |
191 | |
192 | (define_function_unit "imuldiv" 1 0 | |
193 | (and (eq_attr "type" "imul") | |
194 | (eq_attr "cpu" "ppc604,ppc620")) | |
b7ff3d82 | 195 | 4 2) |
51b8fc2c | 196 | |
cac8ce95 DE |
197 | (define_function_unit "imuldiv" 1 0 |
198 | (and (eq_attr "type" "imul") | |
199 | (eq_attr "cpu" "ppc604e")) | |
200 | 2 1) | |
201 | ||
51b8fc2c RK |
202 | (define_function_unit "imuldiv" 1 0 |
203 | (and (eq_attr "type" "idiv") | |
cac8ce95 | 204 | (eq_attr "cpu" "ppc604,ppc604e,ppc620")) |
b7ff3d82 | 205 | 20 19) |
cfb557c4 | 206 | |
bef84347 VM |
207 | ; PPC750 has two integer units: a primary one which can perform all |
208 | ; operations and a secondary one which is fed in lock step with the first | |
209 | ; and can perform "simple" integer operations. | |
210 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
211 | ; for the complex insns. | |
212 | (define_function_unit "iu2" 2 0 | |
213 | (and (eq_attr "type" "integer") | |
214 | (eq_attr "cpu" "ppc750")) | |
215 | 1 1) | |
216 | ||
217 | (define_function_unit "iu2" 2 0 | |
218 | (and (eq_attr "type" "imul") | |
219 | (eq_attr "cpu" "ppc750")) | |
220 | 4 2) | |
221 | ||
222 | (define_function_unit "imuldiv" 1 0 | |
223 | (and (eq_attr "type" "imul") | |
224 | (eq_attr "cpu" "ppc750")) | |
225 | 4 2) | |
226 | ||
227 | (define_function_unit "imuldiv" 1 0 | |
228 | (and (eq_attr "type" "idiv") | |
229 | (eq_attr "cpu" "ppc750")) | |
230 | 19 19) | |
231 | ||
b6c9286a | 232 | ; compare is done on integer unit, but feeds insns which |
acc5239d | 233 | ; execute on the branch unit. |
b6c9286a MM |
234 | (define_function_unit "iu" 1 0 |
235 | (and (eq_attr "type" "compare") | |
b7ff3d82 DE |
236 | (eq_attr "cpu" "rios1")) |
237 | 4 1) | |
238 | ||
239 | (define_function_unit "iu" 1 0 | |
240 | (and (eq_attr "type" "delayed_compare") | |
241 | (eq_attr "cpu" "rios1")) | |
242 | 5 1) | |
243 | ||
244 | (define_function_unit "iu" 1 0 | |
245 | (and (eq_attr "type" "compare,delayed_compare") | |
bef84347 | 246 | (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b7ff3d82 | 247 | 3 1) |
b6c9286a MM |
248 | |
249 | (define_function_unit "iu2" 2 0 | |
b7ff3d82 | 250 | (and (eq_attr "type" "compare,delayed_compare") |
b6c9286a | 251 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 252 | 3 1) |
b6c9286a | 253 | |
b6c9286a | 254 | (define_function_unit "iu2" 2 0 |
b7ff3d82 | 255 | (and (eq_attr "type" "compare,delayed_compare") |
bef84347 | 256 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc750")) |
b6c9286a | 257 | 1 1) |
cfb557c4 | 258 | |
b6c9286a MM |
259 | ; fp compare uses fp unit |
260 | (define_function_unit "fpu" 1 0 | |
cfb557c4 | 261 | (and (eq_attr "type" "fpcompare") |
b6c9286a | 262 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 263 | 9 1) |
cfb557c4 | 264 | |
b6c9286a MM |
265 | ; rios1 and rios2 have different fpcompare delays |
266 | (define_function_unit "fpu2" 2 0 | |
cfb557c4 | 267 | (and (eq_attr "type" "fpcompare") |
b6c9286a MM |
268 | (eq_attr "cpu" "rios2")) |
269 | 5 1) | |
270 | ||
271 | ; on ppc601 and ppc603, fpcompare takes also 2 cycles from | |
272 | ; the integer unit | |
273 | ; here we do not define delays, just occupy the unit. The dependencies | |
b7ff3d82 | 274 | ; will be assigned by the fpcompare definition in the fpu. |
b6c9286a MM |
275 | (define_function_unit "iu" 1 0 |
276 | (and (eq_attr "type" "fpcompare") | |
b7ff3d82 | 277 | (eq_attr "cpu" "ppc601,ppc603")) |
b6c9286a MM |
278 | 0 2) |
279 | ||
280 | ; fp compare uses fp unit | |
281 | (define_function_unit "fpu" 1 0 | |
282 | (and (eq_attr "type" "fpcompare") | |
bef84347 | 283 | (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b6c9286a | 284 | 5 1) |
cfb557c4 | 285 | |
cf27b467 MM |
286 | (define_function_unit "fpu" 1 0 |
287 | (and (eq_attr "type" "fpcompare") | |
288 | (eq_attr "cpu" "mpccore")) | |
289 | 1 1) | |
290 | ||
cfb557c4 | 291 | (define_function_unit "bpu" 1 0 |
324e52cc | 292 | (and (eq_attr "type" "mtjmpr") |
2661cdd9 | 293 | (eq_attr "cpu" "rios1,rios2")) |
b7ff3d82 | 294 | 5 1) |
cfb557c4 RK |
295 | |
296 | (define_function_unit "bpu" 1 0 | |
324e52cc | 297 | (and (eq_attr "type" "mtjmpr") |
bef84347 | 298 | (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b7ff3d82 | 299 | 4 1) |
cfb557c4 | 300 | |
b6c9286a MM |
301 | ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines. |
302 | (define_function_unit "bpu" 1 0 | |
303 | (eq_attr "type" "jmpreg") | |
b7ff3d82 | 304 | 1 1) |
b6c9286a MM |
305 | |
306 | (define_function_unit "bpu" 1 0 | |
307 | (eq_attr "type" "branch") | |
b7ff3d82 | 308 | 1 1) |
b6c9286a | 309 | |
cf27b467 | 310 | ; Floating Point Unit |
cfb557c4 | 311 | (define_function_unit "fpu" 1 0 |
51b8fc2c | 312 | (and (eq_attr "type" "fp,dmul") |
2661cdd9 | 313 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 314 | 2 1) |
cfb557c4 | 315 | |
cf27b467 MM |
316 | (define_function_unit "fpu" 1 0 |
317 | (and (eq_attr "type" "fp") | |
318 | (eq_attr "cpu" "mpccore")) | |
319 | 4 4) | |
320 | ||
cfb557c4 RK |
321 | (define_function_unit "fpu" 1 0 |
322 | (and (eq_attr "type" "fp") | |
51b8fc2c | 323 | (eq_attr "cpu" "ppc601")) |
b7ff3d82 | 324 | 4 1) |
cfb557c4 | 325 | |
51b8fc2c RK |
326 | (define_function_unit "fpu" 1 0 |
327 | (and (eq_attr "type" "fp") | |
bef84347 | 328 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b6c9286a | 329 | 3 1) |
51b8fc2c | 330 | |
cf27b467 MM |
331 | (define_function_unit "fpu" 1 0 |
332 | (and (eq_attr "type" "dmul") | |
333 | (eq_attr "cpu" "mpccore")) | |
334 | 5 5) | |
335 | ||
cfb557c4 RK |
336 | (define_function_unit "fpu" 1 0 |
337 | (and (eq_attr "type" "dmul") | |
51b8fc2c | 338 | (eq_attr "cpu" "ppc601")) |
b6c9286a | 339 | 5 2) |
cfb557c4 | 340 | |
b6c9286a | 341 | ; is this true? |
cfb557c4 RK |
342 | (define_function_unit "fpu" 1 0 |
343 | (and (eq_attr "type" "dmul") | |
bef84347 | 344 | (eq_attr "cpu" "ppc603,ppc750")) |
51b8fc2c | 345 | 4 2) |
cfb557c4 RK |
346 | |
347 | (define_function_unit "fpu" 1 0 | |
51b8fc2c | 348 | (and (eq_attr "type" "dmul") |
cac8ce95 | 349 | (eq_attr "cpu" "ppc604,ppc604e,ppc620")) |
b6c9286a | 350 | 3 1) |
51b8fc2c RK |
351 | |
352 | (define_function_unit "fpu" 1 0 | |
353 | (and (eq_attr "type" "sdiv,ddiv") | |
2661cdd9 | 354 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 355 | 19 19) |
cfb557c4 RK |
356 | |
357 | (define_function_unit "fpu" 1 0 | |
358 | (and (eq_attr "type" "sdiv") | |
51b8fc2c RK |
359 | (eq_attr "cpu" "ppc601")) |
360 | 17 17) | |
361 | ||
cf27b467 MM |
362 | (define_function_unit "fpu" 1 0 |
363 | (and (eq_attr "type" "sdiv") | |
364 | (eq_attr "cpu" "mpccore")) | |
365 | 10 10) | |
366 | ||
51b8fc2c RK |
367 | (define_function_unit "fpu" 1 0 |
368 | (and (eq_attr "type" "sdiv") | |
cac8ce95 | 369 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620")) |
51b8fc2c | 370 | 18 18) |
cfb557c4 | 371 | |
cf27b467 MM |
372 | (define_function_unit "fpu" 1 0 |
373 | (and (eq_attr "type" "ddiv") | |
374 | (eq_attr "cpu" "mpccore")) | |
375 | 17 17) | |
376 | ||
cfb557c4 RK |
377 | (define_function_unit "fpu" 1 0 |
378 | (and (eq_attr "type" "ddiv") | |
bef84347 | 379 | (eq_attr "cpu" "ppc601,ppc604,ppc604e,ppc620,ppc750")) |
51b8fc2c | 380 | 31 31) |
cfb557c4 RK |
381 | |
382 | (define_function_unit "fpu" 1 0 | |
383 | (and (eq_attr "type" "ddiv") | |
b7ff3d82 | 384 | (eq_attr "cpu" "ppc603")) |
51b8fc2c | 385 | 33 33) |
cfb557c4 RK |
386 | |
387 | (define_function_unit "fpu" 1 0 | |
388 | (and (eq_attr "type" "ssqrt") | |
a473029f | 389 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 390 | 31 31) |
cfb557c4 RK |
391 | |
392 | (define_function_unit "fpu" 1 0 | |
393 | (and (eq_attr "type" "dsqrt") | |
a473029f | 394 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 395 | 31 31) |
b73d04f2 | 396 | |
51b8fc2c | 397 | ; RIOS2 has two symmetric FPUs. |
cfb557c4 RK |
398 | (define_function_unit "fpu2" 2 0 |
399 | (and (eq_attr "type" "fp") | |
4652f1d4 | 400 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 401 | 2 1) |
cfb557c4 RK |
402 | |
403 | (define_function_unit "fpu2" 2 0 | |
404 | (and (eq_attr "type" "dmul") | |
405 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 406 | 2 1) |
cfb557c4 RK |
407 | |
408 | (define_function_unit "fpu2" 2 0 | |
51b8fc2c | 409 | (and (eq_attr "type" "sdiv,ddiv") |
cfb557c4 | 410 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 411 | 17 17) |
ca7f5001 RK |
412 | |
413 | (define_function_unit "fpu2" 2 0 | |
51b8fc2c | 414 | (and (eq_attr "type" "ssqrt,dsqrt") |
ca7f5001 | 415 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 416 | 26 26) |
b6c9286a | 417 | |
1fd4e8c1 RK |
418 | \f |
419 | ;; Start with fixed-point load and store insns. Here we put only the more | |
420 | ;; complex forms. Basic data transfer is done later. | |
421 | ||
51b8fc2c RK |
422 | (define_expand "zero_extendqidi2" |
423 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
424 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
425 | "TARGET_POWERPC64" | |
426 | "") | |
427 | ||
428 | (define_insn "" | |
429 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
430 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
431 | "TARGET_POWERPC64" | |
432 | "@ | |
433 | lbz%U1%X1 %0,%1 | |
4371f8af | 434 | rldicl %0,%1,0,56" |
51b8fc2c RK |
435 | [(set_attr "type" "load,*")]) |
436 | ||
437 | (define_insn "" | |
29ae5b89 JL |
438 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
439 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
815cdc52 MM |
440 | (const_int 0))) |
441 | (clobber (match_scratch:DI 2 "=r"))] | |
29ae5b89 JL |
442 | "TARGET_POWERPC64" |
443 | "rldicl. %2,%1,0,56" | |
444 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
445 | |
446 | (define_insn "" | |
29ae5b89 JL |
447 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
448 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 449 | (const_int 0))) |
29ae5b89 | 450 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c | 451 | (zero_extend:DI (match_dup 1)))] |
58e09803 | 452 | "TARGET_POWERPC64" |
29ae5b89 JL |
453 | "rldicl. %0,%1,0,56" |
454 | [(set_attr "type" "compare")]) | |
51b8fc2c | 455 | |
2bee0449 RK |
456 | (define_insn "extendqidi2" |
457 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
458 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 459 | "TARGET_POWERPC64" |
2bee0449 | 460 | "extsb %0,%1") |
51b8fc2c RK |
461 | |
462 | (define_insn "" | |
29ae5b89 JL |
463 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
464 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 465 | (const_int 0))) |
29ae5b89 | 466 | (clobber (match_scratch:DI 2 "=r"))] |
51b8fc2c | 467 | "TARGET_POWERPC64" |
29ae5b89 JL |
468 | "extsb. %2,%1" |
469 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
470 | |
471 | (define_insn "" | |
29ae5b89 JL |
472 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
473 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 474 | (const_int 0))) |
29ae5b89 | 475 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
476 | (sign_extend:DI (match_dup 1)))] |
477 | "TARGET_POWERPC64" | |
29ae5b89 JL |
478 | "extsb. %0,%1" |
479 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
480 | |
481 | (define_expand "zero_extendhidi2" | |
482 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
483 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
484 | "TARGET_POWERPC64" | |
485 | "") | |
486 | ||
487 | (define_insn "" | |
488 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
489 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
490 | "TARGET_POWERPC64" | |
491 | "@ | |
492 | lhz%U1%X1 %0,%1 | |
4371f8af | 493 | rldicl %0,%1,0,48" |
51b8fc2c RK |
494 | [(set_attr "type" "load,*")]) |
495 | ||
496 | (define_insn "" | |
29ae5b89 JL |
497 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
498 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 499 | (const_int 0))) |
29ae5b89 | 500 | (clobber (match_scratch:DI 2 "=r"))] |
51b8fc2c | 501 | "TARGET_POWERPC64" |
29ae5b89 JL |
502 | "rldicl. %2,%1,0,48" |
503 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
504 | |
505 | (define_insn "" | |
29ae5b89 JL |
506 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
507 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 508 | (const_int 0))) |
29ae5b89 | 509 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
510 | (zero_extend:DI (match_dup 1)))] |
511 | "TARGET_POWERPC64" | |
29ae5b89 JL |
512 | "rldicl. %0,%1,0,48" |
513 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
514 | |
515 | (define_expand "extendhidi2" | |
516 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
517 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
518 | "TARGET_POWERPC64" | |
519 | "") | |
520 | ||
521 | (define_insn "" | |
522 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
523 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
524 | "TARGET_POWERPC64" | |
525 | "@ | |
526 | lha%U1%X1 %0,%1 | |
527 | extsh %0,%1" | |
528 | [(set_attr "type" "load,*")]) | |
529 | ||
530 | (define_insn "" | |
29ae5b89 JL |
531 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
532 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 533 | (const_int 0))) |
29ae5b89 | 534 | (clobber (match_scratch:DI 2 "=r"))] |
51b8fc2c | 535 | "TARGET_POWERPC64" |
29ae5b89 JL |
536 | "extsh. %2,%1" |
537 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
538 | |
539 | (define_insn "" | |
29ae5b89 JL |
540 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
541 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 542 | (const_int 0))) |
29ae5b89 | 543 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
544 | (sign_extend:DI (match_dup 1)))] |
545 | "TARGET_POWERPC64" | |
29ae5b89 JL |
546 | "extsh. %0,%1" |
547 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
548 | |
549 | (define_expand "zero_extendsidi2" | |
550 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
551 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
552 | "TARGET_POWERPC64" | |
553 | "") | |
554 | ||
555 | (define_insn "" | |
556 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
557 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
558 | "TARGET_POWERPC64" | |
559 | "@ | |
560 | lwz%U1%X1 %0,%1 | |
561 | rldicl %0,%1,0,32" | |
562 | [(set_attr "type" "load,*")]) | |
563 | ||
564 | (define_insn "" | |
29ae5b89 JL |
565 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
566 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 567 | (const_int 0))) |
29ae5b89 | 568 | (clobber (match_scratch:DI 2 "=r"))] |
51b8fc2c | 569 | "TARGET_POWERPC64" |
29ae5b89 JL |
570 | "rldicl. %2,%1,0,32" |
571 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
572 | |
573 | (define_insn "" | |
29ae5b89 JL |
574 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
575 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 576 | (const_int 0))) |
29ae5b89 | 577 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
578 | (zero_extend:DI (match_dup 1)))] |
579 | "TARGET_POWERPC64" | |
29ae5b89 JL |
580 | "rldicl. %0,%1,0,32" |
581 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
582 | |
583 | (define_expand "extendsidi2" | |
584 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
585 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
586 | "TARGET_POWERPC64" | |
587 | "") | |
588 | ||
589 | (define_insn "" | |
590 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 591 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
592 | "TARGET_POWERPC64" |
593 | "@ | |
594 | lwa%U1%X1 %0,%1 | |
595 | extsw %0,%1" | |
596 | [(set_attr "type" "load,*")]) | |
597 | ||
598 | (define_insn "" | |
29ae5b89 JL |
599 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
600 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 601 | (const_int 0))) |
29ae5b89 | 602 | (clobber (match_scratch:DI 2 "=r"))] |
51b8fc2c | 603 | "TARGET_POWERPC64" |
29ae5b89 JL |
604 | "extsw. %2,%1" |
605 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
606 | |
607 | (define_insn "" | |
29ae5b89 JL |
608 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
609 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 610 | (const_int 0))) |
29ae5b89 | 611 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
612 | (sign_extend:DI (match_dup 1)))] |
613 | "TARGET_POWERPC64" | |
29ae5b89 JL |
614 | "extsw. %0,%1" |
615 | [(set_attr "type" "compare")]) | |
51b8fc2c | 616 | |
1fd4e8c1 | 617 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
618 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
619 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
620 | "" |
621 | "") | |
622 | ||
623 | (define_insn "" | |
cd2b37d9 | 624 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
625 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
626 | "" | |
627 | "@ | |
628 | lbz%U1%X1 %0,%1 | |
005a35b9 | 629 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
630 | [(set_attr "type" "load,*")]) |
631 | ||
632 | (define_insn "" | |
29ae5b89 JL |
633 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
634 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 635 | (const_int 0))) |
29ae5b89 | 636 | (clobber (match_scratch:SI 2 "=r"))] |
1fd4e8c1 | 637 | "" |
29ae5b89 JL |
638 | "{andil.|andi.} %2,%1,0xff" |
639 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
640 | |
641 | (define_insn "" | |
29ae5b89 JL |
642 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
643 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 644 | (const_int 0))) |
29ae5b89 | 645 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
646 | (zero_extend:SI (match_dup 1)))] |
647 | "" | |
29ae5b89 JL |
648 | "{andil.|andi.} %0,%1,0xff" |
649 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 650 | |
51b8fc2c RK |
651 | (define_expand "extendqisi2" |
652 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
653 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
654 | "" | |
655 | " | |
656 | { | |
657 | if (TARGET_POWERPC) | |
658 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
659 | else if (TARGET_POWER) | |
660 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
661 | else | |
662 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
663 | DONE; | |
664 | }") | |
665 | ||
666 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
667 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
668 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 669 | "TARGET_POWERPC" |
2bee0449 | 670 | "extsb %0,%1") |
51b8fc2c RK |
671 | |
672 | (define_insn "" | |
29ae5b89 JL |
673 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
674 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 675 | (const_int 0))) |
29ae5b89 | 676 | (clobber (match_scratch:SI 2 "=r"))] |
51b8fc2c | 677 | "TARGET_POWERPC" |
29ae5b89 JL |
678 | "extsb. %2,%1" |
679 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
680 | |
681 | (define_insn "" | |
29ae5b89 JL |
682 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
683 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 684 | (const_int 0))) |
29ae5b89 | 685 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
686 | (sign_extend:SI (match_dup 1)))] |
687 | "TARGET_POWERPC" | |
29ae5b89 JL |
688 | "extsb. %0,%1" |
689 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
690 | |
691 | (define_expand "extendqisi2_power" | |
692 | [(parallel [(set (match_dup 2) | |
693 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
694 | (const_int 24))) | |
695 | (clobber (scratch:SI))]) | |
696 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
697 | (ashiftrt:SI (match_dup 2) | |
698 | (const_int 24))) | |
699 | (clobber (scratch:SI))])] | |
700 | "TARGET_POWER" | |
701 | " | |
702 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
703 | operands[2] = gen_reg_rtx (SImode); }") | |
704 | ||
705 | (define_expand "extendqisi2_no_power" | |
706 | [(set (match_dup 2) | |
707 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
708 | (const_int 24))) | |
709 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
710 | (ashiftrt:SI (match_dup 2) | |
711 | (const_int 24)))] | |
712 | "! TARGET_POWER && ! TARGET_POWERPC" | |
713 | " | |
714 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
715 | operands[2] = gen_reg_rtx (SImode); }") | |
716 | ||
1fd4e8c1 | 717 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
718 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
719 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
720 | "" |
721 | "") | |
722 | ||
723 | (define_insn "" | |
cd2b37d9 | 724 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
725 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
726 | "" | |
727 | "@ | |
728 | lbz%U1%X1 %0,%1 | |
005a35b9 | 729 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
730 | [(set_attr "type" "load,*")]) |
731 | ||
732 | (define_insn "" | |
29ae5b89 JL |
733 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
734 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 735 | (const_int 0))) |
29ae5b89 | 736 | (clobber (match_scratch:HI 2 "=r"))] |
51b8fc2c | 737 | "" |
29ae5b89 JL |
738 | "{andil.|andi.} %2,%1,0xff" |
739 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 740 | |
51b8fc2c | 741 | (define_insn "" |
29ae5b89 JL |
742 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
743 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 744 | (const_int 0))) |
29ae5b89 | 745 | (set (match_operand:HI 0 "gpc_reg_operand" "=r") |
815cdc52 MM |
746 | (zero_extend:HI (match_dup 1)))] |
747 | "" | |
29ae5b89 JL |
748 | "{andil.|andi.} %0,%1,0xff" |
749 | [(set_attr "type" "compare")]) | |
815cdc52 MM |
750 | |
751 | (define_expand "extendqihi2" | |
752 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
753 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
754 | "" | |
755 | " | |
756 | { | |
757 | if (TARGET_POWERPC) | |
758 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
759 | else if (TARGET_POWER) | |
760 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
761 | else | |
762 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
763 | DONE; | |
764 | }") | |
765 | ||
766 | (define_insn "extendqihi2_ppc" | |
767 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
768 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
769 | "TARGET_POWERPC" | |
770 | "extsb %0,%1") | |
771 | ||
772 | (define_insn "" | |
29ae5b89 JL |
773 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
774 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
815cdc52 | 775 | (const_int 0))) |
29ae5b89 | 776 | (clobber (match_scratch:HI 2 "=r"))] |
815cdc52 | 777 | "TARGET_POWERPC" |
29ae5b89 JL |
778 | "extsb. %2,%1" |
779 | [(set_attr "type" "compare")]) | |
815cdc52 MM |
780 | |
781 | (define_insn "" | |
29ae5b89 JL |
782 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
783 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 784 | (const_int 0))) |
29ae5b89 | 785 | (set (match_operand:HI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
786 | (sign_extend:HI (match_dup 1)))] |
787 | "TARGET_POWERPC" | |
29ae5b89 JL |
788 | "extsb. %0,%1" |
789 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
790 | |
791 | (define_expand "extendqihi2_power" | |
792 | [(parallel [(set (match_dup 2) | |
793 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
794 | (const_int 24))) | |
795 | (clobber (scratch:SI))]) | |
796 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
797 | (ashiftrt:SI (match_dup 2) | |
798 | (const_int 24))) | |
799 | (clobber (scratch:SI))])] | |
800 | "TARGET_POWER" | |
801 | " | |
802 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
803 | operands[1] = gen_lowpart (SImode, operands[1]); | |
804 | operands[2] = gen_reg_rtx (SImode); }") | |
805 | ||
806 | (define_expand "extendqihi2_no_power" | |
807 | [(set (match_dup 2) | |
808 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
809 | (const_int 24))) | |
810 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
811 | (ashiftrt:SI (match_dup 2) | |
812 | (const_int 24)))] | |
813 | "! TARGET_POWER && ! TARGET_POWERPC" | |
814 | " | |
815 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
816 | operands[1] = gen_lowpart (SImode, operands[1]); | |
817 | operands[2] = gen_reg_rtx (SImode); }") | |
818 | ||
1fd4e8c1 | 819 | (define_expand "zero_extendhisi2" |
5f243543 | 820 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 821 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
822 | "" |
823 | "") | |
824 | ||
825 | (define_insn "" | |
cd2b37d9 | 826 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
827 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
828 | "" | |
829 | "@ | |
830 | lhz%U1%X1 %0,%1 | |
005a35b9 | 831 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
832 | [(set_attr "type" "load,*")]) |
833 | ||
834 | (define_insn "" | |
29ae5b89 JL |
835 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
836 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 837 | (const_int 0))) |
29ae5b89 | 838 | (clobber (match_scratch:SI 2 "=r"))] |
1fd4e8c1 | 839 | "" |
29ae5b89 JL |
840 | "{andil.|andi.} %2,%1,0xffff" |
841 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
842 | |
843 | (define_insn "" | |
29ae5b89 JL |
844 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
845 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 846 | (const_int 0))) |
29ae5b89 | 847 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
848 | (zero_extend:SI (match_dup 1)))] |
849 | "" | |
29ae5b89 JL |
850 | "{andil.|andi.} %0,%1,0xffff" |
851 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
852 | |
853 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
854 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
855 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
856 | "" |
857 | "") | |
858 | ||
859 | (define_insn "" | |
cd2b37d9 | 860 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
861 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
862 | "" | |
863 | "@ | |
864 | lha%U1%X1 %0,%1 | |
ca7f5001 | 865 | {exts|extsh} %0,%1" |
1fd4e8c1 RK |
866 | [(set_attr "type" "load,*")]) |
867 | ||
868 | (define_insn "" | |
29ae5b89 JL |
869 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
870 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 871 | (const_int 0))) |
29ae5b89 | 872 | (clobber (match_scratch:SI 2 "=r"))] |
1fd4e8c1 | 873 | "" |
29ae5b89 JL |
874 | "{exts.|extsh.} %2,%1" |
875 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
876 | |
877 | (define_insn "" | |
29ae5b89 JL |
878 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
879 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 880 | (const_int 0))) |
29ae5b89 | 881 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
882 | (sign_extend:SI (match_dup 1)))] |
883 | "" | |
29ae5b89 JL |
884 | "{exts.|extsh.} %0,%1" |
885 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
886 | \f |
887 | ;; Fixed-point arithmetic insns. | |
deb9225a RK |
888 | |
889 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
890 | ;; allowing register zero as source. | |
7cd5235b MM |
891 | (define_expand "addsi3" |
892 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
893 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
894 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
895 | "" | |
896 | " | |
897 | { | |
898 | if (GET_CODE (operands[2]) == CONST_INT && !add_operand (operands[2], SImode)) | |
899 | { | |
900 | rtx tmp = ((reload_in_progress || reload_completed | |
901 | || rtx_equal_p (operands[0], operands[1])) | |
902 | ? operands[0] : gen_reg_rtx (SImode)); | |
903 | ||
904 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; | |
905 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
906 | ||
907 | if (low & 0x8000) | |
908 | high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16; | |
909 | ||
910 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (high))); | |
911 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); | |
912 | DONE; | |
913 | } | |
914 | }") | |
915 | ||
916 | (define_insn "*addsi3_internal1" | |
917 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
918 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
919 | (match_operand:SI 2 "add_operand" "r,I,I,J")))] | |
1fd4e8c1 RK |
920 | "" |
921 | "@ | |
deb9225a RK |
922 | {cax|add} %0,%1,%2 |
923 | {cal %0,%2(%1)|addi %0,%1,%2} | |
924 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
925 | {cau|addis} %0,%1,%v2" |
926 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 927 | |
7cd5235b | 928 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
929 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
930 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
931 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 932 | (const_int 0))) |
cb8cc086 | 933 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
1fd4e8c1 | 934 | "" |
deb9225a RK |
935 | "@ |
936 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
937 | {ai.|addic.} %3,%1,%2 |
938 | # | |
939 | #" | |
940 | [(set_attr "type" "compare") | |
941 | (set_attr "length" "4,4,8,8")]) | |
942 | ||
943 | (define_split | |
944 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
945 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
946 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
947 | (const_int 0))) | |
948 | (clobber (match_scratch:SI 3 ""))] | |
949 | "reload_completed" | |
950 | [(set (match_dup 3) | |
951 | (plus:SI (match_dup 1) | |
952 | (match_dup 2))) | |
953 | (set (match_dup 0) | |
954 | (compare:CC (match_dup 3) | |
955 | (const_int 0)))] | |
956 | "") | |
7e69e155 | 957 | |
7cd5235b | 958 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
959 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
960 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
961 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 962 | (const_int 0))) |
cb8cc086 MM |
963 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
964 | (plus:SI (match_dup 1) | |
965 | (match_dup 2)))] | |
1fd4e8c1 | 966 | "" |
deb9225a RK |
967 | "@ |
968 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
969 | {ai.|addic.} %0,%1,%2 |
970 | # | |
971 | #" | |
972 | [(set_attr "type" "compare") | |
973 | (set_attr "length" "4,4,8,8")]) | |
974 | ||
975 | (define_split | |
976 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
977 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
978 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
979 | (const_int 0))) | |
980 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
981 | (plus:SI (match_dup 1) (match_dup 2)))] | |
982 | "reload_completed" | |
983 | [(set (match_dup 0) | |
984 | (plus:SI (match_dup 1) | |
985 | (match_dup 2))) | |
986 | (set (match_dup 3) | |
987 | (compare:CC (match_dup 0) | |
988 | (const_int 0)))] | |
989 | "") | |
7e69e155 | 990 | |
f357808b RK |
991 | ;; Split an add that we can't do in one insn into two insns, each of which |
992 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
993 | ;; add should be last in case the result gets used in an address. | |
994 | ||
995 | (define_split | |
cd2b37d9 RK |
996 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
997 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 998 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 999 | "" |
f357808b RK |
1000 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1001 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1002 | " | |
1fd4e8c1 | 1003 | { |
e6ca2c17 DE |
1004 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; |
1005 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
1fd4e8c1 | 1006 | |
f357808b | 1007 | if (low & 0x8000) |
e6ca2c17 | 1008 | high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16; |
1fd4e8c1 | 1009 | |
e6ca2c17 DE |
1010 | operands[3] = GEN_INT (high); |
1011 | operands[4] = GEN_INT (low); | |
1fd4e8c1 RK |
1012 | }") |
1013 | ||
8de2a197 | 1014 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1015 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1016 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1017 | "" |
ca7f5001 RK |
1018 | "nor %0,%1,%1") |
1019 | ||
1020 | (define_insn "" | |
29ae5b89 JL |
1021 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1022 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
ca7f5001 | 1023 | (const_int 0))) |
29ae5b89 | 1024 | (clobber (match_scratch:SI 2 "=r"))] |
ca7f5001 | 1025 | "" |
29ae5b89 JL |
1026 | "nor. %2,%1,%1" |
1027 | [(set_attr "type" "compare")]) | |
ca7f5001 RK |
1028 | |
1029 | (define_insn "" | |
29ae5b89 JL |
1030 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
1031 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
815cdc52 MM |
1032 | (const_int 0))) |
1033 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1034 | (not:SI (match_dup 1)))] | |
29ae5b89 JL |
1035 | "" |
1036 | "nor. %0,%1,%1" | |
1037 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
1038 | |
1039 | (define_insn "" | |
3d91674b RK |
1040 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1041 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1042 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1043 | "! TARGET_POWERPC" |
ca7f5001 | 1044 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1045 | |
deb9225a RK |
1046 | (define_insn "" |
1047 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1048 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1049 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1050 | "TARGET_POWERPC" | |
1051 | "@ | |
1052 | subf %0,%2,%1 | |
1053 | subfic %0,%2,%1") | |
1054 | ||
1fd4e8c1 | 1055 | (define_insn "" |
cb8cc086 MM |
1056 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1057 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1058 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1059 | (const_int 0))) |
cb8cc086 | 1060 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1061 | "! TARGET_POWERPC" |
cb8cc086 MM |
1062 | "@ |
1063 | {sf.|subfc.} %3,%2,%1 | |
1064 | #" | |
1065 | [(set_attr "type" "compare") | |
1066 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1067 | |
deb9225a | 1068 | (define_insn "" |
cb8cc086 MM |
1069 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1070 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1071 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1072 | (const_int 0))) |
cb8cc086 | 1073 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1074 | "TARGET_POWERPC" |
cb8cc086 MM |
1075 | "@ |
1076 | subf. %3,%2,%1 | |
1077 | #" | |
1078 | [(set_attr "type" "compare") | |
1079 | (set_attr "length" "4,8")]) | |
1080 | ||
1081 | (define_split | |
1082 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1083 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1084 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1085 | (const_int 0))) | |
1086 | (clobber (match_scratch:SI 3 ""))] | |
1087 | "reload_completed" | |
1088 | [(set (match_dup 3) | |
1089 | (minus:SI (match_dup 1) | |
1090 | (match_dup 2))) | |
1091 | (set (match_dup 0) | |
1092 | (compare:CC (match_dup 3) | |
1093 | (const_int 0)))] | |
1094 | "") | |
deb9225a | 1095 | |
1fd4e8c1 | 1096 | (define_insn "" |
cb8cc086 MM |
1097 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1098 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1099 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1100 | (const_int 0))) |
cb8cc086 | 1101 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1102 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1103 | "! TARGET_POWERPC" |
cb8cc086 MM |
1104 | "@ |
1105 | {sf.|subfc.} %0,%2,%1 | |
1106 | #" | |
1107 | [(set_attr "type" "compare") | |
1108 | (set_attr "length" "4,8")]) | |
815cdc52 | 1109 | |
29ae5b89 | 1110 | (define_insn "" |
cb8cc086 MM |
1111 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1112 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1113 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1114 | (const_int 0))) |
cb8cc086 MM |
1115 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1116 | (minus:SI (match_dup 1) | |
1117 | (match_dup 2)))] | |
29ae5b89 | 1118 | "TARGET_POWERPC" |
90612787 DE |
1119 | "@ |
1120 | subf. %0,%2,%1 | |
1121 | #" | |
cb8cc086 MM |
1122 | [(set_attr "type" "compare") |
1123 | (set_attr "length" "4,8")]) | |
1124 | ||
1125 | (define_split | |
1126 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1127 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1128 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1129 | (const_int 0))) | |
1130 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1131 | (minus:SI (match_dup 1) | |
1132 | (match_dup 2)))] | |
1133 | "reload_completed" | |
1134 | [(set (match_dup 0) | |
1135 | (minus:SI (match_dup 1) | |
1136 | (match_dup 2))) | |
1137 | (set (match_dup 3) | |
1138 | (compare:CC (match_dup 0) | |
1139 | (const_int 0)))] | |
1140 | "") | |
deb9225a | 1141 | |
1fd4e8c1 | 1142 | (define_expand "subsi3" |
cd2b37d9 | 1143 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1144 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
1145 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
1146 | "" | |
a0044fb1 RK |
1147 | " |
1148 | { | |
1149 | if (GET_CODE (operands[2]) == CONST_INT) | |
1150 | { | |
1151 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1152 | negate_rtx (SImode, operands[2]))); | |
1153 | DONE; | |
1154 | } | |
1155 | }") | |
1fd4e8c1 RK |
1156 | |
1157 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1158 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1159 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1160 | ;; combine. | |
1fd4e8c1 RK |
1161 | |
1162 | (define_expand "sminsi3" | |
1163 | [(set (match_dup 3) | |
cd2b37d9 | 1164 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1165 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1166 | (const_int 0) | |
1167 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1168 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1169 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1170 | "TARGET_POWER" |
1fd4e8c1 RK |
1171 | " |
1172 | { operands[3] = gen_reg_rtx (SImode); }") | |
1173 | ||
95ac8e67 RK |
1174 | (define_split |
1175 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1176 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1177 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1178 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1179 | "TARGET_POWER" |
95ac8e67 RK |
1180 | [(set (match_dup 3) |
1181 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1182 | (const_int 0) | |
1183 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1184 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1185 | "") | |
1186 | ||
1fd4e8c1 RK |
1187 | (define_expand "smaxsi3" |
1188 | [(set (match_dup 3) | |
cd2b37d9 | 1189 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1190 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1191 | (const_int 0) | |
1192 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1193 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1194 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1195 | "TARGET_POWER" |
1fd4e8c1 RK |
1196 | " |
1197 | { operands[3] = gen_reg_rtx (SImode); }") | |
1198 | ||
95ac8e67 RK |
1199 | (define_split |
1200 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1201 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1202 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1203 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1204 | "TARGET_POWER" |
95ac8e67 RK |
1205 | [(set (match_dup 3) |
1206 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1207 | (const_int 0) | |
1208 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1209 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1210 | "") | |
1211 | ||
1fd4e8c1 | 1212 | (define_expand "uminsi3" |
cd2b37d9 | 1213 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1214 | (match_dup 5))) |
cd2b37d9 | 1215 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1216 | (match_dup 5))) |
1fd4e8c1 RK |
1217 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1218 | (const_int 0) | |
1219 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1220 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1221 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1222 | "TARGET_POWER" |
1fd4e8c1 | 1223 | " |
bb68ff55 MM |
1224 | { |
1225 | operands[3] = gen_reg_rtx (SImode); | |
1226 | operands[4] = gen_reg_rtx (SImode); | |
1227 | operands[5] = GEN_INT (-2147483647 - 1); | |
1228 | }") | |
1fd4e8c1 RK |
1229 | |
1230 | (define_expand "umaxsi3" | |
cd2b37d9 | 1231 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1232 | (match_dup 5))) |
cd2b37d9 | 1233 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1234 | (match_dup 5))) |
1fd4e8c1 RK |
1235 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1236 | (const_int 0) | |
1237 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1238 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1239 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1240 | "TARGET_POWER" |
1fd4e8c1 | 1241 | " |
bb68ff55 MM |
1242 | { |
1243 | operands[3] = gen_reg_rtx (SImode); | |
1244 | operands[4] = gen_reg_rtx (SImode); | |
1245 | operands[5] = GEN_INT (-2147483647 - 1); | |
1246 | }") | |
1fd4e8c1 RK |
1247 | |
1248 | (define_insn "" | |
cd2b37d9 RK |
1249 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1250 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1251 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1252 | (const_int 0) |
1253 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1254 | "TARGET_POWER" |
1fd4e8c1 RK |
1255 | "doz%I2 %0,%1,%2") |
1256 | ||
1257 | (define_insn "" | |
29ae5b89 | 1258 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 1259 | (compare:CC |
29ae5b89 JL |
1260 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") |
1261 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 RK |
1262 | (const_int 0) |
1263 | (minus:SI (match_dup 2) (match_dup 1))) | |
1264 | (const_int 0))) | |
29ae5b89 | 1265 | (clobber (match_scratch:SI 3 "=r"))] |
ca7f5001 | 1266 | "TARGET_POWER" |
29ae5b89 JL |
1267 | "doz%I2. %3,%1,%2" |
1268 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
1269 | |
1270 | (define_insn "" | |
29ae5b89 | 1271 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 | 1272 | (compare:CC |
29ae5b89 JL |
1273 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") |
1274 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 RK |
1275 | (const_int 0) |
1276 | (minus:SI (match_dup 2) (match_dup 1))) | |
1277 | (const_int 0))) | |
29ae5b89 | 1278 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1279 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1280 | (const_int 0) | |
1281 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1282 | "TARGET_POWER" |
29ae5b89 | 1283 | "doz%I2. %0,%1,%2" |
1fd4e8c1 RK |
1284 | [(set_attr "type" "delayed_compare")]) |
1285 | ||
1286 | ;; We don't need abs with condition code because such comparisons should | |
1287 | ;; never be done. | |
ea9be077 MM |
1288 | (define_expand "abssi2" |
1289 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1290 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1291 | "" | |
1292 | " | |
1293 | { | |
1294 | if (!TARGET_POWER) | |
1295 | { | |
1296 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1297 | DONE; | |
1298 | } | |
1299 | }") | |
1300 | ||
1301 | (define_insn "abssi2_power" | |
cd2b37d9 RK |
1302 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1303 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1304 | "TARGET_POWER" |
1fd4e8c1 RK |
1305 | "abs %0,%1") |
1306 | ||
ea9be077 MM |
1307 | (define_insn "abssi2_nopower" |
1308 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1309 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
1310 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
1311 | "!TARGET_POWER" | |
3595d104 MM |
1312 | "* |
1313 | { | |
1314 | return (TARGET_POWERPC) | |
1315 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\" | |
1316 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\"; | |
1317 | }" | |
ea9be077 MM |
1318 | [(set_attr "length" "12")]) |
1319 | ||
1320 | (define_split | |
1321 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1322 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
1323 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
1324 | "!TARGET_POWER && reload_completed" | |
1325 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) | |
1326 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1327 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1328 | "") |
1329 | ||
463b558b | 1330 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1331 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1332 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1333 | "TARGET_POWER" |
1fd4e8c1 RK |
1334 | "nabs %0,%1") |
1335 | ||
463b558b | 1336 | (define_insn "*nabs_no_power" |
ea9be077 MM |
1337 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
1338 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
1339 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
1340 | "!TARGET_POWER" | |
3595d104 MM |
1341 | "* |
1342 | { | |
1343 | return (TARGET_POWERPC) | |
1344 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\" | |
1345 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\"; | |
1346 | }" | |
ea9be077 MM |
1347 | [(set_attr "length" "12")]) |
1348 | ||
1349 | (define_split | |
1350 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1351 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
1352 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
1353 | "!TARGET_POWER && reload_completed" | |
1354 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) | |
1355 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1356 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1357 | "") |
1358 | ||
1fd4e8c1 | 1359 | (define_insn "negsi2" |
cd2b37d9 RK |
1360 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1361 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1362 | "" |
1363 | "neg %0,%1") | |
1364 | ||
1365 | (define_insn "" | |
29ae5b89 JL |
1366 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1367 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 1368 | (const_int 0))) |
29ae5b89 | 1369 | (clobber (match_scratch:SI 2 "=r"))] |
1fd4e8c1 | 1370 | "" |
29ae5b89 JL |
1371 | "neg. %2,%1" |
1372 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
1373 | |
1374 | (define_insn "" | |
29ae5b89 JL |
1375 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
1376 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
815cdc52 MM |
1377 | (const_int 0))) |
1378 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1379 | (neg:SI (match_dup 1)))] | |
29ae5b89 JL |
1380 | "" |
1381 | "neg. %0,%1" | |
1382 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
1383 | |
1384 | (define_insn "ffssi2" | |
242e8072 RK |
1385 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
1386 | (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1387 | "" |
7f340546 | 1388 | "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" |
b19003d8 | 1389 | [(set_attr "length" "16")]) |
1fd4e8c1 | 1390 | |
ca7f5001 RK |
1391 | (define_expand "mulsi3" |
1392 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1393 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
1394 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
1395 | "" | |
1396 | " | |
1397 | { | |
1398 | if (TARGET_POWER) | |
68b40e7e | 1399 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 1400 | else |
68b40e7e | 1401 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
1402 | DONE; |
1403 | }") | |
1404 | ||
68b40e7e | 1405 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
1406 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1407 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
1408 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
1409 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
1410 | "TARGET_POWER" |
1411 | "@ | |
1412 | {muls|mullw} %0,%1,%2 | |
1413 | {muli|mulli} %0,%1,%2" | |
1414 | [(set_attr "type" "imul")]) | |
1415 | ||
68b40e7e | 1416 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
1417 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1418 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1419 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 1420 | "! TARGET_POWER" |
1fd4e8c1 | 1421 | "@ |
d904e9ed RK |
1422 | {muls|mullw} %0,%1,%2 |
1423 | {muli|mulli} %0,%1,%2" | |
cfb557c4 | 1424 | [(set_attr "type" "imul")]) |
1fd4e8c1 RK |
1425 | |
1426 | (define_insn "" | |
29ae5b89 JL |
1427 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1428 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1429 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 1430 | (const_int 0))) |
29ae5b89 JL |
1431 | (clobber (match_scratch:SI 3 "=r")) |
1432 | (clobber (match_scratch:SI 4 "=q"))] | |
ca7f5001 | 1433 | "TARGET_POWER" |
29ae5b89 JL |
1434 | "{muls.|mullw.} %3,%1,%2" |
1435 | [(set_attr "type" "delayed_compare")]) | |
ca7f5001 RK |
1436 | |
1437 | (define_insn "" | |
29ae5b89 JL |
1438 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1439 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1440 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
ca7f5001 | 1441 | (const_int 0))) |
29ae5b89 | 1442 | (clobber (match_scratch:SI 3 "=r"))] |
25c341fa | 1443 | "! TARGET_POWER" |
29ae5b89 JL |
1444 | "{muls.|mullw.} %3,%1,%2" |
1445 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
1446 | |
1447 | (define_insn "" | |
29ae5b89 JL |
1448 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1449 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1450 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 1451 | (const_int 0))) |
29ae5b89 JL |
1452 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1453 | (mult:SI (match_dup 1) (match_dup 2))) | |
1454 | (clobber (match_scratch:SI 4 "=q"))] | |
ca7f5001 | 1455 | "TARGET_POWER" |
29ae5b89 JL |
1456 | "{muls.|mullw.} %0,%1,%2" |
1457 | [(set_attr "type" "delayed_compare")]) | |
ca7f5001 RK |
1458 | |
1459 | (define_insn "" | |
29ae5b89 JL |
1460 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1461 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1462 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
ca7f5001 | 1463 | (const_int 0))) |
29ae5b89 | 1464 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ca7f5001 | 1465 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 1466 | "! TARGET_POWER" |
29ae5b89 JL |
1467 | "{muls.|mullw.} %0,%1,%2" |
1468 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
1469 | |
1470 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
1471 | ;; 0 and remainder to operand 3. | |
1472 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
1473 | ||
8ffd9c51 RK |
1474 | (define_expand "divmodsi4" |
1475 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1476 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1477 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
1478 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
1479 | (mod:SI (match_dup 1) (match_dup 2)))])] | |
1480 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1481 | " | |
1482 | { | |
1483 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1484 | { | |
39403d82 DE |
1485 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1486 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1487 | emit_insn (gen_divss_call ()); |
39403d82 DE |
1488 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1489 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
1490 | DONE; |
1491 | } | |
1492 | }") | |
deb9225a | 1493 | |
fada905b | 1494 | (define_insn "" |
cd2b37d9 RK |
1495 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1496 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1497 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1498 | (set (match_operand:SI 3 "gpc_reg_operand" "=q") | |
1fd4e8c1 | 1499 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 1500 | "TARGET_POWER" |
cfb557c4 RK |
1501 | "divs %0,%1,%2" |
1502 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 1503 | |
8ffd9c51 RK |
1504 | (define_expand "udivsi3" |
1505 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1506 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1507 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
1508 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1509 | " | |
1510 | { | |
1511 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1512 | { | |
39403d82 DE |
1513 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1514 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1515 | emit_insn (gen_quous_call ()); |
39403d82 | 1516 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1517 | DONE; |
1518 | } | |
f192bf8b DE |
1519 | else if (TARGET_POWER) |
1520 | { | |
1521 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
1522 | DONE; | |
1523 | } | |
8ffd9c51 | 1524 | }") |
deb9225a | 1525 | |
f192bf8b DE |
1526 | (define_insn "udivsi3_mq" |
1527 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1528 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1529 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1530 | (clobber (match_scratch:SI 3 "=q"))] | |
1531 | "TARGET_POWERPC && TARGET_POWER" | |
1532 | "divwu %0,%1,%2" | |
1533 | [(set_attr "type" "idiv")]) | |
1534 | ||
1535 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
1536 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1537 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1538 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 1539 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 1540 | "divwu %0,%1,%2" |
ca7f5001 RK |
1541 | [(set_attr "type" "idiv")]) |
1542 | ||
1fd4e8c1 | 1543 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 1544 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
1545 | ;; used; for PowerPC, force operands into register and do a normal divide; |
1546 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 1547 | (define_expand "divsi3" |
cd2b37d9 RK |
1548 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1549 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
1550 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
1551 | "" | |
1552 | " | |
1553 | { | |
ca7f5001 RK |
1554 | if (GET_CODE (operands[2]) == CONST_INT |
1555 | && exact_log2 (INTVAL (operands[2])) >= 0) | |
1556 | ; | |
b6c9286a | 1557 | else if (TARGET_POWERPC) |
f192bf8b DE |
1558 | { |
1559 | operands[2] = force_reg (SImode, operands[2]); | |
1560 | if (TARGET_POWER) | |
1561 | { | |
1562 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
1563 | DONE; | |
1564 | } | |
1565 | } | |
b6c9286a | 1566 | else if (TARGET_POWER) |
1fd4e8c1 | 1567 | FAIL; |
405c5495 | 1568 | else |
8ffd9c51 | 1569 | { |
39403d82 DE |
1570 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1571 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1572 | emit_insn (gen_quoss_call ()); |
39403d82 | 1573 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1574 | DONE; |
1575 | } | |
1fd4e8c1 RK |
1576 | }") |
1577 | ||
f192bf8b DE |
1578 | (define_insn "divsi3_mq" |
1579 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1580 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1581 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1582 | (clobber (match_scratch:SI 3 "=q"))] | |
1583 | "TARGET_POWERPC && TARGET_POWER" | |
1584 | "divw %0,%1,%2" | |
1585 | [(set_attr "type" "idiv")]) | |
1586 | ||
1587 | (define_insn "*divsi3_no_mq" | |
1588 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1589 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1590 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1591 | "TARGET_POWERPC && ! TARGET_POWER" | |
1592 | "divw %0,%1,%2" | |
1593 | [(set_attr "type" "idiv")]) | |
1594 | ||
1fd4e8c1 | 1595 | (define_expand "modsi3" |
85644414 RK |
1596 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
1597 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 1598 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 1599 | "" |
1fd4e8c1 RK |
1600 | " |
1601 | { | |
39b52ba2 RK |
1602 | int i = exact_log2 (INTVAL (operands[2])); |
1603 | rtx temp1; | |
1604 | rtx temp2; | |
1605 | ||
405c5495 | 1606 | if (GET_CODE (operands[2]) != CONST_INT || i < 0) |
39b52ba2 RK |
1607 | FAIL; |
1608 | ||
1609 | temp1 = gen_reg_rtx (SImode); | |
1610 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 1611 | |
85644414 | 1612 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 1613 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
1614 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
1615 | DONE; | |
1fd4e8c1 RK |
1616 | }") |
1617 | ||
1618 | (define_insn "" | |
cd2b37d9 RK |
1619 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1620 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
1621 | (match_operand:SI 2 "const_int_operand" "N")))] |
1622 | "exact_log2 (INTVAL (operands[2])) >= 0" | |
ca7f5001 | 1623 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 1624 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
1625 | |
1626 | (define_insn "" | |
29ae5b89 JL |
1627 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1628 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1629 | (match_operand:SI 2 "const_int_operand" "N")) | |
b6b12107 | 1630 | (const_int 0))) |
29ae5b89 | 1631 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 1632 | "exact_log2 (INTVAL (operands[2])) >= 0" |
29ae5b89 | 1633 | "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3" |
b19003d8 | 1634 | [(set_attr "type" "compare") |
29ae5b89 | 1635 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
1636 | |
1637 | (define_insn "" | |
29ae5b89 JL |
1638 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1639 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1640 | (match_operand:SI 2 "const_int_operand" "N")) | |
b6b12107 | 1641 | (const_int 0))) |
29ae5b89 JL |
1642 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1643 | (div:SI (match_dup 1) (match_dup 2)))] | |
1fd4e8c1 | 1644 | "exact_log2 (INTVAL (operands[2])) >= 0" |
29ae5b89 | 1645 | "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0" |
b19003d8 | 1646 | [(set_attr "type" "compare") |
29ae5b89 | 1647 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
1648 | |
1649 | (define_insn "" | |
cd2b37d9 | 1650 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 1651 | (udiv:SI |
996a5f59 | 1652 | (plus:DI (ashift:DI |
cd2b37d9 | 1653 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 1654 | (const_int 32)) |
23a900dc | 1655 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 1656 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 1657 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 1658 | (umod:SI |
996a5f59 | 1659 | (plus:DI (ashift:DI |
1fd4e8c1 | 1660 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 1661 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 1662 | (match_dup 3)))] |
ca7f5001 | 1663 | "TARGET_POWER" |
cfb557c4 RK |
1664 | "div %0,%1,%3" |
1665 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
1666 | |
1667 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
1668 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
1669 | ;; have to worry about the branches. So make a few subroutines here. | |
1670 | ;; | |
1671 | ;; First comes the normal case. | |
1672 | (define_expand "udivmodsi4_normal" | |
1673 | [(set (match_dup 4) (const_int 0)) | |
1674 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 1675 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
1676 | (const_int 32)) |
1677 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
1678 | (match_operand:SI 2 "" ""))) | |
1679 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 1680 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
1681 | (const_int 32)) |
1682 | (zero_extend:DI (match_dup 1))) | |
1683 | (match_dup 2)))])] | |
ca7f5001 | 1684 | "TARGET_POWER" |
1fd4e8c1 RK |
1685 | " |
1686 | { operands[4] = gen_reg_rtx (SImode); }") | |
1687 | ||
1688 | ;; This handles the branches. | |
1689 | (define_expand "udivmodsi4_tests" | |
1690 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
1691 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
1692 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
1693 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
1694 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
1695 | (set (match_dup 0) (const_int 1)) | |
1696 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
1697 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
1698 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
1699 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 1700 | "TARGET_POWER" |
1fd4e8c1 RK |
1701 | " |
1702 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
1703 | operands[6] = gen_reg_rtx (CCmode); | |
1704 | }") | |
1705 | ||
1706 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
1707 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1708 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 1709 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 1710 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 1711 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 1712 | "" |
1fd4e8c1 RK |
1713 | " |
1714 | { | |
1715 | rtx label = 0; | |
1716 | ||
8ffd9c51 | 1717 | if (! TARGET_POWER) |
c4d38ccb MM |
1718 | { |
1719 | if (! TARGET_POWERPC) | |
1720 | { | |
39403d82 DE |
1721 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1722 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 1723 | emit_insn (gen_divus_call ()); |
39403d82 DE |
1724 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1725 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
1726 | DONE; |
1727 | } | |
1728 | else | |
1729 | FAIL; | |
1730 | } | |
0081a354 | 1731 | |
1fd4e8c1 RK |
1732 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
1733 | { | |
1734 | operands[2] = force_reg (SImode, operands[2]); | |
1735 | label = gen_label_rtx (); | |
1736 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
1737 | operands[3], label)); | |
1738 | } | |
1739 | else | |
1740 | operands[2] = force_reg (SImode, operands[2]); | |
1741 | ||
1742 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
1743 | operands[3])); | |
1744 | if (label) | |
1745 | emit_label (label); | |
1746 | ||
1747 | DONE; | |
1748 | }") | |
0081a354 | 1749 | |
fada905b MM |
1750 | ;; AIX architecture-independent common-mode multiply (DImode), |
1751 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
1752 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
1753 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
1754 | ;; assumed unused if generating common-mode, so ignore. | |
1755 | (define_insn "mulh_call" | |
1756 | [(set (reg:SI 3) | |
1757 | (truncate:SI | |
1758 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
1759 | (sign_extend:DI (reg:SI 4))) | |
1760 | (const_int 32)))) | |
cf27b467 | 1761 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 1762 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
1763 | "bla __mulh" |
1764 | [(set_attr "type" "imul")]) | |
fada905b MM |
1765 | |
1766 | (define_insn "mull_call" | |
1767 | [(set (reg:DI 3) | |
1768 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
1769 | (sign_extend:DI (reg:SI 4)))) | |
1770 | (clobber (match_scratch:SI 0 "=l")) | |
1771 | (clobber (reg:SI 0))] | |
1772 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
1773 | "bla __mull" |
1774 | [(set_attr "type" "imul")]) | |
fada905b MM |
1775 | |
1776 | (define_insn "divss_call" | |
1777 | [(set (reg:SI 3) | |
1778 | (div:SI (reg:SI 3) (reg:SI 4))) | |
1779 | (set (reg:SI 4) | |
1780 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
1781 | (clobber (match_scratch:SI 0 "=l")) | |
1782 | (clobber (reg:SI 0))] | |
1783 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
1784 | "bla __divss" |
1785 | [(set_attr "type" "idiv")]) | |
fada905b MM |
1786 | |
1787 | (define_insn "divus_call" | |
8ffd9c51 RK |
1788 | [(set (reg:SI 3) |
1789 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
1790 | (set (reg:SI 4) | |
1791 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
1792 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
1793 | (clobber (reg:SI 0)) |
1794 | (clobber (match_scratch:CC 1 "=x")) | |
1795 | (clobber (reg:CC 69))] | |
1796 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
1797 | "bla __divus" |
1798 | [(set_attr "type" "idiv")]) | |
fada905b MM |
1799 | |
1800 | (define_insn "quoss_call" | |
1801 | [(set (reg:SI 3) | |
1802 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 1803 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 1804 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
1805 | "bla __quoss" |
1806 | [(set_attr "type" "idiv")]) | |
0081a354 | 1807 | |
fada905b MM |
1808 | (define_insn "quous_call" |
1809 | [(set (reg:SI 3) | |
1810 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
1811 | (clobber (match_scratch:SI 0 "=l")) | |
1812 | (clobber (reg:SI 0)) | |
1813 | (clobber (match_scratch:CC 1 "=x")) | |
1814 | (clobber (reg:CC 69))] | |
1815 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
1816 | "bla __quous" |
1817 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 1818 | \f |
bb21487f | 1819 | ;; Logical instructions |
29ae5b89 JL |
1820 | (define_insn "andsi3" |
1821 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
1822 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1823 | (match_operand:SI 2 "and_operand" "?r,L,K,J"))) | |
1824 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] | |
1fd4e8c1 RK |
1825 | "" |
1826 | "@ | |
1827 | and %0,%1,%2 | |
ca7f5001 RK |
1828 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
1829 | {andil.|andi.} %0,%1,%b2 | |
29ae5b89 JL |
1830 | {andiu.|andis.} %0,%1,%u2" |
1831 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1832 | |
7cd5235b | 1833 | (define_insn "*andsi3_internal2" |
29ae5b89 JL |
1834 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") |
1835 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1836 | (match_operand:SI 2 "and_operand" "r,K,J,L")) | |
1fd4e8c1 | 1837 | (const_int 0))) |
29ae5b89 | 1838 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
1fd4e8c1 RK |
1839 | "" |
1840 | "@ | |
1841 | and. %3,%1,%2 | |
ca7f5001 RK |
1842 | {andil.|andi.} %3,%1,%b2 |
1843 | {andiu.|andis.} %3,%1,%u2 | |
29ae5b89 JL |
1844 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2" |
1845 | [(set_attr "type" "compare,compare,compare,delayed_compare")]) | |
1fd4e8c1 | 1846 | |
7cd5235b | 1847 | (define_insn "*andsi3_internal3" |
29ae5b89 JL |
1848 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") |
1849 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1850 | (match_operand:SI 2 "and_operand" "r,K,J,L")) | |
1fd4e8c1 | 1851 | (const_int 0))) |
29ae5b89 JL |
1852 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1853 | (and:SI (match_dup 1) (match_dup 2)))] | |
1fd4e8c1 RK |
1854 | "" |
1855 | "@ | |
1856 | and. %0,%1,%2 | |
ca7f5001 RK |
1857 | {andil.|andi.} %0,%1,%b2 |
1858 | {andiu.|andis.} %0,%1,%u2 | |
29ae5b89 JL |
1859 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2" |
1860 | [(set_attr "type" "compare,compare,compare,delayed_compare")]) | |
1fd4e8c1 | 1861 | |
7cd5235b | 1862 | (define_expand "iorsi3" |
cd2b37d9 | 1863 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b MM |
1864 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1865 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
1866 | "" | |
f357808b RK |
1867 | " |
1868 | { | |
7cd5235b MM |
1869 | if (GET_CODE (operands[2]) == CONST_INT |
1870 | && !logical_operand (operands[2], SImode)) | |
1871 | { | |
1872 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
1873 | rtx tmp = ((reload_in_progress || reload_completed | |
1874 | || rtx_equal_p (operands[0], operands[1])) | |
1875 | ? operands[0] : gen_reg_rtx (SImode)); | |
1876 | ||
a260abc9 DE |
1877 | emit_insn (gen_iorsi3 (tmp, operands[1], |
1878 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
1879 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
1880 | DONE; |
1881 | } | |
f357808b RK |
1882 | }") |
1883 | ||
7cd5235b MM |
1884 | (define_insn "*iorsi3_internal1" |
1885 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") | |
1886 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") | |
1887 | (match_operand:SI 2 "logical_operand" "r,K,J")))] | |
1fd4e8c1 RK |
1888 | "" |
1889 | "@ | |
1890 | or %0,%1,%2 | |
ca7f5001 | 1891 | {oril|ori} %0,%1,%b2 |
7cd5235b MM |
1892 | {oriu|oris} %0,%1,%u2" |
1893 | [(set_attr "length" "4,4,4")]) | |
1fd4e8c1 | 1894 | |
7cd5235b | 1895 | (define_insn "*iorsi3_internal2" |
29ae5b89 JL |
1896 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1897 | (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1898 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 1899 | (const_int 0))) |
29ae5b89 | 1900 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 1901 | "" |
29ae5b89 JL |
1902 | "or. %3,%1,%2" |
1903 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 1904 | |
7cd5235b | 1905 | (define_insn "*iorsi3_internal3" |
29ae5b89 JL |
1906 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1907 | (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1908 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 1909 | (const_int 0))) |
29ae5b89 JL |
1910 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1911 | (ior:SI (match_dup 1) (match_dup 2)))] | |
1fd4e8c1 | 1912 | "" |
29ae5b89 | 1913 | "or. %0,%1,%2" |
1fd4e8c1 RK |
1914 | [(set_attr "type" "compare")]) |
1915 | ||
a260abc9 DE |
1916 | ;; Split an IOR that we can't do in one insn into two insns, each of which |
1917 | ;; does one 16-bit part. This is used by combine. | |
1918 | ||
1919 | (define_split | |
1920 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1921 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1922 | (match_operand:SI 2 "non_logical_cint_operand" "")))] | |
1923 | "" | |
1924 | [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3))) | |
1925 | (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))] | |
1926 | " | |
1927 | { | |
1928 | operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
1929 | operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
1930 | }") | |
1931 | ||
7cd5235b | 1932 | (define_expand "xorsi3" |
cd2b37d9 | 1933 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b MM |
1934 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1935 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
1fd4e8c1 | 1936 | "" |
7cd5235b | 1937 | " |
1fd4e8c1 | 1938 | { |
7cd5235b MM |
1939 | if (GET_CODE (operands[2]) == CONST_INT |
1940 | && !logical_operand (operands[2], SImode)) | |
1941 | { | |
1942 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
1943 | rtx tmp = ((reload_in_progress || reload_completed | |
1944 | || rtx_equal_p (operands[0], operands[1])) | |
1945 | ? operands[0] : gen_reg_rtx (SImode)); | |
1946 | ||
a260abc9 DE |
1947 | emit_insn (gen_xorsi3 (tmp, operands[1], |
1948 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
1949 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
1950 | DONE; |
1951 | } | |
1fd4e8c1 RK |
1952 | }") |
1953 | ||
7cd5235b MM |
1954 | (define_insn "*xorsi3_internal1" |
1955 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") | |
1956 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") | |
1957 | (match_operand:SI 2 "logical_operand" "r,K,J")))] | |
1fd4e8c1 RK |
1958 | "" |
1959 | "@ | |
1960 | xor %0,%1,%2 | |
ca7f5001 | 1961 | {xoril|xori} %0,%1,%b2 |
7cd5235b MM |
1962 | {xoriu|xoris} %0,%1,%u2" |
1963 | [(set_attr "length" "4,4,4")]) | |
1fd4e8c1 | 1964 | |
7cd5235b | 1965 | (define_insn "*xorsi3_internal2" |
29ae5b89 JL |
1966 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1967 | (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1968 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 1969 | (const_int 0))) |
29ae5b89 | 1970 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 1971 | "" |
29ae5b89 JL |
1972 | "xor. %3,%1,%2" |
1973 | [(set_attr "type" "compare")]) | |
815cdc52 | 1974 | |
29ae5b89 JL |
1975 | (define_insn "*xorsi3_internal3" |
1976 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
1977 | (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1978 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
815cdc52 | 1979 | (const_int 0))) |
29ae5b89 | 1980 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
815cdc52 | 1981 | (xor:SI (match_dup 1) (match_dup 2)))] |
29ae5b89 JL |
1982 | "" |
1983 | "xor. %0,%1,%2" | |
1984 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 1985 | |
a260abc9 DE |
1986 | ;; Split an XOR that we can't do in one insn into two insns, each of which |
1987 | ;; does one 16-bit part. This is used by combine. | |
1988 | ||
1989 | (define_split | |
1990 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1991 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1992 | (match_operand:SI 2 "non_logical_cint_operand" "")))] | |
1993 | "" | |
1994 | [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3))) | |
1995 | (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))] | |
1996 | " | |
1997 | { | |
1998 | operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
1999 | operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
2000 | }") | |
2001 | ||
2002 | (define_insn "*eqvsi3_internal1" | |
cd2b37d9 RK |
2003 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2004 | (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
2005 | (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
1fd4e8c1 RK |
2006 | "" |
2007 | "eqv %0,%1,%2") | |
2008 | ||
a260abc9 | 2009 | (define_insn "*eqvsi3_internal2" |
29ae5b89 JL |
2010 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
2011 | (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
2012 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1fd4e8c1 | 2013 | (const_int 0))) |
29ae5b89 | 2014 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 2015 | "" |
29ae5b89 JL |
2016 | "eqv. %3,%1,%2" |
2017 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2018 | |
a260abc9 | 2019 | (define_insn "*eqvsi3_internal3" |
29ae5b89 JL |
2020 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
2021 | (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
2022 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1fd4e8c1 | 2023 | (const_int 0))) |
29ae5b89 | 2024 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2025 | (not:SI (xor:SI (match_dup 1) (match_dup 2))))] |
2026 | "" | |
29ae5b89 JL |
2027 | "eqv. %0,%1,%2" |
2028 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2029 | |
a260abc9 | 2030 | (define_insn "*andcsi3_internal1" |
cd2b37d9 RK |
2031 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2032 | (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2033 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
2034 | "" |
2035 | "andc %0,%2,%1") | |
2036 | ||
a260abc9 | 2037 | (define_insn "*andcsi3_internal2" |
29ae5b89 JL |
2038 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
2039 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2040 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 2041 | (const_int 0))) |
29ae5b89 | 2042 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 2043 | "" |
29ae5b89 JL |
2044 | "andc. %3,%2,%1" |
2045 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2046 | |
a260abc9 | 2047 | (define_insn "*andcsi3_internal3" |
29ae5b89 JL |
2048 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
2049 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2050 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 2051 | (const_int 0))) |
29ae5b89 JL |
2052 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2053 | (and:SI (not:SI (match_dup 1)) (match_dup 2)))] | |
1fd4e8c1 | 2054 | "" |
29ae5b89 JL |
2055 | "andc. %0,%2,%1" |
2056 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2057 | |
a260abc9 | 2058 | (define_insn "*iorcsi3_internal1" |
cd2b37d9 RK |
2059 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2060 | (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2061 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
2062 | "" |
2063 | "orc %0,%2,%1") | |
2064 | ||
a260abc9 | 2065 | (define_insn "*iorcsi3_internal2" |
29ae5b89 JL |
2066 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
2067 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2068 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 2069 | (const_int 0))) |
29ae5b89 | 2070 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 2071 | "" |
29ae5b89 JL |
2072 | "orc. %3,%2,%1" |
2073 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2074 | |
a260abc9 | 2075 | (define_insn "*iorcsi3_internal3" |
29ae5b89 JL |
2076 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
2077 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2078 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 2079 | (const_int 0))) |
29ae5b89 | 2080 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2081 | (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] |
2082 | "" | |
29ae5b89 | 2083 | "orc. %0,%2,%1" |
1fd4e8c1 RK |
2084 | [(set_attr "type" "compare")]) |
2085 | ||
a260abc9 | 2086 | (define_insn "*nandsi3_internal1" |
cd2b37d9 | 2087 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
29ae5b89 | 2088 | (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 2089 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] |
1fd4e8c1 RK |
2090 | "" |
2091 | "nand %0,%1,%2") | |
2092 | ||
a260abc9 | 2093 | (define_insn "*nandsi3_internal2" |
29ae5b89 JL |
2094 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
2095 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
2096 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1fd4e8c1 | 2097 | (const_int 0))) |
29ae5b89 | 2098 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 2099 | "" |
29ae5b89 JL |
2100 | "nand. %3,%1,%2" |
2101 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2102 | |
a260abc9 | 2103 | (define_insn "*nandsi3_internal3" |
29ae5b89 JL |
2104 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
2105 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
2106 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1fd4e8c1 | 2107 | (const_int 0))) |
29ae5b89 JL |
2108 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2109 | (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] | |
1fd4e8c1 | 2110 | "" |
29ae5b89 JL |
2111 | "nand. %0,%1,%2" |
2112 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2113 | |
a260abc9 | 2114 | (define_insn "*norsi3_internal1" |
cd2b37d9 | 2115 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
29ae5b89 | 2116 | (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 2117 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] |
1fd4e8c1 RK |
2118 | "" |
2119 | "nor %0,%1,%2") | |
2120 | ||
a260abc9 | 2121 | (define_insn "*norsi3_internal2" |
29ae5b89 JL |
2122 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
2123 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
2124 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1fd4e8c1 | 2125 | (const_int 0))) |
29ae5b89 | 2126 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 2127 | "" |
29ae5b89 JL |
2128 | "nor. %3,%1,%2" |
2129 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2130 | |
a260abc9 | 2131 | (define_insn "*norsi3_internal3" |
29ae5b89 JL |
2132 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
2133 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
2134 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1fd4e8c1 | 2135 | (const_int 0))) |
29ae5b89 JL |
2136 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2137 | (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] | |
1fd4e8c1 | 2138 | "" |
29ae5b89 JL |
2139 | "nor. %0,%1,%2" |
2140 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
2141 | |
2142 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2143 | ;; orders. Don't define forms that only set CR fields because these | |
2144 | ;; would modify an input register. | |
2145 | ||
7cd5235b | 2146 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2147 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2148 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2149 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2150 | (and:SI (match_dup 2) | |
cd2b37d9 | 2151 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2152 | "TARGET_POWER" |
01def764 | 2153 | "maskir %0,%3,%2") |
1fd4e8c1 | 2154 | |
7cd5235b | 2155 | (define_insn "*maskir_internal2" |
242e8072 | 2156 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2157 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2158 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2159 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2160 | (match_dup 2))))] |
ca7f5001 | 2161 | "TARGET_POWER" |
01def764 | 2162 | "maskir %0,%3,%2") |
1fd4e8c1 | 2163 | |
7cd5235b | 2164 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2165 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2166 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2167 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2168 | (and:SI (not:SI (match_dup 2)) |
2169 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2170 | "TARGET_POWER" |
01def764 | 2171 | "maskir %0,%3,%2") |
1fd4e8c1 | 2172 | |
7cd5235b | 2173 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2174 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2175 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2176 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2177 | (and:SI (not:SI (match_dup 2)) | |
2178 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2179 | "TARGET_POWER" |
01def764 | 2180 | "maskir %0,%3,%2") |
1fd4e8c1 | 2181 | |
7cd5235b | 2182 | (define_insn "*maskir_internal5" |
29ae5b89 | 2183 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 2184 | (compare:CC |
29ae5b89 JL |
2185 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2186 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
01def764 | 2187 | (and:SI (match_dup 2) |
29ae5b89 | 2188 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 2189 | (const_int 0))) |
29ae5b89 | 2190 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2191 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2192 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2193 | "TARGET_POWER" |
29ae5b89 JL |
2194 | "maskir. %0,%3,%2" |
2195 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2196 | |
7cd5235b | 2197 | (define_insn "*maskir_internal6" |
29ae5b89 | 2198 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 2199 | (compare:CC |
29ae5b89 JL |
2200 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2201 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2202 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 | 2203 | (match_dup 2))) |
1fd4e8c1 | 2204 | (const_int 0))) |
29ae5b89 | 2205 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2206 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2207 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 2208 | "TARGET_POWER" |
29ae5b89 JL |
2209 | "maskir. %0,%3,%2" |
2210 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2211 | |
7cd5235b | 2212 | (define_insn "*maskir_internal7" |
29ae5b89 | 2213 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
815cdc52 | 2214 | (compare:CC |
29ae5b89 JL |
2215 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
2216 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
815cdc52 | 2217 | (and:SI (not:SI (match_dup 2)) |
29ae5b89 | 2218 | (match_operand:SI 1 "gpc_reg_operand" "0"))) |
815cdc52 | 2219 | (const_int 0))) |
29ae5b89 | 2220 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
815cdc52 MM |
2221 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
2222 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2223 | "TARGET_POWER" | |
29ae5b89 JL |
2224 | "maskir. %0,%3,%2" |
2225 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2226 | |
7cd5235b | 2227 | (define_insn "*maskir_internal8" |
29ae5b89 | 2228 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 2229 | (compare:CC |
29ae5b89 JL |
2230 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
2231 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
01def764 | 2232 | (and:SI (not:SI (match_dup 2)) |
29ae5b89 | 2233 | (match_operand:SI 1 "gpc_reg_operand" "0"))) |
1fd4e8c1 | 2234 | (const_int 0))) |
29ae5b89 | 2235 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2236 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
2237 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 2238 | "TARGET_POWER" |
29ae5b89 JL |
2239 | "maskir. %0,%3,%2" |
2240 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
2241 | \f |
2242 | ;; Rotate and shift insns, in all their variants. These support shifts, | |
2243 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 MM |
2244 | (define_expand "insv" |
2245 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") | |
2246 | (match_operand:SI 1 "const_int_operand" "i") | |
2247 | (match_operand:SI 2 "const_int_operand" "i")) | |
2248 | (match_operand:SI 3 "gpc_reg_operand" "r"))] | |
2249 | "" | |
2250 | " | |
2251 | { | |
2252 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2253 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2254 | compiler if the address of the structure is taken later. */ | |
2255 | if (GET_CODE (operands[0]) == SUBREG | |
2256 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2257 | FAIL; | |
2258 | }") | |
2259 | ||
2260 | (define_insn "" | |
cd2b37d9 | 2261 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
2262 | (match_operand:SI 1 "const_int_operand" "i") |
2263 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 2264 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
2265 | "" |
2266 | "* | |
2267 | { | |
2268 | int start = INTVAL (operands[2]) & 31; | |
2269 | int size = INTVAL (operands[1]) & 31; | |
2270 | ||
89e9f3a8 MM |
2271 | operands[4] = GEN_INT (32 - start - size); |
2272 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2273 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
1fd4e8c1 RK |
2274 | }") |
2275 | ||
d56d506a RK |
2276 | (define_insn "" |
2277 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") | |
2278 | (match_operand:SI 1 "const_int_operand" "i") | |
2279 | (match_operand:SI 2 "const_int_operand" "i")) | |
2280 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2281 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2282 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2283 | "* |
2284 | { | |
2285 | int shift = INTVAL (operands[4]) & 31; | |
2286 | int start = INTVAL (operands[2]) & 31; | |
2287 | int size = INTVAL (operands[1]) & 31; | |
2288 | ||
89e9f3a8 MM |
2289 | operands[4] = GEN_INT (shift - start - size); |
2290 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2291 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
2292 | }") |
2293 | ||
2294 | (define_insn "" | |
2295 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") | |
2296 | (match_operand:SI 1 "const_int_operand" "i") | |
2297 | (match_operand:SI 2 "const_int_operand" "i")) | |
2298 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2299 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2300 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2301 | "* |
2302 | { | |
2303 | int shift = INTVAL (operands[4]) & 31; | |
2304 | int start = INTVAL (operands[2]) & 31; | |
2305 | int size = INTVAL (operands[1]) & 31; | |
2306 | ||
89e9f3a8 MM |
2307 | operands[4] = GEN_INT (32 - shift - start - size); |
2308 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2309 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
2310 | }") |
2311 | ||
2312 | (define_insn "" | |
2313 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") | |
2314 | (match_operand:SI 1 "const_int_operand" "i") | |
2315 | (match_operand:SI 2 "const_int_operand" "i")) | |
2316 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2317 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 2318 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2319 | "* |
2320 | { | |
2321 | int shift = INTVAL (operands[4]) & 31; | |
2322 | int start = INTVAL (operands[2]) & 31; | |
2323 | int size = INTVAL (operands[1]) & 31; | |
2324 | ||
89e9f3a8 MM |
2325 | operands[4] = GEN_INT (32 - shift - start - size); |
2326 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2327 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
2328 | }") |
2329 | ||
2330 | (define_insn "" | |
2331 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") | |
2332 | (match_operand:SI 1 "const_int_operand" "i") | |
2333 | (match_operand:SI 2 "const_int_operand" "i")) | |
2334 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2335 | (match_operand:SI 4 "const_int_operand" "i") | |
2336 | (match_operand:SI 5 "const_int_operand" "i")))] | |
2337 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
2338 | "* | |
2339 | { | |
2340 | int extract_start = INTVAL (operands[5]) & 31; | |
2341 | int extract_size = INTVAL (operands[4]) & 31; | |
2342 | int insert_start = INTVAL (operands[2]) & 31; | |
2343 | int insert_size = INTVAL (operands[1]) & 31; | |
2344 | ||
2345 | /* Align extract field with insert field */ | |
3a598fbe | 2346 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 2347 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 2348 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
d56d506a RK |
2349 | }") |
2350 | ||
685f3906 DE |
2351 | (define_insn "" |
2352 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
2353 | (match_operand:DI 1 "const_int_operand" "i") | |
2354 | (match_operand:DI 2 "const_int_operand" "i")) | |
2355 | (match_operand:DI 3 "gpc_reg_operand" "r"))] | |
2356 | "TARGET_POWERPC64" | |
2357 | "* | |
2358 | { | |
2359 | int start = INTVAL (operands[2]) & 63; | |
2360 | int size = INTVAL (operands[1]) & 63; | |
2361 | ||
89e9f3a8 | 2362 | operands[2] = GEN_INT (64 - start - size); |
a66078ee | 2363 | return \"rldimi %0,%3,%H2,%H1\"; |
685f3906 DE |
2364 | }") |
2365 | ||
034c1be0 MM |
2366 | (define_expand "extzv" |
2367 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2368 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2369 | (match_operand:SI 2 "const_int_operand" "i") | |
2370 | (match_operand:SI 3 "const_int_operand" "i")))] | |
2371 | "" | |
2372 | " | |
2373 | { | |
2374 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2375 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2376 | compiler if the address of the structure is taken later. */ | |
2377 | if (GET_CODE (operands[0]) == SUBREG | |
2378 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2379 | FAIL; | |
2380 | }") | |
2381 | ||
2382 | (define_insn "" | |
cd2b37d9 RK |
2383 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2384 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2385 | (match_operand:SI 2 "const_int_operand" "i") |
2386 | (match_operand:SI 3 "const_int_operand" "i")))] | |
2387 | "" | |
2388 | "* | |
2389 | { | |
2390 | int start = INTVAL (operands[3]) & 31; | |
2391 | int size = INTVAL (operands[2]) & 31; | |
2392 | ||
2393 | if (start + size >= 32) | |
2394 | operands[3] = const0_rtx; | |
2395 | else | |
89e9f3a8 | 2396 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 2397 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
2398 | }") |
2399 | ||
2400 | (define_insn "" | |
29ae5b89 JL |
2401 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
2402 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2403 | (match_operand:SI 2 "const_int_operand" "i") | |
2404 | (match_operand:SI 3 "const_int_operand" "i")) | |
1fd4e8c1 | 2405 | (const_int 0))) |
29ae5b89 | 2406 | (clobber (match_scratch:SI 4 "=r"))] |
1fd4e8c1 RK |
2407 | "" |
2408 | "* | |
2409 | { | |
2410 | int start = INTVAL (operands[3]) & 31; | |
2411 | int size = INTVAL (operands[2]) & 31; | |
2412 | ||
a7a975e1 RK |
2413 | /* If the bitfield being tested fits in the upper or lower half of a |
2414 | word, it is possible to use andiu. or andil. to test it. This is | |
2415 | useful because the condition register set-use delay is smaller for | |
2416 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
2417 | position is 0 because the LT and GT bits may be set wrong. */ | |
2418 | ||
2419 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 2420 | { |
3a598fbe | 2421 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
2422 | - (1 << (16 - (start & 15) - size)))); |
2423 | if (start < 16) | |
ca7f5001 | 2424 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 2425 | else |
ca7f5001 | 2426 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 2427 | } |
7e69e155 | 2428 | |
1fd4e8c1 RK |
2429 | if (start + size >= 32) |
2430 | operands[3] = const0_rtx; | |
2431 | else | |
89e9f3a8 | 2432 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 2433 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 2434 | }" |
29ae5b89 | 2435 | [(set_attr "type" "compare")]) |
1fd4e8c1 RK |
2436 | |
2437 | (define_insn "" | |
29ae5b89 JL |
2438 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
2439 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2440 | (match_operand:SI 2 "const_int_operand" "i") | |
2441 | (match_operand:SI 3 "const_int_operand" "i")) | |
1fd4e8c1 | 2442 | (const_int 0))) |
29ae5b89 | 2443 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2444 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
2445 | "" | |
2446 | "* | |
2447 | { | |
2448 | int start = INTVAL (operands[3]) & 31; | |
2449 | int size = INTVAL (operands[2]) & 31; | |
2450 | ||
a7a975e1 | 2451 | if (start >= 16 && start + size == 32) |
df031c43 | 2452 | { |
89e9f3a8 | 2453 | operands[3] = GEN_INT ((1 << (32 - start)) - 1); |
ca7f5001 | 2454 | return \"{andil.|andi.} %0,%1,%3\"; |
df031c43 | 2455 | } |
7e69e155 | 2456 | |
1fd4e8c1 RK |
2457 | if (start + size >= 32) |
2458 | operands[3] = const0_rtx; | |
2459 | else | |
89e9f3a8 | 2460 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 2461 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
2462 | }" |
2463 | [(set_attr "type" "delayed_compare")]) | |
2464 | ||
685f3906 DE |
2465 | (define_insn "" |
2466 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
2467 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2468 | (match_operand:DI 2 "const_int_operand" "i") | |
2469 | (match_operand:DI 3 "const_int_operand" "i")))] | |
2470 | "TARGET_POWERPC64" | |
2471 | "* | |
2472 | { | |
2473 | int start = INTVAL (operands[3]) & 63; | |
2474 | int size = INTVAL (operands[2]) & 63; | |
2475 | ||
2476 | if (start + size >= 64) | |
2477 | operands[3] = const0_rtx; | |
2478 | else | |
89e9f3a8 MM |
2479 | operands[3] = GEN_INT (start + size); |
2480 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
2481 | return \"rldicl %0,%1,%3,%2\"; |
2482 | }") | |
2483 | ||
2484 | (define_insn "" | |
29ae5b89 JL |
2485 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
2486 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2487 | (match_operand:DI 2 "const_int_operand" "i") | |
2488 | (match_operand:DI 3 "const_int_operand" "i")) | |
685f3906 | 2489 | (const_int 0))) |
29ae5b89 | 2490 | (clobber (match_scratch:DI 4 "=r"))] |
685f3906 DE |
2491 | "TARGET_POWERPC64" |
2492 | "* | |
2493 | { | |
2494 | int start = INTVAL (operands[3]) & 63; | |
2495 | int size = INTVAL (operands[2]) & 63; | |
2496 | ||
2497 | if (start + size >= 64) | |
2498 | operands[3] = const0_rtx; | |
2499 | else | |
89e9f3a8 MM |
2500 | operands[3] = GEN_INT (start + size); |
2501 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
2502 | return \"rldicl. %4,%1,%3,%2\"; |
2503 | }") | |
2504 | ||
2505 | (define_insn "" | |
29ae5b89 JL |
2506 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
2507 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2508 | (match_operand:DI 2 "const_int_operand" "i") | |
2509 | (match_operand:DI 3 "const_int_operand" "i")) | |
685f3906 | 2510 | (const_int 0))) |
29ae5b89 | 2511 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 DE |
2512 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
2513 | "TARGET_POWERPC64" | |
2514 | "* | |
2515 | { | |
2516 | int start = INTVAL (operands[3]) & 63; | |
2517 | int size = INTVAL (operands[2]) & 63; | |
2518 | ||
2519 | if (start + size >= 64) | |
2520 | operands[3] = const0_rtx; | |
2521 | else | |
89e9f3a8 MM |
2522 | operands[3] = GEN_INT (start + size); |
2523 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
2524 | return \"rldicl. %0,%1,%3,%2\"; |
2525 | }") | |
2526 | ||
1fd4e8c1 | 2527 | (define_insn "rotlsi3" |
cd2b37d9 RK |
2528 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2529 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2530 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
2531 | "" | |
ca7f5001 | 2532 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 2533 | |
a260abc9 | 2534 | (define_insn "*rotlsi3_internal2" |
29ae5b89 JL |
2535 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
2536 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2537 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
1fd4e8c1 | 2538 | (const_int 0))) |
29ae5b89 | 2539 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 2540 | "" |
29ae5b89 JL |
2541 | "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff" |
2542 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 2543 | |
a260abc9 | 2544 | (define_insn "*rotlsi3_internal3" |
29ae5b89 JL |
2545 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
2546 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2547 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
1fd4e8c1 | 2548 | (const_int 0))) |
29ae5b89 | 2549 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2550 | (rotate:SI (match_dup 1) (match_dup 2)))] |
2551 | "" | |
29ae5b89 JL |
2552 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff" |
2553 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 2554 | |
a260abc9 | 2555 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
2556 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2557 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2558 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
2559 | (match_operand:SI 3 "mask_operand" "L")))] | |
2560 | "" | |
ca7f5001 | 2561 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 2562 | |
a260abc9 | 2563 | (define_insn "*rotlsi3_internal5" |
29ae5b89 | 2564 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 2565 | (compare:CC (and:SI |
29ae5b89 JL |
2566 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2567 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
2568 | (match_operand:SI 3 "mask_operand" "L")) | |
1fd4e8c1 | 2569 | (const_int 0))) |
29ae5b89 | 2570 | (clobber (match_scratch:SI 4 "=r"))] |
1fd4e8c1 | 2571 | "" |
29ae5b89 JL |
2572 | "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3" |
2573 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 2574 | |
a260abc9 | 2575 | (define_insn "*rotlsi3_internal6" |
29ae5b89 | 2576 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 2577 | (compare:CC (and:SI |
29ae5b89 JL |
2578 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2579 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
2580 | (match_operand:SI 3 "mask_operand" "L")) | |
1fd4e8c1 | 2581 | (const_int 0))) |
29ae5b89 | 2582 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2583 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
2584 | "" | |
29ae5b89 JL |
2585 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3" |
2586 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 2587 | |
a260abc9 | 2588 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 2589 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2590 | (zero_extend:SI |
2591 | (subreg:QI | |
cd2b37d9 | 2592 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2593 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
2594 | "" | |
ca7f5001 | 2595 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 2596 | |
a260abc9 | 2597 | (define_insn "*rotlsi3_internal8" |
29ae5b89 | 2598 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
2599 | (compare:CC (zero_extend:SI |
2600 | (subreg:QI | |
29ae5b89 JL |
2601 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2602 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) | |
1fd4e8c1 | 2603 | (const_int 0))) |
29ae5b89 | 2604 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 2605 | "" |
29ae5b89 JL |
2606 | "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff" |
2607 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 2608 | |
a260abc9 | 2609 | (define_insn "*rotlsi3_internal9" |
29ae5b89 | 2610 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
2611 | (compare:CC (zero_extend:SI |
2612 | (subreg:QI | |
29ae5b89 JL |
2613 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2614 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) | |
1fd4e8c1 | 2615 | (const_int 0))) |
29ae5b89 | 2616 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2617 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
2618 | "" | |
29ae5b89 JL |
2619 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff" |
2620 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 2621 | |
a260abc9 | 2622 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 2623 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2624 | (zero_extend:SI |
2625 | (subreg:HI | |
cd2b37d9 | 2626 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2627 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
2628 | "" | |
ca7f5001 | 2629 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 2630 | |
a260abc9 | 2631 | (define_insn "*rotlsi3_internal11" |
29ae5b89 | 2632 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
2633 | (compare:CC (zero_extend:SI |
2634 | (subreg:HI | |
29ae5b89 JL |
2635 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2636 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) | |
1fd4e8c1 | 2637 | (const_int 0))) |
29ae5b89 | 2638 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 2639 | "" |
29ae5b89 JL |
2640 | "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff" |
2641 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 2642 | |
a260abc9 | 2643 | (define_insn "*rotlsi3_internal12" |
29ae5b89 | 2644 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
2645 | (compare:CC (zero_extend:SI |
2646 | (subreg:HI | |
29ae5b89 JL |
2647 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2648 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) | |
1fd4e8c1 | 2649 | (const_int 0))) |
29ae5b89 | 2650 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2651 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
2652 | "" | |
29ae5b89 JL |
2653 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff" |
2654 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
2655 | |
2656 | ;; Note that we use "sle." instead of "sl." so that we can set | |
2657 | ;; SHIFT_COUNT_TRUNCATED. | |
2658 | ||
ca7f5001 RK |
2659 | (define_expand "ashlsi3" |
2660 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
2661 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
2662 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
2663 | "" | |
2664 | " | |
2665 | { | |
2666 | if (TARGET_POWER) | |
2667 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
2668 | else | |
25c341fa | 2669 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
2670 | DONE; |
2671 | }") | |
2672 | ||
2673 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
2674 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2675 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
2676 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
2677 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 2678 | "TARGET_POWER" |
1fd4e8c1 RK |
2679 | "@ |
2680 | sle %0,%1,%2 | |
ca7f5001 RK |
2681 | {sli|slwi} %0,%1,%h2" |
2682 | [(set_attr "length" "8")]) | |
2683 | ||
25c341fa | 2684 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
2685 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2686 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2687 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 2688 | "! TARGET_POWER" |
d904e9ed | 2689 | "{sl|slw}%I2 %0,%1,%h2" |
b19003d8 | 2690 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
2691 | |
2692 | (define_insn "" | |
29ae5b89 JL |
2693 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
2694 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2695 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) | |
1fd4e8c1 | 2696 | (const_int 0))) |
29ae5b89 JL |
2697 | (clobber (match_scratch:SI 3 "=r,r")) |
2698 | (clobber (match_scratch:SI 4 "=q,X"))] | |
ca7f5001 | 2699 | "TARGET_POWER" |
1fd4e8c1 RK |
2700 | "@ |
2701 | sle. %3,%1,%2 | |
29ae5b89 JL |
2702 | {sli.|slwi.} %3,%1,%h2" |
2703 | [(set_attr "type" "delayed_compare")]) | |
25c341fa | 2704 | |
ca7f5001 | 2705 | (define_insn "" |
29ae5b89 JL |
2706 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
2707 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2708 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
ca7f5001 | 2709 | (const_int 0))) |
29ae5b89 | 2710 | (clobber (match_scratch:SI 3 "=r"))] |
8ffd9c51 | 2711 | "! TARGET_POWER" |
29ae5b89 JL |
2712 | "{sl|slw}%I2. %3,%1,%h2" |
2713 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
2714 | |
2715 | (define_insn "" | |
29ae5b89 JL |
2716 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
2717 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2718 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) | |
1fd4e8c1 | 2719 | (const_int 0))) |
29ae5b89 | 2720 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 2721 | (ashift:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 2722 | (clobber (match_scratch:SI 4 "=q,X"))] |
ca7f5001 | 2723 | "TARGET_POWER" |
1fd4e8c1 RK |
2724 | "@ |
2725 | sle. %0,%1,%2 | |
29ae5b89 | 2726 | {sli.|slwi.} %0,%1,%h2" |
ca7f5001 | 2727 | [(set_attr "type" "delayed_compare")]) |
25c341fa | 2728 | |
ca7f5001 | 2729 | (define_insn "" |
29ae5b89 JL |
2730 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
2731 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2732 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
ca7f5001 | 2733 | (const_int 0))) |
29ae5b89 | 2734 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ca7f5001 | 2735 | (ashift:SI (match_dup 1) (match_dup 2)))] |
8ffd9c51 | 2736 | "! TARGET_POWER" |
d904e9ed | 2737 | "{sl|slw}%I2. %0,%1,%h2" |
1fd4e8c1 RK |
2738 | [(set_attr "type" "delayed_compare")]) |
2739 | ||
2740 | (define_insn "" | |
cd2b37d9 RK |
2741 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2742 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2743 | (match_operand:SI 2 "const_int_operand" "i")) |
2744 | (match_operand:SI 3 "mask_operand" "L")))] | |
2745 | "includes_lshift_p (operands[2], operands[3])" | |
d56d506a | 2746 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
2747 | |
2748 | (define_insn "" | |
29ae5b89 | 2749 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 2750 | (compare:CC |
29ae5b89 JL |
2751 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2752 | (match_operand:SI 2 "const_int_operand" "i")) | |
2753 | (match_operand:SI 3 "mask_operand" "L")) | |
1fd4e8c1 | 2754 | (const_int 0))) |
29ae5b89 | 2755 | (clobber (match_scratch:SI 4 "=r"))] |
1fd4e8c1 | 2756 | "includes_lshift_p (operands[2], operands[3])" |
29ae5b89 | 2757 | "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3" |
1fd4e8c1 RK |
2758 | [(set_attr "type" "delayed_compare")]) |
2759 | ||
2760 | (define_insn "" | |
29ae5b89 | 2761 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 2762 | (compare:CC |
29ae5b89 JL |
2763 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2764 | (match_operand:SI 2 "const_int_operand" "i")) | |
2765 | (match_operand:SI 3 "mask_operand" "L")) | |
1fd4e8c1 | 2766 | (const_int 0))) |
29ae5b89 | 2767 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2768 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
2769 | "includes_lshift_p (operands[2], operands[3])" | |
29ae5b89 | 2770 | "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3" |
1fd4e8c1 RK |
2771 | [(set_attr "type" "delayed_compare")]) |
2772 | ||
ca7f5001 | 2773 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 2774 | ;; "sli x,x,0". |
ca7f5001 RK |
2775 | (define_expand "lshrsi3" |
2776 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
2777 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
2778 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
2779 | "" | |
2780 | " | |
2781 | { | |
2782 | if (TARGET_POWER) | |
2783 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
2784 | else | |
25c341fa | 2785 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
2786 | DONE; |
2787 | }") | |
2788 | ||
2789 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
2790 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
2791 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
2792 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
2793 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 2794 | "TARGET_POWER" |
1fd4e8c1 RK |
2795 | "@ |
2796 | sre %0,%1,%2 | |
bdf423cb | 2797 | mr %0,%1 |
ca7f5001 RK |
2798 | {s%A2i|s%A2wi} %0,%1,%h2") |
2799 | ||
25c341fa | 2800 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
2801 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2802 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2803 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 2804 | "! TARGET_POWER" |
bdf423cb MM |
2805 | "@ |
2806 | mr %0,%1 | |
2807 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
2808 | |
2809 | (define_insn "" | |
29ae5b89 JL |
2810 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x") |
2811 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
2812 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")) | |
1fd4e8c1 | 2813 | (const_int 0))) |
29ae5b89 JL |
2814 | (clobber (match_scratch:SI 3 "=r,X,r")) |
2815 | (clobber (match_scratch:SI 4 "=q,X,X"))] | |
ca7f5001 | 2816 | "TARGET_POWER" |
1fd4e8c1 | 2817 | "@ |
29ae5b89 JL |
2818 | sre. %3,%1,%2 |
2819 | mr. %1,%1 | |
2820 | {s%A2i.|s%A2wi.} %3,%1,%h2" | |
2821 | [(set_attr "type" "delayed_compare")]) | |
ca7f5001 RK |
2822 | |
2823 | (define_insn "" | |
29ae5b89 JL |
2824 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
2825 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2826 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")) | |
ca7f5001 | 2827 | (const_int 0))) |
29ae5b89 | 2828 | (clobber (match_scratch:SI 3 "=X,r"))] |
25c341fa | 2829 | "! TARGET_POWER" |
bdf423cb MM |
2830 | "@ |
2831 | mr. %1,%1 | |
29ae5b89 JL |
2832 | {sr|srw}%I2. %3,%1,%h2" |
2833 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
2834 | |
2835 | (define_insn "" | |
29ae5b89 JL |
2836 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x") |
2837 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
2838 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")) | |
1fd4e8c1 | 2839 | (const_int 0))) |
29ae5b89 | 2840 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1fd4e8c1 | 2841 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 2842 | (clobber (match_scratch:SI 4 "=q,X,X"))] |
ca7f5001 | 2843 | "TARGET_POWER" |
1fd4e8c1 | 2844 | "@ |
29ae5b89 JL |
2845 | sre. %0,%1,%2 |
2846 | mr. %0,%1 | |
2847 | {s%A2i.|s%A2wi.} %0,%1,%h2" | |
2848 | [(set_attr "type" "delayed_compare")]) | |
ca7f5001 RK |
2849 | |
2850 | (define_insn "" | |
29ae5b89 JL |
2851 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
2852 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2853 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")) | |
815cdc52 | 2854 | (const_int 0))) |
29ae5b89 JL |
2855 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2856 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
2857 | "! TARGET_POWER" | |
2858 | "@ | |
2859 | mr. %0,%1 | |
2860 | {sr|srw}%I2. %0,%1,%h2" | |
2861 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
2862 | |
2863 | (define_insn "" | |
cd2b37d9 RK |
2864 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2865 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2866 | (match_operand:SI 2 "const_int_operand" "i")) |
2867 | (match_operand:SI 3 "mask_operand" "L")))] | |
2868 | "includes_rshift_p (operands[2], operands[3])" | |
ca7f5001 | 2869 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
2870 | |
2871 | (define_insn "" | |
29ae5b89 | 2872 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 2873 | (compare:CC |
29ae5b89 JL |
2874 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2875 | (match_operand:SI 2 "const_int_operand" "i")) | |
2876 | (match_operand:SI 3 "mask_operand" "L")) | |
1fd4e8c1 | 2877 | (const_int 0))) |
29ae5b89 | 2878 | (clobber (match_scratch:SI 4 "=r"))] |
1fd4e8c1 | 2879 | "includes_rshift_p (operands[2], operands[3])" |
29ae5b89 JL |
2880 | "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3" |
2881 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
2882 | |
2883 | (define_insn "" | |
29ae5b89 | 2884 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 2885 | (compare:CC |
29ae5b89 JL |
2886 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2887 | (match_operand:SI 2 "const_int_operand" "i")) | |
2888 | (match_operand:SI 3 "mask_operand" "L")) | |
1fd4e8c1 | 2889 | (const_int 0))) |
29ae5b89 | 2890 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2891 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
2892 | "includes_rshift_p (operands[2], operands[3])" | |
29ae5b89 JL |
2893 | "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3" |
2894 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
2895 | |
2896 | (define_insn "" | |
cd2b37d9 | 2897 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2898 | (zero_extend:SI |
2899 | (subreg:QI | |
cd2b37d9 | 2900 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 2901 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 2902 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 2903 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
2904 | |
2905 | (define_insn "" | |
29ae5b89 | 2906 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
2907 | (compare:CC |
2908 | (zero_extend:SI | |
2909 | (subreg:QI | |
29ae5b89 JL |
2910 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2911 | (match_operand:SI 2 "const_int_operand" "i")) 0)) | |
1fd4e8c1 | 2912 | (const_int 0))) |
29ae5b89 | 2913 | (clobber (match_scratch:SI 3 "=r"))] |
89e9f3a8 | 2914 | "includes_rshift_p (operands[2], GEN_INT (255))" |
29ae5b89 JL |
2915 | "{rlinm.|rlwinm.} %3,%1,%s2,0xff" |
2916 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
2917 | |
2918 | (define_insn "" | |
29ae5b89 | 2919 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
2920 | (compare:CC |
2921 | (zero_extend:SI | |
2922 | (subreg:QI | |
29ae5b89 JL |
2923 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2924 | (match_operand:SI 2 "const_int_operand" "i")) 0)) | |
1fd4e8c1 | 2925 | (const_int 0))) |
29ae5b89 | 2926 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2927 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 2928 | "includes_rshift_p (operands[2], GEN_INT (255))" |
29ae5b89 JL |
2929 | "{rlinm.|rlwinm.} %0,%1,%s2,0xff" |
2930 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
2931 | |
2932 | (define_insn "" | |
cd2b37d9 | 2933 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2934 | (zero_extend:SI |
2935 | (subreg:HI | |
cd2b37d9 | 2936 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 2937 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 2938 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 2939 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
2940 | |
2941 | (define_insn "" | |
29ae5b89 | 2942 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
2943 | (compare:CC |
2944 | (zero_extend:SI | |
2945 | (subreg:HI | |
29ae5b89 JL |
2946 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2947 | (match_operand:SI 2 "const_int_operand" "i")) 0)) | |
1fd4e8c1 | 2948 | (const_int 0))) |
29ae5b89 | 2949 | (clobber (match_scratch:SI 3 "=r"))] |
89e9f3a8 | 2950 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
29ae5b89 JL |
2951 | "{rlinm.|rlwinm.} %3,%1,%s2,0xffff" |
2952 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
2953 | |
2954 | (define_insn "" | |
29ae5b89 | 2955 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
2956 | (compare:CC |
2957 | (zero_extend:SI | |
2958 | (subreg:HI | |
29ae5b89 JL |
2959 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2960 | (match_operand:SI 2 "const_int_operand" "i")) 0)) | |
1fd4e8c1 | 2961 | (const_int 0))) |
29ae5b89 | 2962 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2963 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 2964 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 2965 | "{rlinm.|rlwinm.} %0,%1,%s2,0xffff" |
1fd4e8c1 RK |
2966 | [(set_attr "type" "delayed_compare")]) |
2967 | ||
2968 | (define_insn "" | |
cd2b37d9 | 2969 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 2970 | (const_int 1) |
cd2b37d9 RK |
2971 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
2972 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 2973 | (const_int 31)))] |
ca7f5001 | 2974 | "TARGET_POWER" |
1fd4e8c1 RK |
2975 | "rrib %0,%1,%2") |
2976 | ||
2977 | (define_insn "" | |
cd2b37d9 | 2978 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 2979 | (const_int 1) |
cd2b37d9 RK |
2980 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
2981 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 2982 | (const_int 31)))] |
ca7f5001 | 2983 | "TARGET_POWER" |
1fd4e8c1 RK |
2984 | "rrib %0,%1,%2") |
2985 | ||
2986 | (define_insn "" | |
cd2b37d9 | 2987 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 2988 | (const_int 1) |
cd2b37d9 RK |
2989 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
2990 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2991 | (const_int 1) |
2992 | (const_int 0)))] | |
ca7f5001 | 2993 | "TARGET_POWER" |
1fd4e8c1 RK |
2994 | "rrib %0,%1,%2") |
2995 | ||
ca7f5001 RK |
2996 | (define_expand "ashrsi3" |
2997 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2998 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2999 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
3000 | "" | |
3001 | " | |
3002 | { | |
3003 | if (TARGET_POWER) | |
3004 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
3005 | else | |
25c341fa | 3006 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3007 | DONE; |
3008 | }") | |
3009 | ||
3010 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
3011 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3012 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3013 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3014 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3015 | "TARGET_POWER" |
1fd4e8c1 RK |
3016 | "@ |
3017 | srea %0,%1,%2 | |
ca7f5001 RK |
3018 | {srai|srawi} %0,%1,%h2") |
3019 | ||
25c341fa | 3020 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
3021 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3022 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3023 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3024 | "! TARGET_POWER" |
d904e9ed | 3025 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3026 | |
3027 | (define_insn "" | |
29ae5b89 JL |
3028 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
3029 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3030 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) | |
1fd4e8c1 | 3031 | (const_int 0))) |
29ae5b89 JL |
3032 | (clobber (match_scratch:SI 3 "=r,r")) |
3033 | (clobber (match_scratch:SI 4 "=q,X"))] | |
ca7f5001 | 3034 | "TARGET_POWER" |
1fd4e8c1 RK |
3035 | "@ |
3036 | srea. %3,%1,%2 | |
29ae5b89 JL |
3037 | {srai.|srawi.} %3,%1,%h2" |
3038 | [(set_attr "type" "delayed_compare")]) | |
ca7f5001 RK |
3039 | |
3040 | (define_insn "" | |
29ae5b89 JL |
3041 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
3042 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3043 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
ca7f5001 | 3044 | (const_int 0))) |
29ae5b89 | 3045 | (clobber (match_scratch:SI 3 "=r"))] |
25c341fa | 3046 | "! TARGET_POWER" |
29ae5b89 JL |
3047 | "{sra|sraw}%I2. %3,%1,%h2" |
3048 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3049 | |
3050 | (define_insn "" | |
29ae5b89 JL |
3051 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
3052 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3053 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) | |
1fd4e8c1 | 3054 | (const_int 0))) |
29ae5b89 | 3055 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3056 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 3057 | (clobber (match_scratch:SI 4 "=q,X"))] |
ca7f5001 | 3058 | "TARGET_POWER" |
1fd4e8c1 RK |
3059 | "@ |
3060 | srea. %0,%1,%2 | |
29ae5b89 JL |
3061 | {srai.|srawi.} %0,%1,%h2" |
3062 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 3063 | |
ca7f5001 | 3064 | (define_insn "" |
29ae5b89 JL |
3065 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
3066 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3067 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
ca7f5001 | 3068 | (const_int 0))) |
29ae5b89 | 3069 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ca7f5001 | 3070 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 3071 | "! TARGET_POWER" |
29ae5b89 JL |
3072 | "{sra|sraw}%I2. %0,%1,%h2" |
3073 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3074 | \f |
3075 | ;; Floating-point insns, excluding normal data motion. | |
3076 | ;; | |
ca7f5001 RK |
3077 | ;; PowerPC has a full set of single-precision floating point instructions. |
3078 | ;; | |
3079 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
3080 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
3081 | ;; The only conversions we will do will be when storing to memory. In that | |
3082 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
3083 | ;; |
3084 | ;; Note that when we store into a single-precision memory location, we need to | |
3085 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
3086 | ;; need a scratch register for the frsp. But this is difficult when the store | |
3087 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
3088 | ;; this case, we just lose precision that we would have otherwise gotten but | |
3089 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
3090 | ||
e8112008 | 3091 | (define_insn "extendsfdf2" |
cd2b37d9 | 3092 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
e8112008 | 3093 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] |
d14a6d05 | 3094 | "TARGET_HARD_FLOAT" |
e8112008 | 3095 | "* |
5c30aff8 | 3096 | { |
e8112008 RK |
3097 | if (REGNO (operands[0]) == REGNO (operands[1])) |
3098 | return \"\"; | |
3099 | else | |
3100 | return \"fmr %0,%1\"; | |
3101 | }" | |
3102 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
3103 | |
3104 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
3105 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3106 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3107 | "TARGET_HARD_FLOAT" |
dcac138d | 3108 | "frsp %0,%1" |
1fd4e8c1 RK |
3109 | [(set_attr "type" "fp")]) |
3110 | ||
455350f4 RK |
3111 | (define_insn "aux_truncdfsf2" |
3112 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3113 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))] | |
3114 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" | |
3115 | "frsp %0,%1" | |
3116 | [(set_attr "type" "fp")]) | |
3117 | ||
1fd4e8c1 | 3118 | (define_insn "negsf2" |
cd2b37d9 RK |
3119 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3120 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3121 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3122 | "fneg %0,%1" |
3123 | [(set_attr "type" "fp")]) | |
3124 | ||
3125 | (define_insn "abssf2" | |
cd2b37d9 RK |
3126 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3127 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3128 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3129 | "fabs %0,%1" |
3130 | [(set_attr "type" "fp")]) | |
3131 | ||
3132 | (define_insn "" | |
cd2b37d9 RK |
3133 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3134 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 3135 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3136 | "fnabs %0,%1" |
3137 | [(set_attr "type" "fp")]) | |
3138 | ||
ca7f5001 RK |
3139 | (define_expand "addsf3" |
3140 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3141 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
3142 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 3143 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
3144 | "") |
3145 | ||
3146 | (define_insn "" | |
cd2b37d9 RK |
3147 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3148 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3149 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3150 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3151 | "fadds %0,%1,%2" |
ca7f5001 RK |
3152 | [(set_attr "type" "fp")]) |
3153 | ||
3154 | (define_insn "" | |
3155 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3156 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3157 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3158 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3159 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
3160 | [(set_attr "type" "fp")]) |
3161 | ||
3162 | (define_expand "subsf3" | |
3163 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3164 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
3165 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 3166 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
3167 | "") |
3168 | ||
3169 | (define_insn "" | |
3170 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3171 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
3172 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3173 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3174 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
3175 | [(set_attr "type" "fp")]) |
3176 | ||
ca7f5001 | 3177 | (define_insn "" |
cd2b37d9 RK |
3178 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3179 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
3180 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3181 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3182 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
3183 | [(set_attr "type" "fp")]) |
3184 | ||
3185 | (define_expand "mulsf3" | |
3186 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3187 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
3188 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 3189 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
3190 | "") |
3191 | ||
3192 | (define_insn "" | |
3193 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3194 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3195 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3196 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3197 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
3198 | [(set_attr "type" "fp")]) |
3199 | ||
ca7f5001 | 3200 | (define_insn "" |
cd2b37d9 RK |
3201 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3202 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3203 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3204 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3205 | "{fm|fmul} %0,%1,%2" |
0780f386 | 3206 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 3207 | |
ca7f5001 RK |
3208 | (define_expand "divsf3" |
3209 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3210 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
3211 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 3212 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
3213 | "") |
3214 | ||
3215 | (define_insn "" | |
cd2b37d9 RK |
3216 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3217 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
3218 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3219 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3220 | "fdivs %0,%1,%2" |
ca7f5001 RK |
3221 | [(set_attr "type" "sdiv")]) |
3222 | ||
3223 | (define_insn "" | |
3224 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3225 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
3226 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3227 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3228 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 3229 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
3230 | |
3231 | (define_insn "" | |
cd2b37d9 RK |
3232 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3233 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3234 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3235 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 3236 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3237 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
3238 | [(set_attr "type" "fp")]) |
3239 | ||
3240 | (define_insn "" | |
3241 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3242 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3243 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3244 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 3245 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3246 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 3247 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3248 | |
3249 | (define_insn "" | |
cd2b37d9 RK |
3250 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3251 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3252 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3253 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 3254 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3255 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
3256 | [(set_attr "type" "fp")]) |
3257 | ||
3258 | (define_insn "" | |
3259 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3260 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3261 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3262 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 3263 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3264 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 3265 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3266 | |
3267 | (define_insn "" | |
cd2b37d9 RK |
3268 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3269 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3270 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3271 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 3272 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3273 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
3274 | [(set_attr "type" "fp")]) |
3275 | ||
3276 | (define_insn "" | |
3277 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3278 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3279 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3280 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 3281 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3282 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 3283 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3284 | |
3285 | (define_insn "" | |
cd2b37d9 RK |
3286 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3287 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3288 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3289 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 3290 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3291 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
3292 | [(set_attr "type" "fp")]) |
3293 | ||
3294 | (define_insn "" | |
3295 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3296 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3297 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3298 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 3299 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3300 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 3301 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 3302 | |
ca7f5001 RK |
3303 | (define_expand "sqrtsf2" |
3304 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3305 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 3306 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
3307 | "") |
3308 | ||
3309 | (define_insn "" | |
3310 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3311 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3312 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT" |
ca7f5001 RK |
3313 | "fsqrts %0,%1" |
3314 | [(set_attr "type" "ssqrt")]) | |
3315 | ||
3316 | (define_insn "" | |
3317 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3318 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3319 | "TARGET_POWER2 && TARGET_HARD_FLOAT" |
ca7f5001 RK |
3320 | "fsqrt %0,%1" |
3321 | [(set_attr "type" "dsqrt")]) | |
3322 | ||
94d7001a RK |
3323 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
3324 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
3325 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
3326 | ;; combine. |
3327 | (define_expand "maxsf3" | |
3328 | [(set (match_dup 3) | |
3329 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
3330 | (match_operand:SF 2 "gpc_reg_operand" ""))) | |
3331 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
3332 | (if_then_else:SF (ge (match_dup 3) | |
3333 | (const_int 0)) | |
3334 | (match_dup 1) | |
3335 | (match_dup 2)))] | |
d14a6d05 | 3336 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3337 | " |
3338 | { operands[3] = gen_reg_rtx (SFmode); }") | |
2f607b94 | 3339 | |
8e871c05 RK |
3340 | (define_split |
3341 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3342 | (smax:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
f63184ac | 3343 | (match_operand:SF 2 "gpc_reg_operand" ""))) |
8e871c05 | 3344 | (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 3345 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3346 | [(set (match_dup 3) |
3347 | (minus:SF (match_dup 1) (match_dup 2))) | |
a81bd72f | 3348 | (set (match_dup 0) |
8e871c05 RK |
3349 | (if_then_else:SF (ge (match_dup 3) |
3350 | (const_int 0)) | |
3351 | (match_dup 1) | |
3352 | (match_dup 2)))] | |
3353 | "") | |
2f607b94 | 3354 | |
8e871c05 RK |
3355 | (define_expand "minsf3" |
3356 | [(set (match_dup 3) | |
3357 | (minus:SF (match_operand:SF 2 "gpc_reg_operand" "") | |
3358 | (match_operand:SF 1 "gpc_reg_operand" ""))) | |
3359 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
3360 | (if_then_else:SF (ge (match_dup 3) | |
3361 | (const_int 0)) | |
3362 | (match_dup 1) | |
3363 | (match_dup 2)))] | |
d14a6d05 | 3364 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3365 | " |
3366 | { operands[3] = gen_reg_rtx (SFmode); }") | |
2f607b94 | 3367 | |
8e871c05 RK |
3368 | (define_split |
3369 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3370 | (smin:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
f63184ac | 3371 | (match_operand:SF 2 "gpc_reg_operand" ""))) |
8e871c05 | 3372 | (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 3373 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3374 | [(set (match_dup 3) |
3375 | (minus:SF (match_dup 2) (match_dup 1))) | |
a81bd72f | 3376 | (set (match_dup 0) |
8e871c05 RK |
3377 | (if_then_else:SF (ge (match_dup 3) |
3378 | (const_int 0)) | |
3379 | (match_dup 1) | |
3380 | (match_dup 2)))] | |
3381 | "") | |
2f607b94 | 3382 | |
94d7001a RK |
3383 | (define_expand "movsfcc" |
3384 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3385 | (if_then_else:SF (match_operand 1 "comparison_operator" "") | |
3386 | (match_operand:SF 2 "gpc_reg_operand" "f") | |
3387 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3388 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
3389 | " |
3390 | { | |
3391 | rtx temp, op0, op1; | |
3392 | enum rtx_code code = GET_CODE (operands[1]); | |
3393 | if (! rs6000_compare_fp_p) | |
3394 | FAIL; | |
3395 | switch (code) | |
3396 | { | |
3397 | case GE: case EQ: case NE: | |
3398 | op0 = rs6000_compare_op0; | |
3399 | op1 = rs6000_compare_op1; | |
3400 | break; | |
3401 | case GT: | |
3402 | op0 = rs6000_compare_op1; | |
3403 | op1 = rs6000_compare_op0; | |
3404 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
3405 | break; | |
3406 | case LE: | |
3407 | op0 = rs6000_compare_op1; | |
3408 | op1 = rs6000_compare_op0; | |
3409 | break; | |
3410 | case LT: | |
3411 | op0 = rs6000_compare_op0; | |
3412 | op1 = rs6000_compare_op1; | |
3413 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
3414 | break; | |
3415 | default: | |
3416 | FAIL; | |
3417 | } | |
3418 | if (GET_MODE (rs6000_compare_op0) == DFmode) | |
3419 | { | |
3420 | temp = gen_reg_rtx (DFmode); | |
3421 | emit_insn (gen_subdf3 (temp, op0, op1)); | |
3422 | emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3])); | |
3423 | if (code == EQ) | |
3424 | { | |
3425 | emit_insn (gen_negdf2 (temp, temp)); | |
3426 | emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3])); | |
3427 | } | |
a6c2a102 | 3428 | else if (code == NE) |
94d7001a RK |
3429 | { |
3430 | emit_insn (gen_negdf2 (temp, temp)); | |
3431 | emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0])); | |
3432 | } | |
3433 | } | |
3434 | else | |
3435 | { | |
3436 | temp = gen_reg_rtx (SFmode); | |
3437 | emit_insn (gen_subsf3 (temp, op0, op1)); | |
3438 | emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3])); | |
3439 | if (code == EQ) | |
3440 | { | |
3441 | emit_insn (gen_negsf2 (temp, temp)); | |
3442 | emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3])); | |
3443 | } | |
a6c2a102 | 3444 | else if (code == NE) |
94d7001a RK |
3445 | { |
3446 | emit_insn (gen_negsf2 (temp, temp)); | |
3447 | emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0])); | |
3448 | } | |
3449 | } | |
3450 | DONE; | |
3451 | }") | |
d56d506a | 3452 | |
94d7001a | 3453 | (define_insn "fselsfsf4" |
8e871c05 RK |
3454 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3455 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
3456 | (const_int 0)) | |
3457 | (match_operand:SF 2 "gpc_reg_operand" "f") | |
3458 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3459 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3460 | "fsel %0,%1,%2,%3" |
3461 | [(set_attr "type" "fp")]) | |
2f607b94 | 3462 | |
94d7001a RK |
3463 | (define_insn "fseldfsf4" |
3464 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3465 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
3466 | (const_int 0)) | |
3467 | (match_operand:SF 2 "gpc_reg_operand" "f") | |
3468 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3469 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
3470 | "fsel %0,%1,%2,%3" |
3471 | [(set_attr "type" "fp")]) | |
d56d506a | 3472 | |
1fd4e8c1 | 3473 | (define_insn "negdf2" |
cd2b37d9 RK |
3474 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3475 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3476 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3477 | "fneg %0,%1" |
3478 | [(set_attr "type" "fp")]) | |
3479 | ||
3480 | (define_insn "absdf2" | |
cd2b37d9 RK |
3481 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3482 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3483 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3484 | "fabs %0,%1" |
3485 | [(set_attr "type" "fp")]) | |
3486 | ||
3487 | (define_insn "" | |
cd2b37d9 RK |
3488 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3489 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 3490 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3491 | "fnabs %0,%1" |
3492 | [(set_attr "type" "fp")]) | |
3493 | ||
3494 | (define_insn "adddf3" | |
cd2b37d9 RK |
3495 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3496 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3497 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3498 | "TARGET_HARD_FLOAT" |
ca7f5001 | 3499 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
3500 | [(set_attr "type" "fp")]) |
3501 | ||
3502 | (define_insn "subdf3" | |
cd2b37d9 RK |
3503 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3504 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
3505 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3506 | "TARGET_HARD_FLOAT" |
ca7f5001 | 3507 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
3508 | [(set_attr "type" "fp")]) |
3509 | ||
3510 | (define_insn "muldf3" | |
cd2b37d9 RK |
3511 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3512 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3513 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3514 | "TARGET_HARD_FLOAT" |
ca7f5001 | 3515 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 3516 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3517 | |
3518 | (define_insn "divdf3" | |
cd2b37d9 RK |
3519 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3520 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
3521 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3522 | "TARGET_HARD_FLOAT" |
ca7f5001 | 3523 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 3524 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
3525 | |
3526 | (define_insn "" | |
cd2b37d9 RK |
3527 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3528 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3529 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
3530 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 3531 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 3532 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 3533 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3534 | |
3535 | (define_insn "" | |
cd2b37d9 RK |
3536 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3537 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3538 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
3539 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 3540 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 3541 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 3542 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3543 | |
3544 | (define_insn "" | |
cd2b37d9 RK |
3545 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3546 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3547 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
3548 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 3549 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 3550 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 3551 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3552 | |
3553 | (define_insn "" | |
cd2b37d9 RK |
3554 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3555 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3556 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
3557 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 3558 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 3559 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 3560 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
3561 | |
3562 | (define_insn "sqrtdf2" | |
3563 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
3564 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3565 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
3566 | "fsqrt %0,%1" |
3567 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 3568 | |
94d7001a RK |
3569 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
3570 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
3571 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 | 3572 | ;; combine. |
b77dfefc | 3573 | |
8e871c05 RK |
3574 | (define_expand "maxdf3" |
3575 | [(set (match_dup 3) | |
3576 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
3577 | (match_operand:DF 2 "gpc_reg_operand" ""))) | |
3578 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
3579 | (if_then_else:DF (ge (match_dup 3) | |
3580 | (const_int 0)) | |
3581 | (match_dup 1) | |
3582 | (match_dup 2)))] | |
d14a6d05 | 3583 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3584 | " |
3585 | { operands[3] = gen_reg_rtx (DFmode); }") | |
b77dfefc | 3586 | |
8e871c05 RK |
3587 | (define_split |
3588 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
3589 | (smax:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
f63184ac | 3590 | (match_operand:DF 2 "gpc_reg_operand" ""))) |
8e871c05 | 3591 | (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 3592 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3593 | [(set (match_dup 3) |
3594 | (minus:DF (match_dup 1) (match_dup 2))) | |
a81bd72f | 3595 | (set (match_dup 0) |
8e871c05 RK |
3596 | (if_then_else:DF (ge (match_dup 3) |
3597 | (const_int 0)) | |
3598 | (match_dup 1) | |
3599 | (match_dup 2)))] | |
3600 | "") | |
b77dfefc | 3601 | |
8e871c05 RK |
3602 | (define_expand "mindf3" |
3603 | [(set (match_dup 3) | |
3604 | (minus:DF (match_operand:DF 2 "gpc_reg_operand" "") | |
3605 | (match_operand:DF 1 "gpc_reg_operand" ""))) | |
3606 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
3607 | (if_then_else:DF (ge (match_dup 3) | |
3608 | (const_int 0)) | |
3609 | (match_dup 1) | |
3610 | (match_dup 2)))] | |
d14a6d05 | 3611 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3612 | " |
3613 | { operands[3] = gen_reg_rtx (DFmode); }") | |
b77dfefc | 3614 | |
8e871c05 RK |
3615 | (define_split |
3616 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
3617 | (smin:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
f63184ac | 3618 | (match_operand:DF 2 "gpc_reg_operand" ""))) |
8e871c05 | 3619 | (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 3620 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3621 | [(set (match_dup 3) |
3622 | (minus:DF (match_dup 2) (match_dup 1))) | |
a81bd72f | 3623 | (set (match_dup 0) |
8e871c05 RK |
3624 | (if_then_else:DF (ge (match_dup 3) |
3625 | (const_int 0)) | |
3626 | (match_dup 1) | |
3627 | (match_dup 2)))] | |
3628 | "") | |
b77dfefc | 3629 | |
94d7001a RK |
3630 | (define_expand "movdfcc" |
3631 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
3632 | (if_then_else:DF (match_operand 1 "comparison_operator" "") | |
3633 | (match_operand:DF 2 "gpc_reg_operand" "f") | |
3634 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3635 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
3636 | " |
3637 | { | |
3638 | rtx temp, op0, op1; | |
3639 | enum rtx_code code = GET_CODE (operands[1]); | |
3640 | if (! rs6000_compare_fp_p) | |
3641 | FAIL; | |
3642 | switch (code) | |
3643 | { | |
3644 | case GE: case EQ: case NE: | |
3645 | op0 = rs6000_compare_op0; | |
3646 | op1 = rs6000_compare_op1; | |
3647 | break; | |
3648 | case GT: | |
3649 | op0 = rs6000_compare_op1; | |
3650 | op1 = rs6000_compare_op0; | |
3651 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
3652 | break; | |
3653 | case LE: | |
3654 | op0 = rs6000_compare_op1; | |
3655 | op1 = rs6000_compare_op0; | |
3656 | break; | |
3657 | case LT: | |
3658 | op0 = rs6000_compare_op0; | |
3659 | op1 = rs6000_compare_op1; | |
3660 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
3661 | break; | |
3662 | default: | |
3663 | FAIL; | |
3664 | } | |
3665 | if (GET_MODE (rs6000_compare_op0) == DFmode) | |
3666 | { | |
3667 | temp = gen_reg_rtx (DFmode); | |
3668 | emit_insn (gen_subdf3 (temp, op0, op1)); | |
3669 | emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3])); | |
3670 | if (code == EQ) | |
3671 | { | |
3672 | emit_insn (gen_negdf2 (temp, temp)); | |
3673 | emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3])); | |
3674 | } | |
a6c2a102 | 3675 | else if (code == NE) |
94d7001a RK |
3676 | { |
3677 | emit_insn (gen_negdf2 (temp, temp)); | |
3678 | emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0])); | |
3679 | } | |
3680 | } | |
3681 | else | |
3682 | { | |
3683 | temp = gen_reg_rtx (SFmode); | |
3684 | emit_insn (gen_subsf3 (temp, op0, op1)); | |
3685 | emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3])); | |
3686 | if (code == EQ) | |
3687 | { | |
3688 | emit_insn (gen_negsf2 (temp, temp)); | |
3689 | emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3])); | |
3690 | } | |
a6c2a102 | 3691 | else if (code == NE) |
94d7001a RK |
3692 | { |
3693 | emit_insn (gen_negsf2 (temp, temp)); | |
3694 | emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0])); | |
3695 | } | |
3696 | } | |
3697 | DONE; | |
3698 | }") | |
d56d506a | 3699 | |
94d7001a | 3700 | (define_insn "fseldfdf4" |
8e871c05 RK |
3701 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3702 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
3703 | (const_int 0)) | |
3704 | (match_operand:DF 2 "gpc_reg_operand" "f") | |
3705 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3706 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3707 | "fsel %0,%1,%2,%3" |
3708 | [(set_attr "type" "fp")]) | |
d56d506a | 3709 | |
94d7001a RK |
3710 | (define_insn "fselsfdf4" |
3711 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
3712 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
3713 | (const_int 0)) | |
3714 | (match_operand:DF 2 "gpc_reg_operand" "f") | |
3715 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3716 | "TARGET_PPC_GFXOPT" | |
3717 | "fsel %0,%1,%2,%3" | |
3718 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
3719 | \f |
3720 | ;; Conversions to and from floating-point. | |
802a0058 | 3721 | |
1fd4e8c1 | 3722 | (define_expand "floatsidf2" |
802a0058 MM |
3723 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
3724 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3725 | (use (match_dup 2)) | |
3726 | (use (match_dup 3)) | |
208c89ce | 3727 | (clobber (match_dup 4)) |
a7df97e6 | 3728 | (clobber (match_dup 5)) |
802a0058 | 3729 | (clobber (reg:DF 76))])] |
a260abc9 | 3730 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3731 | " |
3732 | { | |
802a0058 MM |
3733 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
3734 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); | |
208c89ce | 3735 | operands[4] = gen_reg_rtx (SImode); |
a7df97e6 | 3736 | operands[5] = gen_reg_rtx (Pmode); |
1fd4e8c1 RK |
3737 | }") |
3738 | ||
802a0058 MM |
3739 | (define_insn "*floatsidf2_internal" |
3740 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
3741 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
3742 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
3743 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
208c89ce | 3744 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
a260abc9 | 3745 | (clobber (match_operand 5 "gpc_reg_operand" "=b")) |
802a0058 | 3746 | (clobber (reg:DF 76))] |
a260abc9 | 3747 | "TARGET_HARD_FLOAT" |
802a0058 | 3748 | "#" |
a7df97e6 | 3749 | [(set_attr "length" "24")]) |
802a0058 MM |
3750 | |
3751 | (define_split | |
dbe3df29 | 3752 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
3753 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
3754 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
3755 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
208c89ce | 3756 | (clobber (match_operand:SI 4 "gpc_reg_operand" "")) |
a260abc9 | 3757 | (clobber (match_operand 5 "gpc_reg_operand" "")) |
802a0058 | 3758 | (clobber (reg:DF 76))] |
a260abc9 | 3759 | "TARGET_HARD_FLOAT" |
802a0058 | 3760 | [(set (match_dup 4) |
208c89ce | 3761 | (xor:SI (match_dup 1) |
a7df97e6 MM |
3762 | (match_dup 6))) |
3763 | (set (match_dup 5) | |
3764 | (unspec [(const_int 0)] 11)) | |
3765 | (set (match_dup 7) | |
3766 | (unspec [(match_dup 4) | |
3767 | (match_dup 5)] 12)) ;; low word | |
3768 | (set (match_dup 7) | |
3769 | (unspec [(match_dup 2) | |
3770 | (match_dup 5) | |
3771 | (match_dup 7)] 13)) ;; high word | |
802a0058 | 3772 | (set (match_dup 0) |
a7df97e6 MM |
3773 | (unspec [(match_dup 7) |
3774 | (match_dup 5)] 14)) | |
802a0058 MM |
3775 | (set (match_dup 0) |
3776 | (minus:DF (match_dup 0) | |
3777 | (match_dup 3)))] | |
208c89ce MM |
3778 | " |
3779 | { | |
a7df97e6 | 3780 | operands[6] = GEN_INT (0x80000000); |
39403d82 | 3781 | operands[7] = gen_rtx_REG (DFmode, FPMEM_REGNUM); |
208c89ce | 3782 | }") |
802a0058 MM |
3783 | |
3784 | (define_expand "floatunssidf2" | |
3785 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
3786 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3787 | (use (match_dup 2)) | |
3788 | (use (match_dup 3)) | |
a7df97e6 | 3789 | (clobber (match_dup 4)) |
802a0058 | 3790 | (clobber (reg:DF 76))])] |
a260abc9 | 3791 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3792 | " |
3793 | { | |
802a0058 MM |
3794 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
3795 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode)); | |
a7df97e6 | 3796 | operands[4] = gen_reg_rtx (Pmode); |
1fd4e8c1 RK |
3797 | }") |
3798 | ||
802a0058 MM |
3799 | (define_insn "*floatunssidf2_internal" |
3800 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
3801 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
3802 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
3803 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
a260abc9 | 3804 | (clobber (match_operand 4 "gpc_reg_operand" "=b")) |
802a0058 | 3805 | (clobber (reg:DF 76))] |
a260abc9 | 3806 | "TARGET_HARD_FLOAT" |
802a0058 | 3807 | "#" |
a7df97e6 | 3808 | [(set_attr "length" "20")]) |
802a0058 MM |
3809 | |
3810 | (define_split | |
3811 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
3812 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3813 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
3814 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
955fc2e7 | 3815 | (clobber (match_operand 4 "gpc_reg_operand" "")) |
802a0058 | 3816 | (clobber (reg:DF 76))] |
a260abc9 | 3817 | "TARGET_HARD_FLOAT" |
802a0058 | 3818 | [(set (match_dup 4) |
a7df97e6 MM |
3819 | (unspec [(const_int 0)] 11)) |
3820 | (set (match_dup 5) | |
3821 | (unspec [(match_dup 1) | |
3822 | (match_dup 4)] 12)) ;; low word | |
3823 | (set (match_dup 5) | |
3824 | (unspec [(match_dup 2) | |
3825 | (match_dup 4) | |
3826 | (match_dup 5)] 13)) ;; high word | |
802a0058 | 3827 | (set (match_dup 0) |
a7df97e6 | 3828 | (unspec [(match_dup 5) |
955fc2e7 | 3829 | (match_dup 4)] 14)) |
802a0058 MM |
3830 | (set (match_dup 0) |
3831 | (minus:DF (match_dup 0) | |
3832 | (match_dup 3)))] | |
39403d82 | 3833 | "operands[5] = gen_rtx_REG (DFmode, FPMEM_REGNUM);") |
802a0058 | 3834 | |
a7df97e6 MM |
3835 | ;; Load up scratch register with base address + offset if needed |
3836 | (define_insn "*floatsidf2_loadaddr" | |
a260abc9 | 3837 | [(set (match_operand 0 "gpc_reg_operand" "=b") |
a7df97e6 MM |
3838 | (unspec [(const_int 0)] 11))] |
3839 | "TARGET_HARD_FLOAT" | |
3840 | "* | |
3841 | { | |
3842 | if (rs6000_fpmem_offset > 32760) | |
3843 | { | |
3844 | rtx xop[3]; | |
3845 | ||
3846 | xop[0] = operands[0]; | |
3847 | xop[1] = (frame_pointer_needed) ? frame_pointer_rtx : stack_pointer_rtx; | |
170e0690 | 3848 | xop[2] = GEN_INT ((rs6000_fpmem_offset >> 16) + ((rs6000_fpmem_offset & 0x8000) >> 15)); |
538bb158 | 3849 | output_asm_insn (\"{cau|addis} %0,%1,%2\", xop); |
a7df97e6 | 3850 | } |
a7df97e6 MM |
3851 | |
3852 | return \"\"; | |
3853 | }" | |
3854 | [(set_attr "length" "4")]) | |
802a0058 MM |
3855 | |
3856 | (define_insn "*floatsidf2_store1" | |
3857 | [(set (reg:DF 76) | |
3858 | (unspec [(match_operand:SI 0 "gpc_reg_operand" "r") | |
a260abc9 DE |
3859 | (match_operand 1 "gpc_reg_operand" "b")] 12))] |
3860 | "TARGET_HARD_FLOAT" | |
802a0058 | 3861 | "* |
dbe3df29 | 3862 | { |
a7df97e6 MM |
3863 | rtx indx; |
3864 | ||
3865 | if (rs6000_fpmem_offset > 32760) | |
3866 | indx = operands[1]; | |
3867 | else if (frame_pointer_needed) | |
3868 | indx = frame_pointer_rtx; | |
3869 | else | |
3870 | indx = stack_pointer_rtx; | |
3871 | ||
39403d82 DE |
3872 | operands[2] = gen_rtx_MEM (SImode, |
3873 | gen_rtx_PLUS (Pmode, | |
a7df97e6 | 3874 | indx, |
170e0690 | 3875 | GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000) |
802a0058 | 3876 | + ((WORDS_BIG_ENDIAN != 0) * 4)))); |
c283c989 | 3877 | |
a7df97e6 | 3878 | return \"{st|stw} %0,%2\"; |
802a0058 MM |
3879 | }" |
3880 | [(set_attr "type" "store")]) | |
3881 | ||
3882 | (define_insn "*floatsidf2_store2" | |
3883 | [(set (reg:DF 76) | |
3884 | (unspec [(match_operand:SI 0 "gpc_reg_operand" "r") | |
a260abc9 | 3885 | (match_operand 1 "gpc_reg_operand" "b") |
a7df97e6 | 3886 | (reg:DF 76)] 13))] |
a260abc9 | 3887 | "TARGET_HARD_FLOAT" |
802a0058 MM |
3888 | "* |
3889 | { | |
a7df97e6 MM |
3890 | rtx indx; |
3891 | ||
3892 | if (rs6000_fpmem_offset > 32760) | |
3893 | indx = operands[1]; | |
3894 | else if (frame_pointer_needed) | |
3895 | indx = frame_pointer_rtx; | |
3896 | else | |
3897 | indx = stack_pointer_rtx; | |
3898 | ||
39403d82 DE |
3899 | operands[2] = gen_rtx_MEM (SImode, |
3900 | gen_rtx_PLUS (Pmode, | |
a7df97e6 | 3901 | indx, |
170e0690 | 3902 | GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000) |
802a0058 MM |
3903 | + ((WORDS_BIG_ENDIAN == 0) * 4)))); |
3904 | ||
a7df97e6 | 3905 | return \"{st|stw} %0,%2\"; |
802a0058 MM |
3906 | }" |
3907 | [(set_attr "type" "store")]) | |
3908 | ||
3909 | (define_insn "*floatsidf2_load" | |
3910 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
3911 | (unspec [(reg:DF 76) | |
a260abc9 DE |
3912 | (match_operand 1 "gpc_reg_operand" "b")] 14))] |
3913 | "TARGET_HARD_FLOAT" | |
802a0058 MM |
3914 | "* |
3915 | { | |
a7df97e6 | 3916 | rtx indx; |
f6968f59 | 3917 | HOST_WIDE_INT offset = rs6000_fpmem_offset; |
a7df97e6 MM |
3918 | |
3919 | if (rs6000_fpmem_offset > 32760) | |
f6968f59 MM |
3920 | { |
3921 | indx = operands[1]; | |
170e0690 | 3922 | offset = (((offset & 0xffff) ^ 0x8000) - 0x8000); |
f6968f59 | 3923 | } |
a7df97e6 MM |
3924 | else if (frame_pointer_needed) |
3925 | indx = frame_pointer_rtx; | |
3926 | else | |
3927 | indx = stack_pointer_rtx; | |
3928 | ||
39403d82 DE |
3929 | operands[2] = gen_rtx_MEM (SImode, |
3930 | gen_rtx_PLUS (Pmode, indx, GEN_INT (offset))); | |
802a0058 | 3931 | |
a7df97e6 | 3932 | return \"lfd %0,%2\"; |
802a0058 MM |
3933 | }" |
3934 | [(set_attr "type" "fpload")]) | |
1fd4e8c1 | 3935 | |
1fd4e8c1 | 3936 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
3937 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
3938 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
3939 | (clobber (match_dup 2)) | |
a7df97e6 MM |
3940 | (clobber (match_dup 3)) |
3941 | (clobber (match_dup 4))])] | |
d14a6d05 | 3942 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3943 | " |
3944 | { | |
802a0058 | 3945 | if (!TARGET_POWER2 && !TARGET_POWERPC) |
8ffd9c51 RK |
3946 | { |
3947 | emit_insn (gen_trunc_call (operands[0], operands[1], | |
39403d82 | 3948 | gen_rtx_SYMBOL_REF (Pmode, RS6000_ITRUNC))); |
8ffd9c51 RK |
3949 | DONE; |
3950 | } | |
802a0058 MM |
3951 | |
3952 | operands[2] = gen_reg_rtx (DImode); | |
a7df97e6 | 3953 | operands[3] = gen_reg_rtx (Pmode); |
39403d82 | 3954 | operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM); |
1fd4e8c1 RK |
3955 | }") |
3956 | ||
802a0058 MM |
3957 | (define_insn "*fix_truncdfsi2_internal" |
3958 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3959 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
3960 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) | |
a260abc9 | 3961 | (clobber (match_operand 3 "gpc_reg_operand" "=b")) |
802a0058 MM |
3962 | (clobber (reg:DI 76))] |
3963 | "TARGET_HARD_FLOAT" | |
3964 | "#" | |
3965 | [(set_attr "length" "12")]) | |
3966 | ||
3967 | (define_split | |
3968 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
3969 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
3970 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) | |
a260abc9 | 3971 | (clobber (match_operand 3 "gpc_reg_operand" "")) |
802a0058 MM |
3972 | (clobber (reg:DI 76))] |
3973 | "TARGET_HARD_FLOAT" | |
3974 | [(set (match_dup 2) | |
3975 | (sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))) | |
3976 | (set (match_dup 3) | |
a7df97e6 MM |
3977 | (unspec [(const_int 0)] 11)) |
3978 | (set (match_dup 4) | |
802a0058 | 3979 | (unspec [(match_dup 2) |
a7df97e6 | 3980 | (match_dup 3)] 15)) |
802a0058 | 3981 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
a7df97e6 MM |
3982 | (unspec [(match_dup 4) |
3983 | (match_dup 3)] 16))] | |
39403d82 | 3984 | "operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM);") |
802a0058 | 3985 | |
802a0058 MM |
3986 | (define_insn "*fix_truncdfsi2_store" |
3987 | [(set (reg:DI 76) | |
3988 | (unspec [(match_operand:DI 0 "gpc_reg_operand" "f") | |
a260abc9 | 3989 | (match_operand 1 "gpc_reg_operand" "b")] 15))] |
802a0058 MM |
3990 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
3991 | "* | |
3992 | { | |
a7df97e6 MM |
3993 | rtx indx; |
3994 | ||
3995 | if (rs6000_fpmem_offset > 32760) | |
3996 | indx = operands[1]; | |
3997 | else if (frame_pointer_needed) | |
3998 | indx = frame_pointer_rtx; | |
3999 | else | |
4000 | indx = stack_pointer_rtx; | |
4001 | ||
39403d82 DE |
4002 | operands[2] = gen_rtx_MEM (DFmode, |
4003 | gen_rtx_PLUS (Pmode, | |
a7df97e6 | 4004 | indx, |
eaf1bcf1 MM |
4005 | GEN_INT ((((rs6000_fpmem_offset & 0xffff) |
4006 | ^ 0x8000) - 0x8000)))); | |
802a0058 | 4007 | |
1427100a | 4008 | return \"stfd %0,%2\"; |
802a0058 MM |
4009 | }" |
4010 | [(set_attr "type" "fpstore")]) | |
4011 | ||
4012 | (define_insn "*fix_truncdfsi2_load" | |
4013 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4014 | (unspec [(reg:DI 76) | |
a260abc9 | 4015 | (match_operand 1 "gpc_reg_operand" "b")] 16))] |
802a0058 MM |
4016 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
4017 | "* | |
4018 | { | |
a7df97e6 MM |
4019 | rtx indx; |
4020 | ||
4021 | if (rs6000_fpmem_offset > 32760) | |
4022 | indx = operands[1]; | |
4023 | else if (frame_pointer_needed) | |
4024 | indx = frame_pointer_rtx; | |
4025 | else | |
4026 | indx = stack_pointer_rtx; | |
4027 | ||
39403d82 DE |
4028 | operands[2] = gen_rtx_MEM (DFmode, |
4029 | gen_rtx_PLUS (Pmode, | |
a7df97e6 | 4030 | indx, |
170e0690 | 4031 | GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000) |
a7df97e6 | 4032 | + ((WORDS_BIG_ENDIAN) ? 4 : 0)))); |
802a0058 | 4033 | |
a7df97e6 | 4034 | return \"{l|lwz} %0,%2\"; |
802a0058 MM |
4035 | }" |
4036 | [(set_attr "type" "load")]) | |
4037 | ||
1fd4e8c1 | 4038 | (define_expand "fixuns_truncdfsi2" |
cd2b37d9 | 4039 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
b542afe9 | 4040 | (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] |
d14a6d05 | 4041 | "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4042 | " |
4043 | { | |
4044 | emit_insn (gen_trunc_call (operands[0], operands[1], | |
39403d82 | 4045 | gen_rtx_SYMBOL_REF (Pmode, RS6000_UITRUNC))); |
1fd4e8c1 RK |
4046 | DONE; |
4047 | }") | |
4048 | ||
1fd4e8c1 RK |
4049 | (define_expand "trunc_call" |
4050 | [(parallel [(set (match_operand:SI 0 "" "") | |
b542afe9 | 4051 | (fix:SI (match_operand:DF 1 "" ""))) |
1fd4e8c1 | 4052 | (use (match_operand:SI 2 "" ""))])] |
d14a6d05 | 4053 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4054 | " |
4055 | { | |
4056 | rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]); | |
4057 | rtx first = XVECEXP (insns, 0, 0); | |
4058 | rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1); | |
4059 | ||
39403d82 | 4060 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, |
1fd4e8c1 | 4061 | REG_NOTES (first)); |
39403d82 | 4062 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last)); |
1fd4e8c1 RK |
4063 | |
4064 | emit_insn (insns); | |
4065 | DONE; | |
4066 | }") | |
4067 | ||
4068 | (define_expand "trunc_call_rtl" | |
cd2b37d9 | 4069 | [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" "")) |
1fd4e8c1 RK |
4070 | (use (reg:DF 33)) |
4071 | (parallel [(set (reg:SI 3) | |
4072 | (call (mem:SI (match_operand 2 "" "")) (const_int 0))) | |
4697a36c | 4073 | (use (const_int 0)) |
1fd4e8c1 | 4074 | (clobber (scratch:SI))]) |
cd2b37d9 | 4075 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 4076 | (reg:SI 3))] |
d14a6d05 | 4077 | "TARGET_HARD_FLOAT" |
1fd4e8c1 | 4078 | " |
7e69e155 | 4079 | { |
1fd4e8c1 RK |
4080 | rs6000_trunc_used = 1; |
4081 | }") | |
a473029f | 4082 | |
a260abc9 DE |
4083 | (define_insn "*fctiwz" |
4084 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
4085 | (sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
4086 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" | |
4087 | "{fcirz|fctiwz} %0,%1" | |
4088 | [(set_attr "type" "fp")]) | |
4089 | ||
a473029f RK |
4090 | (define_insn "floatdidf2" |
4091 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4092 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4093 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
4094 | "fcfid %0,%1" |
4095 | [(set_attr "type" "fp")]) | |
4096 | ||
4097 | (define_insn "fix_truncdfdi2" | |
4098 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
4099 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4100 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
4101 | "fctidz %0,%1" |
4102 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4103 | \f |
4104 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
4105 | ;; of instructions. The & constraints are to prevent the register |
4106 | ;; allocator from allocating registers that overlap with the inputs | |
4107 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 4108 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 4109 | |
266eb58a | 4110 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
4111 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
4112 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
4113 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 4114 | "! TARGET_POWERPC64" |
0f645302 MM |
4115 | "* |
4116 | { | |
4117 | if (WORDS_BIG_ENDIAN) | |
4118 | return (GET_CODE (operands[2])) != CONST_INT | |
4119 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
4120 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
4121 | else | |
4122 | return (GET_CODE (operands[2])) != CONST_INT | |
4123 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
4124 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
4125 | }" | |
b19003d8 | 4126 | [(set_attr "length" "8")]) |
1fd4e8c1 | 4127 | |
266eb58a | 4128 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
4129 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
4130 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
4131 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 4132 | "! TARGET_POWERPC64" |
5502823b RK |
4133 | "* |
4134 | { | |
0f645302 MM |
4135 | if (WORDS_BIG_ENDIAN) |
4136 | return (GET_CODE (operands[1]) != CONST_INT) | |
4137 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
4138 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
4139 | else | |
4140 | return (GET_CODE (operands[1]) != CONST_INT) | |
4141 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
4142 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 4143 | }" |
ca7f5001 RK |
4144 | [(set_attr "length" "8")]) |
4145 | ||
266eb58a | 4146 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
4147 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
4148 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 4149 | "! TARGET_POWERPC64" |
5502823b RK |
4150 | "* |
4151 | { | |
4152 | return (WORDS_BIG_ENDIAN) | |
4153 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
4154 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
4155 | }" | |
ca7f5001 RK |
4156 | [(set_attr "length" "8")]) |
4157 | ||
8ffd9c51 RK |
4158 | (define_expand "mulsidi3" |
4159 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4160 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
4161 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 4162 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
4163 | " |
4164 | { | |
4165 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
4166 | { | |
39403d82 DE |
4167 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
4168 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 4169 | emit_insn (gen_mull_call ()); |
cf27b467 | 4170 | if (WORDS_BIG_ENDIAN) |
39403d82 | 4171 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
4172 | else |
4173 | { | |
4174 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 4175 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 4176 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 4177 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 4178 | } |
8ffd9c51 RK |
4179 | DONE; |
4180 | } | |
4181 | else if (TARGET_POWER) | |
4182 | { | |
4183 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
4184 | DONE; | |
4185 | } | |
4186 | }") | |
deb9225a | 4187 | |
8ffd9c51 | 4188 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 4189 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 4190 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 4191 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 4192 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 4193 | "TARGET_POWER" |
b19003d8 | 4194 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
4195 | [(set_attr "type" "imul") |
4196 | (set_attr "length" "8")]) | |
deb9225a | 4197 | |
f192bf8b | 4198 | (define_insn "*mulsidi3_no_mq" |
425c176f | 4199 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
4200 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
4201 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 4202 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
4203 | "* |
4204 | { | |
4205 | return (WORDS_BIG_ENDIAN) | |
4206 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
4207 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
4208 | }" | |
8ffd9c51 RK |
4209 | [(set_attr "type" "imul") |
4210 | (set_attr "length" "8")]) | |
deb9225a | 4211 | |
ebedb4dd MM |
4212 | (define_split |
4213 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4214 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
4215 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 4216 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
4217 | [(set (match_dup 3) |
4218 | (truncate:SI | |
4219 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
4220 | (sign_extend:DI (match_dup 2))) | |
4221 | (const_int 32)))) | |
4222 | (set (match_dup 4) | |
4223 | (mult:SI (match_dup 1) | |
4224 | (match_dup 2)))] | |
4225 | " | |
4226 | { | |
4227 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4228 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
4229 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
4230 | }") | |
4231 | ||
f192bf8b DE |
4232 | (define_expand "umulsidi3" |
4233 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4234 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
4235 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
4236 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
4237 | " | |
4238 | { | |
4239 | if (TARGET_POWER) | |
4240 | { | |
4241 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
4242 | DONE; | |
4243 | } | |
4244 | }") | |
4245 | ||
4246 | (define_insn "umulsidi3_mq" | |
4247 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
4248 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4249 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
4250 | (clobber (match_scratch:SI 3 "=q"))] | |
4251 | "TARGET_POWERPC && TARGET_POWER" | |
4252 | "* | |
4253 | { | |
4254 | return (WORDS_BIG_ENDIAN) | |
4255 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
4256 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
4257 | }" | |
4258 | [(set_attr "type" "imul") | |
4259 | (set_attr "length" "8")]) | |
4260 | ||
4261 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
4262 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
4263 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4264 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 4265 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
4266 | "* |
4267 | { | |
4268 | return (WORDS_BIG_ENDIAN) | |
4269 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
4270 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
4271 | }" | |
4272 | [(set_attr "type" "imul") | |
4273 | (set_attr "length" "8")]) | |
4274 | ||
ebedb4dd MM |
4275 | (define_split |
4276 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4277 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
4278 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 4279 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
4280 | [(set (match_dup 3) |
4281 | (truncate:SI | |
4282 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
4283 | (zero_extend:DI (match_dup 2))) | |
4284 | (const_int 32)))) | |
4285 | (set (match_dup 4) | |
4286 | (mult:SI (match_dup 1) | |
4287 | (match_dup 2)))] | |
4288 | " | |
4289 | { | |
4290 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4291 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
4292 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
4293 | }") | |
4294 | ||
8ffd9c51 RK |
4295 | (define_expand "smulsi3_highpart" |
4296 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4297 | (truncate:SI | |
4298 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
4299 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4300 | (sign_extend:DI | |
4301 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
4302 | (const_int 32))))] | |
4303 | "" | |
4304 | " | |
4305 | { | |
4306 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
4307 | { | |
39403d82 DE |
4308 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
4309 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 4310 | emit_insn (gen_mulh_call ()); |
39403d82 | 4311 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
4312 | DONE; |
4313 | } | |
4314 | else if (TARGET_POWER) | |
4315 | { | |
4316 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
4317 | DONE; | |
4318 | } | |
4319 | }") | |
deb9225a | 4320 | |
8ffd9c51 RK |
4321 | (define_insn "smulsi3_highpart_mq" |
4322 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4323 | (truncate:SI | |
fada905b MM |
4324 | (lshiftrt:DI (mult:DI (sign_extend:DI |
4325 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4326 | (sign_extend:DI | |
4327 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
4328 | (const_int 32)))) |
4329 | (clobber (match_scratch:SI 3 "=q"))] | |
4330 | "TARGET_POWER" | |
4331 | "mul %0,%1,%2" | |
4332 | [(set_attr "type" "imul")]) | |
deb9225a | 4333 | |
f192bf8b | 4334 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
4335 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4336 | (truncate:SI | |
fada905b MM |
4337 | (lshiftrt:DI (mult:DI (sign_extend:DI |
4338 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4339 | (sign_extend:DI | |
4340 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 4341 | (const_int 32))))] |
f192bf8b | 4342 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
4343 | "mulhw %0,%1,%2" |
4344 | [(set_attr "type" "imul")]) | |
deb9225a | 4345 | |
f192bf8b DE |
4346 | (define_expand "umulsi3_highpart" |
4347 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4348 | (truncate:SI | |
4349 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
4350 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
4351 | (zero_extend:DI | |
4352 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
4353 | (const_int 32))))] | |
4354 | "TARGET_POWERPC" | |
4355 | " | |
4356 | { | |
4357 | if (TARGET_POWER) | |
4358 | { | |
4359 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
4360 | DONE; | |
4361 | } | |
4362 | }") | |
4363 | ||
4364 | (define_insn "umulsi3_highpart_mq" | |
4365 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4366 | (truncate:SI | |
4367 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
4368 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4369 | (zero_extend:DI | |
4370 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
4371 | (const_int 32)))) | |
4372 | (clobber (match_scratch:SI 3 "=q"))] | |
4373 | "TARGET_POWERPC && TARGET_POWER" | |
4374 | "mulhwu %0,%1,%2" | |
4375 | [(set_attr "type" "imul")]) | |
4376 | ||
4377 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
4378 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4379 | (truncate:SI | |
4380 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
4381 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4382 | (zero_extend:DI | |
4383 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
4384 | (const_int 32))))] | |
f192bf8b | 4385 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
4386 | "mulhwu %0,%1,%2" |
4387 | [(set_attr "type" "imul")]) | |
4388 | ||
4389 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
4390 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
4391 | ;; why we have the strange constraints below. | |
4392 | (define_insn "ashldi3_power" | |
4393 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
4394 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
4395 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
4396 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
4397 | "TARGET_POWER" | |
4398 | "@ | |
4399 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
4400 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
4401 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
4402 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
4403 | [(set_attr "length" "8")]) | |
4404 | ||
4405 | (define_insn "lshrdi3_power" | |
47ad8c61 | 4406 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
4407 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
4408 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
4409 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
4410 | "TARGET_POWER" | |
4411 | "@ | |
47ad8c61 | 4412 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
4413 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
4414 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
4415 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
4416 | [(set_attr "length" "8")]) | |
4417 | ||
4418 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
4419 | ;; just handle shifts by constants. | |
4420 | (define_insn "ashrdi3_power" | |
7093ddee | 4421 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
4422 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
4423 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
4424 | (clobber (match_scratch:SI 3 "=X,q"))] | |
4425 | "TARGET_POWER" | |
4426 | "@ | |
4427 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
4428 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
4429 | [(set_attr "length" "8")]) | |
4430 | \f | |
4431 | ;; PowerPC64 DImode operations. | |
4432 | ||
4433 | (define_expand "adddi3" | |
4434 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4435 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
a260abc9 | 4436 | (match_operand:DI 2 "reg_or_cint_operand" "")))] |
266eb58a DE |
4437 | "" |
4438 | " | |
4439 | { | |
a260abc9 DE |
4440 | if (! TARGET_POWERPC64) |
4441 | { | |
4442 | if (non_short_cint_operand (operands[2], DImode)) | |
4443 | FAIL; | |
4444 | } | |
4445 | else | |
4446 | if (GET_CODE (operands[2]) == CONST_INT | |
4447 | && !add_operand (operands[2], DImode)) | |
4448 | { | |
4449 | rtx tmp = ((reload_in_progress || reload_completed | |
4450 | || rtx_equal_p (operands[0], operands[1])) | |
4451 | ? operands[0] : gen_reg_rtx (DImode)); | |
4452 | ||
4453 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; | |
4454 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
4455 | ||
4456 | if (low & 0x8000) | |
4457 | high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16; | |
4458 | ||
4459 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (high))); | |
4460 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); | |
4461 | DONE; | |
4462 | } | |
266eb58a DE |
4463 | }") |
4464 | ||
4465 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
4466 | ;; allowing register zero as source. | |
4467 | ||
a260abc9 | 4468 | (define_insn "*adddi3_internal1" |
266eb58a DE |
4469 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
4470 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
4471 | (match_operand:DI 2 "add_operand" "r,I,I,J")))] | |
4472 | "TARGET_POWERPC64" | |
4473 | "@ | |
4474 | add %0,%1,%2 | |
4475 | addi %0,%1,%2 | |
4476 | addic %0,%1,%2 | |
802a0058 | 4477 | addis %0,%1,%v2") |
266eb58a | 4478 | |
a260abc9 | 4479 | (define_insn "*adddi3_internal2" |
29ae5b89 JL |
4480 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
4481 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
4482 | (match_operand:DI 2 "reg_or_short_operand" "r,I")) | |
266eb58a | 4483 | (const_int 0))) |
29ae5b89 | 4484 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a DE |
4485 | "TARGET_POWERPC64" |
4486 | "@ | |
4487 | add. %3,%1,%2 | |
29ae5b89 JL |
4488 | addic. %3,%1,%2" |
4489 | [(set_attr "type" "compare")]) | |
266eb58a | 4490 | |
a260abc9 | 4491 | (define_insn "*adddi3_internal3" |
29ae5b89 JL |
4492 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
4493 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
4494 | (match_operand:DI 2 "reg_or_short_operand" "r,I")) | |
266eb58a | 4495 | (const_int 0))) |
29ae5b89 | 4496 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
4497 | (plus:DI (match_dup 1) (match_dup 2)))] |
4498 | "TARGET_POWERPC64" | |
4499 | "@ | |
4500 | add. %0,%1,%2 | |
29ae5b89 JL |
4501 | addic. %0,%1,%2" |
4502 | [(set_attr "type" "compare")]) | |
266eb58a DE |
4503 | |
4504 | ;; Split an add that we can't do in one insn into two insns, each of which | |
4505 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
4506 | ;; add should be last in case the result gets used in an address. | |
4507 | ||
4508 | (define_split | |
4509 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4510 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
4511 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
4512 | "TARGET_POWERPC64" | |
4513 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
4514 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
4515 | " | |
4516 | { | |
e6ca2c17 DE |
4517 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; |
4518 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
266eb58a DE |
4519 | |
4520 | if (low & 0x8000) | |
e6ca2c17 | 4521 | high+=0x10000, low |= ((HOST_WIDE_INT) -1) << 16; |
266eb58a | 4522 | |
e6ca2c17 DE |
4523 | operands[3] = GEN_INT (high); |
4524 | operands[4] = GEN_INT (low); | |
266eb58a DE |
4525 | }") |
4526 | ||
4527 | (define_insn "one_cmpldi2" | |
4528 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4529 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
4530 | "TARGET_POWERPC64" | |
4531 | "nor %0,%1,%1") | |
4532 | ||
4533 | (define_insn "" | |
29ae5b89 JL |
4534 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
4535 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
266eb58a | 4536 | (const_int 0))) |
29ae5b89 | 4537 | (clobber (match_scratch:DI 2 "=r"))] |
266eb58a DE |
4538 | "TARGET_POWERPC64" |
4539 | "nor. %2,%1,%1" | |
29ae5b89 | 4540 | [(set_attr "type" "compare")]) |
266eb58a DE |
4541 | |
4542 | (define_insn "" | |
29ae5b89 JL |
4543 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
4544 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
266eb58a | 4545 | (const_int 0))) |
29ae5b89 | 4546 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
4547 | (not:DI (match_dup 1)))] |
4548 | "TARGET_POWERPC64" | |
d944f453 | 4549 | "nor. %0,%1,%1" |
266eb58a DE |
4550 | [(set_attr "type" "compare")]) |
4551 | ||
4552 | (define_insn "" | |
4553 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
4554 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
4555 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
4556 | "TARGET_POWERPC64" | |
4557 | "@ | |
4558 | subf %0,%2,%1 | |
4559 | subfic %0,%2,%1") | |
4560 | ||
4561 | (define_insn "" | |
29ae5b89 JL |
4562 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
4563 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4564 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 4565 | (const_int 0))) |
29ae5b89 | 4566 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a DE |
4567 | "TARGET_POWERPC64" |
4568 | "subf. %3,%2,%1" | |
29ae5b89 | 4569 | [(set_attr "type" "compare")]) |
266eb58a DE |
4570 | |
4571 | (define_insn "" | |
29ae5b89 JL |
4572 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
4573 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4574 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 4575 | (const_int 0))) |
29ae5b89 | 4576 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
4577 | (minus:DI (match_dup 1) (match_dup 2)))] |
4578 | "TARGET_POWERPC64" | |
4579 | "subf. %0,%2,%1" | |
4580 | [(set_attr "type" "compare")]) | |
4581 | ||
4582 | (define_expand "subdi3" | |
4583 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4584 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
4585 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
4586 | "" | |
4587 | " | |
4588 | { | |
4589 | if (GET_CODE (operands[2]) == CONST_INT) | |
4590 | { | |
4591 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
4592 | negate_rtx (DImode, operands[2]))); | |
4593 | DONE; | |
4594 | } | |
4595 | }") | |
4596 | ||
4597 | (define_insn "absdi2" | |
4598 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
4599 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
4600 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
4601 | "TARGET_POWERPC64" | |
a260abc9 | 4602 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0" |
266eb58a DE |
4603 | [(set_attr "length" "12")]) |
4604 | ||
4605 | (define_split | |
4606 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
4607 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
4608 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
4609 | "TARGET_POWERPC64 && reload_completed" | |
a260abc9 | 4610 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 4611 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 4612 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
4613 | "") |
4614 | ||
4615 | (define_insn "" | |
4616 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
4617 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
4618 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
4619 | "TARGET_POWERPC64" | |
a260abc9 | 4620 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2" |
266eb58a DE |
4621 | [(set_attr "length" "12")]) |
4622 | ||
4623 | (define_split | |
4624 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
4625 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
4626 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
4627 | "TARGET_POWERPC64 && reload_completed" | |
a260abc9 | 4628 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a DE |
4629 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
4630 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] | |
4631 | "") | |
4632 | ||
4633 | (define_expand "negdi2" | |
4634 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4635 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
4636 | "" | |
4637 | "") | |
4638 | ||
4639 | (define_insn "" | |
4640 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4641 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
4642 | "TARGET_POWERPC64" | |
4643 | "neg %0,%1") | |
4644 | ||
4645 | (define_insn "" | |
29ae5b89 JL |
4646 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
4647 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
266eb58a | 4648 | (const_int 0))) |
29ae5b89 JL |
4649 | (clobber (match_scratch:DI 2 "=r"))] |
4650 | "TARGET_POWERPC64" | |
4651 | "neg. %2,%1" | |
4652 | [(set_attr "type" "compare")]) | |
815cdc52 | 4653 | |
29ae5b89 JL |
4654 | (define_insn "" |
4655 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
4656 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
815cdc52 | 4657 | (const_int 0))) |
29ae5b89 | 4658 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
815cdc52 | 4659 | (neg:DI (match_dup 1)))] |
29ae5b89 JL |
4660 | "TARGET_POWERPC64" |
4661 | "neg. %0,%1" | |
4662 | [(set_attr "type" "compare")]) | |
266eb58a DE |
4663 | |
4664 | (define_insn "ffsdi2" | |
4665 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
4666 | (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
4667 | "TARGET_POWERPC64" | |
4668 | "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64" | |
4669 | [(set_attr "length" "16")]) | |
4670 | ||
4671 | (define_insn "muldi3" | |
4672 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4673 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
4674 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
4675 | "TARGET_POWERPC64" | |
4676 | "mulld %0,%1,%2" | |
4677 | [(set_attr "type" "imul")]) | |
4678 | ||
4679 | (define_insn "smuldi3_highpart" | |
4680 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4681 | (truncate:DI | |
4682 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
4683 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
4684 | (sign_extend:TI | |
4685 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
4686 | (const_int 64))))] | |
4687 | "TARGET_POWERPC64" | |
4688 | "mulhd %0,%1,%2" | |
4689 | [(set_attr "type" "imul")]) | |
4690 | ||
4691 | (define_insn "umuldi3_highpart" | |
4692 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4693 | (truncate:DI | |
4694 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
4695 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
4696 | (zero_extend:TI | |
4697 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
4698 | (const_int 64))))] | |
4699 | "TARGET_POWERPC64" | |
4700 | "mulhdu %0,%1,%2" | |
4701 | [(set_attr "type" "imul")]) | |
4702 | ||
4703 | (define_expand "divdi3" | |
4704 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4705 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
4706 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
4707 | "TARGET_POWERPC64" | |
4708 | " | |
4709 | { | |
4710 | if (GET_CODE (operands[2]) == CONST_INT | |
4711 | && exact_log2 (INTVAL (operands[2])) >= 0) | |
4712 | ; | |
4713 | else | |
4714 | operands[2] = force_reg (DImode, operands[2]); | |
4715 | }") | |
4716 | ||
4717 | (define_expand "moddi3" | |
4718 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
4719 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
4720 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
4721 | "TARGET_POWERPC64" | |
4722 | " | |
4723 | { | |
4724 | int i = exact_log2 (INTVAL (operands[2])); | |
4725 | rtx temp1; | |
4726 | rtx temp2; | |
4727 | ||
4728 | if (GET_CODE (operands[2]) != CONST_INT || i < 0) | |
4729 | FAIL; | |
4730 | ||
4731 | temp1 = gen_reg_rtx (DImode); | |
4732 | temp2 = gen_reg_rtx (DImode); | |
4733 | ||
4734 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
4735 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
4736 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
4737 | DONE; | |
4738 | }") | |
4739 | ||
4740 | (define_insn "" | |
4741 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4742 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4743 | (match_operand:DI 2 "const_int_operand" "N")))] | |
4744 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" | |
4745 | "sradi %0,%1,%p2\;addze %0,%0" | |
4746 | [(set_attr "length" "8")]) | |
4747 | ||
4748 | (define_insn "" | |
29ae5b89 JL |
4749 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
4750 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4751 | (match_operand:DI 2 "const_int_operand" "N")) | |
266eb58a | 4752 | (const_int 0))) |
29ae5b89 | 4753 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 4754 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" |
29ae5b89 | 4755 | "sradi %3,%1,%p2\;addze. %3,%3" |
266eb58a | 4756 | [(set_attr "type" "compare") |
29ae5b89 | 4757 | (set_attr "length" "8")]) |
266eb58a DE |
4758 | |
4759 | (define_insn "" | |
29ae5b89 JL |
4760 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
4761 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4762 | (match_operand:DI 2 "const_int_operand" "N")) | |
266eb58a | 4763 | (const_int 0))) |
29ae5b89 | 4764 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
4765 | (div:DI (match_dup 1) (match_dup 2)))] |
4766 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" | |
29ae5b89 | 4767 | "sradi %0,%1,%p2\;addze. %0,%0" |
266eb58a | 4768 | [(set_attr "type" "compare") |
29ae5b89 | 4769 | (set_attr "length" "8")]) |
266eb58a DE |
4770 | |
4771 | (define_insn "" | |
4772 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4773 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a260abc9 | 4774 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
4775 | "TARGET_POWERPC64" |
4776 | "divd %0,%1,%2" | |
4777 | [(set_attr "type" "idiv")]) | |
4778 | ||
4779 | (define_insn "udivdi3" | |
4780 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4781 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4782 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
4783 | "TARGET_POWERPC64" | |
4784 | "divdu %0,%1,%2" | |
4785 | [(set_attr "type" "idiv")]) | |
4786 | ||
4787 | (define_insn "rotldi3" | |
4788 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4789 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4790 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
4791 | "TARGET_POWERPC64" | |
a66078ee | 4792 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 4793 | |
a260abc9 | 4794 | (define_insn "*rotldi3_internal2" |
29ae5b89 JL |
4795 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
4796 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4797 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 4798 | (const_int 0))) |
29ae5b89 | 4799 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 4800 | "TARGET_POWERPC64" |
29ae5b89 JL |
4801 | "rld%I2cl. %3,%1,%H2,0" |
4802 | [(set_attr "type" "delayed_compare")]) | |
266eb58a | 4803 | |
a260abc9 | 4804 | (define_insn "*rotldi3_internal3" |
29ae5b89 JL |
4805 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
4806 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4807 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 4808 | (const_int 0))) |
29ae5b89 | 4809 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
4810 | (rotate:DI (match_dup 1) (match_dup 2)))] |
4811 | "TARGET_POWERPC64" | |
29ae5b89 JL |
4812 | "rld%I2cl. %0,%1,%H2,0" |
4813 | [(set_attr "type" "delayed_compare")]) | |
266eb58a | 4814 | |
a260abc9 DE |
4815 | (define_insn "*rotldi3_internal4" |
4816 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4817 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4818 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
4819 | (match_operand:DI 3 "mask64_operand" "S")))] | |
4820 | "TARGET_POWERPC64" | |
4821 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
4822 | ||
4823 | (define_insn "*rotldi3_internal5" | |
29ae5b89 | 4824 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
a260abc9 | 4825 | (compare:CC (and:DI |
29ae5b89 JL |
4826 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
4827 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
4828 | (match_operand:DI 3 "mask64_operand" "S")) | |
a260abc9 | 4829 | (const_int 0))) |
29ae5b89 | 4830 | (clobber (match_scratch:DI 4 "=r"))] |
a260abc9 | 4831 | "TARGET_POWERPC64" |
29ae5b89 JL |
4832 | "rld%I2c%B3. %4,%1,%H2,%S3" |
4833 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
4834 | |
4835 | (define_insn "*rotldi3_internal6" | |
29ae5b89 | 4836 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
a260abc9 | 4837 | (compare:CC (and:DI |
29ae5b89 JL |
4838 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
4839 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
4840 | (match_operand:DI 3 "mask64_operand" "S")) | |
a260abc9 | 4841 | (const_int 0))) |
29ae5b89 | 4842 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
4843 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
4844 | "TARGET_POWERPC64" | |
29ae5b89 JL |
4845 | "rld%I2c%B3. %0,%1,%H2,%S3" |
4846 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
4847 | |
4848 | (define_insn "*rotldi3_internal7" | |
4849 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4850 | (zero_extend:DI | |
4851 | (subreg:QI | |
4852 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4853 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
4854 | "TARGET_POWERPC64" | |
4855 | "rld%I2cl %0,%1,%H2,56") | |
4856 | ||
4857 | (define_insn "*rotldi3_internal8" | |
29ae5b89 | 4858 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
a260abc9 DE |
4859 | (compare:CC (zero_extend:DI |
4860 | (subreg:QI | |
29ae5b89 JL |
4861 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
4862 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 4863 | (const_int 0))) |
29ae5b89 | 4864 | (clobber (match_scratch:DI 3 "=r"))] |
a260abc9 | 4865 | "TARGET_POWERPC64" |
29ae5b89 JL |
4866 | "rld%I2cl. %3,%1,%H2,56" |
4867 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
4868 | |
4869 | (define_insn "*rotldi3_internal9" | |
29ae5b89 | 4870 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
a260abc9 DE |
4871 | (compare:CC (zero_extend:DI |
4872 | (subreg:QI | |
29ae5b89 JL |
4873 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
4874 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 4875 | (const_int 0))) |
29ae5b89 | 4876 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
4877 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
4878 | "TARGET_POWERPC64" | |
29ae5b89 JL |
4879 | "rld%I2cl. %0,%1,%H2,56" |
4880 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
4881 | |
4882 | (define_insn "*rotldi3_internal10" | |
4883 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4884 | (zero_extend:DI | |
4885 | (subreg:HI | |
4886 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4887 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
4888 | "TARGET_POWERPC64" | |
4889 | "rld%I2cl %0,%1,%H2,48") | |
4890 | ||
4891 | (define_insn "*rotldi3_internal11" | |
29ae5b89 | 4892 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
a260abc9 DE |
4893 | (compare:CC (zero_extend:DI |
4894 | (subreg:HI | |
29ae5b89 JL |
4895 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
4896 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 4897 | (const_int 0))) |
29ae5b89 | 4898 | (clobber (match_scratch:DI 3 "=r"))] |
a260abc9 | 4899 | "TARGET_POWERPC64" |
29ae5b89 JL |
4900 | "rld%I2cl. %3,%1,%H2,48" |
4901 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
4902 | |
4903 | (define_insn "*rotldi3_internal12" | |
29ae5b89 | 4904 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
a260abc9 DE |
4905 | (compare:CC (zero_extend:DI |
4906 | (subreg:HI | |
29ae5b89 JL |
4907 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
4908 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 4909 | (const_int 0))) |
29ae5b89 | 4910 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
4911 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
4912 | "TARGET_POWERPC64" | |
29ae5b89 JL |
4913 | "rld%I2cl. %0,%1,%H2,48" |
4914 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
4915 | |
4916 | (define_insn "*rotldi3_internal13" | |
4917 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4918 | (zero_extend:DI | |
4919 | (subreg:SI | |
4920 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4921 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
4922 | "TARGET_POWERPC64" | |
4923 | "rld%I2cl %0,%1,%H2,32") | |
4924 | ||
4925 | (define_insn "*rotldi3_internal14" | |
29ae5b89 | 4926 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
a260abc9 DE |
4927 | (compare:CC (zero_extend:DI |
4928 | (subreg:SI | |
29ae5b89 JL |
4929 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
4930 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 4931 | (const_int 0))) |
29ae5b89 | 4932 | (clobber (match_scratch:DI 3 "=r"))] |
a260abc9 | 4933 | "TARGET_POWERPC64" |
29ae5b89 JL |
4934 | "rld%I2cl. %3,%1,%H2,32" |
4935 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
4936 | |
4937 | (define_insn "*rotldi3_internal15" | |
29ae5b89 | 4938 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
a260abc9 DE |
4939 | (compare:CC (zero_extend:DI |
4940 | (subreg:SI | |
29ae5b89 JL |
4941 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
4942 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 4943 | (const_int 0))) |
29ae5b89 | 4944 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
4945 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
4946 | "TARGET_POWERPC64" | |
29ae5b89 JL |
4947 | "rld%I2cl. %0,%1,%H2,32" |
4948 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 | 4949 | |
266eb58a DE |
4950 | (define_expand "ashldi3" |
4951 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4952 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
4953 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4954 | "TARGET_POWERPC64 || TARGET_POWER" | |
4955 | " | |
4956 | { | |
4957 | if (TARGET_POWERPC64) | |
4958 | ; | |
4959 | else if (TARGET_POWER) | |
4960 | { | |
4961 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
4962 | DONE; | |
4963 | } | |
4964 | else | |
4965 | FAIL; | |
4966 | }") | |
4967 | ||
4968 | (define_insn "" | |
4969 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4970 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4971 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
4972 | "TARGET_POWERPC64" | |
a66078ee | 4973 | "sld%I2 %0,%1,%H2" |
266eb58a DE |
4974 | [(set_attr "length" "8")]) |
4975 | ||
4976 | (define_insn "" | |
29ae5b89 JL |
4977 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
4978 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4979 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 4980 | (const_int 0))) |
29ae5b89 | 4981 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 4982 | "TARGET_POWERPC64" |
29ae5b89 JL |
4983 | "sld%I2. %3,%1,%H2" |
4984 | [(set_attr "type" "delayed_compare")]) | |
4985 | ||
266eb58a | 4986 | (define_insn "" |
29ae5b89 JL |
4987 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
4988 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4989 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 4990 | (const_int 0))) |
29ae5b89 | 4991 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
4992 | (ashift:DI (match_dup 1) (match_dup 2)))] |
4993 | "TARGET_POWERPC64" | |
29ae5b89 JL |
4994 | "sld%I2. %0,%1,%H2" |
4995 | [(set_attr "type" "delayed_compare")]) | |
266eb58a DE |
4996 | |
4997 | (define_expand "lshrdi3" | |
4998 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4999 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5000 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
5001 | "TARGET_POWERPC64 || TARGET_POWER" | |
5002 | " | |
5003 | { | |
5004 | if (TARGET_POWERPC64) | |
5005 | ; | |
5006 | else if (TARGET_POWER) | |
5007 | { | |
5008 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
5009 | DONE; | |
5010 | } | |
5011 | else | |
5012 | FAIL; | |
5013 | }") | |
5014 | ||
5015 | (define_insn "" | |
5016 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5017 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5018 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
5019 | "TARGET_POWERPC64" | |
a66078ee | 5020 | "srd%I2 %0,%1,%H2") |
266eb58a DE |
5021 | |
5022 | (define_insn "" | |
29ae5b89 JL |
5023 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5024 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5025 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
5026 | (const_int 0))) | |
5027 | (clobber (match_scratch:DI 3 "=r"))] | |
5028 | "TARGET_POWERPC64" | |
5029 | "srd%I2. %3,%1,%H2" | |
5030 | [(set_attr "type" "delayed_compare")]) | |
266eb58a | 5031 | |
29ae5b89 JL |
5032 | (define_insn "" |
5033 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
5034 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5035 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5036 | (const_int 0))) |
29ae5b89 JL |
5037 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
5038 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
5039 | "TARGET_POWERPC64" | |
5040 | "srd%I2. %0,%1,%H2" | |
5041 | [(set_attr "type" "delayed_compare")]) | |
266eb58a DE |
5042 | |
5043 | (define_expand "ashrdi3" | |
5044 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5045 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5046 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
5047 | "TARGET_POWERPC64 || TARGET_POWER" | |
5048 | " | |
5049 | { | |
5050 | if (TARGET_POWERPC64) | |
5051 | ; | |
5052 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
5053 | { | |
5054 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
5055 | DONE; | |
5056 | } | |
5057 | else | |
5058 | FAIL; | |
5059 | }") | |
5060 | ||
5061 | (define_insn "" | |
5062 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5063 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5064 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
5065 | "TARGET_POWERPC64" | |
375490e0 | 5066 | "srad%I2 %0,%1,%H2") |
266eb58a DE |
5067 | |
5068 | (define_insn "" | |
29ae5b89 JL |
5069 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5070 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5071 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5072 | (const_int 0))) |
29ae5b89 | 5073 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5074 | "TARGET_POWERPC64" |
29ae5b89 JL |
5075 | "srad%I2. %3,%1,%H2" |
5076 | [(set_attr "type" "delayed_compare")]) | |
266eb58a DE |
5077 | |
5078 | (define_insn "" | |
29ae5b89 JL |
5079 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5080 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5081 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5082 | (const_int 0))) |
29ae5b89 | 5083 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5084 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
5085 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5086 | "srad%I2. %0,%1,%H2" |
5087 | [(set_attr "type" "delayed_compare")]) | |
815cdc52 | 5088 | |
29ae5b89 JL |
5089 | (define_insn "anddi3" |
5090 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") | |
5091 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5092 | (match_operand:DI 2 "and64_operand" "?r,S,K,J"))) | |
5093 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] | |
6ffc8580 | 5094 | "TARGET_POWERPC64" |
266eb58a DE |
5095 | "@ |
5096 | and %0,%1,%2 | |
29ae5b89 JL |
5097 | rldic%B2 %0,%1,0,%S2 |
5098 | andi. %0,%1,%b2 | |
5099 | andis. %0,%1,%u2") | |
266eb58a | 5100 | |
a260abc9 | 5101 | (define_insn "*anddi3_internal2" |
29ae5b89 JL |
5102 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") |
5103 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5104 | (match_operand:DI 2 "and64_operand" "r,K,J,S")) | |
266eb58a | 5105 | (const_int 0))) |
29ae5b89 | 5106 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
6ffc8580 | 5107 | "TARGET_POWERPC64" |
266eb58a DE |
5108 | "@ |
5109 | and. %3,%1,%2 | |
6ffc8580 MM |
5110 | andi. %3,%1,%b2 |
5111 | andis. %3,%1,%u2 | |
29ae5b89 JL |
5112 | rldic%B2. %3,%1,0,%S2" |
5113 | [(set_attr "type" "compare,compare,compare,delayed_compare")]) | |
266eb58a | 5114 | |
a260abc9 | 5115 | (define_insn "*anddi3_internal3" |
29ae5b89 JL |
5116 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") |
5117 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5118 | (match_operand:DI 2 "and64_operand" "r,K,J,S")) | |
266eb58a | 5119 | (const_int 0))) |
29ae5b89 JL |
5120 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
5121 | (and:DI (match_dup 1) (match_dup 2)))] | |
6ffc8580 | 5122 | "TARGET_POWERPC64" |
266eb58a DE |
5123 | "@ |
5124 | and. %0,%1,%2 | |
6ffc8580 MM |
5125 | andi. %0,%1,%b2 |
5126 | andis. %0,%1,%u2 | |
29ae5b89 JL |
5127 | rldic%B2. %3,%1,0,%S2" |
5128 | [(set_attr "type" "compare,compare,compare,delayed_compare")]) | |
266eb58a | 5129 | |
a260abc9 | 5130 | (define_expand "iordi3" |
266eb58a | 5131 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 DE |
5132 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
5133 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
266eb58a | 5134 | "TARGET_POWERPC64" |
266eb58a DE |
5135 | " |
5136 | { | |
a260abc9 DE |
5137 | if (GET_CODE (operands[2]) == CONST_INT |
5138 | && !logical_operand (operands[2], DImode)) | |
266eb58a | 5139 | { |
a260abc9 DE |
5140 | HOST_WIDE_INT value = INTVAL (operands[2]); |
5141 | rtx tmp = ((reload_in_progress || reload_completed | |
5142 | || rtx_equal_p (operands[0], operands[1])) | |
5143 | ? operands[0] : gen_reg_rtx (DImode)); | |
266eb58a | 5144 | |
a260abc9 DE |
5145 | emit_insn (gen_iordi3 (tmp, operands[1], |
5146 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
5147 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
5148 | DONE; | |
266eb58a | 5149 | } |
266eb58a DE |
5150 | }") |
5151 | ||
a260abc9 | 5152 | (define_insn "*iordi3_internal1" |
266eb58a DE |
5153 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
5154 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r") | |
5155 | (match_operand:DI 2 "logical_operand" "r,K,J")))] | |
5156 | "TARGET_POWERPC64" | |
5157 | "@ | |
5158 | or %0,%1,%2 | |
5159 | ori %0,%1,%b2 | |
5160 | oris %0,%1,%u2") | |
5161 | ||
a260abc9 | 5162 | (define_insn "*iordi3_internal2" |
29ae5b89 JL |
5163 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5164 | (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5165 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5166 | (const_int 0))) |
29ae5b89 | 5167 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5168 | "TARGET_POWERPC64" |
29ae5b89 JL |
5169 | "or. %3,%1,%2" |
5170 | [(set_attr "type" "compare")]) | |
266eb58a | 5171 | |
a260abc9 | 5172 | (define_insn "*iordi3_internal3" |
29ae5b89 JL |
5173 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5174 | (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5175 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5176 | (const_int 0))) |
29ae5b89 | 5177 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5178 | (ior:DI (match_dup 1) (match_dup 2)))] |
5179 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5180 | "or. %0,%1,%2" |
5181 | [(set_attr "type" "compare")]) | |
266eb58a DE |
5182 | |
5183 | ;; Split an IOR that we can't do in one insn into two insns, each of which | |
5184 | ;; does one 16-bit part. This is used by combine. | |
5185 | ||
5186 | (define_split | |
5187 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5188 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5189 | (match_operand:DI 2 "non_logical_cint_operand" "")))] | |
5190 | "TARGET_POWERPC64" | |
5191 | [(set (match_dup 0) (ior:DI (match_dup 1) (match_dup 3))) | |
5192 | (set (match_dup 0) (ior:DI (match_dup 0) (match_dup 4)))] | |
5193 | " | |
5194 | { | |
3a598fbe | 5195 | operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); |
89e9f3a8 | 5196 | operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
266eb58a | 5197 | }") |
1fd4e8c1 | 5198 | |
a260abc9 DE |
5199 | (define_expand "xordi3" |
5200 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5201 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5202 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
5203 | "TARGET_POWERPC64" | |
5204 | " | |
5205 | { | |
5206 | if (GET_CODE (operands[2]) == CONST_INT | |
5207 | && !logical_operand (operands[2], DImode)) | |
5208 | { | |
5209 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
5210 | rtx tmp = ((reload_in_progress || reload_completed | |
5211 | || rtx_equal_p (operands[0], operands[1])) | |
5212 | ? operands[0] : gen_reg_rtx (DImode)); | |
5213 | ||
5214 | emit_insn (gen_xordi3 (tmp, operands[1], | |
5215 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
5216 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
5217 | DONE; | |
5218 | } | |
5219 | }") | |
5220 | ||
5221 | (define_insn "*xordi3_internal1" | |
266eb58a DE |
5222 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
5223 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r") | |
5224 | (match_operand:DI 2 "logical_operand" "r,K,J")))] | |
5225 | "TARGET_POWERPC64" | |
1fd4e8c1 | 5226 | "@ |
266eb58a DE |
5227 | xor %0,%1,%2 |
5228 | xori %0,%1,%b2 | |
5229 | xoris %0,%1,%u2") | |
1fd4e8c1 | 5230 | |
a260abc9 | 5231 | (define_insn "*xordi3_internal2" |
29ae5b89 JL |
5232 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5233 | (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5234 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5235 | (const_int 0))) |
29ae5b89 | 5236 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5237 | "TARGET_POWERPC64" |
29ae5b89 JL |
5238 | "xor. %3,%1,%2" |
5239 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 5240 | |
a260abc9 | 5241 | (define_insn "*xordi3_internal3" |
29ae5b89 JL |
5242 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5243 | (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5244 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5245 | (const_int 0))) |
29ae5b89 | 5246 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5247 | (xor:DI (match_dup 1) (match_dup 2)))] |
5248 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5249 | "xor. %0,%1,%2" |
5250 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 5251 | |
266eb58a DE |
5252 | ;; Split an XOR that we can't do in one insn into two insns, each of which |
5253 | ;; does one 16-bit part. This is used by combine. | |
5254 | ||
5255 | (define_split | |
5256 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
a260abc9 DE |
5257 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") |
5258 | (match_operand:DI 2 "non_logical_cint_operand" "")))] | |
266eb58a DE |
5259 | "TARGET_POWERPC64" |
5260 | [(set (match_dup 0) (xor:DI (match_dup 1) (match_dup 3))) | |
5261 | (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 4)))] | |
5262 | " | |
5263 | { | |
a260abc9 | 5264 | operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); |
89e9f3a8 | 5265 | operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
1fd4e8c1 RK |
5266 | }") |
5267 | ||
a260abc9 | 5268 | (define_insn "*eqvdi3_internal1" |
266eb58a DE |
5269 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
5270 | (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5271 | (match_operand:DI 2 "gpc_reg_operand" "r"))))] | |
5272 | "TARGET_POWERPC64" | |
5273 | "eqv %0,%1,%2") | |
a473029f | 5274 | |
a260abc9 | 5275 | (define_insn "*eqvdi3_internal2" |
29ae5b89 JL |
5276 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5277 | (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5278 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
815cdc52 | 5279 | (const_int 0))) |
29ae5b89 JL |
5280 | (clobber (match_scratch:DI 3 "=r"))] |
5281 | "TARGET_POWERPC64" | |
5282 | "eqv. %3,%1,%2" | |
5283 | [(set_attr "type" "compare")]) | |
a473029f | 5284 | |
a260abc9 | 5285 | (define_insn "*eqvdi3_internal3" |
29ae5b89 JL |
5286 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5287 | (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5288 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
266eb58a | 5289 | (const_int 0))) |
29ae5b89 | 5290 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a | 5291 | (not:DI (xor:DI (match_dup 1) (match_dup 2))))] |
29ae5b89 JL |
5292 | "TARGET_POWERPC64" |
5293 | "eqv. %0,%1,%2" | |
5294 | [(set_attr "type" "compare")]) | |
266eb58a | 5295 | |
a260abc9 | 5296 | (define_insn "*andcdi3_internal1" |
a473029f | 5297 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5298 | (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) |
5299 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
a473029f | 5300 | "TARGET_POWERPC64" |
266eb58a | 5301 | "andc %0,%2,%1") |
a473029f | 5302 | |
a260abc9 | 5303 | (define_insn "*andcdi3_internal2" |
29ae5b89 JL |
5304 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5305 | (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
5306 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5307 | (const_int 0))) |
29ae5b89 | 5308 | (clobber (match_scratch:DI 3 "=r"))] |
a473029f | 5309 | "TARGET_POWERPC64" |
29ae5b89 JL |
5310 | "andc. %3,%2,%1" |
5311 | [(set_attr "type" "compare")]) | |
a473029f | 5312 | |
a260abc9 | 5313 | (define_insn "*andcdi3_internal3" |
29ae5b89 JL |
5314 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5315 | (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
5316 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5317 | (const_int 0))) |
29ae5b89 | 5318 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a | 5319 | (and:DI (not:DI (match_dup 1)) (match_dup 2)))] |
a473029f | 5320 | "TARGET_POWERPC64" |
29ae5b89 JL |
5321 | "andc. %0,%2,%1" |
5322 | [(set_attr "type" "compare")]) | |
a473029f | 5323 | |
a260abc9 | 5324 | (define_insn "*iorcdi3_internal1" |
a473029f | 5325 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5326 | (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) |
5327 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
a473029f | 5328 | "TARGET_POWERPC64" |
266eb58a | 5329 | "orc %0,%2,%1") |
a473029f | 5330 | |
a260abc9 | 5331 | (define_insn "*iorcdi3_inernal2" |
29ae5b89 JL |
5332 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5333 | (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
5334 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5335 | (const_int 0))) |
29ae5b89 | 5336 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5337 | "TARGET_POWERPC64" |
29ae5b89 JL |
5338 | "orc. %3,%2,%1" |
5339 | [(set_attr "type" "compare")]) | |
266eb58a | 5340 | |
a260abc9 | 5341 | (define_insn "*iorcdi3_internal3" |
29ae5b89 JL |
5342 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5343 | (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
5344 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5345 | (const_int 0))) |
29ae5b89 | 5346 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5347 | (ior:DI (not:DI (match_dup 1)) (match_dup 2)))] |
5348 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5349 | "orc. %0,%2,%1" |
5350 | [(set_attr "type" "compare")]) | |
266eb58a | 5351 | |
a260abc9 | 5352 | (define_insn "*nanddi3_internal1" |
a473029f | 5353 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
29ae5b89 | 5354 | (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) |
266eb58a | 5355 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))] |
a473029f | 5356 | "TARGET_POWERPC64" |
266eb58a | 5357 | "nand %0,%1,%2") |
a473029f | 5358 | |
a260abc9 | 5359 | (define_insn "*nanddi3_internal2" |
29ae5b89 JL |
5360 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5361 | (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5362 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
266eb58a | 5363 | (const_int 0))) |
29ae5b89 | 5364 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5365 | "TARGET_POWERPC64" |
29ae5b89 JL |
5366 | "nand. %3,%1,%2" |
5367 | [(set_attr "type" "compare")]) | |
266eb58a | 5368 | |
a260abc9 | 5369 | (define_insn "*nanddi3_internal3" |
29ae5b89 JL |
5370 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5371 | (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5372 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
266eb58a | 5373 | (const_int 0))) |
29ae5b89 | 5374 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5375 | (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))] |
5376 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5377 | "nand. %0,%1,%2" |
5378 | [(set_attr "type" "compare")]) | |
266eb58a | 5379 | |
a260abc9 | 5380 | (define_insn "*nordi3_internal1" |
a473029f | 5381 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
29ae5b89 | 5382 | (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) |
266eb58a | 5383 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))] |
a473029f | 5384 | "TARGET_POWERPC64" |
266eb58a | 5385 | "nor %0,%1,%2") |
a473029f | 5386 | |
29ae5b89 JL |
5387 | (define_insn "*nordi3_internal2" |
5388 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
5389 | (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5390 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
815cdc52 | 5391 | (const_int 0))) |
29ae5b89 JL |
5392 | (clobber (match_scratch:DI 3 "=r"))] |
5393 | "TARGET_POWERPC64" | |
5394 | "nor. %3,%1,%2" | |
5395 | [(set_attr "type" "compare")]) | |
a473029f | 5396 | |
a260abc9 | 5397 | (define_insn "*nordi3_internal3" |
29ae5b89 JL |
5398 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5399 | (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5400 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
a473029f | 5401 | (const_int 0))) |
29ae5b89 | 5402 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a | 5403 | (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))] |
a473029f | 5404 | "TARGET_POWERPC64" |
29ae5b89 JL |
5405 | "nor. %0,%1,%2" |
5406 | [(set_attr "type" "compare")]) | |
a473029f | 5407 | \f |
1fd4e8c1 | 5408 | ;; Now define ways of moving data around. |
4697a36c MM |
5409 | |
5410 | ;; Elf specific ways of loading addresses for non-PIC code. | |
5411 | ;; The output of this could be r0, but we limit it to base | |
5412 | ;; registers, since almost all uses of this will need it | |
5413 | ;; in a base register shortly. | |
5414 | (define_insn "elf_high" | |
5415 | [(set (match_operand:SI 0 "register_operand" "=b") | |
5416 | (high:SI (match_operand 1 "" "")))] | |
5417 | "TARGET_ELF && !TARGET_64BIT" | |
a6c2a102 | 5418 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
5419 | |
5420 | (define_insn "elf_low" | |
5421 | [(set (match_operand:SI 0 "register_operand" "=r") | |
5422 | (lo_sum:SI (match_operand:SI 1 "register_operand" "b") | |
5423 | (match_operand 2 "" "")))] | |
5424 | "TARGET_ELF && !TARGET_64BIT" | |
a6c2a102 | 5425 | "{cal|la} %0,%2@l(%1)") |
4697a36c | 5426 | |
766a866c MM |
5427 | ;; Set up a register with a value from the GOT table |
5428 | ||
5429 | (define_expand "movsi_got" | |
5430 | [(set (match_operand:SI 0 "register_operand" "") | |
5431 | (unspec [(match_operand:SI 1 "got_operand" "") | |
5432 | (match_dup 2)] 8))] | |
58307bcd | 5433 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
5434 | " |
5435 | { | |
38c1f2d7 MM |
5436 | if (GET_CODE (operands[1]) == CONST) |
5437 | { | |
5438 | rtx offset = const0_rtx; | |
5439 | HOST_WIDE_INT value; | |
5440 | ||
5441 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
5442 | value = INTVAL (offset); | |
5443 | if (value != 0) | |
5444 | { | |
5445 | rtx tmp = ((reload_in_progress || reload_completed) | |
5446 | ? operands[0] | |
5447 | : gen_reg_rtx (Pmode)); | |
5448 | emit_insn (gen_movsi_got (tmp, operands[1])); | |
5449 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
5450 | DONE; | |
5451 | } | |
5452 | } | |
5453 | ||
c4c40373 | 5454 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
5455 | }") |
5456 | ||
84f414bc | 5457 | (define_insn "*movsi_got_internal" |
766a866c | 5458 | [(set (match_operand:SI 0 "register_operand" "=r") |
38c1f2d7 | 5459 | (unspec [(match_operand:SI 1 "got_no_const_operand" "") |
766a866c | 5460 | (match_operand:SI 2 "register_operand" "b")] 8))] |
c81bebd7 | 5461 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
5462 | "{l|lwz} %0,%a1@got(%2)" |
5463 | [(set_attr "type" "load")]) | |
5464 | ||
b22b9b3e JL |
5465 | ;; Sometimes, though, the GOT `register' will be on the stack. Deal with |
5466 | ;; this case specially. | |
5467 | ;; Force final to split this insn (if it hasn't been split already) to | |
5468 | ;; avoid having to create a suitable output template. | |
5469 | (define_insn "*movsi_got_internal_mem" | |
5470 | [(set (match_operand:SI 0 "register_operand" "=r") | |
5471 | (unspec [(match_operand:SI 1 "got_no_const_operand" "") | |
5472 | (match_operand:SI 2 "memory_operand" "m")] 8))] | |
5473 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
5474 | && flag_pic == 1 | |
5475 | && (reload_in_progress || reload_completed)" | |
5476 | "#" | |
5477 | [(set_attr "type" "load") | |
5478 | (set_attr "length" "8")]) | |
5479 | ||
5480 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg | |
5481 | ;; didn't get allocated to a hard register. | |
5482 | (define_split | |
5483 | [(set (match_operand:SI 0 "register_operand" "=r") | |
5484 | (unspec [(match_operand:SI 1 "got_no_const_operand" "") | |
5485 | (match_operand:SI 2 "memory_operand" "m")] 8))] | |
5486 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
5487 | && flag_pic == 1 | |
5488 | && (reload_in_progress || reload_completed)" | |
5489 | [(set (match_dup 0) (match_dup 2)) | |
5490 | (set (match_dup 0) (unspec [(match_dup 1)(match_dup 0)] 8))] | |
5491 | "") | |
5492 | ||
1fd4e8c1 RK |
5493 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
5494 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
5495 | ;; and this is even supposed to be faster, but it is simpler not to get | |
5496 | ;; integers in the TOC. | |
5497 | (define_expand "movsi" | |
5498 | [(set (match_operand:SI 0 "general_operand" "") | |
5499 | (match_operand:SI 1 "any_operand" ""))] | |
5500 | "" | |
5501 | " | |
5502 | { | |
5503 | if (GET_CODE (operands[0]) != REG) | |
5504 | operands[1] = force_reg (SImode, operands[1]); | |
5505 | ||
ef0e171b RK |
5506 | /* Convert a move of a CONST_DOUBLE into a CONST_INT */ |
5507 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
5508 | operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
5509 | ||
34792e82 | 5510 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 5511 | if (GET_CODE (operands[1]) == CONSTANT_P_RTX) |
34792e82 JL |
5512 | { |
5513 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
5514 | DONE; | |
5515 | } | |
5516 | ||
88228c4b MM |
5517 | /* Use default pattern for address of ELF small data */ |
5518 | if (TARGET_ELF | |
c81bebd7 | 5519 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
88228c4b | 5520 | && (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST) |
e98bb982 | 5521 | && small_data_operand (operands[1], SImode)) |
88228c4b | 5522 | { |
39403d82 | 5523 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
88228c4b MM |
5524 | DONE; |
5525 | } | |
5526 | ||
c81bebd7 | 5527 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
84f414bc | 5528 | && flag_pic == 1 && got_operand (operands[1], SImode)) |
766a866c MM |
5529 | { |
5530 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
5531 | DONE; | |
5532 | } | |
5533 | ||
4697a36c | 5534 | if (TARGET_ELF && TARGET_NO_TOC && !TARGET_64BIT |
461422d5 | 5535 | && !flag_pic |
4697a36c MM |
5536 | && CONSTANT_P (operands[1]) |
5537 | && GET_CODE (operands[1]) != HIGH | |
34792e82 | 5538 | && GET_CODE (operands[1]) != CONST_INT) |
4697a36c MM |
5539 | { |
5540 | rtx target = (reload_completed || reload_in_progress) | |
5541 | ? operands[0] : gen_reg_rtx (SImode); | |
5542 | ||
b6c9286a MM |
5543 | /* If this is a function address on -mcall-aixdesc or -mcall-nt, |
5544 | convert it to the address of the descriptor. */ | |
5545 | if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) | |
5546 | && GET_CODE (operands[1]) == SYMBOL_REF | |
5547 | && XSTR (operands[1], 0)[0] == '.') | |
5548 | { | |
5549 | char *name = XSTR (operands[1], 0); | |
5550 | rtx new_ref; | |
5551 | while (*name == '.') | |
5552 | name++; | |
39403d82 | 5553 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); |
b6c9286a MM |
5554 | CONSTANT_POOL_ADDRESS_P (new_ref) = CONSTANT_POOL_ADDRESS_P (operands[1]); |
5555 | SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]); | |
5556 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); | |
5557 | operands[1] = new_ref; | |
5558 | } | |
5559 | ||
4697a36c MM |
5560 | emit_insn (gen_elf_high (target, operands[1])); |
5561 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
5562 | DONE; | |
5563 | } | |
5564 | ||
b6c9286a MM |
5565 | if (GET_CODE (operands[1]) == CONST |
5566 | && DEFAULT_ABI == ABI_NT | |
5567 | && !side_effects_p (operands[0])) | |
5568 | { | |
5569 | rtx const_term = const0_rtx; | |
5570 | rtx sym = eliminate_constant_term (XEXP (operands[1], 0), &const_term); | |
5571 | if (sym && GET_CODE (const_term) == CONST_INT | |
5572 | && (GET_CODE (sym) == SYMBOL_REF || GET_CODE (sym) == LABEL_REF)) | |
5573 | { | |
354b734b MM |
5574 | unsigned HOST_WIDE_INT value = INTVAL (const_term); |
5575 | int new_reg_p = (flag_expensive_optimizations | |
5576 | && !reload_completed | |
5577 | && !reload_in_progress); | |
5578 | rtx tmp1 = (new_reg_p && value != 0) ? gen_reg_rtx (SImode) : operands[0]; | |
5579 | ||
5580 | emit_insn (gen_movsi (tmp1, sym)); | |
b6c9286a | 5581 | if (INTVAL (const_term) != 0) |
38c1f2d7 | 5582 | emit_insn (gen_addsi3 (operands[0], tmp1, GEN_INT (value))); |
b6c9286a MM |
5583 | DONE; |
5584 | } | |
5585 | else | |
a6c2a102 | 5586 | rs6000_fatal_bad_address (operands[1]); |
b6c9286a MM |
5587 | } |
5588 | ||
5589 | if ((!TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT) | |
5590 | && CONSTANT_P (operands[1]) | |
4697a36c MM |
5591 | && GET_CODE (operands[1]) != CONST_INT |
5592 | && GET_CODE (operands[1]) != HIGH | |
78b8d850 | 5593 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])) |
b45863ec | 5594 | { |
d302f4f2 MM |
5595 | /* Emit a USE operation so that the constant isn't deleted if |
5596 | expensive optimizations are turned on because nobody | |
e0350319 MM |
5597 | references it. This should only be done for operands that |
5598 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
5599 | This should not be done for operands that contain LABEL_REFs. | |
5600 | For now, we just handle the obvious case. */ | |
5601 | if (GET_CODE (operands[1]) != LABEL_REF) | |
39403d82 | 5602 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); |
d302f4f2 | 5603 | |
30a4619d RK |
5604 | /* If we are to limit the number of things we put in the TOC and |
5605 | this is a symbol plus a constant we can add in one insn, | |
abc95ed3 | 5606 | just put the symbol in the TOC and add the constant. Don't do |
30a4619d RK |
5607 | this if reload is in progress. */ |
5608 | if (GET_CODE (operands[1]) == CONST | |
5609 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
5610 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
5611 | && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode) | |
5612 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF | |
5613 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
5614 | && ! side_effects_p (operands[0])) | |
5615 | { | |
5616 | rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0)); | |
5617 | rtx other = XEXP (XEXP (operands[1], 0), 1); | |
5618 | ||
5619 | emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other)); | |
5620 | DONE; | |
5621 | } | |
5622 | ||
b45863ec RK |
5623 | operands[1] = force_const_mem (SImode, operands[1]); |
5624 | if (! memory_address_p (SImode, XEXP (operands[1], 0)) | |
5625 | && ! reload_in_progress) | |
5626 | operands[1] = change_address (operands[1], SImode, | |
5627 | XEXP (operands[1], 0)); | |
5628 | } | |
1fd4e8c1 RK |
5629 | }") |
5630 | ||
5631 | (define_insn "" | |
a260abc9 DE |
5632 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h") |
5633 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,J,n,R,*h,r,r,0"))] | |
19d5775a RK |
5634 | "gpc_reg_operand (operands[0], SImode) |
5635 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 5636 | "@ |
deb9225a | 5637 | mr %0,%1 |
b9442c72 | 5638 | {cal|la} %0,%a1 |
ca7f5001 RK |
5639 | {l%U1%X1|lwz%U1%X1} %0,%1 |
5640 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 5641 | {lil|li} %0,%1 |
802a0058 | 5642 | {liu|lis} %0,%v1 |
beaec479 | 5643 | # |
57fa6739 | 5644 | {cal|la} %0,%1(%*) |
1fd4e8c1 | 5645 | mf%1 %0 |
5c23c401 | 5646 | mt%0 %1 |
e76e75bb RK |
5647 | mt%0 %1 |
5648 | cror 0,0,0" | |
a260abc9 DE |
5649 | [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*") |
5650 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")]) | |
1fd4e8c1 | 5651 | |
77fa0940 RK |
5652 | ;; Split a load of a large constant into the appropriate two-insn |
5653 | ;; sequence. | |
5654 | ||
5655 | (define_split | |
5656 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5657 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 5658 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
5659 | && (INTVAL (operands[1]) & 0xffff) != 0" |
5660 | [(set (match_dup 0) | |
5661 | (match_dup 2)) | |
5662 | (set (match_dup 0) | |
5663 | (ior:SI (match_dup 0) | |
5664 | (match_dup 3)))] | |
5665 | " | |
5666 | { | |
3a598fbe | 5667 | operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000); |
89e9f3a8 | 5668 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); |
77fa0940 RK |
5669 | }") |
5670 | ||
1fd4e8c1 | 5671 | (define_insn "" |
29ae5b89 JL |
5672 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
5673 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 5674 | (const_int 0))) |
29ae5b89 | 5675 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] |
1fd4e8c1 | 5676 | "" |
29ae5b89 | 5677 | "mr. %0,%1" |
1fd4e8c1 RK |
5678 | [(set_attr "type" "compare")]) |
5679 | \f | |
5680 | (define_expand "movhi" | |
5681 | [(set (match_operand:HI 0 "general_operand" "") | |
5682 | (match_operand:HI 1 "any_operand" ""))] | |
5683 | "" | |
5684 | " | |
5685 | { | |
5686 | if (GET_CODE (operands[0]) != REG) | |
5687 | operands[1] = force_reg (HImode, operands[1]); | |
5688 | ||
3345af62 | 5689 | if (CONSTANT_P (operands[1]) |
34792e82 | 5690 | && GET_CODE (operands[1]) != CONST_INT) |
b45863ec RK |
5691 | { |
5692 | operands[1] = force_const_mem (HImode, operands[1]); | |
5693 | if (! memory_address_p (HImode, XEXP (operands[1], 0)) | |
5694 | && ! reload_in_progress) | |
5695 | operands[1] = change_address (operands[1], HImode, | |
5696 | XEXP (operands[1], 0)); | |
5697 | } | |
1fd4e8c1 RK |
5698 | }") |
5699 | ||
5700 | (define_insn "" | |
fb81d7ce RK |
5701 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
5702 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
5703 | "gpc_reg_operand (operands[0], HImode) |
5704 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 5705 | "@ |
deb9225a | 5706 | mr %0,%1 |
1fd4e8c1 RK |
5707 | lhz%U1%X1 %0,%1 |
5708 | sth%U0%X0 %1,%0 | |
19d5775a | 5709 | {lil|li} %0,%w1 |
1fd4e8c1 | 5710 | mf%1 %0 |
e76e75bb | 5711 | mt%0 %1 |
fb81d7ce | 5712 | mt%0 %1 |
e76e75bb | 5713 | cror 0,0,0" |
b7ff3d82 | 5714 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
5715 | |
5716 | (define_expand "movqi" | |
5717 | [(set (match_operand:QI 0 "general_operand" "") | |
5718 | (match_operand:QI 1 "any_operand" ""))] | |
5719 | "" | |
5720 | " | |
5721 | { | |
5722 | if (GET_CODE (operands[0]) != REG) | |
5723 | operands[1] = force_reg (QImode, operands[1]); | |
5724 | ||
3345af62 | 5725 | if (CONSTANT_P (operands[1]) |
34792e82 | 5726 | && GET_CODE (operands[1]) != CONST_INT) |
b45863ec RK |
5727 | { |
5728 | operands[1] = force_const_mem (QImode, operands[1]); | |
5729 | if (! memory_address_p (QImode, XEXP (operands[1], 0)) | |
5730 | && ! reload_in_progress) | |
5731 | operands[1] = change_address (operands[1], QImode, | |
5732 | XEXP (operands[1], 0)); | |
5733 | } | |
1fd4e8c1 RK |
5734 | }") |
5735 | ||
5736 | (define_insn "" | |
fb81d7ce RK |
5737 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
5738 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
5739 | "gpc_reg_operand (operands[0], QImode) |
5740 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 5741 | "@ |
deb9225a | 5742 | mr %0,%1 |
1fd4e8c1 RK |
5743 | lbz%U1%X1 %0,%1 |
5744 | stb%U0%X0 %1,%0 | |
19d5775a | 5745 | {lil|li} %0,%1 |
1fd4e8c1 | 5746 | mf%1 %0 |
e76e75bb | 5747 | mt%0 %1 |
fb81d7ce | 5748 | mt%0 %1 |
e76e75bb | 5749 | cror 0,0,0" |
b7ff3d82 | 5750 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
5751 | \f |
5752 | ;; Here is how to move condition codes around. When we store CC data in | |
5753 | ;; an integer register or memory, we store just the high-order 4 bits. | |
5754 | ;; This lets us not shift in the most common case of CR0. | |
5755 | (define_expand "movcc" | |
5756 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
5757 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
5758 | "" | |
5759 | "") | |
5760 | ||
5761 | (define_insn "" | |
5762 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") | |
5763 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] | |
5764 | "register_operand (operands[0], CCmode) | |
5765 | || register_operand (operands[1], CCmode)" | |
5766 | "@ | |
5767 | mcrf %0,%1 | |
5768 | mtcrf 128,%1 | |
ca7f5001 | 5769 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
1fd4e8c1 | 5770 | mfcr %0 |
ca7f5001 | 5771 | mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 |
deb9225a | 5772 | mr %0,%1 |
ca7f5001 RK |
5773 | {l%U1%X1|lwz%U1%X1} %0,%1 |
5774 | {st%U0%U1|stw%U0%U1} %1,%0" | |
b7ff3d82 | 5775 | [(set_attr "type" "*,*,*,compare,*,*,load,store") |
b19003d8 | 5776 | (set_attr "length" "*,*,12,*,8,*,*,*")]) |
1fd4e8c1 | 5777 | \f |
e52e05ca MM |
5778 | ;; For floating-point, we normally deal with the floating-point registers |
5779 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
5780 | ;; can produce floating-point values in fixed-point registers. Unless the | |
5781 | ;; value is a simple constant or already in memory, we deal with this by | |
5782 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
5783 | (define_expand "movsf" |
5784 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
5785 | (match_operand:SF 1 "any_operand" ""))] | |
5786 | "" | |
5787 | " | |
5788 | { | |
5789 | /* If we are called from reload, we might be getting a SUBREG of a hard | |
5790 | reg. So expand it. */ | |
5791 | if (GET_CODE (operands[0]) == SUBREG | |
5792 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
5793 | && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER) | |
5794 | operands[0] = alter_subreg (operands[0]); | |
5795 | if (GET_CODE (operands[1]) == SUBREG | |
5796 | && GET_CODE (SUBREG_REG (operands[1])) == REG | |
5797 | && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER) | |
5798 | operands[1] = alter_subreg (operands[1]); | |
5799 | ||
f99f88e0 | 5800 | if (GET_CODE (operands[0]) == MEM) |
1fd4e8c1 | 5801 | { |
f99f88e0 DE |
5802 | /* If operands[1] is a register, it may have double-precision data |
5803 | in it, so truncate it to single precision. We need not do | |
5804 | this for POWERPC. */ | |
5805 | if (! TARGET_POWERPC && TARGET_HARD_FLOAT | |
5806 | && GET_CODE (operands[1]) == REG | |
5807 | && (FP_REGNO_P (REGNO (operands[1])) | |
5808 | || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)) | |
f2974b07 | 5809 | { |
f99f88e0 DE |
5810 | rtx newreg |
5811 | = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode); | |
5812 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
5813 | operands[1] = newreg; | |
f2974b07 RK |
5814 | } |
5815 | ||
f99f88e0 | 5816 | operands[1] = force_reg (SFmode, operands[1]); |
1fd4e8c1 RK |
5817 | } |
5818 | ||
c4c40373 | 5819 | if (CONSTANT_P (operands[1]) && TARGET_HARD_FLOAT) |
1fd4e8c1 RK |
5820 | { |
5821 | operands[1] = force_const_mem (SFmode, operands[1]); | |
5822 | if (! memory_address_p (SFmode, XEXP (operands[1], 0)) | |
5823 | && ! reload_in_progress) | |
5824 | operands[1] = change_address (operands[1], SFmode, | |
5825 | XEXP (operands[1], 0)); | |
5826 | } | |
5827 | }") | |
5828 | ||
1fd4e8c1 | 5829 | (define_split |
cd2b37d9 | 5830 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 5831 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 5832 | "reload_completed |
5ae4759c MM |
5833 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
5834 | || (GET_CODE (operands[0]) == SUBREG | |
5835 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
5836 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 5837 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
5838 | " |
5839 | { | |
5840 | long l; | |
5841 | REAL_VALUE_TYPE rv; | |
5842 | ||
5843 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
5844 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 5845 | |
f99f88e0 DE |
5846 | if (! TARGET_POWERPC64) |
5847 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
5848 | else | |
5849 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 5850 | |
a260abc9 DE |
5851 | operands[3] = GEN_INT(l); |
5852 | }") | |
5853 | ||
c4c40373 | 5854 | (define_insn "*movsf_hardfloat" |
f99f88e0 DE |
5855 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r") |
5856 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))] | |
d14a6d05 MM |
5857 | "(gpc_reg_operand (operands[0], SFmode) |
5858 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT" | |
1fd4e8c1 | 5859 | "@ |
f99f88e0 DE |
5860 | mr %0,%1 |
5861 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
5862 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
5863 | fmr %0,%1 |
5864 | lfs%U1%X1 %0,%1 | |
c4c40373 MM |
5865 | stfs%U0%X0 %1,%0 |
5866 | # | |
5867 | #" | |
f99f88e0 DE |
5868 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*") |
5869 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 5870 | |
c4c40373 MM |
5871 | (define_insn "*movsf_softfloat" |
5872 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r") | |
5873 | (match_operand:SF 1 "input_operand" "r,m,r,I,J,R,G,Fn"))] | |
d14a6d05 MM |
5874 | "(gpc_reg_operand (operands[0], SFmode) |
5875 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT" | |
5876 | "@ | |
5877 | mr %0,%1 | |
5878 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
5879 | {st%U0%X0|stw%U0%X0} %1,%0 | |
5880 | {lil|li} %0,%1 | |
802a0058 | 5881 | {liu|lis} %0,%v1 |
c4c40373 MM |
5882 | {cal|la} %0,%1(%*) |
5883 | # | |
5884 | #" | |
5885 | [(set_attr "type" "*,load,store,*,*,*,*,*") | |
5886 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 5887 | |
1fd4e8c1 RK |
5888 | \f |
5889 | (define_expand "movdf" | |
5890 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
5891 | (match_operand:DF 1 "any_operand" ""))] | |
5892 | "" | |
5893 | " | |
5894 | { | |
e7113111 RK |
5895 | if (GET_CODE (operands[0]) != REG) |
5896 | operands[1] = force_reg (DFmode, operands[1]); | |
1fd4e8c1 | 5897 | |
e7113111 | 5898 | if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode)) |
1fd4e8c1 RK |
5899 | { |
5900 | operands[1] = force_const_mem (DFmode, operands[1]); | |
5901 | if (! memory_address_p (DFmode, XEXP (operands[1], 0)) | |
5902 | && ! reload_in_progress) | |
5903 | operands[1] = change_address (operands[1], DFmode, | |
5904 | XEXP (operands[1], 0)); | |
5905 | } | |
e7113111 | 5906 | }") |
1fd4e8c1 RK |
5907 | |
5908 | (define_split | |
cd2b37d9 | 5909 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 5910 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 5911 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
5912 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
5913 | || (GET_CODE (operands[0]) == SUBREG | |
5914 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
5915 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
5916 | [(set (match_dup 2) (match_dup 4)) |
5917 | (set (match_dup 3) (match_dup 1))] | |
5918 | " | |
5919 | { | |
5ae4759c MM |
5920 | int endian = (WORDS_BIG_ENDIAN == 0); |
5921 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); | |
5922 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
c4c40373 MM |
5923 | operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx; |
5924 | }") | |
5925 | ||
c4c40373 MM |
5926 | (define_split |
5927 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5928 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 5929 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
5930 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
5931 | || (GET_CODE (operands[0]) == SUBREG | |
5932 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
5933 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
5934 | [(set (match_dup 2) (match_dup 4)) |
5935 | (set (match_dup 3) (match_dup 5))] | |
5936 | " | |
5937 | { | |
5ae4759c | 5938 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
5939 | long l[2]; |
5940 | REAL_VALUE_TYPE rv; | |
5941 | ||
5942 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
5943 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
5944 | ||
5ae4759c MM |
5945 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
5946 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
47ad8c61 MM |
5947 | operands[4] = GEN_INT (l[endian]); |
5948 | operands[5] = GEN_INT (l[1 - endian]); | |
c4c40373 MM |
5949 | }") |
5950 | ||
efc08378 DE |
5951 | (define_split |
5952 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 5953 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 5954 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
5955 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
5956 | || (GET_CODE (operands[0]) == SUBREG | |
5957 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
5958 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 5959 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 5960 | " |
a260abc9 DE |
5961 | { |
5962 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5963 | long l[2]; | |
5964 | REAL_VALUE_TYPE rv; | |
5965 | ||
5966 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
5967 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
5968 | ||
5969 | operands[2] = gen_lowpart (DImode, operands[0]); | |
5970 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
5971 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); | |
5972 | }") | |
efc08378 | 5973 | |
4eae5fe1 | 5974 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 5975 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
5976 | ;; a non-offsettable memref, but also it is less efficient than loading |
5977 | ;; the constant into an FP register, since it will probably be used there. | |
5978 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
5979 | ;; of handling these non-offsettable values. | |
c4c40373 MM |
5980 | (define_insn "*movdf_hardfloat32" |
5981 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m") | |
5982 | (match_operand:DF 1 "input_operand" "r,o,r,G,H,F,f,m,f"))] | |
dc4f83ca MM |
5983 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT |
5984 | && (register_operand (operands[0], DFmode) | |
5985 | || register_operand (operands[1], DFmode))" | |
e7113111 RK |
5986 | "* |
5987 | { | |
5988 | switch (which_alternative) | |
5989 | { | |
a260abc9 | 5990 | default: |
a6c2a102 | 5991 | abort (); |
e7113111 RK |
5992 | case 0: |
5993 | /* We normally copy the low-numbered register first. However, if | |
5994 | the first register operand 0 is the same as the second register of | |
5995 | operand 1, we must copy in the opposite order. */ | |
5996 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 5997 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 5998 | else |
deb9225a | 5999 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 RK |
6000 | case 1: |
6001 | /* If the low-address word is used in the address, we must load it | |
6002 | last. Otherwise, load it first. Note that we cannot have | |
6003 | auto-increment in that case since the address register is known to be | |
6004 | dead. */ | |
6005 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
6006 | operands [1], 0)) | |
ca7f5001 | 6007 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
e7113111 | 6008 | else |
ca7f5001 | 6009 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
e7113111 | 6010 | case 2: |
ca7f5001 | 6011 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
e7113111 | 6012 | case 3: |
e7113111 | 6013 | case 4: |
e7113111 | 6014 | case 5: |
c4c40373 | 6015 | return \"#\"; |
e7113111 | 6016 | case 6: |
c4c40373 MM |
6017 | return \"fmr %0,%1\"; |
6018 | case 7: | |
6019 | return \"lfd%U1%X1 %0,%1\"; | |
6020 | case 8: | |
e7113111 RK |
6021 | return \"stfd%U0%X0 %1,%0\"; |
6022 | } | |
6023 | }" | |
c4c40373 MM |
6024 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
6025 | (set_attr "length" "8,8,8,8,12,16,*,*,*")]) | |
51b8fc2c | 6026 | |
c4c40373 | 6027 | (define_insn "*movdf_softfloat32" |
1427100a DE |
6028 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
6029 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca MM |
6030 | "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
6031 | && (register_operand (operands[0], DFmode) | |
6032 | || register_operand (operands[1], DFmode))" | |
6033 | "* | |
6034 | { | |
6035 | switch (which_alternative) | |
6036 | { | |
a260abc9 | 6037 | default: |
a6c2a102 | 6038 | abort (); |
dc4f83ca MM |
6039 | case 0: |
6040 | /* We normally copy the low-numbered register first. However, if | |
6041 | the first register operand 0 is the same as the second register of | |
6042 | operand 1, we must copy in the opposite order. */ | |
6043 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
6044 | return \"mr %L0,%L1\;mr %0,%1\"; | |
6045 | else | |
6046 | return \"mr %0,%1\;mr %L0,%L1\"; | |
6047 | case 1: | |
6048 | /* If the low-address word is used in the address, we must load it | |
6049 | last. Otherwise, load it first. Note that we cannot have | |
6050 | auto-increment in that case since the address register is known to be | |
6051 | dead. */ | |
6052 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
6053 | operands [1], 0)) | |
6054 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
6055 | else | |
6056 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
6057 | case 2: | |
6058 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
6059 | case 3: | |
c4c40373 MM |
6060 | case 4: |
6061 | case 5: | |
dc4f83ca MM |
6062 | return \"#\"; |
6063 | } | |
6064 | }" | |
c4c40373 MM |
6065 | [(set_attr "type" "*,load,store,*,*,*") |
6066 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 6067 | |
c4c40373 | 6068 | (define_insn "*movdf_hardfloat64" |
1427100a DE |
6069 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
6070 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca MM |
6071 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT |
6072 | && (register_operand (operands[0], DFmode) | |
6073 | || register_operand (operands[1], DFmode))" | |
51b8fc2c | 6074 | "@ |
3d5570cb RK |
6075 | mr %0,%1 |
6076 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 6077 | std%U0%X0 %1,%0 |
3d5570cb | 6078 | # |
c4c40373 MM |
6079 | # |
6080 | # | |
3d5570cb | 6081 | fmr %0,%1 |
f63184ac | 6082 | lfd%U1%X1 %0,%1 |
3d5570cb | 6083 | stfd%U0%X0 %1,%0" |
c4c40373 MM |
6084 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
6085 | (set_attr "length" "4,4,4,8,12,16,4,4,4")]) | |
dc4f83ca | 6086 | |
c4c40373 | 6087 | (define_insn "*movdf_softfloat64" |
1427100a DE |
6088 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
6089 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca MM |
6090 | "TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
6091 | && (register_operand (operands[0], DFmode) | |
6092 | || register_operand (operands[1], DFmode))" | |
6093 | "@ | |
6094 | mr %0,%1 | |
6095 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 6096 | std%U0%X0 %1,%0 |
c4c40373 MM |
6097 | # |
6098 | # | |
dc4f83ca | 6099 | #" |
c4c40373 MM |
6100 | [(set_attr "type" "*,load,store,*,*,*") |
6101 | (set_attr "length" "*,*,*,8,12,16")]) | |
1fd4e8c1 RK |
6102 | \f |
6103 | ;; Next come the multi-word integer load and store and the load and store | |
6104 | ;; multiple insns. | |
6105 | (define_expand "movdi" | |
6106 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 6107 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 RK |
6108 | "" |
6109 | " | |
6110 | { | |
e6ca2c17 | 6111 | if (GET_CODE (operands[0]) != REG) |
6b6ccd10 RK |
6112 | operands[1] = force_reg (DImode, operands[1]); |
6113 | ||
a260abc9 DE |
6114 | /* Convert a move of a CONST_DOUBLE into a CONST_INT |
6115 | only if sign-extended lower-half for 32-bit host. */ | |
6116 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
e8d791dd | 6117 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
6118 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 |
6119 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0) | |
6120 | || (CONST_DOUBLE_HIGH (operands[1]) == 0xffffffff | |
6121 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0)) | |
e8d791dd | 6122 | #endif |
a260abc9 DE |
6123 | ) |
6124 | operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
6b6ccd10 | 6125 | |
34792e82 | 6126 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 6127 | if (GET_CODE (operands[1]) == CONSTANT_P_RTX) |
34792e82 JL |
6128 | { |
6129 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
6130 | DONE; | |
6131 | } | |
6132 | ||
a260abc9 DE |
6133 | if (TARGET_64BIT |
6134 | && CONSTANT_P (operands[1]) | |
6135 | #if HOST_BITS_PER_WIDE_INT == 32 | |
6136 | && GET_CODE (operands[1]) != CONST_INT | |
6137 | #endif | |
6138 | && ! easy_fp_constant (operands[1], DImode) | |
6139 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])) | |
6140 | { | |
6141 | /* Emit a USE operation so that the constant isn't deleted if | |
6142 | expensive optimizations are turned on because nobody | |
6143 | references it. This should only be done for operands that | |
6144 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
6145 | This should not be done for operands that contain LABEL_REFs. | |
6146 | For now, we just handle the obvious case. */ | |
6147 | if (GET_CODE (operands[1]) != LABEL_REF) | |
39403d82 | 6148 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); |
062284d8 | 6149 | |
a260abc9 DE |
6150 | /* If we are to limit the number of things we put in the TOC and |
6151 | this is a symbol plus a constant we can add in one insn, | |
6152 | just put the symbol in the TOC and add the constant. Don't do | |
6153 | this if reload is in progress. */ | |
6154 | if (GET_CODE (operands[1]) == CONST | |
6155 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
6156 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
6157 | && add_operand (XEXP (XEXP (operands[1], 0), 1), DImode) | |
6158 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF | |
6159 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
6160 | && ! side_effects_p (operands[0])) | |
6161 | { | |
6162 | rtx sym = force_const_mem (DImode, XEXP (XEXP (operands[1], 0), 0)); | |
6163 | rtx other = XEXP (XEXP (operands[1], 0), 1); | |
a473029f | 6164 | |
a260abc9 DE |
6165 | emit_insn (gen_adddi3 (operands[0], force_reg (DImode, sym), other)); |
6166 | DONE; | |
6167 | } | |
a473029f | 6168 | |
a260abc9 DE |
6169 | operands[1] = force_const_mem (DImode, operands[1]); |
6170 | if (! memory_address_p (DImode, XEXP (operands[1], 0)) | |
6171 | && ! reload_in_progress) | |
6172 | operands[1] = change_address (operands[1], DImode, | |
6173 | XEXP (operands[1], 0)); | |
a473029f | 6174 | } |
1fd4e8c1 RK |
6175 | }") |
6176 | ||
c4c40373 | 6177 | (define_insn "*movdi_32" |
4e74d8ec MM |
6178 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") |
6179 | (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] | |
a260abc9 | 6180 | "! TARGET_POWERPC64 |
4e74d8ec MM |
6181 | && (gpc_reg_operand (operands[0], DImode) |
6182 | || gpc_reg_operand (operands[1], DImode))" | |
1fd4e8c1 RK |
6183 | "* |
6184 | { | |
6185 | switch (which_alternative) | |
6186 | { | |
a260abc9 | 6187 | default: |
a6c2a102 | 6188 | abort (); |
1fd4e8c1 RK |
6189 | case 0: |
6190 | /* We normally copy the low-numbered register first. However, if | |
6191 | the first register operand 0 is the same as the second register of | |
6192 | operand 1, we must copy in the opposite order. */ | |
6193 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 6194 | return \"mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 6195 | else |
deb9225a | 6196 | return \"mr %0,%1\;mr %L0,%L1\"; |
1fd4e8c1 RK |
6197 | case 1: |
6198 | /* If the low-address word is used in the address, we must load it | |
6199 | last. Otherwise, load it first. Note that we cannot have | |
6200 | auto-increment in that case since the address register is known to be | |
6201 | dead. */ | |
6202 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
6203 | operands [1], 0)) | |
ca7f5001 | 6204 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
1fd4e8c1 | 6205 | else |
ca7f5001 | 6206 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 | 6207 | case 2: |
ca7f5001 | 6208 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8ffd9c51 RK |
6209 | case 3: |
6210 | return \"fmr %0,%1\"; | |
6211 | case 4: | |
6212 | return \"lfd%U1%X1 %0,%1\"; | |
6213 | case 5: | |
6214 | return \"stfd%U0%X0 %1,%0\"; | |
4e74d8ec MM |
6215 | case 6: |
6216 | case 7: | |
6217 | case 8: | |
6218 | case 9: | |
6219 | case 10: | |
6220 | return \"#\"; | |
1fd4e8c1 RK |
6221 | } |
6222 | }" | |
4e74d8ec MM |
6223 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*") |
6224 | (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")]) | |
6225 | ||
6226 | (define_split | |
6227 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6228 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 6229 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
6230 | [(set (match_dup 2) (match_dup 4)) |
6231 | (set (match_dup 3) (match_dup 1))] | |
6232 | " | |
6233 | { | |
39403d82 DE |
6234 | operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0); |
6235 | operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0); | |
75d39459 | 6236 | #if HOST_BITS_PER_WIDE_INT == 32 |
4e74d8ec | 6237 | operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 DE |
6238 | #else |
6239 | operands[4] = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32; | |
6240 | operands[1] = INTVAL (operands[1]) & 0xffffffff; | |
6241 | #endif | |
4e74d8ec MM |
6242 | }") |
6243 | ||
4e74d8ec MM |
6244 | (define_split |
6245 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6246 | (match_operand:DI 1 "const_double_operand" ""))] | |
75d39459 | 6247 | "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
6248 | [(set (match_dup 2) (match_dup 4)) |
6249 | (set (match_dup 3) (match_dup 5))] | |
6250 | " | |
6251 | { | |
39403d82 DE |
6252 | operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0); |
6253 | operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0); | |
f6968f59 MM |
6254 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
6255 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
4e74d8ec MM |
6256 | }") |
6257 | ||
c4c40373 | 6258 | (define_insn "*movdi_64" |
e6ca2c17 | 6259 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h") |
4e74d8ec | 6260 | (match_operand:DI 1 "input_operand" "r,m,r,I,J,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 6261 | "TARGET_POWERPC64 |
4e74d8ec MM |
6262 | && (gpc_reg_operand (operands[0], DImode) |
6263 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 6264 | "@ |
3d5570cb RK |
6265 | mr %0,%1 |
6266 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 6267 | std%U0%X0 %1,%0 |
3d5570cb | 6268 | li %0,%1 |
802a0058 | 6269 | lis %0,%v1 |
e6ca2c17 | 6270 | # |
57fa6739 | 6271 | {cal|la} %0,%1(%*) |
3d5570cb RK |
6272 | fmr %0,%1 |
6273 | lfd%U1%X1 %0,%1 | |
6274 | stfd%U0%X0 %1,%0 | |
6275 | mf%1 %0 | |
08075ead DE |
6276 | mt%0 %1 |
6277 | cror 0,0,0" | |
b7ff3d82 | 6278 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*") |
e6ca2c17 DE |
6279 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
6280 | ||
a260abc9 DE |
6281 | (define_insn "" |
6282 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6283 | (match_operand:DI 1 "const_double_operand" "F"))] | |
6284 | "TARGET_POWERPC64 && GET_CODE (operands[1]) == CONST_DOUBLE | |
6285 | && num_insns_constant (operands[1], DImode) == 1" | |
6286 | "* | |
6287 | { | |
6288 | return ((unsigned HOST_WIDE_INT) | |
6289 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
6290 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
6291 | }") | |
6292 | ||
6293 | (define_split | |
6294 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6295 | (match_operand:DI 1 "const_int_operand" ""))] | |
6296 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
6297 | && num_insns_constant (operands[1], DImode) > 1" | |
6298 | [(set (match_dup 0) | |
6299 | (match_dup 2)) | |
6300 | (set (match_dup 0) | |
6301 | (ior:DI (match_dup 0) | |
6302 | (match_dup 3)))] | |
6303 | " | |
6304 | { | |
6305 | operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000); | |
6306 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); | |
6307 | }") | |
e6ca2c17 DE |
6308 | |
6309 | (define_split | |
6310 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6311 | (match_operand:DI 1 "const_double_operand" ""))] | |
a260abc9 DE |
6312 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
6313 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
6314 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
6315 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0) | |
6316 | || (CONST_DOUBLE_HIGH (operands[1]) == 0xffffffff | |
6317 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))" | |
e6ca2c17 DE |
6318 | [(set (match_dup 0) |
6319 | (match_dup 2)) | |
6320 | (set (match_dup 0) | |
6321 | (ior:DI (match_dup 0) | |
a260abc9 DE |
6322 | (match_dup 3)))] |
6323 | " | |
6324 | { | |
6325 | operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff0000); | |
6326 | operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff); | |
6327 | }") | |
6328 | ||
6329 | (define_split | |
6330 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6331 | (match_operand:DI 1 "const_double_operand" ""))] | |
6332 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
6333 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
6334 | && CONST_DOUBLE_HIGH (operands[1]) == 0 | |
6335 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0" | |
6336 | [(set (match_dup 0) | |
6337 | (match_dup 2)) | |
6338 | (set (match_dup 0) | |
6339 | (zero_extend:DI (subreg:SI (match_dup 0) 0)))] | |
6340 | " | |
6341 | { operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); }") | |
6342 | ||
6343 | (define_split | |
6344 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6345 | (match_operand:DI 1 "const_double_operand" ""))] | |
6346 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
6347 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
6348 | && CONST_DOUBLE_LOW (operands[1]) == 0" | |
6349 | [(set (match_dup 0) | |
6350 | (match_dup 2)) | |
e6ca2c17 DE |
6351 | (set (match_dup 0) |
6352 | (ashift:DI (match_dup 0) | |
a260abc9 DE |
6353 | (const_int 32)))] |
6354 | " | |
6355 | { operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); }") | |
6356 | ||
6357 | ;; Generate all one-bits and clear left or right. | |
6358 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
6359 | (define_split | |
6360 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6361 | (match_operand:DI 1 "mask64_operand" ""))] | |
6362 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
6363 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 6364 | (set (match_dup 0) |
a260abc9 DE |
6365 | (and:DI (rotate:DI (match_dup 0) |
6366 | (const_int 0)) | |
6367 | (match_dup 1)))] | |
6368 | "") | |
6369 | ||
6370 | ;; Split a load of a large constant into the appropriate five-instruction | |
6371 | ;; sequence. Handle anything in a constant number of insns. | |
6372 | ;; When non-easy constants can go in the TOC, this should use | |
6373 | ;; easy_fp_constant predicate. | |
6374 | (define_split | |
6375 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6376 | (match_operand:DI 1 "const_double_operand" ""))] | |
6377 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
6378 | [(set (match_dup 0) | |
6379 | (match_dup 2)) | |
6380 | (set (match_dup 0) | |
6381 | (ashift:DI (match_dup 0) | |
6382 | (const_int 32))) | |
e6ca2c17 DE |
6383 | (set (match_dup 0) |
6384 | (ior:DI (match_dup 0) | |
a260abc9 | 6385 | (match_dup 3)))] |
e6ca2c17 DE |
6386 | " |
6387 | { | |
6388 | HOST_WIDE_INT low; | |
6389 | HOST_WIDE_INT high; | |
6390 | ||
6391 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
6392 | { | |
f6968f59 MM |
6393 | low = CONST_DOUBLE_LOW (operands[1]); |
6394 | high = CONST_DOUBLE_HIGH (operands[1]); | |
e6ca2c17 | 6395 | } |
e8d791dd DE |
6396 | else |
6397 | #if HOST_BITS_PER_WIDE_INT == 32 | |
e6ca2c17 DE |
6398 | { |
6399 | low = INTVAL (operands[1]); | |
6400 | high = (low < 0) ? ~0 : 0; | |
6401 | } | |
e8d791dd | 6402 | #else |
e6ca2c17 DE |
6403 | { |
6404 | low = INTVAL (operands[1]) & 0xffffffff; | |
f4558646 | 6405 | high = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32; |
e6ca2c17 | 6406 | } |
e8d791dd | 6407 | #endif |
e6ca2c17 | 6408 | |
a260abc9 DE |
6409 | operands[2] = GEN_INT (high); |
6410 | operands[3] = GEN_INT (low); | |
e6ca2c17 | 6411 | }") |
08075ead DE |
6412 | |
6413 | (define_insn "" | |
29ae5b89 JL |
6414 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
6415 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
08075ead | 6416 | (const_int 0))) |
29ae5b89 | 6417 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] |
08075ead | 6418 | "TARGET_POWERPC64" |
29ae5b89 | 6419 | "mr. %0,%1" |
815cdc52 | 6420 | [(set_attr "type" "compare")]) |
1fd4e8c1 RK |
6421 | \f |
6422 | ;; TImode is similar, except that we usually want to compute the address into | |
6423 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 6424 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
6425 | (define_expand "movti" |
6426 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
6427 | (match_operand:TI 1 "general_operand" "")) | |
6428 | (clobber (scratch:SI))])] | |
7e69e155 | 6429 | "TARGET_STRING || TARGET_POWERPC64" |
1fd4e8c1 RK |
6430 | " |
6431 | { | |
6432 | if (GET_CODE (operands[0]) == MEM) | |
6433 | operands[1] = force_reg (TImode, operands[1]); | |
6434 | ||
6435 | if (GET_CODE (operands[0]) == MEM | |
6436 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
6437 | && ! reload_in_progress) | |
6438 | operands[0] = change_address (operands[0], TImode, | |
6439 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
6440 | ||
6441 | if (GET_CODE (operands[1]) == MEM | |
6442 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
6443 | && ! reload_in_progress) | |
6444 | operands[1] = change_address (operands[1], TImode, | |
6445 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
6446 | }") | |
6447 | ||
6448 | ;; We say that MQ is clobbered in the last alternative because the first | |
6449 | ;; alternative would never get used otherwise since it would need a reload | |
6450 | ;; while the 2nd alternative would not. We put memory cases first so they | |
6451 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
6452 | ;; giving the SCRATCH mq. | |
a260abc9 | 6453 | (define_insn "*movti_power" |
e1469d0d | 6454 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
6455 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
6456 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
7e69e155 | 6457 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 6458 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
6459 | "* |
6460 | { | |
6461 | switch (which_alternative) | |
6462 | { | |
dc4f83ca MM |
6463 | default: |
6464 | abort (); | |
6465 | ||
1fd4e8c1 | 6466 | case 0: |
ca7f5001 | 6467 | return \"{stsi|stswi} %1,%P0,16\"; |
1fd4e8c1 RK |
6468 | |
6469 | case 1: | |
ca7f5001 | 6470 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
1fd4e8c1 RK |
6471 | |
6472 | case 2: | |
6473 | /* Normally copy registers with lowest numbered register copied first. | |
6474 | But copy in the other order if the first register of the output | |
6475 | is the second, third, or fourth register in the input. */ | |
6476 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
6477 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
deb9225a | 6478 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 6479 | else |
deb9225a | 6480 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; |
1fd4e8c1 RK |
6481 | case 3: |
6482 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
6483 | fall through to generating four loads. */ | |
6484 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 6485 | return \"{lsi|lswi} %0,%P1,16\"; |
1fd4e8c1 RK |
6486 | /* ... fall through ... */ |
6487 | case 4: | |
6488 | /* If the address register is the same as the register for the lowest- | |
6489 | addressed word, load it last. Similarly for the next two words. | |
6490 | Otherwise load lowest address to highest. */ | |
6491 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
6492 | operands[1], 0)) | |
ca7f5001 | 6493 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; |
1fd4e8c1 RK |
6494 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, |
6495 | REGNO (operands[0]) + 2, operands[1], 0)) | |
ca7f5001 | 6496 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 RK |
6497 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, |
6498 | REGNO (operands[0]) + 3, operands[1], 0)) | |
ca7f5001 | 6499 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; |
1fd4e8c1 | 6500 | else |
ca7f5001 | 6501 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; |
1fd4e8c1 RK |
6502 | } |
6503 | }" | |
b7ff3d82 | 6504 | [(set_attr "type" "store,store,*,load,load") |
b19003d8 | 6505 | (set_attr "length" "*,16,16,*,16")]) |
51b8fc2c | 6506 | |
a260abc9 | 6507 | (define_insn "*movti_string" |
dc4f83ca MM |
6508 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r") |
6509 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,m")) | |
6510 | (clobber (match_scratch:SI 2 "=X,X,X"))] | |
7e69e155 | 6511 | "TARGET_STRING && !TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
6512 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
6513 | "* | |
6514 | { | |
6515 | switch (which_alternative) | |
6516 | { | |
6517 | default: | |
6518 | abort (); | |
6519 | ||
6520 | case 0: | |
6521 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; | |
6522 | ||
6523 | case 1: | |
6524 | /* Normally copy registers with lowest numbered register copied first. | |
6525 | But copy in the other order if the first register of the output | |
6526 | is the second, third, or fourth register in the input. */ | |
6527 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
6528 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
6529 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; | |
6530 | else | |
6531 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; | |
6532 | case 2: | |
6533 | /* If the address register is the same as the register for the lowest- | |
6534 | addressed word, load it last. Similarly for the next two words. | |
6535 | Otherwise load lowest address to highest. */ | |
6536 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
6537 | operands[1], 0)) | |
6538 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; | |
6539 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, | |
6540 | REGNO (operands[0]) + 2, operands[1], 0)) | |
6541 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; | |
6542 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, | |
6543 | REGNO (operands[0]) + 3, operands[1], 0)) | |
6544 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; | |
6545 | else | |
6546 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; | |
6547 | } | |
6548 | }" | |
b7ff3d82 | 6549 | [(set_attr "type" "store,*,load") |
dc4f83ca MM |
6550 | (set_attr "length" "16,16,16")]) |
6551 | ||
a260abc9 | 6552 | (define_insn "*movti_ppc64" |
51b8fc2c RK |
6553 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") |
6554 | (match_operand:TI 1 "input_operand" "r,m,r"))] | |
6555 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) | |
6556 | || gpc_reg_operand (operands[1], TImode))" | |
6557 | "* | |
6558 | { | |
6559 | switch (which_alternative) | |
6560 | { | |
a260abc9 | 6561 | default: |
a6c2a102 | 6562 | abort (); |
51b8fc2c RK |
6563 | case 0: |
6564 | /* We normally copy the low-numbered register first. However, if | |
6565 | the first register operand 0 is the same as the second register of | |
6566 | operand 1, we must copy in the opposite order. */ | |
6567 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
6568 | return \"mr %L0,%L1\;mr %0,%1\"; | |
6569 | else | |
6570 | return \"mr %0,%1\;mr %L0,%L1\"; | |
6571 | case 1: | |
6572 | /* If the low-address word is used in the address, we must load it | |
6573 | last. Otherwise, load it first. Note that we cannot have | |
6574 | auto-increment in that case since the address register is known to be | |
6575 | dead. */ | |
6576 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
6577 | operands [1], 0)) | |
6578 | return \"ld %L0,%L1\;ld %0,%1\"; | |
6579 | else | |
6580 | return \"ld%U1 %0,%1\;ld %L0,%L1\"; | |
6581 | case 2: | |
6582 | return \"std%U0 %1,%0\;std %L1,%L0\"; | |
6583 | } | |
6584 | }" | |
b7ff3d82 | 6585 | [(set_attr "type" "*,load,store") |
51b8fc2c | 6586 | (set_attr "length" "8,8,8")]) |
1fd4e8c1 RK |
6587 | \f |
6588 | (define_expand "load_multiple" | |
2f622005 RK |
6589 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
6590 | (match_operand:SI 1 "" "")) | |
6591 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 6592 | "TARGET_STRING" |
1fd4e8c1 RK |
6593 | " |
6594 | { | |
6595 | int regno; | |
6596 | int count; | |
6597 | rtx from; | |
6598 | int i; | |
6599 | ||
6600 | /* Support only loading a constant number of fixed-point registers from | |
6601 | memory and only bother with this if more than two; the machine | |
6602 | doesn't support more than eight. */ | |
6603 | if (GET_CODE (operands[2]) != CONST_INT | |
6604 | || INTVAL (operands[2]) <= 2 | |
6605 | || INTVAL (operands[2]) > 8 | |
6606 | || GET_CODE (operands[1]) != MEM | |
6607 | || GET_CODE (operands[0]) != REG | |
6608 | || REGNO (operands[0]) >= 32) | |
6609 | FAIL; | |
6610 | ||
6611 | count = INTVAL (operands[2]); | |
6612 | regno = REGNO (operands[0]); | |
6613 | ||
39403d82 | 6614 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
1fd4e8c1 RK |
6615 | from = force_reg (SImode, XEXP (operands[1], 0)); |
6616 | ||
6617 | for (i = 0; i < count; i++) | |
6618 | XVECEXP (operands[3], 0, i) | |
39403d82 | 6619 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
538bb158 JW |
6620 | change_address (operands[1], SImode, |
6621 | plus_constant (from, i * 4))); | |
1fd4e8c1 RK |
6622 | }") |
6623 | ||
6624 | (define_insn "" | |
6625 | [(match_parallel 0 "load_multiple_operation" | |
cd2b37d9 | 6626 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") |
4c99e795 | 6627 | (mem:SI (match_operand:SI 2 "register_operand" "b")))])] |
7e69e155 | 6628 | "TARGET_STRING" |
1fd4e8c1 RK |
6629 | "* |
6630 | { | |
6631 | /* We have to handle the case where the pseudo used to contain the address | |
e82ee4cc RK |
6632 | is assigned to one of the output registers. */ |
6633 | int i, j; | |
6634 | int words = XVECLEN (operands[0], 0); | |
6635 | rtx xop[10]; | |
6636 | ||
6637 | if (XVECLEN (operands[0], 0) == 1) | |
6638 | return \"{l|lwz} %1,0(%2)\"; | |
1fd4e8c1 | 6639 | |
e82ee4cc | 6640 | for (i = 0; i < words; i++) |
1fd4e8c1 RK |
6641 | if (refers_to_regno_p (REGNO (operands[1]) + i, |
6642 | REGNO (operands[1]) + i + 1, operands[2], 0)) | |
6643 | { | |
e82ee4cc RK |
6644 | if (i == words-1) |
6645 | { | |
6646 | xop[0] = operands[1]; | |
6647 | xop[1] = operands[2]; | |
6648 | xop[2] = GEN_INT (4 * (words-1)); | |
d89ddcfd | 6649 | output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop); |
e82ee4cc RK |
6650 | return \"\"; |
6651 | } | |
6652 | else if (i == 0) | |
6653 | { | |
6654 | xop[0] = operands[1]; | |
39403d82 | 6655 | xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
e82ee4cc RK |
6656 | xop[2] = GEN_INT (4 * (words-1)); |
6657 | output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop); | |
6658 | return \"\"; | |
6659 | } | |
6660 | else | |
6661 | { | |
6662 | for (j = 0; j < words; j++) | |
6663 | if (j != i) | |
6664 | { | |
39403d82 | 6665 | xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j); |
e82ee4cc RK |
6666 | xop[1] = operands[2]; |
6667 | xop[2] = GEN_INT (j * 4); | |
6668 | output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop); | |
6669 | } | |
6670 | xop[0] = operands[2]; | |
6671 | xop[1] = GEN_INT (i * 4); | |
6672 | output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop); | |
6673 | return \"\"; | |
6674 | } | |
1fd4e8c1 RK |
6675 | } |
6676 | ||
e82ee4cc | 6677 | return \"{lsi|lswi} %1,%2,%N0\"; |
1fd4e8c1 | 6678 | }" |
b19003d8 | 6679 | [(set_attr "type" "load") |
e82ee4cc | 6680 | (set_attr "length" "32")]) |
b19003d8 | 6681 | |
b7ff3d82 | 6682 | \f |
1fd4e8c1 | 6683 | (define_expand "store_multiple" |
2f622005 RK |
6684 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
6685 | (match_operand:SI 1 "" "")) | |
6686 | (clobber (scratch:SI)) | |
6687 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 6688 | "TARGET_STRING" |
1fd4e8c1 RK |
6689 | " |
6690 | { | |
6691 | int regno; | |
6692 | int count; | |
6693 | rtx to; | |
6694 | int i; | |
6695 | ||
6696 | /* Support only storing a constant number of fixed-point registers to | |
6697 | memory and only bother with this if more than two; the machine | |
6698 | doesn't support more than eight. */ | |
6699 | if (GET_CODE (operands[2]) != CONST_INT | |
6700 | || INTVAL (operands[2]) <= 2 | |
6701 | || INTVAL (operands[2]) > 8 | |
6702 | || GET_CODE (operands[0]) != MEM | |
6703 | || GET_CODE (operands[1]) != REG | |
6704 | || REGNO (operands[1]) >= 32) | |
6705 | FAIL; | |
6706 | ||
6707 | count = INTVAL (operands[2]); | |
6708 | regno = REGNO (operands[1]); | |
6709 | ||
39403d82 | 6710 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 RK |
6711 | to = force_reg (SImode, XEXP (operands[0], 0)); |
6712 | ||
6713 | XVECEXP (operands[3], 0, 0) | |
39403d82 | 6714 | = gen_rtx_SET (VOIDmode, change_address (operands[0], SImode, to), |
538bb158 | 6715 | operands[1]); |
39403d82 DE |
6716 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
6717 | gen_rtx_SCRATCH (SImode)); | |
1fd4e8c1 RK |
6718 | |
6719 | for (i = 1; i < count; i++) | |
6720 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 6721 | = gen_rtx_SET (VOIDmode, |
538bb158 JW |
6722 | change_address (operands[0], SImode, |
6723 | plus_constant (to, i * 4)), | |
39403d82 | 6724 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
6725 | }") |
6726 | ||
6727 | (define_insn "" | |
6728 | [(match_parallel 0 "store_multiple_operation" | |
6729 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 6730 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 6731 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 6732 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
6733 | "{stsi|stswi} %2,%P1,%O0" |
6734 | [(set_attr "type" "store")]) | |
d14a6d05 MM |
6735 | |
6736 | (define_insn "" | |
6737 | [(match_parallel 0 "store_multiple_operation" | |
4c99e795 | 6738 | [(set (mem:SI (match_operand:SI 1 "register_operand" "b")) |
d14a6d05 MM |
6739 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
6740 | (clobber (match_scratch:SI 3 "X"))])] | |
7e69e155 | 6741 | "TARGET_STRING && !TARGET_POWER" |
b7ff3d82 DE |
6742 | "{stsi|stswi} %2,%1,%O0" |
6743 | [(set_attr "type" "store")]) | |
7e69e155 MM |
6744 | |
6745 | \f | |
6746 | ;; String/block move insn. | |
6747 | ;; Argument 0 is the destination | |
6748 | ;; Argument 1 is the source | |
6749 | ;; Argument 2 is the length | |
6750 | ;; Argument 3 is the alignment | |
6751 | ||
6752 | (define_expand "movstrsi" | |
b6c9286a MM |
6753 | [(parallel [(set (match_operand:BLK 0 "" "") |
6754 | (match_operand:BLK 1 "" "")) | |
6755 | (use (match_operand:SI 2 "" "")) | |
6756 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
6757 | "" |
6758 | " | |
6759 | { | |
6760 | if (expand_block_move (operands)) | |
6761 | DONE; | |
6762 | else | |
6763 | FAIL; | |
6764 | }") | |
6765 | ||
6766 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
6767 | ;; register allocator doesn't have a clue about allocating 8 word registers | |
6768 | (define_expand "movstrsi_8reg" | |
b6c9286a MM |
6769 | [(parallel [(set (match_operand 0 "" "") |
6770 | (match_operand 1 "" "")) | |
6771 | (use (match_operand 2 "" "")) | |
6772 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
6773 | (clobber (reg:SI 5)) |
6774 | (clobber (reg:SI 6)) | |
6775 | (clobber (reg:SI 7)) | |
6776 | (clobber (reg:SI 8)) | |
6777 | (clobber (reg:SI 9)) | |
6778 | (clobber (reg:SI 10)) | |
6779 | (clobber (reg:SI 11)) | |
6780 | (clobber (reg:SI 12)) | |
3c67b673 | 6781 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
6782 | "TARGET_STRING" |
6783 | "") | |
6784 | ||
6785 | (define_insn "" | |
3c67b673 RK |
6786 | [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) |
6787 | (mem:BLK (match_operand:SI 1 "register_operand" "b"))) | |
6788 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
6789 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
6790 | (clobber (match_operand:SI 4 "register_operand" "=r")) | |
7e69e155 MM |
6791 | (clobber (reg:SI 6)) |
6792 | (clobber (reg:SI 7)) | |
6793 | (clobber (reg:SI 8)) | |
6794 | (clobber (reg:SI 9)) | |
6795 | (clobber (reg:SI 10)) | |
6796 | (clobber (reg:SI 11)) | |
6797 | (clobber (reg:SI 12)) | |
3c67b673 | 6798 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
6799 | "TARGET_STRING && TARGET_POWER |
6800 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0) | |
6801 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
6802 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
6803 | && REGNO (operands[4]) == 5" |
6804 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
6805 | [(set_attr "type" "load") |
6806 | (set_attr "length" "8")]) | |
7e69e155 MM |
6807 | |
6808 | (define_insn "" | |
3c67b673 RK |
6809 | [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) |
6810 | (mem:BLK (match_operand:SI 1 "register_operand" "b"))) | |
6811 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
6812 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
6813 | (clobber (match_operand:SI 4 "register_operand" "=r")) | |
7e69e155 MM |
6814 | (clobber (reg:SI 6)) |
6815 | (clobber (reg:SI 7)) | |
6816 | (clobber (reg:SI 8)) | |
6817 | (clobber (reg:SI 9)) | |
6818 | (clobber (reg:SI 10)) | |
6819 | (clobber (reg:SI 11)) | |
6820 | (clobber (reg:SI 12)) | |
3c67b673 | 6821 | (clobber (match_scratch:SI 5 "X"))] |
7e69e155 MM |
6822 | "TARGET_STRING && !TARGET_POWER |
6823 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0) | |
6824 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
6825 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
6826 | && REGNO (operands[4]) == 5" |
6827 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
6828 | [(set_attr "type" "load") |
6829 | (set_attr "length" "8")]) | |
7e69e155 MM |
6830 | |
6831 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the | |
6832 | ;; register allocator doesn't have a clue about allocating 6 word registers | |
6833 | (define_expand "movstrsi_6reg" | |
b6c9286a MM |
6834 | [(parallel [(set (match_operand 0 "" "") |
6835 | (match_operand 1 "" "")) | |
6836 | (use (match_operand 2 "" "")) | |
6837 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
6838 | (clobber (reg:SI 7)) |
6839 | (clobber (reg:SI 8)) | |
6840 | (clobber (reg:SI 9)) | |
6841 | (clobber (reg:SI 10)) | |
6842 | (clobber (reg:SI 11)) | |
6843 | (clobber (reg:SI 12)) | |
3c67b673 | 6844 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
6845 | "TARGET_STRING" |
6846 | "") | |
6847 | ||
6848 | (define_insn "" | |
3c67b673 RK |
6849 | [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) |
6850 | (mem:BLK (match_operand:SI 1 "register_operand" "b"))) | |
6851 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
6852 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
6853 | (clobber (match_operand:SI 4 "register_operand" "=r")) | |
7e69e155 MM |
6854 | (clobber (reg:SI 8)) |
6855 | (clobber (reg:SI 9)) | |
6856 | (clobber (reg:SI 10)) | |
6857 | (clobber (reg:SI 11)) | |
6858 | (clobber (reg:SI 12)) | |
3c67b673 | 6859 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
6860 | "TARGET_STRING && TARGET_POWER |
6861 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
6862 | && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12) | |
6863 | && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
6864 | && REGNO (operands[4]) == 7" |
6865 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
6866 | [(set_attr "type" "load") |
6867 | (set_attr "length" "8")]) | |
7e69e155 MM |
6868 | |
6869 | (define_insn "" | |
3c67b673 RK |
6870 | [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) |
6871 | (mem:BLK (match_operand:SI 1 "register_operand" "b"))) | |
6872 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
6873 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
6874 | (clobber (match_operand:SI 4 "register_operand" "=r")) | |
7e69e155 MM |
6875 | (clobber (reg:SI 8)) |
6876 | (clobber (reg:SI 9)) | |
6877 | (clobber (reg:SI 10)) | |
6878 | (clobber (reg:SI 11)) | |
6879 | (clobber (reg:SI 12)) | |
3c67b673 | 6880 | (clobber (match_scratch:SI 5 "X"))] |
7e69e155 MM |
6881 | "TARGET_STRING && !TARGET_POWER |
6882 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 | |
6883 | && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12) | |
6884 | && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
6885 | && REGNO (operands[4]) == 7" |
6886 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
6887 | [(set_attr "type" "load") |
6888 | (set_attr "length" "8")]) | |
7e69e155 MM |
6889 | |
6890 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill problems | |
6891 | ;; with TImode | |
6892 | (define_expand "movstrsi_4reg" | |
b6c9286a MM |
6893 | [(parallel [(set (match_operand 0 "" "") |
6894 | (match_operand 1 "" "")) | |
6895 | (use (match_operand 2 "" "")) | |
6896 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
6897 | (clobber (reg:SI 9)) |
6898 | (clobber (reg:SI 10)) | |
6899 | (clobber (reg:SI 11)) | |
6900 | (clobber (reg:SI 12)) | |
3c67b673 | 6901 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
6902 | "TARGET_STRING" |
6903 | "") | |
6904 | ||
6905 | (define_insn "" | |
3c67b673 RK |
6906 | [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) |
6907 | (mem:BLK (match_operand:SI 1 "register_operand" "b"))) | |
6908 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
6909 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
6910 | (clobber (match_operand:SI 4 "register_operand" "=r")) | |
7e69e155 MM |
6911 | (clobber (reg:SI 10)) |
6912 | (clobber (reg:SI 11)) | |
6913 | (clobber (reg:SI 12)) | |
3c67b673 | 6914 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
6915 | "TARGET_STRING && TARGET_POWER |
6916 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
6917 | && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12) | |
6918 | && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
6919 | && REGNO (operands[4]) == 9" |
6920 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
6921 | [(set_attr "type" "load") |
6922 | (set_attr "length" "8")]) | |
7e69e155 MM |
6923 | |
6924 | (define_insn "" | |
3c67b673 RK |
6925 | [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) |
6926 | (mem:BLK (match_operand:SI 1 "register_operand" "b"))) | |
6927 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
6928 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
6929 | (clobber (match_operand:SI 4 "register_operand" "=r")) | |
7e69e155 MM |
6930 | (clobber (reg:SI 10)) |
6931 | (clobber (reg:SI 11)) | |
6932 | (clobber (reg:SI 12)) | |
3c67b673 | 6933 | (clobber (match_scratch:SI 5 "X"))] |
7e69e155 MM |
6934 | "TARGET_STRING && !TARGET_POWER |
6935 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
6936 | && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12) | |
6937 | && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
6938 | && REGNO (operands[4]) == 9" |
6939 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
6940 | [(set_attr "type" "load") |
6941 | (set_attr "length" "8")]) | |
7e69e155 MM |
6942 | |
6943 | ;; Move up to 8 bytes at a time. | |
6944 | (define_expand "movstrsi_2reg" | |
b6c9286a MM |
6945 | [(parallel [(set (match_operand 0 "" "") |
6946 | (match_operand 1 "" "")) | |
6947 | (use (match_operand 2 "" "")) | |
6948 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
6949 | (clobber (match_scratch:DI 4 "")) |
6950 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
6951 | "TARGET_STRING && !TARGET_64BIT" |
6952 | "") | |
6953 | ||
6954 | (define_insn "" | |
3c67b673 RK |
6955 | [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) |
6956 | (mem:BLK (match_operand:SI 1 "register_operand" "b"))) | |
6957 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
6958 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
6959 | (clobber (match_scratch:DI 4 "=&r")) | |
6960 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 | 6961 | "TARGET_STRING && TARGET_POWER && !TARGET_64BIT |
3c67b673 RK |
6962 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
6963 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
6964 | [(set_attr "type" "load") |
6965 | (set_attr "length" "8")]) | |
7e69e155 MM |
6966 | |
6967 | (define_insn "" | |
3c67b673 RK |
6968 | [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) |
6969 | (mem:BLK (match_operand:SI 1 "register_operand" "b"))) | |
6970 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
6971 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
6972 | (clobber (match_scratch:DI 4 "=&r")) | |
6973 | (clobber (match_scratch:SI 5 "X"))] | |
7e69e155 MM |
6974 | "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT |
6975 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" | |
3c67b673 | 6976 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
6977 | [(set_attr "type" "load") |
6978 | (set_attr "length" "8")]) | |
7e69e155 MM |
6979 | |
6980 | ;; Move up to 4 bytes at a time. | |
6981 | (define_expand "movstrsi_1reg" | |
b6c9286a MM |
6982 | [(parallel [(set (match_operand 0 "" "") |
6983 | (match_operand 1 "" "")) | |
6984 | (use (match_operand 2 "" "")) | |
6985 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
6986 | (clobber (match_scratch:SI 4 "")) |
6987 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
6988 | "TARGET_STRING" |
6989 | "") | |
6990 | ||
6991 | (define_insn "" | |
3c67b673 RK |
6992 | [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) |
6993 | (mem:BLK (match_operand:SI 1 "register_operand" "b"))) | |
6994 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
6995 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
6996 | (clobber (match_scratch:SI 4 "=&r")) | |
6997 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
6998 | "TARGET_STRING && TARGET_POWER |
6999 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 7000 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
7001 | [(set_attr "type" "load") |
7002 | (set_attr "length" "8")]) | |
7e69e155 MM |
7003 | |
7004 | (define_insn "" | |
3c67b673 RK |
7005 | [(set (mem:BLK (match_operand:SI 0 "register_operand" "b")) |
7006 | (mem:BLK (match_operand:SI 1 "register_operand" "b"))) | |
7007 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
7008 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
7009 | (clobber (match_scratch:SI 4 "=&r")) | |
7010 | (clobber (match_scratch:SI 5 "X"))] | |
7e69e155 MM |
7011 | "TARGET_STRING && !TARGET_POWER |
7012 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 7013 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
7014 | [(set_attr "type" "load") |
7015 | (set_attr "length" "8")]) | |
7e69e155 | 7016 | |
1fd4e8c1 | 7017 | \f |
7e69e155 | 7018 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
7019 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
7020 | ;; do cases where the increment is not the size of the object. | |
7021 | ;; | |
7022 | ;; In all these cases, we use operands 0 and 1 for the register being | |
7023 | ;; incremented because those are the operands that local-alloc will | |
7024 | ;; tie and these are the pair most likely to be tieable (and the ones | |
7025 | ;; that will benefit the most). | |
7026 | ||
38c1f2d7 | 7027 | (define_insn "*movdi_update1" |
51b8fc2c | 7028 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 7029 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
51b8fc2c RK |
7030 | (match_operand:DI 2 "reg_or_short_operand" "r,I")))) |
7031 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
7032 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 7033 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
7034 | "@ |
7035 | ldux %3,%0,%2 | |
7036 | ldu %3,%2(%0)" | |
7037 | [(set_attr "type" "load")]) | |
7038 | ||
38c1f2d7 | 7039 | (define_insn "*movdi_update2" |
287f13ff RK |
7040 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") |
7041 | (sign_extend:DI | |
7042 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
7043 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
7044 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
7045 | (plus:DI (match_dup 1) (match_dup 2)))] | |
7046 | "TARGET_POWERPC64" | |
7047 | "lwaux %3,%0,%2" | |
7048 | [(set_attr "type" "load")]) | |
7049 | ||
4697a36c | 7050 | (define_insn "movdi_update" |
51b8fc2c RK |
7051 | [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
7052 | (match_operand:DI 2 "reg_or_short_operand" "r,I"))) | |
7053 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) | |
7054 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
7055 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 7056 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
7057 | "@ |
7058 | stdux %3,%0,%2 | |
b7ff3d82 DE |
7059 | stdu %3,%2(%0)" |
7060 | [(set_attr "type" "store")]) | |
51b8fc2c | 7061 | |
38c1f2d7 | 7062 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
7063 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
7064 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 7065 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 7066 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
7067 | (plus:SI (match_dup 1) (match_dup 2)))] |
7068 | "" | |
7069 | "@ | |
ca7f5001 RK |
7070 | {lux|lwzux} %3,%0,%2 |
7071 | {lu|lwzu} %3,%2(%0)" | |
cfb557c4 | 7072 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7073 | |
4697a36c | 7074 | (define_insn "movsi_update" |
cd2b37d9 | 7075 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7076 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
7077 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
7078 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 7079 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7080 | "TARGET_UPDATE" |
1fd4e8c1 | 7081 | "@ |
ca7f5001 | 7082 | {stux|stwux} %3,%0,%2 |
b7ff3d82 DE |
7083 | {stu|stwu} %3,%2(%0)" |
7084 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 7085 | |
38c1f2d7 | 7086 | (define_insn "*movhi_update" |
cd2b37d9 RK |
7087 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
7088 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 7089 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 7090 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7091 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7092 | "TARGET_UPDATE" |
1fd4e8c1 | 7093 | "@ |
5f243543 RK |
7094 | lhzux %3,%0,%2 |
7095 | lhzu %3,%2(%0)" | |
cfb557c4 | 7096 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7097 | |
38c1f2d7 | 7098 | (define_insn "*movhi_update2" |
cd2b37d9 | 7099 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 7100 | (zero_extend:SI |
cd2b37d9 | 7101 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7102 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 7103 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7104 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7105 | "TARGET_UPDATE" |
1fd4e8c1 | 7106 | "@ |
5f243543 RK |
7107 | lhzux %3,%0,%2 |
7108 | lhzu %3,%2(%0)" | |
cfb557c4 | 7109 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7110 | |
38c1f2d7 | 7111 | (define_insn "*movhi_update3" |
cd2b37d9 | 7112 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 7113 | (sign_extend:SI |
cd2b37d9 | 7114 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7115 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 7116 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7117 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7118 | "TARGET_UPDATE" |
1fd4e8c1 | 7119 | "@ |
5f243543 RK |
7120 | lhaux %3,%0,%2 |
7121 | lhau %3,%2(%0)" | |
cfb557c4 | 7122 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7123 | |
38c1f2d7 | 7124 | (define_insn "*movhi_update4" |
cd2b37d9 | 7125 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7126 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
7127 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
7128 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 7129 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7130 | "TARGET_UPDATE" |
1fd4e8c1 | 7131 | "@ |
5f243543 | 7132 | sthux %3,%0,%2 |
b7ff3d82 DE |
7133 | sthu %3,%2(%0)" |
7134 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 7135 | |
38c1f2d7 | 7136 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
7137 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
7138 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 7139 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 7140 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7141 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7142 | "TARGET_UPDATE" |
1fd4e8c1 | 7143 | "@ |
5f243543 RK |
7144 | lbzux %3,%0,%2 |
7145 | lbzu %3,%2(%0)" | |
cfb557c4 | 7146 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7147 | |
38c1f2d7 | 7148 | (define_insn "*movqi_update2" |
cd2b37d9 | 7149 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 7150 | (zero_extend:SI |
cd2b37d9 | 7151 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7152 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 7153 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7154 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7155 | "TARGET_UPDATE" |
1fd4e8c1 | 7156 | "@ |
5f243543 RK |
7157 | lbzux %3,%0,%2 |
7158 | lbzu %3,%2(%0)" | |
cfb557c4 | 7159 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7160 | |
38c1f2d7 | 7161 | (define_insn "*movqi_update3" |
cd2b37d9 | 7162 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7163 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
7164 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
7165 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 7166 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7167 | "TARGET_UPDATE" |
1fd4e8c1 | 7168 | "@ |
5f243543 | 7169 | stbux %3,%0,%2 |
b7ff3d82 DE |
7170 | stbu %3,%2(%0)" |
7171 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 7172 | |
38c1f2d7 | 7173 | (define_insn "*movsf_update1" |
cd2b37d9 | 7174 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 7175 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7176 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 7177 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7178 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7179 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 7180 | "@ |
5f243543 RK |
7181 | lfsux %3,%0,%2 |
7182 | lfsu %3,%2(%0)" | |
cfb557c4 | 7183 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 7184 | |
38c1f2d7 | 7185 | (define_insn "*movsf_update2" |
cd2b37d9 | 7186 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7187 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
7188 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
7189 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 7190 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7191 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 7192 | "@ |
85fff2f3 | 7193 | stfsux %3,%0,%2 |
b7ff3d82 DE |
7194 | stfsu %3,%2(%0)" |
7195 | [(set_attr "type" "fpstore")]) | |
1fd4e8c1 | 7196 | |
38c1f2d7 MM |
7197 | (define_insn "*movsf_update3" |
7198 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
7199 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
7200 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
7201 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
7202 | (plus:SI (match_dup 1) (match_dup 2)))] | |
7203 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
7204 | "@ | |
7205 | {lux|lwzux} %3,%0,%2 | |
7206 | {lu|lwzu} %3,%2(%0)" | |
7207 | [(set_attr "type" "load")]) | |
7208 | ||
7209 | (define_insn "*movsf_update4" | |
7210 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
7211 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
7212 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
7213 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
7214 | (plus:SI (match_dup 1) (match_dup 2)))] | |
7215 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
7216 | "@ | |
7217 | {stux|stwux} %3,%0,%2 | |
7218 | {stu|stwu} %3,%2(%0)" | |
7219 | [(set_attr "type" "store")]) | |
7220 | ||
7221 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
7222 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
7223 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 7224 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 7225 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7226 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7227 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 7228 | "@ |
5f243543 RK |
7229 | lfdux %3,%0,%2 |
7230 | lfdu %3,%2(%0)" | |
cfb557c4 | 7231 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 7232 | |
38c1f2d7 | 7233 | (define_insn "*movdf_update2" |
cd2b37d9 | 7234 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7235 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
7236 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
7237 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 7238 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7239 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 7240 | "@ |
5f243543 | 7241 | stfdux %3,%0,%2 |
b7ff3d82 DE |
7242 | stfdu %3,%2(%0)" |
7243 | [(set_attr "type" "fpstore")]) | |
4c70a4f3 RK |
7244 | |
7245 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
7246 | ||
7247 | (define_peephole | |
7248 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
7249 | (match_operand:DF 1 "memory_operand" "")) | |
7250 | (set (match_operand:DF 2 "gpc_reg_operand" "=f") | |
7251 | (match_operand:DF 3 "memory_operand" ""))] | |
7252 | "TARGET_POWER2 | |
d14a6d05 | 7253 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
7254 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
7255 | && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) | |
7256 | && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" | |
7257 | "lfq%U1%X1 %0,%1") | |
7258 | ||
7259 | (define_peephole | |
7260 | [(set (match_operand:DF 0 "memory_operand" "") | |
7261 | (match_operand:DF 1 "gpc_reg_operand" "f")) | |
7262 | (set (match_operand:DF 2 "memory_operand" "") | |
7263 | (match_operand:DF 3 "gpc_reg_operand" "f"))] | |
7264 | "TARGET_POWER2 | |
d14a6d05 | 7265 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
7266 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
7267 | && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) | |
7268 | && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" | |
7269 | "stfq%U0%X0 %1,%0") | |
1fd4e8c1 RK |
7270 | \f |
7271 | ;; Next come insns related to the calling sequence. | |
7272 | ;; | |
7273 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 7274 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
7275 | |
7276 | (define_expand "allocate_stack" | |
a260abc9 DE |
7277 | [(set (match_operand 0 "register_operand" "=r") |
7278 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) | |
7279 | (set (reg 1) | |
7280 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
7281 | "" |
7282 | " | |
4697a36c | 7283 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 7284 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 7285 | rtx neg_op0; |
1fd4e8c1 RK |
7286 | |
7287 | emit_move_insn (chain, stack_bot); | |
4697a36c | 7288 | |
e9a25f70 JL |
7289 | /* Under Windows NT, we need to add stack probes for large/variable |
7290 | allocations, so do it via a call to the external function alloca | |
7291 | instead of doing it inline. */ | |
979721f8 | 7292 | if (DEFAULT_ABI == ABI_NT |
e9a25f70 | 7293 | && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) > 4096)) |
979721f8 | 7294 | { |
a260abc9 | 7295 | rtx tmp = gen_reg_rtx (Pmode); |
39403d82 | 7296 | emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, \"__allocate_stack\"), |
a260abc9 | 7297 | tmp, 0, Pmode, 1, operands[1], Pmode); |
cea05fab | 7298 | emit_insn (gen_set_sp (tmp)); |
e9a25f70 | 7299 | emit_move_insn (operands[0], tmp); |
979721f8 MM |
7300 | DONE; |
7301 | } | |
7302 | ||
e9a25f70 JL |
7303 | if (GET_CODE (operands[1]) != CONST_INT |
7304 | || INTVAL (operands[1]) < -32767 | |
7305 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
7306 | { |
7307 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 7308 | if (TARGET_32BIT) |
e9a25f70 | 7309 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 7310 | else |
e9a25f70 | 7311 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
7312 | } |
7313 | else | |
e9a25f70 | 7314 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 7315 | |
38c1f2d7 MM |
7316 | if (TARGET_UPDATE) |
7317 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) | |
7318 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); | |
4697a36c | 7319 | |
38c1f2d7 MM |
7320 | else |
7321 | { | |
7322 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
7323 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 7324 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 7325 | } |
e9a25f70 JL |
7326 | |
7327 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
7328 | DONE; |
7329 | }") | |
59257ff7 | 7330 | |
cea05fab MM |
7331 | ;; Marker to indicate that the stack pointer was changed under NT in |
7332 | ;; ways not known to the compiler | |
7333 | ||
7334 | (define_insn "set_sp" | |
7335 | [(set (reg:SI 1) | |
7336 | (unspec [(match_operand:SI 0 "register_operand" "r")] 7))] | |
7337 | "" | |
7338 | "" | |
7339 | [(set_attr "length" "0")]) | |
7340 | ||
59257ff7 RK |
7341 | ;; These patterns say how to save and restore the stack pointer. We need not |
7342 | ;; save the stack pointer at function level since we are careful to | |
7343 | ;; preserve the backchain. At block level, we have to restore the backchain | |
7344 | ;; when we restore the stack pointer. | |
7345 | ;; | |
7346 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
7347 | ;; backchain and restore both. Note that in the nonlocal case, the | |
7348 | ;; save area is a memory location. | |
7349 | ||
7350 | (define_expand "save_stack_function" | |
ff381587 MM |
7351 | [(match_operand 0 "any_operand" "") |
7352 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 7353 | "" |
ff381587 | 7354 | "DONE;") |
59257ff7 RK |
7355 | |
7356 | (define_expand "restore_stack_function" | |
ff381587 MM |
7357 | [(match_operand 0 "any_operand" "") |
7358 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 7359 | "" |
ff381587 | 7360 | "DONE;") |
59257ff7 RK |
7361 | |
7362 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
7363 | [(use (match_operand 0 "register_operand" "")) |
7364 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 7365 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 7366 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
7367 | "" |
7368 | " | |
dfdfa60f DE |
7369 | { |
7370 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 7371 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 7372 | }") |
59257ff7 RK |
7373 | |
7374 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
7375 | [(match_operand 0 "memory_operand" "") |
7376 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
7377 | "" |
7378 | " | |
7379 | { | |
a260abc9 | 7380 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
7381 | |
7382 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 7383 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
a260abc9 DE |
7384 | emit_move_insn (operand_subword (operands[0], 0, 0, (TARGET_32BIT ? DImode : TImode)), |
7385 | temp); | |
7386 | emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)), | |
7387 | operands[1]); | |
59257ff7 RK |
7388 | DONE; |
7389 | }") | |
7e69e155 | 7390 | |
59257ff7 | 7391 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
7392 | [(match_operand 0 "register_operand" "") |
7393 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
7394 | "" |
7395 | " | |
7396 | { | |
a260abc9 | 7397 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
7398 | |
7399 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 DE |
7400 | emit_move_insn (temp, |
7401 | operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode))); | |
7402 | emit_move_insn (operands[0], | |
7403 | operand_subword (operands[1], 1, 0, (TARGET_32BIT ? DImode : TImode))); | |
39403d82 | 7404 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
7405 | DONE; |
7406 | }") | |
b6c9286a | 7407 | |
956d6950 | 7408 | ;; If we have -mminimal-toc, we need to reload r30 after a nonlocal goto. |
f0f6a223 RK |
7409 | |
7410 | (define_insn "nonlocal_goto_receiver" | |
7411 | [(unspec_volatile [(const_int 0)] 1)] | |
e9a25f70 | 7412 | "TARGET_TOC && TARGET_MINIMAL_TOC" |
f0f6a223 RK |
7413 | "* |
7414 | { | |
38c1f2d7 | 7415 | rs6000_output_load_toc_table (asm_out_file, 30); |
f0f6a223 RK |
7416 | return \"\"; |
7417 | }" | |
7418 | [(set_attr "type" "load")]) | |
b7ff3d82 | 7419 | \f |
b6c9286a MM |
7420 | ;; A function pointer under AIX is a pointer to a data area whose first word |
7421 | ;; contains the actual address of the function, whose second word contains a | |
7422 | ;; pointer to its TOC, and whose third word contains a value to place in the | |
7423 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 RK |
7424 | ;; "trampoline" need not have any executable code. |
7425 | ;; | |
b6c9286a MM |
7426 | ;; operands[0] is a register pointing to the 3 word descriptor (aka, the function address) |
7427 | ;; operands[1] is the stack size to clean up | |
7428 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for AIX) | |
7429 | ;; operands[3] is location to store the TOC | |
7430 | ;; operands[4] is the TOC register | |
7431 | ;; operands[5] is the static chain register | |
7432 | ;; | |
7433 | ;; We do not break this into separate insns, so that the scheduler will not try | |
7434 | ;; to move the load of the new TOC before any loads from the TOC. | |
7435 | ||
a260abc9 | 7436 | (define_insn "call_indirect_aix32" |
b6c9286a MM |
7437 | [(call (mem:SI (match_operand:SI 0 "register_operand" "b")) |
7438 | (match_operand 1 "const_int_operand" "n")) | |
6a4cee5f | 7439 | (use (match_operand 2 "const_int_operand" "n")) |
97f6e72f | 7440 | (use (match_operand 3 "offsettable_mem_operand" "o")) |
b6c9286a MM |
7441 | (use (match_operand 4 "register_operand" "r")) |
7442 | (clobber (match_operand 5 "register_operand" "=r")) | |
7443 | (clobber (match_scratch:SI 6 "=&r")) | |
7444 | (clobber (match_scratch:SI 7 "=l"))] | |
6a4cee5f MM |
7445 | "DEFAULT_ABI == ABI_AIX |
7446 | && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)" | |
97f6e72f | 7447 | "{st|stw} %4,%3\;{l|lwz} %6,0(%0)\;{l|lwz} %4,4(%0)\;mt%7 %6\;{l|lwz} %5,8(%0)\;{brl|blrl}\;{l|lwz} %4,%3" |
b7ff3d82 DE |
7448 | [(set_attr "type" "load") |
7449 | (set_attr "length" "28")]) | |
b6c9286a | 7450 | |
a260abc9 DE |
7451 | (define_insn "call_indirect_aix64" |
7452 | [(call (mem:SI (match_operand:DI 0 "register_operand" "b")) | |
7453 | (match_operand 1 "const_int_operand" "n")) | |
7454 | (use (match_operand 2 "const_int_operand" "n")) | |
97f6e72f | 7455 | (use (match_operand 3 "offsettable_mem_operand" "o")) |
a260abc9 DE |
7456 | (use (match_operand 4 "register_operand" "r")) |
7457 | (clobber (match_operand 5 "register_operand" "=r")) | |
7458 | (clobber (match_scratch:SI 6 "=&r")) | |
7459 | (clobber (match_scratch:SI 7 "=l"))] | |
7460 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX | |
7461 | && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)" | |
97f6e72f | 7462 | "std %4,%3\;ld %6,0(%0)\;ld %4,8(%0)\;mt%7 %6\;ld %5,16(%0)\;blrl\;ld %4,%3" |
a260abc9 DE |
7463 | [(set_attr "type" "load") |
7464 | (set_attr "length" "28")]) | |
7465 | ||
7466 | (define_insn "call_value_indirect_aix32" | |
b6c9286a MM |
7467 | [(set (match_operand 0 "register_operand" "fg") |
7468 | (call (mem:SI (match_operand:SI 1 "register_operand" "b")) | |
7469 | (match_operand 2 "const_int_operand" "n"))) | |
6a4cee5f | 7470 | (use (match_operand 3 "const_int_operand" "n")) |
97f6e72f | 7471 | (use (match_operand 4 "offsettable_mem_operand" "o")) |
b6c9286a MM |
7472 | (use (match_operand 5 "register_operand" "r")) |
7473 | (clobber (match_operand 6 "register_operand" "=r")) | |
7474 | (clobber (match_scratch:SI 7 "=&r")) | |
7475 | (clobber (match_scratch:SI 8 "=l"))] | |
6a4cee5f MM |
7476 | "DEFAULT_ABI == ABI_AIX |
7477 | && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)" | |
97f6e72f | 7478 | "{st|stw} %5,%4\;{l|lwz} %7,0(%1)\;{l|lwz} %5,4(%1)\;mt%8 %7\;{l|lwz} %6,8(%1)\;{brl|blrl}\;{l|lwz} %5,%4" |
a260abc9 DE |
7479 | [(set_attr "type" "load") |
7480 | (set_attr "length" "28")]) | |
7481 | ||
7482 | (define_insn "call_value_indirect_aix64" | |
7483 | [(set (match_operand 0 "register_operand" "fg") | |
7484 | (call (mem:SI (match_operand:DI 1 "register_operand" "b")) | |
7485 | (match_operand 2 "const_int_operand" "n"))) | |
7486 | (use (match_operand 3 "const_int_operand" "n")) | |
97f6e72f | 7487 | (use (match_operand 4 "offsettable_mem_operand" "o")) |
a260abc9 DE |
7488 | (use (match_operand 5 "register_operand" "r")) |
7489 | (clobber (match_operand 6 "register_operand" "=r")) | |
7490 | (clobber (match_scratch:SI 7 "=&r")) | |
7491 | (clobber (match_scratch:SI 8 "=l"))] | |
7492 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX | |
7493 | && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)" | |
97f6e72f | 7494 | "std %5,%4\;ld %7,0(%1)\;ld %5,8(%1)\;mt%8 %7\;ld %6,16(%1)\;blrl\;ld %5,%4" |
b7ff3d82 DE |
7495 | [(set_attr "type" "load") |
7496 | (set_attr "length" "28")]) | |
b6c9286a MM |
7497 | |
7498 | ;; A function pointer undef NT is a pointer to a data area whose first word | |
7499 | ;; contains the actual address of the function, whose second word contains a | |
7500 | ;; pointer to its TOC. The static chain is not stored under NT, which means | |
7501 | ;; that we need a trampoline. | |
7502 | ;; | |
7503 | ;; operands[0] is an SImode pseudo in which we place the address of the function. | |
7504 | ;; operands[1] is the stack size to clean up | |
7505 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for NT) | |
7506 | ;; operands[3] is location to store the TOC | |
7507 | ;; operands[4] is the TOC register | |
7508 | ;; | |
7509 | ;; We do not break this into separate insns, so that the scheduler will not try | |
7510 | ;; to move the load of the new TOC before any loads from the TOC. | |
7511 | ||
7512 | (define_insn "call_indirect_nt" | |
7513 | [(call (mem:SI (match_operand:SI 0 "register_operand" "b")) | |
7514 | (match_operand 1 "const_int_operand" "n")) | |
6a4cee5f | 7515 | (use (match_operand 2 "const_int_operand" "n")) |
97f6e72f | 7516 | (use (match_operand 3 "offsettable_mem_operand" "o")) |
b6c9286a MM |
7517 | (use (match_operand 4 "register_operand" "r")) |
7518 | (clobber (match_scratch:SI 5 "=&r")) | |
7519 | (clobber (match_scratch:SI 6 "=l"))] | |
6a4cee5f MM |
7520 | "DEFAULT_ABI == ABI_NT |
7521 | && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)" | |
e1f83b4d | 7522 | "{st|stw} %4,%a3\;{l|lwz} %5,0(%0)\;{l|lwz} %4,4(%0)\;mt%6 %5\;{brl|blrl}\;{l|lwz} %4,%a3" |
b7ff3d82 DE |
7523 | [(set_attr "type" "load") |
7524 | (set_attr "length" "24")]) | |
b6c9286a MM |
7525 | |
7526 | (define_insn "call_value_indirect_nt" | |
7527 | [(set (match_operand 0 "register_operand" "fg") | |
7528 | (call (mem:SI (match_operand:SI 1 "register_operand" "b")) | |
7529 | (match_operand 2 "const_int_operand" "n"))) | |
6a4cee5f | 7530 | (use (match_operand 3 "const_int_operand" "n")) |
97f6e72f | 7531 | (use (match_operand 4 "offsettable_mem_operand" "o")) |
b6c9286a MM |
7532 | (use (match_operand 5 "register_operand" "r")) |
7533 | (clobber (match_scratch:SI 6 "=&r")) | |
7534 | (clobber (match_scratch:SI 7 "=l"))] | |
6a4cee5f MM |
7535 | "DEFAULT_ABI == ABI_NT |
7536 | && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)" | |
e1f83b4d | 7537 | "{st|stw} %5,%a4\;{l|lwz} %6,0(%1)\;{l|lwz} %5,4(%1)\;mt%7 %6\;{brl|blrl}\;{l|lwz} %5,%a4" |
b7ff3d82 DE |
7538 | [(set_attr "type" "load") |
7539 | (set_attr "length" "24")]) | |
b6c9286a MM |
7540 | |
7541 | ;; A function pointer under System V is just a normal pointer | |
7542 | ;; operands[0] is the function pointer | |
7543 | ;; operands[1] is the stack size to clean up | |
7544 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument which indicates how to set cr1 | |
7545 | ||
7546 | (define_insn "call_indirect_sysv" | |
7547 | [(call (mem:SI (match_operand:SI 0 "register_operand" "l,l")) | |
7548 | (match_operand 1 "const_int_operand" "n,n")) | |
7549 | (use (match_operand 2 "const_int_operand" "O,n")) | |
7550 | (clobber (match_scratch:SI 3 "=l,l"))] | |
c81bebd7 | 7551 | "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC" |
b6c9286a MM |
7552 | "* |
7553 | { | |
6a4cee5f MM |
7554 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
7555 | output_asm_insn (\"crxor 6,6,6\", operands); | |
1fd4e8c1 | 7556 | |
6a4cee5f MM |
7557 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
7558 | output_asm_insn (\"creqv 6,6,6\", operands); | |
b6c9286a MM |
7559 | |
7560 | return \"{brl|blrl}\"; | |
7561 | }" | |
b7ff3d82 DE |
7562 | [(set_attr "type" "jmpreg") |
7563 | (set_attr "length" "4,8")]) | |
b6c9286a MM |
7564 | |
7565 | (define_insn "call_value_indirect_sysv" | |
7566 | [(set (match_operand 0 "register_operand" "=fg,fg") | |
7567 | (call (mem:SI (match_operand:SI 1 "register_operand" "l,l")) | |
7568 | (match_operand 2 "const_int_operand" "n,n"))) | |
7569 | (use (match_operand 3 "const_int_operand" "O,n")) | |
7570 | (clobber (match_scratch:SI 4 "=l,l"))] | |
c81bebd7 | 7571 | "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC" |
b6c9286a MM |
7572 | "* |
7573 | { | |
6a4cee5f MM |
7574 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
7575 | output_asm_insn (\"crxor 6,6,6\", operands); | |
b6c9286a | 7576 | |
6a4cee5f MM |
7577 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) |
7578 | output_asm_insn (\"creqv 6,6,6\", operands); | |
b6c9286a MM |
7579 | |
7580 | return \"{brl|blrl}\"; | |
7581 | }" | |
b7ff3d82 DE |
7582 | [(set_attr "type" "jmpreg") |
7583 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 7584 | |
b6c9286a | 7585 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 7586 | (define_expand "call" |
a260abc9 | 7587 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 7588 | (match_operand 1 "" "")) |
4697a36c | 7589 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
7590 | (clobber (scratch:SI))])] |
7591 | "" | |
7592 | " | |
7593 | { | |
7594 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) | |
7595 | abort (); | |
7596 | ||
7597 | operands[0] = XEXP (operands[0], 0); | |
7509c759 MM |
7598 | |
7599 | /* Convert NT DLL imports into an indirect call. */ | |
7600 | if (GET_CODE (operands[0]) == SYMBOL_REF | |
6a4cee5f | 7601 | && (INTVAL (operands[2]) & CALL_NT_DLLIMPORT) != 0) |
7509c759 MM |
7602 | { |
7603 | operands[0] = rs6000_dll_import_ref (operands[0]); | |
7604 | operands[2] = GEN_INT ((int)CALL_NORMAL); | |
7605 | } | |
7606 | ||
6a4cee5f MM |
7607 | if (GET_CODE (operands[0]) != SYMBOL_REF |
7608 | || (INTVAL (operands[2]) & CALL_LONG) != 0) | |
1fd4e8c1 | 7609 | { |
6a4cee5f MM |
7610 | if (INTVAL (operands[2]) & CALL_LONG) |
7611 | operands[0] = rs6000_longcall_ref (operands[0]); | |
7612 | ||
c81bebd7 | 7613 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS) |
b6c9286a MM |
7614 | emit_call_insn (gen_call_indirect_sysv (force_reg (Pmode, operands[0]), |
7615 | operands[1], operands[2])); | |
7616 | else | |
7617 | { | |
39403d82 | 7618 | rtx toc_reg = gen_rtx_REG (Pmode, 2); |
b6c9286a | 7619 | rtx toc_addr = RS6000_SAVE_TOC; |
1fd4e8c1 | 7620 | |
b6c9286a MM |
7621 | if (DEFAULT_ABI == ABI_AIX) |
7622 | { | |
7623 | /* AIX function pointers are really pointers to a three word area */ | |
39403d82 | 7624 | rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); |
a260abc9 DE |
7625 | emit_call_insn (TARGET_32BIT |
7626 | ? gen_call_indirect_aix32 (force_reg (Pmode, operands[0]), | |
7627 | operands[1], operands[2], | |
7628 | toc_addr, toc_reg, static_chain) | |
7629 | : gen_call_indirect_aix64 (force_reg (Pmode, operands[0]), | |
7630 | operands[1], operands[2], | |
7631 | toc_addr, toc_reg, static_chain)); | |
b6c9286a MM |
7632 | } |
7633 | else if (DEFAULT_ABI == ABI_NT) | |
7634 | { | |
7635 | /* NT function pointers are really pointers to a two word area */ | |
7636 | emit_call_insn (gen_call_indirect_nt (force_reg (Pmode, operands[0]), | |
7637 | operands[1], operands[2], | |
7638 | toc_addr, toc_reg)); | |
7639 | } | |
7640 | else | |
7641 | abort (); | |
7642 | } | |
7643 | DONE; | |
1fd4e8c1 RK |
7644 | } |
7645 | }") | |
7646 | ||
7647 | (define_expand "call_value" | |
7648 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 7649 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 7650 | (match_operand 2 "" ""))) |
4697a36c | 7651 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
7652 | (clobber (scratch:SI))])] |
7653 | "" | |
7654 | " | |
7655 | { | |
7656 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) | |
7657 | abort (); | |
7658 | ||
7659 | operands[1] = XEXP (operands[1], 0); | |
7509c759 MM |
7660 | |
7661 | /* Convert NT DLL imports into an indirect call. */ | |
7662 | if (GET_CODE (operands[1]) == SYMBOL_REF | |
6a4cee5f | 7663 | && (INTVAL (operands[3]) & CALL_NT_DLLIMPORT) != 0) |
7509c759 MM |
7664 | { |
7665 | operands[1] = rs6000_dll_import_ref (operands[1]); | |
7666 | operands[3] = GEN_INT ((int)CALL_NORMAL); | |
7667 | } | |
7668 | ||
6a4cee5f MM |
7669 | if (GET_CODE (operands[1]) != SYMBOL_REF |
7670 | || (INTVAL (operands[3]) & CALL_LONG) != 0) | |
1fd4e8c1 | 7671 | { |
6756293c | 7672 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
7673 | operands[1] = rs6000_longcall_ref (operands[1]); |
7674 | ||
c81bebd7 | 7675 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS) |
b6c9286a MM |
7676 | emit_call_insn (gen_call_value_indirect_sysv (operands[0], operands[1], |
7677 | operands[2], operands[3])); | |
7678 | else | |
7679 | { | |
39403d82 | 7680 | rtx toc_reg = gen_rtx_REG (Pmode, 2); |
b6c9286a | 7681 | rtx toc_addr = RS6000_SAVE_TOC; |
1fd4e8c1 | 7682 | |
b6c9286a MM |
7683 | if (DEFAULT_ABI == ABI_AIX) |
7684 | { | |
7685 | /* AIX function pointers are really pointers to a three word area */ | |
39403d82 | 7686 | rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); |
a260abc9 DE |
7687 | emit_call_insn (TARGET_32BIT |
7688 | ? gen_call_value_indirect_aix32 (operands[0], | |
7689 | force_reg (Pmode, operands[1]), | |
7690 | operands[2], operands[3], | |
7691 | toc_addr, toc_reg, static_chain) | |
7692 | : gen_call_value_indirect_aix64 (operands[0], | |
7693 | force_reg (Pmode, operands[1]), | |
7694 | operands[2], operands[3], | |
7695 | toc_addr, toc_reg, static_chain)); | |
b6c9286a MM |
7696 | } |
7697 | else if (DEFAULT_ABI == ABI_NT) | |
7698 | { | |
7699 | /* NT function pointers are really pointers to a two word area */ | |
7700 | emit_call_insn (gen_call_value_indirect_nt (operands[0], | |
7701 | force_reg (Pmode, operands[1]), | |
7702 | operands[2], operands[3], | |
7703 | toc_addr, toc_reg)); | |
7704 | } | |
7705 | else | |
7706 | abort (); | |
7707 | } | |
7708 | DONE; | |
1fd4e8c1 RK |
7709 | } |
7710 | }") | |
7711 | ||
04780ee7 | 7712 | ;; Call to function in current module. No TOC pointer reload needed. |
4697a36c MM |
7713 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
7714 | ;; either the function was not prototyped, or it was prototyped as a | |
7715 | ;; variable argument function. It is > 0 if FP registers were passed | |
7716 | ;; and < 0 if they were not. | |
04780ee7 | 7717 | |
a260abc9 | 7718 | (define_insn "*call_local32" |
4697a36c MM |
7719 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
7720 | (match_operand 1 "" "g,g")) | |
7721 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
7722 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 7723 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
7724 | "* |
7725 | { | |
6a4cee5f MM |
7726 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
7727 | output_asm_insn (\"crxor 6,6,6\", operands); | |
7728 | ||
7729 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
7730 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 7731 | |
a226df46 | 7732 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 7733 | }" |
b7ff3d82 DE |
7734 | [(set_attr "type" "branch") |
7735 | (set_attr "length" "4,8")]) | |
04780ee7 | 7736 | |
a260abc9 DE |
7737 | (define_insn "*call_local64" |
7738 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
7739 | (match_operand 1 "" "g,g")) | |
7740 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
7741 | (clobber (match_scratch:SI 3 "=l,l"))] | |
7742 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
7743 | "* | |
7744 | { | |
7745 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
7746 | output_asm_insn (\"crxor 6,6,6\", operands); | |
7747 | ||
7748 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
7749 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7750 | ||
7751 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
7752 | }" | |
7753 | [(set_attr "type" "branch") | |
7754 | (set_attr "length" "4,8")]) | |
7755 | ||
7756 | (define_insn "*ret_call_local32" | |
7757 | [(set (match_operand 0 "" "=fg,fg") | |
7758 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
7759 | (match_operand 2 "" "g,g"))) | |
7760 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
7761 | (clobber (match_scratch:SI 4 "=l,l"))] | |
7762 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
7763 | "* | |
7764 | { | |
7765 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
7766 | output_asm_insn (\"crxor 6,6,6\", operands); | |
7767 | ||
7768 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
7769 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7770 | ||
7771 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
7772 | }" | |
7773 | [(set_attr "type" "branch") | |
7774 | (set_attr "length" "4,8")]) | |
7775 | ||
7776 | ||
7777 | (define_insn "*ret_call_local64" | |
7778 | [(set (match_operand 0 "" "=fg,fg") | |
7779 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
7780 | (match_operand 2 "" "g,g"))) | |
7781 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
7782 | (clobber (match_scratch:SI 4 "=l,l"))] | |
7783 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
7784 | "* | |
7785 | { | |
7786 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
7787 | output_asm_insn (\"crxor 6,6,6\", operands); | |
7788 | ||
7789 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
7790 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7791 | ||
7792 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
7793 | }" | |
7794 | [(set_attr "type" "branch") | |
7795 | (set_attr "length" "4,8")]) | |
7796 | ||
04780ee7 | 7797 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 7798 | ;; pointer (r2) after the call unless this is System V. |
4697a36c MM |
7799 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
7800 | ;; either the function was not prototyped, or it was prototyped as a | |
7801 | ;; variable argument function. It is > 0 if FP registers were passed | |
7802 | ;; and < 0 if they were not. | |
04780ee7 | 7803 | |
a260abc9 | 7804 | (define_insn "*call_nonlocal_aix32" |
b6c9286a MM |
7805 | [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s")) |
7806 | (match_operand 1 "" "fg,fg")) | |
7807 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
7808 | (clobber (match_scratch:SI 3 "=l,l"))] | |
6a4cee5f | 7809 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) |
5a19791c | 7810 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
911f679c MM |
7811 | "* |
7812 | { | |
b6c9286a | 7813 | /* Indirect calls should go through call_indirect */ |
0f07e76c | 7814 | if (GET_CODE (operands[0]) == REG) |
b6c9286a | 7815 | abort (); |
911f679c | 7816 | |
6a4cee5f MM |
7817 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
7818 | output_asm_insn (\"crxor 6,6,6\", operands); | |
7819 | ||
7820 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
7821 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 7822 | |
b6c9286a MM |
7823 | return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\"; |
7824 | }" | |
b7ff3d82 DE |
7825 | [(set_attr "type" "branch") |
7826 | (set_attr "length" "8,12")]) | |
59313e4e | 7827 | |
a260abc9 DE |
7828 | (define_insn "*call_nonlocal_aix64" |
7829 | [(call (mem:SI (match_operand:DI 0 "call_operand" "s,s")) | |
7830 | (match_operand 1 "" "fg,fg")) | |
7831 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
7832 | (clobber (match_scratch:SI 3 "=l,l"))] | |
7833 | "TARGET_64BIT && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) | |
7834 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
7835 | "* | |
7836 | { | |
7837 | /* Indirect calls should go through call_indirect */ | |
7838 | if (GET_CODE (operands[0]) == REG) | |
7839 | abort (); | |
7840 | ||
7841 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
7842 | output_asm_insn (\"crxor 6,6,6\", operands); | |
7843 | ||
7844 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
7845 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7846 | ||
7847 | return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\"; | |
7848 | }" | |
7849 | [(set_attr "type" "branch") | |
7850 | (set_attr "length" "8,12")]) | |
7851 | ||
7852 | (define_insn "*call_nonlocal_sysv" | |
b6c9286a MM |
7853 | [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s")) |
7854 | (match_operand 1 "" "fg,fg")) | |
7855 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
7856 | (clobber (match_scratch:SI 3 "=l,l"))] | |
c81bebd7 | 7857 | "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5a19791c | 7858 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
b6c9286a MM |
7859 | "* |
7860 | { | |
b6c9286a | 7861 | /* Indirect calls should go through call_indirect */ |
0f07e76c | 7862 | if (GET_CODE (operands[0]) == REG) |
b6c9286a | 7863 | abort (); |
59313e4e | 7864 | |
6a4cee5f MM |
7865 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
7866 | output_asm_insn (\"crxor 6,6,6\", operands); | |
7867 | ||
7868 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
7869 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 7870 | |
a226df46 | 7871 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\"; |
911f679c | 7872 | }" |
b7ff3d82 DE |
7873 | [(set_attr "type" "branch") |
7874 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 7875 | |
a260abc9 | 7876 | (define_insn "*ret_call_nonlocal_aix32" |
4697a36c | 7877 | [(set (match_operand 0 "" "=fg,fg") |
a260abc9 DE |
7878 | (call (mem:SI (match_operand:SI 1 "call_operand" "s,s")) |
7879 | (match_operand 2 "" "fg,fg"))) | |
4697a36c MM |
7880 | (use (match_operand:SI 3 "immediate_operand" "O,n")) |
7881 | (clobber (match_scratch:SI 4 "=l,l"))] | |
a260abc9 DE |
7882 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) |
7883 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
4697a36c MM |
7884 | "* |
7885 | { | |
a260abc9 DE |
7886 | /* This should be handled by call_value_indirect */ |
7887 | if (GET_CODE (operands[1]) == REG) | |
7888 | abort (); | |
7889 | ||
6a4cee5f MM |
7890 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
7891 | output_asm_insn (\"crxor 6,6,6\", operands); | |
7892 | ||
7893 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
7894 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 7895 | |
a260abc9 | 7896 | return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\"; |
4697a36c | 7897 | }" |
b7ff3d82 | 7898 | [(set_attr "type" "branch") |
a260abc9 | 7899 | (set_attr "length" "8,12")]) |
04780ee7 | 7900 | |
a260abc9 | 7901 | (define_insn "*ret_call_nonlocal_aix64" |
b6c9286a | 7902 | [(set (match_operand 0 "" "=fg,fg") |
a260abc9 | 7903 | (call (mem:SI (match_operand:DI 1 "call_operand" "s,s")) |
b6c9286a MM |
7904 | (match_operand 2 "" "fg,fg"))) |
7905 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
7906 | (clobber (match_scratch:SI 4 "=l,l"))] | |
a260abc9 | 7907 | "TARGET_64BIT && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) |
5a19791c | 7908 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
911f679c MM |
7909 | "* |
7910 | { | |
b6c9286a | 7911 | /* This should be handled by call_value_indirect */ |
59313e4e | 7912 | if (GET_CODE (operands[1]) == REG) |
b6c9286a MM |
7913 | abort (); |
7914 | ||
6a4cee5f MM |
7915 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
7916 | output_asm_insn (\"crxor 6,6,6\", operands); | |
7917 | ||
7918 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
7919 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 7920 | |
b6c9286a MM |
7921 | return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\"; |
7922 | }" | |
b7ff3d82 DE |
7923 | [(set_attr "type" "branch") |
7924 | (set_attr "length" "8,12")]) | |
b6c9286a | 7925 | |
a260abc9 | 7926 | (define_insn "*ret_call_nonlocal_sysv" |
b6c9286a MM |
7927 | [(set (match_operand 0 "" "=fg,fg") |
7928 | (call (mem:SI (match_operand:SI 1 "call_operand" "s,s")) | |
7929 | (match_operand 2 "" "fg,fg"))) | |
7930 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
7931 | (clobber (match_scratch:SI 4 "=l,l"))] | |
c81bebd7 | 7932 | "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5a19791c | 7933 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
b6c9286a MM |
7934 | "* |
7935 | { | |
b6c9286a | 7936 | /* This should be handled by call_value_indirect */ |
59313e4e | 7937 | if (GET_CODE (operands[1]) == REG) |
b6c9286a | 7938 | abort (); |
59313e4e | 7939 | |
6a4cee5f MM |
7940 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
7941 | output_asm_insn (\"crxor 6,6,6\", operands); | |
7942 | ||
7943 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
7944 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 7945 | |
a226df46 | 7946 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\"; |
911f679c | 7947 | }" |
b7ff3d82 DE |
7948 | [(set_attr "type" "branch") |
7949 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
7950 | |
7951 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
7952 | (define_expand "untyped_call" |
7953 | [(parallel [(call (match_operand 0 "" "") | |
7954 | (const_int 0)) | |
7955 | (match_operand 1 "" "") | |
7956 | (match_operand 2 "" "")])] | |
7957 | "" | |
7958 | " | |
7959 | { | |
7960 | int i; | |
7961 | ||
4697a36c | 7962 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
7963 | |
7964 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
7965 | { | |
7966 | rtx set = XVECEXP (operands[2], 0, i); | |
7967 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
7968 | } | |
7969 | ||
7970 | /* The optimizer does not know that the call sets the function value | |
7971 | registers we stored in the result block. We avoid problems by | |
7972 | claiming that all hard registers are used and clobbered at this | |
7973 | point. */ | |
7974 | emit_insn (gen_blockage ()); | |
7975 | ||
7976 | DONE; | |
7977 | }") | |
7978 | ||
7979 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
7980 | ;; all of memory. This blocks insns from being moved across this point. | |
7981 | ||
7982 | (define_insn "blockage" | |
7983 | [(unspec_volatile [(const_int 0)] 0)] | |
7984 | "" | |
7985 | "") | |
4697a36c | 7986 | |
766a866c MM |
7987 | ;; V.4 specific code to initialize the PIC register |
7988 | ||
7989 | (define_insn "init_v4_pic" | |
7990 | [(set (match_operand:SI 0 "register_operand" "=l") | |
7991 | (unspec [(const_int 0)] 7))] | |
c81bebd7 | 7992 | "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS" |
eaf1bcf1 | 7993 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
63d7d7a1 MM |
7994 | [(set_attr "type" "branch") |
7995 | (set_attr "length" "4")]) | |
766a866c | 7996 | |
1fd4e8c1 RK |
7997 | \f |
7998 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 7999 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
8000 | ;; |
8001 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
8002 | ;; insns, and branches. We store the operands of compares until we see | |
8003 | ;; how it is used. | |
8004 | (define_expand "cmpsi" | |
8005 | [(set (cc0) | |
cd2b37d9 | 8006 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8007 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
8008 | "" | |
8009 | " | |
8010 | { | |
8011 | /* Take care of the possibility that operands[1] might be negative but | |
8012 | this might be a logical operation. That insn doesn't exist. */ | |
8013 | if (GET_CODE (operands[1]) == CONST_INT | |
8014 | && INTVAL (operands[1]) < 0) | |
8015 | operands[1] = force_reg (SImode, operands[1]); | |
8016 | ||
8017 | rs6000_compare_op0 = operands[0]; | |
8018 | rs6000_compare_op1 = operands[1]; | |
8019 | rs6000_compare_fp_p = 0; | |
8020 | DONE; | |
8021 | }") | |
8022 | ||
266eb58a DE |
8023 | (define_expand "cmpdi" |
8024 | [(set (cc0) | |
8025 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
8026 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
8027 | "TARGET_POWERPC64" | |
8028 | " | |
8029 | { | |
8030 | /* Take care of the possibility that operands[1] might be negative but | |
8031 | this might be a logical operation. That insn doesn't exist. */ | |
8032 | if (GET_CODE (operands[1]) == CONST_INT | |
8033 | && INTVAL (operands[1]) < 0) | |
8034 | operands[1] = force_reg (DImode, operands[1]); | |
8035 | ||
8036 | rs6000_compare_op0 = operands[0]; | |
8037 | rs6000_compare_op1 = operands[1]; | |
8038 | rs6000_compare_fp_p = 0; | |
8039 | DONE; | |
8040 | }") | |
8041 | ||
1fd4e8c1 | 8042 | (define_expand "cmpsf" |
cd2b37d9 RK |
8043 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
8044 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 8045 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
8046 | " |
8047 | { | |
8048 | rs6000_compare_op0 = operands[0]; | |
8049 | rs6000_compare_op1 = operands[1]; | |
8050 | rs6000_compare_fp_p = 1; | |
8051 | DONE; | |
8052 | }") | |
8053 | ||
8054 | (define_expand "cmpdf" | |
cd2b37d9 RK |
8055 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
8056 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 8057 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
8058 | " |
8059 | { | |
8060 | rs6000_compare_op0 = operands[0]; | |
8061 | rs6000_compare_op1 = operands[1]; | |
8062 | rs6000_compare_fp_p = 1; | |
8063 | DONE; | |
8064 | }") | |
8065 | ||
8066 | (define_expand "beq" | |
8067 | [(set (match_dup 2) (match_dup 1)) | |
8068 | (set (pc) | |
8069 | (if_then_else (eq (match_dup 2) | |
8070 | (const_int 0)) | |
8071 | (label_ref (match_operand 0 "" "")) | |
8072 | (pc)))] | |
8073 | "" | |
8074 | " | |
8075 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8076 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8077 | rs6000_compare_op0, rs6000_compare_op1); |
8078 | operands[2] = gen_reg_rtx (mode); | |
8079 | }") | |
8080 | ||
8081 | (define_expand "bne" | |
8082 | [(set (match_dup 2) (match_dup 1)) | |
8083 | (set (pc) | |
8084 | (if_then_else (ne (match_dup 2) | |
8085 | (const_int 0)) | |
8086 | (label_ref (match_operand 0 "" "")) | |
8087 | (pc)))] | |
8088 | "" | |
8089 | " | |
8090 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8091 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8092 | rs6000_compare_op0, rs6000_compare_op1); |
8093 | operands[2] = gen_reg_rtx (mode); | |
8094 | }") | |
8095 | ||
8096 | (define_expand "blt" | |
8097 | [(set (match_dup 2) (match_dup 1)) | |
8098 | (set (pc) | |
8099 | (if_then_else (lt (match_dup 2) | |
8100 | (const_int 0)) | |
8101 | (label_ref (match_operand 0 "" "")) | |
8102 | (pc)))] | |
8103 | "" | |
8104 | " | |
8105 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8106 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8107 | rs6000_compare_op0, rs6000_compare_op1); |
8108 | operands[2] = gen_reg_rtx (mode); | |
8109 | }") | |
8110 | ||
8111 | (define_expand "bgt" | |
8112 | [(set (match_dup 2) (match_dup 1)) | |
8113 | (set (pc) | |
8114 | (if_then_else (gt (match_dup 2) | |
8115 | (const_int 0)) | |
8116 | (label_ref (match_operand 0 "" "")) | |
8117 | (pc)))] | |
8118 | "" | |
8119 | " | |
8120 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8121 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8122 | rs6000_compare_op0, rs6000_compare_op1); |
8123 | operands[2] = gen_reg_rtx (mode); | |
8124 | }") | |
8125 | ||
8126 | (define_expand "ble" | |
8127 | [(set (match_dup 2) (match_dup 1)) | |
8128 | (set (pc) | |
8129 | (if_then_else (le (match_dup 2) | |
8130 | (const_int 0)) | |
8131 | (label_ref (match_operand 0 "" "")) | |
8132 | (pc)))] | |
8133 | "" | |
8134 | " | |
8135 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8136 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8137 | rs6000_compare_op0, rs6000_compare_op1); |
8138 | operands[2] = gen_reg_rtx (mode); | |
8139 | }") | |
8140 | ||
8141 | (define_expand "bge" | |
8142 | [(set (match_dup 2) (match_dup 1)) | |
8143 | (set (pc) | |
8144 | (if_then_else (ge (match_dup 2) | |
8145 | (const_int 0)) | |
8146 | (label_ref (match_operand 0 "" "")) | |
8147 | (pc)))] | |
8148 | "" | |
8149 | " | |
8150 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8151 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8152 | rs6000_compare_op0, rs6000_compare_op1); |
8153 | operands[2] = gen_reg_rtx (mode); | |
8154 | }") | |
8155 | ||
8156 | (define_expand "bgtu" | |
8157 | [(set (match_dup 2) (match_dup 1)) | |
8158 | (set (pc) | |
8159 | (if_then_else (gtu (match_dup 2) | |
8160 | (const_int 0)) | |
8161 | (label_ref (match_operand 0 "" "")) | |
8162 | (pc)))] | |
8163 | "" | |
8164 | " | |
39403d82 | 8165 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8166 | rs6000_compare_op0, rs6000_compare_op1); |
8167 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8168 | }") | |
8169 | ||
8170 | (define_expand "bltu" | |
8171 | [(set (match_dup 2) (match_dup 1)) | |
8172 | (set (pc) | |
8173 | (if_then_else (ltu (match_dup 2) | |
8174 | (const_int 0)) | |
8175 | (label_ref (match_operand 0 "" "")) | |
8176 | (pc)))] | |
8177 | "" | |
8178 | " | |
39403d82 | 8179 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8180 | rs6000_compare_op0, rs6000_compare_op1); |
8181 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8182 | }") | |
8183 | ||
8184 | (define_expand "bgeu" | |
8185 | [(set (match_dup 2) (match_dup 1)) | |
8186 | (set (pc) | |
8187 | (if_then_else (geu (match_dup 2) | |
8188 | (const_int 0)) | |
8189 | (label_ref (match_operand 0 "" "")) | |
8190 | (pc)))] | |
8191 | "" | |
8192 | " | |
39403d82 | 8193 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8194 | rs6000_compare_op0, rs6000_compare_op1); |
8195 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8196 | }") | |
8197 | ||
8198 | (define_expand "bleu" | |
8199 | [(set (match_dup 2) (match_dup 1)) | |
8200 | (set (pc) | |
8201 | (if_then_else (leu (match_dup 2) | |
8202 | (const_int 0)) | |
8203 | (label_ref (match_operand 0 "" "")) | |
8204 | (pc)))] | |
8205 | "" | |
8206 | " | |
39403d82 | 8207 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8208 | rs6000_compare_op0, rs6000_compare_op1); |
8209 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8210 | }") | |
8211 | ||
8212 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. | |
8213 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
8214 | ;; with an scc insns. However, due to the order that combine see the | |
8215 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
8216 | ;; the cases we don't want to handle. | |
8217 | (define_expand "seq" | |
8218 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8219 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8220 | (eq:SI (match_dup 2) (const_int 0)))] |
8221 | "" | |
8222 | " | |
8223 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8224 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8225 | rs6000_compare_op0, rs6000_compare_op1); |
8226 | operands[2] = gen_reg_rtx (mode); | |
8227 | }") | |
8228 | ||
8229 | (define_expand "sne" | |
8230 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8231 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8232 | (ne:SI (match_dup 2) (const_int 0)))] |
8233 | "" | |
8234 | " | |
8235 | { if (! rs6000_compare_fp_p) | |
8236 | FAIL; | |
8237 | ||
39403d82 | 8238 | operands[1] = gen_rtx_COMPARE (CCFPmode, |
1fd4e8c1 RK |
8239 | rs6000_compare_op0, rs6000_compare_op1); |
8240 | operands[2] = gen_reg_rtx (CCFPmode); | |
8241 | }") | |
8242 | ||
8243 | ;; A > 0 is best done using the portable sequence, so fail in that case. | |
8244 | (define_expand "sgt" | |
8245 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8246 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8247 | (gt:SI (match_dup 2) (const_int 0)))] |
8248 | "" | |
8249 | " | |
8250 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
8251 | ||
8252 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
8253 | FAIL; | |
8254 | ||
39403d82 | 8255 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8256 | rs6000_compare_op0, rs6000_compare_op1); |
8257 | operands[2] = gen_reg_rtx (mode); | |
8258 | }") | |
8259 | ||
8260 | ;; A < 0 is best done in the portable way for A an integer. | |
8261 | (define_expand "slt" | |
8262 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8263 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8264 | (lt:SI (match_dup 2) (const_int 0)))] |
8265 | "" | |
8266 | " | |
8267 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
8268 | ||
8269 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
8270 | FAIL; | |
8271 | ||
39403d82 | 8272 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8273 | rs6000_compare_op0, rs6000_compare_op1); |
8274 | operands[2] = gen_reg_rtx (mode); | |
8275 | }") | |
8276 | ||
8277 | (define_expand "sge" | |
8278 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8279 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8280 | (ge:SI (match_dup 2) (const_int 0)))] |
8281 | "" | |
8282 | " | |
8283 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8284 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8285 | rs6000_compare_op0, rs6000_compare_op1); |
8286 | operands[2] = gen_reg_rtx (mode); | |
8287 | }") | |
8288 | ||
8289 | ;; A <= 0 is best done the portable way for A an integer. | |
8290 | (define_expand "sle" | |
8291 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8292 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8293 | (le:SI (match_dup 2) (const_int 0)))] |
8294 | "" | |
8295 | " | |
8296 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
8297 | ||
8298 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
8299 | FAIL; | |
8300 | ||
39403d82 | 8301 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8302 | rs6000_compare_op0, rs6000_compare_op1); |
8303 | operands[2] = gen_reg_rtx (mode); | |
8304 | }") | |
8305 | ||
8306 | (define_expand "sgtu" | |
8307 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8308 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8309 | (gtu:SI (match_dup 2) (const_int 0)))] |
8310 | "" | |
8311 | " | |
39403d82 | 8312 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8313 | rs6000_compare_op0, rs6000_compare_op1); |
8314 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8315 | }") | |
8316 | ||
8317 | (define_expand "sltu" | |
8318 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8319 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8320 | (ltu:SI (match_dup 2) (const_int 0)))] |
8321 | "" | |
8322 | " | |
39403d82 | 8323 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8324 | rs6000_compare_op0, rs6000_compare_op1); |
8325 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8326 | }") | |
8327 | ||
8328 | (define_expand "sgeu" | |
8329 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8330 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8331 | (geu:SI (match_dup 2) (const_int 0)))] |
8332 | "" | |
8333 | " | |
39403d82 | 8334 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8335 | rs6000_compare_op0, rs6000_compare_op1); |
8336 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8337 | }") | |
8338 | ||
8339 | (define_expand "sleu" | |
8340 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8341 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8342 | (leu:SI (match_dup 2) (const_int 0)))] |
8343 | "" | |
8344 | " | |
39403d82 | 8345 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8346 | rs6000_compare_op0, rs6000_compare_op1); |
8347 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8348 | }") | |
8349 | \f | |
8350 | ;; Here are the actual compare insns. | |
8351 | (define_insn "" | |
8352 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
cd2b37d9 | 8353 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
8354 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
8355 | "" | |
7f340546 | 8356 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
1fd4e8c1 RK |
8357 | [(set_attr "type" "compare")]) |
8358 | ||
266eb58a DE |
8359 | (define_insn "" |
8360 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
8361 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
8362 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
8363 | "TARGET_POWERPC64" | |
8364 | "cmpd%I2 %0,%1,%2" | |
8365 | [(set_attr "type" "compare")]) | |
8366 | ||
f357808b RK |
8367 | ;; If we are comparing a register for equality with a large constant, |
8368 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
8369 | ;; register for the result of the XOR. | |
8370 | ||
8371 | (define_split | |
8372 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 8373 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 8374 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 8375 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
8376 | "find_single_use (operands[0], insn, 0) |
8377 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
8378 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
8379 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
8380 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
8381 | " | |
8382 | { | |
8383 | /* Get the constant we are comparing against, C, and see what it looks like | |
8384 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
8385 | with C to get the sign-extended value. */ | |
8386 | ||
8387 | int c = INTVAL (operands[2]); | |
8388 | int sextc = (c << 16) >> 16; | |
8389 | int xorv = c ^ sextc; | |
8390 | ||
89e9f3a8 MM |
8391 | operands[4] = GEN_INT (xorv); |
8392 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
8393 | }") |
8394 | ||
1fd4e8c1 RK |
8395 | (define_insn "" |
8396 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") | |
cd2b37d9 | 8397 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
8398 | (match_operand:SI 2 "reg_or_u_short_operand" "rI")))] |
8399 | "" | |
7f340546 | 8400 | "{cmpl%I2|cmplw%I2} %0,%1,%W2" |
1fd4e8c1 RK |
8401 | [(set_attr "type" "compare")]) |
8402 | ||
266eb58a DE |
8403 | (define_insn "" |
8404 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") | |
8405 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
8406 | (match_operand:DI 2 "reg_or_u_short_operand" "rI")))] | |
8407 | "" | |
8408 | "cmpld%I2 %0,%1,%W2" | |
8409 | [(set_attr "type" "compare")]) | |
8410 | ||
1fd4e8c1 RK |
8411 | ;; The following two insns don't exist as single insns, but if we provide |
8412 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
8413 | ;; of the required delay between a compare and branch. We generate code for | |
8414 | ;; them by splitting. | |
8415 | ||
8416 | (define_insn "" | |
8417 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 8418 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 8419 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 8420 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
8421 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
8422 | "" | |
baf97f86 RK |
8423 | "#" |
8424 | [(set_attr "length" "8")]) | |
7e69e155 | 8425 | |
1fd4e8c1 RK |
8426 | (define_insn "" |
8427 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 8428 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 8429 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 8430 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
8431 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
8432 | "" | |
baf97f86 RK |
8433 | "#" |
8434 | [(set_attr "length" "8")]) | |
7e69e155 | 8435 | |
1fd4e8c1 RK |
8436 | (define_split |
8437 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 8438 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 8439 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 8440 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8441 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
8442 | "" | |
8443 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
8444 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
8445 | ||
8446 | (define_split | |
8447 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 8448 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 8449 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 8450 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8451 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
8452 | "" | |
8453 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
8454 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
8455 | ||
8456 | (define_insn "" | |
8457 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
cd2b37d9 RK |
8458 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
8459 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 8460 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
8461 | "fcmpu %0,%1,%2" |
8462 | [(set_attr "type" "fpcompare")]) | |
8463 | ||
8464 | (define_insn "" | |
8465 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
cd2b37d9 RK |
8466 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
8467 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 8468 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
8469 | "fcmpu %0,%1,%2" |
8470 | [(set_attr "type" "fpcompare")]) | |
8471 | \f | |
8472 | ;; Now we have the scc insns. We can do some combinations because of the | |
8473 | ;; way the machine works. | |
8474 | ;; | |
8475 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
8476 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
8477 | ;; cases the insns below which don't use an intermediate CR field will | |
8478 | ;; be used instead. | |
1fd4e8c1 | 8479 | (define_insn "" |
cd2b37d9 | 8480 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
8481 | (match_operator:SI 1 "scc_comparison_operator" |
8482 | [(match_operand 2 "cc_reg_operand" "y") | |
8483 | (const_int 0)]))] | |
8484 | "" | |
ca7f5001 | 8485 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" |
b19003d8 | 8486 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
8487 | |
8488 | (define_insn "" | |
8489 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
8490 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
8491 | [(match_operand 2 "cc_reg_operand" "y") | |
8492 | (const_int 0)]) | |
8493 | (const_int 0))) | |
cd2b37d9 | 8494 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
8495 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
8496 | "" | |
ca7f5001 | 8497 | "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1" |
b19003d8 RK |
8498 | [(set_attr "type" "delayed_compare") |
8499 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
8500 | |
8501 | (define_insn "" | |
cd2b37d9 | 8502 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
8503 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
8504 | [(match_operand 2 "cc_reg_operand" "y") | |
8505 | (const_int 0)]) | |
8506 | (match_operand:SI 3 "const_int_operand" "n")))] | |
8507 | "" | |
8508 | "* | |
8509 | { | |
8510 | int is_bit = ccr_bit (operands[1], 1); | |
8511 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
8512 | int count; | |
8513 | ||
8514 | if (is_bit >= put_bit) | |
8515 | count = is_bit - put_bit; | |
8516 | else | |
8517 | count = 32 - (put_bit - is_bit); | |
8518 | ||
89e9f3a8 MM |
8519 | operands[4] = GEN_INT (count); |
8520 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 8521 | |
ca7f5001 | 8522 | return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 RK |
8523 | }" |
8524 | [(set_attr "length" "12")]) | |
1fd4e8c1 RK |
8525 | |
8526 | (define_insn "" | |
8527 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
8528 | (compare:CC | |
8529 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
8530 | [(match_operand 2 "cc_reg_operand" "y") | |
8531 | (const_int 0)]) | |
8532 | (match_operand:SI 3 "const_int_operand" "n")) | |
8533 | (const_int 0))) | |
cd2b37d9 | 8534 | (set (match_operand:SI 4 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
8535 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
8536 | (match_dup 3)))] | |
8537 | "" | |
8538 | "* | |
8539 | { | |
8540 | int is_bit = ccr_bit (operands[1], 1); | |
8541 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
8542 | int count; | |
8543 | ||
8544 | if (is_bit >= put_bit) | |
8545 | count = is_bit - put_bit; | |
8546 | else | |
8547 | count = 32 - (put_bit - is_bit); | |
8548 | ||
89e9f3a8 MM |
8549 | operands[5] = GEN_INT (count); |
8550 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 8551 | |
ca7f5001 | 8552 | return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 8553 | }" |
b19003d8 RK |
8554 | [(set_attr "type" "delayed_compare") |
8555 | (set_attr "length" "12")]) | |
1fd4e8c1 | 8556 | |
c5defebb RK |
8557 | ;; If we are comparing the result of two comparisons, this can be done |
8558 | ;; using creqv or crxor. | |
8559 | ||
8560 | (define_insn "" | |
8561 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
8562 | (compare:CCEQ (match_operator 1 "scc_comparison_operator" | |
8563 | [(match_operand 2 "cc_reg_operand" "y") | |
8564 | (const_int 0)]) | |
8565 | (match_operator 3 "scc_comparison_operator" | |
8566 | [(match_operand 4 "cc_reg_operand" "y") | |
8567 | (const_int 0)])))] | |
8568 | "REGNO (operands[2]) != REGNO (operands[4])" | |
8569 | "* | |
8570 | { | |
8571 | enum rtx_code code1, code2; | |
8572 | ||
8573 | code1 = GET_CODE (operands[1]); | |
8574 | code2 = GET_CODE (operands[3]); | |
8575 | ||
8576 | if ((code1 == EQ || code1 == LT || code1 == GT | |
8577 | || code1 == LTU || code1 == GTU | |
8578 | || (code1 != NE && GET_MODE (operands[2]) == CCFPmode)) | |
8579 | != | |
8580 | (code2 == EQ || code2 == LT || code2 == GT | |
8581 | || code2 == LTU || code2 == GTU | |
8582 | || (code2 != NE && GET_MODE (operands[4]) == CCFPmode))) | |
8583 | return \"%C1%C3crxor %E0,%j1,%j3\"; | |
8584 | else | |
8585 | return \"%C1%C3creqv %E0,%j1,%j3\"; | |
b19003d8 RK |
8586 | }" |
8587 | [(set_attr "length" "12")]) | |
c5defebb RK |
8588 | |
8589 | ;; There is a 3 cycle delay between consecutive mfcr instructions | |
8590 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
8591 | ||
8592 | (define_peephole | |
cd2b37d9 | 8593 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
8594 | (match_operator:SI 1 "scc_comparison_operator" |
8595 | [(match_operand 2 "cc_reg_operand" "y") | |
8596 | (const_int 0)])) | |
cd2b37d9 | 8597 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
8598 | (match_operator:SI 4 "scc_comparison_operator" |
8599 | [(match_operand 5 "cc_reg_operand" "y") | |
8600 | (const_int 0)]))] | |
8601 | "REGNO (operands[2]) != REGNO (operands[5])" | |
ca7f5001 | 8602 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b19003d8 | 8603 | [(set_attr "length" "20")]) |
c5defebb | 8604 | |
1fd4e8c1 RK |
8605 | ;; There are some scc insns that can be done directly, without a compare. |
8606 | ;; These are faster because they don't involve the communications between | |
8607 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
8608 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
8609 | ;; | |
8610 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
8611 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
8612 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
8613 | ;; cases where it is no more expensive than (neg (scc ..)). | |
8614 | ||
8615 | ;; Have reload force a constant into a register for the simple insns that | |
8616 | ;; otherwise won't accept constants. We do this because it is faster than | |
8617 | ;; the cmp/mfcr sequence we would otherwise generate. | |
8618 | ||
8619 | (define_insn "" | |
cd2b37d9 RK |
8620 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
8621 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
1fd4e8c1 RK |
8622 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))) |
8623 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] | |
8624 | "" | |
8625 | "@ | |
ca7f5001 | 8626 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 8627 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
8628 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
8629 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
8630 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 8631 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 8632 | |
a260abc9 DE |
8633 | (define_insn "" |
8634 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
8635 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
8636 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
8637 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
8638 | "TARGET_POWERPC64" | |
8639 | "@ | |
8640 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
8641 | subfic %3,%1,0\;adde %0,%3,%1 | |
8642 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
8643 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
8644 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
8645 | [(set_attr "length" "12,8,12,12,12")]) | |
8646 | ||
1fd4e8c1 | 8647 | (define_insn "" |
29ae5b89 | 8648 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") |
7e69e155 | 8649 | (compare:CC |
29ae5b89 JL |
8650 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
8651 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) | |
1fd4e8c1 | 8652 | (const_int 0))) |
29ae5b89 | 8653 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
1fd4e8c1 | 8654 | (eq:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 8655 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
1fd4e8c1 RK |
8656 | "" |
8657 | "@ | |
ca7f5001 RK |
8658 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
8659 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
8660 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
8661 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
29ae5b89 | 8662 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0" |
b19003d8 | 8663 | [(set_attr "type" "compare") |
29ae5b89 | 8664 | (set_attr "length" "12,8,12,12,12")]) |
b19003d8 | 8665 | |
a260abc9 | 8666 | (define_insn "" |
29ae5b89 | 8667 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") |
a260abc9 | 8668 | (compare:CC |
29ae5b89 JL |
8669 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") |
8670 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")) | |
a260abc9 | 8671 | (const_int 0))) |
29ae5b89 | 8672 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") |
a260abc9 | 8673 | (eq:DI (match_dup 1) (match_dup 2))) |
29ae5b89 | 8674 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] |
a260abc9 DE |
8675 | "TARGET_POWERPC64" |
8676 | "@ | |
8677 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
8678 | subfic %3,%1,0\;adde. %0,%3,%1 | |
8679 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
8680 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
29ae5b89 | 8681 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0" |
a260abc9 | 8682 | [(set_attr "type" "compare") |
29ae5b89 | 8683 | (set_attr "length" "12,8,12,12,12")]) |
a260abc9 | 8684 | |
b19003d8 RK |
8685 | ;; We have insns of the form shown by the first define_insn below. If |
8686 | ;; there is something inside the comparison operation, we must split it. | |
8687 | (define_split | |
8688 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
8689 | (plus:SI (match_operator 1 "comparison_operator" | |
8690 | [(match_operand:SI 2 "" "") | |
8691 | (match_operand:SI 3 | |
8692 | "reg_or_cint_operand" "")]) | |
8693 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
8694 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
8695 | "! gpc_reg_operand (operands[2], SImode)" | |
8696 | [(set (match_dup 5) (match_dup 2)) | |
8697 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
8698 | (match_dup 4)))]) | |
1fd4e8c1 RK |
8699 | |
8700 | (define_insn "" | |
cd2b37d9 RK |
8701 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
8702 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
1fd4e8c1 | 8703 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) |
cd2b37d9 | 8704 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) |
1fd4e8c1 RK |
8705 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
8706 | "" | |
8707 | "@ | |
ca7f5001 RK |
8708 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
8709 | {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3 | |
8710 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
8711 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
d9d934ef | 8712 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" |
b19003d8 | 8713 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
8714 | |
8715 | (define_insn "" | |
29ae5b89 | 8716 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x") |
7e69e155 | 8717 | (compare:CC |
1fd4e8c1 | 8718 | (plus:SI |
29ae5b89 JL |
8719 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
8720 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) | |
8721 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) | |
1fd4e8c1 | 8722 | (const_int 0))) |
29ae5b89 | 8723 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
1fd4e8c1 RK |
8724 | "" |
8725 | "@ | |
ca7f5001 | 8726 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 8727 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
8728 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
8729 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
29ae5b89 | 8730 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" |
b19003d8 | 8731 | [(set_attr "type" "compare") |
29ae5b89 | 8732 | (set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
8733 | |
8734 | (define_insn "" | |
29ae5b89 | 8735 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x") |
7e69e155 | 8736 | (compare:CC |
1fd4e8c1 | 8737 | (plus:SI |
29ae5b89 JL |
8738 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
8739 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) | |
8740 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) | |
1fd4e8c1 | 8741 | (const_int 0))) |
29ae5b89 | 8742 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
1fd4e8c1 | 8743 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 8744 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
1fd4e8c1 RK |
8745 | "" |
8746 | "@ | |
ca7f5001 | 8747 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
19378cf8 | 8748 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3 |
ca7f5001 RK |
8749 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
8750 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
29ae5b89 | 8751 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" |
b19003d8 | 8752 | [(set_attr "type" "compare") |
29ae5b89 | 8753 | (set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
8754 | |
8755 | (define_insn "" | |
cd2b37d9 | 8756 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 8757 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
1fd4e8c1 RK |
8758 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))] |
8759 | "" | |
8760 | "@ | |
ca7f5001 RK |
8761 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
8762 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
8763 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
8764 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
8765 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 8766 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 8767 | |
ea9be077 MM |
8768 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
8769 | ;; since it nabs/sr is just as fast. | |
463b558b | 8770 | (define_insn "*ne0" |
b4e95693 | 8771 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
8772 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
8773 | (const_int 31))) | |
8774 | (clobber (match_scratch:SI 2 "=&r"))] | |
8775 | "!TARGET_POWER" | |
8776 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" | |
8777 | [(set_attr "length" "8")]) | |
8778 | ||
a260abc9 DE |
8779 | (define_insn "" |
8780 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8781 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
8782 | (const_int 63))) | |
8783 | (clobber (match_scratch:DI 2 "=&r"))] | |
8784 | "TARGET_POWERPC64" | |
8785 | "addic %2,%1,-1\;subfe %0,%2,%1" | |
8786 | [(set_attr "length" "8")]) | |
8787 | ||
1fd4e8c1 RK |
8788 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
8789 | (define_insn "" | |
cd2b37d9 | 8790 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 8791 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 8792 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 8793 | (const_int 31)) |
cd2b37d9 | 8794 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
8795 | (clobber (match_scratch:SI 3 "=&r"))] |
8796 | "" | |
ca7f5001 | 8797 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 8798 | [(set_attr "length" "8")]) |
1fd4e8c1 | 8799 | |
a260abc9 DE |
8800 | (define_insn "" |
8801 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8802 | (plus:DI (lshiftrt:DI | |
8803 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
8804 | (const_int 63)) | |
8805 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
8806 | (clobber (match_scratch:DI 3 "=&r"))] | |
8807 | "TARGET_POWERPC64" | |
8808 | "addic %3,%1,-1\;addze %0,%2" | |
8809 | [(set_attr "length" "8")]) | |
8810 | ||
1fd4e8c1 | 8811 | (define_insn "" |
29ae5b89 | 8812 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
8813 | (compare:CC |
8814 | (plus:SI (lshiftrt:SI | |
29ae5b89 | 8815 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 8816 | (const_int 31)) |
29ae5b89 | 8817 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 8818 | (const_int 0))) |
29ae5b89 | 8819 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 8820 | "" |
29ae5b89 | 8821 | "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2" |
b19003d8 | 8822 | [(set_attr "type" "compare") |
29ae5b89 | 8823 | (set_attr "length" "8")]) |
1fd4e8c1 | 8824 | |
a260abc9 | 8825 | (define_insn "" |
29ae5b89 | 8826 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
a260abc9 DE |
8827 | (compare:CC |
8828 | (plus:DI (lshiftrt:DI | |
29ae5b89 | 8829 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) |
a260abc9 | 8830 | (const_int 63)) |
29ae5b89 | 8831 | (match_operand:DI 2 "gpc_reg_operand" "r")) |
a260abc9 | 8832 | (const_int 0))) |
29ae5b89 | 8833 | (clobber (match_scratch:DI 3 "=&r"))] |
a260abc9 | 8834 | "TARGET_POWERPC64" |
29ae5b89 | 8835 | "addic %3,%1,-1\;addze. %3,%2" |
a260abc9 | 8836 | [(set_attr "type" "compare") |
29ae5b89 | 8837 | (set_attr "length" "8")]) |
a260abc9 | 8838 | |
1fd4e8c1 | 8839 | (define_insn "" |
29ae5b89 | 8840 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
8841 | (compare:CC |
8842 | (plus:SI (lshiftrt:SI | |
29ae5b89 | 8843 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 8844 | (const_int 31)) |
29ae5b89 | 8845 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 8846 | (const_int 0))) |
29ae5b89 | 8847 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
8848 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
8849 | (match_dup 2))) | |
29ae5b89 | 8850 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 8851 | "" |
29ae5b89 | 8852 | "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2" |
b19003d8 | 8853 | [(set_attr "type" "compare") |
29ae5b89 | 8854 | (set_attr "length" "8")]) |
1fd4e8c1 | 8855 | |
a260abc9 | 8856 | (define_insn "" |
29ae5b89 | 8857 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
a260abc9 DE |
8858 | (compare:CC |
8859 | (plus:DI (lshiftrt:DI | |
29ae5b89 | 8860 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) |
a260abc9 | 8861 | (const_int 63)) |
29ae5b89 | 8862 | (match_operand:DI 2 "gpc_reg_operand" "r")) |
a260abc9 | 8863 | (const_int 0))) |
29ae5b89 | 8864 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
8865 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
8866 | (match_dup 2))) | |
29ae5b89 | 8867 | (clobber (match_scratch:DI 3 "=&r"))] |
a260abc9 | 8868 | "TARGET_POWERPC64" |
29ae5b89 | 8869 | "addic %3,%1,-1\;addze. %0,%2" |
a260abc9 | 8870 | [(set_attr "type" "compare") |
29ae5b89 | 8871 | (set_attr "length" "8")]) |
a260abc9 | 8872 | |
1fd4e8c1 | 8873 | (define_insn "" |
cd2b37d9 RK |
8874 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
8875 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
8876 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
8877 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 8878 | "TARGET_POWER" |
1fd4e8c1 | 8879 | "@ |
ca7f5001 | 8880 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 8881 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 8882 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
8883 | |
8884 | (define_insn "" | |
29ae5b89 | 8885 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 8886 | (compare:CC |
29ae5b89 JL |
8887 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
8888 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) | |
1fd4e8c1 | 8889 | (const_int 0))) |
29ae5b89 | 8890 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8891 | (le:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 8892 | (clobber (match_scratch:SI 3 "=r,X"))] |
ca7f5001 | 8893 | "TARGET_POWER" |
1fd4e8c1 | 8894 | "@ |
ca7f5001 | 8895 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
29ae5b89 JL |
8896 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31" |
8897 | [(set_attr "type" "compare,delayed_compare") | |
8898 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
8899 | |
8900 | (define_insn "" | |
cd2b37d9 RK |
8901 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
8902 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 8903 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
cd2b37d9 | 8904 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 8905 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 8906 | "TARGET_POWER" |
1fd4e8c1 | 8907 | "@ |
ca7f5001 RK |
8908 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
8909 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" | |
b19003d8 | 8910 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
8911 | |
8912 | (define_insn "" | |
29ae5b89 | 8913 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 8914 | (compare:CC |
29ae5b89 JL |
8915 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
8916 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) | |
8917 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 8918 | (const_int 0))) |
29ae5b89 | 8919 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 8920 | "TARGET_POWER" |
1fd4e8c1 | 8921 | "@ |
ca7f5001 | 8922 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
29ae5b89 | 8923 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3" |
b19003d8 | 8924 | [(set_attr "type" "compare") |
29ae5b89 | 8925 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
8926 | |
8927 | (define_insn "" | |
29ae5b89 | 8928 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 8929 | (compare:CC |
29ae5b89 JL |
8930 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
8931 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) | |
8932 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 8933 | (const_int 0))) |
29ae5b89 | 8934 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8935 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 8936 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 8937 | "TARGET_POWER" |
1fd4e8c1 | 8938 | "@ |
ca7f5001 | 8939 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
29ae5b89 | 8940 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3" |
b19003d8 | 8941 | [(set_attr "type" "compare") |
29ae5b89 | 8942 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
8943 | |
8944 | (define_insn "" | |
cd2b37d9 RK |
8945 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
8946 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 8947 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 8948 | "TARGET_POWER" |
1fd4e8c1 | 8949 | "@ |
ca7f5001 RK |
8950 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
8951 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 8952 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
8953 | |
8954 | (define_insn "" | |
cd2b37d9 RK |
8955 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
8956 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
8957 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
8958 | "" | |
ca7f5001 | 8959 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 8960 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
8961 | |
8962 | (define_insn "" | |
29ae5b89 | 8963 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 | 8964 | (compare:CC |
29ae5b89 JL |
8965 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
8966 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 | 8967 | (const_int 0))) |
29ae5b89 | 8968 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
8969 | (leu:SI (match_dup 1) (match_dup 2)))] |
8970 | "" | |
29ae5b89 | 8971 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" |
b19003d8 | 8972 | [(set_attr "type" "compare") |
29ae5b89 | 8973 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
8974 | |
8975 | (define_insn "" | |
cd2b37d9 RK |
8976 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
8977 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 8978 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 8979 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
8980 | (clobber (match_scratch:SI 4 "=&r"))] |
8981 | "" | |
ca7f5001 | 8982 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 8983 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
8984 | |
8985 | (define_insn "" | |
29ae5b89 | 8986 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 8987 | (compare:CC |
29ae5b89 JL |
8988 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
8989 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
8990 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 8991 | (const_int 0))) |
29ae5b89 | 8992 | (clobber (match_scratch:SI 4 "=&r"))] |
1fd4e8c1 | 8993 | "" |
29ae5b89 | 8994 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3" |
b19003d8 | 8995 | [(set_attr "type" "compare") |
29ae5b89 | 8996 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
8997 | |
8998 | (define_insn "" | |
29ae5b89 | 8999 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") |
1fd4e8c1 | 9000 | (compare:CC |
29ae5b89 JL |
9001 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9002 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9003 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9004 | (const_int 0))) |
29ae5b89 | 9005 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9006 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9007 | (clobber (match_scratch:SI 4 "=&r"))] |
1fd4e8c1 | 9008 | "" |
29ae5b89 | 9009 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3" |
b19003d8 | 9010 | [(set_attr "type" "compare") |
29ae5b89 | 9011 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9012 | |
9013 | (define_insn "" | |
cd2b37d9 RK |
9014 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9015 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
9016 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
9017 | "" | |
ca7f5001 | 9018 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 9019 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9020 | |
9021 | (define_insn "" | |
cd2b37d9 | 9022 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9023 | (and:SI (neg:SI |
cd2b37d9 | 9024 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 9025 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
cd2b37d9 | 9026 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
9027 | (clobber (match_scratch:SI 4 "=&r"))] |
9028 | "" | |
ca7f5001 | 9029 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" |
b19003d8 | 9030 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9031 | |
9032 | (define_insn "" | |
29ae5b89 | 9033 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9034 | (compare:CC |
9035 | (and:SI (neg:SI | |
29ae5b89 JL |
9036 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9037 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) | |
9038 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9039 | (const_int 0))) |
29ae5b89 | 9040 | (clobber (match_scratch:SI 4 "=&r"))] |
1fd4e8c1 | 9041 | "" |
29ae5b89 | 9042 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" |
b19003d8 | 9043 | [(set_attr "type" "compare") |
29ae5b89 | 9044 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9045 | |
9046 | (define_insn "" | |
29ae5b89 | 9047 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9048 | (compare:CC |
9049 | (and:SI (neg:SI | |
29ae5b89 JL |
9050 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9051 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) | |
9052 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9053 | (const_int 0))) |
29ae5b89 | 9054 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9055 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
29ae5b89 | 9056 | (clobber (match_scratch:SI 4 "=&r"))] |
1fd4e8c1 | 9057 | "" |
29ae5b89 | 9058 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" |
b19003d8 | 9059 | [(set_attr "type" "compare") |
29ae5b89 | 9060 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9061 | |
9062 | (define_insn "" | |
cd2b37d9 RK |
9063 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9064 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9065 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 9066 | "TARGET_POWER" |
7f340546 | 9067 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 9068 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9069 | |
9070 | (define_insn "" | |
29ae5b89 | 9071 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 | 9072 | (compare:CC |
29ae5b89 JL |
9073 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9074 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 | 9075 | (const_int 0))) |
29ae5b89 | 9076 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9077 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 9078 | "TARGET_POWER" |
29ae5b89 JL |
9079 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" |
9080 | [(set_attr "type" "delayed_compare") | |
9081 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
9082 | |
9083 | (define_insn "" | |
cd2b37d9 RK |
9084 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9085 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9086 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 9087 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 9088 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
9089 | "TARGET_POWER" |
9090 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 9091 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9092 | |
9093 | (define_insn "" | |
29ae5b89 | 9094 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 9095 | (compare:CC |
29ae5b89 JL |
9096 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9097 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9098 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9099 | (const_int 0))) |
29ae5b89 | 9100 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9101 | "TARGET_POWER" |
29ae5b89 | 9102 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" |
b19003d8 | 9103 | [(set_attr "type" "compare") |
29ae5b89 | 9104 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9105 | |
9106 | (define_insn "" | |
29ae5b89 | 9107 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") |
1fd4e8c1 | 9108 | (compare:CC |
29ae5b89 JL |
9109 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9110 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9111 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9112 | (const_int 0))) |
29ae5b89 | 9113 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9114 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9115 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9116 | "TARGET_POWER" |
29ae5b89 | 9117 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" |
b19003d8 | 9118 | [(set_attr "type" "compare") |
29ae5b89 | 9119 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9120 | |
9121 | (define_insn "" | |
cd2b37d9 RK |
9122 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9123 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9124 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
9125 | "TARGET_POWER" |
9126 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 9127 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9128 | |
9129 | (define_insn "" | |
cd2b37d9 RK |
9130 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9131 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
9132 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
9133 | "" | |
9134 | "@ | |
ca7f5001 RK |
9135 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
9136 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 9137 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9138 | |
9139 | (define_insn "" | |
29ae5b89 | 9140 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9141 | (compare:CC |
29ae5b89 JL |
9142 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9143 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
1fd4e8c1 | 9144 | (const_int 0))) |
29ae5b89 | 9145 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
9146 | (ltu:SI (match_dup 1) (match_dup 2)))] |
9147 | "" | |
9148 | "@ | |
ca7f5001 | 9149 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
29ae5b89 | 9150 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" |
b19003d8 | 9151 | [(set_attr "type" "compare") |
29ae5b89 | 9152 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9153 | |
9154 | (define_insn "" | |
19378cf8 MM |
9155 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9156 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
9157 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
9158 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI"))) | |
9159 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
1fd4e8c1 RK |
9160 | "" |
9161 | "@ | |
ca7f5001 | 9162 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 |
04be6346 | 9163 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
b19003d8 | 9164 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9165 | |
9166 | (define_insn "" | |
29ae5b89 | 9167 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9168 | (compare:CC |
29ae5b89 JL |
9169 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9170 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
9171 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9172 | (const_int 0))) |
29ae5b89 | 9173 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9174 | "" |
9175 | "@ | |
ca7f5001 | 9176 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
29ae5b89 | 9177 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3" |
b19003d8 | 9178 | [(set_attr "type" "compare") |
29ae5b89 | 9179 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9180 | |
9181 | (define_insn "" | |
29ae5b89 | 9182 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9183 | (compare:CC |
29ae5b89 JL |
9184 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9185 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
9186 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9187 | (const_int 0))) |
29ae5b89 | 9188 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9189 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9190 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9191 | "" |
9192 | "@ | |
ca7f5001 | 9193 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
29ae5b89 | 9194 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" |
b19003d8 | 9195 | [(set_attr "type" "compare") |
29ae5b89 | 9196 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9197 | |
9198 | (define_insn "" | |
cd2b37d9 RK |
9199 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9200 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
9201 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
9202 | "" | |
9203 | "@ | |
ca7f5001 RK |
9204 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
9205 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 9206 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
9207 | |
9208 | (define_insn "" | |
cd2b37d9 RK |
9209 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9210 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
9211 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
9212 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
9213 | "TARGET_POWER" |
9214 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 9215 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9216 | |
9217 | (define_insn "" | |
29ae5b89 | 9218 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 9219 | (compare:CC |
29ae5b89 JL |
9220 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9221 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 | 9222 | (const_int 0))) |
29ae5b89 | 9223 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9224 | (ge:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 9225 | (clobber (match_scratch:SI 3 "=r"))] |
ca7f5001 | 9226 | "TARGET_POWER" |
29ae5b89 | 9227 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3" |
b19003d8 | 9228 | [(set_attr "type" "compare") |
29ae5b89 | 9229 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9230 | |
9231 | (define_insn "" | |
cd2b37d9 RK |
9232 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9233 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9234 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 9235 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 9236 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
9237 | "TARGET_POWER" |
9238 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" | |
b19003d8 | 9239 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9240 | |
9241 | (define_insn "" | |
29ae5b89 | 9242 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 9243 | (compare:CC |
29ae5b89 JL |
9244 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9245 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9246 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9247 | (const_int 0))) |
29ae5b89 | 9248 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9249 | "TARGET_POWER" |
29ae5b89 | 9250 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" |
b19003d8 | 9251 | [(set_attr "type" "compare") |
29ae5b89 | 9252 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9253 | |
9254 | (define_insn "" | |
29ae5b89 | 9255 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") |
1fd4e8c1 | 9256 | (compare:CC |
29ae5b89 JL |
9257 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9258 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9259 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9260 | (const_int 0))) |
29ae5b89 | 9261 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9262 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9263 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9264 | "TARGET_POWER" |
29ae5b89 | 9265 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" |
b19003d8 | 9266 | [(set_attr "type" "compare") |
29ae5b89 | 9267 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9268 | |
9269 | (define_insn "" | |
cd2b37d9 RK |
9270 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9271 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9272 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
9273 | "TARGET_POWER" |
9274 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 9275 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9276 | |
9277 | ;; This is (and (neg (ge X (const_int 0))) Y). | |
9278 | (define_insn "" | |
cd2b37d9 | 9279 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9280 | (and:SI (neg:SI |
9281 | (lshiftrt:SI | |
cd2b37d9 | 9282 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9283 | (const_int 31))) |
cd2b37d9 | 9284 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
9285 | (clobber (match_scratch:SI 3 "=&r"))] |
9286 | "" | |
ca7f5001 | 9287 | "{srai|srawi} %3,%1,31\;andc %0,%2,%3" |
b19003d8 | 9288 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
9289 | |
9290 | (define_insn "" | |
29ae5b89 | 9291 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9292 | (compare:CC |
9293 | (and:SI (neg:SI | |
9294 | (lshiftrt:SI | |
29ae5b89 | 9295 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9296 | (const_int 31))) |
29ae5b89 | 9297 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9298 | (const_int 0))) |
29ae5b89 | 9299 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 9300 | "" |
29ae5b89 | 9301 | "{srai|srawi} %3,%1,31\;andc. %3,%2,%3" |
b19003d8 | 9302 | [(set_attr "type" "compare") |
29ae5b89 | 9303 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9304 | |
9305 | (define_insn "" | |
29ae5b89 | 9306 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9307 | (compare:CC |
9308 | (and:SI (neg:SI | |
9309 | (lshiftrt:SI | |
29ae5b89 | 9310 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9311 | (const_int 31))) |
29ae5b89 | 9312 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9313 | (const_int 0))) |
29ae5b89 | 9314 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9315 | (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) |
9316 | (const_int 31))) | |
9317 | (match_dup 2))) | |
29ae5b89 | 9318 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 9319 | "" |
29ae5b89 | 9320 | "{srai|srawi} %3,%1,31\;andc. %0,%2,%3" |
b19003d8 | 9321 | [(set_attr "type" "compare") |
29ae5b89 | 9322 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9323 | |
9324 | (define_insn "" | |
cd2b37d9 RK |
9325 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9326 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
9327 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
9328 | "" | |
9329 | "@ | |
ca7f5001 RK |
9330 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
9331 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 9332 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9333 | |
9334 | (define_insn "" | |
29ae5b89 | 9335 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9336 | (compare:CC |
29ae5b89 JL |
9337 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9338 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
1fd4e8c1 | 9339 | (const_int 0))) |
29ae5b89 | 9340 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
9341 | (geu:SI (match_dup 1) (match_dup 2)))] |
9342 | "" | |
9343 | "@ | |
ca7f5001 | 9344 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
29ae5b89 | 9345 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" |
b19003d8 | 9346 | [(set_attr "type" "compare") |
29ae5b89 | 9347 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9348 | |
9349 | (define_insn "" | |
cd2b37d9 RK |
9350 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9351 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 9352 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
cd2b37d9 | 9353 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 RK |
9354 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
9355 | "" | |
9356 | "@ | |
ca7f5001 RK |
9357 | {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3 |
9358 | {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 9359 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
9360 | |
9361 | (define_insn "" | |
29ae5b89 | 9362 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9363 | (compare:CC |
29ae5b89 JL |
9364 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9365 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
9366 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9367 | (const_int 0))) |
29ae5b89 | 9368 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9369 | "" |
9370 | "@ | |
ca7f5001 | 9371 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
29ae5b89 | 9372 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3" |
b19003d8 | 9373 | [(set_attr "type" "compare") |
29ae5b89 | 9374 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9375 | |
9376 | (define_insn "" | |
29ae5b89 | 9377 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9378 | (compare:CC |
29ae5b89 JL |
9379 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9380 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
9381 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9382 | (const_int 0))) |
29ae5b89 | 9383 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9384 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9385 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9386 | "" |
9387 | "@ | |
ca7f5001 | 9388 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 |
19378cf8 | 9389 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3" |
b19003d8 | 9390 | [(set_attr "type" "compare") |
29ae5b89 | 9391 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9392 | |
9393 | (define_insn "" | |
cd2b37d9 RK |
9394 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9395 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
9396 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
9397 | "" | |
9398 | "@ | |
ca7f5001 | 9399 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 9400 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 9401 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9402 | |
9403 | (define_insn "" | |
cd2b37d9 | 9404 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9405 | (and:SI (neg:SI |
cd2b37d9 | 9406 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 9407 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
cd2b37d9 | 9408 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 RK |
9409 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
9410 | "" | |
9411 | "@ | |
ca7f5001 RK |
9412 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 |
9413 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" | |
b19003d8 | 9414 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9415 | |
9416 | (define_insn "" | |
29ae5b89 | 9417 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 RK |
9418 | (compare:CC |
9419 | (and:SI (neg:SI | |
29ae5b89 JL |
9420 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9421 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) | |
9422 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9423 | (const_int 0))) |
29ae5b89 | 9424 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9425 | "" |
9426 | "@ | |
ca7f5001 | 9427 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
29ae5b89 | 9428 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" |
b19003d8 | 9429 | [(set_attr "type" "compare") |
29ae5b89 | 9430 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9431 | |
9432 | (define_insn "" | |
29ae5b89 | 9433 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 RK |
9434 | (compare:CC |
9435 | (and:SI (neg:SI | |
29ae5b89 JL |
9436 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9437 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) | |
9438 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9439 | (const_int 0))) |
29ae5b89 | 9440 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9441 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
29ae5b89 | 9442 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9443 | "" |
9444 | "@ | |
ca7f5001 | 9445 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
29ae5b89 | 9446 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" |
b19003d8 | 9447 | [(set_attr "type" "compare") |
29ae5b89 | 9448 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9449 | |
9450 | (define_insn "" | |
cd2b37d9 RK |
9451 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9452 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
9453 | (const_int 0)))] |
9454 | "" | |
ca7f5001 | 9455 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 9456 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9457 | |
9458 | (define_insn "" | |
29ae5b89 | 9459 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
1fd4e8c1 | 9460 | (compare:CC |
29ae5b89 | 9461 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
9462 | (const_int 0)) |
9463 | (const_int 0))) | |
29ae5b89 | 9464 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9465 | (gt:SI (match_dup 1) (const_int 0)))] |
9466 | "" | |
29ae5b89 JL |
9467 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31" |
9468 | [(set_attr "type" "delayed_compare") | |
9469 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
9470 | |
9471 | (define_insn "" | |
cd2b37d9 RK |
9472 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9473 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9474 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
9475 | "TARGET_POWER" |
9476 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 9477 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9478 | |
9479 | (define_insn "" | |
29ae5b89 | 9480 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 | 9481 | (compare:CC |
29ae5b89 JL |
9482 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9483 | (match_operand:SI 2 "reg_or_short_operand" "r")) | |
1fd4e8c1 | 9484 | (const_int 0))) |
29ae5b89 | 9485 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9486 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 9487 | "TARGET_POWER" |
29ae5b89 JL |
9488 | "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" |
9489 | [(set_attr "type" "delayed_compare") | |
9490 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
9491 | |
9492 | (define_insn "" | |
cd2b37d9 RK |
9493 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9494 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9495 | (const_int 0)) |
cd2b37d9 | 9496 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
9497 | (clobber (match_scratch:SI 3 "=&r"))] |
9498 | "" | |
ca7f5001 | 9499 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2" |
b19003d8 | 9500 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9501 | |
9502 | (define_insn "" | |
29ae5b89 | 9503 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 9504 | (compare:CC |
29ae5b89 | 9505 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 9506 | (const_int 0)) |
29ae5b89 | 9507 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9508 | (const_int 0))) |
29ae5b89 | 9509 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 9510 | "" |
19378cf8 | 9511 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2" |
b19003d8 | 9512 | [(set_attr "type" "compare") |
29ae5b89 | 9513 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9514 | |
9515 | (define_insn "" | |
29ae5b89 | 9516 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 9517 | (compare:CC |
29ae5b89 | 9518 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 9519 | (const_int 0)) |
29ae5b89 | 9520 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9521 | (const_int 0))) |
29ae5b89 | 9522 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9523 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
29ae5b89 | 9524 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 9525 | "" |
19378cf8 | 9526 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2" |
b19003d8 | 9527 | [(set_attr "type" "compare") |
29ae5b89 | 9528 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9529 | |
9530 | (define_insn "" | |
cd2b37d9 RK |
9531 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9532 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9533 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
cd2b37d9 | 9534 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 9535 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
9536 | "TARGET_POWER" |
9537 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 9538 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9539 | |
9540 | (define_insn "" | |
29ae5b89 | 9541 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 9542 | (compare:CC |
29ae5b89 JL |
9543 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9544 | (match_operand:SI 2 "reg_or_short_operand" "r")) | |
9545 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9546 | (const_int 0))) |
29ae5b89 | 9547 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9548 | "TARGET_POWER" |
29ae5b89 | 9549 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" |
b19003d8 | 9550 | [(set_attr "type" "compare") |
29ae5b89 | 9551 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9552 | |
9553 | (define_insn "" | |
29ae5b89 | 9554 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") |
1fd4e8c1 | 9555 | (compare:CC |
29ae5b89 JL |
9556 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9557 | (match_operand:SI 2 "reg_or_short_operand" "r")) | |
9558 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9559 | (const_int 0))) |
29ae5b89 | 9560 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9561 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9562 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9563 | "TARGET_POWER" |
29ae5b89 | 9564 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" |
b19003d8 | 9565 | [(set_attr "type" "compare") |
29ae5b89 | 9566 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9567 | |
9568 | (define_insn "" | |
cd2b37d9 RK |
9569 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9570 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
9571 | (const_int 0))))] |
9572 | "" | |
ca7f5001 | 9573 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 9574 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9575 | |
9576 | (define_insn "" | |
cd2b37d9 RK |
9577 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9578 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9579 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
9580 | "TARGET_POWER" |
9581 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 9582 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9583 | |
9584 | (define_insn "" | |
cd2b37d9 RK |
9585 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9586 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
9587 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
9588 | "" | |
ca7f5001 | 9589 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 9590 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9591 | |
9592 | (define_insn "" | |
29ae5b89 | 9593 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 | 9594 | (compare:CC |
29ae5b89 JL |
9595 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9596 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 | 9597 | (const_int 0))) |
29ae5b89 | 9598 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9599 | (gtu:SI (match_dup 1) (match_dup 2)))] |
9600 | "" | |
29ae5b89 | 9601 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" |
b19003d8 | 9602 | [(set_attr "type" "compare") |
29ae5b89 | 9603 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9604 | |
9605 | (define_insn "" | |
19378cf8 MM |
9606 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9607 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
9608 | (match_operand:SI 2 "reg_or_short_operand" "I,rI")) | |
9609 | (match_operand:SI 3 "reg_or_short_operand" "r,rI"))) | |
9610 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
1fd4e8c1 | 9611 | "" |
00751805 | 9612 | "@ |
ca7f5001 | 9613 | {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3 |
ca7f5001 | 9614 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
19378cf8 | 9615 | [(set_attr "length" "8,12")]) |
1fd4e8c1 RK |
9616 | |
9617 | (define_insn "" | |
29ae5b89 | 9618 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9619 | (compare:CC |
29ae5b89 JL |
9620 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9621 | (match_operand:SI 2 "reg_or_short_operand" "I,r")) | |
9622 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9623 | (const_int 0))) |
29ae5b89 | 9624 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 | 9625 | "" |
00751805 | 9626 | "@ |
19378cf8 MM |
9627 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
9628 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3" | |
b19003d8 | 9629 | [(set_attr "type" "compare") |
29ae5b89 | 9630 | (set_attr "length" "8,12")]) |
1fd4e8c1 RK |
9631 | |
9632 | (define_insn "" | |
29ae5b89 | 9633 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9634 | (compare:CC |
29ae5b89 JL |
9635 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9636 | (match_operand:SI 2 "reg_or_short_operand" "I,r")) | |
9637 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9638 | (const_int 0))) |
29ae5b89 | 9639 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9640 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9641 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 | 9642 | "" |
00751805 | 9643 | "@ |
ca7f5001 | 9644 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 |
29ae5b89 | 9645 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" |
b19003d8 | 9646 | [(set_attr "type" "compare") |
29ae5b89 | 9647 | (set_attr "length" "8,12")]) |
1fd4e8c1 RK |
9648 | |
9649 | (define_insn "" | |
cd2b37d9 RK |
9650 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9651 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
9652 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
9653 | "" | |
ca7f5001 | 9654 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 9655 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
9656 | \f |
9657 | ;; Define both directions of branch and return. If we need a reload | |
9658 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
9659 | ;; register CC value to there. | |
9660 | ||
9661 | (define_insn "" | |
9662 | [(set (pc) | |
9663 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
9664 | [(match_operand 2 | |
9665 | "cc_reg_operand" "x,?y") | |
9666 | (const_int 0)]) | |
9667 | (label_ref (match_operand 0 "" "")) | |
9668 | (pc)))] | |
9669 | "" | |
b19003d8 RK |
9670 | "* |
9671 | { | |
9672 | if (get_attr_length (insn) == 8) | |
9673 | return \"%C1bc %t1,%j1,%l0\"; | |
9674 | else | |
c81bebd7 MM |
9675 | return \"%C1bc %T1,%j1,%$+8\;b %l0\"; |
9676 | ||
b19003d8 RK |
9677 | }" |
9678 | [(set_attr "type" "branch")]) | |
9679 | ||
1fd4e8c1 RK |
9680 | (define_insn "" |
9681 | [(set (pc) | |
9682 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
9683 | [(match_operand 1 | |
9684 | "cc_reg_operand" "x,?y") | |
9685 | (const_int 0)]) | |
9686 | (return) | |
9687 | (pc)))] | |
9688 | "direct_return ()" | |
ca7f5001 | 9689 | "{%C0bcr|%C0bclr} %t0,%j0" |
b7ff3d82 DE |
9690 | [(set_attr "type" "branch") |
9691 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
9692 | |
9693 | (define_insn "" | |
9694 | [(set (pc) | |
9695 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
9696 | [(match_operand 2 | |
9697 | "cc_reg_operand" "x,?y") | |
9698 | (const_int 0)]) | |
9699 | (pc) | |
9700 | (label_ref (match_operand 0 "" ""))))] | |
9701 | "" | |
b19003d8 RK |
9702 | "* |
9703 | { | |
9704 | if (get_attr_length (insn) == 8) | |
9705 | return \"%C1bc %T1,%j1,%l0\"; | |
9706 | else | |
c81bebd7 | 9707 | return \"%C1bc %t1,%j1,%$+8\;b %l0\"; |
b19003d8 RK |
9708 | }" |
9709 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
9710 | |
9711 | (define_insn "" | |
9712 | [(set (pc) | |
9713 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
9714 | [(match_operand 1 | |
9715 | "cc_reg_operand" "x,?y") | |
9716 | (const_int 0)]) | |
9717 | (pc) | |
9718 | (return)))] | |
9719 | "direct_return ()" | |
ca7f5001 | 9720 | "{%C0bcr|%C0bclr} %T0,%j0" |
b7ff3d82 DE |
9721 | [(set_attr "type" "branch") |
9722 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
9723 | |
9724 | ;; Unconditional branch and return. | |
9725 | ||
9726 | (define_insn "jump" | |
9727 | [(set (pc) | |
9728 | (label_ref (match_operand 0 "" "")))] | |
9729 | "" | |
b7ff3d82 DE |
9730 | "b %l0" |
9731 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
9732 | |
9733 | (define_insn "return" | |
9734 | [(return)] | |
9735 | "direct_return ()" | |
324e52cc TG |
9736 | "{br|blr}" |
9737 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 RK |
9738 | |
9739 | (define_insn "indirect_jump" | |
9740 | [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))] | |
9741 | "" | |
9742 | "@ | |
9743 | bctr | |
324e52cc TG |
9744 | {br|blr}" |
9745 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 9746 | |
266eb58a DE |
9747 | (define_insn "" |
9748 | [(set (pc) (match_operand:DI 0 "register_operand" "c,l"))] | |
9749 | "TARGET_POWERPC64" | |
9750 | "@ | |
9751 | bctr | |
9752 | {br|blr}" | |
9753 | [(set_attr "type" "jmpreg")]) | |
9754 | ||
1fd4e8c1 RK |
9755 | ;; Table jump for switch statements: |
9756 | (define_expand "tablejump" | |
e6ca2c17 DE |
9757 | [(use (match_operand 0 "" "")) |
9758 | (use (label_ref (match_operand 1 "" "")))] | |
9759 | "" | |
9760 | " | |
9761 | { | |
9762 | if (TARGET_32BIT) | |
9763 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
9764 | else | |
9765 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
9766 | DONE; | |
9767 | }") | |
9768 | ||
9769 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
9770 | [(set (match_dup 3) |
9771 | (plus:SI (match_operand:SI 0 "" "") | |
9772 | (match_dup 2))) | |
9773 | (parallel [(set (pc) (match_dup 3)) | |
9774 | (use (label_ref (match_operand 1 "" "")))])] | |
9775 | "" | |
9776 | " | |
9777 | { operands[0] = force_reg (SImode, operands[0]); | |
39403d82 | 9778 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (VOIDmode, operands[1])); |
1fd4e8c1 RK |
9779 | operands[3] = gen_reg_rtx (SImode); |
9780 | }") | |
9781 | ||
e6ca2c17 DE |
9782 | (define_expand "tablejumpdi" |
9783 | [(set (match_dup 3) | |
9784 | (plus:DI (match_operand:DI 0 "" "") | |
9785 | (match_dup 2))) | |
9786 | (parallel [(set (pc) (match_dup 3)) | |
9787 | (use (label_ref (match_operand 1 "" "")))])] | |
9788 | "" | |
9789 | " | |
9790 | { operands[0] = force_reg (DImode, operands[0]); | |
39403d82 | 9791 | operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (VOIDmode, operands[1])); |
e6ca2c17 DE |
9792 | operands[3] = gen_reg_rtx (DImode); |
9793 | }") | |
9794 | ||
1fd4e8c1 RK |
9795 | (define_insn "" |
9796 | [(set (pc) | |
740ab4a2 | 9797 | (match_operand:SI 0 "register_operand" "c,l")) |
1fd4e8c1 RK |
9798 | (use (label_ref (match_operand 1 "" "")))] |
9799 | "" | |
9800 | "@ | |
9801 | bctr | |
a6845123 RK |
9802 | {br|blr}" |
9803 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 9804 | |
266eb58a DE |
9805 | (define_insn "" |
9806 | [(set (pc) | |
9807 | (match_operand:DI 0 "register_operand" "c,l")) | |
9808 | (use (label_ref (match_operand 1 "" "")))] | |
9809 | "TARGET_POWERPC64" | |
9810 | "@ | |
9811 | bctr | |
9812 | {br|blr}" | |
9813 | [(set_attr "type" "jmpreg")]) | |
9814 | ||
1fd4e8c1 RK |
9815 | (define_insn "nop" |
9816 | [(const_int 0)] | |
9817 | "" | |
ca7f5001 | 9818 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 9819 | \f |
7e69e155 | 9820 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
9821 | ;; so loop.c knows what to generate. |
9822 | ||
b6c9286a MM |
9823 | (define_expand "decrement_and_branch_on_count" |
9824 | [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
c225ba7b RK |
9825 | (const_int 1)) |
9826 | (label_ref (match_operand 1 "" "")) | |
9827 | (pc))) | |
b6c9286a MM |
9828 | (set (match_dup 0) |
9829 | (plus:SI (match_dup 0) | |
9830 | (const_int -1))) | |
5f81043f RK |
9831 | (clobber (match_scratch:CC 2 "")) |
9832 | (clobber (match_scratch:SI 3 ""))])] | |
c225ba7b RK |
9833 | "" |
9834 | "") | |
9835 | ||
1fd4e8c1 RK |
9836 | ;; We need to be able to do this for any operand, including MEM, or we |
9837 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 9838 | ;; JUMP_INSNs. |
5f81043f RK |
9839 | ;; In order that the length attribute is calculated correctly, the |
9840 | ;; label MUST be operand 0. | |
9841 | ||
1fd4e8c1 RK |
9842 | (define_insn "" |
9843 | [(set (pc) | |
5f81043f | 9844 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 9845 | (const_int 1)) |
a6845123 | 9846 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 9847 | (pc))) |
5f81043f RK |
9848 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
9849 | (plus:SI (match_dup 1) | |
9850 | (const_int -1))) | |
1fd4e8c1 RK |
9851 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
9852 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
9853 | "" | |
b19003d8 RK |
9854 | "* |
9855 | { | |
af87a13e | 9856 | if (which_alternative != 0) |
b19003d8 RK |
9857 | return \"#\"; |
9858 | else if (get_attr_length (insn) == 8) | |
a6845123 | 9859 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 9860 | else |
c81bebd7 | 9861 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 9862 | }" |
baf97f86 RK |
9863 | [(set_attr "type" "branch") |
9864 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 9865 | |
5f81043f RK |
9866 | (define_insn "" |
9867 | [(set (pc) | |
9868 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") | |
9869 | (const_int 1)) | |
9870 | (pc) | |
9871 | (label_ref (match_operand 0 "" "")))) | |
9872 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
9873 | (plus:SI (match_dup 1) | |
9874 | (const_int -1))) | |
9875 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
9876 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
9877 | "" | |
9878 | "* | |
9879 | { | |
9880 | if (which_alternative != 0) | |
9881 | return \"#\"; | |
9882 | else if (get_attr_length (insn) == 8) | |
9883 | return \"bdz %l0\"; | |
9884 | else | |
c81bebd7 | 9885 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
9886 | }" |
9887 | [(set_attr "type" "branch") | |
9888 | (set_attr "length" "*,12,16")]) | |
9889 | ||
c225ba7b | 9890 | ;; Similar, but we can use GE since we have a REG_NONNEG. |
1fd4e8c1 RK |
9891 | (define_insn "" |
9892 | [(set (pc) | |
5f81043f | 9893 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 9894 | (const_int 0)) |
a6845123 | 9895 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 9896 | (pc))) |
5f81043f RK |
9897 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
9898 | (plus:SI (match_dup 1) | |
9899 | (const_int -1))) | |
1fd4e8c1 RK |
9900 | (clobber (match_scratch:CC 3 "=X,&x,&X")) |
9901 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
9902 | "find_reg_note (insn, REG_NONNEG, 0)" | |
b19003d8 RK |
9903 | "* |
9904 | { | |
af87a13e | 9905 | if (which_alternative != 0) |
b19003d8 RK |
9906 | return \"#\"; |
9907 | else if (get_attr_length (insn) == 8) | |
a6845123 | 9908 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 9909 | else |
c81bebd7 | 9910 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 9911 | }" |
baf97f86 RK |
9912 | [(set_attr "type" "branch") |
9913 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 9914 | |
1fd4e8c1 RK |
9915 | (define_insn "" |
9916 | [(set (pc) | |
5f81043f RK |
9917 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
9918 | (const_int 0)) | |
9919 | (pc) | |
9920 | (label_ref (match_operand 0 "" "")))) | |
9921 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
9922 | (plus:SI (match_dup 1) | |
9923 | (const_int -1))) | |
9924 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
9925 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
9926 | "find_reg_note (insn, REG_NONNEG, 0)" | |
9927 | "* | |
9928 | { | |
9929 | if (which_alternative != 0) | |
9930 | return \"#\"; | |
9931 | else if (get_attr_length (insn) == 8) | |
9932 | return \"bdz %l0\"; | |
9933 | else | |
c81bebd7 | 9934 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
9935 | }" |
9936 | [(set_attr "type" "branch") | |
9937 | (set_attr "length" "*,12,16")]) | |
9938 | ||
9939 | (define_insn "" | |
9940 | [(set (pc) | |
9941 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
1fd4e8c1 | 9942 | (const_int 1)) |
a6845123 | 9943 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 9944 | (pc))) |
5f81043f RK |
9945 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
9946 | (plus:SI (match_dup 1) | |
9947 | (const_int -1))) | |
1fd4e8c1 RK |
9948 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
9949 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
9950 | "" | |
b19003d8 RK |
9951 | "* |
9952 | { | |
af87a13e | 9953 | if (which_alternative != 0) |
b19003d8 RK |
9954 | return \"#\"; |
9955 | else if (get_attr_length (insn) == 8) | |
a6845123 | 9956 | return \"bdz %l0\"; |
b19003d8 | 9957 | else |
c81bebd7 | 9958 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
b19003d8 | 9959 | }" |
baf97f86 RK |
9960 | [(set_attr "type" "branch") |
9961 | (set_attr "length" "*,12,16")]) | |
1fd4e8c1 | 9962 | |
5f81043f RK |
9963 | (define_insn "" |
9964 | [(set (pc) | |
9965 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
9966 | (const_int 1)) | |
9967 | (pc) | |
9968 | (label_ref (match_operand 0 "" "")))) | |
9969 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
9970 | (plus:SI (match_dup 1) | |
9971 | (const_int -1))) | |
9972 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
9973 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
9974 | "" | |
9975 | "* | |
9976 | { | |
9977 | if (which_alternative != 0) | |
9978 | return \"#\"; | |
9979 | else if (get_attr_length (insn) == 8) | |
9980 | return \"{bdn|bdnz} %l0\"; | |
9981 | else | |
c81bebd7 | 9982 | return \"bdz %$+8\;b %l0\"; |
5f81043f RK |
9983 | }" |
9984 | [(set_attr "type" "branch") | |
9985 | (set_attr "length" "*,12,16")]) | |
9986 | ||
1fd4e8c1 RK |
9987 | (define_split |
9988 | [(set (pc) | |
9989 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 9990 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
9991 | (const_int 1)]) |
9992 | (match_operand 5 "" "") | |
9993 | (match_operand 6 "" ""))) | |
cd2b37d9 | 9994 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
9995 | (plus:SI (match_dup 1) |
9996 | (const_int -1))) | |
1fd4e8c1 RK |
9997 | (clobber (match_scratch:CC 3 "")) |
9998 | (clobber (match_scratch:SI 4 ""))] | |
9999 | "reload_completed" | |
10000 | [(parallel [(set (match_dup 3) | |
5f81043f RK |
10001 | (compare:CC (plus:SI (match_dup 1) |
10002 | (const_int -1)) | |
1fd4e8c1 | 10003 | (const_int 0))) |
5f81043f RK |
10004 | (set (match_dup 0) |
10005 | (plus:SI (match_dup 1) | |
10006 | (const_int -1)))]) | |
10007 | (set (pc) (if_then_else (match_dup 7) | |
10008 | (match_dup 5) | |
10009 | (match_dup 6)))] | |
1fd4e8c1 RK |
10010 | " |
10011 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
10012 | const0_rtx); }") | |
10013 | ||
10014 | (define_split | |
10015 | [(set (pc) | |
10016 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 10017 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10018 | (const_int 1)]) |
10019 | (match_operand 5 "" "") | |
10020 | (match_operand 6 "" ""))) | |
10021 | (set (match_operand:SI 0 "general_operand" "") | |
10022 | (plus:SI (match_dup 1) (const_int -1))) | |
10023 | (clobber (match_scratch:CC 3 "")) | |
10024 | (clobber (match_scratch:SI 4 ""))] | |
cd2b37d9 | 10025 | "reload_completed && ! gpc_reg_operand (operands[0], SImode)" |
1fd4e8c1 | 10026 | [(parallel [(set (match_dup 3) |
5f81043f RK |
10027 | (compare:CC (plus:SI (match_dup 1) |
10028 | (const_int -1)) | |
1fd4e8c1 | 10029 | (const_int 0))) |
5f81043f RK |
10030 | (set (match_dup 4) |
10031 | (plus:SI (match_dup 1) | |
10032 | (const_int -1)))]) | |
10033 | (set (match_dup 0) | |
10034 | (match_dup 4)) | |
10035 | (set (pc) (if_then_else (match_dup 7) | |
10036 | (match_dup 5) | |
10037 | (match_dup 6)))] | |
1fd4e8c1 RK |
10038 | " |
10039 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
10040 | const0_rtx); }") | |
e0cd0770 JC |
10041 | \f |
10042 | (define_insn "trap" | |
10043 | [(trap_if (const_int 1) (const_int 0))] | |
10044 | "" | |
10045 | "{t 31,0,0|trap}") | |
10046 | ||
10047 | (define_expand "conditional_trap" | |
10048 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
10049 | [(match_dup 2) (match_dup 3)]) | |
10050 | (match_operand 1 "const_int_operand" ""))] | |
10051 | "" | |
10052 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
10053 | operands[2] = rs6000_compare_op0; | |
10054 | operands[3] = rs6000_compare_op1;") | |
10055 | ||
10056 | (define_insn "" | |
10057 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
10058 | [(match_operand:SI 1 "register_operand" "r") | |
10059 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
10060 | (const_int 0))] | |
10061 | "" | |
10062 | "t%V0%I2 %1,%2") |