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Remove extra bits I included, by mistake, in my previous check-in
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
CommitLineData
996a5f59 1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
d24652ee
GK		 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3;; 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
996a5f59 4;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
1fd4e8c1
RK		 5
6;; This file is part of GNU CC.
7
8;; GNU CC is free software; you can redistribute it and/or modify
9;; it under the terms of the GNU General Public License as published by
10;; the Free Software Foundation; either version 2, or (at your option)
11;; any later version.
12
13;; GNU CC is distributed in the hope that it will be useful,
14;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16;; GNU General Public License for more details.
17
18;; You should have received a copy of the GNU General Public License
19;; along with GNU CC; see the file COPYING. If not, write to
3f63df56
RK		 20;; the Free Software Foundation, 59 Temple Place - Suite 330,
21;; Boston, MA 02111-1307, USA.
1fd4e8c1
RK		 22
23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
9ebbca7d
GK		 24
25;; `unspec' values used in rs6000.md:
26;; Number Use
27;; 0 frsp for POWER machines
28;; 0/v blockage
29;; 5 used to tie the stack contents and the stack pointer
30;; 6 address of a word pointing to the TOC
31;; 7 address of the TOC (more-or-less)
32;; 8 movsi_got
33;; 9/v eh_reg_restore
34;; 10 fctiwz
f51eee6a
GK		 35;; 15 load_macho_picbase
36;; 16 macho_correct_pic
9ebbca7d 37;; 19 movesi_from_cr
b54cf83a 38;; 20 movsi_to_cr
1fd4e8c1
RK		 39\f
40;; Define an insn type attribute. This is used in function unit delay
41;; computations.
a62bfff2 42(define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,cmp,fast_compare,compare,delayed_compare,fpcompare,cr_logical,delayed_cr,mfcr,mtcr,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat"
1fd4e8c1
RK		 43 (const_string "integer"))
44
b19003d8 45;; Length (in bytes).
6cbadf36
GK		 46; '(pc)' in the following doesn't include the instruction itself; it is
47; calculated as if the instruction had zero size.
b19003d8
RK		 48(define_attr "length" ""
49 (if_then_else (eq_attr "type" "branch")
6cbadf36 50 (if_then_else (and (ge (minus (match_dup 0) (pc))
b19003d8 51 (const_int -32768))
6cbadf36
GK		 52 (lt (minus (match_dup 0) (pc))
53 (const_int 32764)))
39a10a29
GK		 54 (const_int 4)
55 (const_int 8))
b19003d8
RK		 56 (const_int 4)))
57
cfb557c4
RK		 58;; Processor type -- this attribute must exactly match the processor_type
59;; enumeration in rs6000.h.
60
b54cf83a 61(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4"
cfb557c4
RK		 62 (const (symbol_ref "rs6000_cpu_attr")))
63
b54cf83a
DE		 64(automata_option "ndfa")
65
66(include "rios1.md")
67(include "rios2.md")
68(include "rs64.md")
69(include "mpc.md")
70(include "40x.md")
71(include "603.md")
72(include "6xx.md")
73(include "7xx.md")
74(include "7450.md")
75(include "power4.md")
309323c2 76
1fd4e8c1
RK		 77\f
78;; Start with fixed-point load and store insns. Here we put only the more
79;; complex forms. Basic data transfer is done later.
80
51b8fc2c
RK		 81(define_expand "zero_extendqidi2"
82 [(set (match_operand:DI 0 "gpc_reg_operand" "")
83 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
84 "TARGET_POWERPC64"
85 "")
86
87(define_insn ""
88 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
89 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
90 "TARGET_POWERPC64"
91 "@
92 lbz%U1%X1 %0,%1
4371f8af 93 rldicl %0,%1,0,56"
51b8fc2c
RK		 94 [(set_attr "type" "load,*")])
95
96(define_insn ""
9ebbca7d
GK		 97 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
98 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815cdc52 99 (const_int 0)))
9ebbca7d 100 (clobber (match_scratch:DI 2 "=r,r"))]
29ae5b89 101 "TARGET_POWERPC64"
9ebbca7d
GK		 102 "@
103 rldicl. %2,%1,0,56
104 #"
105 [(set_attr "type" "compare")
106 (set_attr "length" "4,8")])
107
108(define_split
109 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
110 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
111 (const_int 0)))
112 (clobber (match_scratch:DI 2 ""))]
113 "TARGET_POWERPC64 && reload_completed"
114 [(set (match_dup 2)
115 (zero_extend:DI (match_dup 1)))
116 (set (match_dup 0)
117 (compare:CC (match_dup 2)
118 (const_int 0)))]
119 "")
51b8fc2c
RK		 120
121(define_insn ""
9ebbca7d
GK		 122 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
123 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 124 (const_int 0)))
9ebbca7d 125 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 126 (zero_extend:DI (match_dup 1)))]
58e09803 127 "TARGET_POWERPC64"
9ebbca7d
GK		 128 "@
129 rldicl. %0,%1,0,56
130 #"
131 [(set_attr "type" "compare")
132 (set_attr "length" "4,8")])
133
134(define_split
135 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
136 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
137 (const_int 0)))
138 (set (match_operand:DI 0 "gpc_reg_operand" "")
139 (zero_extend:DI (match_dup 1)))]
140 "TARGET_POWERPC64 && reload_completed"
141 [(set (match_dup 0)
142 (zero_extend:DI (match_dup 1)))
143 (set (match_dup 2)
144 (compare:CC (match_dup 0)
145 (const_int 0)))]
146 "")
51b8fc2c 147
2bee0449
RK		 148(define_insn "extendqidi2"
149 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
150 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 151 "TARGET_POWERPC64"
2bee0449 152 "extsb %0,%1")
51b8fc2c
RK		 153
154(define_insn ""
9ebbca7d
GK		 155 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
156 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 157 (const_int 0)))
9ebbca7d 158 (clobber (match_scratch:DI 2 "=r,r"))]
51b8fc2c 159 "TARGET_POWERPC64"
9ebbca7d
GK		 160 "@
161 extsb. %2,%1
162 #"
163 [(set_attr "type" "compare")
164 (set_attr "length" "4,8")])
165
166(define_split
167 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
168 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
169 (const_int 0)))
170 (clobber (match_scratch:DI 2 ""))]
171 "TARGET_POWERPC64 && reload_completed"
172 [(set (match_dup 2)
173 (sign_extend:DI (match_dup 1)))
174 (set (match_dup 0)
175 (compare:CC (match_dup 2)
176 (const_int 0)))]
177 "")
51b8fc2c
RK		 178
179(define_insn ""
9ebbca7d
GK		 180 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
181 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 182 (const_int 0)))
9ebbca7d 183 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 184 (sign_extend:DI (match_dup 1)))]
185 "TARGET_POWERPC64"
9ebbca7d
GK		 186 "@
187 extsb. %0,%1
188 #"
189 [(set_attr "type" "compare")
190 (set_attr "length" "4,8")])
191
192(define_split
193 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
194 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
195 (const_int 0)))
196 (set (match_operand:DI 0 "gpc_reg_operand" "")
197 (sign_extend:DI (match_dup 1)))]
198 "TARGET_POWERPC64 && reload_completed"
199 [(set (match_dup 0)
200 (sign_extend:DI (match_dup 1)))
201 (set (match_dup 2)
202 (compare:CC (match_dup 0)
203 (const_int 0)))]
204 "")
51b8fc2c
RK		 205
206(define_expand "zero_extendhidi2"
207 [(set (match_operand:DI 0 "gpc_reg_operand" "")
208 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
209 "TARGET_POWERPC64"
210 "")
211
212(define_insn ""
213 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
214 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
215 "TARGET_POWERPC64"
216 "@
217 lhz%U1%X1 %0,%1
4371f8af 218 rldicl %0,%1,0,48"
51b8fc2c
RK		 219 [(set_attr "type" "load,*")])
220
221(define_insn ""
9ebbca7d
GK		 222 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
223 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 224 (const_int 0)))
9ebbca7d 225 (clobber (match_scratch:DI 2 "=r,r"))]
51b8fc2c 226 "TARGET_POWERPC64"
9ebbca7d
GK		 227 "@
228 rldicl. %2,%1,0,48
229 #"
230 [(set_attr "type" "compare")
231 (set_attr "length" "4,8")])
232
233(define_split
234 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
235 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
236 (const_int 0)))
237 (clobber (match_scratch:DI 2 ""))]
238 "TARGET_POWERPC64 && reload_completed"
239 [(set (match_dup 2)
240 (zero_extend:DI (match_dup 1)))
241 (set (match_dup 0)
242 (compare:CC (match_dup 2)
243 (const_int 0)))]
244 "")
51b8fc2c
RK		 245
246(define_insn ""
9ebbca7d
GK		 247 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
248 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 249 (const_int 0)))
9ebbca7d 250 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 251 (zero_extend:DI (match_dup 1)))]
252 "TARGET_POWERPC64"
9ebbca7d
GK		 253 "@
254 rldicl. %0,%1,0,48
255 #"
256 [(set_attr "type" "compare")
257 (set_attr "length" "4,8")])
258
259(define_split
260 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
261 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
262 (const_int 0)))
263 (set (match_operand:DI 0 "gpc_reg_operand" "")
264 (zero_extend:DI (match_dup 1)))]
265 "TARGET_POWERPC64 && reload_completed"
266 [(set (match_dup 0)
267 (zero_extend:DI (match_dup 1)))
268 (set (match_dup 2)
269 (compare:CC (match_dup 0)
270 (const_int 0)))]
271 "")
51b8fc2c
RK		 272
273(define_expand "extendhidi2"
274 [(set (match_operand:DI 0 "gpc_reg_operand" "")
275 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
276 "TARGET_POWERPC64"
277 "")
278
279(define_insn ""
280 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
281 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
282 "TARGET_POWERPC64"
283 "@
284 lha%U1%X1 %0,%1
285 extsh %0,%1"
b54cf83a 286 [(set_attr "type" "load_ext,*")])
51b8fc2c
RK		 287
288(define_insn ""
9ebbca7d
GK		 289 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
290 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 291 (const_int 0)))
9ebbca7d 292 (clobber (match_scratch:DI 2 "=r,r"))]
51b8fc2c 293 "TARGET_POWERPC64"
9ebbca7d
GK		 294 "@
295 extsh. %2,%1
296 #"
297 [(set_attr "type" "compare")
298 (set_attr "length" "4,8")])
299
300(define_split
301 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
302 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
303 (const_int 0)))
304 (clobber (match_scratch:DI 2 ""))]
305 "TARGET_POWERPC64 && reload_completed"
306 [(set (match_dup 2)
307 (sign_extend:DI (match_dup 1)))
308 (set (match_dup 0)
309 (compare:CC (match_dup 2)
310 (const_int 0)))]
311 "")
51b8fc2c
RK		 312
313(define_insn ""
9ebbca7d
GK		 314 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
315 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 316 (const_int 0)))
9ebbca7d 317 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 318 (sign_extend:DI (match_dup 1)))]
319 "TARGET_POWERPC64"
9ebbca7d
GK		 320 "@
321 extsh. %0,%1
322 #"
323 [(set_attr "type" "compare")
324 (set_attr "length" "4,8")])
325
326(define_split
327 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
328 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
329 (const_int 0)))
330 (set (match_operand:DI 0 "gpc_reg_operand" "")
331 (sign_extend:DI (match_dup 1)))]
332 "TARGET_POWERPC64 && reload_completed"
333 [(set (match_dup 0)
334 (sign_extend:DI (match_dup 1)))
335 (set (match_dup 2)
336 (compare:CC (match_dup 0)
337 (const_int 0)))]
338 "")
51b8fc2c
RK		 339
340(define_expand "zero_extendsidi2"
341 [(set (match_operand:DI 0 "gpc_reg_operand" "")
342 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
343 "TARGET_POWERPC64"
344 "")
345
346(define_insn ""
347 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
348 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
349 "TARGET_POWERPC64"
350 "@
351 lwz%U1%X1 %0,%1
352 rldicl %0,%1,0,32"
353 [(set_attr "type" "load,*")])
354
355(define_insn ""
9ebbca7d
GK		 356 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
357 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 358 (const_int 0)))
9ebbca7d 359 (clobber (match_scratch:DI 2 "=r,r"))]
51b8fc2c 360 "TARGET_POWERPC64"
9ebbca7d
GK		 361 "@
362 rldicl. %2,%1,0,32
363 #"
364 [(set_attr "type" "compare")
365 (set_attr "length" "4,8")])
366
367(define_split
368 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
369 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
370 (const_int 0)))
371 (clobber (match_scratch:DI 2 ""))]
372 "TARGET_POWERPC64 && reload_completed"
373 [(set (match_dup 2)
374 (zero_extend:DI (match_dup 1)))
375 (set (match_dup 0)
376 (compare:CC (match_dup 2)
377 (const_int 0)))]
378 "")
51b8fc2c
RK		 379
380(define_insn ""
9ebbca7d
GK		 381 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
382 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 383 (const_int 0)))
9ebbca7d 384 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 385 (zero_extend:DI (match_dup 1)))]
386 "TARGET_POWERPC64"
9ebbca7d
GK		 387 "@
388 rldicl. %0,%1,0,32
389 #"
390 [(set_attr "type" "compare")
391 (set_attr "length" "4,8")])
392
393(define_split
394 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
395 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
396 (const_int 0)))
397 (set (match_operand:DI 0 "gpc_reg_operand" "")
398 (zero_extend:DI (match_dup 1)))]
399 "TARGET_POWERPC64 && reload_completed"
400 [(set (match_dup 0)
401 (zero_extend:DI (match_dup 1)))
402 (set (match_dup 2)
403 (compare:CC (match_dup 0)
404 (const_int 0)))]
405 "")
51b8fc2c
RK		 406
407(define_expand "extendsidi2"
408 [(set (match_operand:DI 0 "gpc_reg_operand" "")
409 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
410 "TARGET_POWERPC64"
411 "")
412
413(define_insn ""
414 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
287f13ff 415 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
51b8fc2c
RK		 416 "TARGET_POWERPC64"
417 "@
418 lwa%U1%X1 %0,%1
419 extsw %0,%1"
b54cf83a 420 [(set_attr "type" "load_ext,*")])
51b8fc2c
RK		 421
422(define_insn ""
9ebbca7d
GK		 423 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
424 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 425 (const_int 0)))
9ebbca7d 426 (clobber (match_scratch:DI 2 "=r,r"))]
51b8fc2c 427 "TARGET_POWERPC64"
9ebbca7d
GK		 428 "@
429 extsw. %2,%1
430 #"
431 [(set_attr "type" "compare")
432 (set_attr "length" "4,8")])
433
434(define_split
435 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
436 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
437 (const_int 0)))
438 (clobber (match_scratch:DI 2 ""))]
439 "TARGET_POWERPC64 && reload_completed"
440 [(set (match_dup 2)
441 (sign_extend:DI (match_dup 1)))
442 (set (match_dup 0)
443 (compare:CC (match_dup 2)
444 (const_int 0)))]
445 "")
51b8fc2c
RK		 446
447(define_insn ""
9ebbca7d
GK		 448 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
449 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 450 (const_int 0)))
9ebbca7d 451 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 452 (sign_extend:DI (match_dup 1)))]
453 "TARGET_POWERPC64"
9ebbca7d
GK		 454 "@
455 extsw. %0,%1
456 #"
457 [(set_attr "type" "compare")
458 (set_attr "length" "4,8")])
459
460(define_split
461 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
462 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
463 (const_int 0)))
464 (set (match_operand:DI 0 "gpc_reg_operand" "")
465 (sign_extend:DI (match_dup 1)))]
466 "TARGET_POWERPC64 && reload_completed"
467 [(set (match_dup 0)
468 (sign_extend:DI (match_dup 1)))
469 (set (match_dup 2)
470 (compare:CC (match_dup 0)
471 (const_int 0)))]
472 "")
51b8fc2c 473
1fd4e8c1 474(define_expand "zero_extendqisi2"
cd2b37d9
RK		 475 [(set (match_operand:SI 0 "gpc_reg_operand" "")
476 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 477 ""
478 "")
479
480(define_insn ""
cd2b37d9 481 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 482 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
483 ""
484 "@
485 lbz%U1%X1 %0,%1
005a35b9 486 {rlinm|rlwinm} %0,%1,0,0xff"
1fd4e8c1
RK		 487 [(set_attr "type" "load,*")])
488
489(define_insn ""
9ebbca7d
GK		 490 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
491 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 492 (const_int 0)))
9ebbca7d 493 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 494 ""
9ebbca7d
GK		 495 "@
496 {andil.|andi.} %2,%1,0xff
497 #"
498 [(set_attr "type" "compare")
499 (set_attr "length" "4,8")])
500
501(define_split
502 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
503 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
504 (const_int 0)))
505 (clobber (match_scratch:SI 2 ""))]
506 "reload_completed"
507 [(set (match_dup 2)
508 (zero_extend:SI (match_dup 1)))
509 (set (match_dup 0)
510 (compare:CC (match_dup 2)
511 (const_int 0)))]
512 "")
1fd4e8c1
RK		 513
514(define_insn ""
9ebbca7d
GK		 515 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
516 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 517 (const_int 0)))
9ebbca7d 518 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 519 (zero_extend:SI (match_dup 1)))]
520 ""
9ebbca7d
GK		 521 "@
522 {andil.|andi.} %0,%1,0xff
523 #"
524 [(set_attr "type" "compare")
525 (set_attr "length" "4,8")])
526
527(define_split
528 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
529 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
530 (const_int 0)))
531 (set (match_operand:SI 0 "gpc_reg_operand" "")
532 (zero_extend:SI (match_dup 1)))]
533 "reload_completed"
534 [(set (match_dup 0)
535 (zero_extend:SI (match_dup 1)))
536 (set (match_dup 2)
537 (compare:CC (match_dup 0)
538 (const_int 0)))]
539 "")
1fd4e8c1 540
51b8fc2c
RK		 541(define_expand "extendqisi2"
542 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
543 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
544 ""
545 "
546{
547 if (TARGET_POWERPC)
548 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
549 else if (TARGET_POWER)
550 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
551 else
552 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
553 DONE;
554}")
555
556(define_insn "extendqisi2_ppc"
2bee0449
RK		 557 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
558 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 559 "TARGET_POWERPC"
2bee0449 560 "extsb %0,%1")
51b8fc2c
RK		 561
562(define_insn ""
9ebbca7d
GK		 563 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
564 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 565 (const_int 0)))
9ebbca7d 566 (clobber (match_scratch:SI 2 "=r,r"))]
51b8fc2c 567 "TARGET_POWERPC"
9ebbca7d
GK		 568 "@
569 extsb. %2,%1
570 #"
571 [(set_attr "type" "compare")
572 (set_attr "length" "4,8")])
573
574(define_split
575 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
576 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
577 (const_int 0)))
578 (clobber (match_scratch:SI 2 ""))]
579 "TARGET_POWERPC && reload_completed"
580 [(set (match_dup 2)
581 (sign_extend:SI (match_dup 1)))
582 (set (match_dup 0)
583 (compare:CC (match_dup 2)
584 (const_int 0)))]
585 "")
51b8fc2c
RK		 586
587(define_insn ""
9ebbca7d
GK		 588 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
589 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 590 (const_int 0)))
9ebbca7d 591 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 592 (sign_extend:SI (match_dup 1)))]
593 "TARGET_POWERPC"
9ebbca7d
GK		 594 "@
595 extsb. %0,%1
596 #"
597 [(set_attr "type" "compare")
598 (set_attr "length" "4,8")])
599
600(define_split
601 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
602 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
603 (const_int 0)))
604 (set (match_operand:SI 0 "gpc_reg_operand" "")
605 (sign_extend:SI (match_dup 1)))]
606 "TARGET_POWERPC && reload_completed"
607 [(set (match_dup 0)
608 (sign_extend:SI (match_dup 1)))
609 (set (match_dup 2)
610 (compare:CC (match_dup 0)
611 (const_int 0)))]
612 "")
51b8fc2c
RK		 613
614(define_expand "extendqisi2_power"
615 [(parallel [(set (match_dup 2)
616 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
617 (const_int 24)))
618 (clobber (scratch:SI))])
619 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
620 (ashiftrt:SI (match_dup 2)
621 (const_int 24)))
622 (clobber (scratch:SI))])]
623 "TARGET_POWER"
624 "
625{ operands[1] = gen_lowpart (SImode, operands[1]);
626 operands[2] = gen_reg_rtx (SImode); }")
627
628(define_expand "extendqisi2_no_power"
629 [(set (match_dup 2)
630 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
631 (const_int 24)))
632 (set (match_operand:SI 0 "gpc_reg_operand" "")
633 (ashiftrt:SI (match_dup 2)
634 (const_int 24)))]
635 "! TARGET_POWER && ! TARGET_POWERPC"
636 "
637{ operands[1] = gen_lowpart (SImode, operands[1]);
638 operands[2] = gen_reg_rtx (SImode); }")
639
1fd4e8c1 640(define_expand "zero_extendqihi2"
cd2b37d9
RK		 641 [(set (match_operand:HI 0 "gpc_reg_operand" "")
642 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 643 ""
644 "")
645
646(define_insn ""
cd2b37d9 647 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 648 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
649 ""
650 "@
651 lbz%U1%X1 %0,%1
005a35b9 652 {rlinm|rlwinm} %0,%1,0,0xff"
51b8fc2c
RK		 653 [(set_attr "type" "load,*")])
654
655(define_insn ""
9ebbca7d
GK		 656 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
657 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 658 (const_int 0)))
9ebbca7d 659 (clobber (match_scratch:HI 2 "=r,r"))]
51b8fc2c 660 ""
9ebbca7d
GK		 661 "@
662 {andil.|andi.} %2,%1,0xff
663 #"
664 [(set_attr "type" "compare")
665 (set_attr "length" "4,8")])
666
667(define_split
668 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
669 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
670 (const_int 0)))
671 (clobber (match_scratch:HI 2 ""))]
672 "reload_completed"
673 [(set (match_dup 2)
674 (zero_extend:HI (match_dup 1)))
675 (set (match_dup 0)
676 (compare:CC (match_dup 2)
677 (const_int 0)))]
678 "")
1fd4e8c1 679
51b8fc2c 680(define_insn ""
9ebbca7d
GK		 681 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
682 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 683 (const_int 0)))
9ebbca7d 684 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 685 (zero_extend:HI (match_dup 1)))]
686 ""
9ebbca7d
GK		 687 "@
688 {andil.|andi.} %0,%1,0xff
689 #"
690 [(set_attr "type" "compare")
691 (set_attr "length" "4,8")])
692
693(define_split
694 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
695 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
696 (const_int 0)))
697 (set (match_operand:HI 0 "gpc_reg_operand" "")
698 (zero_extend:HI (match_dup 1)))]
699 "reload_completed"
700 [(set (match_dup 0)
701 (zero_extend:HI (match_dup 1)))
702 (set (match_dup 2)
703 (compare:CC (match_dup 0)
704 (const_int 0)))]
705 "")
815cdc52
MM		 706
707(define_expand "extendqihi2"
708 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
709 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
710 ""
711 "
712{
713 if (TARGET_POWERPC)
714 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
715 else if (TARGET_POWER)
716 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
717 else
718 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
719 DONE;
720}")
721
722(define_insn "extendqihi2_ppc"
723 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
724 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
725 "TARGET_POWERPC"
726 "extsb %0,%1")
727
728(define_insn ""
9ebbca7d
GK		 729 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
730 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815cdc52 731 (const_int 0)))
9ebbca7d 732 (clobber (match_scratch:HI 2 "=r,r"))]
815cdc52 733 "TARGET_POWERPC"
9ebbca7d
GK		 734 "@
735 extsb. %2,%1
736 #"
737 [(set_attr "type" "compare")
738 (set_attr "length" "4,8")])
739
740(define_split
741 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
742 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
743 (const_int 0)))
744 (clobber (match_scratch:HI 2 ""))]
745 "TARGET_POWERPC && reload_completed"
746 [(set (match_dup 2)
747 (sign_extend:HI (match_dup 1)))
748 (set (match_dup 0)
749 (compare:CC (match_dup 2)
750 (const_int 0)))]
751 "")
815cdc52
MM		 752
753(define_insn ""
9ebbca7d
GK		 754 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
755 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 756 (const_int 0)))
9ebbca7d 757 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 758 (sign_extend:HI (match_dup 1)))]
759 "TARGET_POWERPC"
9ebbca7d
GK		 760 "@
761 extsb. %0,%1
762 #"
763 [(set_attr "type" "compare")
764 (set_attr "length" "4,8")])
765
766(define_split
767 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
768 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
769 (const_int 0)))
770 (set (match_operand:HI 0 "gpc_reg_operand" "")
771 (sign_extend:HI (match_dup 1)))]
772 "TARGET_POWERPC && reload_completed"
773 [(set (match_dup 0)
774 (sign_extend:HI (match_dup 1)))
775 (set (match_dup 2)
776 (compare:CC (match_dup 0)
777 (const_int 0)))]
778 "")
51b8fc2c
RK		 779
780(define_expand "extendqihi2_power"
781 [(parallel [(set (match_dup 2)
782 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
783 (const_int 24)))
784 (clobber (scratch:SI))])
785 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
786 (ashiftrt:SI (match_dup 2)
787 (const_int 24)))
788 (clobber (scratch:SI))])]
789 "TARGET_POWER"
790 "
791{ operands[0] = gen_lowpart (SImode, operands[0]);
792 operands[1] = gen_lowpart (SImode, operands[1]);
793 operands[2] = gen_reg_rtx (SImode); }")
794
795(define_expand "extendqihi2_no_power"
796 [(set (match_dup 2)
797 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
798 (const_int 24)))
799 (set (match_operand:HI 0 "gpc_reg_operand" "")
800 (ashiftrt:SI (match_dup 2)
801 (const_int 24)))]
802 "! TARGET_POWER && ! TARGET_POWERPC"
803 "
804{ operands[0] = gen_lowpart (SImode, operands[0]);
805 operands[1] = gen_lowpart (SImode, operands[1]);
806 operands[2] = gen_reg_rtx (SImode); }")
807
1fd4e8c1 808(define_expand "zero_extendhisi2"
5f243543 809 [(set (match_operand:SI 0 "gpc_reg_operand" "")
cd2b37d9 810 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 811 ""
812 "")
813
814(define_insn ""
cd2b37d9 815 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 816 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
817 ""
818 "@
819 lhz%U1%X1 %0,%1
005a35b9 820 {rlinm|rlwinm} %0,%1,0,0xffff"
1fd4e8c1
RK		 821 [(set_attr "type" "load,*")])
822
823(define_insn ""
9ebbca7d
GK		 824 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
825 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 826 (const_int 0)))
9ebbca7d 827 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 828 ""
9ebbca7d
GK		 829 "@
830 {andil.|andi.} %2,%1,0xffff
831 #"
832 [(set_attr "type" "compare")
833 (set_attr "length" "4,8")])
834
835(define_split
836 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
837 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
838 (const_int 0)))
839 (clobber (match_scratch:SI 2 ""))]
840 "reload_completed"
841 [(set (match_dup 2)
842 (zero_extend:SI (match_dup 1)))
843 (set (match_dup 0)
844 (compare:CC (match_dup 2)
845 (const_int 0)))]
846 "")
1fd4e8c1
RK		 847
848(define_insn ""
9ebbca7d
GK		 849 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
850 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 851 (const_int 0)))
9ebbca7d 852 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 853 (zero_extend:SI (match_dup 1)))]
854 ""
9ebbca7d
GK		 855 "@
856 {andil.|andi.} %0,%1,0xffff
857 #"
858 [(set_attr "type" "compare")
859 (set_attr "length" "4,8")])
860
861(define_split
862 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
863 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
864 (const_int 0)))
865 (set (match_operand:SI 0 "gpc_reg_operand" "")
866 (zero_extend:SI (match_dup 1)))]
867 "reload_completed"
868 [(set (match_dup 0)
869 (zero_extend:SI (match_dup 1)))
870 (set (match_dup 2)
871 (compare:CC (match_dup 0)
872 (const_int 0)))]
873 "")
1fd4e8c1
RK		 874
875(define_expand "extendhisi2"
cd2b37d9
RK		 876 [(set (match_operand:SI 0 "gpc_reg_operand" "")
877 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 878 ""
879 "")
880
881(define_insn ""
cd2b37d9 882 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 883 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
884 ""
885 "@
886 lha%U1%X1 %0,%1
ca7f5001 887 {exts|extsh} %0,%1"
b54cf83a 888 [(set_attr "type" "load_ext,*")])
1fd4e8c1
RK		 889
890(define_insn ""
9ebbca7d
GK		 891 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
892 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 893 (const_int 0)))
9ebbca7d 894 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 895 ""
9ebbca7d
GK		 896 "@
897 {exts.|extsh.} %2,%1
898 #"
899 [(set_attr "type" "compare")
900 (set_attr "length" "4,8")])
901
902(define_split
903 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
904 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
905 (const_int 0)))
906 (clobber (match_scratch:SI 2 ""))]
907 "reload_completed"
908 [(set (match_dup 2)
909 (sign_extend:SI (match_dup 1)))
910 (set (match_dup 0)
911 (compare:CC (match_dup 2)
912 (const_int 0)))]
913 "")
1fd4e8c1
RK		 914
915(define_insn ""
9ebbca7d
GK		 916 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
917 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 918 (const_int 0)))
9ebbca7d 919 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 920 (sign_extend:SI (match_dup 1)))]
921 ""
9ebbca7d
GK		 922 "@
923 {exts.|extsh.} %0,%1
924 #"
925 [(set_attr "type" "compare")
926 (set_attr "length" "4,8")])
1fd4e8c1 927\f
9ebbca7d
GK		 928(define_split
929 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
930 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
931 (const_int 0)))
932 (set (match_operand:SI 0 "gpc_reg_operand" "")
933 (sign_extend:SI (match_dup 1)))]
934 "reload_completed"
935 [(set (match_dup 0)
936 (sign_extend:SI (match_dup 1)))
937 (set (match_dup 2)
938 (compare:CC (match_dup 0)
939 (const_int 0)))]
940 "")
941
1fd4e8c1 942;; Fixed-point arithmetic insns.
deb9225a
RK		 943
944;; Discourage ai/addic because of carry but provide it in an alternative
945;; allowing register zero as source.
7cd5235b
MM		 946(define_expand "addsi3"
947 [(set (match_operand:SI 0 "gpc_reg_operand" "")
948 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
f6bf7de2 949 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
7cd5235b
MM		 950 ""
951 "
952{
677a9668
DE		 953 if (GET_CODE (operands[2]) == CONST_INT
954 && ! add_operand (operands[2], SImode))
7cd5235b 955 {
677a9668 956 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 957 ? operands[0] : gen_reg_rtx (SImode));
958
2bfcf297 959 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 960 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2bfcf297 961 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
7cd5235b 962
9ebbca7d
GK		 963 /* The ordering here is important for the prolog expander.
964 When space is allocated from the stack, adding 'low' first may
965 produce a temporary deallocation (which would be bad). */
2bfcf297 966 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
7cd5235b
MM		 967 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
968 DONE;
969 }
970}")
971
972(define_insn "*addsi3_internal1"
973 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
974 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
9615f239 975 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1fd4e8c1
RK		 976 ""
977 "@
deb9225a
RK		 978 {cax|add} %0,%1,%2
979 {cal %0,%2(%1)|addi %0,%1,%2}
980 {ai|addic} %0,%1,%2
7cd5235b
MM		 981 {cau|addis} %0,%1,%v2"
982 [(set_attr "length" "4,4,4,4")])
1fd4e8c1 983
ee890fe2
SS		 984(define_insn "addsi3_high"
985 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
986 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
987 (high:SI (match_operand 2 "" ""))))]
988 "TARGET_MACHO && !TARGET_64BIT"
989 "{cau|addis} %0,%1,ha16(%2)"
990 [(set_attr "length" "4")])
991
7cd5235b 992(define_insn "*addsi3_internal2"
cb8cc086
MM		 993 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
994 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
995 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 996 (const_int 0)))
cb8cc086 997 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
0ad91047 998 "! TARGET_POWERPC64"
deb9225a
RK		 999 "@
1000 {cax.|add.} %3,%1,%2
cb8cc086
MM		 1001 {ai.|addic.} %3,%1,%2
1002 #
1003 #"
a62bfff2 1004 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1005 (set_attr "length" "4,4,8,8")])
1006
1007(define_split
1008 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1009 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1010 (match_operand:SI 2 "reg_or_short_operand" ""))
1011 (const_int 0)))
1012 (clobber (match_scratch:SI 3 ""))]
0ad91047 1013 "! TARGET_POWERPC64 && reload_completed"
cb8cc086
MM		 1014 [(set (match_dup 3)
1015 (plus:SI (match_dup 1)
1016 (match_dup 2)))
1017 (set (match_dup 0)
1018 (compare:CC (match_dup 3)
1019 (const_int 0)))]
1020 "")
7e69e155 1021
7cd5235b 1022(define_insn "*addsi3_internal3"
cb8cc086
MM		 1023 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1024 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1025 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1026 (const_int 0)))
cb8cc086
MM		 1027 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1028 (plus:SI (match_dup 1)
1029 (match_dup 2)))]
0ad91047 1030 "! TARGET_POWERPC64"
deb9225a
RK		 1031 "@
1032 {cax.|add.} %0,%1,%2
cb8cc086
MM		 1033 {ai.|addic.} %0,%1,%2
1034 #
1035 #"
a62bfff2 1036 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1037 (set_attr "length" "4,4,8,8")])
1038
1039(define_split
1040 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1041 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1042 (match_operand:SI 2 "reg_or_short_operand" ""))
1043 (const_int 0)))
1044 (set (match_operand:SI 0 "gpc_reg_operand" "")
1045 (plus:SI (match_dup 1) (match_dup 2)))]
0ad91047 1046 "! TARGET_POWERPC64 && reload_completed"
cb8cc086
MM		 1047 [(set (match_dup 0)
1048 (plus:SI (match_dup 1)
1049 (match_dup 2)))
1050 (set (match_dup 3)
1051 (compare:CC (match_dup 0)
1052 (const_int 0)))]
1053 "")
7e69e155 1054
f357808b
RK		 1055;; Split an add that we can't do in one insn into two insns, each of which
1056;; does one 16-bit part. This is used by combine. Note that the low-order
1057;; add should be last in case the result gets used in an address.
1058
1059(define_split
cd2b37d9
RK		 1060 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1061 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
f357808b 1062 (match_operand:SI 2 "non_add_cint_operand" "")))]
1fd4e8c1 1063 ""
f357808b
RK		 1064 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1065 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1066"
1fd4e8c1 1067{
2bfcf297 1068 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1069 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2bfcf297 1070 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1fd4e8c1 1071
2bfcf297 1072 operands[3] = GEN_INT (rest);
e6ca2c17 1073 operands[4] = GEN_INT (low);
1fd4e8c1
RK		 1074}")
1075
8de2a197 1076(define_insn "one_cmplsi2"
cd2b37d9
RK		 1077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1078 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1fd4e8c1 1079 ""
ca7f5001
RK		 1080 "nor %0,%1,%1")
1081
1082(define_insn ""
52d3af72
DE		 1083 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1084 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
ca7f5001 1085 (const_int 0)))
52d3af72 1086 (clobber (match_scratch:SI 2 "=r,r"))]
0ad91047 1087 "! TARGET_POWERPC64"
52d3af72
DE		 1088 "@
1089 nor. %2,%1,%1
1090 #"
1091 [(set_attr "type" "compare")
1092 (set_attr "length" "4,8")])
1093
1094(define_split
1095 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1096 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1097 (const_int 0)))
1098 (clobber (match_scratch:SI 2 ""))]
0ad91047 1099 "! TARGET_POWERPC64 && reload_completed"
52d3af72
DE		 1100 [(set (match_dup 2)
1101 (not:SI (match_dup 1)))
1102 (set (match_dup 0)
1103 (compare:CC (match_dup 2)
1104 (const_int 0)))]
1105 "")
ca7f5001
RK		 1106
1107(define_insn ""
52d3af72
DE		 1108 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1109 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
815cdc52 1110 (const_int 0)))
52d3af72 1111 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52 1112 (not:SI (match_dup 1)))]
0ad91047 1113 "! TARGET_POWERPC64"
52d3af72
DE		 1114 "@
1115 nor. %0,%1,%1
1116 #"
1117 [(set_attr "type" "compare")
1118 (set_attr "length" "4,8")])
1119
1120(define_split
1121 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1122 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1123 (const_int 0)))
1cb18e3c 1124 (set (match_operand:SI 0 "gpc_reg_operand" "")
52d3af72 1125 (not:SI (match_dup 1)))]
0ad91047 1126 "! TARGET_POWERPC64 && reload_completed"
52d3af72
DE		 1127 [(set (match_dup 0)
1128 (not:SI (match_dup 1)))
1129 (set (match_dup 2)
1130 (compare:CC (match_dup 0)
1131 (const_int 0)))]
1132 "")
1fd4e8c1
RK		 1133
1134(define_insn ""
3d91674b
RK		 1135 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1136 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1137 (match_operand:SI 2 "gpc_reg_operand" "r")))]
deb9225a 1138 "! TARGET_POWERPC"
ca7f5001 1139 "{sf%I1|subf%I1c} %0,%2,%1")
1fd4e8c1 1140
deb9225a
RK		 1141(define_insn ""
1142 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1143 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1144 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1145 "TARGET_POWERPC"
1146 "@
1147 subf %0,%2,%1
1148 subfic %0,%2,%1")
1149
1fd4e8c1 1150(define_insn ""
cb8cc086
MM		 1151 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1152 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1153 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1154 (const_int 0)))
cb8cc086 1155 (clobber (match_scratch:SI 3 "=r,r"))]
deb9225a 1156 "! TARGET_POWERPC"
cb8cc086
MM		 1157 "@
1158 {sf.|subfc.} %3,%2,%1
1159 #"
1160 [(set_attr "type" "compare")
1161 (set_attr "length" "4,8")])
1fd4e8c1 1162
deb9225a 1163(define_insn ""
cb8cc086
MM		 1164 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1165 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1166 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
deb9225a 1167 (const_int 0)))
cb8cc086 1168 (clobber (match_scratch:SI 3 "=r,r"))]
0ad91047 1169 "TARGET_POWERPC && ! TARGET_POWERPC64"
cb8cc086
MM		 1170 "@
1171 subf. %3,%2,%1
1172 #"
a62bfff2 1173 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1174 (set_attr "length" "4,8")])
1175
1176(define_split
1177 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1178 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1179 (match_operand:SI 2 "gpc_reg_operand" ""))
1180 (const_int 0)))
1181 (clobber (match_scratch:SI 3 ""))]
0ad91047 1182 "! TARGET_POWERPC64 && reload_completed"
cb8cc086
MM		 1183 [(set (match_dup 3)
1184 (minus:SI (match_dup 1)
1185 (match_dup 2)))
1186 (set (match_dup 0)
1187 (compare:CC (match_dup 3)
1188 (const_int 0)))]
1189 "")
deb9225a 1190
1fd4e8c1 1191(define_insn ""
cb8cc086
MM		 1192 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1193 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1194 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1195 (const_int 0)))
cb8cc086 1196 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 1197 (minus:SI (match_dup 1) (match_dup 2)))]
deb9225a 1198 "! TARGET_POWERPC"
cb8cc086
MM		 1199 "@
1200 {sf.|subfc.} %0,%2,%1
1201 #"
1202 [(set_attr "type" "compare")
1203 (set_attr "length" "4,8")])
815cdc52 1204
29ae5b89 1205(define_insn ""
cb8cc086
MM		 1206 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1207 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1208 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
815cdc52 1209 (const_int 0)))
cb8cc086
MM		 1210 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1211 (minus:SI (match_dup 1)
1212 (match_dup 2)))]
0ad91047 1213 "TARGET_POWERPC && ! TARGET_POWERPC64"
90612787
DE		 1214 "@
1215 subf. %0,%2,%1
1216 #"
a62bfff2 1217 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1218 (set_attr "length" "4,8")])
1219
1220(define_split
1221 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1222 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1223 (match_operand:SI 2 "gpc_reg_operand" ""))
1224 (const_int 0)))
1225 (set (match_operand:SI 0 "gpc_reg_operand" "")
1226 (minus:SI (match_dup 1)
1227 (match_dup 2)))]
0ad91047 1228 "! TARGET_POWERPC64 && reload_completed"
cb8cc086
MM		 1229 [(set (match_dup 0)
1230 (minus:SI (match_dup 1)
1231 (match_dup 2)))
1232 (set (match_dup 3)
1233 (compare:CC (match_dup 0)
1234 (const_int 0)))]
1235 "")
deb9225a 1236
1fd4e8c1 1237(define_expand "subsi3"
cd2b37d9 1238 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1239 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
f6bf7de2 1240 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1fd4e8c1 1241 ""
a0044fb1
RK		 1242 "
1243{
1244 if (GET_CODE (operands[2]) == CONST_INT)
1245 {
1246 emit_insn (gen_addsi3 (operands[0], operands[1],
1247 negate_rtx (SImode, operands[2])));
1248 DONE;
1249 }
1250}")
1fd4e8c1
RK		 1251
1252;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1253;; instruction and some auxiliary computations. Then we just have a single
95ac8e67
RK		 1254;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1255;; combine.
1fd4e8c1
RK		 1256
1257(define_expand "sminsi3"
1258 [(set (match_dup 3)
cd2b37d9 1259 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1260 (match_operand:SI 2 "reg_or_short_operand" ""))
1261 (const_int 0)
1262 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1263 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1264 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1265 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1266 "
a3170dc6
AH		 1267{
1268 if (TARGET_ISEL)
1269 {
1270 operands[2] = force_reg (SImode, operands[2]);
1271 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1272 DONE;
1273 }
1274
1275 operands[3] = gen_reg_rtx (SImode);
1276}")
1fd4e8c1 1277
95ac8e67
RK		 1278(define_split
1279 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1280 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1281 (match_operand:SI 2 "reg_or_short_operand" "")))
1282 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1283 "TARGET_POWER"
95ac8e67
RK		 1284 [(set (match_dup 3)
1285 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1286 (const_int 0)
1287 (minus:SI (match_dup 2) (match_dup 1))))
1288 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1289 "")
1290
1fd4e8c1
RK		 1291(define_expand "smaxsi3"
1292 [(set (match_dup 3)
cd2b37d9 1293 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1294 (match_operand:SI 2 "reg_or_short_operand" ""))
1295 (const_int 0)
1296 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1297 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1298 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1299 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1300 "
a3170dc6
AH		 1301{
1302 if (TARGET_ISEL)
1303 {
1304 operands[2] = force_reg (SImode, operands[2]);
1305 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1306 DONE;
1307 }
1308 operands[3] = gen_reg_rtx (SImode);
1309}")
1fd4e8c1 1310
95ac8e67
RK		 1311(define_split
1312 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1313 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1314 (match_operand:SI 2 "reg_or_short_operand" "")))
1315 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1316 "TARGET_POWER"
95ac8e67
RK		 1317 [(set (match_dup 3)
1318 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1319 (const_int 0)
1320 (minus:SI (match_dup 2) (match_dup 1))))
1321 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1322 "")
1323
1fd4e8c1 1324(define_expand "uminsi3"
cd2b37d9 1325 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1326 (match_dup 5)))
cd2b37d9 1327 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1328 (match_dup 5)))
1fd4e8c1
RK		 1329 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1330 (const_int 0)
1331 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1332 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1333 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1334 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1335 "
bb68ff55 1336{
a3170dc6
AH		 1337 if (TARGET_ISEL)
1338 {
1339 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1340 DONE;
1341 }
bb68ff55
MM		 1342 operands[3] = gen_reg_rtx (SImode);
1343 operands[4] = gen_reg_rtx (SImode);
1344 operands[5] = GEN_INT (-2147483647 - 1);
1345}")
1fd4e8c1
RK		 1346
1347(define_expand "umaxsi3"
cd2b37d9 1348 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1349 (match_dup 5)))
cd2b37d9 1350 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1351 (match_dup 5)))
1fd4e8c1
RK		 1352 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1353 (const_int 0)
1354 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1355 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1356 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1357 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1358 "
bb68ff55 1359{
a3170dc6
AH		 1360 if (TARGET_ISEL)
1361 {
1362 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1363 DONE;
1364 }
bb68ff55
MM		 1365 operands[3] = gen_reg_rtx (SImode);
1366 operands[4] = gen_reg_rtx (SImode);
1367 operands[5] = GEN_INT (-2147483647 - 1);
1368}")
1fd4e8c1
RK		 1369
1370(define_insn ""
cd2b37d9
RK		 1371 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1372 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
5c23c401 1373 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 1374 (const_int 0)
1375 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1376 "TARGET_POWER"
1fd4e8c1
RK		 1377 "doz%I2 %0,%1,%2")
1378
1379(define_insn ""
9ebbca7d 1380 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 1381 (compare:CC
9ebbca7d
GK		 1382 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1383 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1384 (const_int 0)
1385 (minus:SI (match_dup 2) (match_dup 1)))
1386 (const_int 0)))
9ebbca7d 1387 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 1388 "TARGET_POWER"
9ebbca7d
GK		 1389 "@
1390 doz%I2. %3,%1,%2
1391 #"
1392 [(set_attr "type" "delayed_compare")
1393 (set_attr "length" "4,8")])
1394
1395(define_split
1396 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1397 (compare:CC
1398 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1399 (match_operand:SI 2 "reg_or_short_operand" ""))
1400 (const_int 0)
1401 (minus:SI (match_dup 2) (match_dup 1)))
1402 (const_int 0)))
1403 (clobber (match_scratch:SI 3 ""))]
1404 "TARGET_POWER && reload_completed"
1405 [(set (match_dup 3)
1406 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1407 (const_int 0)
1408 (minus:SI (match_dup 2) (match_dup 1))))
1409 (set (match_dup 0)
1410 (compare:CC (match_dup 3)
1411 (const_int 0)))]
1412 "")
1fd4e8c1
RK		 1413
1414(define_insn ""
9ebbca7d 1415 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 1416 (compare:CC
9ebbca7d
GK		 1417 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1418 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1419 (const_int 0)
1420 (minus:SI (match_dup 2) (match_dup 1)))
1421 (const_int 0)))
9ebbca7d 1422 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 1423 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1424 (const_int 0)
1425 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1426 "TARGET_POWER"
9ebbca7d
GK		 1427 "@
1428 doz%I2. %0,%1,%2
1429 #"
1430 [(set_attr "type" "delayed_compare")
1431 (set_attr "length" "4,8")])
1432
1433(define_split
1434 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1435 (compare:CC
1436 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1437 (match_operand:SI 2 "reg_or_short_operand" ""))
1438 (const_int 0)
1439 (minus:SI (match_dup 2) (match_dup 1)))
1440 (const_int 0)))
1441 (set (match_operand:SI 0 "gpc_reg_operand" "")
1442 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1443 (const_int 0)
1444 (minus:SI (match_dup 2) (match_dup 1))))]
1445 "TARGET_POWER && reload_completed"
1446 [(set (match_dup 0)
1447 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1448 (const_int 0)
1449 (minus:SI (match_dup 2) (match_dup 1))))
1450 (set (match_dup 3)
1451 (compare:CC (match_dup 0)
1452 (const_int 0)))]
1453 "")
1fd4e8c1
RK		 1454
1455;; We don't need abs with condition code because such comparisons should
1456;; never be done.
ea9be077
MM		 1457(define_expand "abssi2"
1458 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1459 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1460 ""
1461 "
1462{
a3170dc6
AH		 1463 if (TARGET_ISEL)
1464 {
1465 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1466 DONE;
1467 }
1468 else if (! TARGET_POWER)
ea9be077
MM		 1469 {
1470 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1471 DONE;
1472 }
1473}")
1474
ea112fc4 1475(define_insn "*abssi2_power"
cd2b37d9
RK		 1476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1477 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
ca7f5001 1478 "TARGET_POWER"
1fd4e8c1
RK		 1479 "abs %0,%1")
1480
a3170dc6
AH		 1481(define_insn_and_split "abssi2_isel"
1482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1483 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1484 (clobber (match_scratch:SI 2 "=b"))
1485 (clobber (match_scratch:CC 3 "=y"))]
1486 "TARGET_ISEL"
1487 "#"
1488 "&& reload_completed"
1489 [(set (match_dup 2) (neg:SI (match_dup 1)))
1490 (set (match_dup 3)
1491 (compare:CC (match_dup 1)
1492 (const_int 0)))
1493 (set (match_dup 0)
1494 (if_then_else:SI (ge (match_dup 3)
1495 (const_int 0))
1496 (match_dup 1)
1497 (match_dup 2)))]
1498 "")
1499
ea112fc4 1500(define_insn_and_split "abssi2_nopower"
ea9be077 1501 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 1502 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
ea9be077 1503 (clobber (match_scratch:SI 2 "=&r,&r"))]
a3170dc6 1504 "! TARGET_POWER && ! TARGET_ISEL"
ea112fc4
DE		 1505 "#"
1506 "&& reload_completed"
ea9be077
MM		 1507 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1508 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 1509 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
ea9be077
MM		 1510 "")
1511
463b558b 1512(define_insn "*nabs_power"
cd2b37d9
RK		 1513 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1514 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
ca7f5001 1515 "TARGET_POWER"
1fd4e8c1
RK		 1516 "nabs %0,%1")
1517
ea112fc4 1518(define_insn_and_split "*nabs_nopower"
ea9be077 1519 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 1520 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
ea9be077 1521 (clobber (match_scratch:SI 2 "=&r,&r"))]
0ad91047 1522 "! TARGET_POWER"
ea112fc4
DE		 1523 "#"
1524 "&& reload_completed"
ea9be077
MM		 1525 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1526 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 1527 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
ea9be077
MM		 1528 "")
1529
1fd4e8c1 1530(define_insn "negsi2"
cd2b37d9
RK		 1531 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1532 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1fd4e8c1
RK		 1533 ""
1534 "neg %0,%1")
1535
1536(define_insn ""
9ebbca7d
GK		 1537 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1538 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 1539 (const_int 0)))
9ebbca7d 1540 (clobber (match_scratch:SI 2 "=r,r"))]
0ad91047 1541 "! TARGET_POWERPC64"
9ebbca7d
GK		 1542 "@
1543 neg. %2,%1
1544 #"
a62bfff2 1545 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 1546 (set_attr "length" "4,8")])
1547
1548(define_split
1549 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1550 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1551 (const_int 0)))
1552 (clobber (match_scratch:SI 2 ""))]
1553 "! TARGET_POWERPC64 && reload_completed"
1554 [(set (match_dup 2)
1555 (neg:SI (match_dup 1)))
1556 (set (match_dup 0)
1557 (compare:CC (match_dup 2)
1558 (const_int 0)))]
1559 "")
1fd4e8c1
RK		 1560
1561(define_insn ""
9ebbca7d
GK		 1562 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1563 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
815cdc52 1564 (const_int 0)))
9ebbca7d 1565 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52 1566 (neg:SI (match_dup 1)))]
0ad91047 1567 "! TARGET_POWERPC64"
9ebbca7d
GK		 1568 "@
1569 neg. %0,%1
1570 #"
a62bfff2 1571 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 1572 (set_attr "length" "4,8")])
1573
1574(define_split
1575 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1576 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1577 (const_int 0)))
1578 (set (match_operand:SI 0 "gpc_reg_operand" "")
1579 (neg:SI (match_dup 1)))]
1580 "! TARGET_POWERPC64 && reload_completed"
1581 [(set (match_dup 0)
1582 (neg:SI (match_dup 1)))
1583 (set (match_dup 2)
1584 (compare:CC (match_dup 0)
1585 (const_int 0)))]
1586 "")
1fd4e8c1 1587
1b1edcfa
DE		 1588(define_insn "clzsi2"
1589 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1590 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1591 ""
1592 "{cntlz|cntlzw} %0,%1")
1593
1594(define_expand "ctzsi2"
4977bab6 1595 [(set (match_dup 2)
1b1edcfa 1596 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
4977bab6 1597 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1b1edcfa
DE		 1598 (match_dup 2)))
1599 (clobber (scratch:CC))])
d865b122 1600 (set (match_dup 4) (clz:SI (match_dup 3)))
4977bab6 1601 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1b1edcfa 1602 (minus:SI (const_int 31) (match_dup 4)))]
1fd4e8c1 1603 ""
4977bab6
ZW		 1604 {
1605 operands[2] = gen_reg_rtx (SImode);
1606 operands[3] = gen_reg_rtx (SImode);
1607 operands[4] = gen_reg_rtx (SImode);
1608 })
1609
1b1edcfa
DE		 1610(define_expand "ffssi2"
1611 [(set (match_dup 2)
1612 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1613 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1614 (match_dup 2)))
1615 (clobber (scratch:CC))])
1616 (set (match_dup 4) (clz:SI (match_dup 3)))
1617 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1618 (minus:SI (const_int 32) (match_dup 4)))]
4977bab6 1619 ""
1b1edcfa
DE		 1620 {
1621 operands[2] = gen_reg_rtx (SImode);
1622 operands[3] = gen_reg_rtx (SImode);
1623 operands[4] = gen_reg_rtx (SImode);
1624 })
1625
ca7f5001
RK		 1626(define_expand "mulsi3"
1627 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1628 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1629 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1630 ""
1631 "
1632{
1633 if (TARGET_POWER)
68b40e7e 1634 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
ca7f5001 1635 else
68b40e7e 1636 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
ca7f5001
RK		 1637 DONE;
1638}")
1639
68b40e7e 1640(define_insn "mulsi3_mq"
cd2b37d9
RK		 1641 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1642 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1fd4e8c1
RK		 1643 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1644 (clobber (match_scratch:SI 3 "=q,q"))]
ca7f5001
RK		 1645 "TARGET_POWER"
1646 "@
1647 {muls|mullw} %0,%1,%2
1648 {muli|mulli} %0,%1,%2"
c859cda6
DJ		 1649 [(set (attr "type")
1650 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1651 (const_string "imul3")
1652 (match_operand:SI 2 "short_cint_operand" "")
1653 (const_string "imul2")]
1654 (const_string "imul")))])
ca7f5001 1655
68b40e7e 1656(define_insn "mulsi3_no_mq"
ca7f5001
RK		 1657 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1658 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1659 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
68b40e7e 1660 "! TARGET_POWER"
1fd4e8c1 1661 "@
d904e9ed
RK		 1662 {muls|mullw} %0,%1,%2
1663 {muli|mulli} %0,%1,%2"
c859cda6
DJ		 1664 [(set (attr "type")
1665 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1666 (const_string "imul3")
1667 (match_operand:SI 2 "short_cint_operand" "")
1668 (const_string "imul2")]
1669 (const_string "imul")))])
1fd4e8c1
RK		 1670
1671(define_insn ""
9ebbca7d
GK		 1672 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1673 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1674 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1675 (const_int 0)))
9ebbca7d
GK		 1676 (clobber (match_scratch:SI 3 "=r,r"))
1677 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 1678 "TARGET_POWER"
9ebbca7d
GK		 1679 "@
1680 {muls.|mullw.} %3,%1,%2
1681 #"
1682 [(set_attr "type" "delayed_compare")
1683 (set_attr "length" "4,8")])
1684
1685(define_split
1686 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1687 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1688 (match_operand:SI 2 "gpc_reg_operand" ""))
1689 (const_int 0)))
1690 (clobber (match_scratch:SI 3 ""))
1691 (clobber (match_scratch:SI 4 ""))]
1692 "TARGET_POWER && reload_completed"
1693 [(parallel [(set (match_dup 3)
1694 (mult:SI (match_dup 1) (match_dup 2)))
1695 (clobber (match_dup 4))])
1696 (set (match_dup 0)
1697 (compare:CC (match_dup 3)
1698 (const_int 0)))]
1699 "")
ca7f5001
RK		 1700
1701(define_insn ""
9ebbca7d
GK		 1702 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1703 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1704 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 1705 (const_int 0)))
9ebbca7d 1706 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 1707 "! TARGET_POWER"
9ebbca7d
GK		 1708 "@
1709 {muls.|mullw.} %3,%1,%2
1710 #"
1711 [(set_attr "type" "delayed_compare")
1712 (set_attr "length" "4,8")])
1713
1714(define_split
1715 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1716 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1717 (match_operand:SI 2 "gpc_reg_operand" ""))
1718 (const_int 0)))
1719 (clobber (match_scratch:SI 3 ""))]
1720 "! TARGET_POWER && reload_completed"
1721 [(set (match_dup 3)
1722 (mult:SI (match_dup 1) (match_dup 2)))
1723 (set (match_dup 0)
1724 (compare:CC (match_dup 3)
1725 (const_int 0)))]
1726 "")
1fd4e8c1
RK		 1727
1728(define_insn ""
9ebbca7d
GK		 1729 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1730 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1731 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1732 (const_int 0)))
9ebbca7d 1733 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
29ae5b89 1734 (mult:SI (match_dup 1) (match_dup 2)))
9ebbca7d 1735 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 1736 "TARGET_POWER"
9ebbca7d
GK		 1737 "@
1738 {muls.|mullw.} %0,%1,%2
1739 #"
1740 [(set_attr "type" "delayed_compare")
1741 (set_attr "length" "4,8")])
1742
1743(define_split
1744 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1745 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1746 (match_operand:SI 2 "gpc_reg_operand" ""))
1747 (const_int 0)))
1748 (set (match_operand:SI 0 "gpc_reg_operand" "")
1749 (mult:SI (match_dup 1) (match_dup 2)))
1750 (clobber (match_scratch:SI 4 ""))]
1751 "TARGET_POWER && reload_completed"
1752 [(parallel [(set (match_dup 0)
1753 (mult:SI (match_dup 1) (match_dup 2)))
1754 (clobber (match_dup 4))])
1755 (set (match_dup 3)
1756 (compare:CC (match_dup 0)
1757 (const_int 0)))]
1758 "")
ca7f5001
RK		 1759
1760(define_insn ""
9ebbca7d
GK		 1761 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1762 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1763 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 1764 (const_int 0)))
9ebbca7d 1765 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 1766 (mult:SI (match_dup 1) (match_dup 2)))]
25c341fa 1767 "! TARGET_POWER"
9ebbca7d
GK		 1768 "@
1769 {muls.|mullw.} %0,%1,%2
1770 #"
1771 [(set_attr "type" "delayed_compare")
1772 (set_attr "length" "4,8")])
1773
1774(define_split
1775 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1776 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1777 (match_operand:SI 2 "gpc_reg_operand" ""))
1778 (const_int 0)))
1779 (set (match_operand:SI 0 "gpc_reg_operand" "")
1780 (mult:SI (match_dup 1) (match_dup 2)))]
1781 "! TARGET_POWER && reload_completed"
1782 [(set (match_dup 0)
1783 (mult:SI (match_dup 1) (match_dup 2)))
1784 (set (match_dup 3)
1785 (compare:CC (match_dup 0)
1786 (const_int 0)))]
1787 "")
1fd4e8c1
RK		 1788
1789;; Operand 1 is divided by operand 2; quotient goes to operand
1790;; 0 and remainder to operand 3.
1791;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1792
8ffd9c51
RK		 1793(define_expand "divmodsi4"
1794 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1795 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1796 (match_operand:SI 2 "gpc_reg_operand" "")))
bb157ff4 1797 (set (match_operand:SI 3 "register_operand" "")
8ffd9c51
RK		 1798 (mod:SI (match_dup 1) (match_dup 2)))])]
1799 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1800 "
1801{
1802 if (! TARGET_POWER && ! TARGET_POWERPC)
1803 {
39403d82
DE		 1804 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1805 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 1806 emit_insn (gen_divss_call ());
39403d82
DE		 1807 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1808 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
8ffd9c51
RK		 1809 DONE;
1810 }
1811}")
deb9225a 1812
bb157ff4 1813(define_insn "*divmodsi4_internal"
cd2b37d9
RK		 1814 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1815 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1816 (match_operand:SI 2 "gpc_reg_operand" "r")))
bb157ff4 1817 (set (match_operand:SI 3 "register_operand" "=q")
1fd4e8c1 1818 (mod:SI (match_dup 1) (match_dup 2)))]
ca7f5001 1819 "TARGET_POWER"
cfb557c4
RK		 1820 "divs %0,%1,%2"
1821 [(set_attr "type" "idiv")])
1fd4e8c1 1822
8ffd9c51
RK		 1823(define_expand "udivsi3"
1824 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1825 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1826 (match_operand:SI 2 "gpc_reg_operand" "")))]
1827 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1828 "
1829{
1830 if (! TARGET_POWER && ! TARGET_POWERPC)
1831 {
39403d82
DE		 1832 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1833 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 1834 emit_insn (gen_quous_call ());
39403d82 1835 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 1836 DONE;
1837 }
f192bf8b
DE		 1838 else if (TARGET_POWER)
1839 {
1840 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1841 DONE;
1842 }
8ffd9c51 1843}")
deb9225a 1844
f192bf8b
DE		 1845(define_insn "udivsi3_mq"
1846 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1847 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1848 (match_operand:SI 2 "gpc_reg_operand" "r")))
1849 (clobber (match_scratch:SI 3 "=q"))]
1850 "TARGET_POWERPC && TARGET_POWER"
1851 "divwu %0,%1,%2"
1852 [(set_attr "type" "idiv")])
1853
1854(define_insn "*udivsi3_no_mq"
ca7f5001
RK		 1855 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1856 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1857 (match_operand:SI 2 "gpc_reg_operand" "r")))]
f192bf8b 1858 "TARGET_POWERPC && ! TARGET_POWER"
a473029f 1859 "divwu %0,%1,%2"
ca7f5001
RK		 1860 [(set_attr "type" "idiv")])
1861
1fd4e8c1 1862;; For powers of two we can do srai/aze for divide and then adjust for
ca7f5001 1863;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
8ffd9c51
RK		 1864;; used; for PowerPC, force operands into register and do a normal divide;
1865;; for AIX common-mode, use quoss call on register operands.
1fd4e8c1 1866(define_expand "divsi3"
cd2b37d9
RK		 1867 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1868 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1869 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1870 ""
1871 "
1872{
ca7f5001 1873 if (GET_CODE (operands[2]) == CONST_INT
2bfcf297 1874 && INTVAL (operands[2]) > 0
ca7f5001
RK		 1875 && exact_log2 (INTVAL (operands[2])) >= 0)
1876 ;
b6c9286a 1877 else if (TARGET_POWERPC)
f192bf8b
DE		 1878 {
1879 operands[2] = force_reg (SImode, operands[2]);
1880 if (TARGET_POWER)
1881 {
1882 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1883 DONE;
1884 }
1885 }
b6c9286a 1886 else if (TARGET_POWER)
1fd4e8c1 1887 FAIL;
405c5495 1888 else
8ffd9c51 1889 {
39403d82
DE		 1890 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1891 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 1892 emit_insn (gen_quoss_call ());
39403d82 1893 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 1894 DONE;
1895 }
1fd4e8c1
RK		 1896}")
1897
f192bf8b
DE		 1898(define_insn "divsi3_mq"
1899 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1900 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1901 (match_operand:SI 2 "gpc_reg_operand" "r")))
1902 (clobber (match_scratch:SI 3 "=q"))]
1903 "TARGET_POWERPC && TARGET_POWER"
1904 "divw %0,%1,%2"
1905 [(set_attr "type" "idiv")])
1906
1907(define_insn "*divsi3_no_mq"
1908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1909 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1910 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1911 "TARGET_POWERPC && ! TARGET_POWER"
1912 "divw %0,%1,%2"
1913 [(set_attr "type" "idiv")])
1914
1fd4e8c1 1915(define_expand "modsi3"
85644414
RK		 1916 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1917 (use (match_operand:SI 1 "gpc_reg_operand" ""))
405c5495 1918 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
39b52ba2 1919 ""
1fd4e8c1
RK		 1920 "
1921{
481c7efa 1922 int i;
39b52ba2
RK		 1923 rtx temp1;
1924 rtx temp2;
1925
2bfcf297 1926 if (GET_CODE (operands[2]) != CONST_INT
a65c591c 1927 || INTVAL (operands[2]) <= 0
2bfcf297 1928 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
39b52ba2
RK		 1929 FAIL;
1930
1931 temp1 = gen_reg_rtx (SImode);
1932 temp2 = gen_reg_rtx (SImode);
1fd4e8c1 1933
85644414 1934 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
39b52ba2 1935 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
85644414
RK		 1936 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1937 DONE;
1fd4e8c1
RK		 1938}")
1939
1940(define_insn ""
cd2b37d9
RK		 1941 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1942 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2bfcf297
DB		 1943 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
1944 ""
ca7f5001 1945 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
b19003d8 1946 [(set_attr "length" "8")])
1fd4e8c1
RK		 1947
1948(define_insn ""
9ebbca7d
GK		 1949 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1950 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2bfcf297 1951 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
b6b12107 1952 (const_int 0)))
9ebbca7d 1953 (clobber (match_scratch:SI 3 "=r,r"))]
2bfcf297 1954 ""
9ebbca7d
GK		 1955 "@
1956 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
1957 #"
b19003d8 1958 [(set_attr "type" "compare")
9ebbca7d
GK		 1959 (set_attr "length" "8,12")])
1960
1961(define_split
1962 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1963 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2bfcf297 1964 (match_operand:SI 2 "exact_log2_cint_operand" ""))
9ebbca7d
GK		 1965 (const_int 0)))
1966 (clobber (match_scratch:SI 3 ""))]
2bfcf297 1967 "reload_completed"
9ebbca7d
GK		 1968 [(set (match_dup 3)
1969 (div:SI (match_dup 1) (match_dup 2)))
1970 (set (match_dup 0)
1971 (compare:CC (match_dup 3)
1972 (const_int 0)))]
1973 "")
1fd4e8c1
RK		 1974
1975(define_insn ""
9ebbca7d
GK		 1976 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1977 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2bfcf297 1978 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
b6b12107 1979 (const_int 0)))
9ebbca7d 1980 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
29ae5b89 1981 (div:SI (match_dup 1) (match_dup 2)))]
2bfcf297 1982 ""
9ebbca7d
GK		 1983 "@
1984 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
1985 #"
b19003d8 1986 [(set_attr "type" "compare")
9ebbca7d
GK		 1987 (set_attr "length" "8,12")])
1988
1989(define_split
1990 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1991 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2bfcf297 1992 (match_operand:SI 2 "exact_log2_cint_operand" ""))
9ebbca7d
GK		 1993 (const_int 0)))
1994 (set (match_operand:SI 0 "gpc_reg_operand" "")
1995 (div:SI (match_dup 1) (match_dup 2)))]
2bfcf297 1996 "reload_completed"
9ebbca7d
GK		 1997 [(set (match_dup 0)
1998 (div:SI (match_dup 1) (match_dup 2)))
1999 (set (match_dup 3)
2000 (compare:CC (match_dup 0)
2001 (const_int 0)))]
2002 "")
1fd4e8c1
RK		 2003
2004(define_insn ""
cd2b37d9 2005 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 2006 (udiv:SI
996a5f59 2007 (plus:DI (ashift:DI
cd2b37d9 2008 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 2009 (const_int 32))
23a900dc 2010 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
cd2b37d9 2011 (match_operand:SI 3 "gpc_reg_operand" "r")))
740ab4a2 2012 (set (match_operand:SI 2 "register_operand" "=*q")
1fd4e8c1 2013 (umod:SI
996a5f59 2014 (plus:DI (ashift:DI
1fd4e8c1 2015 (zero_extend:DI (match_dup 1)) (const_int 32))
740ab4a2 2016 (zero_extend:DI (match_dup 4)))
1fd4e8c1 2017 (match_dup 3)))]
ca7f5001 2018 "TARGET_POWER"
cfb557c4
RK		 2019 "div %0,%1,%3"
2020 [(set_attr "type" "idiv")])
1fd4e8c1
RK		 2021
2022;; To do unsigned divide we handle the cases of the divisor looking like a
2023;; negative number. If it is a constant that is less than 2**31, we don't
2024;; have to worry about the branches. So make a few subroutines here.
2025;;
2026;; First comes the normal case.
2027(define_expand "udivmodsi4_normal"
2028 [(set (match_dup 4) (const_int 0))
2029 (parallel [(set (match_operand:SI 0 "" "")
996a5f59 2030 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2031 (const_int 32))
2032 (zero_extend:DI (match_operand:SI 1 "" "")))
2033 (match_operand:SI 2 "" "")))
2034 (set (match_operand:SI 3 "" "")
996a5f59 2035 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2036 (const_int 32))
2037 (zero_extend:DI (match_dup 1)))
2038 (match_dup 2)))])]
ca7f5001 2039 "TARGET_POWER"
1fd4e8c1
RK		 2040 "
2041{ operands[4] = gen_reg_rtx (SImode); }")
2042
2043;; This handles the branches.
2044(define_expand "udivmodsi4_tests"
2045 [(set (match_operand:SI 0 "" "") (const_int 0))
2046 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2047 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2048 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2049 (label_ref (match_operand:SI 4 "" "")) (pc)))
2050 (set (match_dup 0) (const_int 1))
2051 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2052 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2053 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2054 (label_ref (match_dup 4)) (pc)))]
ca7f5001 2055 "TARGET_POWER"
1fd4e8c1
RK		 2056 "
2057{ operands[5] = gen_reg_rtx (CCUNSmode);
2058 operands[6] = gen_reg_rtx (CCmode);
2059}")
2060
2061(define_expand "udivmodsi4"
cd2b37d9
RK		 2062 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2063 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 2064 (match_operand:SI 2 "reg_or_cint_operand" "")))
cd2b37d9 2065 (set (match_operand:SI 3 "gpc_reg_operand" "")
1fd4e8c1 2066 (umod:SI (match_dup 1) (match_dup 2)))])]
8ffd9c51 2067 ""
1fd4e8c1
RK		 2068 "
2069{
2070 rtx label = 0;
2071
8ffd9c51 2072 if (! TARGET_POWER)
c4d38ccb
MM		 2073 {
2074 if (! TARGET_POWERPC)
2075 {
39403d82
DE		 2076 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2077 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
c4d38ccb 2078 emit_insn (gen_divus_call ());
39403d82
DE		 2079 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2080 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
c4d38ccb
MM		 2081 DONE;
2082 }
2083 else
2084 FAIL;
2085 }
0081a354 2086
1fd4e8c1
RK		 2087 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2088 {
2089 operands[2] = force_reg (SImode, operands[2]);
2090 label = gen_label_rtx ();
2091 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2092 operands[3], label));
2093 }
2094 else
2095 operands[2] = force_reg (SImode, operands[2]);
2096
2097 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2098 operands[3]));
2099 if (label)
2100 emit_label (label);
2101
2102 DONE;
2103}")
0081a354 2104
fada905b
MM		 2105;; AIX architecture-independent common-mode multiply (DImode),
2106;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2107;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2108;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2109;; assumed unused if generating common-mode, so ignore.
2110(define_insn "mulh_call"
2111 [(set (reg:SI 3)
2112 (truncate:SI
2113 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2114 (sign_extend:DI (reg:SI 4)))
2115 (const_int 32))))
cf27b467 2116 (clobber (match_scratch:SI 0 "=l"))]
fada905b 2117 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2118 "bla __mulh"
2119 [(set_attr "type" "imul")])
fada905b
MM		 2120
2121(define_insn "mull_call"
2122 [(set (reg:DI 3)
2123 (mult:DI (sign_extend:DI (reg:SI 3))
2124 (sign_extend:DI (reg:SI 4))))
2125 (clobber (match_scratch:SI 0 "=l"))
2126 (clobber (reg:SI 0))]
2127 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2128 "bla __mull"
2129 [(set_attr "type" "imul")])
fada905b
MM		 2130
2131(define_insn "divss_call"
2132 [(set (reg:SI 3)
2133 (div:SI (reg:SI 3) (reg:SI 4)))
2134 (set (reg:SI 4)
2135 (mod:SI (reg:SI 3) (reg:SI 4)))
2136 (clobber (match_scratch:SI 0 "=l"))
2137 (clobber (reg:SI 0))]
2138 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2139 "bla __divss"
2140 [(set_attr "type" "idiv")])
fada905b
MM		 2141
2142(define_insn "divus_call"
8ffd9c51
RK		 2143 [(set (reg:SI 3)
2144 (udiv:SI (reg:SI 3) (reg:SI 4)))
2145 (set (reg:SI 4)
2146 (umod:SI (reg:SI 3) (reg:SI 4)))
2147 (clobber (match_scratch:SI 0 "=l"))
fada905b
MM		 2148 (clobber (reg:SI 0))
2149 (clobber (match_scratch:CC 1 "=x"))
2150 (clobber (reg:CC 69))]
2151 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2152 "bla __divus"
2153 [(set_attr "type" "idiv")])
fada905b
MM		 2154
2155(define_insn "quoss_call"
2156 [(set (reg:SI 3)
2157 (div:SI (reg:SI 3) (reg:SI 4)))
cf27b467 2158 (clobber (match_scratch:SI 0 "=l"))]
8ffd9c51 2159 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2160 "bla __quoss"
2161 [(set_attr "type" "idiv")])
0081a354 2162
fada905b
MM		 2163(define_insn "quous_call"
2164 [(set (reg:SI 3)
2165 (udiv:SI (reg:SI 3) (reg:SI 4)))
2166 (clobber (match_scratch:SI 0 "=l"))
2167 (clobber (reg:SI 0))
2168 (clobber (match_scratch:CC 1 "=x"))
2169 (clobber (reg:CC 69))]
2170 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2171 "bla __quous"
2172 [(set_attr "type" "idiv")])
8ffd9c51 2173\f
bb21487f 2174;; Logical instructions
dfbdccdb
GK		 2175;; The logical instructions are mostly combined by using match_operator,
2176;; but the plain AND insns are somewhat different because there is no
2177;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2178;; those rotate-and-mask operations. Thus, the AND insns come first.
2179
29ae5b89
JL		 2180(define_insn "andsi3"
2181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2182 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
5f59ecb7 2183 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
29ae5b89 2184 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1fd4e8c1
RK		 2185 ""
2186 "@
2187 and %0,%1,%2
ca7f5001
RK		 2188 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2189 {andil.|andi.} %0,%1,%b2
9ebbca7d 2190 {andiu.|andis.} %0,%1,%u2")
52d3af72
DE		 2191
2192;; Note to set cr's other than cr0 we do the and immediate and then
0ba1b2ff 2193;; the test again -- this avoids a mfcr which on the higher end
52d3af72 2194;; machines causes an execution serialization
1fd4e8c1 2195
7cd5235b 2196(define_insn "*andsi3_internal2"
52d3af72
DE		 2197 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2198 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2199 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
1fd4e8c1 2200 (const_int 0)))
52d3af72
DE		 2201 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2202 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
0ad91047 2203 "! TARGET_POWERPC64"
1fd4e8c1
RK		 2204 "@
2205 and. %3,%1,%2
ca7f5001
RK		 2206 {andil.|andi.} %3,%1,%b2
2207 {andiu.|andis.} %3,%1,%u2
52d3af72
DE		 2208 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2209 #
2210 #
2211 #
2212 #"
2213 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2214 (set_attr "length" "4,4,4,4,8,8,8,8")])
1fd4e8c1 2215
0ba1b2ff
AM		 2216(define_insn "*andsi3_internal3"
2217 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2218 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2219 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2220 (const_int 0)))
2221 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2222 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2223 "TARGET_POWERPC64"
2224 "@
2225 #
2226 {andil.|andi.} %3,%1,%b2
2227 {andiu.|andis.} %3,%1,%u2
2228 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2229 #
2230 #
2231 #
2232 #"
2233 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2234 (set_attr "length" "8,4,4,4,8,8,8,8")])
2235
52d3af72
DE		 2236(define_split
2237 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2238 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2239 (match_operand:SI 2 "and_operand" ""))
1fd4e8c1 2240 (const_int 0)))
52d3af72
DE		 2241 (clobber (match_scratch:SI 3 ""))
2242 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2243 "reload_completed"
52d3af72
DE		 2244 [(parallel [(set (match_dup 3)
2245 (and:SI (match_dup 1)
2246 (match_dup 2)))
2247 (clobber (match_dup 4))])
2248 (set (match_dup 0)
2249 (compare:CC (match_dup 3)
2250 (const_int 0)))]
2251 "")
2252
0ba1b2ff
AM		 2253;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2254;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2255
2256(define_split
2257 [(set (match_operand:CC 0 "cc_reg_operand" "")
2258 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2259 (match_operand:SI 2 "gpc_reg_operand" ""))
2260 (const_int 0)))
2261 (clobber (match_scratch:SI 3 ""))
2262 (clobber (match_scratch:CC 4 ""))]
2263 "TARGET_POWERPC64 && reload_completed"
2264 [(parallel [(set (match_dup 3)
2265 (and:SI (match_dup 1)
2266 (match_dup 2)))
2267 (clobber (match_dup 4))])
2268 (set (match_dup 0)
2269 (compare:CC (match_dup 3)
2270 (const_int 0)))]
2271 "")
2272
2273(define_insn "*andsi3_internal4"
52d3af72
DE		 2274 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2275 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2276 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
52d3af72
DE		 2277 (const_int 0)))
2278 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2279 (and:SI (match_dup 1)
2280 (match_dup 2)))
2281 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
0ad91047 2282 "! TARGET_POWERPC64"
1fd4e8c1
RK		 2283 "@
2284 and. %0,%1,%2
ca7f5001
RK		 2285 {andil.|andi.} %0,%1,%b2
2286 {andiu.|andis.} %0,%1,%u2
52d3af72
DE		 2287 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2288 #
2289 #
2290 #
2291 #"
2292 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2293 (set_attr "length" "4,4,4,4,8,8,8,8")])
2294
0ba1b2ff
AM		 2295(define_insn "*andsi3_internal5"
2296 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2297 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2298 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2299 (const_int 0)))
2300 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2301 (and:SI (match_dup 1)
2302 (match_dup 2)))
2303 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2304 "TARGET_POWERPC64"
2305 "@
2306 #
2307 {andil.|andi.} %0,%1,%b2
2308 {andiu.|andis.} %0,%1,%u2
2309 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2310 #
2311 #
2312 #
2313 #"
2314 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2315 (set_attr "length" "8,4,4,4,8,8,8,8")])
2316
52d3af72
DE		 2317(define_split
2318 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2319 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2320 (match_operand:SI 2 "and_operand" ""))
2321 (const_int 0)))
2322 (set (match_operand:SI 0 "gpc_reg_operand" "")
2323 (and:SI (match_dup 1)
2324 (match_dup 2)))
2325 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2326 "reload_completed"
52d3af72
DE		 2327 [(parallel [(set (match_dup 0)
2328 (and:SI (match_dup 1)
2329 (match_dup 2)))
2330 (clobber (match_dup 4))])
2331 (set (match_dup 3)
2332 (compare:CC (match_dup 0)
2333 (const_int 0)))]
2334 "")
1fd4e8c1 2335
0ba1b2ff
AM		 2336(define_split
2337 [(set (match_operand:CC 3 "cc_reg_operand" "")
2338 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2339 (match_operand:SI 2 "gpc_reg_operand" ""))
2340 (const_int 0)))
2341 (set (match_operand:SI 0 "gpc_reg_operand" "")
2342 (and:SI (match_dup 1)
2343 (match_dup 2)))
2344 (clobber (match_scratch:CC 4 ""))]
2345 "TARGET_POWERPC64 && reload_completed"
2346 [(parallel [(set (match_dup 0)
2347 (and:SI (match_dup 1)
2348 (match_dup 2)))
2349 (clobber (match_dup 4))])
2350 (set (match_dup 3)
2351 (compare:CC (match_dup 0)
2352 (const_int 0)))]
2353 "")
2354
2355;; Handle the PowerPC64 rlwinm corner case
2356
2357(define_insn_and_split "*andsi3_internal6"
2358 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2359 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2360 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2361 "TARGET_POWERPC64"
2362 "#"
2363 "TARGET_POWERPC64"
2364 [(set (match_dup 0)
2365 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2366 (match_dup 4)))
2367 (set (match_dup 0)
2368 (rotate:SI (match_dup 0) (match_dup 5)))]
2369 "
2370{
2371 int mb = extract_MB (operands[2]);
2372 int me = extract_ME (operands[2]);
2373 operands[3] = GEN_INT (me + 1);
2374 operands[5] = GEN_INT (32 - (me + 1));
2375 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2376}"
2377 [(set_attr "length" "8")])
2378
2379(define_insn_and_split "*andsi3_internal7"
2380 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2381 (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r")
2382 (match_operand:SI 1 "mask_operand_wrap" "i,i"))
2383 (const_int 0)))
2384 (clobber (match_scratch:SI 3 "=r,r"))]
2385 "TARGET_POWERPC64"
2386 "#"
2387 "TARGET_POWERPC64"
2388 [(parallel [(set (match_dup 2)
2389 (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4))
2390 (match_dup 5))
2391 (const_int 0)))
2392 (clobber (match_dup 3))])]
2393 "
2394{
2395 int mb = extract_MB (operands[1]);
2396 int me = extract_ME (operands[1]);
2397 operands[4] = GEN_INT (me + 1);
2398 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2399}"
2400 [(set_attr "type" "delayed_compare,compare")
2401 (set_attr "length" "4,8")])
2402
2403(define_insn_and_split "*andsi3_internal8"
2404 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2405 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2406 (match_operand:SI 2 "mask_operand_wrap" "i,i"))
2407 (const_int 0)))
2408 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2409 (and:SI (match_dup 1)
2410 (match_dup 2)))]
2411 "TARGET_POWERPC64"
2412 "#"
2413 "TARGET_POWERPC64"
2414 [(parallel [(set (match_dup 3)
2415 (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2416 (match_dup 5))
2417 (const_int 0)))
2418 (set (match_dup 0)
2419 (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2420 (match_dup 5)))])
2421 (set (match_dup 0)
2422 (rotate:SI (match_dup 0) (match_dup 6)))]
2423 "
2424{
2425 int mb = extract_MB (operands[2]);
2426 int me = extract_ME (operands[2]);
2427 operands[4] = GEN_INT (me + 1);
2428 operands[6] = GEN_INT (32 - (me + 1));
2429 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2430}"
2431 [(set_attr "type" "delayed_compare,compare")
2432 (set_attr "length" "8,12")])
2433
7cd5235b 2434(define_expand "iorsi3"
cd2b37d9 2435 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 2436 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 2437 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
7cd5235b 2438 ""
f357808b
RK		 2439 "
2440{
7cd5235b 2441 if (GET_CODE (operands[2]) == CONST_INT
677a9668 2442 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 2443 {
2444 HOST_WIDE_INT value = INTVAL (operands[2]);
677a9668 2445 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 2446 ? operands[0] : gen_reg_rtx (SImode));
2447
a260abc9
DE		 2448 emit_insn (gen_iorsi3 (tmp, operands[1],
2449 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2450 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 2451 DONE;
2452 }
f357808b
RK		 2453}")
2454
7cd5235b 2455(define_expand "xorsi3"
cd2b37d9 2456 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 2457 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 2458 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
1fd4e8c1 2459 ""
7cd5235b 2460 "
1fd4e8c1 2461{
7cd5235b 2462 if (GET_CODE (operands[2]) == CONST_INT
677a9668 2463 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 2464 {
2465 HOST_WIDE_INT value = INTVAL (operands[2]);
677a9668 2466 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 2467 ? operands[0] : gen_reg_rtx (SImode));
2468
a260abc9
DE		 2469 emit_insn (gen_xorsi3 (tmp, operands[1],
2470 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2471 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 2472 DONE;
2473 }
1fd4e8c1
RK		 2474}")
2475
dfbdccdb 2476(define_insn "*boolsi3_internal1"
7cd5235b 2477 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 2478 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 2479 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2480 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
1fd4e8c1
RK		 2481 ""
2482 "@
dfbdccdb
GK		 2483 %q3 %0,%1,%2
2484 {%q3il|%q3i} %0,%1,%b2
2485 {%q3iu|%q3is} %0,%1,%u2")
1fd4e8c1 2486
dfbdccdb 2487(define_insn "*boolsi3_internal2"
52d3af72 2488 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 2489 (compare:CC (match_operator:SI 4 "boolean_or_operator"
dfbdccdb
GK		 2490 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2491 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2492 (const_int 0)))
52d3af72 2493 (clobber (match_scratch:SI 3 "=r,r"))]
0ad91047 2494 "! TARGET_POWERPC64"
52d3af72 2495 "@
dfbdccdb 2496 %q4. %3,%1,%2
52d3af72
DE		 2497 #"
2498 [(set_attr "type" "compare")
2499 (set_attr "length" "4,8")])
2500
2501(define_split
2502 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 2503 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2504 [(match_operand:SI 1 "gpc_reg_operand" "")
2505 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2506 (const_int 0)))
52d3af72 2507 (clobber (match_scratch:SI 3 ""))]
0ad91047 2508 "! TARGET_POWERPC64 && reload_completed"
dfbdccdb 2509 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 2510 (set (match_dup 0)
2511 (compare:CC (match_dup 3)
2512 (const_int 0)))]
2513 "")
815cdc52 2514
dfbdccdb 2515(define_insn "*boolsi3_internal3"
52d3af72 2516 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2517 (compare:CC (match_operator:SI 4 "boolean_operator"
2518 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2519 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2520 (const_int 0)))
52d3af72 2521 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 2522 (match_dup 4))]
0ad91047 2523 "! TARGET_POWERPC64"
52d3af72 2524 "@
dfbdccdb 2525 %q4. %0,%1,%2
52d3af72
DE		 2526 #"
2527 [(set_attr "type" "compare")
2528 (set_attr "length" "4,8")])
2529
2530(define_split
e72247f4 2531 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 2532 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2533 [(match_operand:SI 1 "gpc_reg_operand" "")
2534 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2535 (const_int 0)))
75540af0 2536 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 2537 (match_dup 4))]
0ad91047 2538 "! TARGET_POWERPC64 && reload_completed"
dfbdccdb 2539 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 2540 (set (match_dup 3)
2541 (compare:CC (match_dup 0)
2542 (const_int 0)))]
2543 "")
1fd4e8c1 2544
5bdc5878 2545;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 2546;; each of which does one 16-bit part. This is used by combine.
a260abc9
DE		 2547
2548(define_split
2549 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1d328b19 2550 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 2551 [(match_operand:SI 1 "gpc_reg_operand" "")
2552 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
a260abc9 2553 ""
dfbdccdb
GK		 2554 [(set (match_dup 0) (match_dup 4))
2555 (set (match_dup 0) (match_dup 5))]
a260abc9
DE		 2556"
2557{
dfbdccdb
GK		 2558 rtx i;
2559 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2560 operands[4] = gen_rtx (GET_CODE (operands[3]), SImode,
2561 operands[1], i);
2562 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2563 operands[5] = gen_rtx (GET_CODE (operands[3]), SImode,
2564 operands[0], i);
a260abc9
DE		 2565}")
2566
dfbdccdb 2567(define_insn "*boolcsi3_internal1"
cd2b37d9 2568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 2569 (match_operator:SI 3 "boolean_operator"
2570 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 2571 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
1fd4e8c1 2572 ""
dfbdccdb 2573 "%q3 %0,%2,%1")
1fd4e8c1 2574
dfbdccdb 2575(define_insn "*boolcsi3_internal2"
52d3af72 2576 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2577 (compare:CC (match_operator:SI 4 "boolean_operator"
2578 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2579 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2580 (const_int 0)))
52d3af72 2581 (clobber (match_scratch:SI 3 "=r,r"))]
0ad91047 2582 "! TARGET_POWERPC64"
52d3af72 2583 "@
dfbdccdb 2584 %q4. %3,%2,%1
52d3af72
DE		 2585 #"
2586 [(set_attr "type" "compare")
2587 (set_attr "length" "4,8")])
2588
2589(define_split
2590 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 2591 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2592 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2593 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2594 (const_int 0)))
52d3af72 2595 (clobber (match_scratch:SI 3 ""))]
0ad91047 2596 "! TARGET_POWERPC64 && reload_completed"
dfbdccdb 2597 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 2598 (set (match_dup 0)
2599 (compare:CC (match_dup 3)
2600 (const_int 0)))]
2601 "")
1fd4e8c1 2602
dfbdccdb 2603(define_insn "*boolcsi3_internal3"
52d3af72 2604 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2605 (compare:CC (match_operator:SI 4 "boolean_operator"
2606 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2607 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2608 (const_int 0)))
52d3af72 2609 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 2610 (match_dup 4))]
0ad91047 2611 "! TARGET_POWERPC64"
52d3af72 2612 "@
dfbdccdb 2613 %q4. %0,%2,%1
52d3af72
DE		 2614 #"
2615 [(set_attr "type" "compare")
2616 (set_attr "length" "4,8")])
2617
2618(define_split
e72247f4 2619 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 2620 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2621 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2622 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2623 (const_int 0)))
75540af0 2624 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 2625 (match_dup 4))]
0ad91047 2626 "! TARGET_POWERPC64 && reload_completed"
dfbdccdb 2627 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 2628 (set (match_dup 3)
2629 (compare:CC (match_dup 0)
2630 (const_int 0)))]
2631 "")
2632
dfbdccdb 2633(define_insn "*boolccsi3_internal1"
cd2b37d9 2634 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 2635 (match_operator:SI 3 "boolean_operator"
2636 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 2637 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
1fd4e8c1 2638 ""
dfbdccdb 2639 "%q3 %0,%1,%2")
1fd4e8c1 2640
dfbdccdb 2641(define_insn "*boolccsi3_internal2"
52d3af72 2642 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2643 (compare:CC (match_operator:SI 4 "boolean_operator"
2644 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2645 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2646 (const_int 0)))
52d3af72 2647 (clobber (match_scratch:SI 3 "=r,r"))]
0ad91047 2648 "! TARGET_POWERPC64"
52d3af72 2649 "@
dfbdccdb 2650 %q4. %3,%1,%2
52d3af72
DE		 2651 #"
2652 [(set_attr "type" "compare")
2653 (set_attr "length" "4,8")])
2654
2655(define_split
2656 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 2657 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2658 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2659 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 2660 (const_int 0)))
52d3af72 2661 (clobber (match_scratch:SI 3 ""))]
0ad91047 2662 "! TARGET_POWERPC64 && reload_completed"
dfbdccdb 2663 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 2664 (set (match_dup 0)
2665 (compare:CC (match_dup 3)
2666 (const_int 0)))]
2667 "")
1fd4e8c1 2668
dfbdccdb 2669(define_insn "*boolccsi3_internal3"
52d3af72 2670 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2671 (compare:CC (match_operator:SI 4 "boolean_operator"
2672 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2673 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2674 (const_int 0)))
52d3af72 2675 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 2676 (match_dup 4))]
0ad91047 2677 "! TARGET_POWERPC64"
52d3af72 2678 "@
dfbdccdb 2679 %q4. %0,%1,%2
52d3af72
DE		 2680 #"
2681 [(set_attr "type" "compare")
2682 (set_attr "length" "4,8")])
2683
2684(define_split
e72247f4 2685 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 2686 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2687 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2688 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 2689 (const_int 0)))
75540af0 2690 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 2691 (match_dup 4))]
0ad91047 2692 "! TARGET_POWERPC64 && reload_completed"
dfbdccdb 2693 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 2694 (set (match_dup 3)
2695 (compare:CC (match_dup 0)
2696 (const_int 0)))]
2697 "")
1fd4e8c1
RK		 2698
2699;; maskir insn. We need four forms because things might be in arbitrary
2700;; orders. Don't define forms that only set CR fields because these
2701;; would modify an input register.
2702
7cd5235b 2703(define_insn "*maskir_internal1"
cd2b37d9 2704 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 2705 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2706 (match_operand:SI 1 "gpc_reg_operand" "0"))
2707 (and:SI (match_dup 2)
cd2b37d9 2708 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
ca7f5001 2709 "TARGET_POWER"
01def764 2710 "maskir %0,%3,%2")
1fd4e8c1 2711
7cd5235b 2712(define_insn "*maskir_internal2"
242e8072 2713 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 2714 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2715 (match_operand:SI 1 "gpc_reg_operand" "0"))
cd2b37d9 2716 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764 2717 (match_dup 2))))]
ca7f5001 2718 "TARGET_POWER"
01def764 2719 "maskir %0,%3,%2")
1fd4e8c1 2720
7cd5235b 2721(define_insn "*maskir_internal3"
cd2b37d9 2722 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764 2723 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
cd2b37d9 2724 (match_operand:SI 3 "gpc_reg_operand" "r"))
01def764
RK		 2725 (and:SI (not:SI (match_dup 2))
2726 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 2727 "TARGET_POWER"
01def764 2728 "maskir %0,%3,%2")
1fd4e8c1 2729
7cd5235b 2730(define_insn "*maskir_internal4"
cd2b37d9
RK		 2731 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2732 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764
RK		 2733 (match_operand:SI 2 "gpc_reg_operand" "r"))
2734 (and:SI (not:SI (match_dup 2))
2735 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 2736 "TARGET_POWER"
01def764 2737 "maskir %0,%3,%2")
1fd4e8c1 2738
7cd5235b 2739(define_insn "*maskir_internal5"
9ebbca7d 2740 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 2741 (compare:CC
9ebbca7d
GK		 2742 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2743 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
01def764 2744 (and:SI (match_dup 2)
9ebbca7d 2745 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1fd4e8c1 2746 (const_int 0)))
9ebbca7d 2747 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 2748 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2749 (and:SI (match_dup 2) (match_dup 3))))]
ca7f5001 2750 "TARGET_POWER"
9ebbca7d
GK		 2751 "@
2752 maskir. %0,%3,%2
2753 #"
2754 [(set_attr "type" "compare")
2755 (set_attr "length" "4,8")])
2756
2757(define_split
2758 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2759 (compare:CC
2760 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2761 (match_operand:SI 1 "gpc_reg_operand" ""))
2762 (and:SI (match_dup 2)
2763 (match_operand:SI 3 "gpc_reg_operand" "")))
2764 (const_int 0)))
2765 (set (match_operand:SI 0 "gpc_reg_operand" "")
2766 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2767 (and:SI (match_dup 2) (match_dup 3))))]
2768 "TARGET_POWER && reload_completed"
2769 [(set (match_dup 0)
2770 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2771 (and:SI (match_dup 2) (match_dup 3))))
2772 (set (match_dup 4)
2773 (compare:CC (match_dup 0)
2774 (const_int 0)))]
2775 "")
1fd4e8c1 2776
7cd5235b 2777(define_insn "*maskir_internal6"
9ebbca7d 2778 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 2779 (compare:CC
9ebbca7d
GK		 2780 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2781 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2782 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
01def764 2783 (match_dup 2)))
1fd4e8c1 2784 (const_int 0)))
9ebbca7d 2785 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 2786 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2787 (and:SI (match_dup 3) (match_dup 2))))]
ca7f5001 2788 "TARGET_POWER"
9ebbca7d
GK		 2789 "@
2790 maskir. %0,%3,%2
2791 #"
2792 [(set_attr "type" "compare")
2793 (set_attr "length" "4,8")])
2794
2795(define_split
2796 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2797 (compare:CC
2798 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2799 (match_operand:SI 1 "gpc_reg_operand" ""))
2800 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2801 (match_dup 2)))
2802 (const_int 0)))
2803 (set (match_operand:SI 0 "gpc_reg_operand" "")
2804 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2805 (and:SI (match_dup 3) (match_dup 2))))]
2806 "TARGET_POWER && reload_completed"
2807 [(set (match_dup 0)
2808 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2809 (and:SI (match_dup 3) (match_dup 2))))
2810 (set (match_dup 4)
2811 (compare:CC (match_dup 0)
2812 (const_int 0)))]
2813 "")
1fd4e8c1 2814
7cd5235b 2815(define_insn "*maskir_internal7"
9ebbca7d 2816 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
815cdc52 2817 (compare:CC
9ebbca7d
GK		 2818 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2819 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
815cdc52 2820 (and:SI (not:SI (match_dup 2))
9ebbca7d 2821 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
815cdc52 2822 (const_int 0)))
9ebbca7d 2823 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 2824 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2825 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2826 "TARGET_POWER"
9ebbca7d
GK		 2827 "@
2828 maskir. %0,%3,%2
2829 #"
2830 [(set_attr "type" "compare")
2831 (set_attr "length" "4,8")])
2832
2833(define_split
2834 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2835 (compare:CC
2836 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2837 (match_operand:SI 3 "gpc_reg_operand" ""))
2838 (and:SI (not:SI (match_dup 2))
2839 (match_operand:SI 1 "gpc_reg_operand" "")))
2840 (const_int 0)))
2841 (set (match_operand:SI 0 "gpc_reg_operand" "")
2842 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2843 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2844 "TARGET_POWER && reload_completed"
2845 [(set (match_dup 0)
2846 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2847 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2848 (set (match_dup 4)
2849 (compare:CC (match_dup 0)
2850 (const_int 0)))]
2851 "")
1fd4e8c1 2852
7cd5235b 2853(define_insn "*maskir_internal8"
9ebbca7d 2854 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 2855 (compare:CC
9ebbca7d
GK		 2856 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2857 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
01def764 2858 (and:SI (not:SI (match_dup 2))
9ebbca7d 2859 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
1fd4e8c1 2860 (const_int 0)))
9ebbca7d 2861 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 2862 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2863 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
ca7f5001 2864 "TARGET_POWER"
9ebbca7d
GK		 2865 "@
2866 maskir. %0,%3,%2
2867 #"
2868 [(set_attr "type" "compare")
2869 (set_attr "length" "4,8")])
fcce224d 2870
9ebbca7d
GK		 2871(define_split
2872 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2873 (compare:CC
2874 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2875 (match_operand:SI 2 "gpc_reg_operand" ""))
2876 (and:SI (not:SI (match_dup 2))
2877 (match_operand:SI 1 "gpc_reg_operand" "")))
2878 (const_int 0)))
2879 (set (match_operand:SI 0 "gpc_reg_operand" "")
2880 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2881 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2882 "TARGET_POWER && reload_completed"
2883 [(set (match_dup 0)
2884 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2885 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2886 (set (match_dup 4)
2887 (compare:CC (match_dup 0)
2888 (const_int 0)))]
2889 "")
fcce224d 2890\f
1fd4e8c1
RK		 2891;; Rotate and shift insns, in all their variants. These support shifts,
2892;; field inserts and extracts, and various combinations thereof.
034c1be0 2893(define_expand "insv"
0ad91047
DE		 2894 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2895 (match_operand:SI 1 "const_int_operand" "")
2896 (match_operand:SI 2 "const_int_operand" ""))
2897 (match_operand 3 "gpc_reg_operand" ""))]
034c1be0
MM		 2898 ""
2899 "
2900{
2901 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2902 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2903 compiler if the address of the structure is taken later. */
2904 if (GET_CODE (operands[0]) == SUBREG
2905 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2906 FAIL;
a78e33fc
DE		 2907
2908 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2909 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2910 else
2911 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2912 DONE;
034c1be0
MM		 2913}")
2914
a78e33fc 2915(define_insn "insvsi"
cd2b37d9 2916 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1
RK		 2917 (match_operand:SI 1 "const_int_operand" "i")
2918 (match_operand:SI 2 "const_int_operand" "i"))
cd2b37d9 2919 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1fd4e8c1
RK		 2920 ""
2921 "*
2922{
2923 int start = INTVAL (operands[2]) & 31;
2924 int size = INTVAL (operands[1]) & 31;
2925
89e9f3a8
MM		 2926 operands[4] = GEN_INT (32 - start - size);
2927 operands[1] = GEN_INT (start + size - 1);
a66078ee 2928 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
1fd4e8c1
RK		 2929}")
2930
a78e33fc 2931(define_insn "*insvsi_internal1"
d56d506a
RK		 2932 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2933 (match_operand:SI 1 "const_int_operand" "i")
2934 (match_operand:SI 2 "const_int_operand" "i"))
2935 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2936 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 2937 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 2938 "*
2939{
2940 int shift = INTVAL (operands[4]) & 31;
2941 int start = INTVAL (operands[2]) & 31;
2942 int size = INTVAL (operands[1]) & 31;
2943
89e9f3a8
MM		 2944 operands[4] = GEN_INT (shift - start - size);
2945 operands[1] = GEN_INT (start + size - 1);
a66078ee 2946 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
d56d506a
RK		 2947}")
2948
a78e33fc 2949(define_insn "*insvsi_internal2"
d56d506a
RK		 2950 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2951 (match_operand:SI 1 "const_int_operand" "i")
2952 (match_operand:SI 2 "const_int_operand" "i"))
2953 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2954 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 2955 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 2956 "*
2957{
2958 int shift = INTVAL (operands[4]) & 31;
2959 int start = INTVAL (operands[2]) & 31;
2960 int size = INTVAL (operands[1]) & 31;
2961
89e9f3a8
MM		 2962 operands[4] = GEN_INT (32 - shift - start - size);
2963 operands[1] = GEN_INT (start + size - 1);
a66078ee 2964 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
d56d506a
RK		 2965}")
2966
a78e33fc 2967(define_insn "*insvsi_internal3"
d56d506a
RK		 2968 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2969 (match_operand:SI 1 "const_int_operand" "i")
2970 (match_operand:SI 2 "const_int_operand" "i"))
2971 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2972 (match_operand:SI 4 "const_int_operand" "i")))]
95e8f2f3 2973 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 2974 "*
2975{
2976 int shift = INTVAL (operands[4]) & 31;
2977 int start = INTVAL (operands[2]) & 31;
2978 int size = INTVAL (operands[1]) & 31;
2979
89e9f3a8
MM		 2980 operands[4] = GEN_INT (32 - shift - start - size);
2981 operands[1] = GEN_INT (start + size - 1);
a66078ee 2982 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
d56d506a
RK		 2983}")
2984
a78e33fc 2985(define_insn "*insvsi_internal4"
d56d506a
RK		 2986 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2987 (match_operand:SI 1 "const_int_operand" "i")
2988 (match_operand:SI 2 "const_int_operand" "i"))
2989 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2990 (match_operand:SI 4 "const_int_operand" "i")
2991 (match_operand:SI 5 "const_int_operand" "i")))]
2992 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2993 "*
2994{
2995 int extract_start = INTVAL (operands[5]) & 31;
2996 int extract_size = INTVAL (operands[4]) & 31;
2997 int insert_start = INTVAL (operands[2]) & 31;
2998 int insert_size = INTVAL (operands[1]) & 31;
2999
3000/* Align extract field with insert field */
3a598fbe 3001 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
89e9f3a8 3002 operands[1] = GEN_INT (insert_start + insert_size - 1);
a66078ee 3003 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
d56d506a
RK		 3004}")
3005
a78e33fc 3006(define_insn "insvdi"
685f3906 3007 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
a78e33fc
DE		 3008 (match_operand:SI 1 "const_int_operand" "i")
3009 (match_operand:SI 2 "const_int_operand" "i"))
685f3906
DE		 3010 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3011 "TARGET_POWERPC64"
3012 "*
3013{
3014 int start = INTVAL (operands[2]) & 63;
3015 int size = INTVAL (operands[1]) & 63;
3016
a78e33fc
DE		 3017 operands[1] = GEN_INT (64 - start - size);
3018 return \"rldimi %0,%3,%H1,%H2\";
685f3906
DE		 3019}")
3020
034c1be0 3021(define_expand "extzv"
0ad91047
DE		 3022 [(set (match_operand 0 "gpc_reg_operand" "")
3023 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3024 (match_operand:SI 2 "const_int_operand" "")
3025 (match_operand:SI 3 "const_int_operand" "")))]
034c1be0
MM		 3026 ""
3027 "
3028{
3029 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3030 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3031 compiler if the address of the structure is taken later. */
3032 if (GET_CODE (operands[0]) == SUBREG
3033 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3034 FAIL;
a78e33fc
DE		 3035
3036 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3037 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3038 else
3039 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3040 DONE;
034c1be0
MM		 3041}")
3042
a78e33fc 3043(define_insn "extzvsi"
cd2b37d9
RK		 3044 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3045 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3046 (match_operand:SI 2 "const_int_operand" "i")
3047 (match_operand:SI 3 "const_int_operand" "i")))]
3048 ""
3049 "*
3050{
3051 int start = INTVAL (operands[3]) & 31;
3052 int size = INTVAL (operands[2]) & 31;
3053
3054 if (start + size >= 32)
3055 operands[3] = const0_rtx;
3056 else
89e9f3a8 3057 operands[3] = GEN_INT (start + size);
ca7f5001 3058 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
1fd4e8c1
RK		 3059}")
3060
a78e33fc 3061(define_insn "*extzvsi_internal1"
9ebbca7d
GK		 3062 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3063 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3064 (match_operand:SI 2 "const_int_operand" "i,i")
3065 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3066 (const_int 0)))
9ebbca7d 3067 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3068 ""
1fd4e8c1
RK		 3069 "*
3070{
3071 int start = INTVAL (operands[3]) & 31;
3072 int size = INTVAL (operands[2]) & 31;
3073
9ebbca7d
GK		 3074 /* Force split for non-cc0 compare. */
3075 if (which_alternative == 1)
3076 return \"#\";
3077
43a88a8c 3078 /* If the bit-field being tested fits in the upper or lower half of a
a7a975e1
RK		 3079 word, it is possible to use andiu. or andil. to test it. This is
3080 useful because the condition register set-use delay is smaller for
3081 andi[ul]. than for rlinm. This doesn't work when the starting bit
3082 position is 0 because the LT and GT bits may be set wrong. */
3083
3084 if ((start > 0 && start + size <= 16) || start >= 16)
df031c43 3085 {
3a598fbe 3086 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
df031c43
RK		 3087 - (1 << (16 - (start & 15) - size))));
3088 if (start < 16)
ca7f5001 3089 return \"{andiu.|andis.} %4,%1,%3\";
df031c43 3090 else
ca7f5001 3091 return \"{andil.|andi.} %4,%1,%3\";
df031c43 3092 }
7e69e155 3093
1fd4e8c1
RK		 3094 if (start + size >= 32)
3095 operands[3] = const0_rtx;
3096 else
89e9f3a8 3097 operands[3] = GEN_INT (start + size);
ca7f5001 3098 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
1fd4e8c1 3099}"
9ebbca7d
GK		 3100 [(set_attr "type" "compare")
3101 (set_attr "length" "4,8")])
3102
3103(define_split
3104 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3105 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3106 (match_operand:SI 2 "const_int_operand" "")
3107 (match_operand:SI 3 "const_int_operand" ""))
3108 (const_int 0)))
3109 (clobber (match_scratch:SI 4 ""))]
ce71f754 3110 "reload_completed"
9ebbca7d
GK		 3111 [(set (match_dup 4)
3112 (zero_extract:SI (match_dup 1) (match_dup 2)
3113 (match_dup 3)))
3114 (set (match_dup 0)
3115 (compare:CC (match_dup 4)
3116 (const_int 0)))]
3117 "")
1fd4e8c1 3118
a78e33fc 3119(define_insn "*extzvsi_internal2"
9ebbca7d
GK		 3120 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3121 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3122 (match_operand:SI 2 "const_int_operand" "i,i")
3123 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3124 (const_int 0)))
9ebbca7d 3125 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3126 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3127 ""
1fd4e8c1
RK		 3128 "*
3129{
3130 int start = INTVAL (operands[3]) & 31;
3131 int size = INTVAL (operands[2]) & 31;
3132
9ebbca7d
GK		 3133 /* Force split for non-cc0 compare. */
3134 if (which_alternative == 1)
3135 return \"#\";
3136
bc401279 3137 /* Since we are using the output value, we can't ignore any need for
43a88a8c 3138 a shift. The bit-field must end at the LSB. */
bc401279 3139 if (start >= 16 && start + size == 32)
df031c43 3140 {
bc401279
AM		 3141 operands[3] = GEN_INT ((1 << size) - 1);
3142 return \"{andil.|andi.} %0,%1,%3\";
df031c43 3143 }
7e69e155 3144
1fd4e8c1
RK		 3145 if (start + size >= 32)
3146 operands[3] = const0_rtx;
3147 else
89e9f3a8 3148 operands[3] = GEN_INT (start + size);
ca7f5001 3149 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
1fd4e8c1 3150}"
ce71f754 3151 [(set_attr "type" "compare")
9ebbca7d
GK		 3152 (set_attr "length" "4,8")])
3153
3154(define_split
3155 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3156 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3157 (match_operand:SI 2 "const_int_operand" "")
3158 (match_operand:SI 3 "const_int_operand" ""))
3159 (const_int 0)))
3160 (set (match_operand:SI 0 "gpc_reg_operand" "")
3161 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3162 "reload_completed"
9ebbca7d
GK		 3163 [(set (match_dup 0)
3164 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3165 (set (match_dup 4)
3166 (compare:CC (match_dup 0)
3167 (const_int 0)))]
3168 "")
1fd4e8c1 3169
a78e33fc 3170(define_insn "extzvdi"
685f3906
DE		 3171 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3172 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3173 (match_operand:SI 2 "const_int_operand" "i")
3174 (match_operand:SI 3 "const_int_operand" "i")))]
685f3906
DE		 3175 "TARGET_POWERPC64"
3176 "*
3177{
3178 int start = INTVAL (operands[3]) & 63;
3179 int size = INTVAL (operands[2]) & 63;
3180
3181 if (start + size >= 64)
3182 operands[3] = const0_rtx;
3183 else
89e9f3a8
MM		 3184 operands[3] = GEN_INT (start + size);
3185 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3186 return \"rldicl %0,%1,%3,%2\";
3187}")
3188
a78e33fc 3189(define_insn "*extzvdi_internal1"
29ae5b89
JL		 3190 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3191 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3192 (match_operand:SI 2 "const_int_operand" "i")
3193 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3194 (const_int 0)))
29ae5b89 3195 (clobber (match_scratch:DI 4 "=r"))]
685f3906
DE		 3196 "TARGET_POWERPC64"
3197 "*
3198{
3199 int start = INTVAL (operands[3]) & 63;
3200 int size = INTVAL (operands[2]) & 63;
3201
3202 if (start + size >= 64)
3203 operands[3] = const0_rtx;
3204 else
89e9f3a8
MM		 3205 operands[3] = GEN_INT (start + size);
3206 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3207 return \"rldicl. %4,%1,%3,%2\";
3208}")
3209
a78e33fc 3210(define_insn "*extzvdi_internal2"
29ae5b89
JL		 3211 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3212 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3213 (match_operand:SI 2 "const_int_operand" "i")
3214 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3215 (const_int 0)))
29ae5b89 3216 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
685f3906
DE		 3217 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3218 "TARGET_POWERPC64"
3219 "*
3220{
3221 int start = INTVAL (operands[3]) & 63;
3222 int size = INTVAL (operands[2]) & 63;
3223
3224 if (start + size >= 64)
3225 operands[3] = const0_rtx;
3226 else
89e9f3a8
MM		 3227 operands[3] = GEN_INT (start + size);
3228 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3229 return \"rldicl. %0,%1,%3,%2\";
3230}")
3231
1fd4e8c1 3232(define_insn "rotlsi3"
cd2b37d9
RK		 3233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3234 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3235 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3236 ""
ca7f5001 3237 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
1fd4e8c1 3238
a260abc9 3239(define_insn "*rotlsi3_internal2"
9ebbca7d
GK		 3240 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3241 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3242 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
1fd4e8c1 3243 (const_int 0)))
9ebbca7d 3244 (clobber (match_scratch:SI 3 "=r,r"))]
ce71f754 3245 ""
9ebbca7d
GK		 3246 "@
3247 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3248 #"
3249 [(set_attr "type" "delayed_compare")
3250 (set_attr "length" "4,8")])
3251
3252(define_split
3253 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3254 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3255 (match_operand:SI 2 "reg_or_cint_operand" ""))
3256 (const_int 0)))
3257 (clobber (match_scratch:SI 3 ""))]
ce71f754 3258 "reload_completed"
9ebbca7d
GK		 3259 [(set (match_dup 3)
3260 (rotate:SI (match_dup 1) (match_dup 2)))
3261 (set (match_dup 0)
3262 (compare:CC (match_dup 3)
3263 (const_int 0)))]
3264 "")
1fd4e8c1 3265
a260abc9 3266(define_insn "*rotlsi3_internal3"
9ebbca7d
GK		 3267 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3268 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3269 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
1fd4e8c1 3270 (const_int 0)))
9ebbca7d 3271 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3272 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3273 ""
9ebbca7d
GK		 3274 "@
3275 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3276 #"
3277 [(set_attr "type" "delayed_compare")
3278 (set_attr "length" "4,8")])
3279
3280(define_split
3281 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3282 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3283 (match_operand:SI 2 "reg_or_cint_operand" ""))
3284 (const_int 0)))
3285 (set (match_operand:SI 0 "gpc_reg_operand" "")
3286 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3287 "reload_completed"
9ebbca7d
GK		 3288 [(set (match_dup 0)
3289 (rotate:SI (match_dup 1) (match_dup 2)))
3290 (set (match_dup 3)
3291 (compare:CC (match_dup 0)
3292 (const_int 0)))]
3293 "")
1fd4e8c1 3294
a260abc9 3295(define_insn "*rotlsi3_internal4"
cd2b37d9
RK		 3296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3297 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 3298 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
ce71f754 3299 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 3300 ""
ca7f5001 3301 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
1fd4e8c1 3302
a260abc9 3303(define_insn "*rotlsi3_internal5"
9ebbca7d 3304 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 3305 (compare:CC (and:SI
9ebbca7d
GK		 3306 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3307 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ce71f754 3308 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3309 (const_int 0)))
9ebbca7d 3310 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3311 ""
9ebbca7d
GK		 3312 "@
3313 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3314 #"
3315 [(set_attr "type" "delayed_compare")
3316 (set_attr "length" "4,8")])
3317
3318(define_split
3319 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3320 (compare:CC (and:SI
3321 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3322 (match_operand:SI 2 "reg_or_cint_operand" ""))
3323 (match_operand:SI 3 "mask_operand" ""))
3324 (const_int 0)))
3325 (clobber (match_scratch:SI 4 ""))]
ce71f754 3326 "reload_completed"
9ebbca7d
GK		 3327 [(set (match_dup 4)
3328 (and:SI (rotate:SI (match_dup 1)
3329 (match_dup 2))
3330 (match_dup 3)))
3331 (set (match_dup 0)
3332 (compare:CC (match_dup 4)
3333 (const_int 0)))]
3334 "")
1fd4e8c1 3335
a260abc9 3336(define_insn "*rotlsi3_internal6"
9ebbca7d 3337 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3338 (compare:CC (and:SI
9ebbca7d
GK		 3339 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3340 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ce71f754 3341 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3342 (const_int 0)))
9ebbca7d 3343 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3344 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3345 ""
9ebbca7d
GK		 3346 "@
3347 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3348 #"
3349 [(set_attr "type" "delayed_compare")
3350 (set_attr "length" "4,8")])
3351
3352(define_split
3353 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3354 (compare:CC (and:SI
3355 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3356 (match_operand:SI 2 "reg_or_cint_operand" ""))
3357 (match_operand:SI 3 "mask_operand" ""))
3358 (const_int 0)))
3359 (set (match_operand:SI 0 "gpc_reg_operand" "")
3360 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3361 "reload_completed"
9ebbca7d
GK		 3362 [(set (match_dup 0)
3363 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3364 (set (match_dup 4)
3365 (compare:CC (match_dup 0)
3366 (const_int 0)))]
3367 "")
1fd4e8c1 3368
a260abc9 3369(define_insn "*rotlsi3_internal7"
cd2b37d9 3370 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 3371 (zero_extend:SI
3372 (subreg:QI
cd2b37d9 3373 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3374 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3375 ""
ca7f5001 3376 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
1fd4e8c1 3377
a260abc9 3378(define_insn "*rotlsi3_internal8"
9ebbca7d 3379 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3380 (compare:CC (zero_extend:SI
3381 (subreg:QI
9ebbca7d
GK		 3382 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3383 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3384 (const_int 0)))
9ebbca7d 3385 (clobber (match_scratch:SI 3 "=r,r"))]
1fd4e8c1 3386 ""
9ebbca7d
GK		 3387 "@
3388 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3389 #"
3390 [(set_attr "type" "delayed_compare")
3391 (set_attr "length" "4,8")])
3392
3393(define_split
3394 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3395 (compare:CC (zero_extend:SI
3396 (subreg:QI
3397 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3398 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3399 (const_int 0)))
3400 (clobber (match_scratch:SI 3 ""))]
3401 "reload_completed"
3402 [(set (match_dup 3)
3403 (zero_extend:SI (subreg:QI
3404 (rotate:SI (match_dup 1)
3405 (match_dup 2)) 0)))
3406 (set (match_dup 0)
3407 (compare:CC (match_dup 3)
3408 (const_int 0)))]
3409 "")
1fd4e8c1 3410
a260abc9 3411(define_insn "*rotlsi3_internal9"
9ebbca7d 3412 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3413 (compare:CC (zero_extend:SI
3414 (subreg:QI
9ebbca7d
GK		 3415 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3416 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3417 (const_int 0)))
9ebbca7d 3418 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 3419 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3420 ""
9ebbca7d
GK		 3421 "@
3422 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3423 #"
3424 [(set_attr "type" "delayed_compare")
3425 (set_attr "length" "4,8")])
3426
3427(define_split
3428 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3429 (compare:CC (zero_extend:SI
3430 (subreg:QI
3431 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3432 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3433 (const_int 0)))
3434 (set (match_operand:SI 0 "gpc_reg_operand" "")
3435 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3436 "reload_completed"
3437 [(set (match_dup 0)
3438 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3439 (set (match_dup 3)
3440 (compare:CC (match_dup 0)
3441 (const_int 0)))]
3442 "")
1fd4e8c1 3443
a260abc9 3444(define_insn "*rotlsi3_internal10"
cd2b37d9 3445 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 3446 (zero_extend:SI
3447 (subreg:HI
cd2b37d9 3448 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3449 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3450 ""
ca7f5001 3451 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
1fd4e8c1 3452
a260abc9 3453(define_insn "*rotlsi3_internal11"
9ebbca7d 3454 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3455 (compare:CC (zero_extend:SI
3456 (subreg:HI
9ebbca7d
GK		 3457 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3458 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3459 (const_int 0)))
9ebbca7d 3460 (clobber (match_scratch:SI 3 "=r,r"))]
1fd4e8c1 3461 ""
9ebbca7d
GK		 3462 "@
3463 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3464 #"
3465 [(set_attr "type" "delayed_compare")
3466 (set_attr "length" "4,8")])
3467
3468(define_split
3469 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3470 (compare:CC (zero_extend:SI
3471 (subreg:HI
3472 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3473 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3474 (const_int 0)))
3475 (clobber (match_scratch:SI 3 ""))]
3476 "reload_completed"
3477 [(set (match_dup 3)
3478 (zero_extend:SI (subreg:HI
3479 (rotate:SI (match_dup 1)
3480 (match_dup 2)) 0)))
3481 (set (match_dup 0)
3482 (compare:CC (match_dup 3)
3483 (const_int 0)))]
3484 "")
1fd4e8c1 3485
a260abc9 3486(define_insn "*rotlsi3_internal12"
9ebbca7d 3487 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3488 (compare:CC (zero_extend:SI
3489 (subreg:HI
9ebbca7d
GK		 3490 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3491 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3492 (const_int 0)))
9ebbca7d 3493 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 3494 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3495 ""
9ebbca7d
GK		 3496 "@
3497 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3498 #"
3499 [(set_attr "type" "delayed_compare")
3500 (set_attr "length" "4,8")])
3501
3502(define_split
3503 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3504 (compare:CC (zero_extend:SI
3505 (subreg:HI
3506 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3507 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3508 (const_int 0)))
3509 (set (match_operand:SI 0 "gpc_reg_operand" "")
3510 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3511 "reload_completed"
3512 [(set (match_dup 0)
3513 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3514 (set (match_dup 3)
3515 (compare:CC (match_dup 0)
3516 (const_int 0)))]
3517 "")
1fd4e8c1
RK		 3518
3519;; Note that we use "sle." instead of "sl." so that we can set
3520;; SHIFT_COUNT_TRUNCATED.
3521
ca7f5001
RK		 3522(define_expand "ashlsi3"
3523 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3524 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3525 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3526 ""
3527 "
3528{
3529 if (TARGET_POWER)
3530 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3531 else
25c341fa 3532 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 3533 DONE;
3534}")
3535
3536(define_insn "ashlsi3_power"
cd2b37d9
RK		 3537 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3538 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 3539 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3540 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 3541 "TARGET_POWER"
1fd4e8c1
RK		 3542 "@
3543 sle %0,%1,%2
9ebbca7d 3544 {sli|slwi} %0,%1,%h2")
ca7f5001 3545
25c341fa 3546(define_insn "ashlsi3_no_power"
ca7f5001
RK		 3547 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3548 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3549 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
25c341fa 3550 "! TARGET_POWER"
9ebbca7d 3551 "{sl|slw}%I2 %0,%1,%h2")
1fd4e8c1
RK		 3552
3553(define_insn ""
9ebbca7d
GK		 3554 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3555 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3556 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3557 (const_int 0)))
9ebbca7d
GK		 3558 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3559 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 3560 "TARGET_POWER"
1fd4e8c1
RK		 3561 "@
3562 sle. %3,%1,%2
9ebbca7d
GK		 3563 {sli.|slwi.} %3,%1,%h2
3564 #
3565 #"
3566 [(set_attr "type" "delayed_compare")
3567 (set_attr "length" "4,4,8,8")])
3568
3569(define_split
3570 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3571 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3572 (match_operand:SI 2 "reg_or_cint_operand" ""))
3573 (const_int 0)))
3574 (clobber (match_scratch:SI 3 ""))
3575 (clobber (match_scratch:SI 4 ""))]
3576 "TARGET_POWER && reload_completed"
3577 [(parallel [(set (match_dup 3)
3578 (ashift:SI (match_dup 1) (match_dup 2)))
3579 (clobber (match_dup 4))])
3580 (set (match_dup 0)
3581 (compare:CC (match_dup 3)
3582 (const_int 0)))]
3583 "")
25c341fa 3584
ca7f5001 3585(define_insn ""
9ebbca7d
GK		 3586 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3587 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3588 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 3589 (const_int 0)))
9ebbca7d 3590 (clobber (match_scratch:SI 3 "=r,r"))]
0ad91047 3591 "! TARGET_POWER && ! TARGET_POWERPC64"
9ebbca7d
GK		 3592 "@
3593 {sl|slw}%I2. %3,%1,%h2
3594 #"
3595 [(set_attr "type" "delayed_compare")
3596 (set_attr "length" "4,8")])
3597
3598(define_split
3599 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3600 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3601 (match_operand:SI 2 "reg_or_cint_operand" ""))
3602 (const_int 0)))
3603 (clobber (match_scratch:SI 3 ""))]
3604 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3605 [(set (match_dup 3)
3606 (ashift:SI (match_dup 1) (match_dup 2)))
3607 (set (match_dup 0)
3608 (compare:CC (match_dup 3)
3609 (const_int 0)))]
3610 "")
1fd4e8c1
RK		 3611
3612(define_insn ""
9ebbca7d
GK		 3613 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3614 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3615 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3616 (const_int 0)))
9ebbca7d 3617 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 3618 (ashift:SI (match_dup 1) (match_dup 2)))
9ebbca7d 3619 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 3620 "TARGET_POWER"
1fd4e8c1
RK		 3621 "@
3622 sle. %0,%1,%2
9ebbca7d
GK		 3623 {sli.|slwi.} %0,%1,%h2
3624 #
3625 #"
3626 [(set_attr "type" "delayed_compare")
3627 (set_attr "length" "4,4,8,8")])
3628
3629(define_split
3630 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3631 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3632 (match_operand:SI 2 "reg_or_cint_operand" ""))
3633 (const_int 0)))
3634 (set (match_operand:SI 0 "gpc_reg_operand" "")
3635 (ashift:SI (match_dup 1) (match_dup 2)))
3636 (clobber (match_scratch:SI 4 ""))]
3637 "TARGET_POWER && reload_completed"
3638 [(parallel [(set (match_dup 0)
3639 (ashift:SI (match_dup 1) (match_dup 2)))
3640 (clobber (match_dup 4))])
3641 (set (match_dup 3)
3642 (compare:CC (match_dup 0)
3643 (const_int 0)))]
3644 "")
25c341fa 3645
ca7f5001 3646(define_insn ""
9ebbca7d
GK		 3647 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3648 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3649 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 3650 (const_int 0)))
9ebbca7d 3651 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 3652 (ashift:SI (match_dup 1) (match_dup 2)))]
0ad91047 3653 "! TARGET_POWER && ! TARGET_POWERPC64"
9ebbca7d
GK		 3654 "@
3655 {sl|slw}%I2. %0,%1,%h2
3656 #"
3657 [(set_attr "type" "delayed_compare")
3658 (set_attr "length" "4,8")])
3659
3660(define_split
3661 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3662 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3663 (match_operand:SI 2 "reg_or_cint_operand" ""))
3664 (const_int 0)))
3665 (set (match_operand:SI 0 "gpc_reg_operand" "")
3666 (ashift:SI (match_dup 1) (match_dup 2)))]
3667 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3668 [(set (match_dup 0)
3669 (ashift:SI (match_dup 1) (match_dup 2)))
3670 (set (match_dup 3)
3671 (compare:CC (match_dup 0)
3672 (const_int 0)))]
3673 "")
1fd4e8c1
RK		 3674
3675(define_insn ""
cd2b37d9
RK		 3676 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3677 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 3678 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 3679 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 3680 "includes_lshift_p (operands[2], operands[3])"
d56d506a 3681 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
1fd4e8c1
RK		 3682
3683(define_insn ""
9ebbca7d 3684 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 3685 (compare:CC
9ebbca7d
GK		 3686 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3687 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3688 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3689 (const_int 0)))
9ebbca7d 3690 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3691 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 3692 "@
3693 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3694 #"
3695 [(set_attr "type" "delayed_compare")
3696 (set_attr "length" "4,8")])
3697
3698(define_split
3699 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3700 (compare:CC
3701 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3702 (match_operand:SI 2 "const_int_operand" ""))
3703 (match_operand:SI 3 "mask_operand" ""))
3704 (const_int 0)))
3705 (clobber (match_scratch:SI 4 ""))]
ce71f754 3706 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 3707 [(set (match_dup 4)
3708 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3709 (match_dup 3)))
3710 (set (match_dup 0)
3711 (compare:CC (match_dup 4)
3712 (const_int 0)))]
3713 "")
1fd4e8c1
RK		 3714
3715(define_insn ""
9ebbca7d 3716 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3717 (compare:CC
9ebbca7d
GK		 3718 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3719 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3720 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3721 (const_int 0)))
9ebbca7d 3722 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3723 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3724 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 3725 "@
3726 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3727 #"
3728 [(set_attr "type" "delayed_compare")
3729 (set_attr "length" "4,8")])
3730
3731(define_split
3732 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3733 (compare:CC
3734 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3735 (match_operand:SI 2 "const_int_operand" ""))
3736 (match_operand:SI 3 "mask_operand" ""))
3737 (const_int 0)))
3738 (set (match_operand:SI 0 "gpc_reg_operand" "")
3739 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3740 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 3741 [(set (match_dup 0)
3742 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3743 (set (match_dup 4)
3744 (compare:CC (match_dup 0)
3745 (const_int 0)))]
3746 "")
1fd4e8c1 3747
ca7f5001 3748;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5c23c401 3749;; "sli x,x,0".
ca7f5001
RK		 3750(define_expand "lshrsi3"
3751 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3752 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3753 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3754 ""
3755 "
3756{
3757 if (TARGET_POWER)
3758 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3759 else
25c341fa 3760 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 3761 DONE;
3762}")
3763
3764(define_insn "lshrsi3_power"
bdf423cb
MM		 3765 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3766 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3767 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3768 (clobber (match_scratch:SI 3 "=q,X,X"))]
ca7f5001 3769 "TARGET_POWER"
1fd4e8c1
RK		 3770 "@
3771 sre %0,%1,%2
bdf423cb 3772 mr %0,%1
ca7f5001
RK		 3773 {s%A2i|s%A2wi} %0,%1,%h2")
3774
25c341fa 3775(define_insn "lshrsi3_no_power"
bdf423cb
MM		 3776 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3777 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3778 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
25c341fa 3779 "! TARGET_POWER"
bdf423cb
MM		 3780 "@
3781 mr %0,%1
3782 {sr|srw}%I2 %0,%1,%h2")
1fd4e8c1
RK		 3783
3784(define_insn ""
9ebbca7d
GK		 3785 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3786 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3787 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 3788 (const_int 0)))
9ebbca7d
GK		 3789 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3790 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 3791 "TARGET_POWER"
1fd4e8c1 3792 "@
29ae5b89
JL		 3793 sre. %3,%1,%2
3794 mr. %1,%1
9ebbca7d
GK		 3795 {s%A2i.|s%A2wi.} %3,%1,%h2
3796 #
3797 #
3798 #"
3799 [(set_attr "type" "delayed_compare")
3800 (set_attr "length" "4,4,4,8,8,8")])
3801
3802(define_split
3803 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3804 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3805 (match_operand:SI 2 "reg_or_cint_operand" ""))
3806 (const_int 0)))
3807 (clobber (match_scratch:SI 3 ""))
3808 (clobber (match_scratch:SI 4 ""))]
3809 "TARGET_POWER && reload_completed"
3810 [(parallel [(set (match_dup 3)
3811 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3812 (clobber (match_dup 4))])
3813 (set (match_dup 0)
3814 (compare:CC (match_dup 3)
3815 (const_int 0)))]
3816 "")
ca7f5001
RK		 3817
3818(define_insn ""
9ebbca7d
GK		 3819 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3820 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3821 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
ca7f5001 3822 (const_int 0)))
9ebbca7d 3823 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
0ad91047 3824 "! TARGET_POWER && ! TARGET_POWERPC64"
bdf423cb
MM		 3825 "@
3826 mr. %1,%1
9ebbca7d
GK		 3827 {sr|srw}%I2. %3,%1,%h2
3828 #
3829 #"
3830 [(set_attr "type" "delayed_compare")
3831 (set_attr "length" "4,4,8,8")])
1fd4e8c1 3832
9ebbca7d
GK		 3833(define_split
3834 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3835 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3836 (match_operand:SI 2 "reg_or_cint_operand" ""))
3837 (const_int 0)))
3838 (clobber (match_scratch:SI 3 ""))]
3839 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3840 [(set (match_dup 3)
3841 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3842 (set (match_dup 0)
3843 (compare:CC (match_dup 3)
3844 (const_int 0)))]
3845 "")
3846
3847(define_insn ""
3848 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3849 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3850 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 3851 (const_int 0)))
9ebbca7d 3852 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
1fd4e8c1 3853 (lshiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 3854 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 3855 "TARGET_POWER"
1fd4e8c1 3856 "@
29ae5b89
JL		 3857 sre. %0,%1,%2
3858 mr. %0,%1
9ebbca7d
GK		 3859 {s%A2i.|s%A2wi.} %0,%1,%h2
3860 #
3861 #
3862 #"
3863 [(set_attr "type" "delayed_compare")
3864 (set_attr "length" "4,4,4,8,8,8")])
3865
3866(define_split
3867 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3868 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3869 (match_operand:SI 2 "reg_or_cint_operand" ""))
3870 (const_int 0)))
3871 (set (match_operand:SI 0 "gpc_reg_operand" "")
3872 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3873 (clobber (match_scratch:SI 4 ""))]
3874 "TARGET_POWER && reload_completed"
3875 [(parallel [(set (match_dup 0)
3876 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3877 (clobber (match_dup 4))])
3878 (set (match_dup 3)
3879 (compare:CC (match_dup 0)
3880 (const_int 0)))]
3881 "")
ca7f5001
RK		 3882
3883(define_insn ""
9ebbca7d
GK		 3884 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3885 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3886 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
815cdc52 3887 (const_int 0)))
9ebbca7d 3888 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
29ae5b89 3889 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
0ad91047 3890 "! TARGET_POWER && ! TARGET_POWERPC64"
29ae5b89
JL		 3891 "@
3892 mr. %0,%1
9ebbca7d
GK		 3893 {sr|srw}%I2. %0,%1,%h2
3894 #
3895 #"
3896 [(set_attr "type" "delayed_compare")
3897 (set_attr "length" "4,4,8,8")])
3898
3899(define_split
3900 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3901 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3902 (match_operand:SI 2 "reg_or_cint_operand" ""))
3903 (const_int 0)))
3904 (set (match_operand:SI 0 "gpc_reg_operand" "")
3905 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
3906 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3907 [(set (match_dup 0)
3908 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3909 (set (match_dup 3)
3910 (compare:CC (match_dup 0)
3911 (const_int 0)))]
3912 "")
1fd4e8c1
RK		 3913
3914(define_insn ""
cd2b37d9
RK		 3915 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3916 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 3917 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 3918 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 3919 "includes_rshift_p (operands[2], operands[3])"
ca7f5001 3920 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
1fd4e8c1
RK		 3921
3922(define_insn ""
9ebbca7d 3923 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 3924 (compare:CC
9ebbca7d
GK		 3925 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3926 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3927 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3928 (const_int 0)))
9ebbca7d 3929 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3930 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 3931 "@
3932 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3933 #"
3934 [(set_attr "type" "delayed_compare")
3935 (set_attr "length" "4,8")])
3936
3937(define_split
3938 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3939 (compare:CC
3940 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3941 (match_operand:SI 2 "const_int_operand" ""))
3942 (match_operand:SI 3 "mask_operand" ""))
3943 (const_int 0)))
3944 (clobber (match_scratch:SI 4 ""))]
ce71f754 3945 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 3946 [(set (match_dup 4)
3947 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3948 (match_dup 3)))
3949 (set (match_dup 0)
3950 (compare:CC (match_dup 4)
3951 (const_int 0)))]
3952 "")
1fd4e8c1
RK		 3953
3954(define_insn ""
9ebbca7d 3955 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3956 (compare:CC
9ebbca7d
GK		 3957 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3958 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3959 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3960 (const_int 0)))
9ebbca7d 3961 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3962 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3963 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 3964 "@
3965 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
3966 #"
3967 [(set_attr "type" "delayed_compare")
3968 (set_attr "length" "4,8")])
3969
3970(define_split
3971 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3972 (compare:CC
3973 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3974 (match_operand:SI 2 "const_int_operand" ""))
3975 (match_operand:SI 3 "mask_operand" ""))
3976 (const_int 0)))
3977 (set (match_operand:SI 0 "gpc_reg_operand" "")
3978 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3979 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 3980 [(set (match_dup 0)
3981 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3982 (set (match_dup 4)
3983 (compare:CC (match_dup 0)
3984 (const_int 0)))]
3985 "")
1fd4e8c1
RK		 3986
3987(define_insn ""
cd2b37d9 3988 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 3989 (zero_extend:SI
3990 (subreg:QI
cd2b37d9 3991 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 3992 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 3993 "includes_rshift_p (operands[2], GEN_INT (255))"
ca7f5001 3994 "{rlinm|rlwinm} %0,%1,%s2,0xff")
1fd4e8c1
RK		 3995
3996(define_insn ""
9ebbca7d 3997 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3998 (compare:CC
3999 (zero_extend:SI
4000 (subreg:QI
9ebbca7d
GK		 4001 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4002 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4003 (const_int 0)))
9ebbca7d 4004 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4005 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4006 "@
4007 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4008 #"
4009 [(set_attr "type" "delayed_compare")
4010 (set_attr "length" "4,8")])
4011
4012(define_split
4013 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4014 (compare:CC
4015 (zero_extend:SI
4016 (subreg:QI
4017 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4018 (match_operand:SI 2 "const_int_operand" "")) 0))
4019 (const_int 0)))
4020 (clobber (match_scratch:SI 3 ""))]
4021 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4022 [(set (match_dup 3)
4023 (zero_extend:SI (subreg:QI
4024 (lshiftrt:SI (match_dup 1)
4025 (match_dup 2)) 0)))
4026 (set (match_dup 0)
4027 (compare:CC (match_dup 3)
4028 (const_int 0)))]
4029 "")
1fd4e8c1
RK		 4030
4031(define_insn ""
9ebbca7d 4032 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4033 (compare:CC
4034 (zero_extend:SI
4035 (subreg:QI
9ebbca7d
GK		 4036 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4037 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4038 (const_int 0)))
9ebbca7d 4039 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4040 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4041 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4042 "@
4043 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4044 #"
4045 [(set_attr "type" "delayed_compare")
4046 (set_attr "length" "4,8")])
4047
4048(define_split
4049 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4050 (compare:CC
4051 (zero_extend:SI
4052 (subreg:QI
4053 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4054 (match_operand:SI 2 "const_int_operand" "")) 0))
4055 (const_int 0)))
4056 (set (match_operand:SI 0 "gpc_reg_operand" "")
4057 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4058 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4059 [(set (match_dup 0)
4060 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4061 (set (match_dup 3)
4062 (compare:CC (match_dup 0)
4063 (const_int 0)))]
4064 "")
1fd4e8c1
RK		 4065
4066(define_insn ""
cd2b37d9 4067 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4068 (zero_extend:SI
4069 (subreg:HI
cd2b37d9 4070 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4071 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4072 "includes_rshift_p (operands[2], GEN_INT (65535))"
ca7f5001 4073 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
1fd4e8c1
RK		 4074
4075(define_insn ""
9ebbca7d 4076 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4077 (compare:CC
4078 (zero_extend:SI
4079 (subreg:HI
9ebbca7d
GK		 4080 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4081 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4082 (const_int 0)))
9ebbca7d 4083 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4084 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4085 "@
4086 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4087 #"
4088 [(set_attr "type" "delayed_compare")
4089 (set_attr "length" "4,8")])
4090
4091(define_split
4092 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4093 (compare:CC
4094 (zero_extend:SI
4095 (subreg:HI
4096 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4097 (match_operand:SI 2 "const_int_operand" "")) 0))
4098 (const_int 0)))
4099 (clobber (match_scratch:SI 3 ""))]
4100 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4101 [(set (match_dup 3)
4102 (zero_extend:SI (subreg:HI
4103 (lshiftrt:SI (match_dup 1)
4104 (match_dup 2)) 0)))
4105 (set (match_dup 0)
4106 (compare:CC (match_dup 3)
4107 (const_int 0)))]
4108 "")
1fd4e8c1
RK		 4109
4110(define_insn ""
9ebbca7d 4111 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4112 (compare:CC
4113 (zero_extend:SI
4114 (subreg:HI
9ebbca7d
GK		 4115 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4116 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4117 (const_int 0)))
9ebbca7d 4118 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4119 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4120 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4121 "@
4122 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4123 #"
4124 [(set_attr "type" "delayed_compare")
4125 (set_attr "length" "4,8")])
4126
4127(define_split
4128 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4129 (compare:CC
4130 (zero_extend:SI
4131 (subreg:HI
4132 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4133 (match_operand:SI 2 "const_int_operand" "")) 0))
4134 (const_int 0)))
4135 (set (match_operand:SI 0 "gpc_reg_operand" "")
4136 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4137 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4138 [(set (match_dup 0)
4139 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4140 (set (match_dup 3)
4141 (compare:CC (match_dup 0)
4142 (const_int 0)))]
4143 "")
1fd4e8c1
RK		 4144
4145(define_insn ""
cd2b37d9 4146 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4147 (const_int 1)
cd2b37d9
RK		 4148 (match_operand:SI 1 "gpc_reg_operand" "r"))
4149 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4150 (const_int 31)))]
ca7f5001 4151 "TARGET_POWER"
1fd4e8c1
RK		 4152 "rrib %0,%1,%2")
4153
4154(define_insn ""
cd2b37d9 4155 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4156 (const_int 1)
cd2b37d9
RK		 4157 (match_operand:SI 1 "gpc_reg_operand" "r"))
4158 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4159 (const_int 31)))]
ca7f5001 4160 "TARGET_POWER"
1fd4e8c1
RK		 4161 "rrib %0,%1,%2")
4162
4163(define_insn ""
cd2b37d9 4164 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4165 (const_int 1)
cd2b37d9
RK		 4166 (match_operand:SI 1 "gpc_reg_operand" "r"))
4167 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4168 (const_int 1)
4169 (const_int 0)))]
ca7f5001 4170 "TARGET_POWER"
1fd4e8c1
RK		 4171 "rrib %0,%1,%2")
4172
ca7f5001
RK		 4173(define_expand "ashrsi3"
4174 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4175 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4176 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4177 ""
4178 "
4179{
4180 if (TARGET_POWER)
4181 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4182 else
25c341fa 4183 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4184 DONE;
4185}")
4186
4187(define_insn "ashrsi3_power"
cd2b37d9
RK		 4188 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4189 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4190 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4191 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4192 "TARGET_POWER"
1fd4e8c1
RK		 4193 "@
4194 srea %0,%1,%2
ca7f5001
RK		 4195 {srai|srawi} %0,%1,%h2")
4196
25c341fa 4197(define_insn "ashrsi3_no_power"
ca7f5001
RK		 4198 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4199 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4200 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
25c341fa 4201 "! TARGET_POWER"
d904e9ed 4202 "{sra|sraw}%I2 %0,%1,%h2")
1fd4e8c1
RK		 4203
4204(define_insn ""
9ebbca7d
GK		 4205 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4206 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4207 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4208 (const_int 0)))
9ebbca7d
GK		 4209 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4210 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4211 "TARGET_POWER"
1fd4e8c1
RK		 4212 "@
4213 srea. %3,%1,%2
9ebbca7d
GK		 4214 {srai.|srawi.} %3,%1,%h2
4215 #
4216 #"
4217 [(set_attr "type" "delayed_compare")
4218 (set_attr "length" "4,4,8,8")])
4219
4220(define_split
4221 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4222 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4223 (match_operand:SI 2 "reg_or_cint_operand" ""))
4224 (const_int 0)))
4225 (clobber (match_scratch:SI 3 ""))
4226 (clobber (match_scratch:SI 4 ""))]
4227 "TARGET_POWER && reload_completed"
4228 [(parallel [(set (match_dup 3)
4229 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4230 (clobber (match_dup 4))])
4231 (set (match_dup 0)
4232 (compare:CC (match_dup 3)
4233 (const_int 0)))]
4234 "")
ca7f5001
RK		 4235
4236(define_insn ""
9ebbca7d
GK		 4237 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4238 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4239 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 4240 (const_int 0)))
9ebbca7d 4241 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 4242 "! TARGET_POWER"
9ebbca7d
GK		 4243 "@
4244 {sra|sraw}%I2. %3,%1,%h2
4245 #"
4246 [(set_attr "type" "delayed_compare")
4247 (set_attr "length" "4,8")])
4248
4249(define_split
4250 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4251 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4252 (match_operand:SI 2 "reg_or_cint_operand" ""))
4253 (const_int 0)))
4254 (clobber (match_scratch:SI 3 ""))]
4255 "! TARGET_POWER && reload_completed"
4256 [(set (match_dup 3)
4257 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4258 (set (match_dup 0)
4259 (compare:CC (match_dup 3)
4260 (const_int 0)))]
4261 "")
1fd4e8c1
RK		 4262
4263(define_insn ""
9ebbca7d
GK		 4264 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4265 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4266 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4267 (const_int 0)))
9ebbca7d 4268 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4269 (ashiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4270 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4271 "TARGET_POWER"
1fd4e8c1
RK		 4272 "@
4273 srea. %0,%1,%2
9ebbca7d
GK		 4274 {srai.|srawi.} %0,%1,%h2
4275 #
4276 #"
4277 [(set_attr "type" "delayed_compare")
4278 (set_attr "length" "4,4,8,8")])
4279
4280(define_split
4281 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4282 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4283 (match_operand:SI 2 "reg_or_cint_operand" ""))
4284 (const_int 0)))
4285 (set (match_operand:SI 0 "gpc_reg_operand" "")
4286 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4287 (clobber (match_scratch:SI 4 ""))]
4288 "TARGET_POWER && reload_completed"
4289 [(parallel [(set (match_dup 0)
4290 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4291 (clobber (match_dup 4))])
4292 (set (match_dup 3)
4293 (compare:CC (match_dup 0)
4294 (const_int 0)))]
4295 "")
1fd4e8c1 4296
ca7f5001 4297(define_insn ""
9ebbca7d
GK		 4298 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4299 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4300 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 4301 (const_int 0)))
9ebbca7d 4302 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 4303 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
25c341fa 4304 "! TARGET_POWER"
9ebbca7d
GK		 4305 "@
4306 {sra|sraw}%I2. %0,%1,%h2
4307 #"
4308 [(set_attr "type" "delayed_compare")
4309 (set_attr "length" "4,8")])
1fd4e8c1 4310\f
9ebbca7d
GK		 4311(define_split
4312 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4313 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4314 (match_operand:SI 2 "reg_or_cint_operand" ""))
4315 (const_int 0)))
4316 (set (match_operand:SI 0 "gpc_reg_operand" "")
4317 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4318 "! TARGET_POWER && reload_completed"
4319 [(set (match_dup 0)
4320 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4321 (set (match_dup 3)
4322 (compare:CC (match_dup 0)
4323 (const_int 0)))]
4324 "")
4325
1fd4e8c1
RK		 4326;; Floating-point insns, excluding normal data motion.
4327;;
ca7f5001
RK		 4328;; PowerPC has a full set of single-precision floating point instructions.
4329;;
4330;; For the POWER architecture, we pretend that we have both SFmode and
4331;; DFmode insns, while, in fact, all fp insns are actually done in double.
4332;; The only conversions we will do will be when storing to memory. In that
4333;; case, we will use the "frsp" instruction before storing.
1fd4e8c1
RK		 4334;;
4335;; Note that when we store into a single-precision memory location, we need to
4336;; use the frsp insn first. If the register being stored isn't dead, we
4337;; need a scratch register for the frsp. But this is difficult when the store
4338;; is done by reload. It is not incorrect to do the frsp on the register in
4339;; this case, we just lose precision that we would have otherwise gotten but
4340;; is not guaranteed. Perhaps this should be tightened up at some point.
4341
e8112008 4342(define_insn "extendsfdf2"
cd2b37d9 4343 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
e8112008 4344 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4345 "TARGET_HARD_FLOAT && TARGET_FPRS"
e8112008 4346 "*
5c30aff8 4347{
e8112008
RK		 4348 if (REGNO (operands[0]) == REGNO (operands[1]))
4349 return \"\";
4350 else
4351 return \"fmr %0,%1\";
4352}"
4353 [(set_attr "type" "fp")])
1fd4e8c1
RK		 4354
4355(define_insn "truncdfsf2"
cd2b37d9
RK		 4356 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4357 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 4358 "TARGET_HARD_FLOAT && TARGET_FPRS"
dcac138d 4359 "frsp %0,%1"
1fd4e8c1
RK		 4360 [(set_attr "type" "fp")])
4361
455350f4
RK		 4362(define_insn "aux_truncdfsf2"
4363 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4364 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
a3170dc6 4365 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
455350f4
RK		 4366 "frsp %0,%1"
4367 [(set_attr "type" "fp")])
4368
a3170dc6
AH		 4369(define_expand "negsf2"
4370 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4371 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4372 "TARGET_HARD_FLOAT"
4373 "")
4374
4375(define_insn "*negsf2"
cd2b37d9
RK		 4376 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4377 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4378 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4379 "fneg %0,%1"
4380 [(set_attr "type" "fp")])
4381
a3170dc6
AH		 4382(define_expand "abssf2"
4383 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4384 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4385 "TARGET_HARD_FLOAT"
4386 "")
4387
4388(define_insn "*abssf2"
cd2b37d9
RK		 4389 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4390 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4391 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4392 "fabs %0,%1"
4393 [(set_attr "type" "fp")])
4394
4395(define_insn ""
cd2b37d9
RK		 4396 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4397 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
a3170dc6 4398 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4399 "fnabs %0,%1"
4400 [(set_attr "type" "fp")])
4401
ca7f5001
RK		 4402(define_expand "addsf3"
4403 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4404 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4405 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4406 "TARGET_HARD_FLOAT"
ca7f5001
RK		 4407 "")
4408
4409(define_insn ""
cd2b37d9
RK		 4410 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4411 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4412 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4413 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4414 "fadds %0,%1,%2"
ca7f5001
RK		 4415 [(set_attr "type" "fp")])
4416
4417(define_insn ""
4418 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4419 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4420 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4421 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4422 "{fa|fadd} %0,%1,%2"
ca7f5001
RK		 4423 [(set_attr "type" "fp")])
4424
4425(define_expand "subsf3"
4426 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4427 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4428 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4429 "TARGET_HARD_FLOAT"
ca7f5001
RK		 4430 "")
4431
4432(define_insn ""
4433 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4434 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4435 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4436 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4437 "fsubs %0,%1,%2"
1fd4e8c1
RK		 4438 [(set_attr "type" "fp")])
4439
ca7f5001 4440(define_insn ""
cd2b37d9
RK		 4441 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4442 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4443 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4444 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4445 "{fs|fsub} %0,%1,%2"
ca7f5001
RK		 4446 [(set_attr "type" "fp")])
4447
4448(define_expand "mulsf3"
4449 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4450 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4451 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4452 "TARGET_HARD_FLOAT"
ca7f5001
RK		 4453 "")
4454
4455(define_insn ""
4456 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4457 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4458 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4459 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4460 "fmuls %0,%1,%2"
1fd4e8c1
RK		 4461 [(set_attr "type" "fp")])
4462
ca7f5001 4463(define_insn ""
cd2b37d9
RK		 4464 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4465 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4466 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4467 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4468 "{fm|fmul} %0,%1,%2"
0780f386 4469 [(set_attr "type" "dmul")])
1fd4e8c1 4470
ca7f5001
RK		 4471(define_expand "divsf3"
4472 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4473 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4474 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4475 "TARGET_HARD_FLOAT"
ca7f5001
RK		 4476 "")
4477
4478(define_insn ""
cd2b37d9
RK		 4479 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4480 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4481 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4482 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4483 "fdivs %0,%1,%2"
ca7f5001
RK		 4484 [(set_attr "type" "sdiv")])
4485
4486(define_insn ""
4487 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4488 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4489 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4490 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4491 "{fd|fdiv} %0,%1,%2"
0780f386 4492 [(set_attr "type" "ddiv")])
1fd4e8c1
RK		 4493
4494(define_insn ""
cd2b37d9
RK		 4495 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4496 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4497 (match_operand:SF 2 "gpc_reg_operand" "f"))
4498 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4499 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4500 "fmadds %0,%1,%2,%3"
ca7f5001
RK		 4501 [(set_attr "type" "fp")])
4502
4503(define_insn ""
4504 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4505 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4506 (match_operand:SF 2 "gpc_reg_operand" "f"))
4507 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4508 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4509 "{fma|fmadd} %0,%1,%2,%3"
cf27b467 4510 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4511
4512(define_insn ""
cd2b37d9
RK		 4513 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4514 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4515 (match_operand:SF 2 "gpc_reg_operand" "f"))
4516 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4517 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4518 "fmsubs %0,%1,%2,%3"
ca7f5001
RK		 4519 [(set_attr "type" "fp")])
4520
4521(define_insn ""
4522 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4523 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4524 (match_operand:SF 2 "gpc_reg_operand" "f"))
4525 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4526 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4527 "{fms|fmsub} %0,%1,%2,%3"
cf27b467 4528 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4529
4530(define_insn ""
cd2b37d9
RK		 4531 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4532 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4533 (match_operand:SF 2 "gpc_reg_operand" "f"))
4534 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4535 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4536 && HONOR_SIGNED_ZEROS (SFmode)"
4537 "fnmadds %0,%1,%2,%3"
4538 [(set_attr "type" "fp")])
4539
4540(define_insn ""
4541 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4542 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4543 (match_operand:SF 2 "gpc_reg_operand" "f"))
4544 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4545 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4546 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 4547 "fnmadds %0,%1,%2,%3"
ca7f5001
RK		 4548 [(set_attr "type" "fp")])
4549
4550(define_insn ""
4551 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4552 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4553 (match_operand:SF 2 "gpc_reg_operand" "f"))
4554 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 4555 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4556 "{fnma|fnmadd} %0,%1,%2,%3"
cf27b467 4557 [(set_attr "type" "dmul")])
1fd4e8c1 4558
16823694
GK		 4559(define_insn ""
4560 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4561 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4562 (match_operand:SF 2 "gpc_reg_operand" "f"))
4563 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4564 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4565 && ! HONOR_SIGNED_ZEROS (SFmode)"
4566 "{fnma|fnmadd} %0,%1,%2,%3"
4567 [(set_attr "type" "dmul")])
4568
1fd4e8c1 4569(define_insn ""
cd2b37d9
RK		 4570 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4571 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4572 (match_operand:SF 2 "gpc_reg_operand" "f"))
4573 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4574 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4575 && HONOR_SIGNED_ZEROS (SFmode)"
4576 "fnmsubs %0,%1,%2,%3"
4577 [(set_attr "type" "fp")])
4578
4579(define_insn ""
4580 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4581 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4582 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4583 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4584 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4585 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 4586 "fnmsubs %0,%1,%2,%3"
ca7f5001
RK		 4587 [(set_attr "type" "fp")])
4588
4589(define_insn ""
4590 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4591 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4592 (match_operand:SF 2 "gpc_reg_operand" "f"))
4593 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 4594 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4595 "{fnms|fnmsub} %0,%1,%2,%3"
cf27b467 4596 [(set_attr "type" "dmul")])
1fd4e8c1 4597
16823694
GK		 4598(define_insn ""
4599 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4600 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4601 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4602 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4603 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4604 && ! HONOR_SIGNED_ZEROS (SFmode)"
4605 "{fnms|fnmsub} %0,%1,%2,%3"
4606 [(set_attr "type" "fp")])
4607
ca7f5001
RK		 4608(define_expand "sqrtsf2"
4609 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4610 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
a3170dc6 4611 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 4612 "")
4613
4614(define_insn ""
4615 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4616 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4617 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 4618 "fsqrts %0,%1"
4619 [(set_attr "type" "ssqrt")])
4620
4621(define_insn ""
4622 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4623 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4624 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 4625 "fsqrt %0,%1"
4626 [(set_attr "type" "dsqrt")])
4627
94d7001a
RK		 4628;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4629;; fsel instruction and some auxiliary computations. Then we just have a
4630;; single DEFINE_INSN for fsel and the define_splits to make them if made by
8e871c05
RK		 4631;; combine.
4632(define_expand "maxsf3"
8e871c05 4633 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 4634 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4635 (match_operand:SF 2 "gpc_reg_operand" ""))
8e871c05
RK		 4636 (match_dup 1)
4637 (match_dup 2)))]
a3170dc6 4638 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056 4639 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
2f607b94 4640
8e871c05 4641(define_expand "minsf3"
50a0b056
GK		 4642 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4643 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4644 (match_operand:SF 2 "gpc_reg_operand" ""))
4645 (match_dup 2)
4646 (match_dup 1)))]
a3170dc6 4647 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056 4648 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
2f607b94 4649
8e871c05
RK		 4650(define_split
4651 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 4652 (match_operator:SF 3 "min_max_operator"
4653 [(match_operand:SF 1 "gpc_reg_operand" "")
4654 (match_operand:SF 2 "gpc_reg_operand" "")]))]
a3170dc6 4655 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056
GK		 4656 [(const_int 0)]
4657 "
4658{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4659 operands[1], operands[2]);
4660 DONE;
4661}")
2f607b94 4662
a3170dc6
AH		 4663(define_expand "movsicc"
4664 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4665 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4666 (match_operand:SI 2 "gpc_reg_operand" "")
4667 (match_operand:SI 3 "gpc_reg_operand" "")))]
4668 "TARGET_ISEL"
4669 "
4670{
4671 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4672 DONE;
4673 else
4674 FAIL;
4675}")
4676
4677;; We use the BASE_REGS for the isel input operands because, if rA is
4678;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4679;; because we may switch the operands and rB may end up being rA.
4680;;
4681;; We need 2 patterns: an unsigned and a signed pattern. We could
4682;; leave out the mode in operand 4 and use one pattern, but reload can
4683;; change the mode underneath our feet and then gets confused trying
4684;; to reload the value.
4685(define_insn "isel_signed"
4686 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4687 (if_then_else:SI
4688 (match_operator 1 "comparison_operator"
4689 [(match_operand:CC 4 "cc_reg_operand" "y")
4690 (const_int 0)])
4691 (match_operand:SI 2 "gpc_reg_operand" "b")
4692 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4693 "TARGET_ISEL"
4694 "*
4695{ return output_isel (operands); }"
4696 [(set_attr "length" "4")])
4697
4698(define_insn "isel_unsigned"
4699 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4700 (if_then_else:SI
4701 (match_operator 1 "comparison_operator"
4702 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4703 (const_int 0)])
4704 (match_operand:SI 2 "gpc_reg_operand" "b")
4705 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4706 "TARGET_ISEL"
4707 "*
4708{ return output_isel (operands); }"
4709 [(set_attr "length" "4")])
4710
94d7001a 4711(define_expand "movsfcc"
0ad91047 4712 [(set (match_operand:SF 0 "gpc_reg_operand" "")
94d7001a 4713 (if_then_else:SF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 4714 (match_operand:SF 2 "gpc_reg_operand" "")
4715 (match_operand:SF 3 "gpc_reg_operand" "")))]
a3170dc6 4716 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 4717 "
4718{
50a0b056
GK		 4719 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4720 DONE;
94d7001a 4721 else
50a0b056 4722 FAIL;
94d7001a 4723}")
d56d506a 4724
50a0b056 4725(define_insn "*fselsfsf4"
8e871c05
RK		 4726 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4727 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 4728 (match_operand:SF 4 "zero_fp_constant" "F"))
8e871c05
RK		 4729 (match_operand:SF 2 "gpc_reg_operand" "f")
4730 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4731 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 4732 "fsel %0,%1,%2,%3"
4733 [(set_attr "type" "fp")])
2f607b94 4734
50a0b056 4735(define_insn "*fseldfsf4"
94d7001a
RK		 4736 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4737 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
d365ba42 4738 (match_operand:DF 4 "zero_fp_constant" "F"))
94d7001a
RK		 4739 (match_operand:SF 2 "gpc_reg_operand" "f")
4740 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4741 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 4742 "fsel %0,%1,%2,%3"
4743 [(set_attr "type" "fp")])
d56d506a 4744
1fd4e8c1 4745(define_insn "negdf2"
cd2b37d9
RK		 4746 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4747 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 4748 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4749 "fneg %0,%1"
4750 [(set_attr "type" "fp")])
4751
4752(define_insn "absdf2"
cd2b37d9
RK		 4753 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4754 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 4755 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4756 "fabs %0,%1"
4757 [(set_attr "type" "fp")])
4758
4759(define_insn ""
cd2b37d9
RK		 4760 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4761 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
a3170dc6 4762 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4763 "fnabs %0,%1"
4764 [(set_attr "type" "fp")])
4765
4766(define_insn "adddf3"
cd2b37d9
RK		 4767 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4768 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4769 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4770 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4771 "{fa|fadd} %0,%1,%2"
1fd4e8c1
RK		 4772 [(set_attr "type" "fp")])
4773
4774(define_insn "subdf3"
cd2b37d9
RK		 4775 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4776 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4777 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4778 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4779 "{fs|fsub} %0,%1,%2"
1fd4e8c1
RK		 4780 [(set_attr "type" "fp")])
4781
4782(define_insn "muldf3"
cd2b37d9
RK		 4783 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4784 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4785 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4786 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4787 "{fm|fmul} %0,%1,%2"
cfb557c4 4788 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4789
4790(define_insn "divdf3"
cd2b37d9
RK		 4791 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4792 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4793 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4794 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4795 "{fd|fdiv} %0,%1,%2"
cfb557c4 4796 [(set_attr "type" "ddiv")])
1fd4e8c1
RK		 4797
4798(define_insn ""
cd2b37d9
RK		 4799 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4800 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4801 (match_operand:DF 2 "gpc_reg_operand" "f"))
4802 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 4803 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 4804 "{fma|fmadd} %0,%1,%2,%3"
cfb557c4 4805 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4806
4807(define_insn ""
cd2b37d9
RK		 4808 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4809 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4810 (match_operand:DF 2 "gpc_reg_operand" "f"))
4811 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 4812 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 4813 "{fms|fmsub} %0,%1,%2,%3"
cfb557c4 4814 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4815
4816(define_insn ""
cd2b37d9
RK		 4817 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4818 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4819 (match_operand:DF 2 "gpc_reg_operand" "f"))
4820 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4821 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4822 && HONOR_SIGNED_ZEROS (DFmode)"
4823 "{fnma|fnmadd} %0,%1,%2,%3"
4824 [(set_attr "type" "dmul")])
4825
4826(define_insn ""
4827 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4828 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4829 (match_operand:DF 2 "gpc_reg_operand" "f"))
4830 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4831 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4832 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 4833 "{fnma|fnmadd} %0,%1,%2,%3"
cfb557c4 4834 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4835
4836(define_insn ""
cd2b37d9
RK		 4837 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4838 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4839 (match_operand:DF 2 "gpc_reg_operand" "f"))
4840 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4841 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4842 && HONOR_SIGNED_ZEROS (DFmode)"
4843 "{fnms|fnmsub} %0,%1,%2,%3"
4844 [(set_attr "type" "dmul")])
4845
4846(define_insn ""
4847 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4848 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
4849 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4850 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
4851 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4852 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 4853 "{fnms|fnmsub} %0,%1,%2,%3"
cfb557c4 4854 [(set_attr "type" "dmul")])
ca7f5001
RK		 4855
4856(define_insn "sqrtdf2"
4857 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4858 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 4859 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 4860 "fsqrt %0,%1"
4861 [(set_attr "type" "dsqrt")])
b77dfefc 4862
50a0b056
GK		 4863;; The conditional move instructions allow us to perform max and min
4864;; operations even when
b77dfefc 4865
8e871c05 4866(define_expand "maxdf3"
8e871c05 4867 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 4868 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4869 (match_operand:DF 2 "gpc_reg_operand" ""))
8e871c05
RK		 4870 (match_dup 1)
4871 (match_dup 2)))]
a3170dc6 4872 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056 4873 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
b77dfefc 4874
8e871c05 4875(define_expand "mindf3"
50a0b056
GK		 4876 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4877 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4878 (match_operand:DF 2 "gpc_reg_operand" ""))
4879 (match_dup 2)
4880 (match_dup 1)))]
a3170dc6 4881 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056 4882 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
b77dfefc 4883
8e871c05
RK		 4884(define_split
4885 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 4886 (match_operator:DF 3 "min_max_operator"
4887 [(match_operand:DF 1 "gpc_reg_operand" "")
4888 (match_operand:DF 2 "gpc_reg_operand" "")]))]
a3170dc6 4889 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056
GK		 4890 [(const_int 0)]
4891 "
4892{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4893 operands[1], operands[2]);
4894 DONE;
4895}")
b77dfefc 4896
94d7001a 4897(define_expand "movdfcc"
0ad91047 4898 [(set (match_operand:DF 0 "gpc_reg_operand" "")
94d7001a 4899 (if_then_else:DF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 4900 (match_operand:DF 2 "gpc_reg_operand" "")
4901 (match_operand:DF 3 "gpc_reg_operand" "")))]
a3170dc6 4902 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 4903 "
4904{
50a0b056
GK		 4905 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4906 DONE;
94d7001a 4907 else
50a0b056 4908 FAIL;
94d7001a 4909}")
d56d506a 4910
50a0b056 4911(define_insn "*fseldfdf4"
8e871c05
RK		 4912 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4913 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
50a0b056 4914 (match_operand:DF 4 "zero_fp_constant" "F"))
8e871c05
RK		 4915 (match_operand:DF 2 "gpc_reg_operand" "f")
4916 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 4917 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 4918 "fsel %0,%1,%2,%3"
4919 [(set_attr "type" "fp")])
d56d506a 4920
50a0b056 4921(define_insn "*fselsfdf4"
94d7001a
RK		 4922 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4923 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 4924 (match_operand:SF 4 "zero_fp_constant" "F"))
94d7001a
RK		 4925 (match_operand:DF 2 "gpc_reg_operand" "f")
4926 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4927 "TARGET_PPC_GFXOPT"
4928 "fsel %0,%1,%2,%3"
4929 [(set_attr "type" "fp")])
1fd4e8c1
RK		 4930\f
4931;; Conversions to and from floating-point.
802a0058 4932
a3170dc6
AH		 4933(define_expand "fixunssfsi2"
4934 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4935 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "gpc_reg_operand" ""))))]
4936 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4937 "")
4938
4939(define_expand "fix_truncsfsi2"
4940 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4941 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
4942 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4943 "")
4944
9ebbca7d
GK		 4945; For each of these conversions, there is a define_expand, a define_insn
4946; with a '#' template, and a define_split (with C code). The idea is
4947; to allow constant folding with the template of the define_insn,
4948; then to have the insns split later (between sched1 and final).
4949
1fd4e8c1 4950(define_expand "floatsidf2"
802a0058
MM		 4951 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
4952 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4953 (use (match_dup 2))
4954 (use (match_dup 3))
208c89ce 4955 (clobber (match_dup 4))
a7df97e6 4956 (clobber (match_dup 5))
9ebbca7d 4957 (clobber (match_dup 6))])]
a3170dc6 4958 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4959 "
4960{
05d49501
AM		 4961 if (TARGET_POWERPC64)
4962 {
4963 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
4964 rtx t1 = gen_reg_rtx (DImode);
4965 rtx t2 = gen_reg_rtx (DImode);
4966 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
4967 DONE;
4968 }
4969
802a0058 4970 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 4971 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
9ebbca7d
GK		 4972 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
4973 operands[5] = gen_reg_rtx (DFmode);
4974 operands[6] = gen_reg_rtx (SImode);
1fd4e8c1
RK		 4975}")
4976
802a0058
MM		 4977(define_insn "*floatsidf2_internal"
4978 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
4979 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
4980 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
4981 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
9ebbca7d 4982 (clobber (match_operand:DF 4 "memory_operand" "=o"))
6f9c81f5
DJ		 4983 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
4984 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
a3170dc6 4985 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 4986 "#"
a7df97e6 4987 [(set_attr "length" "24")])
802a0058
MM		 4988
4989(define_split
dbe3df29 4990 [(set (match_operand:DF 0 "gpc_reg_operand" "")
802a0058
MM		 4991 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4992 (use (match_operand:SI 2 "gpc_reg_operand" ""))
4993 (use (match_operand:DF 3 "gpc_reg_operand" ""))
9ebbca7d
GK		 4994 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
4995 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
4996 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
a3170dc6 4997 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
9ebbca7d
GK		 4998 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4999 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5000 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5001 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5002 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5003 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5004 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
208c89ce
MM		 5005 "
5006{
9ebbca7d
GK		 5007 rtx lowword, highword;
5008 if (GET_CODE (operands[4]) != MEM)
5009 abort();
5010 highword = XEXP (operands[4], 0);
5011 lowword = plus_constant (highword, 4);
5012 if (! WORDS_BIG_ENDIAN)
5013 {
5014 rtx tmp;
5015 tmp = highword; highword = lowword; lowword = tmp;
5016 }
5017
5018 emit_insn (gen_xorsi3 (operands[6], operands[1],
5019 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5020 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5021 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5022 emit_move_insn (operands[5], operands[4]);
5023 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5024 DONE;
208c89ce 5025}")
802a0058 5026
a3170dc6
AH		 5027(define_expand "floatunssisf2"
5028 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5029 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5030 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5031 "")
5032
802a0058
MM		 5033(define_expand "floatunssidf2"
5034 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5035 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5036 (use (match_dup 2))
5037 (use (match_dup 3))
a7df97e6 5038 (clobber (match_dup 4))
9ebbca7d 5039 (clobber (match_dup 5))])]
a3170dc6 5040 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5041 "
5042{
05d49501
AM		 5043 if (TARGET_POWERPC64)
5044 {
5045 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5046 rtx t1 = gen_reg_rtx (DImode);
5047 rtx t2 = gen_reg_rtx (DImode);
5048 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5049 t1, t2));
5050 DONE;
5051 }
5052
802a0058 5053 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5054 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
9ebbca7d
GK		 5055 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5056 operands[5] = gen_reg_rtx (DFmode);
1fd4e8c1
RK		 5057}")
5058
802a0058
MM		 5059(define_insn "*floatunssidf2_internal"
5060 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5061 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5062 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5063 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
9ebbca7d 5064 (clobber (match_operand:DF 4 "memory_operand" "=o"))
6f9c81f5 5065 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
a3170dc6 5066 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5067 "#"
a7df97e6 5068 [(set_attr "length" "20")])
802a0058
MM		 5069
5070(define_split
5071 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5072 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5073 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5074 (use (match_operand:DF 3 "gpc_reg_operand" ""))
9ebbca7d
GK		 5075 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5076 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
a3170dc6 5077 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
9ebbca7d
GK		 5078 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5079 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5080 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5081 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5082 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5083 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5084 "
802a0058 5085{
9ebbca7d
GK		 5086 rtx lowword, highword;
5087 if (GET_CODE (operands[4]) != MEM)
5088 abort();
5089 highword = XEXP (operands[4], 0);
5090 lowword = plus_constant (highword, 4);
5091 if (! WORDS_BIG_ENDIAN)
f6968f59 5092 {
9ebbca7d
GK		 5093 rtx tmp;
5094 tmp = highword; highword = lowword; lowword = tmp;
f6968f59 5095 }
802a0058 5096
9ebbca7d
GK		 5097 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5098 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5099 emit_move_insn (operands[5], operands[4]);
5100 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5101 DONE;
5102}")
1fd4e8c1 5103
1fd4e8c1 5104(define_expand "fix_truncdfsi2"
802a0058
MM		 5105 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5106 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5107 (clobber (match_dup 2))
9ebbca7d 5108 (clobber (match_dup 3))])]
a3170dc6 5109 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5110 "
5111{
802a0058 5112 operands[2] = gen_reg_rtx (DImode);
9ebbca7d 5113 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
1fd4e8c1
RK		 5114}")
5115
802a0058
MM		 5116(define_insn "*fix_truncdfsi2_internal"
5117 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5118 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
e3485bbc 5119 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
9ebbca7d 5120 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
a3170dc6 5121 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5122 "#"
9ebbca7d 5123 [(set_attr "length" "16")])
802a0058
MM		 5124
5125(define_split
5126 [(set (match_operand:SI 0 "gpc_reg_operand" "")
75540af0 5127 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
802a0058 5128 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
9ebbca7d 5129 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
a3170dc6 5130 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
9ebbca7d 5131 [(set (match_operand:SI 0 "gpc_reg_operand" "")
75540af0 5132 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
9ebbca7d
GK		 5133 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5134 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5135 "
802a0058 5136{
9ebbca7d
GK		 5137 rtx lowword;
5138 if (GET_CODE (operands[3]) != MEM)
5139 abort();
5140 lowword = XEXP (operands[3], 0);
5141 if (WORDS_BIG_ENDIAN)
5142 lowword = plus_constant (lowword, 4);
802a0058 5143
9ebbca7d
GK		 5144 emit_insn (gen_fctiwz (operands[2], operands[1]));
5145 emit_move_insn (operands[3], operands[2]);
5146 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5147 DONE;
5148}")
802a0058 5149
9ebbca7d
GK		 5150; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10))
5151; rather than (set (subreg:SI (reg)) (fix:SI ...))
5152; because the first makes it clear that operand 0 is not live
5153; before the instruction.
5154(define_insn "fctiwz"
61c07d3c 5155 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
9ebbca7d 5156 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))]
a3170dc6 5157 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
a260abc9
DE		 5158 "{fcirz|fctiwz} %0,%1"
5159 [(set_attr "type" "fp")])
5160
a3170dc6
AH		 5161(define_expand "floatsisf2"
5162 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5163 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5164 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5165 "")
5166
a473029f
RK		 5167(define_insn "floatdidf2"
5168 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
61c07d3c 5169 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
a3170dc6 5170 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 5171 "fcfid %0,%1"
5172 [(set_attr "type" "fp")])
5173
05d49501
AM		 5174(define_insn_and_split "floatsidf_ppc64"
5175 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5176 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5177 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5178 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5179 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
a3170dc6 5180 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501
AM		 5181 "#"
5182 ""
5183 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5184 (set (match_dup 2) (match_dup 3))
5185 (set (match_dup 4) (match_dup 2))
5186 (set (match_dup 0) (float:DF (match_dup 4)))]
5187 "")
5188
5189(define_insn_and_split "floatunssidf_ppc64"
5190 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5191 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5192 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5193 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5194 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
a3170dc6 5195 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501
AM		 5196 "#"
5197 ""
5198 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5199 (set (match_dup 2) (match_dup 3))
5200 (set (match_dup 4) (match_dup 2))
5201 (set (match_dup 0) (float:DF (match_dup 4)))]
5202 "")
5203
a473029f 5204(define_insn "fix_truncdfdi2"
61c07d3c 5205 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
a473029f 5206 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5207 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 5208 "fctidz %0,%1"
5209 [(set_attr "type" "fp")])
ea112fc4 5210
678b7733
AM		 5211(define_expand "floatdisf2"
5212 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5213 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5214 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5215 "
5216{
5217 if (!flag_unsafe_math_optimizations)
5218 {
5219 rtx label = gen_label_rtx ();
5220 emit_insn (gen_floatdisf2_internal2 (operands[1], label));
5221 emit_label (label);
5222 }
5223 emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1]));
5224 DONE;
5225}")
5226
5227;; This is not IEEE compliant if rounding mode is "round to nearest".
5228;; If the DI->DF conversion is inexact, then it's possible to suffer
5229;; from double rounding.
5230(define_insn_and_split "floatdisf2_internal1"
ea112fc4 5231 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
61c07d3c 5232 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
ea112fc4 5233 (clobber (match_scratch:DF 2 "=f"))]
678b7733 5234 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
ea112fc4
DE		 5235 "#"
5236 "&& reload_completed"
5237 [(set (match_dup 2)
5238 (float:DF (match_dup 1)))
5239 (set (match_dup 0)
5240 (float_truncate:SF (match_dup 2)))]
5241 "")
678b7733
AM		 5242
5243;; Twiddles bits to avoid double rounding.
b6d08ca1 5244;; Bits that might be truncated when converting to DFmode are replaced
678b7733
AM		 5245;; by a bit that won't be lost at that stage, but is below the SFmode
5246;; rounding position.
5247(define_expand "floatdisf2_internal2"
42a6388c
AM		 5248 [(parallel [(set (match_dup 4)
5249 (compare:CC (and:DI (match_operand:DI 0 "" "")
5250 (const_int 2047))
5251 (const_int 0)))
5252 (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047)))
5253 (clobber (match_scratch:CC 7 ""))])
678b7733
AM		 5254 (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53)))
5255 (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1)))
5256 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
5257 (label_ref (match_operand:DI 1 "" ""))
5258 (pc)))
5259 (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2)))
5260 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
5261 (label_ref (match_dup 1))
5262 (pc)))
5263 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2)))
5264 (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))]
5265 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5266 "
5267{
5268 operands[2] = gen_reg_rtx (DImode);
5269 operands[3] = gen_reg_rtx (DImode);
5270 operands[4] = gen_reg_rtx (CCmode);
5271 operands[5] = gen_reg_rtx (CCUNSmode);
5272}")
1fd4e8c1
RK		 5273\f
5274;; Define the DImode operations that can be done in a small number
a6ec530c
RK		 5275;; of instructions. The & constraints are to prevent the register
5276;; allocator from allocating registers that overlap with the inputs
5277;; (for example, having an input in 7,8 and an output in 6,7). We
38e01259 5278;; also allow for the output being the same as one of the inputs.
a6ec530c 5279
266eb58a 5280(define_insn "*adddi3_noppc64"
a6ec530c
RK		 5281 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5282 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5283 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
e1f83b4d 5284 "! TARGET_POWERPC64"
0f645302
MM		 5285 "*
5286{
5287 if (WORDS_BIG_ENDIAN)
5288 return (GET_CODE (operands[2])) != CONST_INT
5289 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5290 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5291 else
5292 return (GET_CODE (operands[2])) != CONST_INT
5293 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5294 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5295}"
b19003d8 5296 [(set_attr "length" "8")])
1fd4e8c1 5297
266eb58a 5298(define_insn "*subdi3_noppc64"
e7e5df70
RK		 5299 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5300 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5301 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
266eb58a 5302 "! TARGET_POWERPC64"
5502823b
RK		 5303 "*
5304{
0f645302
MM		 5305 if (WORDS_BIG_ENDIAN)
5306 return (GET_CODE (operands[1]) != CONST_INT)
5307 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5308 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5309 else
5310 return (GET_CODE (operands[1]) != CONST_INT)
5311 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5312 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5502823b 5313}"
ca7f5001
RK		 5314 [(set_attr "length" "8")])
5315
266eb58a 5316(define_insn "*negdi2_noppc64"
a6ec530c
RK		 5317 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5318 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
51b8fc2c 5319 "! TARGET_POWERPC64"
5502823b
RK		 5320 "*
5321{
5322 return (WORDS_BIG_ENDIAN)
5323 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5324 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5325}"
ca7f5001
RK		 5326 [(set_attr "length" "8")])
5327
8ffd9c51
RK		 5328(define_expand "mulsidi3"
5329 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5330 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5331 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
a2f270cc 5332 "! TARGET_POWERPC64"
8ffd9c51
RK		 5333 "
5334{
5335 if (! TARGET_POWER && ! TARGET_POWERPC)
5336 {
39403d82
DE		 5337 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5338 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 5339 emit_insn (gen_mull_call ());
cf27b467 5340 if (WORDS_BIG_ENDIAN)
39403d82 5341 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
cf27b467
MM		 5342 else
5343 {
5344 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
39403d82 5345 gen_rtx_REG (SImode, 3));
cf27b467 5346 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
39403d82 5347 gen_rtx_REG (SImode, 4));
cf27b467 5348 }
8ffd9c51
RK		 5349 DONE;
5350 }
5351 else if (TARGET_POWER)
5352 {
5353 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5354 DONE;
5355 }
5356}")
deb9225a 5357
8ffd9c51 5358(define_insn "mulsidi3_mq"
cd2b37d9 5359 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8ffd9c51 5360 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
cd2b37d9 5361 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1fd4e8c1 5362 (clobber (match_scratch:SI 3 "=q"))]
ca7f5001 5363 "TARGET_POWER"
b19003d8 5364 "mul %0,%1,%2\;mfmq %L0"
8ffd9c51
RK		 5365 [(set_attr "type" "imul")
5366 (set_attr "length" "8")])
deb9225a 5367
f192bf8b 5368(define_insn "*mulsidi3_no_mq"
425c176f 5369 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
8ffd9c51
RK		 5370 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5371 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 5372 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5502823b
RK		 5373 "*
5374{
5375 return (WORDS_BIG_ENDIAN)
5376 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5377 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5378}"
8ffd9c51
RK		 5379 [(set_attr "type" "imul")
5380 (set_attr "length" "8")])
deb9225a 5381
ebedb4dd
MM		 5382(define_split
5383 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5384 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5385 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 5386 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 5387 [(set (match_dup 3)
5388 (truncate:SI
5389 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5390 (sign_extend:DI (match_dup 2)))
5391 (const_int 32))))
5392 (set (match_dup 4)
5393 (mult:SI (match_dup 1)
5394 (match_dup 2)))]
5395 "
5396{
5397 int endian = (WORDS_BIG_ENDIAN == 0);
5398 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5399 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5400}")
5401
f192bf8b
DE		 5402(define_expand "umulsidi3"
5403 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5404 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5405 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5406 "TARGET_POWERPC && ! TARGET_POWERPC64"
5407 "
5408{
5409 if (TARGET_POWER)
5410 {
5411 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5412 DONE;
5413 }
5414}")
5415
5416(define_insn "umulsidi3_mq"
5417 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5418 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5419 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5420 (clobber (match_scratch:SI 3 "=q"))]
5421 "TARGET_POWERPC && TARGET_POWER"
5422 "*
5423{
5424 return (WORDS_BIG_ENDIAN)
5425 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5426 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5427}"
5428 [(set_attr "type" "imul")
5429 (set_attr "length" "8")])
5430
5431(define_insn "*umulsidi3_no_mq"
8106dc08
MM		 5432 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5433 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5434 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 5435 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
8106dc08
MM		 5436 "*
5437{
5438 return (WORDS_BIG_ENDIAN)
5439 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5440 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5441}"
5442 [(set_attr "type" "imul")
5443 (set_attr "length" "8")])
5444
ebedb4dd
MM		 5445(define_split
5446 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5447 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5448 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 5449 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 5450 [(set (match_dup 3)
5451 (truncate:SI
5452 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5453 (zero_extend:DI (match_dup 2)))
5454 (const_int 32))))
5455 (set (match_dup 4)
5456 (mult:SI (match_dup 1)
5457 (match_dup 2)))]
5458 "
5459{
5460 int endian = (WORDS_BIG_ENDIAN == 0);
5461 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5462 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5463}")
5464
8ffd9c51
RK		 5465(define_expand "smulsi3_highpart"
5466 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5467 (truncate:SI
5468 (lshiftrt:DI (mult:DI (sign_extend:DI
5469 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5470 (sign_extend:DI
5471 (match_operand:SI 2 "gpc_reg_operand" "r")))
5472 (const_int 32))))]
5473 ""
5474 "
5475{
5476 if (! TARGET_POWER && ! TARGET_POWERPC)
5477 {
39403d82
DE		 5478 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5479 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 5480 emit_insn (gen_mulh_call ());
39403d82 5481 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 5482 DONE;
5483 }
5484 else if (TARGET_POWER)
5485 {
5486 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5487 DONE;
5488 }
5489}")
deb9225a 5490
8ffd9c51
RK		 5491(define_insn "smulsi3_highpart_mq"
5492 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5493 (truncate:SI
fada905b
MM		 5494 (lshiftrt:DI (mult:DI (sign_extend:DI
5495 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5496 (sign_extend:DI
5497 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51
RK		 5498 (const_int 32))))
5499 (clobber (match_scratch:SI 3 "=q"))]
5500 "TARGET_POWER"
5501 "mul %0,%1,%2"
5502 [(set_attr "type" "imul")])
deb9225a 5503
f192bf8b 5504(define_insn "*smulsi3_highpart_no_mq"
8ffd9c51
RK		 5505 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5506 (truncate:SI
fada905b
MM		 5507 (lshiftrt:DI (mult:DI (sign_extend:DI
5508 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5509 (sign_extend:DI
5510 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51 5511 (const_int 32))))]
f192bf8b 5512 "TARGET_POWERPC && ! TARGET_POWER"
8ffd9c51
RK		 5513 "mulhw %0,%1,%2"
5514 [(set_attr "type" "imul")])
deb9225a 5515
f192bf8b
DE		 5516(define_expand "umulsi3_highpart"
5517 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5518 (truncate:SI
5519 (lshiftrt:DI (mult:DI (zero_extend:DI
5520 (match_operand:SI 1 "gpc_reg_operand" ""))
5521 (zero_extend:DI
5522 (match_operand:SI 2 "gpc_reg_operand" "")))
5523 (const_int 32))))]
5524 "TARGET_POWERPC"
5525 "
5526{
5527 if (TARGET_POWER)
5528 {
5529 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5530 DONE;
5531 }
5532}")
5533
5534(define_insn "umulsi3_highpart_mq"
5535 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5536 (truncate:SI
5537 (lshiftrt:DI (mult:DI (zero_extend:DI
5538 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5539 (zero_extend:DI
5540 (match_operand:SI 2 "gpc_reg_operand" "r")))
5541 (const_int 32))))
5542 (clobber (match_scratch:SI 3 "=q"))]
5543 "TARGET_POWERPC && TARGET_POWER"
5544 "mulhwu %0,%1,%2"
5545 [(set_attr "type" "imul")])
5546
5547(define_insn "*umulsi3_highpart_no_mq"
266eb58a
DE		 5548 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5549 (truncate:SI
5550 (lshiftrt:DI (mult:DI (zero_extend:DI
5551 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5552 (zero_extend:DI
5553 (match_operand:SI 2 "gpc_reg_operand" "r")))
5554 (const_int 32))))]
f192bf8b 5555 "TARGET_POWERPC && ! TARGET_POWER"
266eb58a
DE		 5556 "mulhwu %0,%1,%2"
5557 [(set_attr "type" "imul")])
5558
5559;; If operands 0 and 2 are in the same register, we have a problem. But
5560;; operands 0 and 1 (the usual case) can be in the same register. That's
5561;; why we have the strange constraints below.
5562(define_insn "ashldi3_power"
5563 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5564 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5565 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5566 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5567 "TARGET_POWER"
5568 "@
5569 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5570 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5571 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5572 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5573 [(set_attr "length" "8")])
5574
5575(define_insn "lshrdi3_power"
47ad8c61 5576 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
266eb58a
DE		 5577 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5578 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5579 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5580 "TARGET_POWER"
5581 "@
47ad8c61 5582 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
266eb58a
DE		 5583 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5584 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5585 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5586 [(set_attr "length" "8")])
5587
5588;; Shift by a variable amount is too complex to be worth open-coding. We
5589;; just handle shifts by constants.
5590(define_insn "ashrdi3_power"
7093ddee 5591 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
266eb58a
DE		 5592 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5593 (match_operand:SI 2 "const_int_operand" "M,i")))
5594 (clobber (match_scratch:SI 3 "=X,q"))]
5595 "TARGET_POWER"
5596 "@
5597 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5598 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5599 [(set_attr "length" "8")])
4aa74a4f
FS		 5600
5601(define_insn "ashrdi3_no_power"
5602 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5603 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5604 (match_operand:SI 2 "const_int_operand" "M,i")))]
5605 "TARGET_32BIT && !TARGET_POWER"
5606 "@
5607 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5608 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5609 [(set_attr "length" "8,12")])
266eb58a
DE		 5610\f
5611;; PowerPC64 DImode operations.
5612
5613(define_expand "adddi3"
5614 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5615 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
2bfcf297 5616 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
266eb58a
DE		 5617 ""
5618 "
5619{
a260abc9
DE		 5620 if (! TARGET_POWERPC64)
5621 {
5622 if (non_short_cint_operand (operands[2], DImode))
5623 FAIL;
5624 }
5625 else
5626 if (GET_CODE (operands[2]) == CONST_INT
677a9668 5627 && ! add_operand (operands[2], DImode))
a260abc9 5628 {
677a9668 5629 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
a260abc9
DE		 5630 ? operands[0] : gen_reg_rtx (DImode));
5631
2bfcf297 5632 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 5633 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2bfcf297 5634 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
a260abc9 5635
2bfcf297
DB		 5636 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5637 FAIL;
a260abc9 5638
2bfcf297
DB		 5639 /* The ordering here is important for the prolog expander.
5640 When space is allocated from the stack, adding 'low' first may
5641 produce a temporary deallocation (which would be bad). */
5642 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
a260abc9
DE		 5643 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5644 DONE;
5645 }
266eb58a
DE		 5646}")
5647
5648;; Discourage ai/addic because of carry but provide it in an alternative
5649;; allowing register zero as source.
5650
a260abc9 5651(define_insn "*adddi3_internal1"
266eb58a
DE		 5652 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5653 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
9615f239 5654 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
266eb58a
DE		 5655 "TARGET_POWERPC64"
5656 "@
5657 add %0,%1,%2
5658 addi %0,%1,%2
5659 addic %0,%1,%2
802a0058 5660 addis %0,%1,%v2")
266eb58a 5661
a260abc9 5662(define_insn "*adddi3_internal2"
9ebbca7d
GK		 5663 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5664 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5665 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
266eb58a 5666 (const_int 0)))
9ebbca7d 5667 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
266eb58a
DE		 5668 "TARGET_POWERPC64"
5669 "@
5670 add. %3,%1,%2
9ebbca7d
GK		 5671 addic. %3,%1,%2
5672 #
5673 #"
a62bfff2 5674 [(set_attr "type" "fast_compare,compare,compare,compare")
9ebbca7d
GK		 5675 (set_attr "length" "4,4,8,8")])
5676
5677(define_split
5678 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5679 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5680 (match_operand:DI 2 "reg_or_short_operand" ""))
5681 (const_int 0)))
5682 (clobber (match_scratch:DI 3 ""))]
5683 "TARGET_POWERPC64 && reload_completed"
5684 [(set (match_dup 3)
5685 (plus:DI (match_dup 1) (match_dup 2)))
5686 (set (match_dup 0)
5687 (compare:CC (match_dup 3)
5688 (const_int 0)))]
5689 "")
266eb58a 5690
a260abc9 5691(define_insn "*adddi3_internal3"
9ebbca7d
GK		 5692 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5693 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5694 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
266eb58a 5695 (const_int 0)))
9ebbca7d 5696 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a
DE		 5697 (plus:DI (match_dup 1) (match_dup 2)))]
5698 "TARGET_POWERPC64"
5699 "@
5700 add. %0,%1,%2
9ebbca7d
GK		 5701 addic. %0,%1,%2
5702 #
5703 #"
a62bfff2 5704 [(set_attr "type" "fast_compare,compare,compare,compare")
9ebbca7d
GK		 5705 (set_attr "length" "4,4,8,8")])
5706
5707(define_split
5708 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5709 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5710 (match_operand:DI 2 "reg_or_short_operand" ""))
5711 (const_int 0)))
5712 (set (match_operand:DI 0 "gpc_reg_operand" "")
5713 (plus:DI (match_dup 1) (match_dup 2)))]
5714 "TARGET_POWERPC64 && reload_completed"
5715 [(set (match_dup 0)
5716 (plus:DI (match_dup 1) (match_dup 2)))
5717 (set (match_dup 3)
5718 (compare:CC (match_dup 0)
5719 (const_int 0)))]
5720 "")
266eb58a
DE		 5721
5722;; Split an add that we can't do in one insn into two insns, each of which
5723;; does one 16-bit part. This is used by combine. Note that the low-order
5724;; add should be last in case the result gets used in an address.
5725
5726(define_split
5727 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5728 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5729 (match_operand:DI 2 "non_add_cint_operand" "")))]
5730 "TARGET_POWERPC64"
5731 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5732 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5733"
5734{
2bfcf297 5735 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 5736 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2bfcf297 5737 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
266eb58a 5738
2bfcf297
DB		 5739 operands[4] = GEN_INT (low);
5740 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5741 operands[3] = GEN_INT (rest);
5742 else if (! no_new_pseudos)
38886f37 5743 {
2bfcf297
DB		 5744 operands[3] = gen_reg_rtx (DImode);
5745 emit_move_insn (operands[3], operands[2]);
5746 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5747 DONE;
38886f37 5748 }
2bfcf297
DB		 5749 else
5750 FAIL;
266eb58a
DE		 5751}")
5752
5753(define_insn "one_cmpldi2"
5754 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5755 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5756 "TARGET_POWERPC64"
5757 "nor %0,%1,%1")
5758
5759(define_insn ""
9ebbca7d
GK		 5760 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5761 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
266eb58a 5762 (const_int 0)))
9ebbca7d 5763 (clobber (match_scratch:DI 2 "=r,r"))]
266eb58a 5764 "TARGET_POWERPC64"
9ebbca7d
GK		 5765 "@
5766 nor. %2,%1,%1
5767 #"
5768 [(set_attr "type" "compare")
5769 (set_attr "length" "4,8")])
5770
5771(define_split
5772 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5773 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5774 (const_int 0)))
5775 (clobber (match_scratch:DI 2 ""))]
5776 "TARGET_POWERPC64 && reload_completed"
5777 [(set (match_dup 2)
5778 (not:DI (match_dup 1)))
5779 (set (match_dup 0)
5780 (compare:CC (match_dup 2)
5781 (const_int 0)))]
5782 "")
266eb58a
DE		 5783
5784(define_insn ""
9ebbca7d
GK		 5785 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5786 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
266eb58a 5787 (const_int 0)))
9ebbca7d 5788 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a
DE		 5789 (not:DI (match_dup 1)))]
5790 "TARGET_POWERPC64"
9ebbca7d
GK		 5791 "@
5792 nor. %0,%1,%1
5793 #"
5794 [(set_attr "type" "compare")
5795 (set_attr "length" "4,8")])
5796
5797(define_split
5798 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5799 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5800 (const_int 0)))
5801 (set (match_operand:DI 0 "gpc_reg_operand" "")
5802 (not:DI (match_dup 1)))]
5803 "TARGET_POWERPC64 && reload_completed"
5804 [(set (match_dup 0)
5805 (not:DI (match_dup 1)))
5806 (set (match_dup 2)
5807 (compare:CC (match_dup 0)
5808 (const_int 0)))]
5809 "")
266eb58a
DE		 5810
5811(define_insn ""
5812 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5813 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5814 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5815 "TARGET_POWERPC64"
5816 "@
5817 subf %0,%2,%1
5818 subfic %0,%2,%1")
5819
5820(define_insn ""
9ebbca7d
GK		 5821 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5822 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5823 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
266eb58a 5824 (const_int 0)))
9ebbca7d 5825 (clobber (match_scratch:DI 3 "=r,r"))]
266eb58a 5826 "TARGET_POWERPC64"
9ebbca7d
GK		 5827 "@
5828 subf. %3,%2,%1
5829 #"
a62bfff2 5830 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 5831 (set_attr "length" "4,8")])
5832
5833(define_split
5834 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5835 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5836 (match_operand:DI 2 "gpc_reg_operand" ""))
5837 (const_int 0)))
5838 (clobber (match_scratch:DI 3 ""))]
5839 "TARGET_POWERPC64 && reload_completed"
5840 [(set (match_dup 3)
5841 (minus:DI (match_dup 1) (match_dup 2)))
5842 (set (match_dup 0)
5843 (compare:CC (match_dup 3)
5844 (const_int 0)))]
5845 "")
266eb58a
DE		 5846
5847(define_insn ""
9ebbca7d
GK		 5848 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5849 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5850 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
266eb58a 5851 (const_int 0)))
9ebbca7d 5852 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a
DE		 5853 (minus:DI (match_dup 1) (match_dup 2)))]
5854 "TARGET_POWERPC64"
9ebbca7d
GK		 5855 "@
5856 subf. %0,%2,%1
5857 #"
a62bfff2 5858 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 5859 (set_attr "length" "4,8")])
5860
5861(define_split
5862 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5863 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5864 (match_operand:DI 2 "gpc_reg_operand" ""))
5865 (const_int 0)))
5866 (set (match_operand:DI 0 "gpc_reg_operand" "")
5867 (minus:DI (match_dup 1) (match_dup 2)))]
5868 "TARGET_POWERPC64 && reload_completed"
5869 [(set (match_dup 0)
5870 (minus:DI (match_dup 1) (match_dup 2)))
5871 (set (match_dup 3)
5872 (compare:CC (match_dup 0)
5873 (const_int 0)))]
5874 "")
266eb58a
DE		 5875
5876(define_expand "subdi3"
5877 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5878 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
2bfcf297 5879 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
266eb58a
DE		 5880 ""
5881 "
5882{
5883 if (GET_CODE (operands[2]) == CONST_INT)
5884 {
5885 emit_insn (gen_adddi3 (operands[0], operands[1],
5886 negate_rtx (DImode, operands[2])));
5887 DONE;
5888 }
5889}")
5890
ea112fc4 5891(define_insn_and_split "absdi2"
266eb58a 5892 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 5893 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
266eb58a
DE		 5894 (clobber (match_scratch:DI 2 "=&r,&r"))]
5895 "TARGET_POWERPC64"
ea112fc4
DE		 5896 "#"
5897 "&& reload_completed"
a260abc9 5898 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 5899 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
a238cd8b 5900 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
266eb58a
DE		 5901 "")
5902
ea112fc4 5903(define_insn_and_split "*nabsdi2"
266eb58a 5904 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 5905 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
266eb58a
DE		 5906 (clobber (match_scratch:DI 2 "=&r,&r"))]
5907 "TARGET_POWERPC64"
ea112fc4
DE		 5908 "#"
5909 "&& reload_completed"
a260abc9 5910 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 5911 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
19ba8161 5912 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
266eb58a
DE		 5913 "")
5914
5915(define_expand "negdi2"
5916 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5917 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
5918 ""
5919 "")
5920
5921(define_insn ""
5922 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5923 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5924 "TARGET_POWERPC64"
5925 "neg %0,%1")
5926
5927(define_insn ""
9ebbca7d
GK		 5928 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5929 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
266eb58a 5930 (const_int 0)))
9ebbca7d 5931 (clobber (match_scratch:DI 2 "=r,r"))]
29ae5b89 5932 "TARGET_POWERPC64"
9ebbca7d
GK		 5933 "@
5934 neg. %2,%1
5935 #"
a62bfff2 5936 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 5937 (set_attr "length" "4,8")])
5938
5939(define_split
5940 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5941 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5942 (const_int 0)))
5943 (clobber (match_scratch:DI 2 ""))]
5944 "TARGET_POWERPC64 && reload_completed"
5945 [(set (match_dup 2)
5946 (neg:DI (match_dup 1)))
5947 (set (match_dup 0)
5948 (compare:CC (match_dup 2)
5949 (const_int 0)))]
5950 "")
815cdc52 5951
29ae5b89 5952(define_insn ""
9ebbca7d
GK		 5953 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5954 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
815cdc52 5955 (const_int 0)))
9ebbca7d 5956 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
815cdc52 5957 (neg:DI (match_dup 1)))]
29ae5b89 5958 "TARGET_POWERPC64"
9ebbca7d
GK		 5959 "@
5960 neg. %0,%1
5961 #"
a62bfff2 5962 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 5963 (set_attr "length" "4,8")])
5964
5965(define_split
5966 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5967 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5968 (const_int 0)))
5969 (set (match_operand:DI 0 "gpc_reg_operand" "")
5970 (neg:DI (match_dup 1)))]
5971 "TARGET_POWERPC64 && reload_completed"
5972 [(set (match_dup 0)
5973 (neg:DI (match_dup 1)))
5974 (set (match_dup 2)
5975 (compare:CC (match_dup 0)
5976 (const_int 0)))]
5977 "")
266eb58a 5978
1b1edcfa
DE		 5979(define_insn "clzdi2"
5980 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5981 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5982 "TARGET_POWERPC64"
5983 "cntlzd %0,%1")
5984
5985(define_expand "ctzdi2"
4977bab6 5986 [(set (match_dup 2)
1b1edcfa 5987 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
4977bab6 5988 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
1b1edcfa
DE		 5989 (match_dup 2)))
5990 (clobber (scratch:CC))])
d865b122 5991 (set (match_dup 4) (clz:DI (match_dup 3)))
4977bab6 5992 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
1b1edcfa 5993 (minus:DI (const_int 63) (match_dup 4)))]
266eb58a 5994 "TARGET_POWERPC64"
4977bab6
ZW		 5995 {
5996 operands[2] = gen_reg_rtx (DImode);
5997 operands[3] = gen_reg_rtx (DImode);
5998 operands[4] = gen_reg_rtx (DImode);
5999 })
6000
1b1edcfa
DE		 6001(define_expand "ffsdi2"
6002 [(set (match_dup 2)
6003 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6004 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6005 (match_dup 2)))
6006 (clobber (scratch:CC))])
6007 (set (match_dup 4) (clz:DI (match_dup 3)))
6008 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6009 (minus:DI (const_int 64) (match_dup 4)))]
4977bab6 6010 "TARGET_POWERPC64"
1b1edcfa
DE		 6011 {
6012 operands[2] = gen_reg_rtx (DImode);
6013 operands[3] = gen_reg_rtx (DImode);
6014 operands[4] = gen_reg_rtx (DImode);
6015 })
266eb58a
DE		 6016
6017(define_insn "muldi3"
6018 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6019 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6020 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6021 "TARGET_POWERPC64"
6022 "mulld %0,%1,%2"
3cb999d8 6023 [(set_attr "type" "lmul")])
266eb58a
DE		 6024
6025(define_insn "smuldi3_highpart"
6026 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6027 (truncate:DI
6028 (lshiftrt:TI (mult:TI (sign_extend:TI
6029 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6030 (sign_extend:TI
6031 (match_operand:DI 2 "gpc_reg_operand" "r")))
6032 (const_int 64))))]
6033 "TARGET_POWERPC64"
6034 "mulhd %0,%1,%2"
3cb999d8 6035 [(set_attr "type" "lmul")])
266eb58a
DE		 6036
6037(define_insn "umuldi3_highpart"
6038 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6039 (truncate:DI
6040 (lshiftrt:TI (mult:TI (zero_extend:TI
6041 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6042 (zero_extend:TI
6043 (match_operand:DI 2 "gpc_reg_operand" "r")))
6044 (const_int 64))))]
6045 "TARGET_POWERPC64"
6046 "mulhdu %0,%1,%2"
3cb999d8 6047 [(set_attr "type" "lmul")])
266eb58a
DE		 6048
6049(define_expand "divdi3"
6050 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6051 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6052 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6053 "TARGET_POWERPC64"
6054 "
6055{
6056 if (GET_CODE (operands[2]) == CONST_INT
2bfcf297 6057 && INTVAL (operands[2]) > 0
266eb58a
DE		 6058 && exact_log2 (INTVAL (operands[2])) >= 0)
6059 ;
6060 else
6061 operands[2] = force_reg (DImode, operands[2]);
6062}")
6063
6064(define_expand "moddi3"
6065 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6066 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6067 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6068 "TARGET_POWERPC64"
6069 "
6070{
2bfcf297 6071 int i;
266eb58a
DE		 6072 rtx temp1;
6073 rtx temp2;
6074
2bfcf297
DB		 6075 if (GET_CODE (operands[2]) != CONST_INT
6076 || INTVAL (operands[2]) <= 0
6077 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
266eb58a
DE		 6078 FAIL;
6079
6080 temp1 = gen_reg_rtx (DImode);
6081 temp2 = gen_reg_rtx (DImode);
6082
6083 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6084 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6085 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6086 DONE;
6087}")
6088
6089(define_insn ""
6090 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6091 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2bfcf297
DB		 6092 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6093 "TARGET_POWERPC64"
266eb58a
DE		 6094 "sradi %0,%1,%p2\;addze %0,%0"
6095 [(set_attr "length" "8")])
6096
6097(define_insn ""
9ebbca7d
GK		 6098 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6099 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
2bfcf297 6100 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
266eb58a 6101 (const_int 0)))
9ebbca7d 6102 (clobber (match_scratch:DI 3 "=r,r"))]
2bfcf297 6103 "TARGET_POWERPC64"
9ebbca7d
GK		 6104 "@
6105 sradi %3,%1,%p2\;addze. %3,%3
6106 #"
266eb58a 6107 [(set_attr "type" "compare")
9ebbca7d
GK		 6108 (set_attr "length" "8,12")])
6109
6110(define_split
6111 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6112 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
2bfcf297 6113 (match_operand:DI 2 "exact_log2_cint_operand" ""))
9ebbca7d
GK		 6114 (const_int 0)))
6115 (clobber (match_scratch:DI 3 ""))]
2bfcf297 6116 "TARGET_POWERPC64 && reload_completed"
9ebbca7d
GK		 6117 [(set (match_dup 3)
6118 (div:DI (match_dup 1) (match_dup 2)))
6119 (set (match_dup 0)
6120 (compare:CC (match_dup 3)
6121 (const_int 0)))]
6122 "")
266eb58a
DE		 6123
6124(define_insn ""
9ebbca7d
GK		 6125 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6126 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
2bfcf297 6127 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
266eb58a 6128 (const_int 0)))
9ebbca7d 6129 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 6130 (div:DI (match_dup 1) (match_dup 2)))]
2bfcf297 6131 "TARGET_POWERPC64"
9ebbca7d
GK		 6132 "@
6133 sradi %0,%1,%p2\;addze. %0,%0
6134 #"
266eb58a 6135 [(set_attr "type" "compare")
9ebbca7d 6136 (set_attr "length" "8,12")])
266eb58a 6137
9ebbca7d
GK		 6138(define_split
6139 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6140 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
2bfcf297 6141 (match_operand:DI 2 "exact_log2_cint_operand" ""))
9ebbca7d
GK		 6142 (const_int 0)))
6143 (set (match_operand:DI 0 "gpc_reg_operand" "")
6144 (div:DI (match_dup 1) (match_dup 2)))]
2bfcf297 6145 "TARGET_POWERPC64 && reload_completed"
9ebbca7d
GK		 6146 [(set (match_dup 0)
6147 (div:DI (match_dup 1) (match_dup 2)))
6148 (set (match_dup 3)
6149 (compare:CC (match_dup 0)
6150 (const_int 0)))]
6151 "")
6152
6153(define_insn ""
6154 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
266eb58a 6155 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a260abc9 6156 (match_operand:DI 2 "gpc_reg_operand" "r")))]
266eb58a
DE		 6157 "TARGET_POWERPC64"
6158 "divd %0,%1,%2"
3cb999d8 6159 [(set_attr "type" "ldiv")])
266eb58a
DE		 6160
6161(define_insn "udivdi3"
6162 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6163 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6164 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6165 "TARGET_POWERPC64"
6166 "divdu %0,%1,%2"
3cb999d8 6167 [(set_attr "type" "ldiv")])
266eb58a
DE		 6168
6169(define_insn "rotldi3"
6170 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6171 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6172 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6173 "TARGET_POWERPC64"
a66078ee 6174 "rld%I2cl %0,%1,%H2,0")
266eb58a 6175
a260abc9 6176(define_insn "*rotldi3_internal2"
9ebbca7d
GK		 6177 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6178 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6179 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6180 (const_int 0)))
9ebbca7d 6181 (clobber (match_scratch:DI 3 "=r,r"))]
266eb58a 6182 "TARGET_POWERPC64"
9ebbca7d
GK		 6183 "@
6184 rld%I2cl. %3,%1,%H2,0
6185 #"
6186 [(set_attr "type" "delayed_compare")
6187 (set_attr "length" "4,8")])
6188
6189(define_split
6190 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6191 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6192 (match_operand:DI 2 "reg_or_cint_operand" ""))
6193 (const_int 0)))
6194 (clobber (match_scratch:DI 3 ""))]
6195 "TARGET_POWERPC64 && reload_completed"
6196 [(set (match_dup 3)
6197 (rotate:DI (match_dup 1) (match_dup 2)))
6198 (set (match_dup 0)
6199 (compare:CC (match_dup 3)
6200 (const_int 0)))]
6201 "")
266eb58a 6202
a260abc9 6203(define_insn "*rotldi3_internal3"
9ebbca7d
GK		 6204 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6205 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6206 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6207 (const_int 0)))
9ebbca7d 6208 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a
DE		 6209 (rotate:DI (match_dup 1) (match_dup 2)))]
6210 "TARGET_POWERPC64"
9ebbca7d
GK		 6211 "@
6212 rld%I2cl. %0,%1,%H2,0
6213 #"
6214 [(set_attr "type" "delayed_compare")
6215 (set_attr "length" "4,8")])
6216
6217(define_split
6218 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6219 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6220 (match_operand:DI 2 "reg_or_cint_operand" ""))
6221 (const_int 0)))
6222 (set (match_operand:DI 0 "gpc_reg_operand" "")
6223 (rotate:DI (match_dup 1) (match_dup 2)))]
6224 "TARGET_POWERPC64 && reload_completed"
6225 [(set (match_dup 0)
6226 (rotate:DI (match_dup 1) (match_dup 2)))
6227 (set (match_dup 3)
6228 (compare:CC (match_dup 0)
6229 (const_int 0)))]
6230 "")
266eb58a 6231
a260abc9
DE		 6232(define_insn "*rotldi3_internal4"
6233 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6234 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6235 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
ce71f754 6236 (match_operand:DI 3 "mask64_operand" "n")))]
a260abc9
DE		 6237 "TARGET_POWERPC64"
6238 "rld%I2c%B3 %0,%1,%H2,%S3")
6239
6240(define_insn "*rotldi3_internal5"
9ebbca7d 6241 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9 6242 (compare:CC (and:DI
9ebbca7d
GK		 6243 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6244 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
ce71f754 6245 (match_operand:DI 3 "mask64_operand" "n,n"))
a260abc9 6246 (const_int 0)))
9ebbca7d 6247 (clobber (match_scratch:DI 4 "=r,r"))]
a260abc9 6248 "TARGET_POWERPC64"
9ebbca7d
GK		 6249 "@
6250 rld%I2c%B3. %4,%1,%H2,%S3
6251 #"
6252 [(set_attr "type" "delayed_compare")
6253 (set_attr "length" "4,8")])
6254
6255(define_split
6256 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6257 (compare:CC (and:DI
6258 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6259 (match_operand:DI 2 "reg_or_cint_operand" ""))
6260 (match_operand:DI 3 "mask64_operand" ""))
6261 (const_int 0)))
6262 (clobber (match_scratch:DI 4 ""))]
6263 "TARGET_POWERPC64 && reload_completed"
6264 [(set (match_dup 4)
6265 (and:DI (rotate:DI (match_dup 1)
6266 (match_dup 2))
6267 (match_dup 3)))
6268 (set (match_dup 0)
6269 (compare:CC (match_dup 4)
6270 (const_int 0)))]
6271 "")
a260abc9
DE		 6272
6273(define_insn "*rotldi3_internal6"
9ebbca7d 6274 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9 6275 (compare:CC (and:DI
9ebbca7d
GK		 6276 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6277 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
ce71f754 6278 (match_operand:DI 3 "mask64_operand" "n,n"))
a260abc9 6279 (const_int 0)))
9ebbca7d 6280 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6281 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6282 "TARGET_POWERPC64"
9ebbca7d
GK		 6283 "@
6284 rld%I2c%B3. %0,%1,%H2,%S3
6285 #"
6286 [(set_attr "type" "delayed_compare")
6287 (set_attr "length" "4,8")])
6288
6289(define_split
6290 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6291 (compare:CC (and:DI
6292 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6293 (match_operand:DI 2 "reg_or_cint_operand" ""))
6294 (match_operand:DI 3 "mask64_operand" ""))
6295 (const_int 0)))
6296 (set (match_operand:DI 0 "gpc_reg_operand" "")
6297 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6298 "TARGET_POWERPC64 && reload_completed"
6299 [(set (match_dup 0)
6300 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6301 (set (match_dup 4)
6302 (compare:CC (match_dup 0)
6303 (const_int 0)))]
6304 "")
a260abc9
DE		 6305
6306(define_insn "*rotldi3_internal7"
6307 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6308 (zero_extend:DI
6309 (subreg:QI
6310 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6311 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6312 "TARGET_POWERPC64"
6313 "rld%I2cl %0,%1,%H2,56")
6314
6315(define_insn "*rotldi3_internal8"
9ebbca7d 6316 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6317 (compare:CC (zero_extend:DI
6318 (subreg:QI
9ebbca7d
GK		 6319 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6320 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6321 (const_int 0)))
9ebbca7d 6322 (clobber (match_scratch:DI 3 "=r,r"))]
a260abc9 6323 "TARGET_POWERPC64"
9ebbca7d
GK		 6324 "@
6325 rld%I2cl. %3,%1,%H2,56
6326 #"
6327 [(set_attr "type" "delayed_compare")
6328 (set_attr "length" "4,8")])
6329
6330(define_split
6331 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6332 (compare:CC (zero_extend:DI
6333 (subreg:QI
6334 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6335 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6336 (const_int 0)))
6337 (clobber (match_scratch:DI 3 ""))]
6338 "TARGET_POWERPC64 && reload_completed"
6339 [(set (match_dup 3)
6340 (zero_extend:DI (subreg:QI
6341 (rotate:DI (match_dup 1)
6342 (match_dup 2)) 0)))
6343 (set (match_dup 0)
6344 (compare:CC (match_dup 3)
6345 (const_int 0)))]
6346 "")
a260abc9
DE		 6347
6348(define_insn "*rotldi3_internal9"
9ebbca7d 6349 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6350 (compare:CC (zero_extend:DI
6351 (subreg:QI
9ebbca7d
GK		 6352 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6353 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6354 (const_int 0)))
9ebbca7d 6355 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6356 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6357 "TARGET_POWERPC64"
9ebbca7d
GK		 6358 "@
6359 rld%I2cl. %0,%1,%H2,56
6360 #"
6361 [(set_attr "type" "delayed_compare")
6362 (set_attr "length" "4,8")])
6363
6364(define_split
6365 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6366 (compare:CC (zero_extend:DI
6367 (subreg:QI
6368 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6369 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6370 (const_int 0)))
6371 (set (match_operand:DI 0 "gpc_reg_operand" "")
6372 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6373 "TARGET_POWERPC64 && reload_completed"
6374 [(set (match_dup 0)
6375 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6376 (set (match_dup 3)
6377 (compare:CC (match_dup 0)
6378 (const_int 0)))]
6379 "")
a260abc9
DE		 6380
6381(define_insn "*rotldi3_internal10"
6382 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6383 (zero_extend:DI
6384 (subreg:HI
6385 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6386 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6387 "TARGET_POWERPC64"
6388 "rld%I2cl %0,%1,%H2,48")
6389
6390(define_insn "*rotldi3_internal11"
9ebbca7d 6391 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6392 (compare:CC (zero_extend:DI
6393 (subreg:HI
9ebbca7d
GK		 6394 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6395 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6396 (const_int 0)))
9ebbca7d 6397 (clobber (match_scratch:DI 3 "=r,r"))]
a260abc9 6398 "TARGET_POWERPC64"
9ebbca7d
GK		 6399 "@
6400 rld%I2cl. %3,%1,%H2,48
6401 #"
6402 [(set_attr "type" "delayed_compare")
6403 (set_attr "length" "4,8")])
6404
6405(define_split
6406 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6407 (compare:CC (zero_extend:DI
6408 (subreg:HI
6409 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6410 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6411 (const_int 0)))
6412 (clobber (match_scratch:DI 3 ""))]
6413 "TARGET_POWERPC64 && reload_completed"
6414 [(set (match_dup 3)
6415 (zero_extend:DI (subreg:HI
6416 (rotate:DI (match_dup 1)
6417 (match_dup 2)) 0)))
6418 (set (match_dup 0)
6419 (compare:CC (match_dup 3)
6420 (const_int 0)))]
6421 "")
a260abc9
DE		 6422
6423(define_insn "*rotldi3_internal12"
9ebbca7d 6424 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6425 (compare:CC (zero_extend:DI
6426 (subreg:HI
9ebbca7d
GK		 6427 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6428 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6429 (const_int 0)))
9ebbca7d 6430 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6431 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6432 "TARGET_POWERPC64"
9ebbca7d
GK		 6433 "@
6434 rld%I2cl. %0,%1,%H2,48
6435 #"
6436 [(set_attr "type" "delayed_compare")
6437 (set_attr "length" "4,8")])
6438
6439(define_split
6440 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6441 (compare:CC (zero_extend:DI
6442 (subreg:HI
6443 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6444 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6445 (const_int 0)))
6446 (set (match_operand:DI 0 "gpc_reg_operand" "")
6447 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6448 "TARGET_POWERPC64 && reload_completed"
6449 [(set (match_dup 0)
6450 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6451 (set (match_dup 3)
6452 (compare:CC (match_dup 0)
6453 (const_int 0)))]
6454 "")
a260abc9
DE		 6455
6456(define_insn "*rotldi3_internal13"
6457 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6458 (zero_extend:DI
6459 (subreg:SI
6460 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6461 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6462 "TARGET_POWERPC64"
6463 "rld%I2cl %0,%1,%H2,32")
6464
6465(define_insn "*rotldi3_internal14"
9ebbca7d 6466 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6467 (compare:CC (zero_extend:DI
6468 (subreg:SI
9ebbca7d
GK		 6469 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6470 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6471 (const_int 0)))
9ebbca7d 6472 (clobber (match_scratch:DI 3 "=r,r"))]
a260abc9 6473 "TARGET_POWERPC64"
9ebbca7d
GK		 6474 "@
6475 rld%I2cl. %3,%1,%H2,32
6476 #"
6477 [(set_attr "type" "delayed_compare")
6478 (set_attr "length" "4,8")])
6479
6480(define_split
6481 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6482 (compare:CC (zero_extend:DI
6483 (subreg:SI
6484 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6485 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6486 (const_int 0)))
6487 (clobber (match_scratch:DI 3 ""))]
6488 "TARGET_POWERPC64 && reload_completed"
6489 [(set (match_dup 3)
6490 (zero_extend:DI (subreg:SI
6491 (rotate:DI (match_dup 1)
6492 (match_dup 2)) 0)))
6493 (set (match_dup 0)
6494 (compare:CC (match_dup 3)
6495 (const_int 0)))]
6496 "")
a260abc9
DE		 6497
6498(define_insn "*rotldi3_internal15"
9ebbca7d 6499 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6500 (compare:CC (zero_extend:DI
6501 (subreg:SI
9ebbca7d
GK		 6502 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6503 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6504 (const_int 0)))
9ebbca7d 6505 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6506 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6507 "TARGET_POWERPC64"
9ebbca7d
GK		 6508 "@
6509 rld%I2cl. %0,%1,%H2,32
6510 #"
6511 [(set_attr "type" "delayed_compare")
6512 (set_attr "length" "4,8")])
6513
6514(define_split
6515 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6516 (compare:CC (zero_extend:DI
6517 (subreg:SI
6518 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6519 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6520 (const_int 0)))
6521 (set (match_operand:DI 0 "gpc_reg_operand" "")
6522 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6523 "TARGET_POWERPC64 && reload_completed"
6524 [(set (match_dup 0)
6525 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6526 (set (match_dup 3)
6527 (compare:CC (match_dup 0)
6528 (const_int 0)))]
6529 "")
a260abc9 6530
266eb58a
DE		 6531(define_expand "ashldi3"
6532 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6533 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6534 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6535 "TARGET_POWERPC64 || TARGET_POWER"
6536 "
6537{
6538 if (TARGET_POWERPC64)
6539 ;
6540 else if (TARGET_POWER)
6541 {
6542 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6543 DONE;
6544 }
6545 else
6546 FAIL;
6547}")
6548
e2c953b6 6549(define_insn "*ashldi3_internal1"
266eb58a
DE		 6550 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6551 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6552 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6553 "TARGET_POWERPC64"
a66078ee 6554 "sld%I2 %0,%1,%H2"
266eb58a
DE		 6555 [(set_attr "length" "8")])
6556
e2c953b6 6557(define_insn "*ashldi3_internal2"
9ebbca7d
GK		 6558 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6559 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6560 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6561 (const_int 0)))
9ebbca7d 6562 (clobber (match_scratch:DI 3 "=r,r"))]
266eb58a 6563 "TARGET_POWERPC64"
9ebbca7d
GK		 6564 "@
6565 sld%I2. %3,%1,%H2
6566 #"
6567 [(set_attr "type" "delayed_compare")
6568 (set_attr "length" "4,8")])
29ae5b89 6569
9ebbca7d
GK		 6570(define_split
6571 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6572 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6573 (match_operand:SI 2 "reg_or_cint_operand" ""))
6574 (const_int 0)))
6575 (clobber (match_scratch:DI 3 ""))]
6576 "TARGET_POWERPC64 && reload_completed"
6577 [(set (match_dup 3)
6578 (ashift:DI (match_dup 1) (match_dup 2)))
6579 (set (match_dup 0)
6580 (compare:CC (match_dup 3)
6581 (const_int 0)))]
6582 "")
6583
e2c953b6 6584(define_insn "*ashldi3_internal3"
9ebbca7d
GK		 6585 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6586 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6587 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6588 (const_int 0)))
9ebbca7d 6589 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a
DE		 6590 (ashift:DI (match_dup 1) (match_dup 2)))]
6591 "TARGET_POWERPC64"
9ebbca7d
GK		 6592 "@
6593 sld%I2. %0,%1,%H2
6594 #"
6595 [(set_attr "type" "delayed_compare")
6596 (set_attr "length" "4,8")])
6597
6598(define_split
6599 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6600 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6601 (match_operand:SI 2 "reg_or_cint_operand" ""))
6602 (const_int 0)))
6603 (set (match_operand:DI 0 "gpc_reg_operand" "")
6604 (ashift:DI (match_dup 1) (match_dup 2)))]
6605 "TARGET_POWERPC64 && reload_completed"
6606 [(set (match_dup 0)
6607 (ashift:DI (match_dup 1) (match_dup 2)))
6608 (set (match_dup 3)
6609 (compare:CC (match_dup 0)
6610 (const_int 0)))]
6611 "")
266eb58a 6612
e2c953b6 6613(define_insn "*ashldi3_internal4"
3cb999d8
DE		 6614 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6615 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6616 (match_operand:SI 2 "const_int_operand" "i"))
c5059423
AM		 6617 (match_operand:DI 3 "const_int_operand" "n")))]
6618 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
e2c953b6 6619 "rldic %0,%1,%H2,%W3")
3cb999d8 6620
e2c953b6 6621(define_insn "ashldi3_internal5"
9ebbca7d 6622 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3cb999d8 6623 (compare:CC
9ebbca7d
GK		 6624 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6625 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 6626 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 6627 (const_int 0)))
9ebbca7d 6628 (clobber (match_scratch:DI 4 "=r,r"))]
c5059423 6629 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 6630 "@
e2c953b6 6631 rldic. %4,%1,%H2,%W3
9ebbca7d
GK		 6632 #"
6633 [(set_attr "type" "delayed_compare")
6634 (set_attr "length" "4,8")])
6635
6636(define_split
6637 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6638 (compare:CC
6639 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6640 (match_operand:SI 2 "const_int_operand" ""))
c5059423 6641 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 6642 (const_int 0)))
6643 (clobber (match_scratch:DI 4 ""))]
c5059423
AM		 6644 "TARGET_POWERPC64 && reload_completed
6645 && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 6646 [(set (match_dup 4)
6647 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
e2c953b6 6648 (match_dup 3)))
9ebbca7d
GK		 6649 (set (match_dup 0)
6650 (compare:CC (match_dup 4)
6651 (const_int 0)))]
6652 "")
3cb999d8 6653
e2c953b6 6654(define_insn "*ashldi3_internal6"
9ebbca7d 6655 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3cb999d8 6656 (compare:CC
9ebbca7d
GK		 6657 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6658 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 6659 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 6660 (const_int 0)))
9ebbca7d 6661 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3cb999d8 6662 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
c5059423 6663 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 6664 "@
e2c953b6 6665 rldic. %0,%1,%H2,%W3
9ebbca7d
GK		 6666 #"
6667 [(set_attr "type" "delayed_compare")
6668 (set_attr "length" "4,8")])
6669
6670(define_split
6671 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6672 (compare:CC
6673 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6674 (match_operand:SI 2 "const_int_operand" ""))
c5059423 6675 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 6676 (const_int 0)))
6677 (set (match_operand:DI 0 "gpc_reg_operand" "")
6678 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
c5059423
AM		 6679 "TARGET_POWERPC64 && reload_completed
6680 && includes_rldic_lshift_p (operands[2], operands[3])"
6681 [(set (match_dup 0)
6682 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6683 (match_dup 3)))
6684 (set (match_dup 4)
6685 (compare:CC (match_dup 0)
6686 (const_int 0)))]
6687 "")
6688
6689(define_insn "*ashldi3_internal7"
6690 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6691 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6692 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 6693 (match_operand:DI 3 "mask64_operand" "n")))]
c5059423
AM		 6694 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6695 "rldicr %0,%1,%H2,%S3")
6696
6697(define_insn "ashldi3_internal8"
6698 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6699 (compare:CC
6700 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6701 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 6702 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 6703 (const_int 0)))
6704 (clobber (match_scratch:DI 4 "=r,r"))]
6705 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6706 "@
6707 rldicr. %4,%1,%H2,%S3
6708 #"
6709 [(set_attr "type" "delayed_compare")
6710 (set_attr "length" "4,8")])
6711
6712(define_split
6713 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6714 (compare:CC
6715 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6716 (match_operand:SI 2 "const_int_operand" ""))
6717 (match_operand:DI 3 "mask64_operand" ""))
6718 (const_int 0)))
6719 (clobber (match_scratch:DI 4 ""))]
6720 "TARGET_POWERPC64 && reload_completed
6721 && includes_rldicr_lshift_p (operands[2], operands[3])"
6722 [(set (match_dup 4)
6723 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6724 (match_dup 3)))
6725 (set (match_dup 0)
6726 (compare:CC (match_dup 4)
6727 (const_int 0)))]
6728 "")
6729
6730(define_insn "*ashldi3_internal9"
6731 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6732 (compare:CC
6733 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6734 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 6735 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 6736 (const_int 0)))
6737 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6738 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6739 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6740 "@
6741 rldicr. %0,%1,%H2,%S3
6742 #"
6743 [(set_attr "type" "delayed_compare")
6744 (set_attr "length" "4,8")])
6745
6746(define_split
6747 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6748 (compare:CC
6749 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6750 (match_operand:SI 2 "const_int_operand" ""))
6751 (match_operand:DI 3 "mask64_operand" ""))
6752 (const_int 0)))
6753 (set (match_operand:DI 0 "gpc_reg_operand" "")
6754 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6755 "TARGET_POWERPC64 && reload_completed
6756 && includes_rldicr_lshift_p (operands[2], operands[3])"
9ebbca7d 6757 [(set (match_dup 0)
e2c953b6
DE		 6758 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6759 (match_dup 3)))
9ebbca7d
GK		 6760 (set (match_dup 4)
6761 (compare:CC (match_dup 0)
6762 (const_int 0)))]
6763 "")
6764
6765(define_expand "lshrdi3"
266eb58a
DE		 6766 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6767 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6768 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6769 "TARGET_POWERPC64 || TARGET_POWER"
6770 "
6771{
6772 if (TARGET_POWERPC64)
6773 ;
6774 else if (TARGET_POWER)
6775 {
6776 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6777 DONE;
6778 }
6779 else
6780 FAIL;
6781}")
6782
e2c953b6 6783(define_insn "*lshrdi3_internal1"
266eb58a
DE		 6784 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6785 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6786 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6787 "TARGET_POWERPC64"
a66078ee 6788 "srd%I2 %0,%1,%H2")
266eb58a 6789
e2c953b6 6790(define_insn "*lshrdi3_internal2"
9ebbca7d
GK		 6791 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6792 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6793 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
29ae5b89 6794 (const_int 0)))
9ebbca7d 6795 (clobber (match_scratch:DI 3 "=r,r"))]
29ae5b89 6796 "TARGET_POWERPC64"
9ebbca7d
GK		 6797 "@
6798 srd%I2. %3,%1,%H2
6799 #"
6800 [(set_attr "type" "delayed_compare")
6801 (set_attr "length" "4,8")])
6802
6803(define_split
6804 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6805 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6806 (match_operand:SI 2 "reg_or_cint_operand" ""))
6807 (const_int 0)))
6808 (clobber (match_scratch:DI 3 ""))]
6809 "TARGET_POWERPC64 && reload_completed"
6810 [(set (match_dup 3)
6811 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6812 (set (match_dup 0)
6813 (compare:CC (match_dup 3)
6814 (const_int 0)))]
6815 "")
266eb58a 6816
e2c953b6 6817(define_insn "*lshrdi3_internal3"
9ebbca7d
GK		 6818 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6819 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6820 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6821 (const_int 0)))
9ebbca7d 6822 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
29ae5b89
JL		 6823 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6824 "TARGET_POWERPC64"
9ebbca7d
GK		 6825 "@
6826 srd%I2. %0,%1,%H2
6827 #"
6828 [(set_attr "type" "delayed_compare")
6829 (set_attr "length" "4,8")])
6830
6831(define_split
6832 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6833 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6834 (match_operand:SI 2 "reg_or_cint_operand" ""))
6835 (const_int 0)))
6836 (set (match_operand:DI 0 "gpc_reg_operand" "")
6837 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6838 "TARGET_POWERPC64 && reload_completed"
6839 [(set (match_dup 0)
6840 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6841 (set (match_dup 3)
6842 (compare:CC (match_dup 0)
6843 (const_int 0)))]
6844 "")
266eb58a
DE		 6845
6846(define_expand "ashrdi3"
6847 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6848 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6849 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4aa74a4f 6850 ""
266eb58a
DE		 6851 "
6852{
6853 if (TARGET_POWERPC64)
6854 ;
6855 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6856 {
6857 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6858 DONE;
6859 }
4aa74a4f
FS		 6860 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT)
6861 {
6862 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6863 DONE;
6864 }
266eb58a
DE		 6865 else
6866 FAIL;
6867}")
6868
e2c953b6 6869(define_insn "*ashrdi3_internal1"
266eb58a
DE		 6870 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6871 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6872 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6873 "TARGET_POWERPC64"
375490e0 6874 "srad%I2 %0,%1,%H2")
266eb58a 6875
e2c953b6 6876(define_insn "*ashrdi3_internal2"
9ebbca7d
GK		 6877 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6878 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6879 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6880 (const_int 0)))
9ebbca7d 6881 (clobber (match_scratch:DI 3 "=r,r"))]
266eb58a 6882 "TARGET_POWERPC64"
9ebbca7d
GK		 6883 "@
6884 srad%I2. %3,%1,%H2
6885 #"
6886 [(set_attr "type" "delayed_compare")
6887 (set_attr "length" "4,8")])
6888
6889(define_split
6890 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6891 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6892 (match_operand:SI 2 "reg_or_cint_operand" ""))
6893 (const_int 0)))
6894 (clobber (match_scratch:DI 3 ""))]
6895 "TARGET_POWERPC64 && reload_completed"
6896 [(set (match_dup 3)
6897 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6898 (set (match_dup 0)
6899 (compare:CC (match_dup 3)
6900 (const_int 0)))]
6901 "")
266eb58a 6902
e2c953b6 6903(define_insn "*ashrdi3_internal3"
9ebbca7d
GK		 6904 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6905 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6906 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6907 (const_int 0)))
9ebbca7d 6908 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a
DE		 6909 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6910 "TARGET_POWERPC64"
9ebbca7d
GK		 6911 "@
6912 srad%I2. %0,%1,%H2
6913 #"
6914 [(set_attr "type" "delayed_compare")
6915 (set_attr "length" "4,8")])
6916
6917(define_split
6918 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6919 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6920 (match_operand:SI 2 "reg_or_cint_operand" ""))
6921 (const_int 0)))
6922 (set (match_operand:DI 0 "gpc_reg_operand" "")
6923 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6924 "TARGET_POWERPC64 && reload_completed"
6925 [(set (match_dup 0)
6926 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6927 (set (match_dup 3)
6928 (compare:CC (match_dup 0)
6929 (const_int 0)))]
6930 "")
815cdc52 6931
29ae5b89 6932(define_insn "anddi3"
0ba1b2ff
AM		 6933 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
6934 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
6935 (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t")))
6936 (clobber (match_scratch:CC 3 "=X,X,x,x,X"))]
6ffc8580 6937 "TARGET_POWERPC64"
266eb58a
DE		 6938 "@
6939 and %0,%1,%2
29ae5b89
JL		 6940 rldic%B2 %0,%1,0,%S2
6941 andi. %0,%1,%b2
0ba1b2ff
AM		 6942 andis. %0,%1,%u2
6943 #"
6944 [(set_attr "length" "4,4,4,4,8")])
6945
6946(define_split
6947 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6948 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6949 (match_operand:DI 2 "mask64_2_operand" "")))
6950 (clobber (match_scratch:CC 3 ""))]
6951 "TARGET_POWERPC64
6952 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
6953 && !mask64_operand (operands[2], DImode)"
6954 [(set (match_dup 0)
6955 (and:DI (rotate:DI (match_dup 1)
6956 (match_dup 4))
6957 (match_dup 5)))
6958 (set (match_dup 0)
6959 (and:DI (rotate:DI (match_dup 0)
6960 (match_dup 6))
6961 (match_dup 7)))]
6962 "
6963{
6964 build_mask64_2_operands (operands[2], &operands[4]);
6965}")
266eb58a 6966
a260abc9 6967(define_insn "*anddi3_internal2"
0ba1b2ff
AM		 6968 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
6969 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
6970 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
266eb58a 6971 (const_int 0)))
0ba1b2ff
AM		 6972 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
6973 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
6ffc8580 6974 "TARGET_POWERPC64"
266eb58a
DE		 6975 "@
6976 and. %3,%1,%2
6c873122 6977 rldic%B2. %3,%1,0,%S2
6ffc8580
MM		 6978 andi. %3,%1,%b2
6979 andis. %3,%1,%u2
9ebbca7d
GK		 6980 #
6981 #
6982 #
0ba1b2ff
AM		 6983 #
6984 #
9ebbca7d 6985 #"
0ba1b2ff
AM		 6986 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
6987 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
9ebbca7d
GK		 6988
6989(define_split
6990 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6991 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6992 (match_operand:DI 2 "and64_operand" ""))
6993 (const_int 0)))
6994 (clobber (match_scratch:DI 3 ""))
6995 (clobber (match_scratch:CC 4 ""))]
6996 "TARGET_POWERPC64 && reload_completed"
6997 [(parallel [(set (match_dup 3)
6998 (and:DI (match_dup 1)
6999 (match_dup 2)))
7000 (clobber (match_dup 4))])
7001 (set (match_dup 0)
7002 (compare:CC (match_dup 3)
7003 (const_int 0)))]
7004 "")
266eb58a 7005
0ba1b2ff
AM		 7006(define_split
7007 [(set (match_operand:CC 0 "cc_reg_operand" "")
7008 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7009 (match_operand:DI 2 "mask64_2_operand" ""))
7010 (const_int 0)))
7011 (clobber (match_scratch:DI 3 ""))
7012 (clobber (match_scratch:CC 4 ""))]
7013 "TARGET_POWERPC64 && reload_completed
7014 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7015 && !mask64_operand (operands[2], DImode)"
7016 [(set (match_dup 3)
7017 (and:DI (rotate:DI (match_dup 1)
7018 (match_dup 5))
7019 (match_dup 6)))
7020 (parallel [(set (match_dup 0)
7021 (compare:CC (and:DI (rotate:DI (match_dup 3)
7022 (match_dup 7))
7023 (match_dup 8))
7024 (const_int 0)))
7025 (clobber (match_dup 3))])]
7026 "
7027{
7028 build_mask64_2_operands (operands[2], &operands[5]);
7029}")
7030
a260abc9 7031(define_insn "*anddi3_internal3"
0ba1b2ff
AM		 7032 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7033 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7034 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
266eb58a 7035 (const_int 0)))
0ba1b2ff 7036 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
9ebbca7d 7037 (and:DI (match_dup 1) (match_dup 2)))
0ba1b2ff 7038 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
6ffc8580 7039 "TARGET_POWERPC64"
266eb58a
DE		 7040 "@
7041 and. %0,%1,%2
6c873122 7042 rldic%B2. %0,%1,0,%S2
6ffc8580
MM		 7043 andi. %0,%1,%b2
7044 andis. %0,%1,%u2
9ebbca7d
GK		 7045 #
7046 #
7047 #
0ba1b2ff
AM		 7048 #
7049 #
9ebbca7d 7050 #"
0ba1b2ff
AM		 7051 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7052 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
9ebbca7d
GK		 7053
7054(define_split
7055 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7056 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7057 (match_operand:DI 2 "and64_operand" ""))
7058 (const_int 0)))
7059 (set (match_operand:DI 0 "gpc_reg_operand" "")
7060 (and:DI (match_dup 1) (match_dup 2)))
7061 (clobber (match_scratch:CC 4 ""))]
7062 "TARGET_POWERPC64 && reload_completed"
7063 [(parallel [(set (match_dup 0)
7064 (and:DI (match_dup 1) (match_dup 2)))
7065 (clobber (match_dup 4))])
7066 (set (match_dup 3)
7067 (compare:CC (match_dup 0)
7068 (const_int 0)))]
7069 "")
266eb58a 7070
0ba1b2ff
AM		 7071(define_split
7072 [(set (match_operand:CC 3 "cc_reg_operand" "")
7073 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7074 (match_operand:DI 2 "mask64_2_operand" ""))
7075 (const_int 0)))
7076 (set (match_operand:DI 0 "gpc_reg_operand" "")
7077 (and:DI (match_dup 1) (match_dup 2)))
7078 (clobber (match_scratch:CC 4 ""))]
7079 "TARGET_POWERPC64 && reload_completed
7080 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7081 && !mask64_operand (operands[2], DImode)"
7082 [(set (match_dup 0)
7083 (and:DI (rotate:DI (match_dup 1)
7084 (match_dup 5))
7085 (match_dup 6)))
7086 (parallel [(set (match_dup 3)
7087 (compare:CC (and:DI (rotate:DI (match_dup 0)
7088 (match_dup 7))
7089 (match_dup 8))
7090 (const_int 0)))
7091 (set (match_dup 0)
7092 (and:DI (rotate:DI (match_dup 0)
7093 (match_dup 7))
7094 (match_dup 8)))])]
7095 "
7096{
7097 build_mask64_2_operands (operands[2], &operands[5]);
7098}")
7099
a260abc9 7100(define_expand "iordi3"
266eb58a 7101 [(set (match_operand:DI 0 "gpc_reg_operand" "")
a260abc9 7102 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7103 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
266eb58a 7104 "TARGET_POWERPC64"
266eb58a
DE		 7105 "
7106{
dfbdccdb 7107 if (non_logical_cint_operand (operands[2], DImode))
266eb58a 7108 {
dfbdccdb 7109 HOST_WIDE_INT value;
677a9668 7110 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
a260abc9 7111 ? operands[0] : gen_reg_rtx (DImode));
266eb58a 7112
dfbdccdb
GK		 7113 if (GET_CODE (operands[2]) == CONST_INT)
7114 {
7115 value = INTVAL (operands[2]);
7116 emit_insn (gen_iordi3 (tmp, operands[1],
7117 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7118 }
e2c953b6 7119 else
dfbdccdb
GK		 7120 {
7121 value = CONST_DOUBLE_LOW (operands[2]);
7122 emit_insn (gen_iordi3 (tmp, operands[1],
7123 immed_double_const (value
7124 & (~ (HOST_WIDE_INT) 0xffff),
7125 0, DImode)));
7126 }
e2c953b6 7127
9ebbca7d
GK		 7128 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7129 DONE;
7130 }
266eb58a
DE		 7131}")
7132
a260abc9
DE		 7133(define_expand "xordi3"
7134 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7135 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7136 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
a260abc9
DE		 7137 "TARGET_POWERPC64"
7138 "
7139{
dfbdccdb 7140 if (non_logical_cint_operand (operands[2], DImode))
a260abc9 7141 {
dfbdccdb 7142 HOST_WIDE_INT value;
677a9668 7143 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
a260abc9
DE		 7144 ? operands[0] : gen_reg_rtx (DImode));
7145
dfbdccdb
GK		 7146 if (GET_CODE (operands[2]) == CONST_INT)
7147 {
7148 value = INTVAL (operands[2]);
7149 emit_insn (gen_xordi3 (tmp, operands[1],
7150 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7151 }
e2c953b6 7152 else
dfbdccdb
GK		 7153 {
7154 value = CONST_DOUBLE_LOW (operands[2]);
7155 emit_insn (gen_xordi3 (tmp, operands[1],
7156 immed_double_const (value
7157 & (~ (HOST_WIDE_INT) 0xffff),
7158 0, DImode)));
7159 }
e2c953b6 7160
9ebbca7d
GK		 7161 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7162 DONE;
7163 }
a260abc9
DE		 7164}")
7165
dfbdccdb 7166(define_insn "*booldi3_internal1"
266eb58a 7167 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 7168 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7169 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7170 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
266eb58a 7171 "TARGET_POWERPC64"
1fd4e8c1 7172 "@
dfbdccdb
GK		 7173 %q3 %0,%1,%2
7174 %q3i %0,%1,%b2
7175 %q3is %0,%1,%u2")
1fd4e8c1 7176
dfbdccdb 7177(define_insn "*booldi3_internal2"
9ebbca7d 7178 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 7179 (compare:CC (match_operator:DI 4 "boolean_or_operator"
dfbdccdb
GK		 7180 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7181 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7182 (const_int 0)))
9ebbca7d 7183 (clobber (match_scratch:DI 3 "=r,r"))]
266eb58a 7184 "TARGET_POWERPC64"
9ebbca7d 7185 "@
dfbdccdb 7186 %q4. %3,%1,%2
9ebbca7d
GK		 7187 #"
7188 [(set_attr "type" "compare")
7189 (set_attr "length" "4,8")])
7190
7191(define_split
7192 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7193 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7194 [(match_operand:DI 1 "gpc_reg_operand" "")
7195 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7196 (const_int 0)))
9ebbca7d
GK		 7197 (clobber (match_scratch:DI 3 ""))]
7198 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7199 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7200 (set (match_dup 0)
7201 (compare:CC (match_dup 3)
7202 (const_int 0)))]
7203 "")
1fd4e8c1 7204
dfbdccdb 7205(define_insn "*booldi3_internal3"
9ebbca7d 7206 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7207 (compare:CC (match_operator:DI 4 "boolean_operator"
7208 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7209 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7210 (const_int 0)))
9ebbca7d 7211 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7212 (match_dup 4))]
266eb58a 7213 "TARGET_POWERPC64"
9ebbca7d 7214 "@
dfbdccdb 7215 %q4. %0,%1,%2
9ebbca7d
GK		 7216 #"
7217 [(set_attr "type" "compare")
7218 (set_attr "length" "4,8")])
7219
7220(define_split
e72247f4 7221 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7222 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7223 [(match_operand:DI 1 "gpc_reg_operand" "")
7224 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7225 (const_int 0)))
75540af0 7226 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7227 (match_dup 4))]
9ebbca7d 7228 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7229 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7230 (set (match_dup 3)
7231 (compare:CC (match_dup 0)
7232 (const_int 0)))]
7233 "")
1fd4e8c1 7234
5bdc5878 7235;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 7236;; each of which does one 16-bit part. This is used by combine.
266eb58a
DE		 7237
7238(define_split
7239 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1d328b19 7240 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7241 [(match_operand:DI 1 "gpc_reg_operand" "")
7242 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
266eb58a 7243 "TARGET_POWERPC64"
dfbdccdb
GK		 7244 [(set (match_dup 0) (match_dup 4))
7245 (set (match_dup 0) (match_dup 5))]
266eb58a
DE		 7246"
7247{
dfbdccdb
GK		 7248 rtx i3,i4;
7249
9ebbca7d
GK		 7250 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7251 {
7252 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
dfbdccdb 7253 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
9ebbca7d 7254 0, DImode);
dfbdccdb 7255 i4 = GEN_INT (value & 0xffff);
9ebbca7d
GK		 7256 }
7257 else
7258 {
dfbdccdb 7259 i3 = GEN_INT (INTVAL (operands[2])
9ebbca7d 7260 & (~ (HOST_WIDE_INT) 0xffff));
dfbdccdb 7261 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
9ebbca7d 7262 }
dfbdccdb
GK		 7263 operands[4] = gen_rtx (GET_CODE (operands[3]), DImode,
7264 operands[1], i3);
7265 operands[5] = gen_rtx (GET_CODE (operands[3]), DImode,
7266 operands[0], i4);
1fd4e8c1
RK		 7267}")
7268
dfbdccdb 7269(define_insn "*boolcdi3_internal1"
9ebbca7d 7270 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7271 (match_operator:DI 3 "boolean_operator"
7272 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7273 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
a473029f 7274 "TARGET_POWERPC64"
1d328b19 7275 "%q3 %0,%2,%1")
a473029f 7276
dfbdccdb 7277(define_insn "*boolcdi3_internal2"
9ebbca7d 7278 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7279 (compare:CC (match_operator:DI 4 "boolean_operator"
7280 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7281 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7282 (const_int 0)))
9ebbca7d 7283 (clobber (match_scratch:DI 3 "=r,r"))]
a473029f 7284 "TARGET_POWERPC64"
9ebbca7d 7285 "@
1d328b19 7286 %q4. %3,%2,%1
9ebbca7d
GK		 7287 #"
7288 [(set_attr "type" "compare")
7289 (set_attr "length" "4,8")])
7290
7291(define_split
7292 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7293 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7294 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7295 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7296 (const_int 0)))
9ebbca7d
GK		 7297 (clobber (match_scratch:DI 3 ""))]
7298 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7299 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7300 (set (match_dup 0)
7301 (compare:CC (match_dup 3)
7302 (const_int 0)))]
7303 "")
a473029f 7304
dfbdccdb 7305(define_insn "*boolcdi3_internal3"
9ebbca7d 7306 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7307 (compare:CC (match_operator:DI 4 "boolean_operator"
7308 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7309 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7310 (const_int 0)))
9ebbca7d 7311 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7312 (match_dup 4))]
a473029f 7313 "TARGET_POWERPC64"
9ebbca7d 7314 "@
1d328b19 7315 %q4. %0,%2,%1
9ebbca7d
GK		 7316 #"
7317 [(set_attr "type" "compare")
7318 (set_attr "length" "4,8")])
7319
7320(define_split
e72247f4 7321 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7322 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7323 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7324 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7325 (const_int 0)))
75540af0 7326 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7327 (match_dup 4))]
9ebbca7d 7328 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7329 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7330 (set (match_dup 3)
7331 (compare:CC (match_dup 0)
7332 (const_int 0)))]
7333 "")
266eb58a 7334
dfbdccdb 7335(define_insn "*boolccdi3_internal1"
a473029f 7336 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7337 (match_operator:DI 3 "boolean_operator"
7338 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7339 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
a473029f 7340 "TARGET_POWERPC64"
dfbdccdb 7341 "%q3 %0,%1,%2")
a473029f 7342
dfbdccdb 7343(define_insn "*boolccdi3_internal2"
9ebbca7d 7344 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7345 (compare:CC (match_operator:DI 4 "boolean_operator"
7346 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7347 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7348 (const_int 0)))
9ebbca7d 7349 (clobber (match_scratch:DI 3 "=r,r"))]
266eb58a 7350 "TARGET_POWERPC64"
9ebbca7d 7351 "@
dfbdccdb 7352 %q4. %3,%1,%2
9ebbca7d
GK		 7353 #"
7354 [(set_attr "type" "compare")
7355 (set_attr "length" "4,8")])
7356
7357(define_split
7358 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7359 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7360 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7361 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7362 (const_int 0)))
9ebbca7d
GK		 7363 (clobber (match_scratch:DI 3 ""))]
7364 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7365 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7366 (set (match_dup 0)
7367 (compare:CC (match_dup 3)
7368 (const_int 0)))]
7369 "")
266eb58a 7370
dfbdccdb 7371(define_insn "*boolccdi3_internal3"
9ebbca7d 7372 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7373 (compare:CC (match_operator:DI 4 "boolean_operator"
7374 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7375 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7376 (const_int 0)))
9ebbca7d 7377 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7378 (match_dup 4))]
29ae5b89 7379 "TARGET_POWERPC64"
9ebbca7d 7380 "@
dfbdccdb 7381 %q4. %0,%1,%2
9ebbca7d
GK		 7382 #"
7383 [(set_attr "type" "compare")
7384 (set_attr "length" "4,8")])
7385
7386(define_split
e72247f4 7387 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7388 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7389 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7390 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7391 (const_int 0)))
75540af0 7392 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7393 (match_dup 4))]
9ebbca7d 7394 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7395 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7396 (set (match_dup 3)
7397 (compare:CC (match_dup 0)
7398 (const_int 0)))]
7399 "")
dfbdccdb 7400\f
1fd4e8c1 7401;; Now define ways of moving data around.
4697a36c
MM		 7402
7403;; Elf specific ways of loading addresses for non-PIC code.
9ebbca7d
GK		 7404;; The output of this could be r0, but we make a very strong
7405;; preference for a base register because it will usually
7406;; be needed there.
4697a36c 7407(define_insn "elf_high"
9ebbca7d 7408 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
4697a36c 7409 (high:SI (match_operand 1 "" "")))]
0ad91047 7410 "TARGET_ELF && ! TARGET_64BIT"
a6c2a102 7411 "{liu|lis} %0,%1@ha")
4697a36c
MM		 7412
7413(define_insn "elf_low"
9ebbca7d
GK		 7414 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7415 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
4697a36c 7416 (match_operand 2 "" "")))]
0ad91047 7417 "TARGET_ELF && ! TARGET_64BIT"
9ebbca7d
GK		 7418 "@
7419 {cal|la} %0,%2@l(%1)
81eace42 7420 {ai|addic} %0,%1,%K2")
4697a36c 7421
ee890fe2
SS		 7422;; Mach-O PIC trickery.
7423(define_insn "macho_high"
7424 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7425 (high:SI (match_operand 1 "" "")))]
7426 "TARGET_MACHO && ! TARGET_64BIT"
7427 "{liu|lis} %0,ha16(%1)")
7428
7429(define_insn "macho_low"
7430 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7431 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7432 (match_operand 2 "" "")))]
7433 "TARGET_MACHO && ! TARGET_64BIT"
7434 "@
7435 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
7436 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
7437
766a866c
MM		 7438;; Set up a register with a value from the GOT table
7439
7440(define_expand "movsi_got"
52d3af72 7441 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d
GK		 7442 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7443 (match_dup 2)] 8))]
f607bc57 7444 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 7445 "
7446{
38c1f2d7
MM		 7447 if (GET_CODE (operands[1]) == CONST)
7448 {
7449 rtx offset = const0_rtx;
7450 HOST_WIDE_INT value;
7451
7452 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7453 value = INTVAL (offset);
7454 if (value != 0)
7455 {
677a9668 7456 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
38c1f2d7
MM		 7457 emit_insn (gen_movsi_got (tmp, operands[1]));
7458 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7459 DONE;
7460 }
7461 }
7462
c4c40373 7463 operands[2] = rs6000_got_register (operands[1]);
766a866c
MM		 7464}")
7465
84f414bc 7466(define_insn "*movsi_got_internal"
52d3af72 7467 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9ebbca7d
GK		 7468 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7469 (match_operand:SI 2 "gpc_reg_operand" "b")] 8))]
f607bc57 7470 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 7471 "{l|lwz} %0,%a1@got(%2)"
7472 [(set_attr "type" "load")])
7473
b22b9b3e
JL		 7474;; Used by sched, shorten_branches and final when the GOT pseudo reg
7475;; didn't get allocated to a hard register.
7476(define_split
75540af0 7477 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 7478 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
75540af0 7479 (match_operand:SI 2 "memory_operand" "")] 8))]
f607bc57 7480 "DEFAULT_ABI == ABI_V4
b22b9b3e
JL		 7481 && flag_pic == 1
7482 && (reload_in_progress || reload_completed)"
7483 [(set (match_dup 0) (match_dup 2))
9ebbca7d 7484 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))]
b22b9b3e
JL		 7485 "")
7486
1fd4e8c1
RK		 7487;; For SI, we special-case integers that can't be loaded in one insn. We
7488;; do the load 16-bits at a time. We could do this by loading from memory,
7489;; and this is even supposed to be faster, but it is simpler not to get
7490;; integers in the TOC.
7491(define_expand "movsi"
7492 [(set (match_operand:SI 0 "general_operand" "")
7493 (match_operand:SI 1 "any_operand" ""))]
7494 ""
fb4d4348 7495 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
1fd4e8c1 7496
ee890fe2
SS		 7497(define_insn "movsi_low"
7498 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
f585a356 7499 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
ee890fe2
SS		 7500 (match_operand 2 "" ""))))]
7501 "TARGET_MACHO && ! TARGET_64BIT"
7502 "{l|lwz} %0,lo16(%2)(%1)"
7503 [(set_attr "type" "load")
7504 (set_attr "length" "4")])
7505
c859cda6 7506(define_insn "movsi_low_st"
f585a356 7507 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
c859cda6
DJ		 7508 (match_operand 2 "" "")))
7509 (match_operand:SI 0 "gpc_reg_operand" "r"))]
7510 "TARGET_MACHO && ! TARGET_64BIT"
7511 "{st|stw} %0,lo16(%2)(%1)"
7512 [(set_attr "type" "store")
7513 (set_attr "length" "4")])
7514
7515(define_insn "movdf_low"
234e114c 7516 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
f585a356 7517 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
c859cda6 7518 (match_operand 2 "" ""))))]
a3170dc6 7519 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
234e114c
DJ		 7520 "*
7521{
7522 switch (which_alternative)
7523 {
7524 case 0:
7525 return \"lfd %0,lo16(%2)(%1)\";
7526 case 1:
7527 {
7528 rtx operands2[4];
7529 operands2[0] = operands[0];
7530 operands2[1] = operands[1];
7531 operands2[2] = operands[2];
1db02437 7532 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
234e114c
DJ		 7533 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
7534 /* We cannot rely on ha16(low half)==ha16(high half), alas,
7535 although in practice it almost always is. */
7536 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
7537 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
7538 }
7539 default:
7540 abort();
7541 }
7542}"
c859cda6 7543 [(set_attr "type" "load")
234e114c 7544 (set_attr "length" "4,12")])
c859cda6
DJ		 7545
7546(define_insn "movdf_low_st"
f585a356 7547 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
c859cda6
DJ		 7548 (match_operand 2 "" "")))
7549 (match_operand:DF 0 "gpc_reg_operand" "f"))]
a3170dc6 7550 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
c859cda6
DJ		 7551 "stfd %0,lo16(%2)(%1)"
7552 [(set_attr "type" "store")
7553 (set_attr "length" "4")])
7554
7555(define_insn "movsf_low"
fd3b43f2 7556 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
f585a356 7557 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
c859cda6 7558 (match_operand 2 "" ""))))]
a3170dc6 7559 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
fd3b43f2
DJ		 7560 "@
7561 lfs %0,lo16(%2)(%1)
7562 {l|lwz} %0,lo16(%2)(%1)"
c859cda6
DJ		 7563 [(set_attr "type" "load")
7564 (set_attr "length" "4")])
7565
7566(define_insn "movsf_low_st"
f585a356 7567 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
c859cda6 7568 (match_operand 2 "" "")))
fd3b43f2 7569 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
a3170dc6 7570 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
fd3b43f2
DJ		 7571 "@
7572 stfs %0,lo16(%2)(%1)
7573 {st|stw} %0,lo16(%2)(%1)"
c859cda6
DJ		 7574 [(set_attr "type" "store")
7575 (set_attr "length" "4")])
7576
acad7ed3 7577(define_insn "*movsi_internal1"
a004eb82
AH		 7578 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7579 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
19d5775a
RK		 7580 "gpc_reg_operand (operands[0], SImode)
7581 || gpc_reg_operand (operands[1], SImode)"
1fd4e8c1 7582 "@
deb9225a 7583 mr %0,%1
b9442c72 7584 {cal|la} %0,%a1
ca7f5001
RK		 7585 {l%U1%X1|lwz%U1%X1} %0,%1
7586 {st%U0%X0|stw%U0%X0} %1,%0
19d5775a 7587 {lil|li} %0,%1
802a0058 7588 {liu|lis} %0,%v1
beaec479 7589 #
aee86b38 7590 {cal|la} %0,%a1
1fd4e8c1 7591 mf%1 %0
5c23c401 7592 mt%0 %1
e76e75bb 7593 mt%0 %1
a004eb82 7594 mt%0 %1
e34eaae5 7595 {cror 0,0,0|nop}"
a004eb82
AH		 7596 [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*,*")
7597 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
1fd4e8c1 7598
77fa0940
RK		 7599;; Split a load of a large constant into the appropriate two-insn
7600;; sequence.
7601
7602(define_split
7603 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7604 (match_operand:SI 1 "const_int_operand" ""))]
bb21487f 7605 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
77fa0940
RK		 7606 && (INTVAL (operands[1]) & 0xffff) != 0"
7607 [(set (match_dup 0)
7608 (match_dup 2))
7609 (set (match_dup 0)
7610 (ior:SI (match_dup 0)
7611 (match_dup 3)))]
7612 "
af8cb5c5
DE		 7613{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7614
7615 if (tem == operands[0])
7616 DONE;
7617 else
7618 FAIL;
77fa0940
RK		 7619}")
7620
acad7ed3 7621(define_insn "*movsi_internal2"
9ebbca7d
GK		 7622 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
7623 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 7624 (const_int 0)))
9ebbca7d 7625 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
0ad91047 7626 "! TARGET_POWERPC64"
9ebbca7d
GK		 7627 "@
7628 mr. %0,%1
7629 #"
7630 [(set_attr "type" "compare")
7631 (set_attr "length" "4,8")])
1fd4e8c1 7632\f
9ebbca7d
GK		 7633(define_split
7634 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7635 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7636 (const_int 0)))
7637 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7638 "! TARGET_POWERPC64 && reload_completed"
7639 [(set (match_dup 0) (match_dup 1))
7640 (set (match_dup 2)
7641 (compare:CC (match_dup 0)
7642 (const_int 0)))]
7643 "")
7644
1fd4e8c1
RK		 7645(define_expand "movhi"
7646 [(set (match_operand:HI 0 "general_operand" "")
7647 (match_operand:HI 1 "any_operand" ""))]
7648 ""
fb4d4348 7649 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
1fd4e8c1 7650
e34eaae5 7651(define_insn "*movhi_internal"
fb81d7ce
RK		 7652 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7653 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 7654 "gpc_reg_operand (operands[0], HImode)
7655 || gpc_reg_operand (operands[1], HImode)"
1fd4e8c1 7656 "@
deb9225a 7657 mr %0,%1
1fd4e8c1
RK		 7658 lhz%U1%X1 %0,%1
7659 sth%U0%X0 %1,%0
19d5775a 7660 {lil|li} %0,%w1
1fd4e8c1 7661 mf%1 %0
e76e75bb 7662 mt%0 %1
fb81d7ce 7663 mt%0 %1
e34eaae5 7664 {cror 0,0,0|nop}"
b7ff3d82 7665 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
1fd4e8c1
RK		 7666
7667(define_expand "movqi"
7668 [(set (match_operand:QI 0 "general_operand" "")
7669 (match_operand:QI 1 "any_operand" ""))]
7670 ""
fb4d4348 7671 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
1fd4e8c1 7672
e34eaae5 7673(define_insn "*movqi_internal"
fb81d7ce
RK		 7674 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7675 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 7676 "gpc_reg_operand (operands[0], QImode)
7677 || gpc_reg_operand (operands[1], QImode)"
1fd4e8c1 7678 "@
deb9225a 7679 mr %0,%1
1fd4e8c1
RK		 7680 lbz%U1%X1 %0,%1
7681 stb%U0%X0 %1,%0
19d5775a 7682 {lil|li} %0,%1
1fd4e8c1 7683 mf%1 %0
e76e75bb 7684 mt%0 %1
fb81d7ce 7685 mt%0 %1
e34eaae5 7686 {cror 0,0,0|nop}"
b7ff3d82 7687 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
1fd4e8c1
RK		 7688\f
7689;; Here is how to move condition codes around. When we store CC data in
7690;; an integer register or memory, we store just the high-order 4 bits.
7691;; This lets us not shift in the most common case of CR0.
7692(define_expand "movcc"
7693 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7694 (match_operand:CC 1 "nonimmediate_operand" ""))]
7695 ""
7696 "")
7697
a65c591c 7698(define_insn "*movcc_internal1"
b54cf83a
DE		 7699 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7700 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
1fd4e8c1
RK		 7701 "register_operand (operands[0], CCmode)
7702 || register_operand (operands[1], CCmode)"
7703 "@
7704 mcrf %0,%1
7705 mtcrf 128,%1
ca7f5001 7706 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
1fd4e8c1 7707 mfcr %0
ca7f5001 7708 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
deb9225a 7709 mr %0,%1
b54cf83a 7710 mf%1 %0
b991a865
GK		 7711 mt%0 %1
7712 mt%0 %1
ca7f5001
RK		 7713 {l%U1%X1|lwz%U1%X1} %0,%1
7714 {st%U0%U1|stw%U0%U1} %1,%0"
b54cf83a 7715 [(set_attr "type" "cr_logical,mtcr,mtcr,mfcr,mfcr,*,*,*,mtjmpr,load,store")
b991a865 7716 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
1fd4e8c1 7717\f
e52e05ca
MM		 7718;; For floating-point, we normally deal with the floating-point registers
7719;; unless -msoft-float is used. The sole exception is that parameter passing
7720;; can produce floating-point values in fixed-point registers. Unless the
7721;; value is a simple constant or already in memory, we deal with this by
7722;; allocating memory and copying the value explicitly via that memory location.
1fd4e8c1
RK		 7723(define_expand "movsf"
7724 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7725 (match_operand:SF 1 "any_operand" ""))]
7726 ""
fb4d4348 7727 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
1fd4e8c1 7728
1fd4e8c1 7729(define_split
cd2b37d9 7730 [(set (match_operand:SF 0 "gpc_reg_operand" "")
c4c40373 7731 (match_operand:SF 1 "const_double_operand" ""))]
f99f88e0 7732 "reload_completed
5ae4759c
MM		 7733 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7734 || (GET_CODE (operands[0]) == SUBREG
7735 && GET_CODE (SUBREG_REG (operands[0])) == REG
7736 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373 7737 [(set (match_dup 2) (match_dup 3))]
685f3906
DE		 7738 "
7739{
7740 long l;
7741 REAL_VALUE_TYPE rv;
7742
7743 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7744 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
c4c40373 7745
f99f88e0
DE		 7746 if (! TARGET_POWERPC64)
7747 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7748 else
7749 operands[2] = gen_lowpart (SImode, operands[0]);
a260abc9 7750
2496c7bd 7751 operands[3] = gen_int_mode (l, SImode);
a260abc9
DE		 7752}")
7753
c4c40373 7754(define_insn "*movsf_hardfloat"
b991a865
GK		 7755 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!r,!r")
7756 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,G,Fn"))]
d14a6d05 7757 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 7758 || gpc_reg_operand (operands[1], SFmode))
7759 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
1fd4e8c1 7760 "@
f99f88e0
DE		 7761 mr %0,%1
7762 {l%U1%X1|lwz%U1%X1} %0,%1
7763 {st%U0%X0|stw%U0%X0} %1,%0
1fd4e8c1
RK		 7764 fmr %0,%1
7765 lfs%U1%X1 %0,%1
c4c40373 7766 stfs%U0%X0 %1,%0
b991a865
GK		 7767 mt%0 %1
7768 mt%0 %1
7769 mf%1 %0
c4c40373
MM		 7770 #
7771 #"
b991a865
GK		 7772 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*")
7773 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
d14a6d05 7774
c4c40373 7775(define_insn "*movsf_softfloat"
b991a865
GK		 7776 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r")
7777 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn"))]
d14a6d05 7778 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 7779 || gpc_reg_operand (operands[1], SFmode))
7780 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
d14a6d05
MM		 7781 "@
7782 mr %0,%1
b991a865
GK		 7783 mt%0 %1
7784 mt%0 %1
7785 mf%1 %0
d14a6d05
MM		 7786 {l%U1%X1|lwz%U1%X1} %0,%1
7787 {st%U0%X0|stw%U0%X0} %1,%0
7788 {lil|li} %0,%1
802a0058 7789 {liu|lis} %0,%v1
aee86b38 7790 {cal|la} %0,%a1
c4c40373
MM		 7791 #
7792 #"
b991a865
GK		 7793 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*")
7794 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
d14a6d05 7795
1fd4e8c1
RK		 7796\f
7797(define_expand "movdf"
7798 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7799 (match_operand:DF 1 "any_operand" ""))]
7800 ""
fb4d4348 7801 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
1fd4e8c1
RK		 7802
7803(define_split
cd2b37d9 7804 [(set (match_operand:DF 0 "gpc_reg_operand" "")
c4c40373 7805 (match_operand:DF 1 "const_int_operand" ""))]
a260abc9 7806 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 7807 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7808 || (GET_CODE (operands[0]) == SUBREG
7809 && GET_CODE (SUBREG_REG (operands[0])) == REG
7810 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 7811 [(set (match_dup 2) (match_dup 4))
7812 (set (match_dup 3) (match_dup 1))]
7813 "
7814{
5ae4759c 7815 int endian = (WORDS_BIG_ENDIAN == 0);
5f59ecb7
DE		 7816 HOST_WIDE_INT value = INTVAL (operands[1]);
7817
5ae4759c
MM		 7818 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7819 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5f59ecb7
DE		 7820#if HOST_BITS_PER_WIDE_INT == 32
7821 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7822#else
7823 operands[4] = GEN_INT (value >> 32);
a65c591c 7824 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
5f59ecb7 7825#endif
c4c40373
MM		 7826}")
7827
c4c40373
MM		 7828(define_split
7829 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7830 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 7831 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 7832 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7833 || (GET_CODE (operands[0]) == SUBREG
7834 && GET_CODE (SUBREG_REG (operands[0])) == REG
7835 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 7836 [(set (match_dup 2) (match_dup 4))
7837 (set (match_dup 3) (match_dup 5))]
7838 "
7839{
5ae4759c 7840 int endian = (WORDS_BIG_ENDIAN == 0);
47ad8c61
MM		 7841 long l[2];
7842 REAL_VALUE_TYPE rv;
7843
7844 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7845 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7846
5ae4759c
MM		 7847 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7848 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
2496c7bd
LB		 7849 operands[4] = gen_int_mode (l[endian], SImode);
7850 operands[5] = gen_int_mode (l[1 - endian], SImode);
c4c40373
MM		 7851}")
7852
efc08378
DE		 7853(define_split
7854 [(set (match_operand:DF 0 "gpc_reg_operand" "")
685f3906 7855 (match_operand:DF 1 "easy_fp_constant" ""))]
a260abc9 7856 "TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 7857 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7858 || (GET_CODE (operands[0]) == SUBREG
7859 && GET_CODE (SUBREG_REG (operands[0])) == REG
7860 && REGNO (SUBREG_REG (operands[0])) <= 31))"
a260abc9 7861 [(set (match_dup 2) (match_dup 3))]
5ae4759c 7862 "
a260abc9
DE		 7863{
7864 int endian = (WORDS_BIG_ENDIAN == 0);
7865 long l[2];
7866 REAL_VALUE_TYPE rv;
4977bab6 7867#if HOST_BITS_PER_WIDE_INT >= 64
5b029315 7868 HOST_WIDE_INT val;
4977bab6 7869#endif
a260abc9
DE		 7870
7871 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7872 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7873
7874 operands[2] = gen_lowpart (DImode, operands[0]);
7875 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
5b029315 7876#if HOST_BITS_PER_WIDE_INT >= 64
a2419b96
DE		 7877 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
7878 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
5b029315 7879
f5264b52 7880 operands[3] = gen_int_mode (val, DImode);
5b029315 7881#else
a260abc9 7882 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
5b029315 7883#endif
a260abc9 7884}")
efc08378 7885
4eae5fe1 7886;; Don't have reload use general registers to load a constant. First,
1427100a 7887;; it might not work if the output operand is the equivalent of
4eae5fe1
RK		 7888;; a non-offsettable memref, but also it is less efficient than loading
7889;; the constant into an FP register, since it will probably be used there.
7890;; The "??" is a kludge until we can figure out a more reasonable way
7891;; of handling these non-offsettable values.
c4c40373 7892(define_insn "*movdf_hardfloat32"
914a7297
DE		 7893 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
7894 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
a3170dc6 7895 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 7896 && (gpc_reg_operand (operands[0], DFmode)
7897 || gpc_reg_operand (operands[1], DFmode))"
e7113111
RK		 7898 "*
7899{
7900 switch (which_alternative)
7901 {
a260abc9 7902 default:
a6c2a102 7903 abort ();
e7113111
RK		 7904 case 0:
7905 /* We normally copy the low-numbered register first. However, if
000034eb
DE		 7906 the first register operand 0 is the same as the second register
7907 of operand 1, we must copy in the opposite order. */
e7113111 7908 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
deb9225a 7909 return \"mr %L0,%L1\;mr %0,%1\";
e7113111 7910 else
deb9225a 7911 return \"mr %0,%1\;mr %L0,%L1\";
e7113111 7912 case 1:
2b97222d
DE		 7913 if (offsettable_memref_p (operands[1])
7914 || (GET_CODE (operands[1]) == MEM
69f51a21
DE		 7915 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7916 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7917 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
000034eb
DE		 7918 {
7919 /* If the low-address word is used in the address, we must load
7920 it last. Otherwise, load it first. Note that we cannot have
7921 auto-increment in that case since the address register is
7922 known to be dead. */
7923 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7924 operands[1], 0))
7925 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7926 else
7927 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7928 }
e7113111 7929 else
000034eb
DE		 7930 {
7931 rtx addreg;
7932
000034eb
DE		 7933 addreg = find_addr_reg (XEXP (operands[1], 0));
7934 if (refers_to_regno_p (REGNO (operands[0]),
7935 REGNO (operands[0]) + 1,
7936 operands[1], 0))
7937 {
7938 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2b97222d 7939 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
000034eb 7940 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
2b97222d 7941 return \"{lx|lwzx} %0,%1\";
000034eb
DE		 7942 }
7943 else
7944 {
2b97222d 7945 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
000034eb 7946 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2b97222d 7947 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
000034eb
DE		 7948 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7949 return \"\";
7950 }
7951 }
e7113111 7952 case 2:
2b97222d
DE		 7953 if (offsettable_memref_p (operands[0])
7954 || (GET_CODE (operands[0]) == MEM
69f51a21
DE		 7955 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7956 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7957 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
000034eb
DE		 7958 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7959 else
7960 {
7961 rtx addreg;
7962
000034eb 7963 addreg = find_addr_reg (XEXP (operands[0], 0));
2b97222d 7964 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
000034eb 7965 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2b97222d 7966 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
000034eb
DE		 7967 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7968 return \"\";
7969 }
e7113111 7970 case 3:
914a7297 7971 return \"fmr %0,%1\";
e7113111 7972 case 4:
914a7297 7973 return \"lfd%U1%X1 %0,%1\";
e7113111 7974 case 5:
914a7297 7975 return \"stfd%U0%X0 %1,%0\";
e7113111 7976 case 6:
c4c40373 7977 case 7:
c4c40373 7978 case 8:
914a7297 7979 return \"#\";
e7113111
RK		 7980 }
7981}"
914a7297
DE		 7982 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
7983 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
51b8fc2c 7984
c4c40373 7985(define_insn "*movdf_softfloat32"
1427100a
DE		 7986 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7987 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
a3170dc6 7988 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
52d3af72
DE		 7989 && (gpc_reg_operand (operands[0], DFmode)
7990 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca
MM		 7991 "*
7992{
7993 switch (which_alternative)
7994 {
a260abc9 7995 default:
a6c2a102 7996 abort ();
dc4f83ca
MM		 7997 case 0:
7998 /* We normally copy the low-numbered register first. However, if
7999 the first register operand 0 is the same as the second register of
8000 operand 1, we must copy in the opposite order. */
8001 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8002 return \"mr %L0,%L1\;mr %0,%1\";
8003 else
8004 return \"mr %0,%1\;mr %L0,%L1\";
8005 case 1:
3cb999d8
DE		 8006 /* If the low-address word is used in the address, we must load
8007 it last. Otherwise, load it first. Note that we cannot have
8008 auto-increment in that case since the address register is
8009 known to be dead. */
dc4f83ca 8010 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3cb999d8 8011 operands[1], 0))
dc4f83ca
MM		 8012 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8013 else
8014 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8015 case 2:
8016 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8017 case 3:
c4c40373
MM		 8018 case 4:
8019 case 5:
dc4f83ca
MM		 8020 return \"#\";
8021 }
8022}"
c4c40373
MM		 8023 [(set_attr "type" "*,load,store,*,*,*")
8024 (set_attr "length" "8,8,8,8,12,16")])
dc4f83ca 8025
c4c40373 8026(define_insn "*movdf_hardfloat64"
914a7297
DE		 8027 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!cl,!r,!r,!r,!r")
8028 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,r,h,G,H,F"))]
a3170dc6 8029 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8030 && (gpc_reg_operand (operands[0], DFmode)
8031 || gpc_reg_operand (operands[1], DFmode))"
51b8fc2c 8032 "@
3d5570cb
RK		 8033 mr %0,%1
8034 ld%U1%X1 %0,%1
96bb8ed3 8035 std%U0%X0 %1,%0
3d5570cb 8036 fmr %0,%1
f63184ac 8037 lfd%U1%X1 %0,%1
914a7297
DE		 8038 stfd%U0%X0 %1,%0
8039 mt%0 %1
8040 mf%1 %0
8041 #
8042 #
8043 #"
8044 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*")
8045 (set_attr "length" "4,4,4,4,4,4,4,4,8,12,16")])
dc4f83ca 8046
c4c40373 8047(define_insn "*movdf_softfloat64"
914a7297
DE		 8048 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r")
8049 (match_operand:DF 1 "input_operand" "r,r,h,m,r,G,H,F"))]
a3170dc6 8050 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
52d3af72
DE		 8051 && (gpc_reg_operand (operands[0], DFmode)
8052 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca
MM		 8053 "@
8054 mr %0,%1
914a7297
DE		 8055 mt%0 %1
8056 mf%1 %0
dc4f83ca 8057 ld%U1%X1 %0,%1
96bb8ed3 8058 std%U0%X0 %1,%0
c4c40373
MM		 8059 #
8060 #
dc4f83ca 8061 #"
914a7297
DE		 8062 [(set_attr "type" "*,*,*,load,store,*,*,*")
8063 (set_attr "length" "4,4,4,4,4,8,12,16")])
1fd4e8c1 8064\f
06f4e019
DE		 8065(define_expand "movtf"
8066 [(set (match_operand:TF 0 "general_operand" "")
8067 (match_operand:TF 1 "any_operand" ""))]
a3170dc6
AH		 8068 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8069 && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8070 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8071
8072(define_insn "*movtf_internal"
8073 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,m,!r,!r,!r")
8074 (match_operand:TF 1 "input_operand" "f,m,f,G,H,F"))]
a3170dc6
AH		 8075 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8076 && TARGET_LONG_DOUBLE_128
06f4e019
DE		 8077 && (gpc_reg_operand (operands[0], TFmode)
8078 || gpc_reg_operand (operands[1], TFmode))"
8079 "*
8080{
8081 switch (which_alternative)
8082 {
8083 default:
8084 abort ();
8085 case 0:
8086 /* We normally copy the low-numbered register first. However, if
8087 the first register operand 0 is the same as the second register of
8088 operand 1, we must copy in the opposite order. */
8089 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8090 return \"fmr %L0,%L1\;fmr %0,%1\";
8091 else
8092 return \"fmr %0,%1\;fmr %L0,%L1\";
8093 case 1:
f5264b52 8094 return \"lfd %0,%1\;lfd %L0,%Y1\";
06f4e019 8095 case 2:
f5264b52 8096 return \"stfd %1,%0\;stfd %L1,%Y0\";
06f4e019
DE		 8097 case 3:
8098 case 4:
8099 case 5:
8100 return \"#\";
8101 }
8102}"
8103 [(set_attr "type" "fp,fpload,fpstore,*,*,*")
8104 (set_attr "length" "8,8,8,12,16,20")])
8105
8106(define_split
8107 [(set (match_operand:TF 0 "gpc_reg_operand" "")
f5264b52 8108 (match_operand:TF 1 "easy_fp_constant" ""))]
fcce224d
DE		 8109 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8110 && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_POWERPC64
8111 && TARGET_LONG_DOUBLE_128 && reload_completed
8112 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8113 || (GET_CODE (operands[0]) == SUBREG
8114 && GET_CODE (SUBREG_REG (operands[0])) == REG
8115 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8116 [(set (match_dup 2) (match_dup 6))
8117 (set (match_dup 3) (match_dup 7))
8118 (set (match_dup 4) (match_dup 8))
8119 (set (match_dup 5) (match_dup 9))]
8120 "
8121{
8122 long l[4];
8123 REAL_VALUE_TYPE rv;
8124
8125 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8126 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l);
8127
8128 operands[2] = operand_subword (operands[0], 0, 0, TFmode);
8129 operands[3] = operand_subword (operands[0], 1, 0, TFmode);
8130 operands[4] = operand_subword (operands[0], 2, 0, TFmode);
8131 operands[5] = operand_subword (operands[0], 3, 0, TFmode);
8132 operands[6] = gen_int_mode (l[0], SImode);
8133 operands[7] = gen_int_mode (l[1], SImode);
8134 operands[8] = gen_int_mode (l[2], SImode);
8135 operands[9] = gen_int_mode (l[3], SImode);
8136}")
8137
8138(define_split
8139 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8140 (match_operand:TF 1 "easy_fp_constant" ""))]
8141 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8142 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
8143 && TARGET_LONG_DOUBLE_128 && reload_completed
8144 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8145 || (GET_CODE (operands[0]) == SUBREG
8146 && GET_CODE (SUBREG_REG (operands[0])) == REG
8147 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8148 [(set (match_dup 2) (match_dup 4))
8149 (set (match_dup 3) (match_dup 5))]
06f4e019
DE		 8150 "
8151{
fcce224d
DE		 8152 long l[4];
8153 REAL_VALUE_TYPE rv;
d24652ee 8154#if HOST_BITS_PER_WIDE_INT >= 64
f5264b52 8155 HOST_WIDE_INT val;
d24652ee 8156#endif
fcce224d
DE		 8157
8158 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8159 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l);
8160
f5264b52
DE		 8161 operands[2] = gen_lowpart (DImode, operands[0]);
8162 operands[3] = gen_highpart (DImode, operands[0]);
8163#if HOST_BITS_PER_WIDE_INT >= 64
a2419b96
DE		 8164 val = ((HOST_WIDE_INT)(unsigned long)l[0] << 32
8165 | ((HOST_WIDE_INT)(unsigned long)l[1]));
f5264b52
DE		 8166 operands[4] = gen_int_mode (val, DImode);
8167
a2419b96
DE		 8168 val = ((HOST_WIDE_INT)(unsigned long)l[2] << 32
8169 | ((HOST_WIDE_INT)(unsigned long)l[3]));
f5264b52
DE		 8170 operands[5] = gen_int_mode (val, DImode);
8171#else
8172 operands[4] = immed_double_const (l[1], l[0], DImode);
8173 operands[5] = immed_double_const (l[3], l[2], DImode);
8174#endif
06f4e019
DE		 8175}")
8176
a2419b96 8177(define_insn "extenddftf2"
06f4e019
DE		 8178 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8179 (float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6
AH		 8180 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8181 && TARGET_LONG_DOUBLE_128"
a2419b96 8182 "*
06f4e019 8183{
a2419b96
DE		 8184 if (REGNO (operands[0]) == REGNO (operands[1]))
8185 return \"fsub %L0,%L0,%L0\";
8186 else
8187 return \"fmr %0,%1\;fsub %L0,%L0,%L0\";
8188}"
8189 [(set_attr "type" "fp")])
06f4e019 8190
a2419b96 8191(define_insn "extendsftf2"
06f4e019
DE		 8192 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8193 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6
AH		 8194 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8195 && TARGET_LONG_DOUBLE_128"
a2419b96 8196 "*
06f4e019 8197{
a2419b96
DE		 8198 if (REGNO (operands[0]) == REGNO (operands[1]))
8199 return \"fsub %L0,%L0,%L0\";
8200 else
8201 return \"fmr %0,%1\;fsub %L0,%L0,%L0\";
8202}"
8203 [(set_attr "type" "fp")])
06f4e019
DE		 8204
8205(define_insn "trunctfdf2"
8206 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8207 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
a3170dc6
AH		 8208 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8209 && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8210 "fadd %0,%1,%L1"
8211 [(set_attr "type" "fp")
8212 (set_attr "length" "8")])
8213
8214(define_insn_and_split "trunctfsf2"
8215 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
ea112fc4
DE		 8216 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8217 (clobber (match_scratch:DF 2 "=f"))]
a3170dc6
AH		 8218 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT
8219 && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8220 "#"
ea112fc4 8221 "&& reload_completed"
06f4e019
DE		 8222 [(set (match_dup 2)
8223 (float_truncate:DF (match_dup 1)))
8224 (set (match_dup 0)
8225 (float_truncate:SF (match_dup 2)))]
ea112fc4 8226 "")
06f4e019 8227
ea112fc4
DE		 8228(define_insn_and_split "floatditf2"
8229 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
61c07d3c 8230 (float:TF (match_operand:DI 1 "gpc_reg_operand" "*f")))
ea112fc4
DE		 8231 (clobber (match_scratch:DF 2 "=f"))]
8232 "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
a3170dc6 8233 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ea112fc4
DE		 8234 "#"
8235 "&& reload_completed"
06f4e019 8236 [(set (match_dup 2)
a2419b96
DE		 8237 (float:DF (match_dup 1)))
8238 (set (match_dup 0)
06f4e019 8239 (float_extend:TF (match_dup 2)))]
ea112fc4 8240 "")
06f4e019 8241
ea112fc4
DE		 8242(define_insn_and_split "floatsitf2"
8243 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
61c07d3c 8244 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))
ea112fc4 8245 (clobber (match_scratch:DF 2 "=f"))]
a3170dc6
AH		 8246 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8247 && TARGET_LONG_DOUBLE_128"
ea112fc4
DE		 8248 "#"
8249 "&& reload_completed"
06f4e019 8250 [(set (match_dup 2)
a2419b96
DE		 8251 (float:DF (match_dup 1)))
8252 (set (match_dup 0)
06f4e019 8253 (float_extend:TF (match_dup 2)))]
ea112fc4 8254 "")
06f4e019 8255
ea112fc4 8256(define_insn_and_split "fix_trunctfdi2"
61c07d3c 8257 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
a2419b96
DE		 8258 (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))
8259 (clobber (match_scratch:DF 2 "=f"))]
ea112fc4 8260 "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
a3170dc6 8261 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ea112fc4
DE		 8262 "#"
8263 "&& reload_completed"
06f4e019 8264 [(set (match_dup 2)
a2419b96
DE		 8265 (float_truncate:DF (match_dup 1)))
8266 (set (match_dup 0)
8267 (fix:DI (match_dup 2)))]
ea112fc4 8268 "")
06f4e019 8269
ea112fc4 8270(define_insn_and_split "fix_trunctfsi2"
61c07d3c 8271 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
a2419b96
DE		 8272 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8273 (clobber (match_scratch:DF 2 "=f"))]
a3170dc6
AH		 8274 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8275 && TARGET_LONG_DOUBLE_128"
ea112fc4
DE		 8276 "#"
8277 "&& reload_completed"
06f4e019 8278 [(set (match_dup 2)
a2419b96
DE		 8279 (float_truncate:DF (match_dup 1)))
8280 (set (match_dup 0)
06f4e019 8281 (fix:SI (match_dup 2)))]
ea112fc4 8282 "")
06f4e019
DE		 8283
8284(define_insn "negtf2"
8285 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8286 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
a3170dc6
AH		 8287 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8288 && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8289 "*
8290{
8291 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8292 return \"fneg %L0,%L1\;fneg %0,%1\";
8293 else
8294 return \"fneg %0,%1\;fneg %L0,%L1\";
8295}"
8296 [(set_attr "type" "fp")
8297 (set_attr "length" "8")])
8298
8299(define_insn "abstf2"
8300 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8301 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
a3170dc6
AH		 8302 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8303 && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8304 "*
8305{
8306 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8307 return \"fabs %L0,%L1\;fabs %0,%1\";
8308 else
8309 return \"fabs %0,%1\;fabs %L0,%L1\";
8310}"
8311 [(set_attr "type" "fp")
8312 (set_attr "length" "8")])
8313
8314(define_insn ""
8315 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8316 (neg:TF (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f"))))]
a3170dc6
AH		 8317 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8318 && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8319 "*
8320{
8321 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8322 return \"fnabs %L0,%L1\;fnabs %0,%1\";
8323 else
8324 return \"fnabs %0,%1\;fnabs %L0,%L1\";
8325}"
8326 [(set_attr "type" "fp")
8327 (set_attr "length" "8")])
8328\f
1fd4e8c1
RK		 8329;; Next come the multi-word integer load and store and the load and store
8330;; multiple insns.
8331(define_expand "movdi"
8332 [(set (match_operand:DI 0 "general_operand" "")
e6ca2c17 8333 (match_operand:DI 1 "any_operand" ""))]
1fd4e8c1 8334 ""
fb4d4348 8335 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
1fd4e8c1 8336
acad7ed3 8337(define_insn "*movdi_internal32"
4e74d8ec
MM		 8338 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
8339 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
a260abc9 8340 "! TARGET_POWERPC64
4e74d8ec
MM		 8341 && (gpc_reg_operand (operands[0], DImode)
8342 || gpc_reg_operand (operands[1], DImode))"
1fd4e8c1
RK		 8343 "*
8344{
8345 switch (which_alternative)
8346 {
a260abc9 8347 default:
a6c2a102 8348 abort ();
1fd4e8c1
RK		 8349 case 0:
8350 /* We normally copy the low-numbered register first. However, if
8351 the first register operand 0 is the same as the second register of
8352 operand 1, we must copy in the opposite order. */
8353 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
deb9225a 8354 return \"mr %L0,%L1\;mr %0,%1\";
1fd4e8c1 8355 else
deb9225a 8356 return \"mr %0,%1\;mr %L0,%L1\";
1fd4e8c1
RK		 8357 case 1:
8358 /* If the low-address word is used in the address, we must load it
8359 last. Otherwise, load it first. Note that we cannot have
8360 auto-increment in that case since the address register is known to be
8361 dead. */
8362 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3cb999d8 8363 operands[1], 0))
ca7f5001 8364 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
1fd4e8c1 8365 else
ca7f5001 8366 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
1fd4e8c1 8367 case 2:
ca7f5001 8368 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8ffd9c51
RK		 8369 case 3:
8370 return \"fmr %0,%1\";
8371 case 4:
8372 return \"lfd%U1%X1 %0,%1\";
8373 case 5:
8374 return \"stfd%U0%X0 %1,%0\";
4e74d8ec
MM		 8375 case 6:
8376 case 7:
8377 case 8:
8378 case 9:
8379 case 10:
8380 return \"#\";
1fd4e8c1
RK		 8381 }
8382}"
4e74d8ec 8383 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
914a7297 8384 (set_attr "length" "8,8,8,4,4,4,8,12,8,12,16")])
4e74d8ec
MM		 8385
8386(define_split
8387 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8388 (match_operand:DI 1 "const_int_operand" ""))]
a260abc9 8389 "! TARGET_POWERPC64 && reload_completed"
4e74d8ec
MM		 8390 [(set (match_dup 2) (match_dup 4))
8391 (set (match_dup 3) (match_dup 1))]
8392 "
8393{
5f59ecb7 8394 HOST_WIDE_INT value = INTVAL (operands[1]);
bdaa0181
GK		 8395 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8396 DImode);
8397 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8398 DImode);
75d39459 8399#if HOST_BITS_PER_WIDE_INT == 32
5f59ecb7 8400 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
75d39459 8401#else
5f59ecb7 8402 operands[4] = GEN_INT (value >> 32);
a65c591c 8403 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
75d39459 8404#endif
4e74d8ec
MM		 8405}")
8406
4e74d8ec
MM		 8407(define_split
8408 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8409 (match_operand:DI 1 "const_double_operand" ""))]
75d39459 8410 "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed"
4e74d8ec
MM		 8411 [(set (match_dup 2) (match_dup 4))
8412 (set (match_dup 3) (match_dup 5))]
8413 "
8414{
bdaa0181
GK		 8415 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8416 DImode);
8417 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8418 DImode);
f6968f59
MM		 8419 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8420 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4e74d8ec
MM		 8421}")
8422
6fc19dc9
AM		 8423(define_split
8424 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8425 (match_operand:TI 1 "const_double_operand" ""))]
8426 "TARGET_POWERPC64"
8427 [(set (match_dup 2) (match_dup 4))
8428 (set (match_dup 3) (match_dup 5))]
8429 "
8430{
8431 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8432 TImode);
8433 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8434 TImode);
8435 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8436 {
8437 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8438 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8439 }
8440 else if (GET_CODE (operands[1]) == CONST_INT)
8441 {
8442 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8443 operands[5] = operands[1];
8444 }
8445 else
8446 FAIL;
8447}")
8448
acad7ed3 8449(define_insn "*movdi_internal64"
5d7e6254 8450 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h")
9615f239 8451 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
a260abc9 8452 "TARGET_POWERPC64
4e74d8ec
MM		 8453 && (gpc_reg_operand (operands[0], DImode)
8454 || gpc_reg_operand (operands[1], DImode))"
51b8fc2c 8455 "@
3d5570cb
RK		 8456 mr %0,%1
8457 ld%U1%X1 %0,%1
96bb8ed3 8458 std%U0%X0 %1,%0
3d5570cb 8459 li %0,%1
802a0058 8460 lis %0,%v1
e6ca2c17 8461 #
aee86b38 8462 {cal|la} %0,%a1
3d5570cb
RK		 8463 fmr %0,%1
8464 lfd%U1%X1 %0,%1
8465 stfd%U0%X0 %1,%0
8466 mf%1 %0
08075ead 8467 mt%0 %1
e34eaae5 8468 {cror 0,0,0|nop}"
b7ff3d82 8469 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
e6ca2c17
DE		 8470 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8471
5f59ecb7 8472;; immediate value valid for a single instruction hiding in a const_double
a260abc9
DE		 8473(define_insn ""
8474 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8475 (match_operand:DI 1 "const_double_operand" "F"))]
5f59ecb7
DE		 8476 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8477 && GET_CODE (operands[1]) == CONST_DOUBLE
a260abc9
DE		 8478 && num_insns_constant (operands[1], DImode) == 1"
8479 "*
8480{
8481 return ((unsigned HOST_WIDE_INT)
8482 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8483 ? \"li %0,%1\" : \"lis %0,%v1\";
8484}")
8485
a260abc9
DE		 8486;; Generate all one-bits and clear left or right.
8487;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8488(define_split
8489 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8490 (match_operand:DI 1 "mask64_operand" ""))]
8491 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8492 [(set (match_dup 0) (const_int -1))
e6ca2c17 8493 (set (match_dup 0)
a260abc9
DE		 8494 (and:DI (rotate:DI (match_dup 0)
8495 (const_int 0))
8496 (match_dup 1)))]
8497 "")
8498
8499;; Split a load of a large constant into the appropriate five-instruction
8500;; sequence. Handle anything in a constant number of insns.
8501;; When non-easy constants can go in the TOC, this should use
8502;; easy_fp_constant predicate.
8503(define_split
8504 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 8505 (match_operand:DI 1 "const_int_operand" ""))]
8506 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8507 [(set (match_dup 0) (match_dup 2))
8508 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
e6ca2c17 8509 "
2bfcf297
DB		 8510{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8511
8512 if (tem == operands[0])
8513 DONE;
e8d791dd 8514 else
2bfcf297 8515 FAIL;
5f59ecb7 8516}")
e6ca2c17 8517
5f59ecb7
DE		 8518(define_split
8519 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 8520 (match_operand:DI 1 "const_double_operand" ""))]
8521 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8522 [(set (match_dup 0) (match_dup 2))
8523 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5f59ecb7 8524 "
2bfcf297
DB		 8525{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8526
8527 if (tem == operands[0])
8528 DONE;
8529 else
8530 FAIL;
e6ca2c17 8531}")
08075ead 8532
2bfcf297 8533;; Split a load of a large constant into the appropriate five-instruction
acad7ed3 8534(define_insn "*movdi_internal2"
9ebbca7d
GK		 8535 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
8536 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
08075ead 8537 (const_int 0)))
9ebbca7d 8538 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
08075ead 8539 "TARGET_POWERPC64"
9ebbca7d
GK		 8540 "@
8541 mr. %0,%1
8542 #"
8543 [(set_attr "type" "compare")
8544 (set_attr "length" "4,8")])
acad7ed3 8545
9ebbca7d
GK		 8546(define_split
8547 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8548 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8549 (const_int 0)))
8550 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8551 "TARGET_POWERPC64 && reload_completed"
8552 [(set (match_dup 0) (match_dup 1))
8553 (set (match_dup 2)
8554 (compare:CC (match_dup 0)
8555 (const_int 0)))]
8556 "")
acad7ed3 8557\f
1fd4e8c1
RK		 8558;; TImode is similar, except that we usually want to compute the address into
8559;; a register and use lsi/stsi (the exception is during reload). MQ is also
ca7f5001 8560;; clobbered in stsi for POWER, so we need a SCRATCH for it.
1fd4e8c1
RK		 8561(define_expand "movti"
8562 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8563 (match_operand:TI 1 "general_operand" ""))
8564 (clobber (scratch:SI))])]
7e69e155 8565 "TARGET_STRING || TARGET_POWERPC64"
fb4d4348 8566 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
1fd4e8c1
RK		 8567
8568;; We say that MQ is clobbered in the last alternative because the first
8569;; alternative would never get used otherwise since it would need a reload
8570;; while the 2nd alternative would not. We put memory cases first so they
8571;; are preferred. Otherwise, we'd try to reload the output instead of
8572;; giving the SCRATCH mq.
a260abc9 8573(define_insn "*movti_power"
e1469d0d 8574 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
1fd4e8c1
RK		 8575 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8576 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
7e69e155 8577 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca 8578 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
1fd4e8c1
RK		 8579 "*
8580{
8581 switch (which_alternative)
8582 {
dc4f83ca
MM		 8583 default:
8584 abort ();
8585
1fd4e8c1 8586 case 0:
ca7f5001 8587 return \"{stsi|stswi} %1,%P0,16\";
1fd4e8c1 8588 case 1:
ca7f5001 8589 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
1fd4e8c1
RK		 8590 case 2:
8591 /* Normally copy registers with lowest numbered register copied first.
8592 But copy in the other order if the first register of the output
8593 is the second, third, or fourth register in the input. */
8594 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
8595 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
deb9225a 8596 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
1fd4e8c1 8597 else
deb9225a 8598 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
1fd4e8c1
RK		 8599 case 3:
8600 /* If the address is not used in the output, we can use lsi. Otherwise,
8601 fall through to generating four loads. */
8602 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
ca7f5001 8603 return \"{lsi|lswi} %0,%P1,16\";
82e41834 8604 /* ... fall through ... */
1fd4e8c1
RK		 8605 case 4:
8606 /* If the address register is the same as the register for the lowest-
8607 addressed word, load it last. Similarly for the next two words.
8608 Otherwise load lowest address to highest. */
8609 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8610 operands[1], 0))
ca7f5001 8611 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
1fd4e8c1
RK		 8612 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
8613 REGNO (operands[0]) + 2, operands[1], 0))
ca7f5001 8614 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
1fd4e8c1
RK		 8615 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
8616 REGNO (operands[0]) + 3, operands[1], 0))
ca7f5001 8617 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
1fd4e8c1 8618 else
ca7f5001 8619 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
1fd4e8c1
RK		 8620 }
8621}"
b7ff3d82 8622 [(set_attr "type" "store,store,*,load,load")
914a7297 8623 (set_attr "length" "4,16,16,4,16")])
51b8fc2c 8624
a260abc9 8625(define_insn "*movti_string"
cd1d3445 8626 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
27dc0551 8627 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))]
0ad91047 8628 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca
MM		 8629 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8630 "*
8631{
8632 switch (which_alternative)
8633 {
8634 default:
8635 abort ();
8636
8637 case 0:
cd1d3445 8638 return \"{stsi|stswi} %1,%P0,16\";
dc4f83ca 8639 case 1:
cd1d3445
DE		 8640 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
8641 case 2:
dc4f83ca
MM		 8642 /* Normally copy registers with lowest numbered register copied first.
8643 But copy in the other order if the first register of the output
8644 is the second, third, or fourth register in the input. */
8645 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
8646 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
8647 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
8648 else
8649 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
cd1d3445
DE		 8650 case 3:
8651 /* If the address is not used in the output, we can use lsi. Otherwise,
8652 fall through to generating four loads. */
8653 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
8654 return \"{lsi|lswi} %0,%P1,16\";
8655 /* ... fall through ... */
8656 case 4:
dc4f83ca
MM		 8657 /* If the address register is the same as the register for the lowest-
8658 addressed word, load it last. Similarly for the next two words.
8659 Otherwise load lowest address to highest. */
8660 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8661 operands[1], 0))
8662 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
8663 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
8664 REGNO (operands[0]) + 2, operands[1], 0))
8665 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
8666 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
8667 REGNO (operands[0]) + 3, operands[1], 0))
8668 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
8669 else
8670 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
8671 }
8672}"
cd1d3445
DE		 8673 [(set_attr "type" "store,store,*,load,load")
8674 (set_attr "length" "4,16,16,4,16")])
dc4f83ca 8675
a260abc9 8676(define_insn "*movti_ppc64"
51b8fc2c
RK		 8677 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
8678 (match_operand:TI 1 "input_operand" "r,m,r"))]
8679 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8680 || gpc_reg_operand (operands[1], TImode))"
8681 "*
8682{
8683 switch (which_alternative)
8684 {
a260abc9 8685 default:
a6c2a102 8686 abort ();
51b8fc2c
RK		 8687 case 0:
8688 /* We normally copy the low-numbered register first. However, if
8689 the first register operand 0 is the same as the second register of
8690 operand 1, we must copy in the opposite order. */
8691 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8692 return \"mr %L0,%L1\;mr %0,%1\";
8693 else
8694 return \"mr %0,%1\;mr %L0,%L1\";
8695 case 1:
8696 /* If the low-address word is used in the address, we must load it
8697 last. Otherwise, load it first. Note that we cannot have
8698 auto-increment in that case since the address register is known to be
8699 dead. */
8700 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3cb999d8 8701 operands[1], 0))
51b8fc2c
RK		 8702 return \"ld %L0,%L1\;ld %0,%1\";
8703 else
8704 return \"ld%U1 %0,%1\;ld %L0,%L1\";
8705 case 2:
8706 return \"std%U0 %1,%0\;std %L1,%L0\";
8707 }
8708}"
b7ff3d82 8709 [(set_attr "type" "*,load,store")
51b8fc2c 8710 (set_attr "length" "8,8,8")])
1fd4e8c1
RK		 8711\f
8712(define_expand "load_multiple"
2f622005
RK		 8713 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8714 (match_operand:SI 1 "" ""))
8715 (use (match_operand:SI 2 "" ""))])]
09a625f7 8716 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 8717 "
8718{
8719 int regno;
8720 int count;
792760b9 8721 rtx op1;
1fd4e8c1
RK		 8722 int i;
8723
8724 /* Support only loading a constant number of fixed-point registers from
8725 memory and only bother with this if more than two; the machine
8726 doesn't support more than eight. */
8727 if (GET_CODE (operands[2]) != CONST_INT
8728 || INTVAL (operands[2]) <= 2
8729 || INTVAL (operands[2]) > 8
8730 || GET_CODE (operands[1]) != MEM
8731 || GET_CODE (operands[0]) != REG
8732 || REGNO (operands[0]) >= 32)
8733 FAIL;
8734
8735 count = INTVAL (operands[2]);
8736 regno = REGNO (operands[0]);
8737
39403d82 8738 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
792760b9
RK		 8739 op1 = replace_equiv_address (operands[1],
8740 force_reg (SImode, XEXP (operands[1], 0)));
1fd4e8c1
RK		 8741
8742 for (i = 0; i < count; i++)
8743 XVECEXP (operands[3], 0, i)
39403d82 8744 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
7ef788f0 8745 adjust_address_nv (op1, SImode, i * 4));
1fd4e8c1
RK		 8746}")
8747
9caa3eb2 8748(define_insn "*ldmsi8"
1fd4e8c1 8749 [(match_parallel 0 "load_multiple_operation"
9caa3eb2
DE		 8750 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8751 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8752 (set (match_operand:SI 3 "gpc_reg_operand" "")
8753 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8754 (set (match_operand:SI 4 "gpc_reg_operand" "")
8755 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8756 (set (match_operand:SI 5 "gpc_reg_operand" "")
8757 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8758 (set (match_operand:SI 6 "gpc_reg_operand" "")
8759 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8760 (set (match_operand:SI 7 "gpc_reg_operand" "")
8761 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8762 (set (match_operand:SI 8 "gpc_reg_operand" "")
8763 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8764 (set (match_operand:SI 9 "gpc_reg_operand" "")
8765 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8766 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
1fd4e8c1 8767 "*
9caa3eb2
DE		 8768{ return rs6000_output_load_multiple (operands); }"
8769 [(set_attr "type" "load")
8770 (set_attr "length" "32")])
1fd4e8c1 8771
9caa3eb2
DE		 8772(define_insn "*ldmsi7"
8773 [(match_parallel 0 "load_multiple_operation"
8774 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8775 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8776 (set (match_operand:SI 3 "gpc_reg_operand" "")
8777 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8778 (set (match_operand:SI 4 "gpc_reg_operand" "")
8779 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8780 (set (match_operand:SI 5 "gpc_reg_operand" "")
8781 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8782 (set (match_operand:SI 6 "gpc_reg_operand" "")
8783 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8784 (set (match_operand:SI 7 "gpc_reg_operand" "")
8785 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8786 (set (match_operand:SI 8 "gpc_reg_operand" "")
8787 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8788 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8789 "*
8790{ return rs6000_output_load_multiple (operands); }"
8791 [(set_attr "type" "load")
8792 (set_attr "length" "32")])
8793
8794(define_insn "*ldmsi6"
8795 [(match_parallel 0 "load_multiple_operation"
8796 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8797 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8798 (set (match_operand:SI 3 "gpc_reg_operand" "")
8799 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8800 (set (match_operand:SI 4 "gpc_reg_operand" "")
8801 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8802 (set (match_operand:SI 5 "gpc_reg_operand" "")
8803 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8804 (set (match_operand:SI 6 "gpc_reg_operand" "")
8805 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8806 (set (match_operand:SI 7 "gpc_reg_operand" "")
8807 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8808 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8809 "*
8810{ return rs6000_output_load_multiple (operands); }"
8811 [(set_attr "type" "load")
8812 (set_attr "length" "32")])
8813
8814(define_insn "*ldmsi5"
8815 [(match_parallel 0 "load_multiple_operation"
8816 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8817 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8818 (set (match_operand:SI 3 "gpc_reg_operand" "")
8819 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8820 (set (match_operand:SI 4 "gpc_reg_operand" "")
8821 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8822 (set (match_operand:SI 5 "gpc_reg_operand" "")
8823 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8824 (set (match_operand:SI 6 "gpc_reg_operand" "")
8825 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8826 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8827 "*
8828{ return rs6000_output_load_multiple (operands); }"
8829 [(set_attr "type" "load")
8830 (set_attr "length" "32")])
8831
8832(define_insn "*ldmsi4"
8833 [(match_parallel 0 "load_multiple_operation"
8834 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8835 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8836 (set (match_operand:SI 3 "gpc_reg_operand" "")
8837 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8838 (set (match_operand:SI 4 "gpc_reg_operand" "")
8839 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8840 (set (match_operand:SI 5 "gpc_reg_operand" "")
8841 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8842 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8843 "*
8844{ return rs6000_output_load_multiple (operands); }"
8845 [(set_attr "type" "load")
8846 (set_attr "length" "32")])
8847
8848(define_insn "*ldmsi3"
8849 [(match_parallel 0 "load_multiple_operation"
8850 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8851 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8852 (set (match_operand:SI 3 "gpc_reg_operand" "")
8853 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8854 (set (match_operand:SI 4 "gpc_reg_operand" "")
8855 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8856 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8857 "*
8858{ return rs6000_output_load_multiple (operands); }"
b19003d8 8859 [(set_attr "type" "load")
e82ee4cc 8860 (set_attr "length" "32")])
b19003d8 8861
1fd4e8c1 8862(define_expand "store_multiple"
2f622005
RK		 8863 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8864 (match_operand:SI 1 "" ""))
8865 (clobber (scratch:SI))
8866 (use (match_operand:SI 2 "" ""))])]
09a625f7 8867 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 8868 "
8869{
8870 int regno;
8871 int count;
8872 rtx to;
792760b9 8873 rtx op0;
1fd4e8c1
RK		 8874 int i;
8875
8876 /* Support only storing a constant number of fixed-point registers to
8877 memory and only bother with this if more than two; the machine
8878 doesn't support more than eight. */
8879 if (GET_CODE (operands[2]) != CONST_INT
8880 || INTVAL (operands[2]) <= 2
8881 || INTVAL (operands[2]) > 8
8882 || GET_CODE (operands[0]) != MEM
8883 || GET_CODE (operands[1]) != REG
8884 || REGNO (operands[1]) >= 32)
8885 FAIL;
8886
8887 count = INTVAL (operands[2]);
8888 regno = REGNO (operands[1]);
8889
39403d82 8890 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
1fd4e8c1 8891 to = force_reg (SImode, XEXP (operands[0], 0));
792760b9 8892 op0 = replace_equiv_address (operands[0], to);
1fd4e8c1
RK		 8893
8894 XVECEXP (operands[3], 0, 0)
7ef788f0 8895 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
39403d82 8896 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
c5c76735 8897 gen_rtx_SCRATCH (SImode));
1fd4e8c1
RK		 8898
8899 for (i = 1; i < count; i++)
8900 XVECEXP (operands[3], 0, i + 1)
39403d82 8901 = gen_rtx_SET (VOIDmode,
7ef788f0 8902 adjust_address_nv (op0, SImode, i * 4),
c5c76735 8903 gen_rtx_REG (SImode, regno + i));
1fd4e8c1
RK		 8904}")
8905
9caa3eb2 8906(define_insn "*store_multiple_power"
1fd4e8c1
RK		 8907 [(match_parallel 0 "store_multiple_operation"
8908 [(set (match_operand:SI 1 "indirect_operand" "=Q")
cd2b37d9 8909 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1 8910 (clobber (match_scratch:SI 3 "=q"))])]
7e69e155 8911 "TARGET_STRING && TARGET_POWER"
b7ff3d82
DE		 8912 "{stsi|stswi} %2,%P1,%O0"
8913 [(set_attr "type" "store")])
d14a6d05 8914
e46e3130 8915(define_insn "*stmsi8"
d14a6d05 8916 [(match_parallel 0 "store_multiple_operation"
e46e3130
DJ		 8917 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8918 (match_operand:SI 2 "gpc_reg_operand" "r"))
8919 (clobber (match_scratch:SI 3 "X"))
8920 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8921 (match_operand:SI 4 "gpc_reg_operand" "r"))
8922 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8923 (match_operand:SI 5 "gpc_reg_operand" "r"))
8924 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8925 (match_operand:SI 6 "gpc_reg_operand" "r"))
8926 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8927 (match_operand:SI 7 "gpc_reg_operand" "r"))
8928 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8929 (match_operand:SI 8 "gpc_reg_operand" "r"))
8930 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8931 (match_operand:SI 9 "gpc_reg_operand" "r"))
8932 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8933 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8934 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8935 "{stsi|stswi} %2,%1,%O0"
8936 [(set_attr "type" "store")])
8937
8938(define_insn "*stmsi7"
8939 [(match_parallel 0 "store_multiple_operation"
8940 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8941 (match_operand:SI 2 "gpc_reg_operand" "r"))
8942 (clobber (match_scratch:SI 3 "X"))
8943 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8944 (match_operand:SI 4 "gpc_reg_operand" "r"))
8945 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8946 (match_operand:SI 5 "gpc_reg_operand" "r"))
8947 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8948 (match_operand:SI 6 "gpc_reg_operand" "r"))
8949 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8950 (match_operand:SI 7 "gpc_reg_operand" "r"))
8951 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8952 (match_operand:SI 8 "gpc_reg_operand" "r"))
8953 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8954 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8955 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8956 "{stsi|stswi} %2,%1,%O0"
8957 [(set_attr "type" "store")])
8958
8959(define_insn "*stmsi6"
8960 [(match_parallel 0 "store_multiple_operation"
8961 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8962 (match_operand:SI 2 "gpc_reg_operand" "r"))
8963 (clobber (match_scratch:SI 3 "X"))
8964 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8965 (match_operand:SI 4 "gpc_reg_operand" "r"))
8966 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8967 (match_operand:SI 5 "gpc_reg_operand" "r"))
8968 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8969 (match_operand:SI 6 "gpc_reg_operand" "r"))
8970 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8971 (match_operand:SI 7 "gpc_reg_operand" "r"))
8972 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8973 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8974 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8975 "{stsi|stswi} %2,%1,%O0"
8976 [(set_attr "type" "store")])
8977
8978(define_insn "*stmsi5"
8979 [(match_parallel 0 "store_multiple_operation"
8980 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8981 (match_operand:SI 2 "gpc_reg_operand" "r"))
8982 (clobber (match_scratch:SI 3 "X"))
8983 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8984 (match_operand:SI 4 "gpc_reg_operand" "r"))
8985 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8986 (match_operand:SI 5 "gpc_reg_operand" "r"))
8987 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8988 (match_operand:SI 6 "gpc_reg_operand" "r"))
8989 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8990 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8991 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8992 "{stsi|stswi} %2,%1,%O0"
8993 [(set_attr "type" "store")])
8994
8995(define_insn "*stmsi4"
8996 [(match_parallel 0 "store_multiple_operation"
8997 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8998 (match_operand:SI 2 "gpc_reg_operand" "r"))
8999 (clobber (match_scratch:SI 3 "X"))
9000 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9001 (match_operand:SI 4 "gpc_reg_operand" "r"))
9002 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9003 (match_operand:SI 5 "gpc_reg_operand" "r"))
9004 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9005 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9006 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
b7ff3d82
DE		 9007 "{stsi|stswi} %2,%1,%O0"
9008 [(set_attr "type" "store")])
7e69e155 9009
e46e3130
DJ		 9010(define_insn "*stmsi3"
9011 [(match_parallel 0 "store_multiple_operation"
9012 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9013 (match_operand:SI 2 "gpc_reg_operand" "r"))
9014 (clobber (match_scratch:SI 3 "X"))
9015 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9016 (match_operand:SI 4 "gpc_reg_operand" "r"))
9017 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9018 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9019 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9020 "{stsi|stswi} %2,%1,%O0"
9021 [(set_attr "type" "store")])
7e69e155
MM		 9022\f
9023;; String/block move insn.
9024;; Argument 0 is the destination
9025;; Argument 1 is the source
9026;; Argument 2 is the length
9027;; Argument 3 is the alignment
9028
9029(define_expand "movstrsi"
b6c9286a
MM		 9030 [(parallel [(set (match_operand:BLK 0 "" "")
9031 (match_operand:BLK 1 "" ""))
9032 (use (match_operand:SI 2 "" ""))
9033 (use (match_operand:SI 3 "" ""))])]
7e69e155
MM		 9034 ""
9035 "
9036{
9037 if (expand_block_move (operands))
9038 DONE;
9039 else
9040 FAIL;
9041}")
9042
9043;; Move up to 32 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9044;; register allocator doesn't have a clue about allocating 8 word registers.
9045;; rD/rS = r5 is preferred, efficient form.
7e69e155 9046(define_expand "movstrsi_8reg"
b6c9286a
MM		 9047 [(parallel [(set (match_operand 0 "" "")
9048 (match_operand 1 "" ""))
9049 (use (match_operand 2 "" ""))
9050 (use (match_operand 3 "" ""))
7e69e155
MM		 9051 (clobber (reg:SI 5))
9052 (clobber (reg:SI 6))
9053 (clobber (reg:SI 7))
9054 (clobber (reg:SI 8))
9055 (clobber (reg:SI 9))
9056 (clobber (reg:SI 10))
9057 (clobber (reg:SI 11))
9058 (clobber (reg:SI 12))
3c67b673 9059 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9060 "TARGET_STRING"
9061 "")
9062
9063(define_insn ""
52d3af72
DE		 9064 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9065 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9066 (use (match_operand:SI 2 "immediate_operand" "i"))
9067 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9068 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9069 (clobber (reg:SI 6))
9070 (clobber (reg:SI 7))
9071 (clobber (reg:SI 8))
9072 (clobber (reg:SI 9))
9073 (clobber (reg:SI 10))
9074 (clobber (reg:SI 11))
9075 (clobber (reg:SI 12))
3c67b673 9076 (clobber (match_scratch:SI 5 "=q"))]
7e69e155 9077 "TARGET_STRING && TARGET_POWER
f9562f27
DE		 9078 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9079 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9080 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9081 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9082 && REGNO (operands[4]) == 5"
9083 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9084 [(set_attr "type" "load")
9085 (set_attr "length" "8")])
7e69e155
MM		 9086
9087(define_insn ""
52d3af72
DE		 9088 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9089 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9090 (use (match_operand:SI 2 "immediate_operand" "i"))
9091 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9092 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9093 (clobber (reg:SI 6))
9094 (clobber (reg:SI 7))
9095 (clobber (reg:SI 8))
9096 (clobber (reg:SI 9))
9097 (clobber (reg:SI 10))
9098 (clobber (reg:SI 11))
9099 (clobber (reg:SI 12))
3c67b673 9100 (clobber (match_scratch:SI 5 "X"))]
0ad91047 9101 "TARGET_STRING && ! TARGET_POWER
f9562f27
DE		 9102 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9103 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9104 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9105 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9106 && REGNO (operands[4]) == 5"
9107 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9108 [(set_attr "type" "load")
9109 (set_attr "length" "8")])
7e69e155 9110
09a625f7
TR		 9111(define_insn ""
9112 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9113 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9114 (use (match_operand:SI 2 "immediate_operand" "i"))
9115 (use (match_operand:SI 3 "immediate_operand" "i"))
9116 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9117 (clobber (reg:SI 6))
9118 (clobber (reg:SI 7))
9119 (clobber (reg:SI 8))
9120 (clobber (reg:SI 9))
9121 (clobber (reg:SI 10))
9122 (clobber (reg:SI 11))
9123 (clobber (reg:SI 12))
9124 (clobber (match_scratch:SI 5 "X"))]
9125 "TARGET_STRING && TARGET_POWERPC64
9126 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9127 || INTVAL (operands[2]) == 0)
9128 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9129 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9130 && REGNO (operands[4]) == 5"
9131 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9132 [(set_attr "type" "load")
9133 (set_attr "length" "8")])
9134
7e69e155 9135;; Move up to 24 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9136;; register allocator doesn't have a clue about allocating 6 word registers.
9137;; rD/rS = r5 is preferred, efficient form.
7e69e155 9138(define_expand "movstrsi_6reg"
b6c9286a
MM		 9139 [(parallel [(set (match_operand 0 "" "")
9140 (match_operand 1 "" ""))
9141 (use (match_operand 2 "" ""))
9142 (use (match_operand 3 "" ""))
f9562f27
DE		 9143 (clobber (reg:SI 5))
9144 (clobber (reg:SI 6))
7e69e155
MM		 9145 (clobber (reg:SI 7))
9146 (clobber (reg:SI 8))
9147 (clobber (reg:SI 9))
9148 (clobber (reg:SI 10))
3c67b673 9149 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9150 "TARGET_STRING"
9151 "")
9152
9153(define_insn ""
52d3af72
DE		 9154 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9155 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9156 (use (match_operand:SI 2 "immediate_operand" "i"))
9157 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9158 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9159 (clobber (reg:SI 6))
9160 (clobber (reg:SI 7))
7e69e155
MM		 9161 (clobber (reg:SI 8))
9162 (clobber (reg:SI 9))
9163 (clobber (reg:SI 10))
3c67b673 9164 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9165 "TARGET_STRING && TARGET_POWER
9166 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
f9562f27
DE		 9167 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9168 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9169 && REGNO (operands[4]) == 5"
3c67b673 9170 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9171 [(set_attr "type" "load")
9172 (set_attr "length" "8")])
7e69e155
MM		 9173
9174(define_insn ""
52d3af72
DE		 9175 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9176 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9177 (use (match_operand:SI 2 "immediate_operand" "i"))
9178 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9179 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9180 (clobber (reg:SI 6))
9181 (clobber (reg:SI 7))
7e69e155
MM		 9182 (clobber (reg:SI 8))
9183 (clobber (reg:SI 9))
9184 (clobber (reg:SI 10))
3c67b673 9185 (clobber (match_scratch:SI 5 "X"))]
0ad91047 9186 "TARGET_STRING && ! TARGET_POWER
7e69e155 9187 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
f9562f27
DE		 9188 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9189 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9190 && REGNO (operands[4]) == 5"
3c67b673 9191 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9192 [(set_attr "type" "load")
9193 (set_attr "length" "8")])
7e69e155 9194
09a625f7
TR		 9195(define_insn ""
9196 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9197 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9198 (use (match_operand:SI 2 "immediate_operand" "i"))
9199 (use (match_operand:SI 3 "immediate_operand" "i"))
9200 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9201 (clobber (reg:SI 6))
9202 (clobber (reg:SI 7))
9203 (clobber (reg:SI 8))
9204 (clobber (reg:SI 9))
9205 (clobber (reg:SI 10))
9206 (clobber (match_scratch:SI 5 "X"))]
9207 "TARGET_STRING && TARGET_POWERPC64
9208 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9209 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9210 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9211 && REGNO (operands[4]) == 5"
9212 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9213 [(set_attr "type" "load")
9214 (set_attr "length" "8")])
9215
f9562f27
DE		 9216;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9217;; problems with TImode.
9218;; rD/rS = r5 is preferred, efficient form.
7e69e155 9219(define_expand "movstrsi_4reg"
b6c9286a
MM		 9220 [(parallel [(set (match_operand 0 "" "")
9221 (match_operand 1 "" ""))
9222 (use (match_operand 2 "" ""))
9223 (use (match_operand 3 "" ""))
f9562f27
DE		 9224 (clobber (reg:SI 5))
9225 (clobber (reg:SI 6))
9226 (clobber (reg:SI 7))
9227 (clobber (reg:SI 8))
3c67b673 9228 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9229 "TARGET_STRING"
9230 "")
9231
9232(define_insn ""
52d3af72
DE		 9233 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9234 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9235 (use (match_operand:SI 2 "immediate_operand" "i"))
9236 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9237 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9238 (clobber (reg:SI 6))
9239 (clobber (reg:SI 7))
9240 (clobber (reg:SI 8))
3c67b673 9241 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9242 "TARGET_STRING && TARGET_POWER
9243 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9244 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9245 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9246 && REGNO (operands[4]) == 5"
3c67b673 9247 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9248 [(set_attr "type" "load")
9249 (set_attr "length" "8")])
7e69e155
MM		 9250
9251(define_insn ""
52d3af72
DE		 9252 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9253 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9254 (use (match_operand:SI 2 "immediate_operand" "i"))
9255 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9256 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9257 (clobber (reg:SI 6))
9258 (clobber (reg:SI 7))
9259 (clobber (reg:SI 8))
3c67b673 9260 (clobber (match_scratch:SI 5 "X"))]
0ad91047 9261 "TARGET_STRING && ! TARGET_POWER
7e69e155 9262 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9263 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9264 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9265 && REGNO (operands[4]) == 5"
3c67b673 9266 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9267 [(set_attr "type" "load")
9268 (set_attr "length" "8")])
7e69e155 9269
09a625f7
TR		 9270(define_insn ""
9271 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9272 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9273 (use (match_operand:SI 2 "immediate_operand" "i"))
9274 (use (match_operand:SI 3 "immediate_operand" "i"))
9275 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9276 (clobber (reg:SI 6))
9277 (clobber (reg:SI 7))
9278 (clobber (reg:SI 8))
9279 (clobber (match_scratch:SI 5 "X"))]
9280 "TARGET_STRING && TARGET_POWERPC64
9281 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9282 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9283 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9284 && REGNO (operands[4]) == 5"
9285 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9286 [(set_attr "type" "load")
9287 (set_attr "length" "8")])
9288
7e69e155
MM		 9289;; Move up to 8 bytes at a time.
9290(define_expand "movstrsi_2reg"
b6c9286a
MM		 9291 [(parallel [(set (match_operand 0 "" "")
9292 (match_operand 1 "" ""))
9293 (use (match_operand 2 "" ""))
9294 (use (match_operand 3 "" ""))
3c67b673
RK		 9295 (clobber (match_scratch:DI 4 ""))
9296 (clobber (match_scratch:SI 5 ""))])]
f9562f27 9297 "TARGET_STRING && ! TARGET_POWERPC64"
7e69e155
MM		 9298 "")
9299
9300(define_insn ""
52d3af72
DE		 9301 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9302 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9303 (use (match_operand:SI 2 "immediate_operand" "i"))
9304 (use (match_operand:SI 3 "immediate_operand" "i"))
9305 (clobber (match_scratch:DI 4 "=&r"))
9306 (clobber (match_scratch:SI 5 "=q"))]
f9562f27 9307 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
3c67b673
RK		 9308 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9309 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9310 [(set_attr "type" "load")
9311 (set_attr "length" "8")])
7e69e155
MM		 9312
9313(define_insn ""
52d3af72
DE		 9314 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9315 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9316 (use (match_operand:SI 2 "immediate_operand" "i"))
9317 (use (match_operand:SI 3 "immediate_operand" "i"))
9318 (clobber (match_scratch:DI 4 "=&r"))
9319 (clobber (match_scratch:SI 5 "X"))]
f9562f27 9320 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
7e69e155 9321 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
3c67b673 9322 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9323 [(set_attr "type" "load")
9324 (set_attr "length" "8")])
7e69e155
MM		 9325
9326;; Move up to 4 bytes at a time.
9327(define_expand "movstrsi_1reg"
b6c9286a
MM		 9328 [(parallel [(set (match_operand 0 "" "")
9329 (match_operand 1 "" ""))
9330 (use (match_operand 2 "" ""))
9331 (use (match_operand 3 "" ""))
3c67b673
RK		 9332 (clobber (match_scratch:SI 4 ""))
9333 (clobber (match_scratch:SI 5 ""))])]
7e69e155
MM		 9334 "TARGET_STRING"
9335 "")
9336
9337(define_insn ""
52d3af72
DE		 9338 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9339 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9340 (use (match_operand:SI 2 "immediate_operand" "i"))
9341 (use (match_operand:SI 3 "immediate_operand" "i"))
9342 (clobber (match_scratch:SI 4 "=&r"))
9343 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9344 "TARGET_STRING && TARGET_POWER
9345 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
3c67b673 9346 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9347 [(set_attr "type" "load")
9348 (set_attr "length" "8")])
7e69e155
MM		 9349
9350(define_insn ""
52d3af72
DE		 9351 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9352 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9353 (use (match_operand:SI 2 "immediate_operand" "i"))
9354 (use (match_operand:SI 3 "immediate_operand" "i"))
9355 (clobber (match_scratch:SI 4 "=&r"))
9356 (clobber (match_scratch:SI 5 "X"))]
0ad91047 9357 "TARGET_STRING && ! TARGET_POWER
7e69e155 9358 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
09a625f7
TR		 9359 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9360 [(set_attr "type" "load")
9361 (set_attr "length" "8")])
9362
9363(define_insn ""
9364 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9365 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9366 (use (match_operand:SI 2 "immediate_operand" "i"))
9367 (use (match_operand:SI 3 "immediate_operand" "i"))
9368 (clobber (match_scratch:SI 4 "=&r"))
9369 (clobber (match_scratch:SI 5 "X"))]
9370 "TARGET_STRING && TARGET_POWERPC64
9371 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
3c67b673 9372 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9373 [(set_attr "type" "load")
9374 (set_attr "length" "8")])
7e69e155 9375
1fd4e8c1 9376\f
7e69e155 9377;; Define insns that do load or store with update. Some of these we can
1fd4e8c1
RK		 9378;; get by using pre-decrement or pre-increment, but the hardware can also
9379;; do cases where the increment is not the size of the object.
9380;;
9381;; In all these cases, we use operands 0 and 1 for the register being
9382;; incremented because those are the operands that local-alloc will
9383;; tie and these are the pair most likely to be tieable (and the ones
9384;; that will benefit the most).
9385
38c1f2d7 9386(define_insn "*movdi_update1"
51b8fc2c 9387 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
ad8bd902 9388 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
768070a0 9389 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
51b8fc2c
RK		 9390 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9391 (plus:DI (match_dup 1) (match_dup 2)))]
38c1f2d7 9392 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9393 "@
9394 ldux %3,%0,%2
9395 ldu %3,%2(%0)"
b54cf83a 9396 [(set_attr "type" "load_ux,load_u")])
287f13ff 9397
4697a36c 9398(define_insn "movdi_update"
51b8fc2c 9399 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
768070a0 9400 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
51b8fc2c
RK		 9401 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9402 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9403 (plus:DI (match_dup 1) (match_dup 2)))]
38c1f2d7 9404 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9405 "@
9406 stdux %3,%0,%2
b7ff3d82 9407 stdu %3,%2(%0)"
b54cf83a 9408 [(set_attr "type" "store_ux,store_u")])
51b8fc2c 9409
38c1f2d7 9410(define_insn "*movsi_update1"
cd2b37d9
RK		 9411 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9412 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9413 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9414 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9415 (plus:SI (match_dup 1) (match_dup 2)))]
f7b3ab8a 9416 "TARGET_UPDATE"
1fd4e8c1 9417 "@
ca7f5001
RK		 9418 {lux|lwzux} %3,%0,%2
9419 {lu|lwzu} %3,%2(%0)"
b54cf83a
DE		 9420 [(set_attr "type" "load_ux,load_u")])
9421
9422(define_insn "*movsi_update2"
9423 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9424 (sign_extend:DI
9425 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9426 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9427 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9428 (plus:DI (match_dup 1) (match_dup 2)))]
9429 "TARGET_POWERPC64"
9430 "lwaux %3,%0,%2"
9431 [(set_attr "type" "load_ext_ux")])
1fd4e8c1 9432
4697a36c 9433(define_insn "movsi_update"
cd2b37d9 9434 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9435 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9436 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9437 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9438 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9439 "TARGET_UPDATE"
1fd4e8c1 9440 "@
ca7f5001 9441 {stux|stwux} %3,%0,%2
b7ff3d82 9442 {stu|stwu} %3,%2(%0)"
b54cf83a 9443 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9444
b54cf83a 9445(define_insn "*movhi_update1"
cd2b37d9
RK		 9446 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9447 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9448 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9449 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9450 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9451 "TARGET_UPDATE"
1fd4e8c1 9452 "@
5f243543
RK		 9453 lhzux %3,%0,%2
9454 lhzu %3,%2(%0)"
b54cf83a 9455 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9456
38c1f2d7 9457(define_insn "*movhi_update2"
cd2b37d9 9458 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9459 (zero_extend:SI
cd2b37d9 9460 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9461 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9462 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9463 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9464 "TARGET_UPDATE"
1fd4e8c1 9465 "@
5f243543
RK		 9466 lhzux %3,%0,%2
9467 lhzu %3,%2(%0)"
b54cf83a 9468 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9469
38c1f2d7 9470(define_insn "*movhi_update3"
cd2b37d9 9471 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9472 (sign_extend:SI
cd2b37d9 9473 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9474 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9475 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9476 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9477 "TARGET_UPDATE"
1fd4e8c1 9478 "@
5f243543
RK		 9479 lhaux %3,%0,%2
9480 lhau %3,%2(%0)"
b54cf83a 9481 [(set_attr "type" "load_ext_ux,load_ext_u")])
1fd4e8c1 9482
38c1f2d7 9483(define_insn "*movhi_update4"
cd2b37d9 9484 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9485 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9486 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9487 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9488 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9489 "TARGET_UPDATE"
1fd4e8c1 9490 "@
5f243543 9491 sthux %3,%0,%2
b7ff3d82 9492 sthu %3,%2(%0)"
b54cf83a 9493 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9494
38c1f2d7 9495(define_insn "*movqi_update1"
cd2b37d9
RK		 9496 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9497 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9498 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9499 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9500 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9501 "TARGET_UPDATE"
1fd4e8c1 9502 "@
5f243543
RK		 9503 lbzux %3,%0,%2
9504 lbzu %3,%2(%0)"
b54cf83a 9505 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9506
38c1f2d7 9507(define_insn "*movqi_update2"
cd2b37d9 9508 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9509 (zero_extend:SI
cd2b37d9 9510 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9511 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9512 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9513 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9514 "TARGET_UPDATE"
1fd4e8c1 9515 "@
5f243543
RK		 9516 lbzux %3,%0,%2
9517 lbzu %3,%2(%0)"
b54cf83a 9518 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9519
38c1f2d7 9520(define_insn "*movqi_update3"
cd2b37d9 9521 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9522 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9523 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9524 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9525 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9526 "TARGET_UPDATE"
1fd4e8c1 9527 "@
5f243543 9528 stbux %3,%0,%2
b7ff3d82 9529 stbu %3,%2(%0)"
b54cf83a 9530 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9531
38c1f2d7 9532(define_insn "*movsf_update1"
cd2b37d9 9533 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
df8b713c 9534 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9535 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9536 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9537 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9538 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 9539 "@
5f243543
RK		 9540 lfsux %3,%0,%2
9541 lfsu %3,%2(%0)"
b54cf83a 9542 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 9543
38c1f2d7 9544(define_insn "*movsf_update2"
cd2b37d9 9545 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9546 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9547 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9548 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9549 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9550 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 9551 "@
85fff2f3 9552 stfsux %3,%0,%2
b7ff3d82 9553 stfsu %3,%2(%0)"
b54cf83a 9554 [(set_attr "type" "fpstore_ux,fpstore_u")])
1fd4e8c1 9555
38c1f2d7
MM		 9556(define_insn "*movsf_update3"
9557 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9558 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9559 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9560 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9561 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9562 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 9563 "@
9564 {lux|lwzux} %3,%0,%2
9565 {lu|lwzu} %3,%2(%0)"
b54cf83a 9566 [(set_attr "type" "load_ux,load_u")])
38c1f2d7
MM		 9567
9568(define_insn "*movsf_update4"
9569 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9570 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9571 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9572 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9573 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9574 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 9575 "@
9576 {stux|stwux} %3,%0,%2
9577 {stu|stwu} %3,%2(%0)"
b54cf83a 9578 [(set_attr "type" "store_ux,store_u")])
38c1f2d7
MM		 9579
9580(define_insn "*movdf_update1"
cd2b37d9
RK		 9581 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9582 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9583 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9584 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9585 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9586 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 9587 "@
5f243543
RK		 9588 lfdux %3,%0,%2
9589 lfdu %3,%2(%0)"
b54cf83a 9590 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 9591
38c1f2d7 9592(define_insn "*movdf_update2"
cd2b37d9 9593 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9594 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9595 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9596 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9597 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9598 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 9599 "@
5f243543 9600 stfdux %3,%0,%2
b7ff3d82 9601 stfdu %3,%2(%0)"
b54cf83a 9602 [(set_attr "type" "fpstore_ux,fpstore_u")])
4c70a4f3
RK		 9603
9604;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9605
9606(define_peephole
9607 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
9608 (match_operand:DF 1 "memory_operand" ""))
9609 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
9610 (match_operand:DF 3 "memory_operand" ""))]
9611 "TARGET_POWER2
a3170dc6 9612 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3
RK		 9613 && registers_ok_for_quad_peep (operands[0], operands[2])
9614 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
9615 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
9616 "lfq%U1%X1 %0,%1")
9617
9618(define_peephole
9619 [(set (match_operand:DF 0 "memory_operand" "")
9620 (match_operand:DF 1 "gpc_reg_operand" "f"))
9621 (set (match_operand:DF 2 "memory_operand" "")
9622 (match_operand:DF 3 "gpc_reg_operand" "f"))]
9623 "TARGET_POWER2
a3170dc6 9624 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3
RK		 9625 && registers_ok_for_quad_peep (operands[1], operands[3])
9626 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
9627 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
9628 "stfq%U0%X0 %1,%0")
1fd4e8c1
RK		 9629\f
9630;; Next come insns related to the calling sequence.
9631;;
9632;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
7e69e155 9633;; We move the back-chain and decrement the stack pointer.
1fd4e8c1
RK		 9634
9635(define_expand "allocate_stack"
52d3af72 9636 [(set (match_operand 0 "gpc_reg_operand" "=r")
a260abc9
DE		 9637 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9638 (set (reg 1)
9639 (minus (reg 1) (match_dup 1)))]
1fd4e8c1
RK		 9640 ""
9641 "
4697a36c 9642{ rtx chain = gen_reg_rtx (Pmode);
39403d82 9643 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
4697a36c 9644 rtx neg_op0;
1fd4e8c1
RK		 9645
9646 emit_move_insn (chain, stack_bot);
4697a36c 9647
a157febd
GK		 9648 /* Check stack bounds if necessary. */
9649 if (current_function_limit_stack)
9650 {
9651 rtx available;
9652 available = expand_binop (Pmode, sub_optab,
9653 stack_pointer_rtx, stack_limit_rtx,
9654 NULL_RTX, 1, OPTAB_WIDEN);
9655 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9656 }
9657
e9a25f70
JL		 9658 if (GET_CODE (operands[1]) != CONST_INT
9659 || INTVAL (operands[1]) < -32767
9660 || INTVAL (operands[1]) > 32768)
4697a36c
MM		 9661 {
9662 neg_op0 = gen_reg_rtx (Pmode);
e6ca2c17 9663 if (TARGET_32BIT)
e9a25f70 9664 emit_insn (gen_negsi2 (neg_op0, operands[1]));
e6ca2c17 9665 else
e9a25f70 9666 emit_insn (gen_negdi2 (neg_op0, operands[1]));
4697a36c
MM		 9667 }
9668 else
e9a25f70 9669 neg_op0 = GEN_INT (- INTVAL (operands[1]));
4697a36c 9670
38c1f2d7
MM		 9671 if (TARGET_UPDATE)
9672 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
9673 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
4697a36c 9674
38c1f2d7
MM		 9675 else
9676 {
9677 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9678 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
39403d82 9679 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
38c1f2d7 9680 }
e9a25f70
JL		 9681
9682 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
1fd4e8c1
RK		 9683 DONE;
9684}")
59257ff7
RK		 9685
9686;; These patterns say how to save and restore the stack pointer. We need not
9687;; save the stack pointer at function level since we are careful to
9688;; preserve the backchain. At block level, we have to restore the backchain
9689;; when we restore the stack pointer.
9690;;
9691;; For nonlocal gotos, we must save both the stack pointer and its
9692;; backchain and restore both. Note that in the nonlocal case, the
9693;; save area is a memory location.
9694
9695(define_expand "save_stack_function"
ff381587
MM		 9696 [(match_operand 0 "any_operand" "")
9697 (match_operand 1 "any_operand" "")]
59257ff7 9698 ""
ff381587 9699 "DONE;")
59257ff7
RK		 9700
9701(define_expand "restore_stack_function"
ff381587
MM		 9702 [(match_operand 0 "any_operand" "")
9703 (match_operand 1 "any_operand" "")]
59257ff7 9704 ""
ff381587 9705 "DONE;")
59257ff7
RK		 9706
9707(define_expand "restore_stack_block"
dfdfa60f
DE		 9708 [(use (match_operand 0 "register_operand" ""))
9709 (set (match_dup 2) (match_dup 3))
a260abc9 9710 (set (match_dup 0) (match_operand 1 "register_operand" ""))
dfdfa60f 9711 (set (match_dup 3) (match_dup 2))]
59257ff7
RK		 9712 ""
9713 "
dfdfa60f
DE		 9714{
9715 operands[2] = gen_reg_rtx (Pmode);
39403d82 9716 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
dfdfa60f 9717}")
59257ff7
RK		 9718
9719(define_expand "save_stack_nonlocal"
a260abc9
DE		 9720 [(match_operand 0 "memory_operand" "")
9721 (match_operand 1 "register_operand" "")]
59257ff7
RK		 9722 ""
9723 "
9724{
a260abc9 9725 rtx temp = gen_reg_rtx (Pmode);
59257ff7
RK		 9726
9727 /* Copy the backchain to the first word, sp to the second. */
39403d82 9728 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
c5c76735
JL		 9729 emit_move_insn (operand_subword (operands[0], 0, 0,
9730 (TARGET_32BIT ? DImode : TImode)),
a260abc9
DE		 9731 temp);
9732 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)),
9733 operands[1]);
59257ff7
RK		 9734 DONE;
9735}")
7e69e155 9736
59257ff7 9737(define_expand "restore_stack_nonlocal"
a260abc9
DE		 9738 [(match_operand 0 "register_operand" "")
9739 (match_operand 1 "memory_operand" "")]
59257ff7
RK		 9740 ""
9741 "
9742{
a260abc9 9743 rtx temp = gen_reg_rtx (Pmode);
59257ff7
RK		 9744
9745 /* Restore the backchain from the first word, sp from the second. */
a260abc9
DE		 9746 emit_move_insn (temp,
9747 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode)));
9748 emit_move_insn (operands[0],
c5c76735
JL		 9749 operand_subword (operands[1], 1, 0,
9750 (TARGET_32BIT ? DImode : TImode)));
39403d82 9751 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
59257ff7
RK		 9752 DONE;
9753}")
9ebbca7d
GK		 9754\f
9755;; TOC register handling.
b6c9286a 9756
9ebbca7d 9757;; Code to initialize the TOC register...
f0f6a223 9758
9ebbca7d 9759(define_insn "load_toc_aix_si"
e72247f4 9760 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
46aaf10d
DE		 9761 (unspec:SI [(const_int 0)] 7))
9762 (use (reg:SI 2))])]
2bfcf297 9763 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
f0f6a223
RK		 9764 "*
9765{
9ebbca7d
GK		 9766 char buf[30];
9767 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
a8a05998 9768 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 9769 operands[2] = gen_rtx_REG (Pmode, 2);
9770 return \"{l|lwz} %0,%1(%2)\";
f0f6a223
RK		 9771}"
9772 [(set_attr "type" "load")])
9ebbca7d
GK		 9773
9774(define_insn "load_toc_aix_di"
e72247f4 9775 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
46aaf10d
DE		 9776 (unspec:DI [(const_int 0)] 7))
9777 (use (reg:DI 2))])]
2bfcf297 9778 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9ebbca7d
GK		 9779 "*
9780{
9781 char buf[30];
f585a356
DE		 9782#ifdef TARGET_RELOCATABLE
9783 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9784 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9785#else
9ebbca7d 9786 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
f585a356 9787#endif
2bfcf297
DB		 9788 if (TARGET_ELF)
9789 strcat (buf, \"@toc\");
a8a05998 9790 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 9791 operands[2] = gen_rtx_REG (Pmode, 2);
9792 return \"ld %0,%1(%2)\";
9793}"
9794 [(set_attr "type" "load")])
9795
9796(define_insn "load_toc_v4_pic_si"
9797 [(set (match_operand:SI 0 "register_operand" "=l")
9798 (unspec:SI [(const_int 0)] 7))]
f607bc57 9799 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9ebbca7d
GK		 9800 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9801 [(set_attr "type" "branch")
9802 (set_attr "length" "4")])
9803
9ebbca7d
GK		 9804(define_insn "load_toc_v4_PIC_1"
9805 [(set (match_operand:SI 0 "register_operand" "=l")
9806 (match_operand:SI 1 "immediate_operand" "s"))
9807 (unspec [(match_dup 1)] 7)]
20b71b17 9808 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
df7a8989 9809 "bcl 20,31,%1\\n%1:"
9ebbca7d
GK		 9810 [(set_attr "type" "branch")
9811 (set_attr "length" "4")])
9812
9813(define_insn "load_toc_v4_PIC_1b"
9814 [(set (match_operand:SI 0 "register_operand" "=l")
9815 (match_operand:SI 1 "immediate_operand" "s"))
9816 (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)]
20b71b17 9817 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
df7a8989 9818 "bcl 20,31,%1\\n\\t.long %2-%1+4\\n%1:"
9ebbca7d
GK		 9819 [(set_attr "type" "branch")
9820 (set_attr "length" "8")])
9821
9822(define_insn "load_toc_v4_PIC_2"
f585a356 9823 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
a2900460 9824 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9ebbca7d
GK		 9825 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9826 (match_operand:SI 3 "immediate_operand" "s")))))]
20b71b17 9827 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9ebbca7d
GK		 9828 "{l|lwz} %0,%2-%3(%1)"
9829 [(set_attr "type" "load")])
9830
ee890fe2
SS		 9831(define_insn "load_macho_picbase"
9832 [(set (match_operand:SI 0 "register_operand" "=l")
f51eee6a 9833 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] 15))]
ee890fe2 9834 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
f51eee6a 9835 "bcl 20,31,%1\\n%1:"
ee890fe2
SS		 9836 [(set_attr "type" "branch")
9837 (set_attr "length" "4")])
9838
f51eee6a
GK		 9839(define_insn "macho_correct_pic"
9840 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9841 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "=r")
9842 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
9843 (match_operand:SI 3 "immediate_operand" "s")]
9844 16)))]
9845 "DEFAULT_ABI == ABI_DARWIN"
9846 "addis %0,%1,ha16(%2-%3)\n\taddi %1,%1,lo16(%2-%3)"
9847 [(set_attr "length" "8")])
9848
9ebbca7d
GK		 9849;; If the TOC is shared over a translation unit, as happens with all
9850;; the kinds of PIC that we support, we need to restore the TOC
9851;; pointer only when jumping over units of translation.
f51eee6a 9852;; On Darwin, we need to reload the picbase.
9ebbca7d
GK		 9853
9854(define_expand "builtin_setjmp_receiver"
9855 [(use (label_ref (match_operand 0 "" "")))]
f607bc57 9856 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
f51eee6a
GK		 9857 || (TARGET_TOC && TARGET_MINIMAL_TOC)
9858 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9ebbca7d
GK		 9859 "
9860{
84d7dd4a 9861#if TARGET_MACHO
f51eee6a
GK		 9862 if (DEFAULT_ABI == ABI_DARWIN)
9863 {
d24652ee 9864 const char *picbase = machopic_function_base_name ();
f51eee6a
GK		 9865 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1));
9866 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
9867 rtx tmplabrtx;
9868 char tmplab[20];
9869
9870 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
9871 CODE_LABEL_NUMBER (operands[0]));
9872 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (tmplab, -1));
9873
9874 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
9875 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
9876 }
9877 else
84d7dd4a 9878#endif
f51eee6a 9879 rs6000_emit_load_toc_table (FALSE);
9ebbca7d
GK		 9880 DONE;
9881}")
9882\f
9883;; A function pointer under AIX is a pointer to a data area whose first word
9884;; contains the actual address of the function, whose second word contains a
b6c9286a
MM		 9885;; pointer to its TOC, and whose third word contains a value to place in the
9886;; static chain register (r11). Note that if we load the static chain, our
1fd4e8c1 9887;; "trampoline" need not have any executable code.
b6c9286a 9888
cccf3bdc
DE		 9889(define_expand "call_indirect_aix32"
9890 [(set (match_dup 2)
9891 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9892 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9893 (reg:SI 2))
9894 (set (reg:SI 2)
9895 (mem:SI (plus:SI (match_dup 0)
9896 (const_int 4))))
9897 (set (reg:SI 11)
9898 (mem:SI (plus:SI (match_dup 0)
9899 (const_int 8))))
9900 (parallel [(call (mem:SI (match_dup 2))
9901 (match_operand 1 "" ""))
9902 (use (reg:SI 2))
9903 (use (reg:SI 11))
9904 (set (reg:SI 2)
9905 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9906 (clobber (scratch:SI))])]
9907 "TARGET_32BIT"
9908 "
9909{ operands[2] = gen_reg_rtx (SImode); }")
b6c9286a 9910
cccf3bdc
DE		 9911(define_expand "call_indirect_aix64"
9912 [(set (match_dup 2)
9913 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9914 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9915 (reg:DI 2))
9916 (set (reg:DI 2)
9917 (mem:DI (plus:DI (match_dup 0)
9918 (const_int 8))))
9919 (set (reg:DI 11)
9920 (mem:DI (plus:DI (match_dup 0)
9921 (const_int 16))))
9922 (parallel [(call (mem:SI (match_dup 2))
9923 (match_operand 1 "" ""))
9924 (use (reg:DI 2))
9925 (use (reg:DI 11))
9926 (set (reg:DI 2)
9927 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9928 (clobber (scratch:SI))])]
9929 "TARGET_64BIT"
9930 "
9931{ operands[2] = gen_reg_rtx (DImode); }")
b6c9286a 9932
cccf3bdc
DE		 9933(define_expand "call_value_indirect_aix32"
9934 [(set (match_dup 3)
9935 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9936 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9937 (reg:SI 2))
9938 (set (reg:SI 2)
9939 (mem:SI (plus:SI (match_dup 1)
9940 (const_int 4))))
9941 (set (reg:SI 11)
9942 (mem:SI (plus:SI (match_dup 1)
9943 (const_int 8))))
9944 (parallel [(set (match_operand 0 "" "")
9945 (call (mem:SI (match_dup 3))
9946 (match_operand 2 "" "")))
9947 (use (reg:SI 2))
9948 (use (reg:SI 11))
9949 (set (reg:SI 2)
9950 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9951 (clobber (scratch:SI))])]
9952 "TARGET_32BIT"
9953 "
9954{ operands[3] = gen_reg_rtx (SImode); }")
b6c9286a 9955
cccf3bdc
DE		 9956(define_expand "call_value_indirect_aix64"
9957 [(set (match_dup 3)
9958 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9959 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9960 (reg:DI 2))
9961 (set (reg:DI 2)
9962 (mem:DI (plus:DI (match_dup 1)
9963 (const_int 8))))
9964 (set (reg:DI 11)
9965 (mem:DI (plus:DI (match_dup 1)
9966 (const_int 16))))
9967 (parallel [(set (match_operand 0 "" "")
9968 (call (mem:SI (match_dup 3))
9969 (match_operand 2 "" "")))
9970 (use (reg:DI 2))
9971 (use (reg:DI 11))
9972 (set (reg:DI 2)
9973 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9974 (clobber (scratch:SI))])]
9975 "TARGET_64BIT"
9976 "
9977{ operands[3] = gen_reg_rtx (DImode); }")
1fd4e8c1 9978
b6c9286a 9979;; Now the definitions for the call and call_value insns
1fd4e8c1 9980(define_expand "call"
a260abc9 9981 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
1fd4e8c1 9982 (match_operand 1 "" ""))
4697a36c 9983 (use (match_operand 2 "" ""))
1fd4e8c1
RK		 9984 (clobber (scratch:SI))])]
9985 ""
9986 "
9987{
ee890fe2
SS		 9988#if TARGET_MACHO
9989 if (flag_pic)
9990 operands[0] = machopic_indirect_call_target (operands[0]);
9991#endif
9992
1fd4e8c1
RK		 9993 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
9994 abort ();
9995
9996 operands[0] = XEXP (operands[0], 0);
7509c759 9997
6a4cee5f
MM		 9998 if (GET_CODE (operands[0]) != SYMBOL_REF
9999 || (INTVAL (operands[2]) & CALL_LONG) != 0)
1fd4e8c1 10000 {
6a4cee5f
MM		 10001 if (INTVAL (operands[2]) & CALL_LONG)
10002 operands[0] = rs6000_longcall_ref (operands[0]);
10003
cccf3bdc
DE		 10004 if (DEFAULT_ABI == ABI_V4
10005 || DEFAULT_ABI == ABI_AIX_NODESC
f607bc57 10006 || DEFAULT_ABI == ABI_DARWIN)
cccf3bdc 10007 operands[0] = force_reg (Pmode, operands[0]);
1fd4e8c1 10008
cccf3bdc
DE		 10009 else if (DEFAULT_ABI == ABI_AIX)
10010 {
10011 /* AIX function pointers are really pointers to a three word
10012 area. */
10013 emit_call_insn (TARGET_32BIT
10014 ? gen_call_indirect_aix32 (force_reg (SImode,
10015 operands[0]),
10016 operands[1])
10017 : gen_call_indirect_aix64 (force_reg (DImode,
10018 operands[0]),
10019 operands[1]));
10020 DONE;
b6c9286a 10021 }
cccf3bdc
DE		 10022 else
10023 abort ();
1fd4e8c1
RK		 10024 }
10025}")
10026
10027(define_expand "call_value"
10028 [(parallel [(set (match_operand 0 "" "")
a260abc9 10029 (call (mem:SI (match_operand 1 "address_operand" ""))
1fd4e8c1 10030 (match_operand 2 "" "")))
4697a36c 10031 (use (match_operand 3 "" ""))
1fd4e8c1
RK		 10032 (clobber (scratch:SI))])]
10033 ""
10034 "
10035{
ee890fe2
SS		 10036#if TARGET_MACHO
10037 if (flag_pic)
10038 operands[1] = machopic_indirect_call_target (operands[1]);
10039#endif
10040
1fd4e8c1
RK		 10041 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10042 abort ();
10043
10044 operands[1] = XEXP (operands[1], 0);
7509c759 10045
6a4cee5f
MM		 10046 if (GET_CODE (operands[1]) != SYMBOL_REF
10047 || (INTVAL (operands[3]) & CALL_LONG) != 0)
1fd4e8c1 10048 {
6756293c 10049 if (INTVAL (operands[3]) & CALL_LONG)
6a4cee5f
MM		 10050 operands[1] = rs6000_longcall_ref (operands[1]);
10051
cccf3bdc
DE		 10052 if (DEFAULT_ABI == ABI_V4
10053 || DEFAULT_ABI == ABI_AIX_NODESC
f607bc57 10054 || DEFAULT_ABI == ABI_DARWIN)
cccf3bdc 10055 operands[0] = force_reg (Pmode, operands[0]);
1fd4e8c1 10056
cccf3bdc
DE		 10057 else if (DEFAULT_ABI == ABI_AIX)
10058 {
10059 /* AIX function pointers are really pointers to a three word
10060 area. */
10061 emit_call_insn (TARGET_32BIT
10062 ? gen_call_value_indirect_aix32 (operands[0],
10063 force_reg (SImode,
10064 operands[1]),
10065 operands[2])
10066 : gen_call_value_indirect_aix64 (operands[0],
10067 force_reg (DImode,
10068 operands[1]),
10069 operands[2]));
10070 DONE;
b6c9286a 10071 }
cccf3bdc
DE		 10072 else
10073 abort ();
1fd4e8c1
RK		 10074 }
10075}")
10076
04780ee7 10077;; Call to function in current module. No TOC pointer reload needed.
a0ab749a 10078;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10079;; either the function was not prototyped, or it was prototyped as a
10080;; variable argument function. It is > 0 if FP registers were passed
10081;; and < 0 if they were not.
04780ee7 10082
a260abc9 10083(define_insn "*call_local32"
4697a36c
MM		 10084 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10085 (match_operand 1 "" "g,g"))
10086 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10087 (clobber (match_scratch:SI 3 "=l,l"))]
5a19791c 10088 "(INTVAL (operands[2]) & CALL_LONG) == 0"
4697a36c
MM		 10089 "*
10090{
6a4cee5f
MM		 10091 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10092 output_asm_insn (\"crxor 6,6,6\", operands);
10093
10094 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10095 output_asm_insn (\"creqv 6,6,6\", operands);
4697a36c 10096
a226df46 10097 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
4697a36c 10098}"
b7ff3d82
DE		 10099 [(set_attr "type" "branch")
10100 (set_attr "length" "4,8")])
04780ee7 10101
a260abc9
DE		 10102(define_insn "*call_local64"
10103 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10104 (match_operand 1 "" "g,g"))
10105 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10106 (clobber (match_scratch:SI 3 "=l,l"))]
10107 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10108 "*
10109{
10110 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10111 output_asm_insn (\"crxor 6,6,6\", operands);
10112
10113 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10114 output_asm_insn (\"creqv 6,6,6\", operands);
10115
10116 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10117}"
10118 [(set_attr "type" "branch")
10119 (set_attr "length" "4,8")])
10120
cccf3bdc 10121(define_insn "*call_value_local32"
d18dba68 10122 [(set (match_operand 0 "" "")
a260abc9
DE		 10123 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10124 (match_operand 2 "" "g,g")))
10125 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10126 (clobber (match_scratch:SI 4 "=l,l"))]
10127 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10128 "*
10129{
10130 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10131 output_asm_insn (\"crxor 6,6,6\", operands);
10132
10133 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10134 output_asm_insn (\"creqv 6,6,6\", operands);
10135
10136 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10137}"
10138 [(set_attr "type" "branch")
10139 (set_attr "length" "4,8")])
10140
10141
cccf3bdc 10142(define_insn "*call_value_local64"
d18dba68 10143 [(set (match_operand 0 "" "")
a260abc9
DE		 10144 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10145 (match_operand 2 "" "g,g")))
10146 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10147 (clobber (match_scratch:SI 4 "=l,l"))]
10148 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10149 "*
10150{
10151 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10152 output_asm_insn (\"crxor 6,6,6\", operands);
10153
10154 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10155 output_asm_insn (\"creqv 6,6,6\", operands);
10156
10157 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10158}"
10159 [(set_attr "type" "branch")
10160 (set_attr "length" "4,8")])
10161
04780ee7 10162;; Call to function which may be in another module. Restore the TOC
911f679c 10163;; pointer (r2) after the call unless this is System V.
a0ab749a 10164;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10165;; either the function was not prototyped, or it was prototyped as a
10166;; variable argument function. It is > 0 if FP registers were passed
10167;; and < 0 if they were not.
04780ee7 10168
cccf3bdc
DE		 10169(define_insn "*call_indirect_nonlocal_aix32"
10170 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10171 (match_operand 1 "" "g"))
10172 (use (reg:SI 2))
10173 (use (reg:SI 11))
10174 (set (reg:SI 2)
10175 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
c77e04ae 10176 (clobber (match_scratch:SI 2 "=l"))]
cccf3bdc
DE		 10177 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10178 "b%T0l\;{l|lwz} 2,20(1)"
10179 [(set_attr "type" "jmpreg")
10180 (set_attr "length" "8")])
10181
a260abc9 10182(define_insn "*call_nonlocal_aix32"
cc4d5fec 10183 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10184 (match_operand 1 "" "g"))
10185 (use (match_operand:SI 2 "immediate_operand" "O"))
10186 (clobber (match_scratch:SI 3 "=l"))]
10187 "TARGET_32BIT
10188 && DEFAULT_ABI == ABI_AIX
5a19791c 10189 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 10190 "bl %z0\;%."
b7ff3d82 10191 [(set_attr "type" "branch")
cccf3bdc
DE		 10192 (set_attr "length" "8")])
10193
10194(define_insn "*call_indirect_nonlocal_aix64"
10195 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10196 (match_operand 1 "" "g"))
10197 (use (reg:DI 2))
10198 (use (reg:DI 11))
10199 (set (reg:DI 2)
10200 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
c77e04ae 10201 (clobber (match_scratch:SI 2 "=l"))]
cccf3bdc
DE		 10202 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10203 "b%T0l\;ld 2,40(1)"
10204 [(set_attr "type" "jmpreg")
10205 (set_attr "length" "8")])
59313e4e 10206
a260abc9 10207(define_insn "*call_nonlocal_aix64"
cc4d5fec 10208 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10209 (match_operand 1 "" "g"))
10210 (use (match_operand:SI 2 "immediate_operand" "O"))
10211 (clobber (match_scratch:SI 3 "=l"))]
9ebbca7d
GK		 10212 "TARGET_64BIT
10213 && DEFAULT_ABI == ABI_AIX
a260abc9 10214 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 10215 "bl %z0\;%."
a260abc9 10216 [(set_attr "type" "branch")
cccf3bdc 10217 (set_attr "length" "8")])
7509c759 10218
cccf3bdc 10219(define_insn "*call_value_indirect_nonlocal_aix32"
d18dba68 10220 [(set (match_operand 0 "" "")
cccf3bdc
DE		 10221 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10222 (match_operand 2 "" "g")))
10223 (use (reg:SI 2))
10224 (use (reg:SI 11))
10225 (set (reg:SI 2)
10226 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10227 (clobber (match_scratch:SI 3 "=l"))]
10228 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10229 "b%T1l\;{l|lwz} 2,20(1)"
10230 [(set_attr "type" "jmpreg")
10231 (set_attr "length" "8")])
1fd4e8c1 10232
cccf3bdc 10233(define_insn "*call_value_nonlocal_aix32"
d18dba68 10234 [(set (match_operand 0 "" "")
cc4d5fec 10235 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10236 (match_operand 2 "" "g")))
10237 (use (match_operand:SI 3 "immediate_operand" "O"))
10238 (clobber (match_scratch:SI 4 "=l"))]
10239 "TARGET_32BIT
10240 && DEFAULT_ABI == ABI_AIX
a260abc9 10241 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc 10242 "bl %z1\;%."
b7ff3d82 10243 [(set_attr "type" "branch")
cccf3bdc 10244 (set_attr "length" "8")])
04780ee7 10245
cccf3bdc 10246(define_insn "*call_value_indirect_nonlocal_aix64"
d18dba68 10247 [(set (match_operand 0 "" "")
cccf3bdc
DE		 10248 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10249 (match_operand 2 "" "g")))
10250 (use (reg:DI 2))
10251 (use (reg:DI 11))
10252 (set (reg:DI 2)
10253 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10254 (clobber (match_scratch:SI 3 "=l"))]
10255 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10256 "b%T1l\;ld 2,40(1)"
10257 [(set_attr "type" "jmpreg")
10258 (set_attr "length" "8")])
10259
10260(define_insn "*call_value_nonlocal_aix64"
d18dba68 10261 [(set (match_operand 0 "" "")
cc4d5fec 10262 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10263 (match_operand 2 "" "g")))
10264 (use (match_operand:SI 3 "immediate_operand" "O"))
10265 (clobber (match_scratch:SI 4 "=l"))]
9ebbca7d
GK		 10266 "TARGET_64BIT
10267 && DEFAULT_ABI == ABI_AIX
5a19791c 10268 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc
DE		 10269 "bl %z1\;%."
10270 [(set_attr "type" "branch")
10271 (set_attr "length" "8")])
10272
10273;; A function pointer under System V is just a normal pointer
10274;; operands[0] is the function pointer
10275;; operands[1] is the stack size to clean up
10276;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10277;; which indicates how to set cr1
10278
a5c76ee6
ZW		 10279(define_insn "*call_indirect_nonlocal_sysv"
10280 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10281 (match_operand 1 "" "g,g"))
10282 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10283 (clobber (match_scratch:SI 3 "=l,l"))]
cccf3bdc
DE		 10284 "DEFAULT_ABI == ABI_AIX_NODESC
10285 || DEFAULT_ABI == ABI_V4
f607bc57 10286 || DEFAULT_ABI == ABI_DARWIN"
911f679c 10287{
cccf3bdc 10288 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 10289 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f 10290
cccf3bdc 10291 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 10292 output_asm_insn ("creqv 6,6,6", operands);
7509c759 10293
a5c76ee6
ZW		 10294 return "b%T0l";
10295}
10296 [(set_attr "type" "jmpreg,jmpreg")
10297 (set_attr "length" "4,8")])
cccf3bdc 10298
a5c76ee6
ZW		 10299(define_insn "*call_nonlocal_sysv"
10300 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10301 (match_operand 1 "" "g,g"))
10302 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10303 (clobber (match_scratch:SI 3 "=l,l"))]
10304 "(DEFAULT_ABI == ABI_AIX_NODESC
10305 || DEFAULT_ABI == ABI_V4
10306 || DEFAULT_ABI == ABI_DARWIN)
10307 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10308{
10309 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10310 output_asm_insn ("crxor 6,6,6", operands);
10311
10312 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10313 output_asm_insn ("creqv 6,6,6", operands);
10314
10315 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10316}
10317 [(set_attr "type" "branch,branch")
10318 (set_attr "length" "4,8")])
10319
10320(define_insn "*call_value_indirect_nonlocal_sysv"
d18dba68 10321 [(set (match_operand 0 "" "")
a5c76ee6
ZW		 10322 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10323 (match_operand 2 "" "g,g")))
10324 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10325 (clobber (match_scratch:SI 4 "=l,l"))]
cccf3bdc
DE		 10326 "DEFAULT_ABI == ABI_AIX_NODESC
10327 || DEFAULT_ABI == ABI_V4
f607bc57 10328 || DEFAULT_ABI == ABI_DARWIN"
b6c9286a 10329{
6a4cee5f 10330 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 10331 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f
MM		 10332
10333 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 10334 output_asm_insn ("creqv 6,6,6", operands);
7509c759 10335
a5c76ee6
ZW		 10336 return "b%T1l";
10337}
10338 [(set_attr "type" "jmpreg,jmpreg")
10339 (set_attr "length" "4,8")])
10340
10341(define_insn "*call_value_nonlocal_sysv"
10342 [(set (match_operand 0 "" "")
10343 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10344 (match_operand 2 "" "g,g")))
10345 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10346 (clobber (match_scratch:SI 4 "=l,l"))]
10347 "(DEFAULT_ABI == ABI_AIX_NODESC
10348 || DEFAULT_ABI == ABI_V4
10349 || DEFAULT_ABI == ABI_DARWIN)
10350 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10351{
10352 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10353 output_asm_insn ("crxor 6,6,6", operands);
10354
10355 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10356 output_asm_insn ("creqv 6,6,6", operands);
10357
10358 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10359}
10360 [(set_attr "type" "branch,branch")
10361 (set_attr "length" "4,8")])
e6f948e3
RK		 10362
10363;; Call subroutine returning any type.
e6f948e3
RK		 10364(define_expand "untyped_call"
10365 [(parallel [(call (match_operand 0 "" "")
10366 (const_int 0))
10367 (match_operand 1 "" "")
10368 (match_operand 2 "" "")])]
10369 ""
10370 "
10371{
10372 int i;
10373
7d70b8b2 10374 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
e6f948e3
RK		 10375
10376 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10377 {
10378 rtx set = XVECEXP (operands[2], 0, i);
10379 emit_move_insn (SET_DEST (set), SET_SRC (set));
10380 }
10381
10382 /* The optimizer does not know that the call sets the function value
10383 registers we stored in the result block. We avoid problems by
10384 claiming that all hard registers are used and clobbered at this
10385 point. */
10386 emit_insn (gen_blockage ());
10387
10388 DONE;
10389}")
10390
5e1bf043
DJ		 10391;; sibling call patterns
10392(define_expand "sibcall"
10393 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10394 (match_operand 1 "" ""))
10395 (use (match_operand 2 "" ""))
fe352c29 10396 (use (match_operand 3 "" ""))
5e1bf043
DJ		 10397 (return)])]
10398 ""
10399 "
10400{
10401#if TARGET_MACHO
10402 if (flag_pic)
10403 operands[0] = machopic_indirect_call_target (operands[0]);
10404#endif
10405
10406 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10407 abort ();
10408
10409 operands[0] = XEXP (operands[0], 0);
fe352c29 10410 operands[3] = gen_reg_rtx (SImode);
5e1bf043
DJ		 10411
10412}")
10413
10414;; this and similar patterns must be marked as using LR, otherwise
10415;; dataflow will try to delete the store into it. This is true
10416;; even when the actual reg to jump to is in CTR, when LR was
10417;; saved and restored around the PIC-setting BCL.
10418(define_insn "*sibcall_local32"
10419 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10420 (match_operand 1 "" "g,g"))
10421 (use (match_operand:SI 2 "immediate_operand" "O,n"))
fe352c29 10422 (use (match_operand:SI 3 "register_operand" "l,l"))
5e1bf043
DJ		 10423 (return)]
10424 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10425 "*
10426{
10427 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10428 output_asm_insn (\"crxor 6,6,6\", operands);
10429
10430 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10431 output_asm_insn (\"creqv 6,6,6\", operands);
10432
10433 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10434}"
10435 [(set_attr "type" "branch")
10436 (set_attr "length" "4,8")])
10437
10438(define_insn "*sibcall_local64"
10439 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10440 (match_operand 1 "" "g,g"))
10441 (use (match_operand:SI 2 "immediate_operand" "O,n"))
fe352c29 10442 (use (match_operand:SI 3 "register_operand" "l,l"))
5e1bf043
DJ		 10443 (return)]
10444 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10445 "*
10446{
10447 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10448 output_asm_insn (\"crxor 6,6,6\", operands);
10449
10450 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10451 output_asm_insn (\"creqv 6,6,6\", operands);
10452
10453 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10454}"
10455 [(set_attr "type" "branch")
10456 (set_attr "length" "4,8")])
10457
10458(define_insn "*sibcall_value_local32"
10459 [(set (match_operand 0 "" "")
10460 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10461 (match_operand 2 "" "g,g")))
10462 (use (match_operand:SI 3 "immediate_operand" "O,n"))
fe352c29 10463 (use (match_operand:SI 4 "register_operand" "l,l"))
5e1bf043
DJ		 10464 (return)]
10465 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10466 "*
10467{
10468 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10469 output_asm_insn (\"crxor 6,6,6\", operands);
10470
10471 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10472 output_asm_insn (\"creqv 6,6,6\", operands);
10473
10474 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10475}"
10476 [(set_attr "type" "branch")
10477 (set_attr "length" "4,8")])
10478
10479
10480(define_insn "*sibcall_value_local64"
10481 [(set (match_operand 0 "" "")
10482 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10483 (match_operand 2 "" "g,g")))
10484 (use (match_operand:SI 3 "immediate_operand" "O,n"))
fe352c29 10485 (use (match_operand:SI 4 "register_operand" "l,l"))
5e1bf043
DJ		 10486 (return)]
10487 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10488 "*
10489{
10490 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10491 output_asm_insn (\"crxor 6,6,6\", operands);
10492
10493 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10494 output_asm_insn (\"creqv 6,6,6\", operands);
10495
10496 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10497}"
10498 [(set_attr "type" "branch")
10499 (set_attr "length" "4,8")])
10500
10501(define_insn "*sibcall_nonlocal_aix32"
10502 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10503 (match_operand 1 "" "g"))
10504 (use (match_operand:SI 2 "immediate_operand" "O"))
fe352c29 10505 (use (match_operand:SI 3 "register_operand" "l"))
5e1bf043
DJ		 10506 (return)]
10507 "TARGET_32BIT
10508 && DEFAULT_ABI == ABI_AIX
10509 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10510 "b %z0"
10511 [(set_attr "type" "branch")
10512 (set_attr "length" "4")])
10513
10514(define_insn "*sibcall_nonlocal_aix64"
10515 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10516 (match_operand 1 "" "g"))
10517 (use (match_operand:SI 2 "immediate_operand" "O"))
fe352c29 10518 (use (match_operand:SI 3 "register_operand" "l"))
5e1bf043
DJ		 10519 (return)]
10520 "TARGET_64BIT
10521 && DEFAULT_ABI == ABI_AIX
10522 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10523 "b %z0"
10524 [(set_attr "type" "branch")
10525 (set_attr "length" "4")])
10526
10527(define_insn "*sibcall_value_nonlocal_aix32"
10528 [(set (match_operand 0 "" "")
10529 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10530 (match_operand 2 "" "g")))
10531 (use (match_operand:SI 3 "immediate_operand" "O"))
fe352c29 10532 (use (match_operand:SI 4 "register_operand" "l"))
5e1bf043
DJ		 10533 (return)]
10534 "TARGET_32BIT
10535 && DEFAULT_ABI == ABI_AIX
10536 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10537 "b %z1"
10538 [(set_attr "type" "branch")
10539 (set_attr "length" "4")])
10540
10541(define_insn "*sibcall_value_nonlocal_aix64"
10542 [(set (match_operand 0 "" "")
10543 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10544 (match_operand 2 "" "g")))
10545 (use (match_operand:SI 3 "immediate_operand" "O"))
fe352c29 10546 (use (match_operand:SI 4 "register_operand" "l"))
5e1bf043
DJ		 10547 (return)]
10548 "TARGET_64BIT
10549 && DEFAULT_ABI == ABI_AIX
10550 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10551 "b %z1"
10552 [(set_attr "type" "branch")
10553 (set_attr "length" "4")])
10554
10555(define_insn "*sibcall_nonlocal_sysv"
10556 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10557 (match_operand 1 "" ""))
10558 (use (match_operand 2 "immediate_operand" "O,n"))
fe352c29 10559 (use (match_operand:SI 3 "register_operand" "l,l"))
5e1bf043
DJ		 10560 (return)]
10561 "(DEFAULT_ABI == ABI_DARWIN
10562 || DEFAULT_ABI == ABI_V4
10563 || DEFAULT_ABI == ABI_AIX_NODESC)
10564 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10565 "*
10566{
10567 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10568 output_asm_insn (\"crxor 6,6,6\", operands);
10569
10570 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10571 output_asm_insn (\"creqv 6,6,6\", operands);
10572
10573 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10574}"
10575 [(set_attr "type" "branch,branch")
10576 (set_attr "length" "4,8")])
10577
10578(define_expand "sibcall_value"
10579 [(parallel [(set (match_operand 0 "register_operand" "")
10580 (call (mem:SI (match_operand 1 "address_operand" ""))
10581 (match_operand 2 "" "")))
10582 (use (match_operand 3 "" ""))
fe352c29 10583 (use (match_operand 4 "" ""))
5e1bf043
DJ		 10584 (return)])]
10585 ""
10586 "
10587{
10588#if TARGET_MACHO
10589 if (flag_pic)
10590 operands[1] = machopic_indirect_call_target (operands[1]);
10591#endif
10592
10593 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10594 abort ();
10595
10596 operands[1] = XEXP (operands[1], 0);
fe352c29 10597 operands[4] = gen_reg_rtx (SImode);
5e1bf043
DJ		 10598
10599}")
10600
10601(define_insn "*sibcall_value_nonlocal_sysv"
10602 [(set (match_operand 0 "" "")
10603 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10604 (match_operand 2 "" "")))
10605 (use (match_operand:SI 3 "immediate_operand" "O,n"))
fe352c29 10606 (use (match_operand:SI 4 "register_operand" "l,l"))
5e1bf043
DJ		 10607 (return)]
10608 "(DEFAULT_ABI == ABI_DARWIN
10609 || DEFAULT_ABI == ABI_V4
10610 || DEFAULT_ABI == ABI_AIX_NODESC)
10611 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10612 "*
10613{
10614 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10615 output_asm_insn (\"crxor 6,6,6\", operands);
10616
10617 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10618 output_asm_insn (\"creqv 6,6,6\", operands);
10619
10620 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10621}"
10622 [(set_attr "type" "branch,branch")
10623 (set_attr "length" "4,8")])
10624
10625(define_expand "sibcall_epilogue"
10626 [(use (const_int 0))]
10627 "TARGET_SCHED_PROLOG"
10628 "
10629{
10630 rs6000_emit_epilogue (TRUE);
10631 DONE;
10632}")
10633
e6f948e3
RK		 10634;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10635;; all of memory. This blocks insns from being moved across this point.
10636
10637(define_insn "blockage"
10638 [(unspec_volatile [(const_int 0)] 0)]
10639 ""
10640 "")
1fd4e8c1
RK		 10641\f
10642;; Compare insns are next. Note that the RS/6000 has two types of compares,
7e69e155 10643;; signed & unsigned, and one type of branch.
1fd4e8c1
RK		 10644;;
10645;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10646;; insns, and branches. We store the operands of compares until we see
10647;; how it is used.
10648(define_expand "cmpsi"
10649 [(set (cc0)
cd2b37d9 10650 (compare (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 10651 (match_operand:SI 1 "reg_or_short_operand" "")))]
10652 ""
10653 "
10654{
10655 /* Take care of the possibility that operands[1] might be negative but
10656 this might be a logical operation. That insn doesn't exist. */
10657 if (GET_CODE (operands[1]) == CONST_INT
10658 && INTVAL (operands[1]) < 0)
10659 operands[1] = force_reg (SImode, operands[1]);
10660
10661 rs6000_compare_op0 = operands[0];
10662 rs6000_compare_op1 = operands[1];
10663 rs6000_compare_fp_p = 0;
10664 DONE;
10665}")
10666
266eb58a
DE		 10667(define_expand "cmpdi"
10668 [(set (cc0)
10669 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10670 (match_operand:DI 1 "reg_or_short_operand" "")))]
10671 "TARGET_POWERPC64"
10672 "
10673{
10674 /* Take care of the possibility that operands[1] might be negative but
10675 this might be a logical operation. That insn doesn't exist. */
10676 if (GET_CODE (operands[1]) == CONST_INT
10677 && INTVAL (operands[1]) < 0)
10678 operands[1] = force_reg (DImode, operands[1]);
10679
10680 rs6000_compare_op0 = operands[0];
10681 rs6000_compare_op1 = operands[1];
10682 rs6000_compare_fp_p = 0;
10683 DONE;
10684}")
10685
1fd4e8c1 10686(define_expand "cmpsf"
cd2b37d9
RK		 10687 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10688 (match_operand:SF 1 "gpc_reg_operand" "")))]
d14a6d05 10689 "TARGET_HARD_FLOAT"
1fd4e8c1
RK		 10690 "
10691{
10692 rs6000_compare_op0 = operands[0];
10693 rs6000_compare_op1 = operands[1];
10694 rs6000_compare_fp_p = 1;
10695 DONE;
10696}")
10697
10698(define_expand "cmpdf"
cd2b37d9
RK		 10699 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10700 (match_operand:DF 1 "gpc_reg_operand" "")))]
a3170dc6 10701 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 10702 "
10703{
10704 rs6000_compare_op0 = operands[0];
10705 rs6000_compare_op1 = operands[1];
10706 rs6000_compare_fp_p = 1;
10707 DONE;
10708}")
10709
d6f99ca4 10710(define_expand "cmptf"
e7a4130e
DE		 10711 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10712 (match_operand:TF 1 "gpc_reg_operand" "")))]
a3170dc6
AH		 10713 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT
10714 && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
d6f99ca4
DE		 10715 "
10716{
10717 rs6000_compare_op0 = operands[0];
10718 rs6000_compare_op1 = operands[1];
10719 rs6000_compare_fp_p = 1;
10720 DONE;
10721}")
10722
1fd4e8c1 10723(define_expand "beq"
39a10a29 10724 [(use (match_operand 0 "" ""))]
1fd4e8c1 10725 ""
39a10a29 10726 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 10727
10728(define_expand "bne"
39a10a29 10729 [(use (match_operand 0 "" ""))]
1fd4e8c1 10730 ""
39a10a29 10731 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
1fd4e8c1 10732
39a10a29
GK		 10733(define_expand "bge"
10734 [(use (match_operand 0 "" ""))]
1fd4e8c1 10735 ""
39a10a29 10736 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
1fd4e8c1
RK		 10737
10738(define_expand "bgt"
39a10a29 10739 [(use (match_operand 0 "" ""))]
1fd4e8c1 10740 ""
39a10a29 10741 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
1fd4e8c1
RK		 10742
10743(define_expand "ble"
39a10a29 10744 [(use (match_operand 0 "" ""))]
1fd4e8c1 10745 ""
39a10a29 10746 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
1fd4e8c1 10747
39a10a29
GK		 10748(define_expand "blt"
10749 [(use (match_operand 0 "" ""))]
1fd4e8c1 10750 ""
39a10a29 10751 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
1fd4e8c1 10752
39a10a29
GK		 10753(define_expand "bgeu"
10754 [(use (match_operand 0 "" ""))]
1fd4e8c1 10755 ""
39a10a29 10756 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
1fd4e8c1 10757
39a10a29
GK		 10758(define_expand "bgtu"
10759 [(use (match_operand 0 "" ""))]
1fd4e8c1 10760 ""
39a10a29 10761 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
1fd4e8c1 10762
39a10a29
GK		 10763(define_expand "bleu"
10764 [(use (match_operand 0 "" ""))]
1fd4e8c1 10765 ""
39a10a29 10766 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
1fd4e8c1 10767
39a10a29
GK		 10768(define_expand "bltu"
10769 [(use (match_operand 0 "" ""))]
1fd4e8c1 10770 ""
39a10a29 10771 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
1fd4e8c1 10772
1c882ea4 10773(define_expand "bunordered"
39a10a29 10774 [(use (match_operand 0 "" ""))]
1c882ea4 10775 ""
39a10a29 10776 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
1c882ea4
GK		 10777
10778(define_expand "bordered"
39a10a29 10779 [(use (match_operand 0 "" ""))]
1c882ea4 10780 ""
39a10a29 10781 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
1c882ea4
GK		 10782
10783(define_expand "buneq"
39a10a29 10784 [(use (match_operand 0 "" ""))]
1c882ea4 10785 ""
39a10a29 10786 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
1c882ea4
GK		 10787
10788(define_expand "bunge"
39a10a29 10789 [(use (match_operand 0 "" ""))]
1c882ea4 10790 ""
39a10a29 10791 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
1c882ea4
GK		 10792
10793(define_expand "bungt"
39a10a29 10794 [(use (match_operand 0 "" ""))]
1c882ea4 10795 ""
39a10a29 10796 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
1c882ea4
GK		 10797
10798(define_expand "bunle"
39a10a29 10799 [(use (match_operand 0 "" ""))]
1c882ea4 10800 ""
39a10a29 10801 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
1c882ea4
GK		 10802
10803(define_expand "bunlt"
39a10a29 10804 [(use (match_operand 0 "" ""))]
1c882ea4 10805 ""
39a10a29 10806 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
1c882ea4
GK		 10807
10808(define_expand "bltgt"
39a10a29 10809 [(use (match_operand 0 "" ""))]
1c882ea4 10810 ""
39a10a29 10811 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
1c882ea4 10812
1fd4e8c1
RK		 10813;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10814;; For SEQ, likewise, except that comparisons with zero should be done
10815;; with an scc insns. However, due to the order that combine see the
10816;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10817;; the cases we don't want to handle.
10818(define_expand "seq"
39a10a29 10819 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 10820 ""
39a10a29 10821 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 10822
10823(define_expand "sne"
39a10a29 10824 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 10825 ""
10826 "
39a10a29
GK		 10827{
10828 if (! rs6000_compare_fp_p)
1fd4e8c1
RK		 10829 FAIL;
10830
39a10a29
GK		 10831 rs6000_emit_sCOND (NE, operands[0]);
10832 DONE;
1fd4e8c1
RK		 10833}")
10834
10835;; A > 0 is best done using the portable sequence, so fail in that case.
10836(define_expand "sgt"
39a10a29 10837 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 10838 ""
10839 "
5638268e
DE		 10840{
10841 if (! rs6000_compare_fp_p
10842 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
1fd4e8c1
RK		 10843 FAIL;
10844
39a10a29
GK		 10845 rs6000_emit_sCOND (GT, operands[0]);
10846 DONE;
1fd4e8c1
RK		 10847}")
10848
10849;; A < 0 is best done in the portable way for A an integer.
10850(define_expand "slt"
39a10a29 10851 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 10852 ""
10853 "
5638268e
DE		 10854{
10855 if (! rs6000_compare_fp_p
10856 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
1fd4e8c1
RK		 10857 FAIL;
10858
39a10a29
GK		 10859 rs6000_emit_sCOND (LT, operands[0]);
10860 DONE;
1fd4e8c1
RK		 10861}")
10862
5638268e 10863;; A >= 0 is best done the portable way for A an integer.
1fd4e8c1 10864(define_expand "sge"
39a10a29 10865 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 10866 ""
5638268e
DE		 10867 "
10868{
10869 if (! rs6000_compare_fp_p
10870 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
10871 FAIL;
10872
10873 rs6000_emit_sCOND (GE, operands[0]);
10874 DONE;
10875}")
1fd4e8c1
RK		 10876
10877;; A <= 0 is best done the portable way for A an integer.
10878(define_expand "sle"
39a10a29 10879 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 10880 ""
10881 "
5638268e
DE		 10882{
10883 if (! rs6000_compare_fp_p
10884 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
1fd4e8c1
RK		 10885 FAIL;
10886
39a10a29
GK		 10887 rs6000_emit_sCOND (LE, operands[0]);
10888 DONE;
1fd4e8c1
RK		 10889}")
10890
10891(define_expand "sgtu"
39a10a29 10892 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 10893 ""
39a10a29 10894 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
1fd4e8c1
RK		 10895
10896(define_expand "sltu"
39a10a29 10897 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 10898 ""
39a10a29 10899 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
1fd4e8c1
RK		 10900
10901(define_expand "sgeu"
39a10a29 10902 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 10903 ""
39a10a29 10904 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
1fd4e8c1
RK		 10905
10906(define_expand "sleu"
39a10a29 10907 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 10908 ""
39a10a29 10909 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
1fd4e8c1
RK		 10910\f
10911;; Here are the actual compare insns.
acad7ed3 10912(define_insn "*cmpsi_internal1"
1fd4e8c1 10913 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
cd2b37d9 10914 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 10915 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
10916 ""
7f340546 10917 "{cmp%I2|cmpw%I2} %0,%1,%2"
b54cf83a 10918 [(set_attr "type" "cmp")])
1fd4e8c1 10919
acad7ed3 10920(define_insn "*cmpdi_internal1"
266eb58a
DE		 10921 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
10922 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
10923 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
10924 "TARGET_POWERPC64"
10925 "cmpd%I2 %0,%1,%2"
b54cf83a 10926 [(set_attr "type" "cmp")])
266eb58a 10927
f357808b
RK		 10928;; If we are comparing a register for equality with a large constant,
10929;; we can do this with an XOR followed by a compare. But we need a scratch
10930;; register for the result of the XOR.
10931
10932(define_split
10933 [(set (match_operand:CC 0 "cc_reg_operand" "")
cd2b37d9 10934 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
f357808b 10935 (match_operand:SI 2 "non_short_cint_operand" "")))
cd2b37d9 10936 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
f357808b
RK		 10937 "find_single_use (operands[0], insn, 0)
10938 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
10939 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
10940 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
10941 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
10942 "
10943{
10944 /* Get the constant we are comparing against, C, and see what it looks like
10945 sign-extended to 16 bits. Then see what constant could be XOR'ed
10946 with C to get the sign-extended value. */
10947
5f59ecb7 10948 HOST_WIDE_INT c = INTVAL (operands[2]);
a65c591c 10949 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
5f59ecb7 10950 HOST_WIDE_INT xorv = c ^ sextc;
f357808b 10951
89e9f3a8
MM		 10952 operands[4] = GEN_INT (xorv);
10953 operands[5] = GEN_INT (sextc);
f357808b
RK		 10954}")
10955
acad7ed3 10956(define_insn "*cmpsi_internal2"
1fd4e8c1 10957 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
cd2b37d9 10958 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9ebbca7d 10959 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
1fd4e8c1 10960 ""
e2c953b6 10961 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
b54cf83a 10962 [(set_attr "type" "cmp")])
1fd4e8c1 10963
acad7ed3 10964(define_insn "*cmpdi_internal2"
266eb58a
DE		 10965 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
10966 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
9ebbca7d 10967 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
266eb58a 10968 ""
e2c953b6 10969 "cmpld%I2 %0,%1,%b2"
b54cf83a 10970 [(set_attr "type" "cmp")])
266eb58a 10971
1fd4e8c1
RK		 10972;; The following two insns don't exist as single insns, but if we provide
10973;; them, we can swap an add and compare, which will enable us to overlap more
10974;; of the required delay between a compare and branch. We generate code for
10975;; them by splitting.
10976
10977(define_insn ""
10978 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
cd2b37d9 10979 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 10980 (match_operand:SI 2 "short_cint_operand" "i")))
cd2b37d9 10981 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 10982 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10983 ""
baf97f86
RK		 10984 "#"
10985 [(set_attr "length" "8")])
7e69e155 10986
1fd4e8c1
RK		 10987(define_insn ""
10988 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
cd2b37d9 10989 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 10990 (match_operand:SI 2 "u_short_cint_operand" "i")))
cd2b37d9 10991 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 10992 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10993 ""
baf97f86
RK		 10994 "#"
10995 [(set_attr "length" "8")])
7e69e155 10996
1fd4e8c1
RK		 10997(define_split
10998 [(set (match_operand:CC 3 "cc_reg_operand" "")
cd2b37d9 10999 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11000 (match_operand:SI 2 "short_cint_operand" "")))
cd2b37d9 11001 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11002 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11003 ""
11004 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11005 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11006
11007(define_split
11008 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
cd2b37d9 11009 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11010 (match_operand:SI 2 "u_short_cint_operand" "")))
cd2b37d9 11011 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11012 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11013 ""
11014 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11015 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11016
acad7ed3 11017(define_insn "*cmpsf_internal1"
1fd4e8c1 11018 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11019 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11020 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 11021 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11022 "fcmpu %0,%1,%2"
11023 [(set_attr "type" "fpcompare")])
11024
acad7ed3 11025(define_insn "*cmpdf_internal1"
1fd4e8c1 11026 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11027 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11028 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 11029 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11030 "fcmpu %0,%1,%2"
11031 [(set_attr "type" "fpcompare")])
d6f99ca4
DE		 11032
11033;; Only need to compare second words if first words equal
11034(define_insn "*cmptf_internal1"
11035 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11036 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11037 (match_operand:TF 2 "gpc_reg_operand" "f")))]
a3170dc6
AH		 11038 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
11039 && TARGET_LONG_DOUBLE_128"
2e7d5318 11040 "fcmpu %0,%1,%2\;bne %0,$+4\;fcmpu %0,%L1,%L2"
d6f99ca4
DE		 11041 [(set_attr "type" "fpcompare")
11042 (set_attr "length" "12")])
1fd4e8c1
RK		 11043\f
11044;; Now we have the scc insns. We can do some combinations because of the
11045;; way the machine works.
11046;;
11047;; Note that this is probably faster if we can put an insn between the
c5defebb
RK		 11048;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11049;; cases the insns below which don't use an intermediate CR field will
11050;; be used instead.
1fd4e8c1 11051(define_insn ""
cd2b37d9 11052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11053 (match_operator:SI 1 "scc_comparison_operator"
11054 [(match_operand 2 "cc_reg_operand" "y")
11055 (const_int 0)]))]
11056 ""
ca7f5001 11057 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
b54cf83a 11058 [(set_attr "type" "mfcr")
309323c2 11059 (set_attr "length" "12")])
1fd4e8c1 11060
a3170dc6
AH		 11061;; Same as above, but get the OV/ORDERED bit.
11062(define_insn "move_from_CR_ov_bit"
11063 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11064 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] 724))]
11065 "TARGET_ISEL"
11066 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
b54cf83a
DE		 11067 [(set_attr "type" "mfcr")
11068 (set_attr "length" "12")])
a3170dc6 11069
1fd4e8c1 11070(define_insn ""
9ebbca7d
GK		 11071 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11072 (match_operator:DI 1 "scc_comparison_operator"
11073 [(match_operand 2 "cc_reg_operand" "y")
11074 (const_int 0)]))]
11075 "TARGET_POWERPC64"
11076 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
b54cf83a 11077 [(set_attr "type" "mfcr")
309323c2 11078 (set_attr "length" "12")])
9ebbca7d
GK		 11079
11080(define_insn ""
11081 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 11082 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 11083 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1
RK		 11084 (const_int 0)])
11085 (const_int 0)))
9ebbca7d 11086 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 11087 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
0ad91047 11088 "! TARGET_POWERPC64"
9ebbca7d
GK		 11089 "@
11090 %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1
11091 #"
b19003d8 11092 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 11093 (set_attr "length" "12,16")])
11094
11095(define_split
11096 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11097 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11098 [(match_operand 2 "cc_reg_operand" "")
11099 (const_int 0)])
11100 (const_int 0)))
11101 (set (match_operand:SI 3 "gpc_reg_operand" "")
11102 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11103 "! TARGET_POWERPC64 && reload_completed"
11104 [(set (match_dup 3)
11105 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11106 (set (match_dup 0)
11107 (compare:CC (match_dup 3)
11108 (const_int 0)))]
11109 "")
1fd4e8c1
RK		 11110
11111(define_insn ""
cd2b37d9 11112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11113 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11114 [(match_operand 2 "cc_reg_operand" "y")
11115 (const_int 0)])
11116 (match_operand:SI 3 "const_int_operand" "n")))]
11117 ""
11118 "*
11119{
11120 int is_bit = ccr_bit (operands[1], 1);
11121 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11122 int count;
11123
11124 if (is_bit >= put_bit)
11125 count = is_bit - put_bit;
11126 else
11127 count = 32 - (put_bit - is_bit);
11128
89e9f3a8
MM		 11129 operands[4] = GEN_INT (count);
11130 operands[5] = GEN_INT (put_bit);
1fd4e8c1 11131
ca7f5001 11132 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
b19003d8 11133}"
b54cf83a 11134 [(set_attr "type" "mfcr")
309323c2 11135 (set_attr "length" "12")])
1fd4e8c1
RK		 11136
11137(define_insn ""
9ebbca7d 11138 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 11139 (compare:CC
11140 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 11141 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1 11142 (const_int 0)])
9ebbca7d 11143 (match_operand:SI 3 "const_int_operand" "n,n"))
1fd4e8c1 11144 (const_int 0)))
9ebbca7d 11145 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 11146 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11147 (match_dup 3)))]
ce71f754 11148 ""
1fd4e8c1
RK		 11149 "*
11150{
11151 int is_bit = ccr_bit (operands[1], 1);
11152 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11153 int count;
11154
9ebbca7d
GK		 11155 /* Force split for non-cc0 compare. */
11156 if (which_alternative == 1)
11157 return \"#\";
11158
1fd4e8c1
RK		 11159 if (is_bit >= put_bit)
11160 count = is_bit - put_bit;
11161 else
11162 count = 32 - (put_bit - is_bit);
11163
89e9f3a8
MM		 11164 operands[5] = GEN_INT (count);
11165 operands[6] = GEN_INT (put_bit);
1fd4e8c1 11166
ca7f5001 11167 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
1fd4e8c1 11168}"
b19003d8 11169 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 11170 (set_attr "length" "12,16")])
11171
11172(define_split
11173 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11174 (compare:CC
11175 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11176 [(match_operand 2 "cc_reg_operand" "")
11177 (const_int 0)])
11178 (match_operand:SI 3 "const_int_operand" ""))
11179 (const_int 0)))
11180 (set (match_operand:SI 4 "gpc_reg_operand" "")
11181 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11182 (match_dup 3)))]
ce71f754 11183 "reload_completed"
9ebbca7d
GK		 11184 [(set (match_dup 4)
11185 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11186 (match_dup 3)))
11187 (set (match_dup 0)
11188 (compare:CC (match_dup 4)
11189 (const_int 0)))]
11190 "")
1fd4e8c1 11191
c5defebb
RK		 11192;; There is a 3 cycle delay between consecutive mfcr instructions
11193;; so it is useful to combine 2 scc instructions to use only one mfcr.
11194
11195(define_peephole
cd2b37d9 11196 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
c5defebb
RK		 11197 (match_operator:SI 1 "scc_comparison_operator"
11198 [(match_operand 2 "cc_reg_operand" "y")
11199 (const_int 0)]))
cd2b37d9 11200 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
c5defebb
RK		 11201 (match_operator:SI 4 "scc_comparison_operator"
11202 [(match_operand 5 "cc_reg_operand" "y")
11203 (const_int 0)]))]
309323c2
DE		 11204 "REGNO (operands[2]) != REGNO (operands[5])"
11205 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 11206 [(set_attr "type" "mfcr")
309323c2 11207 (set_attr "length" "20")])
c5defebb 11208
9ebbca7d
GK		 11209(define_peephole
11210 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11211 (match_operator:DI 1 "scc_comparison_operator"
11212 [(match_operand 2 "cc_reg_operand" "y")
11213 (const_int 0)]))
11214 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11215 (match_operator:DI 4 "scc_comparison_operator"
11216 [(match_operand 5 "cc_reg_operand" "y")
11217 (const_int 0)]))]
309323c2
DE		 11218 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11219 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 11220 [(set_attr "type" "mfcr")
309323c2 11221 (set_attr "length" "20")])
9ebbca7d 11222
1fd4e8c1
RK		 11223;; There are some scc insns that can be done directly, without a compare.
11224;; These are faster because they don't involve the communications between
11225;; the FXU and branch units. In fact, we will be replacing all of the
11226;; integer scc insns here or in the portable methods in emit_store_flag.
11227;;
11228;; Also support (neg (scc ..)) since that construct is used to replace
11229;; branches, (plus (scc ..) ..) since that construct is common and
11230;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11231;; cases where it is no more expensive than (neg (scc ..)).
11232
11233;; Have reload force a constant into a register for the simple insns that
11234;; otherwise won't accept constants. We do this because it is faster than
11235;; the cmp/mfcr sequence we would otherwise generate.
11236
11237(define_insn ""
cd2b37d9
RK		 11238 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11239 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5f59ecb7 11240 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
1fd4e8c1 11241 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
f9562f27 11242 "! TARGET_POWERPC64"
1fd4e8c1 11243 "@
ca7f5001 11244 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
71d2371f 11245 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
ca7f5001
RK		 11246 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11247 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11248 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
b19003d8 11249 [(set_attr "length" "12,8,12,12,12")])
1fd4e8c1 11250
a260abc9
DE		 11251(define_insn ""
11252 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11253 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11254 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11255 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11256 "TARGET_POWERPC64"
11257 "@
11258 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11259 subfic %3,%1,0\;adde %0,%3,%1
11260 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11261 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11262 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11263 [(set_attr "length" "12,8,12,12,12")])
11264
1fd4e8c1 11265(define_insn ""
9ebbca7d 11266 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 11267 (compare:CC
9ebbca7d
GK		 11268 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11269 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
1fd4e8c1 11270 (const_int 0)))
9ebbca7d 11271 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
1fd4e8c1 11272 (eq:SI (match_dup 1) (match_dup 2)))
9ebbca7d 11273 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
f9562f27 11274 "! TARGET_POWERPC64"
1fd4e8c1 11275 "@
ca7f5001
RK		 11276 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11277 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11278 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11279 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
9ebbca7d
GK		 11280 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11281 #
11282 #
11283 #
11284 #
11285 #"
b19003d8 11286 [(set_attr "type" "compare")
9ebbca7d
GK		 11287 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11288
11289(define_split
11290 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11291 (compare:CC
11292 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11293 (match_operand:SI 2 "reg_or_cint_operand" ""))
11294 (const_int 0)))
11295 (set (match_operand:SI 0 "gpc_reg_operand" "")
11296 (eq:SI (match_dup 1) (match_dup 2)))
11297 (clobber (match_scratch:SI 3 ""))]
11298 "! TARGET_POWERPC64 && reload_completed"
11299 [(parallel [(set (match_dup 0)
11300 (eq:SI (match_dup 1) (match_dup 2)))
11301 (clobber (match_dup 3))])
11302 (set (match_dup 4)
11303 (compare:CC (match_dup 0)
11304 (const_int 0)))]
11305 "")
b19003d8 11306
a260abc9 11307(define_insn ""
9ebbca7d 11308 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
a260abc9 11309 (compare:CC
9ebbca7d
GK		 11310 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11311 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
a260abc9 11312 (const_int 0)))
9ebbca7d 11313 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
a260abc9 11314 (eq:DI (match_dup 1) (match_dup 2)))
9ebbca7d 11315 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
a260abc9
DE		 11316 "TARGET_POWERPC64"
11317 "@
11318 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11319 subfic %3,%1,0\;adde. %0,%3,%1
11320 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11321 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
9ebbca7d
GK		 11322 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11323 #
11324 #
11325 #
11326 #
11327 #"
a260abc9 11328 [(set_attr "type" "compare")
9ebbca7d
GK		 11329 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11330
11331(define_split
11332 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11333 (compare:CC
11334 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11335 (match_operand:DI 2 "reg_or_cint_operand" ""))
11336 (const_int 0)))
11337 (set (match_operand:DI 0 "gpc_reg_operand" "")
11338 (eq:DI (match_dup 1) (match_dup 2)))
11339 (clobber (match_scratch:DI 3 ""))]
11340 "TARGET_POWERPC64 && reload_completed"
11341 [(parallel [(set (match_dup 0)
11342 (eq:DI (match_dup 1) (match_dup 2)))
11343 (clobber (match_dup 3))])
11344 (set (match_dup 4)
11345 (compare:CC (match_dup 0)
11346 (const_int 0)))]
11347 "")
a260abc9 11348
b19003d8
RK		 11349;; We have insns of the form shown by the first define_insn below. If
11350;; there is something inside the comparison operation, we must split it.
11351(define_split
11352 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11353 (plus:SI (match_operator 1 "comparison_operator"
11354 [(match_operand:SI 2 "" "")
11355 (match_operand:SI 3
11356 "reg_or_cint_operand" "")])
11357 (match_operand:SI 4 "gpc_reg_operand" "")))
11358 (clobber (match_operand:SI 5 "register_operand" ""))]
11359 "! gpc_reg_operand (operands[2], SImode)"
11360 [(set (match_dup 5) (match_dup 2))
11361 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11362 (match_dup 4)))])
1fd4e8c1
RK		 11363
11364(define_insn ""
5276df18 11365 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
cd2b37d9 11366 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5f59ecb7 11367 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
5276df18 11368 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
f9562f27 11369 "! TARGET_POWERPC64"
1fd4e8c1 11370 "@
5276df18
DE		 11371 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11372 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11373 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11374 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11375 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
b19003d8 11376 [(set_attr "length" "12,8,12,12,12")])
1fd4e8c1
RK		 11377
11378(define_insn ""
9ebbca7d 11379 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 11380 (compare:CC
1fd4e8c1 11381 (plus:SI
9ebbca7d
GK		 11382 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11383 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11384 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 11385 (const_int 0)))
9ebbca7d 11386 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
f9562f27 11387 "! TARGET_POWERPC64"
1fd4e8c1 11388 "@
ca7f5001 11389 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
19378cf8 11390 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
ca7f5001
RK		 11391 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11392 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 11393 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11394 #
11395 #
11396 #
11397 #
11398 #"
b19003d8 11399 [(set_attr "type" "compare")
9ebbca7d
GK		 11400 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11401
11402(define_split
11403 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11404 (compare:CC
11405 (plus:SI
11406 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11407 (match_operand:SI 2 "reg_or_cint_operand" ""))
11408 (match_operand:SI 3 "gpc_reg_operand" ""))
11409 (const_int 0)))
11410 (clobber (match_scratch:SI 4 ""))]
11411 "! TARGET_POWERPC64 && reload_completed"
11412 [(set (match_dup 4)
11413 (plus:SI (eq:SI (match_dup 1)
11414 (match_dup 2))
11415 (match_dup 3)))
11416 (set (match_dup 0)
11417 (compare:CC (match_dup 4)
11418 (const_int 0)))]
11419 "")
1fd4e8c1
RK		 11420
11421(define_insn ""
0387639b 11422 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 11423 (compare:CC
1fd4e8c1 11424 (plus:SI
9ebbca7d
GK		 11425 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11426 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11427 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 11428 (const_int 0)))
0387639b
DE		 11429 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11430 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
f9562f27 11431 "! TARGET_POWERPC64"
1fd4e8c1 11432 "@
0387639b
DE		 11433 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11434 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11435 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11436 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11437 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 11438 #
11439 #
11440 #
11441 #
11442 #"
11443 [(set_attr "type" "compare")
11444 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11445
11446(define_split
0387639b 11447 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 11448 (compare:CC
11449 (plus:SI
11450 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11451 (match_operand:SI 2 "reg_or_cint_operand" ""))
11452 (match_operand:SI 3 "gpc_reg_operand" ""))
11453 (const_int 0)))
11454 (set (match_operand:SI 0 "gpc_reg_operand" "")
0387639b 11455 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 11456 "! TARGET_POWERPC64 && reload_completed"
0387639b 11457 [(set (match_dup 0)
9ebbca7d 11458 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
0387639b 11459 (set (match_dup 4)
9ebbca7d
GK		 11460 (compare:CC (match_dup 0)
11461 (const_int 0)))]
11462 "")
11463
1fd4e8c1 11464(define_insn ""
cd2b37d9 11465 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
deb9225a 11466 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5f59ecb7 11467 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
f9562f27 11468 "! TARGET_POWERPC64"
1fd4e8c1 11469 "@
ca7f5001
RK		 11470 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11471 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11472 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11473 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11474 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 11475 [(set_attr "length" "12,8,12,12,12")])
1fd4e8c1 11476
ea9be077
MM		 11477;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11478;; since it nabs/sr is just as fast.
463b558b 11479(define_insn "*ne0"
b4e95693 11480 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
ea9be077
MM		 11481 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11482 (const_int 31)))
11483 (clobber (match_scratch:SI 2 "=&r"))]
a3170dc6 11484 "! TARGET_POWER && ! TARGET_POWERPC64 && !TARGET_ISEL"
ea9be077
MM		 11485 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11486 [(set_attr "length" "8")])
11487
a260abc9
DE		 11488(define_insn ""
11489 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11490 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11491 (const_int 63)))
11492 (clobber (match_scratch:DI 2 "=&r"))]
11493 "TARGET_POWERPC64"
11494 "addic %2,%1,-1\;subfe %0,%2,%1"
11495 [(set_attr "length" "8")])
11496
1fd4e8c1
RK		 11497;; This is what (plus (ne X (const_int 0)) Y) looks like.
11498(define_insn ""
cd2b37d9 11499 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 11500 (plus:SI (lshiftrt:SI
cd2b37d9 11501 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1fd4e8c1 11502 (const_int 31))
cd2b37d9 11503 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1 11504 (clobber (match_scratch:SI 3 "=&r"))]
f9562f27 11505 "! TARGET_POWERPC64"
ca7f5001 11506 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
b19003d8 11507 [(set_attr "length" "8")])
1fd4e8c1 11508
a260abc9
DE		 11509(define_insn ""
11510 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11511 (plus:DI (lshiftrt:DI
11512 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11513 (const_int 63))
11514 (match_operand:DI 2 "gpc_reg_operand" "r")))
11515 (clobber (match_scratch:DI 3 "=&r"))]
11516 "TARGET_POWERPC64"
11517 "addic %3,%1,-1\;addze %0,%2"
11518 [(set_attr "length" "8")])
11519
1fd4e8c1 11520(define_insn ""
9ebbca7d 11521 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 11522 (compare:CC
11523 (plus:SI (lshiftrt:SI
9ebbca7d 11524 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 11525 (const_int 31))
9ebbca7d 11526 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 11527 (const_int 0)))
889b90a1
GK		 11528 (clobber (match_scratch:SI 3 "=&r,&r"))
11529 (clobber (match_scratch:SI 4 "=X,&r"))]
f9562f27 11530 "! TARGET_POWERPC64"
9ebbca7d
GK		 11531 "@
11532 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11533 #"
b19003d8 11534 [(set_attr "type" "compare")
9ebbca7d
GK		 11535 (set_attr "length" "8,12")])
11536
11537(define_split
11538 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11539 (compare:CC
11540 (plus:SI (lshiftrt:SI
11541 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11542 (const_int 31))
11543 (match_operand:SI 2 "gpc_reg_operand" ""))
11544 (const_int 0)))
889b90a1
GK		 11545 (clobber (match_scratch:SI 3 ""))
11546 (clobber (match_scratch:SI 4 ""))]
9ebbca7d 11547 "! TARGET_POWERPC64 && reload_completed"
889b90a1 11548 [(parallel [(set (match_dup 3)
ce71f754
AM		 11549 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11550 (const_int 31))
11551 (match_dup 2)))
889b90a1 11552 (clobber (match_dup 4))])
9ebbca7d
GK		 11553 (set (match_dup 0)
11554 (compare:CC (match_dup 3)
11555 (const_int 0)))]
11556 "")
1fd4e8c1 11557
a260abc9 11558(define_insn ""
9ebbca7d 11559 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 11560 (compare:CC
11561 (plus:DI (lshiftrt:DI
9ebbca7d 11562 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 11563 (const_int 63))
9ebbca7d 11564 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 11565 (const_int 0)))
9ebbca7d 11566 (clobber (match_scratch:DI 3 "=&r,&r"))]
a260abc9 11567 "TARGET_POWERPC64"
9ebbca7d
GK		 11568 "@
11569 addic %3,%1,-1\;addze. %3,%2
11570 #"
a260abc9 11571 [(set_attr "type" "compare")
9ebbca7d
GK		 11572 (set_attr "length" "8,12")])
11573
11574(define_split
11575 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11576 (compare:CC
11577 (plus:DI (lshiftrt:DI
11578 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11579 (const_int 63))
11580 (match_operand:DI 2 "gpc_reg_operand" ""))
11581 (const_int 0)))
11582 (clobber (match_scratch:DI 3 ""))]
11583 "TARGET_POWERPC64 && reload_completed"
11584 [(set (match_dup 3)
11585 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11586 (const_int 63))
11587 (match_dup 2)))
11588 (set (match_dup 0)
11589 (compare:CC (match_dup 3)
11590 (const_int 0)))]
11591 "")
a260abc9 11592
1fd4e8c1 11593(define_insn ""
9ebbca7d 11594 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 11595 (compare:CC
11596 (plus:SI (lshiftrt:SI
9ebbca7d 11597 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 11598 (const_int 31))
9ebbca7d 11599 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 11600 (const_int 0)))
9ebbca7d 11601 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 11602 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11603 (match_dup 2)))
9ebbca7d 11604 (clobber (match_scratch:SI 3 "=&r,&r"))]
f9562f27 11605 "! TARGET_POWERPC64"
9ebbca7d
GK		 11606 "@
11607 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11608 #"
b19003d8 11609 [(set_attr "type" "compare")
9ebbca7d
GK		 11610 (set_attr "length" "8,12")])
11611
11612(define_split
11613 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11614 (compare:CC
11615 (plus:SI (lshiftrt:SI
11616 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11617 (const_int 31))
11618 (match_operand:SI 2 "gpc_reg_operand" ""))
11619 (const_int 0)))
11620 (set (match_operand:SI 0 "gpc_reg_operand" "")
11621 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11622 (match_dup 2)))
11623 (clobber (match_scratch:SI 3 ""))]
11624 "! TARGET_POWERPC64 && reload_completed"
11625 [(parallel [(set (match_dup 0)
11626 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11627 (match_dup 2)))
11628 (clobber (match_dup 3))])
11629 (set (match_dup 4)
11630 (compare:CC (match_dup 0)
11631 (const_int 0)))]
11632 "")
1fd4e8c1 11633
a260abc9 11634(define_insn ""
9ebbca7d 11635 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9
DE		 11636 (compare:CC
11637 (plus:DI (lshiftrt:DI
9ebbca7d 11638 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 11639 (const_int 63))
9ebbca7d 11640 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 11641 (const_int 0)))
9ebbca7d 11642 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 11643 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11644 (match_dup 2)))
9ebbca7d 11645 (clobber (match_scratch:DI 3 "=&r,&r"))]
a260abc9 11646 "TARGET_POWERPC64"
9ebbca7d
GK		 11647 "@
11648 addic %3,%1,-1\;addze. %0,%2
11649 #"
a260abc9 11650 [(set_attr "type" "compare")
9ebbca7d
GK		 11651 (set_attr "length" "8,12")])
11652
11653(define_split
11654 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11655 (compare:CC
11656 (plus:DI (lshiftrt:DI
11657 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11658 (const_int 63))
11659 (match_operand:DI 2 "gpc_reg_operand" ""))
11660 (const_int 0)))
11661 (set (match_operand:DI 0 "gpc_reg_operand" "")
11662 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11663 (match_dup 2)))
11664 (clobber (match_scratch:DI 3 ""))]
11665 "TARGET_POWERPC64 && reload_completed"
11666 [(parallel [(set (match_dup 0)
11667 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11668 (match_dup 2)))
11669 (clobber (match_dup 3))])
11670 (set (match_dup 4)
11671 (compare:CC (match_dup 0)
11672 (const_int 0)))]
11673 "")
a260abc9 11674
1fd4e8c1 11675(define_insn ""
cd2b37d9
RK		 11676 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11677 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 11678 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11679 (clobber (match_scratch:SI 3 "=r,X"))]
ca7f5001 11680 "TARGET_POWER"
1fd4e8c1 11681 "@
ca7f5001 11682 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
7f340546 11683 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 11684 [(set_attr "length" "12")])
1fd4e8c1
RK		 11685
11686(define_insn ""
9ebbca7d 11687 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 11688 (compare:CC
9ebbca7d
GK		 11689 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11690 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
1fd4e8c1 11691 (const_int 0)))
9ebbca7d 11692 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 11693 (le:SI (match_dup 1) (match_dup 2)))
9ebbca7d 11694 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
ca7f5001 11695 "TARGET_POWER"
1fd4e8c1 11696 "@
ca7f5001 11697 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
9ebbca7d
GK		 11698 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11699 #
11700 #"
11701 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11702 (set_attr "length" "12,12,16,16")])
11703
11704(define_split
11705 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11706 (compare:CC
11707 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11708 (match_operand:SI 2 "reg_or_short_operand" ""))
11709 (const_int 0)))
11710 (set (match_operand:SI 0 "gpc_reg_operand" "")
11711 (le:SI (match_dup 1) (match_dup 2)))
11712 (clobber (match_scratch:SI 3 ""))]
11713 "TARGET_POWER && reload_completed"
11714 [(parallel [(set (match_dup 0)
11715 (le:SI (match_dup 1) (match_dup 2)))
11716 (clobber (match_dup 3))])
11717 (set (match_dup 4)
11718 (compare:CC (match_dup 0)
11719 (const_int 0)))]
11720 "")
1fd4e8c1
RK		 11721
11722(define_insn ""
097657c3 11723 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
cd2b37d9 11724 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 11725 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
097657c3 11726 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
ca7f5001 11727 "TARGET_POWER"
1fd4e8c1 11728 "@
097657c3
AM		 11729 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11730 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
b19003d8 11731 [(set_attr "length" "12")])
1fd4e8c1
RK		 11732
11733(define_insn ""
9ebbca7d 11734 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 11735 (compare:CC
9ebbca7d
GK		 11736 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11737 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11738 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 11739 (const_int 0)))
9ebbca7d 11740 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
ca7f5001 11741 "TARGET_POWER"
1fd4e8c1 11742 "@
ca7f5001 11743 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 11744 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11745 #
11746 #"
b19003d8 11747 [(set_attr "type" "compare")
9ebbca7d
GK		 11748 (set_attr "length" "12,12,16,16")])
11749
11750(define_split
11751 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11752 (compare:CC
11753 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11754 (match_operand:SI 2 "reg_or_short_operand" ""))
11755 (match_operand:SI 3 "gpc_reg_operand" ""))
11756 (const_int 0)))
11757 (clobber (match_scratch:SI 4 ""))]
11758 "TARGET_POWER && reload_completed"
11759 [(set (match_dup 4)
11760 (plus:SI (le:SI (match_dup 1) (match_dup 2))
097657c3 11761 (match_dup 3)))
9ebbca7d
GK		 11762 (set (match_dup 0)
11763 (compare:CC (match_dup 4)
11764 (const_int 0)))]
11765 "")
1fd4e8c1
RK		 11766
11767(define_insn ""
097657c3 11768 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 11769 (compare:CC
9ebbca7d
GK		 11770 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11771 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11772 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 11773 (const_int 0)))
097657c3
AM		 11774 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
11775 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 11776 "TARGET_POWER"
1fd4e8c1 11777 "@
097657c3
AM		 11778 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11779 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 11780 #
11781 #"
b19003d8 11782 [(set_attr "type" "compare")
9ebbca7d
GK		 11783 (set_attr "length" "12,12,16,16")])
11784
11785(define_split
097657c3 11786 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 11787 (compare:CC
11788 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11789 (match_operand:SI 2 "reg_or_short_operand" ""))
11790 (match_operand:SI 3 "gpc_reg_operand" ""))
11791 (const_int 0)))
11792 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 11793 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 11794 "TARGET_POWER && reload_completed"
097657c3 11795 [(set (match_dup 0)
9ebbca7d 11796 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 11797 (set (match_dup 4)
9ebbca7d
GK		 11798 (compare:CC (match_dup 0)
11799 (const_int 0)))]
11800 "")
1fd4e8c1
RK		 11801
11802(define_insn ""
cd2b37d9
RK		 11803 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11804 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 11805 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
ca7f5001 11806 "TARGET_POWER"
1fd4e8c1 11807 "@
ca7f5001
RK		 11808 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11809 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 11810 [(set_attr "length" "12")])
1fd4e8c1
RK		 11811
11812(define_insn ""
cd2b37d9
RK		 11813 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11814 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11815 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
f9562f27 11816 "! TARGET_POWERPC64"
ca7f5001 11817 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
b19003d8 11818 [(set_attr "length" "12")])
1fd4e8c1 11819
f9562f27
DE		 11820(define_insn ""
11821 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11822 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
11823 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11824 "TARGET_POWERPC64"
11825 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
11826 [(set_attr "length" "12")])
11827
11828(define_insn ""
9ebbca7d 11829 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 11830 (compare:CC
9ebbca7d
GK		 11831 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11832 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
f9562f27 11833 (const_int 0)))
9ebbca7d 11834 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
f9562f27
DE		 11835 (leu:DI (match_dup 1) (match_dup 2)))]
11836 "TARGET_POWERPC64"
9ebbca7d
GK		 11837 "@
11838 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
11839 #"
f9562f27 11840 [(set_attr "type" "compare")
9ebbca7d
GK		 11841 (set_attr "length" "12,16")])
11842
11843(define_split
11844 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11845 (compare:CC
11846 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
11847 (match_operand:DI 2 "reg_or_short_operand" ""))
11848 (const_int 0)))
11849 (set (match_operand:DI 0 "gpc_reg_operand" "")
11850 (leu:DI (match_dup 1) (match_dup 2)))]
11851 "TARGET_POWERPC64 && reload_completed"
11852 [(set (match_dup 0)
11853 (leu:DI (match_dup 1) (match_dup 2)))
11854 (set (match_dup 3)
11855 (compare:CC (match_dup 0)
11856 (const_int 0)))]
11857 "")
f9562f27 11858
1fd4e8c1 11859(define_insn ""
9ebbca7d 11860 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 11861 (compare:CC
9ebbca7d
GK		 11862 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11863 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 11864 (const_int 0)))
9ebbca7d 11865 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 11866 (leu:SI (match_dup 1) (match_dup 2)))]
f9562f27 11867 "! TARGET_POWERPC64"
9ebbca7d
GK		 11868 "@
11869 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11870 #"
b19003d8 11871 [(set_attr "type" "compare")
9ebbca7d
GK		 11872 (set_attr "length" "12,16")])
11873
11874(define_split
11875 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11876 (compare:CC
11877 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11878 (match_operand:SI 2 "reg_or_short_operand" ""))
11879 (const_int 0)))
11880 (set (match_operand:SI 0 "gpc_reg_operand" "")
11881 (leu:SI (match_dup 1) (match_dup 2)))]
11882 "! TARGET_POWERPC64 && reload_completed"
11883 [(set (match_dup 0)
11884 (leu:SI (match_dup 1) (match_dup 2)))
11885 (set (match_dup 3)
11886 (compare:CC (match_dup 0)
11887 (const_int 0)))]
11888 "")
1fd4e8c1 11889
f9562f27 11890(define_insn ""
9ebbca7d 11891 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 11892 (compare:CC
9ebbca7d
GK		 11893 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11894 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
f9562f27 11895 (const_int 0)))
9ebbca7d 11896 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
f9562f27
DE		 11897 (leu:DI (match_dup 1) (match_dup 2)))]
11898 "TARGET_POWERPC64"
9ebbca7d
GK		 11899 "@
11900 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
11901 #"
f9562f27 11902 [(set_attr "type" "compare")
9ebbca7d 11903 (set_attr "length" "12,16")])
f9562f27 11904
1fd4e8c1 11905(define_insn ""
80103f96 11906 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 11907 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11908 (match_operand:SI 2 "reg_or_short_operand" "rI"))
80103f96 11909 (match_operand:SI 3 "gpc_reg_operand" "r")))]
f9562f27 11910 "! TARGET_POWERPC64"
80103f96 11911 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
b19003d8 11912 [(set_attr "length" "8")])
1fd4e8c1
RK		 11913
11914(define_insn ""
9ebbca7d 11915 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 11916 (compare:CC
9ebbca7d
GK		 11917 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11918 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11919 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 11920 (const_int 0)))
9ebbca7d 11921 (clobber (match_scratch:SI 4 "=&r,&r"))]
f9562f27 11922 "! TARGET_POWERPC64"
9ebbca7d
GK		 11923 "@
11924 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
11925 #"
b19003d8 11926 [(set_attr "type" "compare")
9ebbca7d
GK		 11927 (set_attr "length" "8,12")])
11928
11929(define_split
11930 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11931 (compare:CC
11932 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11933 (match_operand:SI 2 "reg_or_short_operand" ""))
11934 (match_operand:SI 3 "gpc_reg_operand" ""))
11935 (const_int 0)))
11936 (clobber (match_scratch:SI 4 ""))]
11937 "! TARGET_POWERPC64 && reload_completed"
11938 [(set (match_dup 4)
11939 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
11940 (match_dup 3)))
11941 (set (match_dup 0)
11942 (compare:CC (match_dup 4)
11943 (const_int 0)))]
11944 "")
1fd4e8c1
RK		 11945
11946(define_insn ""
097657c3 11947 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 11948 (compare:CC
9ebbca7d
GK		 11949 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11950 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11951 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 11952 (const_int 0)))
097657c3
AM		 11953 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
11954 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
f9562f27 11955 "! TARGET_POWERPC64"
9ebbca7d 11956 "@
097657c3 11957 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
9ebbca7d 11958 #"
b19003d8 11959 [(set_attr "type" "compare")
9ebbca7d
GK		 11960 (set_attr "length" "8,12")])
11961
11962(define_split
097657c3 11963 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 11964 (compare:CC
11965 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11966 (match_operand:SI 2 "reg_or_short_operand" ""))
11967 (match_operand:SI 3 "gpc_reg_operand" ""))
11968 (const_int 0)))
11969 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 11970 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 11971 "! TARGET_POWERPC64 && reload_completed"
097657c3 11972 [(set (match_dup 0)
9ebbca7d 11973 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 11974 (set (match_dup 4)
9ebbca7d
GK		 11975 (compare:CC (match_dup 0)
11976 (const_int 0)))]
11977 "")
1fd4e8c1
RK		 11978
11979(define_insn ""
cd2b37d9
RK		 11980 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11981 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11982 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
f9562f27 11983 "! TARGET_POWERPC64"
ca7f5001 11984 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
b19003d8 11985 [(set_attr "length" "12")])
1fd4e8c1
RK		 11986
11987(define_insn ""
097657c3 11988 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
1fd4e8c1 11989 (and:SI (neg:SI
cd2b37d9 11990 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11991 (match_operand:SI 2 "reg_or_short_operand" "rI")))
097657c3 11992 (match_operand:SI 3 "gpc_reg_operand" "r")))]
f9562f27 11993 "! TARGET_POWERPC64"
097657c3 11994 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
b19003d8 11995 [(set_attr "length" "12")])
1fd4e8c1
RK		 11996
11997(define_insn ""
9ebbca7d 11998 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 11999 (compare:CC
12000 (and:SI (neg:SI
9ebbca7d
GK		 12001 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12002 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12003 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12004 (const_int 0)))
9ebbca7d 12005 (clobber (match_scratch:SI 4 "=&r,&r"))]
f9562f27 12006 "! TARGET_POWERPC64"
9ebbca7d
GK		 12007 "@
12008 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12009 #"
12010 [(set_attr "type" "compare")
12011 (set_attr "length" "12,16")])
12012
12013(define_split
12014 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12015 (compare:CC
12016 (and:SI (neg:SI
12017 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12018 (match_operand:SI 2 "reg_or_short_operand" "")))
12019 (match_operand:SI 3 "gpc_reg_operand" ""))
12020 (const_int 0)))
12021 (clobber (match_scratch:SI 4 ""))]
12022 "! TARGET_POWERPC64 && reload_completed"
12023 [(set (match_dup 4)
097657c3
AM		 12024 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12025 (match_dup 3)))
9ebbca7d
GK		 12026 (set (match_dup 0)
12027 (compare:CC (match_dup 4)
12028 (const_int 0)))]
12029 "")
1fd4e8c1
RK		 12030
12031(define_insn ""
097657c3 12032 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12033 (compare:CC
12034 (and:SI (neg:SI
9ebbca7d
GK		 12035 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12036 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12037 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12038 (const_int 0)))
097657c3
AM		 12039 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12040 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
f9562f27 12041 "! TARGET_POWERPC64"
9ebbca7d 12042 "@
097657c3 12043 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d 12044 #"
b19003d8 12045 [(set_attr "type" "compare")
9ebbca7d
GK		 12046 (set_attr "length" "12,16")])
12047
12048(define_split
097657c3 12049 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12050 (compare:CC
12051 (and:SI (neg:SI
12052 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12053 (match_operand:SI 2 "reg_or_short_operand" "")))
12054 (match_operand:SI 3 "gpc_reg_operand" ""))
12055 (const_int 0)))
12056 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12057 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
9ebbca7d 12058 "! TARGET_POWERPC64 && reload_completed"
097657c3
AM		 12059 [(set (match_dup 0)
12060 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12061 (match_dup 3)))
12062 (set (match_dup 4)
9ebbca7d
GK		 12063 (compare:CC (match_dup 0)
12064 (const_int 0)))]
12065 "")
1fd4e8c1
RK		 12066
12067(define_insn ""
cd2b37d9
RK		 12068 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12069 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12070 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
ca7f5001 12071 "TARGET_POWER"
7f340546 12072 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12073 [(set_attr "length" "12")])
1fd4e8c1
RK		 12074
12075(define_insn ""
9ebbca7d 12076 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 12077 (compare:CC
9ebbca7d
GK		 12078 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12079 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12080 (const_int 0)))
9ebbca7d 12081 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 12082 (lt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 12083 "TARGET_POWER"
9ebbca7d
GK		 12084 "@
12085 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12086 #"
29ae5b89 12087 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 12088 (set_attr "length" "12,16")])
12089
12090(define_split
12091 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12092 (compare:CC
12093 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12094 (match_operand:SI 2 "reg_or_short_operand" ""))
12095 (const_int 0)))
12096 (set (match_operand:SI 0 "gpc_reg_operand" "")
12097 (lt:SI (match_dup 1) (match_dup 2)))]
12098 "TARGET_POWER && reload_completed"
12099 [(set (match_dup 0)
12100 (lt:SI (match_dup 1) (match_dup 2)))
12101 (set (match_dup 3)
12102 (compare:CC (match_dup 0)
12103 (const_int 0)))]
12104 "")
1fd4e8c1
RK		 12105
12106(define_insn ""
097657c3 12107 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 12108 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12109 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 12110 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 12111 "TARGET_POWER"
097657c3 12112 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 12113 [(set_attr "length" "12")])
1fd4e8c1
RK		 12114
12115(define_insn ""
9ebbca7d 12116 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12117 (compare:CC
9ebbca7d
GK		 12118 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12119 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12120 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12121 (const_int 0)))
9ebbca7d 12122 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 12123 "TARGET_POWER"
9ebbca7d
GK		 12124 "@
12125 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12126 #"
b19003d8 12127 [(set_attr "type" "compare")
9ebbca7d
GK		 12128 (set_attr "length" "12,16")])
12129
12130(define_split
12131 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12132 (compare:CC
12133 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12134 (match_operand:SI 2 "reg_or_short_operand" ""))
12135 (match_operand:SI 3 "gpc_reg_operand" ""))
12136 (const_int 0)))
12137 (clobber (match_scratch:SI 4 ""))]
12138 "TARGET_POWER && reload_completed"
12139 [(set (match_dup 4)
12140 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
097657c3 12141 (match_dup 3)))
9ebbca7d
GK		 12142 (set (match_dup 0)
12143 (compare:CC (match_dup 4)
12144 (const_int 0)))]
12145 "")
1fd4e8c1
RK		 12146
12147(define_insn ""
097657c3 12148 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12149 (compare:CC
9ebbca7d
GK		 12150 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12151 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12152 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12153 (const_int 0)))
097657c3
AM		 12154 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12155 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12156 "TARGET_POWER"
9ebbca7d 12157 "@
097657c3 12158 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 12159 #"
b19003d8 12160 [(set_attr "type" "compare")
9ebbca7d
GK		 12161 (set_attr "length" "12,16")])
12162
12163(define_split
097657c3 12164 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12165 (compare:CC
12166 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12167 (match_operand:SI 2 "reg_or_short_operand" ""))
12168 (match_operand:SI 3 "gpc_reg_operand" ""))
12169 (const_int 0)))
12170 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12171 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12172 "TARGET_POWER && reload_completed"
097657c3 12173 [(set (match_dup 0)
9ebbca7d 12174 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12175 (set (match_dup 4)
9ebbca7d
GK		 12176 (compare:CC (match_dup 0)
12177 (const_int 0)))]
12178 "")
1fd4e8c1
RK		 12179
12180(define_insn ""
cd2b37d9
RK		 12181 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12182 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12183 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 12184 "TARGET_POWER"
12185 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 12186 [(set_attr "length" "12")])
1fd4e8c1
RK		 12187
12188(define_insn ""
cd2b37d9
RK		 12189 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12190 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12191 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
f9562f27 12192 "! TARGET_POWERPC64"
1fd4e8c1 12193 "@
ca7f5001
RK		 12194 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
12195 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
b19003d8 12196 [(set_attr "length" "12")])
1fd4e8c1
RK		 12197
12198(define_insn ""
9ebbca7d 12199 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12200 (compare:CC
9ebbca7d
GK		 12201 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12202 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 12203 (const_int 0)))
9ebbca7d 12204 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 12205 (ltu:SI (match_dup 1) (match_dup 2)))]
f9562f27 12206 "! TARGET_POWERPC64"
1fd4e8c1 12207 "@
ca7f5001 12208 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
9ebbca7d
GK		 12209 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12210 #
12211 #"
b19003d8 12212 [(set_attr "type" "compare")
9ebbca7d
GK		 12213 (set_attr "length" "12,12,16,16")])
12214
12215(define_split
12216 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12217 (compare:CC
12218 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12219 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12220 (const_int 0)))
12221 (set (match_operand:SI 0 "gpc_reg_operand" "")
12222 (ltu:SI (match_dup 1) (match_dup 2)))]
12223 "! TARGET_POWERPC64 && reload_completed"
12224 [(set (match_dup 0)
12225 (ltu:SI (match_dup 1) (match_dup 2)))
12226 (set (match_dup 3)
12227 (compare:CC (match_dup 0)
12228 (const_int 0)))]
12229 "")
1fd4e8c1
RK		 12230
12231(define_insn ""
80103f96 12232 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
19378cf8
MM		 12233 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12234 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
80103f96 12235 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
f9562f27 12236 "! TARGET_POWERPC64"
1fd4e8c1 12237 "@
80103f96
FS		 12238 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
12239 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
b19003d8 12240 [(set_attr "length" "12")])
1fd4e8c1
RK		 12241
12242(define_insn ""
9ebbca7d 12243 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12244 (compare:CC
9ebbca7d
GK		 12245 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12246 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12247 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12248 (const_int 0)))
9ebbca7d 12249 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
f9562f27 12250 "! TARGET_POWERPC64"
1fd4e8c1 12251 "@
ca7f5001 12252 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
9ebbca7d
GK		 12253 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12254 #
12255 #"
b19003d8 12256 [(set_attr "type" "compare")
9ebbca7d
GK		 12257 (set_attr "length" "12,12,16,16")])
12258
12259(define_split
12260 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12261 (compare:CC
12262 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12263 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12264 (match_operand:SI 3 "gpc_reg_operand" ""))
12265 (const_int 0)))
12266 (clobber (match_scratch:SI 4 ""))]
12267 "! TARGET_POWERPC64 && reload_completed"
12268 [(set (match_dup 4)
12269 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
097657c3 12270 (match_dup 3)))
9ebbca7d
GK		 12271 (set (match_dup 0)
12272 (compare:CC (match_dup 4)
12273 (const_int 0)))]
12274 "")
1fd4e8c1
RK		 12275
12276(define_insn ""
097657c3 12277 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12278 (compare:CC
9ebbca7d
GK		 12279 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12280 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12281 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12282 (const_int 0)))
097657c3
AM		 12283 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12284 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
f9562f27 12285 "! TARGET_POWERPC64"
1fd4e8c1 12286 "@
097657c3
AM		 12287 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12288 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
9ebbca7d
GK		 12289 #
12290 #"
b19003d8 12291 [(set_attr "type" "compare")
9ebbca7d
GK		 12292 (set_attr "length" "12,12,16,16")])
12293
12294(define_split
097657c3 12295 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12296 (compare:CC
12297 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12298 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12299 (match_operand:SI 3 "gpc_reg_operand" ""))
12300 (const_int 0)))
12301 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12302 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12303 "! TARGET_POWERPC64 && reload_completed"
097657c3 12304 [(set (match_dup 0)
9ebbca7d 12305 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12306 (set (match_dup 4)
9ebbca7d
GK		 12307 (compare:CC (match_dup 0)
12308 (const_int 0)))]
12309 "")
1fd4e8c1
RK		 12310
12311(define_insn ""
cd2b37d9
RK		 12312 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12313 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12314 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
f9562f27 12315 "! TARGET_POWERPC64"
1fd4e8c1 12316 "@
ca7f5001
RK		 12317 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12318 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
b19003d8 12319 [(set_attr "length" "8")])
1fd4e8c1
RK		 12320
12321(define_insn ""
cd2b37d9
RK		 12322 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12323 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 12324 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12325 (clobber (match_scratch:SI 3 "=r"))]
ca7f5001
RK		 12326 "TARGET_POWER"
12327 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
b19003d8 12328 [(set_attr "length" "12")])
1fd4e8c1 12329
9ebbca7d
GK		 12330(define_insn ""
12331 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12332 (compare:CC
9ebbca7d
GK		 12333 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12334 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12335 (const_int 0)))
9ebbca7d 12336 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 12337 (ge:SI (match_dup 1) (match_dup 2)))
9ebbca7d 12338 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 12339 "TARGET_POWER"
9ebbca7d
GK		 12340 "@
12341 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12342 #"
12343 [(set_attr "type" "compare")
12344 (set_attr "length" "12,16")])
12345
12346(define_split
12347 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12348 (compare:CC
12349 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12350 (match_operand:SI 2 "reg_or_short_operand" ""))
12351 (const_int 0)))
12352 (set (match_operand:SI 0 "gpc_reg_operand" "")
12353 (ge:SI (match_dup 1) (match_dup 2)))
12354 (clobber (match_scratch:SI 3 ""))]
12355 "TARGET_POWER && reload_completed"
12356 [(parallel [(set (match_dup 0)
097657c3
AM		 12357 (ge:SI (match_dup 1) (match_dup 2)))
12358 (clobber (match_dup 3))])
9ebbca7d
GK		 12359 (set (match_dup 4)
12360 (compare:CC (match_dup 0)
12361 (const_int 0)))]
12362 "")
12363
1fd4e8c1 12364(define_insn ""
097657c3 12365 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 12366 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12367 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 12368 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 12369 "TARGET_POWER"
097657c3 12370 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
b19003d8 12371 [(set_attr "length" "12")])
1fd4e8c1
RK		 12372
12373(define_insn ""
9ebbca7d 12374 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12375 (compare:CC
9ebbca7d
GK		 12376 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12377 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12378 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12379 (const_int 0)))
9ebbca7d 12380 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 12381 "TARGET_POWER"
9ebbca7d
GK		 12382 "@
12383 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12384 #"
b19003d8 12385 [(set_attr "type" "compare")
9ebbca7d
GK		 12386 (set_attr "length" "12,16")])
12387
12388(define_split
12389 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12390 (compare:CC
12391 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12392 (match_operand:SI 2 "reg_or_short_operand" ""))
12393 (match_operand:SI 3 "gpc_reg_operand" ""))
12394 (const_int 0)))
12395 (clobber (match_scratch:SI 4 ""))]
12396 "TARGET_POWER && reload_completed"
12397 [(set (match_dup 4)
12398 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
097657c3 12399 (match_dup 3)))
9ebbca7d
GK		 12400 (set (match_dup 0)
12401 (compare:CC (match_dup 4)
12402 (const_int 0)))]
12403 "")
1fd4e8c1
RK		 12404
12405(define_insn ""
097657c3 12406 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12407 (compare:CC
9ebbca7d
GK		 12408 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12409 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12410 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12411 (const_int 0)))
097657c3
AM		 12412 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12413 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12414 "TARGET_POWER"
9ebbca7d 12415 "@
097657c3 12416 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d 12417 #"
b19003d8 12418 [(set_attr "type" "compare")
9ebbca7d
GK		 12419 (set_attr "length" "12,16")])
12420
12421(define_split
097657c3 12422 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12423 (compare:CC
12424 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12425 (match_operand:SI 2 "reg_or_short_operand" ""))
12426 (match_operand:SI 3 "gpc_reg_operand" ""))
12427 (const_int 0)))
12428 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12429 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12430 "TARGET_POWER && reload_completed"
097657c3 12431 [(set (match_dup 0)
9ebbca7d 12432 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12433 (set (match_dup 4)
9ebbca7d
GK		 12434 (compare:CC (match_dup 0)
12435 (const_int 0)))]
12436 "")
1fd4e8c1
RK		 12437
12438(define_insn ""
cd2b37d9
RK		 12439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12440 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12441 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 12442 "TARGET_POWER"
12443 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 12444 [(set_attr "length" "12")])
1fd4e8c1 12445
1fd4e8c1 12446(define_insn ""
cd2b37d9
RK		 12447 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12448 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12449 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
f9562f27 12450 "! TARGET_POWERPC64"
1fd4e8c1 12451 "@
ca7f5001
RK		 12452 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12453 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
b19003d8 12454 [(set_attr "length" "12")])
1fd4e8c1 12455
f9562f27
DE		 12456(define_insn ""
12457 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12458 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12459 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
12460 "TARGET_POWERPC64"
12461 "@
12462 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12463 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12464 [(set_attr "length" "12")])
12465
1fd4e8c1 12466(define_insn ""
9ebbca7d 12467 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12468 (compare:CC
9ebbca7d
GK		 12469 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12470 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 12471 (const_int 0)))
9ebbca7d 12472 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 12473 (geu:SI (match_dup 1) (match_dup 2)))]
f9562f27 12474 "! TARGET_POWERPC64"
1fd4e8c1 12475 "@
ca7f5001 12476 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
9ebbca7d
GK		 12477 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12478 #
12479 #"
b19003d8 12480 [(set_attr "type" "compare")
9ebbca7d
GK		 12481 (set_attr "length" "12,12,16,16")])
12482
12483(define_split
12484 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12485 (compare:CC
12486 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12487 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12488 (const_int 0)))
12489 (set (match_operand:SI 0 "gpc_reg_operand" "")
12490 (geu:SI (match_dup 1) (match_dup 2)))]
12491 "! TARGET_POWERPC64 && reload_completed"
12492 [(set (match_dup 0)
12493 (geu:SI (match_dup 1) (match_dup 2)))
12494 (set (match_dup 3)
12495 (compare:CC (match_dup 0)
12496 (const_int 0)))]
12497 "")
1fd4e8c1 12498
f9562f27 12499(define_insn ""
9ebbca7d 12500 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 12501 (compare:CC
9ebbca7d
GK		 12502 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12503 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
f9562f27 12504 (const_int 0)))
9ebbca7d 12505 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
f9562f27
DE		 12506 (geu:DI (match_dup 1) (match_dup 2)))]
12507 "TARGET_POWERPC64"
12508 "@
12509 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
9ebbca7d
GK		 12510 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12511 #
12512 #"
f9562f27 12513 [(set_attr "type" "compare")
9ebbca7d
GK		 12514 (set_attr "length" "12,12,16,16")])
12515
12516(define_split
12517 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12518 (compare:CC
12519 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12520 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12521 (const_int 0)))
12522 (set (match_operand:DI 0 "gpc_reg_operand" "")
12523 (geu:DI (match_dup 1) (match_dup 2)))]
12524 "TARGET_POWERPC64 && reload_completed"
12525 [(set (match_dup 0)
12526 (geu:DI (match_dup 1) (match_dup 2)))
12527 (set (match_dup 3)
12528 (compare:CC (match_dup 0)
12529 (const_int 0)))]
12530 "")
f9562f27 12531
1fd4e8c1 12532(define_insn ""
80103f96 12533 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
cd2b37d9 12534 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12535 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
80103f96 12536 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
f9562f27 12537 "! TARGET_POWERPC64"
1fd4e8c1 12538 "@
80103f96
FS		 12539 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12540 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
b19003d8 12541 [(set_attr "length" "8")])
1fd4e8c1
RK		 12542
12543(define_insn ""
9ebbca7d 12544 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12545 (compare:CC
9ebbca7d
GK		 12546 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12547 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12548 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12549 (const_int 0)))
9ebbca7d 12550 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
f9562f27 12551 "! TARGET_POWERPC64"
1fd4e8c1 12552 "@
ca7f5001 12553 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12554 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12555 #
12556 #"
b19003d8 12557 [(set_attr "type" "compare")
9ebbca7d
GK		 12558 (set_attr "length" "8,8,12,12")])
12559
12560(define_split
12561 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12562 (compare:CC
12563 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12564 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12565 (match_operand:SI 3 "gpc_reg_operand" ""))
12566 (const_int 0)))
12567 (clobber (match_scratch:SI 4 ""))]
12568 "! TARGET_POWERPC64 && reload_completed"
12569 [(set (match_dup 4)
12570 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12571 (match_dup 3)))
12572 (set (match_dup 0)
12573 (compare:CC (match_dup 4)
12574 (const_int 0)))]
12575 "")
1fd4e8c1
RK		 12576
12577(define_insn ""
097657c3 12578 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12579 (compare:CC
9ebbca7d
GK		 12580 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12581 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12582 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12583 (const_int 0)))
097657c3
AM		 12584 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12585 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
f9562f27 12586 "! TARGET_POWERPC64"
1fd4e8c1 12587 "@
097657c3
AM		 12588 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12589 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12590 #
12591 #"
b19003d8 12592 [(set_attr "type" "compare")
9ebbca7d
GK		 12593 (set_attr "length" "8,8,12,12")])
12594
12595(define_split
097657c3 12596 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12597 (compare:CC
12598 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12599 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12600 (match_operand:SI 3 "gpc_reg_operand" ""))
12601 (const_int 0)))
12602 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12603 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12604 "! TARGET_POWERPC64 && reload_completed"
097657c3 12605 [(set (match_dup 0)
9ebbca7d 12606 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12607 (set (match_dup 4)
9ebbca7d
GK		 12608 (compare:CC (match_dup 0)
12609 (const_int 0)))]
12610 "")
1fd4e8c1
RK		 12611
12612(define_insn ""
cd2b37d9
RK		 12613 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12614 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12615 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
f9562f27 12616 "! TARGET_POWERPC64"
1fd4e8c1 12617 "@
ca7f5001 12618 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
8106dc08 12619 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
b19003d8 12620 [(set_attr "length" "12")])
1fd4e8c1
RK		 12621
12622(define_insn ""
097657c3 12623 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
1fd4e8c1 12624 (and:SI (neg:SI
cd2b37d9 12625 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12626 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
097657c3 12627 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
f9562f27 12628 "! TARGET_POWERPC64"
1fd4e8c1 12629 "@
097657c3
AM		 12630 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12631 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
b19003d8 12632 [(set_attr "length" "12")])
1fd4e8c1
RK		 12633
12634(define_insn ""
9ebbca7d 12635 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 12636 (compare:CC
12637 (and:SI (neg:SI
9ebbca7d
GK		 12638 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12639 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12640 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12641 (const_int 0)))
9ebbca7d 12642 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
f9562f27 12643 "! TARGET_POWERPC64"
1fd4e8c1 12644 "@
ca7f5001 12645 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
9ebbca7d
GK		 12646 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12647 #
12648 #"
b19003d8 12649 [(set_attr "type" "compare")
9ebbca7d
GK		 12650 (set_attr "length" "12,12,16,16")])
12651
12652(define_split
12653 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12654 (compare:CC
12655 (and:SI (neg:SI
12656 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12657 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12658 (match_operand:SI 3 "gpc_reg_operand" ""))
12659 (const_int 0)))
12660 (clobber (match_scratch:SI 4 ""))]
12661 "! TARGET_POWERPC64 && reload_completed"
12662 [(set (match_dup 4)
097657c3
AM		 12663 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12664 (match_dup 3)))
9ebbca7d
GK		 12665 (set (match_dup 0)
12666 (compare:CC (match_dup 4)
12667 (const_int 0)))]
12668 "")
1fd4e8c1
RK		 12669
12670(define_insn ""
097657c3 12671 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 12672 (compare:CC
12673 (and:SI (neg:SI
9ebbca7d
GK		 12674 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12675 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12676 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12677 (const_int 0)))
097657c3
AM		 12678 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12679 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
f9562f27 12680 "! TARGET_POWERPC64"
1fd4e8c1 12681 "@
097657c3
AM		 12682 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12683 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d
GK		 12684 #
12685 #"
b19003d8 12686 [(set_attr "type" "compare")
9ebbca7d
GK		 12687 (set_attr "length" "12,12,16,16")])
12688
12689(define_split
097657c3 12690 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12691 (compare:CC
12692 (and:SI (neg:SI
12693 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12694 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12695 (match_operand:SI 3 "gpc_reg_operand" ""))
12696 (const_int 0)))
12697 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12698 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
9ebbca7d 12699 "! TARGET_POWERPC64 && reload_completed"
097657c3 12700 [(set (match_dup 0)
9ebbca7d 12701 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
097657c3 12702 (set (match_dup 4)
9ebbca7d
GK		 12703 (compare:CC (match_dup 0)
12704 (const_int 0)))]
12705 "")
1fd4e8c1
RK		 12706
12707(define_insn ""
cd2b37d9
RK		 12708 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12709 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12710 (const_int 0)))]
f9562f27 12711 "! TARGET_POWERPC64"
ca7f5001 12712 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12713 [(set_attr "length" "12")])
1fd4e8c1 12714
f9562f27
DE		 12715(define_insn ""
12716 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12717 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12718 (const_int 0)))]
12719 "TARGET_POWERPC64"
12720 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
12721 [(set_attr "length" "12")])
12722
1fd4e8c1 12723(define_insn ""
9ebbca7d 12724 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1fd4e8c1 12725 (compare:CC
9ebbca7d 12726 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 12727 (const_int 0))
12728 (const_int 0)))
9ebbca7d 12729 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 12730 (gt:SI (match_dup 1) (const_int 0)))]
f9562f27 12731 "! TARGET_POWERPC64"
9ebbca7d
GK		 12732 "@
12733 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
12734 #"
29ae5b89 12735 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 12736 (set_attr "length" "12,16")])
12737
12738(define_split
12739 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12740 (compare:CC
12741 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12742 (const_int 0))
12743 (const_int 0)))
12744 (set (match_operand:SI 0 "gpc_reg_operand" "")
12745 (gt:SI (match_dup 1) (const_int 0)))]
12746 "! TARGET_POWERPC64 && reload_completed"
12747 [(set (match_dup 0)
12748 (gt:SI (match_dup 1) (const_int 0)))
12749 (set (match_dup 2)
12750 (compare:CC (match_dup 0)
12751 (const_int 0)))]
12752 "")
1fd4e8c1 12753
f9562f27 12754(define_insn ""
9ebbca7d 12755 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
f9562f27 12756 (compare:CC
9ebbca7d 12757 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27
DE		 12758 (const_int 0))
12759 (const_int 0)))
9ebbca7d 12760 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
f9562f27
DE		 12761 (gt:DI (match_dup 1) (const_int 0)))]
12762 "TARGET_POWERPC64"
9ebbca7d
GK		 12763 "@
12764 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
12765 #"
f9562f27 12766 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 12767 (set_attr "length" "12,16")])
12768
12769(define_split
12770 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12771 (compare:CC
12772 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12773 (const_int 0))
12774 (const_int 0)))
12775 (set (match_operand:DI 0 "gpc_reg_operand" "")
12776 (gt:DI (match_dup 1) (const_int 0)))]
12777 "TARGET_POWERPC64 && reload_completed"
12778 [(set (match_dup 0)
12779 (gt:DI (match_dup 1) (const_int 0)))
12780 (set (match_dup 2)
12781 (compare:CC (match_dup 0)
12782 (const_int 0)))]
12783 "")
f9562f27 12784
1fd4e8c1 12785(define_insn ""
cd2b37d9
RK		 12786 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12787 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12788 (match_operand:SI 2 "reg_or_short_operand" "r")))]
ca7f5001
RK		 12789 "TARGET_POWER"
12790 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12791 [(set_attr "length" "12")])
1fd4e8c1
RK		 12792
12793(define_insn ""
9ebbca7d 12794 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 12795 (compare:CC
9ebbca7d
GK		 12796 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12797 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
1fd4e8c1 12798 (const_int 0)))
9ebbca7d 12799 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 12800 (gt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 12801 "TARGET_POWER"
9ebbca7d
GK		 12802 "@
12803 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12804 #"
29ae5b89 12805 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 12806 (set_attr "length" "12,16")])
12807
12808(define_split
12809 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12810 (compare:CC
12811 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12812 (match_operand:SI 2 "reg_or_short_operand" ""))
12813 (const_int 0)))
12814 (set (match_operand:SI 0 "gpc_reg_operand" "")
12815 (gt:SI (match_dup 1) (match_dup 2)))]
12816 "TARGET_POWER && reload_completed"
12817 [(set (match_dup 0)
12818 (gt:SI (match_dup 1) (match_dup 2)))
12819 (set (match_dup 3)
12820 (compare:CC (match_dup 0)
12821 (const_int 0)))]
12822 "")
1fd4e8c1
RK		 12823
12824(define_insn ""
80103f96 12825 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 12826 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12827 (const_int 0))
80103f96 12828 (match_operand:SI 2 "gpc_reg_operand" "r")))]
f9562f27 12829 "! TARGET_POWERPC64"
80103f96 12830 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
b19003d8 12831 [(set_attr "length" "12")])
1fd4e8c1 12832
f9562f27 12833(define_insn ""
097657c3 12834 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
f9562f27
DE		 12835 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12836 (const_int 0))
097657c3 12837 (match_operand:DI 2 "gpc_reg_operand" "r")))]
f9562f27 12838 "TARGET_POWERPC64"
097657c3 12839 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
f9562f27
DE		 12840 [(set_attr "length" "12")])
12841
1fd4e8c1 12842(define_insn ""
9ebbca7d 12843 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12844 (compare:CC
9ebbca7d 12845 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12846 (const_int 0))
9ebbca7d 12847 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12848 (const_int 0)))
9ebbca7d 12849 (clobber (match_scratch:SI 3 "=&r,&r"))]
f9562f27 12850 "! TARGET_POWERPC64"
9ebbca7d
GK		 12851 "@
12852 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
12853 #"
b19003d8 12854 [(set_attr "type" "compare")
9ebbca7d
GK		 12855 (set_attr "length" "12,16")])
12856
12857(define_split
12858 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12859 (compare:CC
12860 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12861 (const_int 0))
12862 (match_operand:SI 2 "gpc_reg_operand" ""))
12863 (const_int 0)))
12864 (clobber (match_scratch:SI 3 ""))]
12865 "! TARGET_POWERPC64 && reload_completed"
12866 [(set (match_dup 3)
12867 (plus:SI (gt:SI (match_dup 1) (const_int 0))
12868 (match_dup 2)))
12869 (set (match_dup 0)
12870 (compare:CC (match_dup 3)
12871 (const_int 0)))]
12872 "")
1fd4e8c1 12873
f9562f27 12874(define_insn ""
9ebbca7d 12875 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
f9562f27 12876 (compare:CC
9ebbca7d 12877 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 12878 (const_int 0))
9ebbca7d 12879 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 12880 (const_int 0)))
9ebbca7d 12881 (clobber (match_scratch:DI 3 "=&r,&r"))]
f9562f27 12882 "TARGET_POWERPC64"
9ebbca7d
GK		 12883 "@
12884 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
12885 #"
f9562f27 12886 [(set_attr "type" "compare")
9ebbca7d
GK		 12887 (set_attr "length" "12,16")])
12888
12889(define_split
12890 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12891 (compare:CC
12892 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12893 (const_int 0))
12894 (match_operand:DI 2 "gpc_reg_operand" ""))
12895 (const_int 0)))
12896 (clobber (match_scratch:DI 3 ""))]
12897 "TARGET_POWERPC64 && reload_completed"
12898 [(set (match_dup 3)
12899 (plus:DI (gt:DI (match_dup 1) (const_int 0))
097657c3 12900 (match_dup 2)))
9ebbca7d
GK		 12901 (set (match_dup 0)
12902 (compare:CC (match_dup 3)
12903 (const_int 0)))]
12904 "")
f9562f27 12905
1fd4e8c1 12906(define_insn ""
097657c3 12907 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9ebbca7d
GK		 12908 (compare:CC
12909 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12910 (const_int 0))
12911 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12912 (const_int 0)))
097657c3
AM		 12913 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12914 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
9ebbca7d
GK		 12915 "! TARGET_POWERPC64"
12916 "@
097657c3 12917 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
9ebbca7d
GK		 12918 #"
12919 [(set_attr "type" "compare")
12920 (set_attr "length" "12,16")])
12921
12922(define_split
097657c3 12923 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1fd4e8c1 12924 (compare:CC
9ebbca7d 12925 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 12926 (const_int 0))
9ebbca7d 12927 (match_operand:SI 2 "gpc_reg_operand" ""))
1fd4e8c1 12928 (const_int 0)))
9ebbca7d 12929 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12930 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
9ebbca7d 12931 "! TARGET_POWERPC64 && reload_completed"
097657c3 12932 [(set (match_dup 0)
9ebbca7d 12933 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 12934 (set (match_dup 3)
9ebbca7d
GK		 12935 (compare:CC (match_dup 0)
12936 (const_int 0)))]
12937 "")
1fd4e8c1 12938
f9562f27 12939(define_insn ""
097657c3 12940 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 12941 (compare:CC
9ebbca7d 12942 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 12943 (const_int 0))
9ebbca7d 12944 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 12945 (const_int 0)))
097657c3
AM		 12946 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
12947 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
f9562f27 12948 "TARGET_POWERPC64"
9ebbca7d 12949 "@
097657c3 12950 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
9ebbca7d 12951 #"
f9562f27 12952 [(set_attr "type" "compare")
9ebbca7d
GK		 12953 (set_attr "length" "12,16")])
12954
12955(define_split
097657c3 12956 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12957 (compare:CC
12958 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12959 (const_int 0))
12960 (match_operand:DI 2 "gpc_reg_operand" ""))
12961 (const_int 0)))
12962 (set (match_operand:DI 0 "gpc_reg_operand" "")
097657c3 12963 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
9ebbca7d 12964 "TARGET_POWERPC64 && reload_completed"
097657c3 12965 [(set (match_dup 0)
9ebbca7d 12966 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 12967 (set (match_dup 3)
9ebbca7d
GK		 12968 (compare:CC (match_dup 0)
12969 (const_int 0)))]
12970 "")
f9562f27 12971
1fd4e8c1 12972(define_insn ""
097657c3 12973 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 12974 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12975 (match_operand:SI 2 "reg_or_short_operand" "r"))
097657c3 12976 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 12977 "TARGET_POWER"
097657c3 12978 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 12979 [(set_attr "length" "12")])
1fd4e8c1
RK		 12980
12981(define_insn ""
9ebbca7d 12982 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12983 (compare:CC
9ebbca7d
GK		 12984 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12985 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12986 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12987 (const_int 0)))
9ebbca7d 12988 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 12989 "TARGET_POWER"
9ebbca7d
GK		 12990 "@
12991 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12992 #"
b19003d8 12993 [(set_attr "type" "compare")
9ebbca7d
GK		 12994 (set_attr "length" "12,16")])
12995
12996(define_split
12997 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12998 (compare:CC
12999 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13000 (match_operand:SI 2 "reg_or_short_operand" ""))
13001 (match_operand:SI 3 "gpc_reg_operand" ""))
13002 (const_int 0)))
13003 (clobber (match_scratch:SI 4 ""))]
13004 "TARGET_POWER && reload_completed"
13005 [(set (match_dup 4)
097657c3 13006 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9ebbca7d
GK		 13007 (set (match_dup 0)
13008 (compare:CC (match_dup 4)
13009 (const_int 0)))]
13010 "")
1fd4e8c1
RK		 13011
13012(define_insn ""
097657c3 13013 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13014 (compare:CC
9ebbca7d
GK		 13015 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13016 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13017 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13018 (const_int 0)))
097657c3
AM		 13019 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13020 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13021 "TARGET_POWER"
9ebbca7d 13022 "@
097657c3 13023 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13024 #"
b19003d8 13025 [(set_attr "type" "compare")
9ebbca7d
GK		 13026 (set_attr "length" "12,16")])
13027
13028(define_split
097657c3 13029 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13030 (compare:CC
13031 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13032 (match_operand:SI 2 "reg_or_short_operand" ""))
13033 (match_operand:SI 3 "gpc_reg_operand" ""))
13034 (const_int 0)))
13035 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13036 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13037 "TARGET_POWER && reload_completed"
097657c3 13038 [(set (match_dup 0)
9ebbca7d 13039 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13040 (set (match_dup 4)
9ebbca7d
GK		 13041 (compare:CC (match_dup 0)
13042 (const_int 0)))]
13043 "")
1fd4e8c1
RK		 13044
13045(define_insn ""
cd2b37d9
RK		 13046 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13047 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13048 (const_int 0))))]
f9562f27 13049 "! TARGET_POWERPC64"
ca7f5001 13050 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13051 [(set_attr "length" "12")])
1fd4e8c1 13052
f9562f27
DE		 13053(define_insn ""
13054 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13055 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13056 (const_int 0))))]
13057 "TARGET_POWERPC64"
8377288b 13058 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
f9562f27
DE		 13059 [(set_attr "length" "12")])
13060
1fd4e8c1 13061(define_insn ""
cd2b37d9
RK		 13062 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13063 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13064 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
ca7f5001
RK		 13065 "TARGET_POWER"
13066 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13067 [(set_attr "length" "12")])
1fd4e8c1
RK		 13068
13069(define_insn ""
cd2b37d9
RK		 13070 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13071 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13072 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
f9562f27 13073 "! TARGET_POWERPC64"
ca7f5001 13074 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
b19003d8 13075 [(set_attr "length" "12")])
1fd4e8c1 13076
f9562f27
DE		 13077(define_insn ""
13078 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13079 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13080 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13081 "TARGET_POWERPC64"
13082 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
13083 [(set_attr "length" "12")])
13084
1fd4e8c1 13085(define_insn ""
9ebbca7d 13086 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13087 (compare:CC
9ebbca7d
GK		 13088 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13089 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13090 (const_int 0)))
9ebbca7d 13091 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13092 (gtu:SI (match_dup 1) (match_dup 2)))]
f9562f27 13093 "! TARGET_POWERPC64"
9ebbca7d
GK		 13094 "@
13095 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13096 #"
b19003d8 13097 [(set_attr "type" "compare")
9ebbca7d
GK		 13098 (set_attr "length" "12,16")])
13099
13100(define_split
13101 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13102 (compare:CC
13103 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13104 (match_operand:SI 2 "reg_or_short_operand" ""))
13105 (const_int 0)))
13106 (set (match_operand:SI 0 "gpc_reg_operand" "")
13107 (gtu:SI (match_dup 1) (match_dup 2)))]
13108 "! TARGET_POWERPC64 && reload_completed"
13109 [(set (match_dup 0)
13110 (gtu:SI (match_dup 1) (match_dup 2)))
13111 (set (match_dup 3)
13112 (compare:CC (match_dup 0)
13113 (const_int 0)))]
13114 "")
1fd4e8c1 13115
f9562f27 13116(define_insn ""
9ebbca7d 13117 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 13118 (compare:CC
9ebbca7d
GK		 13119 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13120 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
f9562f27 13121 (const_int 0)))
9ebbca7d 13122 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
f9562f27
DE		 13123 (gtu:DI (match_dup 1) (match_dup 2)))]
13124 "TARGET_POWERPC64"
9ebbca7d
GK		 13125 "@
13126 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13127 #"
f9562f27 13128 [(set_attr "type" "compare")
9ebbca7d
GK		 13129 (set_attr "length" "12,16")])
13130
13131(define_split
13132 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13133 (compare:CC
13134 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13135 (match_operand:DI 2 "reg_or_short_operand" ""))
13136 (const_int 0)))
13137 (set (match_operand:DI 0 "gpc_reg_operand" "")
13138 (gtu:DI (match_dup 1) (match_dup 2)))]
13139 "TARGET_POWERPC64 && reload_completed"
13140 [(set (match_dup 0)
13141 (gtu:DI (match_dup 1) (match_dup 2)))
13142 (set (match_dup 3)
13143 (compare:CC (match_dup 0)
13144 (const_int 0)))]
13145 "")
f9562f27 13146
1fd4e8c1 13147(define_insn ""
80103f96 13148 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
19378cf8
MM		 13149 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13150 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
80103f96 13151 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
f9562f27 13152 "! TARGET_POWERPC64"
00751805 13153 "@
80103f96
FS		 13154 {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
13155 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
19378cf8 13156 [(set_attr "length" "8,12")])
1fd4e8c1 13157
f9562f27 13158(define_insn ""
097657c3 13159 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
f9562f27
DE		 13160 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13161 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
097657c3 13162 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
f9562f27
DE		 13163 "TARGET_POWERPC64"
13164 "@
097657c3
AM		 13165 addic %0,%1,%k2\;addze %0,%3
13166 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
f9562f27
DE		 13167 [(set_attr "length" "8,12")])
13168
1fd4e8c1 13169(define_insn ""
9ebbca7d 13170 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13171 (compare:CC
9ebbca7d
GK		 13172 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13173 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13174 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13175 (const_int 0)))
9ebbca7d 13176 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
f9562f27 13177 "! TARGET_POWERPC64"
00751805 13178 "@
19378cf8 13179 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
9ebbca7d
GK		 13180 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
13181 #
13182 #"
b19003d8 13183 [(set_attr "type" "compare")
9ebbca7d
GK		 13184 (set_attr "length" "8,12,12,16")])
13185
13186(define_split
13187 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13188 (compare:CC
13189 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13190 (match_operand:SI 2 "reg_or_short_operand" ""))
13191 (match_operand:SI 3 "gpc_reg_operand" ""))
13192 (const_int 0)))
13193 (clobber (match_scratch:SI 4 ""))]
13194 "! TARGET_POWERPC64 && reload_completed"
13195 [(set (match_dup 4)
13196 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
097657c3 13197 (match_dup 3)))
9ebbca7d
GK		 13198 (set (match_dup 0)
13199 (compare:CC (match_dup 4)
13200 (const_int 0)))]
13201 "")
1fd4e8c1 13202
f9562f27 13203(define_insn ""
9ebbca7d 13204 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 13205 (compare:CC
9ebbca7d
GK		 13206 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13207 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13208 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
f9562f27 13209 (const_int 0)))
9ebbca7d 13210 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
f9562f27
DE		 13211 "TARGET_POWERPC64"
13212 "@
13213 addic %4,%1,%k2\;addze. %4,%3
9ebbca7d
GK		 13214 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
13215 #
13216 #"
f9562f27 13217 [(set_attr "type" "compare")
9ebbca7d
GK		 13218 (set_attr "length" "8,12,12,16")])
13219
13220(define_split
13221 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13222 (compare:CC
13223 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13224 (match_operand:DI 2 "reg_or_short_operand" ""))
13225 (match_operand:DI 3 "gpc_reg_operand" ""))
13226 (const_int 0)))
13227 (clobber (match_scratch:DI 4 ""))]
13228 "TARGET_POWERPC64 && reload_completed"
13229 [(set (match_dup 4)
13230 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13231 (match_dup 3)))
13232 (set (match_dup 0)
13233 (compare:CC (match_dup 4)
13234 (const_int 0)))]
13235 "")
f9562f27 13236
1fd4e8c1 13237(define_insn ""
097657c3 13238 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13239 (compare:CC
9ebbca7d
GK		 13240 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13241 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13242 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13243 (const_int 0)))
097657c3
AM		 13244 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13245 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
f9562f27 13246 "! TARGET_POWERPC64"
00751805 13247 "@
097657c3
AM		 13248 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13249 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
9ebbca7d
GK		 13250 #
13251 #"
b19003d8 13252 [(set_attr "type" "compare")
9ebbca7d
GK		 13253 (set_attr "length" "8,12,12,16")])
13254
13255(define_split
097657c3 13256 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13257 (compare:CC
13258 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13259 (match_operand:SI 2 "reg_or_short_operand" ""))
13260 (match_operand:SI 3 "gpc_reg_operand" ""))
13261 (const_int 0)))
13262 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13263 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13264 "! TARGET_POWERPC64 && reload_completed"
097657c3 13265 [(set (match_dup 0)
9ebbca7d 13266 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13267 (set (match_dup 4)
9ebbca7d
GK		 13268 (compare:CC (match_dup 0)
13269 (const_int 0)))]
13270 "")
1fd4e8c1 13271
f9562f27 13272(define_insn ""
097657c3 13273 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 13274 (compare:CC
9ebbca7d
GK		 13275 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13276 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13277 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
f9562f27 13278 (const_int 0)))
097657c3
AM		 13279 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13280 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
f9562f27
DE		 13281 "TARGET_POWERPC64"
13282 "@
097657c3
AM		 13283 addic %0,%1,%k2\;addze. %0,%3
13284 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
9ebbca7d
GK		 13285 #
13286 #"
f9562f27 13287 [(set_attr "type" "compare")
9ebbca7d
GK		 13288 (set_attr "length" "8,12,12,16")])
13289
13290(define_split
097657c3 13291 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13292 (compare:CC
13293 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13294 (match_operand:DI 2 "reg_or_short_operand" ""))
13295 (match_operand:DI 3 "gpc_reg_operand" ""))
13296 (const_int 0)))
13297 (set (match_operand:DI 0 "gpc_reg_operand" "")
097657c3 13298 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13299 "TARGET_POWERPC64 && reload_completed"
097657c3 13300 [(set (match_dup 0)
9ebbca7d 13301 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13302 (set (match_dup 4)
9ebbca7d
GK		 13303 (compare:CC (match_dup 0)
13304 (const_int 0)))]
13305 "")
f9562f27 13306
1fd4e8c1 13307(define_insn ""
cd2b37d9
RK		 13308 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13309 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13310 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
f9562f27 13311 "! TARGET_POWERPC64"
ca7f5001 13312 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
b19003d8 13313 [(set_attr "length" "8")])
f9562f27
DE		 13314
13315(define_insn ""
13316 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13317 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13318 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13319 "TARGET_POWERPC64"
13320 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13321 [(set_attr "length" "8")])
1fd4e8c1
RK		 13322\f
13323;; Define both directions of branch and return. If we need a reload
13324;; register, we'd rather use CR0 since it is much easier to copy a
13325;; register CC value to there.
13326
13327(define_insn ""
13328 [(set (pc)
13329 (if_then_else (match_operator 1 "branch_comparison_operator"
13330 [(match_operand 2
b54cf83a 13331 "cc_reg_operand" "y")
1fd4e8c1
RK		 13332 (const_int 0)])
13333 (label_ref (match_operand 0 "" ""))
13334 (pc)))]
13335 ""
b19003d8
RK		 13336 "*
13337{
12a4e8c5 13338 return output_cbranch (operands[1], \"%l0\", 0, insn);
b19003d8
RK		 13339}"
13340 [(set_attr "type" "branch")])
13341
1fd4e8c1
RK		 13342(define_insn ""
13343 [(set (pc)
13344 (if_then_else (match_operator 0 "branch_comparison_operator"
13345 [(match_operand 1
b54cf83a 13346 "cc_reg_operand" "y")
1fd4e8c1
RK		 13347 (const_int 0)])
13348 (return)
13349 (pc)))]
13350 "direct_return ()"
12a4e8c5
GK		 13351 "*
13352{
13353 return output_cbranch (operands[0], NULL, 0, insn);
13354}"
b7ff3d82 13355 [(set_attr "type" "branch")
39a10a29 13356 (set_attr "length" "4")])
1fd4e8c1
RK		 13357
13358(define_insn ""
13359 [(set (pc)
13360 (if_then_else (match_operator 1 "branch_comparison_operator"
13361 [(match_operand 2
b54cf83a 13362 "cc_reg_operand" "y")
1fd4e8c1
RK		 13363 (const_int 0)])
13364 (pc)
13365 (label_ref (match_operand 0 "" ""))))]
13366 ""
b19003d8
RK		 13367 "*
13368{
12a4e8c5 13369 return output_cbranch (operands[1], \"%l0\", 1, insn);
b19003d8
RK		 13370}"
13371 [(set_attr "type" "branch")])
1fd4e8c1
RK		 13372
13373(define_insn ""
13374 [(set (pc)
13375 (if_then_else (match_operator 0 "branch_comparison_operator"
13376 [(match_operand 1
b54cf83a 13377 "cc_reg_operand" "y")
1fd4e8c1
RK		 13378 (const_int 0)])
13379 (pc)
13380 (return)))]
13381 "direct_return ()"
12a4e8c5
GK		 13382 "*
13383{
13384 return output_cbranch (operands[0], NULL, 1, insn);
13385}"
b7ff3d82 13386 [(set_attr "type" "branch")
39a10a29
GK		 13387 (set_attr "length" "4")])
13388
13389;; Logic on condition register values.
13390
13391; This pattern matches things like
13392; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13393; (eq:SI (reg:CCFP 68) (const_int 0)))
13394; (const_int 1)))
13395; which are generated by the branch logic.
b54cf83a 13396; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
39a10a29
GK		 13397
13398(define_insn ""
b54cf83a 13399 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13400 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
b54cf83a 13401 [(match_operator:SI 2
39a10a29
GK		 13402 "branch_positive_comparison_operator"
13403 [(match_operand 3
b54cf83a 13404 "cc_reg_operand" "y,y")
39a10a29 13405 (const_int 0)])
b54cf83a 13406 (match_operator:SI 4
39a10a29
GK		 13407 "branch_positive_comparison_operator"
13408 [(match_operand 5
b54cf83a 13409 "cc_reg_operand" "0,y")
39a10a29
GK		 13410 (const_int 0)])])
13411 (const_int 1)))]
13412 ""
13413 "cr%q1 %E0,%j2,%j4"
b54cf83a 13414 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 13415
13416; Why is the constant -1 here, but 1 in the previous pattern?
13417; Because ~1 has all but the low bit set.
13418(define_insn ""
b54cf83a 13419 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13420 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
b54cf83a 13421 [(not:SI (match_operator:SI 2
39a10a29
GK		 13422 "branch_positive_comparison_operator"
13423 [(match_operand 3
b54cf83a 13424 "cc_reg_operand" "y,y")
39a10a29
GK		 13425 (const_int 0)]))
13426 (match_operator:SI 4
13427 "branch_positive_comparison_operator"
13428 [(match_operand 5
b54cf83a 13429 "cc_reg_operand" "0,y")
39a10a29
GK		 13430 (const_int 0)])])
13431 (const_int -1)))]
13432 ""
13433 "cr%q1 %E0,%j2,%j4"
b54cf83a 13434 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 13435
13436(define_insn ""
b54cf83a 13437 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
6c873122 13438 (compare:CCEQ (match_operator:SI 1
39a10a29 13439 "branch_positive_comparison_operator"
6c873122 13440 [(match_operand 2
b54cf83a 13441 "cc_reg_operand" "0,y")
39a10a29
GK		 13442 (const_int 0)])
13443 (const_int 0)))]
fe6b547a 13444 "!TARGET_SPE"
251b3667 13445 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
b54cf83a 13446 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 13447
13448;; If we are comparing the result of two comparisons, this can be done
13449;; using creqv or crxor.
13450
13451(define_insn_and_split ""
13452 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13453 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13454 [(match_operand 2 "cc_reg_operand" "y")
13455 (const_int 0)])
13456 (match_operator 3 "branch_comparison_operator"
13457 [(match_operand 4 "cc_reg_operand" "y")
13458 (const_int 0)])))]
13459 ""
13460 "#"
13461 ""
13462 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13463 (match_dup 5)))]
13464 "
13465{
13466 int positive_1, positive_2;
13467
13468 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
13469 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13470
13471 if (! positive_1)
2d4368e6 13472 operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]),
39a10a29 13473 GET_CODE (operands[1])),
2d4368e6
DE		 13474 SImode,
13475 operands[2], const0_rtx);
39a10a29 13476 else if (GET_MODE (operands[1]) != SImode)
2d4368e6
DE		 13477 operands[1] = gen_rtx (GET_CODE (operands[1]),
13478 SImode,
13479 operands[2], const0_rtx);
39a10a29
GK		 13480
13481 if (! positive_2)
2d4368e6 13482 operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]),
39a10a29 13483 GET_CODE (operands[3])),
2d4368e6
DE		 13484 SImode,
13485 operands[4], const0_rtx);
39a10a29 13486 else if (GET_MODE (operands[3]) != SImode)
2d4368e6
DE		 13487 operands[3] = gen_rtx (GET_CODE (operands[3]),
13488 SImode,
13489 operands[4], const0_rtx);
39a10a29
GK		 13490
13491 if (positive_1 == positive_2)
251b3667
DE		 13492 {
13493 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13494 operands[5] = constm1_rtx;
13495 }
13496 else
13497 {
13498 operands[5] = const1_rtx;
13499 }
39a10a29 13500}")
1fd4e8c1
RK		 13501
13502;; Unconditional branch and return.
13503
13504(define_insn "jump"
13505 [(set (pc)
13506 (label_ref (match_operand 0 "" "")))]
13507 ""
b7ff3d82
DE		 13508 "b %l0"
13509 [(set_attr "type" "branch")])
1fd4e8c1
RK		 13510
13511(define_insn "return"
13512 [(return)]
13513 "direct_return ()"
324e52cc
TG		 13514 "{br|blr}"
13515 [(set_attr "type" "jmpreg")])
1fd4e8c1 13516
0ad91047
DE		 13517(define_expand "indirect_jump"
13518 [(set (pc) (match_operand 0 "register_operand" ""))]
1fd4e8c1 13519 ""
0ad91047
DE		 13520 "
13521{
13522 if (TARGET_32BIT)
13523 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13524 else
13525 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13526 DONE;
13527}")
13528
13529(define_insn "indirect_jumpsi"
b92b324d 13530 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
0ad91047 13531 "TARGET_32BIT"
b92b324d
DE		 13532 "@
13533 bctr
13534 {br|blr}"
324e52cc 13535 [(set_attr "type" "jmpreg")])
1fd4e8c1 13536
0ad91047 13537(define_insn "indirect_jumpdi"
b92b324d 13538 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
0ad91047 13539 "TARGET_64BIT"
b92b324d
DE		 13540 "@
13541 bctr
13542 blr"
266eb58a
DE		 13543 [(set_attr "type" "jmpreg")])
13544
1fd4e8c1
RK		 13545;; Table jump for switch statements:
13546(define_expand "tablejump"
e6ca2c17
DE		 13547 [(use (match_operand 0 "" ""))
13548 (use (label_ref (match_operand 1 "" "")))]
13549 ""
13550 "
13551{
13552 if (TARGET_32BIT)
13553 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13554 else
13555 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13556 DONE;
13557}")
13558
13559(define_expand "tablejumpsi"
1fd4e8c1
RK		 13560 [(set (match_dup 3)
13561 (plus:SI (match_operand:SI 0 "" "")
13562 (match_dup 2)))
13563 (parallel [(set (pc) (match_dup 3))
13564 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 13565 "TARGET_32BIT"
1fd4e8c1
RK		 13566 "
13567{ operands[0] = force_reg (SImode, operands[0]);
c5c76735 13568 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
1fd4e8c1
RK		 13569 operands[3] = gen_reg_rtx (SImode);
13570}")
13571
e6ca2c17 13572(define_expand "tablejumpdi"
9ebbca7d
GK		 13573 [(set (match_dup 4)
13574 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13575 (set (match_dup 3)
13576 (plus:DI (match_dup 4)
e6ca2c17
DE		 13577 (match_dup 2)))
13578 (parallel [(set (pc) (match_dup 3))
13579 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 13580 "TARGET_64BIT"
e6ca2c17 13581 "
9ebbca7d 13582{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
e6ca2c17 13583 operands[3] = gen_reg_rtx (DImode);
9ebbca7d 13584 operands[4] = gen_reg_rtx (DImode);
e6ca2c17
DE		 13585}")
13586
1fd4e8c1
RK		 13587(define_insn ""
13588 [(set (pc)
c859cda6 13589 (match_operand:SI 0 "register_operand" "c,*l"))
1fd4e8c1 13590 (use (label_ref (match_operand 1 "" "")))]
0ad91047 13591 "TARGET_32BIT"
c859cda6
DJ		 13592 "@
13593 bctr
13594 {br|blr}"
a6845123 13595 [(set_attr "type" "jmpreg")])
1fd4e8c1 13596
266eb58a
DE		 13597(define_insn ""
13598 [(set (pc)
c859cda6 13599 (match_operand:DI 0 "register_operand" "c,*l"))
266eb58a 13600 (use (label_ref (match_operand 1 "" "")))]
0ad91047 13601 "TARGET_64BIT"
c859cda6
DJ		 13602 "@
13603 bctr
13604 blr"
266eb58a
DE		 13605 [(set_attr "type" "jmpreg")])
13606
1fd4e8c1
RK		 13607(define_insn "nop"
13608 [(const_int 0)]
13609 ""
ca7f5001 13610 "{cror 0,0,0|nop}")
1fd4e8c1 13611\f
7e69e155 13612;; Define the subtract-one-and-jump insns, starting with the template
c225ba7b
RK		 13613;; so loop.c knows what to generate.
13614
5527bf14
RH		 13615(define_expand "doloop_end"
13616 [(use (match_operand 0 "" "")) ; loop pseudo
13617 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13618 (use (match_operand 2 "" "")) ; max iterations
13619 (use (match_operand 3 "" "")) ; loop level
13620 (use (match_operand 4 "" ""))] ; label
0ad91047
DE		 13621 ""
13622 "
13623{
5527bf14
RH		 13624 /* Only use this on innermost loops. */
13625 if (INTVAL (operands[3]) > 1)
13626 FAIL;
0ad91047 13627 if (TARGET_POWERPC64)
5527bf14
RH		 13628 {
13629 if (GET_MODE (operands[0]) != DImode)
13630 FAIL;
13631 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13632 }
0ad91047 13633 else
5527bf14
RH		 13634 {
13635 if (GET_MODE (operands[0]) != SImode)
13636 FAIL;
13637 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13638 }
0ad91047
DE		 13639 DONE;
13640}")
13641
13642(define_expand "ctrsi"
3cb999d8
DE		 13643 [(parallel [(set (pc)
13644 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13645 (const_int 1))
13646 (label_ref (match_operand 1 "" ""))
13647 (pc)))
b6c9286a
MM		 13648 (set (match_dup 0)
13649 (plus:SI (match_dup 0)
13650 (const_int -1)))
5f81043f
RK		 13651 (clobber (match_scratch:CC 2 ""))
13652 (clobber (match_scratch:SI 3 ""))])]
0ad91047
DE		 13653 "! TARGET_POWERPC64"
13654 "")
13655
13656(define_expand "ctrdi"
3cb999d8
DE		 13657 [(parallel [(set (pc)
13658 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13659 (const_int 1))
13660 (label_ref (match_operand 1 "" ""))
13661 (pc)))
0ad91047
DE		 13662 (set (match_dup 0)
13663 (plus:DI (match_dup 0)
13664 (const_int -1)))
13665 (clobber (match_scratch:CC 2 ""))
61c07d3c 13666 (clobber (match_scratch:DI 3 ""))])]
0ad91047 13667 "TARGET_POWERPC64"
61c07d3c 13668 "")
c225ba7b 13669
1fd4e8c1
RK		 13670;; We need to be able to do this for any operand, including MEM, or we
13671;; will cause reload to blow up since we don't allow output reloads on
7e69e155 13672;; JUMP_INSNs.
0ad91047 13673;; For the length attribute to be calculated correctly, the
5f81043f
RK		 13674;; label MUST be operand 0.
13675
0ad91047 13676(define_insn "*ctrsi_internal1"
1fd4e8c1 13677 [(set (pc)
5f81043f 13678 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
1fd4e8c1 13679 (const_int 1))
a6845123 13680 (label_ref (match_operand 0 "" ""))
1fd4e8c1 13681 (pc)))
5f81043f
RK		 13682 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13683 (plus:SI (match_dup 1)
13684 (const_int -1)))
1fd4e8c1
RK		 13685 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13686 (clobber (match_scratch:SI 4 "=X,X,r"))]
0ad91047 13687 "! TARGET_POWERPC64"
b19003d8
RK		 13688 "*
13689{
af87a13e 13690 if (which_alternative != 0)
b19003d8 13691 return \"#\";
856a6884 13692 else if (get_attr_length (insn) == 4)
a6845123 13693 return \"{bdn|bdnz} %l0\";
b19003d8 13694 else
f607bc57 13695 return \"bdz $+8\;b %l0\";
b19003d8 13696}"
baf97f86 13697 [(set_attr "type" "branch")
914a7297 13698 (set_attr "length" "4,12,16")])
7e69e155 13699
0ad91047 13700(define_insn "*ctrsi_internal2"
5f81043f
RK		 13701 [(set (pc)
13702 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
13703 (const_int 1))
13704 (pc)
13705 (label_ref (match_operand 0 "" ""))))
13706 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13707 (plus:SI (match_dup 1)
13708 (const_int -1)))
13709 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13710 (clobber (match_scratch:SI 4 "=X,X,r"))]
0ad91047
DE		 13711 "! TARGET_POWERPC64"
13712 "*
13713{
13714 if (which_alternative != 0)
13715 return \"#\";
856a6884 13716 else if (get_attr_length (insn) == 4)
0ad91047
DE		 13717 return \"bdz %l0\";
13718 else
f607bc57 13719 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 13720}"
13721 [(set_attr "type" "branch")
914a7297 13722 (set_attr "length" "4,12,16")])
0ad91047
DE		 13723
13724(define_insn "*ctrdi_internal1"
13725 [(set (pc)
61c07d3c 13726 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
0ad91047
DE		 13727 (const_int 1))
13728 (label_ref (match_operand 0 "" ""))
13729 (pc)))
61c07d3c 13730 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
0ad91047
DE		 13731 (plus:DI (match_dup 1)
13732 (const_int -1)))
61c07d3c
DE		 13733 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13734 (clobber (match_scratch:DI 4 "=X,X,r"))]
0ad91047
DE		 13735 "TARGET_POWERPC64"
13736 "*
13737{
13738 if (which_alternative != 0)
13739 return \"#\";
856a6884 13740 else if (get_attr_length (insn) == 4)
0ad91047
DE		 13741 return \"{bdn|bdnz} %l0\";
13742 else
f607bc57 13743 return \"bdz $+8\;b %l0\";
0ad91047
DE		 13744}"
13745 [(set_attr "type" "branch")
914a7297 13746 (set_attr "length" "4,12,16")])
0ad91047
DE		 13747
13748(define_insn "*ctrdi_internal2"
13749 [(set (pc)
61c07d3c 13750 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
0ad91047
DE		 13751 (const_int 1))
13752 (pc)
13753 (label_ref (match_operand 0 "" ""))))
61c07d3c 13754 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
0ad91047
DE		 13755 (plus:DI (match_dup 1)
13756 (const_int -1)))
61c07d3c
DE		 13757 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13758 (clobber (match_scratch:DI 4 "=X,X,r"))]
0ad91047 13759 "TARGET_POWERPC64"
5f81043f
RK		 13760 "*
13761{
13762 if (which_alternative != 0)
13763 return \"#\";
856a6884 13764 else if (get_attr_length (insn) == 4)
5f81043f
RK		 13765 return \"bdz %l0\";
13766 else
f607bc57 13767 return \"{bdn|bdnz} $+8\;b %l0\";
5f81043f
RK		 13768}"
13769 [(set_attr "type" "branch")
914a7297 13770 (set_attr "length" "4,12,16")])
5f81043f 13771
c225ba7b 13772;; Similar, but we can use GE since we have a REG_NONNEG.
0ad91047
DE		 13773
13774(define_insn "*ctrsi_internal3"
1fd4e8c1 13775 [(set (pc)
5f81043f 13776 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
1fd4e8c1 13777 (const_int 0))
a6845123 13778 (label_ref (match_operand 0 "" ""))
1fd4e8c1 13779 (pc)))
5f81043f
RK		 13780 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13781 (plus:SI (match_dup 1)
13782 (const_int -1)))
1fd4e8c1
RK		 13783 (clobber (match_scratch:CC 3 "=X,&x,&X"))
13784 (clobber (match_scratch:SI 4 "=X,X,r"))]
0ad91047 13785 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
b19003d8
RK		 13786 "*
13787{
af87a13e 13788 if (which_alternative != 0)
b19003d8 13789 return \"#\";
856a6884 13790 else if (get_attr_length (insn) == 4)
a6845123 13791 return \"{bdn|bdnz} %l0\";
b19003d8 13792 else
f607bc57 13793 return \"bdz $+8\;b %l0\";
b19003d8 13794}"
baf97f86 13795 [(set_attr "type" "branch")
914a7297 13796 (set_attr "length" "4,12,16")])
7e69e155 13797
0ad91047 13798(define_insn "*ctrsi_internal4"
1fd4e8c1 13799 [(set (pc)
5f81043f
RK		 13800 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
13801 (const_int 0))
13802 (pc)
13803 (label_ref (match_operand 0 "" ""))))
13804 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13805 (plus:SI (match_dup 1)
13806 (const_int -1)))
13807 (clobber (match_scratch:CC 3 "=X,&x,&X"))
13808 (clobber (match_scratch:SI 4 "=X,X,r"))]
0ad91047 13809 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
5f81043f
RK		 13810 "*
13811{
13812 if (which_alternative != 0)
13813 return \"#\";
856a6884 13814 else if (get_attr_length (insn) == 4)
5f81043f
RK		 13815 return \"bdz %l0\";
13816 else
f607bc57 13817 return \"{bdn|bdnz} $+8\;b %l0\";
5f81043f
RK		 13818}"
13819 [(set_attr "type" "branch")
914a7297 13820 (set_attr "length" "4,12,16")])
5f81043f 13821
0ad91047
DE		 13822(define_insn "*ctrdi_internal3"
13823 [(set (pc)
61c07d3c 13824 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
0ad91047
DE		 13825 (const_int 0))
13826 (label_ref (match_operand 0 "" ""))
13827 (pc)))
61c07d3c 13828 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
0ad91047
DE		 13829 (plus:DI (match_dup 1)
13830 (const_int -1)))
61c07d3c
DE		 13831 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13832 (clobber (match_scratch:DI 4 "=X,X,r"))]
0ad91047
DE		 13833 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
13834 "*
13835{
13836 if (which_alternative != 0)
13837 return \"#\";
856a6884 13838 else if (get_attr_length (insn) == 4)
0ad91047
DE		 13839 return \"{bdn|bdnz} %l0\";
13840 else
f607bc57 13841 return \"bdz $+8\;b %l0\";
0ad91047
DE		 13842}"
13843 [(set_attr "type" "branch")
914a7297 13844 (set_attr "length" "4,12,16")])
0ad91047
DE		 13845
13846(define_insn "*ctrdi_internal4"
13847 [(set (pc)
61c07d3c 13848 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
0ad91047
DE		 13849 (const_int 0))
13850 (pc)
13851 (label_ref (match_operand 0 "" ""))))
61c07d3c 13852 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
0ad91047
DE		 13853 (plus:DI (match_dup 1)
13854 (const_int -1)))
61c07d3c
DE		 13855 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13856 (clobber (match_scratch:DI 4 "=X,X,r"))]
0ad91047
DE		 13857 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
13858 "*
13859{
13860 if (which_alternative != 0)
13861 return \"#\";
856a6884 13862 else if (get_attr_length (insn) == 4)
0ad91047
DE		 13863 return \"bdz %l0\";
13864 else
f607bc57 13865 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 13866}"
13867 [(set_attr "type" "branch")
914a7297 13868 (set_attr "length" "4,12,16")])
0ad91047
DE		 13869
13870;; Similar but use EQ
13871
13872(define_insn "*ctrsi_internal5"
5f81043f
RK		 13873 [(set (pc)
13874 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
1fd4e8c1 13875 (const_int 1))
a6845123 13876 (label_ref (match_operand 0 "" ""))
1fd4e8c1 13877 (pc)))
5f81043f
RK		 13878 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13879 (plus:SI (match_dup 1)
13880 (const_int -1)))
1fd4e8c1
RK		 13881 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13882 (clobber (match_scratch:SI 4 "=X,X,r"))]
0ad91047 13883 "! TARGET_POWERPC64"
b19003d8
RK		 13884 "*
13885{
af87a13e 13886 if (which_alternative != 0)
b19003d8 13887 return \"#\";
856a6884 13888 else if (get_attr_length (insn) == 4)
a6845123 13889 return \"bdz %l0\";
b19003d8 13890 else
f607bc57 13891 return \"{bdn|bdnz} $+8\;b %l0\";
b19003d8 13892}"
baf97f86 13893 [(set_attr "type" "branch")
914a7297 13894 (set_attr "length" "4,12,16")])
1fd4e8c1 13895
0ad91047 13896(define_insn "*ctrsi_internal6"
5f81043f
RK		 13897 [(set (pc)
13898 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
13899 (const_int 1))
13900 (pc)
13901 (label_ref (match_operand 0 "" ""))))
13902 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
13903 (plus:SI (match_dup 1)
13904 (const_int -1)))
13905 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13906 (clobber (match_scratch:SI 4 "=X,X,r"))]
0ad91047
DE		 13907 "! TARGET_POWERPC64"
13908 "*
13909{
13910 if (which_alternative != 0)
13911 return \"#\";
856a6884 13912 else if (get_attr_length (insn) == 4)
0ad91047
DE		 13913 return \"{bdn|bdnz} %l0\";
13914 else
f607bc57 13915 return \"bdz $+8\;b %l0\";
0ad91047
DE		 13916}"
13917 [(set_attr "type" "branch")
914a7297 13918 (set_attr "length" "4,12,16")])
0ad91047
DE		 13919
13920(define_insn "*ctrdi_internal5"
13921 [(set (pc)
61c07d3c 13922 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
0ad91047
DE		 13923 (const_int 1))
13924 (label_ref (match_operand 0 "" ""))
13925 (pc)))
61c07d3c 13926 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
0ad91047
DE		 13927 (plus:DI (match_dup 1)
13928 (const_int -1)))
61c07d3c
DE		 13929 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13930 (clobber (match_scratch:DI 4 "=X,X,r"))]
0ad91047
DE		 13931 "TARGET_POWERPC64"
13932 "*
13933{
13934 if (which_alternative != 0)
13935 return \"#\";
856a6884 13936 else if (get_attr_length (insn) == 4)
0ad91047
DE		 13937 return \"bdz %l0\";
13938 else
f607bc57 13939 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 13940}"
13941 [(set_attr "type" "branch")
914a7297 13942 (set_attr "length" "4,12,16")])
0ad91047
DE		 13943
13944(define_insn "*ctrdi_internal6"
13945 [(set (pc)
61c07d3c 13946 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
0ad91047
DE		 13947 (const_int 1))
13948 (pc)
13949 (label_ref (match_operand 0 "" ""))))
61c07d3c 13950 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
0ad91047
DE		 13951 (plus:DI (match_dup 1)
13952 (const_int -1)))
61c07d3c
DE		 13953 (clobber (match_scratch:CC 3 "=X,&x,&x"))
13954 (clobber (match_scratch:DI 4 "=X,X,r"))]
0ad91047 13955 "TARGET_POWERPC64"
5f81043f
RK		 13956 "*
13957{
13958 if (which_alternative != 0)
13959 return \"#\";
856a6884 13960 else if (get_attr_length (insn) == 4)
5f81043f
RK		 13961 return \"{bdn|bdnz} %l0\";
13962 else
f607bc57 13963 return \"bdz $+8\;b %l0\";
5f81043f
RK		 13964}"
13965 [(set_attr "type" "branch")
914a7297 13966 (set_attr "length" "4,12,16")])
5f81043f 13967
0ad91047
DE		 13968;; Now the splitters if we could not allocate the CTR register
13969
1fd4e8c1
RK		 13970(define_split
13971 [(set (pc)
13972 (if_then_else (match_operator 2 "comparison_operator"
cd2b37d9 13973 [(match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 13974 (const_int 1)])
13975 (match_operand 5 "" "")
13976 (match_operand 6 "" "")))
cd2b37d9 13977 (set (match_operand:SI 0 "gpc_reg_operand" "")
5f81043f
RK		 13978 (plus:SI (match_dup 1)
13979 (const_int -1)))
1fd4e8c1
RK		 13980 (clobber (match_scratch:CC 3 ""))
13981 (clobber (match_scratch:SI 4 ""))]
0ad91047 13982 "! TARGET_POWERPC64 && reload_completed"
1fd4e8c1 13983 [(parallel [(set (match_dup 3)
5f81043f
RK		 13984 (compare:CC (plus:SI (match_dup 1)
13985 (const_int -1))
1fd4e8c1 13986 (const_int 0)))
5f81043f
RK		 13987 (set (match_dup 0)
13988 (plus:SI (match_dup 1)
13989 (const_int -1)))])
13990 (set (pc) (if_then_else (match_dup 7)
13991 (match_dup 5)
13992 (match_dup 6)))]
1fd4e8c1
RK		 13993 "
13994{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13995 const0_rtx); }")
13996
13997(define_split
13998 [(set (pc)
13999 (if_then_else (match_operator 2 "comparison_operator"
cd2b37d9 14000 [(match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 14001 (const_int 1)])
14002 (match_operand 5 "" "")
14003 (match_operand 6 "" "")))
9ebbca7d 14004 (set (match_operand:SI 0 "nonimmediate_operand" "")
1fd4e8c1
RK		 14005 (plus:SI (match_dup 1) (const_int -1)))
14006 (clobber (match_scratch:CC 3 ""))
14007 (clobber (match_scratch:SI 4 ""))]
0ad91047
DE		 14008 "! TARGET_POWERPC64 && reload_completed
14009 && ! gpc_reg_operand (operands[0], SImode)"
1fd4e8c1 14010 [(parallel [(set (match_dup 3)
5f81043f
RK		 14011 (compare:CC (plus:SI (match_dup 1)
14012 (const_int -1))
1fd4e8c1 14013 (const_int 0)))
5f81043f
RK		 14014 (set (match_dup 4)
14015 (plus:SI (match_dup 1)
14016 (const_int -1)))])
14017 (set (match_dup 0)
14018 (match_dup 4))
14019 (set (pc) (if_then_else (match_dup 7)
14020 (match_dup 5)
14021 (match_dup 6)))]
1fd4e8c1
RK		 14022 "
14023{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14024 const0_rtx); }")
0ad91047
DE		 14025(define_split
14026 [(set (pc)
14027 (if_then_else (match_operator 2 "comparison_operator"
14028 [(match_operand:DI 1 "gpc_reg_operand" "")
14029 (const_int 1)])
61c07d3c
DE		 14030 (match_operand 5 "" "")
14031 (match_operand 6 "" "")))
0ad91047
DE		 14032 (set (match_operand:DI 0 "gpc_reg_operand" "")
14033 (plus:DI (match_dup 1)
14034 (const_int -1)))
14035 (clobber (match_scratch:CC 3 ""))
61c07d3c
DE		 14036 (clobber (match_scratch:DI 4 ""))]
14037 "TARGET_POWERPC64 && reload_completed"
0ad91047
DE		 14038 [(parallel [(set (match_dup 3)
14039 (compare:CC (plus:DI (match_dup 1)
14040 (const_int -1))
14041 (const_int 0)))
14042 (set (match_dup 0)
14043 (plus:DI (match_dup 1)
14044 (const_int -1)))])
61c07d3c
DE		 14045 (set (pc) (if_then_else (match_dup 7)
14046 (match_dup 5)
14047 (match_dup 6)))]
0ad91047 14048 "
61c07d3c 14049{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
0ad91047
DE		 14050 const0_rtx); }")
14051
14052(define_split
14053 [(set (pc)
14054 (if_then_else (match_operator 2 "comparison_operator"
14055 [(match_operand:DI 1 "gpc_reg_operand" "")
14056 (const_int 1)])
61c07d3c
DE		 14057 (match_operand 5 "" "")
14058 (match_operand 6 "" "")))
9ebbca7d 14059 (set (match_operand:DI 0 "nonimmediate_operand" "")
0ad91047
DE		 14060 (plus:DI (match_dup 1) (const_int -1)))
14061 (clobber (match_scratch:CC 3 ""))
61c07d3c 14062 (clobber (match_scratch:DI 4 ""))]
0ad91047
DE		 14063 "TARGET_POWERPC64 && reload_completed
14064 && ! gpc_reg_operand (operands[0], DImode)"
14065 [(parallel [(set (match_dup 3)
14066 (compare:CC (plus:DI (match_dup 1)
14067 (const_int -1))
14068 (const_int 0)))
14069 (set (match_dup 4)
14070 (plus:DI (match_dup 1)
14071 (const_int -1)))])
14072 (set (match_dup 0)
14073 (match_dup 4))
61c07d3c
DE		 14074 (set (pc) (if_then_else (match_dup 7)
14075 (match_dup 5)
14076 (match_dup 6)))]
0ad91047 14077 "
61c07d3c 14078{ operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
0ad91047 14079 const0_rtx); }")
c94ccb87 14080
e0cd0770
JC		 14081\f
14082(define_insn "trap"
14083 [(trap_if (const_int 1) (const_int 0))]
14084 ""
14085 "{t 31,0,0|trap}")
14086
14087(define_expand "conditional_trap"
14088 [(trap_if (match_operator 0 "trap_comparison_operator"
14089 [(match_dup 2) (match_dup 3)])
14090 (match_operand 1 "const_int_operand" ""))]
14091 ""
14092 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14093 operands[2] = rs6000_compare_op0;
14094 operands[3] = rs6000_compare_op1;")
14095
14096(define_insn ""
14097 [(trap_if (match_operator 0 "trap_comparison_operator"
14098 [(match_operand:SI 1 "register_operand" "r")
14099 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14100 (const_int 0))]
14101 ""
a157febd
GK		 14102 "{t|tw}%V0%I2 %1,%2")
14103
14104(define_insn ""
14105 [(trap_if (match_operator 0 "trap_comparison_operator"
14106 [(match_operand:DI 1 "register_operand" "r")
14107 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14108 (const_int 0))]
14109 "TARGET_POWERPC64"
14110 "td%V0%I2 %1,%2")
9ebbca7d
GK		 14111\f
14112;; Insns related to generating the function prologue and epilogue.
14113
14114(define_expand "prologue"
14115 [(use (const_int 0))]
14116 "TARGET_SCHED_PROLOG"
14117 "
14118{
14119 rs6000_emit_prologue ();
14120 DONE;
14121}")
14122
14123(define_insn "movesi_from_cr"
14124 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14125 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14126 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))]
14127 ""
309323c2 14128 "mfcr %0"
b54cf83a 14129 [(set_attr "type" "mfcr")])
9ebbca7d
GK		 14130
14131(define_insn "*stmw"
14132 [(match_parallel 0 "stmw_operation"
14133 [(set (match_operand:SI 1 "memory_operand" "=m")
14134 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14135 "TARGET_MULTIPLE"
14136 "{stm|stmw} %2,%1")
14137
14138(define_insn "*save_fpregs_si"
14139 [(match_parallel 0 "any_operand"
14140 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14141 (use (match_operand:SI 2 "call_operand" "s"))
14142 (set (match_operand:DF 3 "memory_operand" "=m")
14143 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14144 "TARGET_32BIT"
14145 "bl %z2")
14146
14147(define_insn "*save_fpregs_di"
14148 [(match_parallel 0 "any_operand"
14149 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14150 (use (match_operand:DI 2 "call_operand" "s"))
14151 (set (match_operand:DF 3 "memory_operand" "=m")
14152 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14153 "TARGET_64BIT"
14154 "bl %z2")
14155
14156; These are to explain that changes to the stack pointer should
14157; not be moved over stores to stack memory.
14158(define_insn "stack_tie"
14159 [(set (match_operand:BLK 0 "memory_operand" "+m")
14160 (unspec:BLK [(match_dup 0)] 5))]
14161 ""
14162 ""
14163 [(set_attr "length" "0")])
14164
14165
14166(define_expand "epilogue"
14167 [(use (const_int 0))]
14168 "TARGET_SCHED_PROLOG"
14169 "
14170{
14171 rs6000_emit_epilogue (FALSE);
14172 DONE;
14173}")
14174
14175; On some processors, doing the mtcrf one CC register at a time is
14176; faster (like on the 604e). On others, doing them all at once is
14177; faster; for instance, on the 601 and 750.
14178
14179(define_expand "movsi_to_cr_one"
35aba846
DE		 14180 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14181 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14182 (match_dup 2)] 20))]
14183 ""
14184 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
9ebbca7d
GK		 14185
14186(define_insn "*movsi_to_cr"
35aba846
DE		 14187 [(match_parallel 0 "mtcrf_operation"
14188 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14189 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14190 (match_operand 3 "immediate_operand" "n")]
9ebbca7d
GK		 14191 20))])]
14192 ""
e35b9579
GK		 14193 "*
14194{
14195 int mask = 0;
14196 int i;
14197 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14198 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14199 operands[4] = GEN_INT (mask);
14200 return \"mtcrf %4,%2\";
309323c2 14201}"
b54cf83a 14202 [(set_attr "type" "mtcr")])
9ebbca7d 14203
b54cf83a 14204(define_insn "*mtcrfsi"
309323c2
DE		 14205 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14206 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14207 (match_operand 2 "immediate_operand" "n")] 20))]
14208 "GET_CODE (operands[0]) == REG
14209 && CR_REGNO_P (REGNO (operands[0]))
14210 && GET_CODE (operands[2]) == CONST_INT
14211 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14212 "mtcrf %R0,%1"
b54cf83a 14213 [(set_attr "type" "mtcr")])
9ebbca7d
GK		 14214
14215; The load-multiple instructions have similar properties.
14216; Note that "load_multiple" is a name known to the machine-independent
14217; code that actually corresponds to the powerpc load-string.
14218
14219(define_insn "*lmw"
35aba846
DE		 14220 [(match_parallel 0 "lmw_operation"
14221 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14222 (match_operand:SI 2 "memory_operand" "m"))])]
14223 "TARGET_MULTIPLE"
14224 "{lm|lmw} %1,%2")
9ebbca7d
GK		 14225
14226(define_insn "*return_internal_si"
e35b9579
GK		 14227 [(return)
14228 (use (match_operand:SI 0 "register_operand" "lc"))]
9ebbca7d 14229 "TARGET_32BIT"
cccf3bdc 14230 "b%T0"
9ebbca7d
GK		 14231 [(set_attr "type" "jmpreg")])
14232
14233(define_insn "*return_internal_di"
e35b9579
GK		 14234 [(return)
14235 (use (match_operand:DI 0 "register_operand" "lc"))]
9ebbca7d 14236 "TARGET_64BIT"
cccf3bdc 14237 "b%T0"
9ebbca7d
GK		 14238 [(set_attr "type" "jmpreg")])
14239
14240; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14241; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
14242
14243(define_insn "*return_and_restore_fpregs_si"
14244 [(match_parallel 0 "any_operand"
e35b9579
GK		 14245 [(return)
14246 (use (match_operand:SI 1 "register_operand" "l"))
9ebbca7d
GK		 14247 (use (match_operand:SI 2 "call_operand" "s"))
14248 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14249 (match_operand:DF 4 "memory_operand" "m"))])]
14250 "TARGET_32BIT"
14251 "b %z2")
14252
14253(define_insn "*return_and_restore_fpregs_di"
14254 [(match_parallel 0 "any_operand"
e35b9579
GK		 14255 [(return)
14256 (use (match_operand:DI 1 "register_operand" "l"))
9ebbca7d
GK		 14257 (use (match_operand:DI 2 "call_operand" "s"))
14258 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14259 (match_operand:DF 4 "memory_operand" "m"))])]
14260 "TARGET_64BIT"
14261 "b %z2")
14262
83720594
RH		 14263; This is used in compiling the unwind routines.
14264(define_expand "eh_return"
14265 [(use (match_operand 0 "general_operand" ""))
14266 (use (match_operand 1 "general_operand" ""))]
9ebbca7d
GK		 14267 ""
14268 "
14269{
3553b09d 14270#if TARGET_AIX
83720594 14271 rs6000_emit_eh_toc_restore (operands[0]);
3553b09d 14272#endif
83720594
RH		 14273 if (TARGET_32BIT)
14274 emit_insn (gen_eh_set_lr_si (operands[1]));
9ebbca7d 14275 else
83720594
RH		 14276 emit_insn (gen_eh_set_lr_di (operands[1]));
14277 emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]);
9ebbca7d
GK		 14278 DONE;
14279}")
14280
83720594
RH		 14281; We can't expand this before we know where the link register is stored.
14282(define_insn "eh_set_lr_si"
14283 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9)
466eb3e0 14284 (clobber (match_scratch:SI 1 "=&b"))]
83720594
RH		 14285 "TARGET_32BIT"
14286 "#")
14287
14288(define_insn "eh_set_lr_di"
14289 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9)
466eb3e0 14290 (clobber (match_scratch:DI 1 "=&b"))]
83720594
RH		 14291 "TARGET_64BIT"
14292 "#")
9ebbca7d
GK		 14293
14294(define_split
83720594
RH		 14295 [(unspec_volatile [(match_operand 0 "register_operand" "")] 9)
14296 (clobber (match_scratch 1 ""))]
14297 "reload_completed"
14298 [(const_int 0)]
9ebbca7d
GK		 14299 "
14300{
83720594 14301 rs6000_stack_t *info = rs6000_stack_info ();
9ebbca7d 14302
83720594
RH		 14303 if (info->lr_save_p)
14304 {
14305 rtx frame_rtx = stack_pointer_rtx;
14306 int sp_offset = 0;
14307 rtx tmp;
9ebbca7d 14308
83720594
RH		 14309 if (frame_pointer_needed
14310 || current_function_calls_alloca
14311 || info->total_size > 32767)
14312 {
14313 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
14314 frame_rtx = operands[1];
14315 }
14316 else if (info->push_p)
14317 sp_offset = info->total_size;
9ebbca7d 14318
83720594
RH		 14319 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
14320 tmp = gen_rtx_MEM (Pmode, tmp);
14321 emit_move_insn (tmp, operands[0]);
14322 }
14323 else
14324 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
14325 DONE;
14326}")
0ac081f6 14327
01a2ccd0
DE		 14328(define_insn "prefetch"
14329 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
6041bf2f
DE		 14330 (match_operand:SI 1 "const_int_operand" "n")
14331 (match_operand:SI 2 "const_int_operand" "n"))]
01a2ccd0 14332 "TARGET_POWERPC"
6041bf2f
DE		 14333 "*
14334{
01a2ccd0
DE		 14335 if (GET_CODE (operands[0]) == REG)
14336 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14337 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
6041bf2f
DE		 14338}"
14339 [(set_attr "type" "load")])
a3170dc6 14340
10ed84db 14341(include "altivec.md")
a3170dc6 14342(include "spe.md")
Mirror of https://gcc.gnu.org/git/gcc.git