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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
9ebbca7d | 2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
792760b9 | 3 | ;; 1999, 2000, 2001 Free Software Foundation, Inc. |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 RK |
5 | |
6 | ;; This file is part of GNU CC. | |
7 | ||
8 | ;; GNU CC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 2, or (at your option) | |
11 | ;; any later version. | |
12 | ||
13 | ;; GNU CC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GNU CC; see the file COPYING. If not, write to | |
3f63df56 RK |
20 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | ;; Boston, MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d GK |
24 | |
25 | ;; `unspec' values used in rs6000.md: | |
26 | ;; Number Use | |
27 | ;; 0 frsp for POWER machines | |
28 | ;; 0/v blockage | |
29 | ;; 5 used to tie the stack contents and the stack pointer | |
30 | ;; 6 address of a word pointing to the TOC | |
31 | ;; 7 address of the TOC (more-or-less) | |
32 | ;; 8 movsi_got | |
33 | ;; 9/v eh_reg_restore | |
34 | ;; 10 fctiwz | |
35 | ;; 19 movesi_from_cr | |
36 | ;; 20 movesi_to_cr | |
1fd4e8c1 RK |
37 | \f |
38 | ;; Define an insn type attribute. This is used in function unit delay | |
39 | ;; computations. | |
c859cda6 | 40 | (define_attr "type" "integer,load,store,fpload,fpstore,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat,altivec" |
1fd4e8c1 RK |
41 | (const_string "integer")) |
42 | ||
b19003d8 | 43 | ;; Length (in bytes). |
6cbadf36 GK |
44 | ; '(pc)' in the following doesn't include the instruction itself; it is |
45 | ; calculated as if the instruction had zero size. | |
b19003d8 RK |
46 | (define_attr "length" "" |
47 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 48 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 49 | (const_int -32768)) |
6cbadf36 GK |
50 | (lt (minus (match_dup 0) (pc)) |
51 | (const_int 32764))) | |
39a10a29 GK |
52 | (const_int 4) |
53 | (const_int 8)) | |
b19003d8 RK |
54 | (const_int 4))) |
55 | ||
cfb557c4 RK |
56 | ;; Processor type -- this attribute must exactly match the processor_type |
57 | ;; enumeration in rs6000.h. | |
58 | ||
309323c2 | 59 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,power4" |
cfb557c4 RK |
60 | (const (symbol_ref "rs6000_cpu_attr"))) |
61 | ||
62 | ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY | |
63 | ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) | |
64 | ||
b7ff3d82 | 65 | ; Load/Store Unit -- pure PowerPC only |
51b8fc2c | 66 | ; (POWER and 601 use Integer Unit) |
cfb557c4 RK |
67 | (define_function_unit "lsu" 1 0 |
68 | (and (eq_attr "type" "load") | |
ed947a96 | 69 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400")) |
b6c9286a | 70 | 2 1) |
cfb557c4 | 71 | |
ed947a96 | 72 | (define_function_unit "lsu" 1 0 |
f18c054f | 73 | (and (eq_attr "type" "load,vecload") |
ed947a96 DJ |
74 | (eq_attr "cpu" "ppc7450")) |
75 | 3 1) | |
76 | ||
cfb557c4 | 77 | (define_function_unit "lsu" 1 0 |
b7ff3d82 | 78 | (and (eq_attr "type" "store,fpstore") |
ed947a96 | 79 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 80 | 1 1) |
b6c9286a | 81 | |
ed947a96 DJ |
82 | (define_function_unit "lsu" 1 0 |
83 | (and (eq_attr "type" "store,fpstore") | |
84 | (eq_attr "cpu" "ppc750,ppc7400")) | |
85 | 2 1) | |
86 | ||
87 | (define_function_unit "lsu" 1 0 | |
f18c054f | 88 | (and (eq_attr "type" "store,vecstore") |
ed947a96 DJ |
89 | (eq_attr "cpu" "ppc7450")) |
90 | 3 1) | |
91 | ||
92 | (define_function_unit "lsu" 1 0 | |
93 | (and (eq_attr "type" "fpstore") | |
94 | (eq_attr "cpu" "ppc7450")) | |
95 | 3 3) | |
96 | ||
b6c9286a MM |
97 | (define_function_unit "lsu" 1 0 |
98 | (and (eq_attr "type" "fpload") | |
ed947a96 | 99 | (eq_attr "cpu" "mpccore,ppc603,ppc750,ppc7400")) |
b6c9286a | 100 | 2 1) |
cfb557c4 | 101 | |
ed947a96 DJ |
102 | (define_function_unit "lsu" 1 0 |
103 | (and (eq_attr "type" "fpload") | |
104 | (eq_attr "cpu" "ppc7450")) | |
105 | 4 1) | |
106 | ||
b7ff3d82 DE |
107 | (define_function_unit "lsu" 1 0 |
108 | (and (eq_attr "type" "fpload") | |
3cb999d8 | 109 | (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 DE |
110 | 3 1) |
111 | ||
cfb557c4 RK |
112 | (define_function_unit "iu" 1 0 |
113 | (and (eq_attr "type" "load") | |
fe7f5677 | 114 | (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601")) |
b6c9286a | 115 | 2 1) |
cfb557c4 RK |
116 | |
117 | (define_function_unit "iu" 1 0 | |
b7ff3d82 | 118 | (and (eq_attr "type" "store,fpstore") |
fe7f5677 | 119 | (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601")) |
b7ff3d82 DE |
120 | 1 1) |
121 | ||
122 | (define_function_unit "fpu" 1 0 | |
123 | (and (eq_attr "type" "fpstore") | |
3624a679 | 124 | (eq_attr "cpu" "rios1,ppc601")) |
b7ff3d82 | 125 | 0 1) |
cfb557c4 | 126 | |
49a0b204 | 127 | (define_function_unit "iu" 1 0 |
b7ff3d82 | 128 | (and (eq_attr "type" "fpload") |
b6c9286a | 129 | (eq_attr "cpu" "rios1")) |
b7ff3d82 DE |
130 | 2 1) |
131 | ||
132 | (define_function_unit "iu" 1 0 | |
133 | (and (eq_attr "type" "fpload") | |
134 | (eq_attr "cpu" "ppc601")) | |
135 | 3 1) | |
136 | ||
137 | (define_function_unit "iu2" 2 0 | |
138 | (and (eq_attr "type" "load,fpload") | |
139 | (eq_attr "cpu" "rios2")) | |
140 | 2 1) | |
141 | ||
142 | (define_function_unit "iu2" 2 0 | |
143 | (and (eq_attr "type" "store,fpstore") | |
144 | (eq_attr "cpu" "rios2")) | |
145 | 1 1) | |
146 | ||
3cb999d8 | 147 | ; Integer Unit (RIOS1, PPC601, PPC603, RS64a) |
b7ff3d82 DE |
148 | (define_function_unit "iu" 1 0 |
149 | (and (eq_attr "type" "integer") | |
fe7f5677 | 150 | (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603")) |
b7ff3d82 | 151 | 1 1) |
49a0b204 | 152 | |
39a10a29 GK |
153 | (define_function_unit "iu" 1 0 |
154 | (and (eq_attr "type" "cr_logical") | |
fe7f5677 | 155 | (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601")) |
39a10a29 GK |
156 | 1 1) |
157 | ||
da0ae67f | 158 | (define_function_unit "iu" 1 0 |
c859cda6 | 159 | (and (eq_attr "type" "imul,imul2,imul3") |
da0ae67f MM |
160 | (eq_attr "cpu" "ppc403")) |
161 | 4 4) | |
162 | ||
cfb557c4 | 163 | (define_function_unit "iu" 1 0 |
fe7f5677 DE |
164 | (and (eq_attr "type" "imul") |
165 | (eq_attr "cpu" "ppc405")) | |
166 | 4 3) | |
167 | ||
168 | (define_function_unit "iu" 1 0 | |
169 | (and (eq_attr "type" "imul2,imul3") | |
170 | (eq_attr "cpu" "ppc405")) | |
171 | 3 2) | |
172 | ||
173 | (define_function_unit "iu" 1 0 | |
174 | (and (eq_attr "type" "imul") | |
175 | (eq_attr "cpu" "rios1")) | |
51b8fc2c | 176 | 5 5) |
cfb557c4 | 177 | |
fe7f5677 DE |
178 | (define_function_unit "iu" 1 0 |
179 | (and (eq_attr "type" "imul2") | |
180 | (eq_attr "cpu" "rios1")) | |
181 | 4 4) | |
182 | ||
183 | (define_function_unit "iu" 1 0 | |
184 | (and (eq_attr "type" "imul3") | |
185 | (eq_attr "cpu" "rios1")) | |
186 | 3 3) | |
187 | ||
3cb999d8 | 188 | (define_function_unit "iu" 1 0 |
c859cda6 | 189 | (and (eq_attr "type" "imul,imul2,imul3") |
fe7f5677 DE |
190 | (eq_attr "cpu" "ppc601,ppc603")) |
191 | 5 5) | |
192 | ||
193 | (define_function_unit "iu" 1 0 | |
194 | (and (eq_attr "type" "imul") | |
195 | (eq_attr "cpu" "rs64a")) | |
196 | 20 20) | |
197 | ||
198 | (define_function_unit "iu" 1 0 | |
199 | (and (eq_attr "type" "imul2") | |
3cb999d8 | 200 | (eq_attr "cpu" "rs64a")) |
fe7f5677 DE |
201 | 12 12) |
202 | ||
203 | (define_function_unit "iu" 1 0 | |
204 | (and (eq_attr "type" "imul3") | |
205 | (eq_attr "cpu" "rs64a")) | |
206 | 8 8) | |
3cb999d8 DE |
207 | |
208 | (define_function_unit "iu" 1 0 | |
209 | (and (eq_attr "type" "lmul") | |
210 | (eq_attr "cpu" "rs64a")) | |
211 | 34 34) | |
212 | ||
cfb557c4 RK |
213 | (define_function_unit "iu" 1 0 |
214 | (and (eq_attr "type" "idiv") | |
ca7f5001 | 215 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 216 | 19 19) |
cfb557c4 | 217 | |
3cb999d8 DE |
218 | (define_function_unit "iu" 1 0 |
219 | (and (eq_attr "type" "idiv") | |
220 | (eq_attr "cpu" "rs64a")) | |
221 | 66 66) | |
222 | ||
223 | (define_function_unit "iu" 1 0 | |
224 | (and (eq_attr "type" "ldiv") | |
225 | (eq_attr "cpu" "rs64a")) | |
226 | 66 66) | |
227 | ||
cfb557c4 RK |
228 | (define_function_unit "iu" 1 0 |
229 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
230 | (eq_attr "cpu" "ppc403")) |
231 | 33 33) | |
51b8fc2c | 232 | |
fe7f5677 DE |
233 | (define_function_unit "iu" 1 0 |
234 | (and (eq_attr "type" "idiv") | |
235 | (eq_attr "cpu" "ppc405")) | |
236 | 35 35) | |
237 | ||
da0ae67f MM |
238 | (define_function_unit "iu" 1 0 |
239 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
240 | (eq_attr "cpu" "ppc601")) |
241 | 36 36) | |
da0ae67f | 242 | |
51b8fc2c RK |
243 | (define_function_unit "iu" 1 0 |
244 | (and (eq_attr "type" "idiv") | |
b7ff3d82 | 245 | (eq_attr "cpu" "ppc603")) |
51b8fc2c RK |
246 | 37 36) |
247 | ||
248 | ; RIOS2 has two integer units: a primary one which can perform all | |
249 | ; operations and a secondary one which is fed in lock step with the first | |
b6c9286a MM |
250 | ; and can perform "simple" integer operations. |
251 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
252 | ; for the complex insns. | |
51b8fc2c RK |
253 | (define_function_unit "iu2" 2 0 |
254 | (and (eq_attr "type" "integer") | |
255 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 256 | 1 1) |
b6c9286a MM |
257 | |
258 | (define_function_unit "iu2" 2 0 | |
c859cda6 | 259 | (and (eq_attr "type" "imul,imul2,imul3") |
b6c9286a MM |
260 | (eq_attr "cpu" "rios2")) |
261 | 2 2) | |
262 | ||
263 | (define_function_unit "iu2" 2 0 | |
264 | (and (eq_attr "type" "idiv") | |
265 | (eq_attr "cpu" "rios2")) | |
266 | 13 13) | |
51b8fc2c RK |
267 | |
268 | (define_function_unit "imuldiv" 1 0 | |
c859cda6 | 269 | (and (eq_attr "type" "imul,imul2,imul3") |
51b8fc2c | 270 | (eq_attr "cpu" "rios2")) |
b6c9286a MM |
271 | 2 2) |
272 | ||
51b8fc2c RK |
273 | (define_function_unit "imuldiv" 1 0 |
274 | (and (eq_attr "type" "idiv") | |
275 | (eq_attr "cpu" "rios2")) | |
b6c9286a | 276 | 13 13) |
51b8fc2c | 277 | |
cf27b467 MM |
278 | ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions |
279 | ; Divide latency varies greatly from 2-11, use 6 as average | |
280 | (define_function_unit "imuldiv" 1 0 | |
c859cda6 | 281 | (and (eq_attr "type" "imul,imul2,imul3") |
cf27b467 MM |
282 | (eq_attr "cpu" "mpccore")) |
283 | 2 1) | |
284 | ||
285 | (define_function_unit "imuldiv" 1 0 | |
286 | (and (eq_attr "type" "idiv") | |
287 | (eq_attr "cpu" "mpccore")) | |
288 | 6 6) | |
289 | ||
cac8ce95 | 290 | ; PPC604{,e} has two units that perform integer operations |
b6c9286a MM |
291 | ; and one unit for divide/multiply operations (and move |
292 | ; from/to spr). | |
293 | (define_function_unit "iu2" 2 0 | |
51b8fc2c | 294 | (and (eq_attr "type" "integer") |
3cb999d8 | 295 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 296 | 1 1) |
51b8fc2c RK |
297 | |
298 | (define_function_unit "imuldiv" 1 0 | |
c859cda6 | 299 | (and (eq_attr "type" "imul,imul2,imul3") |
3cb999d8 | 300 | (eq_attr "cpu" "ppc604")) |
b7ff3d82 | 301 | 4 2) |
51b8fc2c | 302 | |
3cb999d8 | 303 | (define_function_unit "imuldiv" 1 0 |
c859cda6 | 304 | (and (eq_attr "type" "imul,imul2,imul3") |
fe7f5677 DE |
305 | (eq_attr "cpu" "ppc604e")) |
306 | 2 1) | |
307 | ||
308 | (define_function_unit "imuldiv" 1 0 | |
309 | (and (eq_attr "type" "imul") | |
3cb999d8 DE |
310 | (eq_attr "cpu" "ppc620,ppc630")) |
311 | 5 3) | |
312 | ||
313 | (define_function_unit "imuldiv" 1 0 | |
fe7f5677 | 314 | (and (eq_attr "type" "imul2") |
3cb999d8 | 315 | (eq_attr "cpu" "ppc620,ppc630")) |
fe7f5677 | 316 | 4 3) |
3cb999d8 | 317 | |
cac8ce95 | 318 | (define_function_unit "imuldiv" 1 0 |
fe7f5677 DE |
319 | (and (eq_attr "type" "imul3") |
320 | (eq_attr "cpu" "ppc620,ppc630")) | |
321 | 3 3) | |
322 | ||
323 | (define_function_unit "imuldiv" 1 0 | |
324 | (and (eq_attr "type" "lmul") | |
325 | (eq_attr "cpu" "ppc620,ppc630")) | |
326 | 7 5) | |
cac8ce95 | 327 | |
51b8fc2c RK |
328 | (define_function_unit "imuldiv" 1 0 |
329 | (and (eq_attr "type" "idiv") | |
3cb999d8 | 330 | (eq_attr "cpu" "ppc604,ppc604e")) |
b7ff3d82 | 331 | 20 19) |
cfb557c4 | 332 | |
3cb999d8 DE |
333 | (define_function_unit "imuldiv" 1 0 |
334 | (and (eq_attr "type" "idiv") | |
335 | (eq_attr "cpu" "ppc620")) | |
336 | 37 36) | |
337 | ||
338 | (define_function_unit "imuldiv" 1 0 | |
339 | (and (eq_attr "type" "idiv") | |
340 | (eq_attr "cpu" "ppc630")) | |
341 | 21 20) | |
342 | ||
343 | (define_function_unit "imuldiv" 1 0 | |
344 | (and (eq_attr "type" "ldiv") | |
345 | (eq_attr "cpu" "ppc620,ppc630")) | |
346 | 37 36) | |
347 | ||
ed947a96 DJ |
348 | ; PPC7450 has 3 integer units (for most integer insns) and one mul/div |
349 | ; unit, which also does CR-logical insns and move to/from SPR. | |
2212663f DB |
350 | ; It also has 4 vector units, one for each type of vector instruction. |
351 | ; However, we can only dispatch 2 instructions per cycle. | |
352 | ; We model this as saying that dispatching two of the same type of instruction | |
353 | ; in a row incurs a single cycle delay. | |
ed947a96 DJ |
354 | (define_function_unit "iu3" 3 0 |
355 | (and (eq_attr "type" "integer") | |
356 | (eq_attr "cpu" "ppc7450")) | |
357 | 1 1) | |
358 | ||
359 | (define_function_unit "imuldiv" 1 0 | |
360 | (and (eq_attr "type" "imul") | |
361 | (eq_attr "cpu" "ppc7450")) | |
fd3b43f2 | 362 | 4 2) |
ed947a96 | 363 | |
c859cda6 DJ |
364 | (define_function_unit "imuldiv" 1 0 |
365 | (and (eq_attr "type" "imul2,imul3") | |
366 | (eq_attr "cpu" "ppc7450")) | |
367 | 3 1) | |
368 | ||
ed947a96 DJ |
369 | (define_function_unit "imuldiv" 1 0 |
370 | (and (eq_attr "type" "idiv") | |
371 | (eq_attr "cpu" "ppc7450")) | |
372 | 23 23) | |
373 | ||
374 | (define_function_unit "imuldiv" 1 0 | |
375 | (and (eq_attr "type" "cr_logical") | |
376 | (eq_attr "cpu" "ppc7450")) | |
377 | 1 1) | |
309323c2 | 378 | |
2212663f | 379 | (define_function_unit "vec_alu2" 2 0 |
f18c054f DB |
380 | (and (eq_attr "type" "vecsimple") |
381 | (eq_attr "cpu" "ppc7450")) | |
2212663f | 382 | 1 2 [(eq_attr "type" "vecsimple")]) |
309323c2 | 383 | |
2212663f DB |
384 | (define_function_unit "vec_alu2" 2 0 |
385 | (and (eq_attr "type" "vecsimple") | |
386 | (eq_attr "cpu" "ppc7450")) | |
387 | 1 1 [(eq_attr "type" "!vecsimple")]) | |
309323c2 | 388 | |
2212663f | 389 | (define_function_unit "vec_alu2" 2 0 |
f18c054f DB |
390 | (and (eq_attr "type" "veccomplex") |
391 | (eq_attr "cpu" "ppc7450")) | |
2212663f | 392 | 4 2 [(eq_attr "type" "veccomplex")]) |
309323c2 | 393 | |
2212663f DB |
394 | (define_function_unit "vec_alu2" 2 0 |
395 | (and (eq_attr "type" "veccomplex") | |
396 | (eq_attr "cpu" "ppc7450")) | |
397 | 4 1 [(eq_attr "type" "!veccomplex")]) | |
309323c2 | 398 | |
2212663f | 399 | (define_function_unit "vec_alu2" 2 0 |
f18c054f DB |
400 | (and (eq_attr "type" "veccmp") |
401 | (eq_attr "cpu" "ppc7450")) | |
2212663f | 402 | 2 2 [(eq_attr "type" "veccmp")]) |
309323c2 | 403 | |
2212663f DB |
404 | (define_function_unit "vec_alu2" 2 0 |
405 | (and (eq_attr "type" "veccmp") | |
406 | (eq_attr "cpu" "ppc7450")) | |
407 | 2 1 [(eq_attr "type" "!veccmp")]) | |
309323c2 | 408 | |
2212663f | 409 | (define_function_unit "vec_alu2" 2 0 |
f18c054f DB |
410 | (and (eq_attr "type" "vecfloat") |
411 | (eq_attr "cpu" "ppc7450")) | |
2212663f | 412 | 4 2 [(eq_attr "type" "vecfloat")]) |
309323c2 | 413 | |
2212663f DB |
414 | (define_function_unit "vec_alu2" 2 0 |
415 | (and (eq_attr "type" "vecfloat") | |
416 | (eq_attr "cpu" "ppc7450")) | |
417 | 4 1 [(eq_attr "type" "!vecfloat")]) | |
309323c2 | 418 | |
2212663f | 419 | (define_function_unit "vec_alu2" 2 0 |
f18c054f DB |
420 | (and (eq_attr "type" "vecperm") |
421 | (eq_attr "cpu" "ppc7450")) | |
2212663f | 422 | 2 2 [(eq_attr "type" "vecperm")]) |
309323c2 | 423 | |
2212663f DB |
424 | (define_function_unit "vec_alu2" 2 0 |
425 | (and (eq_attr "type" "vecperm") | |
426 | (eq_attr "cpu" "ppc7450")) | |
427 | 2 1 [(eq_attr "type" "!vecperm")]) | |
ed947a96 | 428 | |
bef84347 VM |
429 | ; PPC750 has two integer units: a primary one which can perform all |
430 | ; operations and a secondary one which is fed in lock step with the first | |
431 | ; and can perform "simple" integer operations. | |
432 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
433 | ; for the complex insns. | |
434 | (define_function_unit "iu2" 2 0 | |
435 | (and (eq_attr "type" "integer") | |
ed947a96 | 436 | (eq_attr "cpu" "ppc750,ppc7400")) |
bef84347 VM |
437 | 1 1) |
438 | ||
439 | (define_function_unit "iu2" 2 0 | |
440 | (and (eq_attr "type" "imul") | |
ed947a96 DJ |
441 | (eq_attr "cpu" "ppc750,ppc7400")) |
442 | 4 4) | |
443 | ||
c859cda6 DJ |
444 | (define_function_unit "iu2" 2 0 |
445 | (and (eq_attr "type" "imul2") | |
446 | (eq_attr "cpu" "ppc750,ppc7400")) | |
447 | 3 2) | |
448 | ||
449 | (define_function_unit "iu2" 2 0 | |
450 | (and (eq_attr "type" "imul3") | |
451 | (eq_attr "cpu" "ppc750,ppc7400")) | |
452 | 2 1) | |
453 | ||
ed947a96 DJ |
454 | (define_function_unit "iu2" 2 0 |
455 | (and (eq_attr "type" "idiv") | |
456 | (eq_attr "cpu" "ppc750,ppc7400")) | |
457 | 19 19) | |
bef84347 VM |
458 | |
459 | (define_function_unit "imuldiv" 1 0 | |
460 | (and (eq_attr "type" "imul") | |
ed947a96 DJ |
461 | (eq_attr "cpu" "ppc750,ppc7400")) |
462 | 4 4) | |
bef84347 | 463 | |
c859cda6 DJ |
464 | (define_function_unit "imuldiv" 1 0 |
465 | (and (eq_attr "type" "imul2") | |
466 | (eq_attr "cpu" "ppc750,ppc7400")) | |
467 | 3 2) | |
468 | ||
469 | (define_function_unit "imuldiv" 1 0 | |
470 | (and (eq_attr "type" "imul3") | |
471 | (eq_attr "cpu" "ppc750,ppc7400")) | |
472 | 2 1) | |
473 | ||
bef84347 VM |
474 | (define_function_unit "imuldiv" 1 0 |
475 | (and (eq_attr "type" "idiv") | |
ed947a96 | 476 | (eq_attr "cpu" "ppc750,ppc7400")) |
bef84347 VM |
477 | 19 19) |
478 | ||
39a10a29 GK |
479 | ; CR-logical operations are execute-serialized, that is they don't |
480 | ; start (and block the function unit) until all preceding operations | |
481 | ; have finished. They don't block dispatch of other insns, though. | |
482 | ; I've imitated this by giving them longer latency. | |
483 | (define_function_unit "sru" 1 0 | |
484 | (and (eq_attr "type" "cr_logical") | |
ed947a96 | 485 | (eq_attr "cpu" "ppc603,ppc750,ppc7400")) |
39a10a29 GK |
486 | 3 2) |
487 | ||
b6c9286a | 488 | ; compare is done on integer unit, but feeds insns which |
acc5239d | 489 | ; execute on the branch unit. |
b6c9286a MM |
490 | (define_function_unit "iu" 1 0 |
491 | (and (eq_attr "type" "compare") | |
b7ff3d82 DE |
492 | (eq_attr "cpu" "rios1")) |
493 | 4 1) | |
494 | ||
495 | (define_function_unit "iu" 1 0 | |
496 | (and (eq_attr "type" "delayed_compare") | |
497 | (eq_attr "cpu" "rios1")) | |
498 | 5 1) | |
499 | ||
500 | (define_function_unit "iu" 1 0 | |
501 | (and (eq_attr "type" "compare,delayed_compare") | |
309323c2 | 502 | (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc601,ppc603")) |
b7ff3d82 | 503 | 3 1) |
b6c9286a | 504 | |
ed947a96 DJ |
505 | ; some extra cycles added by TARGET_SCHED_ADJUST_COST between compare |
506 | ; and a following branch, to reduce mispredicts | |
ed947a96 DJ |
507 | (define_function_unit "iu3" 3 0 |
508 | (and (eq_attr "type" "compare,delayed_compare") | |
509 | (eq_attr "cpu" "ppc7450")) | |
510 | 1 1) | |
511 | ||
b6c9286a | 512 | (define_function_unit "iu2" 2 0 |
b7ff3d82 | 513 | (and (eq_attr "type" "compare,delayed_compare") |
b6c9286a | 514 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 515 | 3 1) |
b6c9286a | 516 | |
b6c9286a | 517 | (define_function_unit "iu2" 2 0 |
b7ff3d82 | 518 | (and (eq_attr "type" "compare,delayed_compare") |
ed947a96 | 519 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400")) |
b6c9286a | 520 | 1 1) |
cfb557c4 | 521 | |
b6c9286a MM |
522 | ; fp compare uses fp unit |
523 | (define_function_unit "fpu" 1 0 | |
cfb557c4 | 524 | (and (eq_attr "type" "fpcompare") |
b6c9286a | 525 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 526 | 9 1) |
cfb557c4 | 527 | |
b6c9286a MM |
528 | ; rios1 and rios2 have different fpcompare delays |
529 | (define_function_unit "fpu2" 2 0 | |
cfb557c4 | 530 | (and (eq_attr "type" "fpcompare") |
3cb999d8 | 531 | (eq_attr "cpu" "rios2,ppc630")) |
b6c9286a MM |
532 | 5 1) |
533 | ||
534 | ; on ppc601 and ppc603, fpcompare takes also 2 cycles from | |
535 | ; the integer unit | |
536 | ; here we do not define delays, just occupy the unit. The dependencies | |
b7ff3d82 | 537 | ; will be assigned by the fpcompare definition in the fpu. |
b6c9286a MM |
538 | (define_function_unit "iu" 1 0 |
539 | (and (eq_attr "type" "fpcompare") | |
b7ff3d82 | 540 | (eq_attr "cpu" "ppc601,ppc603")) |
b6c9286a MM |
541 | 0 2) |
542 | ||
543 | ; fp compare uses fp unit | |
544 | (define_function_unit "fpu" 1 0 | |
545 | (and (eq_attr "type" "fpcompare") | |
e3485bbc | 546 | (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620")) |
b6c9286a | 547 | 5 1) |
cfb557c4 | 548 | |
ed947a96 DJ |
549 | (define_function_unit "fpu" 1 0 |
550 | (and (eq_attr "type" "fpcompare") | |
551 | (eq_attr "cpu" "ppc750,ppc7400,ppc7450")) | |
552 | 3 1) | |
553 | ||
cf27b467 MM |
554 | (define_function_unit "fpu" 1 0 |
555 | (and (eq_attr "type" "fpcompare") | |
556 | (eq_attr "cpu" "mpccore")) | |
557 | 1 1) | |
558 | ||
cfb557c4 | 559 | (define_function_unit "bpu" 1 0 |
324e52cc | 560 | (and (eq_attr "type" "mtjmpr") |
3cb999d8 | 561 | (eq_attr "cpu" "rios1,rios2,rs64a")) |
b7ff3d82 | 562 | 5 1) |
cfb557c4 RK |
563 | |
564 | (define_function_unit "bpu" 1 0 | |
324e52cc | 565 | (and (eq_attr "type" "mtjmpr") |
fe7f5677 | 566 | (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 567 | 4 1) |
cfb557c4 | 568 | |
c859cda6 DJ |
569 | (define_function_unit "sru" 1 0 |
570 | (and (eq_attr "type" "mtjmpr") | |
571 | (eq_attr "cpu" "ppc750,ppc7400")) | |
572 | 2 2) | |
573 | ||
574 | (define_function_unit "imuldiv" 1 0 | |
575 | (and (eq_attr "type" "mtjmpr") | |
576 | (eq_attr "cpu" "ppc7450")) | |
577 | 2 2) | |
578 | ||
39a10a29 GK |
579 | (define_function_unit "bpu" 1 0 |
580 | (and (eq_attr "type" "cr_logical") | |
5638268e | 581 | (eq_attr "cpu" "rios1,rios2,ppc604")) |
39a10a29 GK |
582 | 4 1) |
583 | ||
584 | (define_function_unit "cru" 1 0 | |
585 | (and (eq_attr "type" "cr_logical") | |
5638268e DE |
586 | (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a")) |
587 | 1 1) | |
39a10a29 | 588 | |
b6c9286a MM |
589 | ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines. |
590 | (define_function_unit "bpu" 1 0 | |
591 | (eq_attr "type" "jmpreg") | |
b7ff3d82 | 592 | 1 1) |
b6c9286a MM |
593 | |
594 | (define_function_unit "bpu" 1 0 | |
595 | (eq_attr "type" "branch") | |
b7ff3d82 | 596 | 1 1) |
b6c9286a | 597 | |
cf27b467 | 598 | ; Floating Point Unit |
cfb557c4 | 599 | (define_function_unit "fpu" 1 0 |
51b8fc2c | 600 | (and (eq_attr "type" "fp,dmul") |
2661cdd9 | 601 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 602 | 2 1) |
cfb557c4 | 603 | |
cf27b467 MM |
604 | (define_function_unit "fpu" 1 0 |
605 | (and (eq_attr "type" "fp") | |
3cb999d8 DE |
606 | (eq_attr "cpu" "rs64a,mpccore")) |
607 | 4 2) | |
cf27b467 | 608 | |
cfb557c4 RK |
609 | (define_function_unit "fpu" 1 0 |
610 | (and (eq_attr "type" "fp") | |
51b8fc2c | 611 | (eq_attr "cpu" "ppc601")) |
b7ff3d82 | 612 | 4 1) |
cfb557c4 | 613 | |
51b8fc2c RK |
614 | (define_function_unit "fpu" 1 0 |
615 | (and (eq_attr "type" "fp") | |
ed947a96 | 616 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750,ppc7400")) |
b6c9286a | 617 | 3 1) |
51b8fc2c | 618 | |
ed947a96 DJ |
619 | (define_function_unit "fpu" 1 0 |
620 | (and (eq_attr "type" "fp,dmul") | |
621 | (eq_attr "cpu" "ppc7450")) | |
622 | 5 1) | |
623 | ||
3cb999d8 DE |
624 | (define_function_unit "fpu" 1 0 |
625 | (and (eq_attr "type" "dmul") | |
626 | (eq_attr "cpu" "rs64a")) | |
627 | 7 2) | |
628 | ||
cf27b467 MM |
629 | (define_function_unit "fpu" 1 0 |
630 | (and (eq_attr "type" "dmul") | |
631 | (eq_attr "cpu" "mpccore")) | |
632 | 5 5) | |
633 | ||
cfb557c4 RK |
634 | (define_function_unit "fpu" 1 0 |
635 | (and (eq_attr "type" "dmul") | |
51b8fc2c | 636 | (eq_attr "cpu" "ppc601")) |
b6c9286a | 637 | 5 2) |
cfb557c4 | 638 | |
b6c9286a | 639 | ; is this true? |
cfb557c4 RK |
640 | (define_function_unit "fpu" 1 0 |
641 | (and (eq_attr "type" "dmul") | |
bef84347 | 642 | (eq_attr "cpu" "ppc603,ppc750")) |
51b8fc2c | 643 | 4 2) |
cfb557c4 RK |
644 | |
645 | (define_function_unit "fpu" 1 0 | |
51b8fc2c | 646 | (and (eq_attr "type" "dmul") |
ed947a96 | 647 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc7400")) |
b6c9286a | 648 | 3 1) |
51b8fc2c RK |
649 | |
650 | (define_function_unit "fpu" 1 0 | |
651 | (and (eq_attr "type" "sdiv,ddiv") | |
2661cdd9 | 652 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 653 | 19 19) |
cfb557c4 | 654 | |
3cb999d8 DE |
655 | (define_function_unit "fpu" 1 0 |
656 | (and (eq_attr "type" "sdiv") | |
657 | (eq_attr "cpu" "rs64a")) | |
658 | 31 31) | |
659 | ||
cfb557c4 RK |
660 | (define_function_unit "fpu" 1 0 |
661 | (and (eq_attr "type" "sdiv") | |
ed947a96 | 662 | (eq_attr "cpu" "ppc601,ppc750,ppc7400")) |
51b8fc2c RK |
663 | 17 17) |
664 | ||
ed947a96 DJ |
665 | (define_function_unit "fpu" 1 0 |
666 | (and (eq_attr "type" "sdiv") | |
667 | (eq_attr "cpu" "ppc7450")) | |
668 | 21 21) | |
669 | ||
cf27b467 MM |
670 | (define_function_unit "fpu" 1 0 |
671 | (and (eq_attr "type" "sdiv") | |
672 | (eq_attr "cpu" "mpccore")) | |
673 | 10 10) | |
674 | ||
51b8fc2c RK |
675 | (define_function_unit "fpu" 1 0 |
676 | (and (eq_attr "type" "sdiv") | |
cac8ce95 | 677 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620")) |
51b8fc2c | 678 | 18 18) |
cfb557c4 | 679 | |
cf27b467 MM |
680 | (define_function_unit "fpu" 1 0 |
681 | (and (eq_attr "type" "ddiv") | |
682 | (eq_attr "cpu" "mpccore")) | |
683 | 17 17) | |
684 | ||
cfb557c4 RK |
685 | (define_function_unit "fpu" 1 0 |
686 | (and (eq_attr "type" "ddiv") | |
ed947a96 | 687 | (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620,ppc7400")) |
51b8fc2c | 688 | 31 31) |
cfb557c4 | 689 | |
ed947a96 DJ |
690 | (define_function_unit "fpu" 1 0 |
691 | (and (eq_attr "type" "ddiv") | |
692 | (eq_attr "cpu" "ppc7450")) | |
693 | 35 35) | |
694 | ||
cfb557c4 RK |
695 | (define_function_unit "fpu" 1 0 |
696 | (and (eq_attr "type" "ddiv") | |
b7ff3d82 | 697 | (eq_attr "cpu" "ppc603")) |
51b8fc2c | 698 | 33 33) |
cfb557c4 RK |
699 | |
700 | (define_function_unit "fpu" 1 0 | |
701 | (and (eq_attr "type" "ssqrt") | |
a473029f | 702 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 703 | 31 31) |
cfb557c4 RK |
704 | |
705 | (define_function_unit "fpu" 1 0 | |
706 | (and (eq_attr "type" "dsqrt") | |
a473029f | 707 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 708 | 31 31) |
b73d04f2 | 709 | |
51b8fc2c | 710 | ; RIOS2 has two symmetric FPUs. |
cfb557c4 | 711 | (define_function_unit "fpu2" 2 0 |
309323c2 | 712 | (and (eq_attr "type" "fp,dmul") |
cfb557c4 | 713 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 714 | 2 1) |
cfb557c4 | 715 | |
3cb999d8 | 716 | (define_function_unit "fpu2" 2 0 |
309323c2 | 717 | (and (eq_attr "type" "fp,dmul") |
3cb999d8 DE |
718 | (eq_attr "cpu" "ppc630")) |
719 | 3 1) | |
720 | ||
cfb557c4 | 721 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 722 | (and (eq_attr "type" "sdiv,ddiv") |
cfb557c4 | 723 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 724 | 17 17) |
ca7f5001 | 725 | |
3cb999d8 DE |
726 | (define_function_unit "fpu2" 2 0 |
727 | (and (eq_attr "type" "sdiv") | |
728 | (eq_attr "cpu" "ppc630")) | |
729 | 17 17) | |
730 | ||
731 | (define_function_unit "fpu2" 2 0 | |
732 | (and (eq_attr "type" "ddiv") | |
733 | (eq_attr "cpu" "ppc630")) | |
734 | 21 21) | |
735 | ||
ca7f5001 | 736 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 737 | (and (eq_attr "type" "ssqrt,dsqrt") |
ca7f5001 | 738 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 739 | 26 26) |
b6c9286a | 740 | |
3cb999d8 DE |
741 | (define_function_unit "fpu2" 2 0 |
742 | (and (eq_attr "type" "ssqrt") | |
743 | (eq_attr "cpu" "ppc630")) | |
744 | 18 18) | |
745 | ||
746 | (define_function_unit "fpu2" 2 0 | |
747 | (and (eq_attr "type" "dsqrt") | |
748 | (eq_attr "cpu" "ppc630")) | |
749 | 26 26) | |
750 | ||
309323c2 DE |
751 | ;; Power4 |
752 | (define_function_unit "lsu2" 2 0 | |
753 | (and (eq_attr "type" "load") | |
754 | (eq_attr "cpu" "power4")) | |
755 | 3 1) | |
756 | ||
757 | (define_function_unit "lsu2" 2 0 | |
758 | (and (eq_attr "type" "fpload") | |
759 | (eq_attr "cpu" "power4")) | |
760 | 5 1) | |
761 | ||
762 | (define_function_unit "lsu2" 2 0 | |
763 | (and (eq_attr "type" "store,fpstore") | |
764 | (eq_attr "cpu" "power4")) | |
765 | 1 1) | |
766 | ||
767 | (define_function_unit "iu2" 2 0 | |
768 | (and (eq_attr "type" "integer") | |
769 | (eq_attr "cpu" "power4")) | |
770 | 2 1) | |
771 | ||
772 | (define_function_unit "iu2" 2 0 | |
773 | (and (eq_attr "type" "imul,lmul") | |
774 | (eq_attr "cpu" "power4")) | |
775 | 7 6) | |
776 | ||
777 | (define_function_unit "iu2" 2 0 | |
778 | (and (eq_attr "type" "imul2") | |
779 | (eq_attr "cpu" "power4")) | |
780 | 5 4) | |
781 | ||
782 | (define_function_unit "iu2" 2 0 | |
783 | (and (eq_attr "type" "imul3") | |
784 | (eq_attr "cpu" "power4")) | |
785 | 4 3) | |
786 | ||
787 | (define_function_unit "iu2" 2 0 | |
788 | (and (eq_attr "type" "idiv") | |
789 | (eq_attr "cpu" "power4")) | |
790 | 36 35) | |
791 | ||
792 | (define_function_unit "iu2" 2 0 | |
793 | (and (eq_attr "type" "ldiv") | |
794 | (eq_attr "cpu" "power4")) | |
795 | 68 67) | |
796 | ||
797 | (define_function_unit "imuldiv" 1 0 | |
798 | (and (eq_attr "type" "idiv") | |
799 | (eq_attr "cpu" "power4")) | |
800 | 36 35) | |
801 | ||
802 | (define_function_unit "imuldiv" 1 0 | |
803 | (and (eq_attr "type" "ldiv") | |
804 | (eq_attr "cpu" "power4")) | |
805 | 68 67) | |
806 | ||
807 | (define_function_unit "iu2" 2 0 | |
e3485bbc | 808 | (and (eq_attr "type" "compare") |
309323c2 | 809 | (eq_attr "cpu" "power4")) |
e3485bbc | 810 | 3 1) |
309323c2 DE |
811 | |
812 | (define_function_unit "iu2" 2 0 | |
e3485bbc | 813 | (and (eq_attr "type" "delayed_compare") |
309323c2 | 814 | (eq_attr "cpu" "power4")) |
e3485bbc | 815 | 4 1) |
309323c2 DE |
816 | |
817 | (define_function_unit "bpu" 1 0 | |
818 | (and (eq_attr "type" "mtjmpr") | |
819 | (eq_attr "cpu" "power4")) | |
820 | 3 1) | |
821 | ||
822 | (define_function_unit "bpu" 1 0 | |
823 | (and (eq_attr "type" "jmpreg,branch") | |
824 | (eq_attr "cpu" "power4")) | |
825 | 2 1) | |
826 | ||
827 | (define_function_unit "cru" 1 0 | |
828 | (and (eq_attr "type" "cr_logical") | |
829 | (eq_attr "cpu" "power4")) | |
830 | 4 1) | |
831 | ||
832 | (define_function_unit "fpu2" 2 0 | |
833 | (and (eq_attr "type" "fp,dmul") | |
834 | (eq_attr "cpu" "power4")) | |
835 | 6 1) | |
836 | ||
e3485bbc DE |
837 | ; adjust_cost increases the cost of dependent branches, |
838 | ; so shave a few cycles off for fpcompare. | |
309323c2 DE |
839 | (define_function_unit "fpu2" 2 0 |
840 | (and (eq_attr "type" "fpcompare") | |
841 | (eq_attr "cpu" "power4")) | |
e3485bbc | 842 | 5 1) |
309323c2 DE |
843 | |
844 | (define_function_unit "fpu2" 2 0 | |
845 | (and (eq_attr "type" "sdiv,ddiv") | |
846 | (eq_attr "cpu" "power4")) | |
847 | 33 28) | |
848 | ||
849 | (define_function_unit "fpu2" 2 0 | |
850 | (and (eq_attr "type" "ssqrt,dsqrt") | |
851 | (eq_attr "cpu" "power4")) | |
852 | 40 35) | |
853 | ||
1fd4e8c1 RK |
854 | \f |
855 | ;; Start with fixed-point load and store insns. Here we put only the more | |
856 | ;; complex forms. Basic data transfer is done later. | |
857 | ||
51b8fc2c RK |
858 | (define_expand "zero_extendqidi2" |
859 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
860 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
861 | "TARGET_POWERPC64" | |
862 | "") | |
863 | ||
864 | (define_insn "" | |
865 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
866 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
867 | "TARGET_POWERPC64" | |
868 | "@ | |
869 | lbz%U1%X1 %0,%1 | |
4371f8af | 870 | rldicl %0,%1,0,56" |
51b8fc2c RK |
871 | [(set_attr "type" "load,*")]) |
872 | ||
873 | (define_insn "" | |
9ebbca7d GK |
874 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
875 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 876 | (const_int 0))) |
9ebbca7d | 877 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 878 | "TARGET_POWERPC64" |
9ebbca7d GK |
879 | "@ |
880 | rldicl. %2,%1,0,56 | |
881 | #" | |
882 | [(set_attr "type" "compare") | |
883 | (set_attr "length" "4,8")]) | |
884 | ||
885 | (define_split | |
886 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
887 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
888 | (const_int 0))) | |
889 | (clobber (match_scratch:DI 2 ""))] | |
890 | "TARGET_POWERPC64 && reload_completed" | |
891 | [(set (match_dup 2) | |
892 | (zero_extend:DI (match_dup 1))) | |
893 | (set (match_dup 0) | |
894 | (compare:CC (match_dup 2) | |
895 | (const_int 0)))] | |
896 | "") | |
51b8fc2c RK |
897 | |
898 | (define_insn "" | |
9ebbca7d GK |
899 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
900 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 901 | (const_int 0))) |
9ebbca7d | 902 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 903 | (zero_extend:DI (match_dup 1)))] |
58e09803 | 904 | "TARGET_POWERPC64" |
9ebbca7d GK |
905 | "@ |
906 | rldicl. %0,%1,0,56 | |
907 | #" | |
908 | [(set_attr "type" "compare") | |
909 | (set_attr "length" "4,8")]) | |
910 | ||
911 | (define_split | |
912 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
913 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
914 | (const_int 0))) | |
915 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
916 | (zero_extend:DI (match_dup 1)))] | |
917 | "TARGET_POWERPC64 && reload_completed" | |
918 | [(set (match_dup 0) | |
919 | (zero_extend:DI (match_dup 1))) | |
920 | (set (match_dup 2) | |
921 | (compare:CC (match_dup 0) | |
922 | (const_int 0)))] | |
923 | "") | |
51b8fc2c | 924 | |
2bee0449 RK |
925 | (define_insn "extendqidi2" |
926 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
927 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 928 | "TARGET_POWERPC64" |
2bee0449 | 929 | "extsb %0,%1") |
51b8fc2c RK |
930 | |
931 | (define_insn "" | |
9ebbca7d GK |
932 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
933 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 934 | (const_int 0))) |
9ebbca7d | 935 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 936 | "TARGET_POWERPC64" |
9ebbca7d GK |
937 | "@ |
938 | extsb. %2,%1 | |
939 | #" | |
940 | [(set_attr "type" "compare") | |
941 | (set_attr "length" "4,8")]) | |
942 | ||
943 | (define_split | |
944 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
945 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
946 | (const_int 0))) | |
947 | (clobber (match_scratch:DI 2 ""))] | |
948 | "TARGET_POWERPC64 && reload_completed" | |
949 | [(set (match_dup 2) | |
950 | (sign_extend:DI (match_dup 1))) | |
951 | (set (match_dup 0) | |
952 | (compare:CC (match_dup 2) | |
953 | (const_int 0)))] | |
954 | "") | |
51b8fc2c RK |
955 | |
956 | (define_insn "" | |
9ebbca7d GK |
957 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
958 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 959 | (const_int 0))) |
9ebbca7d | 960 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
961 | (sign_extend:DI (match_dup 1)))] |
962 | "TARGET_POWERPC64" | |
9ebbca7d GK |
963 | "@ |
964 | extsb. %0,%1 | |
965 | #" | |
966 | [(set_attr "type" "compare") | |
967 | (set_attr "length" "4,8")]) | |
968 | ||
969 | (define_split | |
970 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
971 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
972 | (const_int 0))) | |
973 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
974 | (sign_extend:DI (match_dup 1)))] | |
975 | "TARGET_POWERPC64 && reload_completed" | |
976 | [(set (match_dup 0) | |
977 | (sign_extend:DI (match_dup 1))) | |
978 | (set (match_dup 2) | |
979 | (compare:CC (match_dup 0) | |
980 | (const_int 0)))] | |
981 | "") | |
51b8fc2c RK |
982 | |
983 | (define_expand "zero_extendhidi2" | |
984 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
985 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
986 | "TARGET_POWERPC64" | |
987 | "") | |
988 | ||
989 | (define_insn "" | |
990 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
991 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
992 | "TARGET_POWERPC64" | |
993 | "@ | |
994 | lhz%U1%X1 %0,%1 | |
4371f8af | 995 | rldicl %0,%1,0,48" |
51b8fc2c RK |
996 | [(set_attr "type" "load,*")]) |
997 | ||
998 | (define_insn "" | |
9ebbca7d GK |
999 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1000 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1001 | (const_int 0))) |
9ebbca7d | 1002 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 1003 | "TARGET_POWERPC64" |
9ebbca7d GK |
1004 | "@ |
1005 | rldicl. %2,%1,0,48 | |
1006 | #" | |
1007 | [(set_attr "type" "compare") | |
1008 | (set_attr "length" "4,8")]) | |
1009 | ||
1010 | (define_split | |
1011 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1012 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1013 | (const_int 0))) | |
1014 | (clobber (match_scratch:DI 2 ""))] | |
1015 | "TARGET_POWERPC64 && reload_completed" | |
1016 | [(set (match_dup 2) | |
1017 | (zero_extend:DI (match_dup 1))) | |
1018 | (set (match_dup 0) | |
1019 | (compare:CC (match_dup 2) | |
1020 | (const_int 0)))] | |
1021 | "") | |
51b8fc2c RK |
1022 | |
1023 | (define_insn "" | |
9ebbca7d GK |
1024 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1025 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1026 | (const_int 0))) |
9ebbca7d | 1027 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1028 | (zero_extend:DI (match_dup 1)))] |
1029 | "TARGET_POWERPC64" | |
9ebbca7d GK |
1030 | "@ |
1031 | rldicl. %0,%1,0,48 | |
1032 | #" | |
1033 | [(set_attr "type" "compare") | |
1034 | (set_attr "length" "4,8")]) | |
1035 | ||
1036 | (define_split | |
1037 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1038 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1039 | (const_int 0))) | |
1040 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
1041 | (zero_extend:DI (match_dup 1)))] | |
1042 | "TARGET_POWERPC64 && reload_completed" | |
1043 | [(set (match_dup 0) | |
1044 | (zero_extend:DI (match_dup 1))) | |
1045 | (set (match_dup 2) | |
1046 | (compare:CC (match_dup 0) | |
1047 | (const_int 0)))] | |
1048 | "") | |
51b8fc2c RK |
1049 | |
1050 | (define_expand "extendhidi2" | |
1051 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1052 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1053 | "TARGET_POWERPC64" | |
1054 | "") | |
1055 | ||
1056 | (define_insn "" | |
1057 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
1058 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
1059 | "TARGET_POWERPC64" | |
1060 | "@ | |
1061 | lha%U1%X1 %0,%1 | |
1062 | extsh %0,%1" | |
1063 | [(set_attr "type" "load,*")]) | |
1064 | ||
1065 | (define_insn "" | |
9ebbca7d GK |
1066 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1067 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1068 | (const_int 0))) |
9ebbca7d | 1069 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 1070 | "TARGET_POWERPC64" |
9ebbca7d GK |
1071 | "@ |
1072 | extsh. %2,%1 | |
1073 | #" | |
1074 | [(set_attr "type" "compare") | |
1075 | (set_attr "length" "4,8")]) | |
1076 | ||
1077 | (define_split | |
1078 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1079 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1080 | (const_int 0))) | |
1081 | (clobber (match_scratch:DI 2 ""))] | |
1082 | "TARGET_POWERPC64 && reload_completed" | |
1083 | [(set (match_dup 2) | |
1084 | (sign_extend:DI (match_dup 1))) | |
1085 | (set (match_dup 0) | |
1086 | (compare:CC (match_dup 2) | |
1087 | (const_int 0)))] | |
1088 | "") | |
51b8fc2c RK |
1089 | |
1090 | (define_insn "" | |
9ebbca7d GK |
1091 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1092 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1093 | (const_int 0))) |
9ebbca7d | 1094 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1095 | (sign_extend:DI (match_dup 1)))] |
1096 | "TARGET_POWERPC64" | |
9ebbca7d GK |
1097 | "@ |
1098 | extsh. %0,%1 | |
1099 | #" | |
1100 | [(set_attr "type" "compare") | |
1101 | (set_attr "length" "4,8")]) | |
1102 | ||
1103 | (define_split | |
1104 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1105 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1106 | (const_int 0))) | |
1107 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
1108 | (sign_extend:DI (match_dup 1)))] | |
1109 | "TARGET_POWERPC64 && reload_completed" | |
1110 | [(set (match_dup 0) | |
1111 | (sign_extend:DI (match_dup 1))) | |
1112 | (set (match_dup 2) | |
1113 | (compare:CC (match_dup 0) | |
1114 | (const_int 0)))] | |
1115 | "") | |
51b8fc2c RK |
1116 | |
1117 | (define_expand "zero_extendsidi2" | |
1118 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1119 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1120 | "TARGET_POWERPC64" | |
1121 | "") | |
1122 | ||
1123 | (define_insn "" | |
1124 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
1125 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
1126 | "TARGET_POWERPC64" | |
1127 | "@ | |
1128 | lwz%U1%X1 %0,%1 | |
1129 | rldicl %0,%1,0,32" | |
1130 | [(set_attr "type" "load,*")]) | |
1131 | ||
1132 | (define_insn "" | |
9ebbca7d GK |
1133 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1134 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1135 | (const_int 0))) |
9ebbca7d | 1136 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 1137 | "TARGET_POWERPC64" |
9ebbca7d GK |
1138 | "@ |
1139 | rldicl. %2,%1,0,32 | |
1140 | #" | |
1141 | [(set_attr "type" "compare") | |
1142 | (set_attr "length" "4,8")]) | |
1143 | ||
1144 | (define_split | |
1145 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1146 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1147 | (const_int 0))) | |
1148 | (clobber (match_scratch:DI 2 ""))] | |
1149 | "TARGET_POWERPC64 && reload_completed" | |
1150 | [(set (match_dup 2) | |
1151 | (zero_extend:DI (match_dup 1))) | |
1152 | (set (match_dup 0) | |
1153 | (compare:CC (match_dup 2) | |
1154 | (const_int 0)))] | |
1155 | "") | |
51b8fc2c RK |
1156 | |
1157 | (define_insn "" | |
9ebbca7d GK |
1158 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1159 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1160 | (const_int 0))) |
9ebbca7d | 1161 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1162 | (zero_extend:DI (match_dup 1)))] |
1163 | "TARGET_POWERPC64" | |
9ebbca7d GK |
1164 | "@ |
1165 | rldicl. %0,%1,0,32 | |
1166 | #" | |
1167 | [(set_attr "type" "compare") | |
1168 | (set_attr "length" "4,8")]) | |
1169 | ||
1170 | (define_split | |
1171 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1172 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1173 | (const_int 0))) | |
1174 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
1175 | (zero_extend:DI (match_dup 1)))] | |
1176 | "TARGET_POWERPC64 && reload_completed" | |
1177 | [(set (match_dup 0) | |
1178 | (zero_extend:DI (match_dup 1))) | |
1179 | (set (match_dup 2) | |
1180 | (compare:CC (match_dup 0) | |
1181 | (const_int 0)))] | |
1182 | "") | |
51b8fc2c RK |
1183 | |
1184 | (define_expand "extendsidi2" | |
1185 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1186 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1187 | "TARGET_POWERPC64" | |
1188 | "") | |
1189 | ||
1190 | (define_insn "" | |
1191 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 1192 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
1193 | "TARGET_POWERPC64" |
1194 | "@ | |
1195 | lwa%U1%X1 %0,%1 | |
1196 | extsw %0,%1" | |
1197 | [(set_attr "type" "load,*")]) | |
1198 | ||
1199 | (define_insn "" | |
9ebbca7d GK |
1200 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1201 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1202 | (const_int 0))) |
9ebbca7d | 1203 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 1204 | "TARGET_POWERPC64" |
9ebbca7d GK |
1205 | "@ |
1206 | extsw. %2,%1 | |
1207 | #" | |
1208 | [(set_attr "type" "compare") | |
1209 | (set_attr "length" "4,8")]) | |
1210 | ||
1211 | (define_split | |
1212 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1213 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1214 | (const_int 0))) | |
1215 | (clobber (match_scratch:DI 2 ""))] | |
1216 | "TARGET_POWERPC64 && reload_completed" | |
1217 | [(set (match_dup 2) | |
1218 | (sign_extend:DI (match_dup 1))) | |
1219 | (set (match_dup 0) | |
1220 | (compare:CC (match_dup 2) | |
1221 | (const_int 0)))] | |
1222 | "") | |
51b8fc2c RK |
1223 | |
1224 | (define_insn "" | |
9ebbca7d GK |
1225 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1226 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1227 | (const_int 0))) |
9ebbca7d | 1228 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1229 | (sign_extend:DI (match_dup 1)))] |
1230 | "TARGET_POWERPC64" | |
9ebbca7d GK |
1231 | "@ |
1232 | extsw. %0,%1 | |
1233 | #" | |
1234 | [(set_attr "type" "compare") | |
1235 | (set_attr "length" "4,8")]) | |
1236 | ||
1237 | (define_split | |
1238 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1239 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1240 | (const_int 0))) | |
1241 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
1242 | (sign_extend:DI (match_dup 1)))] | |
1243 | "TARGET_POWERPC64 && reload_completed" | |
1244 | [(set (match_dup 0) | |
1245 | (sign_extend:DI (match_dup 1))) | |
1246 | (set (match_dup 2) | |
1247 | (compare:CC (match_dup 0) | |
1248 | (const_int 0)))] | |
1249 | "") | |
51b8fc2c | 1250 | |
1fd4e8c1 | 1251 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
1252 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1253 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1254 | "" |
1255 | "") | |
1256 | ||
1257 | (define_insn "" | |
cd2b37d9 | 1258 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1259 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
1260 | "" | |
1261 | "@ | |
1262 | lbz%U1%X1 %0,%1 | |
005a35b9 | 1263 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
1264 | [(set_attr "type" "load,*")]) |
1265 | ||
1266 | (define_insn "" | |
9ebbca7d GK |
1267 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1268 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1269 | (const_int 0))) |
9ebbca7d | 1270 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1271 | "" |
9ebbca7d GK |
1272 | "@ |
1273 | {andil.|andi.} %2,%1,0xff | |
1274 | #" | |
1275 | [(set_attr "type" "compare") | |
1276 | (set_attr "length" "4,8")]) | |
1277 | ||
1278 | (define_split | |
1279 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1280 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1281 | (const_int 0))) | |
1282 | (clobber (match_scratch:SI 2 ""))] | |
1283 | "reload_completed" | |
1284 | [(set (match_dup 2) | |
1285 | (zero_extend:SI (match_dup 1))) | |
1286 | (set (match_dup 0) | |
1287 | (compare:CC (match_dup 2) | |
1288 | (const_int 0)))] | |
1289 | "") | |
1fd4e8c1 RK |
1290 | |
1291 | (define_insn "" | |
9ebbca7d GK |
1292 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1293 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1294 | (const_int 0))) |
9ebbca7d | 1295 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1296 | (zero_extend:SI (match_dup 1)))] |
1297 | "" | |
9ebbca7d GK |
1298 | "@ |
1299 | {andil.|andi.} %0,%1,0xff | |
1300 | #" | |
1301 | [(set_attr "type" "compare") | |
1302 | (set_attr "length" "4,8")]) | |
1303 | ||
1304 | (define_split | |
1305 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1306 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1307 | (const_int 0))) | |
1308 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1309 | (zero_extend:SI (match_dup 1)))] | |
1310 | "reload_completed" | |
1311 | [(set (match_dup 0) | |
1312 | (zero_extend:SI (match_dup 1))) | |
1313 | (set (match_dup 2) | |
1314 | (compare:CC (match_dup 0) | |
1315 | (const_int 0)))] | |
1316 | "") | |
1fd4e8c1 | 1317 | |
51b8fc2c RK |
1318 | (define_expand "extendqisi2" |
1319 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1320 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
1321 | "" | |
1322 | " | |
1323 | { | |
1324 | if (TARGET_POWERPC) | |
1325 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
1326 | else if (TARGET_POWER) | |
1327 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
1328 | else | |
1329 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
1330 | DONE; | |
1331 | }") | |
1332 | ||
1333 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
1334 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1335 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 1336 | "TARGET_POWERPC" |
2bee0449 | 1337 | "extsb %0,%1") |
51b8fc2c RK |
1338 | |
1339 | (define_insn "" | |
9ebbca7d GK |
1340 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1341 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1342 | (const_int 0))) |
9ebbca7d | 1343 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 1344 | "TARGET_POWERPC" |
9ebbca7d GK |
1345 | "@ |
1346 | extsb. %2,%1 | |
1347 | #" | |
1348 | [(set_attr "type" "compare") | |
1349 | (set_attr "length" "4,8")]) | |
1350 | ||
1351 | (define_split | |
1352 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1353 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1354 | (const_int 0))) | |
1355 | (clobber (match_scratch:SI 2 ""))] | |
1356 | "TARGET_POWERPC && reload_completed" | |
1357 | [(set (match_dup 2) | |
1358 | (sign_extend:SI (match_dup 1))) | |
1359 | (set (match_dup 0) | |
1360 | (compare:CC (match_dup 2) | |
1361 | (const_int 0)))] | |
1362 | "") | |
51b8fc2c RK |
1363 | |
1364 | (define_insn "" | |
9ebbca7d GK |
1365 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1366 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1367 | (const_int 0))) |
9ebbca7d | 1368 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1369 | (sign_extend:SI (match_dup 1)))] |
1370 | "TARGET_POWERPC" | |
9ebbca7d GK |
1371 | "@ |
1372 | extsb. %0,%1 | |
1373 | #" | |
1374 | [(set_attr "type" "compare") | |
1375 | (set_attr "length" "4,8")]) | |
1376 | ||
1377 | (define_split | |
1378 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1379 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1380 | (const_int 0))) | |
1381 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1382 | (sign_extend:SI (match_dup 1)))] | |
1383 | "TARGET_POWERPC && reload_completed" | |
1384 | [(set (match_dup 0) | |
1385 | (sign_extend:SI (match_dup 1))) | |
1386 | (set (match_dup 2) | |
1387 | (compare:CC (match_dup 0) | |
1388 | (const_int 0)))] | |
1389 | "") | |
51b8fc2c RK |
1390 | |
1391 | (define_expand "extendqisi2_power" | |
1392 | [(parallel [(set (match_dup 2) | |
1393 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1394 | (const_int 24))) | |
1395 | (clobber (scratch:SI))]) | |
1396 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1397 | (ashiftrt:SI (match_dup 2) | |
1398 | (const_int 24))) | |
1399 | (clobber (scratch:SI))])] | |
1400 | "TARGET_POWER" | |
1401 | " | |
1402 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1403 | operands[2] = gen_reg_rtx (SImode); }") | |
1404 | ||
1405 | (define_expand "extendqisi2_no_power" | |
1406 | [(set (match_dup 2) | |
1407 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1408 | (const_int 24))) | |
1409 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1410 | (ashiftrt:SI (match_dup 2) | |
1411 | (const_int 24)))] | |
1412 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1413 | " | |
1414 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1415 | operands[2] = gen_reg_rtx (SImode); }") | |
1416 | ||
1fd4e8c1 | 1417 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
1418 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
1419 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1420 | "" |
1421 | "") | |
1422 | ||
1423 | (define_insn "" | |
cd2b37d9 | 1424 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1425 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
1426 | "" | |
1427 | "@ | |
1428 | lbz%U1%X1 %0,%1 | |
005a35b9 | 1429 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
1430 | [(set_attr "type" "load,*")]) |
1431 | ||
1432 | (define_insn "" | |
9ebbca7d GK |
1433 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1434 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1435 | (const_int 0))) |
9ebbca7d | 1436 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 1437 | "" |
9ebbca7d GK |
1438 | "@ |
1439 | {andil.|andi.} %2,%1,0xff | |
1440 | #" | |
1441 | [(set_attr "type" "compare") | |
1442 | (set_attr "length" "4,8")]) | |
1443 | ||
1444 | (define_split | |
1445 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1446 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1447 | (const_int 0))) | |
1448 | (clobber (match_scratch:HI 2 ""))] | |
1449 | "reload_completed" | |
1450 | [(set (match_dup 2) | |
1451 | (zero_extend:HI (match_dup 1))) | |
1452 | (set (match_dup 0) | |
1453 | (compare:CC (match_dup 2) | |
1454 | (const_int 0)))] | |
1455 | "") | |
1fd4e8c1 | 1456 | |
51b8fc2c | 1457 | (define_insn "" |
9ebbca7d GK |
1458 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1459 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1460 | (const_int 0))) |
9ebbca7d | 1461 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
1462 | (zero_extend:HI (match_dup 1)))] |
1463 | "" | |
9ebbca7d GK |
1464 | "@ |
1465 | {andil.|andi.} %0,%1,0xff | |
1466 | #" | |
1467 | [(set_attr "type" "compare") | |
1468 | (set_attr "length" "4,8")]) | |
1469 | ||
1470 | (define_split | |
1471 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1472 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1473 | (const_int 0))) | |
1474 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1475 | (zero_extend:HI (match_dup 1)))] | |
1476 | "reload_completed" | |
1477 | [(set (match_dup 0) | |
1478 | (zero_extend:HI (match_dup 1))) | |
1479 | (set (match_dup 2) | |
1480 | (compare:CC (match_dup 0) | |
1481 | (const_int 0)))] | |
1482 | "") | |
815cdc52 MM |
1483 | |
1484 | (define_expand "extendqihi2" | |
1485 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
1486 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
1487 | "" | |
1488 | " | |
1489 | { | |
1490 | if (TARGET_POWERPC) | |
1491 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
1492 | else if (TARGET_POWER) | |
1493 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
1494 | else | |
1495 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
1496 | DONE; | |
1497 | }") | |
1498 | ||
1499 | (define_insn "extendqihi2_ppc" | |
1500 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
1501 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
1502 | "TARGET_POWERPC" | |
1503 | "extsb %0,%1") | |
1504 | ||
1505 | (define_insn "" | |
9ebbca7d GK |
1506 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1507 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1508 | (const_int 0))) |
9ebbca7d | 1509 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 1510 | "TARGET_POWERPC" |
9ebbca7d GK |
1511 | "@ |
1512 | extsb. %2,%1 | |
1513 | #" | |
1514 | [(set_attr "type" "compare") | |
1515 | (set_attr "length" "4,8")]) | |
1516 | ||
1517 | (define_split | |
1518 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1519 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1520 | (const_int 0))) | |
1521 | (clobber (match_scratch:HI 2 ""))] | |
1522 | "TARGET_POWERPC && reload_completed" | |
1523 | [(set (match_dup 2) | |
1524 | (sign_extend:HI (match_dup 1))) | |
1525 | (set (match_dup 0) | |
1526 | (compare:CC (match_dup 2) | |
1527 | (const_int 0)))] | |
1528 | "") | |
815cdc52 MM |
1529 | |
1530 | (define_insn "" | |
9ebbca7d GK |
1531 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1532 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1533 | (const_int 0))) |
9ebbca7d | 1534 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1535 | (sign_extend:HI (match_dup 1)))] |
1536 | "TARGET_POWERPC" | |
9ebbca7d GK |
1537 | "@ |
1538 | extsb. %0,%1 | |
1539 | #" | |
1540 | [(set_attr "type" "compare") | |
1541 | (set_attr "length" "4,8")]) | |
1542 | ||
1543 | (define_split | |
1544 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1545 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1546 | (const_int 0))) | |
1547 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1548 | (sign_extend:HI (match_dup 1)))] | |
1549 | "TARGET_POWERPC && reload_completed" | |
1550 | [(set (match_dup 0) | |
1551 | (sign_extend:HI (match_dup 1))) | |
1552 | (set (match_dup 2) | |
1553 | (compare:CC (match_dup 0) | |
1554 | (const_int 0)))] | |
1555 | "") | |
51b8fc2c RK |
1556 | |
1557 | (define_expand "extendqihi2_power" | |
1558 | [(parallel [(set (match_dup 2) | |
1559 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1560 | (const_int 24))) | |
1561 | (clobber (scratch:SI))]) | |
1562 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
1563 | (ashiftrt:SI (match_dup 2) | |
1564 | (const_int 24))) | |
1565 | (clobber (scratch:SI))])] | |
1566 | "TARGET_POWER" | |
1567 | " | |
1568 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1569 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1570 | operands[2] = gen_reg_rtx (SImode); }") | |
1571 | ||
1572 | (define_expand "extendqihi2_no_power" | |
1573 | [(set (match_dup 2) | |
1574 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1575 | (const_int 24))) | |
1576 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1577 | (ashiftrt:SI (match_dup 2) | |
1578 | (const_int 24)))] | |
1579 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1580 | " | |
1581 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1582 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1583 | operands[2] = gen_reg_rtx (SImode); }") | |
1584 | ||
1fd4e8c1 | 1585 | (define_expand "zero_extendhisi2" |
5f243543 | 1586 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 1587 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
1588 | "" |
1589 | "") | |
1590 | ||
1591 | (define_insn "" | |
cd2b37d9 | 1592 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1593 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1594 | "" | |
1595 | "@ | |
1596 | lhz%U1%X1 %0,%1 | |
005a35b9 | 1597 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
1598 | [(set_attr "type" "load,*")]) |
1599 | ||
1600 | (define_insn "" | |
9ebbca7d GK |
1601 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1602 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1603 | (const_int 0))) |
9ebbca7d | 1604 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1605 | "" |
9ebbca7d GK |
1606 | "@ |
1607 | {andil.|andi.} %2,%1,0xffff | |
1608 | #" | |
1609 | [(set_attr "type" "compare") | |
1610 | (set_attr "length" "4,8")]) | |
1611 | ||
1612 | (define_split | |
1613 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1614 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1615 | (const_int 0))) | |
1616 | (clobber (match_scratch:SI 2 ""))] | |
1617 | "reload_completed" | |
1618 | [(set (match_dup 2) | |
1619 | (zero_extend:SI (match_dup 1))) | |
1620 | (set (match_dup 0) | |
1621 | (compare:CC (match_dup 2) | |
1622 | (const_int 0)))] | |
1623 | "") | |
1fd4e8c1 RK |
1624 | |
1625 | (define_insn "" | |
9ebbca7d GK |
1626 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1627 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1628 | (const_int 0))) |
9ebbca7d | 1629 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1630 | (zero_extend:SI (match_dup 1)))] |
1631 | "" | |
9ebbca7d GK |
1632 | "@ |
1633 | {andil.|andi.} %0,%1,0xffff | |
1634 | #" | |
1635 | [(set_attr "type" "compare") | |
1636 | (set_attr "length" "4,8")]) | |
1637 | ||
1638 | (define_split | |
1639 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1640 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1641 | (const_int 0))) | |
1642 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1643 | (zero_extend:SI (match_dup 1)))] | |
1644 | "reload_completed" | |
1645 | [(set (match_dup 0) | |
1646 | (zero_extend:SI (match_dup 1))) | |
1647 | (set (match_dup 2) | |
1648 | (compare:CC (match_dup 0) | |
1649 | (const_int 0)))] | |
1650 | "") | |
1fd4e8c1 RK |
1651 | |
1652 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
1653 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1654 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1655 | "" |
1656 | "") | |
1657 | ||
1658 | (define_insn "" | |
cd2b37d9 | 1659 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1660 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1661 | "" | |
1662 | "@ | |
1663 | lha%U1%X1 %0,%1 | |
ca7f5001 | 1664 | {exts|extsh} %0,%1" |
1fd4e8c1 RK |
1665 | [(set_attr "type" "load,*")]) |
1666 | ||
1667 | (define_insn "" | |
9ebbca7d GK |
1668 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1669 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1670 | (const_int 0))) |
9ebbca7d | 1671 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1672 | "" |
9ebbca7d GK |
1673 | "@ |
1674 | {exts.|extsh.} %2,%1 | |
1675 | #" | |
1676 | [(set_attr "type" "compare") | |
1677 | (set_attr "length" "4,8")]) | |
1678 | ||
1679 | (define_split | |
1680 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1681 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1682 | (const_int 0))) | |
1683 | (clobber (match_scratch:SI 2 ""))] | |
1684 | "reload_completed" | |
1685 | [(set (match_dup 2) | |
1686 | (sign_extend:SI (match_dup 1))) | |
1687 | (set (match_dup 0) | |
1688 | (compare:CC (match_dup 2) | |
1689 | (const_int 0)))] | |
1690 | "") | |
1fd4e8c1 RK |
1691 | |
1692 | (define_insn "" | |
9ebbca7d GK |
1693 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1694 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1695 | (const_int 0))) |
9ebbca7d | 1696 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1697 | (sign_extend:SI (match_dup 1)))] |
1698 | "" | |
9ebbca7d GK |
1699 | "@ |
1700 | {exts.|extsh.} %0,%1 | |
1701 | #" | |
1702 | [(set_attr "type" "compare") | |
1703 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1704 | \f |
9ebbca7d GK |
1705 | (define_split |
1706 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1707 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1708 | (const_int 0))) | |
1709 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1710 | (sign_extend:SI (match_dup 1)))] | |
1711 | "reload_completed" | |
1712 | [(set (match_dup 0) | |
1713 | (sign_extend:SI (match_dup 1))) | |
1714 | (set (match_dup 2) | |
1715 | (compare:CC (match_dup 0) | |
1716 | (const_int 0)))] | |
1717 | "") | |
1718 | ||
1fd4e8c1 | 1719 | ;; Fixed-point arithmetic insns. |
deb9225a RK |
1720 | |
1721 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
1722 | ;; allowing register zero as source. | |
7cd5235b MM |
1723 | (define_expand "addsi3" |
1724 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1725 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 1726 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
7cd5235b MM |
1727 | "" |
1728 | " | |
1729 | { | |
677a9668 DE |
1730 | if (GET_CODE (operands[2]) == CONST_INT |
1731 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 1732 | { |
677a9668 | 1733 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
1734 | ? operands[0] : gen_reg_rtx (SImode)); |
1735 | ||
2bfcf297 | 1736 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1737 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 1738 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
7cd5235b | 1739 | |
9ebbca7d GK |
1740 | /* The ordering here is important for the prolog expander. |
1741 | When space is allocated from the stack, adding 'low' first may | |
1742 | produce a temporary deallocation (which would be bad). */ | |
2bfcf297 | 1743 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest))); |
7cd5235b MM |
1744 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); |
1745 | DONE; | |
1746 | } | |
1747 | }") | |
1748 | ||
1749 | (define_insn "*addsi3_internal1" | |
1750 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
1751 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 1752 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1753 | "" |
1754 | "@ | |
deb9225a RK |
1755 | {cax|add} %0,%1,%2 |
1756 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1757 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1758 | {cau|addis} %0,%1,%v2" |
1759 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1760 | |
ee890fe2 SS |
1761 | (define_insn "addsi3_high" |
1762 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1763 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1764 | (high:SI (match_operand 2 "" ""))))] | |
1765 | "TARGET_MACHO && !TARGET_64BIT" | |
1766 | "{cau|addis} %0,%1,ha16(%2)" | |
1767 | [(set_attr "length" "4")]) | |
1768 | ||
7cd5235b | 1769 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1770 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1771 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1772 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1773 | (const_int 0))) |
cb8cc086 | 1774 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
0ad91047 | 1775 | "! TARGET_POWERPC64" |
deb9225a RK |
1776 | "@ |
1777 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1778 | {ai.|addic.} %3,%1,%2 |
1779 | # | |
1780 | #" | |
1781 | [(set_attr "type" "compare") | |
1782 | (set_attr "length" "4,4,8,8")]) | |
1783 | ||
1784 | (define_split | |
1785 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1786 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1787 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1788 | (const_int 0))) | |
1789 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1790 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1791 | [(set (match_dup 3) |
1792 | (plus:SI (match_dup 1) | |
1793 | (match_dup 2))) | |
1794 | (set (match_dup 0) | |
1795 | (compare:CC (match_dup 3) | |
1796 | (const_int 0)))] | |
1797 | "") | |
7e69e155 | 1798 | |
7cd5235b | 1799 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1800 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1801 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1802 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1803 | (const_int 0))) |
cb8cc086 MM |
1804 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1805 | (plus:SI (match_dup 1) | |
1806 | (match_dup 2)))] | |
0ad91047 | 1807 | "! TARGET_POWERPC64" |
deb9225a RK |
1808 | "@ |
1809 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1810 | {ai.|addic.} %0,%1,%2 |
1811 | # | |
1812 | #" | |
1813 | [(set_attr "type" "compare") | |
1814 | (set_attr "length" "4,4,8,8")]) | |
1815 | ||
1816 | (define_split | |
1817 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1818 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1819 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1820 | (const_int 0))) | |
1821 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1822 | (plus:SI (match_dup 1) (match_dup 2)))] | |
0ad91047 | 1823 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1824 | [(set (match_dup 0) |
1825 | (plus:SI (match_dup 1) | |
1826 | (match_dup 2))) | |
1827 | (set (match_dup 3) | |
1828 | (compare:CC (match_dup 0) | |
1829 | (const_int 0)))] | |
1830 | "") | |
7e69e155 | 1831 | |
f357808b RK |
1832 | ;; Split an add that we can't do in one insn into two insns, each of which |
1833 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1834 | ;; add should be last in case the result gets used in an address. | |
1835 | ||
1836 | (define_split | |
cd2b37d9 RK |
1837 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1838 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1839 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1840 | "" |
f357808b RK |
1841 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1842 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1843 | " | |
1fd4e8c1 | 1844 | { |
2bfcf297 | 1845 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1846 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 1847 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
1fd4e8c1 | 1848 | |
2bfcf297 | 1849 | operands[3] = GEN_INT (rest); |
e6ca2c17 | 1850 | operands[4] = GEN_INT (low); |
1fd4e8c1 RK |
1851 | }") |
1852 | ||
8de2a197 | 1853 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1854 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1855 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1856 | "" |
ca7f5001 RK |
1857 | "nor %0,%1,%1") |
1858 | ||
1859 | (define_insn "" | |
52d3af72 DE |
1860 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1861 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1862 | (const_int 0))) |
52d3af72 | 1863 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1864 | "! TARGET_POWERPC64" |
52d3af72 DE |
1865 | "@ |
1866 | nor. %2,%1,%1 | |
1867 | #" | |
1868 | [(set_attr "type" "compare") | |
1869 | (set_attr "length" "4,8")]) | |
1870 | ||
1871 | (define_split | |
1872 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1873 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1874 | (const_int 0))) | |
1875 | (clobber (match_scratch:SI 2 ""))] | |
0ad91047 | 1876 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1877 | [(set (match_dup 2) |
1878 | (not:SI (match_dup 1))) | |
1879 | (set (match_dup 0) | |
1880 | (compare:CC (match_dup 2) | |
1881 | (const_int 0)))] | |
1882 | "") | |
ca7f5001 RK |
1883 | |
1884 | (define_insn "" | |
52d3af72 DE |
1885 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1886 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1887 | (const_int 0))) |
52d3af72 | 1888 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1889 | (not:SI (match_dup 1)))] |
0ad91047 | 1890 | "! TARGET_POWERPC64" |
52d3af72 DE |
1891 | "@ |
1892 | nor. %0,%1,%1 | |
1893 | #" | |
1894 | [(set_attr "type" "compare") | |
1895 | (set_attr "length" "4,8")]) | |
1896 | ||
1897 | (define_split | |
1898 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1899 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1900 | (const_int 0))) | |
1cb18e3c | 1901 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
52d3af72 | 1902 | (not:SI (match_dup 1)))] |
0ad91047 | 1903 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1904 | [(set (match_dup 0) |
1905 | (not:SI (match_dup 1))) | |
1906 | (set (match_dup 2) | |
1907 | (compare:CC (match_dup 0) | |
1908 | (const_int 0)))] | |
1909 | "") | |
1fd4e8c1 RK |
1910 | |
1911 | (define_insn "" | |
3d91674b RK |
1912 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1913 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1914 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1915 | "! TARGET_POWERPC" |
ca7f5001 | 1916 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1917 | |
deb9225a RK |
1918 | (define_insn "" |
1919 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1920 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1921 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1922 | "TARGET_POWERPC" | |
1923 | "@ | |
1924 | subf %0,%2,%1 | |
1925 | subfic %0,%2,%1") | |
1926 | ||
1fd4e8c1 | 1927 | (define_insn "" |
cb8cc086 MM |
1928 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1929 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1930 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1931 | (const_int 0))) |
cb8cc086 | 1932 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1933 | "! TARGET_POWERPC" |
cb8cc086 MM |
1934 | "@ |
1935 | {sf.|subfc.} %3,%2,%1 | |
1936 | #" | |
1937 | [(set_attr "type" "compare") | |
1938 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1939 | |
deb9225a | 1940 | (define_insn "" |
cb8cc086 MM |
1941 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1942 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1943 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1944 | (const_int 0))) |
cb8cc086 | 1945 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 1946 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
cb8cc086 MM |
1947 | "@ |
1948 | subf. %3,%2,%1 | |
1949 | #" | |
1950 | [(set_attr "type" "compare") | |
1951 | (set_attr "length" "4,8")]) | |
1952 | ||
1953 | (define_split | |
1954 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1955 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1956 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1957 | (const_int 0))) | |
1958 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1959 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1960 | [(set (match_dup 3) |
1961 | (minus:SI (match_dup 1) | |
1962 | (match_dup 2))) | |
1963 | (set (match_dup 0) | |
1964 | (compare:CC (match_dup 3) | |
1965 | (const_int 0)))] | |
1966 | "") | |
deb9225a | 1967 | |
1fd4e8c1 | 1968 | (define_insn "" |
cb8cc086 MM |
1969 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1970 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1971 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1972 | (const_int 0))) |
cb8cc086 | 1973 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1974 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1975 | "! TARGET_POWERPC" |
cb8cc086 MM |
1976 | "@ |
1977 | {sf.|subfc.} %0,%2,%1 | |
1978 | #" | |
1979 | [(set_attr "type" "compare") | |
1980 | (set_attr "length" "4,8")]) | |
815cdc52 | 1981 | |
29ae5b89 | 1982 | (define_insn "" |
cb8cc086 MM |
1983 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1984 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1985 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1986 | (const_int 0))) |
cb8cc086 MM |
1987 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1988 | (minus:SI (match_dup 1) | |
1989 | (match_dup 2)))] | |
0ad91047 | 1990 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
90612787 DE |
1991 | "@ |
1992 | subf. %0,%2,%1 | |
1993 | #" | |
cb8cc086 MM |
1994 | [(set_attr "type" "compare") |
1995 | (set_attr "length" "4,8")]) | |
1996 | ||
1997 | (define_split | |
1998 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1999 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2000 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2001 | (const_int 0))) | |
2002 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2003 | (minus:SI (match_dup 1) | |
2004 | (match_dup 2)))] | |
0ad91047 | 2005 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
2006 | [(set (match_dup 0) |
2007 | (minus:SI (match_dup 1) | |
2008 | (match_dup 2))) | |
2009 | (set (match_dup 3) | |
2010 | (compare:CC (match_dup 0) | |
2011 | (const_int 0)))] | |
2012 | "") | |
deb9225a | 2013 | |
1fd4e8c1 | 2014 | (define_expand "subsi3" |
cd2b37d9 | 2015 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 2016 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
f6bf7de2 | 2017 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
1fd4e8c1 | 2018 | "" |
a0044fb1 RK |
2019 | " |
2020 | { | |
2021 | if (GET_CODE (operands[2]) == CONST_INT) | |
2022 | { | |
2023 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
2024 | negate_rtx (SImode, operands[2]))); | |
2025 | DONE; | |
2026 | } | |
2027 | }") | |
1fd4e8c1 RK |
2028 | |
2029 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
2030 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
2031 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
2032 | ;; combine. | |
1fd4e8c1 RK |
2033 | |
2034 | (define_expand "sminsi3" | |
2035 | [(set (match_dup 3) | |
cd2b37d9 | 2036 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
2037 | (match_operand:SI 2 "reg_or_short_operand" "")) |
2038 | (const_int 0) | |
2039 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 2040 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 2041 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 2042 | "TARGET_POWER" |
1fd4e8c1 RK |
2043 | " |
2044 | { operands[3] = gen_reg_rtx (SImode); }") | |
2045 | ||
95ac8e67 RK |
2046 | (define_split |
2047 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2048 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2049 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
2050 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 2051 | "TARGET_POWER" |
95ac8e67 RK |
2052 | [(set (match_dup 3) |
2053 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
2054 | (const_int 0) | |
2055 | (minus:SI (match_dup 2) (match_dup 1)))) | |
2056 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
2057 | "") | |
2058 | ||
1fd4e8c1 RK |
2059 | (define_expand "smaxsi3" |
2060 | [(set (match_dup 3) | |
cd2b37d9 | 2061 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
2062 | (match_operand:SI 2 "reg_or_short_operand" "")) |
2063 | (const_int 0) | |
2064 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 2065 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 2066 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 2067 | "TARGET_POWER" |
1fd4e8c1 RK |
2068 | " |
2069 | { operands[3] = gen_reg_rtx (SImode); }") | |
2070 | ||
95ac8e67 RK |
2071 | (define_split |
2072 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2073 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2074 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
2075 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 2076 | "TARGET_POWER" |
95ac8e67 RK |
2077 | [(set (match_dup 3) |
2078 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
2079 | (const_int 0) | |
2080 | (minus:SI (match_dup 2) (match_dup 1)))) | |
2081 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
2082 | "") | |
2083 | ||
1fd4e8c1 | 2084 | (define_expand "uminsi3" |
cd2b37d9 | 2085 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 2086 | (match_dup 5))) |
cd2b37d9 | 2087 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 2088 | (match_dup 5))) |
1fd4e8c1 RK |
2089 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
2090 | (const_int 0) | |
2091 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 2092 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 2093 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 2094 | "TARGET_POWER" |
1fd4e8c1 | 2095 | " |
bb68ff55 MM |
2096 | { |
2097 | operands[3] = gen_reg_rtx (SImode); | |
2098 | operands[4] = gen_reg_rtx (SImode); | |
2099 | operands[5] = GEN_INT (-2147483647 - 1); | |
2100 | }") | |
1fd4e8c1 RK |
2101 | |
2102 | (define_expand "umaxsi3" | |
cd2b37d9 | 2103 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 2104 | (match_dup 5))) |
cd2b37d9 | 2105 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 2106 | (match_dup 5))) |
1fd4e8c1 RK |
2107 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
2108 | (const_int 0) | |
2109 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 2110 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 2111 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 2112 | "TARGET_POWER" |
1fd4e8c1 | 2113 | " |
bb68ff55 MM |
2114 | { |
2115 | operands[3] = gen_reg_rtx (SImode); | |
2116 | operands[4] = gen_reg_rtx (SImode); | |
2117 | operands[5] = GEN_INT (-2147483647 - 1); | |
2118 | }") | |
1fd4e8c1 RK |
2119 | |
2120 | (define_insn "" | |
cd2b37d9 RK |
2121 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2122 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 2123 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
2124 | (const_int 0) |
2125 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 2126 | "TARGET_POWER" |
1fd4e8c1 RK |
2127 | "doz%I2 %0,%1,%2") |
2128 | ||
2129 | (define_insn "" | |
9ebbca7d | 2130 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2131 | (compare:CC |
9ebbca7d GK |
2132 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
2133 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
2134 | (const_int 0) |
2135 | (minus:SI (match_dup 2) (match_dup 1))) | |
2136 | (const_int 0))) | |
9ebbca7d | 2137 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 2138 | "TARGET_POWER" |
9ebbca7d GK |
2139 | "@ |
2140 | doz%I2. %3,%1,%2 | |
2141 | #" | |
2142 | [(set_attr "type" "delayed_compare") | |
2143 | (set_attr "length" "4,8")]) | |
2144 | ||
2145 | (define_split | |
2146 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2147 | (compare:CC | |
2148 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
2149 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
2150 | (const_int 0) | |
2151 | (minus:SI (match_dup 2) (match_dup 1))) | |
2152 | (const_int 0))) | |
2153 | (clobber (match_scratch:SI 3 ""))] | |
2154 | "TARGET_POWER && reload_completed" | |
2155 | [(set (match_dup 3) | |
2156 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
2157 | (const_int 0) | |
2158 | (minus:SI (match_dup 2) (match_dup 1)))) | |
2159 | (set (match_dup 0) | |
2160 | (compare:CC (match_dup 3) | |
2161 | (const_int 0)))] | |
2162 | "") | |
1fd4e8c1 RK |
2163 | |
2164 | (define_insn "" | |
9ebbca7d | 2165 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2166 | (compare:CC |
9ebbca7d GK |
2167 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
2168 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
2169 | (const_int 0) |
2170 | (minus:SI (match_dup 2) (match_dup 1))) | |
2171 | (const_int 0))) | |
9ebbca7d | 2172 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
2173 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
2174 | (const_int 0) | |
2175 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 2176 | "TARGET_POWER" |
9ebbca7d GK |
2177 | "@ |
2178 | doz%I2. %0,%1,%2 | |
2179 | #" | |
2180 | [(set_attr "type" "delayed_compare") | |
2181 | (set_attr "length" "4,8")]) | |
2182 | ||
2183 | (define_split | |
2184 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2185 | (compare:CC | |
2186 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
2187 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
2188 | (const_int 0) | |
2189 | (minus:SI (match_dup 2) (match_dup 1))) | |
2190 | (const_int 0))) | |
2191 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2192 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
2193 | (const_int 0) | |
2194 | (minus:SI (match_dup 2) (match_dup 1))))] | |
2195 | "TARGET_POWER && reload_completed" | |
2196 | [(set (match_dup 0) | |
2197 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
2198 | (const_int 0) | |
2199 | (minus:SI (match_dup 2) (match_dup 1)))) | |
2200 | (set (match_dup 3) | |
2201 | (compare:CC (match_dup 0) | |
2202 | (const_int 0)))] | |
2203 | "") | |
1fd4e8c1 RK |
2204 | |
2205 | ;; We don't need abs with condition code because such comparisons should | |
2206 | ;; never be done. | |
ea9be077 MM |
2207 | (define_expand "abssi2" |
2208 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2209 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
2210 | "" | |
2211 | " | |
2212 | { | |
0ad91047 | 2213 | if (! TARGET_POWER) |
ea9be077 MM |
2214 | { |
2215 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
2216 | DONE; | |
2217 | } | |
2218 | }") | |
2219 | ||
ea112fc4 | 2220 | (define_insn "*abssi2_power" |
cd2b37d9 RK |
2221 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2222 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 2223 | "TARGET_POWER" |
1fd4e8c1 RK |
2224 | "abs %0,%1") |
2225 | ||
ea112fc4 | 2226 | (define_insn_and_split "abssi2_nopower" |
ea9be077 | 2227 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 2228 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) |
ea9be077 | 2229 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
0ad91047 | 2230 | "! TARGET_POWER" |
ea112fc4 DE |
2231 | "#" |
2232 | "&& reload_completed" | |
ea9be077 MM |
2233 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
2234 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 2235 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
2236 | "") |
2237 | ||
463b558b | 2238 | (define_insn "*nabs_power" |
cd2b37d9 RK |
2239 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2240 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 2241 | "TARGET_POWER" |
1fd4e8c1 RK |
2242 | "nabs %0,%1") |
2243 | ||
ea112fc4 | 2244 | (define_insn_and_split "*nabs_nopower" |
ea9be077 | 2245 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 2246 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) |
ea9be077 | 2247 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
0ad91047 | 2248 | "! TARGET_POWER" |
ea112fc4 DE |
2249 | "#" |
2250 | "&& reload_completed" | |
ea9be077 MM |
2251 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
2252 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 2253 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
2254 | "") |
2255 | ||
1fd4e8c1 | 2256 | (define_insn "negsi2" |
cd2b37d9 RK |
2257 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2258 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
2259 | "" |
2260 | "neg %0,%1") | |
2261 | ||
2262 | (define_insn "" | |
9ebbca7d GK |
2263 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2264 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2265 | (const_int 0))) |
9ebbca7d | 2266 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 2267 | "! TARGET_POWERPC64" |
9ebbca7d GK |
2268 | "@ |
2269 | neg. %2,%1 | |
2270 | #" | |
2271 | [(set_attr "type" "compare") | |
2272 | (set_attr "length" "4,8")]) | |
2273 | ||
2274 | (define_split | |
2275 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2276 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2277 | (const_int 0))) | |
2278 | (clobber (match_scratch:SI 2 ""))] | |
2279 | "! TARGET_POWERPC64 && reload_completed" | |
2280 | [(set (match_dup 2) | |
2281 | (neg:SI (match_dup 1))) | |
2282 | (set (match_dup 0) | |
2283 | (compare:CC (match_dup 2) | |
2284 | (const_int 0)))] | |
2285 | "") | |
1fd4e8c1 RK |
2286 | |
2287 | (define_insn "" | |
9ebbca7d GK |
2288 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
2289 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2290 | (const_int 0))) |
9ebbca7d | 2291 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 2292 | (neg:SI (match_dup 1)))] |
0ad91047 | 2293 | "! TARGET_POWERPC64" |
9ebbca7d GK |
2294 | "@ |
2295 | neg. %0,%1 | |
2296 | #" | |
2297 | [(set_attr "type" "compare") | |
2298 | (set_attr "length" "4,8")]) | |
2299 | ||
2300 | (define_split | |
2301 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
2302 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2303 | (const_int 0))) | |
2304 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2305 | (neg:SI (match_dup 1)))] | |
2306 | "! TARGET_POWERPC64 && reload_completed" | |
2307 | [(set (match_dup 0) | |
2308 | (neg:SI (match_dup 1))) | |
2309 | (set (match_dup 2) | |
2310 | (compare:CC (match_dup 0) | |
2311 | (const_int 0)))] | |
2312 | "") | |
1fd4e8c1 RK |
2313 | |
2314 | (define_insn "ffssi2" | |
242e8072 RK |
2315 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
2316 | (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 2317 | "" |
7f340546 | 2318 | "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" |
b19003d8 | 2319 | [(set_attr "length" "16")]) |
1fd4e8c1 | 2320 | |
ca7f5001 RK |
2321 | (define_expand "mulsi3" |
2322 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
2323 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
2324 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
2325 | "" | |
2326 | " | |
2327 | { | |
2328 | if (TARGET_POWER) | |
68b40e7e | 2329 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 2330 | else |
68b40e7e | 2331 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
2332 | DONE; |
2333 | }") | |
2334 | ||
68b40e7e | 2335 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
2336 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2337 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
2338 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
2339 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
2340 | "TARGET_POWER" |
2341 | "@ | |
2342 | {muls|mullw} %0,%1,%2 | |
2343 | {muli|mulli} %0,%1,%2" | |
c859cda6 DJ |
2344 | [(set (attr "type") |
2345 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") | |
2346 | (const_string "imul3") | |
2347 | (match_operand:SI 2 "short_cint_operand" "") | |
2348 | (const_string "imul2")] | |
2349 | (const_string "imul")))]) | |
ca7f5001 | 2350 | |
68b40e7e | 2351 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
2352 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2353 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2354 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 2355 | "! TARGET_POWER" |
1fd4e8c1 | 2356 | "@ |
d904e9ed RK |
2357 | {muls|mullw} %0,%1,%2 |
2358 | {muli|mulli} %0,%1,%2" | |
c859cda6 DJ |
2359 | [(set (attr "type") |
2360 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") | |
2361 | (const_string "imul3") | |
2362 | (match_operand:SI 2 "short_cint_operand" "") | |
2363 | (const_string "imul2")] | |
2364 | (const_string "imul")))]) | |
1fd4e8c1 RK |
2365 | |
2366 | (define_insn "" | |
9ebbca7d GK |
2367 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2368 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2369 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2370 | (const_int 0))) |
9ebbca7d GK |
2371 | (clobber (match_scratch:SI 3 "=r,r")) |
2372 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 2373 | "TARGET_POWER" |
9ebbca7d GK |
2374 | "@ |
2375 | {muls.|mullw.} %3,%1,%2 | |
2376 | #" | |
2377 | [(set_attr "type" "delayed_compare") | |
2378 | (set_attr "length" "4,8")]) | |
2379 | ||
2380 | (define_split | |
2381 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2382 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2383 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2384 | (const_int 0))) | |
2385 | (clobber (match_scratch:SI 3 "")) | |
2386 | (clobber (match_scratch:SI 4 ""))] | |
2387 | "TARGET_POWER && reload_completed" | |
2388 | [(parallel [(set (match_dup 3) | |
2389 | (mult:SI (match_dup 1) (match_dup 2))) | |
2390 | (clobber (match_dup 4))]) | |
2391 | (set (match_dup 0) | |
2392 | (compare:CC (match_dup 3) | |
2393 | (const_int 0)))] | |
2394 | "") | |
ca7f5001 RK |
2395 | |
2396 | (define_insn "" | |
9ebbca7d GK |
2397 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2398 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2399 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2400 | (const_int 0))) |
9ebbca7d | 2401 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 2402 | "! TARGET_POWER" |
9ebbca7d GK |
2403 | "@ |
2404 | {muls.|mullw.} %3,%1,%2 | |
2405 | #" | |
2406 | [(set_attr "type" "delayed_compare") | |
2407 | (set_attr "length" "4,8")]) | |
2408 | ||
2409 | (define_split | |
2410 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2411 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2412 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2413 | (const_int 0))) | |
2414 | (clobber (match_scratch:SI 3 ""))] | |
2415 | "! TARGET_POWER && reload_completed" | |
2416 | [(set (match_dup 3) | |
2417 | (mult:SI (match_dup 1) (match_dup 2))) | |
2418 | (set (match_dup 0) | |
2419 | (compare:CC (match_dup 3) | |
2420 | (const_int 0)))] | |
2421 | "") | |
1fd4e8c1 RK |
2422 | |
2423 | (define_insn "" | |
9ebbca7d GK |
2424 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2425 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2426 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2427 | (const_int 0))) |
9ebbca7d | 2428 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2429 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 2430 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 2431 | "TARGET_POWER" |
9ebbca7d GK |
2432 | "@ |
2433 | {muls.|mullw.} %0,%1,%2 | |
2434 | #" | |
2435 | [(set_attr "type" "delayed_compare") | |
2436 | (set_attr "length" "4,8")]) | |
2437 | ||
2438 | (define_split | |
2439 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2440 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2441 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2442 | (const_int 0))) | |
2443 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2444 | (mult:SI (match_dup 1) (match_dup 2))) | |
2445 | (clobber (match_scratch:SI 4 ""))] | |
2446 | "TARGET_POWER && reload_completed" | |
2447 | [(parallel [(set (match_dup 0) | |
2448 | (mult:SI (match_dup 1) (match_dup 2))) | |
2449 | (clobber (match_dup 4))]) | |
2450 | (set (match_dup 3) | |
2451 | (compare:CC (match_dup 0) | |
2452 | (const_int 0)))] | |
2453 | "") | |
ca7f5001 RK |
2454 | |
2455 | (define_insn "" | |
9ebbca7d GK |
2456 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2457 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2458 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2459 | (const_int 0))) |
9ebbca7d | 2460 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 2461 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 2462 | "! TARGET_POWER" |
9ebbca7d GK |
2463 | "@ |
2464 | {muls.|mullw.} %0,%1,%2 | |
2465 | #" | |
2466 | [(set_attr "type" "delayed_compare") | |
2467 | (set_attr "length" "4,8")]) | |
2468 | ||
2469 | (define_split | |
2470 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2471 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2472 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2473 | (const_int 0))) | |
2474 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2475 | (mult:SI (match_dup 1) (match_dup 2)))] | |
2476 | "! TARGET_POWER && reload_completed" | |
2477 | [(set (match_dup 0) | |
2478 | (mult:SI (match_dup 1) (match_dup 2))) | |
2479 | (set (match_dup 3) | |
2480 | (compare:CC (match_dup 0) | |
2481 | (const_int 0)))] | |
2482 | "") | |
1fd4e8c1 RK |
2483 | |
2484 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
2485 | ;; 0 and remainder to operand 3. | |
2486 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
2487 | ||
8ffd9c51 RK |
2488 | (define_expand "divmodsi4" |
2489 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2490 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2491 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2492 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
2493 | (mod:SI (match_dup 1) (match_dup 2)))])] | |
2494 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2495 | " | |
2496 | { | |
2497 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2498 | { | |
39403d82 DE |
2499 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2500 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2501 | emit_insn (gen_divss_call ()); |
39403d82 DE |
2502 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2503 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
2504 | DONE; |
2505 | } | |
2506 | }") | |
deb9225a | 2507 | |
fada905b | 2508 | (define_insn "" |
cd2b37d9 RK |
2509 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2510 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2511 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2512 | (set (match_operand:SI 3 "gpc_reg_operand" "=q") | |
1fd4e8c1 | 2513 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 2514 | "TARGET_POWER" |
cfb557c4 RK |
2515 | "divs %0,%1,%2" |
2516 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 2517 | |
8ffd9c51 RK |
2518 | (define_expand "udivsi3" |
2519 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2520 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2521 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
2522 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2523 | " | |
2524 | { | |
2525 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2526 | { | |
39403d82 DE |
2527 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2528 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2529 | emit_insn (gen_quous_call ()); |
39403d82 | 2530 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2531 | DONE; |
2532 | } | |
f192bf8b DE |
2533 | else if (TARGET_POWER) |
2534 | { | |
2535 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
2536 | DONE; | |
2537 | } | |
8ffd9c51 | 2538 | }") |
deb9225a | 2539 | |
f192bf8b DE |
2540 | (define_insn "udivsi3_mq" |
2541 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2542 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2543 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2544 | (clobber (match_scratch:SI 3 "=q"))] | |
2545 | "TARGET_POWERPC && TARGET_POWER" | |
2546 | "divwu %0,%1,%2" | |
2547 | [(set_attr "type" "idiv")]) | |
2548 | ||
2549 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
2550 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2551 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2552 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 2553 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 2554 | "divwu %0,%1,%2" |
ca7f5001 RK |
2555 | [(set_attr "type" "idiv")]) |
2556 | ||
1fd4e8c1 | 2557 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 2558 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
2559 | ;; used; for PowerPC, force operands into register and do a normal divide; |
2560 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 2561 | (define_expand "divsi3" |
cd2b37d9 RK |
2562 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2563 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
2564 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
2565 | "" | |
2566 | " | |
2567 | { | |
ca7f5001 | 2568 | if (GET_CODE (operands[2]) == CONST_INT |
2bfcf297 | 2569 | && INTVAL (operands[2]) > 0 |
ca7f5001 RK |
2570 | && exact_log2 (INTVAL (operands[2])) >= 0) |
2571 | ; | |
b6c9286a | 2572 | else if (TARGET_POWERPC) |
f192bf8b DE |
2573 | { |
2574 | operands[2] = force_reg (SImode, operands[2]); | |
2575 | if (TARGET_POWER) | |
2576 | { | |
2577 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
2578 | DONE; | |
2579 | } | |
2580 | } | |
b6c9286a | 2581 | else if (TARGET_POWER) |
1fd4e8c1 | 2582 | FAIL; |
405c5495 | 2583 | else |
8ffd9c51 | 2584 | { |
39403d82 DE |
2585 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2586 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2587 | emit_insn (gen_quoss_call ()); |
39403d82 | 2588 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2589 | DONE; |
2590 | } | |
1fd4e8c1 RK |
2591 | }") |
2592 | ||
f192bf8b DE |
2593 | (define_insn "divsi3_mq" |
2594 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2595 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2596 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2597 | (clobber (match_scratch:SI 3 "=q"))] | |
2598 | "TARGET_POWERPC && TARGET_POWER" | |
2599 | "divw %0,%1,%2" | |
2600 | [(set_attr "type" "idiv")]) | |
2601 | ||
2602 | (define_insn "*divsi3_no_mq" | |
2603 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2604 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2605 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
2606 | "TARGET_POWERPC && ! TARGET_POWER" | |
2607 | "divw %0,%1,%2" | |
2608 | [(set_attr "type" "idiv")]) | |
2609 | ||
1fd4e8c1 | 2610 | (define_expand "modsi3" |
85644414 RK |
2611 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
2612 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 2613 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 2614 | "" |
1fd4e8c1 RK |
2615 | " |
2616 | { | |
481c7efa | 2617 | int i; |
39b52ba2 RK |
2618 | rtx temp1; |
2619 | rtx temp2; | |
2620 | ||
2bfcf297 | 2621 | if (GET_CODE (operands[2]) != CONST_INT |
a65c591c | 2622 | || INTVAL (operands[2]) <= 0 |
2bfcf297 | 2623 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) |
39b52ba2 RK |
2624 | FAIL; |
2625 | ||
2626 | temp1 = gen_reg_rtx (SImode); | |
2627 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 2628 | |
85644414 | 2629 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 2630 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
2631 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
2632 | DONE; | |
1fd4e8c1 RK |
2633 | }") |
2634 | ||
2635 | (define_insn "" | |
cd2b37d9 RK |
2636 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2637 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
2638 | (match_operand:SI 2 "exact_log2_cint_operand" "N")))] |
2639 | "" | |
ca7f5001 | 2640 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 2641 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
2642 | |
2643 | (define_insn "" | |
9ebbca7d GK |
2644 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2645 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2646 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2647 | (const_int 0))) |
9ebbca7d | 2648 | (clobber (match_scratch:SI 3 "=r,r"))] |
2bfcf297 | 2649 | "" |
9ebbca7d GK |
2650 | "@ |
2651 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
2652 | #" | |
b19003d8 | 2653 | [(set_attr "type" "compare") |
9ebbca7d GK |
2654 | (set_attr "length" "8,12")]) |
2655 | ||
2656 | (define_split | |
2657 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2658 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2659 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2660 | (const_int 0))) |
2661 | (clobber (match_scratch:SI 3 ""))] | |
2bfcf297 | 2662 | "reload_completed" |
9ebbca7d GK |
2663 | [(set (match_dup 3) |
2664 | (div:SI (match_dup 1) (match_dup 2))) | |
2665 | (set (match_dup 0) | |
2666 | (compare:CC (match_dup 3) | |
2667 | (const_int 0)))] | |
2668 | "") | |
1fd4e8c1 RK |
2669 | |
2670 | (define_insn "" | |
9ebbca7d GK |
2671 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2672 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2673 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2674 | (const_int 0))) |
9ebbca7d | 2675 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2676 | (div:SI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 2677 | "" |
9ebbca7d GK |
2678 | "@ |
2679 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2680 | #" | |
b19003d8 | 2681 | [(set_attr "type" "compare") |
9ebbca7d GK |
2682 | (set_attr "length" "8,12")]) |
2683 | ||
2684 | (define_split | |
2685 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2686 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2687 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2688 | (const_int 0))) |
2689 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2690 | (div:SI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2691 | "reload_completed" |
9ebbca7d GK |
2692 | [(set (match_dup 0) |
2693 | (div:SI (match_dup 1) (match_dup 2))) | |
2694 | (set (match_dup 3) | |
2695 | (compare:CC (match_dup 0) | |
2696 | (const_int 0)))] | |
2697 | "") | |
1fd4e8c1 RK |
2698 | |
2699 | (define_insn "" | |
cd2b37d9 | 2700 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2701 | (udiv:SI |
996a5f59 | 2702 | (plus:DI (ashift:DI |
cd2b37d9 | 2703 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2704 | (const_int 32)) |
23a900dc | 2705 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2706 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2707 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2708 | (umod:SI |
996a5f59 | 2709 | (plus:DI (ashift:DI |
1fd4e8c1 | 2710 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2711 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2712 | (match_dup 3)))] |
ca7f5001 | 2713 | "TARGET_POWER" |
cfb557c4 RK |
2714 | "div %0,%1,%3" |
2715 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2716 | |
2717 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2718 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2719 | ;; have to worry about the branches. So make a few subroutines here. | |
2720 | ;; | |
2721 | ;; First comes the normal case. | |
2722 | (define_expand "udivmodsi4_normal" | |
2723 | [(set (match_dup 4) (const_int 0)) | |
2724 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2725 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2726 | (const_int 32)) |
2727 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2728 | (match_operand:SI 2 "" ""))) | |
2729 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2730 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2731 | (const_int 32)) |
2732 | (zero_extend:DI (match_dup 1))) | |
2733 | (match_dup 2)))])] | |
ca7f5001 | 2734 | "TARGET_POWER" |
1fd4e8c1 RK |
2735 | " |
2736 | { operands[4] = gen_reg_rtx (SImode); }") | |
2737 | ||
2738 | ;; This handles the branches. | |
2739 | (define_expand "udivmodsi4_tests" | |
2740 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2741 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2742 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2743 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2744 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2745 | (set (match_dup 0) (const_int 1)) | |
2746 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2747 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2748 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2749 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2750 | "TARGET_POWER" |
1fd4e8c1 RK |
2751 | " |
2752 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2753 | operands[6] = gen_reg_rtx (CCmode); | |
2754 | }") | |
2755 | ||
2756 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2757 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2758 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2759 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2760 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2761 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2762 | "" |
1fd4e8c1 RK |
2763 | " |
2764 | { | |
2765 | rtx label = 0; | |
2766 | ||
8ffd9c51 | 2767 | if (! TARGET_POWER) |
c4d38ccb MM |
2768 | { |
2769 | if (! TARGET_POWERPC) | |
2770 | { | |
39403d82 DE |
2771 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2772 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2773 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2774 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2775 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2776 | DONE; |
2777 | } | |
2778 | else | |
2779 | FAIL; | |
2780 | } | |
0081a354 | 2781 | |
1fd4e8c1 RK |
2782 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2783 | { | |
2784 | operands[2] = force_reg (SImode, operands[2]); | |
2785 | label = gen_label_rtx (); | |
2786 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2787 | operands[3], label)); | |
2788 | } | |
2789 | else | |
2790 | operands[2] = force_reg (SImode, operands[2]); | |
2791 | ||
2792 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2793 | operands[3])); | |
2794 | if (label) | |
2795 | emit_label (label); | |
2796 | ||
2797 | DONE; | |
2798 | }") | |
0081a354 | 2799 | |
fada905b MM |
2800 | ;; AIX architecture-independent common-mode multiply (DImode), |
2801 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2802 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2803 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2804 | ;; assumed unused if generating common-mode, so ignore. | |
2805 | (define_insn "mulh_call" | |
2806 | [(set (reg:SI 3) | |
2807 | (truncate:SI | |
2808 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2809 | (sign_extend:DI (reg:SI 4))) | |
2810 | (const_int 32)))) | |
cf27b467 | 2811 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2812 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2813 | "bla __mulh" |
2814 | [(set_attr "type" "imul")]) | |
fada905b MM |
2815 | |
2816 | (define_insn "mull_call" | |
2817 | [(set (reg:DI 3) | |
2818 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2819 | (sign_extend:DI (reg:SI 4)))) | |
2820 | (clobber (match_scratch:SI 0 "=l")) | |
2821 | (clobber (reg:SI 0))] | |
2822 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2823 | "bla __mull" |
2824 | [(set_attr "type" "imul")]) | |
fada905b MM |
2825 | |
2826 | (define_insn "divss_call" | |
2827 | [(set (reg:SI 3) | |
2828 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2829 | (set (reg:SI 4) | |
2830 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2831 | (clobber (match_scratch:SI 0 "=l")) | |
2832 | (clobber (reg:SI 0))] | |
2833 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2834 | "bla __divss" |
2835 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2836 | |
2837 | (define_insn "divus_call" | |
8ffd9c51 RK |
2838 | [(set (reg:SI 3) |
2839 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2840 | (set (reg:SI 4) | |
2841 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2842 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2843 | (clobber (reg:SI 0)) |
2844 | (clobber (match_scratch:CC 1 "=x")) | |
2845 | (clobber (reg:CC 69))] | |
2846 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2847 | "bla __divus" |
2848 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2849 | |
2850 | (define_insn "quoss_call" | |
2851 | [(set (reg:SI 3) | |
2852 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2853 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2854 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2855 | "bla __quoss" |
2856 | [(set_attr "type" "idiv")]) | |
0081a354 | 2857 | |
fada905b MM |
2858 | (define_insn "quous_call" |
2859 | [(set (reg:SI 3) | |
2860 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2861 | (clobber (match_scratch:SI 0 "=l")) | |
2862 | (clobber (reg:SI 0)) | |
2863 | (clobber (match_scratch:CC 1 "=x")) | |
2864 | (clobber (reg:CC 69))] | |
2865 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2866 | "bla __quous" |
2867 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2868 | \f |
bb21487f | 2869 | ;; Logical instructions |
dfbdccdb GK |
2870 | ;; The logical instructions are mostly combined by using match_operator, |
2871 | ;; but the plain AND insns are somewhat different because there is no | |
2872 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2873 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2874 | ||
29ae5b89 JL |
2875 | (define_insn "andsi3" |
2876 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2877 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2878 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2879 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2880 | "" |
2881 | "@ | |
2882 | and %0,%1,%2 | |
ca7f5001 RK |
2883 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2884 | {andil.|andi.} %0,%1,%b2 | |
9ebbca7d | 2885 | {andiu.|andis.} %0,%1,%u2") |
52d3af72 DE |
2886 | |
2887 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
0ba1b2ff | 2888 | ;; the test again -- this avoids a mfcr which on the higher end |
52d3af72 | 2889 | ;; machines causes an execution serialization |
1fd4e8c1 | 2890 | |
7cd5235b | 2891 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2892 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2893 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2894 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2895 | (const_int 0))) |
52d3af72 DE |
2896 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2897 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2898 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2899 | "@ |
2900 | and. %3,%1,%2 | |
ca7f5001 RK |
2901 | {andil.|andi.} %3,%1,%b2 |
2902 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2903 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2904 | # | |
2905 | # | |
2906 | # | |
2907 | #" | |
2908 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2909 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2910 | |
0ba1b2ff AM |
2911 | (define_insn "*andsi3_internal3" |
2912 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2913 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2914 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2915 | (const_int 0))) | |
2916 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) | |
2917 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
2918 | "TARGET_POWERPC64" | |
2919 | "@ | |
2920 | # | |
2921 | {andil.|andi.} %3,%1,%b2 | |
2922 | {andiu.|andis.} %3,%1,%u2 | |
2923 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 | |
2924 | # | |
2925 | # | |
2926 | # | |
2927 | #" | |
2928 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2929 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2930 | ||
52d3af72 DE |
2931 | (define_split |
2932 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2933 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2934 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 2935 | (const_int 0))) |
52d3af72 DE |
2936 | (clobber (match_scratch:SI 3 "")) |
2937 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2938 | "reload_completed" |
52d3af72 DE |
2939 | [(parallel [(set (match_dup 3) |
2940 | (and:SI (match_dup 1) | |
2941 | (match_dup 2))) | |
2942 | (clobber (match_dup 4))]) | |
2943 | (set (match_dup 0) | |
2944 | (compare:CC (match_dup 3) | |
2945 | (const_int 0)))] | |
2946 | "") | |
2947 | ||
0ba1b2ff AM |
2948 | ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the |
2949 | ;; whole 64 bit reg, and we don't know what is in the high 32 bits. | |
2950 | ||
2951 | (define_split | |
2952 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
2953 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2954 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2955 | (const_int 0))) | |
2956 | (clobber (match_scratch:SI 3 "")) | |
2957 | (clobber (match_scratch:CC 4 ""))] | |
2958 | "TARGET_POWERPC64 && reload_completed" | |
2959 | [(parallel [(set (match_dup 3) | |
2960 | (and:SI (match_dup 1) | |
2961 | (match_dup 2))) | |
2962 | (clobber (match_dup 4))]) | |
2963 | (set (match_dup 0) | |
2964 | (compare:CC (match_dup 3) | |
2965 | (const_int 0)))] | |
2966 | "") | |
2967 | ||
2968 | (define_insn "*andsi3_internal4" | |
52d3af72 DE |
2969 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2970 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2971 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2972 | (const_int 0))) |
2973 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2974 | (and:SI (match_dup 1) | |
2975 | (match_dup 2))) | |
2976 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2977 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2978 | "@ |
2979 | and. %0,%1,%2 | |
ca7f5001 RK |
2980 | {andil.|andi.} %0,%1,%b2 |
2981 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2982 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2983 | # | |
2984 | # | |
2985 | # | |
2986 | #" | |
2987 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2988 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2989 | ||
0ba1b2ff AM |
2990 | (define_insn "*andsi3_internal5" |
2991 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2992 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2993 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2994 | (const_int 0))) | |
2995 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2996 | (and:SI (match_dup 1) | |
2997 | (match_dup 2))) | |
2998 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
2999 | "TARGET_POWERPC64" | |
3000 | "@ | |
3001 | # | |
3002 | {andil.|andi.} %0,%1,%b2 | |
3003 | {andiu.|andis.} %0,%1,%u2 | |
3004 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 | |
3005 | # | |
3006 | # | |
3007 | # | |
3008 | #" | |
3009 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
3010 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
3011 | ||
52d3af72 DE |
3012 | (define_split |
3013 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3014 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3015 | (match_operand:SI 2 "and_operand" "")) | |
3016 | (const_int 0))) | |
3017 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3018 | (and:SI (match_dup 1) | |
3019 | (match_dup 2))) | |
3020 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 3021 | "reload_completed" |
52d3af72 DE |
3022 | [(parallel [(set (match_dup 0) |
3023 | (and:SI (match_dup 1) | |
3024 | (match_dup 2))) | |
3025 | (clobber (match_dup 4))]) | |
3026 | (set (match_dup 3) | |
3027 | (compare:CC (match_dup 0) | |
3028 | (const_int 0)))] | |
3029 | "") | |
1fd4e8c1 | 3030 | |
0ba1b2ff AM |
3031 | (define_split |
3032 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
3033 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3034 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
3035 | (const_int 0))) | |
3036 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3037 | (and:SI (match_dup 1) | |
3038 | (match_dup 2))) | |
3039 | (clobber (match_scratch:CC 4 ""))] | |
3040 | "TARGET_POWERPC64 && reload_completed" | |
3041 | [(parallel [(set (match_dup 0) | |
3042 | (and:SI (match_dup 1) | |
3043 | (match_dup 2))) | |
3044 | (clobber (match_dup 4))]) | |
3045 | (set (match_dup 3) | |
3046 | (compare:CC (match_dup 0) | |
3047 | (const_int 0)))] | |
3048 | "") | |
3049 | ||
3050 | ;; Handle the PowerPC64 rlwinm corner case | |
3051 | ||
3052 | (define_insn_and_split "*andsi3_internal6" | |
3053 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3054 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3055 | (match_operand:SI 2 "mask_operand_wrap" "i")))] | |
3056 | "TARGET_POWERPC64" | |
3057 | "#" | |
3058 | "TARGET_POWERPC64" | |
3059 | [(set (match_dup 0) | |
3060 | (and:SI (rotate:SI (match_dup 1) (match_dup 3)) | |
3061 | (match_dup 4))) | |
3062 | (set (match_dup 0) | |
3063 | (rotate:SI (match_dup 0) (match_dup 5)))] | |
3064 | " | |
3065 | { | |
3066 | int mb = extract_MB (operands[2]); | |
3067 | int me = extract_ME (operands[2]); | |
3068 | operands[3] = GEN_INT (me + 1); | |
3069 | operands[5] = GEN_INT (32 - (me + 1)); | |
3070 | operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
3071 | }" | |
3072 | [(set_attr "length" "8")]) | |
3073 | ||
3074 | (define_insn_and_split "*andsi3_internal7" | |
3075 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") | |
3076 | (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r") | |
3077 | (match_operand:SI 1 "mask_operand_wrap" "i,i")) | |
3078 | (const_int 0))) | |
3079 | (clobber (match_scratch:SI 3 "=r,r"))] | |
3080 | "TARGET_POWERPC64" | |
3081 | "#" | |
3082 | "TARGET_POWERPC64" | |
3083 | [(parallel [(set (match_dup 2) | |
3084 | (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4)) | |
3085 | (match_dup 5)) | |
3086 | (const_int 0))) | |
3087 | (clobber (match_dup 3))])] | |
3088 | " | |
3089 | { | |
3090 | int mb = extract_MB (operands[1]); | |
3091 | int me = extract_ME (operands[1]); | |
3092 | operands[4] = GEN_INT (me + 1); | |
3093 | operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
3094 | }" | |
3095 | [(set_attr "type" "delayed_compare,compare") | |
3096 | (set_attr "length" "4,8")]) | |
3097 | ||
3098 | (define_insn_and_split "*andsi3_internal8" | |
3099 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y") | |
3100 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3101 | (match_operand:SI 2 "mask_operand_wrap" "i,i")) | |
3102 | (const_int 0))) | |
3103 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
3104 | (and:SI (match_dup 1) | |
3105 | (match_dup 2)))] | |
3106 | "TARGET_POWERPC64" | |
3107 | "#" | |
3108 | "TARGET_POWERPC64" | |
3109 | [(parallel [(set (match_dup 3) | |
3110 | (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4)) | |
3111 | (match_dup 5)) | |
3112 | (const_int 0))) | |
3113 | (set (match_dup 0) | |
3114 | (and:SI (rotate:SI (match_dup 1) (match_dup 4)) | |
3115 | (match_dup 5)))]) | |
3116 | (set (match_dup 0) | |
3117 | (rotate:SI (match_dup 0) (match_dup 6)))] | |
3118 | " | |
3119 | { | |
3120 | int mb = extract_MB (operands[2]); | |
3121 | int me = extract_ME (operands[2]); | |
3122 | operands[4] = GEN_INT (me + 1); | |
3123 | operands[6] = GEN_INT (32 - (me + 1)); | |
3124 | operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
3125 | }" | |
3126 | [(set_attr "type" "delayed_compare,compare") | |
3127 | (set_attr "length" "8,12")]) | |
3128 | ||
7cd5235b | 3129 | (define_expand "iorsi3" |
cd2b37d9 | 3130 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 3131 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 3132 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 3133 | "" |
f357808b RK |
3134 | " |
3135 | { | |
7cd5235b | 3136 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 3137 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
3138 | { |
3139 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 3140 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
3141 | ? operands[0] : gen_reg_rtx (SImode)); |
3142 | ||
a260abc9 DE |
3143 | emit_insn (gen_iorsi3 (tmp, operands[1], |
3144 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
3145 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
3146 | DONE; |
3147 | } | |
f357808b RK |
3148 | }") |
3149 | ||
7cd5235b | 3150 | (define_expand "xorsi3" |
cd2b37d9 | 3151 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 3152 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 3153 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 3154 | "" |
7cd5235b | 3155 | " |
1fd4e8c1 | 3156 | { |
7cd5235b | 3157 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 3158 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
3159 | { |
3160 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 3161 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
3162 | ? operands[0] : gen_reg_rtx (SImode)); |
3163 | ||
a260abc9 DE |
3164 | emit_insn (gen_xorsi3 (tmp, operands[1], |
3165 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
3166 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
3167 | DONE; |
3168 | } | |
1fd4e8c1 RK |
3169 | }") |
3170 | ||
dfbdccdb | 3171 | (define_insn "*boolsi3_internal1" |
7cd5235b | 3172 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 3173 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
3174 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
3175 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
3176 | "" |
3177 | "@ | |
dfbdccdb GK |
3178 | %q3 %0,%1,%2 |
3179 | {%q3il|%q3i} %0,%1,%b2 | |
3180 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 3181 | |
dfbdccdb | 3182 | (define_insn "*boolsi3_internal2" |
52d3af72 | 3183 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 3184 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
3185 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
3186 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
3187 | (const_int 0))) | |
52d3af72 | 3188 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3189 | "! TARGET_POWERPC64" |
52d3af72 | 3190 | "@ |
dfbdccdb | 3191 | %q4. %3,%1,%2 |
52d3af72 DE |
3192 | #" |
3193 | [(set_attr "type" "compare") | |
3194 | (set_attr "length" "4,8")]) | |
3195 | ||
3196 | (define_split | |
3197 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 3198 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3199 | [(match_operand:SI 1 "gpc_reg_operand" "") |
3200 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 3201 | (const_int 0))) |
52d3af72 | 3202 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 3203 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3204 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
3205 | (set (match_dup 0) |
3206 | (compare:CC (match_dup 3) | |
3207 | (const_int 0)))] | |
3208 | "") | |
815cdc52 | 3209 | |
dfbdccdb | 3210 | (define_insn "*boolsi3_internal3" |
52d3af72 | 3211 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
3212 | (compare:CC (match_operator:SI 4 "boolean_operator" |
3213 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
3214 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
3215 | (const_int 0))) | |
52d3af72 | 3216 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 3217 | (match_dup 4))] |
0ad91047 | 3218 | "! TARGET_POWERPC64" |
52d3af72 | 3219 | "@ |
dfbdccdb | 3220 | %q4. %0,%1,%2 |
52d3af72 DE |
3221 | #" |
3222 | [(set_attr "type" "compare") | |
3223 | (set_attr "length" "4,8")]) | |
3224 | ||
3225 | (define_split | |
e72247f4 | 3226 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 3227 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3228 | [(match_operand:SI 1 "gpc_reg_operand" "") |
3229 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 3230 | (const_int 0))) |
75540af0 | 3231 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 3232 | (match_dup 4))] |
0ad91047 | 3233 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3234 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
3235 | (set (match_dup 3) |
3236 | (compare:CC (match_dup 0) | |
3237 | (const_int 0)))] | |
3238 | "") | |
1fd4e8c1 | 3239 | |
dfbdccdb GK |
3240 | ;; Split an logical operation that we can't do in one insn into two insns, |
3241 | ;; each of which does one 16-bit part. This is used by combine. | |
a260abc9 DE |
3242 | |
3243 | (define_split | |
3244 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 3245 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
3246 | [(match_operand:SI 1 "gpc_reg_operand" "") |
3247 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 3248 | "" |
dfbdccdb GK |
3249 | [(set (match_dup 0) (match_dup 4)) |
3250 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
3251 | " |
3252 | { | |
dfbdccdb GK |
3253 | rtx i; |
3254 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
3255 | operands[4] = gen_rtx (GET_CODE (operands[3]), SImode, | |
3256 | operands[1], i); | |
3257 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
3258 | operands[5] = gen_rtx (GET_CODE (operands[3]), SImode, | |
3259 | operands[0], i); | |
a260abc9 DE |
3260 | }") |
3261 | ||
dfbdccdb | 3262 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 3263 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
3264 | (match_operator:SI 3 "boolean_operator" |
3265 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 3266 | (match_operand:SI 2 "gpc_reg_operand" "r")]))] |
1fd4e8c1 | 3267 | "" |
dfbdccdb | 3268 | "%q3 %0,%2,%1") |
1fd4e8c1 | 3269 | |
dfbdccdb | 3270 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 3271 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
3272 | (compare:CC (match_operator:SI 4 "boolean_operator" |
3273 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
3274 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
3275 | (const_int 0))) | |
52d3af72 | 3276 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3277 | "! TARGET_POWERPC64" |
52d3af72 | 3278 | "@ |
dfbdccdb | 3279 | %q4. %3,%2,%1 |
52d3af72 DE |
3280 | #" |
3281 | [(set_attr "type" "compare") | |
3282 | (set_attr "length" "4,8")]) | |
3283 | ||
3284 | (define_split | |
3285 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 3286 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3287 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
3288 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 3289 | (const_int 0))) |
52d3af72 | 3290 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 3291 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3292 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
3293 | (set (match_dup 0) |
3294 | (compare:CC (match_dup 3) | |
3295 | (const_int 0)))] | |
3296 | "") | |
1fd4e8c1 | 3297 | |
dfbdccdb | 3298 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 3299 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
3300 | (compare:CC (match_operator:SI 4 "boolean_operator" |
3301 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
3302 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
3303 | (const_int 0))) | |
52d3af72 | 3304 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 3305 | (match_dup 4))] |
0ad91047 | 3306 | "! TARGET_POWERPC64" |
52d3af72 | 3307 | "@ |
dfbdccdb | 3308 | %q4. %0,%2,%1 |
52d3af72 DE |
3309 | #" |
3310 | [(set_attr "type" "compare") | |
3311 | (set_attr "length" "4,8")]) | |
3312 | ||
3313 | (define_split | |
e72247f4 | 3314 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 3315 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3316 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
3317 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 3318 | (const_int 0))) |
75540af0 | 3319 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 3320 | (match_dup 4))] |
0ad91047 | 3321 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3322 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
3323 | (set (match_dup 3) |
3324 | (compare:CC (match_dup 0) | |
3325 | (const_int 0)))] | |
3326 | "") | |
3327 | ||
dfbdccdb | 3328 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 3329 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
3330 | (match_operator:SI 3 "boolean_operator" |
3331 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 3332 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] |
1fd4e8c1 | 3333 | "" |
dfbdccdb | 3334 | "%q3 %0,%1,%2") |
1fd4e8c1 | 3335 | |
dfbdccdb | 3336 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 3337 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
3338 | (compare:CC (match_operator:SI 4 "boolean_operator" |
3339 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
3340 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
3341 | (const_int 0))) | |
52d3af72 | 3342 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3343 | "! TARGET_POWERPC64" |
52d3af72 | 3344 | "@ |
dfbdccdb | 3345 | %q4. %3,%1,%2 |
52d3af72 DE |
3346 | #" |
3347 | [(set_attr "type" "compare") | |
3348 | (set_attr "length" "4,8")]) | |
3349 | ||
3350 | (define_split | |
3351 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 3352 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3353 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
3354 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 3355 | (const_int 0))) |
52d3af72 | 3356 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 3357 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3358 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
3359 | (set (match_dup 0) |
3360 | (compare:CC (match_dup 3) | |
3361 | (const_int 0)))] | |
3362 | "") | |
1fd4e8c1 | 3363 | |
dfbdccdb | 3364 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 3365 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
3366 | (compare:CC (match_operator:SI 4 "boolean_operator" |
3367 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
3368 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
3369 | (const_int 0))) | |
52d3af72 | 3370 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 3371 | (match_dup 4))] |
0ad91047 | 3372 | "! TARGET_POWERPC64" |
52d3af72 | 3373 | "@ |
dfbdccdb | 3374 | %q4. %0,%1,%2 |
52d3af72 DE |
3375 | #" |
3376 | [(set_attr "type" "compare") | |
3377 | (set_attr "length" "4,8")]) | |
3378 | ||
3379 | (define_split | |
e72247f4 | 3380 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 3381 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
3382 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
3383 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 3384 | (const_int 0))) |
75540af0 | 3385 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 3386 | (match_dup 4))] |
0ad91047 | 3387 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 3388 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
3389 | (set (match_dup 3) |
3390 | (compare:CC (match_dup 0) | |
3391 | (const_int 0)))] | |
3392 | "") | |
1fd4e8c1 RK |
3393 | |
3394 | ;; maskir insn. We need four forms because things might be in arbitrary | |
3395 | ;; orders. Don't define forms that only set CR fields because these | |
3396 | ;; would modify an input register. | |
3397 | ||
7cd5235b | 3398 | (define_insn "*maskir_internal1" |
cd2b37d9 | 3399 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
3400 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
3401 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
3402 | (and:SI (match_dup 2) | |
cd2b37d9 | 3403 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 3404 | "TARGET_POWER" |
01def764 | 3405 | "maskir %0,%3,%2") |
1fd4e8c1 | 3406 | |
7cd5235b | 3407 | (define_insn "*maskir_internal2" |
242e8072 | 3408 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
3409 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
3410 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 3411 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 3412 | (match_dup 2))))] |
ca7f5001 | 3413 | "TARGET_POWER" |
01def764 | 3414 | "maskir %0,%3,%2") |
1fd4e8c1 | 3415 | |
7cd5235b | 3416 | (define_insn "*maskir_internal3" |
cd2b37d9 | 3417 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 3418 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 3419 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
3420 | (and:SI (not:SI (match_dup 2)) |
3421 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 3422 | "TARGET_POWER" |
01def764 | 3423 | "maskir %0,%3,%2") |
1fd4e8c1 | 3424 | |
7cd5235b | 3425 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
3426 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3427 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
3428 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
3429 | (and:SI (not:SI (match_dup 2)) | |
3430 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 3431 | "TARGET_POWER" |
01def764 | 3432 | "maskir %0,%3,%2") |
1fd4e8c1 | 3433 | |
7cd5235b | 3434 | (define_insn "*maskir_internal5" |
9ebbca7d | 3435 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3436 | (compare:CC |
9ebbca7d GK |
3437 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
3438 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 3439 | (and:SI (match_dup 2) |
9ebbca7d | 3440 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 3441 | (const_int 0))) |
9ebbca7d | 3442 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3443 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
3444 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 3445 | "TARGET_POWER" |
9ebbca7d GK |
3446 | "@ |
3447 | maskir. %0,%3,%2 | |
3448 | #" | |
3449 | [(set_attr "type" "compare") | |
3450 | (set_attr "length" "4,8")]) | |
3451 | ||
3452 | (define_split | |
3453 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3454 | (compare:CC | |
3455 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
3456 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
3457 | (and:SI (match_dup 2) | |
3458 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
3459 | (const_int 0))) | |
3460 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3461 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3462 | (and:SI (match_dup 2) (match_dup 3))))] | |
3463 | "TARGET_POWER && reload_completed" | |
3464 | [(set (match_dup 0) | |
3465 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3466 | (and:SI (match_dup 2) (match_dup 3)))) | |
3467 | (set (match_dup 4) | |
3468 | (compare:CC (match_dup 0) | |
3469 | (const_int 0)))] | |
3470 | "") | |
1fd4e8c1 | 3471 | |
7cd5235b | 3472 | (define_insn "*maskir_internal6" |
9ebbca7d | 3473 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3474 | (compare:CC |
9ebbca7d GK |
3475 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
3476 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
3477 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 3478 | (match_dup 2))) |
1fd4e8c1 | 3479 | (const_int 0))) |
9ebbca7d | 3480 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3481 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
3482 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 3483 | "TARGET_POWER" |
9ebbca7d GK |
3484 | "@ |
3485 | maskir. %0,%3,%2 | |
3486 | #" | |
3487 | [(set_attr "type" "compare") | |
3488 | (set_attr "length" "4,8")]) | |
3489 | ||
3490 | (define_split | |
3491 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3492 | (compare:CC | |
3493 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
3494 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
3495 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3496 | (match_dup 2))) | |
3497 | (const_int 0))) | |
3498 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3499 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3500 | (and:SI (match_dup 3) (match_dup 2))))] | |
3501 | "TARGET_POWER && reload_completed" | |
3502 | [(set (match_dup 0) | |
3503 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3504 | (and:SI (match_dup 3) (match_dup 2)))) | |
3505 | (set (match_dup 4) | |
3506 | (compare:CC (match_dup 0) | |
3507 | (const_int 0)))] | |
3508 | "") | |
1fd4e8c1 | 3509 | |
7cd5235b | 3510 | (define_insn "*maskir_internal7" |
9ebbca7d | 3511 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 3512 | (compare:CC |
9ebbca7d GK |
3513 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
3514 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 3515 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3516 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 3517 | (const_int 0))) |
9ebbca7d | 3518 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
3519 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
3520 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3521 | "TARGET_POWER" | |
9ebbca7d GK |
3522 | "@ |
3523 | maskir. %0,%3,%2 | |
3524 | #" | |
3525 | [(set_attr "type" "compare") | |
3526 | (set_attr "length" "4,8")]) | |
3527 | ||
3528 | (define_split | |
3529 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3530 | (compare:CC | |
3531 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
3532 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
3533 | (and:SI (not:SI (match_dup 2)) | |
3534 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3535 | (const_int 0))) | |
3536 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3537 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3538 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3539 | "TARGET_POWER && reload_completed" | |
3540 | [(set (match_dup 0) | |
3541 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3542 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3543 | (set (match_dup 4) | |
3544 | (compare:CC (match_dup 0) | |
3545 | (const_int 0)))] | |
3546 | "") | |
1fd4e8c1 | 3547 | |
7cd5235b | 3548 | (define_insn "*maskir_internal8" |
9ebbca7d | 3549 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3550 | (compare:CC |
9ebbca7d GK |
3551 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
3552 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 3553 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3554 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 3555 | (const_int 0))) |
9ebbca7d | 3556 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3557 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
3558 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 3559 | "TARGET_POWER" |
9ebbca7d GK |
3560 | "@ |
3561 | maskir. %0,%3,%2 | |
3562 | #" | |
3563 | [(set_attr "type" "compare") | |
3564 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 3565 | \f |
9ebbca7d GK |
3566 | (define_split |
3567 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3568 | (compare:CC | |
3569 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3570 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
3571 | (and:SI (not:SI (match_dup 2)) | |
3572 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3573 | (const_int 0))) | |
3574 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3575 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3576 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3577 | "TARGET_POWER && reload_completed" | |
3578 | [(set (match_dup 0) | |
3579 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3580 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3581 | (set (match_dup 4) | |
3582 | (compare:CC (match_dup 0) | |
3583 | (const_int 0)))] | |
3584 | "") | |
3585 | ||
1fd4e8c1 RK |
3586 | ;; Rotate and shift insns, in all their variants. These support shifts, |
3587 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 3588 | (define_expand "insv" |
0ad91047 DE |
3589 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
3590 | (match_operand:SI 1 "const_int_operand" "") | |
3591 | (match_operand:SI 2 "const_int_operand" "")) | |
3592 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
3593 | "" |
3594 | " | |
3595 | { | |
3596 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3597 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3598 | compiler if the address of the structure is taken later. */ | |
3599 | if (GET_CODE (operands[0]) == SUBREG | |
3600 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3601 | FAIL; | |
a78e33fc DE |
3602 | |
3603 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
3604 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
3605 | else | |
3606 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
3607 | DONE; | |
034c1be0 MM |
3608 | }") |
3609 | ||
a78e33fc | 3610 | (define_insn "insvsi" |
cd2b37d9 | 3611 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
3612 | (match_operand:SI 1 "const_int_operand" "i") |
3613 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 3614 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
3615 | "" |
3616 | "* | |
3617 | { | |
3618 | int start = INTVAL (operands[2]) & 31; | |
3619 | int size = INTVAL (operands[1]) & 31; | |
3620 | ||
89e9f3a8 MM |
3621 | operands[4] = GEN_INT (32 - start - size); |
3622 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3623 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
1fd4e8c1 RK |
3624 | }") |
3625 | ||
a78e33fc | 3626 | (define_insn "*insvsi_internal1" |
d56d506a RK |
3627 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3628 | (match_operand:SI 1 "const_int_operand" "i") | |
3629 | (match_operand:SI 2 "const_int_operand" "i")) | |
3630 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3631 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3632 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3633 | "* |
3634 | { | |
3635 | int shift = INTVAL (operands[4]) & 31; | |
3636 | int start = INTVAL (operands[2]) & 31; | |
3637 | int size = INTVAL (operands[1]) & 31; | |
3638 | ||
89e9f3a8 MM |
3639 | operands[4] = GEN_INT (shift - start - size); |
3640 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3641 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3642 | }") |
3643 | ||
a78e33fc | 3644 | (define_insn "*insvsi_internal2" |
d56d506a RK |
3645 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3646 | (match_operand:SI 1 "const_int_operand" "i") | |
3647 | (match_operand:SI 2 "const_int_operand" "i")) | |
3648 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3649 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3650 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3651 | "* |
3652 | { | |
3653 | int shift = INTVAL (operands[4]) & 31; | |
3654 | int start = INTVAL (operands[2]) & 31; | |
3655 | int size = INTVAL (operands[1]) & 31; | |
3656 | ||
89e9f3a8 MM |
3657 | operands[4] = GEN_INT (32 - shift - start - size); |
3658 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3659 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3660 | }") |
3661 | ||
a78e33fc | 3662 | (define_insn "*insvsi_internal3" |
d56d506a RK |
3663 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3664 | (match_operand:SI 1 "const_int_operand" "i") | |
3665 | (match_operand:SI 2 "const_int_operand" "i")) | |
3666 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3667 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 3668 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3669 | "* |
3670 | { | |
3671 | int shift = INTVAL (operands[4]) & 31; | |
3672 | int start = INTVAL (operands[2]) & 31; | |
3673 | int size = INTVAL (operands[1]) & 31; | |
3674 | ||
89e9f3a8 MM |
3675 | operands[4] = GEN_INT (32 - shift - start - size); |
3676 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3677 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3678 | }") |
3679 | ||
a78e33fc | 3680 | (define_insn "*insvsi_internal4" |
d56d506a RK |
3681 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3682 | (match_operand:SI 1 "const_int_operand" "i") | |
3683 | (match_operand:SI 2 "const_int_operand" "i")) | |
3684 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3685 | (match_operand:SI 4 "const_int_operand" "i") | |
3686 | (match_operand:SI 5 "const_int_operand" "i")))] | |
3687 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
3688 | "* | |
3689 | { | |
3690 | int extract_start = INTVAL (operands[5]) & 31; | |
3691 | int extract_size = INTVAL (operands[4]) & 31; | |
3692 | int insert_start = INTVAL (operands[2]) & 31; | |
3693 | int insert_size = INTVAL (operands[1]) & 31; | |
3694 | ||
3695 | /* Align extract field with insert field */ | |
3a598fbe | 3696 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 3697 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 3698 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
d56d506a RK |
3699 | }") |
3700 | ||
a78e33fc | 3701 | (define_insn "insvdi" |
685f3906 | 3702 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3703 | (match_operand:SI 1 "const_int_operand" "i") |
3704 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3705 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3706 | "TARGET_POWERPC64" | |
3707 | "* | |
3708 | { | |
3709 | int start = INTVAL (operands[2]) & 63; | |
3710 | int size = INTVAL (operands[1]) & 63; | |
3711 | ||
a78e33fc DE |
3712 | operands[1] = GEN_INT (64 - start - size); |
3713 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3714 | }") |
3715 | ||
034c1be0 | 3716 | (define_expand "extzv" |
0ad91047 DE |
3717 | [(set (match_operand 0 "gpc_reg_operand" "") |
3718 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3719 | (match_operand:SI 2 "const_int_operand" "") | |
3720 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3721 | "" |
3722 | " | |
3723 | { | |
3724 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3725 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3726 | compiler if the address of the structure is taken later. */ | |
3727 | if (GET_CODE (operands[0]) == SUBREG | |
3728 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3729 | FAIL; | |
a78e33fc DE |
3730 | |
3731 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3732 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3733 | else | |
3734 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3735 | DONE; | |
034c1be0 MM |
3736 | }") |
3737 | ||
a78e33fc | 3738 | (define_insn "extzvsi" |
cd2b37d9 RK |
3739 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3740 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3741 | (match_operand:SI 2 "const_int_operand" "i") |
3742 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3743 | "" | |
3744 | "* | |
3745 | { | |
3746 | int start = INTVAL (operands[3]) & 31; | |
3747 | int size = INTVAL (operands[2]) & 31; | |
3748 | ||
3749 | if (start + size >= 32) | |
3750 | operands[3] = const0_rtx; | |
3751 | else | |
89e9f3a8 | 3752 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3753 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3754 | }") |
3755 | ||
a78e33fc | 3756 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3757 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3758 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3759 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3760 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3761 | (const_int 0))) |
9ebbca7d | 3762 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3763 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
3764 | "* |
3765 | { | |
3766 | int start = INTVAL (operands[3]) & 31; | |
3767 | int size = INTVAL (operands[2]) & 31; | |
3768 | ||
9ebbca7d GK |
3769 | /* Force split for non-cc0 compare. */ |
3770 | if (which_alternative == 1) | |
3771 | return \"#\"; | |
3772 | ||
a7a975e1 RK |
3773 | /* If the bitfield being tested fits in the upper or lower half of a |
3774 | word, it is possible to use andiu. or andil. to test it. This is | |
3775 | useful because the condition register set-use delay is smaller for | |
3776 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3777 | position is 0 because the LT and GT bits may be set wrong. */ | |
3778 | ||
3779 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3780 | { |
3a598fbe | 3781 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3782 | - (1 << (16 - (start & 15) - size)))); |
3783 | if (start < 16) | |
ca7f5001 | 3784 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3785 | else |
ca7f5001 | 3786 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3787 | } |
7e69e155 | 3788 | |
1fd4e8c1 RK |
3789 | if (start + size >= 32) |
3790 | operands[3] = const0_rtx; | |
3791 | else | |
89e9f3a8 | 3792 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3793 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3794 | }" |
9ebbca7d GK |
3795 | [(set_attr "type" "compare") |
3796 | (set_attr "length" "4,8")]) | |
3797 | ||
3798 | (define_split | |
3799 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3800 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3801 | (match_operand:SI 2 "const_int_operand" "") | |
3802 | (match_operand:SI 3 "const_int_operand" "")) | |
3803 | (const_int 0))) | |
3804 | (clobber (match_scratch:SI 4 ""))] | |
3805 | "! TARGET_POWERPC64 && reload_completed" | |
3806 | [(set (match_dup 4) | |
3807 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3808 | (match_dup 3))) | |
3809 | (set (match_dup 0) | |
3810 | (compare:CC (match_dup 4) | |
3811 | (const_int 0)))] | |
3812 | "") | |
1fd4e8c1 | 3813 | |
a78e33fc | 3814 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3815 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3816 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3817 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3818 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3819 | (const_int 0))) |
9ebbca7d | 3820 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3821 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
0ad91047 | 3822 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
3823 | "* |
3824 | { | |
3825 | int start = INTVAL (operands[3]) & 31; | |
3826 | int size = INTVAL (operands[2]) & 31; | |
3827 | ||
9ebbca7d GK |
3828 | /* Force split for non-cc0 compare. */ |
3829 | if (which_alternative == 1) | |
3830 | return \"#\"; | |
3831 | ||
a7a975e1 | 3832 | if (start >= 16 && start + size == 32) |
df031c43 | 3833 | { |
89e9f3a8 | 3834 | operands[3] = GEN_INT ((1 << (32 - start)) - 1); |
ca7f5001 | 3835 | return \"{andil.|andi.} %0,%1,%3\"; |
df031c43 | 3836 | } |
7e69e155 | 3837 | |
1fd4e8c1 RK |
3838 | if (start + size >= 32) |
3839 | operands[3] = const0_rtx; | |
3840 | else | |
89e9f3a8 | 3841 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3842 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3843 | }" |
9ebbca7d GK |
3844 | [(set_attr "type" "delayed_compare") |
3845 | (set_attr "length" "4,8")]) | |
3846 | ||
3847 | (define_split | |
3848 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3849 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3850 | (match_operand:SI 2 "const_int_operand" "") | |
3851 | (match_operand:SI 3 "const_int_operand" "")) | |
3852 | (const_int 0))) | |
3853 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3854 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
3855 | "! TARGET_POWERPC64 && reload_completed" | |
3856 | [(set (match_dup 0) | |
3857 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3858 | (set (match_dup 4) | |
3859 | (compare:CC (match_dup 0) | |
3860 | (const_int 0)))] | |
3861 | "") | |
1fd4e8c1 | 3862 | |
a78e33fc | 3863 | (define_insn "extzvdi" |
685f3906 DE |
3864 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3865 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3866 | (match_operand:SI 2 "const_int_operand" "i") |
3867 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3868 | "TARGET_POWERPC64" |
3869 | "* | |
3870 | { | |
3871 | int start = INTVAL (operands[3]) & 63; | |
3872 | int size = INTVAL (operands[2]) & 63; | |
3873 | ||
3874 | if (start + size >= 64) | |
3875 | operands[3] = const0_rtx; | |
3876 | else | |
89e9f3a8 MM |
3877 | operands[3] = GEN_INT (start + size); |
3878 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3879 | return \"rldicl %0,%1,%3,%2\"; |
3880 | }") | |
3881 | ||
a78e33fc | 3882 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3883 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3884 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3885 | (match_operand:SI 2 "const_int_operand" "i") |
3886 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3887 | (const_int 0))) |
29ae5b89 | 3888 | (clobber (match_scratch:DI 4 "=r"))] |
685f3906 DE |
3889 | "TARGET_POWERPC64" |
3890 | "* | |
3891 | { | |
3892 | int start = INTVAL (operands[3]) & 63; | |
3893 | int size = INTVAL (operands[2]) & 63; | |
3894 | ||
3895 | if (start + size >= 64) | |
3896 | operands[3] = const0_rtx; | |
3897 | else | |
89e9f3a8 MM |
3898 | operands[3] = GEN_INT (start + size); |
3899 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3900 | return \"rldicl. %4,%1,%3,%2\"; |
3901 | }") | |
3902 | ||
a78e33fc | 3903 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3904 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3905 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3906 | (match_operand:SI 2 "const_int_operand" "i") |
3907 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3908 | (const_int 0))) |
29ae5b89 | 3909 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 DE |
3910 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
3911 | "TARGET_POWERPC64" | |
3912 | "* | |
3913 | { | |
3914 | int start = INTVAL (operands[3]) & 63; | |
3915 | int size = INTVAL (operands[2]) & 63; | |
3916 | ||
3917 | if (start + size >= 64) | |
3918 | operands[3] = const0_rtx; | |
3919 | else | |
89e9f3a8 MM |
3920 | operands[3] = GEN_INT (start + size); |
3921 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3922 | return \"rldicl. %0,%1,%3,%2\"; |
3923 | }") | |
3924 | ||
1fd4e8c1 | 3925 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3926 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3927 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3928 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3929 | "" | |
ca7f5001 | 3930 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3931 | |
a260abc9 | 3932 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3933 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3934 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3935 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3936 | (const_int 0))) |
9ebbca7d | 3937 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3938 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3939 | "@ |
3940 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3941 | #" | |
3942 | [(set_attr "type" "delayed_compare") | |
3943 | (set_attr "length" "4,8")]) | |
3944 | ||
3945 | (define_split | |
3946 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3947 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3948 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3949 | (const_int 0))) | |
3950 | (clobber (match_scratch:SI 3 ""))] | |
3951 | "! TARGET_POWERPC64 && reload_completed" | |
3952 | [(set (match_dup 3) | |
3953 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3954 | (set (match_dup 0) | |
3955 | (compare:CC (match_dup 3) | |
3956 | (const_int 0)))] | |
3957 | "") | |
1fd4e8c1 | 3958 | |
a260abc9 | 3959 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3960 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3961 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3962 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3963 | (const_int 0))) |
9ebbca7d | 3964 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3965 | (rotate:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3966 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3967 | "@ |
3968 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3969 | #" | |
3970 | [(set_attr "type" "delayed_compare") | |
3971 | (set_attr "length" "4,8")]) | |
3972 | ||
3973 | (define_split | |
3974 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3975 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3976 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3977 | (const_int 0))) | |
3978 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3979 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
3980 | "! TARGET_POWERPC64 && reload_completed" | |
3981 | [(set (match_dup 0) | |
3982 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3983 | (set (match_dup 3) | |
3984 | (compare:CC (match_dup 0) | |
3985 | (const_int 0)))] | |
3986 | "") | |
1fd4e8c1 | 3987 | |
a260abc9 | 3988 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3989 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3990 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3991 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
9615f239 | 3992 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 3993 | "" |
ca7f5001 | 3994 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3995 | |
a260abc9 | 3996 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3997 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3998 | (compare:CC (and:SI |
9ebbca7d GK |
3999 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4000 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
4001 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4002 | (const_int 0))) |
9ebbca7d | 4003 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 4004 | "! TARGET_POWERPC64" |
9ebbca7d GK |
4005 | "@ |
4006 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
4007 | #" | |
4008 | [(set_attr "type" "delayed_compare") | |
4009 | (set_attr "length" "4,8")]) | |
4010 | ||
4011 | (define_split | |
4012 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4013 | (compare:CC (and:SI | |
4014 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4015 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4016 | (match_operand:SI 3 "mask_operand" "")) | |
4017 | (const_int 0))) | |
4018 | (clobber (match_scratch:SI 4 ""))] | |
4019 | "! TARGET_POWERPC64 && reload_completed" | |
4020 | [(set (match_dup 4) | |
4021 | (and:SI (rotate:SI (match_dup 1) | |
4022 | (match_dup 2)) | |
4023 | (match_dup 3))) | |
4024 | (set (match_dup 0) | |
4025 | (compare:CC (match_dup 4) | |
4026 | (const_int 0)))] | |
4027 | "") | |
1fd4e8c1 | 4028 | |
a260abc9 | 4029 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 4030 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4031 | (compare:CC (and:SI |
9ebbca7d GK |
4032 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4033 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
4034 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4035 | (const_int 0))) |
9ebbca7d | 4036 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4037 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 4038 | "! TARGET_POWERPC64" |
9ebbca7d GK |
4039 | "@ |
4040 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
4041 | #" | |
4042 | [(set_attr "type" "delayed_compare") | |
4043 | (set_attr "length" "4,8")]) | |
4044 | ||
4045 | (define_split | |
4046 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4047 | (compare:CC (and:SI | |
4048 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4049 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4050 | (match_operand:SI 3 "mask_operand" "")) | |
4051 | (const_int 0))) | |
4052 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4053 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4054 | "! TARGET_POWERPC64 && reload_completed" | |
4055 | [(set (match_dup 0) | |
4056 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4057 | (set (match_dup 4) | |
4058 | (compare:CC (match_dup 0) | |
4059 | (const_int 0)))] | |
4060 | "") | |
1fd4e8c1 | 4061 | |
a260abc9 | 4062 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 4063 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4064 | (zero_extend:SI |
4065 | (subreg:QI | |
cd2b37d9 | 4066 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
4067 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
4068 | "" | |
ca7f5001 | 4069 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 4070 | |
a260abc9 | 4071 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 4072 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4073 | (compare:CC (zero_extend:SI |
4074 | (subreg:QI | |
9ebbca7d GK |
4075 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4076 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 4077 | (const_int 0))) |
9ebbca7d | 4078 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 4079 | "" |
9ebbca7d GK |
4080 | "@ |
4081 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
4082 | #" | |
4083 | [(set_attr "type" "delayed_compare") | |
4084 | (set_attr "length" "4,8")]) | |
4085 | ||
4086 | (define_split | |
4087 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4088 | (compare:CC (zero_extend:SI | |
4089 | (subreg:QI | |
4090 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4091 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
4092 | (const_int 0))) | |
4093 | (clobber (match_scratch:SI 3 ""))] | |
4094 | "reload_completed" | |
4095 | [(set (match_dup 3) | |
4096 | (zero_extend:SI (subreg:QI | |
4097 | (rotate:SI (match_dup 1) | |
4098 | (match_dup 2)) 0))) | |
4099 | (set (match_dup 0) | |
4100 | (compare:CC (match_dup 3) | |
4101 | (const_int 0)))] | |
4102 | "") | |
1fd4e8c1 | 4103 | |
a260abc9 | 4104 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 4105 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4106 | (compare:CC (zero_extend:SI |
4107 | (subreg:QI | |
9ebbca7d GK |
4108 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4109 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 4110 | (const_int 0))) |
9ebbca7d | 4111 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
4112 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
4113 | "" | |
9ebbca7d GK |
4114 | "@ |
4115 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
4116 | #" | |
4117 | [(set_attr "type" "delayed_compare") | |
4118 | (set_attr "length" "4,8")]) | |
4119 | ||
4120 | (define_split | |
4121 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4122 | (compare:CC (zero_extend:SI | |
4123 | (subreg:QI | |
4124 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4125 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
4126 | (const_int 0))) | |
4127 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4128 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
4129 | "reload_completed" | |
4130 | [(set (match_dup 0) | |
4131 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
4132 | (set (match_dup 3) | |
4133 | (compare:CC (match_dup 0) | |
4134 | (const_int 0)))] | |
4135 | "") | |
1fd4e8c1 | 4136 | |
a260abc9 | 4137 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 4138 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4139 | (zero_extend:SI |
4140 | (subreg:HI | |
cd2b37d9 | 4141 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
4142 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
4143 | "" | |
ca7f5001 | 4144 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 4145 | |
a260abc9 | 4146 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 4147 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4148 | (compare:CC (zero_extend:SI |
4149 | (subreg:HI | |
9ebbca7d GK |
4150 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4151 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 4152 | (const_int 0))) |
9ebbca7d | 4153 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 4154 | "" |
9ebbca7d GK |
4155 | "@ |
4156 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
4157 | #" | |
4158 | [(set_attr "type" "delayed_compare") | |
4159 | (set_attr "length" "4,8")]) | |
4160 | ||
4161 | (define_split | |
4162 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4163 | (compare:CC (zero_extend:SI | |
4164 | (subreg:HI | |
4165 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4166 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
4167 | (const_int 0))) | |
4168 | (clobber (match_scratch:SI 3 ""))] | |
4169 | "reload_completed" | |
4170 | [(set (match_dup 3) | |
4171 | (zero_extend:SI (subreg:HI | |
4172 | (rotate:SI (match_dup 1) | |
4173 | (match_dup 2)) 0))) | |
4174 | (set (match_dup 0) | |
4175 | (compare:CC (match_dup 3) | |
4176 | (const_int 0)))] | |
4177 | "") | |
1fd4e8c1 | 4178 | |
a260abc9 | 4179 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 4180 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4181 | (compare:CC (zero_extend:SI |
4182 | (subreg:HI | |
9ebbca7d GK |
4183 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4184 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 4185 | (const_int 0))) |
9ebbca7d | 4186 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
4187 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
4188 | "" | |
9ebbca7d GK |
4189 | "@ |
4190 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
4191 | #" | |
4192 | [(set_attr "type" "delayed_compare") | |
4193 | (set_attr "length" "4,8")]) | |
4194 | ||
4195 | (define_split | |
4196 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4197 | (compare:CC (zero_extend:SI | |
4198 | (subreg:HI | |
4199 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4200 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
4201 | (const_int 0))) | |
4202 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4203 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
4204 | "reload_completed" | |
4205 | [(set (match_dup 0) | |
4206 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
4207 | (set (match_dup 3) | |
4208 | (compare:CC (match_dup 0) | |
4209 | (const_int 0)))] | |
4210 | "") | |
1fd4e8c1 RK |
4211 | |
4212 | ;; Note that we use "sle." instead of "sl." so that we can set | |
4213 | ;; SHIFT_COUNT_TRUNCATED. | |
4214 | ||
ca7f5001 RK |
4215 | (define_expand "ashlsi3" |
4216 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
4217 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
4218 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
4219 | "" | |
4220 | " | |
4221 | { | |
4222 | if (TARGET_POWER) | |
4223 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
4224 | else | |
25c341fa | 4225 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4226 | DONE; |
4227 | }") | |
4228 | ||
4229 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
4230 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4231 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4232 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4233 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4234 | "TARGET_POWER" |
1fd4e8c1 RK |
4235 | "@ |
4236 | sle %0,%1,%2 | |
9ebbca7d | 4237 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 4238 | |
25c341fa | 4239 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
4240 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4241 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4242 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4243 | "! TARGET_POWER" |
9ebbca7d | 4244 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4245 | |
4246 | (define_insn "" | |
9ebbca7d GK |
4247 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4248 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4249 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4250 | (const_int 0))) |
9ebbca7d GK |
4251 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4252 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4253 | "TARGET_POWER" |
1fd4e8c1 RK |
4254 | "@ |
4255 | sle. %3,%1,%2 | |
9ebbca7d GK |
4256 | {sli.|slwi.} %3,%1,%h2 |
4257 | # | |
4258 | #" | |
4259 | [(set_attr "type" "delayed_compare") | |
4260 | (set_attr "length" "4,4,8,8")]) | |
4261 | ||
4262 | (define_split | |
4263 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4264 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4265 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4266 | (const_int 0))) | |
4267 | (clobber (match_scratch:SI 3 "")) | |
4268 | (clobber (match_scratch:SI 4 ""))] | |
4269 | "TARGET_POWER && reload_completed" | |
4270 | [(parallel [(set (match_dup 3) | |
4271 | (ashift:SI (match_dup 1) (match_dup 2))) | |
4272 | (clobber (match_dup 4))]) | |
4273 | (set (match_dup 0) | |
4274 | (compare:CC (match_dup 3) | |
4275 | (const_int 0)))] | |
4276 | "") | |
25c341fa | 4277 | |
ca7f5001 | 4278 | (define_insn "" |
9ebbca7d GK |
4279 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4280 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4281 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4282 | (const_int 0))) |
9ebbca7d | 4283 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 4284 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
4285 | "@ |
4286 | {sl|slw}%I2. %3,%1,%h2 | |
4287 | #" | |
4288 | [(set_attr "type" "delayed_compare") | |
4289 | (set_attr "length" "4,8")]) | |
4290 | ||
4291 | (define_split | |
4292 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4293 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4294 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4295 | (const_int 0))) | |
4296 | (clobber (match_scratch:SI 3 ""))] | |
4297 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4298 | [(set (match_dup 3) | |
4299 | (ashift:SI (match_dup 1) (match_dup 2))) | |
4300 | (set (match_dup 0) | |
4301 | (compare:CC (match_dup 3) | |
4302 | (const_int 0)))] | |
4303 | "") | |
1fd4e8c1 RK |
4304 | |
4305 | (define_insn "" | |
9ebbca7d GK |
4306 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4307 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4308 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4309 | (const_int 0))) |
9ebbca7d | 4310 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4311 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4312 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4313 | "TARGET_POWER" |
1fd4e8c1 RK |
4314 | "@ |
4315 | sle. %0,%1,%2 | |
9ebbca7d GK |
4316 | {sli.|slwi.} %0,%1,%h2 |
4317 | # | |
4318 | #" | |
4319 | [(set_attr "type" "delayed_compare") | |
4320 | (set_attr "length" "4,4,8,8")]) | |
4321 | ||
4322 | (define_split | |
4323 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4324 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4325 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4326 | (const_int 0))) | |
4327 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4328 | (ashift:SI (match_dup 1) (match_dup 2))) | |
4329 | (clobber (match_scratch:SI 4 ""))] | |
4330 | "TARGET_POWER && reload_completed" | |
4331 | [(parallel [(set (match_dup 0) | |
4332 | (ashift:SI (match_dup 1) (match_dup 2))) | |
4333 | (clobber (match_dup 4))]) | |
4334 | (set (match_dup 3) | |
4335 | (compare:CC (match_dup 0) | |
4336 | (const_int 0)))] | |
4337 | "") | |
25c341fa | 4338 | |
ca7f5001 | 4339 | (define_insn "" |
9ebbca7d GK |
4340 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4341 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4342 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4343 | (const_int 0))) |
9ebbca7d | 4344 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4345 | (ashift:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 4346 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
4347 | "@ |
4348 | {sl|slw}%I2. %0,%1,%h2 | |
4349 | #" | |
4350 | [(set_attr "type" "delayed_compare") | |
4351 | (set_attr "length" "4,8")]) | |
4352 | ||
4353 | (define_split | |
4354 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4355 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4356 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4357 | (const_int 0))) | |
4358 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4359 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
4360 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4361 | [(set (match_dup 0) | |
4362 | (ashift:SI (match_dup 1) (match_dup 2))) | |
4363 | (set (match_dup 3) | |
4364 | (compare:CC (match_dup 0) | |
4365 | (const_int 0)))] | |
4366 | "") | |
1fd4e8c1 RK |
4367 | |
4368 | (define_insn "" | |
cd2b37d9 RK |
4369 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4370 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4371 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 4372 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 4373 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 4374 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
4375 | |
4376 | (define_insn "" | |
9ebbca7d | 4377 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4378 | (compare:CC |
9ebbca7d GK |
4379 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4380 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4381 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4382 | (const_int 0))) |
9ebbca7d | 4383 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 4384 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4385 | "@ |
4386 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
4387 | #" | |
4388 | [(set_attr "type" "delayed_compare") | |
4389 | (set_attr "length" "4,8")]) | |
4390 | ||
4391 | (define_split | |
4392 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4393 | (compare:CC | |
4394 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4395 | (match_operand:SI 2 "const_int_operand" "")) | |
4396 | (match_operand:SI 3 "mask_operand" "")) | |
4397 | (const_int 0))) | |
4398 | (clobber (match_scratch:SI 4 ""))] | |
4399 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" | |
4400 | [(set (match_dup 4) | |
4401 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
4402 | (match_dup 3))) | |
4403 | (set (match_dup 0) | |
4404 | (compare:CC (match_dup 4) | |
4405 | (const_int 0)))] | |
4406 | "") | |
1fd4e8c1 RK |
4407 | |
4408 | (define_insn "" | |
9ebbca7d | 4409 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4410 | (compare:CC |
9ebbca7d GK |
4411 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4412 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4413 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4414 | (const_int 0))) |
9ebbca7d | 4415 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4416 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 4417 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4418 | "@ |
4419 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
4420 | #" | |
4421 | [(set_attr "type" "delayed_compare") | |
4422 | (set_attr "length" "4,8")]) | |
4423 | ||
4424 | (define_split | |
4425 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4426 | (compare:CC | |
4427 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4428 | (match_operand:SI 2 "const_int_operand" "")) | |
4429 | (match_operand:SI 3 "mask_operand" "")) | |
4430 | (const_int 0))) | |
4431 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4432 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4433 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" | |
4434 | [(set (match_dup 0) | |
4435 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4436 | (set (match_dup 4) | |
4437 | (compare:CC (match_dup 0) | |
4438 | (const_int 0)))] | |
4439 | "") | |
1fd4e8c1 | 4440 | |
ca7f5001 | 4441 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 4442 | ;; "sli x,x,0". |
ca7f5001 RK |
4443 | (define_expand "lshrsi3" |
4444 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
4445 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
4446 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
4447 | "" | |
4448 | " | |
4449 | { | |
4450 | if (TARGET_POWER) | |
4451 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
4452 | else | |
25c341fa | 4453 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4454 | DONE; |
4455 | }") | |
4456 | ||
4457 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
4458 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
4459 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
4460 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
4461 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 4462 | "TARGET_POWER" |
1fd4e8c1 RK |
4463 | "@ |
4464 | sre %0,%1,%2 | |
bdf423cb | 4465 | mr %0,%1 |
ca7f5001 RK |
4466 | {s%A2i|s%A2wi} %0,%1,%h2") |
4467 | ||
25c341fa | 4468 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
4469 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4470 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4471 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 4472 | "! TARGET_POWER" |
bdf423cb MM |
4473 | "@ |
4474 | mr %0,%1 | |
4475 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
4476 | |
4477 | (define_insn "" | |
9ebbca7d GK |
4478 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
4479 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4480 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4481 | (const_int 0))) |
9ebbca7d GK |
4482 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
4483 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 4484 | "TARGET_POWER" |
1fd4e8c1 | 4485 | "@ |
29ae5b89 JL |
4486 | sre. %3,%1,%2 |
4487 | mr. %1,%1 | |
9ebbca7d GK |
4488 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
4489 | # | |
4490 | # | |
4491 | #" | |
4492 | [(set_attr "type" "delayed_compare") | |
4493 | (set_attr "length" "4,4,4,8,8,8")]) | |
4494 | ||
4495 | (define_split | |
4496 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4497 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4498 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4499 | (const_int 0))) | |
4500 | (clobber (match_scratch:SI 3 "")) | |
4501 | (clobber (match_scratch:SI 4 ""))] | |
4502 | "TARGET_POWER && reload_completed" | |
4503 | [(parallel [(set (match_dup 3) | |
4504 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4505 | (clobber (match_dup 4))]) | |
4506 | (set (match_dup 0) | |
4507 | (compare:CC (match_dup 3) | |
4508 | (const_int 0)))] | |
4509 | "") | |
ca7f5001 RK |
4510 | |
4511 | (define_insn "" | |
9ebbca7d GK |
4512 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4513 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4514 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 4515 | (const_int 0))) |
9ebbca7d | 4516 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
0ad91047 | 4517 | "! TARGET_POWER && ! TARGET_POWERPC64" |
bdf423cb MM |
4518 | "@ |
4519 | mr. %1,%1 | |
9ebbca7d GK |
4520 | {sr|srw}%I2. %3,%1,%h2 |
4521 | # | |
4522 | #" | |
4523 | [(set_attr "type" "delayed_compare") | |
4524 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 4525 | |
9ebbca7d GK |
4526 | (define_split |
4527 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4528 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4529 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4530 | (const_int 0))) | |
4531 | (clobber (match_scratch:SI 3 ""))] | |
4532 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4533 | [(set (match_dup 3) | |
4534 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4535 | (set (match_dup 0) | |
4536 | (compare:CC (match_dup 3) | |
4537 | (const_int 0)))] | |
4538 | "") | |
4539 | ||
4540 | (define_insn "" | |
4541 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
4542 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4543 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4544 | (const_int 0))) |
9ebbca7d | 4545 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 4546 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4547 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 4548 | "TARGET_POWER" |
1fd4e8c1 | 4549 | "@ |
29ae5b89 JL |
4550 | sre. %0,%1,%2 |
4551 | mr. %0,%1 | |
9ebbca7d GK |
4552 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
4553 | # | |
4554 | # | |
4555 | #" | |
4556 | [(set_attr "type" "delayed_compare") | |
4557 | (set_attr "length" "4,4,4,8,8,8")]) | |
4558 | ||
4559 | (define_split | |
4560 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4561 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4562 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4563 | (const_int 0))) | |
4564 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4565 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4566 | (clobber (match_scratch:SI 4 ""))] | |
4567 | "TARGET_POWER && reload_completed" | |
4568 | [(parallel [(set (match_dup 0) | |
4569 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4570 | (clobber (match_dup 4))]) | |
4571 | (set (match_dup 3) | |
4572 | (compare:CC (match_dup 0) | |
4573 | (const_int 0)))] | |
4574 | "") | |
ca7f5001 RK |
4575 | |
4576 | (define_insn "" | |
9ebbca7d GK |
4577 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4578 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4579 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 4580 | (const_int 0))) |
9ebbca7d | 4581 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 4582 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 4583 | "! TARGET_POWER && ! TARGET_POWERPC64" |
29ae5b89 JL |
4584 | "@ |
4585 | mr. %0,%1 | |
9ebbca7d GK |
4586 | {sr|srw}%I2. %0,%1,%h2 |
4587 | # | |
4588 | #" | |
4589 | [(set_attr "type" "delayed_compare") | |
4590 | (set_attr "length" "4,4,8,8")]) | |
4591 | ||
4592 | (define_split | |
4593 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4594 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4595 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4596 | (const_int 0))) | |
4597 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4598 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4599 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4600 | [(set (match_dup 0) | |
4601 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4602 | (set (match_dup 3) | |
4603 | (compare:CC (match_dup 0) | |
4604 | (const_int 0)))] | |
4605 | "") | |
1fd4e8c1 RK |
4606 | |
4607 | (define_insn "" | |
cd2b37d9 RK |
4608 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4609 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4610 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 4611 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 4612 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 4613 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
4614 | |
4615 | (define_insn "" | |
9ebbca7d | 4616 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4617 | (compare:CC |
9ebbca7d GK |
4618 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4619 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4620 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4621 | (const_int 0))) |
9ebbca7d | 4622 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 4623 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4624 | "@ |
4625 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
4626 | #" | |
4627 | [(set_attr "type" "delayed_compare") | |
4628 | (set_attr "length" "4,8")]) | |
4629 | ||
4630 | (define_split | |
4631 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4632 | (compare:CC | |
4633 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4634 | (match_operand:SI 2 "const_int_operand" "")) | |
4635 | (match_operand:SI 3 "mask_operand" "")) | |
4636 | (const_int 0))) | |
4637 | (clobber (match_scratch:SI 4 ""))] | |
4638 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" | |
4639 | [(set (match_dup 4) | |
4640 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
4641 | (match_dup 3))) | |
4642 | (set (match_dup 0) | |
4643 | (compare:CC (match_dup 4) | |
4644 | (const_int 0)))] | |
4645 | "") | |
1fd4e8c1 RK |
4646 | |
4647 | (define_insn "" | |
9ebbca7d | 4648 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4649 | (compare:CC |
9ebbca7d GK |
4650 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4651 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4652 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4653 | (const_int 0))) |
9ebbca7d | 4654 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4655 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 4656 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4657 | "@ |
4658 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
4659 | #" | |
4660 | [(set_attr "type" "delayed_compare") | |
4661 | (set_attr "length" "4,8")]) | |
4662 | ||
4663 | (define_split | |
4664 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4665 | (compare:CC | |
4666 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4667 | (match_operand:SI 2 "const_int_operand" "")) | |
4668 | (match_operand:SI 3 "mask_operand" "")) | |
4669 | (const_int 0))) | |
4670 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4671 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4672 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" | |
4673 | [(set (match_dup 0) | |
4674 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4675 | (set (match_dup 4) | |
4676 | (compare:CC (match_dup 0) | |
4677 | (const_int 0)))] | |
4678 | "") | |
1fd4e8c1 RK |
4679 | |
4680 | (define_insn "" | |
cd2b37d9 | 4681 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4682 | (zero_extend:SI |
4683 | (subreg:QI | |
cd2b37d9 | 4684 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4685 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4686 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4687 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4688 | |
4689 | (define_insn "" | |
9ebbca7d | 4690 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4691 | (compare:CC |
4692 | (zero_extend:SI | |
4693 | (subreg:QI | |
9ebbca7d GK |
4694 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4695 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4696 | (const_int 0))) |
9ebbca7d | 4697 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4698 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4699 | "@ |
4700 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4701 | #" | |
4702 | [(set_attr "type" "delayed_compare") | |
4703 | (set_attr "length" "4,8")]) | |
4704 | ||
4705 | (define_split | |
4706 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4707 | (compare:CC | |
4708 | (zero_extend:SI | |
4709 | (subreg:QI | |
4710 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4711 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4712 | (const_int 0))) | |
4713 | (clobber (match_scratch:SI 3 ""))] | |
4714 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4715 | [(set (match_dup 3) | |
4716 | (zero_extend:SI (subreg:QI | |
4717 | (lshiftrt:SI (match_dup 1) | |
4718 | (match_dup 2)) 0))) | |
4719 | (set (match_dup 0) | |
4720 | (compare:CC (match_dup 3) | |
4721 | (const_int 0)))] | |
4722 | "") | |
1fd4e8c1 RK |
4723 | |
4724 | (define_insn "" | |
9ebbca7d | 4725 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4726 | (compare:CC |
4727 | (zero_extend:SI | |
4728 | (subreg:QI | |
9ebbca7d GK |
4729 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4730 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4731 | (const_int 0))) |
9ebbca7d | 4732 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4733 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4734 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4735 | "@ |
4736 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4737 | #" | |
4738 | [(set_attr "type" "delayed_compare") | |
4739 | (set_attr "length" "4,8")]) | |
4740 | ||
4741 | (define_split | |
4742 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4743 | (compare:CC | |
4744 | (zero_extend:SI | |
4745 | (subreg:QI | |
4746 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4747 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4748 | (const_int 0))) | |
4749 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4750 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4751 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4752 | [(set (match_dup 0) | |
4753 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4754 | (set (match_dup 3) | |
4755 | (compare:CC (match_dup 0) | |
4756 | (const_int 0)))] | |
4757 | "") | |
1fd4e8c1 RK |
4758 | |
4759 | (define_insn "" | |
cd2b37d9 | 4760 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4761 | (zero_extend:SI |
4762 | (subreg:HI | |
cd2b37d9 | 4763 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4764 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4765 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4766 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4767 | |
4768 | (define_insn "" | |
9ebbca7d | 4769 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4770 | (compare:CC |
4771 | (zero_extend:SI | |
4772 | (subreg:HI | |
9ebbca7d GK |
4773 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4774 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4775 | (const_int 0))) |
9ebbca7d | 4776 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4777 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4778 | "@ |
4779 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4780 | #" | |
4781 | [(set_attr "type" "delayed_compare") | |
4782 | (set_attr "length" "4,8")]) | |
4783 | ||
4784 | (define_split | |
4785 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4786 | (compare:CC | |
4787 | (zero_extend:SI | |
4788 | (subreg:HI | |
4789 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4790 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4791 | (const_int 0))) | |
4792 | (clobber (match_scratch:SI 3 ""))] | |
4793 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4794 | [(set (match_dup 3) | |
4795 | (zero_extend:SI (subreg:HI | |
4796 | (lshiftrt:SI (match_dup 1) | |
4797 | (match_dup 2)) 0))) | |
4798 | (set (match_dup 0) | |
4799 | (compare:CC (match_dup 3) | |
4800 | (const_int 0)))] | |
4801 | "") | |
1fd4e8c1 RK |
4802 | |
4803 | (define_insn "" | |
9ebbca7d | 4804 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4805 | (compare:CC |
4806 | (zero_extend:SI | |
4807 | (subreg:HI | |
9ebbca7d GK |
4808 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4809 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4810 | (const_int 0))) |
9ebbca7d | 4811 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4812 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4813 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4814 | "@ |
4815 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4816 | #" | |
4817 | [(set_attr "type" "delayed_compare") | |
4818 | (set_attr "length" "4,8")]) | |
4819 | ||
4820 | (define_split | |
4821 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4822 | (compare:CC | |
4823 | (zero_extend:SI | |
4824 | (subreg:HI | |
4825 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4826 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4827 | (const_int 0))) | |
4828 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4829 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4830 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4831 | [(set (match_dup 0) | |
4832 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4833 | (set (match_dup 3) | |
4834 | (compare:CC (match_dup 0) | |
4835 | (const_int 0)))] | |
4836 | "") | |
1fd4e8c1 RK |
4837 | |
4838 | (define_insn "" | |
cd2b37d9 | 4839 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4840 | (const_int 1) |
cd2b37d9 RK |
4841 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4842 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4843 | (const_int 31)))] |
ca7f5001 | 4844 | "TARGET_POWER" |
1fd4e8c1 RK |
4845 | "rrib %0,%1,%2") |
4846 | ||
4847 | (define_insn "" | |
cd2b37d9 | 4848 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4849 | (const_int 1) |
cd2b37d9 RK |
4850 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4851 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4852 | (const_int 31)))] |
ca7f5001 | 4853 | "TARGET_POWER" |
1fd4e8c1 RK |
4854 | "rrib %0,%1,%2") |
4855 | ||
4856 | (define_insn "" | |
cd2b37d9 | 4857 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4858 | (const_int 1) |
cd2b37d9 RK |
4859 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4860 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4861 | (const_int 1) |
4862 | (const_int 0)))] | |
ca7f5001 | 4863 | "TARGET_POWER" |
1fd4e8c1 RK |
4864 | "rrib %0,%1,%2") |
4865 | ||
ca7f5001 RK |
4866 | (define_expand "ashrsi3" |
4867 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4868 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4869 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4870 | "" | |
4871 | " | |
4872 | { | |
4873 | if (TARGET_POWER) | |
4874 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4875 | else | |
25c341fa | 4876 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4877 | DONE; |
4878 | }") | |
4879 | ||
4880 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4881 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4882 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4883 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4884 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4885 | "TARGET_POWER" |
1fd4e8c1 RK |
4886 | "@ |
4887 | srea %0,%1,%2 | |
ca7f5001 RK |
4888 | {srai|srawi} %0,%1,%h2") |
4889 | ||
25c341fa | 4890 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4891 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4892 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4893 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4894 | "! TARGET_POWER" |
d904e9ed | 4895 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4896 | |
4897 | (define_insn "" | |
9ebbca7d GK |
4898 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4899 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4900 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4901 | (const_int 0))) |
9ebbca7d GK |
4902 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4903 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4904 | "TARGET_POWER" |
1fd4e8c1 RK |
4905 | "@ |
4906 | srea. %3,%1,%2 | |
9ebbca7d GK |
4907 | {srai.|srawi.} %3,%1,%h2 |
4908 | # | |
4909 | #" | |
4910 | [(set_attr "type" "delayed_compare") | |
4911 | (set_attr "length" "4,4,8,8")]) | |
4912 | ||
4913 | (define_split | |
4914 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4915 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4916 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4917 | (const_int 0))) | |
4918 | (clobber (match_scratch:SI 3 "")) | |
4919 | (clobber (match_scratch:SI 4 ""))] | |
4920 | "TARGET_POWER && reload_completed" | |
4921 | [(parallel [(set (match_dup 3) | |
4922 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4923 | (clobber (match_dup 4))]) | |
4924 | (set (match_dup 0) | |
4925 | (compare:CC (match_dup 3) | |
4926 | (const_int 0)))] | |
4927 | "") | |
ca7f5001 RK |
4928 | |
4929 | (define_insn "" | |
9ebbca7d GK |
4930 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4931 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4932 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4933 | (const_int 0))) |
9ebbca7d | 4934 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4935 | "! TARGET_POWER" |
9ebbca7d GK |
4936 | "@ |
4937 | {sra|sraw}%I2. %3,%1,%h2 | |
4938 | #" | |
4939 | [(set_attr "type" "delayed_compare") | |
4940 | (set_attr "length" "4,8")]) | |
4941 | ||
4942 | (define_split | |
4943 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4944 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4945 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4946 | (const_int 0))) | |
4947 | (clobber (match_scratch:SI 3 ""))] | |
4948 | "! TARGET_POWER && reload_completed" | |
4949 | [(set (match_dup 3) | |
4950 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4951 | (set (match_dup 0) | |
4952 | (compare:CC (match_dup 3) | |
4953 | (const_int 0)))] | |
4954 | "") | |
1fd4e8c1 RK |
4955 | |
4956 | (define_insn "" | |
9ebbca7d GK |
4957 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4958 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4959 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4960 | (const_int 0))) |
9ebbca7d | 4961 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4962 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4963 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4964 | "TARGET_POWER" |
1fd4e8c1 RK |
4965 | "@ |
4966 | srea. %0,%1,%2 | |
9ebbca7d GK |
4967 | {srai.|srawi.} %0,%1,%h2 |
4968 | # | |
4969 | #" | |
4970 | [(set_attr "type" "delayed_compare") | |
4971 | (set_attr "length" "4,4,8,8")]) | |
4972 | ||
4973 | (define_split | |
4974 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4975 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4976 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4977 | (const_int 0))) | |
4978 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4979 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4980 | (clobber (match_scratch:SI 4 ""))] | |
4981 | "TARGET_POWER && reload_completed" | |
4982 | [(parallel [(set (match_dup 0) | |
4983 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4984 | (clobber (match_dup 4))]) | |
4985 | (set (match_dup 3) | |
4986 | (compare:CC (match_dup 0) | |
4987 | (const_int 0)))] | |
4988 | "") | |
1fd4e8c1 | 4989 | |
ca7f5001 | 4990 | (define_insn "" |
9ebbca7d GK |
4991 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4992 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4993 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4994 | (const_int 0))) |
9ebbca7d | 4995 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4996 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4997 | "! TARGET_POWER" |
9ebbca7d GK |
4998 | "@ |
4999 | {sra|sraw}%I2. %0,%1,%h2 | |
5000 | #" | |
5001 | [(set_attr "type" "delayed_compare") | |
5002 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 5003 | \f |
9ebbca7d GK |
5004 | (define_split |
5005 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5006 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
5007 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
5008 | (const_int 0))) | |
5009 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
5010 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
5011 | "! TARGET_POWER && reload_completed" | |
5012 | [(set (match_dup 0) | |
5013 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
5014 | (set (match_dup 3) | |
5015 | (compare:CC (match_dup 0) | |
5016 | (const_int 0)))] | |
5017 | "") | |
5018 | ||
1fd4e8c1 RK |
5019 | ;; Floating-point insns, excluding normal data motion. |
5020 | ;; | |
ca7f5001 RK |
5021 | ;; PowerPC has a full set of single-precision floating point instructions. |
5022 | ;; | |
5023 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
5024 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
5025 | ;; The only conversions we will do will be when storing to memory. In that | |
5026 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
5027 | ;; |
5028 | ;; Note that when we store into a single-precision memory location, we need to | |
5029 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
5030 | ;; need a scratch register for the frsp. But this is difficult when the store | |
5031 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
5032 | ;; this case, we just lose precision that we would have otherwise gotten but | |
5033 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
5034 | ||
e8112008 | 5035 | (define_insn "extendsfdf2" |
cd2b37d9 | 5036 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
e8112008 | 5037 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] |
d14a6d05 | 5038 | "TARGET_HARD_FLOAT" |
e8112008 | 5039 | "* |
5c30aff8 | 5040 | { |
e8112008 RK |
5041 | if (REGNO (operands[0]) == REGNO (operands[1])) |
5042 | return \"\"; | |
5043 | else | |
5044 | return \"fmr %0,%1\"; | |
5045 | }" | |
5046 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5047 | |
5048 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
5049 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5050 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5051 | "TARGET_HARD_FLOAT" |
dcac138d | 5052 | "frsp %0,%1" |
1fd4e8c1 RK |
5053 | [(set_attr "type" "fp")]) |
5054 | ||
455350f4 RK |
5055 | (define_insn "aux_truncdfsf2" |
5056 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5057 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))] | |
5058 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" | |
5059 | "frsp %0,%1" | |
5060 | [(set_attr "type" "fp")]) | |
5061 | ||
1fd4e8c1 | 5062 | (define_insn "negsf2" |
cd2b37d9 RK |
5063 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5064 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5065 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5066 | "fneg %0,%1" |
5067 | [(set_attr "type" "fp")]) | |
5068 | ||
5069 | (define_insn "abssf2" | |
cd2b37d9 RK |
5070 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5071 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5072 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5073 | "fabs %0,%1" |
5074 | [(set_attr "type" "fp")]) | |
5075 | ||
5076 | (define_insn "" | |
cd2b37d9 RK |
5077 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5078 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 5079 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5080 | "fnabs %0,%1" |
5081 | [(set_attr "type" "fp")]) | |
5082 | ||
ca7f5001 RK |
5083 | (define_expand "addsf3" |
5084 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5085 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
5086 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 5087 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
5088 | "") |
5089 | ||
5090 | (define_insn "" | |
cd2b37d9 RK |
5091 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5092 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5093 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5094 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 5095 | "fadds %0,%1,%2" |
ca7f5001 RK |
5096 | [(set_attr "type" "fp")]) |
5097 | ||
5098 | (define_insn "" | |
5099 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5100 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5101 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5102 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 5103 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
5104 | [(set_attr "type" "fp")]) |
5105 | ||
5106 | (define_expand "subsf3" | |
5107 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5108 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
5109 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 5110 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
5111 | "") |
5112 | ||
5113 | (define_insn "" | |
5114 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5115 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
5116 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5117 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 5118 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
5119 | [(set_attr "type" "fp")]) |
5120 | ||
ca7f5001 | 5121 | (define_insn "" |
cd2b37d9 RK |
5122 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5123 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
5124 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5125 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 5126 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
5127 | [(set_attr "type" "fp")]) |
5128 | ||
5129 | (define_expand "mulsf3" | |
5130 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5131 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
5132 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 5133 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
5134 | "") |
5135 | ||
5136 | (define_insn "" | |
5137 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5138 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5139 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5140 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 5141 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
5142 | [(set_attr "type" "fp")]) |
5143 | ||
ca7f5001 | 5144 | (define_insn "" |
cd2b37d9 RK |
5145 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5146 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5147 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5148 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 5149 | "{fm|fmul} %0,%1,%2" |
0780f386 | 5150 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 5151 | |
ca7f5001 RK |
5152 | (define_expand "divsf3" |
5153 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5154 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
5155 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 5156 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
5157 | "") |
5158 | ||
5159 | (define_insn "" | |
cd2b37d9 RK |
5160 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5161 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
5162 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5163 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 5164 | "fdivs %0,%1,%2" |
ca7f5001 RK |
5165 | [(set_attr "type" "sdiv")]) |
5166 | ||
5167 | (define_insn "" | |
5168 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5169 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
5170 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5171 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 5172 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 5173 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
5174 | |
5175 | (define_insn "" | |
cd2b37d9 RK |
5176 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5177 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5178 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5179 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 5180 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 5181 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
5182 | [(set_attr "type" "fp")]) |
5183 | ||
5184 | (define_insn "" | |
5185 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5186 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5187 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5188 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 5189 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 5190 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 5191 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5192 | |
5193 | (define_insn "" | |
cd2b37d9 RK |
5194 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5195 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5196 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5197 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 5198 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 5199 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
5200 | [(set_attr "type" "fp")]) |
5201 | ||
5202 | (define_insn "" | |
5203 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5204 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5205 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5206 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 5207 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 5208 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 5209 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5210 | |
5211 | (define_insn "" | |
cd2b37d9 RK |
5212 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5213 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5214 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5215 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 5216 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 5217 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
5218 | [(set_attr "type" "fp")]) |
5219 | ||
5220 | (define_insn "" | |
5221 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5222 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5223 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5224 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 5225 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 5226 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 5227 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5228 | |
5229 | (define_insn "" | |
cd2b37d9 RK |
5230 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5231 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5232 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5233 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 5234 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 5235 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
5236 | [(set_attr "type" "fp")]) |
5237 | ||
5238 | (define_insn "" | |
5239 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5240 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
5241 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
5242 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 5243 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 5244 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 5245 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 5246 | |
ca7f5001 RK |
5247 | (define_expand "sqrtsf2" |
5248 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5249 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 5250 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
5251 | "") |
5252 | ||
5253 | (define_insn "" | |
5254 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5255 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5256 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT" |
ca7f5001 RK |
5257 | "fsqrts %0,%1" |
5258 | [(set_attr "type" "ssqrt")]) | |
5259 | ||
5260 | (define_insn "" | |
5261 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
5262 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5263 | "TARGET_POWER2 && TARGET_HARD_FLOAT" |
ca7f5001 RK |
5264 | "fsqrt %0,%1" |
5265 | [(set_attr "type" "dsqrt")]) | |
5266 | ||
94d7001a RK |
5267 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
5268 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
5269 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
5270 | ;; combine. |
5271 | (define_expand "maxsf3" | |
8e871c05 | 5272 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
5273 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
5274 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
5275 | (match_dup 1) |
5276 | (match_dup 2)))] | |
50a0b056 GK |
5277 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
5278 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") | |
2f607b94 | 5279 | |
8e871c05 | 5280 | (define_expand "minsf3" |
50a0b056 GK |
5281 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
5282 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
5283 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
5284 | (match_dup 2) | |
5285 | (match_dup 1)))] | |
d14a6d05 | 5286 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 | 5287 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 5288 | |
8e871c05 RK |
5289 | (define_split |
5290 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
5291 | (match_operator:SF 3 "min_max_operator" |
5292 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
5293 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
d14a6d05 | 5294 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 GK |
5295 | [(const_int 0)] |
5296 | " | |
5297 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
5298 | operands[1], operands[2]); | |
5299 | DONE; | |
5300 | }") | |
2f607b94 | 5301 | |
94d7001a | 5302 | (define_expand "movsfcc" |
0ad91047 | 5303 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 5304 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5305 | (match_operand:SF 2 "gpc_reg_operand" "") |
5306 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 5307 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
5308 | " |
5309 | { | |
50a0b056 GK |
5310 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5311 | DONE; | |
94d7001a | 5312 | else |
50a0b056 | 5313 | FAIL; |
94d7001a | 5314 | }") |
d56d506a | 5315 | |
50a0b056 | 5316 | (define_insn "*fselsfsf4" |
8e871c05 RK |
5317 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5318 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5319 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5320 | (match_operand:SF 2 "gpc_reg_operand" "f") |
5321 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5322 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5323 | "fsel %0,%1,%2,%3" |
5324 | [(set_attr "type" "fp")]) | |
2f607b94 | 5325 | |
50a0b056 | 5326 | (define_insn "*fseldfsf4" |
94d7001a RK |
5327 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
5328 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 5329 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5330 | (match_operand:SF 2 "gpc_reg_operand" "f") |
5331 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5332 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
5333 | "fsel %0,%1,%2,%3" |
5334 | [(set_attr "type" "fp")]) | |
d56d506a | 5335 | |
1fd4e8c1 | 5336 | (define_insn "negdf2" |
cd2b37d9 RK |
5337 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5338 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5339 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5340 | "fneg %0,%1" |
5341 | [(set_attr "type" "fp")]) | |
5342 | ||
5343 | (define_insn "absdf2" | |
cd2b37d9 RK |
5344 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5345 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5346 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5347 | "fabs %0,%1" |
5348 | [(set_attr "type" "fp")]) | |
5349 | ||
5350 | (define_insn "" | |
cd2b37d9 RK |
5351 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5352 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 5353 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5354 | "fnabs %0,%1" |
5355 | [(set_attr "type" "fp")]) | |
5356 | ||
5357 | (define_insn "adddf3" | |
cd2b37d9 RK |
5358 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5359 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5360 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5361 | "TARGET_HARD_FLOAT" |
ca7f5001 | 5362 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
5363 | [(set_attr "type" "fp")]) |
5364 | ||
5365 | (define_insn "subdf3" | |
cd2b37d9 RK |
5366 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5367 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
5368 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5369 | "TARGET_HARD_FLOAT" |
ca7f5001 | 5370 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
5371 | [(set_attr "type" "fp")]) |
5372 | ||
5373 | (define_insn "muldf3" | |
cd2b37d9 RK |
5374 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5375 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5376 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5377 | "TARGET_HARD_FLOAT" |
ca7f5001 | 5378 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 5379 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5380 | |
5381 | (define_insn "divdf3" | |
cd2b37d9 RK |
5382 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5383 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
5384 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5385 | "TARGET_HARD_FLOAT" |
ca7f5001 | 5386 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 5387 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
5388 | |
5389 | (define_insn "" | |
cd2b37d9 RK |
5390 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5391 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5392 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5393 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 5394 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5395 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 5396 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5397 | |
5398 | (define_insn "" | |
cd2b37d9 RK |
5399 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5400 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5401 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5402 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 5403 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5404 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 5405 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5406 | |
5407 | (define_insn "" | |
cd2b37d9 RK |
5408 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5409 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5410 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5411 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 5412 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5413 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 5414 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5415 | |
5416 | (define_insn "" | |
cd2b37d9 RK |
5417 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5418 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5419 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5420 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 5421 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5422 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 5423 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
5424 | |
5425 | (define_insn "sqrtdf2" | |
5426 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5427 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5428 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
5429 | "fsqrt %0,%1" |
5430 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 5431 | |
50a0b056 GK |
5432 | ;; The conditional move instructions allow us to perform max and min |
5433 | ;; operations even when | |
b77dfefc | 5434 | |
8e871c05 | 5435 | (define_expand "maxdf3" |
8e871c05 | 5436 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
5437 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
5438 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
5439 | (match_dup 1) |
5440 | (match_dup 2)))] | |
50a0b056 GK |
5441 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
5442 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") | |
b77dfefc | 5443 | |
8e871c05 | 5444 | (define_expand "mindf3" |
50a0b056 GK |
5445 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5446 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
5447 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
5448 | (match_dup 2) | |
5449 | (match_dup 1)))] | |
d14a6d05 | 5450 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 | 5451 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 5452 | |
8e871c05 RK |
5453 | (define_split |
5454 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
5455 | (match_operator:DF 3 "min_max_operator" |
5456 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
5457 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
d14a6d05 | 5458 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 GK |
5459 | [(const_int 0)] |
5460 | " | |
5461 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
5462 | operands[1], operands[2]); | |
5463 | DONE; | |
5464 | }") | |
b77dfefc | 5465 | |
94d7001a | 5466 | (define_expand "movdfcc" |
0ad91047 | 5467 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 5468 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5469 | (match_operand:DF 2 "gpc_reg_operand" "") |
5470 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 5471 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
5472 | " |
5473 | { | |
50a0b056 GK |
5474 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5475 | DONE; | |
94d7001a | 5476 | else |
50a0b056 | 5477 | FAIL; |
94d7001a | 5478 | }") |
d56d506a | 5479 | |
50a0b056 | 5480 | (define_insn "*fseldfdf4" |
8e871c05 RK |
5481 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5482 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5483 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5484 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5485 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5486 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5487 | "fsel %0,%1,%2,%3" |
5488 | [(set_attr "type" "fp")]) | |
d56d506a | 5489 | |
50a0b056 | 5490 | (define_insn "*fselsfdf4" |
94d7001a RK |
5491 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5492 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5493 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5494 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5495 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5496 | "TARGET_PPC_GFXOPT" | |
5497 | "fsel %0,%1,%2,%3" | |
5498 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5499 | \f |
5500 | ;; Conversions to and from floating-point. | |
802a0058 | 5501 | |
9ebbca7d GK |
5502 | ; For each of these conversions, there is a define_expand, a define_insn |
5503 | ; with a '#' template, and a define_split (with C code). The idea is | |
5504 | ; to allow constant folding with the template of the define_insn, | |
5505 | ; then to have the insns split later (between sched1 and final). | |
5506 | ||
1fd4e8c1 | 5507 | (define_expand "floatsidf2" |
802a0058 MM |
5508 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5509 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5510 | (use (match_dup 2)) | |
5511 | (use (match_dup 3)) | |
208c89ce | 5512 | (clobber (match_dup 4)) |
a7df97e6 | 5513 | (clobber (match_dup 5)) |
9ebbca7d | 5514 | (clobber (match_dup 6))])] |
05d49501 | 5515 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5516 | " |
5517 | { | |
05d49501 AM |
5518 | if (TARGET_POWERPC64) |
5519 | { | |
5520 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5521 | rtx t1 = gen_reg_rtx (DImode); | |
5522 | rtx t2 = gen_reg_rtx (DImode); | |
5523 | emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); | |
5524 | DONE; | |
5525 | } | |
5526 | ||
802a0058 | 5527 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5528 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); |
9ebbca7d GK |
5529 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5530 | operands[5] = gen_reg_rtx (DFmode); | |
5531 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5532 | }") |
5533 | ||
802a0058 MM |
5534 | (define_insn "*floatsidf2_internal" |
5535 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5536 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5537 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5538 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d GK |
5539 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
5540 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=f")) | |
5541 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=r"))] | |
31bfaa0b | 5542 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 5543 | "#" |
a7df97e6 | 5544 | [(set_attr "length" "24")]) |
802a0058 MM |
5545 | |
5546 | (define_split | |
dbe3df29 | 5547 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
5548 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
5549 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5550 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5551 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5552 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5553 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
31bfaa0b | 5554 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5555 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5556 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5557 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5558 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5559 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5560 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5561 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
208c89ce MM |
5562 | " |
5563 | { | |
9ebbca7d GK |
5564 | rtx lowword, highword; |
5565 | if (GET_CODE (operands[4]) != MEM) | |
5566 | abort(); | |
5567 | highword = XEXP (operands[4], 0); | |
5568 | lowword = plus_constant (highword, 4); | |
5569 | if (! WORDS_BIG_ENDIAN) | |
5570 | { | |
5571 | rtx tmp; | |
5572 | tmp = highword; highword = lowword; lowword = tmp; | |
5573 | } | |
5574 | ||
5575 | emit_insn (gen_xorsi3 (operands[6], operands[1], | |
5576 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); | |
5577 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); | |
5578 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5579 | emit_move_insn (operands[5], operands[4]); | |
5580 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5581 | DONE; | |
208c89ce | 5582 | }") |
802a0058 MM |
5583 | |
5584 | (define_expand "floatunssidf2" | |
5585 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5586 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5587 | (use (match_dup 2)) | |
5588 | (use (match_dup 3)) | |
a7df97e6 | 5589 | (clobber (match_dup 4)) |
9ebbca7d | 5590 | (clobber (match_dup 5))])] |
05d49501 | 5591 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5592 | " |
5593 | { | |
05d49501 AM |
5594 | if (TARGET_POWERPC64) |
5595 | { | |
5596 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5597 | rtx t1 = gen_reg_rtx (DImode); | |
5598 | rtx t2 = gen_reg_rtx (DImode); | |
5599 | emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, | |
5600 | t1, t2)); | |
5601 | DONE; | |
5602 | } | |
5603 | ||
802a0058 | 5604 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5605 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); |
9ebbca7d GK |
5606 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5607 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5608 | }") |
5609 | ||
802a0058 MM |
5610 | (define_insn "*floatunssidf2_internal" |
5611 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5612 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5613 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5614 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d GK |
5615 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
5616 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))] | |
31bfaa0b | 5617 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 5618 | "#" |
a7df97e6 | 5619 | [(set_attr "length" "20")]) |
802a0058 MM |
5620 | |
5621 | (define_split | |
5622 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5623 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5624 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5625 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5626 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5627 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
31bfaa0b | 5628 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5629 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5630 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5631 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5632 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5633 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5634 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
5635 | " | |
802a0058 | 5636 | { |
9ebbca7d GK |
5637 | rtx lowword, highword; |
5638 | if (GET_CODE (operands[4]) != MEM) | |
5639 | abort(); | |
5640 | highword = XEXP (operands[4], 0); | |
5641 | lowword = plus_constant (highword, 4); | |
5642 | if (! WORDS_BIG_ENDIAN) | |
f6968f59 | 5643 | { |
9ebbca7d GK |
5644 | rtx tmp; |
5645 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5646 | } |
802a0058 | 5647 | |
9ebbca7d GK |
5648 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); |
5649 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5650 | emit_move_insn (operands[5], operands[4]); | |
5651 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5652 | DONE; | |
5653 | }") | |
1fd4e8c1 | 5654 | |
1fd4e8c1 | 5655 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
5656 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5657 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5658 | (clobber (match_dup 2)) | |
9ebbca7d | 5659 | (clobber (match_dup 3))])] |
9cb8fcaf | 5660 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5661 | " |
5662 | { | |
802a0058 | 5663 | operands[2] = gen_reg_rtx (DImode); |
9ebbca7d | 5664 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5665 | }") |
5666 | ||
802a0058 MM |
5667 | (define_insn "*fix_truncdfsi2_internal" |
5668 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5669 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
e3485bbc | 5670 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) |
9ebbca7d | 5671 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
9cb8fcaf | 5672 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
802a0058 | 5673 | "#" |
9ebbca7d | 5674 | [(set_attr "length" "16")]) |
802a0058 MM |
5675 | |
5676 | (define_split | |
5677 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
75540af0 | 5678 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
802a0058 | 5679 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
9ebbca7d | 5680 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] |
9cb8fcaf | 5681 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
9ebbca7d | 5682 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
75540af0 | 5683 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
9ebbca7d GK |
5684 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
5685 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] | |
5686 | " | |
802a0058 | 5687 | { |
9ebbca7d GK |
5688 | rtx lowword; |
5689 | if (GET_CODE (operands[3]) != MEM) | |
5690 | abort(); | |
5691 | lowword = XEXP (operands[3], 0); | |
5692 | if (WORDS_BIG_ENDIAN) | |
5693 | lowword = plus_constant (lowword, 4); | |
802a0058 | 5694 | |
9ebbca7d GK |
5695 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5696 | emit_move_insn (operands[3], operands[2]); | |
5697 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
5698 | DONE; | |
5699 | }") | |
802a0058 | 5700 | |
9ebbca7d GK |
5701 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10)) |
5702 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) | |
5703 | ; because the first makes it clear that operand 0 is not live | |
5704 | ; before the instruction. | |
5705 | (define_insn "fctiwz" | |
61c07d3c | 5706 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
9ebbca7d | 5707 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))] |
a260abc9 DE |
5708 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
5709 | "{fcirz|fctiwz} %0,%1" | |
5710 | [(set_attr "type" "fp")]) | |
5711 | ||
a473029f RK |
5712 | (define_insn "floatdidf2" |
5713 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 5714 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] |
d14a6d05 | 5715 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
5716 | "fcfid %0,%1" |
5717 | [(set_attr "type" "fp")]) | |
5718 | ||
05d49501 AM |
5719 | (define_insn_and_split "floatsidf_ppc64" |
5720 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5721 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5722 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5723 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5724 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
5725 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" | |
5726 | "#" | |
5727 | "" | |
5728 | [(set (match_dup 3) (sign_extend:DI (match_dup 1))) | |
5729 | (set (match_dup 2) (match_dup 3)) | |
5730 | (set (match_dup 4) (match_dup 2)) | |
5731 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5732 | "") | |
5733 | ||
5734 | (define_insn_and_split "floatunssidf_ppc64" | |
5735 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5736 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5737 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5738 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5739 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
5740 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" | |
5741 | "#" | |
5742 | "" | |
5743 | [(set (match_dup 3) (zero_extend:DI (match_dup 1))) | |
5744 | (set (match_dup 2) (match_dup 3)) | |
5745 | (set (match_dup 4) (match_dup 2)) | |
5746 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5747 | "") | |
5748 | ||
a473029f | 5749 | (define_insn "fix_truncdfdi2" |
61c07d3c | 5750 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
a473029f | 5751 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] |
d14a6d05 | 5752 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
5753 | "fctidz %0,%1" |
5754 | [(set_attr "type" "fp")]) | |
ea112fc4 DE |
5755 | |
5756 | ;; This only is safe if rounding mode set appropriately. | |
5757 | (define_insn_and_split "floatdisf2" | |
5758 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 5759 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 DE |
5760 | (clobber (match_scratch:DF 2 "=f"))] |
5761 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && flag_unsafe_math_optimizations" | |
5762 | "#" | |
5763 | "&& reload_completed" | |
5764 | [(set (match_dup 2) | |
5765 | (float:DF (match_dup 1))) | |
5766 | (set (match_dup 0) | |
5767 | (float_truncate:SF (match_dup 2)))] | |
5768 | "") | |
1fd4e8c1 RK |
5769 | \f |
5770 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5771 | ;; of instructions. The & constraints are to prevent the register |
5772 | ;; allocator from allocating registers that overlap with the inputs | |
5773 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5774 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5775 | |
266eb58a | 5776 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5777 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5778 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5779 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5780 | "! TARGET_POWERPC64" |
0f645302 MM |
5781 | "* |
5782 | { | |
5783 | if (WORDS_BIG_ENDIAN) | |
5784 | return (GET_CODE (operands[2])) != CONST_INT | |
5785 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5786 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5787 | else | |
5788 | return (GET_CODE (operands[2])) != CONST_INT | |
5789 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5790 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5791 | }" | |
b19003d8 | 5792 | [(set_attr "length" "8")]) |
1fd4e8c1 | 5793 | |
266eb58a | 5794 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5795 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5796 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5797 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5798 | "! TARGET_POWERPC64" |
5502823b RK |
5799 | "* |
5800 | { | |
0f645302 MM |
5801 | if (WORDS_BIG_ENDIAN) |
5802 | return (GET_CODE (operands[1]) != CONST_INT) | |
5803 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5804 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5805 | else | |
5806 | return (GET_CODE (operands[1]) != CONST_INT) | |
5807 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5808 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5809 | }" |
ca7f5001 RK |
5810 | [(set_attr "length" "8")]) |
5811 | ||
266eb58a | 5812 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5813 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5814 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5815 | "! TARGET_POWERPC64" |
5502823b RK |
5816 | "* |
5817 | { | |
5818 | return (WORDS_BIG_ENDIAN) | |
5819 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5820 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5821 | }" | |
ca7f5001 RK |
5822 | [(set_attr "length" "8")]) |
5823 | ||
8ffd9c51 RK |
5824 | (define_expand "mulsidi3" |
5825 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5826 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5827 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5828 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5829 | " |
5830 | { | |
5831 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5832 | { | |
39403d82 DE |
5833 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5834 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5835 | emit_insn (gen_mull_call ()); |
cf27b467 | 5836 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5837 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5838 | else |
5839 | { | |
5840 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5841 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5842 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5843 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5844 | } |
8ffd9c51 RK |
5845 | DONE; |
5846 | } | |
5847 | else if (TARGET_POWER) | |
5848 | { | |
5849 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5850 | DONE; | |
5851 | } | |
5852 | }") | |
deb9225a | 5853 | |
8ffd9c51 | 5854 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5855 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5856 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5857 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5858 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5859 | "TARGET_POWER" |
b19003d8 | 5860 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5861 | [(set_attr "type" "imul") |
5862 | (set_attr "length" "8")]) | |
deb9225a | 5863 | |
f192bf8b | 5864 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5865 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5866 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5867 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5868 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5869 | "* |
5870 | { | |
5871 | return (WORDS_BIG_ENDIAN) | |
5872 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5873 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5874 | }" | |
8ffd9c51 RK |
5875 | [(set_attr "type" "imul") |
5876 | (set_attr "length" "8")]) | |
deb9225a | 5877 | |
ebedb4dd MM |
5878 | (define_split |
5879 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5880 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5881 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5882 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5883 | [(set (match_dup 3) |
5884 | (truncate:SI | |
5885 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5886 | (sign_extend:DI (match_dup 2))) | |
5887 | (const_int 32)))) | |
5888 | (set (match_dup 4) | |
5889 | (mult:SI (match_dup 1) | |
5890 | (match_dup 2)))] | |
5891 | " | |
5892 | { | |
5893 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5894 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5895 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5896 | }") | |
5897 | ||
f192bf8b DE |
5898 | (define_expand "umulsidi3" |
5899 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5900 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5901 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5902 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5903 | " | |
5904 | { | |
5905 | if (TARGET_POWER) | |
5906 | { | |
5907 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5908 | DONE; | |
5909 | } | |
5910 | }") | |
5911 | ||
5912 | (define_insn "umulsidi3_mq" | |
5913 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5914 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5915 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5916 | (clobber (match_scratch:SI 3 "=q"))] | |
5917 | "TARGET_POWERPC && TARGET_POWER" | |
5918 | "* | |
5919 | { | |
5920 | return (WORDS_BIG_ENDIAN) | |
5921 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5922 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5923 | }" | |
5924 | [(set_attr "type" "imul") | |
5925 | (set_attr "length" "8")]) | |
5926 | ||
5927 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5928 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5929 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5930 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5931 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5932 | "* |
5933 | { | |
5934 | return (WORDS_BIG_ENDIAN) | |
5935 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5936 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5937 | }" | |
5938 | [(set_attr "type" "imul") | |
5939 | (set_attr "length" "8")]) | |
5940 | ||
ebedb4dd MM |
5941 | (define_split |
5942 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5943 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5944 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5945 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5946 | [(set (match_dup 3) |
5947 | (truncate:SI | |
5948 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5949 | (zero_extend:DI (match_dup 2))) | |
5950 | (const_int 32)))) | |
5951 | (set (match_dup 4) | |
5952 | (mult:SI (match_dup 1) | |
5953 | (match_dup 2)))] | |
5954 | " | |
5955 | { | |
5956 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5957 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5958 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5959 | }") | |
5960 | ||
8ffd9c51 RK |
5961 | (define_expand "smulsi3_highpart" |
5962 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5963 | (truncate:SI | |
5964 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5965 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5966 | (sign_extend:DI | |
5967 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5968 | (const_int 32))))] | |
5969 | "" | |
5970 | " | |
5971 | { | |
5972 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5973 | { | |
39403d82 DE |
5974 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5975 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5976 | emit_insn (gen_mulh_call ()); |
39403d82 | 5977 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5978 | DONE; |
5979 | } | |
5980 | else if (TARGET_POWER) | |
5981 | { | |
5982 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5983 | DONE; | |
5984 | } | |
5985 | }") | |
deb9225a | 5986 | |
8ffd9c51 RK |
5987 | (define_insn "smulsi3_highpart_mq" |
5988 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5989 | (truncate:SI | |
fada905b MM |
5990 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5991 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5992 | (sign_extend:DI | |
5993 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5994 | (const_int 32)))) |
5995 | (clobber (match_scratch:SI 3 "=q"))] | |
5996 | "TARGET_POWER" | |
5997 | "mul %0,%1,%2" | |
5998 | [(set_attr "type" "imul")]) | |
deb9225a | 5999 | |
f192bf8b | 6000 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
6001 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6002 | (truncate:SI | |
fada905b MM |
6003 | (lshiftrt:DI (mult:DI (sign_extend:DI |
6004 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
6005 | (sign_extend:DI | |
6006 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 6007 | (const_int 32))))] |
f192bf8b | 6008 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
6009 | "mulhw %0,%1,%2" |
6010 | [(set_attr "type" "imul")]) | |
deb9225a | 6011 | |
f192bf8b DE |
6012 | (define_expand "umulsi3_highpart" |
6013 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
6014 | (truncate:SI | |
6015 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
6016 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
6017 | (zero_extend:DI | |
6018 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
6019 | (const_int 32))))] | |
6020 | "TARGET_POWERPC" | |
6021 | " | |
6022 | { | |
6023 | if (TARGET_POWER) | |
6024 | { | |
6025 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
6026 | DONE; | |
6027 | } | |
6028 | }") | |
6029 | ||
6030 | (define_insn "umulsi3_highpart_mq" | |
6031 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6032 | (truncate:SI | |
6033 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
6034 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
6035 | (zero_extend:DI | |
6036 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
6037 | (const_int 32)))) | |
6038 | (clobber (match_scratch:SI 3 "=q"))] | |
6039 | "TARGET_POWERPC && TARGET_POWER" | |
6040 | "mulhwu %0,%1,%2" | |
6041 | [(set_attr "type" "imul")]) | |
6042 | ||
6043 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
6044 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6045 | (truncate:SI | |
6046 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
6047 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
6048 | (zero_extend:DI | |
6049 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
6050 | (const_int 32))))] | |
f192bf8b | 6051 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
6052 | "mulhwu %0,%1,%2" |
6053 | [(set_attr "type" "imul")]) | |
6054 | ||
6055 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
6056 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
6057 | ;; why we have the strange constraints below. | |
6058 | (define_insn "ashldi3_power" | |
6059 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
6060 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
6061 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
6062 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
6063 | "TARGET_POWER" | |
6064 | "@ | |
6065 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
6066 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
6067 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
6068 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
6069 | [(set_attr "length" "8")]) | |
6070 | ||
6071 | (define_insn "lshrdi3_power" | |
47ad8c61 | 6072 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
6073 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
6074 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
6075 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
6076 | "TARGET_POWER" | |
6077 | "@ | |
47ad8c61 | 6078 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
6079 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
6080 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
6081 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
6082 | [(set_attr "length" "8")]) | |
6083 | ||
6084 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
6085 | ;; just handle shifts by constants. | |
6086 | (define_insn "ashrdi3_power" | |
7093ddee | 6087 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
6088 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6089 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
6090 | (clobber (match_scratch:SI 3 "=X,q"))] | |
6091 | "TARGET_POWER" | |
6092 | "@ | |
6093 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
6094 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
6095 | [(set_attr "length" "8")]) | |
4aa74a4f FS |
6096 | |
6097 | (define_insn "ashrdi3_no_power" | |
6098 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") | |
6099 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6100 | (match_operand:SI 2 "const_int_operand" "M,i")))] | |
6101 | "TARGET_32BIT && !TARGET_POWER" | |
6102 | "@ | |
6103 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
6104 | {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" | |
6105 | [(set_attr "length" "8,12")]) | |
266eb58a DE |
6106 | \f |
6107 | ;; PowerPC64 DImode operations. | |
6108 | ||
6109 | (define_expand "adddi3" | |
6110 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6111 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6112 | (match_operand:DI 2 "reg_or_add_cint64_operand" "")))] |
266eb58a DE |
6113 | "" |
6114 | " | |
6115 | { | |
a260abc9 DE |
6116 | if (! TARGET_POWERPC64) |
6117 | { | |
6118 | if (non_short_cint_operand (operands[2], DImode)) | |
6119 | FAIL; | |
6120 | } | |
6121 | else | |
6122 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 6123 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 6124 | { |
677a9668 | 6125 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
6126 | ? operands[0] : gen_reg_rtx (DImode)); |
6127 | ||
2bfcf297 | 6128 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 6129 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 6130 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
a260abc9 | 6131 | |
2bfcf297 DB |
6132 | if (!CONST_OK_FOR_LETTER_P (rest, 'L')) |
6133 | FAIL; | |
a260abc9 | 6134 | |
2bfcf297 DB |
6135 | /* The ordering here is important for the prolog expander. |
6136 | When space is allocated from the stack, adding 'low' first may | |
6137 | produce a temporary deallocation (which would be bad). */ | |
6138 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest))); | |
a260abc9 DE |
6139 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); |
6140 | DONE; | |
6141 | } | |
266eb58a DE |
6142 | }") |
6143 | ||
6144 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
6145 | ;; allowing register zero as source. | |
6146 | ||
a260abc9 | 6147 | (define_insn "*adddi3_internal1" |
266eb58a DE |
6148 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
6149 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 6150 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
6151 | "TARGET_POWERPC64" |
6152 | "@ | |
6153 | add %0,%1,%2 | |
6154 | addi %0,%1,%2 | |
6155 | addic %0,%1,%2 | |
802a0058 | 6156 | addis %0,%1,%v2") |
266eb58a | 6157 | |
a260abc9 | 6158 | (define_insn "*adddi3_internal2" |
9ebbca7d GK |
6159 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
6160 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
6161 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 6162 | (const_int 0))) |
9ebbca7d | 6163 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
266eb58a DE |
6164 | "TARGET_POWERPC64" |
6165 | "@ | |
6166 | add. %3,%1,%2 | |
9ebbca7d GK |
6167 | addic. %3,%1,%2 |
6168 | # | |
6169 | #" | |
6170 | [(set_attr "type" "compare") | |
6171 | (set_attr "length" "4,4,8,8")]) | |
6172 | ||
6173 | (define_split | |
6174 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6175 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6176 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
6177 | (const_int 0))) | |
6178 | (clobber (match_scratch:DI 3 ""))] | |
6179 | "TARGET_POWERPC64 && reload_completed" | |
6180 | [(set (match_dup 3) | |
6181 | (plus:DI (match_dup 1) (match_dup 2))) | |
6182 | (set (match_dup 0) | |
6183 | (compare:CC (match_dup 3) | |
6184 | (const_int 0)))] | |
6185 | "") | |
266eb58a | 6186 | |
a260abc9 | 6187 | (define_insn "*adddi3_internal3" |
9ebbca7d GK |
6188 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
6189 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
6190 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 6191 | (const_int 0))) |
9ebbca7d | 6192 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
266eb58a DE |
6193 | (plus:DI (match_dup 1) (match_dup 2)))] |
6194 | "TARGET_POWERPC64" | |
6195 | "@ | |
6196 | add. %0,%1,%2 | |
9ebbca7d GK |
6197 | addic. %0,%1,%2 |
6198 | # | |
6199 | #" | |
6200 | [(set_attr "type" "compare") | |
6201 | (set_attr "length" "4,4,8,8")]) | |
6202 | ||
6203 | (define_split | |
6204 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6205 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6206 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
6207 | (const_int 0))) | |
6208 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6209 | (plus:DI (match_dup 1) (match_dup 2)))] | |
6210 | "TARGET_POWERPC64 && reload_completed" | |
6211 | [(set (match_dup 0) | |
6212 | (plus:DI (match_dup 1) (match_dup 2))) | |
6213 | (set (match_dup 3) | |
6214 | (compare:CC (match_dup 0) | |
6215 | (const_int 0)))] | |
6216 | "") | |
266eb58a DE |
6217 | |
6218 | ;; Split an add that we can't do in one insn into two insns, each of which | |
6219 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
6220 | ;; add should be last in case the result gets used in an address. | |
6221 | ||
6222 | (define_split | |
6223 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6224 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6225 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
6226 | "TARGET_POWERPC64" | |
6227 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
6228 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
6229 | " | |
6230 | { | |
2bfcf297 | 6231 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 6232 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 6233 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
266eb58a | 6234 | |
2bfcf297 DB |
6235 | operands[4] = GEN_INT (low); |
6236 | if (CONST_OK_FOR_LETTER_P (rest, 'L')) | |
6237 | operands[3] = GEN_INT (rest); | |
6238 | else if (! no_new_pseudos) | |
38886f37 | 6239 | { |
2bfcf297 DB |
6240 | operands[3] = gen_reg_rtx (DImode); |
6241 | emit_move_insn (operands[3], operands[2]); | |
6242 | emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); | |
6243 | DONE; | |
38886f37 | 6244 | } |
2bfcf297 DB |
6245 | else |
6246 | FAIL; | |
266eb58a DE |
6247 | }") |
6248 | ||
6249 | (define_insn "one_cmpldi2" | |
6250 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6251 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6252 | "TARGET_POWERPC64" | |
6253 | "nor %0,%1,%1") | |
6254 | ||
6255 | (define_insn "" | |
9ebbca7d GK |
6256 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6257 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 6258 | (const_int 0))) |
9ebbca7d | 6259 | (clobber (match_scratch:DI 2 "=r,r"))] |
266eb58a | 6260 | "TARGET_POWERPC64" |
9ebbca7d GK |
6261 | "@ |
6262 | nor. %2,%1,%1 | |
6263 | #" | |
6264 | [(set_attr "type" "compare") | |
6265 | (set_attr "length" "4,8")]) | |
6266 | ||
6267 | (define_split | |
6268 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6269 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6270 | (const_int 0))) | |
6271 | (clobber (match_scratch:DI 2 ""))] | |
6272 | "TARGET_POWERPC64 && reload_completed" | |
6273 | [(set (match_dup 2) | |
6274 | (not:DI (match_dup 1))) | |
6275 | (set (match_dup 0) | |
6276 | (compare:CC (match_dup 2) | |
6277 | (const_int 0)))] | |
6278 | "") | |
266eb58a DE |
6279 | |
6280 | (define_insn "" | |
9ebbca7d GK |
6281 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
6282 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 6283 | (const_int 0))) |
9ebbca7d | 6284 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6285 | (not:DI (match_dup 1)))] |
6286 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6287 | "@ |
6288 | nor. %0,%1,%1 | |
6289 | #" | |
6290 | [(set_attr "type" "compare") | |
6291 | (set_attr "length" "4,8")]) | |
6292 | ||
6293 | (define_split | |
6294 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
6295 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6296 | (const_int 0))) | |
6297 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6298 | (not:DI (match_dup 1)))] | |
6299 | "TARGET_POWERPC64 && reload_completed" | |
6300 | [(set (match_dup 0) | |
6301 | (not:DI (match_dup 1))) | |
6302 | (set (match_dup 2) | |
6303 | (compare:CC (match_dup 0) | |
6304 | (const_int 0)))] | |
6305 | "") | |
266eb58a DE |
6306 | |
6307 | (define_insn "" | |
6308 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6309 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
6310 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
6311 | "TARGET_POWERPC64" | |
6312 | "@ | |
6313 | subf %0,%2,%1 | |
6314 | subfic %0,%2,%1") | |
6315 | ||
6316 | (define_insn "" | |
9ebbca7d GK |
6317 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6318 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6319 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 6320 | (const_int 0))) |
9ebbca7d | 6321 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6322 | "TARGET_POWERPC64" |
9ebbca7d GK |
6323 | "@ |
6324 | subf. %3,%2,%1 | |
6325 | #" | |
6326 | [(set_attr "type" "compare") | |
6327 | (set_attr "length" "4,8")]) | |
6328 | ||
6329 | (define_split | |
6330 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6331 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6332 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6333 | (const_int 0))) | |
6334 | (clobber (match_scratch:DI 3 ""))] | |
6335 | "TARGET_POWERPC64 && reload_completed" | |
6336 | [(set (match_dup 3) | |
6337 | (minus:DI (match_dup 1) (match_dup 2))) | |
6338 | (set (match_dup 0) | |
6339 | (compare:CC (match_dup 3) | |
6340 | (const_int 0)))] | |
6341 | "") | |
266eb58a DE |
6342 | |
6343 | (define_insn "" | |
9ebbca7d GK |
6344 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6345 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6346 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 6347 | (const_int 0))) |
9ebbca7d | 6348 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6349 | (minus:DI (match_dup 1) (match_dup 2)))] |
6350 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6351 | "@ |
6352 | subf. %0,%2,%1 | |
6353 | #" | |
6354 | [(set_attr "type" "compare") | |
6355 | (set_attr "length" "4,8")]) | |
6356 | ||
6357 | (define_split | |
6358 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6359 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6360 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6361 | (const_int 0))) | |
6362 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6363 | (minus:DI (match_dup 1) (match_dup 2)))] | |
6364 | "TARGET_POWERPC64 && reload_completed" | |
6365 | [(set (match_dup 0) | |
6366 | (minus:DI (match_dup 1) (match_dup 2))) | |
6367 | (set (match_dup 3) | |
6368 | (compare:CC (match_dup 0) | |
6369 | (const_int 0)))] | |
6370 | "") | |
266eb58a DE |
6371 | |
6372 | (define_expand "subdi3" | |
6373 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6374 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
2bfcf297 | 6375 | (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))] |
266eb58a DE |
6376 | "" |
6377 | " | |
6378 | { | |
6379 | if (GET_CODE (operands[2]) == CONST_INT) | |
6380 | { | |
6381 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
6382 | negate_rtx (DImode, operands[2]))); | |
6383 | DONE; | |
6384 | } | |
6385 | }") | |
6386 | ||
ea112fc4 | 6387 | (define_insn_and_split "absdi2" |
266eb58a | 6388 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 6389 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) |
266eb58a DE |
6390 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
6391 | "TARGET_POWERPC64" | |
ea112fc4 DE |
6392 | "#" |
6393 | "&& reload_completed" | |
a260abc9 | 6394 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6395 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 6396 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
6397 | "") |
6398 | ||
ea112fc4 | 6399 | (define_insn_and_split "*nabsdi2" |
266eb58a | 6400 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 6401 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) |
266eb58a DE |
6402 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
6403 | "TARGET_POWERPC64" | |
ea112fc4 DE |
6404 | "#" |
6405 | "&& reload_completed" | |
a260abc9 | 6406 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6407 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 6408 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
6409 | "") |
6410 | ||
6411 | (define_expand "negdi2" | |
6412 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6413 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
6414 | "" | |
6415 | "") | |
6416 | ||
6417 | (define_insn "" | |
6418 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6419 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6420 | "TARGET_POWERPC64" | |
6421 | "neg %0,%1") | |
6422 | ||
6423 | (define_insn "" | |
9ebbca7d GK |
6424 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6425 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 6426 | (const_int 0))) |
9ebbca7d | 6427 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 6428 | "TARGET_POWERPC64" |
9ebbca7d GK |
6429 | "@ |
6430 | neg. %2,%1 | |
6431 | #" | |
6432 | [(set_attr "type" "compare") | |
6433 | (set_attr "length" "4,8")]) | |
6434 | ||
6435 | (define_split | |
6436 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6437 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6438 | (const_int 0))) | |
6439 | (clobber (match_scratch:DI 2 ""))] | |
6440 | "TARGET_POWERPC64 && reload_completed" | |
6441 | [(set (match_dup 2) | |
6442 | (neg:DI (match_dup 1))) | |
6443 | (set (match_dup 0) | |
6444 | (compare:CC (match_dup 2) | |
6445 | (const_int 0)))] | |
6446 | "") | |
815cdc52 | 6447 | |
29ae5b89 | 6448 | (define_insn "" |
9ebbca7d GK |
6449 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
6450 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 6451 | (const_int 0))) |
9ebbca7d | 6452 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 6453 | (neg:DI (match_dup 1)))] |
29ae5b89 | 6454 | "TARGET_POWERPC64" |
9ebbca7d GK |
6455 | "@ |
6456 | neg. %0,%1 | |
6457 | #" | |
6458 | [(set_attr "type" "compare") | |
6459 | (set_attr "length" "4,8")]) | |
6460 | ||
6461 | (define_split | |
6462 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
6463 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6464 | (const_int 0))) | |
6465 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6466 | (neg:DI (match_dup 1)))] | |
6467 | "TARGET_POWERPC64 && reload_completed" | |
6468 | [(set (match_dup 0) | |
6469 | (neg:DI (match_dup 1))) | |
6470 | (set (match_dup 2) | |
6471 | (compare:CC (match_dup 0) | |
6472 | (const_int 0)))] | |
6473 | "") | |
266eb58a DE |
6474 | |
6475 | (define_insn "ffsdi2" | |
6476 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
6477 | (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6478 | "TARGET_POWERPC64" | |
6479 | "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64" | |
6480 | [(set_attr "length" "16")]) | |
6481 | ||
6482 | (define_insn "muldi3" | |
6483 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6484 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
6485 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6486 | "TARGET_POWERPC64" | |
6487 | "mulld %0,%1,%2" | |
3cb999d8 | 6488 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6489 | |
6490 | (define_insn "smuldi3_highpart" | |
6491 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6492 | (truncate:DI | |
6493 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
6494 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6495 | (sign_extend:TI | |
6496 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6497 | (const_int 64))))] | |
6498 | "TARGET_POWERPC64" | |
6499 | "mulhd %0,%1,%2" | |
3cb999d8 | 6500 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6501 | |
6502 | (define_insn "umuldi3_highpart" | |
6503 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6504 | (truncate:DI | |
6505 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
6506 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6507 | (zero_extend:TI | |
6508 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6509 | (const_int 64))))] | |
6510 | "TARGET_POWERPC64" | |
6511 | "mulhdu %0,%1,%2" | |
3cb999d8 | 6512 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6513 | |
6514 | (define_expand "divdi3" | |
6515 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6516 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6517 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6518 | "TARGET_POWERPC64" | |
6519 | " | |
6520 | { | |
6521 | if (GET_CODE (operands[2]) == CONST_INT | |
2bfcf297 | 6522 | && INTVAL (operands[2]) > 0 |
266eb58a DE |
6523 | && exact_log2 (INTVAL (operands[2])) >= 0) |
6524 | ; | |
6525 | else | |
6526 | operands[2] = force_reg (DImode, operands[2]); | |
6527 | }") | |
6528 | ||
6529 | (define_expand "moddi3" | |
6530 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6531 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6532 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6533 | "TARGET_POWERPC64" | |
6534 | " | |
6535 | { | |
2bfcf297 | 6536 | int i; |
266eb58a DE |
6537 | rtx temp1; |
6538 | rtx temp2; | |
6539 | ||
2bfcf297 DB |
6540 | if (GET_CODE (operands[2]) != CONST_INT |
6541 | || INTVAL (operands[2]) <= 0 | |
6542 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) | |
266eb58a DE |
6543 | FAIL; |
6544 | ||
6545 | temp1 = gen_reg_rtx (DImode); | |
6546 | temp2 = gen_reg_rtx (DImode); | |
6547 | ||
6548 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6549 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6550 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6551 | DONE; | |
6552 | }") | |
6553 | ||
6554 | (define_insn "" | |
6555 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6556 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
6557 | (match_operand:DI 2 "exact_log2_cint_operand" "N")))] |
6558 | "TARGET_POWERPC64" | |
266eb58a DE |
6559 | "sradi %0,%1,%p2\;addze %0,%0" |
6560 | [(set_attr "length" "8")]) | |
6561 | ||
6562 | (define_insn "" | |
9ebbca7d GK |
6563 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6564 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6565 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6566 | (const_int 0))) |
9ebbca7d | 6567 | (clobber (match_scratch:DI 3 "=r,r"))] |
2bfcf297 | 6568 | "TARGET_POWERPC64" |
9ebbca7d GK |
6569 | "@ |
6570 | sradi %3,%1,%p2\;addze. %3,%3 | |
6571 | #" | |
266eb58a | 6572 | [(set_attr "type" "compare") |
9ebbca7d GK |
6573 | (set_attr "length" "8,12")]) |
6574 | ||
6575 | (define_split | |
6576 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6577 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6578 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6579 | (const_int 0))) |
6580 | (clobber (match_scratch:DI 3 ""))] | |
2bfcf297 | 6581 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6582 | [(set (match_dup 3) |
6583 | (div:DI (match_dup 1) (match_dup 2))) | |
6584 | (set (match_dup 0) | |
6585 | (compare:CC (match_dup 3) | |
6586 | (const_int 0)))] | |
6587 | "") | |
266eb58a DE |
6588 | |
6589 | (define_insn "" | |
9ebbca7d GK |
6590 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6591 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6592 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6593 | (const_int 0))) |
9ebbca7d | 6594 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6595 | (div:DI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 6596 | "TARGET_POWERPC64" |
9ebbca7d GK |
6597 | "@ |
6598 | sradi %0,%1,%p2\;addze. %0,%0 | |
6599 | #" | |
266eb58a | 6600 | [(set_attr "type" "compare") |
9ebbca7d | 6601 | (set_attr "length" "8,12")]) |
266eb58a | 6602 | |
9ebbca7d GK |
6603 | (define_split |
6604 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6605 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6606 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6607 | (const_int 0))) |
6608 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6609 | (div:DI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 6610 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6611 | [(set (match_dup 0) |
6612 | (div:DI (match_dup 1) (match_dup 2))) | |
6613 | (set (match_dup 3) | |
6614 | (compare:CC (match_dup 0) | |
6615 | (const_int 0)))] | |
6616 | "") | |
6617 | ||
6618 | (define_insn "" | |
6619 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6620 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6621 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6622 | "TARGET_POWERPC64" |
6623 | "divd %0,%1,%2" | |
3cb999d8 | 6624 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6625 | |
6626 | (define_insn "udivdi3" | |
6627 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6628 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6629 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6630 | "TARGET_POWERPC64" | |
6631 | "divdu %0,%1,%2" | |
3cb999d8 | 6632 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6633 | |
6634 | (define_insn "rotldi3" | |
6635 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6636 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6637 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6638 | "TARGET_POWERPC64" | |
a66078ee | 6639 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6640 | |
a260abc9 | 6641 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6642 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6643 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6644 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6645 | (const_int 0))) |
9ebbca7d | 6646 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6647 | "TARGET_POWERPC64" |
9ebbca7d GK |
6648 | "@ |
6649 | rld%I2cl. %3,%1,%H2,0 | |
6650 | #" | |
6651 | [(set_attr "type" "delayed_compare") | |
6652 | (set_attr "length" "4,8")]) | |
6653 | ||
6654 | (define_split | |
6655 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6656 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6657 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6658 | (const_int 0))) | |
6659 | (clobber (match_scratch:DI 3 ""))] | |
6660 | "TARGET_POWERPC64 && reload_completed" | |
6661 | [(set (match_dup 3) | |
6662 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6663 | (set (match_dup 0) | |
6664 | (compare:CC (match_dup 3) | |
6665 | (const_int 0)))] | |
6666 | "") | |
266eb58a | 6667 | |
a260abc9 | 6668 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6669 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6670 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6671 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6672 | (const_int 0))) |
9ebbca7d | 6673 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6674 | (rotate:DI (match_dup 1) (match_dup 2)))] |
6675 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6676 | "@ |
6677 | rld%I2cl. %0,%1,%H2,0 | |
6678 | #" | |
6679 | [(set_attr "type" "delayed_compare") | |
6680 | (set_attr "length" "4,8")]) | |
6681 | ||
6682 | (define_split | |
6683 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6684 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6685 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6686 | (const_int 0))) | |
6687 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6688 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6689 | "TARGET_POWERPC64 && reload_completed" | |
6690 | [(set (match_dup 0) | |
6691 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6692 | (set (match_dup 3) | |
6693 | (compare:CC (match_dup 0) | |
6694 | (const_int 0)))] | |
6695 | "") | |
266eb58a | 6696 | |
a260abc9 DE |
6697 | (define_insn "*rotldi3_internal4" |
6698 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6699 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6700 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
6701 | (match_operand:DI 3 "mask64_operand" "S")))] | |
6702 | "TARGET_POWERPC64" | |
6703 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6704 | ||
6705 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6706 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6707 | (compare:CC (and:DI |
9ebbca7d GK |
6708 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6709 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
6710 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
a260abc9 | 6711 | (const_int 0))) |
9ebbca7d | 6712 | (clobber (match_scratch:DI 4 "=r,r"))] |
a260abc9 | 6713 | "TARGET_POWERPC64" |
9ebbca7d GK |
6714 | "@ |
6715 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6716 | #" | |
6717 | [(set_attr "type" "delayed_compare") | |
6718 | (set_attr "length" "4,8")]) | |
6719 | ||
6720 | (define_split | |
6721 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6722 | (compare:CC (and:DI | |
6723 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6724 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6725 | (match_operand:DI 3 "mask64_operand" "")) | |
6726 | (const_int 0))) | |
6727 | (clobber (match_scratch:DI 4 ""))] | |
6728 | "TARGET_POWERPC64 && reload_completed" | |
6729 | [(set (match_dup 4) | |
6730 | (and:DI (rotate:DI (match_dup 1) | |
6731 | (match_dup 2)) | |
6732 | (match_dup 3))) | |
6733 | (set (match_dup 0) | |
6734 | (compare:CC (match_dup 4) | |
6735 | (const_int 0)))] | |
6736 | "") | |
a260abc9 DE |
6737 | |
6738 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6739 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6740 | (compare:CC (and:DI |
9ebbca7d GK |
6741 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6742 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
6743 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
a260abc9 | 6744 | (const_int 0))) |
9ebbca7d | 6745 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6746 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
6747 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6748 | "@ |
6749 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6750 | #" | |
6751 | [(set_attr "type" "delayed_compare") | |
6752 | (set_attr "length" "4,8")]) | |
6753 | ||
6754 | (define_split | |
6755 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6756 | (compare:CC (and:DI | |
6757 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6758 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6759 | (match_operand:DI 3 "mask64_operand" "")) | |
6760 | (const_int 0))) | |
6761 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6762 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6763 | "TARGET_POWERPC64 && reload_completed" | |
6764 | [(set (match_dup 0) | |
6765 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6766 | (set (match_dup 4) | |
6767 | (compare:CC (match_dup 0) | |
6768 | (const_int 0)))] | |
6769 | "") | |
a260abc9 DE |
6770 | |
6771 | (define_insn "*rotldi3_internal7" | |
6772 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6773 | (zero_extend:DI | |
6774 | (subreg:QI | |
6775 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6776 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6777 | "TARGET_POWERPC64" | |
6778 | "rld%I2cl %0,%1,%H2,56") | |
6779 | ||
6780 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6781 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6782 | (compare:CC (zero_extend:DI |
6783 | (subreg:QI | |
9ebbca7d GK |
6784 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6785 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6786 | (const_int 0))) |
9ebbca7d | 6787 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6788 | "TARGET_POWERPC64" |
9ebbca7d GK |
6789 | "@ |
6790 | rld%I2cl. %3,%1,%H2,56 | |
6791 | #" | |
6792 | [(set_attr "type" "delayed_compare") | |
6793 | (set_attr "length" "4,8")]) | |
6794 | ||
6795 | (define_split | |
6796 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6797 | (compare:CC (zero_extend:DI | |
6798 | (subreg:QI | |
6799 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6800 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6801 | (const_int 0))) | |
6802 | (clobber (match_scratch:DI 3 ""))] | |
6803 | "TARGET_POWERPC64 && reload_completed" | |
6804 | [(set (match_dup 3) | |
6805 | (zero_extend:DI (subreg:QI | |
6806 | (rotate:DI (match_dup 1) | |
6807 | (match_dup 2)) 0))) | |
6808 | (set (match_dup 0) | |
6809 | (compare:CC (match_dup 3) | |
6810 | (const_int 0)))] | |
6811 | "") | |
a260abc9 DE |
6812 | |
6813 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6814 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6815 | (compare:CC (zero_extend:DI |
6816 | (subreg:QI | |
9ebbca7d GK |
6817 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6818 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6819 | (const_int 0))) |
9ebbca7d | 6820 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6821 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6822 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6823 | "@ |
6824 | rld%I2cl. %0,%1,%H2,56 | |
6825 | #" | |
6826 | [(set_attr "type" "delayed_compare") | |
6827 | (set_attr "length" "4,8")]) | |
6828 | ||
6829 | (define_split | |
6830 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6831 | (compare:CC (zero_extend:DI | |
6832 | (subreg:QI | |
6833 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6834 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6835 | (const_int 0))) | |
6836 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6837 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6838 | "TARGET_POWERPC64 && reload_completed" | |
6839 | [(set (match_dup 0) | |
6840 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6841 | (set (match_dup 3) | |
6842 | (compare:CC (match_dup 0) | |
6843 | (const_int 0)))] | |
6844 | "") | |
a260abc9 DE |
6845 | |
6846 | (define_insn "*rotldi3_internal10" | |
6847 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6848 | (zero_extend:DI | |
6849 | (subreg:HI | |
6850 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6851 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6852 | "TARGET_POWERPC64" | |
6853 | "rld%I2cl %0,%1,%H2,48") | |
6854 | ||
6855 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6856 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6857 | (compare:CC (zero_extend:DI |
6858 | (subreg:HI | |
9ebbca7d GK |
6859 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6860 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6861 | (const_int 0))) |
9ebbca7d | 6862 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6863 | "TARGET_POWERPC64" |
9ebbca7d GK |
6864 | "@ |
6865 | rld%I2cl. %3,%1,%H2,48 | |
6866 | #" | |
6867 | [(set_attr "type" "delayed_compare") | |
6868 | (set_attr "length" "4,8")]) | |
6869 | ||
6870 | (define_split | |
6871 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6872 | (compare:CC (zero_extend:DI | |
6873 | (subreg:HI | |
6874 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6875 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6876 | (const_int 0))) | |
6877 | (clobber (match_scratch:DI 3 ""))] | |
6878 | "TARGET_POWERPC64 && reload_completed" | |
6879 | [(set (match_dup 3) | |
6880 | (zero_extend:DI (subreg:HI | |
6881 | (rotate:DI (match_dup 1) | |
6882 | (match_dup 2)) 0))) | |
6883 | (set (match_dup 0) | |
6884 | (compare:CC (match_dup 3) | |
6885 | (const_int 0)))] | |
6886 | "") | |
a260abc9 DE |
6887 | |
6888 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6889 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6890 | (compare:CC (zero_extend:DI |
6891 | (subreg:HI | |
9ebbca7d GK |
6892 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6893 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6894 | (const_int 0))) |
9ebbca7d | 6895 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6896 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6897 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6898 | "@ |
6899 | rld%I2cl. %0,%1,%H2,48 | |
6900 | #" | |
6901 | [(set_attr "type" "delayed_compare") | |
6902 | (set_attr "length" "4,8")]) | |
6903 | ||
6904 | (define_split | |
6905 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6906 | (compare:CC (zero_extend:DI | |
6907 | (subreg:HI | |
6908 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6909 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6910 | (const_int 0))) | |
6911 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6912 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6913 | "TARGET_POWERPC64 && reload_completed" | |
6914 | [(set (match_dup 0) | |
6915 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6916 | (set (match_dup 3) | |
6917 | (compare:CC (match_dup 0) | |
6918 | (const_int 0)))] | |
6919 | "") | |
a260abc9 DE |
6920 | |
6921 | (define_insn "*rotldi3_internal13" | |
6922 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6923 | (zero_extend:DI | |
6924 | (subreg:SI | |
6925 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6926 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6927 | "TARGET_POWERPC64" | |
6928 | "rld%I2cl %0,%1,%H2,32") | |
6929 | ||
6930 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6931 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6932 | (compare:CC (zero_extend:DI |
6933 | (subreg:SI | |
9ebbca7d GK |
6934 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6935 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6936 | (const_int 0))) |
9ebbca7d | 6937 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6938 | "TARGET_POWERPC64" |
9ebbca7d GK |
6939 | "@ |
6940 | rld%I2cl. %3,%1,%H2,32 | |
6941 | #" | |
6942 | [(set_attr "type" "delayed_compare") | |
6943 | (set_attr "length" "4,8")]) | |
6944 | ||
6945 | (define_split | |
6946 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6947 | (compare:CC (zero_extend:DI | |
6948 | (subreg:SI | |
6949 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6950 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6951 | (const_int 0))) | |
6952 | (clobber (match_scratch:DI 3 ""))] | |
6953 | "TARGET_POWERPC64 && reload_completed" | |
6954 | [(set (match_dup 3) | |
6955 | (zero_extend:DI (subreg:SI | |
6956 | (rotate:DI (match_dup 1) | |
6957 | (match_dup 2)) 0))) | |
6958 | (set (match_dup 0) | |
6959 | (compare:CC (match_dup 3) | |
6960 | (const_int 0)))] | |
6961 | "") | |
a260abc9 DE |
6962 | |
6963 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6964 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6965 | (compare:CC (zero_extend:DI |
6966 | (subreg:SI | |
9ebbca7d GK |
6967 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6968 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6969 | (const_int 0))) |
9ebbca7d | 6970 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6971 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6972 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6973 | "@ |
6974 | rld%I2cl. %0,%1,%H2,32 | |
6975 | #" | |
6976 | [(set_attr "type" "delayed_compare") | |
6977 | (set_attr "length" "4,8")]) | |
6978 | ||
6979 | (define_split | |
6980 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6981 | (compare:CC (zero_extend:DI | |
6982 | (subreg:SI | |
6983 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6984 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6985 | (const_int 0))) | |
6986 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6987 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6988 | "TARGET_POWERPC64 && reload_completed" | |
6989 | [(set (match_dup 0) | |
6990 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6991 | (set (match_dup 3) | |
6992 | (compare:CC (match_dup 0) | |
6993 | (const_int 0)))] | |
6994 | "") | |
a260abc9 | 6995 | |
266eb58a DE |
6996 | (define_expand "ashldi3" |
6997 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6998 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6999 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
7000 | "TARGET_POWERPC64 || TARGET_POWER" | |
7001 | " | |
7002 | { | |
7003 | if (TARGET_POWERPC64) | |
7004 | ; | |
7005 | else if (TARGET_POWER) | |
7006 | { | |
7007 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
7008 | DONE; | |
7009 | } | |
7010 | else | |
7011 | FAIL; | |
7012 | }") | |
7013 | ||
e2c953b6 | 7014 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
7015 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7016 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7017 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
7018 | "TARGET_POWERPC64" | |
a66078ee | 7019 | "sld%I2 %0,%1,%H2" |
266eb58a DE |
7020 | [(set_attr "length" "8")]) |
7021 | ||
e2c953b6 | 7022 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
7023 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
7024 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7025 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7026 | (const_int 0))) |
9ebbca7d | 7027 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7028 | "TARGET_POWERPC64" |
9ebbca7d GK |
7029 | "@ |
7030 | sld%I2. %3,%1,%H2 | |
7031 | #" | |
7032 | [(set_attr "type" "delayed_compare") | |
7033 | (set_attr "length" "4,8")]) | |
29ae5b89 | 7034 | |
9ebbca7d GK |
7035 | (define_split |
7036 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7037 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7038 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7039 | (const_int 0))) | |
7040 | (clobber (match_scratch:DI 3 ""))] | |
7041 | "TARGET_POWERPC64 && reload_completed" | |
7042 | [(set (match_dup 3) | |
7043 | (ashift:DI (match_dup 1) (match_dup 2))) | |
7044 | (set (match_dup 0) | |
7045 | (compare:CC (match_dup 3) | |
7046 | (const_int 0)))] | |
7047 | "") | |
7048 | ||
e2c953b6 | 7049 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
7050 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7051 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7052 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7053 | (const_int 0))) |
9ebbca7d | 7054 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
7055 | (ashift:DI (match_dup 1) (match_dup 2)))] |
7056 | "TARGET_POWERPC64" | |
9ebbca7d GK |
7057 | "@ |
7058 | sld%I2. %0,%1,%H2 | |
7059 | #" | |
7060 | [(set_attr "type" "delayed_compare") | |
7061 | (set_attr "length" "4,8")]) | |
7062 | ||
7063 | (define_split | |
7064 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7065 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7066 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7067 | (const_int 0))) | |
7068 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7069 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
7070 | "TARGET_POWERPC64 && reload_completed" | |
7071 | [(set (match_dup 0) | |
7072 | (ashift:DI (match_dup 1) (match_dup 2))) | |
7073 | (set (match_dup 3) | |
7074 | (compare:CC (match_dup 0) | |
7075 | (const_int 0)))] | |
7076 | "") | |
266eb58a | 7077 | |
e2c953b6 | 7078 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
7079 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7080 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7081 | (match_operand:SI 2 "const_int_operand" "i")) | |
c5059423 AM |
7082 | (match_operand:DI 3 "const_int_operand" "n")))] |
7083 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" | |
e2c953b6 | 7084 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 7085 | |
e2c953b6 | 7086 | (define_insn "ashldi3_internal5" |
9ebbca7d | 7087 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 7088 | (compare:CC |
9ebbca7d GK |
7089 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
7090 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 7091 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 7092 | (const_int 0))) |
9ebbca7d | 7093 | (clobber (match_scratch:DI 4 "=r,r"))] |
c5059423 | 7094 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 7095 | "@ |
e2c953b6 | 7096 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
7097 | #" |
7098 | [(set_attr "type" "delayed_compare") | |
7099 | (set_attr "length" "4,8")]) | |
7100 | ||
7101 | (define_split | |
7102 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7103 | (compare:CC | |
7104 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7105 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 7106 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
7107 | (const_int 0))) |
7108 | (clobber (match_scratch:DI 4 ""))] | |
c5059423 AM |
7109 | "TARGET_POWERPC64 && reload_completed |
7110 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
9ebbca7d GK |
7111 | [(set (match_dup 4) |
7112 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 7113 | (match_dup 3))) |
9ebbca7d GK |
7114 | (set (match_dup 0) |
7115 | (compare:CC (match_dup 4) | |
7116 | (const_int 0)))] | |
7117 | "") | |
3cb999d8 | 7118 | |
e2c953b6 | 7119 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 7120 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 7121 | (compare:CC |
9ebbca7d GK |
7122 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
7123 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 7124 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 7125 | (const_int 0))) |
9ebbca7d | 7126 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 7127 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
c5059423 | 7128 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 7129 | "@ |
e2c953b6 | 7130 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
7131 | #" |
7132 | [(set_attr "type" "delayed_compare") | |
7133 | (set_attr "length" "4,8")]) | |
7134 | ||
7135 | (define_split | |
7136 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
7137 | (compare:CC | |
7138 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7139 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 7140 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
7141 | (const_int 0))) |
7142 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7143 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
c5059423 AM |
7144 | "TARGET_POWERPC64 && reload_completed |
7145 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
7146 | [(set (match_dup 0) | |
7147 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
7148 | (match_dup 3))) | |
7149 | (set (match_dup 4) | |
7150 | (compare:CC (match_dup 0) | |
7151 | (const_int 0)))] | |
7152 | "") | |
7153 | ||
7154 | (define_insn "*ashldi3_internal7" | |
7155 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
7156 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7157 | (match_operand:SI 2 "const_int_operand" "i")) | |
7158 | (match_operand:DI 3 "mask64_operand" "S")))] | |
7159 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" | |
7160 | "rldicr %0,%1,%H2,%S3") | |
7161 | ||
7162 | (define_insn "ashldi3_internal8" | |
7163 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
7164 | (compare:CC | |
7165 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7166 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
7167 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
7168 | (const_int 0))) | |
7169 | (clobber (match_scratch:DI 4 "=r,r"))] | |
7170 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" | |
7171 | "@ | |
7172 | rldicr. %4,%1,%H2,%S3 | |
7173 | #" | |
7174 | [(set_attr "type" "delayed_compare") | |
7175 | (set_attr "length" "4,8")]) | |
7176 | ||
7177 | (define_split | |
7178 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7179 | (compare:CC | |
7180 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7181 | (match_operand:SI 2 "const_int_operand" "")) | |
7182 | (match_operand:DI 3 "mask64_operand" "")) | |
7183 | (const_int 0))) | |
7184 | (clobber (match_scratch:DI 4 ""))] | |
7185 | "TARGET_POWERPC64 && reload_completed | |
7186 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
7187 | [(set (match_dup 4) | |
7188 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
7189 | (match_dup 3))) | |
7190 | (set (match_dup 0) | |
7191 | (compare:CC (match_dup 4) | |
7192 | (const_int 0)))] | |
7193 | "") | |
7194 | ||
7195 | (define_insn "*ashldi3_internal9" | |
7196 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
7197 | (compare:CC | |
7198 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7199 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
7200 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
7201 | (const_int 0))) | |
7202 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
7203 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
7204 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" | |
7205 | "@ | |
7206 | rldicr. %0,%1,%H2,%S3 | |
7207 | #" | |
7208 | [(set_attr "type" "delayed_compare") | |
7209 | (set_attr "length" "4,8")]) | |
7210 | ||
7211 | (define_split | |
7212 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
7213 | (compare:CC | |
7214 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7215 | (match_operand:SI 2 "const_int_operand" "")) | |
7216 | (match_operand:DI 3 "mask64_operand" "")) | |
7217 | (const_int 0))) | |
7218 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7219 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
7220 | "TARGET_POWERPC64 && reload_completed | |
7221 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
9ebbca7d | 7222 | [(set (match_dup 0) |
e2c953b6 DE |
7223 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
7224 | (match_dup 3))) | |
9ebbca7d GK |
7225 | (set (match_dup 4) |
7226 | (compare:CC (match_dup 0) | |
7227 | (const_int 0)))] | |
7228 | "") | |
7229 | ||
7230 | (define_expand "lshrdi3" | |
266eb58a DE |
7231 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
7232 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7233 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
7234 | "TARGET_POWERPC64 || TARGET_POWER" | |
7235 | " | |
7236 | { | |
7237 | if (TARGET_POWERPC64) | |
7238 | ; | |
7239 | else if (TARGET_POWER) | |
7240 | { | |
7241 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
7242 | DONE; | |
7243 | } | |
7244 | else | |
7245 | FAIL; | |
7246 | }") | |
7247 | ||
e2c953b6 | 7248 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
7249 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7250 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7251 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
7252 | "TARGET_POWERPC64" | |
a66078ee | 7253 | "srd%I2 %0,%1,%H2") |
266eb58a | 7254 | |
e2c953b6 | 7255 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
7256 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
7257 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7258 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 7259 | (const_int 0))) |
9ebbca7d | 7260 | (clobber (match_scratch:DI 3 "=r,r"))] |
29ae5b89 | 7261 | "TARGET_POWERPC64" |
9ebbca7d GK |
7262 | "@ |
7263 | srd%I2. %3,%1,%H2 | |
7264 | #" | |
7265 | [(set_attr "type" "delayed_compare") | |
7266 | (set_attr "length" "4,8")]) | |
7267 | ||
7268 | (define_split | |
7269 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7270 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7271 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7272 | (const_int 0))) | |
7273 | (clobber (match_scratch:DI 3 ""))] | |
7274 | "TARGET_POWERPC64 && reload_completed" | |
7275 | [(set (match_dup 3) | |
7276 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
7277 | (set (match_dup 0) | |
7278 | (compare:CC (match_dup 3) | |
7279 | (const_int 0)))] | |
7280 | "") | |
266eb58a | 7281 | |
e2c953b6 | 7282 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
7283 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7284 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7285 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7286 | (const_int 0))) |
9ebbca7d | 7287 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 JL |
7288 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
7289 | "TARGET_POWERPC64" | |
9ebbca7d GK |
7290 | "@ |
7291 | srd%I2. %0,%1,%H2 | |
7292 | #" | |
7293 | [(set_attr "type" "delayed_compare") | |
7294 | (set_attr "length" "4,8")]) | |
7295 | ||
7296 | (define_split | |
7297 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7298 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7299 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7300 | (const_int 0))) | |
7301 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7302 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
7303 | "TARGET_POWERPC64 && reload_completed" | |
7304 | [(set (match_dup 0) | |
7305 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
7306 | (set (match_dup 3) | |
7307 | (compare:CC (match_dup 0) | |
7308 | (const_int 0)))] | |
7309 | "") | |
266eb58a DE |
7310 | |
7311 | (define_expand "ashrdi3" | |
7312 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7313 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7314 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4aa74a4f | 7315 | "" |
266eb58a DE |
7316 | " |
7317 | { | |
7318 | if (TARGET_POWERPC64) | |
7319 | ; | |
7320 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
7321 | { | |
7322 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
7323 | DONE; | |
7324 | } | |
4aa74a4f FS |
7325 | else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT) |
7326 | { | |
7327 | emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); | |
7328 | DONE; | |
7329 | } | |
266eb58a DE |
7330 | else |
7331 | FAIL; | |
7332 | }") | |
7333 | ||
e2c953b6 | 7334 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
7335 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7336 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7337 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
7338 | "TARGET_POWERPC64" | |
375490e0 | 7339 | "srad%I2 %0,%1,%H2") |
266eb58a | 7340 | |
e2c953b6 | 7341 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
7342 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
7343 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7344 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7345 | (const_int 0))) |
9ebbca7d | 7346 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7347 | "TARGET_POWERPC64" |
9ebbca7d GK |
7348 | "@ |
7349 | srad%I2. %3,%1,%H2 | |
7350 | #" | |
7351 | [(set_attr "type" "delayed_compare") | |
7352 | (set_attr "length" "4,8")]) | |
7353 | ||
7354 | (define_split | |
7355 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7356 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7357 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7358 | (const_int 0))) | |
7359 | (clobber (match_scratch:DI 3 ""))] | |
7360 | "TARGET_POWERPC64 && reload_completed" | |
7361 | [(set (match_dup 3) | |
7362 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7363 | (set (match_dup 0) | |
7364 | (compare:CC (match_dup 3) | |
7365 | (const_int 0)))] | |
7366 | "") | |
266eb58a | 7367 | |
e2c953b6 | 7368 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
7369 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7370 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7371 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7372 | (const_int 0))) |
9ebbca7d | 7373 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
7374 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
7375 | "TARGET_POWERPC64" | |
9ebbca7d GK |
7376 | "@ |
7377 | srad%I2. %0,%1,%H2 | |
7378 | #" | |
7379 | [(set_attr "type" "delayed_compare") | |
7380 | (set_attr "length" "4,8")]) | |
7381 | ||
7382 | (define_split | |
7383 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7384 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7385 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7386 | (const_int 0))) | |
7387 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7388 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
7389 | "TARGET_POWERPC64 && reload_completed" | |
7390 | [(set (match_dup 0) | |
7391 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7392 | (set (match_dup 3) | |
7393 | (compare:CC (match_dup 0) | |
7394 | (const_int 0)))] | |
7395 | "") | |
815cdc52 | 7396 | |
29ae5b89 | 7397 | (define_insn "anddi3" |
0ba1b2ff AM |
7398 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") |
7399 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
7400 | (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t"))) | |
7401 | (clobber (match_scratch:CC 3 "=X,X,x,x,X"))] | |
6ffc8580 | 7402 | "TARGET_POWERPC64" |
266eb58a DE |
7403 | "@ |
7404 | and %0,%1,%2 | |
29ae5b89 JL |
7405 | rldic%B2 %0,%1,0,%S2 |
7406 | andi. %0,%1,%b2 | |
0ba1b2ff AM |
7407 | andis. %0,%1,%u2 |
7408 | #" | |
7409 | [(set_attr "length" "4,4,4,4,8")]) | |
7410 | ||
7411 | (define_split | |
7412 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7413 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7414 | (match_operand:DI 2 "mask64_2_operand" ""))) | |
7415 | (clobber (match_scratch:CC 3 ""))] | |
7416 | "TARGET_POWERPC64 | |
7417 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7418 | && !mask64_operand (operands[2], DImode)" | |
7419 | [(set (match_dup 0) | |
7420 | (and:DI (rotate:DI (match_dup 1) | |
7421 | (match_dup 4)) | |
7422 | (match_dup 5))) | |
7423 | (set (match_dup 0) | |
7424 | (and:DI (rotate:DI (match_dup 0) | |
7425 | (match_dup 6)) | |
7426 | (match_dup 7)))] | |
7427 | " | |
7428 | { | |
7429 | build_mask64_2_operands (operands[2], &operands[4]); | |
7430 | }") | |
266eb58a | 7431 | |
a260abc9 | 7432 | (define_insn "*anddi3_internal2" |
0ba1b2ff AM |
7433 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7434 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7435 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7436 | (const_int 0))) |
0ba1b2ff AM |
7437 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r")) |
7438 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] | |
6ffc8580 | 7439 | "TARGET_POWERPC64" |
266eb58a DE |
7440 | "@ |
7441 | and. %3,%1,%2 | |
6c873122 | 7442 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
7443 | andi. %3,%1,%b2 |
7444 | andis. %3,%1,%u2 | |
9ebbca7d GK |
7445 | # |
7446 | # | |
7447 | # | |
0ba1b2ff AM |
7448 | # |
7449 | # | |
9ebbca7d | 7450 | #" |
0ba1b2ff AM |
7451 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7452 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7453 | |
7454 | (define_split | |
7455 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7456 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7457 | (match_operand:DI 2 "and64_operand" "")) | |
7458 | (const_int 0))) | |
7459 | (clobber (match_scratch:DI 3 "")) | |
7460 | (clobber (match_scratch:CC 4 ""))] | |
7461 | "TARGET_POWERPC64 && reload_completed" | |
7462 | [(parallel [(set (match_dup 3) | |
7463 | (and:DI (match_dup 1) | |
7464 | (match_dup 2))) | |
7465 | (clobber (match_dup 4))]) | |
7466 | (set (match_dup 0) | |
7467 | (compare:CC (match_dup 3) | |
7468 | (const_int 0)))] | |
7469 | "") | |
266eb58a | 7470 | |
0ba1b2ff AM |
7471 | (define_split |
7472 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
7473 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7474 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7475 | (const_int 0))) | |
7476 | (clobber (match_scratch:DI 3 "")) | |
7477 | (clobber (match_scratch:CC 4 ""))] | |
7478 | "TARGET_POWERPC64 && reload_completed | |
7479 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7480 | && !mask64_operand (operands[2], DImode)" | |
7481 | [(set (match_dup 3) | |
7482 | (and:DI (rotate:DI (match_dup 1) | |
7483 | (match_dup 5)) | |
7484 | (match_dup 6))) | |
7485 | (parallel [(set (match_dup 0) | |
7486 | (compare:CC (and:DI (rotate:DI (match_dup 3) | |
7487 | (match_dup 7)) | |
7488 | (match_dup 8)) | |
7489 | (const_int 0))) | |
7490 | (clobber (match_dup 3))])] | |
7491 | " | |
7492 | { | |
7493 | build_mask64_2_operands (operands[2], &operands[5]); | |
7494 | }") | |
7495 | ||
a260abc9 | 7496 | (define_insn "*anddi3_internal3" |
0ba1b2ff AM |
7497 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7498 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7499 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7500 | (const_int 0))) |
0ba1b2ff | 7501 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
9ebbca7d | 7502 | (and:DI (match_dup 1) (match_dup 2))) |
0ba1b2ff | 7503 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] |
6ffc8580 | 7504 | "TARGET_POWERPC64" |
266eb58a DE |
7505 | "@ |
7506 | and. %0,%1,%2 | |
6c873122 | 7507 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
7508 | andi. %0,%1,%b2 |
7509 | andis. %0,%1,%u2 | |
9ebbca7d GK |
7510 | # |
7511 | # | |
7512 | # | |
0ba1b2ff AM |
7513 | # |
7514 | # | |
9ebbca7d | 7515 | #" |
0ba1b2ff AM |
7516 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7517 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7518 | |
7519 | (define_split | |
7520 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7521 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7522 | (match_operand:DI 2 "and64_operand" "")) | |
7523 | (const_int 0))) | |
7524 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7525 | (and:DI (match_dup 1) (match_dup 2))) | |
7526 | (clobber (match_scratch:CC 4 ""))] | |
7527 | "TARGET_POWERPC64 && reload_completed" | |
7528 | [(parallel [(set (match_dup 0) | |
7529 | (and:DI (match_dup 1) (match_dup 2))) | |
7530 | (clobber (match_dup 4))]) | |
7531 | (set (match_dup 3) | |
7532 | (compare:CC (match_dup 0) | |
7533 | (const_int 0)))] | |
7534 | "") | |
266eb58a | 7535 | |
0ba1b2ff AM |
7536 | (define_split |
7537 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
7538 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7539 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7540 | (const_int 0))) | |
7541 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7542 | (and:DI (match_dup 1) (match_dup 2))) | |
7543 | (clobber (match_scratch:CC 4 ""))] | |
7544 | "TARGET_POWERPC64 && reload_completed | |
7545 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7546 | && !mask64_operand (operands[2], DImode)" | |
7547 | [(set (match_dup 0) | |
7548 | (and:DI (rotate:DI (match_dup 1) | |
7549 | (match_dup 5)) | |
7550 | (match_dup 6))) | |
7551 | (parallel [(set (match_dup 3) | |
7552 | (compare:CC (and:DI (rotate:DI (match_dup 0) | |
7553 | (match_dup 7)) | |
7554 | (match_dup 8)) | |
7555 | (const_int 0))) | |
7556 | (set (match_dup 0) | |
7557 | (and:DI (rotate:DI (match_dup 0) | |
7558 | (match_dup 7)) | |
7559 | (match_dup 8)))])] | |
7560 | " | |
7561 | { | |
7562 | build_mask64_2_operands (operands[2], &operands[5]); | |
7563 | }") | |
7564 | ||
a260abc9 | 7565 | (define_expand "iordi3" |
266eb58a | 7566 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 7567 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 7568 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 7569 | "TARGET_POWERPC64" |
266eb58a DE |
7570 | " |
7571 | { | |
dfbdccdb | 7572 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 7573 | { |
dfbdccdb | 7574 | HOST_WIDE_INT value; |
677a9668 | 7575 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 7576 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 7577 | |
dfbdccdb GK |
7578 | if (GET_CODE (operands[2]) == CONST_INT) |
7579 | { | |
7580 | value = INTVAL (operands[2]); | |
7581 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7582 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7583 | } | |
e2c953b6 | 7584 | else |
dfbdccdb GK |
7585 | { |
7586 | value = CONST_DOUBLE_LOW (operands[2]); | |
7587 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7588 | immed_double_const (value | |
7589 | & (~ (HOST_WIDE_INT) 0xffff), | |
7590 | 0, DImode))); | |
7591 | } | |
e2c953b6 | 7592 | |
9ebbca7d GK |
7593 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7594 | DONE; | |
7595 | } | |
266eb58a DE |
7596 | }") |
7597 | ||
a260abc9 DE |
7598 | (define_expand "xordi3" |
7599 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7600 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 7601 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
7602 | "TARGET_POWERPC64" |
7603 | " | |
7604 | { | |
dfbdccdb | 7605 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 7606 | { |
dfbdccdb | 7607 | HOST_WIDE_INT value; |
677a9668 | 7608 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
7609 | ? operands[0] : gen_reg_rtx (DImode)); |
7610 | ||
dfbdccdb GK |
7611 | if (GET_CODE (operands[2]) == CONST_INT) |
7612 | { | |
7613 | value = INTVAL (operands[2]); | |
7614 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7615 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7616 | } | |
e2c953b6 | 7617 | else |
dfbdccdb GK |
7618 | { |
7619 | value = CONST_DOUBLE_LOW (operands[2]); | |
7620 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7621 | immed_double_const (value | |
7622 | & (~ (HOST_WIDE_INT) 0xffff), | |
7623 | 0, DImode))); | |
7624 | } | |
e2c953b6 | 7625 | |
9ebbca7d GK |
7626 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7627 | DONE; | |
7628 | } | |
a260abc9 DE |
7629 | }") |
7630 | ||
dfbdccdb | 7631 | (define_insn "*booldi3_internal1" |
266eb58a | 7632 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 7633 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7634 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
7635 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 7636 | "TARGET_POWERPC64" |
1fd4e8c1 | 7637 | "@ |
dfbdccdb GK |
7638 | %q3 %0,%1,%2 |
7639 | %q3i %0,%1,%b2 | |
7640 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 7641 | |
dfbdccdb | 7642 | (define_insn "*booldi3_internal2" |
9ebbca7d | 7643 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 7644 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
7645 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
7646 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7647 | (const_int 0))) | |
9ebbca7d | 7648 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7649 | "TARGET_POWERPC64" |
9ebbca7d | 7650 | "@ |
dfbdccdb | 7651 | %q4. %3,%1,%2 |
9ebbca7d GK |
7652 | #" |
7653 | [(set_attr "type" "compare") | |
7654 | (set_attr "length" "4,8")]) | |
7655 | ||
7656 | (define_split | |
7657 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7658 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7659 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7660 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7661 | (const_int 0))) |
9ebbca7d GK |
7662 | (clobber (match_scratch:DI 3 ""))] |
7663 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7664 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7665 | (set (match_dup 0) |
7666 | (compare:CC (match_dup 3) | |
7667 | (const_int 0)))] | |
7668 | "") | |
1fd4e8c1 | 7669 | |
dfbdccdb | 7670 | (define_insn "*booldi3_internal3" |
9ebbca7d | 7671 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7672 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7673 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7674 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7675 | (const_int 0))) | |
9ebbca7d | 7676 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7677 | (match_dup 4))] |
266eb58a | 7678 | "TARGET_POWERPC64" |
9ebbca7d | 7679 | "@ |
dfbdccdb | 7680 | %q4. %0,%1,%2 |
9ebbca7d GK |
7681 | #" |
7682 | [(set_attr "type" "compare") | |
7683 | (set_attr "length" "4,8")]) | |
7684 | ||
7685 | (define_split | |
e72247f4 | 7686 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7687 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7688 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7689 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7690 | (const_int 0))) |
75540af0 | 7691 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7692 | (match_dup 4))] |
9ebbca7d | 7693 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7694 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7695 | (set (match_dup 3) |
7696 | (compare:CC (match_dup 0) | |
7697 | (const_int 0)))] | |
7698 | "") | |
1fd4e8c1 | 7699 | |
dfbdccdb GK |
7700 | ;; Split an logical operation that we can't do in one insn into two insns, |
7701 | ;; each of which does one 16-bit part. This is used by combine. | |
266eb58a DE |
7702 | |
7703 | (define_split | |
7704 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 7705 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7706 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7707 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7708 | "TARGET_POWERPC64" |
dfbdccdb GK |
7709 | [(set (match_dup 0) (match_dup 4)) |
7710 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7711 | " |
7712 | { | |
dfbdccdb GK |
7713 | rtx i3,i4; |
7714 | ||
9ebbca7d GK |
7715 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7716 | { | |
7717 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7718 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7719 | 0, DImode); |
dfbdccdb | 7720 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7721 | } |
7722 | else | |
7723 | { | |
dfbdccdb | 7724 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7725 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7726 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7727 | } |
dfbdccdb GK |
7728 | operands[4] = gen_rtx (GET_CODE (operands[3]), DImode, |
7729 | operands[1], i3); | |
7730 | operands[5] = gen_rtx (GET_CODE (operands[3]), DImode, | |
7731 | operands[0], i4); | |
1fd4e8c1 RK |
7732 | }") |
7733 | ||
dfbdccdb | 7734 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7735 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7736 | (match_operator:DI 3 "boolean_operator" |
7737 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7738 | (match_operand:DI 2 "gpc_reg_operand" "r")]))] |
a473029f | 7739 | "TARGET_POWERPC64" |
1d328b19 | 7740 | "%q3 %0,%2,%1") |
a473029f | 7741 | |
dfbdccdb | 7742 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7743 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7744 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7745 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7746 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7747 | (const_int 0))) | |
9ebbca7d | 7748 | (clobber (match_scratch:DI 3 "=r,r"))] |
a473029f | 7749 | "TARGET_POWERPC64" |
9ebbca7d | 7750 | "@ |
1d328b19 | 7751 | %q4. %3,%2,%1 |
9ebbca7d GK |
7752 | #" |
7753 | [(set_attr "type" "compare") | |
7754 | (set_attr "length" "4,8")]) | |
7755 | ||
7756 | (define_split | |
7757 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7758 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7759 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7760 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7761 | (const_int 0))) |
9ebbca7d GK |
7762 | (clobber (match_scratch:DI 3 ""))] |
7763 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7764 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7765 | (set (match_dup 0) |
7766 | (compare:CC (match_dup 3) | |
7767 | (const_int 0)))] | |
7768 | "") | |
a473029f | 7769 | |
dfbdccdb | 7770 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7771 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7772 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7773 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7774 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7775 | (const_int 0))) | |
9ebbca7d | 7776 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7777 | (match_dup 4))] |
a473029f | 7778 | "TARGET_POWERPC64" |
9ebbca7d | 7779 | "@ |
1d328b19 | 7780 | %q4. %0,%2,%1 |
9ebbca7d GK |
7781 | #" |
7782 | [(set_attr "type" "compare") | |
7783 | (set_attr "length" "4,8")]) | |
7784 | ||
7785 | (define_split | |
e72247f4 | 7786 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7787 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7788 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7789 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7790 | (const_int 0))) |
75540af0 | 7791 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7792 | (match_dup 4))] |
9ebbca7d | 7793 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7794 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7795 | (set (match_dup 3) |
7796 | (compare:CC (match_dup 0) | |
7797 | (const_int 0)))] | |
7798 | "") | |
266eb58a | 7799 | |
dfbdccdb | 7800 | (define_insn "*boolccdi3_internal1" |
a473029f | 7801 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7802 | (match_operator:DI 3 "boolean_operator" |
7803 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7804 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] |
a473029f | 7805 | "TARGET_POWERPC64" |
dfbdccdb | 7806 | "%q3 %0,%1,%2") |
a473029f | 7807 | |
dfbdccdb | 7808 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7809 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7810 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7811 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7812 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7813 | (const_int 0))) | |
9ebbca7d | 7814 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7815 | "TARGET_POWERPC64" |
9ebbca7d | 7816 | "@ |
dfbdccdb | 7817 | %q4. %3,%1,%2 |
9ebbca7d GK |
7818 | #" |
7819 | [(set_attr "type" "compare") | |
7820 | (set_attr "length" "4,8")]) | |
7821 | ||
7822 | (define_split | |
7823 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7824 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7825 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7826 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7827 | (const_int 0))) |
9ebbca7d GK |
7828 | (clobber (match_scratch:DI 3 ""))] |
7829 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7830 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7831 | (set (match_dup 0) |
7832 | (compare:CC (match_dup 3) | |
7833 | (const_int 0)))] | |
7834 | "") | |
266eb58a | 7835 | |
dfbdccdb | 7836 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7837 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7838 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7839 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7840 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7841 | (const_int 0))) | |
9ebbca7d | 7842 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7843 | (match_dup 4))] |
29ae5b89 | 7844 | "TARGET_POWERPC64" |
9ebbca7d | 7845 | "@ |
dfbdccdb | 7846 | %q4. %0,%1,%2 |
9ebbca7d GK |
7847 | #" |
7848 | [(set_attr "type" "compare") | |
7849 | (set_attr "length" "4,8")]) | |
7850 | ||
7851 | (define_split | |
e72247f4 | 7852 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7853 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7854 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7855 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7856 | (const_int 0))) |
75540af0 | 7857 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7858 | (match_dup 4))] |
9ebbca7d | 7859 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7860 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7861 | (set (match_dup 3) |
7862 | (compare:CC (match_dup 0) | |
7863 | (const_int 0)))] | |
7864 | "") | |
dfbdccdb | 7865 | \f |
1fd4e8c1 | 7866 | ;; Now define ways of moving data around. |
4697a36c MM |
7867 | |
7868 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
7869 | ;; The output of this could be r0, but we make a very strong |
7870 | ;; preference for a base register because it will usually | |
7871 | ;; be needed there. | |
4697a36c | 7872 | (define_insn "elf_high" |
9ebbca7d | 7873 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 7874 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 7875 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 7876 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
7877 | |
7878 | (define_insn "elf_low" | |
9ebbca7d GK |
7879 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
7880 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 7881 | (match_operand 2 "" "")))] |
0ad91047 | 7882 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
7883 | "@ |
7884 | {cal|la} %0,%2@l(%1) | |
81eace42 | 7885 | {ai|addic} %0,%1,%K2") |
4697a36c | 7886 | |
ee890fe2 SS |
7887 | ;; Mach-O PIC trickery. |
7888 | (define_insn "macho_high" | |
7889 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") | |
7890 | (high:SI (match_operand 1 "" "")))] | |
7891 | "TARGET_MACHO && ! TARGET_64BIT" | |
7892 | "{liu|lis} %0,ha16(%1)") | |
7893 | ||
7894 | (define_insn "macho_low" | |
7895 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
7896 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
7897 | (match_operand 2 "" "")))] | |
7898 | "TARGET_MACHO && ! TARGET_64BIT" | |
7899 | "@ | |
7900 | {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} | |
7901 | {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") | |
7902 | ||
766a866c MM |
7903 | ;; Set up a register with a value from the GOT table |
7904 | ||
7905 | (define_expand "movsi_got" | |
52d3af72 | 7906 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d GK |
7907 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
7908 | (match_dup 2)] 8))] | |
f607bc57 | 7909 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7910 | " |
7911 | { | |
38c1f2d7 MM |
7912 | if (GET_CODE (operands[1]) == CONST) |
7913 | { | |
7914 | rtx offset = const0_rtx; | |
7915 | HOST_WIDE_INT value; | |
7916 | ||
7917 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7918 | value = INTVAL (offset); | |
7919 | if (value != 0) | |
7920 | { | |
677a9668 | 7921 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7922 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7923 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7924 | DONE; | |
7925 | } | |
7926 | } | |
7927 | ||
c4c40373 | 7928 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7929 | }") |
7930 | ||
84f414bc | 7931 | (define_insn "*movsi_got_internal" |
52d3af72 | 7932 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d GK |
7933 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
7934 | (match_operand:SI 2 "gpc_reg_operand" "b")] 8))] | |
f607bc57 | 7935 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7936 | "{l|lwz} %0,%a1@got(%2)" |
7937 | [(set_attr "type" "load")]) | |
7938 | ||
b22b9b3e JL |
7939 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7940 | ;; didn't get allocated to a hard register. | |
7941 | (define_split | |
75540af0 | 7942 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7943 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
75540af0 | 7944 | (match_operand:SI 2 "memory_operand" "")] 8))] |
f607bc57 | 7945 | "DEFAULT_ABI == ABI_V4 |
b22b9b3e JL |
7946 | && flag_pic == 1 |
7947 | && (reload_in_progress || reload_completed)" | |
7948 | [(set (match_dup 0) (match_dup 2)) | |
9ebbca7d | 7949 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))] |
b22b9b3e JL |
7950 | "") |
7951 | ||
1fd4e8c1 RK |
7952 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7953 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7954 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7955 | ;; integers in the TOC. | |
7956 | (define_expand "movsi" | |
7957 | [(set (match_operand:SI 0 "general_operand" "") | |
7958 | (match_operand:SI 1 "any_operand" ""))] | |
7959 | "" | |
fb4d4348 | 7960 | "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") |
1fd4e8c1 | 7961 | |
ee890fe2 SS |
7962 | (define_insn "movsi_low" |
7963 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
f585a356 | 7964 | (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
ee890fe2 SS |
7965 | (match_operand 2 "" ""))))] |
7966 | "TARGET_MACHO && ! TARGET_64BIT" | |
7967 | "{l|lwz} %0,lo16(%2)(%1)" | |
7968 | [(set_attr "type" "load") | |
7969 | (set_attr "length" "4")]) | |
7970 | ||
c859cda6 | 7971 | (define_insn "movsi_low_st" |
f585a356 | 7972 | [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
c859cda6 DJ |
7973 | (match_operand 2 "" ""))) |
7974 | (match_operand:SI 0 "gpc_reg_operand" "r"))] | |
7975 | "TARGET_MACHO && ! TARGET_64BIT" | |
7976 | "{st|stw} %0,lo16(%2)(%1)" | |
7977 | [(set_attr "type" "store") | |
7978 | (set_attr "length" "4")]) | |
7979 | ||
7980 | (define_insn "movdf_low" | |
234e114c | 7981 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") |
f585a356 | 7982 | (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 DJ |
7983 | (match_operand 2 "" ""))))] |
7984 | "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" | |
234e114c DJ |
7985 | "* |
7986 | { | |
7987 | switch (which_alternative) | |
7988 | { | |
7989 | case 0: | |
7990 | return \"lfd %0,lo16(%2)(%1)\"; | |
7991 | case 1: | |
7992 | { | |
7993 | rtx operands2[4]; | |
7994 | operands2[0] = operands[0]; | |
7995 | operands2[1] = operands[1]; | |
7996 | operands2[2] = operands[2]; | |
1db02437 | 7997 | operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
234e114c DJ |
7998 | output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands); |
7999 | /* We cannot rely on ha16(low half)==ha16(high half), alas, | |
8000 | although in practice it almost always is. */ | |
8001 | output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2); | |
8002 | return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\"); | |
8003 | } | |
8004 | default: | |
8005 | abort(); | |
8006 | } | |
8007 | }" | |
c859cda6 | 8008 | [(set_attr "type" "load") |
234e114c | 8009 | (set_attr "length" "4,12")]) |
c859cda6 DJ |
8010 | |
8011 | (define_insn "movdf_low_st" | |
f585a356 | 8012 | [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
c859cda6 DJ |
8013 | (match_operand 2 "" ""))) |
8014 | (match_operand:DF 0 "gpc_reg_operand" "f"))] | |
8015 | "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" | |
8016 | "stfd %0,lo16(%2)(%1)" | |
8017 | [(set_attr "type" "store") | |
8018 | (set_attr "length" "4")]) | |
8019 | ||
8020 | (define_insn "movsf_low" | |
fd3b43f2 | 8021 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") |
f585a356 | 8022 | (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 DJ |
8023 | (match_operand 2 "" ""))))] |
8024 | "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" | |
fd3b43f2 DJ |
8025 | "@ |
8026 | lfs %0,lo16(%2)(%1) | |
8027 | {l|lwz} %0,lo16(%2)(%1)" | |
c859cda6 DJ |
8028 | [(set_attr "type" "load") |
8029 | (set_attr "length" "4")]) | |
8030 | ||
8031 | (define_insn "movsf_low_st" | |
f585a356 | 8032 | [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") |
c859cda6 | 8033 | (match_operand 2 "" ""))) |
fd3b43f2 | 8034 | (match_operand:SF 0 "gpc_reg_operand" "f,!r"))] |
c859cda6 | 8035 | "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" |
fd3b43f2 DJ |
8036 | "@ |
8037 | stfs %0,lo16(%2)(%1) | |
8038 | {st|stw} %0,lo16(%2)(%1)" | |
c859cda6 DJ |
8039 | [(set_attr "type" "store") |
8040 | (set_attr "length" "4")]) | |
8041 | ||
acad7ed3 | 8042 | (define_insn "*movsi_internal1" |
a004eb82 AH |
8043 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") |
8044 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] | |
19d5775a RK |
8045 | "gpc_reg_operand (operands[0], SImode) |
8046 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 8047 | "@ |
deb9225a | 8048 | mr %0,%1 |
b9442c72 | 8049 | {cal|la} %0,%a1 |
ca7f5001 RK |
8050 | {l%U1%X1|lwz%U1%X1} %0,%1 |
8051 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 8052 | {lil|li} %0,%1 |
802a0058 | 8053 | {liu|lis} %0,%v1 |
beaec479 | 8054 | # |
aee86b38 | 8055 | {cal|la} %0,%a1 |
1fd4e8c1 | 8056 | mf%1 %0 |
5c23c401 | 8057 | mt%0 %1 |
e76e75bb | 8058 | mt%0 %1 |
a004eb82 | 8059 | mt%0 %1 |
e76e75bb | 8060 | cror 0,0,0" |
a004eb82 AH |
8061 | [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*,*") |
8062 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) | |
1fd4e8c1 | 8063 | |
77fa0940 RK |
8064 | ;; Split a load of a large constant into the appropriate two-insn |
8065 | ;; sequence. | |
8066 | ||
8067 | (define_split | |
8068 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
8069 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 8070 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
8071 | && (INTVAL (operands[1]) & 0xffff) != 0" |
8072 | [(set (match_dup 0) | |
8073 | (match_dup 2)) | |
8074 | (set (match_dup 0) | |
8075 | (ior:SI (match_dup 0) | |
8076 | (match_dup 3)))] | |
8077 | " | |
8078 | { | |
5f59ecb7 | 8079 | operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); |
89e9f3a8 | 8080 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); |
77fa0940 RK |
8081 | }") |
8082 | ||
acad7ed3 | 8083 | (define_insn "*movsi_internal2" |
9ebbca7d GK |
8084 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
8085 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 8086 | (const_int 0))) |
9ebbca7d | 8087 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
0ad91047 | 8088 | "! TARGET_POWERPC64" |
9ebbca7d GK |
8089 | "@ |
8090 | mr. %0,%1 | |
8091 | #" | |
8092 | [(set_attr "type" "compare") | |
8093 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 8094 | \f |
9ebbca7d GK |
8095 | (define_split |
8096 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8097 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
8098 | (const_int 0))) | |
8099 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8100 | "! TARGET_POWERPC64 && reload_completed" | |
8101 | [(set (match_dup 0) (match_dup 1)) | |
8102 | (set (match_dup 2) | |
8103 | (compare:CC (match_dup 0) | |
8104 | (const_int 0)))] | |
8105 | "") | |
8106 | ||
1fd4e8c1 RK |
8107 | (define_expand "movhi" |
8108 | [(set (match_operand:HI 0 "general_operand" "") | |
8109 | (match_operand:HI 1 "any_operand" ""))] | |
8110 | "" | |
fb4d4348 | 8111 | "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") |
1fd4e8c1 RK |
8112 | |
8113 | (define_insn "" | |
fb81d7ce RK |
8114 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
8115 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
8116 | "gpc_reg_operand (operands[0], HImode) |
8117 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 8118 | "@ |
deb9225a | 8119 | mr %0,%1 |
1fd4e8c1 RK |
8120 | lhz%U1%X1 %0,%1 |
8121 | sth%U0%X0 %1,%0 | |
19d5775a | 8122 | {lil|li} %0,%w1 |
1fd4e8c1 | 8123 | mf%1 %0 |
e76e75bb | 8124 | mt%0 %1 |
fb81d7ce | 8125 | mt%0 %1 |
e76e75bb | 8126 | cror 0,0,0" |
b7ff3d82 | 8127 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
8128 | |
8129 | (define_expand "movqi" | |
8130 | [(set (match_operand:QI 0 "general_operand" "") | |
8131 | (match_operand:QI 1 "any_operand" ""))] | |
8132 | "" | |
fb4d4348 | 8133 | "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") |
1fd4e8c1 RK |
8134 | |
8135 | (define_insn "" | |
fb81d7ce RK |
8136 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
8137 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
8138 | "gpc_reg_operand (operands[0], QImode) |
8139 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 8140 | "@ |
deb9225a | 8141 | mr %0,%1 |
1fd4e8c1 RK |
8142 | lbz%U1%X1 %0,%1 |
8143 | stb%U0%X0 %1,%0 | |
19d5775a | 8144 | {lil|li} %0,%1 |
1fd4e8c1 | 8145 | mf%1 %0 |
e76e75bb | 8146 | mt%0 %1 |
fb81d7ce | 8147 | mt%0 %1 |
e76e75bb | 8148 | cror 0,0,0" |
b7ff3d82 | 8149 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
8150 | \f |
8151 | ;; Here is how to move condition codes around. When we store CC data in | |
8152 | ;; an integer register or memory, we store just the high-order 4 bits. | |
8153 | ;; This lets us not shift in the most common case of CR0. | |
8154 | (define_expand "movcc" | |
8155 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
8156 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
8157 | "" | |
8158 | "") | |
8159 | ||
a65c591c | 8160 | (define_insn "*movcc_internal1" |
1fd4e8c1 RK |
8161 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") |
8162 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] | |
8163 | "register_operand (operands[0], CCmode) | |
8164 | || register_operand (operands[1], CCmode)" | |
8165 | "@ | |
8166 | mcrf %0,%1 | |
8167 | mtcrf 128,%1 | |
ca7f5001 | 8168 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
1fd4e8c1 | 8169 | mfcr %0 |
ca7f5001 | 8170 | mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 |
deb9225a | 8171 | mr %0,%1 |
ca7f5001 RK |
8172 | {l%U1%X1|lwz%U1%X1} %0,%1 |
8173 | {st%U0%U1|stw%U0%U1} %1,%0" | |
309323c2 | 8174 | [(set_attr "type" "cr_logical,cr_logical,cr_logical,cr_logical,cr_logical,*,load,store") |
b19003d8 | 8175 | (set_attr "length" "*,*,12,*,8,*,*,*")]) |
1fd4e8c1 | 8176 | \f |
e52e05ca MM |
8177 | ;; For floating-point, we normally deal with the floating-point registers |
8178 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
8179 | ;; can produce floating-point values in fixed-point registers. Unless the | |
8180 | ;; value is a simple constant or already in memory, we deal with this by | |
8181 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
8182 | (define_expand "movsf" |
8183 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
8184 | (match_operand:SF 1 "any_operand" ""))] | |
8185 | "" | |
fb4d4348 | 8186 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 8187 | |
1fd4e8c1 | 8188 | (define_split |
cd2b37d9 | 8189 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 8190 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 8191 | "reload_completed |
5ae4759c MM |
8192 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8193 | || (GET_CODE (operands[0]) == SUBREG | |
8194 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8195 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 8196 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
8197 | " |
8198 | { | |
8199 | long l; | |
8200 | REAL_VALUE_TYPE rv; | |
8201 | ||
8202 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8203 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 8204 | |
f99f88e0 DE |
8205 | if (! TARGET_POWERPC64) |
8206 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
8207 | else | |
8208 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 8209 | |
2496c7bd | 8210 | operands[3] = gen_int_mode (l, SImode); |
a260abc9 DE |
8211 | }") |
8212 | ||
c4c40373 | 8213 | (define_insn "*movsf_hardfloat" |
f99f88e0 DE |
8214 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r") |
8215 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))] | |
d14a6d05 MM |
8216 | "(gpc_reg_operand (operands[0], SFmode) |
8217 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT" | |
1fd4e8c1 | 8218 | "@ |
f99f88e0 DE |
8219 | mr %0,%1 |
8220 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
8221 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
8222 | fmr %0,%1 |
8223 | lfs%U1%X1 %0,%1 | |
c4c40373 MM |
8224 | stfs%U0%X0 %1,%0 |
8225 | # | |
8226 | #" | |
f99f88e0 DE |
8227 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*") |
8228 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 8229 | |
c4c40373 MM |
8230 | (define_insn "*movsf_softfloat" |
8231 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r") | |
9615f239 | 8232 | (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))] |
d14a6d05 MM |
8233 | "(gpc_reg_operand (operands[0], SFmode) |
8234 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT" | |
8235 | "@ | |
8236 | mr %0,%1 | |
8237 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
8238 | {st%U0%X0|stw%U0%X0} %1,%0 | |
8239 | {lil|li} %0,%1 | |
802a0058 | 8240 | {liu|lis} %0,%v1 |
aee86b38 | 8241 | {cal|la} %0,%a1 |
c4c40373 MM |
8242 | # |
8243 | #" | |
8244 | [(set_attr "type" "*,load,store,*,*,*,*,*") | |
8245 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 8246 | |
1fd4e8c1 RK |
8247 | \f |
8248 | (define_expand "movdf" | |
8249 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
8250 | (match_operand:DF 1 "any_operand" ""))] | |
8251 | "" | |
fb4d4348 | 8252 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
8253 | |
8254 | (define_split | |
cd2b37d9 | 8255 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 8256 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 8257 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
8258 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8259 | || (GET_CODE (operands[0]) == SUBREG | |
8260 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8261 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
8262 | [(set (match_dup 2) (match_dup 4)) |
8263 | (set (match_dup 3) (match_dup 1))] | |
8264 | " | |
8265 | { | |
5ae4759c | 8266 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
8267 | HOST_WIDE_INT value = INTVAL (operands[1]); |
8268 | ||
5ae4759c MM |
8269 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
8270 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
8271 | #if HOST_BITS_PER_WIDE_INT == 32 |
8272 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
8273 | #else | |
8274 | operands[4] = GEN_INT (value >> 32); | |
a65c591c | 8275 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
5f59ecb7 | 8276 | #endif |
c4c40373 MM |
8277 | }") |
8278 | ||
c4c40373 MM |
8279 | (define_split |
8280 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
8281 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 8282 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
8283 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8284 | || (GET_CODE (operands[0]) == SUBREG | |
8285 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8286 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
8287 | [(set (match_dup 2) (match_dup 4)) |
8288 | (set (match_dup 3) (match_dup 5))] | |
8289 | " | |
8290 | { | |
5ae4759c | 8291 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
8292 | long l[2]; |
8293 | REAL_VALUE_TYPE rv; | |
8294 | ||
8295 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8296 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
8297 | ||
5ae4759c MM |
8298 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
8299 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
2496c7bd LB |
8300 | operands[4] = gen_int_mode (l[endian], SImode); |
8301 | operands[5] = gen_int_mode (l[1 - endian], SImode); | |
c4c40373 MM |
8302 | }") |
8303 | ||
efc08378 DE |
8304 | (define_split |
8305 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 8306 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 8307 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
8308 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8309 | || (GET_CODE (operands[0]) == SUBREG | |
8310 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8311 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 8312 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 8313 | " |
a260abc9 DE |
8314 | { |
8315 | int endian = (WORDS_BIG_ENDIAN == 0); | |
8316 | long l[2]; | |
8317 | REAL_VALUE_TYPE rv; | |
5b029315 | 8318 | HOST_WIDE_INT val; |
a260abc9 DE |
8319 | |
8320 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8321 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
8322 | ||
8323 | operands[2] = gen_lowpart (DImode, operands[0]); | |
8324 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
5b029315 TR |
8325 | #if HOST_BITS_PER_WIDE_INT >= 64 |
8326 | val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 | | |
8327 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); | |
8328 | ||
8329 | operands[3] = immed_double_const (val, -(val < 0), DImode); | |
8330 | #else | |
a260abc9 | 8331 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); |
5b029315 | 8332 | #endif |
a260abc9 | 8333 | }") |
efc08378 | 8334 | |
4eae5fe1 | 8335 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 8336 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
8337 | ;; a non-offsettable memref, but also it is less efficient than loading |
8338 | ;; the constant into an FP register, since it will probably be used there. | |
8339 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
8340 | ;; of handling these non-offsettable values. | |
c4c40373 | 8341 | (define_insn "*movdf_hardfloat32" |
000034eb DE |
8342 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
8343 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 8344 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
8345 | && (gpc_reg_operand (operands[0], DFmode) |
8346 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
8347 | "* |
8348 | { | |
8349 | switch (which_alternative) | |
8350 | { | |
a260abc9 | 8351 | default: |
a6c2a102 | 8352 | abort (); |
e7113111 RK |
8353 | case 0: |
8354 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
8355 | the first register operand 0 is the same as the second register |
8356 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 8357 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 8358 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 8359 | else |
deb9225a | 8360 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 8361 | case 1: |
2b97222d DE |
8362 | if (offsettable_memref_p (operands[1]) |
8363 | || (GET_CODE (operands[1]) == MEM | |
69f51a21 DE |
8364 | && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM |
8365 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC | |
8366 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))) | |
000034eb DE |
8367 | { |
8368 | /* If the low-address word is used in the address, we must load | |
8369 | it last. Otherwise, load it first. Note that we cannot have | |
8370 | auto-increment in that case since the address register is | |
8371 | known to be dead. */ | |
8372 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8373 | operands[1], 0)) | |
8374 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
8375 | else | |
8376 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8377 | } | |
e7113111 | 8378 | else |
000034eb DE |
8379 | { |
8380 | rtx addreg; | |
8381 | ||
000034eb DE |
8382 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
8383 | if (refers_to_regno_p (REGNO (operands[0]), | |
8384 | REGNO (operands[0]) + 1, | |
8385 | operands[1], 0)) | |
8386 | { | |
8387 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 8388 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 8389 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 8390 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
8391 | } |
8392 | else | |
8393 | { | |
2b97222d | 8394 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 8395 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8396 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
8397 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8398 | return \"\"; | |
8399 | } | |
8400 | } | |
e7113111 | 8401 | case 2: |
2b97222d DE |
8402 | if (offsettable_memref_p (operands[0]) |
8403 | || (GET_CODE (operands[0]) == MEM | |
69f51a21 DE |
8404 | && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM |
8405 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC | |
8406 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))) | |
000034eb DE |
8407 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8408 | else | |
8409 | { | |
8410 | rtx addreg; | |
8411 | ||
000034eb | 8412 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 8413 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 8414 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8415 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
8416 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8417 | return \"\"; | |
8418 | } | |
e7113111 | 8419 | case 3: |
e7113111 | 8420 | case 4: |
e7113111 | 8421 | case 5: |
c4c40373 | 8422 | return \"#\"; |
e7113111 | 8423 | case 6: |
c4c40373 MM |
8424 | return \"fmr %0,%1\"; |
8425 | case 7: | |
8426 | return \"lfd%U1%X1 %0,%1\"; | |
8427 | case 8: | |
e7113111 RK |
8428 | return \"stfd%U0%X0 %1,%0\"; |
8429 | } | |
8430 | }" | |
c4c40373 | 8431 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
2f76d42c | 8432 | (set_attr "length" "8,16,16,8,12,16,*,*,*")]) |
51b8fc2c | 8433 | |
c4c40373 | 8434 | (define_insn "*movdf_softfloat32" |
1427100a DE |
8435 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
8436 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 8437 | "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
8438 | && (gpc_reg_operand (operands[0], DFmode) |
8439 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8440 | "* |
8441 | { | |
8442 | switch (which_alternative) | |
8443 | { | |
a260abc9 | 8444 | default: |
a6c2a102 | 8445 | abort (); |
dc4f83ca MM |
8446 | case 0: |
8447 | /* We normally copy the low-numbered register first. However, if | |
8448 | the first register operand 0 is the same as the second register of | |
8449 | operand 1, we must copy in the opposite order. */ | |
8450 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8451 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8452 | else | |
8453 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8454 | case 1: | |
3cb999d8 DE |
8455 | /* If the low-address word is used in the address, we must load |
8456 | it last. Otherwise, load it first. Note that we cannot have | |
8457 | auto-increment in that case since the address register is | |
8458 | known to be dead. */ | |
dc4f83ca | 8459 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 8460 | operands[1], 0)) |
dc4f83ca MM |
8461 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
8462 | else | |
8463 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8464 | case 2: | |
8465 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
8466 | case 3: | |
c4c40373 MM |
8467 | case 4: |
8468 | case 5: | |
dc4f83ca MM |
8469 | return \"#\"; |
8470 | } | |
8471 | }" | |
c4c40373 MM |
8472 | [(set_attr "type" "*,load,store,*,*,*") |
8473 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 8474 | |
c4c40373 | 8475 | (define_insn "*movdf_hardfloat64" |
1427100a DE |
8476 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
8477 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 8478 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
8479 | && (gpc_reg_operand (operands[0], DFmode) |
8480 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 8481 | "@ |
3d5570cb RK |
8482 | mr %0,%1 |
8483 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8484 | std%U0%X0 %1,%0 |
3d5570cb | 8485 | # |
c4c40373 MM |
8486 | # |
8487 | # | |
3d5570cb | 8488 | fmr %0,%1 |
f63184ac | 8489 | lfd%U1%X1 %0,%1 |
3d5570cb | 8490 | stfd%U0%X0 %1,%0" |
c4c40373 MM |
8491 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
8492 | (set_attr "length" "4,4,4,8,12,16,4,4,4")]) | |
dc4f83ca | 8493 | |
c4c40373 | 8494 | (define_insn "*movdf_softfloat64" |
1427100a DE |
8495 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
8496 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 8497 | "TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
8498 | && (gpc_reg_operand (operands[0], DFmode) |
8499 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8500 | "@ |
8501 | mr %0,%1 | |
8502 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8503 | std%U0%X0 %1,%0 |
c4c40373 MM |
8504 | # |
8505 | # | |
dc4f83ca | 8506 | #" |
c4c40373 MM |
8507 | [(set_attr "type" "*,load,store,*,*,*") |
8508 | (set_attr "length" "*,*,*,8,12,16")]) | |
1fd4e8c1 | 8509 | \f |
06f4e019 DE |
8510 | (define_expand "movtf" |
8511 | [(set (match_operand:TF 0 "general_operand" "") | |
8512 | (match_operand:TF 1 "any_operand" ""))] | |
8513 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8514 | "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") | |
8515 | ||
8516 | (define_insn "*movtf_internal" | |
8517 | [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,m,!r,!r,!r") | |
8518 | (match_operand:TF 1 "input_operand" "f,m,f,G,H,F"))] | |
8519 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128 | |
8520 | && (gpc_reg_operand (operands[0], TFmode) | |
8521 | || gpc_reg_operand (operands[1], TFmode))" | |
8522 | "* | |
8523 | { | |
8524 | switch (which_alternative) | |
8525 | { | |
8526 | default: | |
8527 | abort (); | |
8528 | case 0: | |
8529 | /* We normally copy the low-numbered register first. However, if | |
8530 | the first register operand 0 is the same as the second register of | |
8531 | operand 1, we must copy in the opposite order. */ | |
8532 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8533 | return \"fmr %L0,%L1\;fmr %0,%1\"; | |
8534 | else | |
8535 | return \"fmr %0,%1\;fmr %L0,%L1\"; | |
8536 | case 1: | |
8537 | return \"lfd %0,%1\;lfd %L0,%L1\"; | |
8538 | case 2: | |
8539 | return \"stfd %1,%0\;stfd %L1,%L0\"; | |
8540 | case 3: | |
8541 | case 4: | |
8542 | case 5: | |
8543 | return \"#\"; | |
8544 | } | |
8545 | }" | |
8546 | [(set_attr "type" "fp,fpload,fpstore,*,*,*") | |
8547 | (set_attr "length" "8,8,8,12,16,20")]) | |
8548 | ||
8549 | (define_split | |
8550 | [(set (match_operand:TF 0 "gpc_reg_operand" "") | |
8551 | (match_operand:TF 1 "const_double_operand" ""))] | |
8552 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8553 | [(set (match_dup 3) (match_dup 1)) | |
8554 | (set (match_dup 0) | |
8555 | (float_extend:TF (match_dup 3)))] | |
8556 | " | |
8557 | { | |
8558 | operands[2] = operand_subword (operands[1], 0, 0, DFmode); | |
8559 | operands[3] = gen_reg_rtx (DFmode); | |
8560 | }") | |
8561 | ||
8562 | (define_insn_and_split "extenddftf2" | |
8563 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8564 | (float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
8565 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8566 | "#" | |
8567 | "" | |
8568 | [(set (match_dup 2) (match_dup 3))] | |
8569 | " | |
8570 | { | |
8571 | operands[2] = gen_rtx_REG (DFmode, REGNO (operands[0] + 1)); | |
8572 | operands[3] = CONST0_RTX (DFmode); | |
8573 | }") | |
8574 | ||
8575 | (define_insn_and_split "extendsftf2" | |
8576 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8577 | (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
8578 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8579 | "#" | |
8580 | "" | |
8581 | [(set (match_dup 2) (match_dup 3))] | |
8582 | " | |
8583 | { | |
8584 | operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0] + 1)); | |
8585 | operands[3] = CONST0_RTX (SFmode); | |
8586 | }") | |
8587 | ||
8588 | (define_insn "trunctfdf2" | |
8589 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8590 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
8591 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8592 | "fadd %0,%1,%L1" | |
8593 | [(set_attr "type" "fp") | |
8594 | (set_attr "length" "8")]) | |
8595 | ||
8596 | (define_insn_and_split "trunctfsf2" | |
8597 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
ea112fc4 DE |
8598 | (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8599 | (clobber (match_scratch:DF 2 "=f"))] | |
06f4e019 DE |
8600 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" |
8601 | "#" | |
ea112fc4 | 8602 | "&& reload_completed" |
06f4e019 DE |
8603 | [(set (match_dup 2) |
8604 | (float_truncate:DF (match_dup 1))) | |
8605 | (set (match_dup 0) | |
8606 | (float_truncate:SF (match_dup 2)))] | |
ea112fc4 | 8607 | "") |
06f4e019 | 8608 | |
ea112fc4 DE |
8609 | (define_insn_and_split "floatditf2" |
8610 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 8611 | (float:TF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 DE |
8612 | (clobber (match_scratch:DF 2 "=f"))] |
8613 | "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 | |
8614 | && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8615 | "#" | |
8616 | "&& reload_completed" | |
06f4e019 DE |
8617 | [(set (match_dup 2) |
8618 | (float:DF (match_operand:DI 1 "gpc_reg_operand" ""))) | |
8619 | (set (match_operand:TF 0 "gpc_reg_operand" "") | |
8620 | (float_extend:TF (match_dup 2)))] | |
ea112fc4 | 8621 | "") |
06f4e019 | 8622 | |
ea112fc4 DE |
8623 | (define_insn_and_split "floatsitf2" |
8624 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 8625 | (float:TF (match_operand:SI 1 "gpc_reg_operand" "r"))) |
ea112fc4 DE |
8626 | (clobber (match_scratch:DF 2 "=f"))] |
8627 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8628 | "#" | |
8629 | "&& reload_completed" | |
06f4e019 DE |
8630 | [(set (match_dup 2) |
8631 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
8632 | (set (match_operand:TF 0 "gpc_reg_operand" "") | |
8633 | (float_extend:TF (match_dup 2)))] | |
ea112fc4 | 8634 | "") |
06f4e019 | 8635 | |
ea112fc4 | 8636 | (define_insn_and_split "fix_trunctfdi2" |
61c07d3c | 8637 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
ea112fc4 DE |
8638 | (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))] |
8639 | "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 | |
8640 | && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8641 | "#" | |
8642 | "&& reload_completed" | |
06f4e019 DE |
8643 | [(set (match_dup 2) |
8644 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" ""))) | |
8645 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
8646 | (fix:SI (match_dup 2)))] | |
ea112fc4 | 8647 | "") |
06f4e019 | 8648 | |
ea112fc4 | 8649 | (define_insn_and_split "fix_trunctfsi2" |
61c07d3c | 8650 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ea112fc4 DE |
8651 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))] |
8652 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8653 | "#" | |
8654 | "&& reload_completed" | |
06f4e019 DE |
8655 | [(set (match_dup 2) |
8656 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" ""))) | |
8657 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
8658 | (fix:SI (match_dup 2)))] | |
ea112fc4 | 8659 | "") |
06f4e019 DE |
8660 | |
8661 | (define_insn "negtf2" | |
8662 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8663 | (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
8664 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8665 | "* | |
8666 | { | |
8667 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8668 | return \"fneg %L0,%L1\;fneg %0,%1\"; | |
8669 | else | |
8670 | return \"fneg %0,%1\;fneg %L0,%L1\"; | |
8671 | }" | |
8672 | [(set_attr "type" "fp") | |
8673 | (set_attr "length" "8")]) | |
8674 | ||
8675 | (define_insn "abstf2" | |
8676 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8677 | (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
8678 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8679 | "* | |
8680 | { | |
8681 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8682 | return \"fabs %L0,%L1\;fabs %0,%1\"; | |
8683 | else | |
8684 | return \"fabs %0,%1\;fabs %L0,%L1\"; | |
8685 | }" | |
8686 | [(set_attr "type" "fp") | |
8687 | (set_attr "length" "8")]) | |
8688 | ||
8689 | (define_insn "" | |
8690 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8691 | (neg:TF (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f"))))] | |
8692 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
8693 | "* | |
8694 | { | |
8695 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8696 | return \"fnabs %L0,%L1\;fnabs %0,%1\"; | |
8697 | else | |
8698 | return \"fnabs %0,%1\;fnabs %L0,%L1\"; | |
8699 | }" | |
8700 | [(set_attr "type" "fp") | |
8701 | (set_attr "length" "8")]) | |
8702 | \f | |
1fd4e8c1 RK |
8703 | ;; Next come the multi-word integer load and store and the load and store |
8704 | ;; multiple insns. | |
8705 | (define_expand "movdi" | |
8706 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 8707 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 | 8708 | "" |
fb4d4348 | 8709 | "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") |
1fd4e8c1 | 8710 | |
acad7ed3 | 8711 | (define_insn "*movdi_internal32" |
4e74d8ec MM |
8712 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") |
8713 | (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] | |
a260abc9 | 8714 | "! TARGET_POWERPC64 |
4e74d8ec MM |
8715 | && (gpc_reg_operand (operands[0], DImode) |
8716 | || gpc_reg_operand (operands[1], DImode))" | |
1fd4e8c1 RK |
8717 | "* |
8718 | { | |
8719 | switch (which_alternative) | |
8720 | { | |
a260abc9 | 8721 | default: |
a6c2a102 | 8722 | abort (); |
1fd4e8c1 RK |
8723 | case 0: |
8724 | /* We normally copy the low-numbered register first. However, if | |
8725 | the first register operand 0 is the same as the second register of | |
8726 | operand 1, we must copy in the opposite order. */ | |
8727 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 8728 | return \"mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 8729 | else |
deb9225a | 8730 | return \"mr %0,%1\;mr %L0,%L1\"; |
1fd4e8c1 RK |
8731 | case 1: |
8732 | /* If the low-address word is used in the address, we must load it | |
8733 | last. Otherwise, load it first. Note that we cannot have | |
8734 | auto-increment in that case since the address register is known to be | |
8735 | dead. */ | |
8736 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 8737 | operands[1], 0)) |
ca7f5001 | 8738 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
1fd4e8c1 | 8739 | else |
ca7f5001 | 8740 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 | 8741 | case 2: |
ca7f5001 | 8742 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8ffd9c51 RK |
8743 | case 3: |
8744 | return \"fmr %0,%1\"; | |
8745 | case 4: | |
8746 | return \"lfd%U1%X1 %0,%1\"; | |
8747 | case 5: | |
8748 | return \"stfd%U0%X0 %1,%0\"; | |
4e74d8ec MM |
8749 | case 6: |
8750 | case 7: | |
8751 | case 8: | |
8752 | case 9: | |
8753 | case 10: | |
8754 | return \"#\"; | |
1fd4e8c1 RK |
8755 | } |
8756 | }" | |
4e74d8ec MM |
8757 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*") |
8758 | (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")]) | |
8759 | ||
8760 | (define_split | |
8761 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8762 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 8763 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8764 | [(set (match_dup 2) (match_dup 4)) |
8765 | (set (match_dup 3) (match_dup 1))] | |
8766 | " | |
8767 | { | |
5f59ecb7 | 8768 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
8769 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8770 | DImode); | |
8771 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8772 | DImode); | |
75d39459 | 8773 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 8774 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 8775 | #else |
5f59ecb7 | 8776 | operands[4] = GEN_INT (value >> 32); |
a65c591c | 8777 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
75d39459 | 8778 | #endif |
4e74d8ec MM |
8779 | }") |
8780 | ||
4e74d8ec MM |
8781 | (define_split |
8782 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8783 | (match_operand:DI 1 "const_double_operand" ""))] | |
75d39459 | 8784 | "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8785 | [(set (match_dup 2) (match_dup 4)) |
8786 | (set (match_dup 3) (match_dup 5))] | |
8787 | " | |
8788 | { | |
bdaa0181 GK |
8789 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8790 | DImode); | |
8791 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8792 | DImode); | |
f6968f59 MM |
8793 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
8794 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
4e74d8ec MM |
8795 | }") |
8796 | ||
acad7ed3 | 8797 | (define_insn "*movdi_internal64" |
e6ca2c17 | 8798 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h") |
9615f239 | 8799 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 8800 | "TARGET_POWERPC64 |
4e74d8ec MM |
8801 | && (gpc_reg_operand (operands[0], DImode) |
8802 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 8803 | "@ |
3d5570cb RK |
8804 | mr %0,%1 |
8805 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8806 | std%U0%X0 %1,%0 |
3d5570cb | 8807 | li %0,%1 |
802a0058 | 8808 | lis %0,%v1 |
e6ca2c17 | 8809 | # |
aee86b38 | 8810 | {cal|la} %0,%a1 |
3d5570cb RK |
8811 | fmr %0,%1 |
8812 | lfd%U1%X1 %0,%1 | |
8813 | stfd%U0%X0 %1,%0 | |
8814 | mf%1 %0 | |
08075ead DE |
8815 | mt%0 %1 |
8816 | cror 0,0,0" | |
b7ff3d82 | 8817 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*") |
e6ca2c17 DE |
8818 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
8819 | ||
5f59ecb7 | 8820 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
8821 | (define_insn "" |
8822 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8823 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
8824 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8825 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
8826 | && num_insns_constant (operands[1], DImode) == 1" |
8827 | "* | |
8828 | { | |
8829 | return ((unsigned HOST_WIDE_INT) | |
8830 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
8831 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
8832 | }") | |
8833 | ||
a260abc9 DE |
8834 | ;; Generate all one-bits and clear left or right. |
8835 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8836 | (define_split | |
8837 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8838 | (match_operand:DI 1 "mask64_operand" ""))] | |
8839 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8840 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8841 | (set (match_dup 0) |
a260abc9 DE |
8842 | (and:DI (rotate:DI (match_dup 0) |
8843 | (const_int 0)) | |
8844 | (match_dup 1)))] | |
8845 | "") | |
8846 | ||
8847 | ;; Split a load of a large constant into the appropriate five-instruction | |
8848 | ;; sequence. Handle anything in a constant number of insns. | |
8849 | ;; When non-easy constants can go in the TOC, this should use | |
8850 | ;; easy_fp_constant predicate. | |
8851 | (define_split | |
8852 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8853 | (match_operand:DI 1 "const_int_operand" ""))] |
8854 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8855 | [(set (match_dup 0) (match_dup 2)) | |
8856 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
e6ca2c17 | 8857 | " |
2bfcf297 DB |
8858 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8859 | ||
8860 | if (tem == operands[0]) | |
8861 | DONE; | |
e8d791dd | 8862 | else |
2bfcf297 | 8863 | FAIL; |
5f59ecb7 | 8864 | }") |
e6ca2c17 | 8865 | |
5f59ecb7 DE |
8866 | (define_split |
8867 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8868 | (match_operand:DI 1 "const_double_operand" ""))] |
8869 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8870 | [(set (match_dup 0) (match_dup 2)) | |
8871 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
5f59ecb7 | 8872 | " |
2bfcf297 DB |
8873 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8874 | ||
8875 | if (tem == operands[0]) | |
8876 | DONE; | |
8877 | else | |
8878 | FAIL; | |
e6ca2c17 | 8879 | }") |
08075ead | 8880 | |
2bfcf297 | 8881 | ;; Split a load of a large constant into the appropriate five-instruction |
acad7ed3 | 8882 | (define_insn "*movdi_internal2" |
9ebbca7d GK |
8883 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
8884 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
08075ead | 8885 | (const_int 0))) |
9ebbca7d | 8886 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
08075ead | 8887 | "TARGET_POWERPC64" |
9ebbca7d GK |
8888 | "@ |
8889 | mr. %0,%1 | |
8890 | #" | |
8891 | [(set_attr "type" "compare") | |
8892 | (set_attr "length" "4,8")]) | |
acad7ed3 | 8893 | |
9ebbca7d GK |
8894 | (define_split |
8895 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8896 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
8897 | (const_int 0))) | |
8898 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8899 | "TARGET_POWERPC64 && reload_completed" | |
8900 | [(set (match_dup 0) (match_dup 1)) | |
8901 | (set (match_dup 2) | |
8902 | (compare:CC (match_dup 0) | |
8903 | (const_int 0)))] | |
8904 | "") | |
acad7ed3 | 8905 | \f |
1fd4e8c1 RK |
8906 | ;; TImode is similar, except that we usually want to compute the address into |
8907 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8908 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8909 | (define_expand "movti" |
8910 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
8911 | (match_operand:TI 1 "general_operand" "")) | |
8912 | (clobber (scratch:SI))])] | |
7e69e155 | 8913 | "TARGET_STRING || TARGET_POWERPC64" |
fb4d4348 | 8914 | "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") |
1fd4e8c1 RK |
8915 | |
8916 | ;; We say that MQ is clobbered in the last alternative because the first | |
8917 | ;; alternative would never get used otherwise since it would need a reload | |
8918 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8919 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8920 | ;; giving the SCRATCH mq. | |
a260abc9 | 8921 | (define_insn "*movti_power" |
e1469d0d | 8922 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
8923 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
8924 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
7e69e155 | 8925 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8926 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8927 | "* |
8928 | { | |
8929 | switch (which_alternative) | |
8930 | { | |
dc4f83ca MM |
8931 | default: |
8932 | abort (); | |
8933 | ||
1fd4e8c1 | 8934 | case 0: |
ca7f5001 | 8935 | return \"{stsi|stswi} %1,%P0,16\"; |
1fd4e8c1 RK |
8936 | |
8937 | case 1: | |
ca7f5001 | 8938 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
1fd4e8c1 RK |
8939 | |
8940 | case 2: | |
8941 | /* Normally copy registers with lowest numbered register copied first. | |
8942 | But copy in the other order if the first register of the output | |
8943 | is the second, third, or fourth register in the input. */ | |
8944 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8945 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
deb9225a | 8946 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 8947 | else |
deb9225a | 8948 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; |
1fd4e8c1 RK |
8949 | case 3: |
8950 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8951 | fall through to generating four loads. */ | |
8952 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8953 | return \"{lsi|lswi} %0,%P1,16\"; |
82e41834 | 8954 | /* ... fall through ... */ |
1fd4e8c1 RK |
8955 | case 4: |
8956 | /* If the address register is the same as the register for the lowest- | |
8957 | addressed word, load it last. Similarly for the next two words. | |
8958 | Otherwise load lowest address to highest. */ | |
8959 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8960 | operands[1], 0)) | |
ca7f5001 | 8961 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; |
1fd4e8c1 RK |
8962 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, |
8963 | REGNO (operands[0]) + 2, operands[1], 0)) | |
ca7f5001 | 8964 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 RK |
8965 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, |
8966 | REGNO (operands[0]) + 3, operands[1], 0)) | |
ca7f5001 | 8967 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; |
1fd4e8c1 | 8968 | else |
ca7f5001 | 8969 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; |
1fd4e8c1 RK |
8970 | } |
8971 | }" | |
b7ff3d82 | 8972 | [(set_attr "type" "store,store,*,load,load") |
b19003d8 | 8973 | (set_attr "length" "*,16,16,*,16")]) |
51b8fc2c | 8974 | |
a260abc9 | 8975 | (define_insn "*movti_string" |
dc4f83ca MM |
8976 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r") |
8977 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,m")) | |
8978 | (clobber (match_scratch:SI 2 "=X,X,X"))] | |
0ad91047 | 8979 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8980 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8981 | "* | |
8982 | { | |
8983 | switch (which_alternative) | |
8984 | { | |
8985 | default: | |
8986 | abort (); | |
8987 | ||
8988 | case 0: | |
8989 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; | |
8990 | ||
8991 | case 1: | |
8992 | /* Normally copy registers with lowest numbered register copied first. | |
8993 | But copy in the other order if the first register of the output | |
8994 | is the second, third, or fourth register in the input. */ | |
8995 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8996 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
8997 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; | |
8998 | else | |
8999 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; | |
9000 | case 2: | |
9001 | /* If the address register is the same as the register for the lowest- | |
9002 | addressed word, load it last. Similarly for the next two words. | |
9003 | Otherwise load lowest address to highest. */ | |
9004 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
9005 | operands[1], 0)) | |
9006 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; | |
9007 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, | |
9008 | REGNO (operands[0]) + 2, operands[1], 0)) | |
9009 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; | |
9010 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, | |
9011 | REGNO (operands[0]) + 3, operands[1], 0)) | |
9012 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; | |
9013 | else | |
9014 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; | |
9015 | } | |
9016 | }" | |
b7ff3d82 | 9017 | [(set_attr "type" "store,*,load") |
dc4f83ca MM |
9018 | (set_attr "length" "16,16,16")]) |
9019 | ||
a260abc9 | 9020 | (define_insn "*movti_ppc64" |
51b8fc2c RK |
9021 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") |
9022 | (match_operand:TI 1 "input_operand" "r,m,r"))] | |
9023 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) | |
9024 | || gpc_reg_operand (operands[1], TImode))" | |
9025 | "* | |
9026 | { | |
9027 | switch (which_alternative) | |
9028 | { | |
a260abc9 | 9029 | default: |
a6c2a102 | 9030 | abort (); |
51b8fc2c RK |
9031 | case 0: |
9032 | /* We normally copy the low-numbered register first. However, if | |
9033 | the first register operand 0 is the same as the second register of | |
9034 | operand 1, we must copy in the opposite order. */ | |
9035 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
9036 | return \"mr %L0,%L1\;mr %0,%1\"; | |
9037 | else | |
9038 | return \"mr %0,%1\;mr %L0,%L1\"; | |
9039 | case 1: | |
9040 | /* If the low-address word is used in the address, we must load it | |
9041 | last. Otherwise, load it first. Note that we cannot have | |
9042 | auto-increment in that case since the address register is known to be | |
9043 | dead. */ | |
9044 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 9045 | operands[1], 0)) |
51b8fc2c RK |
9046 | return \"ld %L0,%L1\;ld %0,%1\"; |
9047 | else | |
9048 | return \"ld%U1 %0,%1\;ld %L0,%L1\"; | |
9049 | case 2: | |
9050 | return \"std%U0 %1,%0\;std %L1,%L0\"; | |
9051 | } | |
9052 | }" | |
b7ff3d82 | 9053 | [(set_attr "type" "*,load,store") |
51b8fc2c | 9054 | (set_attr "length" "8,8,8")]) |
1fd4e8c1 RK |
9055 | \f |
9056 | (define_expand "load_multiple" | |
2f622005 RK |
9057 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
9058 | (match_operand:SI 1 "" "")) | |
9059 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 9060 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
9061 | " |
9062 | { | |
9063 | int regno; | |
9064 | int count; | |
792760b9 | 9065 | rtx op1; |
1fd4e8c1 RK |
9066 | int i; |
9067 | ||
9068 | /* Support only loading a constant number of fixed-point registers from | |
9069 | memory and only bother with this if more than two; the machine | |
9070 | doesn't support more than eight. */ | |
9071 | if (GET_CODE (operands[2]) != CONST_INT | |
9072 | || INTVAL (operands[2]) <= 2 | |
9073 | || INTVAL (operands[2]) > 8 | |
9074 | || GET_CODE (operands[1]) != MEM | |
9075 | || GET_CODE (operands[0]) != REG | |
9076 | || REGNO (operands[0]) >= 32) | |
9077 | FAIL; | |
9078 | ||
9079 | count = INTVAL (operands[2]); | |
9080 | regno = REGNO (operands[0]); | |
9081 | ||
39403d82 | 9082 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
9083 | op1 = replace_equiv_address (operands[1], |
9084 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
9085 | |
9086 | for (i = 0; i < count; i++) | |
9087 | XVECEXP (operands[3], 0, i) | |
39403d82 | 9088 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
792760b9 | 9089 | adjust_address (op1, SImode, i * 4)); |
1fd4e8c1 RK |
9090 | }") |
9091 | ||
9092 | (define_insn "" | |
9093 | [(match_parallel 0 "load_multiple_operation" | |
cd2b37d9 | 9094 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") |
52d3af72 | 9095 | (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])] |
7e69e155 | 9096 | "TARGET_STRING" |
1fd4e8c1 RK |
9097 | "* |
9098 | { | |
9099 | /* We have to handle the case where the pseudo used to contain the address | |
e82ee4cc RK |
9100 | is assigned to one of the output registers. */ |
9101 | int i, j; | |
9102 | int words = XVECLEN (operands[0], 0); | |
9103 | rtx xop[10]; | |
9104 | ||
9105 | if (XVECLEN (operands[0], 0) == 1) | |
9106 | return \"{l|lwz} %1,0(%2)\"; | |
1fd4e8c1 | 9107 | |
e82ee4cc | 9108 | for (i = 0; i < words; i++) |
1fd4e8c1 RK |
9109 | if (refers_to_regno_p (REGNO (operands[1]) + i, |
9110 | REGNO (operands[1]) + i + 1, operands[2], 0)) | |
9111 | { | |
e82ee4cc RK |
9112 | if (i == words-1) |
9113 | { | |
9114 | xop[0] = operands[1]; | |
9115 | xop[1] = operands[2]; | |
9116 | xop[2] = GEN_INT (4 * (words-1)); | |
d89ddcfd | 9117 | output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop); |
e82ee4cc RK |
9118 | return \"\"; |
9119 | } | |
9120 | else if (i == 0) | |
9121 | { | |
9122 | xop[0] = operands[1]; | |
39403d82 | 9123 | xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
e82ee4cc RK |
9124 | xop[2] = GEN_INT (4 * (words-1)); |
9125 | output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop); | |
9126 | return \"\"; | |
9127 | } | |
9128 | else | |
9129 | { | |
9130 | for (j = 0; j < words; j++) | |
9131 | if (j != i) | |
9132 | { | |
39403d82 | 9133 | xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j); |
e82ee4cc RK |
9134 | xop[1] = operands[2]; |
9135 | xop[2] = GEN_INT (j * 4); | |
9136 | output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop); | |
9137 | } | |
9138 | xop[0] = operands[2]; | |
9139 | xop[1] = GEN_INT (i * 4); | |
9140 | output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop); | |
9141 | return \"\"; | |
9142 | } | |
1fd4e8c1 RK |
9143 | } |
9144 | ||
e82ee4cc | 9145 | return \"{lsi|lswi} %1,%2,%N0\"; |
1fd4e8c1 | 9146 | }" |
b19003d8 | 9147 | [(set_attr "type" "load") |
e82ee4cc | 9148 | (set_attr "length" "32")]) |
b19003d8 | 9149 | |
b7ff3d82 | 9150 | \f |
1fd4e8c1 | 9151 | (define_expand "store_multiple" |
2f622005 RK |
9152 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
9153 | (match_operand:SI 1 "" "")) | |
9154 | (clobber (scratch:SI)) | |
9155 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 9156 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
9157 | " |
9158 | { | |
9159 | int regno; | |
9160 | int count; | |
9161 | rtx to; | |
792760b9 | 9162 | rtx op0; |
1fd4e8c1 RK |
9163 | int i; |
9164 | ||
9165 | /* Support only storing a constant number of fixed-point registers to | |
9166 | memory and only bother with this if more than two; the machine | |
9167 | doesn't support more than eight. */ | |
9168 | if (GET_CODE (operands[2]) != CONST_INT | |
9169 | || INTVAL (operands[2]) <= 2 | |
9170 | || INTVAL (operands[2]) > 8 | |
9171 | || GET_CODE (operands[0]) != MEM | |
9172 | || GET_CODE (operands[1]) != REG | |
9173 | || REGNO (operands[1]) >= 32) | |
9174 | FAIL; | |
9175 | ||
9176 | count = INTVAL (operands[2]); | |
9177 | regno = REGNO (operands[1]); | |
9178 | ||
39403d82 | 9179 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 9180 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 9181 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
9182 | |
9183 | XVECEXP (operands[3], 0, 0) | |
68350f4f | 9184 | = gen_rtx_SET (VOIDmode, adjust_address (op0, SImode, 0), operands[1]); |
39403d82 | 9185 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 9186 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
9187 | |
9188 | for (i = 1; i < count; i++) | |
9189 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 9190 | = gen_rtx_SET (VOIDmode, |
792760b9 | 9191 | adjust_address (op0, SImode, i * 4), |
c5c76735 | 9192 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
9193 | }") |
9194 | ||
9195 | (define_insn "" | |
9196 | [(match_parallel 0 "store_multiple_operation" | |
9197 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 9198 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9199 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 9200 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
9201 | "{stsi|stswi} %2,%P1,%O0" |
9202 | [(set_attr "type" "store")]) | |
d14a6d05 MM |
9203 | |
9204 | (define_insn "" | |
9205 | [(match_parallel 0 "store_multiple_operation" | |
52d3af72 | 9206 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
d14a6d05 MM |
9207 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
9208 | (clobber (match_scratch:SI 3 "X"))])] | |
0ad91047 | 9209 | "TARGET_STRING && ! TARGET_POWER" |
b7ff3d82 DE |
9210 | "{stsi|stswi} %2,%1,%O0" |
9211 | [(set_attr "type" "store")]) | |
7e69e155 MM |
9212 | |
9213 | \f | |
9214 | ;; String/block move insn. | |
9215 | ;; Argument 0 is the destination | |
9216 | ;; Argument 1 is the source | |
9217 | ;; Argument 2 is the length | |
9218 | ;; Argument 3 is the alignment | |
9219 | ||
9220 | (define_expand "movstrsi" | |
b6c9286a MM |
9221 | [(parallel [(set (match_operand:BLK 0 "" "") |
9222 | (match_operand:BLK 1 "" "")) | |
9223 | (use (match_operand:SI 2 "" "")) | |
9224 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
9225 | "" |
9226 | " | |
9227 | { | |
9228 | if (expand_block_move (operands)) | |
9229 | DONE; | |
9230 | else | |
9231 | FAIL; | |
9232 | }") | |
9233 | ||
9234 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
9235 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
9236 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9237 | (define_expand "movstrsi_8reg" |
b6c9286a MM |
9238 | [(parallel [(set (match_operand 0 "" "") |
9239 | (match_operand 1 "" "")) | |
9240 | (use (match_operand 2 "" "")) | |
9241 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
9242 | (clobber (reg:SI 5)) |
9243 | (clobber (reg:SI 6)) | |
9244 | (clobber (reg:SI 7)) | |
9245 | (clobber (reg:SI 8)) | |
9246 | (clobber (reg:SI 9)) | |
9247 | (clobber (reg:SI 10)) | |
9248 | (clobber (reg:SI 11)) | |
9249 | (clobber (reg:SI 12)) | |
3c67b673 | 9250 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9251 | "TARGET_STRING" |
9252 | "") | |
9253 | ||
9254 | (define_insn "" | |
52d3af72 DE |
9255 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9256 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9257 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9258 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9259 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9260 | (clobber (reg:SI 6)) |
9261 | (clobber (reg:SI 7)) | |
9262 | (clobber (reg:SI 8)) | |
9263 | (clobber (reg:SI 9)) | |
9264 | (clobber (reg:SI 10)) | |
9265 | (clobber (reg:SI 11)) | |
9266 | (clobber (reg:SI 12)) | |
3c67b673 | 9267 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 9268 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
9269 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9270 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9271 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9272 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9273 | && REGNO (operands[4]) == 5" |
9274 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9275 | [(set_attr "type" "load") |
9276 | (set_attr "length" "8")]) | |
7e69e155 MM |
9277 | |
9278 | (define_insn "" | |
52d3af72 DE |
9279 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9280 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9281 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9282 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9283 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9284 | (clobber (reg:SI 6)) |
9285 | (clobber (reg:SI 7)) | |
9286 | (clobber (reg:SI 8)) | |
9287 | (clobber (reg:SI 9)) | |
9288 | (clobber (reg:SI 10)) | |
9289 | (clobber (reg:SI 11)) | |
9290 | (clobber (reg:SI 12)) | |
3c67b673 | 9291 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9292 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
9293 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9294 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9295 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9296 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9297 | && REGNO (operands[4]) == 5" |
9298 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9299 | [(set_attr "type" "load") |
9300 | (set_attr "length" "8")]) | |
7e69e155 | 9301 | |
09a625f7 TR |
9302 | (define_insn "" |
9303 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9304 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9305 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9306 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9307 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9308 | (clobber (reg:SI 6)) | |
9309 | (clobber (reg:SI 7)) | |
9310 | (clobber (reg:SI 8)) | |
9311 | (clobber (reg:SI 9)) | |
9312 | (clobber (reg:SI 10)) | |
9313 | (clobber (reg:SI 11)) | |
9314 | (clobber (reg:SI 12)) | |
9315 | (clobber (match_scratch:SI 5 "X"))] | |
9316 | "TARGET_STRING && TARGET_POWERPC64 | |
9317 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) | |
9318 | || INTVAL (operands[2]) == 0) | |
9319 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
9320 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
9321 | && REGNO (operands[4]) == 5" | |
9322 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9323 | [(set_attr "type" "load") | |
9324 | (set_attr "length" "8")]) | |
9325 | ||
7e69e155 | 9326 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the |
f9562f27 DE |
9327 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
9328 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9329 | (define_expand "movstrsi_6reg" |
b6c9286a MM |
9330 | [(parallel [(set (match_operand 0 "" "") |
9331 | (match_operand 1 "" "")) | |
9332 | (use (match_operand 2 "" "")) | |
9333 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9334 | (clobber (reg:SI 5)) |
9335 | (clobber (reg:SI 6)) | |
7e69e155 MM |
9336 | (clobber (reg:SI 7)) |
9337 | (clobber (reg:SI 8)) | |
9338 | (clobber (reg:SI 9)) | |
9339 | (clobber (reg:SI 10)) | |
3c67b673 | 9340 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9341 | "TARGET_STRING" |
9342 | "") | |
9343 | ||
9344 | (define_insn "" | |
52d3af72 DE |
9345 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9346 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9347 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9348 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9349 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9350 | (clobber (reg:SI 6)) |
9351 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9352 | (clobber (reg:SI 8)) |
9353 | (clobber (reg:SI 9)) | |
9354 | (clobber (reg:SI 10)) | |
3c67b673 | 9355 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9356 | "TARGET_STRING && TARGET_POWER |
9357 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
9358 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9359 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9360 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9361 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9362 | [(set_attr "type" "load") |
9363 | (set_attr "length" "8")]) | |
7e69e155 MM |
9364 | |
9365 | (define_insn "" | |
52d3af72 DE |
9366 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9367 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9368 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9369 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9370 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9371 | (clobber (reg:SI 6)) |
9372 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9373 | (clobber (reg:SI 8)) |
9374 | (clobber (reg:SI 9)) | |
9375 | (clobber (reg:SI 10)) | |
3c67b673 | 9376 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9377 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9378 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
9379 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9380 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9381 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9382 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9383 | [(set_attr "type" "load") |
9384 | (set_attr "length" "8")]) | |
7e69e155 | 9385 | |
09a625f7 TR |
9386 | (define_insn "" |
9387 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9388 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9389 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9390 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9391 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9392 | (clobber (reg:SI 6)) | |
9393 | (clobber (reg:SI 7)) | |
9394 | (clobber (reg:SI 8)) | |
9395 | (clobber (reg:SI 9)) | |
9396 | (clobber (reg:SI 10)) | |
9397 | (clobber (match_scratch:SI 5 "X"))] | |
9398 | "TARGET_STRING && TARGET_POWERPC64 | |
9399 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 | |
9400 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) | |
9401 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9402 | && REGNO (operands[4]) == 5" | |
9403 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9404 | [(set_attr "type" "load") | |
9405 | (set_attr "length" "8")]) | |
9406 | ||
f9562f27 DE |
9407 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
9408 | ;; problems with TImode. | |
9409 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 9410 | (define_expand "movstrsi_4reg" |
b6c9286a MM |
9411 | [(parallel [(set (match_operand 0 "" "") |
9412 | (match_operand 1 "" "")) | |
9413 | (use (match_operand 2 "" "")) | |
9414 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9415 | (clobber (reg:SI 5)) |
9416 | (clobber (reg:SI 6)) | |
9417 | (clobber (reg:SI 7)) | |
9418 | (clobber (reg:SI 8)) | |
3c67b673 | 9419 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9420 | "TARGET_STRING" |
9421 | "") | |
9422 | ||
9423 | (define_insn "" | |
52d3af72 DE |
9424 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9425 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9426 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9427 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9428 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9429 | (clobber (reg:SI 6)) |
9430 | (clobber (reg:SI 7)) | |
9431 | (clobber (reg:SI 8)) | |
3c67b673 | 9432 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9433 | "TARGET_STRING && TARGET_POWER |
9434 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
9435 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9436 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9437 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9438 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9439 | [(set_attr "type" "load") |
9440 | (set_attr "length" "8")]) | |
7e69e155 MM |
9441 | |
9442 | (define_insn "" | |
52d3af72 DE |
9443 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9444 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9445 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9446 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9447 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9448 | (clobber (reg:SI 6)) |
9449 | (clobber (reg:SI 7)) | |
9450 | (clobber (reg:SI 8)) | |
3c67b673 | 9451 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9452 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9453 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
9454 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9455 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9456 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9457 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9458 | [(set_attr "type" "load") |
9459 | (set_attr "length" "8")]) | |
7e69e155 | 9460 | |
09a625f7 TR |
9461 | (define_insn "" |
9462 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9463 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9464 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9465 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9466 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9467 | (clobber (reg:SI 6)) | |
9468 | (clobber (reg:SI 7)) | |
9469 | (clobber (reg:SI 8)) | |
9470 | (clobber (match_scratch:SI 5 "X"))] | |
9471 | "TARGET_STRING && TARGET_POWERPC64 | |
9472 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
9473 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) | |
9474 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9475 | && REGNO (operands[4]) == 5" | |
9476 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9477 | [(set_attr "type" "load") | |
9478 | (set_attr "length" "8")]) | |
9479 | ||
7e69e155 MM |
9480 | ;; Move up to 8 bytes at a time. |
9481 | (define_expand "movstrsi_2reg" | |
b6c9286a MM |
9482 | [(parallel [(set (match_operand 0 "" "") |
9483 | (match_operand 1 "" "")) | |
9484 | (use (match_operand 2 "" "")) | |
9485 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9486 | (clobber (match_scratch:DI 4 "")) |
9487 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 9488 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
9489 | "") |
9490 | ||
9491 | (define_insn "" | |
52d3af72 DE |
9492 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9493 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9494 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9495 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9496 | (clobber (match_scratch:DI 4 "=&r")) | |
9497 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 9498 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
9499 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
9500 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9501 | [(set_attr "type" "load") |
9502 | (set_attr "length" "8")]) | |
7e69e155 MM |
9503 | |
9504 | (define_insn "" | |
52d3af72 DE |
9505 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9506 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9507 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9508 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9509 | (clobber (match_scratch:DI 4 "=&r")) | |
9510 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 9511 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 9512 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 9513 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9514 | [(set_attr "type" "load") |
9515 | (set_attr "length" "8")]) | |
7e69e155 MM |
9516 | |
9517 | ;; Move up to 4 bytes at a time. | |
9518 | (define_expand "movstrsi_1reg" | |
b6c9286a MM |
9519 | [(parallel [(set (match_operand 0 "" "") |
9520 | (match_operand 1 "" "")) | |
9521 | (use (match_operand 2 "" "")) | |
9522 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9523 | (clobber (match_scratch:SI 4 "")) |
9524 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
9525 | "TARGET_STRING" |
9526 | "") | |
9527 | ||
9528 | (define_insn "" | |
52d3af72 DE |
9529 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9530 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9531 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9532 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9533 | (clobber (match_scratch:SI 4 "=&r")) | |
9534 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
9535 | "TARGET_STRING && TARGET_POWER |
9536 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9537 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9538 | [(set_attr "type" "load") |
9539 | (set_attr "length" "8")]) | |
7e69e155 MM |
9540 | |
9541 | (define_insn "" | |
52d3af72 DE |
9542 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9543 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9544 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9545 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9546 | (clobber (match_scratch:SI 4 "=&r")) | |
9547 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 9548 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9549 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
09a625f7 TR |
9550 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
9551 | [(set_attr "type" "load") | |
9552 | (set_attr "length" "8")]) | |
9553 | ||
9554 | (define_insn "" | |
9555 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9556 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9557 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9558 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9559 | (clobber (match_scratch:SI 4 "=&r")) | |
9560 | (clobber (match_scratch:SI 5 "X"))] | |
9561 | "TARGET_STRING && TARGET_POWERPC64 | |
9562 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9563 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9564 | [(set_attr "type" "load") |
9565 | (set_attr "length" "8")]) | |
7e69e155 | 9566 | |
1fd4e8c1 | 9567 | \f |
7e69e155 | 9568 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
9569 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
9570 | ;; do cases where the increment is not the size of the object. | |
9571 | ;; | |
9572 | ;; In all these cases, we use operands 0 and 1 for the register being | |
9573 | ;; incremented because those are the operands that local-alloc will | |
9574 | ;; tie and these are the pair most likely to be tieable (and the ones | |
9575 | ;; that will benefit the most). | |
9576 | ||
38c1f2d7 | 9577 | (define_insn "*movdi_update1" |
51b8fc2c | 9578 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 9579 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 9580 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) |
51b8fc2c RK |
9581 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") |
9582 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9583 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9584 | "@ |
9585 | ldux %3,%0,%2 | |
9586 | ldu %3,%2(%0)" | |
9587 | [(set_attr "type" "load")]) | |
9588 | ||
38c1f2d7 | 9589 | (define_insn "*movdi_update2" |
287f13ff RK |
9590 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") |
9591 | (sign_extend:DI | |
9592 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
9593 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
9594 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
9595 | (plus:DI (match_dup 1) (match_dup 2)))] | |
9596 | "TARGET_POWERPC64" | |
9597 | "lwaux %3,%0,%2" | |
9598 | [(set_attr "type" "load")]) | |
9599 | ||
4697a36c | 9600 | (define_insn "movdi_update" |
51b8fc2c | 9601 | [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 9602 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))) |
51b8fc2c RK |
9603 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) |
9604 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
9605 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9606 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9607 | "@ |
9608 | stdux %3,%0,%2 | |
b7ff3d82 DE |
9609 | stdu %3,%2(%0)" |
9610 | [(set_attr "type" "store")]) | |
51b8fc2c | 9611 | |
38c1f2d7 | 9612 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
9613 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
9614 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9615 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9616 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
9617 | (plus:SI (match_dup 1) (match_dup 2)))] |
9618 | "" | |
9619 | "@ | |
ca7f5001 RK |
9620 | {lux|lwzux} %3,%0,%2 |
9621 | {lu|lwzu} %3,%2(%0)" | |
cfb557c4 | 9622 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9623 | |
4697a36c | 9624 | (define_insn "movsi_update" |
cd2b37d9 | 9625 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9626 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9627 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
9628 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9629 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9630 | "TARGET_UPDATE" |
1fd4e8c1 | 9631 | "@ |
ca7f5001 | 9632 | {stux|stwux} %3,%0,%2 |
b7ff3d82 DE |
9633 | {stu|stwu} %3,%2(%0)" |
9634 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 9635 | |
38c1f2d7 | 9636 | (define_insn "*movhi_update" |
cd2b37d9 RK |
9637 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
9638 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9639 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9640 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9641 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9642 | "TARGET_UPDATE" |
1fd4e8c1 | 9643 | "@ |
5f243543 RK |
9644 | lhzux %3,%0,%2 |
9645 | lhzu %3,%2(%0)" | |
cfb557c4 | 9646 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9647 | |
38c1f2d7 | 9648 | (define_insn "*movhi_update2" |
cd2b37d9 | 9649 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9650 | (zero_extend:SI |
cd2b37d9 | 9651 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9652 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9653 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9654 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9655 | "TARGET_UPDATE" |
1fd4e8c1 | 9656 | "@ |
5f243543 RK |
9657 | lhzux %3,%0,%2 |
9658 | lhzu %3,%2(%0)" | |
cfb557c4 | 9659 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9660 | |
38c1f2d7 | 9661 | (define_insn "*movhi_update3" |
cd2b37d9 | 9662 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9663 | (sign_extend:SI |
cd2b37d9 | 9664 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9665 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9666 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9667 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9668 | "TARGET_UPDATE" |
1fd4e8c1 | 9669 | "@ |
5f243543 RK |
9670 | lhaux %3,%0,%2 |
9671 | lhau %3,%2(%0)" | |
cfb557c4 | 9672 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9673 | |
38c1f2d7 | 9674 | (define_insn "*movhi_update4" |
cd2b37d9 | 9675 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9676 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9677 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
9678 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9679 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9680 | "TARGET_UPDATE" |
1fd4e8c1 | 9681 | "@ |
5f243543 | 9682 | sthux %3,%0,%2 |
b7ff3d82 DE |
9683 | sthu %3,%2(%0)" |
9684 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 9685 | |
38c1f2d7 | 9686 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
9687 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
9688 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9689 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9690 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9691 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9692 | "TARGET_UPDATE" |
1fd4e8c1 | 9693 | "@ |
5f243543 RK |
9694 | lbzux %3,%0,%2 |
9695 | lbzu %3,%2(%0)" | |
cfb557c4 | 9696 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9697 | |
38c1f2d7 | 9698 | (define_insn "*movqi_update2" |
cd2b37d9 | 9699 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9700 | (zero_extend:SI |
cd2b37d9 | 9701 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9702 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9703 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9704 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9705 | "TARGET_UPDATE" |
1fd4e8c1 | 9706 | "@ |
5f243543 RK |
9707 | lbzux %3,%0,%2 |
9708 | lbzu %3,%2(%0)" | |
cfb557c4 | 9709 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9710 | |
38c1f2d7 | 9711 | (define_insn "*movqi_update3" |
cd2b37d9 | 9712 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9713 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9714 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
9715 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9716 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9717 | "TARGET_UPDATE" |
1fd4e8c1 | 9718 | "@ |
5f243543 | 9719 | stbux %3,%0,%2 |
b7ff3d82 DE |
9720 | stbu %3,%2(%0)" |
9721 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 9722 | |
38c1f2d7 | 9723 | (define_insn "*movsf_update1" |
cd2b37d9 | 9724 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 9725 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9726 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9727 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9728 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9729 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9730 | "@ |
5f243543 RK |
9731 | lfsux %3,%0,%2 |
9732 | lfsu %3,%2(%0)" | |
cfb557c4 | 9733 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 9734 | |
38c1f2d7 | 9735 | (define_insn "*movsf_update2" |
cd2b37d9 | 9736 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9737 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9738 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
9739 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9740 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9741 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9742 | "@ |
85fff2f3 | 9743 | stfsux %3,%0,%2 |
b7ff3d82 DE |
9744 | stfsu %3,%2(%0)" |
9745 | [(set_attr "type" "fpstore")]) | |
1fd4e8c1 | 9746 | |
38c1f2d7 MM |
9747 | (define_insn "*movsf_update3" |
9748 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
9749 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9750 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
9751 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9752 | (plus:SI (match_dup 1) (match_dup 2)))] | |
9753 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
9754 | "@ | |
9755 | {lux|lwzux} %3,%0,%2 | |
9756 | {lu|lwzu} %3,%2(%0)" | |
9757 | [(set_attr "type" "load")]) | |
9758 | ||
9759 | (define_insn "*movsf_update4" | |
9760 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9761 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
9762 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
9763 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9764 | (plus:SI (match_dup 1) (match_dup 2)))] | |
9765 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
9766 | "@ | |
9767 | {stux|stwux} %3,%0,%2 | |
9768 | {stu|stwu} %3,%2(%0)" | |
9769 | [(set_attr "type" "store")]) | |
9770 | ||
9771 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
9772 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
9773 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9774 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9775 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9776 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9777 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9778 | "@ |
5f243543 RK |
9779 | lfdux %3,%0,%2 |
9780 | lfdu %3,%2(%0)" | |
cfb557c4 | 9781 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 9782 | |
38c1f2d7 | 9783 | (define_insn "*movdf_update2" |
cd2b37d9 | 9784 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9785 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9786 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
9787 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9788 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9789 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9790 | "@ |
5f243543 | 9791 | stfdux %3,%0,%2 |
b7ff3d82 DE |
9792 | stfdu %3,%2(%0)" |
9793 | [(set_attr "type" "fpstore")]) | |
4c70a4f3 RK |
9794 | |
9795 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
9796 | ||
9797 | (define_peephole | |
9798 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
9799 | (match_operand:DF 1 "memory_operand" "")) | |
9800 | (set (match_operand:DF 2 "gpc_reg_operand" "=f") | |
9801 | (match_operand:DF 3 "memory_operand" ""))] | |
9802 | "TARGET_POWER2 | |
d14a6d05 | 9803 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
9804 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
9805 | && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) | |
9806 | && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" | |
9807 | "lfq%U1%X1 %0,%1") | |
9808 | ||
9809 | (define_peephole | |
9810 | [(set (match_operand:DF 0 "memory_operand" "") | |
9811 | (match_operand:DF 1 "gpc_reg_operand" "f")) | |
9812 | (set (match_operand:DF 2 "memory_operand" "") | |
9813 | (match_operand:DF 3 "gpc_reg_operand" "f"))] | |
9814 | "TARGET_POWER2 | |
d14a6d05 | 9815 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
9816 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
9817 | && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) | |
9818 | && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" | |
9819 | "stfq%U0%X0 %1,%0") | |
1fd4e8c1 RK |
9820 | \f |
9821 | ;; Next come insns related to the calling sequence. | |
9822 | ;; | |
9823 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 9824 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
9825 | |
9826 | (define_expand "allocate_stack" | |
52d3af72 | 9827 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9828 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
9829 | (set (reg 1) | |
9830 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
9831 | "" |
9832 | " | |
4697a36c | 9833 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 9834 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 9835 | rtx neg_op0; |
1fd4e8c1 RK |
9836 | |
9837 | emit_move_insn (chain, stack_bot); | |
4697a36c | 9838 | |
a157febd GK |
9839 | /* Check stack bounds if necessary. */ |
9840 | if (current_function_limit_stack) | |
9841 | { | |
9842 | rtx available; | |
9843 | available = expand_binop (Pmode, sub_optab, | |
9844 | stack_pointer_rtx, stack_limit_rtx, | |
9845 | NULL_RTX, 1, OPTAB_WIDEN); | |
9846 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
9847 | } | |
9848 | ||
e9a25f70 JL |
9849 | if (GET_CODE (operands[1]) != CONST_INT |
9850 | || INTVAL (operands[1]) < -32767 | |
9851 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
9852 | { |
9853 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 9854 | if (TARGET_32BIT) |
e9a25f70 | 9855 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 9856 | else |
e9a25f70 | 9857 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
9858 | } |
9859 | else | |
e9a25f70 | 9860 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 9861 | |
38c1f2d7 MM |
9862 | if (TARGET_UPDATE) |
9863 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) | |
9864 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); | |
4697a36c | 9865 | |
38c1f2d7 MM |
9866 | else |
9867 | { | |
9868 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
9869 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 9870 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 9871 | } |
e9a25f70 JL |
9872 | |
9873 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
9874 | DONE; |
9875 | }") | |
59257ff7 RK |
9876 | |
9877 | ;; These patterns say how to save and restore the stack pointer. We need not | |
9878 | ;; save the stack pointer at function level since we are careful to | |
9879 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9880 | ;; when we restore the stack pointer. | |
9881 | ;; | |
9882 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9883 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9884 | ;; save area is a memory location. | |
9885 | ||
9886 | (define_expand "save_stack_function" | |
ff381587 MM |
9887 | [(match_operand 0 "any_operand" "") |
9888 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9889 | "" |
ff381587 | 9890 | "DONE;") |
59257ff7 RK |
9891 | |
9892 | (define_expand "restore_stack_function" | |
ff381587 MM |
9893 | [(match_operand 0 "any_operand" "") |
9894 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9895 | "" |
ff381587 | 9896 | "DONE;") |
59257ff7 RK |
9897 | |
9898 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
9899 | [(use (match_operand 0 "register_operand" "")) |
9900 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 9901 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 9902 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
9903 | "" |
9904 | " | |
dfdfa60f DE |
9905 | { |
9906 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 9907 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 9908 | }") |
59257ff7 RK |
9909 | |
9910 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
9911 | [(match_operand 0 "memory_operand" "") |
9912 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
9913 | "" |
9914 | " | |
9915 | { | |
a260abc9 | 9916 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
9917 | |
9918 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 9919 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
c5c76735 JL |
9920 | emit_move_insn (operand_subword (operands[0], 0, 0, |
9921 | (TARGET_32BIT ? DImode : TImode)), | |
a260abc9 DE |
9922 | temp); |
9923 | emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)), | |
9924 | operands[1]); | |
59257ff7 RK |
9925 | DONE; |
9926 | }") | |
7e69e155 | 9927 | |
59257ff7 | 9928 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
9929 | [(match_operand 0 "register_operand" "") |
9930 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
9931 | "" |
9932 | " | |
9933 | { | |
a260abc9 | 9934 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
9935 | |
9936 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 DE |
9937 | emit_move_insn (temp, |
9938 | operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode))); | |
9939 | emit_move_insn (operands[0], | |
c5c76735 JL |
9940 | operand_subword (operands[1], 1, 0, |
9941 | (TARGET_32BIT ? DImode : TImode))); | |
39403d82 | 9942 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
9943 | DONE; |
9944 | }") | |
9ebbca7d GK |
9945 | \f |
9946 | ;; TOC register handling. | |
b6c9286a | 9947 | |
9ebbca7d | 9948 | ;; Code to initialize the TOC register... |
f0f6a223 | 9949 | |
9ebbca7d | 9950 | (define_insn "load_toc_aix_si" |
e72247f4 | 9951 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
46aaf10d DE |
9952 | (unspec:SI [(const_int 0)] 7)) |
9953 | (use (reg:SI 2))])] | |
2bfcf297 | 9954 | "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" |
f0f6a223 RK |
9955 | "* |
9956 | { | |
9ebbca7d GK |
9957 | char buf[30]; |
9958 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 9959 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9960 | operands[2] = gen_rtx_REG (Pmode, 2); |
9961 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
9962 | }" |
9963 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
9964 | |
9965 | (define_insn "load_toc_aix_di" | |
e72247f4 | 9966 | [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
46aaf10d DE |
9967 | (unspec:DI [(const_int 0)] 7)) |
9968 | (use (reg:DI 2))])] | |
2bfcf297 | 9969 | "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" |
9ebbca7d GK |
9970 | "* |
9971 | { | |
9972 | char buf[30]; | |
f585a356 DE |
9973 | #ifdef TARGET_RELOCATABLE |
9974 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", | |
9975 | !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); | |
9976 | #else | |
9ebbca7d | 9977 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); |
f585a356 | 9978 | #endif |
2bfcf297 DB |
9979 | if (TARGET_ELF) |
9980 | strcat (buf, \"@toc\"); | |
a8a05998 | 9981 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9982 | operands[2] = gen_rtx_REG (Pmode, 2); |
9983 | return \"ld %0,%1(%2)\"; | |
9984 | }" | |
9985 | [(set_attr "type" "load")]) | |
9986 | ||
9987 | (define_insn "load_toc_v4_pic_si" | |
9988 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9989 | (unspec:SI [(const_int 0)] 7))] | |
f607bc57 | 9990 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" |
9ebbca7d GK |
9991 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
9992 | [(set_attr "type" "branch") | |
9993 | (set_attr "length" "4")]) | |
9994 | ||
9ebbca7d GK |
9995 | (define_insn "load_toc_v4_PIC_1" |
9996 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9997 | (match_operand:SI 1 "immediate_operand" "s")) | |
9998 | (unspec [(match_dup 1)] 7)] | |
9999 | "TARGET_ELF && flag_pic == 2" | |
10000 | "bl %1\\n%1:" | |
10001 | [(set_attr "type" "branch") | |
10002 | (set_attr "length" "4")]) | |
10003 | ||
10004 | (define_insn "load_toc_v4_PIC_1b" | |
10005 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10006 | (match_operand:SI 1 "immediate_operand" "s")) | |
10007 | (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)] | |
10008 | "TARGET_ELF && flag_pic == 2" | |
10009 | "bl %1\\n\\t.long %2-%1+4\\n%1:" | |
10010 | [(set_attr "type" "branch") | |
10011 | (set_attr "length" "8")]) | |
10012 | ||
10013 | (define_insn "load_toc_v4_PIC_2" | |
f585a356 DE |
10014 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10015 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
9ebbca7d GK |
10016 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") |
10017 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
10018 | "TARGET_ELF && flag_pic == 2" | |
10019 | "{l|lwz} %0,%2-%3(%1)" | |
10020 | [(set_attr "type" "load")]) | |
10021 | ||
ee890fe2 SS |
10022 | (define_insn "load_macho_picbase" |
10023 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10024 | (unspec:SI [(const_int 0)] 15))] | |
10025 | "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" | |
10026 | "* | |
10027 | { | |
10028 | #if TARGET_MACHO | |
10029 | char *picbase = machopic_function_base_name (); | |
10030 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1)); | |
10031 | #endif | |
10032 | return \"bcl 20,31,%1\\n%1:\"; | |
10033 | }" | |
10034 | [(set_attr "type" "branch") | |
10035 | (set_attr "length" "4")]) | |
10036 | ||
9ebbca7d GK |
10037 | ;; If the TOC is shared over a translation unit, as happens with all |
10038 | ;; the kinds of PIC that we support, we need to restore the TOC | |
10039 | ;; pointer only when jumping over units of translation. | |
10040 | ||
10041 | (define_expand "builtin_setjmp_receiver" | |
10042 | [(use (label_ref (match_operand 0 "" "")))] | |
f607bc57 | 10043 | "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
9ebbca7d GK |
10044 | || (TARGET_TOC && TARGET_MINIMAL_TOC)" |
10045 | " | |
10046 | { | |
10047 | rs6000_emit_load_toc_table (FALSE); | |
10048 | DONE; | |
10049 | }") | |
10050 | \f | |
10051 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
10052 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
10053 | ;; pointer to its TOC, and whose third word contains a value to place in the |
10054 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 10055 | ;; "trampoline" need not have any executable code. |
b6c9286a | 10056 | |
cccf3bdc DE |
10057 | (define_expand "call_indirect_aix32" |
10058 | [(set (match_dup 2) | |
10059 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
10060 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10061 | (reg:SI 2)) | |
10062 | (set (reg:SI 2) | |
10063 | (mem:SI (plus:SI (match_dup 0) | |
10064 | (const_int 4)))) | |
10065 | (set (reg:SI 11) | |
10066 | (mem:SI (plus:SI (match_dup 0) | |
10067 | (const_int 8)))) | |
10068 | (parallel [(call (mem:SI (match_dup 2)) | |
10069 | (match_operand 1 "" "")) | |
10070 | (use (reg:SI 2)) | |
10071 | (use (reg:SI 11)) | |
10072 | (set (reg:SI 2) | |
10073 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10074 | (clobber (scratch:SI))])] | |
10075 | "TARGET_32BIT" | |
10076 | " | |
10077 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10078 | |
cccf3bdc DE |
10079 | (define_expand "call_indirect_aix64" |
10080 | [(set (match_dup 2) | |
10081 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
10082 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10083 | (reg:DI 2)) | |
10084 | (set (reg:DI 2) | |
10085 | (mem:DI (plus:DI (match_dup 0) | |
10086 | (const_int 8)))) | |
10087 | (set (reg:DI 11) | |
10088 | (mem:DI (plus:DI (match_dup 0) | |
10089 | (const_int 16)))) | |
10090 | (parallel [(call (mem:SI (match_dup 2)) | |
10091 | (match_operand 1 "" "")) | |
10092 | (use (reg:DI 2)) | |
10093 | (use (reg:DI 11)) | |
10094 | (set (reg:DI 2) | |
10095 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10096 | (clobber (scratch:SI))])] | |
10097 | "TARGET_64BIT" | |
10098 | " | |
10099 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 10100 | |
cccf3bdc DE |
10101 | (define_expand "call_value_indirect_aix32" |
10102 | [(set (match_dup 3) | |
10103 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10104 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10105 | (reg:SI 2)) | |
10106 | (set (reg:SI 2) | |
10107 | (mem:SI (plus:SI (match_dup 1) | |
10108 | (const_int 4)))) | |
10109 | (set (reg:SI 11) | |
10110 | (mem:SI (plus:SI (match_dup 1) | |
10111 | (const_int 8)))) | |
10112 | (parallel [(set (match_operand 0 "" "") | |
10113 | (call (mem:SI (match_dup 3)) | |
10114 | (match_operand 2 "" ""))) | |
10115 | (use (reg:SI 2)) | |
10116 | (use (reg:SI 11)) | |
10117 | (set (reg:SI 2) | |
10118 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10119 | (clobber (scratch:SI))])] | |
10120 | "TARGET_32BIT" | |
10121 | " | |
10122 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10123 | |
cccf3bdc DE |
10124 | (define_expand "call_value_indirect_aix64" |
10125 | [(set (match_dup 3) | |
10126 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10127 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10128 | (reg:DI 2)) | |
10129 | (set (reg:DI 2) | |
10130 | (mem:DI (plus:DI (match_dup 1) | |
10131 | (const_int 8)))) | |
10132 | (set (reg:DI 11) | |
10133 | (mem:DI (plus:DI (match_dup 1) | |
10134 | (const_int 16)))) | |
10135 | (parallel [(set (match_operand 0 "" "") | |
10136 | (call (mem:SI (match_dup 3)) | |
10137 | (match_operand 2 "" ""))) | |
10138 | (use (reg:DI 2)) | |
10139 | (use (reg:DI 11)) | |
10140 | (set (reg:DI 2) | |
10141 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10142 | (clobber (scratch:SI))])] | |
10143 | "TARGET_64BIT" | |
10144 | " | |
10145 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 10146 | |
b6c9286a | 10147 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 10148 | (define_expand "call" |
a260abc9 | 10149 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 10150 | (match_operand 1 "" "")) |
4697a36c | 10151 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
10152 | (clobber (scratch:SI))])] |
10153 | "" | |
10154 | " | |
10155 | { | |
ee890fe2 SS |
10156 | #if TARGET_MACHO |
10157 | if (flag_pic) | |
10158 | operands[0] = machopic_indirect_call_target (operands[0]); | |
10159 | #endif | |
10160 | ||
1fd4e8c1 RK |
10161 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) |
10162 | abort (); | |
10163 | ||
10164 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 10165 | |
6a4cee5f MM |
10166 | if (GET_CODE (operands[0]) != SYMBOL_REF |
10167 | || (INTVAL (operands[2]) & CALL_LONG) != 0) | |
1fd4e8c1 | 10168 | { |
6a4cee5f MM |
10169 | if (INTVAL (operands[2]) & CALL_LONG) |
10170 | operands[0] = rs6000_longcall_ref (operands[0]); | |
10171 | ||
cccf3bdc DE |
10172 | if (DEFAULT_ABI == ABI_V4 |
10173 | || DEFAULT_ABI == ABI_AIX_NODESC | |
f607bc57 | 10174 | || DEFAULT_ABI == ABI_DARWIN) |
cccf3bdc | 10175 | operands[0] = force_reg (Pmode, operands[0]); |
1fd4e8c1 | 10176 | |
cccf3bdc DE |
10177 | else if (DEFAULT_ABI == ABI_AIX) |
10178 | { | |
10179 | /* AIX function pointers are really pointers to a three word | |
10180 | area. */ | |
10181 | emit_call_insn (TARGET_32BIT | |
10182 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
10183 | operands[0]), | |
10184 | operands[1]) | |
10185 | : gen_call_indirect_aix64 (force_reg (DImode, | |
10186 | operands[0]), | |
10187 | operands[1])); | |
10188 | DONE; | |
b6c9286a | 10189 | } |
cccf3bdc DE |
10190 | else |
10191 | abort (); | |
1fd4e8c1 RK |
10192 | } |
10193 | }") | |
10194 | ||
10195 | (define_expand "call_value" | |
10196 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 10197 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 10198 | (match_operand 2 "" ""))) |
4697a36c | 10199 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
10200 | (clobber (scratch:SI))])] |
10201 | "" | |
10202 | " | |
10203 | { | |
ee890fe2 SS |
10204 | #if TARGET_MACHO |
10205 | if (flag_pic) | |
10206 | operands[1] = machopic_indirect_call_target (operands[1]); | |
10207 | #endif | |
10208 | ||
1fd4e8c1 RK |
10209 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) |
10210 | abort (); | |
10211 | ||
10212 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 10213 | |
6a4cee5f MM |
10214 | if (GET_CODE (operands[1]) != SYMBOL_REF |
10215 | || (INTVAL (operands[3]) & CALL_LONG) != 0) | |
1fd4e8c1 | 10216 | { |
6756293c | 10217 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
10218 | operands[1] = rs6000_longcall_ref (operands[1]); |
10219 | ||
cccf3bdc DE |
10220 | if (DEFAULT_ABI == ABI_V4 |
10221 | || DEFAULT_ABI == ABI_AIX_NODESC | |
f607bc57 | 10222 | || DEFAULT_ABI == ABI_DARWIN) |
cccf3bdc | 10223 | operands[0] = force_reg (Pmode, operands[0]); |
1fd4e8c1 | 10224 | |
cccf3bdc DE |
10225 | else if (DEFAULT_ABI == ABI_AIX) |
10226 | { | |
10227 | /* AIX function pointers are really pointers to a three word | |
10228 | area. */ | |
10229 | emit_call_insn (TARGET_32BIT | |
10230 | ? gen_call_value_indirect_aix32 (operands[0], | |
10231 | force_reg (SImode, | |
10232 | operands[1]), | |
10233 | operands[2]) | |
10234 | : gen_call_value_indirect_aix64 (operands[0], | |
10235 | force_reg (DImode, | |
10236 | operands[1]), | |
10237 | operands[2])); | |
10238 | DONE; | |
b6c9286a | 10239 | } |
cccf3bdc DE |
10240 | else |
10241 | abort (); | |
1fd4e8c1 RK |
10242 | } |
10243 | }") | |
10244 | ||
04780ee7 | 10245 | ;; Call to function in current module. No TOC pointer reload needed. |
4697a36c MM |
10246 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
10247 | ;; either the function was not prototyped, or it was prototyped as a | |
10248 | ;; variable argument function. It is > 0 if FP registers were passed | |
10249 | ;; and < 0 if they were not. | |
04780ee7 | 10250 | |
a260abc9 | 10251 | (define_insn "*call_local32" |
4697a36c MM |
10252 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
10253 | (match_operand 1 "" "g,g")) | |
10254 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10255 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 10256 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
10257 | "* |
10258 | { | |
6a4cee5f MM |
10259 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
10260 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10261 | ||
10262 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10263 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 10264 | |
a226df46 | 10265 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 10266 | }" |
b7ff3d82 DE |
10267 | [(set_attr "type" "branch") |
10268 | (set_attr "length" "4,8")]) | |
04780ee7 | 10269 | |
a260abc9 DE |
10270 | (define_insn "*call_local64" |
10271 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10272 | (match_operand 1 "" "g,g")) | |
10273 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10274 | (clobber (match_scratch:SI 3 "=l,l"))] | |
10275 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10276 | "* | |
10277 | { | |
10278 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10279 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10280 | ||
10281 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10282 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10283 | ||
10284 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
10285 | }" | |
10286 | [(set_attr "type" "branch") | |
10287 | (set_attr "length" "4,8")]) | |
10288 | ||
cccf3bdc | 10289 | (define_insn "*call_value_local32" |
d18dba68 | 10290 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10291 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) |
10292 | (match_operand 2 "" "g,g"))) | |
10293 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10294 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10295 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10296 | "* | |
10297 | { | |
10298 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10299 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10300 | ||
10301 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10302 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10303 | ||
10304 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10305 | }" | |
10306 | [(set_attr "type" "branch") | |
10307 | (set_attr "length" "4,8")]) | |
10308 | ||
10309 | ||
cccf3bdc | 10310 | (define_insn "*call_value_local64" |
d18dba68 | 10311 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10312 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) |
10313 | (match_operand 2 "" "g,g"))) | |
10314 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10315 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10316 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10317 | "* | |
10318 | { | |
10319 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10320 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10321 | ||
10322 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10323 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10324 | ||
10325 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10326 | }" | |
10327 | [(set_attr "type" "branch") | |
10328 | (set_attr "length" "4,8")]) | |
10329 | ||
04780ee7 | 10330 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 10331 | ;; pointer (r2) after the call unless this is System V. |
4697a36c MM |
10332 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
10333 | ;; either the function was not prototyped, or it was prototyped as a | |
10334 | ;; variable argument function. It is > 0 if FP registers were passed | |
10335 | ;; and < 0 if they were not. | |
04780ee7 | 10336 | |
cccf3bdc DE |
10337 | (define_insn "*call_indirect_nonlocal_aix32" |
10338 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) | |
10339 | (match_operand 1 "" "g")) | |
10340 | (use (reg:SI 2)) | |
10341 | (use (reg:SI 11)) | |
10342 | (set (reg:SI 2) | |
10343 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
c77e04ae | 10344 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10345 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
10346 | "b%T0l\;{l|lwz} 2,20(1)" | |
10347 | [(set_attr "type" "jmpreg") | |
10348 | (set_attr "length" "8")]) | |
10349 | ||
a260abc9 | 10350 | (define_insn "*call_nonlocal_aix32" |
cc4d5fec | 10351 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10352 | (match_operand 1 "" "g")) |
10353 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10354 | (clobber (match_scratch:SI 3 "=l"))] | |
10355 | "TARGET_32BIT | |
10356 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10357 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10358 | "bl %z0\;%." |
b7ff3d82 | 10359 | [(set_attr "type" "branch") |
cccf3bdc DE |
10360 | (set_attr "length" "8")]) |
10361 | ||
10362 | (define_insn "*call_indirect_nonlocal_aix64" | |
10363 | [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) | |
10364 | (match_operand 1 "" "g")) | |
10365 | (use (reg:DI 2)) | |
10366 | (use (reg:DI 11)) | |
10367 | (set (reg:DI 2) | |
10368 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
c77e04ae | 10369 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10370 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
10371 | "b%T0l\;ld 2,40(1)" | |
10372 | [(set_attr "type" "jmpreg") | |
10373 | (set_attr "length" "8")]) | |
59313e4e | 10374 | |
a260abc9 | 10375 | (define_insn "*call_nonlocal_aix64" |
cc4d5fec | 10376 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10377 | (match_operand 1 "" "g")) |
10378 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10379 | (clobber (match_scratch:SI 3 "=l"))] | |
9ebbca7d GK |
10380 | "TARGET_64BIT |
10381 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10382 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10383 | "bl %z0\;%." |
a260abc9 | 10384 | [(set_attr "type" "branch") |
cccf3bdc | 10385 | (set_attr "length" "8")]) |
7509c759 | 10386 | |
cccf3bdc | 10387 | (define_insn "*call_value_indirect_nonlocal_aix32" |
d18dba68 | 10388 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10389 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) |
10390 | (match_operand 2 "" "g"))) | |
10391 | (use (reg:SI 2)) | |
10392 | (use (reg:SI 11)) | |
10393 | (set (reg:SI 2) | |
10394 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10395 | (clobber (match_scratch:SI 3 "=l"))] | |
10396 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" | |
10397 | "b%T1l\;{l|lwz} 2,20(1)" | |
10398 | [(set_attr "type" "jmpreg") | |
10399 | (set_attr "length" "8")]) | |
1fd4e8c1 | 10400 | |
cccf3bdc | 10401 | (define_insn "*call_value_nonlocal_aix32" |
d18dba68 | 10402 | [(set (match_operand 0 "" "") |
cc4d5fec | 10403 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10404 | (match_operand 2 "" "g"))) |
10405 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10406 | (clobber (match_scratch:SI 4 "=l"))] | |
10407 | "TARGET_32BIT | |
10408 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10409 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 10410 | "bl %z1\;%." |
b7ff3d82 | 10411 | [(set_attr "type" "branch") |
cccf3bdc | 10412 | (set_attr "length" "8")]) |
04780ee7 | 10413 | |
cccf3bdc | 10414 | (define_insn "*call_value_indirect_nonlocal_aix64" |
d18dba68 | 10415 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10416 | (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) |
10417 | (match_operand 2 "" "g"))) | |
10418 | (use (reg:DI 2)) | |
10419 | (use (reg:DI 11)) | |
10420 | (set (reg:DI 2) | |
10421 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10422 | (clobber (match_scratch:SI 3 "=l"))] | |
10423 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" | |
10424 | "b%T1l\;ld 2,40(1)" | |
10425 | [(set_attr "type" "jmpreg") | |
10426 | (set_attr "length" "8")]) | |
10427 | ||
10428 | (define_insn "*call_value_nonlocal_aix64" | |
d18dba68 | 10429 | [(set (match_operand 0 "" "") |
cc4d5fec | 10430 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10431 | (match_operand 2 "" "g"))) |
10432 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10433 | (clobber (match_scratch:SI 4 "=l"))] | |
9ebbca7d GK |
10434 | "TARGET_64BIT |
10435 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10436 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
10437 | "bl %z1\;%." |
10438 | [(set_attr "type" "branch") | |
10439 | (set_attr "length" "8")]) | |
10440 | ||
10441 | ;; A function pointer under System V is just a normal pointer | |
10442 | ;; operands[0] is the function pointer | |
10443 | ;; operands[1] is the stack size to clean up | |
10444 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
10445 | ;; which indicates how to set cr1 | |
10446 | ||
a5c76ee6 ZW |
10447 | (define_insn "*call_indirect_nonlocal_sysv" |
10448 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl")) | |
10449 | (match_operand 1 "" "g,g")) | |
10450 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10451 | (clobber (match_scratch:SI 3 "=l,l"))] | |
cccf3bdc DE |
10452 | "DEFAULT_ABI == ABI_AIX_NODESC |
10453 | || DEFAULT_ABI == ABI_V4 | |
f607bc57 | 10454 | || DEFAULT_ABI == ABI_DARWIN" |
911f679c | 10455 | { |
cccf3bdc | 10456 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10457 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f | 10458 | |
cccf3bdc | 10459 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
a5c76ee6 | 10460 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10461 | |
a5c76ee6 ZW |
10462 | return "b%T0l"; |
10463 | } | |
10464 | [(set_attr "type" "jmpreg,jmpreg") | |
10465 | (set_attr "length" "4,8")]) | |
cccf3bdc | 10466 | |
a5c76ee6 ZW |
10467 | (define_insn "*call_nonlocal_sysv" |
10468 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10469 | (match_operand 1 "" "g,g")) | |
10470 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10471 | (clobber (match_scratch:SI 3 "=l,l"))] | |
10472 | "(DEFAULT_ABI == ABI_AIX_NODESC | |
10473 | || DEFAULT_ABI == ABI_V4 | |
10474 | || DEFAULT_ABI == ABI_DARWIN) | |
10475 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10476 | { | |
10477 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10478 | output_asm_insn ("crxor 6,6,6", operands); | |
10479 | ||
10480 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10481 | output_asm_insn ("creqv 6,6,6", operands); | |
10482 | ||
10483 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0"; | |
10484 | } | |
10485 | [(set_attr "type" "branch,branch") | |
10486 | (set_attr "length" "4,8")]) | |
10487 | ||
10488 | (define_insn "*call_value_indirect_nonlocal_sysv" | |
d18dba68 | 10489 | [(set (match_operand 0 "" "") |
a5c76ee6 ZW |
10490 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl")) |
10491 | (match_operand 2 "" "g,g"))) | |
10492 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10493 | (clobber (match_scratch:SI 4 "=l,l"))] | |
cccf3bdc DE |
10494 | "DEFAULT_ABI == ABI_AIX_NODESC |
10495 | || DEFAULT_ABI == ABI_V4 | |
f607bc57 | 10496 | || DEFAULT_ABI == ABI_DARWIN" |
b6c9286a | 10497 | { |
6a4cee5f | 10498 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10499 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f MM |
10500 | |
10501 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
a5c76ee6 | 10502 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10503 | |
a5c76ee6 ZW |
10504 | return "b%T1l"; |
10505 | } | |
10506 | [(set_attr "type" "jmpreg,jmpreg") | |
10507 | (set_attr "length" "4,8")]) | |
10508 | ||
10509 | (define_insn "*call_value_nonlocal_sysv" | |
10510 | [(set (match_operand 0 "" "") | |
10511 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10512 | (match_operand 2 "" "g,g"))) | |
10513 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10514 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10515 | "(DEFAULT_ABI == ABI_AIX_NODESC | |
10516 | || DEFAULT_ABI == ABI_V4 | |
10517 | || DEFAULT_ABI == ABI_DARWIN) | |
10518 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10519 | { | |
10520 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10521 | output_asm_insn ("crxor 6,6,6", operands); | |
10522 | ||
10523 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10524 | output_asm_insn ("creqv 6,6,6", operands); | |
10525 | ||
10526 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1"; | |
10527 | } | |
10528 | [(set_attr "type" "branch,branch") | |
10529 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
10530 | |
10531 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
10532 | (define_expand "untyped_call" |
10533 | [(parallel [(call (match_operand 0 "" "") | |
10534 | (const_int 0)) | |
10535 | (match_operand 1 "" "") | |
10536 | (match_operand 2 "" "")])] | |
10537 | "" | |
10538 | " | |
10539 | { | |
10540 | int i; | |
10541 | ||
7d70b8b2 | 10542 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
10543 | |
10544 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10545 | { | |
10546 | rtx set = XVECEXP (operands[2], 0, i); | |
10547 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10548 | } | |
10549 | ||
10550 | /* The optimizer does not know that the call sets the function value | |
10551 | registers we stored in the result block. We avoid problems by | |
10552 | claiming that all hard registers are used and clobbered at this | |
10553 | point. */ | |
10554 | emit_insn (gen_blockage ()); | |
10555 | ||
10556 | DONE; | |
10557 | }") | |
10558 | ||
10559 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
10560 | ;; all of memory. This blocks insns from being moved across this point. | |
10561 | ||
10562 | (define_insn "blockage" | |
10563 | [(unspec_volatile [(const_int 0)] 0)] | |
10564 | "" | |
10565 | "") | |
1fd4e8c1 RK |
10566 | \f |
10567 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 10568 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
10569 | ;; |
10570 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
10571 | ;; insns, and branches. We store the operands of compares until we see | |
10572 | ;; how it is used. | |
10573 | (define_expand "cmpsi" | |
10574 | [(set (cc0) | |
cd2b37d9 | 10575 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10576 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
10577 | "" | |
10578 | " | |
10579 | { | |
10580 | /* Take care of the possibility that operands[1] might be negative but | |
10581 | this might be a logical operation. That insn doesn't exist. */ | |
10582 | if (GET_CODE (operands[1]) == CONST_INT | |
10583 | && INTVAL (operands[1]) < 0) | |
10584 | operands[1] = force_reg (SImode, operands[1]); | |
10585 | ||
10586 | rs6000_compare_op0 = operands[0]; | |
10587 | rs6000_compare_op1 = operands[1]; | |
10588 | rs6000_compare_fp_p = 0; | |
10589 | DONE; | |
10590 | }") | |
10591 | ||
266eb58a DE |
10592 | (define_expand "cmpdi" |
10593 | [(set (cc0) | |
10594 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
10595 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
10596 | "TARGET_POWERPC64" | |
10597 | " | |
10598 | { | |
10599 | /* Take care of the possibility that operands[1] might be negative but | |
10600 | this might be a logical operation. That insn doesn't exist. */ | |
10601 | if (GET_CODE (operands[1]) == CONST_INT | |
10602 | && INTVAL (operands[1]) < 0) | |
10603 | operands[1] = force_reg (DImode, operands[1]); | |
10604 | ||
10605 | rs6000_compare_op0 = operands[0]; | |
10606 | rs6000_compare_op1 = operands[1]; | |
10607 | rs6000_compare_fp_p = 0; | |
10608 | DONE; | |
10609 | }") | |
10610 | ||
1fd4e8c1 | 10611 | (define_expand "cmpsf" |
cd2b37d9 RK |
10612 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
10613 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 10614 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10615 | " |
10616 | { | |
10617 | rs6000_compare_op0 = operands[0]; | |
10618 | rs6000_compare_op1 = operands[1]; | |
10619 | rs6000_compare_fp_p = 1; | |
10620 | DONE; | |
10621 | }") | |
10622 | ||
10623 | (define_expand "cmpdf" | |
cd2b37d9 RK |
10624 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
10625 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 10626 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10627 | " |
10628 | { | |
10629 | rs6000_compare_op0 = operands[0]; | |
10630 | rs6000_compare_op1 = operands[1]; | |
10631 | rs6000_compare_fp_p = 1; | |
10632 | DONE; | |
10633 | }") | |
10634 | ||
d6f99ca4 | 10635 | (define_expand "cmptf" |
e7a4130e DE |
10636 | [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "") |
10637 | (match_operand:TF 1 "gpc_reg_operand" "")))] | |
d6f99ca4 DE |
10638 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" |
10639 | " | |
10640 | { | |
10641 | rs6000_compare_op0 = operands[0]; | |
10642 | rs6000_compare_op1 = operands[1]; | |
10643 | rs6000_compare_fp_p = 1; | |
10644 | DONE; | |
10645 | }") | |
10646 | ||
1fd4e8c1 | 10647 | (define_expand "beq" |
39a10a29 | 10648 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10649 | "" |
39a10a29 | 10650 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10651 | |
10652 | (define_expand "bne" | |
39a10a29 | 10653 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10654 | "" |
39a10a29 | 10655 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 10656 | |
39a10a29 GK |
10657 | (define_expand "bge" |
10658 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10659 | "" |
39a10a29 | 10660 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
10661 | |
10662 | (define_expand "bgt" | |
39a10a29 | 10663 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10664 | "" |
39a10a29 | 10665 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
10666 | |
10667 | (define_expand "ble" | |
39a10a29 | 10668 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10669 | "" |
39a10a29 | 10670 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 10671 | |
39a10a29 GK |
10672 | (define_expand "blt" |
10673 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10674 | "" |
39a10a29 | 10675 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 10676 | |
39a10a29 GK |
10677 | (define_expand "bgeu" |
10678 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10679 | "" |
39a10a29 | 10680 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 10681 | |
39a10a29 GK |
10682 | (define_expand "bgtu" |
10683 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10684 | "" |
39a10a29 | 10685 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 10686 | |
39a10a29 GK |
10687 | (define_expand "bleu" |
10688 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10689 | "" |
39a10a29 | 10690 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 10691 | |
39a10a29 GK |
10692 | (define_expand "bltu" |
10693 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10694 | "" |
39a10a29 | 10695 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 10696 | |
1c882ea4 | 10697 | (define_expand "bunordered" |
39a10a29 | 10698 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10699 | "" |
39a10a29 | 10700 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
10701 | |
10702 | (define_expand "bordered" | |
39a10a29 | 10703 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10704 | "" |
39a10a29 | 10705 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
10706 | |
10707 | (define_expand "buneq" | |
39a10a29 | 10708 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10709 | "" |
39a10a29 | 10710 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
10711 | |
10712 | (define_expand "bunge" | |
39a10a29 | 10713 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10714 | "" |
39a10a29 | 10715 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
10716 | |
10717 | (define_expand "bungt" | |
39a10a29 | 10718 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10719 | "" |
39a10a29 | 10720 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
10721 | |
10722 | (define_expand "bunle" | |
39a10a29 | 10723 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10724 | "" |
39a10a29 | 10725 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
10726 | |
10727 | (define_expand "bunlt" | |
39a10a29 | 10728 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10729 | "" |
39a10a29 | 10730 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
10731 | |
10732 | (define_expand "bltgt" | |
39a10a29 | 10733 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10734 | "" |
39a10a29 | 10735 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 10736 | |
1fd4e8c1 RK |
10737 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
10738 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
10739 | ;; with an scc insns. However, due to the order that combine see the | |
10740 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
10741 | ;; the cases we don't want to handle. | |
10742 | (define_expand "seq" | |
39a10a29 | 10743 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10744 | "" |
39a10a29 | 10745 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10746 | |
10747 | (define_expand "sne" | |
39a10a29 | 10748 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10749 | "" |
10750 | " | |
39a10a29 GK |
10751 | { |
10752 | if (! rs6000_compare_fp_p) | |
1fd4e8c1 RK |
10753 | FAIL; |
10754 | ||
39a10a29 GK |
10755 | rs6000_emit_sCOND (NE, operands[0]); |
10756 | DONE; | |
1fd4e8c1 RK |
10757 | }") |
10758 | ||
10759 | ;; A > 0 is best done using the portable sequence, so fail in that case. | |
10760 | (define_expand "sgt" | |
39a10a29 | 10761 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10762 | "" |
10763 | " | |
5638268e DE |
10764 | { |
10765 | if (! rs6000_compare_fp_p | |
10766 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
10767 | FAIL; |
10768 | ||
39a10a29 GK |
10769 | rs6000_emit_sCOND (GT, operands[0]); |
10770 | DONE; | |
1fd4e8c1 RK |
10771 | }") |
10772 | ||
10773 | ;; A < 0 is best done in the portable way for A an integer. | |
10774 | (define_expand "slt" | |
39a10a29 | 10775 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10776 | "" |
10777 | " | |
5638268e DE |
10778 | { |
10779 | if (! rs6000_compare_fp_p | |
10780 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
10781 | FAIL; |
10782 | ||
39a10a29 GK |
10783 | rs6000_emit_sCOND (LT, operands[0]); |
10784 | DONE; | |
1fd4e8c1 RK |
10785 | }") |
10786 | ||
5638268e | 10787 | ;; A >= 0 is best done the portable way for A an integer. |
1fd4e8c1 | 10788 | (define_expand "sge" |
39a10a29 | 10789 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10790 | "" |
5638268e DE |
10791 | " |
10792 | { | |
10793 | if (! rs6000_compare_fp_p | |
10794 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
10795 | FAIL; | |
10796 | ||
10797 | rs6000_emit_sCOND (GE, operands[0]); | |
10798 | DONE; | |
10799 | }") | |
1fd4e8c1 RK |
10800 | |
10801 | ;; A <= 0 is best done the portable way for A an integer. | |
10802 | (define_expand "sle" | |
39a10a29 | 10803 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10804 | "" |
10805 | " | |
5638268e DE |
10806 | { |
10807 | if (! rs6000_compare_fp_p | |
10808 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
10809 | FAIL; |
10810 | ||
39a10a29 GK |
10811 | rs6000_emit_sCOND (LE, operands[0]); |
10812 | DONE; | |
1fd4e8c1 RK |
10813 | }") |
10814 | ||
10815 | (define_expand "sgtu" | |
39a10a29 | 10816 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10817 | "" |
39a10a29 | 10818 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10819 | |
10820 | (define_expand "sltu" | |
39a10a29 | 10821 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10822 | "" |
39a10a29 | 10823 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10824 | |
10825 | (define_expand "sgeu" | |
39a10a29 | 10826 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10827 | "" |
39a10a29 | 10828 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10829 | |
10830 | (define_expand "sleu" | |
39a10a29 | 10831 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10832 | "" |
39a10a29 | 10833 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
10834 | \f |
10835 | ;; Here are the actual compare insns. | |
acad7ed3 | 10836 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 10837 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 10838 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
10839 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
10840 | "" | |
7f340546 | 10841 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
1fd4e8c1 RK |
10842 | [(set_attr "type" "compare")]) |
10843 | ||
acad7ed3 | 10844 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
10845 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
10846 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
10847 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
10848 | "TARGET_POWERPC64" | |
10849 | "cmpd%I2 %0,%1,%2" | |
10850 | [(set_attr "type" "compare")]) | |
10851 | ||
f357808b RK |
10852 | ;; If we are comparing a register for equality with a large constant, |
10853 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
10854 | ;; register for the result of the XOR. | |
10855 | ||
10856 | (define_split | |
10857 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 10858 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 10859 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 10860 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
10861 | "find_single_use (operands[0], insn, 0) |
10862 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
10863 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
10864 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
10865 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
10866 | " | |
10867 | { | |
10868 | /* Get the constant we are comparing against, C, and see what it looks like | |
10869 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
10870 | with C to get the sign-extended value. */ | |
10871 | ||
5f59ecb7 | 10872 | HOST_WIDE_INT c = INTVAL (operands[2]); |
a65c591c | 10873 | HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; |
5f59ecb7 | 10874 | HOST_WIDE_INT xorv = c ^ sextc; |
f357808b | 10875 | |
89e9f3a8 MM |
10876 | operands[4] = GEN_INT (xorv); |
10877 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
10878 | }") |
10879 | ||
acad7ed3 | 10880 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 10881 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 10882 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 10883 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 10884 | "" |
e2c953b6 | 10885 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
1fd4e8c1 RK |
10886 | [(set_attr "type" "compare")]) |
10887 | ||
acad7ed3 | 10888 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
10889 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
10890 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 10891 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 10892 | "" |
e2c953b6 | 10893 | "cmpld%I2 %0,%1,%b2" |
266eb58a DE |
10894 | [(set_attr "type" "compare")]) |
10895 | ||
1fd4e8c1 RK |
10896 | ;; The following two insns don't exist as single insns, but if we provide |
10897 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
10898 | ;; of the required delay between a compare and branch. We generate code for | |
10899 | ;; them by splitting. | |
10900 | ||
10901 | (define_insn "" | |
10902 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 10903 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10904 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 10905 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10906 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
10907 | "" | |
baf97f86 RK |
10908 | "#" |
10909 | [(set_attr "length" "8")]) | |
7e69e155 | 10910 | |
1fd4e8c1 RK |
10911 | (define_insn "" |
10912 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 10913 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10914 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 10915 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10916 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
10917 | "" | |
baf97f86 RK |
10918 | "#" |
10919 | [(set_attr "length" "8")]) | |
7e69e155 | 10920 | |
1fd4e8c1 RK |
10921 | (define_split |
10922 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 10923 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10924 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 10925 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10926 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10927 | "" | |
10928 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
10929 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10930 | ||
10931 | (define_split | |
10932 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 10933 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10934 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 10935 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10936 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10937 | "" | |
10938 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
10939 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10940 | ||
acad7ed3 | 10941 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 10942 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10943 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
10944 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 10945 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10946 | "fcmpu %0,%1,%2" |
10947 | [(set_attr "type" "fpcompare")]) | |
10948 | ||
acad7ed3 | 10949 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 10950 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10951 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
10952 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 10953 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10954 | "fcmpu %0,%1,%2" |
10955 | [(set_attr "type" "fpcompare")]) | |
d6f99ca4 DE |
10956 | |
10957 | ;; Only need to compare second words if first words equal | |
10958 | (define_insn "*cmptf_internal1" | |
10959 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
10960 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
10961 | (match_operand:TF 2 "gpc_reg_operand" "f")))] | |
10962 | "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" | |
2e7d5318 | 10963 | "fcmpu %0,%1,%2\;bne %0,$+4\;fcmpu %0,%L1,%L2" |
d6f99ca4 DE |
10964 | [(set_attr "type" "fpcompare") |
10965 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
10966 | \f |
10967 | ;; Now we have the scc insns. We can do some combinations because of the | |
10968 | ;; way the machine works. | |
10969 | ;; | |
10970 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
10971 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
10972 | ;; cases the insns below which don't use an intermediate CR field will | |
10973 | ;; be used instead. | |
1fd4e8c1 | 10974 | (define_insn "" |
cd2b37d9 | 10975 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10976 | (match_operator:SI 1 "scc_comparison_operator" |
10977 | [(match_operand 2 "cc_reg_operand" "y") | |
10978 | (const_int 0)]))] | |
10979 | "" | |
ca7f5001 | 10980 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" |
309323c2 DE |
10981 | [(set_attr "type" "cr_logical") |
10982 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
10983 | |
10984 | (define_insn "" | |
9ebbca7d GK |
10985 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
10986 | (match_operator:DI 1 "scc_comparison_operator" | |
10987 | [(match_operand 2 "cc_reg_operand" "y") | |
10988 | (const_int 0)]))] | |
10989 | "TARGET_POWERPC64" | |
10990 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" | |
309323c2 DE |
10991 | [(set_attr "type" "cr_logical") |
10992 | (set_attr "length" "12")]) | |
9ebbca7d GK |
10993 | |
10994 | (define_insn "" | |
10995 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 10996 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 10997 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
10998 | (const_int 0)]) |
10999 | (const_int 0))) | |
9ebbca7d | 11000 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11001 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
0ad91047 | 11002 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11003 | "@ |
11004 | %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1 | |
11005 | #" | |
b19003d8 | 11006 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11007 | (set_attr "length" "12,16")]) |
11008 | ||
11009 | (define_split | |
11010 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11011 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
11012 | [(match_operand 2 "cc_reg_operand" "") | |
11013 | (const_int 0)]) | |
11014 | (const_int 0))) | |
11015 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
11016 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
11017 | "! TARGET_POWERPC64 && reload_completed" | |
11018 | [(set (match_dup 3) | |
11019 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
11020 | (set (match_dup 0) | |
11021 | (compare:CC (match_dup 3) | |
11022 | (const_int 0)))] | |
11023 | "") | |
1fd4e8c1 RK |
11024 | |
11025 | (define_insn "" | |
cd2b37d9 | 11026 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11027 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
11028 | [(match_operand 2 "cc_reg_operand" "y") | |
11029 | (const_int 0)]) | |
11030 | (match_operand:SI 3 "const_int_operand" "n")))] | |
11031 | "" | |
11032 | "* | |
11033 | { | |
11034 | int is_bit = ccr_bit (operands[1], 1); | |
11035 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11036 | int count; | |
11037 | ||
11038 | if (is_bit >= put_bit) | |
11039 | count = is_bit - put_bit; | |
11040 | else | |
11041 | count = 32 - (put_bit - is_bit); | |
11042 | ||
89e9f3a8 MM |
11043 | operands[4] = GEN_INT (count); |
11044 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 11045 | |
ca7f5001 | 11046 | return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 | 11047 | }" |
309323c2 DE |
11048 | [(set_attr "type" "cr_logical") |
11049 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
11050 | |
11051 | (define_insn "" | |
9ebbca7d | 11052 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11053 | (compare:CC |
11054 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 11055 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 11056 | (const_int 0)]) |
9ebbca7d | 11057 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 11058 | (const_int 0))) |
9ebbca7d | 11059 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11060 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
11061 | (match_dup 3)))] | |
9ebbca7d | 11062 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
11063 | "* |
11064 | { | |
11065 | int is_bit = ccr_bit (operands[1], 1); | |
11066 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11067 | int count; | |
11068 | ||
9ebbca7d GK |
11069 | /* Force split for non-cc0 compare. */ |
11070 | if (which_alternative == 1) | |
11071 | return \"#\"; | |
11072 | ||
1fd4e8c1 RK |
11073 | if (is_bit >= put_bit) |
11074 | count = is_bit - put_bit; | |
11075 | else | |
11076 | count = 32 - (put_bit - is_bit); | |
11077 | ||
89e9f3a8 MM |
11078 | operands[5] = GEN_INT (count); |
11079 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 11080 | |
ca7f5001 | 11081 | return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 11082 | }" |
b19003d8 | 11083 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11084 | (set_attr "length" "12,16")]) |
11085 | ||
11086 | (define_split | |
11087 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11088 | (compare:CC | |
11089 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
11090 | [(match_operand 2 "cc_reg_operand" "") | |
11091 | (const_int 0)]) | |
11092 | (match_operand:SI 3 "const_int_operand" "")) | |
11093 | (const_int 0))) | |
11094 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
11095 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11096 | (match_dup 3)))] | |
11097 | "! TARGET_POWERPC64 && reload_completed" | |
11098 | [(set (match_dup 4) | |
11099 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11100 | (match_dup 3))) | |
11101 | (set (match_dup 0) | |
11102 | (compare:CC (match_dup 4) | |
11103 | (const_int 0)))] | |
11104 | "") | |
1fd4e8c1 | 11105 | |
c5defebb RK |
11106 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
11107 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
11108 | ||
11109 | (define_peephole | |
cd2b37d9 | 11110 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
11111 | (match_operator:SI 1 "scc_comparison_operator" |
11112 | [(match_operand 2 "cc_reg_operand" "y") | |
11113 | (const_int 0)])) | |
cd2b37d9 | 11114 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
11115 | (match_operator:SI 4 "scc_comparison_operator" |
11116 | [(match_operand 5 "cc_reg_operand" "y") | |
11117 | (const_int 0)]))] | |
309323c2 DE |
11118 | "REGNO (operands[2]) != REGNO (operands[5])" |
11119 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" | |
11120 | [(set_attr "type" "cr_logical") | |
11121 | (set_attr "length" "20")]) | |
c5defebb | 11122 | |
9ebbca7d GK |
11123 | (define_peephole |
11124 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11125 | (match_operator:DI 1 "scc_comparison_operator" | |
11126 | [(match_operand 2 "cc_reg_operand" "y") | |
11127 | (const_int 0)])) | |
11128 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
11129 | (match_operator:DI 4 "scc_comparison_operator" | |
11130 | [(match_operand 5 "cc_reg_operand" "y") | |
11131 | (const_int 0)]))] | |
309323c2 DE |
11132 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" |
11133 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" | |
11134 | [(set_attr "type" "cr_logical") | |
11135 | (set_attr "length" "20")]) | |
9ebbca7d | 11136 | |
1fd4e8c1 RK |
11137 | ;; There are some scc insns that can be done directly, without a compare. |
11138 | ;; These are faster because they don't involve the communications between | |
11139 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
11140 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
11141 | ;; | |
11142 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
11143 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
11144 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
11145 | ;; cases where it is no more expensive than (neg (scc ..)). | |
11146 | ||
11147 | ;; Have reload force a constant into a register for the simple insns that | |
11148 | ;; otherwise won't accept constants. We do this because it is faster than | |
11149 | ;; the cmp/mfcr sequence we would otherwise generate. | |
11150 | ||
11151 | (define_insn "" | |
cd2b37d9 RK |
11152 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
11153 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 11154 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 11155 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
f9562f27 | 11156 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11157 | "@ |
ca7f5001 | 11158 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 11159 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
11160 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
11161 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
11162 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 11163 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 11164 | |
a260abc9 DE |
11165 | (define_insn "" |
11166 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
11167 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
11168 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
11169 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
11170 | "TARGET_POWERPC64" | |
11171 | "@ | |
11172 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11173 | subfic %3,%1,0\;adde %0,%3,%1 | |
11174 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11175 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11176 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
11177 | [(set_attr "length" "12,8,12,12,12")]) | |
11178 | ||
1fd4e8c1 | 11179 | (define_insn "" |
9ebbca7d | 11180 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11181 | (compare:CC |
9ebbca7d GK |
11182 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11183 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 11184 | (const_int 0))) |
9ebbca7d | 11185 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 11186 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11187 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
f9562f27 | 11188 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11189 | "@ |
ca7f5001 RK |
11190 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11191 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
11192 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
11193 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
11194 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11195 | # | |
11196 | # | |
11197 | # | |
11198 | # | |
11199 | #" | |
b19003d8 | 11200 | [(set_attr "type" "compare") |
9ebbca7d GK |
11201 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11202 | ||
11203 | (define_split | |
11204 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11205 | (compare:CC | |
11206 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11207 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11208 | (const_int 0))) | |
11209 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11210 | (eq:SI (match_dup 1) (match_dup 2))) | |
11211 | (clobber (match_scratch:SI 3 ""))] | |
11212 | "! TARGET_POWERPC64 && reload_completed" | |
11213 | [(parallel [(set (match_dup 0) | |
11214 | (eq:SI (match_dup 1) (match_dup 2))) | |
11215 | (clobber (match_dup 3))]) | |
11216 | (set (match_dup 4) | |
11217 | (compare:CC (match_dup 0) | |
11218 | (const_int 0)))] | |
11219 | "") | |
b19003d8 | 11220 | |
a260abc9 | 11221 | (define_insn "" |
9ebbca7d | 11222 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 11223 | (compare:CC |
9ebbca7d GK |
11224 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11225 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 11226 | (const_int 0))) |
9ebbca7d | 11227 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 11228 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11229 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
a260abc9 DE |
11230 | "TARGET_POWERPC64" |
11231 | "@ | |
11232 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11233 | subfic %3,%1,0\;adde. %0,%3,%1 | |
11234 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11235 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
11236 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
11237 | # | |
11238 | # | |
11239 | # | |
11240 | # | |
11241 | #" | |
a260abc9 | 11242 | [(set_attr "type" "compare") |
9ebbca7d GK |
11243 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11244 | ||
11245 | (define_split | |
11246 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11247 | (compare:CC | |
11248 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11249 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
11250 | (const_int 0))) | |
11251 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11252 | (eq:DI (match_dup 1) (match_dup 2))) | |
11253 | (clobber (match_scratch:DI 3 ""))] | |
11254 | "TARGET_POWERPC64 && reload_completed" | |
11255 | [(parallel [(set (match_dup 0) | |
11256 | (eq:DI (match_dup 1) (match_dup 2))) | |
11257 | (clobber (match_dup 3))]) | |
11258 | (set (match_dup 4) | |
11259 | (compare:CC (match_dup 0) | |
11260 | (const_int 0)))] | |
11261 | "") | |
a260abc9 | 11262 | |
b19003d8 RK |
11263 | ;; We have insns of the form shown by the first define_insn below. If |
11264 | ;; there is something inside the comparison operation, we must split it. | |
11265 | (define_split | |
11266 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
11267 | (plus:SI (match_operator 1 "comparison_operator" | |
11268 | [(match_operand:SI 2 "" "") | |
11269 | (match_operand:SI 3 | |
11270 | "reg_or_cint_operand" "")]) | |
11271 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
11272 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
11273 | "! gpc_reg_operand (operands[2], SImode)" | |
11274 | [(set (match_dup 5) (match_dup 2)) | |
11275 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
11276 | (match_dup 4)))]) | |
1fd4e8c1 RK |
11277 | |
11278 | (define_insn "" | |
5276df18 | 11279 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") |
cd2b37d9 | 11280 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11281 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
5276df18 | 11282 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] |
f9562f27 | 11283 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11284 | "@ |
5276df18 DE |
11285 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11286 | {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 | |
11287 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11288 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11289 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" | |
b19003d8 | 11290 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
11291 | |
11292 | (define_insn "" | |
9ebbca7d | 11293 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11294 | (compare:CC |
1fd4e8c1 | 11295 | (plus:SI |
9ebbca7d GK |
11296 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11297 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11298 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11299 | (const_int 0))) |
9ebbca7d | 11300 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 11301 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11302 | "@ |
ca7f5001 | 11303 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 11304 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
11305 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11306 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
11307 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11308 | # | |
11309 | # | |
11310 | # | |
11311 | # | |
11312 | #" | |
b19003d8 | 11313 | [(set_attr "type" "compare") |
9ebbca7d GK |
11314 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11315 | ||
11316 | (define_split | |
11317 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11318 | (compare:CC | |
11319 | (plus:SI | |
11320 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11321 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11322 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11323 | (const_int 0))) | |
11324 | (clobber (match_scratch:SI 4 ""))] | |
11325 | "! TARGET_POWERPC64 && reload_completed" | |
11326 | [(set (match_dup 4) | |
11327 | (plus:SI (eq:SI (match_dup 1) | |
11328 | (match_dup 2)) | |
11329 | (match_dup 3))) | |
11330 | (set (match_dup 0) | |
11331 | (compare:CC (match_dup 4) | |
11332 | (const_int 0)))] | |
11333 | "") | |
1fd4e8c1 RK |
11334 | |
11335 | (define_insn "" | |
0387639b | 11336 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11337 | (compare:CC |
1fd4e8c1 | 11338 | (plus:SI |
9ebbca7d GK |
11339 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11340 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11341 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11342 | (const_int 0))) |
0387639b DE |
11343 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") |
11344 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 11345 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11346 | "@ |
0387639b DE |
11347 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11348 | {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 | |
11349 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11350 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11351 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11352 | # |
11353 | # | |
11354 | # | |
11355 | # | |
11356 | #" | |
11357 | [(set_attr "type" "compare") | |
11358 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
11359 | ||
11360 | (define_split | |
0387639b | 11361 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11362 | (compare:CC |
11363 | (plus:SI | |
11364 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11365 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11366 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11367 | (const_int 0))) | |
11368 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
0387639b | 11369 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 11370 | "! TARGET_POWERPC64 && reload_completed" |
0387639b | 11371 | [(set (match_dup 0) |
9ebbca7d | 11372 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
0387639b | 11373 | (set (match_dup 4) |
9ebbca7d GK |
11374 | (compare:CC (match_dup 0) |
11375 | (const_int 0)))] | |
11376 | "") | |
11377 | ||
1fd4e8c1 | 11378 | (define_insn "" |
cd2b37d9 | 11379 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 11380 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11381 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
f9562f27 | 11382 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11383 | "@ |
ca7f5001 RK |
11384 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11385 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
11386 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11387 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11388 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11389 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 11390 | |
ea9be077 MM |
11391 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
11392 | ;; since it nabs/sr is just as fast. | |
463b558b | 11393 | (define_insn "*ne0" |
b4e95693 | 11394 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
11395 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
11396 | (const_int 31))) | |
11397 | (clobber (match_scratch:SI 2 "=&r"))] | |
9ebbca7d | 11398 | "! TARGET_POWER && ! TARGET_POWERPC64" |
ea9be077 MM |
11399 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
11400 | [(set_attr "length" "8")]) | |
11401 | ||
a260abc9 DE |
11402 | (define_insn "" |
11403 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11404 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11405 | (const_int 63))) | |
11406 | (clobber (match_scratch:DI 2 "=&r"))] | |
11407 | "TARGET_POWERPC64" | |
11408 | "addic %2,%1,-1\;subfe %0,%2,%1" | |
11409 | [(set_attr "length" "8")]) | |
11410 | ||
1fd4e8c1 RK |
11411 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
11412 | (define_insn "" | |
cd2b37d9 | 11413 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 11414 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 11415 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11416 | (const_int 31)) |
cd2b37d9 | 11417 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11418 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 11419 | "! TARGET_POWERPC64" |
ca7f5001 | 11420 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 11421 | [(set_attr "length" "8")]) |
1fd4e8c1 | 11422 | |
a260abc9 DE |
11423 | (define_insn "" |
11424 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11425 | (plus:DI (lshiftrt:DI | |
11426 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11427 | (const_int 63)) | |
11428 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11429 | (clobber (match_scratch:DI 3 "=&r"))] | |
11430 | "TARGET_POWERPC64" | |
11431 | "addic %3,%1,-1\;addze %0,%2" | |
11432 | [(set_attr "length" "8")]) | |
11433 | ||
1fd4e8c1 | 11434 | (define_insn "" |
9ebbca7d | 11435 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11436 | (compare:CC |
11437 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11438 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11439 | (const_int 31)) |
9ebbca7d | 11440 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11441 | (const_int 0))) |
889b90a1 GK |
11442 | (clobber (match_scratch:SI 3 "=&r,&r")) |
11443 | (clobber (match_scratch:SI 4 "=X,&r"))] | |
f9562f27 | 11444 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11445 | "@ |
11446 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
11447 | #" | |
b19003d8 | 11448 | [(set_attr "type" "compare") |
9ebbca7d GK |
11449 | (set_attr "length" "8,12")]) |
11450 | ||
11451 | (define_split | |
11452 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11453 | (compare:CC | |
11454 | (plus:SI (lshiftrt:SI | |
11455 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11456 | (const_int 31)) | |
11457 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11458 | (const_int 0))) | |
889b90a1 GK |
11459 | (clobber (match_scratch:SI 3 "")) |
11460 | (clobber (match_scratch:SI 4 ""))] | |
9ebbca7d | 11461 | "! TARGET_POWERPC64 && reload_completed" |
889b90a1 GK |
11462 | [(parallel [(set (match_dup 3) |
11463 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) | |
11464 | (const_int 31)) | |
11465 | (match_dup 2))) | |
11466 | (clobber (match_dup 4))]) | |
9ebbca7d GK |
11467 | (set (match_dup 0) |
11468 | (compare:CC (match_dup 3) | |
11469 | (const_int 0)))] | |
11470 | "") | |
1fd4e8c1 | 11471 | |
a260abc9 | 11472 | (define_insn "" |
9ebbca7d | 11473 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11474 | (compare:CC |
11475 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11476 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11477 | (const_int 63)) |
9ebbca7d | 11478 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11479 | (const_int 0))) |
9ebbca7d | 11480 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 11481 | "TARGET_POWERPC64" |
9ebbca7d GK |
11482 | "@ |
11483 | addic %3,%1,-1\;addze. %3,%2 | |
11484 | #" | |
a260abc9 | 11485 | [(set_attr "type" "compare") |
9ebbca7d GK |
11486 | (set_attr "length" "8,12")]) |
11487 | ||
11488 | (define_split | |
11489 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11490 | (compare:CC | |
11491 | (plus:DI (lshiftrt:DI | |
11492 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11493 | (const_int 63)) | |
11494 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11495 | (const_int 0))) | |
11496 | (clobber (match_scratch:DI 3 ""))] | |
11497 | "TARGET_POWERPC64 && reload_completed" | |
11498 | [(set (match_dup 3) | |
11499 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
11500 | (const_int 63)) | |
11501 | (match_dup 2))) | |
11502 | (set (match_dup 0) | |
11503 | (compare:CC (match_dup 3) | |
11504 | (const_int 0)))] | |
11505 | "") | |
a260abc9 | 11506 | |
1fd4e8c1 | 11507 | (define_insn "" |
9ebbca7d | 11508 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11509 | (compare:CC |
11510 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11511 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11512 | (const_int 31)) |
9ebbca7d | 11513 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11514 | (const_int 0))) |
9ebbca7d | 11515 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11516 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
11517 | (match_dup 2))) | |
9ebbca7d | 11518 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 11519 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11520 | "@ |
11521 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
11522 | #" | |
b19003d8 | 11523 | [(set_attr "type" "compare") |
9ebbca7d GK |
11524 | (set_attr "length" "8,12")]) |
11525 | ||
11526 | (define_split | |
11527 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11528 | (compare:CC | |
11529 | (plus:SI (lshiftrt:SI | |
11530 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11531 | (const_int 31)) | |
11532 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11533 | (const_int 0))) | |
11534 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11535 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11536 | (match_dup 2))) | |
11537 | (clobber (match_scratch:SI 3 ""))] | |
11538 | "! TARGET_POWERPC64 && reload_completed" | |
11539 | [(parallel [(set (match_dup 0) | |
11540 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11541 | (match_dup 2))) | |
11542 | (clobber (match_dup 3))]) | |
11543 | (set (match_dup 4) | |
11544 | (compare:CC (match_dup 0) | |
11545 | (const_int 0)))] | |
11546 | "") | |
1fd4e8c1 | 11547 | |
a260abc9 | 11548 | (define_insn "" |
9ebbca7d | 11549 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11550 | (compare:CC |
11551 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11552 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11553 | (const_int 63)) |
9ebbca7d | 11554 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11555 | (const_int 0))) |
9ebbca7d | 11556 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
11557 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
11558 | (match_dup 2))) | |
9ebbca7d | 11559 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 11560 | "TARGET_POWERPC64" |
9ebbca7d GK |
11561 | "@ |
11562 | addic %3,%1,-1\;addze. %0,%2 | |
11563 | #" | |
a260abc9 | 11564 | [(set_attr "type" "compare") |
9ebbca7d GK |
11565 | (set_attr "length" "8,12")]) |
11566 | ||
11567 | (define_split | |
11568 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11569 | (compare:CC | |
11570 | (plus:DI (lshiftrt:DI | |
11571 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11572 | (const_int 63)) | |
11573 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11574 | (const_int 0))) | |
11575 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11576 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11577 | (match_dup 2))) | |
11578 | (clobber (match_scratch:DI 3 ""))] | |
11579 | "TARGET_POWERPC64 && reload_completed" | |
11580 | [(parallel [(set (match_dup 0) | |
11581 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11582 | (match_dup 2))) | |
11583 | (clobber (match_dup 3))]) | |
11584 | (set (match_dup 4) | |
11585 | (compare:CC (match_dup 0) | |
11586 | (const_int 0)))] | |
11587 | "") | |
a260abc9 | 11588 | |
1fd4e8c1 | 11589 | (define_insn "" |
cd2b37d9 RK |
11590 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11591 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
11592 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
11593 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 11594 | "TARGET_POWER" |
1fd4e8c1 | 11595 | "@ |
ca7f5001 | 11596 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 11597 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11598 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11599 | |
11600 | (define_insn "" | |
9ebbca7d | 11601 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11602 | (compare:CC |
9ebbca7d GK |
11603 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11604 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 11605 | (const_int 0))) |
9ebbca7d | 11606 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11607 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11608 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 11609 | "TARGET_POWER" |
1fd4e8c1 | 11610 | "@ |
ca7f5001 | 11611 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
11612 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
11613 | # | |
11614 | #" | |
11615 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
11616 | (set_attr "length" "12,12,16,16")]) | |
11617 | ||
11618 | (define_split | |
11619 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11620 | (compare:CC | |
11621 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11622 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11623 | (const_int 0))) | |
11624 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11625 | (le:SI (match_dup 1) (match_dup 2))) | |
11626 | (clobber (match_scratch:SI 3 ""))] | |
11627 | "TARGET_POWER && reload_completed" | |
11628 | [(parallel [(set (match_dup 0) | |
11629 | (le:SI (match_dup 1) (match_dup 2))) | |
11630 | (clobber (match_dup 3))]) | |
11631 | (set (match_dup 4) | |
11632 | (compare:CC (match_dup 0) | |
11633 | (const_int 0)))] | |
11634 | "") | |
1fd4e8c1 RK |
11635 | |
11636 | (define_insn "" | |
097657c3 | 11637 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 11638 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 11639 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
097657c3 | 11640 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
ca7f5001 | 11641 | "TARGET_POWER" |
1fd4e8c1 | 11642 | "@ |
097657c3 AM |
11643 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11644 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" | |
b19003d8 | 11645 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11646 | |
11647 | (define_insn "" | |
9ebbca7d | 11648 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11649 | (compare:CC |
9ebbca7d GK |
11650 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11651 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
11652 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11653 | (const_int 0))) |
9ebbca7d | 11654 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 11655 | "TARGET_POWER" |
1fd4e8c1 | 11656 | "@ |
ca7f5001 | 11657 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
11658 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
11659 | # | |
11660 | #" | |
b19003d8 | 11661 | [(set_attr "type" "compare") |
9ebbca7d GK |
11662 | (set_attr "length" "12,12,16,16")]) |
11663 | ||
11664 | (define_split | |
11665 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11666 | (compare:CC | |
11667 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11668 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11669 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11670 | (const_int 0))) | |
11671 | (clobber (match_scratch:SI 4 ""))] | |
11672 | "TARGET_POWER && reload_completed" | |
11673 | [(set (match_dup 4) | |
11674 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 11675 | (match_dup 3))) |
9ebbca7d GK |
11676 | (set (match_dup 0) |
11677 | (compare:CC (match_dup 4) | |
11678 | (const_int 0)))] | |
11679 | "") | |
1fd4e8c1 RK |
11680 | |
11681 | (define_insn "" | |
097657c3 | 11682 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11683 | (compare:CC |
9ebbca7d GK |
11684 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11685 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
11686 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11687 | (const_int 0))) |
097657c3 AM |
11688 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
11689 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 11690 | "TARGET_POWER" |
1fd4e8c1 | 11691 | "@ |
097657c3 AM |
11692 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11693 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11694 | # |
11695 | #" | |
b19003d8 | 11696 | [(set_attr "type" "compare") |
9ebbca7d GK |
11697 | (set_attr "length" "12,12,16,16")]) |
11698 | ||
11699 | (define_split | |
097657c3 | 11700 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11701 | (compare:CC |
11702 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11703 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11704 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11705 | (const_int 0))) | |
11706 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 11707 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 11708 | "TARGET_POWER && reload_completed" |
097657c3 | 11709 | [(set (match_dup 0) |
9ebbca7d | 11710 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 11711 | (set (match_dup 4) |
9ebbca7d GK |
11712 | (compare:CC (match_dup 0) |
11713 | (const_int 0)))] | |
11714 | "") | |
1fd4e8c1 RK |
11715 | |
11716 | (define_insn "" | |
cd2b37d9 RK |
11717 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11718 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11719 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 11720 | "TARGET_POWER" |
1fd4e8c1 | 11721 | "@ |
ca7f5001 RK |
11722 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11723 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 11724 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11725 | |
11726 | (define_insn "" | |
cd2b37d9 RK |
11727 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11728 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11729 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 11730 | "! TARGET_POWERPC64" |
ca7f5001 | 11731 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 11732 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11733 | |
f9562f27 DE |
11734 | (define_insn "" |
11735 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11736 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
11737 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
11738 | "TARGET_POWERPC64" | |
11739 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" | |
11740 | [(set_attr "length" "12")]) | |
11741 | ||
11742 | (define_insn "" | |
9ebbca7d | 11743 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 11744 | (compare:CC |
9ebbca7d GK |
11745 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
11746 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 11747 | (const_int 0))) |
9ebbca7d | 11748 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
11749 | (leu:DI (match_dup 1) (match_dup 2)))] |
11750 | "TARGET_POWERPC64" | |
9ebbca7d GK |
11751 | "@ |
11752 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
11753 | #" | |
f9562f27 | 11754 | [(set_attr "type" "compare") |
9ebbca7d GK |
11755 | (set_attr "length" "12,16")]) |
11756 | ||
11757 | (define_split | |
11758 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11759 | (compare:CC | |
11760 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11761 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
11762 | (const_int 0))) | |
11763 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11764 | (leu:DI (match_dup 1) (match_dup 2)))] | |
11765 | "TARGET_POWERPC64 && reload_completed" | |
11766 | [(set (match_dup 0) | |
11767 | (leu:DI (match_dup 1) (match_dup 2))) | |
11768 | (set (match_dup 3) | |
11769 | (compare:CC (match_dup 0) | |
11770 | (const_int 0)))] | |
11771 | "") | |
f9562f27 | 11772 | |
1fd4e8c1 | 11773 | (define_insn "" |
9ebbca7d | 11774 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11775 | (compare:CC |
9ebbca7d GK |
11776 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11777 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11778 | (const_int 0))) |
9ebbca7d | 11779 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11780 | (leu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11781 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11782 | "@ |
11783 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
11784 | #" | |
b19003d8 | 11785 | [(set_attr "type" "compare") |
9ebbca7d GK |
11786 | (set_attr "length" "12,16")]) |
11787 | ||
11788 | (define_split | |
11789 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11790 | (compare:CC | |
11791 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11792 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11793 | (const_int 0))) | |
11794 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11795 | (leu:SI (match_dup 1) (match_dup 2)))] | |
11796 | "! TARGET_POWERPC64 && reload_completed" | |
11797 | [(set (match_dup 0) | |
11798 | (leu:SI (match_dup 1) (match_dup 2))) | |
11799 | (set (match_dup 3) | |
11800 | (compare:CC (match_dup 0) | |
11801 | (const_int 0)))] | |
11802 | "") | |
1fd4e8c1 | 11803 | |
f9562f27 | 11804 | (define_insn "" |
9ebbca7d | 11805 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 11806 | (compare:CC |
9ebbca7d GK |
11807 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
11808 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 11809 | (const_int 0))) |
9ebbca7d | 11810 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
11811 | (leu:DI (match_dup 1) (match_dup 2)))] |
11812 | "TARGET_POWERPC64" | |
9ebbca7d GK |
11813 | "@ |
11814 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
11815 | #" | |
f9562f27 | 11816 | [(set_attr "type" "compare") |
9ebbca7d | 11817 | (set_attr "length" "12,16")]) |
f9562f27 | 11818 | |
1fd4e8c1 | 11819 | (define_insn "" |
80103f96 | 11820 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 11821 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11822 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
80103f96 | 11823 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
f9562f27 | 11824 | "! TARGET_POWERPC64" |
80103f96 | 11825 | "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 11826 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
11827 | |
11828 | (define_insn "" | |
9ebbca7d | 11829 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11830 | (compare:CC |
9ebbca7d GK |
11831 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11832 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11833 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11834 | (const_int 0))) |
9ebbca7d | 11835 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11836 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11837 | "@ |
11838 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
11839 | #" | |
b19003d8 | 11840 | [(set_attr "type" "compare") |
9ebbca7d GK |
11841 | (set_attr "length" "8,12")]) |
11842 | ||
11843 | (define_split | |
11844 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11845 | (compare:CC | |
11846 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11847 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11848 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11849 | (const_int 0))) | |
11850 | (clobber (match_scratch:SI 4 ""))] | |
11851 | "! TARGET_POWERPC64 && reload_completed" | |
11852 | [(set (match_dup 4) | |
11853 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
11854 | (match_dup 3))) | |
11855 | (set (match_dup 0) | |
11856 | (compare:CC (match_dup 4) | |
11857 | (const_int 0)))] | |
11858 | "") | |
1fd4e8c1 RK |
11859 | |
11860 | (define_insn "" | |
097657c3 | 11861 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11862 | (compare:CC |
9ebbca7d GK |
11863 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11864 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11865 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11866 | (const_int 0))) |
097657c3 AM |
11867 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
11868 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 11869 | "! TARGET_POWERPC64" |
9ebbca7d | 11870 | "@ |
097657c3 | 11871 | {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 |
9ebbca7d | 11872 | #" |
b19003d8 | 11873 | [(set_attr "type" "compare") |
9ebbca7d GK |
11874 | (set_attr "length" "8,12")]) |
11875 | ||
11876 | (define_split | |
097657c3 | 11877 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11878 | (compare:CC |
11879 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11880 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11881 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11882 | (const_int 0))) | |
11883 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 11884 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 11885 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 11886 | [(set (match_dup 0) |
9ebbca7d | 11887 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 11888 | (set (match_dup 4) |
9ebbca7d GK |
11889 | (compare:CC (match_dup 0) |
11890 | (const_int 0)))] | |
11891 | "") | |
1fd4e8c1 RK |
11892 | |
11893 | (define_insn "" | |
cd2b37d9 RK |
11894 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11895 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11896 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 11897 | "! TARGET_POWERPC64" |
ca7f5001 | 11898 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 11899 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11900 | |
11901 | (define_insn "" | |
097657c3 | 11902 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
1fd4e8c1 | 11903 | (and:SI (neg:SI |
cd2b37d9 | 11904 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11905 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
097657c3 | 11906 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
f9562f27 | 11907 | "! TARGET_POWERPC64" |
097657c3 | 11908 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" |
b19003d8 | 11909 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11910 | |
11911 | (define_insn "" | |
9ebbca7d | 11912 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11913 | (compare:CC |
11914 | (and:SI (neg:SI | |
9ebbca7d GK |
11915 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11916 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11917 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11918 | (const_int 0))) |
9ebbca7d | 11919 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11920 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11921 | "@ |
11922 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
11923 | #" | |
11924 | [(set_attr "type" "compare") | |
11925 | (set_attr "length" "12,16")]) | |
11926 | ||
11927 | (define_split | |
11928 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11929 | (compare:CC | |
11930 | (and:SI (neg:SI | |
11931 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11932 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11933 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11934 | (const_int 0))) | |
11935 | (clobber (match_scratch:SI 4 ""))] | |
11936 | "! TARGET_POWERPC64 && reload_completed" | |
11937 | [(set (match_dup 4) | |
097657c3 AM |
11938 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) |
11939 | (match_dup 3))) | |
9ebbca7d GK |
11940 | (set (match_dup 0) |
11941 | (compare:CC (match_dup 4) | |
11942 | (const_int 0)))] | |
11943 | "") | |
1fd4e8c1 RK |
11944 | |
11945 | (define_insn "" | |
097657c3 | 11946 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11947 | (compare:CC |
11948 | (and:SI (neg:SI | |
9ebbca7d GK |
11949 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11950 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11951 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11952 | (const_int 0))) |
097657c3 AM |
11953 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
11954 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
f9562f27 | 11955 | "! TARGET_POWERPC64" |
9ebbca7d | 11956 | "@ |
097657c3 | 11957 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
9ebbca7d | 11958 | #" |
b19003d8 | 11959 | [(set_attr "type" "compare") |
9ebbca7d GK |
11960 | (set_attr "length" "12,16")]) |
11961 | ||
11962 | (define_split | |
097657c3 | 11963 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11964 | (compare:CC |
11965 | (and:SI (neg:SI | |
11966 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11967 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11968 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11969 | (const_int 0))) | |
11970 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 11971 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
9ebbca7d | 11972 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 AM |
11973 | [(set (match_dup 0) |
11974 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) | |
11975 | (match_dup 3))) | |
11976 | (set (match_dup 4) | |
9ebbca7d GK |
11977 | (compare:CC (match_dup 0) |
11978 | (const_int 0)))] | |
11979 | "") | |
1fd4e8c1 RK |
11980 | |
11981 | (define_insn "" | |
cd2b37d9 RK |
11982 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11983 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11984 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 11985 | "TARGET_POWER" |
7f340546 | 11986 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11987 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11988 | |
11989 | (define_insn "" | |
9ebbca7d | 11990 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11991 | (compare:CC |
9ebbca7d GK |
11992 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11993 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11994 | (const_int 0))) |
9ebbca7d | 11995 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11996 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 11997 | "TARGET_POWER" |
9ebbca7d GK |
11998 | "@ |
11999 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12000 | #" | |
29ae5b89 | 12001 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12002 | (set_attr "length" "12,16")]) |
12003 | ||
12004 | (define_split | |
12005 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12006 | (compare:CC | |
12007 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12008 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12009 | (const_int 0))) | |
12010 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12011 | (lt:SI (match_dup 1) (match_dup 2)))] | |
12012 | "TARGET_POWER && reload_completed" | |
12013 | [(set (match_dup 0) | |
12014 | (lt:SI (match_dup 1) (match_dup 2))) | |
12015 | (set (match_dup 3) | |
12016 | (compare:CC (match_dup 0) | |
12017 | (const_int 0)))] | |
12018 | "") | |
1fd4e8c1 RK |
12019 | |
12020 | (define_insn "" | |
097657c3 | 12021 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12022 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12023 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12024 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12025 | "TARGET_POWER" |
097657c3 | 12026 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 12027 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12028 | |
12029 | (define_insn "" | |
9ebbca7d | 12030 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12031 | (compare:CC |
9ebbca7d GK |
12032 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12033 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12034 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12035 | (const_int 0))) |
9ebbca7d | 12036 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12037 | "TARGET_POWER" |
9ebbca7d GK |
12038 | "@ |
12039 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12040 | #" | |
b19003d8 | 12041 | [(set_attr "type" "compare") |
9ebbca7d GK |
12042 | (set_attr "length" "12,16")]) |
12043 | ||
12044 | (define_split | |
12045 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12046 | (compare:CC | |
12047 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12048 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12049 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12050 | (const_int 0))) | |
12051 | (clobber (match_scratch:SI 4 ""))] | |
12052 | "TARGET_POWER && reload_completed" | |
12053 | [(set (match_dup 4) | |
12054 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12055 | (match_dup 3))) |
9ebbca7d GK |
12056 | (set (match_dup 0) |
12057 | (compare:CC (match_dup 4) | |
12058 | (const_int 0)))] | |
12059 | "") | |
1fd4e8c1 RK |
12060 | |
12061 | (define_insn "" | |
097657c3 | 12062 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12063 | (compare:CC |
9ebbca7d GK |
12064 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12065 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12066 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12067 | (const_int 0))) |
097657c3 AM |
12068 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12069 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12070 | "TARGET_POWER" |
9ebbca7d | 12071 | "@ |
097657c3 | 12072 | doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 12073 | #" |
b19003d8 | 12074 | [(set_attr "type" "compare") |
9ebbca7d GK |
12075 | (set_attr "length" "12,16")]) |
12076 | ||
12077 | (define_split | |
097657c3 | 12078 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12079 | (compare:CC |
12080 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12081 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12082 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12083 | (const_int 0))) | |
12084 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12085 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12086 | "TARGET_POWER && reload_completed" |
097657c3 | 12087 | [(set (match_dup 0) |
9ebbca7d | 12088 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12089 | (set (match_dup 4) |
9ebbca7d GK |
12090 | (compare:CC (match_dup 0) |
12091 | (const_int 0)))] | |
12092 | "") | |
1fd4e8c1 RK |
12093 | |
12094 | (define_insn "" | |
cd2b37d9 RK |
12095 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12096 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12097 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12098 | "TARGET_POWER" |
12099 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12100 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12101 | |
12102 | (define_insn "" | |
cd2b37d9 RK |
12103 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12104 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12105 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 12106 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12107 | "@ |
ca7f5001 RK |
12108 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
12109 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 12110 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12111 | |
12112 | (define_insn "" | |
9ebbca7d | 12113 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12114 | (compare:CC |
9ebbca7d GK |
12115 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12116 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12117 | (const_int 0))) |
9ebbca7d | 12118 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12119 | (ltu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 12120 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12121 | "@ |
ca7f5001 | 12122 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
12123 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
12124 | # | |
12125 | #" | |
b19003d8 | 12126 | [(set_attr "type" "compare") |
9ebbca7d GK |
12127 | (set_attr "length" "12,12,16,16")]) |
12128 | ||
12129 | (define_split | |
12130 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12131 | (compare:CC | |
12132 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12133 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12134 | (const_int 0))) | |
12135 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12136 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
12137 | "! TARGET_POWERPC64 && reload_completed" | |
12138 | [(set (match_dup 0) | |
12139 | (ltu:SI (match_dup 1) (match_dup 2))) | |
12140 | (set (match_dup 3) | |
12141 | (compare:CC (match_dup 0) | |
12142 | (const_int 0)))] | |
12143 | "") | |
1fd4e8c1 RK |
12144 | |
12145 | (define_insn "" | |
80103f96 | 12146 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
19378cf8 MM |
12147 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12148 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
80103f96 | 12149 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))] |
f9562f27 | 12150 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12151 | "@ |
80103f96 FS |
12152 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3 |
12153 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" | |
b19003d8 | 12154 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12155 | |
12156 | (define_insn "" | |
9ebbca7d | 12157 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12158 | (compare:CC |
9ebbca7d GK |
12159 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12160 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12161 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12162 | (const_int 0))) |
9ebbca7d | 12163 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12164 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12165 | "@ |
ca7f5001 | 12166 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
9ebbca7d GK |
12167 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
12168 | # | |
12169 | #" | |
b19003d8 | 12170 | [(set_attr "type" "compare") |
9ebbca7d GK |
12171 | (set_attr "length" "12,12,16,16")]) |
12172 | ||
12173 | (define_split | |
12174 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12175 | (compare:CC | |
12176 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12177 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12178 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12179 | (const_int 0))) | |
12180 | (clobber (match_scratch:SI 4 ""))] | |
12181 | "! TARGET_POWERPC64 && reload_completed" | |
12182 | [(set (match_dup 4) | |
12183 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12184 | (match_dup 3))) |
9ebbca7d GK |
12185 | (set (match_dup 0) |
12186 | (compare:CC (match_dup 4) | |
12187 | (const_int 0)))] | |
12188 | "") | |
1fd4e8c1 RK |
12189 | |
12190 | (define_insn "" | |
097657c3 | 12191 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12192 | (compare:CC |
9ebbca7d GK |
12193 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12194 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12195 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12196 | (const_int 0))) |
097657c3 AM |
12197 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12198 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 12199 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12200 | "@ |
097657c3 AM |
12201 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 |
12202 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 | |
9ebbca7d GK |
12203 | # |
12204 | #" | |
b19003d8 | 12205 | [(set_attr "type" "compare") |
9ebbca7d GK |
12206 | (set_attr "length" "12,12,16,16")]) |
12207 | ||
12208 | (define_split | |
097657c3 | 12209 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12210 | (compare:CC |
12211 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12212 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12213 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12214 | (const_int 0))) | |
12215 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12216 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12217 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 12218 | [(set (match_dup 0) |
9ebbca7d | 12219 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12220 | (set (match_dup 4) |
9ebbca7d GK |
12221 | (compare:CC (match_dup 0) |
12222 | (const_int 0)))] | |
12223 | "") | |
1fd4e8c1 RK |
12224 | |
12225 | (define_insn "" | |
cd2b37d9 RK |
12226 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12227 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12228 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
f9562f27 | 12229 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12230 | "@ |
ca7f5001 RK |
12231 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
12232 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12233 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12234 | |
12235 | (define_insn "" | |
cd2b37d9 RK |
12236 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12237 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
12238 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
12239 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
12240 | "TARGET_POWER" |
12241 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 12242 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12243 | |
9ebbca7d GK |
12244 | (define_insn "" |
12245 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 12246 | (compare:CC |
9ebbca7d GK |
12247 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12248 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12249 | (const_int 0))) |
9ebbca7d | 12250 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12251 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12252 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 12253 | "TARGET_POWER" |
9ebbca7d GK |
12254 | "@ |
12255 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
12256 | #" | |
12257 | [(set_attr "type" "compare") | |
12258 | (set_attr "length" "12,16")]) | |
12259 | ||
12260 | (define_split | |
12261 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12262 | (compare:CC | |
12263 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12264 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12265 | (const_int 0))) | |
12266 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12267 | (ge:SI (match_dup 1) (match_dup 2))) | |
12268 | (clobber (match_scratch:SI 3 ""))] | |
12269 | "TARGET_POWER && reload_completed" | |
12270 | [(parallel [(set (match_dup 0) | |
097657c3 AM |
12271 | (ge:SI (match_dup 1) (match_dup 2))) |
12272 | (clobber (match_dup 3))]) | |
9ebbca7d GK |
12273 | (set (match_dup 4) |
12274 | (compare:CC (match_dup 0) | |
12275 | (const_int 0)))] | |
12276 | "") | |
12277 | ||
1fd4e8c1 | 12278 | (define_insn "" |
097657c3 | 12279 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12280 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12281 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12282 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12283 | "TARGET_POWER" |
097657c3 | 12284 | "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" |
b19003d8 | 12285 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12286 | |
12287 | (define_insn "" | |
9ebbca7d | 12288 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12289 | (compare:CC |
9ebbca7d GK |
12290 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12291 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12292 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12293 | (const_int 0))) |
9ebbca7d | 12294 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12295 | "TARGET_POWER" |
9ebbca7d GK |
12296 | "@ |
12297 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
12298 | #" | |
b19003d8 | 12299 | [(set_attr "type" "compare") |
9ebbca7d GK |
12300 | (set_attr "length" "12,16")]) |
12301 | ||
12302 | (define_split | |
12303 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12304 | (compare:CC | |
12305 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12306 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12307 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12308 | (const_int 0))) | |
12309 | (clobber (match_scratch:SI 4 ""))] | |
12310 | "TARGET_POWER && reload_completed" | |
12311 | [(set (match_dup 4) | |
12312 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12313 | (match_dup 3))) |
9ebbca7d GK |
12314 | (set (match_dup 0) |
12315 | (compare:CC (match_dup 4) | |
12316 | (const_int 0)))] | |
12317 | "") | |
1fd4e8c1 RK |
12318 | |
12319 | (define_insn "" | |
097657c3 | 12320 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12321 | (compare:CC |
9ebbca7d GK |
12322 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12323 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12324 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12325 | (const_int 0))) |
097657c3 AM |
12326 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12327 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12328 | "TARGET_POWER" |
9ebbca7d | 12329 | "@ |
097657c3 | 12330 | doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
9ebbca7d | 12331 | #" |
b19003d8 | 12332 | [(set_attr "type" "compare") |
9ebbca7d GK |
12333 | (set_attr "length" "12,16")]) |
12334 | ||
12335 | (define_split | |
097657c3 | 12336 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12337 | (compare:CC |
12338 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12339 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12340 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12341 | (const_int 0))) | |
12342 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12343 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12344 | "TARGET_POWER && reload_completed" |
097657c3 | 12345 | [(set (match_dup 0) |
9ebbca7d | 12346 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12347 | (set (match_dup 4) |
9ebbca7d GK |
12348 | (compare:CC (match_dup 0) |
12349 | (const_int 0)))] | |
12350 | "") | |
1fd4e8c1 RK |
12351 | |
12352 | (define_insn "" | |
cd2b37d9 RK |
12353 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12354 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12355 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12356 | "TARGET_POWER" |
12357 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12358 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12359 | |
1fd4e8c1 | 12360 | (define_insn "" |
cd2b37d9 RK |
12361 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12362 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12363 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 12364 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12365 | "@ |
ca7f5001 RK |
12366 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
12367 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 12368 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12369 | |
f9562f27 DE |
12370 | (define_insn "" |
12371 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12372 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12373 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
12374 | "TARGET_POWERPC64" | |
12375 | "@ | |
12376 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
12377 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
12378 | [(set_attr "length" "12")]) | |
12379 | ||
1fd4e8c1 | 12380 | (define_insn "" |
9ebbca7d | 12381 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12382 | (compare:CC |
9ebbca7d GK |
12383 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12384 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12385 | (const_int 0))) |
9ebbca7d | 12386 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12387 | (geu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 12388 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12389 | "@ |
ca7f5001 | 12390 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
12391 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
12392 | # | |
12393 | #" | |
b19003d8 | 12394 | [(set_attr "type" "compare") |
9ebbca7d GK |
12395 | (set_attr "length" "12,12,16,16")]) |
12396 | ||
12397 | (define_split | |
12398 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12399 | (compare:CC | |
12400 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12401 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12402 | (const_int 0))) | |
12403 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12404 | (geu:SI (match_dup 1) (match_dup 2)))] | |
12405 | "! TARGET_POWERPC64 && reload_completed" | |
12406 | [(set (match_dup 0) | |
12407 | (geu:SI (match_dup 1) (match_dup 2))) | |
12408 | (set (match_dup 3) | |
12409 | (compare:CC (match_dup 0) | |
12410 | (const_int 0)))] | |
12411 | "") | |
1fd4e8c1 | 12412 | |
f9562f27 | 12413 | (define_insn "" |
9ebbca7d | 12414 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12415 | (compare:CC |
9ebbca7d GK |
12416 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12417 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 12418 | (const_int 0))) |
9ebbca7d | 12419 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 DE |
12420 | (geu:DI (match_dup 1) (match_dup 2)))] |
12421 | "TARGET_POWERPC64" | |
12422 | "@ | |
12423 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
12424 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
12425 | # | |
12426 | #" | |
f9562f27 | 12427 | [(set_attr "type" "compare") |
9ebbca7d GK |
12428 | (set_attr "length" "12,12,16,16")]) |
12429 | ||
12430 | (define_split | |
12431 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12432 | (compare:CC | |
12433 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12434 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
12435 | (const_int 0))) | |
12436 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12437 | (geu:DI (match_dup 1) (match_dup 2)))] | |
12438 | "TARGET_POWERPC64 && reload_completed" | |
12439 | [(set (match_dup 0) | |
12440 | (geu:DI (match_dup 1) (match_dup 2))) | |
12441 | (set (match_dup 3) | |
12442 | (compare:CC (match_dup 0) | |
12443 | (const_int 0)))] | |
12444 | "") | |
f9562f27 | 12445 | |
1fd4e8c1 | 12446 | (define_insn "" |
80103f96 | 12447 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 12448 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12449 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
80103f96 | 12450 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
f9562f27 | 12451 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12452 | "@ |
80103f96 FS |
12453 | {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 |
12454 | {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 12455 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12456 | |
12457 | (define_insn "" | |
9ebbca7d | 12458 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12459 | (compare:CC |
9ebbca7d GK |
12460 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12461 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12462 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12463 | (const_int 0))) |
9ebbca7d | 12464 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12465 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12466 | "@ |
ca7f5001 | 12467 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12468 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
12469 | # | |
12470 | #" | |
b19003d8 | 12471 | [(set_attr "type" "compare") |
9ebbca7d GK |
12472 | (set_attr "length" "8,8,12,12")]) |
12473 | ||
12474 | (define_split | |
12475 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12476 | (compare:CC | |
12477 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12478 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12479 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12480 | (const_int 0))) | |
12481 | (clobber (match_scratch:SI 4 ""))] | |
12482 | "! TARGET_POWERPC64 && reload_completed" | |
12483 | [(set (match_dup 4) | |
12484 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
12485 | (match_dup 3))) | |
12486 | (set (match_dup 0) | |
12487 | (compare:CC (match_dup 4) | |
12488 | (const_int 0)))] | |
12489 | "") | |
1fd4e8c1 RK |
12490 | |
12491 | (define_insn "" | |
097657c3 | 12492 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12493 | (compare:CC |
9ebbca7d GK |
12494 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12495 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12496 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12497 | (const_int 0))) |
097657c3 AM |
12498 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12499 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 12500 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12501 | "@ |
097657c3 AM |
12502 | {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 |
12503 | {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12504 | # |
12505 | #" | |
b19003d8 | 12506 | [(set_attr "type" "compare") |
9ebbca7d GK |
12507 | (set_attr "length" "8,8,12,12")]) |
12508 | ||
12509 | (define_split | |
097657c3 | 12510 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12511 | (compare:CC |
12512 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12513 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12514 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12515 | (const_int 0))) | |
12516 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12517 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12518 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 12519 | [(set (match_dup 0) |
9ebbca7d | 12520 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12521 | (set (match_dup 4) |
9ebbca7d GK |
12522 | (compare:CC (match_dup 0) |
12523 | (const_int 0)))] | |
12524 | "") | |
1fd4e8c1 RK |
12525 | |
12526 | (define_insn "" | |
cd2b37d9 RK |
12527 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12528 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12529 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
f9562f27 | 12530 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12531 | "@ |
ca7f5001 | 12532 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 12533 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 12534 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12535 | |
12536 | (define_insn "" | |
097657c3 | 12537 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
1fd4e8c1 | 12538 | (and:SI (neg:SI |
cd2b37d9 | 12539 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12540 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
097657c3 | 12541 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
f9562f27 | 12542 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12543 | "@ |
097657c3 AM |
12544 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 |
12545 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" | |
b19003d8 | 12546 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12547 | |
12548 | (define_insn "" | |
9ebbca7d | 12549 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12550 | (compare:CC |
12551 | (and:SI (neg:SI | |
9ebbca7d GK |
12552 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12553 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12554 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12555 | (const_int 0))) |
9ebbca7d | 12556 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12557 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12558 | "@ |
ca7f5001 | 12559 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
12560 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
12561 | # | |
12562 | #" | |
b19003d8 | 12563 | [(set_attr "type" "compare") |
9ebbca7d GK |
12564 | (set_attr "length" "12,12,16,16")]) |
12565 | ||
12566 | (define_split | |
12567 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12568 | (compare:CC | |
12569 | (and:SI (neg:SI | |
12570 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12571 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12572 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12573 | (const_int 0))) | |
12574 | (clobber (match_scratch:SI 4 ""))] | |
12575 | "! TARGET_POWERPC64 && reload_completed" | |
12576 | [(set (match_dup 4) | |
097657c3 AM |
12577 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) |
12578 | (match_dup 3))) | |
9ebbca7d GK |
12579 | (set (match_dup 0) |
12580 | (compare:CC (match_dup 4) | |
12581 | (const_int 0)))] | |
12582 | "") | |
1fd4e8c1 RK |
12583 | |
12584 | (define_insn "" | |
097657c3 | 12585 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12586 | (compare:CC |
12587 | (and:SI (neg:SI | |
9ebbca7d GK |
12588 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12589 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12590 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12591 | (const_int 0))) |
097657c3 AM |
12592 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12593 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
f9562f27 | 12594 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12595 | "@ |
097657c3 AM |
12596 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
12597 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 | |
9ebbca7d GK |
12598 | # |
12599 | #" | |
b19003d8 | 12600 | [(set_attr "type" "compare") |
9ebbca7d GK |
12601 | (set_attr "length" "12,12,16,16")]) |
12602 | ||
12603 | (define_split | |
097657c3 | 12604 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12605 | (compare:CC |
12606 | (and:SI (neg:SI | |
12607 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12608 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12609 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12610 | (const_int 0))) | |
12611 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12612 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
9ebbca7d | 12613 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 12614 | [(set (match_dup 0) |
9ebbca7d | 12615 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
097657c3 | 12616 | (set (match_dup 4) |
9ebbca7d GK |
12617 | (compare:CC (match_dup 0) |
12618 | (const_int 0)))] | |
12619 | "") | |
1fd4e8c1 RK |
12620 | |
12621 | (define_insn "" | |
cd2b37d9 RK |
12622 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12623 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12624 | (const_int 0)))] |
f9562f27 | 12625 | "! TARGET_POWERPC64" |
ca7f5001 | 12626 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12627 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12628 | |
f9562f27 DE |
12629 | (define_insn "" |
12630 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12631 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12632 | (const_int 0)))] | |
12633 | "TARGET_POWERPC64" | |
12634 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" | |
12635 | [(set_attr "length" "12")]) | |
12636 | ||
1fd4e8c1 | 12637 | (define_insn "" |
9ebbca7d | 12638 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12639 | (compare:CC |
9ebbca7d | 12640 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
12641 | (const_int 0)) |
12642 | (const_int 0))) | |
9ebbca7d | 12643 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12644 | (gt:SI (match_dup 1) (const_int 0)))] |
f9562f27 | 12645 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12646 | "@ |
12647 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
12648 | #" | |
29ae5b89 | 12649 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12650 | (set_attr "length" "12,16")]) |
12651 | ||
12652 | (define_split | |
12653 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
12654 | (compare:CC | |
12655 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12656 | (const_int 0)) | |
12657 | (const_int 0))) | |
12658 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12659 | (gt:SI (match_dup 1) (const_int 0)))] | |
12660 | "! TARGET_POWERPC64 && reload_completed" | |
12661 | [(set (match_dup 0) | |
12662 | (gt:SI (match_dup 1) (const_int 0))) | |
12663 | (set (match_dup 2) | |
12664 | (compare:CC (match_dup 0) | |
12665 | (const_int 0)))] | |
12666 | "") | |
1fd4e8c1 | 12667 | |
f9562f27 | 12668 | (define_insn "" |
9ebbca7d | 12669 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 12670 | (compare:CC |
9ebbca7d | 12671 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
12672 | (const_int 0)) |
12673 | (const_int 0))) | |
9ebbca7d | 12674 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
12675 | (gt:DI (match_dup 1) (const_int 0)))] |
12676 | "TARGET_POWERPC64" | |
9ebbca7d GK |
12677 | "@ |
12678 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
12679 | #" | |
f9562f27 | 12680 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12681 | (set_attr "length" "12,16")]) |
12682 | ||
12683 | (define_split | |
12684 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
12685 | (compare:CC | |
12686 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12687 | (const_int 0)) | |
12688 | (const_int 0))) | |
12689 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12690 | (gt:DI (match_dup 1) (const_int 0)))] | |
12691 | "TARGET_POWERPC64 && reload_completed" | |
12692 | [(set (match_dup 0) | |
12693 | (gt:DI (match_dup 1) (const_int 0))) | |
12694 | (set (match_dup 2) | |
12695 | (compare:CC (match_dup 0) | |
12696 | (const_int 0)))] | |
12697 | "") | |
f9562f27 | 12698 | |
1fd4e8c1 | 12699 | (define_insn "" |
cd2b37d9 RK |
12700 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12701 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12702 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
12703 | "TARGET_POWER" |
12704 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 12705 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12706 | |
12707 | (define_insn "" | |
9ebbca7d | 12708 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12709 | (compare:CC |
9ebbca7d GK |
12710 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12711 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 12712 | (const_int 0))) |
9ebbca7d | 12713 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12714 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12715 | "TARGET_POWER" |
9ebbca7d GK |
12716 | "@ |
12717 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12718 | #" | |
29ae5b89 | 12719 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12720 | (set_attr "length" "12,16")]) |
12721 | ||
12722 | (define_split | |
12723 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12724 | (compare:CC | |
12725 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12726 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12727 | (const_int 0))) | |
12728 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12729 | (gt:SI (match_dup 1) (match_dup 2)))] | |
12730 | "TARGET_POWER && reload_completed" | |
12731 | [(set (match_dup 0) | |
12732 | (gt:SI (match_dup 1) (match_dup 2))) | |
12733 | (set (match_dup 3) | |
12734 | (compare:CC (match_dup 0) | |
12735 | (const_int 0)))] | |
12736 | "") | |
1fd4e8c1 RK |
12737 | |
12738 | (define_insn "" | |
80103f96 | 12739 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12740 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12741 | (const_int 0)) |
80103f96 | 12742 | (match_operand:SI 2 "gpc_reg_operand" "r")))] |
f9562f27 | 12743 | "! TARGET_POWERPC64" |
80103f96 | 12744 | "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" |
b19003d8 | 12745 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12746 | |
f9562f27 | 12747 | (define_insn "" |
097657c3 | 12748 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
f9562f27 DE |
12749 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
12750 | (const_int 0)) | |
097657c3 | 12751 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
f9562f27 | 12752 | "TARGET_POWERPC64" |
097657c3 | 12753 | "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" |
f9562f27 DE |
12754 | [(set_attr "length" "12")]) |
12755 | ||
1fd4e8c1 | 12756 | (define_insn "" |
9ebbca7d | 12757 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12758 | (compare:CC |
9ebbca7d | 12759 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12760 | (const_int 0)) |
9ebbca7d | 12761 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 12762 | (const_int 0))) |
9ebbca7d | 12763 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 12764 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12765 | "@ |
12766 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
12767 | #" | |
b19003d8 | 12768 | [(set_attr "type" "compare") |
9ebbca7d GK |
12769 | (set_attr "length" "12,16")]) |
12770 | ||
12771 | (define_split | |
12772 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12773 | (compare:CC | |
12774 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12775 | (const_int 0)) | |
12776 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
12777 | (const_int 0))) | |
12778 | (clobber (match_scratch:SI 3 ""))] | |
12779 | "! TARGET_POWERPC64 && reload_completed" | |
12780 | [(set (match_dup 3) | |
12781 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
12782 | (match_dup 2))) | |
12783 | (set (match_dup 0) | |
12784 | (compare:CC (match_dup 3) | |
12785 | (const_int 0)))] | |
12786 | "") | |
1fd4e8c1 | 12787 | |
f9562f27 | 12788 | (define_insn "" |
9ebbca7d | 12789 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 12790 | (compare:CC |
9ebbca7d | 12791 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 12792 | (const_int 0)) |
9ebbca7d | 12793 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 12794 | (const_int 0))) |
9ebbca7d | 12795 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 12796 | "TARGET_POWERPC64" |
9ebbca7d GK |
12797 | "@ |
12798 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
12799 | #" | |
f9562f27 | 12800 | [(set_attr "type" "compare") |
9ebbca7d GK |
12801 | (set_attr "length" "12,16")]) |
12802 | ||
12803 | (define_split | |
12804 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12805 | (compare:CC | |
12806 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12807 | (const_int 0)) | |
12808 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12809 | (const_int 0))) | |
12810 | (clobber (match_scratch:DI 3 ""))] | |
12811 | "TARGET_POWERPC64 && reload_completed" | |
12812 | [(set (match_dup 3) | |
12813 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
097657c3 | 12814 | (match_dup 2))) |
9ebbca7d GK |
12815 | (set (match_dup 0) |
12816 | (compare:CC (match_dup 3) | |
12817 | (const_int 0)))] | |
12818 | "") | |
f9562f27 | 12819 | |
1fd4e8c1 | 12820 | (define_insn "" |
097657c3 | 12821 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
9ebbca7d GK |
12822 | (compare:CC |
12823 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12824 | (const_int 0)) | |
12825 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
12826 | (const_int 0))) | |
097657c3 AM |
12827 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12828 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
9ebbca7d GK |
12829 | "! TARGET_POWERPC64" |
12830 | "@ | |
097657c3 | 12831 | {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 |
9ebbca7d GK |
12832 | #" |
12833 | [(set_attr "type" "compare") | |
12834 | (set_attr "length" "12,16")]) | |
12835 | ||
12836 | (define_split | |
097657c3 | 12837 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
1fd4e8c1 | 12838 | (compare:CC |
9ebbca7d | 12839 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 12840 | (const_int 0)) |
9ebbca7d | 12841 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 12842 | (const_int 0))) |
9ebbca7d | 12843 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
097657c3 | 12844 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] |
9ebbca7d | 12845 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 12846 | [(set (match_dup 0) |
9ebbca7d | 12847 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 12848 | (set (match_dup 3) |
9ebbca7d GK |
12849 | (compare:CC (match_dup 0) |
12850 | (const_int 0)))] | |
12851 | "") | |
1fd4e8c1 | 12852 | |
f9562f27 | 12853 | (define_insn "" |
097657c3 | 12854 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12855 | (compare:CC |
9ebbca7d | 12856 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 12857 | (const_int 0)) |
9ebbca7d | 12858 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 12859 | (const_int 0))) |
097657c3 AM |
12860 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
12861 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
f9562f27 | 12862 | "TARGET_POWERPC64" |
9ebbca7d | 12863 | "@ |
097657c3 | 12864 | addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 |
9ebbca7d | 12865 | #" |
f9562f27 | 12866 | [(set_attr "type" "compare") |
9ebbca7d GK |
12867 | (set_attr "length" "12,16")]) |
12868 | ||
12869 | (define_split | |
097657c3 | 12870 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12871 | (compare:CC |
12872 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12873 | (const_int 0)) | |
12874 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12875 | (const_int 0))) | |
12876 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 12877 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] |
9ebbca7d | 12878 | "TARGET_POWERPC64 && reload_completed" |
097657c3 | 12879 | [(set (match_dup 0) |
9ebbca7d | 12880 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 12881 | (set (match_dup 3) |
9ebbca7d GK |
12882 | (compare:CC (match_dup 0) |
12883 | (const_int 0)))] | |
12884 | "") | |
f9562f27 | 12885 | |
1fd4e8c1 | 12886 | (define_insn "" |
097657c3 | 12887 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12888 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12889 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
097657c3 | 12890 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12891 | "TARGET_POWER" |
097657c3 | 12892 | "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 12893 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12894 | |
12895 | (define_insn "" | |
9ebbca7d | 12896 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12897 | (compare:CC |
9ebbca7d GK |
12898 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12899 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
12900 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12901 | (const_int 0))) |
9ebbca7d | 12902 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12903 | "TARGET_POWER" |
9ebbca7d GK |
12904 | "@ |
12905 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12906 | #" | |
b19003d8 | 12907 | [(set_attr "type" "compare") |
9ebbca7d GK |
12908 | (set_attr "length" "12,16")]) |
12909 | ||
12910 | (define_split | |
12911 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12912 | (compare:CC | |
12913 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12914 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12915 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12916 | (const_int 0))) | |
12917 | (clobber (match_scratch:SI 4 ""))] | |
12918 | "TARGET_POWER && reload_completed" | |
12919 | [(set (match_dup 4) | |
097657c3 | 12920 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d GK |
12921 | (set (match_dup 0) |
12922 | (compare:CC (match_dup 4) | |
12923 | (const_int 0)))] | |
12924 | "") | |
1fd4e8c1 RK |
12925 | |
12926 | (define_insn "" | |
097657c3 | 12927 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12928 | (compare:CC |
9ebbca7d GK |
12929 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12930 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
12931 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12932 | (const_int 0))) |
097657c3 AM |
12933 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12934 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12935 | "TARGET_POWER" |
9ebbca7d | 12936 | "@ |
097657c3 | 12937 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 12938 | #" |
b19003d8 | 12939 | [(set_attr "type" "compare") |
9ebbca7d GK |
12940 | (set_attr "length" "12,16")]) |
12941 | ||
12942 | (define_split | |
097657c3 | 12943 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12944 | (compare:CC |
12945 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12946 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12947 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12948 | (const_int 0))) | |
12949 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12950 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12951 | "TARGET_POWER && reload_completed" |
097657c3 | 12952 | [(set (match_dup 0) |
9ebbca7d | 12953 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12954 | (set (match_dup 4) |
9ebbca7d GK |
12955 | (compare:CC (match_dup 0) |
12956 | (const_int 0)))] | |
12957 | "") | |
1fd4e8c1 RK |
12958 | |
12959 | (define_insn "" | |
cd2b37d9 RK |
12960 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12961 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12962 | (const_int 0))))] |
f9562f27 | 12963 | "! TARGET_POWERPC64" |
ca7f5001 | 12964 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 12965 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12966 | |
f9562f27 DE |
12967 | (define_insn "" |
12968 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12969 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12970 | (const_int 0))))] | |
12971 | "TARGET_POWERPC64" | |
8377288b | 12972 | "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63" |
f9562f27 DE |
12973 | [(set_attr "length" "12")]) |
12974 | ||
1fd4e8c1 | 12975 | (define_insn "" |
cd2b37d9 RK |
12976 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12977 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12978 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
12979 | "TARGET_POWER" |
12980 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12981 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12982 | |
12983 | (define_insn "" | |
cd2b37d9 RK |
12984 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12985 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12986 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 12987 | "! TARGET_POWERPC64" |
ca7f5001 | 12988 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 12989 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12990 | |
f9562f27 DE |
12991 | (define_insn "" |
12992 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12993 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12994 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
12995 | "TARGET_POWERPC64" | |
12996 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0" | |
12997 | [(set_attr "length" "12")]) | |
12998 | ||
1fd4e8c1 | 12999 | (define_insn "" |
9ebbca7d | 13000 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13001 | (compare:CC |
9ebbca7d GK |
13002 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13003 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 13004 | (const_int 0))) |
9ebbca7d | 13005 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13006 | (gtu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 13007 | "! TARGET_POWERPC64" |
9ebbca7d GK |
13008 | "@ |
13009 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
13010 | #" | |
b19003d8 | 13011 | [(set_attr "type" "compare") |
9ebbca7d GK |
13012 | (set_attr "length" "12,16")]) |
13013 | ||
13014 | (define_split | |
13015 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13016 | (compare:CC | |
13017 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13018 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13019 | (const_int 0))) | |
13020 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13021 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
13022 | "! TARGET_POWERPC64 && reload_completed" | |
13023 | [(set (match_dup 0) | |
13024 | (gtu:SI (match_dup 1) (match_dup 2))) | |
13025 | (set (match_dup 3) | |
13026 | (compare:CC (match_dup 0) | |
13027 | (const_int 0)))] | |
13028 | "") | |
1fd4e8c1 | 13029 | |
f9562f27 | 13030 | (define_insn "" |
9ebbca7d | 13031 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13032 | (compare:CC |
9ebbca7d GK |
13033 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13034 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 13035 | (const_int 0))) |
9ebbca7d | 13036 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
13037 | (gtu:DI (match_dup 1) (match_dup 2)))] |
13038 | "TARGET_POWERPC64" | |
9ebbca7d GK |
13039 | "@ |
13040 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
13041 | #" | |
f9562f27 | 13042 | [(set_attr "type" "compare") |
9ebbca7d GK |
13043 | (set_attr "length" "12,16")]) |
13044 | ||
13045 | (define_split | |
13046 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13047 | (compare:CC | |
13048 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13049 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13050 | (const_int 0))) | |
13051 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13052 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
13053 | "TARGET_POWERPC64 && reload_completed" | |
13054 | [(set (match_dup 0) | |
13055 | (gtu:DI (match_dup 1) (match_dup 2))) | |
13056 | (set (match_dup 3) | |
13057 | (compare:CC (match_dup 0) | |
13058 | (const_int 0)))] | |
13059 | "") | |
f9562f27 | 13060 | |
1fd4e8c1 | 13061 | (define_insn "" |
80103f96 | 13062 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
19378cf8 MM |
13063 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13064 | (match_operand:SI 2 "reg_or_short_operand" "I,rI")) | |
80103f96 | 13065 | (match_operand:SI 3 "reg_or_short_operand" "r,rI")))] |
f9562f27 | 13066 | "! TARGET_POWERPC64" |
00751805 | 13067 | "@ |
80103f96 FS |
13068 | {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3 |
13069 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3" | |
19378cf8 | 13070 | [(set_attr "length" "8,12")]) |
1fd4e8c1 | 13071 | |
f9562f27 | 13072 | (define_insn "" |
097657c3 | 13073 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
f9562f27 DE |
13074 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13075 | (match_operand:DI 2 "reg_or_short_operand" "I,rI")) | |
097657c3 | 13076 | (match_operand:DI 3 "reg_or_short_operand" "r,rI")))] |
f9562f27 DE |
13077 | "TARGET_POWERPC64" |
13078 | "@ | |
097657c3 AM |
13079 | addic %0,%1,%k2\;addze %0,%3 |
13080 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3" | |
f9562f27 DE |
13081 | [(set_attr "length" "8,12")]) |
13082 | ||
1fd4e8c1 | 13083 | (define_insn "" |
9ebbca7d | 13084 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13085 | (compare:CC |
9ebbca7d GK |
13086 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13087 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13088 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13089 | (const_int 0))) |
9ebbca7d | 13090 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 13091 | "! TARGET_POWERPC64" |
00751805 | 13092 | "@ |
19378cf8 | 13093 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
13094 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
13095 | # | |
13096 | #" | |
b19003d8 | 13097 | [(set_attr "type" "compare") |
9ebbca7d GK |
13098 | (set_attr "length" "8,12,12,16")]) |
13099 | ||
13100 | (define_split | |
13101 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13102 | (compare:CC | |
13103 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13104 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13105 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13106 | (const_int 0))) | |
13107 | (clobber (match_scratch:SI 4 ""))] | |
13108 | "! TARGET_POWERPC64 && reload_completed" | |
13109 | [(set (match_dup 4) | |
13110 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 13111 | (match_dup 3))) |
9ebbca7d GK |
13112 | (set (match_dup 0) |
13113 | (compare:CC (match_dup 4) | |
13114 | (const_int 0)))] | |
13115 | "") | |
1fd4e8c1 | 13116 | |
f9562f27 | 13117 | (define_insn "" |
9ebbca7d | 13118 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13119 | (compare:CC |
9ebbca7d GK |
13120 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13121 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13122 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13123 | (const_int 0))) |
9ebbca7d | 13124 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
13125 | "TARGET_POWERPC64" |
13126 | "@ | |
13127 | addic %4,%1,%k2\;addze. %4,%3 | |
9ebbca7d GK |
13128 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3 |
13129 | # | |
13130 | #" | |
f9562f27 | 13131 | [(set_attr "type" "compare") |
9ebbca7d GK |
13132 | (set_attr "length" "8,12,12,16")]) |
13133 | ||
13134 | (define_split | |
13135 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13136 | (compare:CC | |
13137 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13138 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13139 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13140 | (const_int 0))) | |
13141 | (clobber (match_scratch:DI 4 ""))] | |
13142 | "TARGET_POWERPC64 && reload_completed" | |
13143 | [(set (match_dup 4) | |
13144 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
13145 | (match_dup 3))) | |
13146 | (set (match_dup 0) | |
13147 | (compare:CC (match_dup 4) | |
13148 | (const_int 0)))] | |
13149 | "") | |
f9562f27 | 13150 | |
1fd4e8c1 | 13151 | (define_insn "" |
097657c3 | 13152 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13153 | (compare:CC |
9ebbca7d GK |
13154 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13155 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13156 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13157 | (const_int 0))) |
097657c3 AM |
13158 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13159 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 | 13160 | "! TARGET_POWERPC64" |
00751805 | 13161 | "@ |
097657c3 AM |
13162 | {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 |
13163 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3 | |
9ebbca7d GK |
13164 | # |
13165 | #" | |
b19003d8 | 13166 | [(set_attr "type" "compare") |
9ebbca7d GK |
13167 | (set_attr "length" "8,12,12,16")]) |
13168 | ||
13169 | (define_split | |
097657c3 | 13170 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13171 | (compare:CC |
13172 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13173 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13174 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13175 | (const_int 0))) | |
13176 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13177 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13178 | "! TARGET_POWERPC64 && reload_completed" |
097657c3 | 13179 | [(set (match_dup 0) |
9ebbca7d | 13180 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13181 | (set (match_dup 4) |
9ebbca7d GK |
13182 | (compare:CC (match_dup 0) |
13183 | (const_int 0)))] | |
13184 | "") | |
1fd4e8c1 | 13185 | |
f9562f27 | 13186 | (define_insn "" |
097657c3 | 13187 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13188 | (compare:CC |
9ebbca7d GK |
13189 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13190 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13191 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13192 | (const_int 0))) |
097657c3 AM |
13193 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13194 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
f9562f27 DE |
13195 | "TARGET_POWERPC64" |
13196 | "@ | |
097657c3 AM |
13197 | addic %0,%1,%k2\;addze. %0,%3 |
13198 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3 | |
9ebbca7d GK |
13199 | # |
13200 | #" | |
f9562f27 | 13201 | [(set_attr "type" "compare") |
9ebbca7d GK |
13202 | (set_attr "length" "8,12,12,16")]) |
13203 | ||
13204 | (define_split | |
097657c3 | 13205 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13206 | (compare:CC |
13207 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13208 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13209 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13210 | (const_int 0))) | |
13211 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13212 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13213 | "TARGET_POWERPC64 && reload_completed" |
097657c3 | 13214 | [(set (match_dup 0) |
9ebbca7d | 13215 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13216 | (set (match_dup 4) |
9ebbca7d GK |
13217 | (compare:CC (match_dup 0) |
13218 | (const_int 0)))] | |
13219 | "") | |
f9562f27 | 13220 | |
1fd4e8c1 | 13221 | (define_insn "" |
cd2b37d9 RK |
13222 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13223 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13224 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 13225 | "! TARGET_POWERPC64" |
ca7f5001 | 13226 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 13227 | [(set_attr "length" "8")]) |
f9562f27 DE |
13228 | |
13229 | (define_insn "" | |
13230 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13231 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13232 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
13233 | "TARGET_POWERPC64" | |
13234 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" | |
13235 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
13236 | \f |
13237 | ;; Define both directions of branch and return. If we need a reload | |
13238 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
13239 | ;; register CC value to there. | |
13240 | ||
13241 | (define_insn "" | |
13242 | [(set (pc) | |
13243 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13244 | [(match_operand 2 | |
13245 | "cc_reg_operand" "x,?y") | |
13246 | (const_int 0)]) | |
13247 | (label_ref (match_operand 0 "" "")) | |
13248 | (pc)))] | |
13249 | "" | |
b19003d8 RK |
13250 | "* |
13251 | { | |
12a4e8c5 | 13252 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
13253 | }" |
13254 | [(set_attr "type" "branch")]) | |
13255 | ||
1fd4e8c1 RK |
13256 | (define_insn "" |
13257 | [(set (pc) | |
13258 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13259 | [(match_operand 1 | |
13260 | "cc_reg_operand" "x,?y") | |
13261 | (const_int 0)]) | |
13262 | (return) | |
13263 | (pc)))] | |
13264 | "direct_return ()" | |
12a4e8c5 GK |
13265 | "* |
13266 | { | |
13267 | return output_cbranch (operands[0], NULL, 0, insn); | |
13268 | }" | |
b7ff3d82 | 13269 | [(set_attr "type" "branch") |
39a10a29 | 13270 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
13271 | |
13272 | (define_insn "" | |
13273 | [(set (pc) | |
13274 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13275 | [(match_operand 2 | |
13276 | "cc_reg_operand" "x,?y") | |
13277 | (const_int 0)]) | |
13278 | (pc) | |
13279 | (label_ref (match_operand 0 "" ""))))] | |
13280 | "" | |
b19003d8 RK |
13281 | "* |
13282 | { | |
12a4e8c5 | 13283 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
13284 | }" |
13285 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13286 | |
13287 | (define_insn "" | |
13288 | [(set (pc) | |
13289 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13290 | [(match_operand 1 | |
13291 | "cc_reg_operand" "x,?y") | |
13292 | (const_int 0)]) | |
13293 | (pc) | |
13294 | (return)))] | |
13295 | "direct_return ()" | |
12a4e8c5 GK |
13296 | "* |
13297 | { | |
13298 | return output_cbranch (operands[0], NULL, 1, insn); | |
13299 | }" | |
b7ff3d82 | 13300 | [(set_attr "type" "branch") |
39a10a29 GK |
13301 | (set_attr "length" "4")]) |
13302 | ||
13303 | ;; Logic on condition register values. | |
13304 | ||
13305 | ; This pattern matches things like | |
13306 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
13307 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
13308 | ; (const_int 1))) | |
13309 | ; which are generated by the branch logic. | |
13310 | ||
13311 | (define_insn "" | |
13312 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
13313 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" | |
13314 | [(match_operator:SI 2 | |
13315 | "branch_positive_comparison_operator" | |
13316 | [(match_operand 3 | |
13317 | "cc_reg_operand" "y") | |
13318 | (const_int 0)]) | |
13319 | (match_operator:SI 4 | |
13320 | "branch_positive_comparison_operator" | |
13321 | [(match_operand 5 | |
13322 | "cc_reg_operand" "y") | |
13323 | (const_int 0)])]) | |
13324 | (const_int 1)))] | |
13325 | "" | |
13326 | "cr%q1 %E0,%j2,%j4" | |
13327 | [(set_attr "type" "cr_logical")]) | |
13328 | ||
13329 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
13330 | ; Because ~1 has all but the low bit set. | |
13331 | (define_insn "" | |
13332 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
13333 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" | |
13334 | [(not:SI (match_operator:SI 2 | |
13335 | "branch_positive_comparison_operator" | |
13336 | [(match_operand 3 | |
13337 | "cc_reg_operand" "y") | |
13338 | (const_int 0)])) | |
13339 | (match_operator:SI 4 | |
13340 | "branch_positive_comparison_operator" | |
13341 | [(match_operand 5 | |
13342 | "cc_reg_operand" "y") | |
13343 | (const_int 0)])]) | |
13344 | (const_int -1)))] | |
13345 | "" | |
13346 | "cr%q1 %E0,%j2,%j4" | |
13347 | [(set_attr "type" "cr_logical")]) | |
13348 | ||
13349 | (define_insn "" | |
13350 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
6c873122 | 13351 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 13352 | "branch_positive_comparison_operator" |
6c873122 | 13353 | [(match_operand 2 |
39a10a29 GK |
13354 | "cc_reg_operand" "y") |
13355 | (const_int 0)]) | |
13356 | (const_int 0)))] | |
13357 | "" | |
251b3667 | 13358 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
39a10a29 GK |
13359 | [(set_attr "type" "cr_logical")]) |
13360 | ||
13361 | ;; If we are comparing the result of two comparisons, this can be done | |
13362 | ;; using creqv or crxor. | |
13363 | ||
13364 | (define_insn_and_split "" | |
13365 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
13366 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
13367 | [(match_operand 2 "cc_reg_operand" "y") | |
13368 | (const_int 0)]) | |
13369 | (match_operator 3 "branch_comparison_operator" | |
13370 | [(match_operand 4 "cc_reg_operand" "y") | |
13371 | (const_int 0)])))] | |
13372 | "" | |
13373 | "#" | |
13374 | "" | |
13375 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
13376 | (match_dup 5)))] | |
13377 | " | |
13378 | { | |
13379 | int positive_1, positive_2; | |
13380 | ||
13381 | positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode); | |
13382 | positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode); | |
13383 | ||
13384 | if (! positive_1) | |
2d4368e6 | 13385 | operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]), |
39a10a29 | 13386 | GET_CODE (operands[1])), |
2d4368e6 DE |
13387 | SImode, |
13388 | operands[2], const0_rtx); | |
39a10a29 | 13389 | else if (GET_MODE (operands[1]) != SImode) |
2d4368e6 DE |
13390 | operands[1] = gen_rtx (GET_CODE (operands[1]), |
13391 | SImode, | |
13392 | operands[2], const0_rtx); | |
39a10a29 GK |
13393 | |
13394 | if (! positive_2) | |
2d4368e6 | 13395 | operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]), |
39a10a29 | 13396 | GET_CODE (operands[3])), |
2d4368e6 DE |
13397 | SImode, |
13398 | operands[4], const0_rtx); | |
39a10a29 | 13399 | else if (GET_MODE (operands[3]) != SImode) |
2d4368e6 DE |
13400 | operands[3] = gen_rtx (GET_CODE (operands[3]), |
13401 | SImode, | |
13402 | operands[4], const0_rtx); | |
39a10a29 GK |
13403 | |
13404 | if (positive_1 == positive_2) | |
251b3667 DE |
13405 | { |
13406 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
13407 | operands[5] = constm1_rtx; | |
13408 | } | |
13409 | else | |
13410 | { | |
13411 | operands[5] = const1_rtx; | |
13412 | } | |
39a10a29 | 13413 | }") |
1fd4e8c1 RK |
13414 | |
13415 | ;; Unconditional branch and return. | |
13416 | ||
13417 | (define_insn "jump" | |
13418 | [(set (pc) | |
13419 | (label_ref (match_operand 0 "" "")))] | |
13420 | "" | |
b7ff3d82 DE |
13421 | "b %l0" |
13422 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13423 | |
13424 | (define_insn "return" | |
13425 | [(return)] | |
13426 | "direct_return ()" | |
324e52cc TG |
13427 | "{br|blr}" |
13428 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 13429 | |
0ad91047 DE |
13430 | (define_expand "indirect_jump" |
13431 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 13432 | "" |
0ad91047 DE |
13433 | " |
13434 | { | |
13435 | if (TARGET_32BIT) | |
13436 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
13437 | else | |
13438 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
13439 | DONE; | |
13440 | }") | |
13441 | ||
13442 | (define_insn "indirect_jumpsi" | |
b92b324d | 13443 | [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))] |
0ad91047 | 13444 | "TARGET_32BIT" |
b92b324d DE |
13445 | "@ |
13446 | bctr | |
13447 | {br|blr}" | |
324e52cc | 13448 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13449 | |
0ad91047 | 13450 | (define_insn "indirect_jumpdi" |
b92b324d | 13451 | [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))] |
0ad91047 | 13452 | "TARGET_64BIT" |
b92b324d DE |
13453 | "@ |
13454 | bctr | |
13455 | blr" | |
266eb58a DE |
13456 | [(set_attr "type" "jmpreg")]) |
13457 | ||
1fd4e8c1 RK |
13458 | ;; Table jump for switch statements: |
13459 | (define_expand "tablejump" | |
e6ca2c17 DE |
13460 | [(use (match_operand 0 "" "")) |
13461 | (use (label_ref (match_operand 1 "" "")))] | |
13462 | "" | |
13463 | " | |
13464 | { | |
13465 | if (TARGET_32BIT) | |
13466 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
13467 | else | |
13468 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
13469 | DONE; | |
13470 | }") | |
13471 | ||
13472 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
13473 | [(set (match_dup 3) |
13474 | (plus:SI (match_operand:SI 0 "" "") | |
13475 | (match_dup 2))) | |
13476 | (parallel [(set (pc) (match_dup 3)) | |
13477 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13478 | "TARGET_32BIT" |
1fd4e8c1 RK |
13479 | " |
13480 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 13481 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
13482 | operands[3] = gen_reg_rtx (SImode); |
13483 | }") | |
13484 | ||
e6ca2c17 | 13485 | (define_expand "tablejumpdi" |
9ebbca7d GK |
13486 | [(set (match_dup 4) |
13487 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) | |
13488 | (set (match_dup 3) | |
13489 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
13490 | (match_dup 2))) |
13491 | (parallel [(set (pc) (match_dup 3)) | |
13492 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13493 | "TARGET_64BIT" |
e6ca2c17 | 13494 | " |
9ebbca7d | 13495 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 13496 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 13497 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
13498 | }") |
13499 | ||
1fd4e8c1 RK |
13500 | (define_insn "" |
13501 | [(set (pc) | |
c859cda6 | 13502 | (match_operand:SI 0 "register_operand" "c,*l")) |
1fd4e8c1 | 13503 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13504 | "TARGET_32BIT" |
c859cda6 DJ |
13505 | "@ |
13506 | bctr | |
13507 | {br|blr}" | |
a6845123 | 13508 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13509 | |
266eb58a DE |
13510 | (define_insn "" |
13511 | [(set (pc) | |
c859cda6 | 13512 | (match_operand:DI 0 "register_operand" "c,*l")) |
266eb58a | 13513 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13514 | "TARGET_64BIT" |
c859cda6 DJ |
13515 | "@ |
13516 | bctr | |
13517 | blr" | |
266eb58a DE |
13518 | [(set_attr "type" "jmpreg")]) |
13519 | ||
1fd4e8c1 RK |
13520 | (define_insn "nop" |
13521 | [(const_int 0)] | |
13522 | "" | |
ca7f5001 | 13523 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 13524 | \f |
7e69e155 | 13525 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
13526 | ;; so loop.c knows what to generate. |
13527 | ||
5527bf14 RH |
13528 | (define_expand "doloop_end" |
13529 | [(use (match_operand 0 "" "")) ; loop pseudo | |
13530 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
13531 | (use (match_operand 2 "" "")) ; max iterations | |
13532 | (use (match_operand 3 "" "")) ; loop level | |
13533 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
13534 | "" |
13535 | " | |
13536 | { | |
5527bf14 RH |
13537 | /* Only use this on innermost loops. */ |
13538 | if (INTVAL (operands[3]) > 1) | |
13539 | FAIL; | |
0ad91047 | 13540 | if (TARGET_POWERPC64) |
5527bf14 RH |
13541 | { |
13542 | if (GET_MODE (operands[0]) != DImode) | |
13543 | FAIL; | |
13544 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
13545 | } | |
0ad91047 | 13546 | else |
5527bf14 RH |
13547 | { |
13548 | if (GET_MODE (operands[0]) != SImode) | |
13549 | FAIL; | |
13550 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
13551 | } | |
0ad91047 DE |
13552 | DONE; |
13553 | }") | |
13554 | ||
13555 | (define_expand "ctrsi" | |
3cb999d8 DE |
13556 | [(parallel [(set (pc) |
13557 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
13558 | (const_int 1)) | |
13559 | (label_ref (match_operand 1 "" "")) | |
13560 | (pc))) | |
b6c9286a MM |
13561 | (set (match_dup 0) |
13562 | (plus:SI (match_dup 0) | |
13563 | (const_int -1))) | |
5f81043f RK |
13564 | (clobber (match_scratch:CC 2 "")) |
13565 | (clobber (match_scratch:SI 3 ""))])] | |
0ad91047 DE |
13566 | "! TARGET_POWERPC64" |
13567 | "") | |
13568 | ||
13569 | (define_expand "ctrdi" | |
3cb999d8 DE |
13570 | [(parallel [(set (pc) |
13571 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
13572 | (const_int 1)) | |
13573 | (label_ref (match_operand 1 "" "")) | |
13574 | (pc))) | |
0ad91047 DE |
13575 | (set (match_dup 0) |
13576 | (plus:DI (match_dup 0) | |
13577 | (const_int -1))) | |
13578 | (clobber (match_scratch:CC 2 "")) | |
61c07d3c | 13579 | (clobber (match_scratch:DI 3 ""))])] |
0ad91047 | 13580 | "TARGET_POWERPC64" |
61c07d3c | 13581 | "") |
c225ba7b | 13582 | |
1fd4e8c1 RK |
13583 | ;; We need to be able to do this for any operand, including MEM, or we |
13584 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 13585 | ;; JUMP_INSNs. |
0ad91047 | 13586 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
13587 | ;; label MUST be operand 0. |
13588 | ||
0ad91047 | 13589 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 13590 | [(set (pc) |
5f81043f | 13591 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 13592 | (const_int 1)) |
a6845123 | 13593 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13594 | (pc))) |
5f81043f RK |
13595 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
13596 | (plus:SI (match_dup 1) | |
13597 | (const_int -1))) | |
1fd4e8c1 RK |
13598 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13599 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13600 | "! TARGET_POWERPC64" |
b19003d8 RK |
13601 | "* |
13602 | { | |
af87a13e | 13603 | if (which_alternative != 0) |
b19003d8 | 13604 | return \"#\"; |
856a6884 | 13605 | else if (get_attr_length (insn) == 4) |
a6845123 | 13606 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 13607 | else |
f607bc57 | 13608 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 13609 | }" |
baf97f86 RK |
13610 | [(set_attr "type" "branch") |
13611 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 13612 | |
0ad91047 | 13613 | (define_insn "*ctrsi_internal2" |
5f81043f RK |
13614 | [(set (pc) |
13615 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") | |
13616 | (const_int 1)) | |
13617 | (pc) | |
13618 | (label_ref (match_operand 0 "" "")))) | |
13619 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
13620 | (plus:SI (match_dup 1) | |
13621 | (const_int -1))) | |
13622 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
13623 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
13624 | "! TARGET_POWERPC64" |
13625 | "* | |
13626 | { | |
13627 | if (which_alternative != 0) | |
13628 | return \"#\"; | |
856a6884 | 13629 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13630 | return \"bdz %l0\"; |
13631 | else | |
f607bc57 | 13632 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
13633 | }" |
13634 | [(set_attr "type" "branch") | |
13635 | (set_attr "length" "*,12,16")]) | |
13636 | ||
13637 | (define_insn "*ctrdi_internal1" | |
13638 | [(set (pc) | |
61c07d3c | 13639 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
13640 | (const_int 1)) |
13641 | (label_ref (match_operand 0 "" "")) | |
13642 | (pc))) | |
61c07d3c | 13643 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
13644 | (plus:DI (match_dup 1) |
13645 | (const_int -1))) | |
61c07d3c DE |
13646 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13647 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
13648 | "TARGET_POWERPC64" |
13649 | "* | |
13650 | { | |
13651 | if (which_alternative != 0) | |
13652 | return \"#\"; | |
856a6884 | 13653 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13654 | return \"{bdn|bdnz} %l0\"; |
13655 | else | |
f607bc57 | 13656 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
13657 | }" |
13658 | [(set_attr "type" "branch") | |
61c07d3c | 13659 | (set_attr "length" "*,12,16")]) |
0ad91047 DE |
13660 | |
13661 | (define_insn "*ctrdi_internal2" | |
13662 | [(set (pc) | |
61c07d3c | 13663 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
13664 | (const_int 1)) |
13665 | (pc) | |
13666 | (label_ref (match_operand 0 "" "")))) | |
61c07d3c | 13667 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
13668 | (plus:DI (match_dup 1) |
13669 | (const_int -1))) | |
61c07d3c DE |
13670 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13671 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 | 13672 | "TARGET_POWERPC64" |
5f81043f RK |
13673 | "* |
13674 | { | |
13675 | if (which_alternative != 0) | |
13676 | return \"#\"; | |
856a6884 | 13677 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
13678 | return \"bdz %l0\"; |
13679 | else | |
f607bc57 | 13680 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
13681 | }" |
13682 | [(set_attr "type" "branch") | |
61c07d3c | 13683 | (set_attr "length" "*,12,16")]) |
5f81043f | 13684 | |
c225ba7b | 13685 | ;; Similar, but we can use GE since we have a REG_NONNEG. |
0ad91047 DE |
13686 | |
13687 | (define_insn "*ctrsi_internal3" | |
1fd4e8c1 | 13688 | [(set (pc) |
5f81043f | 13689 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 13690 | (const_int 0)) |
a6845123 | 13691 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13692 | (pc))) |
5f81043f RK |
13693 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
13694 | (plus:SI (match_dup 1) | |
13695 | (const_int -1))) | |
1fd4e8c1 RK |
13696 | (clobber (match_scratch:CC 3 "=X,&x,&X")) |
13697 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13698 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
b19003d8 RK |
13699 | "* |
13700 | { | |
af87a13e | 13701 | if (which_alternative != 0) |
b19003d8 | 13702 | return \"#\"; |
856a6884 | 13703 | else if (get_attr_length (insn) == 4) |
a6845123 | 13704 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 13705 | else |
f607bc57 | 13706 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 13707 | }" |
baf97f86 RK |
13708 | [(set_attr "type" "branch") |
13709 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 13710 | |
0ad91047 | 13711 | (define_insn "*ctrsi_internal4" |
1fd4e8c1 | 13712 | [(set (pc) |
5f81043f RK |
13713 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
13714 | (const_int 0)) | |
13715 | (pc) | |
13716 | (label_ref (match_operand 0 "" "")))) | |
13717 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
13718 | (plus:SI (match_dup 1) | |
13719 | (const_int -1))) | |
13720 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
13721 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13722 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
5f81043f RK |
13723 | "* |
13724 | { | |
13725 | if (which_alternative != 0) | |
13726 | return \"#\"; | |
856a6884 | 13727 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
13728 | return \"bdz %l0\"; |
13729 | else | |
f607bc57 | 13730 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
13731 | }" |
13732 | [(set_attr "type" "branch") | |
13733 | (set_attr "length" "*,12,16")]) | |
13734 | ||
0ad91047 DE |
13735 | (define_insn "*ctrdi_internal3" |
13736 | [(set (pc) | |
61c07d3c | 13737 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
13738 | (const_int 0)) |
13739 | (label_ref (match_operand 0 "" "")) | |
13740 | (pc))) | |
61c07d3c | 13741 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
13742 | (plus:DI (match_dup 1) |
13743 | (const_int -1))) | |
61c07d3c DE |
13744 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13745 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
13746 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
13747 | "* | |
13748 | { | |
13749 | if (which_alternative != 0) | |
13750 | return \"#\"; | |
856a6884 | 13751 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13752 | return \"{bdn|bdnz} %l0\"; |
13753 | else | |
f607bc57 | 13754 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
13755 | }" |
13756 | [(set_attr "type" "branch") | |
61c07d3c | 13757 | (set_attr "length" "*,12,16")]) |
0ad91047 DE |
13758 | |
13759 | (define_insn "*ctrdi_internal4" | |
13760 | [(set (pc) | |
61c07d3c | 13761 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
13762 | (const_int 0)) |
13763 | (pc) | |
13764 | (label_ref (match_operand 0 "" "")))) | |
61c07d3c | 13765 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
13766 | (plus:DI (match_dup 1) |
13767 | (const_int -1))) | |
61c07d3c DE |
13768 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13769 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
13770 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
13771 | "* | |
13772 | { | |
13773 | if (which_alternative != 0) | |
13774 | return \"#\"; | |
856a6884 | 13775 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13776 | return \"bdz %l0\"; |
13777 | else | |
f607bc57 | 13778 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
13779 | }" |
13780 | [(set_attr "type" "branch") | |
61c07d3c | 13781 | (set_attr "length" "*,12,16")]) |
0ad91047 DE |
13782 | |
13783 | ;; Similar but use EQ | |
13784 | ||
13785 | (define_insn "*ctrsi_internal5" | |
5f81043f RK |
13786 | [(set (pc) |
13787 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
1fd4e8c1 | 13788 | (const_int 1)) |
a6845123 | 13789 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13790 | (pc))) |
5f81043f RK |
13791 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
13792 | (plus:SI (match_dup 1) | |
13793 | (const_int -1))) | |
1fd4e8c1 RK |
13794 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13795 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13796 | "! TARGET_POWERPC64" |
b19003d8 RK |
13797 | "* |
13798 | { | |
af87a13e | 13799 | if (which_alternative != 0) |
b19003d8 | 13800 | return \"#\"; |
856a6884 | 13801 | else if (get_attr_length (insn) == 4) |
a6845123 | 13802 | return \"bdz %l0\"; |
b19003d8 | 13803 | else |
f607bc57 | 13804 | return \"{bdn|bdnz} $+8\;b %l0\"; |
b19003d8 | 13805 | }" |
baf97f86 RK |
13806 | [(set_attr "type" "branch") |
13807 | (set_attr "length" "*,12,16")]) | |
1fd4e8c1 | 13808 | |
0ad91047 | 13809 | (define_insn "*ctrsi_internal6" |
5f81043f RK |
13810 | [(set (pc) |
13811 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
13812 | (const_int 1)) | |
13813 | (pc) | |
13814 | (label_ref (match_operand 0 "" "")))) | |
13815 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
13816 | (plus:SI (match_dup 1) | |
13817 | (const_int -1))) | |
13818 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
13819 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
13820 | "! TARGET_POWERPC64" |
13821 | "* | |
13822 | { | |
13823 | if (which_alternative != 0) | |
13824 | return \"#\"; | |
856a6884 | 13825 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13826 | return \"{bdn|bdnz} %l0\"; |
13827 | else | |
f607bc57 | 13828 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
13829 | }" |
13830 | [(set_attr "type" "branch") | |
13831 | (set_attr "length" "*,12,16")]) | |
13832 | ||
13833 | (define_insn "*ctrdi_internal5" | |
13834 | [(set (pc) | |
61c07d3c | 13835 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
13836 | (const_int 1)) |
13837 | (label_ref (match_operand 0 "" "")) | |
13838 | (pc))) | |
61c07d3c | 13839 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
13840 | (plus:DI (match_dup 1) |
13841 | (const_int -1))) | |
61c07d3c DE |
13842 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13843 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 DE |
13844 | "TARGET_POWERPC64" |
13845 | "* | |
13846 | { | |
13847 | if (which_alternative != 0) | |
13848 | return \"#\"; | |
856a6884 | 13849 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13850 | return \"bdz %l0\"; |
13851 | else | |
f607bc57 | 13852 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
13853 | }" |
13854 | [(set_attr "type" "branch") | |
61c07d3c | 13855 | (set_attr "length" "*,12,16")]) |
0ad91047 DE |
13856 | |
13857 | (define_insn "*ctrdi_internal6" | |
13858 | [(set (pc) | |
61c07d3c | 13859 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") |
0ad91047 DE |
13860 | (const_int 1)) |
13861 | (pc) | |
13862 | (label_ref (match_operand 0 "" "")))) | |
61c07d3c | 13863 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l") |
0ad91047 DE |
13864 | (plus:DI (match_dup 1) |
13865 | (const_int -1))) | |
61c07d3c DE |
13866 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13867 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
0ad91047 | 13868 | "TARGET_POWERPC64" |
5f81043f RK |
13869 | "* |
13870 | { | |
13871 | if (which_alternative != 0) | |
13872 | return \"#\"; | |
856a6884 | 13873 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
13874 | return \"{bdn|bdnz} %l0\"; |
13875 | else | |
f607bc57 | 13876 | return \"bdz $+8\;b %l0\"; |
5f81043f RK |
13877 | }" |
13878 | [(set_attr "type" "branch") | |
61c07d3c | 13879 | (set_attr "length" "*,12,16")]) |
5f81043f | 13880 | |
0ad91047 DE |
13881 | ;; Now the splitters if we could not allocate the CTR register |
13882 | ||
1fd4e8c1 RK |
13883 | (define_split |
13884 | [(set (pc) | |
13885 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 13886 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
13887 | (const_int 1)]) |
13888 | (match_operand 5 "" "") | |
13889 | (match_operand 6 "" ""))) | |
cd2b37d9 | 13890 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
13891 | (plus:SI (match_dup 1) |
13892 | (const_int -1))) | |
1fd4e8c1 RK |
13893 | (clobber (match_scratch:CC 3 "")) |
13894 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 | 13895 | "! TARGET_POWERPC64 && reload_completed" |
1fd4e8c1 | 13896 | [(parallel [(set (match_dup 3) |
5f81043f RK |
13897 | (compare:CC (plus:SI (match_dup 1) |
13898 | (const_int -1)) | |
1fd4e8c1 | 13899 | (const_int 0))) |
5f81043f RK |
13900 | (set (match_dup 0) |
13901 | (plus:SI (match_dup 1) | |
13902 | (const_int -1)))]) | |
13903 | (set (pc) (if_then_else (match_dup 7) | |
13904 | (match_dup 5) | |
13905 | (match_dup 6)))] | |
1fd4e8c1 RK |
13906 | " |
13907 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13908 | const0_rtx); }") | |
13909 | ||
13910 | (define_split | |
13911 | [(set (pc) | |
13912 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 13913 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
13914 | (const_int 1)]) |
13915 | (match_operand 5 "" "") | |
13916 | (match_operand 6 "" ""))) | |
9ebbca7d | 13917 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
13918 | (plus:SI (match_dup 1) (const_int -1))) |
13919 | (clobber (match_scratch:CC 3 "")) | |
13920 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 DE |
13921 | "! TARGET_POWERPC64 && reload_completed |
13922 | && ! gpc_reg_operand (operands[0], SImode)" | |
1fd4e8c1 | 13923 | [(parallel [(set (match_dup 3) |
5f81043f RK |
13924 | (compare:CC (plus:SI (match_dup 1) |
13925 | (const_int -1)) | |
1fd4e8c1 | 13926 | (const_int 0))) |
5f81043f RK |
13927 | (set (match_dup 4) |
13928 | (plus:SI (match_dup 1) | |
13929 | (const_int -1)))]) | |
13930 | (set (match_dup 0) | |
13931 | (match_dup 4)) | |
13932 | (set (pc) (if_then_else (match_dup 7) | |
13933 | (match_dup 5) | |
13934 | (match_dup 6)))] | |
1fd4e8c1 RK |
13935 | " |
13936 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13937 | const0_rtx); }") | |
0ad91047 DE |
13938 | (define_split |
13939 | [(set (pc) | |
13940 | (if_then_else (match_operator 2 "comparison_operator" | |
13941 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
13942 | (const_int 1)]) | |
61c07d3c DE |
13943 | (match_operand 5 "" "") |
13944 | (match_operand 6 "" ""))) | |
0ad91047 DE |
13945 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
13946 | (plus:DI (match_dup 1) | |
13947 | (const_int -1))) | |
13948 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c DE |
13949 | (clobber (match_scratch:DI 4 ""))] |
13950 | "TARGET_POWERPC64 && reload_completed" | |
0ad91047 DE |
13951 | [(parallel [(set (match_dup 3) |
13952 | (compare:CC (plus:DI (match_dup 1) | |
13953 | (const_int -1)) | |
13954 | (const_int 0))) | |
13955 | (set (match_dup 0) | |
13956 | (plus:DI (match_dup 1) | |
13957 | (const_int -1)))]) | |
61c07d3c DE |
13958 | (set (pc) (if_then_else (match_dup 7) |
13959 | (match_dup 5) | |
13960 | (match_dup 6)))] | |
0ad91047 | 13961 | " |
61c07d3c | 13962 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], |
0ad91047 DE |
13963 | const0_rtx); }") |
13964 | ||
13965 | (define_split | |
13966 | [(set (pc) | |
13967 | (if_then_else (match_operator 2 "comparison_operator" | |
13968 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
13969 | (const_int 1)]) | |
61c07d3c DE |
13970 | (match_operand 5 "" "") |
13971 | (match_operand 6 "" ""))) | |
9ebbca7d | 13972 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
13973 | (plus:DI (match_dup 1) (const_int -1))) |
13974 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 13975 | (clobber (match_scratch:DI 4 ""))] |
0ad91047 DE |
13976 | "TARGET_POWERPC64 && reload_completed |
13977 | && ! gpc_reg_operand (operands[0], DImode)" | |
13978 | [(parallel [(set (match_dup 3) | |
13979 | (compare:CC (plus:DI (match_dup 1) | |
13980 | (const_int -1)) | |
13981 | (const_int 0))) | |
13982 | (set (match_dup 4) | |
13983 | (plus:DI (match_dup 1) | |
13984 | (const_int -1)))]) | |
13985 | (set (match_dup 0) | |
13986 | (match_dup 4)) | |
61c07d3c DE |
13987 | (set (pc) (if_then_else (match_dup 7) |
13988 | (match_dup 5) | |
13989 | (match_dup 6)))] | |
0ad91047 | 13990 | " |
61c07d3c | 13991 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], |
0ad91047 | 13992 | const0_rtx); }") |
c94ccb87 | 13993 | |
e0cd0770 JC |
13994 | \f |
13995 | (define_insn "trap" | |
13996 | [(trap_if (const_int 1) (const_int 0))] | |
13997 | "" | |
13998 | "{t 31,0,0|trap}") | |
13999 | ||
14000 | (define_expand "conditional_trap" | |
14001 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14002 | [(match_dup 2) (match_dup 3)]) | |
14003 | (match_operand 1 "const_int_operand" ""))] | |
14004 | "" | |
14005 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
14006 | operands[2] = rs6000_compare_op0; | |
14007 | operands[3] = rs6000_compare_op1;") | |
14008 | ||
14009 | (define_insn "" | |
14010 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14011 | [(match_operand:SI 1 "register_operand" "r") | |
14012 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
14013 | (const_int 0))] | |
14014 | "" | |
a157febd GK |
14015 | "{t|tw}%V0%I2 %1,%2") |
14016 | ||
14017 | (define_insn "" | |
14018 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14019 | [(match_operand:DI 1 "register_operand" "r") | |
14020 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
14021 | (const_int 0))] | |
14022 | "TARGET_POWERPC64" | |
14023 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
14024 | \f |
14025 | ;; Insns related to generating the function prologue and epilogue. | |
14026 | ||
14027 | (define_expand "prologue" | |
14028 | [(use (const_int 0))] | |
14029 | "TARGET_SCHED_PROLOG" | |
14030 | " | |
14031 | { | |
14032 | rs6000_emit_prologue (); | |
14033 | DONE; | |
14034 | }") | |
14035 | ||
14036 | (define_insn "movesi_from_cr" | |
14037 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
14038 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) | |
14039 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))] | |
14040 | "" | |
309323c2 DE |
14041 | "mfcr %0" |
14042 | [(set_attr "type" "cr_logical")]) | |
9ebbca7d GK |
14043 | |
14044 | (define_insn "*stmw" | |
14045 | [(match_parallel 0 "stmw_operation" | |
14046 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
14047 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
14048 | "TARGET_MULTIPLE" | |
14049 | "{stm|stmw} %2,%1") | |
14050 | ||
14051 | (define_insn "*save_fpregs_si" | |
14052 | [(match_parallel 0 "any_operand" | |
14053 | [(clobber (match_operand:SI 1 "register_operand" "=l")) | |
14054 | (use (match_operand:SI 2 "call_operand" "s")) | |
14055 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14056 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14057 | "TARGET_32BIT" | |
14058 | "bl %z2") | |
14059 | ||
14060 | (define_insn "*save_fpregs_di" | |
14061 | [(match_parallel 0 "any_operand" | |
14062 | [(clobber (match_operand:DI 1 "register_operand" "=l")) | |
14063 | (use (match_operand:DI 2 "call_operand" "s")) | |
14064 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14065 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14066 | "TARGET_64BIT" | |
14067 | "bl %z2") | |
14068 | ||
14069 | ; These are to explain that changes to the stack pointer should | |
14070 | ; not be moved over stores to stack memory. | |
14071 | (define_insn "stack_tie" | |
14072 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
14073 | (unspec:BLK [(match_dup 0)] 5))] | |
14074 | "" | |
14075 | "" | |
14076 | [(set_attr "length" "0")]) | |
14077 | ||
14078 | ||
14079 | (define_expand "epilogue" | |
14080 | [(use (const_int 0))] | |
14081 | "TARGET_SCHED_PROLOG" | |
14082 | " | |
14083 | { | |
14084 | rs6000_emit_epilogue (FALSE); | |
14085 | DONE; | |
14086 | }") | |
14087 | ||
14088 | ; On some processors, doing the mtcrf one CC register at a time is | |
14089 | ; faster (like on the 604e). On others, doing them all at once is | |
14090 | ; faster; for instance, on the 601 and 750. | |
14091 | ||
14092 | (define_expand "movsi_to_cr_one" | |
35aba846 DE |
14093 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14094 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
14095 | (match_dup 2)] 20))] | |
14096 | "" | |
14097 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
9ebbca7d GK |
14098 | |
14099 | (define_insn "*movsi_to_cr" | |
35aba846 DE |
14100 | [(match_parallel 0 "mtcrf_operation" |
14101 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") | |
14102 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
14103 | (match_operand 3 "immediate_operand" "n")] | |
9ebbca7d GK |
14104 | 20))])] |
14105 | "" | |
e35b9579 GK |
14106 | "* |
14107 | { | |
14108 | int mask = 0; | |
14109 | int i; | |
14110 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14111 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14112 | operands[4] = GEN_INT (mask); | |
14113 | return \"mtcrf %4,%2\"; | |
309323c2 DE |
14114 | }" |
14115 | [(set_attr "type" "cr_logical")]) | |
9ebbca7d GK |
14116 | |
14117 | (define_insn "" | |
309323c2 DE |
14118 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14119 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
14120 | (match_operand 2 "immediate_operand" "n")] 20))] | |
14121 | "GET_CODE (operands[0]) == REG | |
14122 | && CR_REGNO_P (REGNO (operands[0])) | |
14123 | && GET_CODE (operands[2]) == CONST_INT | |
14124 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
14125 | "mtcrf %R0,%1" | |
14126 | [(set_attr "type" "cr_logical")]) | |
9ebbca7d GK |
14127 | |
14128 | ; The load-multiple instructions have similar properties. | |
14129 | ; Note that "load_multiple" is a name known to the machine-independent | |
14130 | ; code that actually corresponds to the powerpc load-string. | |
14131 | ||
14132 | (define_insn "*lmw" | |
35aba846 DE |
14133 | [(match_parallel 0 "lmw_operation" |
14134 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14135 | (match_operand:SI 2 "memory_operand" "m"))])] | |
14136 | "TARGET_MULTIPLE" | |
14137 | "{lm|lmw} %1,%2") | |
9ebbca7d GK |
14138 | |
14139 | (define_insn "*return_internal_si" | |
e35b9579 GK |
14140 | [(return) |
14141 | (use (match_operand:SI 0 "register_operand" "lc"))] | |
9ebbca7d | 14142 | "TARGET_32BIT" |
cccf3bdc | 14143 | "b%T0" |
9ebbca7d GK |
14144 | [(set_attr "type" "jmpreg")]) |
14145 | ||
14146 | (define_insn "*return_internal_di" | |
e35b9579 GK |
14147 | [(return) |
14148 | (use (match_operand:DI 0 "register_operand" "lc"))] | |
9ebbca7d | 14149 | "TARGET_64BIT" |
cccf3bdc | 14150 | "b%T0" |
9ebbca7d GK |
14151 | [(set_attr "type" "jmpreg")]) |
14152 | ||
14153 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
14154 | ; stuff was in GCC. Oh, and "any_operand" is a bit flexible... | |
14155 | ||
14156 | (define_insn "*return_and_restore_fpregs_si" | |
14157 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
14158 | [(return) |
14159 | (use (match_operand:SI 1 "register_operand" "l")) | |
9ebbca7d GK |
14160 | (use (match_operand:SI 2 "call_operand" "s")) |
14161 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14162 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14163 | "TARGET_32BIT" | |
14164 | "b %z2") | |
14165 | ||
14166 | (define_insn "*return_and_restore_fpregs_di" | |
14167 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
14168 | [(return) |
14169 | (use (match_operand:DI 1 "register_operand" "l")) | |
9ebbca7d GK |
14170 | (use (match_operand:DI 2 "call_operand" "s")) |
14171 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14172 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14173 | "TARGET_64BIT" | |
14174 | "b %z2") | |
14175 | ||
83720594 RH |
14176 | ; This is used in compiling the unwind routines. |
14177 | (define_expand "eh_return" | |
14178 | [(use (match_operand 0 "general_operand" "")) | |
14179 | (use (match_operand 1 "general_operand" ""))] | |
9ebbca7d GK |
14180 | "" |
14181 | " | |
14182 | { | |
3553b09d | 14183 | #if TARGET_AIX |
83720594 | 14184 | rs6000_emit_eh_toc_restore (operands[0]); |
3553b09d | 14185 | #endif |
83720594 RH |
14186 | if (TARGET_32BIT) |
14187 | emit_insn (gen_eh_set_lr_si (operands[1])); | |
9ebbca7d | 14188 | else |
83720594 RH |
14189 | emit_insn (gen_eh_set_lr_di (operands[1])); |
14190 | emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]); | |
9ebbca7d GK |
14191 | DONE; |
14192 | }") | |
14193 | ||
83720594 RH |
14194 | ; We can't expand this before we know where the link register is stored. |
14195 | (define_insn "eh_set_lr_si" | |
14196 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9) | |
466eb3e0 | 14197 | (clobber (match_scratch:SI 1 "=&b"))] |
83720594 RH |
14198 | "TARGET_32BIT" |
14199 | "#") | |
14200 | ||
14201 | (define_insn "eh_set_lr_di" | |
14202 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9) | |
466eb3e0 | 14203 | (clobber (match_scratch:DI 1 "=&b"))] |
83720594 RH |
14204 | "TARGET_64BIT" |
14205 | "#") | |
9ebbca7d GK |
14206 | |
14207 | (define_split | |
83720594 RH |
14208 | [(unspec_volatile [(match_operand 0 "register_operand" "")] 9) |
14209 | (clobber (match_scratch 1 ""))] | |
14210 | "reload_completed" | |
14211 | [(const_int 0)] | |
9ebbca7d GK |
14212 | " |
14213 | { | |
83720594 | 14214 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d | 14215 | |
83720594 RH |
14216 | if (info->lr_save_p) |
14217 | { | |
14218 | rtx frame_rtx = stack_pointer_rtx; | |
14219 | int sp_offset = 0; | |
14220 | rtx tmp; | |
9ebbca7d | 14221 | |
83720594 RH |
14222 | if (frame_pointer_needed |
14223 | || current_function_calls_alloca | |
14224 | || info->total_size > 32767) | |
14225 | { | |
14226 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
14227 | frame_rtx = operands[1]; | |
14228 | } | |
14229 | else if (info->push_p) | |
14230 | sp_offset = info->total_size; | |
9ebbca7d | 14231 | |
83720594 RH |
14232 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); |
14233 | tmp = gen_rtx_MEM (Pmode, tmp); | |
14234 | emit_move_insn (tmp, operands[0]); | |
14235 | } | |
14236 | else | |
14237 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
14238 | DONE; | |
14239 | }") | |
0ac081f6 | 14240 | |
01a2ccd0 DE |
14241 | (define_insn "prefetch" |
14242 | [(prefetch (match_operand:V4SI 0 "address_operand" "p") | |
6041bf2f DE |
14243 | (match_operand:SI 1 "const_int_operand" "n") |
14244 | (match_operand:SI 2 "const_int_operand" "n"))] | |
01a2ccd0 | 14245 | "TARGET_POWERPC" |
6041bf2f DE |
14246 | "* |
14247 | { | |
01a2ccd0 DE |
14248 | if (GET_CODE (operands[0]) == REG) |
14249 | return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; | |
14250 | return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; | |
6041bf2f DE |
14251 | }" |
14252 | [(set_attr "type" "load")]) | |
14253 | \f | |
0ac081f6 AH |
14254 | ;; AltiVec patterns |
14255 | ||
14256 | ;; Generic LVX load instruction. | |
f18c054f | 14257 | (define_insn "altivec_lvx_4si" |
0ec4e2a8 | 14258 | [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") |
0ac081f6 AH |
14259 | (match_operand:V4SI 1 "memory_operand" "m"))] |
14260 | "TARGET_ALTIVEC" | |
9bddde52 | 14261 | "lvx %0,%y1" |
f18c054f DB |
14262 | [(set_attr "type" "vecload")]) |
14263 | ||
14264 | (define_insn "altivec_lvx_8hi" | |
0ec4e2a8 | 14265 | [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") |
f18c054f DB |
14266 | (match_operand:V8HI 1 "memory_operand" "m"))] |
14267 | "TARGET_ALTIVEC" | |
14268 | "lvx %0,%y1" | |
14269 | [(set_attr "type" "vecload")]) | |
14270 | ||
14271 | (define_insn "altivec_lvx_16qi" | |
0ec4e2a8 | 14272 | [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") |
f18c054f DB |
14273 | (match_operand:V16QI 1 "memory_operand" "m"))] |
14274 | "TARGET_ALTIVEC" | |
14275 | "lvx %0,%y1" | |
14276 | [(set_attr "type" "vecload")]) | |
14277 | ||
14278 | (define_insn "altivec_lvx_4sf" | |
0ec4e2a8 | 14279 | [(set (match_operand:V4SF 0 "altivec_register_operand" "=v") |
f18c054f DB |
14280 | (match_operand:V4SF 1 "memory_operand" "m"))] |
14281 | "TARGET_ALTIVEC" | |
14282 | "lvx %0,%y1" | |
14283 | [(set_attr "type" "vecload")]) | |
0ac081f6 AH |
14284 | |
14285 | ;; Generic STVX store instruction. | |
f18c054f | 14286 | (define_insn "altivec_stvx_4si" |
0ac081f6 | 14287 | [(set (match_operand:V4SI 0 "memory_operand" "=m") |
0ec4e2a8 | 14288 | (match_operand:V4SI 1 "altivec_register_operand" "v"))] |
0ac081f6 | 14289 | "TARGET_ALTIVEC" |
9bddde52 | 14290 | "stvx %1,%y0" |
f18c054f DB |
14291 | [(set_attr "type" "vecstore")]) |
14292 | ||
14293 | (define_insn "altivec_stvx_8hi" | |
14294 | [(set (match_operand:V8HI 0 "memory_operand" "=m") | |
0ec4e2a8 | 14295 | (match_operand:V8HI 1 "altivec_register_operand" "v"))] |
f18c054f DB |
14296 | "TARGET_ALTIVEC" |
14297 | "stvx %1,%y0" | |
14298 | [(set_attr "type" "vecstore")]) | |
14299 | ||
14300 | (define_insn "altivec_stvx_16qi" | |
14301 | [(set (match_operand:V16QI 0 "memory_operand" "=m") | |
0ec4e2a8 | 14302 | (match_operand:V16QI 1 "altivec_register_operand" "v"))] |
f18c054f DB |
14303 | "TARGET_ALTIVEC" |
14304 | "stvx %1,%y0" | |
14305 | [(set_attr "type" "vecstore")]) | |
14306 | ||
14307 | (define_insn "altivec_stvx_4sf" | |
14308 | [(set (match_operand:V4SF 0 "memory_operand" "=m") | |
0ec4e2a8 | 14309 | (match_operand:V4SF 1 "altivec_register_operand" "v"))] |
f18c054f DB |
14310 | "TARGET_ALTIVEC" |
14311 | "stvx %1,%y0" | |
14312 | [(set_attr "type" "vecstore")]) | |
0ac081f6 AH |
14313 | |
14314 | ;; Vector move instructions. | |
14315 | (define_expand "movv4si" | |
14316 | [(set (match_operand:V4SI 0 "nonimmediate_operand" "") | |
14317 | (match_operand:V4SI 1 "any_operand" ""))] | |
14318 | "TARGET_ALTIVEC" | |
14319 | "{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }") | |
14320 | ||
14321 | (define_insn "*movv4si_internal" | |
04428ad4 AH |
14322 | [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,o,r,r") |
14323 | (match_operand:V4SI 1 "input_operand" "v,m,v,r,o,r"))] | |
0ac081f6 AH |
14324 | "TARGET_ALTIVEC" |
14325 | "@ | |
9bddde52 | 14326 | stvx %1,%y0 |
f3fe2696 | 14327 | lvx %0,%y1 |
0ec4e2a8 | 14328 | vor %0,%1,%1 |
78c875e8 AH |
14329 | stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 |
14330 | lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 | |
14331 | mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" | |
0ec4e2a8 | 14332 | [(set_attr "type" "altivec") |
78c875e8 | 14333 | (set_attr "length" "*,*,*,16,16,16")]) |
0ac081f6 AH |
14334 | |
14335 | (define_expand "movv8hi" | |
14336 | [(set (match_operand:V8HI 0 "nonimmediate_operand" "") | |
14337 | (match_operand:V8HI 1 "any_operand" ""))] | |
14338 | "TARGET_ALTIVEC" | |
14339 | "{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }") | |
14340 | ||
14341 | (define_insn "*movv8hi_internal1" | |
04428ad4 AH |
14342 | [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,o,r,r") |
14343 | (match_operand:V8HI 1 "input_operand" "v,m,v,r,o,r"))] | |
0ac081f6 AH |
14344 | "TARGET_ALTIVEC" |
14345 | "@ | |
9bddde52 | 14346 | stvx %1,%y0 |
f3fe2696 | 14347 | lvx %0,%y1 |
0ec4e2a8 | 14348 | vor %0,%1,%1 |
78c875e8 AH |
14349 | stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 |
14350 | lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 | |
14351 | mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" | |
0ec4e2a8 | 14352 | [(set_attr "type" "altivec") |
78c875e8 | 14353 | (set_attr "length" "*,*,*,16,16,16")]) |
0ac081f6 AH |
14354 | |
14355 | (define_expand "movv16qi" | |
14356 | [(set (match_operand:V16QI 0 "nonimmediate_operand" "") | |
14357 | (match_operand:V16QI 1 "any_operand" ""))] | |
14358 | "TARGET_ALTIVEC" | |
14359 | "{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }") | |
14360 | ||
14361 | (define_insn "*movv16qi_internal1" | |
04428ad4 AH |
14362 | [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,o,r,r") |
14363 | (match_operand:V16QI 1 "input_operand" "v,m,v,r,o,r"))] | |
0ac081f6 AH |
14364 | "TARGET_ALTIVEC" |
14365 | "@ | |
9bddde52 | 14366 | stvx %1,%y0 |
f3fe2696 | 14367 | lvx %0,%y1 |
0ec4e2a8 | 14368 | vor %0,%1,%1 |
78c875e8 AH |
14369 | stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 |
14370 | lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 | |
14371 | mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" | |
0ec4e2a8 | 14372 | [(set_attr "type" "altivec") |
78c875e8 | 14373 | (set_attr "length" "*,*,*,16,16,16")]) |
0ac081f6 AH |
14374 | |
14375 | (define_expand "movv4sf" | |
14376 | [(set (match_operand:V4SF 0 "nonimmediate_operand" "") | |
14377 | (match_operand:V4SF 1 "any_operand" ""))] | |
14378 | "TARGET_ALTIVEC" | |
14379 | "{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }") | |
14380 | ||
14381 | (define_insn "*movv4sf_internal1" | |
04428ad4 AH |
14382 | [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,o,r,r") |
14383 | (match_operand:V4SF 1 "input_operand" "v,m,v,r,o,r"))] | |
0ac081f6 AH |
14384 | "TARGET_ALTIVEC" |
14385 | "@ | |
9bddde52 | 14386 | stvx %1,%y0 |
f3fe2696 | 14387 | lvx %0,%y1 |
0ec4e2a8 | 14388 | vor %0,%1,%1 |
78c875e8 AH |
14389 | stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 |
14390 | lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 | |
14391 | mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" | |
0ec4e2a8 | 14392 | [(set_attr "type" "altivec") |
78c875e8 | 14393 | (set_attr "length" "*,*,*,16,16,16")]) |
0ac081f6 | 14394 | |
b188f760 AH |
14395 | (define_insn "get_vrsave_internal" |
14396 | [(set (match_operand:SI 0 "register_operand" "=r") | |
14397 | (unspec:SI [(reg:SI 109)] 214))] | |
14398 | "TARGET_ALTIVEC" | |
14399 | "* | |
14400 | { | |
14401 | if (TARGET_MACHO) | |
376aec5d | 14402 | return \"mfspr %0,256\"; |
b188f760 | 14403 | else |
376aec5d | 14404 | return \"mfvrsave %0\"; |
b188f760 AH |
14405 | }" |
14406 | [(set_attr "type" "altivec")]) | |
14407 | ||
00b960c7 AH |
14408 | (define_insn "*set_vrsave_internal" |
14409 | [(match_parallel 0 "vrsave_operation" | |
14410 | [(set (reg:SI 109) | |
a004eb82 AH |
14411 | (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r") |
14412 | (reg:SI 109)] 30))])] | |
00b960c7 | 14413 | "TARGET_ALTIVEC" |
b188f760 AH |
14414 | "* |
14415 | { | |
14416 | if (TARGET_MACHO) | |
376aec5d | 14417 | return \"mtspr 256,%1\"; |
b188f760 AH |
14418 | else |
14419 | return \"mtvrsave %1\"; | |
14420 | }" | |
00b960c7 AH |
14421 | [(set_attr "type" "altivec")]) |
14422 | ||
69ef87e2 AH |
14423 | ;; Vector clears |
14424 | (define_insn "*movv4si_const0" | |
14425 | [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") | |
14426 | (match_operand:V4SI 1 "zero_constant" ""))] | |
14427 | "TARGET_ALTIVEC" | |
14428 | "vxor %0,%0,%0" | |
14429 | [(set_attr "type" "vecsimple")]) | |
14430 | ||
14431 | (define_insn "*movv4sf_const0" | |
14432 | [(set (match_operand:V4SF 0 "altivec_register_operand" "=v") | |
14433 | (match_operand:V4SF 1 "zero_constant" ""))] | |
14434 | ||
14435 | "TARGET_ALTIVEC" | |
14436 | "vxor %0,%0,%0" | |
14437 | [(set_attr "type" "vecsimple")]) | |
14438 | ||
14439 | (define_insn "*movv8hi_const0" | |
14440 | [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") | |
14441 | (match_operand:V8HI 1 "zero_constant" ""))] | |
14442 | "TARGET_ALTIVEC" | |
14443 | "vxor %0,%0,%0" | |
14444 | [(set_attr "type" "vecsimple")]) | |
14445 | ||
14446 | (define_insn "*movv16qi_const0" | |
14447 | [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") | |
14448 | (match_operand:V16QI 1 "zero_constant" ""))] | |
14449 | "TARGET_ALTIVEC" | |
14450 | "vxor %0,%0,%0" | |
14451 | [(set_attr "type" "vecsimple")]) | |
14452 | ||
0ac081f6 AH |
14453 | ;; Simple binary operations. |
14454 | ||
f18c054f | 14455 | (define_insn "addv16qi3" |
0ac081f6 | 14456 | [(set (match_operand:V16QI 0 "register_operand" "=v") |
f18c054f DB |
14457 | (plus:V16QI (match_operand:V16QI 1 "register_operand" "v") |
14458 | (match_operand:V16QI 2 "register_operand" "v")))] | |
0ac081f6 | 14459 | "TARGET_ALTIVEC" |
9bddde52 | 14460 | "vaddubm %0,%1,%2" |
f18c054f | 14461 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14462 | |
f18c054f | 14463 | (define_insn "addv8hi3" |
0ac081f6 | 14464 | [(set (match_operand:V8HI 0 "register_operand" "=v") |
f18c054f DB |
14465 | (plus:V8HI (match_operand:V8HI 1 "register_operand" "v") |
14466 | (match_operand:V8HI 2 "register_operand" "v")))] | |
0ac081f6 | 14467 | "TARGET_ALTIVEC" |
9bddde52 | 14468 | "vadduhm %0,%1,%2" |
f18c054f | 14469 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14470 | |
f18c054f | 14471 | (define_insn "addv4si3" |
0ac081f6 | 14472 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
14473 | (plus:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14474 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 14475 | "TARGET_ALTIVEC" |
9bddde52 | 14476 | "vadduwm %0,%1,%2" |
f18c054f | 14477 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14478 | |
f18c054f | 14479 | (define_insn "addv4sf3" |
0ac081f6 | 14480 | [(set (match_operand:V4SF 0 "register_operand" "=v") |
f18c054f DB |
14481 | (plus:V4SF (match_operand:V4SF 1 "register_operand" "v") |
14482 | (match_operand:V4SF 2 "register_operand" "v")))] | |
0ac081f6 | 14483 | "TARGET_ALTIVEC" |
9bddde52 | 14484 | "vaddfp %0,%1,%2" |
f18c054f | 14485 | [(set_attr "type" "vecfloat")]) |
0ac081f6 AH |
14486 | |
14487 | (define_insn "altivec_vaddcuw" | |
14488 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14489 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14490 | (match_operand:V4SI 2 "register_operand" "v")] 35))] | |
14491 | "TARGET_ALTIVEC" | |
9bddde52 | 14492 | "vaddcuw %0,%1,%2" |
f18c054f | 14493 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14494 | |
14495 | (define_insn "altivec_vaddubs" | |
14496 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14497 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
5f004351 AH |
14498 | (match_operand:V16QI 2 "register_operand" "v")] 36)) |
14499 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 14500 | "TARGET_ALTIVEC" |
9bddde52 | 14501 | "vaddubs %0,%1,%2" |
f18c054f | 14502 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14503 | |
14504 | (define_insn "altivec_vaddsbs" | |
14505 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14506 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
5f004351 AH |
14507 | (match_operand:V16QI 2 "register_operand" "v")] 37)) |
14508 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 14509 | "TARGET_ALTIVEC" |
9bddde52 | 14510 | "vaddsbs %0,%1,%2" |
f18c054f | 14511 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14512 | |
14513 | (define_insn "altivec_vadduhs" | |
14514 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14515 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
5f004351 AH |
14516 | (match_operand:V8HI 2 "register_operand" "v")] 38)) |
14517 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 14518 | "TARGET_ALTIVEC" |
9bddde52 | 14519 | "vadduhs %0,%1,%2" |
f18c054f | 14520 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14521 | |
14522 | (define_insn "altivec_vaddshs" | |
14523 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14524 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
5f004351 AH |
14525 | (match_operand:V8HI 2 "register_operand" "v")] 39)) |
14526 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 14527 | "TARGET_ALTIVEC" |
9bddde52 | 14528 | "vaddshs %0,%1,%2" |
f18c054f | 14529 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14530 | |
14531 | (define_insn "altivec_vadduws" | |
14532 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14533 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
5f004351 AH |
14534 | (match_operand:V4SI 2 "register_operand" "v")] 40)) |
14535 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 14536 | "TARGET_ALTIVEC" |
9bddde52 | 14537 | "vadduws %0,%1,%2" |
f18c054f | 14538 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14539 | |
14540 | (define_insn "altivec_vaddsws" | |
14541 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14542 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
5f004351 AH |
14543 | (match_operand:V4SI 2 "register_operand" "v")] 41)) |
14544 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 14545 | "TARGET_ALTIVEC" |
9bddde52 | 14546 | "vaddsws %0,%1,%2" |
f18c054f | 14547 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14548 | |
f18c054f | 14549 | (define_insn "andv4si3" |
0ac081f6 | 14550 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
14551 | (and:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14552 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 14553 | "TARGET_ALTIVEC" |
9bddde52 | 14554 | "vand %0,%1,%2" |
f18c054f | 14555 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14556 | |
14557 | (define_insn "altivec_vandc" | |
14558 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
2212663f DB |
14559 | (and:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14560 | (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))))] | |
0ac081f6 | 14561 | "TARGET_ALTIVEC" |
9bddde52 | 14562 | "vandc %0,%1,%2" |
f18c054f | 14563 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14564 | |
14565 | (define_insn "altivec_vavgub" | |
14566 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14567 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14568 | (match_operand:V16QI 2 "register_operand" "v")] 44))] | |
14569 | "TARGET_ALTIVEC" | |
9bddde52 | 14570 | "vavgub %0,%1,%2" |
f18c054f | 14571 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14572 | |
14573 | (define_insn "altivec_vavgsb" | |
14574 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14575 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14576 | (match_operand:V16QI 2 "register_operand" "v")] 45))] | |
14577 | "TARGET_ALTIVEC" | |
9bddde52 | 14578 | "vavgsb %0,%1,%2" |
f18c054f | 14579 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14580 | |
14581 | (define_insn "altivec_vavguh" | |
14582 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14583 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14584 | (match_operand:V8HI 2 "register_operand" "v")] 46))] | |
14585 | "TARGET_ALTIVEC" | |
9bddde52 | 14586 | "vavguh %0,%1,%2" |
f18c054f | 14587 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14588 | |
14589 | (define_insn "altivec_vavgsh" | |
14590 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14591 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14592 | (match_operand:V8HI 2 "register_operand" "v")] 47))] | |
14593 | "TARGET_ALTIVEC" | |
9bddde52 | 14594 | "vavgsh %0,%1,%2" |
f18c054f | 14595 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14596 | |
14597 | (define_insn "altivec_vavguw" | |
14598 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14599 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14600 | (match_operand:V4SI 2 "register_operand" "v")] 48))] | |
14601 | "TARGET_ALTIVEC" | |
9bddde52 | 14602 | "vavguw %0,%1,%2" |
f18c054f | 14603 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14604 | |
14605 | (define_insn "altivec_vavgsw" | |
14606 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14607 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14608 | (match_operand:V4SI 2 "register_operand" "v")] 49))] | |
14609 | "TARGET_ALTIVEC" | |
9bddde52 | 14610 | "vavgsw %0,%1,%2" |
f18c054f | 14611 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14612 | |
14613 | (define_insn "altivec_vcmpbfp" | |
14614 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14615 | (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") | |
14616 | (match_operand:V4SF 2 "register_operand" "v")] 50))] | |
14617 | "TARGET_ALTIVEC" | |
9bddde52 | 14618 | "vcmpbfp %0,%1,%2" |
f18c054f | 14619 | [(set_attr "type" "veccmp")]) |
0ac081f6 AH |
14620 | |
14621 | (define_insn "altivec_vcmpequb" | |
14622 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14623 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14624 | (match_operand:V16QI 2 "register_operand" "v")] 51))] | |
14625 | "TARGET_ALTIVEC" | |
9bddde52 | 14626 | "vcmpequb %0,%1,%2" |
f18c054f | 14627 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14628 | |
14629 | (define_insn "altivec_vcmpequh" | |
14630 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14631 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14632 | (match_operand:V8HI 2 "register_operand" "v")] 52))] | |
14633 | "TARGET_ALTIVEC" | |
9bddde52 | 14634 | "vcmpequh %0,%1,%2" |
f18c054f | 14635 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14636 | |
14637 | (define_insn "altivec_vcmpequw" | |
14638 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14639 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14640 | (match_operand:V4SI 2 "register_operand" "v")] 53))] | |
14641 | "TARGET_ALTIVEC" | |
9bddde52 | 14642 | "vcmpequw %0,%1,%2" |
f18c054f | 14643 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14644 | |
14645 | (define_insn "altivec_vcmpeqfp" | |
14646 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14647 | (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") | |
14648 | (match_operand:V4SF 2 "register_operand" "v")] 54))] | |
14649 | "TARGET_ALTIVEC" | |
9bddde52 | 14650 | "vcmpeqfp %0,%1,%2" |
f18c054f | 14651 | [(set_attr "type" "veccmp")]) |
0ac081f6 AH |
14652 | |
14653 | (define_insn "altivec_vcmpgefp" | |
14654 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14655 | (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") | |
14656 | (match_operand:V4SF 2 "register_operand" "v")] 55))] | |
14657 | "TARGET_ALTIVEC" | |
9bddde52 | 14658 | "vcmpgefp %0,%1,%2" |
f18c054f | 14659 | [(set_attr "type" "veccmp")]) |
0ac081f6 AH |
14660 | |
14661 | (define_insn "altivec_vcmpgtub" | |
14662 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14663 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14664 | (match_operand:V16QI 2 "register_operand" "v")] 56))] | |
14665 | "TARGET_ALTIVEC" | |
9bddde52 | 14666 | "vcmpgtub %0,%1,%2" |
f18c054f | 14667 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14668 | |
14669 | (define_insn "altivec_vcmpgtsb" | |
14670 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
14671 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
14672 | (match_operand:V16QI 2 "register_operand" "v")] 57))] | |
14673 | "TARGET_ALTIVEC" | |
9bddde52 | 14674 | "vcmpgtsb %0,%1,%2" |
f18c054f | 14675 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14676 | |
14677 | (define_insn "altivec_vcmpgtuh" | |
14678 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14679 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14680 | (match_operand:V8HI 2 "register_operand" "v")] 58))] | |
14681 | "TARGET_ALTIVEC" | |
9bddde52 | 14682 | "vcmpgtuh %0,%1,%2" |
f18c054f | 14683 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14684 | |
14685 | (define_insn "altivec_vcmpgtsh" | |
14686 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14687 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14688 | (match_operand:V8HI 2 "register_operand" "v")] 59))] | |
14689 | "TARGET_ALTIVEC" | |
9bddde52 | 14690 | "vcmpgtsh %0,%1,%2" |
f18c054f | 14691 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14692 | |
14693 | (define_insn "altivec_vcmpgtuw" | |
14694 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14695 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14696 | (match_operand:V4SI 2 "register_operand" "v")] 60))] | |
14697 | "TARGET_ALTIVEC" | |
9bddde52 | 14698 | "vcmpgtuw %0,%1,%2" |
f18c054f | 14699 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14700 | |
14701 | (define_insn "altivec_vcmpgtsw" | |
14702 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14703 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
14704 | (match_operand:V4SI 2 "register_operand" "v")] 61))] | |
14705 | "TARGET_ALTIVEC" | |
9bddde52 | 14706 | "vcmpgtsw %0,%1,%2" |
f18c054f | 14707 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
14708 | |
14709 | (define_insn "altivec_vcmpgtfp" | |
14710 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14711 | (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") | |
14712 | (match_operand:V4SF 2 "register_operand" "v")] 62))] | |
14713 | "TARGET_ALTIVEC" | |
9bddde52 | 14714 | "vcmpgtfp %0,%1,%2" |
f18c054f | 14715 | [(set_attr "type" "veccmp")]) |
0ac081f6 | 14716 | |
2212663f DB |
14717 | ;; Fused multiply add |
14718 | (define_insn "altivec_vmaddfp" | |
14719 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
14720 | (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") | |
14721 | (match_operand:V4SF 2 "register_operand" "v")) | |
14722 | (match_operand:V4SF 3 "register_operand" "v")))] | |
14723 | "TARGET_ALTIVEC" | |
14724 | "vmaddfp %0,%1,%2,%3" | |
14725 | [(set_attr "type" "vecfloat")]) | |
14726 | ||
14727 | ;; The unspec here is a vec splat of 0. We do multiply as a fused | |
14728 | ;; multiply-add with an add of a 0 vector. | |
14729 | ||
14730 | (define_expand "mulv4sf3" | |
14731 | [(set (match_dup 3) (unspec:V4SF [(const_int 0)] 142)) | |
14732 | (set (match_operand:V4SF 0 "register_operand" "=v") | |
14733 | (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") | |
14734 | (match_operand:V4SF 2 "register_operand" "v")) | |
14735 | (match_dup 3)))] | |
14736 | "TARGET_ALTIVEC && TARGET_FUSED_MADD" | |
14737 | " | |
14738 | { operands[3] = gen_reg_rtx (V4SFmode); }") | |
14739 | ||
14740 | ;; Fused multiply subtract | |
14741 | (define_insn "altivec_vnmsubfp" | |
14742 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
14743 | (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") | |
14744 | (match_operand:V4SF 2 "register_operand" "v")) | |
14745 | (match_operand:V4SF 3 "register_operand" "v")))] | |
14746 | "TARGET_ALTIVEC" | |
95385cbb | 14747 | "vnmsubfp %0,%1,%2,%3" |
2212663f DB |
14748 | [(set_attr "type" "vecfloat")]) |
14749 | ||
14750 | ||
14751 | (define_insn "altivec_vmsumubm" | |
14752 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14753 | (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") | |
14754 | (match_operand:V16QI 2 "register_operand" "v") | |
14755 | (match_operand:V4SI 3 "register_operand" "v")] 65))] | |
14756 | "TARGET_ALTIVEC" | |
14757 | "vmsumubm %0, %1, %2, %3" | |
14758 | [(set_attr "type" "veccomplex")]) | |
14759 | ||
14760 | (define_insn "altivec_vmsummbm" | |
14761 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14762 | (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") | |
14763 | (match_operand:V16QI 2 "register_operand" "v") | |
14764 | (match_operand:V4SI 3 "register_operand" "v")] 66))] | |
14765 | "TARGET_ALTIVEC" | |
14766 | "vmsumubm %0, %1, %2, %3" | |
14767 | [(set_attr "type" "veccomplex")]) | |
14768 | ||
14769 | (define_insn "altivec_vmsumuhm" | |
14770 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14771 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
14772 | (match_operand:V8HI 2 "register_operand" "v") | |
14773 | (match_operand:V4SI 3 "register_operand" "v")] 67))] | |
14774 | "TARGET_ALTIVEC" | |
14775 | "vmsumuhm %0, %1, %2, %3" | |
14776 | [(set_attr "type" "veccomplex")]) | |
14777 | ||
14778 | (define_insn "altivec_vmsumshm" | |
14779 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14780 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
14781 | (match_operand:V8HI 2 "register_operand" "v") | |
14782 | (match_operand:V4SI 3 "register_operand" "v")] 68))] | |
14783 | "TARGET_ALTIVEC" | |
14784 | "vmsumshm %0, %1, %2, %3" | |
14785 | [(set_attr "type" "veccomplex")]) | |
14786 | ||
14787 | (define_insn "altivec_vmsumuhs" | |
14788 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14789 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
14790 | (match_operand:V8HI 2 "register_operand" "v") | |
5f004351 AH |
14791 | (match_operand:V4SI 3 "register_operand" "v")] 69)) |
14792 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
2212663f DB |
14793 | "TARGET_ALTIVEC" |
14794 | "vmsumuhs %0, %1, %2, %3" | |
14795 | [(set_attr "type" "veccomplex")]) | |
14796 | ||
14797 | (define_insn "altivec_vmsumshs" | |
14798 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
14799 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
14800 | (match_operand:V8HI 2 "register_operand" "v") | |
5f004351 AH |
14801 | (match_operand:V4SI 3 "register_operand" "v")] 70)) |
14802 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
2212663f DB |
14803 | "TARGET_ALTIVEC" |
14804 | "vmsumshs %0, %1, %2, %3" | |
14805 | [(set_attr "type" "veccomplex")]) | |
14806 | ||
f18c054f | 14807 | (define_insn "umaxv16qi3" |
0ac081f6 | 14808 | [(set (match_operand:V16QI 0 "register_operand" "=v") |
f18c054f DB |
14809 | (umax:V16QI (match_operand:V16QI 1 "register_operand" "v") |
14810 | (match_operand:V16QI 2 "register_operand" "v")))] | |
0ac081f6 | 14811 | "TARGET_ALTIVEC" |
9bddde52 | 14812 | "vmaxub %0,%1,%2" |
f18c054f | 14813 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14814 | |
f18c054f | 14815 | (define_insn "smaxv16qi3" |
0ac081f6 | 14816 | [(set (match_operand:V16QI 0 "register_operand" "=v") |
f18c054f DB |
14817 | (smax:V16QI (match_operand:V16QI 1 "register_operand" "v") |
14818 | (match_operand:V16QI 2 "register_operand" "v")))] | |
0ac081f6 | 14819 | "TARGET_ALTIVEC" |
9bddde52 | 14820 | "vmaxsb %0,%1,%2" |
f18c054f | 14821 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14822 | |
f18c054f | 14823 | (define_insn "umaxv8hi3" |
0ac081f6 | 14824 | [(set (match_operand:V8HI 0 "register_operand" "=v") |
f18c054f DB |
14825 | (umax:V8HI (match_operand:V8HI 1 "register_operand" "v") |
14826 | (match_operand:V8HI 2 "register_operand" "v")))] | |
0ac081f6 | 14827 | "TARGET_ALTIVEC" |
9bddde52 | 14828 | "vmaxuh %0,%1,%2" |
f18c054f | 14829 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14830 | |
f18c054f | 14831 | (define_insn "smaxv8hi3" |
0ac081f6 | 14832 | [(set (match_operand:V8HI 0 "register_operand" "=v") |
f18c054f DB |
14833 | (smax:V8HI (match_operand:V8HI 1 "register_operand" "v") |
14834 | (match_operand:V8HI 2 "register_operand" "v")))] | |
0ac081f6 | 14835 | "TARGET_ALTIVEC" |
9bddde52 | 14836 | "vmaxsh %0,%1,%2" |
f18c054f | 14837 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14838 | |
f18c054f | 14839 | (define_insn "umaxv4si3" |
0ac081f6 | 14840 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
14841 | (umax:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14842 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 14843 | "TARGET_ALTIVEC" |
9bddde52 | 14844 | "vmaxuw %0,%1,%2" |
f18c054f | 14845 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14846 | |
f18c054f | 14847 | (define_insn "smaxv4si3" |
0ac081f6 | 14848 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
14849 | (smax:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14850 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 14851 | "TARGET_ALTIVEC" |
9bddde52 | 14852 | "vmaxsw %0,%1,%2" |
f18c054f | 14853 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 14854 | |
f18c054f | 14855 | (define_insn "smaxv4sf3" |
0ac081f6 | 14856 | [(set (match_operand:V4SF 0 "register_operand" "=v") |
f18c054f DB |
14857 | (smax:V4SF (match_operand:V4SF 1 "register_operand" "v") |
14858 | (match_operand:V4SF 2 "register_operand" "v")))] | |
0ac081f6 | 14859 | "TARGET_ALTIVEC" |
9bddde52 | 14860 | "vmaxfp %0,%1,%2" |
f18c054f | 14861 | [(set_attr "type" "veccmp")]) |
0ac081f6 | 14862 | |
2212663f DB |
14863 | (define_insn "altivec_vmhaddshs" |
14864 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14865 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14866 | (match_operand:V8HI 2 "register_operand" "v") | |
5f004351 AH |
14867 | (match_operand:V8HI 3 "register_operand" "v")] 71)) |
14868 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
2212663f DB |
14869 | "TARGET_ALTIVEC" |
14870 | "vmhaddshs %0, %1, %2, %3" | |
14871 | [(set_attr "type" "veccomplex")]) | |
14872 | (define_insn "altivec_vmhraddshs" | |
14873 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14874 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14875 | (match_operand:V8HI 2 "register_operand" "v") | |
5f004351 AH |
14876 | (match_operand:V8HI 3 "register_operand" "v")] 72)) |
14877 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
2212663f DB |
14878 | "TARGET_ALTIVEC" |
14879 | "vmhraddshs %0, %1, %2, %3" | |
14880 | [(set_attr "type" "veccomplex")]) | |
14881 | (define_insn "altivec_vmladduhm" | |
14882 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
14883 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
14884 | (match_operand:V8HI 2 "register_operand" "v") | |
14885 | (match_operand:V8HI 3 "register_operand" "v")] 73))] | |
14886 | "TARGET_ALTIVEC" | |
14887 | "vmladduhm %0, %1, %2, %3" | |
14888 | [(set_attr "type" "veccomplex")]) | |
14889 | ||
0ac081f6 AH |
14890 | (define_insn "altivec_vmrghb" |
14891 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
2212663f DB |
14892 | (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v") |
14893 | (parallel [(const_int 8) | |
14894 | (const_int 9) | |
14895 | (const_int 10) | |
14896 | (const_int 11) | |
14897 | (const_int 12) | |
14898 | (const_int 13) | |
14899 | (const_int 14) | |
14900 | (const_int 15) | |
14901 | (const_int 0) | |
14902 | (const_int 1) | |
14903 | (const_int 2) | |
14904 | (const_int 3) | |
14905 | (const_int 4) | |
14906 | (const_int 5) | |
14907 | (const_int 6) | |
14908 | (const_int 7)])) | |
14909 | (match_operand:V16QI 2 "register_operand" "v") | |
14910 | (const_int 255)))] | |
0ac081f6 | 14911 | "TARGET_ALTIVEC" |
9bddde52 | 14912 | "vmrghb %0,%1,%2" |
f18c054f | 14913 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14914 | |
14915 | (define_insn "altivec_vmrghh" | |
14916 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
2212663f DB |
14917 | (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v") |
14918 | (parallel [(const_int 4) | |
14919 | (const_int 5) | |
14920 | (const_int 6) | |
14921 | (const_int 7) | |
14922 | (const_int 0) | |
14923 | (const_int 1) | |
14924 | (const_int 2) | |
14925 | (const_int 3)])) | |
14926 | (match_operand:V8HI 2 "register_operand" "v") | |
14927 | (const_int 15)))] | |
0ac081f6 | 14928 | "TARGET_ALTIVEC" |
9bddde52 | 14929 | "vmrghh %0,%1,%2" |
f18c054f | 14930 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14931 | |
14932 | (define_insn "altivec_vmrghw" | |
14933 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
2212663f DB |
14934 | (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v") |
14935 | (parallel [(const_int 2) | |
14936 | (const_int 3) | |
14937 | (const_int 0) | |
14938 | (const_int 1)])) | |
14939 | (match_operand:V4SI 2 "register_operand" "v") | |
14940 | (const_int 12)))] | |
0ac081f6 | 14941 | "TARGET_ALTIVEC" |
9bddde52 | 14942 | "vmrghw %0,%1,%2" |
f18c054f | 14943 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14944 | |
14945 | (define_insn "altivec_vmrglb" | |
14946 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
2212663f | 14947 | (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v") |
a50cfd52 DE |
14948 | |
14949 | (parallel [(const_int 0) | |
2212663f DB |
14950 | (const_int 1) |
14951 | (const_int 2) | |
14952 | (const_int 3) | |
14953 | (const_int 4) | |
14954 | (const_int 5) | |
a50cfd52 DE |
14955 | (const_int 6) |
14956 | (const_int 7) | |
14957 | (const_int 8) | |
14958 | (const_int 9) | |
14959 | (const_int 10) | |
14960 | (const_int 11) | |
14961 | (const_int 12) | |
14962 | (const_int 13) | |
14963 | (const_int 14) | |
14964 | (const_int 15)])) | |
2212663f DB |
14965 | (match_operand:V16QI 1 "register_operand" "v") |
14966 | (const_int 255)))] | |
0ac081f6 | 14967 | "TARGET_ALTIVEC" |
9bddde52 | 14968 | "vmrglb %0,%1,%2" |
f18c054f | 14969 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14970 | |
14971 | (define_insn "altivec_vmrglh" | |
14972 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
2212663f | 14973 | (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v") |
a50cfd52 | 14974 | (parallel [(const_int 0) |
2212663f DB |
14975 | (const_int 1) |
14976 | (const_int 2) | |
a50cfd52 DE |
14977 | (const_int 3) |
14978 | (const_int 4) | |
14979 | (const_int 5) | |
14980 | (const_int 6) | |
14981 | (const_int 7)])) | |
2212663f DB |
14982 | (match_operand:V8HI 1 "register_operand" "v") |
14983 | (const_int 15)))] | |
0ac081f6 | 14984 | "TARGET_ALTIVEC" |
9bddde52 | 14985 | "vmrglh %0,%1,%2" |
f18c054f | 14986 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
14987 | |
14988 | (define_insn "altivec_vmrglw" | |
14989 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
2212663f | 14990 | (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v") |
a50cfd52 DE |
14991 | (parallel [(const_int 0) |
14992 | (const_int 1) | |
14993 | (const_int 2) | |
14994 | (const_int 3)])) | |
2212663f DB |
14995 | (match_operand:V4SI 1 "register_operand" "v") |
14996 | (const_int 12)))] | |
0ac081f6 | 14997 | "TARGET_ALTIVEC" |
9bddde52 | 14998 | "vmrglw %0,%1,%2" |
f18c054f | 14999 | [(set_attr "type" "vecperm")]) |
0ac081f6 | 15000 | |
f18c054f | 15001 | (define_insn "uminv16qi3" |
0ac081f6 | 15002 | [(set (match_operand:V16QI 0 "register_operand" "=v") |
f18c054f DB |
15003 | (umin:V16QI (match_operand:V16QI 1 "register_operand" "v") |
15004 | (match_operand:V16QI 2 "register_operand" "v")))] | |
0ac081f6 | 15005 | "TARGET_ALTIVEC" |
9bddde52 | 15006 | "vminub %0,%1,%2" |
f18c054f | 15007 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 15008 | |
f18c054f | 15009 | (define_insn "sminv16qi3" |
0ac081f6 | 15010 | [(set (match_operand:V16QI 0 "register_operand" "=v") |
f18c054f DB |
15011 | (smin:V16QI (match_operand:V16QI 1 "register_operand" "v") |
15012 | (match_operand:V16QI 2 "register_operand" "v")))] | |
0ac081f6 | 15013 | "TARGET_ALTIVEC" |
9bddde52 | 15014 | "vminsb %0,%1,%2" |
f18c054f | 15015 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 15016 | |
f18c054f | 15017 | (define_insn "uminv8hi3" |
0ac081f6 | 15018 | [(set (match_operand:V8HI 0 "register_operand" "=v") |
f18c054f DB |
15019 | (umin:V8HI (match_operand:V8HI 1 "register_operand" "v") |
15020 | (match_operand:V8HI 2 "register_operand" "v")))] | |
0ac081f6 | 15021 | "TARGET_ALTIVEC" |
9bddde52 | 15022 | "vminuh %0,%1,%2" |
f18c054f | 15023 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 15024 | |
f18c054f | 15025 | (define_insn "sminv8hi3" |
0ac081f6 | 15026 | [(set (match_operand:V8HI 0 "register_operand" "=v") |
f18c054f DB |
15027 | (smin:V8HI (match_operand:V8HI 1 "register_operand" "v") |
15028 | (match_operand:V8HI 2 "register_operand" "v")))] | |
0ac081f6 | 15029 | "TARGET_ALTIVEC" |
9bddde52 | 15030 | "vminsh %0,%1,%2" |
f18c054f | 15031 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 15032 | |
f18c054f | 15033 | (define_insn "uminv4si3" |
0ac081f6 | 15034 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
15035 | (umin:V4SI (match_operand:V4SI 1 "register_operand" "v") |
15036 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 15037 | "TARGET_ALTIVEC" |
9bddde52 | 15038 | "vminuw %0,%1,%2" |
f18c054f | 15039 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 15040 | |
f18c054f | 15041 | (define_insn "sminv4si3" |
0ac081f6 | 15042 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
15043 | (smin:V4SI (match_operand:V4SI 1 "register_operand" "v") |
15044 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 15045 | "TARGET_ALTIVEC" |
9bddde52 | 15046 | "vminsw %0,%1,%2" |
f18c054f | 15047 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 15048 | |
f18c054f | 15049 | (define_insn "sminv4sf3" |
0ac081f6 | 15050 | [(set (match_operand:V4SF 0 "register_operand" "=v") |
f18c054f DB |
15051 | (smin:V4SF (match_operand:V4SF 1 "register_operand" "v") |
15052 | (match_operand:V4SF 2 "register_operand" "v")))] | |
0ac081f6 | 15053 | "TARGET_ALTIVEC" |
9bddde52 | 15054 | "vminfp %0,%1,%2" |
f18c054f | 15055 | [(set_attr "type" "veccmp")]) |
0ac081f6 AH |
15056 | |
15057 | (define_insn "altivec_vmuleub" | |
15058 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15059 | (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") | |
15060 | (match_operand:V16QI 2 "register_operand" "v")] 83))] | |
15061 | "TARGET_ALTIVEC" | |
9bddde52 | 15062 | "vmuleub %0,%1,%2" |
f18c054f | 15063 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15064 | |
15065 | (define_insn "altivec_vmulesb" | |
15066 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15067 | (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") | |
15068 | (match_operand:V16QI 2 "register_operand" "v")] 84))] | |
15069 | "TARGET_ALTIVEC" | |
9bddde52 | 15070 | "vmulesb %0,%1,%2" |
f18c054f | 15071 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15072 | |
15073 | (define_insn "altivec_vmuleuh" | |
15074 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15075 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
15076 | (match_operand:V8HI 2 "register_operand" "v")] 85))] | |
15077 | "TARGET_ALTIVEC" | |
9bddde52 | 15078 | "vmuleuh %0,%1,%2" |
f18c054f | 15079 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15080 | |
15081 | (define_insn "altivec_vmulesh" | |
15082 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15083 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
15084 | (match_operand:V8HI 2 "register_operand" "v")] 86))] | |
15085 | "TARGET_ALTIVEC" | |
9bddde52 | 15086 | "vmulesh %0,%1,%2" |
f18c054f | 15087 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15088 | |
15089 | (define_insn "altivec_vmuloub" | |
15090 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15091 | (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") | |
15092 | (match_operand:V16QI 2 "register_operand" "v")] 87))] | |
15093 | "TARGET_ALTIVEC" | |
9bddde52 | 15094 | "vmuloub %0,%1,%2" |
f18c054f | 15095 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15096 | |
15097 | (define_insn "altivec_vmulosb" | |
15098 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15099 | (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") | |
15100 | (match_operand:V16QI 2 "register_operand" "v")] 88))] | |
15101 | "TARGET_ALTIVEC" | |
9bddde52 | 15102 | "vmulosb %0,%1,%2" |
f18c054f | 15103 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15104 | |
15105 | (define_insn "altivec_vmulouh" | |
15106 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15107 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
15108 | (match_operand:V8HI 2 "register_operand" "v")] 89))] | |
15109 | "TARGET_ALTIVEC" | |
9bddde52 | 15110 | "vmulouh %0,%1,%2" |
f18c054f | 15111 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15112 | |
15113 | (define_insn "altivec_vmulosh" | |
15114 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15115 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
15116 | (match_operand:V8HI 2 "register_operand" "v")] 90))] | |
15117 | "TARGET_ALTIVEC" | |
9bddde52 | 15118 | "vmulosh %0,%1,%2" |
f18c054f | 15119 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15120 | |
15121 | (define_insn "altivec_vnor" | |
15122 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
f18c054f DB |
15123 | (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v") |
15124 | (match_operand:V4SI 2 "register_operand" "v"))))] | |
0ac081f6 | 15125 | "TARGET_ALTIVEC" |
9bddde52 | 15126 | "vnor %0,%1,%2" |
f18c054f | 15127 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 15128 | |
f18c054f | 15129 | (define_insn "iorv4si3" |
0ac081f6 | 15130 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
15131 | (ior:V4SI (match_operand:V4SI 1 "register_operand" "v") |
15132 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 15133 | "TARGET_ALTIVEC" |
9bddde52 | 15134 | "vor %0,%1,%2" |
f18c054f | 15135 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15136 | |
15137 | (define_insn "altivec_vpkuhum" | |
15138 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15139 | (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") | |
15140 | (match_operand:V8HI 2 "register_operand" "v")] 93))] | |
15141 | "TARGET_ALTIVEC" | |
9bddde52 | 15142 | "vpkuhum %0,%1,%2" |
f18c054f | 15143 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
15144 | |
15145 | (define_insn "altivec_vpkuwum" | |
15146 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15147 | (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") | |
15148 | (match_operand:V4SI 2 "register_operand" "v")] 94))] | |
15149 | "TARGET_ALTIVEC" | |
9bddde52 | 15150 | "vpkuwum %0,%1,%2" |
f18c054f | 15151 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
15152 | |
15153 | (define_insn "altivec_vpkpx" | |
15154 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15155 | (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") | |
15156 | (match_operand:V4SI 2 "register_operand" "v")] 95))] | |
15157 | "TARGET_ALTIVEC" | |
9bddde52 | 15158 | "vpkpx %0,%1,%2" |
f18c054f | 15159 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
15160 | |
15161 | (define_insn "altivec_vpkuhss" | |
15162 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15163 | (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") | |
5f004351 AH |
15164 | (match_operand:V8HI 2 "register_operand" "v")] 96)) |
15165 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15166 | "TARGET_ALTIVEC" |
9bddde52 | 15167 | "vpkuhss %0,%1,%2" |
f18c054f | 15168 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
15169 | |
15170 | (define_insn "altivec_vpkshss" | |
15171 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15172 | (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") | |
5f004351 AH |
15173 | (match_operand:V8HI 2 "register_operand" "v")] 97)) |
15174 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15175 | "TARGET_ALTIVEC" |
9bddde52 | 15176 | "vpkshss %0,%1,%2" |
f18c054f | 15177 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
15178 | |
15179 | (define_insn "altivec_vpkuwss" | |
15180 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15181 | (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") | |
5f004351 AH |
15182 | (match_operand:V4SI 2 "register_operand" "v")] 98)) |
15183 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15184 | "TARGET_ALTIVEC" |
9bddde52 | 15185 | "vpkuwss %0,%1,%2" |
f18c054f | 15186 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
15187 | |
15188 | (define_insn "altivec_vpkswss" | |
15189 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15190 | (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") | |
5f004351 AH |
15191 | (match_operand:V4SI 2 "register_operand" "v")] 99)) |
15192 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15193 | "TARGET_ALTIVEC" |
9bddde52 | 15194 | "vpkswss %0,%1,%2" |
f18c054f | 15195 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
15196 | |
15197 | (define_insn "altivec_vpkuhus" | |
15198 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15199 | (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") | |
5f004351 AH |
15200 | (match_operand:V8HI 2 "register_operand" "v")] 100)) |
15201 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15202 | "TARGET_ALTIVEC" |
9bddde52 | 15203 | "vpkuhus %0,%1,%2" |
f18c054f | 15204 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
15205 | |
15206 | (define_insn "altivec_vpkshus" | |
15207 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15208 | (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") | |
5f004351 AH |
15209 | (match_operand:V8HI 2 "register_operand" "v")] 101)) |
15210 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15211 | "TARGET_ALTIVEC" |
9bddde52 | 15212 | "vpkshus %0,%1,%2" |
f18c054f | 15213 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
15214 | |
15215 | (define_insn "altivec_vpkuwus" | |
15216 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15217 | (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") | |
5f004351 AH |
15218 | (match_operand:V4SI 2 "register_operand" "v")] 102)) |
15219 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15220 | "TARGET_ALTIVEC" |
9bddde52 | 15221 | "vpkuwus %0,%1,%2" |
f18c054f | 15222 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
15223 | |
15224 | (define_insn "altivec_vpkswus" | |
15225 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15226 | (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") | |
5f004351 AH |
15227 | (match_operand:V4SI 2 "register_operand" "v")] 103)) |
15228 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15229 | "TARGET_ALTIVEC" |
9bddde52 | 15230 | "vpkswus %0,%1,%2" |
f18c054f | 15231 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
15232 | |
15233 | (define_insn "altivec_vrlb" | |
15234 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15235 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
15236 | (match_operand:V16QI 2 "register_operand" "v")] 104))] | |
15237 | "TARGET_ALTIVEC" | |
9bddde52 | 15238 | "vrlb %0,%1,%2" |
f18c054f | 15239 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15240 | |
15241 | (define_insn "altivec_vrlh" | |
15242 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15243 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
15244 | (match_operand:V8HI 2 "register_operand" "v")] 105))] | |
15245 | "TARGET_ALTIVEC" | |
9bddde52 | 15246 | "vrlh %0,%1,%2" |
f18c054f | 15247 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15248 | |
15249 | (define_insn "altivec_vrlw" | |
15250 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15251 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15252 | (match_operand:V4SI 2 "register_operand" "v")] 106))] | |
15253 | "TARGET_ALTIVEC" | |
9bddde52 | 15254 | "vrlw %0,%1,%2" |
f18c054f | 15255 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15256 | |
15257 | (define_insn "altivec_vslb" | |
15258 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15259 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
15260 | (match_operand:V16QI 2 "register_operand" "v")] 107))] | |
15261 | "TARGET_ALTIVEC" | |
9bddde52 | 15262 | "vslb %0,%1,%2" |
f18c054f | 15263 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15264 | |
15265 | (define_insn "altivec_vslh" | |
15266 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15267 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
15268 | (match_operand:V8HI 2 "register_operand" "v")] 108))] | |
15269 | "TARGET_ALTIVEC" | |
9bddde52 | 15270 | "vslh %0,%1,%2" |
f18c054f | 15271 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15272 | |
15273 | (define_insn "altivec_vslw" | |
15274 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15275 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15276 | (match_operand:V4SI 2 "register_operand" "v")] 109))] | |
15277 | "TARGET_ALTIVEC" | |
9bddde52 | 15278 | "vslw %0,%1,%2" |
f18c054f | 15279 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15280 | |
15281 | (define_insn "altivec_vsl" | |
15282 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15283 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15284 | (match_operand:V4SI 2 "register_operand" "v")] 110))] | |
15285 | "TARGET_ALTIVEC" | |
9bddde52 | 15286 | "vsl %0,%1,%2" |
f18c054f | 15287 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
15288 | |
15289 | (define_insn "altivec_vslo" | |
15290 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15291 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15292 | (match_operand:V4SI 2 "register_operand" "v")] 111))] | |
15293 | "TARGET_ALTIVEC" | |
9bddde52 | 15294 | "vslo %0,%1,%2" |
f18c054f | 15295 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
15296 | |
15297 | (define_insn "altivec_vsrb" | |
15298 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15299 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
15300 | (match_operand:V16QI 2 "register_operand" "v")] 112))] | |
15301 | "TARGET_ALTIVEC" | |
9bddde52 | 15302 | "vsrb %0,%1,%2" |
f18c054f | 15303 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 15304 | |
f18c054f | 15305 | (define_insn "altivec_vsrh" |
0ac081f6 AH |
15306 | [(set (match_operand:V8HI 0 "register_operand" "=v") |
15307 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
15308 | (match_operand:V8HI 2 "register_operand" "v")] 113))] | |
15309 | "TARGET_ALTIVEC" | |
f18c054f DB |
15310 | "vsrh %0,%1,%2" |
15311 | [(set_attr "type" "vecsimple")]) | |
0ac081f6 | 15312 | |
f18c054f | 15313 | (define_insn "altivec_vsrw" |
0ac081f6 AH |
15314 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
15315 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15316 | (match_operand:V4SI 2 "register_operand" "v")] 114))] | |
15317 | "TARGET_ALTIVEC" | |
f18c054f DB |
15318 | "vsrw %0,%1,%2" |
15319 | [(set_attr "type" "vecsimple")]) | |
0ac081f6 AH |
15320 | |
15321 | (define_insn "altivec_vsrab" | |
15322 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15323 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
15324 | (match_operand:V16QI 2 "register_operand" "v")] 115))] | |
15325 | "TARGET_ALTIVEC" | |
9bddde52 | 15326 | "vsrab %0,%1,%2" |
f18c054f | 15327 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15328 | |
15329 | (define_insn "altivec_vsrah" | |
15330 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15331 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
15332 | (match_operand:V8HI 2 "register_operand" "v")] 116))] | |
15333 | "TARGET_ALTIVEC" | |
9bddde52 | 15334 | "vsrah %0,%1,%2" |
f18c054f | 15335 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15336 | |
15337 | (define_insn "altivec_vsraw" | |
15338 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15339 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15340 | (match_operand:V4SI 2 "register_operand" "v")] 117))] | |
15341 | "TARGET_ALTIVEC" | |
9bddde52 | 15342 | "vsraw %0,%1,%2" |
f18c054f | 15343 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15344 | |
15345 | (define_insn "altivec_vsr" | |
15346 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15347 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15348 | (match_operand:V4SI 2 "register_operand" "v")] 118))] | |
15349 | "TARGET_ALTIVEC" | |
9bddde52 | 15350 | "vsr %0,%1,%2" |
f18c054f | 15351 | [(set_attr "type" "vecperm")]) |
0ac081f6 AH |
15352 | |
15353 | (define_insn "altivec_vsro" | |
15354 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15355 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15356 | (match_operand:V4SI 2 "register_operand" "v")] 119))] | |
15357 | "TARGET_ALTIVEC" | |
9bddde52 | 15358 | "vsro %0,%1,%2" |
f18c054f | 15359 | [(set_attr "type" "vecperm")]) |
0ac081f6 | 15360 | |
f18c054f | 15361 | (define_insn "subv16qi3" |
0ac081f6 | 15362 | [(set (match_operand:V16QI 0 "register_operand" "=v") |
f18c054f DB |
15363 | (minus:V16QI (match_operand:V16QI 1 "register_operand" "v") |
15364 | (match_operand:V16QI 2 "register_operand" "v")))] | |
0ac081f6 | 15365 | "TARGET_ALTIVEC" |
9bddde52 | 15366 | "vsububm %0,%1,%2" |
f18c054f | 15367 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 15368 | |
f18c054f | 15369 | (define_insn "subv8hi3" |
0ac081f6 | 15370 | [(set (match_operand:V8HI 0 "register_operand" "=v") |
f18c054f DB |
15371 | (minus:V8HI (match_operand:V8HI 1 "register_operand" "v") |
15372 | (match_operand:V8HI 2 "register_operand" "v")))] | |
0ac081f6 | 15373 | "TARGET_ALTIVEC" |
9bddde52 | 15374 | "vsubuhm %0,%1,%2" |
f18c054f | 15375 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 15376 | |
f18c054f | 15377 | (define_insn "subv4si3" |
0ac081f6 | 15378 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
15379 | (minus:V4SI (match_operand:V4SI 1 "register_operand" "v") |
15380 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 15381 | "TARGET_ALTIVEC" |
9bddde52 | 15382 | "vsubuwm %0,%1,%2" |
f18c054f | 15383 | [(set_attr "type" "vecsimple")]) |
0ac081f6 | 15384 | |
f18c054f | 15385 | (define_insn "subv4sf3" |
0ac081f6 | 15386 | [(set (match_operand:V4SF 0 "register_operand" "=v") |
f18c054f DB |
15387 | (minus:V4SF (match_operand:V4SF 1 "register_operand" "v") |
15388 | (match_operand:V4SF 2 "register_operand" "v")))] | |
0ac081f6 | 15389 | "TARGET_ALTIVEC" |
9bddde52 | 15390 | "vsubfp %0,%1,%2" |
f18c054f | 15391 | [(set_attr "type" "vecfloat")]) |
0ac081f6 AH |
15392 | |
15393 | (define_insn "altivec_vsubcuw" | |
15394 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15395 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15396 | (match_operand:V4SI 2 "register_operand" "v")] 124))] | |
15397 | "TARGET_ALTIVEC" | |
9bddde52 | 15398 | "vsubcuw %0,%1,%2" |
f18c054f | 15399 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15400 | |
15401 | (define_insn "altivec_vsububs" | |
15402 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15403 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
5f004351 AH |
15404 | (match_operand:V16QI 2 "register_operand" "v")] 125)) |
15405 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15406 | "TARGET_ALTIVEC" |
9bddde52 | 15407 | "vsububs %0,%1,%2" |
f18c054f | 15408 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15409 | |
15410 | (define_insn "altivec_vsubsbs" | |
15411 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15412 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
5f004351 AH |
15413 | (match_operand:V16QI 2 "register_operand" "v")] 126)) |
15414 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15415 | "TARGET_ALTIVEC" |
9bddde52 | 15416 | "vsubsbs %0,%1,%2" |
f18c054f | 15417 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15418 | |
15419 | (define_insn "altivec_vsubuhs" | |
15420 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15421 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
5f004351 AH |
15422 | (match_operand:V8HI 2 "register_operand" "v")] 127)) |
15423 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15424 | "TARGET_ALTIVEC" |
9bddde52 | 15425 | "vsubuhs %0,%1,%2" |
f18c054f | 15426 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15427 | |
15428 | (define_insn "altivec_vsubshs" | |
15429 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15430 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
5f004351 AH |
15431 | (match_operand:V8HI 2 "register_operand" "v")] 128)) |
15432 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15433 | "TARGET_ALTIVEC" |
9bddde52 | 15434 | "vsubshs %0,%1,%2" |
f18c054f | 15435 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15436 | |
15437 | (define_insn "altivec_vsubuws" | |
15438 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15439 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
5f004351 AH |
15440 | (match_operand:V4SI 2 "register_operand" "v")] 129)) |
15441 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15442 | "TARGET_ALTIVEC" |
9bddde52 | 15443 | "vsubuws %0,%1,%2" |
f18c054f | 15444 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15445 | |
15446 | (define_insn "altivec_vsubsws" | |
15447 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15448 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
5f004351 AH |
15449 | (match_operand:V4SI 2 "register_operand" "v")] 130)) |
15450 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15451 | "TARGET_ALTIVEC" |
9bddde52 | 15452 | "vsubsws %0,%1,%2" |
f18c054f | 15453 | [(set_attr "type" "vecsimple")]) |
0ac081f6 AH |
15454 | |
15455 | (define_insn "altivec_vsum4ubs" | |
15456 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15457 | (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") | |
5f004351 AH |
15458 | (match_operand:V4SI 2 "register_operand" "v")] 131)) |
15459 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15460 | "TARGET_ALTIVEC" |
9bddde52 | 15461 | "vsum4ubs %0,%1,%2" |
f18c054f | 15462 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15463 | |
15464 | (define_insn "altivec_vsum4sbs" | |
15465 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15466 | (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") | |
5f004351 AH |
15467 | (match_operand:V4SI 2 "register_operand" "v")] 132)) |
15468 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15469 | "TARGET_ALTIVEC" |
9bddde52 | 15470 | "vsum4sbs %0,%1,%2" |
f18c054f | 15471 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15472 | |
15473 | (define_insn "altivec_vsum4shs" | |
15474 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15475 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") | |
5f004351 AH |
15476 | (match_operand:V4SI 2 "register_operand" "v")] 133)) |
15477 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15478 | "TARGET_ALTIVEC" |
9bddde52 | 15479 | "vsum4shs %0,%1,%2" |
f18c054f | 15480 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15481 | |
15482 | (define_insn "altivec_vsum2sws" | |
15483 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15484 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
5f004351 AH |
15485 | (match_operand:V4SI 2 "register_operand" "v")] 134)) |
15486 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15487 | "TARGET_ALTIVEC" |
9bddde52 | 15488 | "vsum2sws %0,%1,%2" |
f18c054f | 15489 | [(set_attr "type" "veccomplex")]) |
0ac081f6 AH |
15490 | |
15491 | (define_insn "altivec_vsumsws" | |
15492 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15493 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
5f004351 AH |
15494 | (match_operand:V4SI 2 "register_operand" "v")] 135)) |
15495 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
0ac081f6 | 15496 | "TARGET_ALTIVEC" |
9bddde52 | 15497 | "vsumsws %0,%1,%2" |
f18c054f | 15498 | [(set_attr "type" "veccomplex")]) |
0ac081f6 | 15499 | |
f18c054f | 15500 | (define_insn "xorv4si3" |
0ac081f6 | 15501 | [(set (match_operand:V4SI 0 "register_operand" "=v") |
f18c054f DB |
15502 | (xor:V4SI (match_operand:V4SI 1 "register_operand" "v") |
15503 | (match_operand:V4SI 2 "register_operand" "v")))] | |
0ac081f6 | 15504 | "TARGET_ALTIVEC" |
9bddde52 | 15505 | "vxor %0,%1,%2" |
f18c054f | 15506 | [(set_attr "type" "vecsimple")]) |
2212663f DB |
15507 | |
15508 | (define_insn "altivec_vspltb" | |
15509 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15510 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
15511 | (match_operand:QI 2 "immediate_operand" "i")] 136))] | |
15512 | "TARGET_ALTIVEC" | |
15513 | "vspltb %0,%1,%2" | |
15514 | [(set_attr "type" "vecperm")]) | |
100c4561 | 15515 | |
2212663f DB |
15516 | (define_insn "altivec_vsplth" |
15517 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15518 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
15519 | (match_operand:QI 2 "immediate_operand" "i")] 137))] | |
15520 | "TARGET_ALTIVEC" | |
15521 | "vsplth %0,%1,%2" | |
15522 | [(set_attr "type" "vecperm")]) | |
15523 | ||
15524 | (define_insn "altivec_vspltw" | |
15525 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15526 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15527 | (match_operand:QI 2 "immediate_operand" "i")] 138))] | |
15528 | "TARGET_ALTIVEC" | |
15529 | "vspltw %0,%1,%2" | |
15530 | [(set_attr "type" "vecperm")]) | |
15531 | ||
15532 | (define_insn "altivec_vspltisb" | |
15533 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15534 | (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")] 139))] | |
15535 | "TARGET_ALTIVEC" | |
15536 | "vspltisb %0, %1" | |
15537 | [(set_attr "type" "vecsimple")]) | |
15538 | ||
15539 | ||
15540 | (define_insn "altivec_vspltish" | |
15541 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15542 | (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")] 140))] | |
15543 | "TARGET_ALTIVEC" | |
15544 | "vspltish %0, %1" | |
15545 | [(set_attr "type" "vecsimple")]) | |
15546 | ||
15547 | (define_insn "altivec_vspltisw" | |
15548 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15549 | (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")] 141))] | |
15550 | "TARGET_ALTIVEC" | |
15551 | "vspltisw %0, %1" | |
15552 | [(set_attr "type" "vecsimple")]) | |
15553 | ||
15554 | (define_insn "" | |
15555 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15556 | (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))] | |
15557 | "TARGET_ALTIVEC" | |
15558 | "vspltisw %0, %1" | |
15559 | [(set_attr "type" "vecsimple")]) | |
15560 | ||
15561 | (define_insn "ftruncv4sf2" | |
617e0e1d DB |
15562 | [(set (match_operand:V4SF 0 "register_operand" "=v") |
15563 | (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))] | |
15564 | "TARGET_ALTIVEC" | |
15565 | "vrfiz %0, %1" | |
15566 | [(set_attr "type" "vecfloat")]) | |
2212663f DB |
15567 | |
15568 | (define_insn "altivec_vperm_4si" | |
15569 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15570 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15571 | (match_operand:V4SI 2 "register_operand" "v") | |
15572 | (match_operand:V16QI 3 "register_operand" "v")] 144))] | |
15573 | "TARGET_ALTIVEC" | |
15574 | "vperm %0,%1,%2,%3" | |
15575 | [(set_attr "type" "vecperm")]) | |
15576 | ||
15577 | (define_insn "altivec_vperm_4sf" | |
15578 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15579 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") | |
15580 | (match_operand:V4SF 2 "register_operand" "v") | |
15581 | (match_operand:V16QI 3 "register_operand" "v")] 145))] | |
15582 | "TARGET_ALTIVEC" | |
15583 | "vperm %0,%1,%2,%3" | |
15584 | [(set_attr "type" "vecperm")]) | |
15585 | ||
15586 | (define_insn "altivec_vperm_8hi" | |
15587 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15588 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
15589 | (match_operand:V8HI 2 "register_operand" "v") | |
15590 | (match_operand:V16QI 3 "register_operand" "v")] 146))] | |
15591 | "TARGET_ALTIVEC" | |
15592 | "vperm %0,%1,%2,%3" | |
15593 | [(set_attr "type" "vecperm")]) | |
15594 | ||
15595 | (define_insn "altivec_vperm_16qi" | |
15596 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15597 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
15598 | (match_operand:V16QI 2 "register_operand" "v") | |
15599 | (match_operand:V16QI 3 "register_operand" "v")] 147))] | |
15600 | "TARGET_ALTIVEC" | |
15601 | "vperm %0,%1,%2,%3" | |
15602 | [(set_attr "type" "vecperm")]) | |
617e0e1d DB |
15603 | |
15604 | (define_insn "altivec_vrfip" | |
15605 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15606 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))] | |
15607 | "TARGET_ALTIVEC" | |
15608 | "vrfip %0, %1" | |
15609 | [(set_attr "type" "vecfloat")]) | |
15610 | ||
15611 | (define_insn "altivec_vrfin" | |
15612 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15613 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))] | |
15614 | "TARGET_ALTIVEC" | |
15615 | "vrfin %0, %1" | |
15616 | [(set_attr "type" "vecfloat")]) | |
15617 | ||
15618 | (define_insn "altivec_vrfim" | |
15619 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15620 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))] | |
15621 | "TARGET_ALTIVEC" | |
15622 | "vrfim %0, %1" | |
15623 | [(set_attr "type" "vecfloat")]) | |
15624 | ||
15625 | (define_insn "altivec_vcfux" | |
15626 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15627 | (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") | |
15628 | (match_operand:QI 2 "immediate_operand" "i")] 151))] | |
15629 | "TARGET_ALTIVEC" | |
15630 | "vcfux %0, %1, %2" | |
15631 | [(set_attr "type" "vecfloat")]) | |
15632 | ||
15633 | (define_insn "altivec_vcfsx" | |
15634 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15635 | (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") | |
15636 | (match_operand:QI 2 "immediate_operand" "i")] 152))] | |
15637 | "TARGET_ALTIVEC" | |
15638 | "vcfsx %0, %1, %2" | |
15639 | [(set_attr "type" "vecfloat")]) | |
15640 | ||
15641 | (define_insn "altivec_vctuxs" | |
15642 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15643 | (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") | |
5f004351 AH |
15644 | (match_operand:QI 2 "immediate_operand" "i")] 153)) |
15645 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
617e0e1d | 15646 | "TARGET_ALTIVEC" |
95385cbb | 15647 | "vctuxs %0, %1, %2" |
617e0e1d DB |
15648 | [(set_attr "type" "vecfloat")]) |
15649 | ||
15650 | (define_insn "altivec_vctsxs" | |
15651 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15652 | (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") | |
5f004351 AH |
15653 | (match_operand:QI 2 "immediate_operand" "i")] 154)) |
15654 | (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] | |
617e0e1d DB |
15655 | "TARGET_ALTIVEC" |
15656 | "vctsxs %0, %1, %2" | |
15657 | [(set_attr "type" "vecfloat")]) | |
15658 | ||
15659 | (define_insn "altivec_vlogefp" | |
15660 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15661 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))] | |
15662 | "TARGET_ALTIVEC" | |
15663 | "vlogefp %0, %1" | |
15664 | [(set_attr "type" "vecfloat")]) | |
15665 | ||
15666 | (define_insn "altivec_vexptefp" | |
15667 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15668 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))] | |
15669 | "TARGET_ALTIVEC" | |
15670 | "vexptefp %0, %1" | |
15671 | [(set_attr "type" "vecfloat")]) | |
15672 | ||
15673 | (define_insn "altivec_vrsqrtefp" | |
15674 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15675 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))] | |
15676 | "TARGET_ALTIVEC" | |
15677 | "vrsqrtefp %0, %1" | |
15678 | [(set_attr "type" "vecfloat")]) | |
15679 | ||
15680 | (define_insn "altivec_vrefp" | |
15681 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15682 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))] | |
15683 | "TARGET_ALTIVEC" | |
15684 | "vrefp %0, %1" | |
15685 | [(set_attr "type" "vecfloat")]) | |
15686 | ||
15687 | (define_insn "altivec_vsel_4si" | |
15688 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15689 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15690 | (match_operand:V4SI 2 "register_operand" "v") | |
15691 | (match_operand:V4SI 3 "register_operand" "v")] 159))] | |
15692 | "TARGET_ALTIVEC" | |
15693 | "vsel %0,%1,%2,%3" | |
15694 | [(set_attr "type" "vecperm")]) | |
15695 | ||
15696 | (define_insn "altivec_vsel_4sf" | |
15697 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15698 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") | |
15699 | (match_operand:V4SF 2 "register_operand" "v") | |
15700 | (match_operand:V4SI 3 "register_operand" "v")] 160))] | |
15701 | "TARGET_ALTIVEC" | |
15702 | "vsel %0,%1,%2,%3" | |
15703 | [(set_attr "type" "vecperm")]) | |
15704 | ||
15705 | (define_insn "altivec_vsel_8hi" | |
15706 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15707 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
15708 | (match_operand:V8HI 2 "register_operand" "v") | |
15709 | (match_operand:V8HI 3 "register_operand" "v")] 161))] | |
15710 | "TARGET_ALTIVEC" | |
15711 | "vsel %0,%1,%2,%3" | |
15712 | [(set_attr "type" "vecperm")]) | |
15713 | ||
15714 | (define_insn "altivec_vsel_16qi" | |
15715 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15716 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
15717 | (match_operand:V16QI 2 "register_operand" "v") | |
15718 | (match_operand:V16QI 3 "register_operand" "v")] 162))] | |
15719 | "TARGET_ALTIVEC" | |
15720 | "vsel %0,%1,%2,%3" | |
15721 | [(set_attr "type" "vecperm")]) | |
15722 | ||
24408032 AH |
15723 | (define_insn "altivec_vsldoi_4si" |
15724 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15725 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") | |
15726 | (match_operand:V4SI 2 "register_operand" "v") | |
15727 | (match_operand:QI 3 "immediate_operand" "i")] 163))] | |
15728 | "TARGET_ALTIVEC" | |
15729 | "vsldoi %0, %1, %2, %3" | |
15730 | [(set_attr "type" "vecperm")]) | |
15731 | ||
15732 | (define_insn "altivec_vsldoi_4sf" | |
15733 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
15734 | (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") | |
15735 | (match_operand:V4SF 2 "register_operand" "v") | |
15736 | (match_operand:QI 3 "immediate_operand" "i")] 164))] | |
15737 | "TARGET_ALTIVEC" | |
15738 | "vsldoi %0, %1, %2, %3" | |
15739 | [(set_attr "type" "vecperm")]) | |
617e0e1d | 15740 | |
24408032 AH |
15741 | (define_insn "altivec_vsldoi_8hi" |
15742 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15743 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") | |
15744 | (match_operand:V8HI 2 "register_operand" "v") | |
15745 | (match_operand:QI 3 "immediate_operand" "i")] 165))] | |
15746 | "TARGET_ALTIVEC" | |
15747 | "vsldoi %0, %1, %2, %3" | |
15748 | [(set_attr "type" "vecperm")]) | |
15749 | ||
15750 | (define_insn "altivec_vsldoi_16qi" | |
15751 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15752 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") | |
15753 | (match_operand:V16QI 2 "register_operand" "v") | |
15754 | (match_operand:QI 3 "immediate_operand" "i")] 166))] | |
15755 | "TARGET_ALTIVEC" | |
15756 | "vsldoi %0, %1, %2, %3" | |
15757 | [(set_attr "type" "vecperm")]) | |
20e26713 AH |
15758 | |
15759 | (define_insn "altivec_vupkhsb" | |
15760 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15761 | (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))] | |
15762 | "TARGET_ALTIVEC" | |
15763 | "vupkhsb %0, %1" | |
15764 | [(set_attr "type" "vecperm")]) | |
15765 | ||
15766 | (define_insn "altivec_vupkhpx" | |
15767 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15768 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))] | |
15769 | "TARGET_ALTIVEC" | |
15770 | "vupkhpx %0, %1" | |
15771 | [(set_attr "type" "vecperm")]) | |
15772 | ||
15773 | (define_insn "altivec_vupkhsh" | |
15774 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15775 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))] | |
15776 | "TARGET_ALTIVEC" | |
15777 | "vupkhsh %0, %1" | |
15778 | [(set_attr "type" "vecperm")]) | |
15779 | ||
15780 | (define_insn "altivec_vupklsb" | |
15781 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15782 | (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))] | |
15783 | "TARGET_ALTIVEC" | |
15784 | "vupklsb %0, %1" | |
15785 | [(set_attr "type" "vecperm")]) | |
15786 | ||
15787 | (define_insn "altivec_vupklpx" | |
15788 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15789 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))] | |
15790 | "TARGET_ALTIVEC" | |
15791 | "vupklpx %0, %1" | |
15792 | [(set_attr "type" "vecperm")]) | |
15793 | ||
15794 | (define_insn "altivec_vupklsh" | |
15795 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15796 | (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))] | |
15797 | "TARGET_ALTIVEC" | |
15798 | "vupklsh %0, %1" | |
15799 | [(set_attr "type" "vecperm")]) | |
fa066a23 AH |
15800 | |
15801 | ;; AltiVec predicates. | |
15802 | ||
ae4b4a02 AH |
15803 | (define_expand "cr6_test_for_zero" |
15804 | [(set (match_operand:SI 0 "register_operand" "=r") | |
15805 | (eq:SI (reg:CC 74) | |
15806 | (const_int 0)))] | |
fa066a23 | 15807 | "TARGET_ALTIVEC" |
768070a0 | 15808 | "") |
fa066a23 | 15809 | |
ae4b4a02 AH |
15810 | (define_expand "cr6_test_for_zero_reverse" |
15811 | [(set (match_operand:SI 0 "register_operand" "=r") | |
15812 | (eq:SI (reg:CC 74) | |
15813 | (const_int 0))) | |
15814 | (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))] | |
fa066a23 | 15815 | "TARGET_ALTIVEC" |
ae4b4a02 | 15816 | "") |
fa066a23 | 15817 | |
ae4b4a02 AH |
15818 | (define_expand "cr6_test_for_lt" |
15819 | [(set (match_operand:SI 0 "register_operand" "=r") | |
15820 | (lt:SI (reg:CC 74) | |
15821 | (const_int 0)))] | |
fa066a23 | 15822 | "TARGET_ALTIVEC" |
ae4b4a02 | 15823 | "") |
fa066a23 | 15824 | |
ae4b4a02 AH |
15825 | (define_expand "cr6_test_for_lt_reverse" |
15826 | [(set (match_operand:SI 0 "register_operand" "=r") | |
15827 | (lt:SI (reg:CC 74) | |
15828 | (const_int 0))) | |
15829 | (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))] | |
fa066a23 | 15830 | "TARGET_ALTIVEC" |
ae4b4a02 | 15831 | "") |
fa066a23 | 15832 | |
ae4b4a02 AH |
15833 | ;; We can get away with generating the opcode on the fly (%3 below) |
15834 | ;; because all the predicates have the same scheduling parameters. | |
fa066a23 | 15835 | |
ae4b4a02 AH |
15836 | (define_insn "altivec_predicate_v4si" |
15837 | [(set (reg:CC 74) | |
15838 | (unspec:CC [(match_operand:V4SI 1 "register_operand" "v") | |
15839 | (match_operand:V4SI 2 "register_operand" "v") | |
15840 | (match_operand 3 "any_operand" "")] 173)) | |
15841 | (clobber (match_scratch:V4SI 0 "=v"))] | |
fa066a23 | 15842 | "TARGET_ALTIVEC" |
ae4b4a02 | 15843 | "%3 %0,%1,%2" |
fa066a23 AH |
15844 | [(set_attr "type" "veccmp")]) |
15845 | ||
ae4b4a02 AH |
15846 | (define_insn "altivec_predicate_v4sf" |
15847 | [(set (reg:CC 74) | |
15848 | (unspec:CC [(match_operand:V4SF 1 "register_operand" "v") | |
15849 | (match_operand:V4SF 2 "register_operand" "v") | |
15850 | (match_operand 3 "any_operand" "")] 174)) | |
15851 | (clobber (match_scratch:V4SF 0 "=v"))] | |
fa066a23 | 15852 | "TARGET_ALTIVEC" |
ae4b4a02 | 15853 | "%3 %0,%1,%2" |
fa066a23 AH |
15854 | [(set_attr "type" "veccmp")]) |
15855 | ||
ae4b4a02 AH |
15856 | (define_insn "altivec_predicate_v8hi" |
15857 | [(set (reg:CC 74) | |
15858 | (unspec:CC [(match_operand:V8HI 1 "register_operand" "v") | |
15859 | (match_operand:V8HI 2 "register_operand" "v") | |
15860 | (match_operand 3 "any_operand" "")] 175)) | |
15861 | (clobber (match_scratch:V8HI 0 "=v"))] | |
fa066a23 | 15862 | "TARGET_ALTIVEC" |
ae4b4a02 | 15863 | "%3 %0,%1,%2" |
fa066a23 AH |
15864 | [(set_attr "type" "veccmp")]) |
15865 | ||
ae4b4a02 AH |
15866 | (define_insn "altivec_predicate_v16qi" |
15867 | [(set (reg:CC 74) | |
15868 | (unspec:CC [(match_operand:V16QI 1 "register_operand" "v") | |
15869 | (match_operand:V16QI 2 "register_operand" "v") | |
15870 | (match_operand 3 "any_operand" "")] 175)) | |
15871 | (clobber (match_scratch:V16QI 0 "=v"))] | |
fa066a23 | 15872 | "TARGET_ALTIVEC" |
ae4b4a02 | 15873 | "%3 %0,%1,%2" |
fa066a23 AH |
15874 | [(set_attr "type" "veccmp")]) |
15875 | ||
95385cbb | 15876 | (define_insn "altivec_mtvscr" |
5f004351 AH |
15877 | [(set (reg:SI 110) |
15878 | (unspec_volatile:SI | |
15879 | [(match_operand:V4SI 0 "register_operand" "v")] 186))] | |
95385cbb AH |
15880 | "TARGET_ALTIVEC" |
15881 | "mtvscr %0" | |
15882 | [(set_attr "type" "vecsimple")]) | |
15883 | ||
15884 | (define_insn "altivec_mfvscr" | |
15885 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
5f004351 | 15886 | (unspec_volatile:V8HI [(reg:SI 110)] 187))] |
95385cbb AH |
15887 | "TARGET_ALTIVEC" |
15888 | "mfvscr %0" | |
15889 | [(set_attr "type" "vecsimple")]) | |
15890 | ||
15891 | (define_insn "altivec_dssall" | |
15892 | [(unspec [(const_int 0)] 188)] | |
15893 | "TARGET_ALTIVEC" | |
15894 | "dssall" | |
15895 | [(set_attr "type" "vecsimple")]) | |
15896 | ||
15897 | (define_insn "altivec_dss" | |
15898 | [(unspec [(match_operand:QI 0 "immediate_operand" "i")] 189)] | |
15899 | "TARGET_ALTIVEC" | |
15900 | "dss %0" | |
15901 | [(set_attr "type" "vecsimple")]) | |
15902 | ||
15903 | (define_insn "altivec_dst" | |
15904 | [(unspec [(match_operand:SI 0 "register_operand" "b") | |
15905 | (match_operand:SI 1 "register_operand" "r") | |
15906 | (match_operand:QI 2 "immediate_operand" "i")] 190)] | |
15907 | "TARGET_ALTIVEC" | |
15908 | "dst %0,%1,%2" | |
15909 | [(set_attr "type" "vecsimple")]) | |
15910 | ||
15911 | (define_insn "altivec_dstt" | |
15912 | [(unspec [(match_operand:SI 0 "register_operand" "b") | |
15913 | (match_operand:SI 1 "register_operand" "r") | |
15914 | (match_operand:QI 2 "immediate_operand" "i")] 191)] | |
15915 | "TARGET_ALTIVEC" | |
15916 | "dstt %0,%1,%2" | |
15917 | [(set_attr "type" "vecsimple")]) | |
15918 | ||
15919 | (define_insn "altivec_dstst" | |
15920 | [(unspec [(match_operand:SI 0 "register_operand" "b") | |
15921 | (match_operand:SI 1 "register_operand" "r") | |
15922 | (match_operand:QI 2 "immediate_operand" "i")] 192)] | |
15923 | "TARGET_ALTIVEC" | |
15924 | "dstst %0,%1,%2" | |
15925 | [(set_attr "type" "vecsimple")]) | |
15926 | ||
15927 | (define_insn "altivec_dststt" | |
15928 | [(unspec [(match_operand:SI 0 "register_operand" "b") | |
15929 | (match_operand:SI 1 "register_operand" "r") | |
15930 | (match_operand:QI 2 "immediate_operand" "i")] 193)] | |
15931 | "TARGET_ALTIVEC" | |
15932 | "dststt %0,%1,%2" | |
15933 | [(set_attr "type" "vecsimple")]) | |
15934 | ||
15935 | (define_insn "altivec_lvsl" | |
15936 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
acfab996 | 15937 | (unspec:V16QI [(match_operand:SI 1 "register_operand" "b") |
95385cbb AH |
15938 | (match_operand:SI 2 "register_operand" "r")] 194))] |
15939 | "TARGET_ALTIVEC" | |
15940 | "lvsl %0,%1,%2" | |
15941 | [(set_attr "type" "vecload")]) | |
15942 | ||
15943 | (define_insn "altivec_lvsr" | |
15944 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
acfab996 | 15945 | (unspec:V16QI [(match_operand:SI 1 "register_operand" "b") |
95385cbb AH |
15946 | (match_operand:SI 2 "register_operand" "r")] 195))] |
15947 | "TARGET_ALTIVEC" | |
15948 | "lvsr %0,%1,%2" | |
15949 | [(set_attr "type" "vecload")]) | |
6525c0e7 | 15950 | |
69ef87e2 AH |
15951 | ;; Parallel some of the LVE* and STV*'s with unspecs because some have |
15952 | ;; identical rtl but different instructions-- and gcc gets confused. | |
15953 | ||
6525c0e7 | 15954 | (define_insn "altivec_lvebx" |
69ef87e2 AH |
15955 | [(parallel |
15956 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
15957 | (mem:V16QI (plus:SI (match_operand:SI 1 "register_operand" "b") | |
15958 | (match_operand:SI 2 "register_operand" "r")))) | |
15959 | (unspec [(const_int 0)] 196)])] | |
6525c0e7 AH |
15960 | "TARGET_ALTIVEC" |
15961 | "lvebx %0,%1,%2" | |
15962 | [(set_attr "type" "vecload")]) | |
15963 | ||
15964 | (define_insn "altivec_lvehx" | |
69ef87e2 AH |
15965 | [(parallel |
15966 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
15967 | (mem:V8HI | |
15968 | (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b") | |
15969 | (match_operand:SI 2 "register_operand" "r")) | |
15970 | (const_int -2)))) | |
15971 | (unspec [(const_int 0)] 197)])] | |
6525c0e7 AH |
15972 | "TARGET_ALTIVEC" |
15973 | "lvehx %0,%1,%2" | |
15974 | [(set_attr "type" "vecload")]) | |
15975 | ||
15976 | (define_insn "altivec_lvewx" | |
69ef87e2 AH |
15977 | [(parallel |
15978 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15979 | (mem:V4SI | |
15980 | (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b") | |
15981 | (match_operand:SI 2 "register_operand" "r")) | |
15982 | (const_int -4)))) | |
15983 | (unspec [(const_int 0)] 198)])] | |
6525c0e7 AH |
15984 | "TARGET_ALTIVEC" |
15985 | "lvewx %0,%1,%2" | |
15986 | [(set_attr "type" "vecload")]) | |
15987 | ||
15988 | (define_insn "altivec_lvxl" | |
69ef87e2 AH |
15989 | [(parallel |
15990 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
15991 | (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b") | |
15992 | (match_operand:SI 2 "register_operand" "r")))) | |
15993 | (unspec [(const_int 0)] 213)])] | |
6525c0e7 AH |
15994 | "TARGET_ALTIVEC" |
15995 | "lvxl %0,%1,%2" | |
15996 | [(set_attr "type" "vecload")]) | |
15997 | ||
15998 | (define_insn "altivec_lvx" | |
15999 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
69ef87e2 AH |
16000 | (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b") |
16001 | (match_operand:SI 2 "register_operand" "r"))))] | |
6525c0e7 AH |
16002 | "TARGET_ALTIVEC" |
16003 | "lvx %0,%1,%2" | |
16004 | [(set_attr "type" "vecload")]) | |
16005 | ||
16006 | (define_insn "altivec_stvx" | |
acfab996 AH |
16007 | [(parallel |
16008 | [(set (mem:V4SI | |
16009 | (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") | |
16010 | (match_operand:SI 1 "register_operand" "r")) | |
16011 | (const_int -16))) | |
16012 | (match_operand:V4SI 2 "register_operand" "v")) | |
16013 | (unspec [(const_int 0)] 201)])] | |
6525c0e7 AH |
16014 | "TARGET_ALTIVEC" |
16015 | "stvx %2,%0,%1" | |
16016 | [(set_attr "type" "vecstore")]) | |
16017 | ||
16018 | (define_insn "altivec_stvxl" | |
16019 | [(parallel | |
16020 | [(set (mem:V4SI | |
acfab996 | 16021 | (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") |
6525c0e7 AH |
16022 | (match_operand:SI 1 "register_operand" "r")) |
16023 | (const_int -16))) | |
16024 | (match_operand:V4SI 2 "register_operand" "v")) | |
acfab996 | 16025 | (unspec [(const_int 0)] 202)])] |
6525c0e7 AH |
16026 | "TARGET_ALTIVEC" |
16027 | "stvxl %2,%0,%1" | |
16028 | [(set_attr "type" "vecstore")]) | |
16029 | ||
16030 | (define_insn "altivec_stvebx" | |
16031 | [(parallel | |
16032 | [(set (mem:V16QI | |
acfab996 | 16033 | (plus:SI (match_operand:SI 0 "register_operand" "b") |
6525c0e7 AH |
16034 | (match_operand:SI 1 "register_operand" "r"))) |
16035 | (match_operand:V16QI 2 "register_operand" "v")) | |
acfab996 | 16036 | (unspec [(const_int 0)] 203)])] |
6525c0e7 AH |
16037 | "TARGET_ALTIVEC" |
16038 | "stvebx %2,%0,%1" | |
16039 | [(set_attr "type" "vecstore")]) | |
16040 | ||
16041 | (define_insn "altivec_stvehx" | |
acfab996 AH |
16042 | [(parallel |
16043 | [(set (mem:V8HI | |
16044 | (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") | |
16045 | (match_operand:SI 1 "register_operand" "r")) | |
16046 | (const_int -2))) | |
16047 | (match_operand:V8HI 2 "register_operand" "v")) | |
16048 | (unspec [(const_int 0)] 204)])] | |
6525c0e7 AH |
16049 | "TARGET_ALTIVEC" |
16050 | "stvehx %2,%0,%1" | |
16051 | [(set_attr "type" "vecstore")]) | |
16052 | ||
16053 | (define_insn "altivec_stvewx" | |
acfab996 AH |
16054 | [(parallel |
16055 | [(set (mem:V4SI | |
16056 | (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") | |
16057 | (match_operand:SI 1 "register_operand" "r")) | |
16058 | (const_int -4))) | |
16059 | (match_operand:V4SI 2 "register_operand" "v")) | |
16060 | (unspec [(const_int 0)] 205)])] | |
6525c0e7 AH |
16061 | "TARGET_ALTIVEC" |
16062 | "stvewx %2,%0,%1" | |
16063 | [(set_attr "type" "vecstore")]) | |
100c4561 AH |
16064 | |
16065 | (define_insn "absv16qi2" | |
16066 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
16067 | (abs:V16QI (match_operand:V16QI 1 "register_operand" "v"))) | |
16068 | (clobber (match_scratch:V16QI 2 "=v")) | |
16069 | (clobber (match_scratch:V16QI 3 "=v"))] | |
16070 | "TARGET_ALTIVEC" | |
16071 | "vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3" | |
16072 | [(set_attr "type" "altivec") | |
16073 | (set_attr "length" "12")]) | |
16074 | ||
16075 | (define_insn "absv8hi2" | |
16076 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
16077 | (abs:V8HI (match_operand:V8HI 1 "register_operand" "v"))) | |
16078 | (clobber (match_scratch:V8HI 2 "=v")) | |
16079 | (clobber (match_scratch:V8HI 3 "=v"))] | |
16080 | "TARGET_ALTIVEC" | |
16081 | "vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3" | |
16082 | [(set_attr "type" "altivec") | |
16083 | (set_attr "length" "12")]) | |
16084 | ||
16085 | (define_insn "absv4si2" | |
16086 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
16087 | (abs:V4SI (match_operand:V4SI 1 "register_operand" "v"))) | |
16088 | (clobber (match_scratch:V4SI 2 "=v")) | |
16089 | (clobber (match_scratch:V4SI 3 "=v"))] | |
16090 | "TARGET_ALTIVEC" | |
16091 | "vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3" | |
16092 | [(set_attr "type" "altivec") | |
16093 | (set_attr "length" "12")]) | |
16094 | ||
16095 | (define_insn "absv4sf2" | |
16096 | [(set (match_operand:V4SF 0 "register_operand" "=v") | |
16097 | (abs:V4SF (match_operand:V4SF 1 "register_operand" "v"))) | |
16098 | (clobber (match_scratch:V4SF 2 "=v")) | |
16099 | (clobber (match_scratch:V4SF 3 "=v"))] | |
16100 | "TARGET_ALTIVEC" | |
16101 | "vspltisw %2, -1\;vslw %3,%2,%2\;vandc %0,%1,%3" | |
16102 | [(set_attr "type" "altivec") | |
16103 | (set_attr "length" "12")]) | |
16104 | ||
16105 | (define_insn "altivec_abss_v16qi" | |
16106 | [(set (match_operand:V16QI 0 "register_operand" "=v") | |
16107 | (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210)) | |
16108 | (clobber (match_scratch:V16QI 2 "=v")) | |
16109 | (clobber (match_scratch:V16QI 3 "=v"))] | |
16110 | "TARGET_ALTIVEC" | |
16111 | "vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3" | |
16112 | [(set_attr "type" "altivec") | |
16113 | (set_attr "length" "12")]) | |
16114 | ||
16115 | (define_insn "altivec_abss_v8hi" | |
16116 | [(set (match_operand:V8HI 0 "register_operand" "=v") | |
16117 | (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211)) | |
16118 | (clobber (match_scratch:V8HI 2 "=v")) | |
16119 | (clobber (match_scratch:V8HI 3 "=v"))] | |
16120 | "TARGET_ALTIVEC" | |
16121 | "vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3" | |
16122 | [(set_attr "type" "altivec") | |
16123 | (set_attr "length" "12")]) | |
16124 | ||
16125 | (define_insn "altivec_abss_v4si" | |
16126 | [(set (match_operand:V4SI 0 "register_operand" "=v") | |
16127 | (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212)) | |
16128 | (clobber (match_scratch:V4SI 2 "=v")) | |
16129 | (clobber (match_scratch:V4SI 3 "=v"))] | |
16130 | "TARGET_ALTIVEC" | |
16131 | "vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3" | |
16132 | [(set_attr "type" "altivec") | |
16133 | (set_attr "length" "12")]) |