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Fixed a typo.
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
CommitLineData
996a5f59 1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
d24652ee 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
affad9a4 3;; 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
996a5f59 4;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
1fd4e8c1 5
5de601cf 6;; This file is part of GCC.
1fd4e8c1 7
5de601cf
NC		 8;; GCC is free software; you can redistribute it and/or modify it
9;; under the terms of the GNU General Public License as published
10;; by the Free Software Foundation; either version 2, or (at your
11;; option) any later version.
1fd4e8c1 12
5de601cf
NC		 13;; GCC is distributed in the hope that it will be useful, but WITHOUT
14;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16;; License for more details.
1fd4e8c1
RK		 17
18;; You should have received a copy of the GNU General Public License
5de601cf
NC		 19;; along with GCC; see the file COPYING. If not, write to the
20;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21;; MA 02111-1307, USA.
1fd4e8c1
RK		 22
23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
9ebbca7d 24
615158e2
JJ		 25;;
26;; UNSPEC usage
27;;
28
29(define_constants
30 [(UNSPEC_FRSP 0) ; frsp for POWER machines
31 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
32 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
33 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
34 (UNSPEC_MOVSI_GOT 8)
35 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
36 (UNSPEC_FCTIWZ 10)
37 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
38 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
39 (UNSPEC_TLSGD 17)
40 (UNSPEC_TLSLD 18)
41 (UNSPEC_MOVESI_FROM_CR 19)
42 (UNSPEC_MOVESI_TO_CR 20)
43 (UNSPEC_TLSDTPREL 21)
44 (UNSPEC_TLSDTPRELHA 22)
45 (UNSPEC_TLSDTPRELLO 23)
46 (UNSPEC_TLSGOTDTPREL 24)
47 (UNSPEC_TLSTPREL 25)
48 (UNSPEC_TLSTPRELHA 26)
49 (UNSPEC_TLSTPRELLO 27)
50 (UNSPEC_TLSGOTTPREL 28)
51 (UNSPEC_TLSTLS 29)
ecb62ae7 52 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
615158e2
JJ		 53 ])
54
55;;
56;; UNSPEC_VOLATILE usage
57;;
58
59(define_constants
60 [(UNSPECV_BLOCK 0)
61 (UNSPECV_EH_RR 9) ; eh_reg_restore
62 ])
1fd4e8c1
RK		 63\f
64;; Define an insn type attribute. This is used in function unit delay
65;; computations.
2c4a9cff 66(define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
1fd4e8c1
RK		 67 (const_string "integer"))
68
b19003d8 69;; Length (in bytes).
6cbadf36
GK		 70; '(pc)' in the following doesn't include the instruction itself; it is
71; calculated as if the instruction had zero size.
b19003d8
RK		 72(define_attr "length" ""
73 (if_then_else (eq_attr "type" "branch")
6cbadf36 74 (if_then_else (and (ge (minus (match_dup 0) (pc))
b19003d8 75 (const_int -32768))
6cbadf36
GK		 76 (lt (minus (match_dup 0) (pc))
77 (const_int 32764)))
39a10a29
GK		 78 (const_int 4)
79 (const_int 8))
b19003d8
RK		 80 (const_int 4)))
81
cfb557c4
RK		 82;; Processor type -- this attribute must exactly match the processor_type
83;; enumeration in rs6000.h.
84
b54cf83a 85(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4"
cfb557c4
RK		 86 (const (symbol_ref "rs6000_cpu_attr")))
87
b54cf83a
DE		 88(automata_option "ndfa")
89
90(include "rios1.md")
91(include "rios2.md")
92(include "rs64.md")
93(include "mpc.md")
94(include "40x.md")
02ca7595 95(include "440.md")
b54cf83a
DE		 96(include "603.md")
97(include "6xx.md")
98(include "7xx.md")
99(include "7450.md")
5e8006fa 100(include "8540.md")
b54cf83a 101(include "power4.md")
309323c2 102
1fd4e8c1
RK		 103\f
104;; Start with fixed-point load and store insns. Here we put only the more
105;; complex forms. Basic data transfer is done later.
106
51b8fc2c
RK		 107(define_expand "zero_extendqidi2"
108 [(set (match_operand:DI 0 "gpc_reg_operand" "")
109 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
110 "TARGET_POWERPC64"
111 "")
112
113(define_insn ""
114 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
115 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
116 "TARGET_POWERPC64"
117 "@
118 lbz%U1%X1 %0,%1
4371f8af 119 rldicl %0,%1,0,56"
51b8fc2c
RK		 120 [(set_attr "type" "load,*")])
121
122(define_insn ""
9ebbca7d
GK		 123 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
124 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815cdc52 125 (const_int 0)))
9ebbca7d 126 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 127 "TARGET_64BIT"
9ebbca7d
GK		 128 "@
129 rldicl. %2,%1,0,56
130 #"
131 [(set_attr "type" "compare")
132 (set_attr "length" "4,8")])
133
134(define_split
135 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
136 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
137 (const_int 0)))
138 (clobber (match_scratch:DI 2 ""))]
139 "TARGET_POWERPC64 && reload_completed"
140 [(set (match_dup 2)
141 (zero_extend:DI (match_dup 1)))
142 (set (match_dup 0)
143 (compare:CC (match_dup 2)
144 (const_int 0)))]
145 "")
51b8fc2c
RK		 146
147(define_insn ""
9ebbca7d
GK		 148 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
149 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 150 (const_int 0)))
9ebbca7d 151 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 152 (zero_extend:DI (match_dup 1)))]
683bdff7 153 "TARGET_64BIT"
9ebbca7d
GK		 154 "@
155 rldicl. %0,%1,0,56
156 #"
157 [(set_attr "type" "compare")
158 (set_attr "length" "4,8")])
159
160(define_split
161 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
162 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
163 (const_int 0)))
164 (set (match_operand:DI 0 "gpc_reg_operand" "")
165 (zero_extend:DI (match_dup 1)))]
166 "TARGET_POWERPC64 && reload_completed"
167 [(set (match_dup 0)
168 (zero_extend:DI (match_dup 1)))
169 (set (match_dup 2)
170 (compare:CC (match_dup 0)
171 (const_int 0)))]
172 "")
51b8fc2c 173
2bee0449
RK		 174(define_insn "extendqidi2"
175 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
176 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 177 "TARGET_POWERPC64"
2bee0449 178 "extsb %0,%1")
51b8fc2c
RK		 179
180(define_insn ""
9ebbca7d
GK		 181 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
182 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 183 (const_int 0)))
9ebbca7d 184 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 185 "TARGET_64BIT"
9ebbca7d
GK		 186 "@
187 extsb. %2,%1
188 #"
189 [(set_attr "type" "compare")
190 (set_attr "length" "4,8")])
191
192(define_split
193 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
194 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
195 (const_int 0)))
196 (clobber (match_scratch:DI 2 ""))]
197 "TARGET_POWERPC64 && reload_completed"
198 [(set (match_dup 2)
199 (sign_extend:DI (match_dup 1)))
200 (set (match_dup 0)
201 (compare:CC (match_dup 2)
202 (const_int 0)))]
203 "")
51b8fc2c
RK		 204
205(define_insn ""
9ebbca7d
GK		 206 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
207 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 208 (const_int 0)))
9ebbca7d 209 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 210 (sign_extend:DI (match_dup 1)))]
683bdff7 211 "TARGET_64BIT"
9ebbca7d
GK		 212 "@
213 extsb. %0,%1
214 #"
215 [(set_attr "type" "compare")
216 (set_attr "length" "4,8")])
217
218(define_split
219 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
220 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
221 (const_int 0)))
222 (set (match_operand:DI 0 "gpc_reg_operand" "")
223 (sign_extend:DI (match_dup 1)))]
224 "TARGET_POWERPC64 && reload_completed"
225 [(set (match_dup 0)
226 (sign_extend:DI (match_dup 1)))
227 (set (match_dup 2)
228 (compare:CC (match_dup 0)
229 (const_int 0)))]
230 "")
51b8fc2c
RK		 231
232(define_expand "zero_extendhidi2"
233 [(set (match_operand:DI 0 "gpc_reg_operand" "")
234 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
235 "TARGET_POWERPC64"
236 "")
237
238(define_insn ""
239 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
240 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
241 "TARGET_POWERPC64"
242 "@
243 lhz%U1%X1 %0,%1
4371f8af 244 rldicl %0,%1,0,48"
51b8fc2c
RK		 245 [(set_attr "type" "load,*")])
246
247(define_insn ""
9ebbca7d
GK		 248 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
249 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 250 (const_int 0)))
9ebbca7d 251 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 252 "TARGET_64BIT"
9ebbca7d
GK		 253 "@
254 rldicl. %2,%1,0,48
255 #"
256 [(set_attr "type" "compare")
257 (set_attr "length" "4,8")])
258
259(define_split
260 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
261 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
262 (const_int 0)))
263 (clobber (match_scratch:DI 2 ""))]
264 "TARGET_POWERPC64 && reload_completed"
265 [(set (match_dup 2)
266 (zero_extend:DI (match_dup 1)))
267 (set (match_dup 0)
268 (compare:CC (match_dup 2)
269 (const_int 0)))]
270 "")
51b8fc2c
RK		 271
272(define_insn ""
9ebbca7d
GK		 273 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
274 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 275 (const_int 0)))
9ebbca7d 276 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 277 (zero_extend:DI (match_dup 1)))]
683bdff7 278 "TARGET_64BIT"
9ebbca7d
GK		 279 "@
280 rldicl. %0,%1,0,48
281 #"
282 [(set_attr "type" "compare")
283 (set_attr "length" "4,8")])
284
285(define_split
286 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
287 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
288 (const_int 0)))
289 (set (match_operand:DI 0 "gpc_reg_operand" "")
290 (zero_extend:DI (match_dup 1)))]
291 "TARGET_POWERPC64 && reload_completed"
292 [(set (match_dup 0)
293 (zero_extend:DI (match_dup 1)))
294 (set (match_dup 2)
295 (compare:CC (match_dup 0)
296 (const_int 0)))]
297 "")
51b8fc2c
RK		 298
299(define_expand "extendhidi2"
300 [(set (match_operand:DI 0 "gpc_reg_operand" "")
301 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
302 "TARGET_POWERPC64"
303 "")
304
305(define_insn ""
306 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
307 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
308 "TARGET_POWERPC64"
309 "@
310 lha%U1%X1 %0,%1
311 extsh %0,%1"
b54cf83a 312 [(set_attr "type" "load_ext,*")])
51b8fc2c
RK		 313
314(define_insn ""
9ebbca7d
GK		 315 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
316 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 317 (const_int 0)))
9ebbca7d 318 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 319 "TARGET_64BIT"
9ebbca7d
GK		 320 "@
321 extsh. %2,%1
322 #"
323 [(set_attr "type" "compare")
324 (set_attr "length" "4,8")])
325
326(define_split
327 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
328 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
329 (const_int 0)))
330 (clobber (match_scratch:DI 2 ""))]
331 "TARGET_POWERPC64 && reload_completed"
332 [(set (match_dup 2)
333 (sign_extend:DI (match_dup 1)))
334 (set (match_dup 0)
335 (compare:CC (match_dup 2)
336 (const_int 0)))]
337 "")
51b8fc2c
RK		 338
339(define_insn ""
9ebbca7d
GK		 340 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
341 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 342 (const_int 0)))
9ebbca7d 343 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 344 (sign_extend:DI (match_dup 1)))]
683bdff7 345 "TARGET_64BIT"
9ebbca7d
GK		 346 "@
347 extsh. %0,%1
348 #"
349 [(set_attr "type" "compare")
350 (set_attr "length" "4,8")])
351
352(define_split
353 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
354 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
355 (const_int 0)))
356 (set (match_operand:DI 0 "gpc_reg_operand" "")
357 (sign_extend:DI (match_dup 1)))]
358 "TARGET_POWERPC64 && reload_completed"
359 [(set (match_dup 0)
360 (sign_extend:DI (match_dup 1)))
361 (set (match_dup 2)
362 (compare:CC (match_dup 0)
363 (const_int 0)))]
364 "")
51b8fc2c
RK		 365
366(define_expand "zero_extendsidi2"
367 [(set (match_operand:DI 0 "gpc_reg_operand" "")
368 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
369 "TARGET_POWERPC64"
370 "")
371
372(define_insn ""
373 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
374 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
375 "TARGET_POWERPC64"
376 "@
377 lwz%U1%X1 %0,%1
378 rldicl %0,%1,0,32"
379 [(set_attr "type" "load,*")])
380
381(define_insn ""
9ebbca7d
GK		 382 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
383 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 384 (const_int 0)))
9ebbca7d 385 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 386 "TARGET_64BIT"
9ebbca7d
GK		 387 "@
388 rldicl. %2,%1,0,32
389 #"
390 [(set_attr "type" "compare")
391 (set_attr "length" "4,8")])
392
393(define_split
394 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
395 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
396 (const_int 0)))
397 (clobber (match_scratch:DI 2 ""))]
398 "TARGET_POWERPC64 && reload_completed"
399 [(set (match_dup 2)
400 (zero_extend:DI (match_dup 1)))
401 (set (match_dup 0)
402 (compare:CC (match_dup 2)
403 (const_int 0)))]
404 "")
51b8fc2c
RK		 405
406(define_insn ""
9ebbca7d
GK		 407 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
408 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 409 (const_int 0)))
9ebbca7d 410 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 411 (zero_extend:DI (match_dup 1)))]
683bdff7 412 "TARGET_64BIT"
9ebbca7d
GK		 413 "@
414 rldicl. %0,%1,0,32
415 #"
416 [(set_attr "type" "compare")
417 (set_attr "length" "4,8")])
418
419(define_split
420 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
421 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
422 (const_int 0)))
423 (set (match_operand:DI 0 "gpc_reg_operand" "")
424 (zero_extend:DI (match_dup 1)))]
425 "TARGET_POWERPC64 && reload_completed"
426 [(set (match_dup 0)
427 (zero_extend:DI (match_dup 1)))
428 (set (match_dup 2)
429 (compare:CC (match_dup 0)
430 (const_int 0)))]
431 "")
51b8fc2c
RK		 432
433(define_expand "extendsidi2"
434 [(set (match_operand:DI 0 "gpc_reg_operand" "")
435 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
436 "TARGET_POWERPC64"
437 "")
438
439(define_insn ""
440 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
287f13ff 441 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
51b8fc2c
RK		 442 "TARGET_POWERPC64"
443 "@
444 lwa%U1%X1 %0,%1
445 extsw %0,%1"
b54cf83a 446 [(set_attr "type" "load_ext,*")])
51b8fc2c
RK		 447
448(define_insn ""
9ebbca7d
GK		 449 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
450 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 451 (const_int 0)))
9ebbca7d 452 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 453 "TARGET_64BIT"
9ebbca7d
GK		 454 "@
455 extsw. %2,%1
456 #"
457 [(set_attr "type" "compare")
458 (set_attr "length" "4,8")])
459
460(define_split
461 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
462 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
463 (const_int 0)))
464 (clobber (match_scratch:DI 2 ""))]
465 "TARGET_POWERPC64 && reload_completed"
466 [(set (match_dup 2)
467 (sign_extend:DI (match_dup 1)))
468 (set (match_dup 0)
469 (compare:CC (match_dup 2)
470 (const_int 0)))]
471 "")
51b8fc2c
RK		 472
473(define_insn ""
9ebbca7d
GK		 474 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
475 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 476 (const_int 0)))
9ebbca7d 477 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 478 (sign_extend:DI (match_dup 1)))]
683bdff7 479 "TARGET_64BIT"
9ebbca7d
GK		 480 "@
481 extsw. %0,%1
482 #"
483 [(set_attr "type" "compare")
484 (set_attr "length" "4,8")])
485
486(define_split
487 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
488 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
489 (const_int 0)))
490 (set (match_operand:DI 0 "gpc_reg_operand" "")
491 (sign_extend:DI (match_dup 1)))]
492 "TARGET_POWERPC64 && reload_completed"
493 [(set (match_dup 0)
494 (sign_extend:DI (match_dup 1)))
495 (set (match_dup 2)
496 (compare:CC (match_dup 0)
497 (const_int 0)))]
498 "")
51b8fc2c 499
1fd4e8c1 500(define_expand "zero_extendqisi2"
cd2b37d9
RK		 501 [(set (match_operand:SI 0 "gpc_reg_operand" "")
502 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 503 ""
504 "")
505
506(define_insn ""
cd2b37d9 507 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 508 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
509 ""
510 "@
511 lbz%U1%X1 %0,%1
005a35b9 512 {rlinm|rlwinm} %0,%1,0,0xff"
1fd4e8c1
RK		 513 [(set_attr "type" "load,*")])
514
515(define_insn ""
9ebbca7d
GK		 516 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
517 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 518 (const_int 0)))
9ebbca7d 519 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 520 ""
9ebbca7d
GK		 521 "@
522 {andil.|andi.} %2,%1,0xff
523 #"
524 [(set_attr "type" "compare")
525 (set_attr "length" "4,8")])
526
527(define_split
528 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
529 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
530 (const_int 0)))
531 (clobber (match_scratch:SI 2 ""))]
532 "reload_completed"
533 [(set (match_dup 2)
534 (zero_extend:SI (match_dup 1)))
535 (set (match_dup 0)
536 (compare:CC (match_dup 2)
537 (const_int 0)))]
538 "")
1fd4e8c1
RK		 539
540(define_insn ""
9ebbca7d
GK		 541 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
542 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 543 (const_int 0)))
9ebbca7d 544 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 545 (zero_extend:SI (match_dup 1)))]
546 ""
9ebbca7d
GK		 547 "@
548 {andil.|andi.} %0,%1,0xff
549 #"
550 [(set_attr "type" "compare")
551 (set_attr "length" "4,8")])
552
553(define_split
554 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
555 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
556 (const_int 0)))
557 (set (match_operand:SI 0 "gpc_reg_operand" "")
558 (zero_extend:SI (match_dup 1)))]
559 "reload_completed"
560 [(set (match_dup 0)
561 (zero_extend:SI (match_dup 1)))
562 (set (match_dup 2)
563 (compare:CC (match_dup 0)
564 (const_int 0)))]
565 "")
1fd4e8c1 566
51b8fc2c
RK		 567(define_expand "extendqisi2"
568 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
569 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
570 ""
571 "
572{
573 if (TARGET_POWERPC)
574 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
575 else if (TARGET_POWER)
576 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
577 else
578 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
579 DONE;
580}")
581
582(define_insn "extendqisi2_ppc"
2bee0449
RK		 583 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
584 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 585 "TARGET_POWERPC"
2bee0449 586 "extsb %0,%1")
51b8fc2c
RK		 587
588(define_insn ""
9ebbca7d
GK		 589 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
590 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 591 (const_int 0)))
9ebbca7d 592 (clobber (match_scratch:SI 2 "=r,r"))]
51b8fc2c 593 "TARGET_POWERPC"
9ebbca7d
GK		 594 "@
595 extsb. %2,%1
596 #"
597 [(set_attr "type" "compare")
598 (set_attr "length" "4,8")])
599
600(define_split
601 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
602 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
603 (const_int 0)))
604 (clobber (match_scratch:SI 2 ""))]
605 "TARGET_POWERPC && reload_completed"
606 [(set (match_dup 2)
607 (sign_extend:SI (match_dup 1)))
608 (set (match_dup 0)
609 (compare:CC (match_dup 2)
610 (const_int 0)))]
611 "")
51b8fc2c
RK		 612
613(define_insn ""
9ebbca7d
GK		 614 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
615 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 616 (const_int 0)))
9ebbca7d 617 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 618 (sign_extend:SI (match_dup 1)))]
619 "TARGET_POWERPC"
9ebbca7d
GK		 620 "@
621 extsb. %0,%1
622 #"
623 [(set_attr "type" "compare")
624 (set_attr "length" "4,8")])
625
626(define_split
627 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
628 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
629 (const_int 0)))
630 (set (match_operand:SI 0 "gpc_reg_operand" "")
631 (sign_extend:SI (match_dup 1)))]
632 "TARGET_POWERPC && reload_completed"
633 [(set (match_dup 0)
634 (sign_extend:SI (match_dup 1)))
635 (set (match_dup 2)
636 (compare:CC (match_dup 0)
637 (const_int 0)))]
638 "")
51b8fc2c
RK		 639
640(define_expand "extendqisi2_power"
641 [(parallel [(set (match_dup 2)
642 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
643 (const_int 24)))
644 (clobber (scratch:SI))])
645 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
646 (ashiftrt:SI (match_dup 2)
647 (const_int 24)))
648 (clobber (scratch:SI))])]
649 "TARGET_POWER"
650 "
651{ operands[1] = gen_lowpart (SImode, operands[1]);
652 operands[2] = gen_reg_rtx (SImode); }")
653
654(define_expand "extendqisi2_no_power"
655 [(set (match_dup 2)
656 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
657 (const_int 24)))
658 (set (match_operand:SI 0 "gpc_reg_operand" "")
659 (ashiftrt:SI (match_dup 2)
660 (const_int 24)))]
661 "! TARGET_POWER && ! TARGET_POWERPC"
662 "
663{ operands[1] = gen_lowpart (SImode, operands[1]);
664 operands[2] = gen_reg_rtx (SImode); }")
665
1fd4e8c1 666(define_expand "zero_extendqihi2"
cd2b37d9
RK		 667 [(set (match_operand:HI 0 "gpc_reg_operand" "")
668 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 669 ""
670 "")
671
672(define_insn ""
cd2b37d9 673 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 674 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
675 ""
676 "@
677 lbz%U1%X1 %0,%1
005a35b9 678 {rlinm|rlwinm} %0,%1,0,0xff"
51b8fc2c
RK		 679 [(set_attr "type" "load,*")])
680
681(define_insn ""
9ebbca7d
GK		 682 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
683 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 684 (const_int 0)))
9ebbca7d 685 (clobber (match_scratch:HI 2 "=r,r"))]
51b8fc2c 686 ""
9ebbca7d
GK		 687 "@
688 {andil.|andi.} %2,%1,0xff
689 #"
690 [(set_attr "type" "compare")
691 (set_attr "length" "4,8")])
692
693(define_split
694 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
695 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
696 (const_int 0)))
697 (clobber (match_scratch:HI 2 ""))]
698 "reload_completed"
699 [(set (match_dup 2)
700 (zero_extend:HI (match_dup 1)))
701 (set (match_dup 0)
702 (compare:CC (match_dup 2)
703 (const_int 0)))]
704 "")
1fd4e8c1 705
51b8fc2c 706(define_insn ""
9ebbca7d
GK		 707 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
708 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 709 (const_int 0)))
9ebbca7d 710 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 711 (zero_extend:HI (match_dup 1)))]
712 ""
9ebbca7d
GK		 713 "@
714 {andil.|andi.} %0,%1,0xff
715 #"
716 [(set_attr "type" "compare")
717 (set_attr "length" "4,8")])
718
719(define_split
720 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
721 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
722 (const_int 0)))
723 (set (match_operand:HI 0 "gpc_reg_operand" "")
724 (zero_extend:HI (match_dup 1)))]
725 "reload_completed"
726 [(set (match_dup 0)
727 (zero_extend:HI (match_dup 1)))
728 (set (match_dup 2)
729 (compare:CC (match_dup 0)
730 (const_int 0)))]
731 "")
815cdc52
MM		 732
733(define_expand "extendqihi2"
734 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
735 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
736 ""
737 "
738{
739 if (TARGET_POWERPC)
740 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
741 else if (TARGET_POWER)
742 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
743 else
744 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
745 DONE;
746}")
747
748(define_insn "extendqihi2_ppc"
749 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
750 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
751 "TARGET_POWERPC"
752 "extsb %0,%1")
753
754(define_insn ""
9ebbca7d
GK		 755 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
756 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815cdc52 757 (const_int 0)))
9ebbca7d 758 (clobber (match_scratch:HI 2 "=r,r"))]
815cdc52 759 "TARGET_POWERPC"
9ebbca7d
GK		 760 "@
761 extsb. %2,%1
762 #"
763 [(set_attr "type" "compare")
764 (set_attr "length" "4,8")])
765
766(define_split
767 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
768 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
769 (const_int 0)))
770 (clobber (match_scratch:HI 2 ""))]
771 "TARGET_POWERPC && reload_completed"
772 [(set (match_dup 2)
773 (sign_extend:HI (match_dup 1)))
774 (set (match_dup 0)
775 (compare:CC (match_dup 2)
776 (const_int 0)))]
777 "")
815cdc52
MM		 778
779(define_insn ""
9ebbca7d
GK		 780 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
781 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 782 (const_int 0)))
9ebbca7d 783 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 784 (sign_extend:HI (match_dup 1)))]
785 "TARGET_POWERPC"
9ebbca7d
GK		 786 "@
787 extsb. %0,%1
788 #"
789 [(set_attr "type" "compare")
790 (set_attr "length" "4,8")])
791
792(define_split
793 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
794 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
795 (const_int 0)))
796 (set (match_operand:HI 0 "gpc_reg_operand" "")
797 (sign_extend:HI (match_dup 1)))]
798 "TARGET_POWERPC && reload_completed"
799 [(set (match_dup 0)
800 (sign_extend:HI (match_dup 1)))
801 (set (match_dup 2)
802 (compare:CC (match_dup 0)
803 (const_int 0)))]
804 "")
51b8fc2c
RK		 805
806(define_expand "extendqihi2_power"
807 [(parallel [(set (match_dup 2)
808 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
809 (const_int 24)))
810 (clobber (scratch:SI))])
811 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
812 (ashiftrt:SI (match_dup 2)
813 (const_int 24)))
814 (clobber (scratch:SI))])]
815 "TARGET_POWER"
816 "
817{ operands[0] = gen_lowpart (SImode, operands[0]);
818 operands[1] = gen_lowpart (SImode, operands[1]);
819 operands[2] = gen_reg_rtx (SImode); }")
820
821(define_expand "extendqihi2_no_power"
822 [(set (match_dup 2)
823 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
824 (const_int 24)))
825 (set (match_operand:HI 0 "gpc_reg_operand" "")
826 (ashiftrt:SI (match_dup 2)
827 (const_int 24)))]
828 "! TARGET_POWER && ! TARGET_POWERPC"
829 "
830{ operands[0] = gen_lowpart (SImode, operands[0]);
831 operands[1] = gen_lowpart (SImode, operands[1]);
832 operands[2] = gen_reg_rtx (SImode); }")
833
1fd4e8c1 834(define_expand "zero_extendhisi2"
5f243543 835 [(set (match_operand:SI 0 "gpc_reg_operand" "")
cd2b37d9 836 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 837 ""
838 "")
839
840(define_insn ""
cd2b37d9 841 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 842 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
843 ""
844 "@
845 lhz%U1%X1 %0,%1
005a35b9 846 {rlinm|rlwinm} %0,%1,0,0xffff"
1fd4e8c1
RK		 847 [(set_attr "type" "load,*")])
848
849(define_insn ""
9ebbca7d
GK		 850 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
851 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 852 (const_int 0)))
9ebbca7d 853 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 854 ""
9ebbca7d
GK		 855 "@
856 {andil.|andi.} %2,%1,0xffff
857 #"
858 [(set_attr "type" "compare")
859 (set_attr "length" "4,8")])
860
861(define_split
862 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
863 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
864 (const_int 0)))
865 (clobber (match_scratch:SI 2 ""))]
866 "reload_completed"
867 [(set (match_dup 2)
868 (zero_extend:SI (match_dup 1)))
869 (set (match_dup 0)
870 (compare:CC (match_dup 2)
871 (const_int 0)))]
872 "")
1fd4e8c1
RK		 873
874(define_insn ""
9ebbca7d
GK		 875 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
876 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 877 (const_int 0)))
9ebbca7d 878 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 879 (zero_extend:SI (match_dup 1)))]
880 ""
9ebbca7d
GK		 881 "@
882 {andil.|andi.} %0,%1,0xffff
883 #"
884 [(set_attr "type" "compare")
885 (set_attr "length" "4,8")])
886
887(define_split
888 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
889 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
890 (const_int 0)))
891 (set (match_operand:SI 0 "gpc_reg_operand" "")
892 (zero_extend:SI (match_dup 1)))]
893 "reload_completed"
894 [(set (match_dup 0)
895 (zero_extend:SI (match_dup 1)))
896 (set (match_dup 2)
897 (compare:CC (match_dup 0)
898 (const_int 0)))]
899 "")
1fd4e8c1
RK		 900
901(define_expand "extendhisi2"
cd2b37d9
RK		 902 [(set (match_operand:SI 0 "gpc_reg_operand" "")
903 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 904 ""
905 "")
906
907(define_insn ""
cd2b37d9 908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 909 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
910 ""
911 "@
912 lha%U1%X1 %0,%1
ca7f5001 913 {exts|extsh} %0,%1"
b54cf83a 914 [(set_attr "type" "load_ext,*")])
1fd4e8c1
RK		 915
916(define_insn ""
9ebbca7d
GK		 917 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
918 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 919 (const_int 0)))
9ebbca7d 920 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 921 ""
9ebbca7d
GK		 922 "@
923 {exts.|extsh.} %2,%1
924 #"
925 [(set_attr "type" "compare")
926 (set_attr "length" "4,8")])
927
928(define_split
929 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
930 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
931 (const_int 0)))
932 (clobber (match_scratch:SI 2 ""))]
933 "reload_completed"
934 [(set (match_dup 2)
935 (sign_extend:SI (match_dup 1)))
936 (set (match_dup 0)
937 (compare:CC (match_dup 2)
938 (const_int 0)))]
939 "")
1fd4e8c1
RK		 940
941(define_insn ""
9ebbca7d
GK		 942 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
943 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 944 (const_int 0)))
9ebbca7d 945 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 946 (sign_extend:SI (match_dup 1)))]
947 ""
9ebbca7d
GK		 948 "@
949 {exts.|extsh.} %0,%1
950 #"
951 [(set_attr "type" "compare")
952 (set_attr "length" "4,8")])
1fd4e8c1 953\f
9ebbca7d
GK		 954(define_split
955 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
956 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
957 (const_int 0)))
958 (set (match_operand:SI 0 "gpc_reg_operand" "")
959 (sign_extend:SI (match_dup 1)))]
960 "reload_completed"
961 [(set (match_dup 0)
962 (sign_extend:SI (match_dup 1)))
963 (set (match_dup 2)
964 (compare:CC (match_dup 0)
965 (const_int 0)))]
966 "")
967
1fd4e8c1 968;; Fixed-point arithmetic insns.
deb9225a
RK		 969
970;; Discourage ai/addic because of carry but provide it in an alternative
971;; allowing register zero as source.
7cd5235b
MM		 972(define_expand "addsi3"
973 [(set (match_operand:SI 0 "gpc_reg_operand" "")
974 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
f6bf7de2 975 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
7cd5235b
MM		 976 ""
977 "
978{
677a9668
DE		 979 if (GET_CODE (operands[2]) == CONST_INT
980 && ! add_operand (operands[2], SImode))
7cd5235b 981 {
677a9668 982 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 983 ? operands[0] : gen_reg_rtx (SImode));
984
2bfcf297 985 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 986 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2bfcf297 987 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
7cd5235b 988
9ebbca7d
GK		 989 /* The ordering here is important for the prolog expander.
990 When space is allocated from the stack, adding 'low' first may
991 produce a temporary deallocation (which would be bad). */
2bfcf297 992 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
7cd5235b
MM		 993 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
994 DONE;
995 }
996}")
997
998(define_insn "*addsi3_internal1"
999 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1000 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
9615f239 1001 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1fd4e8c1
RK		 1002 ""
1003 "@
deb9225a
RK		 1004 {cax|add} %0,%1,%2
1005 {cal %0,%2(%1)|addi %0,%1,%2}
1006 {ai|addic} %0,%1,%2
7cd5235b
MM		 1007 {cau|addis} %0,%1,%v2"
1008 [(set_attr "length" "4,4,4,4")])
1fd4e8c1 1009
ee890fe2
SS		 1010(define_insn "addsi3_high"
1011 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1012 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1013 (high:SI (match_operand 2 "" ""))))]
1014 "TARGET_MACHO && !TARGET_64BIT"
1015 "{cau|addis} %0,%1,ha16(%2)"
1016 [(set_attr "length" "4")])
1017
7cd5235b 1018(define_insn "*addsi3_internal2"
cb8cc086
MM		 1019 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1020 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1021 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1022 (const_int 0)))
cb8cc086 1023 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4b8a63d6 1024 "TARGET_32BIT"
deb9225a
RK		 1025 "@
1026 {cax.|add.} %3,%1,%2
cb8cc086
MM		 1027 {ai.|addic.} %3,%1,%2
1028 #
1029 #"
a62bfff2 1030 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1031 (set_attr "length" "4,4,8,8")])
1032
1033(define_split
1034 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1035 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1036 (match_operand:SI 2 "reg_or_short_operand" ""))
1037 (const_int 0)))
1038 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 1039 "TARGET_32BIT && reload_completed"
cb8cc086
MM		 1040 [(set (match_dup 3)
1041 (plus:SI (match_dup 1)
1042 (match_dup 2)))
1043 (set (match_dup 0)
1044 (compare:CC (match_dup 3)
1045 (const_int 0)))]
1046 "")
7e69e155 1047
7cd5235b 1048(define_insn "*addsi3_internal3"
cb8cc086
MM		 1049 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1050 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1051 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1052 (const_int 0)))
cb8cc086
MM		 1053 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1054 (plus:SI (match_dup 1)
1055 (match_dup 2)))]
4b8a63d6 1056 "TARGET_32BIT"
deb9225a
RK		 1057 "@
1058 {cax.|add.} %0,%1,%2
cb8cc086
MM		 1059 {ai.|addic.} %0,%1,%2
1060 #
1061 #"
a62bfff2 1062 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1063 (set_attr "length" "4,4,8,8")])
1064
1065(define_split
1066 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1067 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1068 (match_operand:SI 2 "reg_or_short_operand" ""))
1069 (const_int 0)))
1070 (set (match_operand:SI 0 "gpc_reg_operand" "")
1071 (plus:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 1072 "TARGET_32BIT && reload_completed"
cb8cc086
MM		 1073 [(set (match_dup 0)
1074 (plus:SI (match_dup 1)
1075 (match_dup 2)))
1076 (set (match_dup 3)
1077 (compare:CC (match_dup 0)
1078 (const_int 0)))]
1079 "")
7e69e155 1080
f357808b
RK		 1081;; Split an add that we can't do in one insn into two insns, each of which
1082;; does one 16-bit part. This is used by combine. Note that the low-order
1083;; add should be last in case the result gets used in an address.
1084
1085(define_split
cd2b37d9
RK		 1086 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1087 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
f357808b 1088 (match_operand:SI 2 "non_add_cint_operand" "")))]
1fd4e8c1 1089 ""
f357808b
RK		 1090 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1091 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1092"
1fd4e8c1 1093{
2bfcf297 1094 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1095 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2bfcf297 1096 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1fd4e8c1 1097
2bfcf297 1098 operands[3] = GEN_INT (rest);
e6ca2c17 1099 operands[4] = GEN_INT (low);
1fd4e8c1
RK		 1100}")
1101
8de2a197 1102(define_insn "one_cmplsi2"
cd2b37d9
RK		 1103 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1104 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1fd4e8c1 1105 ""
ca7f5001
RK		 1106 "nor %0,%1,%1")
1107
1108(define_insn ""
52d3af72
DE		 1109 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1110 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
ca7f5001 1111 (const_int 0)))
52d3af72 1112 (clobber (match_scratch:SI 2 "=r,r"))]
4b8a63d6 1113 "TARGET_32BIT"
52d3af72
DE		 1114 "@
1115 nor. %2,%1,%1
1116 #"
1117 [(set_attr "type" "compare")
1118 (set_attr "length" "4,8")])
1119
1120(define_split
1121 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1122 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1123 (const_int 0)))
1124 (clobber (match_scratch:SI 2 ""))]
4b8a63d6 1125 "TARGET_32BIT && reload_completed"
52d3af72
DE		 1126 [(set (match_dup 2)
1127 (not:SI (match_dup 1)))
1128 (set (match_dup 0)
1129 (compare:CC (match_dup 2)
1130 (const_int 0)))]
1131 "")
ca7f5001
RK		 1132
1133(define_insn ""
52d3af72
DE		 1134 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1135 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
815cdc52 1136 (const_int 0)))
52d3af72 1137 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52 1138 (not:SI (match_dup 1)))]
4b8a63d6 1139 "TARGET_32BIT"
52d3af72
DE		 1140 "@
1141 nor. %0,%1,%1
1142 #"
1143 [(set_attr "type" "compare")
1144 (set_attr "length" "4,8")])
1145
1146(define_split
1147 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1148 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1149 (const_int 0)))
1cb18e3c 1150 (set (match_operand:SI 0 "gpc_reg_operand" "")
52d3af72 1151 (not:SI (match_dup 1)))]
4b8a63d6 1152 "TARGET_32BIT && reload_completed"
52d3af72
DE		 1153 [(set (match_dup 0)
1154 (not:SI (match_dup 1)))
1155 (set (match_dup 2)
1156 (compare:CC (match_dup 0)
1157 (const_int 0)))]
1158 "")
1fd4e8c1
RK		 1159
1160(define_insn ""
3d91674b
RK		 1161 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1162 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1163 (match_operand:SI 2 "gpc_reg_operand" "r")))]
deb9225a 1164 "! TARGET_POWERPC"
ca7f5001 1165 "{sf%I1|subf%I1c} %0,%2,%1")
1fd4e8c1 1166
deb9225a
RK		 1167(define_insn ""
1168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1169 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1170 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1171 "TARGET_POWERPC"
1172 "@
1173 subf %0,%2,%1
1174 subfic %0,%2,%1")
1175
1fd4e8c1 1176(define_insn ""
cb8cc086
MM		 1177 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1178 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1179 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1180 (const_int 0)))
cb8cc086 1181 (clobber (match_scratch:SI 3 "=r,r"))]
deb9225a 1182 "! TARGET_POWERPC"
cb8cc086
MM		 1183 "@
1184 {sf.|subfc.} %3,%2,%1
1185 #"
1186 [(set_attr "type" "compare")
1187 (set_attr "length" "4,8")])
1fd4e8c1 1188
deb9225a 1189(define_insn ""
cb8cc086
MM		 1190 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1191 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1192 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
deb9225a 1193 (const_int 0)))
cb8cc086 1194 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 1195 "TARGET_POWERPC && TARGET_32BIT"
cb8cc086
MM		 1196 "@
1197 subf. %3,%2,%1
1198 #"
a62bfff2 1199 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1200 (set_attr "length" "4,8")])
1201
1202(define_split
1203 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1204 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1205 (match_operand:SI 2 "gpc_reg_operand" ""))
1206 (const_int 0)))
1207 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 1208 "TARGET_32BIT && reload_completed"
cb8cc086
MM		 1209 [(set (match_dup 3)
1210 (minus:SI (match_dup 1)
1211 (match_dup 2)))
1212 (set (match_dup 0)
1213 (compare:CC (match_dup 3)
1214 (const_int 0)))]
1215 "")
deb9225a 1216
1fd4e8c1 1217(define_insn ""
cb8cc086
MM		 1218 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1219 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1220 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1221 (const_int 0)))
cb8cc086 1222 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 1223 (minus:SI (match_dup 1) (match_dup 2)))]
deb9225a 1224 "! TARGET_POWERPC"
cb8cc086
MM		 1225 "@
1226 {sf.|subfc.} %0,%2,%1
1227 #"
1228 [(set_attr "type" "compare")
1229 (set_attr "length" "4,8")])
815cdc52 1230
29ae5b89 1231(define_insn ""
cb8cc086
MM		 1232 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1233 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1234 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
815cdc52 1235 (const_int 0)))
cb8cc086
MM		 1236 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1237 (minus:SI (match_dup 1)
1238 (match_dup 2)))]
4b8a63d6 1239 "TARGET_POWERPC && TARGET_32BIT"
90612787
DE		 1240 "@
1241 subf. %0,%2,%1
1242 #"
a62bfff2 1243 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1244 (set_attr "length" "4,8")])
1245
1246(define_split
1247 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1248 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1249 (match_operand:SI 2 "gpc_reg_operand" ""))
1250 (const_int 0)))
1251 (set (match_operand:SI 0 "gpc_reg_operand" "")
1252 (minus:SI (match_dup 1)
1253 (match_dup 2)))]
4b8a63d6 1254 "TARGET_32BIT && reload_completed"
cb8cc086
MM		 1255 [(set (match_dup 0)
1256 (minus:SI (match_dup 1)
1257 (match_dup 2)))
1258 (set (match_dup 3)
1259 (compare:CC (match_dup 0)
1260 (const_int 0)))]
1261 "")
deb9225a 1262
1fd4e8c1 1263(define_expand "subsi3"
cd2b37d9 1264 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1265 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
f6bf7de2 1266 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1fd4e8c1 1267 ""
a0044fb1
RK		 1268 "
1269{
1270 if (GET_CODE (operands[2]) == CONST_INT)
1271 {
1272 emit_insn (gen_addsi3 (operands[0], operands[1],
1273 negate_rtx (SImode, operands[2])));
1274 DONE;
1275 }
1276}")
1fd4e8c1
RK		 1277
1278;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1279;; instruction and some auxiliary computations. Then we just have a single
95ac8e67
RK		 1280;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1281;; combine.
1fd4e8c1
RK		 1282
1283(define_expand "sminsi3"
1284 [(set (match_dup 3)
cd2b37d9 1285 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1286 (match_operand:SI 2 "reg_or_short_operand" ""))
1287 (const_int 0)
1288 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1289 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1290 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1291 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1292 "
a3170dc6
AH		 1293{
1294 if (TARGET_ISEL)
1295 {
1296 operands[2] = force_reg (SImode, operands[2]);
1297 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1298 DONE;
1299 }
1300
1301 operands[3] = gen_reg_rtx (SImode);
1302}")
1fd4e8c1 1303
95ac8e67
RK		 1304(define_split
1305 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1306 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1307 (match_operand:SI 2 "reg_or_short_operand" "")))
1308 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1309 "TARGET_POWER"
95ac8e67
RK		 1310 [(set (match_dup 3)
1311 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1312 (const_int 0)
1313 (minus:SI (match_dup 2) (match_dup 1))))
1314 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1315 "")
1316
1fd4e8c1
RK		 1317(define_expand "smaxsi3"
1318 [(set (match_dup 3)
cd2b37d9 1319 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1320 (match_operand:SI 2 "reg_or_short_operand" ""))
1321 (const_int 0)
1322 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1323 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1324 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1325 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1326 "
a3170dc6
AH		 1327{
1328 if (TARGET_ISEL)
1329 {
1330 operands[2] = force_reg (SImode, operands[2]);
1331 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1332 DONE;
1333 }
1334 operands[3] = gen_reg_rtx (SImode);
1335}")
1fd4e8c1 1336
95ac8e67
RK		 1337(define_split
1338 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1339 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1340 (match_operand:SI 2 "reg_or_short_operand" "")))
1341 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1342 "TARGET_POWER"
95ac8e67
RK		 1343 [(set (match_dup 3)
1344 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1345 (const_int 0)
1346 (minus:SI (match_dup 2) (match_dup 1))))
1347 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1348 "")
1349
1fd4e8c1 1350(define_expand "uminsi3"
cd2b37d9 1351 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1352 (match_dup 5)))
cd2b37d9 1353 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1354 (match_dup 5)))
1fd4e8c1
RK		 1355 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1356 (const_int 0)
1357 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1358 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1359 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1360 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1361 "
bb68ff55 1362{
a3170dc6
AH		 1363 if (TARGET_ISEL)
1364 {
1365 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1366 DONE;
1367 }
bb68ff55
MM		 1368 operands[3] = gen_reg_rtx (SImode);
1369 operands[4] = gen_reg_rtx (SImode);
1370 operands[5] = GEN_INT (-2147483647 - 1);
1371}")
1fd4e8c1
RK		 1372
1373(define_expand "umaxsi3"
cd2b37d9 1374 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1375 (match_dup 5)))
cd2b37d9 1376 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1377 (match_dup 5)))
1fd4e8c1
RK		 1378 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1379 (const_int 0)
1380 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1381 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1382 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1383 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1384 "
bb68ff55 1385{
a3170dc6
AH		 1386 if (TARGET_ISEL)
1387 {
1388 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1389 DONE;
1390 }
bb68ff55
MM		 1391 operands[3] = gen_reg_rtx (SImode);
1392 operands[4] = gen_reg_rtx (SImode);
1393 operands[5] = GEN_INT (-2147483647 - 1);
1394}")
1fd4e8c1
RK		 1395
1396(define_insn ""
cd2b37d9
RK		 1397 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1398 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
5c23c401 1399 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 1400 (const_int 0)
1401 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1402 "TARGET_POWER"
1fd4e8c1
RK		 1403 "doz%I2 %0,%1,%2")
1404
1405(define_insn ""
9ebbca7d 1406 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 1407 (compare:CC
9ebbca7d
GK		 1408 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1409 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1410 (const_int 0)
1411 (minus:SI (match_dup 2) (match_dup 1)))
1412 (const_int 0)))
9ebbca7d 1413 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 1414 "TARGET_POWER"
9ebbca7d
GK		 1415 "@
1416 doz%I2. %3,%1,%2
1417 #"
1418 [(set_attr "type" "delayed_compare")
1419 (set_attr "length" "4,8")])
1420
1421(define_split
1422 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1423 (compare:CC
1424 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1425 (match_operand:SI 2 "reg_or_short_operand" ""))
1426 (const_int 0)
1427 (minus:SI (match_dup 2) (match_dup 1)))
1428 (const_int 0)))
1429 (clobber (match_scratch:SI 3 ""))]
1430 "TARGET_POWER && reload_completed"
1431 [(set (match_dup 3)
1432 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1433 (const_int 0)
1434 (minus:SI (match_dup 2) (match_dup 1))))
1435 (set (match_dup 0)
1436 (compare:CC (match_dup 3)
1437 (const_int 0)))]
1438 "")
1fd4e8c1
RK		 1439
1440(define_insn ""
9ebbca7d 1441 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 1442 (compare:CC
9ebbca7d
GK		 1443 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1444 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1445 (const_int 0)
1446 (minus:SI (match_dup 2) (match_dup 1)))
1447 (const_int 0)))
9ebbca7d 1448 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 1449 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1450 (const_int 0)
1451 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1452 "TARGET_POWER"
9ebbca7d
GK		 1453 "@
1454 doz%I2. %0,%1,%2
1455 #"
1456 [(set_attr "type" "delayed_compare")
1457 (set_attr "length" "4,8")])
1458
1459(define_split
1460 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1461 (compare:CC
1462 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1463 (match_operand:SI 2 "reg_or_short_operand" ""))
1464 (const_int 0)
1465 (minus:SI (match_dup 2) (match_dup 1)))
1466 (const_int 0)))
1467 (set (match_operand:SI 0 "gpc_reg_operand" "")
1468 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1469 (const_int 0)
1470 (minus:SI (match_dup 2) (match_dup 1))))]
1471 "TARGET_POWER && reload_completed"
1472 [(set (match_dup 0)
1473 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1474 (const_int 0)
1475 (minus:SI (match_dup 2) (match_dup 1))))
1476 (set (match_dup 3)
1477 (compare:CC (match_dup 0)
1478 (const_int 0)))]
1479 "")
1fd4e8c1
RK		 1480
1481;; We don't need abs with condition code because such comparisons should
1482;; never be done.
ea9be077
MM		 1483(define_expand "abssi2"
1484 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1485 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1486 ""
1487 "
1488{
a3170dc6
AH		 1489 if (TARGET_ISEL)
1490 {
1491 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1492 DONE;
1493 }
1494 else if (! TARGET_POWER)
ea9be077
MM		 1495 {
1496 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1497 DONE;
1498 }
1499}")
1500
ea112fc4 1501(define_insn "*abssi2_power"
cd2b37d9
RK		 1502 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1503 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
ca7f5001 1504 "TARGET_POWER"
1fd4e8c1
RK		 1505 "abs %0,%1")
1506
a3170dc6
AH		 1507(define_insn_and_split "abssi2_isel"
1508 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1509 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8c48b6f5 1510 (clobber (match_scratch:SI 2 "=&b"))
a3170dc6
AH		 1511 (clobber (match_scratch:CC 3 "=y"))]
1512 "TARGET_ISEL"
1513 "#"
1514 "&& reload_completed"
1515 [(set (match_dup 2) (neg:SI (match_dup 1)))
1516 (set (match_dup 3)
1517 (compare:CC (match_dup 1)
1518 (const_int 0)))
1519 (set (match_dup 0)
1520 (if_then_else:SI (ge (match_dup 3)
1521 (const_int 0))
1522 (match_dup 1)
1523 (match_dup 2)))]
1524 "")
1525
ea112fc4 1526(define_insn_and_split "abssi2_nopower"
ea9be077 1527 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 1528 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
ea9be077 1529 (clobber (match_scratch:SI 2 "=&r,&r"))]
a3170dc6 1530 "! TARGET_POWER && ! TARGET_ISEL"
ea112fc4
DE		 1531 "#"
1532 "&& reload_completed"
ea9be077
MM		 1533 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1534 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 1535 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
ea9be077
MM		 1536 "")
1537
463b558b 1538(define_insn "*nabs_power"
cd2b37d9
RK		 1539 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1540 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
ca7f5001 1541 "TARGET_POWER"
1fd4e8c1
RK		 1542 "nabs %0,%1")
1543
ea112fc4 1544(define_insn_and_split "*nabs_nopower"
ea9be077 1545 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 1546 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
ea9be077 1547 (clobber (match_scratch:SI 2 "=&r,&r"))]
0ad91047 1548 "! TARGET_POWER"
ea112fc4
DE		 1549 "#"
1550 "&& reload_completed"
ea9be077
MM		 1551 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1552 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 1553 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
ea9be077
MM		 1554 "")
1555
1fd4e8c1 1556(define_insn "negsi2"
cd2b37d9
RK		 1557 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1558 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1fd4e8c1
RK		 1559 ""
1560 "neg %0,%1")
1561
1562(define_insn ""
9ebbca7d
GK		 1563 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1564 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 1565 (const_int 0)))
9ebbca7d 1566 (clobber (match_scratch:SI 2 "=r,r"))]
4b8a63d6 1567 "TARGET_32BIT"
9ebbca7d
GK		 1568 "@
1569 neg. %2,%1
1570 #"
a62bfff2 1571 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 1572 (set_attr "length" "4,8")])
1573
1574(define_split
1575 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1576 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1577 (const_int 0)))
1578 (clobber (match_scratch:SI 2 ""))]
4b8a63d6 1579 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 1580 [(set (match_dup 2)
1581 (neg:SI (match_dup 1)))
1582 (set (match_dup 0)
1583 (compare:CC (match_dup 2)
1584 (const_int 0)))]
1585 "")
1fd4e8c1
RK		 1586
1587(define_insn ""
9ebbca7d
GK		 1588 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1589 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
815cdc52 1590 (const_int 0)))
9ebbca7d 1591 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52 1592 (neg:SI (match_dup 1)))]
4b8a63d6 1593 "TARGET_32BIT"
9ebbca7d
GK		 1594 "@
1595 neg. %0,%1
1596 #"
a62bfff2 1597 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 1598 (set_attr "length" "4,8")])
1599
1600(define_split
1601 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1602 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1603 (const_int 0)))
1604 (set (match_operand:SI 0 "gpc_reg_operand" "")
1605 (neg:SI (match_dup 1)))]
4b8a63d6 1606 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 1607 [(set (match_dup 0)
1608 (neg:SI (match_dup 1)))
1609 (set (match_dup 2)
1610 (compare:CC (match_dup 0)
1611 (const_int 0)))]
1612 "")
1fd4e8c1 1613
1b1edcfa
DE		 1614(define_insn "clzsi2"
1615 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1616 (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1617 ""
1618 "{cntlz|cntlzw} %0,%1")
1619
1620(define_expand "ctzsi2"
4977bab6 1621 [(set (match_dup 2)
1b1edcfa 1622 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
4977bab6 1623 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1b1edcfa
DE		 1624 (match_dup 2)))
1625 (clobber (scratch:CC))])
d865b122 1626 (set (match_dup 4) (clz:SI (match_dup 3)))
4977bab6 1627 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1b1edcfa 1628 (minus:SI (const_int 31) (match_dup 4)))]
1fd4e8c1 1629 ""
4977bab6
ZW		 1630 {
1631 operands[2] = gen_reg_rtx (SImode);
1632 operands[3] = gen_reg_rtx (SImode);
1633 operands[4] = gen_reg_rtx (SImode);
1634 })
1635
1b1edcfa
DE		 1636(define_expand "ffssi2"
1637 [(set (match_dup 2)
1638 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1639 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
1640 (match_dup 2)))
1641 (clobber (scratch:CC))])
1642 (set (match_dup 4) (clz:SI (match_dup 3)))
1643 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1644 (minus:SI (const_int 32) (match_dup 4)))]
4977bab6 1645 ""
1b1edcfa
DE		 1646 {
1647 operands[2] = gen_reg_rtx (SImode);
1648 operands[3] = gen_reg_rtx (SImode);
1649 operands[4] = gen_reg_rtx (SImode);
1650 })
1651
ca7f5001
RK		 1652(define_expand "mulsi3"
1653 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1654 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1655 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1656 ""
1657 "
1658{
1659 if (TARGET_POWER)
68b40e7e 1660 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
ca7f5001 1661 else
68b40e7e 1662 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
ca7f5001
RK		 1663 DONE;
1664}")
1665
68b40e7e 1666(define_insn "mulsi3_mq"
cd2b37d9
RK		 1667 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1668 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1fd4e8c1
RK		 1669 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1670 (clobber (match_scratch:SI 3 "=q,q"))]
ca7f5001
RK		 1671 "TARGET_POWER"
1672 "@
1673 {muls|mullw} %0,%1,%2
1674 {muli|mulli} %0,%1,%2"
c859cda6
DJ		 1675 [(set (attr "type")
1676 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1677 (const_string "imul3")
1678 (match_operand:SI 2 "short_cint_operand" "")
1679 (const_string "imul2")]
1680 (const_string "imul")))])
ca7f5001 1681
68b40e7e 1682(define_insn "mulsi3_no_mq"
ca7f5001
RK		 1683 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1684 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1685 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
68b40e7e 1686 "! TARGET_POWER"
1fd4e8c1 1687 "@
d904e9ed
RK		 1688 {muls|mullw} %0,%1,%2
1689 {muli|mulli} %0,%1,%2"
c859cda6
DJ		 1690 [(set (attr "type")
1691 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
1692 (const_string "imul3")
1693 (match_operand:SI 2 "short_cint_operand" "")
1694 (const_string "imul2")]
1695 (const_string "imul")))])
1fd4e8c1 1696
9259f3b0 1697(define_insn "*mulsi3_mq_internal1"
9ebbca7d
GK		 1698 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1699 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1700 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1701 (const_int 0)))
9ebbca7d
GK		 1702 (clobber (match_scratch:SI 3 "=r,r"))
1703 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 1704 "TARGET_POWER"
9ebbca7d
GK		 1705 "@
1706 {muls.|mullw.} %3,%1,%2
1707 #"
9259f3b0 1708 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 1709 (set_attr "length" "4,8")])
1710
1711(define_split
1712 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1713 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1714 (match_operand:SI 2 "gpc_reg_operand" ""))
1715 (const_int 0)))
1716 (clobber (match_scratch:SI 3 ""))
1717 (clobber (match_scratch:SI 4 ""))]
1718 "TARGET_POWER && reload_completed"
1719 [(parallel [(set (match_dup 3)
1720 (mult:SI (match_dup 1) (match_dup 2)))
1721 (clobber (match_dup 4))])
1722 (set (match_dup 0)
1723 (compare:CC (match_dup 3)
1724 (const_int 0)))]
1725 "")
ca7f5001 1726
9259f3b0 1727(define_insn "*mulsi3_no_mq_internal1"
9ebbca7d
GK		 1728 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1729 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1730 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 1731 (const_int 0)))
9ebbca7d 1732 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 1733 "! TARGET_POWER"
9ebbca7d
GK		 1734 "@
1735 {muls.|mullw.} %3,%1,%2
1736 #"
9259f3b0 1737 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 1738 (set_attr "length" "4,8")])
1739
1740(define_split
1741 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1742 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1743 (match_operand:SI 2 "gpc_reg_operand" ""))
1744 (const_int 0)))
1745 (clobber (match_scratch:SI 3 ""))]
1746 "! TARGET_POWER && reload_completed"
1747 [(set (match_dup 3)
1748 (mult:SI (match_dup 1) (match_dup 2)))
1749 (set (match_dup 0)
1750 (compare:CC (match_dup 3)
1751 (const_int 0)))]
1752 "")
1fd4e8c1 1753
9259f3b0 1754(define_insn "*mulsi3_mq_internal2"
9ebbca7d
GK		 1755 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1756 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1757 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1758 (const_int 0)))
9ebbca7d 1759 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
29ae5b89 1760 (mult:SI (match_dup 1) (match_dup 2)))
9ebbca7d 1761 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 1762 "TARGET_POWER"
9ebbca7d
GK		 1763 "@
1764 {muls.|mullw.} %0,%1,%2
1765 #"
9259f3b0 1766 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 1767 (set_attr "length" "4,8")])
1768
1769(define_split
1770 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1771 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1772 (match_operand:SI 2 "gpc_reg_operand" ""))
1773 (const_int 0)))
1774 (set (match_operand:SI 0 "gpc_reg_operand" "")
1775 (mult:SI (match_dup 1) (match_dup 2)))
1776 (clobber (match_scratch:SI 4 ""))]
1777 "TARGET_POWER && reload_completed"
1778 [(parallel [(set (match_dup 0)
1779 (mult:SI (match_dup 1) (match_dup 2)))
1780 (clobber (match_dup 4))])
1781 (set (match_dup 3)
1782 (compare:CC (match_dup 0)
1783 (const_int 0)))]
1784 "")
ca7f5001 1785
9259f3b0 1786(define_insn "*mulsi3_no_mq_internal2"
9ebbca7d
GK		 1787 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1788 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1789 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 1790 (const_int 0)))
9ebbca7d 1791 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 1792 (mult:SI (match_dup 1) (match_dup 2)))]
25c341fa 1793 "! TARGET_POWER"
9ebbca7d
GK		 1794 "@
1795 {muls.|mullw.} %0,%1,%2
1796 #"
9259f3b0 1797 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 1798 (set_attr "length" "4,8")])
1799
1800(define_split
1801 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1802 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
1803 (match_operand:SI 2 "gpc_reg_operand" ""))
1804 (const_int 0)))
1805 (set (match_operand:SI 0 "gpc_reg_operand" "")
1806 (mult:SI (match_dup 1) (match_dup 2)))]
1807 "! TARGET_POWER && reload_completed"
1808 [(set (match_dup 0)
1809 (mult:SI (match_dup 1) (match_dup 2)))
1810 (set (match_dup 3)
1811 (compare:CC (match_dup 0)
1812 (const_int 0)))]
1813 "")
1fd4e8c1
RK		 1814
1815;; Operand 1 is divided by operand 2; quotient goes to operand
1816;; 0 and remainder to operand 3.
1817;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1818
8ffd9c51
RK		 1819(define_expand "divmodsi4"
1820 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1821 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1822 (match_operand:SI 2 "gpc_reg_operand" "")))
bb157ff4 1823 (set (match_operand:SI 3 "register_operand" "")
8ffd9c51
RK		 1824 (mod:SI (match_dup 1) (match_dup 2)))])]
1825 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1826 "
1827{
1828 if (! TARGET_POWER && ! TARGET_POWERPC)
1829 {
39403d82
DE		 1830 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1831 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 1832 emit_insn (gen_divss_call ());
39403d82
DE		 1833 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
1834 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
8ffd9c51
RK		 1835 DONE;
1836 }
1837}")
deb9225a 1838
bb157ff4 1839(define_insn "*divmodsi4_internal"
cd2b37d9
RK		 1840 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1841 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1842 (match_operand:SI 2 "gpc_reg_operand" "r")))
bb157ff4 1843 (set (match_operand:SI 3 "register_operand" "=q")
1fd4e8c1 1844 (mod:SI (match_dup 1) (match_dup 2)))]
ca7f5001 1845 "TARGET_POWER"
cfb557c4
RK		 1846 "divs %0,%1,%2"
1847 [(set_attr "type" "idiv")])
1fd4e8c1 1848
8ffd9c51
RK		 1849(define_expand "udivsi3"
1850 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1851 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1852 (match_operand:SI 2 "gpc_reg_operand" "")))]
1853 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1854 "
1855{
1856 if (! TARGET_POWER && ! TARGET_POWERPC)
1857 {
39403d82
DE		 1858 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1859 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 1860 emit_insn (gen_quous_call ());
39403d82 1861 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 1862 DONE;
1863 }
f192bf8b
DE		 1864 else if (TARGET_POWER)
1865 {
1866 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
1867 DONE;
1868 }
8ffd9c51 1869}")
deb9225a 1870
f192bf8b
DE		 1871(define_insn "udivsi3_mq"
1872 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1873 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1874 (match_operand:SI 2 "gpc_reg_operand" "r")))
1875 (clobber (match_scratch:SI 3 "=q"))]
1876 "TARGET_POWERPC && TARGET_POWER"
1877 "divwu %0,%1,%2"
1878 [(set_attr "type" "idiv")])
1879
1880(define_insn "*udivsi3_no_mq"
ca7f5001
RK		 1881 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1882 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1883 (match_operand:SI 2 "gpc_reg_operand" "r")))]
f192bf8b 1884 "TARGET_POWERPC && ! TARGET_POWER"
a473029f 1885 "divwu %0,%1,%2"
ca7f5001
RK		 1886 [(set_attr "type" "idiv")])
1887
1fd4e8c1 1888;; For powers of two we can do srai/aze for divide and then adjust for
ca7f5001 1889;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
8ffd9c51
RK		 1890;; used; for PowerPC, force operands into register and do a normal divide;
1891;; for AIX common-mode, use quoss call on register operands.
1fd4e8c1 1892(define_expand "divsi3"
cd2b37d9
RK		 1893 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1894 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1895 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1896 ""
1897 "
1898{
ca7f5001 1899 if (GET_CODE (operands[2]) == CONST_INT
2bfcf297 1900 && INTVAL (operands[2]) > 0
ca7f5001
RK		 1901 && exact_log2 (INTVAL (operands[2])) >= 0)
1902 ;
b6c9286a 1903 else if (TARGET_POWERPC)
f192bf8b
DE		 1904 {
1905 operands[2] = force_reg (SImode, operands[2]);
1906 if (TARGET_POWER)
1907 {
1908 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
1909 DONE;
1910 }
1911 }
b6c9286a 1912 else if (TARGET_POWER)
1fd4e8c1 1913 FAIL;
405c5495 1914 else
8ffd9c51 1915 {
39403d82
DE		 1916 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
1917 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 1918 emit_insn (gen_quoss_call ());
39403d82 1919 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 1920 DONE;
1921 }
1fd4e8c1
RK		 1922}")
1923
f192bf8b
DE		 1924(define_insn "divsi3_mq"
1925 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1926 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1927 (match_operand:SI 2 "gpc_reg_operand" "r")))
1928 (clobber (match_scratch:SI 3 "=q"))]
1929 "TARGET_POWERPC && TARGET_POWER"
1930 "divw %0,%1,%2"
1931 [(set_attr "type" "idiv")])
1932
1933(define_insn "*divsi3_no_mq"
1934 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1935 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1936 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1937 "TARGET_POWERPC && ! TARGET_POWER"
1938 "divw %0,%1,%2"
1939 [(set_attr "type" "idiv")])
1940
1fd4e8c1 1941(define_expand "modsi3"
85644414
RK		 1942 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1943 (use (match_operand:SI 1 "gpc_reg_operand" ""))
405c5495 1944 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
39b52ba2 1945 ""
1fd4e8c1
RK		 1946 "
1947{
481c7efa 1948 int i;
39b52ba2
RK		 1949 rtx temp1;
1950 rtx temp2;
1951
2bfcf297 1952 if (GET_CODE (operands[2]) != CONST_INT
a65c591c 1953 || INTVAL (operands[2]) <= 0
2bfcf297 1954 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
39b52ba2
RK		 1955 FAIL;
1956
1957 temp1 = gen_reg_rtx (SImode);
1958 temp2 = gen_reg_rtx (SImode);
1fd4e8c1 1959
85644414 1960 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
39b52ba2 1961 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
85644414
RK		 1962 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1963 DONE;
1fd4e8c1
RK		 1964}")
1965
1966(define_insn ""
cd2b37d9
RK		 1967 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1968 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2bfcf297
DB		 1969 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
1970 ""
ca7f5001 1971 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
b19003d8 1972 [(set_attr "length" "8")])
1fd4e8c1
RK		 1973
1974(define_insn ""
9ebbca7d
GK		 1975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1976 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2bfcf297 1977 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
b6b12107 1978 (const_int 0)))
9ebbca7d 1979 (clobber (match_scratch:SI 3 "=r,r"))]
2bfcf297 1980 ""
9ebbca7d
GK		 1981 "@
1982 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
1983 #"
b19003d8 1984 [(set_attr "type" "compare")
9ebbca7d
GK		 1985 (set_attr "length" "8,12")])
1986
1987(define_split
1988 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1989 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2bfcf297 1990 (match_operand:SI 2 "exact_log2_cint_operand" ""))
9ebbca7d
GK		 1991 (const_int 0)))
1992 (clobber (match_scratch:SI 3 ""))]
2bfcf297 1993 "reload_completed"
9ebbca7d
GK		 1994 [(set (match_dup 3)
1995 (div:SI (match_dup 1) (match_dup 2)))
1996 (set (match_dup 0)
1997 (compare:CC (match_dup 3)
1998 (const_int 0)))]
1999 "")
1fd4e8c1
RK		 2000
2001(define_insn ""
9ebbca7d
GK		 2002 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2003 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2bfcf297 2004 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2005 (const_int 0)))
9ebbca7d 2006 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
29ae5b89 2007 (div:SI (match_dup 1) (match_dup 2)))]
2bfcf297 2008 ""
9ebbca7d
GK		 2009 "@
2010 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2011 #"
b19003d8 2012 [(set_attr "type" "compare")
9ebbca7d
GK		 2013 (set_attr "length" "8,12")])
2014
2015(define_split
2016 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2017 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2bfcf297 2018 (match_operand:SI 2 "exact_log2_cint_operand" ""))
9ebbca7d
GK		 2019 (const_int 0)))
2020 (set (match_operand:SI 0 "gpc_reg_operand" "")
2021 (div:SI (match_dup 1) (match_dup 2)))]
2bfcf297 2022 "reload_completed"
9ebbca7d
GK		 2023 [(set (match_dup 0)
2024 (div:SI (match_dup 1) (match_dup 2)))
2025 (set (match_dup 3)
2026 (compare:CC (match_dup 0)
2027 (const_int 0)))]
2028 "")
1fd4e8c1
RK		 2029
2030(define_insn ""
cd2b37d9 2031 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 2032 (udiv:SI
996a5f59 2033 (plus:DI (ashift:DI
cd2b37d9 2034 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 2035 (const_int 32))
23a900dc 2036 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
cd2b37d9 2037 (match_operand:SI 3 "gpc_reg_operand" "r")))
740ab4a2 2038 (set (match_operand:SI 2 "register_operand" "=*q")
1fd4e8c1 2039 (umod:SI
996a5f59 2040 (plus:DI (ashift:DI
1fd4e8c1 2041 (zero_extend:DI (match_dup 1)) (const_int 32))
740ab4a2 2042 (zero_extend:DI (match_dup 4)))
1fd4e8c1 2043 (match_dup 3)))]
ca7f5001 2044 "TARGET_POWER"
cfb557c4
RK		 2045 "div %0,%1,%3"
2046 [(set_attr "type" "idiv")])
1fd4e8c1
RK		 2047
2048;; To do unsigned divide we handle the cases of the divisor looking like a
2049;; negative number. If it is a constant that is less than 2**31, we don't
2050;; have to worry about the branches. So make a few subroutines here.
2051;;
2052;; First comes the normal case.
2053(define_expand "udivmodsi4_normal"
2054 [(set (match_dup 4) (const_int 0))
2055 (parallel [(set (match_operand:SI 0 "" "")
996a5f59 2056 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2057 (const_int 32))
2058 (zero_extend:DI (match_operand:SI 1 "" "")))
2059 (match_operand:SI 2 "" "")))
2060 (set (match_operand:SI 3 "" "")
996a5f59 2061 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2062 (const_int 32))
2063 (zero_extend:DI (match_dup 1)))
2064 (match_dup 2)))])]
ca7f5001 2065 "TARGET_POWER"
1fd4e8c1
RK		 2066 "
2067{ operands[4] = gen_reg_rtx (SImode); }")
2068
2069;; This handles the branches.
2070(define_expand "udivmodsi4_tests"
2071 [(set (match_operand:SI 0 "" "") (const_int 0))
2072 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2073 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2074 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2075 (label_ref (match_operand:SI 4 "" "")) (pc)))
2076 (set (match_dup 0) (const_int 1))
2077 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2078 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2079 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2080 (label_ref (match_dup 4)) (pc)))]
ca7f5001 2081 "TARGET_POWER"
1fd4e8c1
RK		 2082 "
2083{ operands[5] = gen_reg_rtx (CCUNSmode);
2084 operands[6] = gen_reg_rtx (CCmode);
2085}")
2086
2087(define_expand "udivmodsi4"
cd2b37d9
RK		 2088 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2089 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 2090 (match_operand:SI 2 "reg_or_cint_operand" "")))
cd2b37d9 2091 (set (match_operand:SI 3 "gpc_reg_operand" "")
1fd4e8c1 2092 (umod:SI (match_dup 1) (match_dup 2)))])]
8ffd9c51 2093 ""
1fd4e8c1
RK		 2094 "
2095{
2096 rtx label = 0;
2097
8ffd9c51 2098 if (! TARGET_POWER)
c4d38ccb
MM		 2099 {
2100 if (! TARGET_POWERPC)
2101 {
39403d82
DE		 2102 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2103 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
c4d38ccb 2104 emit_insn (gen_divus_call ());
39403d82
DE		 2105 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2106 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
c4d38ccb
MM		 2107 DONE;
2108 }
2109 else
2110 FAIL;
2111 }
0081a354 2112
1fd4e8c1
RK		 2113 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2114 {
2115 operands[2] = force_reg (SImode, operands[2]);
2116 label = gen_label_rtx ();
2117 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2118 operands[3], label));
2119 }
2120 else
2121 operands[2] = force_reg (SImode, operands[2]);
2122
2123 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2124 operands[3]));
2125 if (label)
2126 emit_label (label);
2127
2128 DONE;
2129}")
0081a354 2130
fada905b
MM		 2131;; AIX architecture-independent common-mode multiply (DImode),
2132;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2133;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2134;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2135;; assumed unused if generating common-mode, so ignore.
2136(define_insn "mulh_call"
2137 [(set (reg:SI 3)
2138 (truncate:SI
2139 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2140 (sign_extend:DI (reg:SI 4)))
2141 (const_int 32))))
cf27b467 2142 (clobber (match_scratch:SI 0 "=l"))]
fada905b 2143 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2144 "bla __mulh"
2145 [(set_attr "type" "imul")])
fada905b
MM		 2146
2147(define_insn "mull_call"
2148 [(set (reg:DI 3)
2149 (mult:DI (sign_extend:DI (reg:SI 3))
2150 (sign_extend:DI (reg:SI 4))))
2151 (clobber (match_scratch:SI 0 "=l"))
2152 (clobber (reg:SI 0))]
2153 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2154 "bla __mull"
2155 [(set_attr "type" "imul")])
fada905b
MM		 2156
2157(define_insn "divss_call"
2158 [(set (reg:SI 3)
2159 (div:SI (reg:SI 3) (reg:SI 4)))
2160 (set (reg:SI 4)
2161 (mod:SI (reg:SI 3) (reg:SI 4)))
2162 (clobber (match_scratch:SI 0 "=l"))
2163 (clobber (reg:SI 0))]
2164 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2165 "bla __divss"
2166 [(set_attr "type" "idiv")])
fada905b
MM		 2167
2168(define_insn "divus_call"
8ffd9c51
RK		 2169 [(set (reg:SI 3)
2170 (udiv:SI (reg:SI 3) (reg:SI 4)))
2171 (set (reg:SI 4)
2172 (umod:SI (reg:SI 3) (reg:SI 4)))
2173 (clobber (match_scratch:SI 0 "=l"))
fada905b
MM		 2174 (clobber (reg:SI 0))
2175 (clobber (match_scratch:CC 1 "=x"))
2176 (clobber (reg:CC 69))]
2177 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2178 "bla __divus"
2179 [(set_attr "type" "idiv")])
fada905b
MM		 2180
2181(define_insn "quoss_call"
2182 [(set (reg:SI 3)
2183 (div:SI (reg:SI 3) (reg:SI 4)))
cf27b467 2184 (clobber (match_scratch:SI 0 "=l"))]
8ffd9c51 2185 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2186 "bla __quoss"
2187 [(set_attr "type" "idiv")])
0081a354 2188
fada905b
MM		 2189(define_insn "quous_call"
2190 [(set (reg:SI 3)
2191 (udiv:SI (reg:SI 3) (reg:SI 4)))
2192 (clobber (match_scratch:SI 0 "=l"))
2193 (clobber (reg:SI 0))
2194 (clobber (match_scratch:CC 1 "=x"))
2195 (clobber (reg:CC 69))]
2196 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2197 "bla __quous"
2198 [(set_attr "type" "idiv")])
8ffd9c51 2199\f
bb21487f 2200;; Logical instructions
dfbdccdb
GK		 2201;; The logical instructions are mostly combined by using match_operator,
2202;; but the plain AND insns are somewhat different because there is no
2203;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2204;; those rotate-and-mask operations. Thus, the AND insns come first.
2205
29ae5b89
JL		 2206(define_insn "andsi3"
2207 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2208 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
5f59ecb7 2209 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
29ae5b89 2210 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1fd4e8c1
RK		 2211 ""
2212 "@
2213 and %0,%1,%2
ca7f5001
RK		 2214 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2215 {andil.|andi.} %0,%1,%b2
9ebbca7d 2216 {andiu.|andis.} %0,%1,%u2")
52d3af72
DE		 2217
2218;; Note to set cr's other than cr0 we do the and immediate and then
0ba1b2ff 2219;; the test again -- this avoids a mfcr which on the higher end
52d3af72 2220;; machines causes an execution serialization
1fd4e8c1 2221
7cd5235b 2222(define_insn "*andsi3_internal2"
52d3af72
DE		 2223 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2224 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2225 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
1fd4e8c1 2226 (const_int 0)))
52d3af72
DE		 2227 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2228 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2229 "TARGET_32BIT"
1fd4e8c1
RK		 2230 "@
2231 and. %3,%1,%2
ca7f5001
RK		 2232 {andil.|andi.} %3,%1,%b2
2233 {andiu.|andis.} %3,%1,%u2
52d3af72
DE		 2234 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2235 #
2236 #
2237 #
2238 #"
2239 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2240 (set_attr "length" "4,4,4,4,8,8,8,8")])
1fd4e8c1 2241
0ba1b2ff
AM		 2242(define_insn "*andsi3_internal3"
2243 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2244 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2245 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2246 (const_int 0)))
2247 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2248 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2249 "TARGET_64BIT"
0ba1b2ff
AM		 2250 "@
2251 #
2252 {andil.|andi.} %3,%1,%b2
2253 {andiu.|andis.} %3,%1,%u2
2254 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2255 #
2256 #
2257 #
2258 #"
2259 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2260 (set_attr "length" "8,4,4,4,8,8,8,8")])
2261
52d3af72
DE		 2262(define_split
2263 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2264 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2265 (match_operand:SI 2 "and_operand" ""))
1fd4e8c1 2266 (const_int 0)))
52d3af72
DE		 2267 (clobber (match_scratch:SI 3 ""))
2268 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2269 "reload_completed"
52d3af72
DE		 2270 [(parallel [(set (match_dup 3)
2271 (and:SI (match_dup 1)
2272 (match_dup 2)))
2273 (clobber (match_dup 4))])
2274 (set (match_dup 0)
2275 (compare:CC (match_dup 3)
2276 (const_int 0)))]
2277 "")
2278
0ba1b2ff
AM		 2279;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2280;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2281
2282(define_split
2283 [(set (match_operand:CC 0 "cc_reg_operand" "")
2284 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2285 (match_operand:SI 2 "gpc_reg_operand" ""))
2286 (const_int 0)))
2287 (clobber (match_scratch:SI 3 ""))
2288 (clobber (match_scratch:CC 4 ""))]
2289 "TARGET_POWERPC64 && reload_completed"
2290 [(parallel [(set (match_dup 3)
2291 (and:SI (match_dup 1)
2292 (match_dup 2)))
2293 (clobber (match_dup 4))])
2294 (set (match_dup 0)
2295 (compare:CC (match_dup 3)
2296 (const_int 0)))]
2297 "")
2298
2299(define_insn "*andsi3_internal4"
52d3af72
DE		 2300 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2301 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2302 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
52d3af72
DE		 2303 (const_int 0)))
2304 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2305 (and:SI (match_dup 1)
2306 (match_dup 2)))
2307 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2308 "TARGET_32BIT"
1fd4e8c1
RK		 2309 "@
2310 and. %0,%1,%2
ca7f5001
RK		 2311 {andil.|andi.} %0,%1,%b2
2312 {andiu.|andis.} %0,%1,%u2
52d3af72
DE		 2313 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2314 #
2315 #
2316 #
2317 #"
2318 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2319 (set_attr "length" "4,4,4,4,8,8,8,8")])
2320
0ba1b2ff
AM		 2321(define_insn "*andsi3_internal5"
2322 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2323 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2324 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2325 (const_int 0)))
2326 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2327 (and:SI (match_dup 1)
2328 (match_dup 2)))
2329 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2330 "TARGET_64BIT"
0ba1b2ff
AM		 2331 "@
2332 #
2333 {andil.|andi.} %0,%1,%b2
2334 {andiu.|andis.} %0,%1,%u2
2335 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2336 #
2337 #
2338 #
2339 #"
2340 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2341 (set_attr "length" "8,4,4,4,8,8,8,8")])
2342
52d3af72
DE		 2343(define_split
2344 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2345 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2346 (match_operand:SI 2 "and_operand" ""))
2347 (const_int 0)))
2348 (set (match_operand:SI 0 "gpc_reg_operand" "")
2349 (and:SI (match_dup 1)
2350 (match_dup 2)))
2351 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2352 "reload_completed"
52d3af72
DE		 2353 [(parallel [(set (match_dup 0)
2354 (and:SI (match_dup 1)
2355 (match_dup 2)))
2356 (clobber (match_dup 4))])
2357 (set (match_dup 3)
2358 (compare:CC (match_dup 0)
2359 (const_int 0)))]
2360 "")
1fd4e8c1 2361
0ba1b2ff
AM		 2362(define_split
2363 [(set (match_operand:CC 3 "cc_reg_operand" "")
2364 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2365 (match_operand:SI 2 "gpc_reg_operand" ""))
2366 (const_int 0)))
2367 (set (match_operand:SI 0 "gpc_reg_operand" "")
2368 (and:SI (match_dup 1)
2369 (match_dup 2)))
2370 (clobber (match_scratch:CC 4 ""))]
2371 "TARGET_POWERPC64 && reload_completed"
2372 [(parallel [(set (match_dup 0)
2373 (and:SI (match_dup 1)
2374 (match_dup 2)))
2375 (clobber (match_dup 4))])
2376 (set (match_dup 3)
2377 (compare:CC (match_dup 0)
2378 (const_int 0)))]
2379 "")
2380
2381;; Handle the PowerPC64 rlwinm corner case
2382
2383(define_insn_and_split "*andsi3_internal6"
2384 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2385 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2386 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2387 "TARGET_POWERPC64"
2388 "#"
2389 "TARGET_POWERPC64"
2390 [(set (match_dup 0)
2391 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2392 (match_dup 4)))
2393 (set (match_dup 0)
2394 (rotate:SI (match_dup 0) (match_dup 5)))]
2395 "
2396{
2397 int mb = extract_MB (operands[2]);
2398 int me = extract_ME (operands[2]);
2399 operands[3] = GEN_INT (me + 1);
2400 operands[5] = GEN_INT (32 - (me + 1));
2401 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2402}"
2403 [(set_attr "length" "8")])
2404
2405(define_insn_and_split "*andsi3_internal7"
2406 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2407 (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r")
2408 (match_operand:SI 1 "mask_operand_wrap" "i,i"))
2409 (const_int 0)))
2410 (clobber (match_scratch:SI 3 "=r,r"))]
2411 "TARGET_POWERPC64"
2412 "#"
2413 "TARGET_POWERPC64"
2414 [(parallel [(set (match_dup 2)
2415 (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4))
2416 (match_dup 5))
2417 (const_int 0)))
2418 (clobber (match_dup 3))])]
2419 "
2420{
2421 int mb = extract_MB (operands[1]);
2422 int me = extract_ME (operands[1]);
2423 operands[4] = GEN_INT (me + 1);
2424 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2425}"
2426 [(set_attr "type" "delayed_compare,compare")
2427 (set_attr "length" "4,8")])
2428
2429(define_insn_and_split "*andsi3_internal8"
2430 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
2431 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2432 (match_operand:SI 2 "mask_operand_wrap" "i,i"))
2433 (const_int 0)))
2434 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2435 (and:SI (match_dup 1)
2436 (match_dup 2)))]
2437 "TARGET_POWERPC64"
2438 "#"
2439 "TARGET_POWERPC64"
2440 [(parallel [(set (match_dup 3)
2441 (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2442 (match_dup 5))
2443 (const_int 0)))
2444 (set (match_dup 0)
2445 (and:SI (rotate:SI (match_dup 1) (match_dup 4))
2446 (match_dup 5)))])
2447 (set (match_dup 0)
2448 (rotate:SI (match_dup 0) (match_dup 6)))]
2449 "
2450{
2451 int mb = extract_MB (operands[2]);
2452 int me = extract_ME (operands[2]);
2453 operands[4] = GEN_INT (me + 1);
2454 operands[6] = GEN_INT (32 - (me + 1));
2455 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2456}"
2457 [(set_attr "type" "delayed_compare,compare")
2458 (set_attr "length" "8,12")])
2459
7cd5235b 2460(define_expand "iorsi3"
cd2b37d9 2461 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 2462 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 2463 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
7cd5235b 2464 ""
f357808b
RK		 2465 "
2466{
7cd5235b 2467 if (GET_CODE (operands[2]) == CONST_INT
677a9668 2468 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 2469 {
2470 HOST_WIDE_INT value = INTVAL (operands[2]);
677a9668 2471 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 2472 ? operands[0] : gen_reg_rtx (SImode));
2473
a260abc9
DE		 2474 emit_insn (gen_iorsi3 (tmp, operands[1],
2475 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2476 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 2477 DONE;
2478 }
f357808b
RK		 2479}")
2480
7cd5235b 2481(define_expand "xorsi3"
cd2b37d9 2482 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 2483 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 2484 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
1fd4e8c1 2485 ""
7cd5235b 2486 "
1fd4e8c1 2487{
7cd5235b 2488 if (GET_CODE (operands[2]) == CONST_INT
677a9668 2489 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 2490 {
2491 HOST_WIDE_INT value = INTVAL (operands[2]);
677a9668 2492 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 2493 ? operands[0] : gen_reg_rtx (SImode));
2494
a260abc9
DE		 2495 emit_insn (gen_xorsi3 (tmp, operands[1],
2496 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2497 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 2498 DONE;
2499 }
1fd4e8c1
RK		 2500}")
2501
dfbdccdb 2502(define_insn "*boolsi3_internal1"
7cd5235b 2503 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 2504 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 2505 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2506 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
1fd4e8c1
RK		 2507 ""
2508 "@
dfbdccdb
GK		 2509 %q3 %0,%1,%2
2510 {%q3il|%q3i} %0,%1,%b2
2511 {%q3iu|%q3is} %0,%1,%u2")
1fd4e8c1 2512
dfbdccdb 2513(define_insn "*boolsi3_internal2"
52d3af72 2514 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 2515 (compare:CC (match_operator:SI 4 "boolean_or_operator"
dfbdccdb
GK		 2516 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2517 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2518 (const_int 0)))
52d3af72 2519 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 2520 "TARGET_32BIT"
52d3af72 2521 "@
dfbdccdb 2522 %q4. %3,%1,%2
52d3af72
DE		 2523 #"
2524 [(set_attr "type" "compare")
2525 (set_attr "length" "4,8")])
2526
2527(define_split
2528 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 2529 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2530 [(match_operand:SI 1 "gpc_reg_operand" "")
2531 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2532 (const_int 0)))
52d3af72 2533 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 2534 "TARGET_32BIT && reload_completed"
dfbdccdb 2535 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 2536 (set (match_dup 0)
2537 (compare:CC (match_dup 3)
2538 (const_int 0)))]
2539 "")
815cdc52 2540
dfbdccdb 2541(define_insn "*boolsi3_internal3"
52d3af72 2542 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2543 (compare:CC (match_operator:SI 4 "boolean_operator"
2544 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2545 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2546 (const_int 0)))
52d3af72 2547 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 2548 (match_dup 4))]
4b8a63d6 2549 "TARGET_32BIT"
52d3af72 2550 "@
dfbdccdb 2551 %q4. %0,%1,%2
52d3af72
DE		 2552 #"
2553 [(set_attr "type" "compare")
2554 (set_attr "length" "4,8")])
2555
2556(define_split
e72247f4 2557 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 2558 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2559 [(match_operand:SI 1 "gpc_reg_operand" "")
2560 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2561 (const_int 0)))
75540af0 2562 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 2563 (match_dup 4))]
4b8a63d6 2564 "TARGET_32BIT && reload_completed"
dfbdccdb 2565 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 2566 (set (match_dup 3)
2567 (compare:CC (match_dup 0)
2568 (const_int 0)))]
2569 "")
1fd4e8c1 2570
5bdc5878 2571;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 2572;; each of which does one 16-bit part. This is used by combine.
a260abc9
DE		 2573
2574(define_split
2575 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1d328b19 2576 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 2577 [(match_operand:SI 1 "gpc_reg_operand" "")
2578 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
a260abc9 2579 ""
dfbdccdb
GK		 2580 [(set (match_dup 0) (match_dup 4))
2581 (set (match_dup 0) (match_dup 5))]
a260abc9
DE		 2582"
2583{
dfbdccdb
GK		 2584 rtx i;
2585 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
1c563bed 2586 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
dfbdccdb
GK		 2587 operands[1], i);
2588 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
1c563bed 2589 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
dfbdccdb 2590 operands[0], i);
a260abc9
DE		 2591}")
2592
dfbdccdb 2593(define_insn "*boolcsi3_internal1"
cd2b37d9 2594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 2595 (match_operator:SI 3 "boolean_operator"
2596 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 2597 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
1fd4e8c1 2598 ""
dfbdccdb 2599 "%q3 %0,%2,%1")
1fd4e8c1 2600
dfbdccdb 2601(define_insn "*boolcsi3_internal2"
52d3af72 2602 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2603 (compare:CC (match_operator:SI 4 "boolean_operator"
2604 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2605 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2606 (const_int 0)))
52d3af72 2607 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 2608 "TARGET_32BIT"
52d3af72 2609 "@
dfbdccdb 2610 %q4. %3,%2,%1
52d3af72
DE		 2611 #"
2612 [(set_attr "type" "compare")
2613 (set_attr "length" "4,8")])
2614
2615(define_split
2616 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 2617 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2618 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2619 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2620 (const_int 0)))
52d3af72 2621 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 2622 "TARGET_32BIT && reload_completed"
dfbdccdb 2623 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 2624 (set (match_dup 0)
2625 (compare:CC (match_dup 3)
2626 (const_int 0)))]
2627 "")
1fd4e8c1 2628
dfbdccdb 2629(define_insn "*boolcsi3_internal3"
52d3af72 2630 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2631 (compare:CC (match_operator:SI 4 "boolean_operator"
2632 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2633 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2634 (const_int 0)))
52d3af72 2635 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 2636 (match_dup 4))]
4b8a63d6 2637 "TARGET_32BIT"
52d3af72 2638 "@
dfbdccdb 2639 %q4. %0,%2,%1
52d3af72
DE		 2640 #"
2641 [(set_attr "type" "compare")
2642 (set_attr "length" "4,8")])
2643
2644(define_split
e72247f4 2645 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 2646 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2647 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2648 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 2649 (const_int 0)))
75540af0 2650 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 2651 (match_dup 4))]
4b8a63d6 2652 "TARGET_32BIT && reload_completed"
dfbdccdb 2653 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 2654 (set (match_dup 3)
2655 (compare:CC (match_dup 0)
2656 (const_int 0)))]
2657 "")
2658
dfbdccdb 2659(define_insn "*boolccsi3_internal1"
cd2b37d9 2660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 2661 (match_operator:SI 3 "boolean_operator"
2662 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 2663 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
1fd4e8c1 2664 ""
dfbdccdb 2665 "%q3 %0,%1,%2")
1fd4e8c1 2666
dfbdccdb 2667(define_insn "*boolccsi3_internal2"
52d3af72 2668 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2669 (compare:CC (match_operator:SI 4 "boolean_operator"
2670 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2671 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2672 (const_int 0)))
52d3af72 2673 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 2674 "TARGET_32BIT"
52d3af72 2675 "@
dfbdccdb 2676 %q4. %3,%1,%2
52d3af72
DE		 2677 #"
2678 [(set_attr "type" "compare")
2679 (set_attr "length" "4,8")])
2680
2681(define_split
2682 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 2683 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2684 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2685 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 2686 (const_int 0)))
52d3af72 2687 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 2688 "TARGET_32BIT && reload_completed"
dfbdccdb 2689 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 2690 (set (match_dup 0)
2691 (compare:CC (match_dup 3)
2692 (const_int 0)))]
2693 "")
1fd4e8c1 2694
dfbdccdb 2695(define_insn "*boolccsi3_internal3"
52d3af72 2696 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 2697 (compare:CC (match_operator:SI 4 "boolean_operator"
2698 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2699 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2700 (const_int 0)))
52d3af72 2701 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 2702 (match_dup 4))]
4b8a63d6 2703 "TARGET_32BIT"
52d3af72 2704 "@
dfbdccdb 2705 %q4. %0,%1,%2
52d3af72
DE		 2706 #"
2707 [(set_attr "type" "compare")
2708 (set_attr "length" "4,8")])
2709
2710(define_split
e72247f4 2711 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 2712 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 2713 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2714 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 2715 (const_int 0)))
75540af0 2716 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 2717 (match_dup 4))]
4b8a63d6 2718 "TARGET_32BIT && reload_completed"
dfbdccdb 2719 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 2720 (set (match_dup 3)
2721 (compare:CC (match_dup 0)
2722 (const_int 0)))]
2723 "")
1fd4e8c1
RK		 2724
2725;; maskir insn. We need four forms because things might be in arbitrary
2726;; orders. Don't define forms that only set CR fields because these
2727;; would modify an input register.
2728
7cd5235b 2729(define_insn "*maskir_internal1"
cd2b37d9 2730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 2731 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2732 (match_operand:SI 1 "gpc_reg_operand" "0"))
2733 (and:SI (match_dup 2)
cd2b37d9 2734 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
ca7f5001 2735 "TARGET_POWER"
01def764 2736 "maskir %0,%3,%2")
1fd4e8c1 2737
7cd5235b 2738(define_insn "*maskir_internal2"
242e8072 2739 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 2740 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
2741 (match_operand:SI 1 "gpc_reg_operand" "0"))
cd2b37d9 2742 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764 2743 (match_dup 2))))]
ca7f5001 2744 "TARGET_POWER"
01def764 2745 "maskir %0,%3,%2")
1fd4e8c1 2746
7cd5235b 2747(define_insn "*maskir_internal3"
cd2b37d9 2748 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764 2749 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
cd2b37d9 2750 (match_operand:SI 3 "gpc_reg_operand" "r"))
01def764
RK		 2751 (and:SI (not:SI (match_dup 2))
2752 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 2753 "TARGET_POWER"
01def764 2754 "maskir %0,%3,%2")
1fd4e8c1 2755
7cd5235b 2756(define_insn "*maskir_internal4"
cd2b37d9
RK		 2757 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2758 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764
RK		 2759 (match_operand:SI 2 "gpc_reg_operand" "r"))
2760 (and:SI (not:SI (match_dup 2))
2761 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 2762 "TARGET_POWER"
01def764 2763 "maskir %0,%3,%2")
1fd4e8c1 2764
7cd5235b 2765(define_insn "*maskir_internal5"
9ebbca7d 2766 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 2767 (compare:CC
9ebbca7d
GK		 2768 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2769 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
01def764 2770 (and:SI (match_dup 2)
9ebbca7d 2771 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1fd4e8c1 2772 (const_int 0)))
9ebbca7d 2773 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 2774 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2775 (and:SI (match_dup 2) (match_dup 3))))]
ca7f5001 2776 "TARGET_POWER"
9ebbca7d
GK		 2777 "@
2778 maskir. %0,%3,%2
2779 #"
2780 [(set_attr "type" "compare")
2781 (set_attr "length" "4,8")])
2782
2783(define_split
2784 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2785 (compare:CC
2786 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2787 (match_operand:SI 1 "gpc_reg_operand" ""))
2788 (and:SI (match_dup 2)
2789 (match_operand:SI 3 "gpc_reg_operand" "")))
2790 (const_int 0)))
2791 (set (match_operand:SI 0 "gpc_reg_operand" "")
2792 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2793 (and:SI (match_dup 2) (match_dup 3))))]
2794 "TARGET_POWER && reload_completed"
2795 [(set (match_dup 0)
2796 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2797 (and:SI (match_dup 2) (match_dup 3))))
2798 (set (match_dup 4)
2799 (compare:CC (match_dup 0)
2800 (const_int 0)))]
2801 "")
1fd4e8c1 2802
7cd5235b 2803(define_insn "*maskir_internal6"
9ebbca7d 2804 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 2805 (compare:CC
9ebbca7d
GK		 2806 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2807 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
2808 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
01def764 2809 (match_dup 2)))
1fd4e8c1 2810 (const_int 0)))
9ebbca7d 2811 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 2812 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2813 (and:SI (match_dup 3) (match_dup 2))))]
ca7f5001 2814 "TARGET_POWER"
9ebbca7d
GK		 2815 "@
2816 maskir. %0,%3,%2
2817 #"
2818 [(set_attr "type" "compare")
2819 (set_attr "length" "4,8")])
2820
2821(define_split
2822 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2823 (compare:CC
2824 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
2825 (match_operand:SI 1 "gpc_reg_operand" ""))
2826 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2827 (match_dup 2)))
2828 (const_int 0)))
2829 (set (match_operand:SI 0 "gpc_reg_operand" "")
2830 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2831 (and:SI (match_dup 3) (match_dup 2))))]
2832 "TARGET_POWER && reload_completed"
2833 [(set (match_dup 0)
2834 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2835 (and:SI (match_dup 3) (match_dup 2))))
2836 (set (match_dup 4)
2837 (compare:CC (match_dup 0)
2838 (const_int 0)))]
2839 "")
1fd4e8c1 2840
7cd5235b 2841(define_insn "*maskir_internal7"
9ebbca7d 2842 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
815cdc52 2843 (compare:CC
9ebbca7d
GK		 2844 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
2845 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
815cdc52 2846 (and:SI (not:SI (match_dup 2))
9ebbca7d 2847 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
815cdc52 2848 (const_int 0)))
9ebbca7d 2849 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 2850 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2851 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2852 "TARGET_POWER"
9ebbca7d
GK		 2853 "@
2854 maskir. %0,%3,%2
2855 #"
2856 [(set_attr "type" "compare")
2857 (set_attr "length" "4,8")])
2858
2859(define_split
2860 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2861 (compare:CC
2862 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
2863 (match_operand:SI 3 "gpc_reg_operand" ""))
2864 (and:SI (not:SI (match_dup 2))
2865 (match_operand:SI 1 "gpc_reg_operand" "")))
2866 (const_int 0)))
2867 (set (match_operand:SI 0 "gpc_reg_operand" "")
2868 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2869 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2870 "TARGET_POWER && reload_completed"
2871 [(set (match_dup 0)
2872 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2873 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2874 (set (match_dup 4)
2875 (compare:CC (match_dup 0)
2876 (const_int 0)))]
2877 "")
1fd4e8c1 2878
7cd5235b 2879(define_insn "*maskir_internal8"
9ebbca7d 2880 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 2881 (compare:CC
9ebbca7d
GK		 2882 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
2883 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
01def764 2884 (and:SI (not:SI (match_dup 2))
9ebbca7d 2885 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
1fd4e8c1 2886 (const_int 0)))
9ebbca7d 2887 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 2888 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2889 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
ca7f5001 2890 "TARGET_POWER"
9ebbca7d
GK		 2891 "@
2892 maskir. %0,%3,%2
2893 #"
2894 [(set_attr "type" "compare")
2895 (set_attr "length" "4,8")])
fcce224d 2896
9ebbca7d
GK		 2897(define_split
2898 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
2899 (compare:CC
2900 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
2901 (match_operand:SI 2 "gpc_reg_operand" ""))
2902 (and:SI (not:SI (match_dup 2))
2903 (match_operand:SI 1 "gpc_reg_operand" "")))
2904 (const_int 0)))
2905 (set (match_operand:SI 0 "gpc_reg_operand" "")
2906 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2907 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2908 "TARGET_POWER && reload_completed"
2909 [(set (match_dup 0)
2910 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2911 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
2912 (set (match_dup 4)
2913 (compare:CC (match_dup 0)
2914 (const_int 0)))]
2915 "")
fcce224d 2916\f
1fd4e8c1
RK		 2917;; Rotate and shift insns, in all their variants. These support shifts,
2918;; field inserts and extracts, and various combinations thereof.
034c1be0 2919(define_expand "insv"
0ad91047
DE		 2920 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
2921 (match_operand:SI 1 "const_int_operand" "")
2922 (match_operand:SI 2 "const_int_operand" ""))
2923 (match_operand 3 "gpc_reg_operand" ""))]
034c1be0
MM		 2924 ""
2925 "
2926{
2927 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2928 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2929 compiler if the address of the structure is taken later. */
2930 if (GET_CODE (operands[0]) == SUBREG
2931 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2932 FAIL;
a78e33fc
DE		 2933
2934 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
2935 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
2936 else
2937 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
2938 DONE;
034c1be0
MM		 2939}")
2940
a78e33fc 2941(define_insn "insvsi"
cd2b37d9 2942 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1
RK		 2943 (match_operand:SI 1 "const_int_operand" "i")
2944 (match_operand:SI 2 "const_int_operand" "i"))
cd2b37d9 2945 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1fd4e8c1
RK		 2946 ""
2947 "*
2948{
2949 int start = INTVAL (operands[2]) & 31;
2950 int size = INTVAL (operands[1]) & 31;
2951
89e9f3a8
MM		 2952 operands[4] = GEN_INT (32 - start - size);
2953 operands[1] = GEN_INT (start + size - 1);
a66078ee 2954 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 2955}"
2956 [(set_attr "type" "insert_word")])
1fd4e8c1 2957
a78e33fc 2958(define_insn "*insvsi_internal1"
d56d506a
RK		 2959 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2960 (match_operand:SI 1 "const_int_operand" "i")
2961 (match_operand:SI 2 "const_int_operand" "i"))
2962 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2963 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 2964 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 2965 "*
2966{
2967 int shift = INTVAL (operands[4]) & 31;
2968 int start = INTVAL (operands[2]) & 31;
2969 int size = INTVAL (operands[1]) & 31;
2970
89e9f3a8
MM		 2971 operands[4] = GEN_INT (shift - start - size);
2972 operands[1] = GEN_INT (start + size - 1);
a66078ee 2973 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 2974}"
2975 [(set_attr "type" "insert_word")])
d56d506a 2976
a78e33fc 2977(define_insn "*insvsi_internal2"
d56d506a
RK		 2978 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2979 (match_operand:SI 1 "const_int_operand" "i")
2980 (match_operand:SI 2 "const_int_operand" "i"))
2981 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2982 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 2983 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 2984 "*
2985{
2986 int shift = INTVAL (operands[4]) & 31;
2987 int start = INTVAL (operands[2]) & 31;
2988 int size = INTVAL (operands[1]) & 31;
2989
89e9f3a8
MM		 2990 operands[4] = GEN_INT (32 - shift - start - size);
2991 operands[1] = GEN_INT (start + size - 1);
a66078ee 2992 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 2993}"
2994 [(set_attr "type" "insert_word")])
d56d506a 2995
a78e33fc 2996(define_insn "*insvsi_internal3"
d56d506a
RK		 2997 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2998 (match_operand:SI 1 "const_int_operand" "i")
2999 (match_operand:SI 2 "const_int_operand" "i"))
3000 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3001 (match_operand:SI 4 "const_int_operand" "i")))]
95e8f2f3 3002 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3003 "*
3004{
3005 int shift = INTVAL (operands[4]) & 31;
3006 int start = INTVAL (operands[2]) & 31;
3007 int size = INTVAL (operands[1]) & 31;
3008
89e9f3a8
MM		 3009 operands[4] = GEN_INT (32 - shift - start - size);
3010 operands[1] = GEN_INT (start + size - 1);
a66078ee 3011 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3012}"
3013 [(set_attr "type" "insert_word")])
d56d506a 3014
a78e33fc 3015(define_insn "*insvsi_internal4"
d56d506a
RK		 3016 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3017 (match_operand:SI 1 "const_int_operand" "i")
3018 (match_operand:SI 2 "const_int_operand" "i"))
3019 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3020 (match_operand:SI 4 "const_int_operand" "i")
3021 (match_operand:SI 5 "const_int_operand" "i")))]
3022 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3023 "*
3024{
3025 int extract_start = INTVAL (operands[5]) & 31;
3026 int extract_size = INTVAL (operands[4]) & 31;
3027 int insert_start = INTVAL (operands[2]) & 31;
3028 int insert_size = INTVAL (operands[1]) & 31;
3029
3030/* Align extract field with insert field */
3a598fbe 3031 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
89e9f3a8 3032 operands[1] = GEN_INT (insert_start + insert_size - 1);
a66078ee 3033 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
8e8238f1
DE		 3034}"
3035 [(set_attr "type" "insert_word")])
d56d506a 3036
a78e33fc 3037(define_insn "insvdi"
685f3906 3038 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
a78e33fc
DE		 3039 (match_operand:SI 1 "const_int_operand" "i")
3040 (match_operand:SI 2 "const_int_operand" "i"))
685f3906
DE		 3041 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3042 "TARGET_POWERPC64"
3043 "*
3044{
3045 int start = INTVAL (operands[2]) & 63;
3046 int size = INTVAL (operands[1]) & 63;
3047
a78e33fc
DE		 3048 operands[1] = GEN_INT (64 - start - size);
3049 return \"rldimi %0,%3,%H1,%H2\";
685f3906
DE		 3050}")
3051
034c1be0 3052(define_expand "extzv"
0ad91047
DE		 3053 [(set (match_operand 0 "gpc_reg_operand" "")
3054 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3055 (match_operand:SI 2 "const_int_operand" "")
3056 (match_operand:SI 3 "const_int_operand" "")))]
034c1be0
MM		 3057 ""
3058 "
3059{
3060 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3061 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3062 compiler if the address of the structure is taken later. */
3063 if (GET_CODE (operands[0]) == SUBREG
3064 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3065 FAIL;
a78e33fc
DE		 3066
3067 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3068 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3069 else
3070 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3071 DONE;
034c1be0
MM		 3072}")
3073
a78e33fc 3074(define_insn "extzvsi"
cd2b37d9
RK		 3075 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3076 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3077 (match_operand:SI 2 "const_int_operand" "i")
3078 (match_operand:SI 3 "const_int_operand" "i")))]
3079 ""
3080 "*
3081{
3082 int start = INTVAL (operands[3]) & 31;
3083 int size = INTVAL (operands[2]) & 31;
3084
3085 if (start + size >= 32)
3086 operands[3] = const0_rtx;
3087 else
89e9f3a8 3088 operands[3] = GEN_INT (start + size);
ca7f5001 3089 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
1fd4e8c1
RK		 3090}")
3091
a78e33fc 3092(define_insn "*extzvsi_internal1"
9ebbca7d
GK		 3093 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3094 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3095 (match_operand:SI 2 "const_int_operand" "i,i")
3096 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3097 (const_int 0)))
9ebbca7d 3098 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3099 ""
1fd4e8c1
RK		 3100 "*
3101{
3102 int start = INTVAL (operands[3]) & 31;
3103 int size = INTVAL (operands[2]) & 31;
3104
9ebbca7d
GK		 3105 /* Force split for non-cc0 compare. */
3106 if (which_alternative == 1)
3107 return \"#\";
3108
43a88a8c 3109 /* If the bit-field being tested fits in the upper or lower half of a
a7a975e1
RK		 3110 word, it is possible to use andiu. or andil. to test it. This is
3111 useful because the condition register set-use delay is smaller for
3112 andi[ul]. than for rlinm. This doesn't work when the starting bit
3113 position is 0 because the LT and GT bits may be set wrong. */
3114
3115 if ((start > 0 && start + size <= 16) || start >= 16)
df031c43 3116 {
3a598fbe 3117 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
df031c43
RK		 3118 - (1 << (16 - (start & 15) - size))));
3119 if (start < 16)
ca7f5001 3120 return \"{andiu.|andis.} %4,%1,%3\";
df031c43 3121 else
ca7f5001 3122 return \"{andil.|andi.} %4,%1,%3\";
df031c43 3123 }
7e69e155 3124
1fd4e8c1
RK		 3125 if (start + size >= 32)
3126 operands[3] = const0_rtx;
3127 else
89e9f3a8 3128 operands[3] = GEN_INT (start + size);
ca7f5001 3129 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
1fd4e8c1 3130}"
9ebbca7d
GK		 3131 [(set_attr "type" "compare")
3132 (set_attr "length" "4,8")])
3133
3134(define_split
3135 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3136 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3137 (match_operand:SI 2 "const_int_operand" "")
3138 (match_operand:SI 3 "const_int_operand" ""))
3139 (const_int 0)))
3140 (clobber (match_scratch:SI 4 ""))]
ce71f754 3141 "reload_completed"
9ebbca7d
GK		 3142 [(set (match_dup 4)
3143 (zero_extract:SI (match_dup 1) (match_dup 2)
3144 (match_dup 3)))
3145 (set (match_dup 0)
3146 (compare:CC (match_dup 4)
3147 (const_int 0)))]
3148 "")
1fd4e8c1 3149
a78e33fc 3150(define_insn "*extzvsi_internal2"
9ebbca7d
GK		 3151 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3152 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3153 (match_operand:SI 2 "const_int_operand" "i,i")
3154 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3155 (const_int 0)))
9ebbca7d 3156 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3157 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3158 ""
1fd4e8c1
RK		 3159 "*
3160{
3161 int start = INTVAL (operands[3]) & 31;
3162 int size = INTVAL (operands[2]) & 31;
3163
9ebbca7d
GK		 3164 /* Force split for non-cc0 compare. */
3165 if (which_alternative == 1)
3166 return \"#\";
3167
bc401279 3168 /* Since we are using the output value, we can't ignore any need for
43a88a8c 3169 a shift. The bit-field must end at the LSB. */
bc401279 3170 if (start >= 16 && start + size == 32)
df031c43 3171 {
bc401279
AM		 3172 operands[3] = GEN_INT ((1 << size) - 1);
3173 return \"{andil.|andi.} %0,%1,%3\";
df031c43 3174 }
7e69e155 3175
1fd4e8c1
RK		 3176 if (start + size >= 32)
3177 operands[3] = const0_rtx;
3178 else
89e9f3a8 3179 operands[3] = GEN_INT (start + size);
ca7f5001 3180 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
1fd4e8c1 3181}"
ce71f754 3182 [(set_attr "type" "compare")
9ebbca7d
GK		 3183 (set_attr "length" "4,8")])
3184
3185(define_split
3186 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3187 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3188 (match_operand:SI 2 "const_int_operand" "")
3189 (match_operand:SI 3 "const_int_operand" ""))
3190 (const_int 0)))
3191 (set (match_operand:SI 0 "gpc_reg_operand" "")
3192 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3193 "reload_completed"
9ebbca7d
GK		 3194 [(set (match_dup 0)
3195 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3196 (set (match_dup 4)
3197 (compare:CC (match_dup 0)
3198 (const_int 0)))]
3199 "")
1fd4e8c1 3200
a78e33fc 3201(define_insn "extzvdi"
685f3906
DE		 3202 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3203 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3204 (match_operand:SI 2 "const_int_operand" "i")
3205 (match_operand:SI 3 "const_int_operand" "i")))]
685f3906
DE		 3206 "TARGET_POWERPC64"
3207 "*
3208{
3209 int start = INTVAL (operands[3]) & 63;
3210 int size = INTVAL (operands[2]) & 63;
3211
3212 if (start + size >= 64)
3213 operands[3] = const0_rtx;
3214 else
89e9f3a8
MM		 3215 operands[3] = GEN_INT (start + size);
3216 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3217 return \"rldicl %0,%1,%3,%2\";
3218}")
3219
a78e33fc 3220(define_insn "*extzvdi_internal1"
29ae5b89
JL		 3221 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3222 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3223 (match_operand:SI 2 "const_int_operand" "i")
3224 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3225 (const_int 0)))
29ae5b89 3226 (clobber (match_scratch:DI 4 "=r"))]
683bdff7 3227 "TARGET_64BIT"
685f3906
DE		 3228 "*
3229{
3230 int start = INTVAL (operands[3]) & 63;
3231 int size = INTVAL (operands[2]) & 63;
3232
3233 if (start + size >= 64)
3234 operands[3] = const0_rtx;
3235 else
89e9f3a8
MM		 3236 operands[3] = GEN_INT (start + size);
3237 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3238 return \"rldicl. %4,%1,%3,%2\";
3239}")
3240
a78e33fc 3241(define_insn "*extzvdi_internal2"
29ae5b89
JL		 3242 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3243 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3244 (match_operand:SI 2 "const_int_operand" "i")
3245 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3246 (const_int 0)))
29ae5b89 3247 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
685f3906 3248 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
683bdff7 3249 "TARGET_64BIT"
685f3906
DE		 3250 "*
3251{
3252 int start = INTVAL (operands[3]) & 63;
3253 int size = INTVAL (operands[2]) & 63;
3254
3255 if (start + size >= 64)
3256 operands[3] = const0_rtx;
3257 else
89e9f3a8
MM		 3258 operands[3] = GEN_INT (start + size);
3259 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3260 return \"rldicl. %0,%1,%3,%2\";
3261}")
3262
1fd4e8c1 3263(define_insn "rotlsi3"
cd2b37d9
RK		 3264 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3265 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3266 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3267 ""
ca7f5001 3268 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
1fd4e8c1 3269
a260abc9 3270(define_insn "*rotlsi3_internal2"
9ebbca7d
GK		 3271 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3272 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3273 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
1fd4e8c1 3274 (const_int 0)))
9ebbca7d 3275 (clobber (match_scratch:SI 3 "=r,r"))]
ce71f754 3276 ""
9ebbca7d
GK		 3277 "@
3278 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3279 #"
3280 [(set_attr "type" "delayed_compare")
3281 (set_attr "length" "4,8")])
3282
3283(define_split
3284 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3285 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3286 (match_operand:SI 2 "reg_or_cint_operand" ""))
3287 (const_int 0)))
3288 (clobber (match_scratch:SI 3 ""))]
ce71f754 3289 "reload_completed"
9ebbca7d
GK		 3290 [(set (match_dup 3)
3291 (rotate:SI (match_dup 1) (match_dup 2)))
3292 (set (match_dup 0)
3293 (compare:CC (match_dup 3)
3294 (const_int 0)))]
3295 "")
1fd4e8c1 3296
a260abc9 3297(define_insn "*rotlsi3_internal3"
9ebbca7d
GK		 3298 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3299 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3300 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
1fd4e8c1 3301 (const_int 0)))
9ebbca7d 3302 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3303 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3304 ""
9ebbca7d
GK		 3305 "@
3306 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3307 #"
3308 [(set_attr "type" "delayed_compare")
3309 (set_attr "length" "4,8")])
3310
3311(define_split
3312 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3313 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3314 (match_operand:SI 2 "reg_or_cint_operand" ""))
3315 (const_int 0)))
3316 (set (match_operand:SI 0 "gpc_reg_operand" "")
3317 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3318 "reload_completed"
9ebbca7d
GK		 3319 [(set (match_dup 0)
3320 (rotate:SI (match_dup 1) (match_dup 2)))
3321 (set (match_dup 3)
3322 (compare:CC (match_dup 0)
3323 (const_int 0)))]
3324 "")
1fd4e8c1 3325
a260abc9 3326(define_insn "*rotlsi3_internal4"
cd2b37d9
RK		 3327 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3328 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 3329 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
ce71f754 3330 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 3331 ""
ca7f5001 3332 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
1fd4e8c1 3333
a260abc9 3334(define_insn "*rotlsi3_internal5"
9ebbca7d 3335 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 3336 (compare:CC (and:SI
9ebbca7d
GK		 3337 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3338 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ce71f754 3339 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3340 (const_int 0)))
9ebbca7d 3341 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3342 ""
9ebbca7d
GK		 3343 "@
3344 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3345 #"
3346 [(set_attr "type" "delayed_compare")
3347 (set_attr "length" "4,8")])
3348
3349(define_split
3350 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3351 (compare:CC (and:SI
3352 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3353 (match_operand:SI 2 "reg_or_cint_operand" ""))
3354 (match_operand:SI 3 "mask_operand" ""))
3355 (const_int 0)))
3356 (clobber (match_scratch:SI 4 ""))]
ce71f754 3357 "reload_completed"
9ebbca7d
GK		 3358 [(set (match_dup 4)
3359 (and:SI (rotate:SI (match_dup 1)
3360 (match_dup 2))
3361 (match_dup 3)))
3362 (set (match_dup 0)
3363 (compare:CC (match_dup 4)
3364 (const_int 0)))]
3365 "")
1fd4e8c1 3366
a260abc9 3367(define_insn "*rotlsi3_internal6"
9ebbca7d 3368 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3369 (compare:CC (and:SI
9ebbca7d
GK		 3370 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3371 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ce71f754 3372 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3373 (const_int 0)))
9ebbca7d 3374 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3375 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3376 ""
9ebbca7d
GK		 3377 "@
3378 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3379 #"
3380 [(set_attr "type" "delayed_compare")
3381 (set_attr "length" "4,8")])
3382
3383(define_split
3384 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3385 (compare:CC (and:SI
3386 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3387 (match_operand:SI 2 "reg_or_cint_operand" ""))
3388 (match_operand:SI 3 "mask_operand" ""))
3389 (const_int 0)))
3390 (set (match_operand:SI 0 "gpc_reg_operand" "")
3391 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3392 "reload_completed"
9ebbca7d
GK		 3393 [(set (match_dup 0)
3394 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3395 (set (match_dup 4)
3396 (compare:CC (match_dup 0)
3397 (const_int 0)))]
3398 "")
1fd4e8c1 3399
a260abc9 3400(define_insn "*rotlsi3_internal7"
cd2b37d9 3401 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 3402 (zero_extend:SI
3403 (subreg:QI
cd2b37d9 3404 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3405 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3406 ""
ca7f5001 3407 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
1fd4e8c1 3408
a260abc9 3409(define_insn "*rotlsi3_internal8"
9ebbca7d 3410 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3411 (compare:CC (zero_extend:SI
3412 (subreg:QI
9ebbca7d
GK		 3413 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3414 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3415 (const_int 0)))
9ebbca7d 3416 (clobber (match_scratch:SI 3 "=r,r"))]
1fd4e8c1 3417 ""
9ebbca7d
GK		 3418 "@
3419 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3420 #"
3421 [(set_attr "type" "delayed_compare")
3422 (set_attr "length" "4,8")])
3423
3424(define_split
3425 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3426 (compare:CC (zero_extend:SI
3427 (subreg:QI
3428 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3429 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3430 (const_int 0)))
3431 (clobber (match_scratch:SI 3 ""))]
3432 "reload_completed"
3433 [(set (match_dup 3)
3434 (zero_extend:SI (subreg:QI
3435 (rotate:SI (match_dup 1)
3436 (match_dup 2)) 0)))
3437 (set (match_dup 0)
3438 (compare:CC (match_dup 3)
3439 (const_int 0)))]
3440 "")
1fd4e8c1 3441
a260abc9 3442(define_insn "*rotlsi3_internal9"
9ebbca7d 3443 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3444 (compare:CC (zero_extend:SI
3445 (subreg:QI
9ebbca7d
GK		 3446 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3447 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3448 (const_int 0)))
9ebbca7d 3449 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 3450 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3451 ""
9ebbca7d
GK		 3452 "@
3453 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3454 #"
3455 [(set_attr "type" "delayed_compare")
3456 (set_attr "length" "4,8")])
3457
3458(define_split
3459 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3460 (compare:CC (zero_extend:SI
3461 (subreg:QI
3462 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3463 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3464 (const_int 0)))
3465 (set (match_operand:SI 0 "gpc_reg_operand" "")
3466 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3467 "reload_completed"
3468 [(set (match_dup 0)
3469 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3470 (set (match_dup 3)
3471 (compare:CC (match_dup 0)
3472 (const_int 0)))]
3473 "")
1fd4e8c1 3474
a260abc9 3475(define_insn "*rotlsi3_internal10"
cd2b37d9 3476 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 3477 (zero_extend:SI
3478 (subreg:HI
cd2b37d9 3479 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3480 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3481 ""
ca7f5001 3482 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
1fd4e8c1 3483
a260abc9 3484(define_insn "*rotlsi3_internal11"
9ebbca7d 3485 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3486 (compare:CC (zero_extend:SI
3487 (subreg:HI
9ebbca7d
GK		 3488 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3489 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3490 (const_int 0)))
9ebbca7d 3491 (clobber (match_scratch:SI 3 "=r,r"))]
1fd4e8c1 3492 ""
9ebbca7d
GK		 3493 "@
3494 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3495 #"
3496 [(set_attr "type" "delayed_compare")
3497 (set_attr "length" "4,8")])
3498
3499(define_split
3500 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3501 (compare:CC (zero_extend:SI
3502 (subreg:HI
3503 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3504 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3505 (const_int 0)))
3506 (clobber (match_scratch:SI 3 ""))]
3507 "reload_completed"
3508 [(set (match_dup 3)
3509 (zero_extend:SI (subreg:HI
3510 (rotate:SI (match_dup 1)
3511 (match_dup 2)) 0)))
3512 (set (match_dup 0)
3513 (compare:CC (match_dup 3)
3514 (const_int 0)))]
3515 "")
1fd4e8c1 3516
a260abc9 3517(define_insn "*rotlsi3_internal12"
9ebbca7d 3518 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 3519 (compare:CC (zero_extend:SI
3520 (subreg:HI
9ebbca7d
GK		 3521 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3522 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
1fd4e8c1 3523 (const_int 0)))
9ebbca7d 3524 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 3525 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3526 ""
9ebbca7d
GK		 3527 "@
3528 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3529 #"
3530 [(set_attr "type" "delayed_compare")
3531 (set_attr "length" "4,8")])
3532
3533(define_split
3534 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3535 (compare:CC (zero_extend:SI
3536 (subreg:HI
3537 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3538 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3539 (const_int 0)))
3540 (set (match_operand:SI 0 "gpc_reg_operand" "")
3541 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3542 "reload_completed"
3543 [(set (match_dup 0)
3544 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3545 (set (match_dup 3)
3546 (compare:CC (match_dup 0)
3547 (const_int 0)))]
3548 "")
1fd4e8c1
RK		 3549
3550;; Note that we use "sle." instead of "sl." so that we can set
3551;; SHIFT_COUNT_TRUNCATED.
3552
ca7f5001
RK		 3553(define_expand "ashlsi3"
3554 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3555 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3556 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3557 ""
3558 "
3559{
3560 if (TARGET_POWER)
3561 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3562 else
25c341fa 3563 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 3564 DONE;
3565}")
3566
3567(define_insn "ashlsi3_power"
cd2b37d9
RK		 3568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3569 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 3570 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3571 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 3572 "TARGET_POWER"
1fd4e8c1
RK		 3573 "@
3574 sle %0,%1,%2
9ebbca7d 3575 {sli|slwi} %0,%1,%h2")
ca7f5001 3576
25c341fa 3577(define_insn "ashlsi3_no_power"
ca7f5001
RK		 3578 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3579 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3580 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
25c341fa 3581 "! TARGET_POWER"
9ebbca7d 3582 "{sl|slw}%I2 %0,%1,%h2")
1fd4e8c1
RK		 3583
3584(define_insn ""
9ebbca7d
GK		 3585 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3586 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3587 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3588 (const_int 0)))
9ebbca7d
GK		 3589 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3590 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 3591 "TARGET_POWER"
1fd4e8c1
RK		 3592 "@
3593 sle. %3,%1,%2
9ebbca7d
GK		 3594 {sli.|slwi.} %3,%1,%h2
3595 #
3596 #"
3597 [(set_attr "type" "delayed_compare")
3598 (set_attr "length" "4,4,8,8")])
3599
3600(define_split
3601 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3602 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3603 (match_operand:SI 2 "reg_or_cint_operand" ""))
3604 (const_int 0)))
3605 (clobber (match_scratch:SI 3 ""))
3606 (clobber (match_scratch:SI 4 ""))]
3607 "TARGET_POWER && reload_completed"
3608 [(parallel [(set (match_dup 3)
3609 (ashift:SI (match_dup 1) (match_dup 2)))
3610 (clobber (match_dup 4))])
3611 (set (match_dup 0)
3612 (compare:CC (match_dup 3)
3613 (const_int 0)))]
3614 "")
25c341fa 3615
ca7f5001 3616(define_insn ""
9ebbca7d
GK		 3617 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3618 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3619 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 3620 (const_int 0)))
9ebbca7d 3621 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3622 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d
GK		 3623 "@
3624 {sl|slw}%I2. %3,%1,%h2
3625 #"
3626 [(set_attr "type" "delayed_compare")
3627 (set_attr "length" "4,8")])
3628
3629(define_split
3630 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3631 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3632 (match_operand:SI 2 "reg_or_cint_operand" ""))
3633 (const_int 0)))
3634 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3635 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 3636 [(set (match_dup 3)
3637 (ashift:SI (match_dup 1) (match_dup 2)))
3638 (set (match_dup 0)
3639 (compare:CC (match_dup 3)
3640 (const_int 0)))]
3641 "")
1fd4e8c1
RK		 3642
3643(define_insn ""
9ebbca7d
GK		 3644 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3645 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3646 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3647 (const_int 0)))
9ebbca7d 3648 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 3649 (ashift:SI (match_dup 1) (match_dup 2)))
9ebbca7d 3650 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 3651 "TARGET_POWER"
1fd4e8c1
RK		 3652 "@
3653 sle. %0,%1,%2
9ebbca7d
GK		 3654 {sli.|slwi.} %0,%1,%h2
3655 #
3656 #"
3657 [(set_attr "type" "delayed_compare")
3658 (set_attr "length" "4,4,8,8")])
3659
3660(define_split
3661 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3662 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3663 (match_operand:SI 2 "reg_or_cint_operand" ""))
3664 (const_int 0)))
3665 (set (match_operand:SI 0 "gpc_reg_operand" "")
3666 (ashift:SI (match_dup 1) (match_dup 2)))
3667 (clobber (match_scratch:SI 4 ""))]
3668 "TARGET_POWER && reload_completed"
3669 [(parallel [(set (match_dup 0)
3670 (ashift:SI (match_dup 1) (match_dup 2)))
3671 (clobber (match_dup 4))])
3672 (set (match_dup 3)
3673 (compare:CC (match_dup 0)
3674 (const_int 0)))]
3675 "")
25c341fa 3676
ca7f5001 3677(define_insn ""
9ebbca7d
GK		 3678 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3679 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3680 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 3681 (const_int 0)))
9ebbca7d 3682 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 3683 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 3684 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d
GK		 3685 "@
3686 {sl|slw}%I2. %0,%1,%h2
3687 #"
3688 [(set_attr "type" "delayed_compare")
3689 (set_attr "length" "4,8")])
3690
3691(define_split
3692 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3693 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3694 (match_operand:SI 2 "reg_or_cint_operand" ""))
3695 (const_int 0)))
3696 (set (match_operand:SI 0 "gpc_reg_operand" "")
3697 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 3698 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 3699 [(set (match_dup 0)
3700 (ashift:SI (match_dup 1) (match_dup 2)))
3701 (set (match_dup 3)
3702 (compare:CC (match_dup 0)
3703 (const_int 0)))]
3704 "")
1fd4e8c1
RK		 3705
3706(define_insn ""
cd2b37d9
RK		 3707 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3708 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 3709 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 3710 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 3711 "includes_lshift_p (operands[2], operands[3])"
d56d506a 3712 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
1fd4e8c1
RK		 3713
3714(define_insn ""
9ebbca7d 3715 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 3716 (compare:CC
9ebbca7d
GK		 3717 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3718 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3719 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3720 (const_int 0)))
9ebbca7d 3721 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3722 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 3723 "@
3724 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3725 #"
3726 [(set_attr "type" "delayed_compare")
3727 (set_attr "length" "4,8")])
3728
3729(define_split
3730 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3731 (compare:CC
3732 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3733 (match_operand:SI 2 "const_int_operand" ""))
3734 (match_operand:SI 3 "mask_operand" ""))
3735 (const_int 0)))
3736 (clobber (match_scratch:SI 4 ""))]
ce71f754 3737 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 3738 [(set (match_dup 4)
3739 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
3740 (match_dup 3)))
3741 (set (match_dup 0)
3742 (compare:CC (match_dup 4)
3743 (const_int 0)))]
3744 "")
1fd4e8c1
RK		 3745
3746(define_insn ""
9ebbca7d 3747 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3748 (compare:CC
9ebbca7d
GK		 3749 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3750 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3751 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3752 (const_int 0)))
9ebbca7d 3753 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3754 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3755 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 3756 "@
3757 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
3758 #"
3759 [(set_attr "type" "delayed_compare")
3760 (set_attr "length" "4,8")])
3761
3762(define_split
3763 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3764 (compare:CC
3765 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3766 (match_operand:SI 2 "const_int_operand" ""))
3767 (match_operand:SI 3 "mask_operand" ""))
3768 (const_int 0)))
3769 (set (match_operand:SI 0 "gpc_reg_operand" "")
3770 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3771 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 3772 [(set (match_dup 0)
3773 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3774 (set (match_dup 4)
3775 (compare:CC (match_dup 0)
3776 (const_int 0)))]
3777 "")
1fd4e8c1 3778
ca7f5001 3779;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5c23c401 3780;; "sli x,x,0".
ca7f5001
RK		 3781(define_expand "lshrsi3"
3782 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3783 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3784 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3785 ""
3786 "
3787{
3788 if (TARGET_POWER)
3789 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
3790 else
25c341fa 3791 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 3792 DONE;
3793}")
3794
3795(define_insn "lshrsi3_power"
bdf423cb
MM		 3796 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3797 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
3798 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
3799 (clobber (match_scratch:SI 3 "=q,X,X"))]
ca7f5001 3800 "TARGET_POWER"
1fd4e8c1
RK		 3801 "@
3802 sre %0,%1,%2
bdf423cb 3803 mr %0,%1
ca7f5001
RK		 3804 {s%A2i|s%A2wi} %0,%1,%h2")
3805
25c341fa 3806(define_insn "lshrsi3_no_power"
bdf423cb
MM		 3807 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3808 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3809 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
25c341fa 3810 "! TARGET_POWER"
bdf423cb
MM		 3811 "@
3812 mr %0,%1
3813 {sr|srw}%I2 %0,%1,%h2")
1fd4e8c1
RK		 3814
3815(define_insn ""
9ebbca7d
GK		 3816 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3817 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3818 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 3819 (const_int 0)))
9ebbca7d
GK		 3820 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
3821 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 3822 "TARGET_POWER"
1fd4e8c1 3823 "@
29ae5b89
JL		 3824 sre. %3,%1,%2
3825 mr. %1,%1
9ebbca7d
GK		 3826 {s%A2i.|s%A2wi.} %3,%1,%h2
3827 #
3828 #
3829 #"
3830 [(set_attr "type" "delayed_compare")
3831 (set_attr "length" "4,4,4,8,8,8")])
3832
3833(define_split
3834 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3835 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3836 (match_operand:SI 2 "reg_or_cint_operand" ""))
3837 (const_int 0)))
3838 (clobber (match_scratch:SI 3 ""))
3839 (clobber (match_scratch:SI 4 ""))]
3840 "TARGET_POWER && reload_completed"
3841 [(parallel [(set (match_dup 3)
3842 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3843 (clobber (match_dup 4))])
3844 (set (match_dup 0)
3845 (compare:CC (match_dup 3)
3846 (const_int 0)))]
3847 "")
ca7f5001
RK		 3848
3849(define_insn ""
9ebbca7d
GK		 3850 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3851 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3852 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
ca7f5001 3853 (const_int 0)))
9ebbca7d 3854 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
4b8a63d6 3855 "! TARGET_POWER && TARGET_32BIT"
bdf423cb
MM		 3856 "@
3857 mr. %1,%1
9ebbca7d
GK		 3858 {sr|srw}%I2. %3,%1,%h2
3859 #
3860 #"
3861 [(set_attr "type" "delayed_compare")
3862 (set_attr "length" "4,4,8,8")])
1fd4e8c1 3863
9ebbca7d
GK		 3864(define_split
3865 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3866 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3867 (match_operand:SI 2 "reg_or_cint_operand" ""))
3868 (const_int 0)))
3869 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3870 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 3871 [(set (match_dup 3)
3872 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3873 (set (match_dup 0)
3874 (compare:CC (match_dup 3)
3875 (const_int 0)))]
3876 "")
3877
3878(define_insn ""
3879 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
3880 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
3881 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 3882 (const_int 0)))
9ebbca7d 3883 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
1fd4e8c1 3884 (lshiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 3885 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 3886 "TARGET_POWER"
1fd4e8c1 3887 "@
29ae5b89
JL		 3888 sre. %0,%1,%2
3889 mr. %0,%1
9ebbca7d
GK		 3890 {s%A2i.|s%A2wi.} %0,%1,%h2
3891 #
3892 #
3893 #"
3894 [(set_attr "type" "delayed_compare")
3895 (set_attr "length" "4,4,4,8,8,8")])
3896
3897(define_split
3898 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3899 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3900 (match_operand:SI 2 "reg_or_cint_operand" ""))
3901 (const_int 0)))
3902 (set (match_operand:SI 0 "gpc_reg_operand" "")
3903 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3904 (clobber (match_scratch:SI 4 ""))]
3905 "TARGET_POWER && reload_completed"
3906 [(parallel [(set (match_dup 0)
3907 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3908 (clobber (match_dup 4))])
3909 (set (match_dup 3)
3910 (compare:CC (match_dup 0)
3911 (const_int 0)))]
3912 "")
ca7f5001
RK		 3913
3914(define_insn ""
9ebbca7d
GK		 3915 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3916 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3917 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
815cdc52 3918 (const_int 0)))
9ebbca7d 3919 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
29ae5b89 3920 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 3921 "! TARGET_POWER && TARGET_32BIT"
29ae5b89
JL		 3922 "@
3923 mr. %0,%1
9ebbca7d
GK		 3924 {sr|srw}%I2. %0,%1,%h2
3925 #
3926 #"
3927 [(set_attr "type" "delayed_compare")
3928 (set_attr "length" "4,4,8,8")])
3929
3930(define_split
3931 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3932 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3933 (match_operand:SI 2 "reg_or_cint_operand" ""))
3934 (const_int 0)))
3935 (set (match_operand:SI 0 "gpc_reg_operand" "")
3936 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 3937 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 3938 [(set (match_dup 0)
3939 (lshiftrt:SI (match_dup 1) (match_dup 2)))
3940 (set (match_dup 3)
3941 (compare:CC (match_dup 0)
3942 (const_int 0)))]
3943 "")
1fd4e8c1
RK		 3944
3945(define_insn ""
cd2b37d9
RK		 3946 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3947 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 3948 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 3949 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 3950 "includes_rshift_p (operands[2], operands[3])"
ca7f5001 3951 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
1fd4e8c1
RK		 3952
3953(define_insn ""
9ebbca7d 3954 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 3955 (compare:CC
9ebbca7d
GK		 3956 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3957 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3958 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3959 (const_int 0)))
9ebbca7d 3960 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3961 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 3962 "@
3963 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
3964 #"
3965 [(set_attr "type" "delayed_compare")
3966 (set_attr "length" "4,8")])
3967
3968(define_split
3969 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3970 (compare:CC
3971 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
3972 (match_operand:SI 2 "const_int_operand" ""))
3973 (match_operand:SI 3 "mask_operand" ""))
3974 (const_int 0)))
3975 (clobber (match_scratch:SI 4 ""))]
ce71f754 3976 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 3977 [(set (match_dup 4)
3978 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3979 (match_dup 3)))
3980 (set (match_dup 0)
3981 (compare:CC (match_dup 4)
3982 (const_int 0)))]
3983 "")
1fd4e8c1
RK		 3984
3985(define_insn ""
9ebbca7d 3986 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3987 (compare:CC
9ebbca7d
GK		 3988 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3989 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 3990 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 3991 (const_int 0)))
9ebbca7d 3992 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3993 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 3994 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 3995 "@
3996 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
3997 #"
3998 [(set_attr "type" "delayed_compare")
3999 (set_attr "length" "4,8")])
4000
4001(define_split
4002 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4003 (compare:CC
4004 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4005 (match_operand:SI 2 "const_int_operand" ""))
4006 (match_operand:SI 3 "mask_operand" ""))
4007 (const_int 0)))
4008 (set (match_operand:SI 0 "gpc_reg_operand" "")
4009 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4010 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4011 [(set (match_dup 0)
4012 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4013 (set (match_dup 4)
4014 (compare:CC (match_dup 0)
4015 (const_int 0)))]
4016 "")
1fd4e8c1
RK		 4017
4018(define_insn ""
cd2b37d9 4019 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4020 (zero_extend:SI
4021 (subreg:QI
cd2b37d9 4022 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4023 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4024 "includes_rshift_p (operands[2], GEN_INT (255))"
ca7f5001 4025 "{rlinm|rlwinm} %0,%1,%s2,0xff")
1fd4e8c1
RK		 4026
4027(define_insn ""
9ebbca7d 4028 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4029 (compare:CC
4030 (zero_extend:SI
4031 (subreg:QI
9ebbca7d
GK		 4032 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4033 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4034 (const_int 0)))
9ebbca7d 4035 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4036 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4037 "@
4038 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4039 #"
4040 [(set_attr "type" "delayed_compare")
4041 (set_attr "length" "4,8")])
4042
4043(define_split
4044 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4045 (compare:CC
4046 (zero_extend:SI
4047 (subreg:QI
4048 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4049 (match_operand:SI 2 "const_int_operand" "")) 0))
4050 (const_int 0)))
4051 (clobber (match_scratch:SI 3 ""))]
4052 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4053 [(set (match_dup 3)
4054 (zero_extend:SI (subreg:QI
4055 (lshiftrt:SI (match_dup 1)
4056 (match_dup 2)) 0)))
4057 (set (match_dup 0)
4058 (compare:CC (match_dup 3)
4059 (const_int 0)))]
4060 "")
1fd4e8c1
RK		 4061
4062(define_insn ""
9ebbca7d 4063 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4064 (compare:CC
4065 (zero_extend:SI
4066 (subreg:QI
9ebbca7d
GK		 4067 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4068 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4069 (const_int 0)))
9ebbca7d 4070 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4071 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4072 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4073 "@
4074 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4075 #"
4076 [(set_attr "type" "delayed_compare")
4077 (set_attr "length" "4,8")])
4078
4079(define_split
4080 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4081 (compare:CC
4082 (zero_extend:SI
4083 (subreg:QI
4084 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4085 (match_operand:SI 2 "const_int_operand" "")) 0))
4086 (const_int 0)))
4087 (set (match_operand:SI 0 "gpc_reg_operand" "")
4088 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4089 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4090 [(set (match_dup 0)
4091 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4092 (set (match_dup 3)
4093 (compare:CC (match_dup 0)
4094 (const_int 0)))]
4095 "")
1fd4e8c1
RK		 4096
4097(define_insn ""
cd2b37d9 4098 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4099 (zero_extend:SI
4100 (subreg:HI
cd2b37d9 4101 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4102 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4103 "includes_rshift_p (operands[2], GEN_INT (65535))"
ca7f5001 4104 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
1fd4e8c1
RK		 4105
4106(define_insn ""
9ebbca7d 4107 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4108 (compare:CC
4109 (zero_extend:SI
4110 (subreg:HI
9ebbca7d
GK		 4111 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4112 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4113 (const_int 0)))
9ebbca7d 4114 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4115 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4116 "@
4117 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4118 #"
4119 [(set_attr "type" "delayed_compare")
4120 (set_attr "length" "4,8")])
4121
4122(define_split
4123 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4124 (compare:CC
4125 (zero_extend:SI
4126 (subreg:HI
4127 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4128 (match_operand:SI 2 "const_int_operand" "")) 0))
4129 (const_int 0)))
4130 (clobber (match_scratch:SI 3 ""))]
4131 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4132 [(set (match_dup 3)
4133 (zero_extend:SI (subreg:HI
4134 (lshiftrt:SI (match_dup 1)
4135 (match_dup 2)) 0)))
4136 (set (match_dup 0)
4137 (compare:CC (match_dup 3)
4138 (const_int 0)))]
4139 "")
1fd4e8c1
RK		 4140
4141(define_insn ""
9ebbca7d 4142 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4143 (compare:CC
4144 (zero_extend:SI
4145 (subreg:HI
9ebbca7d
GK		 4146 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4147 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4148 (const_int 0)))
9ebbca7d 4149 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4150 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4151 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4152 "@
4153 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4154 #"
4155 [(set_attr "type" "delayed_compare")
4156 (set_attr "length" "4,8")])
4157
4158(define_split
4159 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4160 (compare:CC
4161 (zero_extend:SI
4162 (subreg:HI
4163 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4164 (match_operand:SI 2 "const_int_operand" "")) 0))
4165 (const_int 0)))
4166 (set (match_operand:SI 0 "gpc_reg_operand" "")
4167 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4168 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4169 [(set (match_dup 0)
4170 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4171 (set (match_dup 3)
4172 (compare:CC (match_dup 0)
4173 (const_int 0)))]
4174 "")
1fd4e8c1
RK		 4175
4176(define_insn ""
cd2b37d9 4177 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4178 (const_int 1)
cd2b37d9
RK		 4179 (match_operand:SI 1 "gpc_reg_operand" "r"))
4180 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4181 (const_int 31)))]
ca7f5001 4182 "TARGET_POWER"
1fd4e8c1
RK		 4183 "rrib %0,%1,%2")
4184
4185(define_insn ""
cd2b37d9 4186 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4187 (const_int 1)
cd2b37d9
RK		 4188 (match_operand:SI 1 "gpc_reg_operand" "r"))
4189 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4190 (const_int 31)))]
ca7f5001 4191 "TARGET_POWER"
1fd4e8c1
RK		 4192 "rrib %0,%1,%2")
4193
4194(define_insn ""
cd2b37d9 4195 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4196 (const_int 1)
cd2b37d9
RK		 4197 (match_operand:SI 1 "gpc_reg_operand" "r"))
4198 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4199 (const_int 1)
4200 (const_int 0)))]
ca7f5001 4201 "TARGET_POWER"
1fd4e8c1
RK		 4202 "rrib %0,%1,%2")
4203
ca7f5001
RK		 4204(define_expand "ashrsi3"
4205 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4206 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4207 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4208 ""
4209 "
4210{
4211 if (TARGET_POWER)
4212 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4213 else
25c341fa 4214 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4215 DONE;
4216}")
4217
4218(define_insn "ashrsi3_power"
cd2b37d9
RK		 4219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4220 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4221 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4222 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4223 "TARGET_POWER"
1fd4e8c1
RK		 4224 "@
4225 srea %0,%1,%2
ca7f5001
RK		 4226 {srai|srawi} %0,%1,%h2")
4227
25c341fa 4228(define_insn "ashrsi3_no_power"
ca7f5001
RK		 4229 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4230 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4231 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
25c341fa 4232 "! TARGET_POWER"
d904e9ed 4233 "{sra|sraw}%I2 %0,%1,%h2")
1fd4e8c1
RK		 4234
4235(define_insn ""
9ebbca7d
GK		 4236 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4237 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4238 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4239 (const_int 0)))
9ebbca7d
GK		 4240 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4241 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4242 "TARGET_POWER"
1fd4e8c1
RK		 4243 "@
4244 srea. %3,%1,%2
9ebbca7d
GK		 4245 {srai.|srawi.} %3,%1,%h2
4246 #
4247 #"
4248 [(set_attr "type" "delayed_compare")
4249 (set_attr "length" "4,4,8,8")])
4250
4251(define_split
4252 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4253 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4254 (match_operand:SI 2 "reg_or_cint_operand" ""))
4255 (const_int 0)))
4256 (clobber (match_scratch:SI 3 ""))
4257 (clobber (match_scratch:SI 4 ""))]
4258 "TARGET_POWER && reload_completed"
4259 [(parallel [(set (match_dup 3)
4260 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4261 (clobber (match_dup 4))])
4262 (set (match_dup 0)
4263 (compare:CC (match_dup 3)
4264 (const_int 0)))]
4265 "")
ca7f5001
RK		 4266
4267(define_insn ""
9ebbca7d
GK		 4268 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4269 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4270 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 4271 (const_int 0)))
9ebbca7d 4272 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 4273 "! TARGET_POWER"
9ebbca7d
GK		 4274 "@
4275 {sra|sraw}%I2. %3,%1,%h2
4276 #"
4277 [(set_attr "type" "delayed_compare")
4278 (set_attr "length" "4,8")])
4279
4280(define_split
4281 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4282 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4283 (match_operand:SI 2 "reg_or_cint_operand" ""))
4284 (const_int 0)))
4285 (clobber (match_scratch:SI 3 ""))]
4286 "! TARGET_POWER && reload_completed"
4287 [(set (match_dup 3)
4288 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4289 (set (match_dup 0)
4290 (compare:CC (match_dup 3)
4291 (const_int 0)))]
4292 "")
1fd4e8c1
RK		 4293
4294(define_insn ""
9ebbca7d
GK		 4295 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4296 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4297 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4298 (const_int 0)))
9ebbca7d 4299 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4300 (ashiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4301 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4302 "TARGET_POWER"
1fd4e8c1
RK		 4303 "@
4304 srea. %0,%1,%2
9ebbca7d
GK		 4305 {srai.|srawi.} %0,%1,%h2
4306 #
4307 #"
4308 [(set_attr "type" "delayed_compare")
4309 (set_attr "length" "4,4,8,8")])
4310
4311(define_split
4312 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4313 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4314 (match_operand:SI 2 "reg_or_cint_operand" ""))
4315 (const_int 0)))
4316 (set (match_operand:SI 0 "gpc_reg_operand" "")
4317 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4318 (clobber (match_scratch:SI 4 ""))]
4319 "TARGET_POWER && reload_completed"
4320 [(parallel [(set (match_dup 0)
4321 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4322 (clobber (match_dup 4))])
4323 (set (match_dup 3)
4324 (compare:CC (match_dup 0)
4325 (const_int 0)))]
4326 "")
1fd4e8c1 4327
ca7f5001 4328(define_insn ""
9ebbca7d
GK		 4329 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4330 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4331 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
ca7f5001 4332 (const_int 0)))
9ebbca7d 4333 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 4334 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
25c341fa 4335 "! TARGET_POWER"
9ebbca7d
GK		 4336 "@
4337 {sra|sraw}%I2. %0,%1,%h2
4338 #"
4339 [(set_attr "type" "delayed_compare")
4340 (set_attr "length" "4,8")])
1fd4e8c1 4341\f
9ebbca7d
GK		 4342(define_split
4343 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4344 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4345 (match_operand:SI 2 "reg_or_cint_operand" ""))
4346 (const_int 0)))
4347 (set (match_operand:SI 0 "gpc_reg_operand" "")
4348 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4349 "! TARGET_POWER && reload_completed"
4350 [(set (match_dup 0)
4351 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4352 (set (match_dup 3)
4353 (compare:CC (match_dup 0)
4354 (const_int 0)))]
4355 "")
4356
1fd4e8c1
RK		 4357;; Floating-point insns, excluding normal data motion.
4358;;
ca7f5001
RK		 4359;; PowerPC has a full set of single-precision floating point instructions.
4360;;
4361;; For the POWER architecture, we pretend that we have both SFmode and
4362;; DFmode insns, while, in fact, all fp insns are actually done in double.
4363;; The only conversions we will do will be when storing to memory. In that
4364;; case, we will use the "frsp" instruction before storing.
1fd4e8c1
RK		 4365;;
4366;; Note that when we store into a single-precision memory location, we need to
4367;; use the frsp insn first. If the register being stored isn't dead, we
4368;; need a scratch register for the frsp. But this is difficult when the store
4369;; is done by reload. It is not incorrect to do the frsp on the register in
4370;; this case, we just lose precision that we would have otherwise gotten but
4371;; is not guaranteed. Perhaps this should be tightened up at some point.
4372
e8112008 4373(define_insn "extendsfdf2"
cd2b37d9 4374 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
e8112008 4375 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4376 "TARGET_HARD_FLOAT && TARGET_FPRS"
e8112008 4377 "*
5c30aff8 4378{
e8112008
RK		 4379 if (REGNO (operands[0]) == REGNO (operands[1]))
4380 return \"\";
4381 else
4382 return \"fmr %0,%1\";
4383}"
4384 [(set_attr "type" "fp")])
1fd4e8c1
RK		 4385
4386(define_insn "truncdfsf2"
cd2b37d9
RK		 4387 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4388 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 4389 "TARGET_HARD_FLOAT && TARGET_FPRS"
dcac138d 4390 "frsp %0,%1"
1fd4e8c1
RK		 4391 [(set_attr "type" "fp")])
4392
455350f4
RK		 4393(define_insn "aux_truncdfsf2"
4394 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
615158e2 4395 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
a3170dc6 4396 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
455350f4
RK		 4397 "frsp %0,%1"
4398 [(set_attr "type" "fp")])
4399
a3170dc6
AH		 4400(define_expand "negsf2"
4401 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4402 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4403 "TARGET_HARD_FLOAT"
4404 "")
4405
4406(define_insn "*negsf2"
cd2b37d9
RK		 4407 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4408 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4409 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4410 "fneg %0,%1"
4411 [(set_attr "type" "fp")])
4412
a3170dc6
AH		 4413(define_expand "abssf2"
4414 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4415 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4416 "TARGET_HARD_FLOAT"
4417 "")
4418
4419(define_insn "*abssf2"
cd2b37d9
RK		 4420 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4421 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4422 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4423 "fabs %0,%1"
4424 [(set_attr "type" "fp")])
4425
4426(define_insn ""
cd2b37d9
RK		 4427 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4428 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
a3170dc6 4429 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4430 "fnabs %0,%1"
4431 [(set_attr "type" "fp")])
4432
ca7f5001
RK		 4433(define_expand "addsf3"
4434 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4435 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4436 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4437 "TARGET_HARD_FLOAT"
ca7f5001
RK		 4438 "")
4439
4440(define_insn ""
cd2b37d9
RK		 4441 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4442 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4443 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4444 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4445 "fadds %0,%1,%2"
ca7f5001
RK		 4446 [(set_attr "type" "fp")])
4447
4448(define_insn ""
4449 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4450 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4451 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4452 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4453 "{fa|fadd} %0,%1,%2"
ca7f5001
RK		 4454 [(set_attr "type" "fp")])
4455
4456(define_expand "subsf3"
4457 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4458 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4459 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4460 "TARGET_HARD_FLOAT"
ca7f5001
RK		 4461 "")
4462
4463(define_insn ""
4464 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4465 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4466 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4467 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4468 "fsubs %0,%1,%2"
1fd4e8c1
RK		 4469 [(set_attr "type" "fp")])
4470
ca7f5001 4471(define_insn ""
cd2b37d9
RK		 4472 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4473 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4474 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4475 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4476 "{fs|fsub} %0,%1,%2"
ca7f5001
RK		 4477 [(set_attr "type" "fp")])
4478
4479(define_expand "mulsf3"
4480 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4481 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4482 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4483 "TARGET_HARD_FLOAT"
ca7f5001
RK		 4484 "")
4485
4486(define_insn ""
4487 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4488 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4489 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4490 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4491 "fmuls %0,%1,%2"
1fd4e8c1
RK		 4492 [(set_attr "type" "fp")])
4493
ca7f5001 4494(define_insn ""
cd2b37d9
RK		 4495 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4496 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4497 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4498 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4499 "{fm|fmul} %0,%1,%2"
0780f386 4500 [(set_attr "type" "dmul")])
1fd4e8c1 4501
ca7f5001
RK		 4502(define_expand "divsf3"
4503 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4504 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4505 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 4506 "TARGET_HARD_FLOAT"
ca7f5001
RK		 4507 "")
4508
4509(define_insn ""
cd2b37d9
RK		 4510 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4511 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4512 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4513 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4514 "fdivs %0,%1,%2"
ca7f5001
RK		 4515 [(set_attr "type" "sdiv")])
4516
4517(define_insn ""
4518 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4519 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4520 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 4521 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 4522 "{fd|fdiv} %0,%1,%2"
0780f386 4523 [(set_attr "type" "ddiv")])
1fd4e8c1
RK		 4524
4525(define_insn ""
cd2b37d9
RK		 4526 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4527 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4528 (match_operand:SF 2 "gpc_reg_operand" "f"))
4529 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4530 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4531 "fmadds %0,%1,%2,%3"
ca7f5001
RK		 4532 [(set_attr "type" "fp")])
4533
4534(define_insn ""
4535 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4536 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4537 (match_operand:SF 2 "gpc_reg_operand" "f"))
4538 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4539 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4540 "{fma|fmadd} %0,%1,%2,%3"
cf27b467 4541 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4542
4543(define_insn ""
cd2b37d9
RK		 4544 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4545 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4546 (match_operand:SF 2 "gpc_reg_operand" "f"))
4547 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4548 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4549 "fmsubs %0,%1,%2,%3"
ca7f5001
RK		 4550 [(set_attr "type" "fp")])
4551
4552(define_insn ""
4553 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4554 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4555 (match_operand:SF 2 "gpc_reg_operand" "f"))
4556 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4557 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4558 "{fms|fmsub} %0,%1,%2,%3"
cf27b467 4559 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4560
4561(define_insn ""
cd2b37d9
RK		 4562 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4563 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4564 (match_operand:SF 2 "gpc_reg_operand" "f"))
4565 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4566 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4567 && HONOR_SIGNED_ZEROS (SFmode)"
4568 "fnmadds %0,%1,%2,%3"
4569 [(set_attr "type" "fp")])
4570
4571(define_insn ""
4572 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4573 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4574 (match_operand:SF 2 "gpc_reg_operand" "f"))
4575 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4576 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4577 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 4578 "fnmadds %0,%1,%2,%3"
ca7f5001
RK		 4579 [(set_attr "type" "fp")])
4580
4581(define_insn ""
4582 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4583 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4584 (match_operand:SF 2 "gpc_reg_operand" "f"))
4585 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 4586 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4587 "{fnma|fnmadd} %0,%1,%2,%3"
cf27b467 4588 [(set_attr "type" "dmul")])
1fd4e8c1 4589
16823694
GK		 4590(define_insn ""
4591 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4592 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
4593 (match_operand:SF 2 "gpc_reg_operand" "f"))
4594 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4595 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4596 && ! HONOR_SIGNED_ZEROS (SFmode)"
4597 "{fnma|fnmadd} %0,%1,%2,%3"
4598 [(set_attr "type" "dmul")])
4599
1fd4e8c1 4600(define_insn ""
cd2b37d9
RK		 4601 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4602 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4603 (match_operand:SF 2 "gpc_reg_operand" "f"))
4604 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4605 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4606 && HONOR_SIGNED_ZEROS (SFmode)"
4607 "fnmsubs %0,%1,%2,%3"
4608 [(set_attr "type" "fp")])
4609
4610(define_insn ""
4611 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4612 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4613 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4614 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4615 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4616 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 4617 "fnmsubs %0,%1,%2,%3"
ca7f5001
RK		 4618 [(set_attr "type" "fp")])
4619
4620(define_insn ""
4621 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4622 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4623 (match_operand:SF 2 "gpc_reg_operand" "f"))
4624 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 4625 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 4626 "{fnms|fnmsub} %0,%1,%2,%3"
cf27b467 4627 [(set_attr "type" "dmul")])
1fd4e8c1 4628
16823694
GK		 4629(define_insn ""
4630 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4631 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
4632 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4633 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
4634 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4635 && ! HONOR_SIGNED_ZEROS (SFmode)"
4636 "{fnms|fnmsub} %0,%1,%2,%3"
4637 [(set_attr "type" "fp")])
4638
ca7f5001
RK		 4639(define_expand "sqrtsf2"
4640 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4641 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
a3170dc6 4642 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 4643 "")
4644
4645(define_insn ""
4646 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4647 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4648 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 4649 "fsqrts %0,%1"
4650 [(set_attr "type" "ssqrt")])
4651
4652(define_insn ""
4653 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4654 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 4655 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 4656 "fsqrt %0,%1"
4657 [(set_attr "type" "dsqrt")])
4658
94d7001a
RK		 4659;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4660;; fsel instruction and some auxiliary computations. Then we just have a
4661;; single DEFINE_INSN for fsel and the define_splits to make them if made by
8e871c05
RK		 4662;; combine.
4663(define_expand "maxsf3"
8e871c05 4664 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 4665 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4666 (match_operand:SF 2 "gpc_reg_operand" ""))
8e871c05
RK		 4667 (match_dup 1)
4668 (match_dup 2)))]
a3170dc6 4669 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056 4670 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
2f607b94 4671
8e871c05 4672(define_expand "minsf3"
50a0b056
GK		 4673 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4674 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4675 (match_operand:SF 2 "gpc_reg_operand" ""))
4676 (match_dup 2)
4677 (match_dup 1)))]
a3170dc6 4678 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056 4679 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
2f607b94 4680
8e871c05
RK		 4681(define_split
4682 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 4683 (match_operator:SF 3 "min_max_operator"
4684 [(match_operand:SF 1 "gpc_reg_operand" "")
4685 (match_operand:SF 2 "gpc_reg_operand" "")]))]
a3170dc6 4686 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056
GK		 4687 [(const_int 0)]
4688 "
4689{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4690 operands[1], operands[2]);
4691 DONE;
4692}")
2f607b94 4693
a3170dc6
AH		 4694(define_expand "movsicc"
4695 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4696 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4697 (match_operand:SI 2 "gpc_reg_operand" "")
4698 (match_operand:SI 3 "gpc_reg_operand" "")))]
4699 "TARGET_ISEL"
4700 "
4701{
4702 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4703 DONE;
4704 else
4705 FAIL;
4706}")
4707
4708;; We use the BASE_REGS for the isel input operands because, if rA is
4709;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
4710;; because we may switch the operands and rB may end up being rA.
4711;;
4712;; We need 2 patterns: an unsigned and a signed pattern. We could
4713;; leave out the mode in operand 4 and use one pattern, but reload can
4714;; change the mode underneath our feet and then gets confused trying
4715;; to reload the value.
4716(define_insn "isel_signed"
4717 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4718 (if_then_else:SI
4719 (match_operator 1 "comparison_operator"
4720 [(match_operand:CC 4 "cc_reg_operand" "y")
4721 (const_int 0)])
4722 (match_operand:SI 2 "gpc_reg_operand" "b")
4723 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4724 "TARGET_ISEL"
4725 "*
4726{ return output_isel (operands); }"
4727 [(set_attr "length" "4")])
4728
4729(define_insn "isel_unsigned"
4730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4731 (if_then_else:SI
4732 (match_operator 1 "comparison_operator"
4733 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
4734 (const_int 0)])
4735 (match_operand:SI 2 "gpc_reg_operand" "b")
4736 (match_operand:SI 3 "gpc_reg_operand" "b")))]
4737 "TARGET_ISEL"
4738 "*
4739{ return output_isel (operands); }"
4740 [(set_attr "length" "4")])
4741
94d7001a 4742(define_expand "movsfcc"
0ad91047 4743 [(set (match_operand:SF 0 "gpc_reg_operand" "")
94d7001a 4744 (if_then_else:SF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 4745 (match_operand:SF 2 "gpc_reg_operand" "")
4746 (match_operand:SF 3 "gpc_reg_operand" "")))]
a3170dc6 4747 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 4748 "
4749{
50a0b056
GK		 4750 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4751 DONE;
94d7001a 4752 else
50a0b056 4753 FAIL;
94d7001a 4754}")
d56d506a 4755
50a0b056 4756(define_insn "*fselsfsf4"
8e871c05
RK		 4757 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4758 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 4759 (match_operand:SF 4 "zero_fp_constant" "F"))
8e871c05
RK		 4760 (match_operand:SF 2 "gpc_reg_operand" "f")
4761 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4762 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 4763 "fsel %0,%1,%2,%3"
4764 [(set_attr "type" "fp")])
2f607b94 4765
50a0b056 4766(define_insn "*fseldfsf4"
94d7001a
RK		 4767 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4768 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
d365ba42 4769 (match_operand:DF 4 "zero_fp_constant" "F"))
94d7001a
RK		 4770 (match_operand:SF 2 "gpc_reg_operand" "f")
4771 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 4772 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 4773 "fsel %0,%1,%2,%3"
4774 [(set_attr "type" "fp")])
d56d506a 4775
1fd4e8c1 4776(define_insn "negdf2"
cd2b37d9
RK		 4777 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4778 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 4779 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4780 "fneg %0,%1"
4781 [(set_attr "type" "fp")])
4782
4783(define_insn "absdf2"
cd2b37d9
RK		 4784 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4785 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 4786 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4787 "fabs %0,%1"
4788 [(set_attr "type" "fp")])
4789
4790(define_insn ""
cd2b37d9
RK		 4791 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4792 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
a3170dc6 4793 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4794 "fnabs %0,%1"
4795 [(set_attr "type" "fp")])
4796
4797(define_insn "adddf3"
cd2b37d9
RK		 4798 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4799 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4800 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4801 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4802 "{fa|fadd} %0,%1,%2"
1fd4e8c1
RK		 4803 [(set_attr "type" "fp")])
4804
4805(define_insn "subdf3"
cd2b37d9
RK		 4806 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4807 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4808 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4809 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4810 "{fs|fsub} %0,%1,%2"
1fd4e8c1
RK		 4811 [(set_attr "type" "fp")])
4812
4813(define_insn "muldf3"
cd2b37d9
RK		 4814 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4815 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4816 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4817 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4818 "{fm|fmul} %0,%1,%2"
cfb557c4 4819 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4820
4821(define_insn "divdf3"
cd2b37d9
RK		 4822 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4823 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4824 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 4825 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 4826 "{fd|fdiv} %0,%1,%2"
cfb557c4 4827 [(set_attr "type" "ddiv")])
1fd4e8c1
RK		 4828
4829(define_insn ""
cd2b37d9
RK		 4830 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4831 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4832 (match_operand:DF 2 "gpc_reg_operand" "f"))
4833 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 4834 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 4835 "{fma|fmadd} %0,%1,%2,%3"
cfb557c4 4836 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4837
4838(define_insn ""
cd2b37d9
RK		 4839 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4840 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4841 (match_operand:DF 2 "gpc_reg_operand" "f"))
4842 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 4843 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 4844 "{fms|fmsub} %0,%1,%2,%3"
cfb557c4 4845 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4846
4847(define_insn ""
cd2b37d9
RK		 4848 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4849 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4850 (match_operand:DF 2 "gpc_reg_operand" "f"))
4851 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4852 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4853 && HONOR_SIGNED_ZEROS (DFmode)"
4854 "{fnma|fnmadd} %0,%1,%2,%3"
4855 [(set_attr "type" "dmul")])
4856
4857(define_insn ""
4858 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4859 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
4860 (match_operand:DF 2 "gpc_reg_operand" "f"))
4861 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4862 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4863 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 4864 "{fnma|fnmadd} %0,%1,%2,%3"
cfb557c4 4865 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 4866
4867(define_insn ""
cd2b37d9
RK		 4868 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4869 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4870 (match_operand:DF 2 "gpc_reg_operand" "f"))
4871 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 4872 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4873 && HONOR_SIGNED_ZEROS (DFmode)"
4874 "{fnms|fnmsub} %0,%1,%2,%3"
4875 [(set_attr "type" "dmul")])
4876
4877(define_insn ""
4878 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4879 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
4880 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4881 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
4882 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
4883 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 4884 "{fnms|fnmsub} %0,%1,%2,%3"
cfb557c4 4885 [(set_attr "type" "dmul")])
ca7f5001
RK		 4886
4887(define_insn "sqrtdf2"
4888 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4889 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 4890 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 4891 "fsqrt %0,%1"
4892 [(set_attr "type" "dsqrt")])
b77dfefc 4893
50a0b056
GK		 4894;; The conditional move instructions allow us to perform max and min
4895;; operations even when
b77dfefc 4896
8e871c05 4897(define_expand "maxdf3"
8e871c05 4898 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 4899 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4900 (match_operand:DF 2 "gpc_reg_operand" ""))
8e871c05
RK		 4901 (match_dup 1)
4902 (match_dup 2)))]
a3170dc6 4903 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056 4904 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
b77dfefc 4905
8e871c05 4906(define_expand "mindf3"
50a0b056
GK		 4907 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4908 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
4909 (match_operand:DF 2 "gpc_reg_operand" ""))
4910 (match_dup 2)
4911 (match_dup 1)))]
a3170dc6 4912 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056 4913 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
b77dfefc 4914
8e871c05
RK		 4915(define_split
4916 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 4917 (match_operator:DF 3 "min_max_operator"
4918 [(match_operand:DF 1 "gpc_reg_operand" "")
4919 (match_operand:DF 2 "gpc_reg_operand" "")]))]
a3170dc6 4920 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
50a0b056
GK		 4921 [(const_int 0)]
4922 "
4923{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4924 operands[1], operands[2]);
4925 DONE;
4926}")
b77dfefc 4927
94d7001a 4928(define_expand "movdfcc"
0ad91047 4929 [(set (match_operand:DF 0 "gpc_reg_operand" "")
94d7001a 4930 (if_then_else:DF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 4931 (match_operand:DF 2 "gpc_reg_operand" "")
4932 (match_operand:DF 3 "gpc_reg_operand" "")))]
a3170dc6 4933 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 4934 "
4935{
50a0b056
GK		 4936 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4937 DONE;
94d7001a 4938 else
50a0b056 4939 FAIL;
94d7001a 4940}")
d56d506a 4941
50a0b056 4942(define_insn "*fseldfdf4"
8e871c05
RK		 4943 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4944 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
50a0b056 4945 (match_operand:DF 4 "zero_fp_constant" "F"))
8e871c05
RK		 4946 (match_operand:DF 2 "gpc_reg_operand" "f")
4947 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 4948 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 4949 "fsel %0,%1,%2,%3"
4950 [(set_attr "type" "fp")])
d56d506a 4951
50a0b056 4952(define_insn "*fselsfdf4"
94d7001a
RK		 4953 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4954 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 4955 (match_operand:SF 4 "zero_fp_constant" "F"))
94d7001a
RK		 4956 (match_operand:DF 2 "gpc_reg_operand" "f")
4957 (match_operand:DF 3 "gpc_reg_operand" "f")))]
4958 "TARGET_PPC_GFXOPT"
4959 "fsel %0,%1,%2,%3"
4960 [(set_attr "type" "fp")])
1fd4e8c1
RK		 4961\f
4962;; Conversions to and from floating-point.
802a0058 4963
a3170dc6
AH		 4964(define_expand "fixunssfsi2"
4965 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4966 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "gpc_reg_operand" ""))))]
4967 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4968 "")
4969
4970(define_expand "fix_truncsfsi2"
4971 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4972 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
4973 "TARGET_HARD_FLOAT && !TARGET_FPRS"
4974 "")
4975
9ebbca7d
GK		 4976; For each of these conversions, there is a define_expand, a define_insn
4977; with a '#' template, and a define_split (with C code). The idea is
4978; to allow constant folding with the template of the define_insn,
4979; then to have the insns split later (between sched1 and final).
4980
1fd4e8c1 4981(define_expand "floatsidf2"
802a0058
MM		 4982 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
4983 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
4984 (use (match_dup 2))
4985 (use (match_dup 3))
208c89ce 4986 (clobber (match_dup 4))
a7df97e6 4987 (clobber (match_dup 5))
9ebbca7d 4988 (clobber (match_dup 6))])]
a3170dc6 4989 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 4990 "
4991{
05d49501
AM		 4992 if (TARGET_POWERPC64)
4993 {
4994 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
4995 rtx t1 = gen_reg_rtx (DImode);
4996 rtx t2 = gen_reg_rtx (DImode);
4997 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
4998 DONE;
4999 }
5000
802a0058 5001 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5002 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
9ebbca7d
GK		 5003 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5004 operands[5] = gen_reg_rtx (DFmode);
5005 operands[6] = gen_reg_rtx (SImode);
1fd4e8c1
RK		 5006}")
5007
802a0058
MM		 5008(define_insn "*floatsidf2_internal"
5009 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5010 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5011 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5012 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
9ebbca7d 5013 (clobber (match_operand:DF 4 "memory_operand" "=o"))
6f9c81f5
DJ		 5014 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5015 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
a3170dc6 5016 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5017 "#"
a7df97e6 5018 [(set_attr "length" "24")])
802a0058
MM		 5019
5020(define_split
dbe3df29 5021 [(set (match_operand:DF 0 "gpc_reg_operand" "")
802a0058
MM		 5022 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5023 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5024 (use (match_operand:DF 3 "gpc_reg_operand" ""))
9ebbca7d
GK		 5025 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5026 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5027 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
a3170dc6 5028 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
9ebbca7d
GK		 5029 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5030 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5031 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5032 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5033 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5034 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5035 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
208c89ce
MM		 5036 "
5037{
9ebbca7d
GK		 5038 rtx lowword, highword;
5039 if (GET_CODE (operands[4]) != MEM)
5040 abort();
5041 highword = XEXP (operands[4], 0);
5042 lowword = plus_constant (highword, 4);
5043 if (! WORDS_BIG_ENDIAN)
5044 {
5045 rtx tmp;
5046 tmp = highword; highword = lowword; lowword = tmp;
5047 }
5048
5049 emit_insn (gen_xorsi3 (operands[6], operands[1],
5050 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5051 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5052 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5053 emit_move_insn (operands[5], operands[4]);
5054 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5055 DONE;
208c89ce 5056}")
802a0058 5057
a3170dc6
AH		 5058(define_expand "floatunssisf2"
5059 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5060 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5061 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5062 "")
5063
802a0058
MM		 5064(define_expand "floatunssidf2"
5065 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5066 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5067 (use (match_dup 2))
5068 (use (match_dup 3))
a7df97e6 5069 (clobber (match_dup 4))
9ebbca7d 5070 (clobber (match_dup 5))])]
a3170dc6 5071 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5072 "
5073{
05d49501
AM		 5074 if (TARGET_POWERPC64)
5075 {
5076 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5077 rtx t1 = gen_reg_rtx (DImode);
5078 rtx t2 = gen_reg_rtx (DImode);
5079 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5080 t1, t2));
5081 DONE;
5082 }
5083
802a0058 5084 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5085 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
9ebbca7d
GK		 5086 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5087 operands[5] = gen_reg_rtx (DFmode);
1fd4e8c1
RK		 5088}")
5089
802a0058
MM		 5090(define_insn "*floatunssidf2_internal"
5091 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5092 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5093 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5094 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
9ebbca7d 5095 (clobber (match_operand:DF 4 "memory_operand" "=o"))
6f9c81f5 5096 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
a3170dc6 5097 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5098 "#"
a7df97e6 5099 [(set_attr "length" "20")])
802a0058
MM		 5100
5101(define_split
5102 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5103 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5104 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5105 (use (match_operand:DF 3 "gpc_reg_operand" ""))
9ebbca7d
GK		 5106 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5107 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
a3170dc6 5108 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
9ebbca7d
GK		 5109 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5110 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5111 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5112 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5113 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5114 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5115 "
802a0058 5116{
9ebbca7d
GK		 5117 rtx lowword, highword;
5118 if (GET_CODE (operands[4]) != MEM)
5119 abort();
5120 highword = XEXP (operands[4], 0);
5121 lowword = plus_constant (highword, 4);
5122 if (! WORDS_BIG_ENDIAN)
f6968f59 5123 {
9ebbca7d
GK		 5124 rtx tmp;
5125 tmp = highword; highword = lowword; lowword = tmp;
f6968f59 5126 }
802a0058 5127
9ebbca7d
GK		 5128 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5129 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5130 emit_move_insn (operands[5], operands[4]);
5131 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5132 DONE;
5133}")
1fd4e8c1 5134
1fd4e8c1 5135(define_expand "fix_truncdfsi2"
802a0058
MM		 5136 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5137 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5138 (clobber (match_dup 2))
9ebbca7d 5139 (clobber (match_dup 3))])]
a3170dc6 5140 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5141 "
5142{
802a0058 5143 operands[2] = gen_reg_rtx (DImode);
9ebbca7d 5144 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
1fd4e8c1
RK		 5145}")
5146
802a0058
MM		 5147(define_insn "*fix_truncdfsi2_internal"
5148 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5149 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
e3485bbc 5150 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
9ebbca7d 5151 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
a3170dc6 5152 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5153 "#"
9ebbca7d 5154 [(set_attr "length" "16")])
802a0058
MM		 5155
5156(define_split
5157 [(set (match_operand:SI 0 "gpc_reg_operand" "")
75540af0 5158 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
802a0058 5159 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
9ebbca7d 5160 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
a3170dc6 5161 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
9ebbca7d 5162 [(set (match_operand:SI 0 "gpc_reg_operand" "")
75540af0 5163 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
9ebbca7d
GK		 5164 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5165 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5166 "
802a0058 5167{
9ebbca7d
GK		 5168 rtx lowword;
5169 if (GET_CODE (operands[3]) != MEM)
5170 abort();
5171 lowword = XEXP (operands[3], 0);
5172 if (WORDS_BIG_ENDIAN)
5173 lowword = plus_constant (lowword, 4);
802a0058 5174
9ebbca7d
GK		 5175 emit_insn (gen_fctiwz (operands[2], operands[1]));
5176 emit_move_insn (operands[3], operands[2]);
5177 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5178 DONE;
5179}")
802a0058 5180
615158e2 5181; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
9ebbca7d
GK		 5182; rather than (set (subreg:SI (reg)) (fix:SI ...))
5183; because the first makes it clear that operand 0 is not live
5184; before the instruction.
5185(define_insn "fctiwz"
61c07d3c 5186 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
615158e2
JJ		 5187 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5188 UNSPEC_FCTIWZ))]
a3170dc6 5189 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
a260abc9
DE		 5190 "{fcirz|fctiwz} %0,%1"
5191 [(set_attr "type" "fp")])
5192
a3170dc6
AH		 5193(define_expand "floatsisf2"
5194 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5195 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5196 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5197 "")
5198
a473029f
RK		 5199(define_insn "floatdidf2"
5200 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
61c07d3c 5201 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
a3170dc6 5202 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 5203 "fcfid %0,%1"
5204 [(set_attr "type" "fp")])
5205
05d49501
AM		 5206(define_insn_and_split "floatsidf_ppc64"
5207 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5208 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5209 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5210 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5211 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
a3170dc6 5212 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501 5213 "#"
ecb62ae7 5214 "&& 1"
05d49501
AM		 5215 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5216 (set (match_dup 2) (match_dup 3))
5217 (set (match_dup 4) (match_dup 2))
5218 (set (match_dup 0) (float:DF (match_dup 4)))]
5219 "")
5220
5221(define_insn_and_split "floatunssidf_ppc64"
5222 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5223 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5224 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5225 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5226 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
a3170dc6 5227 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501 5228 "#"
ecb62ae7 5229 "&& 1"
05d49501
AM		 5230 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5231 (set (match_dup 2) (match_dup 3))
5232 (set (match_dup 4) (match_dup 2))
5233 (set (match_dup 0) (float:DF (match_dup 4)))]
5234 "")
5235
a473029f 5236(define_insn "fix_truncdfdi2"
61c07d3c 5237 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
a473029f 5238 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5239 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 5240 "fctidz %0,%1"
5241 [(set_attr "type" "fp")])
ea112fc4 5242
678b7733
AM		 5243(define_expand "floatdisf2"
5244 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5245 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
683bdff7 5246 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 5247 "
5248{
5249 if (!flag_unsafe_math_optimizations)
5250 {
5251 rtx label = gen_label_rtx ();
5252 emit_insn (gen_floatdisf2_internal2 (operands[1], label));
5253 emit_label (label);
5254 }
5255 emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1]));
5256 DONE;
5257}")
5258
5259;; This is not IEEE compliant if rounding mode is "round to nearest".
5260;; If the DI->DF conversion is inexact, then it's possible to suffer
5261;; from double rounding.
5262(define_insn_and_split "floatdisf2_internal1"
ea112fc4 5263 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
61c07d3c 5264 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
ea112fc4 5265 (clobber (match_scratch:DF 2 "=f"))]
678b7733 5266 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
ea112fc4
DE		 5267 "#"
5268 "&& reload_completed"
5269 [(set (match_dup 2)
5270 (float:DF (match_dup 1)))
5271 (set (match_dup 0)
5272 (float_truncate:SF (match_dup 2)))]
5273 "")
678b7733
AM		 5274
5275;; Twiddles bits to avoid double rounding.
b6d08ca1 5276;; Bits that might be truncated when converting to DFmode are replaced
678b7733
AM		 5277;; by a bit that won't be lost at that stage, but is below the SFmode
5278;; rounding position.
5279(define_expand "floatdisf2_internal2"
42a6388c
AM		 5280 [(parallel [(set (match_dup 4)
5281 (compare:CC (and:DI (match_operand:DI 0 "" "")
5282 (const_int 2047))
5283 (const_int 0)))
5284 (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047)))
5285 (clobber (match_scratch:CC 7 ""))])
678b7733
AM		 5286 (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53)))
5287 (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1)))
5288 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
5289 (label_ref (match_operand:DI 1 "" ""))
5290 (pc)))
5291 (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2)))
5292 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
5293 (label_ref (match_dup 1))
5294 (pc)))
5295 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2)))
5296 (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))]
683bdff7 5297 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 5298 "
5299{
5300 operands[2] = gen_reg_rtx (DImode);
5301 operands[3] = gen_reg_rtx (DImode);
5302 operands[4] = gen_reg_rtx (CCmode);
5303 operands[5] = gen_reg_rtx (CCUNSmode);
5304}")
1fd4e8c1
RK		 5305\f
5306;; Define the DImode operations that can be done in a small number
a6ec530c
RK		 5307;; of instructions. The & constraints are to prevent the register
5308;; allocator from allocating registers that overlap with the inputs
5309;; (for example, having an input in 7,8 and an output in 6,7). We
38e01259 5310;; also allow for the output being the same as one of the inputs.
a6ec530c 5311
266eb58a 5312(define_insn "*adddi3_noppc64"
a6ec530c
RK		 5313 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5314 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5315 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
e1f83b4d 5316 "! TARGET_POWERPC64"
0f645302
MM		 5317 "*
5318{
5319 if (WORDS_BIG_ENDIAN)
5320 return (GET_CODE (operands[2])) != CONST_INT
5321 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5322 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5323 else
5324 return (GET_CODE (operands[2])) != CONST_INT
5325 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5326 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5327}"
b19003d8 5328 [(set_attr "length" "8")])
1fd4e8c1 5329
266eb58a 5330(define_insn "*subdi3_noppc64"
e7e5df70
RK		 5331 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5332 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5333 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
266eb58a 5334 "! TARGET_POWERPC64"
5502823b
RK		 5335 "*
5336{
0f645302
MM		 5337 if (WORDS_BIG_ENDIAN)
5338 return (GET_CODE (operands[1]) != CONST_INT)
5339 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5340 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5341 else
5342 return (GET_CODE (operands[1]) != CONST_INT)
5343 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5344 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5502823b 5345}"
ca7f5001
RK		 5346 [(set_attr "length" "8")])
5347
266eb58a 5348(define_insn "*negdi2_noppc64"
a6ec530c
RK		 5349 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5350 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
51b8fc2c 5351 "! TARGET_POWERPC64"
5502823b
RK		 5352 "*
5353{
5354 return (WORDS_BIG_ENDIAN)
5355 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5356 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5357}"
ca7f5001
RK		 5358 [(set_attr "length" "8")])
5359
8ffd9c51
RK		 5360(define_expand "mulsidi3"
5361 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5362 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5363 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
a2f270cc 5364 "! TARGET_POWERPC64"
8ffd9c51
RK		 5365 "
5366{
5367 if (! TARGET_POWER && ! TARGET_POWERPC)
5368 {
39403d82
DE		 5369 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5370 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 5371 emit_insn (gen_mull_call ());
cf27b467 5372 if (WORDS_BIG_ENDIAN)
39403d82 5373 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
cf27b467
MM		 5374 else
5375 {
5376 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
39403d82 5377 gen_rtx_REG (SImode, 3));
cf27b467 5378 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
39403d82 5379 gen_rtx_REG (SImode, 4));
cf27b467 5380 }
8ffd9c51
RK		 5381 DONE;
5382 }
5383 else if (TARGET_POWER)
5384 {
5385 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5386 DONE;
5387 }
5388}")
deb9225a 5389
8ffd9c51 5390(define_insn "mulsidi3_mq"
cd2b37d9 5391 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8ffd9c51 5392 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
cd2b37d9 5393 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1fd4e8c1 5394 (clobber (match_scratch:SI 3 "=q"))]
ca7f5001 5395 "TARGET_POWER"
b19003d8 5396 "mul %0,%1,%2\;mfmq %L0"
8ffd9c51
RK		 5397 [(set_attr "type" "imul")
5398 (set_attr "length" "8")])
deb9225a 5399
f192bf8b 5400(define_insn "*mulsidi3_no_mq"
425c176f 5401 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
8ffd9c51
RK		 5402 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5403 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 5404 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5502823b
RK		 5405 "*
5406{
5407 return (WORDS_BIG_ENDIAN)
5408 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5409 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5410}"
8ffd9c51
RK		 5411 [(set_attr "type" "imul")
5412 (set_attr "length" "8")])
deb9225a 5413
ebedb4dd
MM		 5414(define_split
5415 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5416 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5417 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 5418 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 5419 [(set (match_dup 3)
5420 (truncate:SI
5421 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5422 (sign_extend:DI (match_dup 2)))
5423 (const_int 32))))
5424 (set (match_dup 4)
5425 (mult:SI (match_dup 1)
5426 (match_dup 2)))]
5427 "
5428{
5429 int endian = (WORDS_BIG_ENDIAN == 0);
5430 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5431 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5432}")
5433
f192bf8b
DE		 5434(define_expand "umulsidi3"
5435 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5436 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5437 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5438 "TARGET_POWERPC && ! TARGET_POWERPC64"
5439 "
5440{
5441 if (TARGET_POWER)
5442 {
5443 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5444 DONE;
5445 }
5446}")
5447
5448(define_insn "umulsidi3_mq"
5449 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5450 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5451 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5452 (clobber (match_scratch:SI 3 "=q"))]
5453 "TARGET_POWERPC && TARGET_POWER"
5454 "*
5455{
5456 return (WORDS_BIG_ENDIAN)
5457 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5458 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5459}"
5460 [(set_attr "type" "imul")
5461 (set_attr "length" "8")])
5462
5463(define_insn "*umulsidi3_no_mq"
8106dc08
MM		 5464 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5465 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5466 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 5467 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
8106dc08
MM		 5468 "*
5469{
5470 return (WORDS_BIG_ENDIAN)
5471 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5472 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5473}"
5474 [(set_attr "type" "imul")
5475 (set_attr "length" "8")])
5476
ebedb4dd
MM		 5477(define_split
5478 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5479 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5480 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 5481 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 5482 [(set (match_dup 3)
5483 (truncate:SI
5484 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5485 (zero_extend:DI (match_dup 2)))
5486 (const_int 32))))
5487 (set (match_dup 4)
5488 (mult:SI (match_dup 1)
5489 (match_dup 2)))]
5490 "
5491{
5492 int endian = (WORDS_BIG_ENDIAN == 0);
5493 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5494 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5495}")
5496
8ffd9c51
RK		 5497(define_expand "smulsi3_highpart"
5498 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5499 (truncate:SI
5500 (lshiftrt:DI (mult:DI (sign_extend:DI
5501 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5502 (sign_extend:DI
5503 (match_operand:SI 2 "gpc_reg_operand" "r")))
5504 (const_int 32))))]
5505 ""
5506 "
5507{
5508 if (! TARGET_POWER && ! TARGET_POWERPC)
5509 {
39403d82
DE		 5510 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5511 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 5512 emit_insn (gen_mulh_call ());
39403d82 5513 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 5514 DONE;
5515 }
5516 else if (TARGET_POWER)
5517 {
5518 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5519 DONE;
5520 }
5521}")
deb9225a 5522
8ffd9c51
RK		 5523(define_insn "smulsi3_highpart_mq"
5524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5525 (truncate:SI
fada905b
MM		 5526 (lshiftrt:DI (mult:DI (sign_extend:DI
5527 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5528 (sign_extend:DI
5529 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51
RK		 5530 (const_int 32))))
5531 (clobber (match_scratch:SI 3 "=q"))]
5532 "TARGET_POWER"
5533 "mul %0,%1,%2"
5534 [(set_attr "type" "imul")])
deb9225a 5535
f192bf8b 5536(define_insn "*smulsi3_highpart_no_mq"
8ffd9c51
RK		 5537 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5538 (truncate:SI
fada905b
MM		 5539 (lshiftrt:DI (mult:DI (sign_extend:DI
5540 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5541 (sign_extend:DI
5542 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51 5543 (const_int 32))))]
f192bf8b 5544 "TARGET_POWERPC && ! TARGET_POWER"
8ffd9c51
RK		 5545 "mulhw %0,%1,%2"
5546 [(set_attr "type" "imul")])
deb9225a 5547
f192bf8b
DE		 5548(define_expand "umulsi3_highpart"
5549 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5550 (truncate:SI
5551 (lshiftrt:DI (mult:DI (zero_extend:DI
5552 (match_operand:SI 1 "gpc_reg_operand" ""))
5553 (zero_extend:DI
5554 (match_operand:SI 2 "gpc_reg_operand" "")))
5555 (const_int 32))))]
5556 "TARGET_POWERPC"
5557 "
5558{
5559 if (TARGET_POWER)
5560 {
5561 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5562 DONE;
5563 }
5564}")
5565
5566(define_insn "umulsi3_highpart_mq"
5567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5568 (truncate:SI
5569 (lshiftrt:DI (mult:DI (zero_extend:DI
5570 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5571 (zero_extend:DI
5572 (match_operand:SI 2 "gpc_reg_operand" "r")))
5573 (const_int 32))))
5574 (clobber (match_scratch:SI 3 "=q"))]
5575 "TARGET_POWERPC && TARGET_POWER"
5576 "mulhwu %0,%1,%2"
5577 [(set_attr "type" "imul")])
5578
5579(define_insn "*umulsi3_highpart_no_mq"
266eb58a
DE		 5580 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5581 (truncate:SI
5582 (lshiftrt:DI (mult:DI (zero_extend:DI
5583 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5584 (zero_extend:DI
5585 (match_operand:SI 2 "gpc_reg_operand" "r")))
5586 (const_int 32))))]
f192bf8b 5587 "TARGET_POWERPC && ! TARGET_POWER"
266eb58a
DE		 5588 "mulhwu %0,%1,%2"
5589 [(set_attr "type" "imul")])
5590
5591;; If operands 0 and 2 are in the same register, we have a problem. But
5592;; operands 0 and 1 (the usual case) can be in the same register. That's
5593;; why we have the strange constraints below.
5594(define_insn "ashldi3_power"
5595 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5596 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5597 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5598 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5599 "TARGET_POWER"
5600 "@
5601 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5602 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5603 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5604 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5605 [(set_attr "length" "8")])
5606
5607(define_insn "lshrdi3_power"
47ad8c61 5608 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
266eb58a
DE		 5609 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5610 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5611 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5612 "TARGET_POWER"
5613 "@
47ad8c61 5614 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
266eb58a
DE		 5615 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5616 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5617 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5618 [(set_attr "length" "8")])
5619
5620;; Shift by a variable amount is too complex to be worth open-coding. We
5621;; just handle shifts by constants.
5622(define_insn "ashrdi3_power"
7093ddee 5623 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
266eb58a
DE		 5624 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5625 (match_operand:SI 2 "const_int_operand" "M,i")))
5626 (clobber (match_scratch:SI 3 "=X,q"))]
5627 "TARGET_POWER"
5628 "@
5629 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5630 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5631 [(set_attr "length" "8")])
4aa74a4f
FS		 5632
5633(define_insn "ashrdi3_no_power"
5634 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
5635 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5636 (match_operand:SI 2 "const_int_operand" "M,i")))]
683bdff7 5637 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER"
4aa74a4f
FS		 5638 "@
5639 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5640 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
5641 [(set_attr "length" "8,12")])
683bdff7
FJ		 5642
5643(define_insn "*ashrdisi3_noppc64"
5644 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5645 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
5646 (const_int 32)) 4))]
5647 "TARGET_32BIT && !TARGET_POWERPC64"
5648 "*
5649{
5650 if (REGNO (operands[0]) == REGNO (operands[1]))
5651 return \"\";
5652 else
5653 return \"mr %0,%1\";
5654}"
5655 [(set_attr "length" "4")])
5656
266eb58a
DE		 5657\f
5658;; PowerPC64 DImode operations.
5659
5660(define_expand "adddi3"
5661 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5662 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
2bfcf297 5663 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
266eb58a
DE		 5664 ""
5665 "
5666{
a260abc9
DE		 5667 if (! TARGET_POWERPC64)
5668 {
5669 if (non_short_cint_operand (operands[2], DImode))
5670 FAIL;
5671 }
5672 else
5673 if (GET_CODE (operands[2]) == CONST_INT
677a9668 5674 && ! add_operand (operands[2], DImode))
a260abc9 5675 {
677a9668 5676 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
a260abc9
DE		 5677 ? operands[0] : gen_reg_rtx (DImode));
5678
2bfcf297 5679 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 5680 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2bfcf297 5681 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
a260abc9 5682
2bfcf297
DB		 5683 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5684 FAIL;
a260abc9 5685
2bfcf297
DB		 5686 /* The ordering here is important for the prolog expander.
5687 When space is allocated from the stack, adding 'low' first may
5688 produce a temporary deallocation (which would be bad). */
5689 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
a260abc9
DE		 5690 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5691 DONE;
5692 }
266eb58a
DE		 5693}")
5694
5695;; Discourage ai/addic because of carry but provide it in an alternative
5696;; allowing register zero as source.
5697
a260abc9 5698(define_insn "*adddi3_internal1"
266eb58a
DE		 5699 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5700 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
9615f239 5701 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
266eb58a
DE		 5702 "TARGET_POWERPC64"
5703 "@
5704 add %0,%1,%2
5705 addi %0,%1,%2
5706 addic %0,%1,%2
802a0058 5707 addis %0,%1,%v2")
266eb58a 5708
a260abc9 5709(define_insn "*adddi3_internal2"
9ebbca7d
GK		 5710 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5711 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5712 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
266eb58a 5713 (const_int 0)))
9ebbca7d 5714 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 5715 "TARGET_64BIT"
266eb58a
DE		 5716 "@
5717 add. %3,%1,%2
9ebbca7d
GK		 5718 addic. %3,%1,%2
5719 #
5720 #"
a62bfff2 5721 [(set_attr "type" "fast_compare,compare,compare,compare")
9ebbca7d
GK		 5722 (set_attr "length" "4,4,8,8")])
5723
5724(define_split
5725 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5726 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5727 (match_operand:DI 2 "reg_or_short_operand" ""))
5728 (const_int 0)))
5729 (clobber (match_scratch:DI 3 ""))]
5730 "TARGET_POWERPC64 && reload_completed"
5731 [(set (match_dup 3)
5732 (plus:DI (match_dup 1) (match_dup 2)))
5733 (set (match_dup 0)
5734 (compare:CC (match_dup 3)
5735 (const_int 0)))]
5736 "")
266eb58a 5737
a260abc9 5738(define_insn "*adddi3_internal3"
9ebbca7d
GK		 5739 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5740 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5741 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
266eb58a 5742 (const_int 0)))
9ebbca7d 5743 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 5744 (plus:DI (match_dup 1) (match_dup 2)))]
683bdff7 5745 "TARGET_64BIT"
266eb58a
DE		 5746 "@
5747 add. %0,%1,%2
9ebbca7d
GK		 5748 addic. %0,%1,%2
5749 #
5750 #"
a62bfff2 5751 [(set_attr "type" "fast_compare,compare,compare,compare")
9ebbca7d
GK		 5752 (set_attr "length" "4,4,8,8")])
5753
5754(define_split
5755 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5756 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5757 (match_operand:DI 2 "reg_or_short_operand" ""))
5758 (const_int 0)))
5759 (set (match_operand:DI 0 "gpc_reg_operand" "")
5760 (plus:DI (match_dup 1) (match_dup 2)))]
5761 "TARGET_POWERPC64 && reload_completed"
5762 [(set (match_dup 0)
5763 (plus:DI (match_dup 1) (match_dup 2)))
5764 (set (match_dup 3)
5765 (compare:CC (match_dup 0)
5766 (const_int 0)))]
5767 "")
266eb58a
DE		 5768
5769;; Split an add that we can't do in one insn into two insns, each of which
5770;; does one 16-bit part. This is used by combine. Note that the low-order
5771;; add should be last in case the result gets used in an address.
5772
5773(define_split
5774 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5775 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5776 (match_operand:DI 2 "non_add_cint_operand" "")))]
5777 "TARGET_POWERPC64"
5778 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5779 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5780"
5781{
2bfcf297 5782 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 5783 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
2bfcf297 5784 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
266eb58a 5785
2bfcf297
DB		 5786 operands[4] = GEN_INT (low);
5787 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5788 operands[3] = GEN_INT (rest);
5789 else if (! no_new_pseudos)
38886f37 5790 {
2bfcf297
DB		 5791 operands[3] = gen_reg_rtx (DImode);
5792 emit_move_insn (operands[3], operands[2]);
5793 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5794 DONE;
38886f37 5795 }
2bfcf297
DB		 5796 else
5797 FAIL;
266eb58a
DE		 5798}")
5799
5800(define_insn "one_cmpldi2"
5801 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5802 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5803 "TARGET_POWERPC64"
5804 "nor %0,%1,%1")
5805
5806(define_insn ""
9ebbca7d
GK		 5807 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5808 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
266eb58a 5809 (const_int 0)))
9ebbca7d 5810 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 5811 "TARGET_64BIT"
9ebbca7d
GK		 5812 "@
5813 nor. %2,%1,%1
5814 #"
5815 [(set_attr "type" "compare")
5816 (set_attr "length" "4,8")])
5817
5818(define_split
5819 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5820 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5821 (const_int 0)))
5822 (clobber (match_scratch:DI 2 ""))]
5823 "TARGET_POWERPC64 && reload_completed"
5824 [(set (match_dup 2)
5825 (not:DI (match_dup 1)))
5826 (set (match_dup 0)
5827 (compare:CC (match_dup 2)
5828 (const_int 0)))]
5829 "")
266eb58a
DE		 5830
5831(define_insn ""
9ebbca7d
GK		 5832 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5833 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
266eb58a 5834 (const_int 0)))
9ebbca7d 5835 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 5836 (not:DI (match_dup 1)))]
683bdff7 5837 "TARGET_64BIT"
9ebbca7d
GK		 5838 "@
5839 nor. %0,%1,%1
5840 #"
5841 [(set_attr "type" "compare")
5842 (set_attr "length" "4,8")])
5843
5844(define_split
5845 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5846 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5847 (const_int 0)))
5848 (set (match_operand:DI 0 "gpc_reg_operand" "")
5849 (not:DI (match_dup 1)))]
5850 "TARGET_POWERPC64 && reload_completed"
5851 [(set (match_dup 0)
5852 (not:DI (match_dup 1)))
5853 (set (match_dup 2)
5854 (compare:CC (match_dup 0)
5855 (const_int 0)))]
5856 "")
266eb58a
DE		 5857
5858(define_insn ""
5859 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5860 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5861 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5862 "TARGET_POWERPC64"
5863 "@
5864 subf %0,%2,%1
5865 subfic %0,%2,%1")
5866
5867(define_insn ""
9ebbca7d
GK		 5868 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5869 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5870 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
266eb58a 5871 (const_int 0)))
9ebbca7d 5872 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 5873 "TARGET_64BIT"
9ebbca7d
GK		 5874 "@
5875 subf. %3,%2,%1
5876 #"
a62bfff2 5877 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 5878 (set_attr "length" "4,8")])
5879
5880(define_split
5881 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5882 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5883 (match_operand:DI 2 "gpc_reg_operand" ""))
5884 (const_int 0)))
5885 (clobber (match_scratch:DI 3 ""))]
5886 "TARGET_POWERPC64 && reload_completed"
5887 [(set (match_dup 3)
5888 (minus:DI (match_dup 1) (match_dup 2)))
5889 (set (match_dup 0)
5890 (compare:CC (match_dup 3)
5891 (const_int 0)))]
5892 "")
266eb58a
DE		 5893
5894(define_insn ""
9ebbca7d
GK		 5895 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5896 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5897 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
266eb58a 5898 (const_int 0)))
9ebbca7d 5899 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 5900 (minus:DI (match_dup 1) (match_dup 2)))]
683bdff7 5901 "TARGET_64BIT"
9ebbca7d
GK		 5902 "@
5903 subf. %0,%2,%1
5904 #"
a62bfff2 5905 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 5906 (set_attr "length" "4,8")])
5907
5908(define_split
5909 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5910 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5911 (match_operand:DI 2 "gpc_reg_operand" ""))
5912 (const_int 0)))
5913 (set (match_operand:DI 0 "gpc_reg_operand" "")
5914 (minus:DI (match_dup 1) (match_dup 2)))]
5915 "TARGET_POWERPC64 && reload_completed"
5916 [(set (match_dup 0)
5917 (minus:DI (match_dup 1) (match_dup 2)))
5918 (set (match_dup 3)
5919 (compare:CC (match_dup 0)
5920 (const_int 0)))]
5921 "")
266eb58a
DE		 5922
5923(define_expand "subdi3"
5924 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5925 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
2bfcf297 5926 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
266eb58a
DE		 5927 ""
5928 "
5929{
5930 if (GET_CODE (operands[2]) == CONST_INT)
5931 {
5932 emit_insn (gen_adddi3 (operands[0], operands[1],
5933 negate_rtx (DImode, operands[2])));
5934 DONE;
5935 }
5936}")
5937
ea112fc4 5938(define_insn_and_split "absdi2"
266eb58a 5939 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 5940 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
266eb58a
DE		 5941 (clobber (match_scratch:DI 2 "=&r,&r"))]
5942 "TARGET_POWERPC64"
ea112fc4
DE		 5943 "#"
5944 "&& reload_completed"
a260abc9 5945 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 5946 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
a238cd8b 5947 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
266eb58a
DE		 5948 "")
5949
ea112fc4 5950(define_insn_and_split "*nabsdi2"
266eb58a 5951 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 5952 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
266eb58a
DE		 5953 (clobber (match_scratch:DI 2 "=&r,&r"))]
5954 "TARGET_POWERPC64"
ea112fc4
DE		 5955 "#"
5956 "&& reload_completed"
a260abc9 5957 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 5958 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
19ba8161 5959 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
266eb58a
DE		 5960 "")
5961
5962(define_expand "negdi2"
5963 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5964 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
5965 ""
5966 "")
5967
5968(define_insn ""
5969 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5970 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5971 "TARGET_POWERPC64"
5972 "neg %0,%1")
5973
5974(define_insn ""
9ebbca7d
GK		 5975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5976 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
266eb58a 5977 (const_int 0)))
9ebbca7d 5978 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 5979 "TARGET_64BIT"
9ebbca7d
GK		 5980 "@
5981 neg. %2,%1
5982 #"
a62bfff2 5983 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 5984 (set_attr "length" "4,8")])
5985
5986(define_split
5987 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5988 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5989 (const_int 0)))
5990 (clobber (match_scratch:DI 2 ""))]
5991 "TARGET_POWERPC64 && reload_completed"
5992 [(set (match_dup 2)
5993 (neg:DI (match_dup 1)))
5994 (set (match_dup 0)
5995 (compare:CC (match_dup 2)
5996 (const_int 0)))]
5997 "")
815cdc52 5998
29ae5b89 5999(define_insn ""
9ebbca7d
GK		 6000 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6001 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
815cdc52 6002 (const_int 0)))
9ebbca7d 6003 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
815cdc52 6004 (neg:DI (match_dup 1)))]
683bdff7 6005 "TARGET_64BIT"
9ebbca7d
GK		 6006 "@
6007 neg. %0,%1
6008 #"
a62bfff2 6009 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 6010 (set_attr "length" "4,8")])
6011
6012(define_split
6013 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6014 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6015 (const_int 0)))
6016 (set (match_operand:DI 0 "gpc_reg_operand" "")
6017 (neg:DI (match_dup 1)))]
6018 "TARGET_POWERPC64 && reload_completed"
6019 [(set (match_dup 0)
6020 (neg:DI (match_dup 1)))
6021 (set (match_dup 2)
6022 (compare:CC (match_dup 0)
6023 (const_int 0)))]
6024 "")
266eb58a 6025
1b1edcfa
DE		 6026(define_insn "clzdi2"
6027 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6028 (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6029 "TARGET_POWERPC64"
6030 "cntlzd %0,%1")
6031
6032(define_expand "ctzdi2"
4977bab6 6033 [(set (match_dup 2)
1b1edcfa 6034 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
4977bab6 6035 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
1b1edcfa
DE		 6036 (match_dup 2)))
6037 (clobber (scratch:CC))])
d865b122 6038 (set (match_dup 4) (clz:DI (match_dup 3)))
4977bab6 6039 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
1b1edcfa 6040 (minus:DI (const_int 63) (match_dup 4)))]
266eb58a 6041 "TARGET_POWERPC64"
4977bab6
ZW		 6042 {
6043 operands[2] = gen_reg_rtx (DImode);
6044 operands[3] = gen_reg_rtx (DImode);
6045 operands[4] = gen_reg_rtx (DImode);
6046 })
6047
1b1edcfa
DE		 6048(define_expand "ffsdi2"
6049 [(set (match_dup 2)
6050 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6051 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6052 (match_dup 2)))
6053 (clobber (scratch:CC))])
6054 (set (match_dup 4) (clz:DI (match_dup 3)))
6055 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6056 (minus:DI (const_int 64) (match_dup 4)))]
4977bab6 6057 "TARGET_POWERPC64"
1b1edcfa
DE		 6058 {
6059 operands[2] = gen_reg_rtx (DImode);
6060 operands[3] = gen_reg_rtx (DImode);
6061 operands[4] = gen_reg_rtx (DImode);
6062 })
266eb58a
DE		 6063
6064(define_insn "muldi3"
6065 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6066 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6067 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6068 "TARGET_POWERPC64"
6069 "mulld %0,%1,%2"
3cb999d8 6070 [(set_attr "type" "lmul")])
266eb58a 6071
9259f3b0
DE		 6072(define_insn "*muldi3_internal1"
6073 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6074 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6075 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6076 (const_int 0)))
6077 (clobber (match_scratch:DI 3 "=r,r"))]
6078 "TARGET_POWERPC64"
6079 "@
6080 mulld. %3,%1,%2
6081 #"
6082 [(set_attr "type" "lmul_compare")
6083 (set_attr "length" "4,8")])
6084
6085(define_split
6086 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6087 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6088 (match_operand:DI 2 "gpc_reg_operand" ""))
6089 (const_int 0)))
6090 (clobber (match_scratch:DI 3 ""))]
6091 "TARGET_POWERPC64 && reload_completed"
6092 [(set (match_dup 3)
6093 (mult:DI (match_dup 1) (match_dup 2)))
6094 (set (match_dup 0)
6095 (compare:CC (match_dup 3)
6096 (const_int 0)))]
6097 "")
6098
6099(define_insn "*muldi3_internal2"
6100 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6101 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6102 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6103 (const_int 0)))
6104 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6105 (mult:DI (match_dup 1) (match_dup 2)))]
6106 "TARGET_POWERPC64"
6107 "@
6108 mulld. %0,%1,%2
6109 #"
6110 [(set_attr "type" "lmul_compare")
6111 (set_attr "length" "4,8")])
6112
6113(define_split
6114 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6115 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6116 (match_operand:DI 2 "gpc_reg_operand" ""))
6117 (const_int 0)))
6118 (set (match_operand:DI 0 "gpc_reg_operand" "")
6119 (mult:DI (match_dup 1) (match_dup 2)))]
6120 "TARGET_POWERPC64 && reload_completed"
6121 [(set (match_dup 0)
6122 (mult:DI (match_dup 1) (match_dup 2)))
6123 (set (match_dup 3)
6124 (compare:CC (match_dup 0)
6125 (const_int 0)))]
6126 "")
6127
266eb58a
DE		 6128(define_insn "smuldi3_highpart"
6129 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6130 (truncate:DI
6131 (lshiftrt:TI (mult:TI (sign_extend:TI
6132 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6133 (sign_extend:TI
6134 (match_operand:DI 2 "gpc_reg_operand" "r")))
6135 (const_int 64))))]
6136 "TARGET_POWERPC64"
6137 "mulhd %0,%1,%2"
3cb999d8 6138 [(set_attr "type" "lmul")])
266eb58a
DE		 6139
6140(define_insn "umuldi3_highpart"
6141 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6142 (truncate:DI
6143 (lshiftrt:TI (mult:TI (zero_extend:TI
6144 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6145 (zero_extend:TI
6146 (match_operand:DI 2 "gpc_reg_operand" "r")))
6147 (const_int 64))))]
6148 "TARGET_POWERPC64"
6149 "mulhdu %0,%1,%2"
3cb999d8 6150 [(set_attr "type" "lmul")])
266eb58a
DE		 6151
6152(define_expand "divdi3"
6153 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6154 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6155 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6156 "TARGET_POWERPC64"
6157 "
6158{
6159 if (GET_CODE (operands[2]) == CONST_INT
2bfcf297 6160 && INTVAL (operands[2]) > 0
266eb58a
DE		 6161 && exact_log2 (INTVAL (operands[2])) >= 0)
6162 ;
6163 else
6164 operands[2] = force_reg (DImode, operands[2]);
6165}")
6166
6167(define_expand "moddi3"
6168 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6169 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6170 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6171 "TARGET_POWERPC64"
6172 "
6173{
2bfcf297 6174 int i;
266eb58a
DE		 6175 rtx temp1;
6176 rtx temp2;
6177
2bfcf297
DB		 6178 if (GET_CODE (operands[2]) != CONST_INT
6179 || INTVAL (operands[2]) <= 0
6180 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
266eb58a
DE		 6181 FAIL;
6182
6183 temp1 = gen_reg_rtx (DImode);
6184 temp2 = gen_reg_rtx (DImode);
6185
6186 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6187 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6188 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6189 DONE;
6190}")
6191
6192(define_insn ""
6193 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6194 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
2bfcf297
DB		 6195 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6196 "TARGET_POWERPC64"
266eb58a
DE		 6197 "sradi %0,%1,%p2\;addze %0,%0"
6198 [(set_attr "length" "8")])
6199
6200(define_insn ""
9ebbca7d
GK		 6201 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6202 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
2bfcf297 6203 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
266eb58a 6204 (const_int 0)))
9ebbca7d 6205 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6206 "TARGET_64BIT"
9ebbca7d
GK		 6207 "@
6208 sradi %3,%1,%p2\;addze. %3,%3
6209 #"
266eb58a 6210 [(set_attr "type" "compare")
9ebbca7d
GK		 6211 (set_attr "length" "8,12")])
6212
6213(define_split
6214 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6215 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
2bfcf297 6216 (match_operand:DI 2 "exact_log2_cint_operand" ""))
9ebbca7d
GK		 6217 (const_int 0)))
6218 (clobber (match_scratch:DI 3 ""))]
2bfcf297 6219 "TARGET_POWERPC64 && reload_completed"
9ebbca7d
GK		 6220 [(set (match_dup 3)
6221 (div:DI (match_dup 1) (match_dup 2)))
6222 (set (match_dup 0)
6223 (compare:CC (match_dup 3)
6224 (const_int 0)))]
6225 "")
266eb58a
DE		 6226
6227(define_insn ""
9ebbca7d
GK		 6228 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6229 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
2bfcf297 6230 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
266eb58a 6231 (const_int 0)))
9ebbca7d 6232 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 6233 (div:DI (match_dup 1) (match_dup 2)))]
683bdff7 6234 "TARGET_64BIT"
9ebbca7d
GK		 6235 "@
6236 sradi %0,%1,%p2\;addze. %0,%0
6237 #"
266eb58a 6238 [(set_attr "type" "compare")
9ebbca7d 6239 (set_attr "length" "8,12")])
266eb58a 6240
9ebbca7d
GK		 6241(define_split
6242 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6243 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
2bfcf297 6244 (match_operand:DI 2 "exact_log2_cint_operand" ""))
9ebbca7d
GK		 6245 (const_int 0)))
6246 (set (match_operand:DI 0 "gpc_reg_operand" "")
6247 (div:DI (match_dup 1) (match_dup 2)))]
2bfcf297 6248 "TARGET_POWERPC64 && reload_completed"
9ebbca7d
GK		 6249 [(set (match_dup 0)
6250 (div:DI (match_dup 1) (match_dup 2)))
6251 (set (match_dup 3)
6252 (compare:CC (match_dup 0)
6253 (const_int 0)))]
6254 "")
6255
6256(define_insn ""
6257 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
266eb58a 6258 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a260abc9 6259 (match_operand:DI 2 "gpc_reg_operand" "r")))]
266eb58a
DE		 6260 "TARGET_POWERPC64"
6261 "divd %0,%1,%2"
3cb999d8 6262 [(set_attr "type" "ldiv")])
266eb58a
DE		 6263
6264(define_insn "udivdi3"
6265 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6266 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6267 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6268 "TARGET_POWERPC64"
6269 "divdu %0,%1,%2"
3cb999d8 6270 [(set_attr "type" "ldiv")])
266eb58a
DE		 6271
6272(define_insn "rotldi3"
6273 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6274 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6275 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6276 "TARGET_POWERPC64"
a66078ee 6277 "rld%I2cl %0,%1,%H2,0")
266eb58a 6278
a260abc9 6279(define_insn "*rotldi3_internal2"
9ebbca7d
GK		 6280 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6281 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6282 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6283 (const_int 0)))
9ebbca7d 6284 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6285 "TARGET_64BIT"
9ebbca7d
GK		 6286 "@
6287 rld%I2cl. %3,%1,%H2,0
6288 #"
6289 [(set_attr "type" "delayed_compare")
6290 (set_attr "length" "4,8")])
6291
6292(define_split
6293 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6294 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6295 (match_operand:DI 2 "reg_or_cint_operand" ""))
6296 (const_int 0)))
6297 (clobber (match_scratch:DI 3 ""))]
6298 "TARGET_POWERPC64 && reload_completed"
6299 [(set (match_dup 3)
6300 (rotate:DI (match_dup 1) (match_dup 2)))
6301 (set (match_dup 0)
6302 (compare:CC (match_dup 3)
6303 (const_int 0)))]
6304 "")
266eb58a 6305
a260abc9 6306(define_insn "*rotldi3_internal3"
9ebbca7d
GK		 6307 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6308 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6309 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6310 (const_int 0)))
9ebbca7d 6311 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 6312 (rotate:DI (match_dup 1) (match_dup 2)))]
683bdff7 6313 "TARGET_64BIT"
9ebbca7d
GK		 6314 "@
6315 rld%I2cl. %0,%1,%H2,0
6316 #"
6317 [(set_attr "type" "delayed_compare")
6318 (set_attr "length" "4,8")])
6319
6320(define_split
6321 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6322 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6323 (match_operand:DI 2 "reg_or_cint_operand" ""))
6324 (const_int 0)))
6325 (set (match_operand:DI 0 "gpc_reg_operand" "")
6326 (rotate:DI (match_dup 1) (match_dup 2)))]
6327 "TARGET_POWERPC64 && reload_completed"
6328 [(set (match_dup 0)
6329 (rotate:DI (match_dup 1) (match_dup 2)))
6330 (set (match_dup 3)
6331 (compare:CC (match_dup 0)
6332 (const_int 0)))]
6333 "")
266eb58a 6334
a260abc9
DE		 6335(define_insn "*rotldi3_internal4"
6336 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6337 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6338 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
ce71f754 6339 (match_operand:DI 3 "mask64_operand" "n")))]
a260abc9
DE		 6340 "TARGET_POWERPC64"
6341 "rld%I2c%B3 %0,%1,%H2,%S3")
6342
6343(define_insn "*rotldi3_internal5"
9ebbca7d 6344 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9 6345 (compare:CC (and:DI
9ebbca7d
GK		 6346 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6347 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
ce71f754 6348 (match_operand:DI 3 "mask64_operand" "n,n"))
a260abc9 6349 (const_int 0)))
9ebbca7d 6350 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 6351 "TARGET_64BIT"
9ebbca7d
GK		 6352 "@
6353 rld%I2c%B3. %4,%1,%H2,%S3
6354 #"
6355 [(set_attr "type" "delayed_compare")
6356 (set_attr "length" "4,8")])
6357
6358(define_split
6359 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6360 (compare:CC (and:DI
6361 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6362 (match_operand:DI 2 "reg_or_cint_operand" ""))
6363 (match_operand:DI 3 "mask64_operand" ""))
6364 (const_int 0)))
6365 (clobber (match_scratch:DI 4 ""))]
6366 "TARGET_POWERPC64 && reload_completed"
6367 [(set (match_dup 4)
6368 (and:DI (rotate:DI (match_dup 1)
6369 (match_dup 2))
6370 (match_dup 3)))
6371 (set (match_dup 0)
6372 (compare:CC (match_dup 4)
6373 (const_int 0)))]
6374 "")
a260abc9
DE		 6375
6376(define_insn "*rotldi3_internal6"
9ebbca7d 6377 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9 6378 (compare:CC (and:DI
9ebbca7d
GK		 6379 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6380 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
ce71f754 6381 (match_operand:DI 3 "mask64_operand" "n,n"))
a260abc9 6382 (const_int 0)))
9ebbca7d 6383 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9 6384 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6385 "TARGET_64BIT"
9ebbca7d
GK		 6386 "@
6387 rld%I2c%B3. %0,%1,%H2,%S3
6388 #"
6389 [(set_attr "type" "delayed_compare")
6390 (set_attr "length" "4,8")])
6391
6392(define_split
6393 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6394 (compare:CC (and:DI
6395 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6396 (match_operand:DI 2 "reg_or_cint_operand" ""))
6397 (match_operand:DI 3 "mask64_operand" ""))
6398 (const_int 0)))
6399 (set (match_operand:DI 0 "gpc_reg_operand" "")
6400 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6401 "TARGET_POWERPC64 && reload_completed"
6402 [(set (match_dup 0)
6403 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6404 (set (match_dup 4)
6405 (compare:CC (match_dup 0)
6406 (const_int 0)))]
6407 "")
a260abc9
DE		 6408
6409(define_insn "*rotldi3_internal7"
6410 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6411 (zero_extend:DI
6412 (subreg:QI
6413 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6414 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6415 "TARGET_POWERPC64"
6416 "rld%I2cl %0,%1,%H2,56")
6417
6418(define_insn "*rotldi3_internal8"
9ebbca7d 6419 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6420 (compare:CC (zero_extend:DI
6421 (subreg:QI
9ebbca7d
GK		 6422 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6423 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6424 (const_int 0)))
9ebbca7d 6425 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6426 "TARGET_64BIT"
9ebbca7d
GK		 6427 "@
6428 rld%I2cl. %3,%1,%H2,56
6429 #"
6430 [(set_attr "type" "delayed_compare")
6431 (set_attr "length" "4,8")])
6432
6433(define_split
6434 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6435 (compare:CC (zero_extend:DI
6436 (subreg:QI
6437 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6438 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6439 (const_int 0)))
6440 (clobber (match_scratch:DI 3 ""))]
6441 "TARGET_POWERPC64 && reload_completed"
6442 [(set (match_dup 3)
6443 (zero_extend:DI (subreg:QI
6444 (rotate:DI (match_dup 1)
6445 (match_dup 2)) 0)))
6446 (set (match_dup 0)
6447 (compare:CC (match_dup 3)
6448 (const_int 0)))]
6449 "")
a260abc9
DE		 6450
6451(define_insn "*rotldi3_internal9"
9ebbca7d 6452 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6453 (compare:CC (zero_extend:DI
6454 (subreg:QI
9ebbca7d
GK		 6455 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6456 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6457 (const_int 0)))
9ebbca7d 6458 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9 6459 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6460 "TARGET_64BIT"
9ebbca7d
GK		 6461 "@
6462 rld%I2cl. %0,%1,%H2,56
6463 #"
6464 [(set_attr "type" "delayed_compare")
6465 (set_attr "length" "4,8")])
6466
6467(define_split
6468 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6469 (compare:CC (zero_extend:DI
6470 (subreg:QI
6471 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6472 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6473 (const_int 0)))
6474 (set (match_operand:DI 0 "gpc_reg_operand" "")
6475 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6476 "TARGET_POWERPC64 && reload_completed"
6477 [(set (match_dup 0)
6478 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6479 (set (match_dup 3)
6480 (compare:CC (match_dup 0)
6481 (const_int 0)))]
6482 "")
a260abc9
DE		 6483
6484(define_insn "*rotldi3_internal10"
6485 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6486 (zero_extend:DI
6487 (subreg:HI
6488 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6489 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6490 "TARGET_POWERPC64"
6491 "rld%I2cl %0,%1,%H2,48")
6492
6493(define_insn "*rotldi3_internal11"
9ebbca7d 6494 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6495 (compare:CC (zero_extend:DI
6496 (subreg:HI
9ebbca7d
GK		 6497 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6498 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6499 (const_int 0)))
9ebbca7d 6500 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6501 "TARGET_64BIT"
9ebbca7d
GK		 6502 "@
6503 rld%I2cl. %3,%1,%H2,48
6504 #"
6505 [(set_attr "type" "delayed_compare")
6506 (set_attr "length" "4,8")])
6507
6508(define_split
6509 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6510 (compare:CC (zero_extend:DI
6511 (subreg:HI
6512 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6513 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6514 (const_int 0)))
6515 (clobber (match_scratch:DI 3 ""))]
6516 "TARGET_POWERPC64 && reload_completed"
6517 [(set (match_dup 3)
6518 (zero_extend:DI (subreg:HI
6519 (rotate:DI (match_dup 1)
6520 (match_dup 2)) 0)))
6521 (set (match_dup 0)
6522 (compare:CC (match_dup 3)
6523 (const_int 0)))]
6524 "")
a260abc9
DE		 6525
6526(define_insn "*rotldi3_internal12"
9ebbca7d 6527 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6528 (compare:CC (zero_extend:DI
6529 (subreg:HI
9ebbca7d
GK		 6530 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6531 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6532 (const_int 0)))
9ebbca7d 6533 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9 6534 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6535 "TARGET_64BIT"
9ebbca7d
GK		 6536 "@
6537 rld%I2cl. %0,%1,%H2,48
6538 #"
6539 [(set_attr "type" "delayed_compare")
6540 (set_attr "length" "4,8")])
6541
6542(define_split
6543 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6544 (compare:CC (zero_extend:DI
6545 (subreg:HI
6546 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6547 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6548 (const_int 0)))
6549 (set (match_operand:DI 0 "gpc_reg_operand" "")
6550 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6551 "TARGET_POWERPC64 && reload_completed"
6552 [(set (match_dup 0)
6553 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6554 (set (match_dup 3)
6555 (compare:CC (match_dup 0)
6556 (const_int 0)))]
6557 "")
a260abc9
DE		 6558
6559(define_insn "*rotldi3_internal13"
6560 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6561 (zero_extend:DI
6562 (subreg:SI
6563 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6564 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6565 "TARGET_POWERPC64"
6566 "rld%I2cl %0,%1,%H2,32")
6567
6568(define_insn "*rotldi3_internal14"
9ebbca7d 6569 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6570 (compare:CC (zero_extend:DI
6571 (subreg:SI
9ebbca7d
GK		 6572 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6573 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6574 (const_int 0)))
9ebbca7d 6575 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6576 "TARGET_64BIT"
9ebbca7d
GK		 6577 "@
6578 rld%I2cl. %3,%1,%H2,32
6579 #"
6580 [(set_attr "type" "delayed_compare")
6581 (set_attr "length" "4,8")])
6582
6583(define_split
6584 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6585 (compare:CC (zero_extend:DI
6586 (subreg:SI
6587 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6588 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6589 (const_int 0)))
6590 (clobber (match_scratch:DI 3 ""))]
6591 "TARGET_POWERPC64 && reload_completed"
6592 [(set (match_dup 3)
6593 (zero_extend:DI (subreg:SI
6594 (rotate:DI (match_dup 1)
6595 (match_dup 2)) 0)))
6596 (set (match_dup 0)
6597 (compare:CC (match_dup 3)
6598 (const_int 0)))]
6599 "")
a260abc9
DE		 6600
6601(define_insn "*rotldi3_internal15"
9ebbca7d 6602 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
a260abc9
DE		 6603 (compare:CC (zero_extend:DI
6604 (subreg:SI
9ebbca7d
GK		 6605 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6606 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
a260abc9 6607 (const_int 0)))
9ebbca7d 6608 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9 6609 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6610 "TARGET_64BIT"
9ebbca7d
GK		 6611 "@
6612 rld%I2cl. %0,%1,%H2,32
6613 #"
6614 [(set_attr "type" "delayed_compare")
6615 (set_attr "length" "4,8")])
6616
6617(define_split
6618 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6619 (compare:CC (zero_extend:DI
6620 (subreg:SI
6621 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6622 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6623 (const_int 0)))
6624 (set (match_operand:DI 0 "gpc_reg_operand" "")
6625 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6626 "TARGET_POWERPC64 && reload_completed"
6627 [(set (match_dup 0)
6628 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6629 (set (match_dup 3)
6630 (compare:CC (match_dup 0)
6631 (const_int 0)))]
6632 "")
a260abc9 6633
266eb58a
DE		 6634(define_expand "ashldi3"
6635 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6636 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6637 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6638 "TARGET_POWERPC64 || TARGET_POWER"
6639 "
6640{
6641 if (TARGET_POWERPC64)
6642 ;
6643 else if (TARGET_POWER)
6644 {
6645 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6646 DONE;
6647 }
6648 else
6649 FAIL;
6650}")
6651
e2c953b6 6652(define_insn "*ashldi3_internal1"
266eb58a
DE		 6653 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6654 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6655 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6656 "TARGET_POWERPC64"
a66078ee 6657 "sld%I2 %0,%1,%H2"
266eb58a
DE		 6658 [(set_attr "length" "8")])
6659
e2c953b6 6660(define_insn "*ashldi3_internal2"
9ebbca7d
GK		 6661 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6662 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6663 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6664 (const_int 0)))
9ebbca7d 6665 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6666 "TARGET_64BIT"
9ebbca7d
GK		 6667 "@
6668 sld%I2. %3,%1,%H2
6669 #"
6670 [(set_attr "type" "delayed_compare")
6671 (set_attr "length" "4,8")])
29ae5b89 6672
9ebbca7d
GK		 6673(define_split
6674 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6675 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6676 (match_operand:SI 2 "reg_or_cint_operand" ""))
6677 (const_int 0)))
6678 (clobber (match_scratch:DI 3 ""))]
6679 "TARGET_POWERPC64 && reload_completed"
6680 [(set (match_dup 3)
6681 (ashift:DI (match_dup 1) (match_dup 2)))
6682 (set (match_dup 0)
6683 (compare:CC (match_dup 3)
6684 (const_int 0)))]
6685 "")
6686
e2c953b6 6687(define_insn "*ashldi3_internal3"
9ebbca7d
GK		 6688 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6689 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6690 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6691 (const_int 0)))
9ebbca7d 6692 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 6693 (ashift:DI (match_dup 1) (match_dup 2)))]
683bdff7 6694 "TARGET_64BIT"
9ebbca7d
GK		 6695 "@
6696 sld%I2. %0,%1,%H2
6697 #"
6698 [(set_attr "type" "delayed_compare")
6699 (set_attr "length" "4,8")])
6700
6701(define_split
6702 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6703 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6704 (match_operand:SI 2 "reg_or_cint_operand" ""))
6705 (const_int 0)))
6706 (set (match_operand:DI 0 "gpc_reg_operand" "")
6707 (ashift:DI (match_dup 1) (match_dup 2)))]
6708 "TARGET_POWERPC64 && reload_completed"
6709 [(set (match_dup 0)
6710 (ashift:DI (match_dup 1) (match_dup 2)))
6711 (set (match_dup 3)
6712 (compare:CC (match_dup 0)
6713 (const_int 0)))]
6714 "")
266eb58a 6715
e2c953b6 6716(define_insn "*ashldi3_internal4"
3cb999d8
DE		 6717 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6718 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6719 (match_operand:SI 2 "const_int_operand" "i"))
c5059423
AM		 6720 (match_operand:DI 3 "const_int_operand" "n")))]
6721 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
e2c953b6 6722 "rldic %0,%1,%H2,%W3")
3cb999d8 6723
e2c953b6 6724(define_insn "ashldi3_internal5"
9ebbca7d 6725 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3cb999d8 6726 (compare:CC
9ebbca7d
GK		 6727 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6728 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 6729 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 6730 (const_int 0)))
9ebbca7d 6731 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 6732 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 6733 "@
e2c953b6 6734 rldic. %4,%1,%H2,%W3
9ebbca7d
GK		 6735 #"
6736 [(set_attr "type" "delayed_compare")
6737 (set_attr "length" "4,8")])
6738
6739(define_split
6740 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6741 (compare:CC
6742 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6743 (match_operand:SI 2 "const_int_operand" ""))
c5059423 6744 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 6745 (const_int 0)))
6746 (clobber (match_scratch:DI 4 ""))]
c5059423
AM		 6747 "TARGET_POWERPC64 && reload_completed
6748 && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 6749 [(set (match_dup 4)
6750 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
e2c953b6 6751 (match_dup 3)))
9ebbca7d
GK		 6752 (set (match_dup 0)
6753 (compare:CC (match_dup 4)
6754 (const_int 0)))]
6755 "")
3cb999d8 6756
e2c953b6 6757(define_insn "*ashldi3_internal6"
9ebbca7d 6758 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3cb999d8 6759 (compare:CC
9ebbca7d
GK		 6760 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6761 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 6762 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 6763 (const_int 0)))
9ebbca7d 6764 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3cb999d8 6765 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6766 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 6767 "@
e2c953b6 6768 rldic. %0,%1,%H2,%W3
9ebbca7d
GK		 6769 #"
6770 [(set_attr "type" "delayed_compare")
6771 (set_attr "length" "4,8")])
6772
6773(define_split
6774 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6775 (compare:CC
6776 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6777 (match_operand:SI 2 "const_int_operand" ""))
c5059423 6778 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 6779 (const_int 0)))
6780 (set (match_operand:DI 0 "gpc_reg_operand" "")
6781 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
c5059423
AM		 6782 "TARGET_POWERPC64 && reload_completed
6783 && includes_rldic_lshift_p (operands[2], operands[3])"
6784 [(set (match_dup 0)
6785 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6786 (match_dup 3)))
6787 (set (match_dup 4)
6788 (compare:CC (match_dup 0)
6789 (const_int 0)))]
6790 "")
6791
6792(define_insn "*ashldi3_internal7"
6793 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6794 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6795 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 6796 (match_operand:DI 3 "mask64_operand" "n")))]
c5059423
AM		 6797 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6798 "rldicr %0,%1,%H2,%S3")
6799
6800(define_insn "ashldi3_internal8"
6801 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6802 (compare:CC
6803 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6804 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 6805 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 6806 (const_int 0)))
6807 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 6808 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 6809 "@
6810 rldicr. %4,%1,%H2,%S3
6811 #"
6812 [(set_attr "type" "delayed_compare")
6813 (set_attr "length" "4,8")])
6814
6815(define_split
6816 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6817 (compare:CC
6818 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6819 (match_operand:SI 2 "const_int_operand" ""))
6820 (match_operand:DI 3 "mask64_operand" ""))
6821 (const_int 0)))
6822 (clobber (match_scratch:DI 4 ""))]
6823 "TARGET_POWERPC64 && reload_completed
6824 && includes_rldicr_lshift_p (operands[2], operands[3])"
6825 [(set (match_dup 4)
6826 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6827 (match_dup 3)))
6828 (set (match_dup 0)
6829 (compare:CC (match_dup 4)
6830 (const_int 0)))]
6831 "")
6832
6833(define_insn "*ashldi3_internal9"
6834 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6835 (compare:CC
6836 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6837 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 6838 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 6839 (const_int 0)))
6840 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6841 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6842 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 6843 "@
6844 rldicr. %0,%1,%H2,%S3
6845 #"
6846 [(set_attr "type" "delayed_compare")
6847 (set_attr "length" "4,8")])
6848
6849(define_split
6850 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6851 (compare:CC
6852 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6853 (match_operand:SI 2 "const_int_operand" ""))
6854 (match_operand:DI 3 "mask64_operand" ""))
6855 (const_int 0)))
6856 (set (match_operand:DI 0 "gpc_reg_operand" "")
6857 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6858 "TARGET_POWERPC64 && reload_completed
6859 && includes_rldicr_lshift_p (operands[2], operands[3])"
9ebbca7d 6860 [(set (match_dup 0)
e2c953b6
DE		 6861 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6862 (match_dup 3)))
9ebbca7d
GK		 6863 (set (match_dup 4)
6864 (compare:CC (match_dup 0)
6865 (const_int 0)))]
6866 "")
6867
6868(define_expand "lshrdi3"
266eb58a
DE		 6869 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6870 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6871 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6872 "TARGET_POWERPC64 || TARGET_POWER"
6873 "
6874{
6875 if (TARGET_POWERPC64)
6876 ;
6877 else if (TARGET_POWER)
6878 {
6879 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6880 DONE;
6881 }
6882 else
6883 FAIL;
6884}")
6885
e2c953b6 6886(define_insn "*lshrdi3_internal1"
266eb58a
DE		 6887 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6888 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6889 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6890 "TARGET_POWERPC64"
a66078ee 6891 "srd%I2 %0,%1,%H2")
266eb58a 6892
e2c953b6 6893(define_insn "*lshrdi3_internal2"
9ebbca7d
GK		 6894 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6895 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6896 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
29ae5b89 6897 (const_int 0)))
9ebbca7d 6898 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6899 "TARGET_64BIT "
9ebbca7d
GK		 6900 "@
6901 srd%I2. %3,%1,%H2
6902 #"
6903 [(set_attr "type" "delayed_compare")
6904 (set_attr "length" "4,8")])
6905
6906(define_split
6907 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6908 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6909 (match_operand:SI 2 "reg_or_cint_operand" ""))
6910 (const_int 0)))
6911 (clobber (match_scratch:DI 3 ""))]
6912 "TARGET_POWERPC64 && reload_completed"
6913 [(set (match_dup 3)
6914 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6915 (set (match_dup 0)
6916 (compare:CC (match_dup 3)
6917 (const_int 0)))]
6918 "")
266eb58a 6919
e2c953b6 6920(define_insn "*lshrdi3_internal3"
9ebbca7d
GK		 6921 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6922 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6923 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6924 (const_int 0)))
9ebbca7d 6925 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
29ae5b89 6926 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 6927 "TARGET_64BIT"
9ebbca7d
GK		 6928 "@
6929 srd%I2. %0,%1,%H2
6930 #"
6931 [(set_attr "type" "delayed_compare")
6932 (set_attr "length" "4,8")])
6933
6934(define_split
6935 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6936 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6937 (match_operand:SI 2 "reg_or_cint_operand" ""))
6938 (const_int 0)))
6939 (set (match_operand:DI 0 "gpc_reg_operand" "")
6940 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6941 "TARGET_POWERPC64 && reload_completed"
6942 [(set (match_dup 0)
6943 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6944 (set (match_dup 3)
6945 (compare:CC (match_dup 0)
6946 (const_int 0)))]
6947 "")
266eb58a
DE		 6948
6949(define_expand "ashrdi3"
6950 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6951 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6952 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4aa74a4f 6953 ""
266eb58a
DE		 6954 "
6955{
6956 if (TARGET_POWERPC64)
6957 ;
6958 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6959 {
6960 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6961 DONE;
6962 }
4aa74a4f
FS		 6963 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT)
6964 {
6965 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
6966 DONE;
6967 }
266eb58a
DE		 6968 else
6969 FAIL;
6970}")
6971
e2c953b6 6972(define_insn "*ashrdi3_internal1"
266eb58a
DE		 6973 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6974 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6975 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6976 "TARGET_POWERPC64"
375490e0 6977 "srad%I2 %0,%1,%H2")
266eb58a 6978
e2c953b6 6979(define_insn "*ashrdi3_internal2"
9ebbca7d
GK		 6980 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6981 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6982 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 6983 (const_int 0)))
9ebbca7d 6984 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 6985 "TARGET_64BIT"
9ebbca7d
GK		 6986 "@
6987 srad%I2. %3,%1,%H2
6988 #"
6989 [(set_attr "type" "delayed_compare")
6990 (set_attr "length" "4,8")])
6991
6992(define_split
6993 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6994 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6995 (match_operand:SI 2 "reg_or_cint_operand" ""))
6996 (const_int 0)))
6997 (clobber (match_scratch:DI 3 ""))]
6998 "TARGET_POWERPC64 && reload_completed"
6999 [(set (match_dup 3)
7000 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7001 (set (match_dup 0)
7002 (compare:CC (match_dup 3)
7003 (const_int 0)))]
7004 "")
266eb58a 7005
e2c953b6 7006(define_insn "*ashrdi3_internal3"
9ebbca7d
GK		 7007 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7008 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7009 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
266eb58a 7010 (const_int 0)))
9ebbca7d 7011 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
266eb58a 7012 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7013 "TARGET_64BIT"
9ebbca7d
GK		 7014 "@
7015 srad%I2. %0,%1,%H2
7016 #"
7017 [(set_attr "type" "delayed_compare")
7018 (set_attr "length" "4,8")])
7019
7020(define_split
7021 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7022 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7023 (match_operand:SI 2 "reg_or_cint_operand" ""))
7024 (const_int 0)))
7025 (set (match_operand:DI 0 "gpc_reg_operand" "")
7026 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7027 "TARGET_POWERPC64 && reload_completed"
7028 [(set (match_dup 0)
7029 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7030 (set (match_dup 3)
7031 (compare:CC (match_dup 0)
7032 (const_int 0)))]
7033 "")
815cdc52 7034
29ae5b89 7035(define_insn "anddi3"
0ba1b2ff
AM		 7036 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
7037 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
7038 (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t")))
7039 (clobber (match_scratch:CC 3 "=X,X,x,x,X"))]
6ffc8580 7040 "TARGET_POWERPC64"
266eb58a
DE		 7041 "@
7042 and %0,%1,%2
29ae5b89
JL		 7043 rldic%B2 %0,%1,0,%S2
7044 andi. %0,%1,%b2
0ba1b2ff
AM		 7045 andis. %0,%1,%u2
7046 #"
7047 [(set_attr "length" "4,4,4,4,8")])
7048
7049(define_split
7050 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7051 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7052 (match_operand:DI 2 "mask64_2_operand" "")))
7053 (clobber (match_scratch:CC 3 ""))]
7054 "TARGET_POWERPC64
7055 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7056 && !mask64_operand (operands[2], DImode)"
7057 [(set (match_dup 0)
7058 (and:DI (rotate:DI (match_dup 1)
7059 (match_dup 4))
7060 (match_dup 5)))
7061 (set (match_dup 0)
7062 (and:DI (rotate:DI (match_dup 0)
7063 (match_dup 6))
7064 (match_dup 7)))]
7065 "
7066{
7067 build_mask64_2_operands (operands[2], &operands[4]);
7068}")
266eb58a 7069
a260abc9 7070(define_insn "*anddi3_internal2"
0ba1b2ff
AM		 7071 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7072 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7073 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
266eb58a 7074 (const_int 0)))
0ba1b2ff
AM		 7075 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
7076 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7077 "TARGET_64BIT"
266eb58a
DE		 7078 "@
7079 and. %3,%1,%2
6c873122 7080 rldic%B2. %3,%1,0,%S2
6ffc8580
MM		 7081 andi. %3,%1,%b2
7082 andis. %3,%1,%u2
9ebbca7d
GK		 7083 #
7084 #
7085 #
0ba1b2ff
AM		 7086 #
7087 #
9ebbca7d 7088 #"
0ba1b2ff
AM		 7089 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7090 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
9ebbca7d
GK		 7091
7092(define_split
7093 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7094 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7095 (match_operand:DI 2 "and64_operand" ""))
7096 (const_int 0)))
7097 (clobber (match_scratch:DI 3 ""))
7098 (clobber (match_scratch:CC 4 ""))]
7099 "TARGET_POWERPC64 && reload_completed"
7100 [(parallel [(set (match_dup 3)
7101 (and:DI (match_dup 1)
7102 (match_dup 2)))
7103 (clobber (match_dup 4))])
7104 (set (match_dup 0)
7105 (compare:CC (match_dup 3)
7106 (const_int 0)))]
7107 "")
266eb58a 7108
0ba1b2ff
AM		 7109(define_split
7110 [(set (match_operand:CC 0 "cc_reg_operand" "")
7111 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7112 (match_operand:DI 2 "mask64_2_operand" ""))
7113 (const_int 0)))
7114 (clobber (match_scratch:DI 3 ""))
7115 (clobber (match_scratch:CC 4 ""))]
7116 "TARGET_POWERPC64 && reload_completed
7117 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7118 && !mask64_operand (operands[2], DImode)"
7119 [(set (match_dup 3)
7120 (and:DI (rotate:DI (match_dup 1)
7121 (match_dup 5))
7122 (match_dup 6)))
7123 (parallel [(set (match_dup 0)
7124 (compare:CC (and:DI (rotate:DI (match_dup 3)
7125 (match_dup 7))
7126 (match_dup 8))
7127 (const_int 0)))
7128 (clobber (match_dup 3))])]
7129 "
7130{
7131 build_mask64_2_operands (operands[2], &operands[5]);
7132}")
7133
a260abc9 7134(define_insn "*anddi3_internal3"
0ba1b2ff
AM		 7135 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7136 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7137 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
266eb58a 7138 (const_int 0)))
0ba1b2ff 7139 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
9ebbca7d 7140 (and:DI (match_dup 1) (match_dup 2)))
0ba1b2ff 7141 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7142 "TARGET_64BIT"
266eb58a
DE		 7143 "@
7144 and. %0,%1,%2
6c873122 7145 rldic%B2. %0,%1,0,%S2
6ffc8580
MM		 7146 andi. %0,%1,%b2
7147 andis. %0,%1,%u2
9ebbca7d
GK		 7148 #
7149 #
7150 #
0ba1b2ff
AM		 7151 #
7152 #
9ebbca7d 7153 #"
0ba1b2ff
AM		 7154 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7155 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
9ebbca7d
GK		 7156
7157(define_split
7158 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7159 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7160 (match_operand:DI 2 "and64_operand" ""))
7161 (const_int 0)))
7162 (set (match_operand:DI 0 "gpc_reg_operand" "")
7163 (and:DI (match_dup 1) (match_dup 2)))
7164 (clobber (match_scratch:CC 4 ""))]
7165 "TARGET_POWERPC64 && reload_completed"
7166 [(parallel [(set (match_dup 0)
7167 (and:DI (match_dup 1) (match_dup 2)))
7168 (clobber (match_dup 4))])
7169 (set (match_dup 3)
7170 (compare:CC (match_dup 0)
7171 (const_int 0)))]
7172 "")
266eb58a 7173
0ba1b2ff
AM		 7174(define_split
7175 [(set (match_operand:CC 3 "cc_reg_operand" "")
7176 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7177 (match_operand:DI 2 "mask64_2_operand" ""))
7178 (const_int 0)))
7179 (set (match_operand:DI 0 "gpc_reg_operand" "")
7180 (and:DI (match_dup 1) (match_dup 2)))
7181 (clobber (match_scratch:CC 4 ""))]
7182 "TARGET_POWERPC64 && reload_completed
7183 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7184 && !mask64_operand (operands[2], DImode)"
7185 [(set (match_dup 0)
7186 (and:DI (rotate:DI (match_dup 1)
7187 (match_dup 5))
7188 (match_dup 6)))
7189 (parallel [(set (match_dup 3)
7190 (compare:CC (and:DI (rotate:DI (match_dup 0)
7191 (match_dup 7))
7192 (match_dup 8))
7193 (const_int 0)))
7194 (set (match_dup 0)
7195 (and:DI (rotate:DI (match_dup 0)
7196 (match_dup 7))
7197 (match_dup 8)))])]
7198 "
7199{
7200 build_mask64_2_operands (operands[2], &operands[5]);
7201}")
7202
a260abc9 7203(define_expand "iordi3"
266eb58a 7204 [(set (match_operand:DI 0 "gpc_reg_operand" "")
a260abc9 7205 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7206 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
266eb58a 7207 "TARGET_POWERPC64"
266eb58a
DE		 7208 "
7209{
dfbdccdb 7210 if (non_logical_cint_operand (operands[2], DImode))
266eb58a 7211 {
dfbdccdb 7212 HOST_WIDE_INT value;
677a9668 7213 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
a260abc9 7214 ? operands[0] : gen_reg_rtx (DImode));
266eb58a 7215
dfbdccdb
GK		 7216 if (GET_CODE (operands[2]) == CONST_INT)
7217 {
7218 value = INTVAL (operands[2]);
7219 emit_insn (gen_iordi3 (tmp, operands[1],
7220 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7221 }
e2c953b6 7222 else
dfbdccdb
GK		 7223 {
7224 value = CONST_DOUBLE_LOW (operands[2]);
7225 emit_insn (gen_iordi3 (tmp, operands[1],
7226 immed_double_const (value
7227 & (~ (HOST_WIDE_INT) 0xffff),
7228 0, DImode)));
7229 }
e2c953b6 7230
9ebbca7d
GK		 7231 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7232 DONE;
7233 }
266eb58a
DE		 7234}")
7235
a260abc9
DE		 7236(define_expand "xordi3"
7237 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7238 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7239 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
a260abc9
DE		 7240 "TARGET_POWERPC64"
7241 "
7242{
dfbdccdb 7243 if (non_logical_cint_operand (operands[2], DImode))
a260abc9 7244 {
dfbdccdb 7245 HOST_WIDE_INT value;
677a9668 7246 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
a260abc9
DE		 7247 ? operands[0] : gen_reg_rtx (DImode));
7248
dfbdccdb
GK		 7249 if (GET_CODE (operands[2]) == CONST_INT)
7250 {
7251 value = INTVAL (operands[2]);
7252 emit_insn (gen_xordi3 (tmp, operands[1],
7253 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7254 }
e2c953b6 7255 else
dfbdccdb
GK		 7256 {
7257 value = CONST_DOUBLE_LOW (operands[2]);
7258 emit_insn (gen_xordi3 (tmp, operands[1],
7259 immed_double_const (value
7260 & (~ (HOST_WIDE_INT) 0xffff),
7261 0, DImode)));
7262 }
e2c953b6 7263
9ebbca7d
GK		 7264 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7265 DONE;
7266 }
a260abc9
DE		 7267}")
7268
dfbdccdb 7269(define_insn "*booldi3_internal1"
266eb58a 7270 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 7271 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7272 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7273 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
266eb58a 7274 "TARGET_POWERPC64"
1fd4e8c1 7275 "@
dfbdccdb
GK		 7276 %q3 %0,%1,%2
7277 %q3i %0,%1,%b2
7278 %q3is %0,%1,%u2")
1fd4e8c1 7279
dfbdccdb 7280(define_insn "*booldi3_internal2"
9ebbca7d 7281 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 7282 (compare:CC (match_operator:DI 4 "boolean_or_operator"
dfbdccdb
GK		 7283 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7284 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7285 (const_int 0)))
9ebbca7d 7286 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7287 "TARGET_64BIT"
9ebbca7d 7288 "@
dfbdccdb 7289 %q4. %3,%1,%2
9ebbca7d
GK		 7290 #"
7291 [(set_attr "type" "compare")
7292 (set_attr "length" "4,8")])
7293
7294(define_split
7295 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7296 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7297 [(match_operand:DI 1 "gpc_reg_operand" "")
7298 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7299 (const_int 0)))
9ebbca7d
GK		 7300 (clobber (match_scratch:DI 3 ""))]
7301 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7302 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7303 (set (match_dup 0)
7304 (compare:CC (match_dup 3)
7305 (const_int 0)))]
7306 "")
1fd4e8c1 7307
dfbdccdb 7308(define_insn "*booldi3_internal3"
9ebbca7d 7309 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7310 (compare:CC (match_operator:DI 4 "boolean_operator"
7311 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7312 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7313 (const_int 0)))
9ebbca7d 7314 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7315 (match_dup 4))]
683bdff7 7316 "TARGET_64BIT"
9ebbca7d 7317 "@
dfbdccdb 7318 %q4. %0,%1,%2
9ebbca7d
GK		 7319 #"
7320 [(set_attr "type" "compare")
7321 (set_attr "length" "4,8")])
7322
7323(define_split
e72247f4 7324 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7325 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7326 [(match_operand:DI 1 "gpc_reg_operand" "")
7327 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7328 (const_int 0)))
75540af0 7329 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7330 (match_dup 4))]
9ebbca7d 7331 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7332 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7333 (set (match_dup 3)
7334 (compare:CC (match_dup 0)
7335 (const_int 0)))]
7336 "")
1fd4e8c1 7337
5bdc5878 7338;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 7339;; each of which does one 16-bit part. This is used by combine.
266eb58a
DE		 7340
7341(define_split
7342 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1d328b19 7343 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7344 [(match_operand:DI 1 "gpc_reg_operand" "")
7345 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
266eb58a 7346 "TARGET_POWERPC64"
dfbdccdb
GK		 7347 [(set (match_dup 0) (match_dup 4))
7348 (set (match_dup 0) (match_dup 5))]
266eb58a
DE		 7349"
7350{
dfbdccdb
GK		 7351 rtx i3,i4;
7352
9ebbca7d
GK		 7353 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7354 {
7355 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
dfbdccdb 7356 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
9ebbca7d 7357 0, DImode);
dfbdccdb 7358 i4 = GEN_INT (value & 0xffff);
9ebbca7d
GK		 7359 }
7360 else
7361 {
dfbdccdb 7362 i3 = GEN_INT (INTVAL (operands[2])
9ebbca7d 7363 & (~ (HOST_WIDE_INT) 0xffff));
dfbdccdb 7364 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
9ebbca7d 7365 }
1c563bed 7366 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
dfbdccdb 7367 operands[1], i3);
1c563bed 7368 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
dfbdccdb 7369 operands[0], i4);
1fd4e8c1
RK		 7370}")
7371
dfbdccdb 7372(define_insn "*boolcdi3_internal1"
9ebbca7d 7373 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7374 (match_operator:DI 3 "boolean_operator"
7375 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7376 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
a473029f 7377 "TARGET_POWERPC64"
1d328b19 7378 "%q3 %0,%2,%1")
a473029f 7379
dfbdccdb 7380(define_insn "*boolcdi3_internal2"
9ebbca7d 7381 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7382 (compare:CC (match_operator:DI 4 "boolean_operator"
7383 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7384 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7385 (const_int 0)))
9ebbca7d 7386 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7387 "TARGET_64BIT"
9ebbca7d 7388 "@
1d328b19 7389 %q4. %3,%2,%1
9ebbca7d
GK		 7390 #"
7391 [(set_attr "type" "compare")
7392 (set_attr "length" "4,8")])
7393
7394(define_split
7395 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7396 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7397 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7398 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7399 (const_int 0)))
9ebbca7d
GK		 7400 (clobber (match_scratch:DI 3 ""))]
7401 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7402 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7403 (set (match_dup 0)
7404 (compare:CC (match_dup 3)
7405 (const_int 0)))]
7406 "")
a473029f 7407
dfbdccdb 7408(define_insn "*boolcdi3_internal3"
9ebbca7d 7409 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7410 (compare:CC (match_operator:DI 4 "boolean_operator"
7411 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7412 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7413 (const_int 0)))
9ebbca7d 7414 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7415 (match_dup 4))]
683bdff7 7416 "TARGET_64BIT"
9ebbca7d 7417 "@
1d328b19 7418 %q4. %0,%2,%1
9ebbca7d
GK		 7419 #"
7420 [(set_attr "type" "compare")
7421 (set_attr "length" "4,8")])
7422
7423(define_split
e72247f4 7424 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7425 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7426 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7427 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7428 (const_int 0)))
75540af0 7429 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7430 (match_dup 4))]
9ebbca7d 7431 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7432 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7433 (set (match_dup 3)
7434 (compare:CC (match_dup 0)
7435 (const_int 0)))]
7436 "")
266eb58a 7437
dfbdccdb 7438(define_insn "*boolccdi3_internal1"
a473029f 7439 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7440 (match_operator:DI 3 "boolean_operator"
7441 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7442 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
a473029f 7443 "TARGET_POWERPC64"
dfbdccdb 7444 "%q3 %0,%1,%2")
a473029f 7445
dfbdccdb 7446(define_insn "*boolccdi3_internal2"
9ebbca7d 7447 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7448 (compare:CC (match_operator:DI 4 "boolean_operator"
7449 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7450 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7451 (const_int 0)))
9ebbca7d 7452 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7453 "TARGET_64BIT"
9ebbca7d 7454 "@
dfbdccdb 7455 %q4. %3,%1,%2
9ebbca7d
GK		 7456 #"
7457 [(set_attr "type" "compare")
7458 (set_attr "length" "4,8")])
7459
7460(define_split
7461 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7462 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7463 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7464 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7465 (const_int 0)))
9ebbca7d
GK		 7466 (clobber (match_scratch:DI 3 ""))]
7467 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7468 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7469 (set (match_dup 0)
7470 (compare:CC (match_dup 3)
7471 (const_int 0)))]
7472 "")
266eb58a 7473
dfbdccdb 7474(define_insn "*boolccdi3_internal3"
9ebbca7d 7475 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7476 (compare:CC (match_operator:DI 4 "boolean_operator"
7477 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7478 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7479 (const_int 0)))
9ebbca7d 7480 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7481 (match_dup 4))]
683bdff7 7482 "TARGET_64BIT"
9ebbca7d 7483 "@
dfbdccdb 7484 %q4. %0,%1,%2
9ebbca7d
GK		 7485 #"
7486 [(set_attr "type" "compare")
7487 (set_attr "length" "4,8")])
7488
7489(define_split
e72247f4 7490 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7491 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7492 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7493 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7494 (const_int 0)))
75540af0 7495 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7496 (match_dup 4))]
9ebbca7d 7497 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7498 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7499 (set (match_dup 3)
7500 (compare:CC (match_dup 0)
7501 (const_int 0)))]
7502 "")
dfbdccdb 7503\f
1fd4e8c1 7504;; Now define ways of moving data around.
4697a36c
MM		 7505
7506;; Elf specific ways of loading addresses for non-PIC code.
9ebbca7d
GK		 7507;; The output of this could be r0, but we make a very strong
7508;; preference for a base register because it will usually
7509;; be needed there.
4697a36c 7510(define_insn "elf_high"
9ebbca7d 7511 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
4697a36c 7512 (high:SI (match_operand 1 "" "")))]
0ad91047 7513 "TARGET_ELF && ! TARGET_64BIT"
a6c2a102 7514 "{liu|lis} %0,%1@ha")
4697a36c
MM		 7515
7516(define_insn "elf_low"
9ebbca7d
GK		 7517 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7518 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
4697a36c 7519 (match_operand 2 "" "")))]
0ad91047 7520 "TARGET_ELF && ! TARGET_64BIT"
9ebbca7d
GK		 7521 "@
7522 {cal|la} %0,%2@l(%1)
81eace42 7523 {ai|addic} %0,%1,%K2")
4697a36c 7524
ee890fe2
SS		 7525;; Mach-O PIC trickery.
7526(define_insn "macho_high"
7527 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7528 (high:SI (match_operand 1 "" "")))]
7529 "TARGET_MACHO && ! TARGET_64BIT"
7530 "{liu|lis} %0,ha16(%1)")
7531
7532(define_insn "macho_low"
7533 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7534 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7535 (match_operand 2 "" "")))]
7536 "TARGET_MACHO && ! TARGET_64BIT"
7537 "@
7538 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
7539 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
7540
766a866c
MM		 7541;; Set up a register with a value from the GOT table
7542
7543(define_expand "movsi_got"
52d3af72 7544 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 7545 (unspec:SI [(match_operand:SI 1 "got_operand" "")
615158e2 7546 (match_dup 2)] UNSPEC_MOVSI_GOT))]
f607bc57 7547 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 7548 "
7549{
38c1f2d7
MM		 7550 if (GET_CODE (operands[1]) == CONST)
7551 {
7552 rtx offset = const0_rtx;
7553 HOST_WIDE_INT value;
7554
7555 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7556 value = INTVAL (offset);
7557 if (value != 0)
7558 {
677a9668 7559 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
38c1f2d7
MM		 7560 emit_insn (gen_movsi_got (tmp, operands[1]));
7561 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7562 DONE;
7563 }
7564 }
7565
c4c40373 7566 operands[2] = rs6000_got_register (operands[1]);
766a866c
MM		 7567}")
7568
84f414bc 7569(define_insn "*movsi_got_internal"
52d3af72 7570 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9ebbca7d 7571 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 7572 (match_operand:SI 2 "gpc_reg_operand" "b")]
7573 UNSPEC_MOVSI_GOT))]
f607bc57 7574 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 7575 "{l|lwz} %0,%a1@got(%2)"
7576 [(set_attr "type" "load")])
7577
b22b9b3e
JL		 7578;; Used by sched, shorten_branches and final when the GOT pseudo reg
7579;; didn't get allocated to a hard register.
7580(define_split
75540af0 7581 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 7582 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 7583 (match_operand:SI 2 "memory_operand" "")]
7584 UNSPEC_MOVSI_GOT))]
f607bc57 7585 "DEFAULT_ABI == ABI_V4
b22b9b3e
JL		 7586 && flag_pic == 1
7587 && (reload_in_progress || reload_completed)"
7588 [(set (match_dup 0) (match_dup 2))
615158e2
JJ		 7589 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7590 UNSPEC_MOVSI_GOT))]
b22b9b3e
JL		 7591 "")
7592
1fd4e8c1
RK		 7593;; For SI, we special-case integers that can't be loaded in one insn. We
7594;; do the load 16-bits at a time. We could do this by loading from memory,
7595;; and this is even supposed to be faster, but it is simpler not to get
7596;; integers in the TOC.
7597(define_expand "movsi"
7598 [(set (match_operand:SI 0 "general_operand" "")
7599 (match_operand:SI 1 "any_operand" ""))]
7600 ""
fb4d4348 7601 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
1fd4e8c1 7602
ee890fe2
SS		 7603(define_insn "movsi_low"
7604 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
f585a356 7605 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
ee890fe2
SS		 7606 (match_operand 2 "" ""))))]
7607 "TARGET_MACHO && ! TARGET_64BIT"
7608 "{l|lwz} %0,lo16(%2)(%1)"
7609 [(set_attr "type" "load")
7610 (set_attr "length" "4")])
7611
c859cda6 7612(define_insn "movsi_low_st"
f585a356 7613 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
c859cda6
DJ		 7614 (match_operand 2 "" "")))
7615 (match_operand:SI 0 "gpc_reg_operand" "r"))]
7616 "TARGET_MACHO && ! TARGET_64BIT"
7617 "{st|stw} %0,lo16(%2)(%1)"
7618 [(set_attr "type" "store")
7619 (set_attr "length" "4")])
7620
7621(define_insn "movdf_low"
234e114c 7622 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
f585a356 7623 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
c859cda6 7624 (match_operand 2 "" ""))))]
a3170dc6 7625 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
234e114c
DJ		 7626 "*
7627{
7628 switch (which_alternative)
7629 {
7630 case 0:
7631 return \"lfd %0,lo16(%2)(%1)\";
7632 case 1:
7633 {
7634 rtx operands2[4];
7635 operands2[0] = operands[0];
7636 operands2[1] = operands[1];
7637 operands2[2] = operands[2];
683bdff7 7638 if (TARGET_POWERPC64 && TARGET_32BIT)
a3c9585f 7639 /* Note, old assemblers didn't support relocation here. */
683bdff7 7640 return \"ld %0,lo16(%2)(%1)\";
ab82a49f 7641 else
683bdff7
FJ		 7642 {
7643 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
7644 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
7645#if TARGET_MACHO
7646 if (MACHO_DYNAMIC_NO_PIC_P)
7647 output_asm_insn (\"{liu|lis} %L0,ha16(%2+4)\", operands);
7648 else
7649 /* We cannot rely on ha16(low half)==ha16(high half), alas,
7650 although in practice it almost always is. */
7651 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
ab82a49f 7652#endif
683bdff7
FJ		 7653 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
7654 }
234e114c
DJ		 7655 }
7656 default:
7657 abort();
7658 }
7659}"
c859cda6 7660 [(set_attr "type" "load")
234e114c 7661 (set_attr "length" "4,12")])
c859cda6
DJ		 7662
7663(define_insn "movdf_low_st"
f585a356 7664 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
c859cda6
DJ		 7665 (match_operand 2 "" "")))
7666 (match_operand:DF 0 "gpc_reg_operand" "f"))]
a3170dc6 7667 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
c859cda6
DJ		 7668 "stfd %0,lo16(%2)(%1)"
7669 [(set_attr "type" "store")
7670 (set_attr "length" "4")])
7671
7672(define_insn "movsf_low"
fd3b43f2 7673 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
f585a356 7674 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
c859cda6 7675 (match_operand 2 "" ""))))]
a3170dc6 7676 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
fd3b43f2
DJ		 7677 "@
7678 lfs %0,lo16(%2)(%1)
7679 {l|lwz} %0,lo16(%2)(%1)"
c859cda6
DJ		 7680 [(set_attr "type" "load")
7681 (set_attr "length" "4")])
7682
7683(define_insn "movsf_low_st"
f585a356 7684 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
c859cda6 7685 (match_operand 2 "" "")))
fd3b43f2 7686 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
a3170dc6 7687 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
fd3b43f2
DJ		 7688 "@
7689 stfs %0,lo16(%2)(%1)
7690 {st|stw} %0,lo16(%2)(%1)"
c859cda6
DJ		 7691 [(set_attr "type" "store")
7692 (set_attr "length" "4")])
7693
acad7ed3 7694(define_insn "*movsi_internal1"
a004eb82
AH		 7695 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7696 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
19d5775a
RK		 7697 "gpc_reg_operand (operands[0], SImode)
7698 || gpc_reg_operand (operands[1], SImode)"
1fd4e8c1 7699 "@
deb9225a 7700 mr %0,%1
b9442c72 7701 {cal|la} %0,%a1
ca7f5001
RK		 7702 {l%U1%X1|lwz%U1%X1} %0,%1
7703 {st%U0%X0|stw%U0%X0} %1,%0
19d5775a 7704 {lil|li} %0,%1
802a0058 7705 {liu|lis} %0,%v1
beaec479 7706 #
aee86b38 7707 {cal|la} %0,%a1
1fd4e8c1 7708 mf%1 %0
5c23c401 7709 mt%0 %1
e76e75bb 7710 mt%0 %1
a004eb82 7711 mt%0 %1
e34eaae5 7712 {cror 0,0,0|nop}"
02ca7595 7713 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
a004eb82 7714 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
1fd4e8c1 7715
77fa0940
RK		 7716;; Split a load of a large constant into the appropriate two-insn
7717;; sequence.
7718
7719(define_split
7720 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7721 (match_operand:SI 1 "const_int_operand" ""))]
bb21487f 7722 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
77fa0940
RK		 7723 && (INTVAL (operands[1]) & 0xffff) != 0"
7724 [(set (match_dup 0)
7725 (match_dup 2))
7726 (set (match_dup 0)
7727 (ior:SI (match_dup 0)
7728 (match_dup 3)))]
7729 "
af8cb5c5
DE		 7730{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7731
7732 if (tem == operands[0])
7733 DONE;
7734 else
7735 FAIL;
77fa0940
RK		 7736}")
7737
acad7ed3 7738(define_insn "*movsi_internal2"
bb84cb12
DE		 7739 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7740 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r")
1fd4e8c1 7741 (const_int 0)))
bb84cb12 7742 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
4b8a63d6 7743 "TARGET_32BIT"
9ebbca7d 7744 "@
bb84cb12 7745 {cmpi|cmpwi} %2,%0,0
9ebbca7d
GK		 7746 mr. %0,%1
7747 #"
bb84cb12
DE		 7748 [(set_attr "type" "cmp,compare,cmp")
7749 (set_attr "length" "4,4,8")])
7750
9ebbca7d
GK		 7751(define_split
7752 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7753 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7754 (const_int 0)))
7755 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
4b8a63d6 7756 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 7757 [(set (match_dup 0) (match_dup 1))
7758 (set (match_dup 2)
7759 (compare:CC (match_dup 0)
7760 (const_int 0)))]
7761 "")
bb84cb12 7762\f
1fd4e8c1
RK		 7763(define_expand "movhi"
7764 [(set (match_operand:HI 0 "general_operand" "")
7765 (match_operand:HI 1 "any_operand" ""))]
7766 ""
fb4d4348 7767 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
1fd4e8c1 7768
e34eaae5 7769(define_insn "*movhi_internal"
fb81d7ce
RK		 7770 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7771 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 7772 "gpc_reg_operand (operands[0], HImode)
7773 || gpc_reg_operand (operands[1], HImode)"
1fd4e8c1 7774 "@
deb9225a 7775 mr %0,%1
1fd4e8c1
RK		 7776 lhz%U1%X1 %0,%1
7777 sth%U0%X0 %1,%0
19d5775a 7778 {lil|li} %0,%w1
1fd4e8c1 7779 mf%1 %0
e76e75bb 7780 mt%0 %1
fb81d7ce 7781 mt%0 %1
e34eaae5 7782 {cror 0,0,0|nop}"
02ca7595 7783 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1
RK		 7784
7785(define_expand "movqi"
7786 [(set (match_operand:QI 0 "general_operand" "")
7787 (match_operand:QI 1 "any_operand" ""))]
7788 ""
fb4d4348 7789 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
1fd4e8c1 7790
e34eaae5 7791(define_insn "*movqi_internal"
fb81d7ce
RK		 7792 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7793 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 7794 "gpc_reg_operand (operands[0], QImode)
7795 || gpc_reg_operand (operands[1], QImode)"
1fd4e8c1 7796 "@
deb9225a 7797 mr %0,%1
1fd4e8c1
RK		 7798 lbz%U1%X1 %0,%1
7799 stb%U0%X0 %1,%0
19d5775a 7800 {lil|li} %0,%1
1fd4e8c1 7801 mf%1 %0
e76e75bb 7802 mt%0 %1
fb81d7ce 7803 mt%0 %1
e34eaae5 7804 {cror 0,0,0|nop}"
02ca7595 7805 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1
RK		 7806\f
7807;; Here is how to move condition codes around. When we store CC data in
7808;; an integer register or memory, we store just the high-order 4 bits.
7809;; This lets us not shift in the most common case of CR0.
7810(define_expand "movcc"
7811 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7812 (match_operand:CC 1 "nonimmediate_operand" ""))]
7813 ""
7814 "")
7815
a65c591c 7816(define_insn "*movcc_internal1"
b54cf83a
DE		 7817 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7818 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
1fd4e8c1
RK		 7819 "register_operand (operands[0], CCmode)
7820 || register_operand (operands[1], CCmode)"
7821 "@
7822 mcrf %0,%1
7823 mtcrf 128,%1
ca7f5001 7824 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
2c4a9cff
DE		 7825 mfcr %0%Q1
7826 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
deb9225a 7827 mr %0,%1
b54cf83a 7828 mf%1 %0
b991a865
GK		 7829 mt%0 %1
7830 mt%0 %1
ca7f5001
RK		 7831 {l%U1%X1|lwz%U1%X1} %0,%1
7832 {st%U0%U1|stw%U0%U1} %1,%0"
2c4a9cff
DE		 7833 [(set (attr "type")
7834 (cond [(eq_attr "alternative" "0")
7835 (const_string "cr_logical")
7836 (eq_attr "alternative" "1,2")
7837 (const_string "mtcr")
7838 (eq_attr "alternative" "5,7")
7839 (const_string "integer")
7840 (eq_attr "alternative" "6")
7841 (const_string "mfjmpr")
7842 (eq_attr "alternative" "8")
7843 (const_string "mtjmpr")
7844 (eq_attr "alternative" "9")
7845 (const_string "load")
7846 (eq_attr "alternative" "10")
7847 (const_string "store")
7848 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7849 (const_string "mfcrf")
7850 ]
7851 (const_string "mfcr")))
b991a865 7852 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
1fd4e8c1 7853\f
e52e05ca
MM		 7854;; For floating-point, we normally deal with the floating-point registers
7855;; unless -msoft-float is used. The sole exception is that parameter passing
7856;; can produce floating-point values in fixed-point registers. Unless the
7857;; value is a simple constant or already in memory, we deal with this by
7858;; allocating memory and copying the value explicitly via that memory location.
1fd4e8c1
RK		 7859(define_expand "movsf"
7860 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7861 (match_operand:SF 1 "any_operand" ""))]
7862 ""
fb4d4348 7863 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
1fd4e8c1 7864
1fd4e8c1 7865(define_split
cd2b37d9 7866 [(set (match_operand:SF 0 "gpc_reg_operand" "")
c4c40373 7867 (match_operand:SF 1 "const_double_operand" ""))]
f99f88e0 7868 "reload_completed
5ae4759c
MM		 7869 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7870 || (GET_CODE (operands[0]) == SUBREG
7871 && GET_CODE (SUBREG_REG (operands[0])) == REG
7872 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373 7873 [(set (match_dup 2) (match_dup 3))]
685f3906
DE		 7874 "
7875{
7876 long l;
7877 REAL_VALUE_TYPE rv;
7878
7879 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7880 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
c4c40373 7881
f99f88e0
DE		 7882 if (! TARGET_POWERPC64)
7883 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7884 else
7885 operands[2] = gen_lowpart (SImode, operands[0]);
a260abc9 7886
2496c7bd 7887 operands[3] = gen_int_mode (l, SImode);
a260abc9
DE		 7888}")
7889
c4c40373 7890(define_insn "*movsf_hardfloat"
b991a865
GK		 7891 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!r,!r")
7892 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,G,Fn"))]
d14a6d05 7893 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 7894 || gpc_reg_operand (operands[1], SFmode))
7895 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
1fd4e8c1 7896 "@
f99f88e0
DE		 7897 mr %0,%1
7898 {l%U1%X1|lwz%U1%X1} %0,%1
7899 {st%U0%X0|stw%U0%X0} %1,%0
1fd4e8c1
RK		 7900 fmr %0,%1
7901 lfs%U1%X1 %0,%1
c4c40373 7902 stfs%U0%X0 %1,%0
b991a865
GK		 7903 mt%0 %1
7904 mt%0 %1
7905 mf%1 %0
c4c40373
MM		 7906 #
7907 #"
b991a865
GK		 7908 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*")
7909 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
d14a6d05 7910
c4c40373 7911(define_insn "*movsf_softfloat"
dd0fbae2
MK		 7912 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
7913 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
d14a6d05 7914 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 7915 || gpc_reg_operand (operands[1], SFmode))
7916 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
d14a6d05
MM		 7917 "@
7918 mr %0,%1
b991a865
GK		 7919 mt%0 %1
7920 mt%0 %1
7921 mf%1 %0
d14a6d05
MM		 7922 {l%U1%X1|lwz%U1%X1} %0,%1
7923 {st%U0%X0|stw%U0%X0} %1,%0
7924 {lil|li} %0,%1
802a0058 7925 {liu|lis} %0,%v1
aee86b38 7926 {cal|la} %0,%a1
c4c40373 7927 #
dd0fbae2
MK		 7928 #
7929 {cror 0,0,0|nop}"
7930 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
7931 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
d14a6d05 7932
1fd4e8c1
RK		 7933\f
7934(define_expand "movdf"
7935 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7936 (match_operand:DF 1 "any_operand" ""))]
7937 ""
fb4d4348 7938 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
1fd4e8c1
RK		 7939
7940(define_split
cd2b37d9 7941 [(set (match_operand:DF 0 "gpc_reg_operand" "")
c4c40373 7942 (match_operand:DF 1 "const_int_operand" ""))]
a260abc9 7943 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 7944 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7945 || (GET_CODE (operands[0]) == SUBREG
7946 && GET_CODE (SUBREG_REG (operands[0])) == REG
7947 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 7948 [(set (match_dup 2) (match_dup 4))
7949 (set (match_dup 3) (match_dup 1))]
7950 "
7951{
5ae4759c 7952 int endian = (WORDS_BIG_ENDIAN == 0);
5f59ecb7
DE		 7953 HOST_WIDE_INT value = INTVAL (operands[1]);
7954
5ae4759c
MM		 7955 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7956 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5f59ecb7
DE		 7957#if HOST_BITS_PER_WIDE_INT == 32
7958 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7959#else
7960 operands[4] = GEN_INT (value >> 32);
a65c591c 7961 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
5f59ecb7 7962#endif
c4c40373
MM		 7963}")
7964
c4c40373
MM		 7965(define_split
7966 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7967 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 7968 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 7969 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7970 || (GET_CODE (operands[0]) == SUBREG
7971 && GET_CODE (SUBREG_REG (operands[0])) == REG
7972 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 7973 [(set (match_dup 2) (match_dup 4))
7974 (set (match_dup 3) (match_dup 5))]
7975 "
7976{
5ae4759c 7977 int endian = (WORDS_BIG_ENDIAN == 0);
47ad8c61
MM		 7978 long l[2];
7979 REAL_VALUE_TYPE rv;
7980
7981 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7982 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7983
5ae4759c
MM		 7984 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7985 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
2496c7bd
LB		 7986 operands[4] = gen_int_mode (l[endian], SImode);
7987 operands[5] = gen_int_mode (l[1 - endian], SImode);
c4c40373
MM		 7988}")
7989
efc08378
DE		 7990(define_split
7991 [(set (match_operand:DF 0 "gpc_reg_operand" "")
685f3906 7992 (match_operand:DF 1 "easy_fp_constant" ""))]
a260abc9 7993 "TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 7994 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7995 || (GET_CODE (operands[0]) == SUBREG
7996 && GET_CODE (SUBREG_REG (operands[0])) == REG
7997 && REGNO (SUBREG_REG (operands[0])) <= 31))"
a260abc9 7998 [(set (match_dup 2) (match_dup 3))]
5ae4759c 7999 "
a260abc9
DE		 8000{
8001 int endian = (WORDS_BIG_ENDIAN == 0);
8002 long l[2];
8003 REAL_VALUE_TYPE rv;
4977bab6 8004#if HOST_BITS_PER_WIDE_INT >= 64
5b029315 8005 HOST_WIDE_INT val;
4977bab6 8006#endif
a260abc9
DE		 8007
8008 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8009 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8010
8011 operands[2] = gen_lowpart (DImode, operands[0]);
8012 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
5b029315 8013#if HOST_BITS_PER_WIDE_INT >= 64
a2419b96
DE		 8014 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8015 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
5b029315 8016
f5264b52 8017 operands[3] = gen_int_mode (val, DImode);
5b029315 8018#else
a260abc9 8019 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
5b029315 8020#endif
a260abc9 8021}")
efc08378 8022
4eae5fe1 8023;; Don't have reload use general registers to load a constant. First,
1427100a 8024;; it might not work if the output operand is the equivalent of
4eae5fe1
RK		 8025;; a non-offsettable memref, but also it is less efficient than loading
8026;; the constant into an FP register, since it will probably be used there.
8027;; The "??" is a kludge until we can figure out a more reasonable way
8028;; of handling these non-offsettable values.
c4c40373 8029(define_insn "*movdf_hardfloat32"
914a7297
DE		 8030 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8031 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
a3170dc6 8032 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8033 && (gpc_reg_operand (operands[0], DFmode)
8034 || gpc_reg_operand (operands[1], DFmode))"
e7113111
RK		 8035 "*
8036{
8037 switch (which_alternative)
8038 {
a260abc9 8039 default:
a6c2a102 8040 abort ();
e7113111
RK		 8041 case 0:
8042 /* We normally copy the low-numbered register first. However, if
000034eb
DE		 8043 the first register operand 0 is the same as the second register
8044 of operand 1, we must copy in the opposite order. */
e7113111 8045 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
deb9225a 8046 return \"mr %L0,%L1\;mr %0,%1\";
e7113111 8047 else
deb9225a 8048 return \"mr %0,%1\;mr %L0,%L1\";
e7113111 8049 case 1:
2b97222d
DE		 8050 if (offsettable_memref_p (operands[1])
8051 || (GET_CODE (operands[1]) == MEM
69f51a21
DE		 8052 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8053 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8054 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
000034eb
DE		 8055 {
8056 /* If the low-address word is used in the address, we must load
8057 it last. Otherwise, load it first. Note that we cannot have
8058 auto-increment in that case since the address register is
8059 known to be dead. */
8060 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8061 operands[1], 0))
8062 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8063 else
8064 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8065 }
e7113111 8066 else
000034eb
DE		 8067 {
8068 rtx addreg;
8069
000034eb
DE		 8070 addreg = find_addr_reg (XEXP (operands[1], 0));
8071 if (refers_to_regno_p (REGNO (operands[0]),
8072 REGNO (operands[0]) + 1,
8073 operands[1], 0))
8074 {
8075 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2b97222d 8076 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
000034eb 8077 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
2b97222d 8078 return \"{lx|lwzx} %0,%1\";
000034eb
DE		 8079 }
8080 else
8081 {
2b97222d 8082 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
000034eb 8083 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2b97222d 8084 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
000034eb
DE		 8085 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8086 return \"\";
8087 }
8088 }
e7113111 8089 case 2:
2b97222d
DE		 8090 if (offsettable_memref_p (operands[0])
8091 || (GET_CODE (operands[0]) == MEM
69f51a21
DE		 8092 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8093 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8094 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
000034eb
DE		 8095 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8096 else
8097 {
8098 rtx addreg;
8099
000034eb 8100 addreg = find_addr_reg (XEXP (operands[0], 0));
2b97222d 8101 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
000034eb 8102 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2b97222d 8103 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
000034eb
DE		 8104 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8105 return \"\";
8106 }
e7113111 8107 case 3:
914a7297 8108 return \"fmr %0,%1\";
e7113111 8109 case 4:
914a7297 8110 return \"lfd%U1%X1 %0,%1\";
e7113111 8111 case 5:
914a7297 8112 return \"stfd%U0%X0 %1,%0\";
e7113111 8113 case 6:
c4c40373 8114 case 7:
c4c40373 8115 case 8:
914a7297 8116 return \"#\";
e7113111
RK		 8117 }
8118}"
914a7297
DE		 8119 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
8120 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
51b8fc2c 8121
c4c40373 8122(define_insn "*movdf_softfloat32"
1427100a
DE		 8123 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8124 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
a3170dc6 8125 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
52d3af72
DE		 8126 && (gpc_reg_operand (operands[0], DFmode)
8127 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca
MM		 8128 "*
8129{
8130 switch (which_alternative)
8131 {
a260abc9 8132 default:
a6c2a102 8133 abort ();
dc4f83ca
MM		 8134 case 0:
8135 /* We normally copy the low-numbered register first. However, if
8136 the first register operand 0 is the same as the second register of
8137 operand 1, we must copy in the opposite order. */
8138 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8139 return \"mr %L0,%L1\;mr %0,%1\";
8140 else
8141 return \"mr %0,%1\;mr %L0,%L1\";
8142 case 1:
3cb999d8
DE		 8143 /* If the low-address word is used in the address, we must load
8144 it last. Otherwise, load it first. Note that we cannot have
8145 auto-increment in that case since the address register is
8146 known to be dead. */
dc4f83ca 8147 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3cb999d8 8148 operands[1], 0))
dc4f83ca
MM		 8149 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8150 else
8151 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8152 case 2:
8153 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8154 case 3:
c4c40373
MM		 8155 case 4:
8156 case 5:
dc4f83ca
MM		 8157 return \"#\";
8158 }
8159}"
c4c40373
MM		 8160 [(set_attr "type" "*,load,store,*,*,*")
8161 (set_attr "length" "8,8,8,8,12,16")])
dc4f83ca 8162
d2288d5d
HP		 8163; ld/std require word-aligned displacements -> 'Y' constraint.
8164; List Y->r and r->Y before r->r for reload.
c4c40373 8165(define_insn "*movdf_hardfloat64"
99e5c00b 8166 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!r,!r,!r")
d2288d5d 8167 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,G,H,F"))]
a3170dc6 8168 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8169 && (gpc_reg_operand (operands[0], DFmode)
8170 || gpc_reg_operand (operands[1], DFmode))"
51b8fc2c 8171 "@
96bb8ed3 8172 std%U0%X0 %1,%0
3364872d
FJ		 8173 ld%U1%X1 %0,%1
8174 mr %0,%1
3d5570cb 8175 fmr %0,%1
f63184ac 8176 lfd%U1%X1 %0,%1
914a7297
DE		 8177 stfd%U0%X0 %1,%0
8178 mt%0 %1
8179 mf%1 %0
8180 #
8181 #
8182 #"
8183 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*")
8184 (set_attr "length" "4,4,4,4,4,4,4,4,8,12,16")])
dc4f83ca 8185
c4c40373 8186(define_insn "*movdf_softfloat64"
d2288d5d
HP		 8187 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8188 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
a3170dc6 8189 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
52d3af72
DE		 8190 && (gpc_reg_operand (operands[0], DFmode)
8191 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca 8192 "@
d2288d5d
HP		 8193 ld%U1%X1 %0,%1
8194 std%U0%X0 %1,%0
dc4f83ca 8195 mr %0,%1
914a7297
DE		 8196 mt%0 %1
8197 mf%1 %0
c4c40373
MM		 8198 #
8199 #
e2d0915c
AM		 8200 #
8201 nop"
d2288d5d 8202 [(set_attr "type" "load,store,*,*,*,*,*,*,*")
e2d0915c 8203 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
1fd4e8c1 8204\f
06f4e019
DE		 8205(define_expand "movtf"
8206 [(set (match_operand:TF 0 "general_operand" "")
8207 (match_operand:TF 1 "any_operand" ""))]
39e63627
GK		 8208 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8209 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8210 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8211
a9baceb1
GK		 8212; It's important to list the o->f and f->o moves before f->f because
8213; otherwise reload, given m->f, will try to pick f->f and reload it,
8214; which doesn't make progress.
8215(define_insn_and_split "*movtf_internal"
8216 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,rm,r")
8217 (match_operand:TF 1 "input_operand" "f,o,f,r,mGHF"))]
39e63627
GK		 8218 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8219 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
06f4e019
DE		 8220 && (gpc_reg_operand (operands[0], TFmode)
8221 || gpc_reg_operand (operands[1], TFmode))"
a9baceb1 8222 "#"
ecb62ae7 8223 "&& reload_completed"
a9baceb1
GK		 8224 [(pc)]
8225{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8226 [(set_attr "length" "8,8,8,20,20")])
06f4e019 8227
ecb62ae7
GK		 8228(define_expand "extenddftf2"
8229 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8230 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8231 (use (match_dup 2))])]
39e63627
GK		 8232 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8233 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8234{
ecb62ae7
GK		 8235 operands[2] = CONST0_RTX (DFmode);
8236})
06f4e019 8237
ecb62ae7
GK		 8238(define_insn_and_split "*extenddftf2_internal"
8239 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8240 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8241 (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))]
39e63627
GK		 8242 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8243 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8244 "#"
8245 "&& reload_completed"
8246 [(pc)]
06f4e019 8247{
ecb62ae7
GK		 8248 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8249 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8250 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8251 operands[1]);
8252 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8253 operands[2]);
8254 DONE;
8255})
8256
8257(define_expand "extendsftf2"
8258 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8259 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8260 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8261 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8262{
8263 rtx tmp = gen_reg_rtx (DFmode);
8264 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8265 emit_insn (gen_extenddftf2 (operands[0], tmp));
8266 DONE;
8267})
06f4e019
DE		 8268
8269(define_insn "trunctfdf2"
8270 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8271 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
39e63627
GK		 8272 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8273 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8274 "fadd %0,%1,%L1"
8275 [(set_attr "type" "fp")
ecb62ae7 8276 (set_attr "length" "4")])
06f4e019
DE		 8277
8278(define_insn_and_split "trunctfsf2"
8279 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
ea112fc4
DE		 8280 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8281 (clobber (match_scratch:DF 2 "=f"))]
39e63627
GK		 8282 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8283 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8284 "#"
ea112fc4 8285 "&& reload_completed"
06f4e019
DE		 8286 [(set (match_dup 2)
8287 (float_truncate:DF (match_dup 1)))
8288 (set (match_dup 0)
8289 (float_truncate:SF (match_dup 2)))]
ea112fc4 8290 "")
06f4e019 8291
0c90aa3c 8292(define_expand "floatsitf2"
ea112fc4 8293 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
0c90aa3c 8294 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
39e63627
GK		 8295 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8296 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
0c90aa3c
GK		 8297{
8298 rtx tmp = gen_reg_rtx (DFmode);
8299 expand_float (tmp, operands[1], false);
8300 emit_insn (gen_extenddftf2 (operands[0], tmp));
8301 DONE;
8302})
06f4e019 8303
ecb62ae7
GK		 8304; fadd, but rounding towards zero.
8305; This is probably not the optimal code sequence.
8306(define_insn "fix_trunc_helper"
8307 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8308 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8309 UNSPEC_FIX_TRUNC_TF))
8310 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8311 "TARGET_HARD_FLOAT && TARGET_FPRS"
8312 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8313 [(set_attr "type" "fp")
8314 (set_attr "length" "20")])
8315
0c90aa3c 8316(define_expand "fix_trunctfsi2"
ecb62ae7
GK		 8317 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8318 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8319 (clobber (match_dup 2))
8320 (clobber (match_dup 3))
8321 (clobber (match_dup 4))
8322 (clobber (match_dup 5))])]
8323 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8324 && (TARGET_POWER2 || TARGET_POWERPC)
8325 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8326{
8327 operands[2] = gen_reg_rtx (DFmode);
8328 operands[3] = gen_reg_rtx (DFmode);
8329 operands[4] = gen_reg_rtx (DImode);
8330 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8331})
8332
8333(define_insn_and_split "*fix_trunctfsi2_internal"
61c07d3c 8334 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
ecb62ae7
GK		 8335 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8336 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8337 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8338 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8339 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
39e63627
GK		 8340 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8341 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8342 "#"
8343 "&& reload_completed"
8344 [(pc)]
0c90aa3c 8345{
ecb62ae7
GK		 8346 rtx lowword;
8347 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8348
8349 if (GET_CODE (operands[5]) != MEM)
8350 abort();
8351 lowword = XEXP (operands[5], 0);
8352 if (WORDS_BIG_ENDIAN)
8353 lowword = plus_constant (lowword, 4);
8354
8355 emit_insn (gen_fctiwz (operands[4], operands[2]));
8356 emit_move_insn (operands[5], operands[4]);
8357 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
0c90aa3c
GK		 8358 DONE;
8359})
06f4e019
DE		 8360
8361(define_insn "negtf2"
8362 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8363 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
39e63627
GK		 8364 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8365 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8366 "*
8367{
8368 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8369 return \"fneg %L0,%L1\;fneg %0,%1\";
8370 else
8371 return \"fneg %0,%1\;fneg %L0,%L1\";
8372}"
8373 [(set_attr "type" "fp")
8374 (set_attr "length" "8")])
8375
8376(define_insn "abstf2"
8377 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8378 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
39e63627
GK		 8379 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8380 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8381 "*
8382{
8383 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8384 return \"fabs %L0,%L1\;fabs %0,%1\";
8385 else
8386 return \"fabs %0,%1\;fabs %L0,%L1\";
8387}"
8388 [(set_attr "type" "fp")
8389 (set_attr "length" "8")])
8390
8391(define_insn ""
8392 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8393 (neg:TF (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f"))))]
39e63627
GK		 8394 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8395 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8396 "*
8397{
8398 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8399 return \"fnabs %L0,%L1\;fnabs %0,%1\";
8400 else
8401 return \"fnabs %0,%1\;fnabs %L0,%L1\";
8402}"
8403 [(set_attr "type" "fp")
8404 (set_attr "length" "8")])
8405\f
1fd4e8c1
RK		 8406;; Next come the multi-word integer load and store and the load and store
8407;; multiple insns.
8408(define_expand "movdi"
8409 [(set (match_operand:DI 0 "general_operand" "")
e6ca2c17 8410 (match_operand:DI 1 "any_operand" ""))]
1fd4e8c1 8411 ""
fb4d4348 8412 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
1fd4e8c1 8413
acad7ed3 8414(define_insn "*movdi_internal32"
4e74d8ec
MM		 8415 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
8416 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
a260abc9 8417 "! TARGET_POWERPC64
4e74d8ec
MM		 8418 && (gpc_reg_operand (operands[0], DImode)
8419 || gpc_reg_operand (operands[1], DImode))"
1fd4e8c1
RK		 8420 "*
8421{
8422 switch (which_alternative)
8423 {
a260abc9 8424 default:
a6c2a102 8425 abort ();
1fd4e8c1 8426 case 0:
1fd4e8c1 8427 case 1:
1fd4e8c1 8428 case 2:
3a1f863f 8429 return \"#\";
8ffd9c51
RK		 8430 case 3:
8431 return \"fmr %0,%1\";
8432 case 4:
8433 return \"lfd%U1%X1 %0,%1\";
8434 case 5:
8435 return \"stfd%U0%X0 %1,%0\";
4e74d8ec
MM		 8436 case 6:
8437 case 7:
8438 case 8:
8439 case 9:
8440 case 10:
8441 return \"#\";
1fd4e8c1
RK		 8442 }
8443}"
3a1f863f 8444 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")])
4e74d8ec
MM		 8445
8446(define_split
8447 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8448 (match_operand:DI 1 "const_int_operand" ""))]
a260abc9 8449 "! TARGET_POWERPC64 && reload_completed"
4e74d8ec
MM		 8450 [(set (match_dup 2) (match_dup 4))
8451 (set (match_dup 3) (match_dup 1))]
8452 "
8453{
5f59ecb7 8454 HOST_WIDE_INT value = INTVAL (operands[1]);
bdaa0181
GK		 8455 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8456 DImode);
8457 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8458 DImode);
75d39459 8459#if HOST_BITS_PER_WIDE_INT == 32
5f59ecb7 8460 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
75d39459 8461#else
5f59ecb7 8462 operands[4] = GEN_INT (value >> 32);
a65c591c 8463 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
75d39459 8464#endif
4e74d8ec
MM		 8465}")
8466
3a1f863f
DE		 8467(define_split
8468 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8469 (match_operand:DI 1 "input_operand" ""))]
8470 "reload_completed && !TARGET_POWERPC64
8471 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 8472 [(pc)]
8473{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
3a1f863f 8474
6fc19dc9
AM		 8475(define_split
8476 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8477 (match_operand:TI 1 "const_double_operand" ""))]
8478 "TARGET_POWERPC64"
8479 [(set (match_dup 2) (match_dup 4))
8480 (set (match_dup 3) (match_dup 5))]
8481 "
8482{
8483 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8484 TImode);
8485 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8486 TImode);
8487 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8488 {
8489 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8490 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8491 }
8492 else if (GET_CODE (operands[1]) == CONST_INT)
8493 {
8494 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8495 operands[5] = operands[1];
8496 }
8497 else
8498 FAIL;
8499}")
8500
acad7ed3 8501(define_insn "*movdi_internal64"
5d7e6254 8502 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h")
9615f239 8503 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
a260abc9 8504 "TARGET_POWERPC64
4e74d8ec
MM		 8505 && (gpc_reg_operand (operands[0], DImode)
8506 || gpc_reg_operand (operands[1], DImode))"
51b8fc2c 8507 "@
3d5570cb
RK		 8508 mr %0,%1
8509 ld%U1%X1 %0,%1
96bb8ed3 8510 std%U0%X0 %1,%0
3d5570cb 8511 li %0,%1
802a0058 8512 lis %0,%v1
e6ca2c17 8513 #
aee86b38 8514 {cal|la} %0,%a1
3d5570cb
RK		 8515 fmr %0,%1
8516 lfd%U1%X1 %0,%1
8517 stfd%U0%X0 %1,%0
8518 mf%1 %0
08075ead 8519 mt%0 %1
e34eaae5 8520 {cror 0,0,0|nop}"
02ca7595 8521 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
e6ca2c17
DE		 8522 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8523
5f59ecb7 8524;; immediate value valid for a single instruction hiding in a const_double
a260abc9
DE		 8525(define_insn ""
8526 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8527 (match_operand:DI 1 "const_double_operand" "F"))]
5f59ecb7
DE		 8528 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8529 && GET_CODE (operands[1]) == CONST_DOUBLE
a260abc9
DE		 8530 && num_insns_constant (operands[1], DImode) == 1"
8531 "*
8532{
8533 return ((unsigned HOST_WIDE_INT)
8534 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8535 ? \"li %0,%1\" : \"lis %0,%v1\";
8536}")
8537
a260abc9
DE		 8538;; Generate all one-bits and clear left or right.
8539;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8540(define_split
8541 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8542 (match_operand:DI 1 "mask64_operand" ""))]
8543 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8544 [(set (match_dup 0) (const_int -1))
e6ca2c17 8545 (set (match_dup 0)
a260abc9
DE		 8546 (and:DI (rotate:DI (match_dup 0)
8547 (const_int 0))
8548 (match_dup 1)))]
8549 "")
8550
8551;; Split a load of a large constant into the appropriate five-instruction
8552;; sequence. Handle anything in a constant number of insns.
8553;; When non-easy constants can go in the TOC, this should use
8554;; easy_fp_constant predicate.
8555(define_split
8556 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 8557 (match_operand:DI 1 "const_int_operand" ""))]
8558 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8559 [(set (match_dup 0) (match_dup 2))
8560 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
e6ca2c17 8561 "
2bfcf297
DB		 8562{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8563
8564 if (tem == operands[0])
8565 DONE;
e8d791dd 8566 else
2bfcf297 8567 FAIL;
5f59ecb7 8568}")
e6ca2c17 8569
5f59ecb7
DE		 8570(define_split
8571 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 8572 (match_operand:DI 1 "const_double_operand" ""))]
8573 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8574 [(set (match_dup 0) (match_dup 2))
8575 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5f59ecb7 8576 "
2bfcf297
DB		 8577{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8578
8579 if (tem == operands[0])
8580 DONE;
8581 else
8582 FAIL;
e6ca2c17 8583}")
08075ead 8584
acad7ed3 8585(define_insn "*movdi_internal2"
bb84cb12
DE		 8586 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8587 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r")
08075ead 8588 (const_int 0)))
bb84cb12 8589 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
683bdff7 8590 "TARGET_64BIT"
9ebbca7d 8591 "@
bb84cb12 8592 cmpdi %2,%0,0
9ebbca7d
GK		 8593 mr. %0,%1
8594 #"
bb84cb12
DE		 8595 [(set_attr "type" "cmp,compare,cmp")
8596 (set_attr "length" "4,4,8")])
acad7ed3 8597
9ebbca7d
GK		 8598(define_split
8599 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8600 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8601 (const_int 0)))
8602 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8603 "TARGET_POWERPC64 && reload_completed"
8604 [(set (match_dup 0) (match_dup 1))
8605 (set (match_dup 2)
8606 (compare:CC (match_dup 0)
8607 (const_int 0)))]
8608 "")
acad7ed3 8609\f
1fd4e8c1
RK		 8610;; TImode is similar, except that we usually want to compute the address into
8611;; a register and use lsi/stsi (the exception is during reload). MQ is also
ca7f5001 8612;; clobbered in stsi for POWER, so we need a SCRATCH for it.
1fd4e8c1
RK		 8613(define_expand "movti"
8614 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8615 (match_operand:TI 1 "general_operand" ""))
8616 (clobber (scratch:SI))])]
3a1f863f 8617 ""
fb4d4348 8618 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
1fd4e8c1
RK		 8619
8620;; We say that MQ is clobbered in the last alternative because the first
8621;; alternative would never get used otherwise since it would need a reload
8622;; while the 2nd alternative would not. We put memory cases first so they
8623;; are preferred. Otherwise, we'd try to reload the output instead of
8624;; giving the SCRATCH mq.
3a1f863f 8625
a260abc9 8626(define_insn "*movti_power"
e1469d0d 8627 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
1fd4e8c1
RK		 8628 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8629 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
683bdff7 8630 "TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca 8631 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
1fd4e8c1
RK		 8632 "*
8633{
8634 switch (which_alternative)
8635 {
dc4f83ca
MM		 8636 default:
8637 abort ();
8638
1fd4e8c1 8639 case 0:
3a1f863f
DE		 8640 if (TARGET_STRING)
8641 return \"{stsi|stswi} %1,%P0,16\";
1fd4e8c1 8642 case 1:
1fd4e8c1 8643 case 2:
3a1f863f 8644 return \"#\";
1fd4e8c1
RK		 8645 case 3:
8646 /* If the address is not used in the output, we can use lsi. Otherwise,
8647 fall through to generating four loads. */
e876481c
DE		 8648 if (TARGET_STRING
8649 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
ca7f5001 8650 return \"{lsi|lswi} %0,%P1,16\";
82e41834 8651 /* ... fall through ... */
1fd4e8c1 8652 case 4:
3a1f863f 8653 return \"#\";
1fd4e8c1
RK		 8654 }
8655}"
3a1f863f 8656 [(set_attr "type" "store,store,*,load,load")])
51b8fc2c 8657
a260abc9 8658(define_insn "*movti_string"
cd1d3445 8659 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
27dc0551 8660 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))]
3a1f863f 8661 "! TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca
MM		 8662 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8663 "*
8664{
8665 switch (which_alternative)
8666 {
8667 default:
8668 abort ();
dc4f83ca 8669 case 0:
3a1f863f
DE		 8670 if (TARGET_STRING)
8671 return \"{stsi|stswi} %1,%P0,16\";
dc4f83ca 8672 case 1:
cd1d3445 8673 case 2:
3a1f863f 8674 return \"#\";
cd1d3445
DE		 8675 case 3:
8676 /* If the address is not used in the output, we can use lsi. Otherwise,
8677 fall through to generating four loads. */
3a1f863f
DE		 8678 if (TARGET_STRING
8679 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
cd1d3445
DE		 8680 return \"{lsi|lswi} %0,%P1,16\";
8681 /* ... fall through ... */
8682 case 4:
3a1f863f 8683 return \"#\";
dc4f83ca
MM		 8684 }
8685}"
3a1f863f 8686 [(set_attr "type" "store,store,*,load,load")])
dc4f83ca 8687
a260abc9 8688(define_insn "*movti_ppc64"
3a1f863f
DE		 8689 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,m,r")
8690 (match_operand:TI 1 "input_operand" "r,r,o"))]
51b8fc2c
RK		 8691 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8692 || gpc_reg_operand (operands[1], TImode))"
3a1f863f
DE		 8693 "@
8694 #
8695 #
8696 #"
8697 [(set_attr "type" "*,load,store")])
8698
8699(define_split
8700 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8701 (match_operand:TI 1 "input_operand" ""))]
a9baceb1 8702 "reload_completed
3a1f863f 8703 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 8704 [(pc)]
8705{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
1fd4e8c1
RK		 8706\f
8707(define_expand "load_multiple"
2f622005
RK		 8708 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8709 (match_operand:SI 1 "" ""))
8710 (use (match_operand:SI 2 "" ""))])]
09a625f7 8711 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 8712 "
8713{
8714 int regno;
8715 int count;
792760b9 8716 rtx op1;
1fd4e8c1
RK		 8717 int i;
8718
8719 /* Support only loading a constant number of fixed-point registers from
8720 memory and only bother with this if more than two; the machine
8721 doesn't support more than eight. */
8722 if (GET_CODE (operands[2]) != CONST_INT
8723 || INTVAL (operands[2]) <= 2
8724 || INTVAL (operands[2]) > 8
8725 || GET_CODE (operands[1]) != MEM
8726 || GET_CODE (operands[0]) != REG
8727 || REGNO (operands[0]) >= 32)
8728 FAIL;
8729
8730 count = INTVAL (operands[2]);
8731 regno = REGNO (operands[0]);
8732
39403d82 8733 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
792760b9
RK		 8734 op1 = replace_equiv_address (operands[1],
8735 force_reg (SImode, XEXP (operands[1], 0)));
1fd4e8c1
RK		 8736
8737 for (i = 0; i < count; i++)
8738 XVECEXP (operands[3], 0, i)
39403d82 8739 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
7ef788f0 8740 adjust_address_nv (op1, SImode, i * 4));
1fd4e8c1
RK		 8741}")
8742
9caa3eb2 8743(define_insn "*ldmsi8"
1fd4e8c1 8744 [(match_parallel 0 "load_multiple_operation"
9caa3eb2
DE		 8745 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8746 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8747 (set (match_operand:SI 3 "gpc_reg_operand" "")
8748 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8749 (set (match_operand:SI 4 "gpc_reg_operand" "")
8750 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8751 (set (match_operand:SI 5 "gpc_reg_operand" "")
8752 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8753 (set (match_operand:SI 6 "gpc_reg_operand" "")
8754 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8755 (set (match_operand:SI 7 "gpc_reg_operand" "")
8756 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8757 (set (match_operand:SI 8 "gpc_reg_operand" "")
8758 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8759 (set (match_operand:SI 9 "gpc_reg_operand" "")
8760 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8761 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
1fd4e8c1 8762 "*
9caa3eb2
DE		 8763{ return rs6000_output_load_multiple (operands); }"
8764 [(set_attr "type" "load")
8765 (set_attr "length" "32")])
1fd4e8c1 8766
9caa3eb2
DE		 8767(define_insn "*ldmsi7"
8768 [(match_parallel 0 "load_multiple_operation"
8769 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8770 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8771 (set (match_operand:SI 3 "gpc_reg_operand" "")
8772 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8773 (set (match_operand:SI 4 "gpc_reg_operand" "")
8774 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8775 (set (match_operand:SI 5 "gpc_reg_operand" "")
8776 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8777 (set (match_operand:SI 6 "gpc_reg_operand" "")
8778 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8779 (set (match_operand:SI 7 "gpc_reg_operand" "")
8780 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8781 (set (match_operand:SI 8 "gpc_reg_operand" "")
8782 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8783 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8784 "*
8785{ return rs6000_output_load_multiple (operands); }"
8786 [(set_attr "type" "load")
8787 (set_attr "length" "32")])
8788
8789(define_insn "*ldmsi6"
8790 [(match_parallel 0 "load_multiple_operation"
8791 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8792 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8793 (set (match_operand:SI 3 "gpc_reg_operand" "")
8794 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8795 (set (match_operand:SI 4 "gpc_reg_operand" "")
8796 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8797 (set (match_operand:SI 5 "gpc_reg_operand" "")
8798 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8799 (set (match_operand:SI 6 "gpc_reg_operand" "")
8800 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8801 (set (match_operand:SI 7 "gpc_reg_operand" "")
8802 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8803 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8804 "*
8805{ return rs6000_output_load_multiple (operands); }"
8806 [(set_attr "type" "load")
8807 (set_attr "length" "32")])
8808
8809(define_insn "*ldmsi5"
8810 [(match_parallel 0 "load_multiple_operation"
8811 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8812 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8813 (set (match_operand:SI 3 "gpc_reg_operand" "")
8814 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8815 (set (match_operand:SI 4 "gpc_reg_operand" "")
8816 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8817 (set (match_operand:SI 5 "gpc_reg_operand" "")
8818 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8819 (set (match_operand:SI 6 "gpc_reg_operand" "")
8820 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8821 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8822 "*
8823{ return rs6000_output_load_multiple (operands); }"
8824 [(set_attr "type" "load")
8825 (set_attr "length" "32")])
8826
8827(define_insn "*ldmsi4"
8828 [(match_parallel 0 "load_multiple_operation"
8829 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8830 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8831 (set (match_operand:SI 3 "gpc_reg_operand" "")
8832 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8833 (set (match_operand:SI 4 "gpc_reg_operand" "")
8834 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8835 (set (match_operand:SI 5 "gpc_reg_operand" "")
8836 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8837 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8838 "*
8839{ return rs6000_output_load_multiple (operands); }"
8840 [(set_attr "type" "load")
8841 (set_attr "length" "32")])
8842
8843(define_insn "*ldmsi3"
8844 [(match_parallel 0 "load_multiple_operation"
8845 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8846 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8847 (set (match_operand:SI 3 "gpc_reg_operand" "")
8848 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8849 (set (match_operand:SI 4 "gpc_reg_operand" "")
8850 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8851 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8852 "*
8853{ return rs6000_output_load_multiple (operands); }"
b19003d8 8854 [(set_attr "type" "load")
e82ee4cc 8855 (set_attr "length" "32")])
b19003d8 8856
1fd4e8c1 8857(define_expand "store_multiple"
2f622005
RK		 8858 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8859 (match_operand:SI 1 "" ""))
8860 (clobber (scratch:SI))
8861 (use (match_operand:SI 2 "" ""))])]
09a625f7 8862 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 8863 "
8864{
8865 int regno;
8866 int count;
8867 rtx to;
792760b9 8868 rtx op0;
1fd4e8c1
RK		 8869 int i;
8870
8871 /* Support only storing a constant number of fixed-point registers to
8872 memory and only bother with this if more than two; the machine
8873 doesn't support more than eight. */
8874 if (GET_CODE (operands[2]) != CONST_INT
8875 || INTVAL (operands[2]) <= 2
8876 || INTVAL (operands[2]) > 8
8877 || GET_CODE (operands[0]) != MEM
8878 || GET_CODE (operands[1]) != REG
8879 || REGNO (operands[1]) >= 32)
8880 FAIL;
8881
8882 count = INTVAL (operands[2]);
8883 regno = REGNO (operands[1]);
8884
39403d82 8885 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
1fd4e8c1 8886 to = force_reg (SImode, XEXP (operands[0], 0));
792760b9 8887 op0 = replace_equiv_address (operands[0], to);
1fd4e8c1
RK		 8888
8889 XVECEXP (operands[3], 0, 0)
7ef788f0 8890 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
39403d82 8891 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
c5c76735 8892 gen_rtx_SCRATCH (SImode));
1fd4e8c1
RK		 8893
8894 for (i = 1; i < count; i++)
8895 XVECEXP (operands[3], 0, i + 1)
39403d82 8896 = gen_rtx_SET (VOIDmode,
7ef788f0 8897 adjust_address_nv (op0, SImode, i * 4),
c5c76735 8898 gen_rtx_REG (SImode, regno + i));
1fd4e8c1
RK		 8899}")
8900
9caa3eb2 8901(define_insn "*store_multiple_power"
1fd4e8c1
RK		 8902 [(match_parallel 0 "store_multiple_operation"
8903 [(set (match_operand:SI 1 "indirect_operand" "=Q")
cd2b37d9 8904 (match_operand:SI 2 "gpc_reg_operand" "r"))
1fd4e8c1 8905 (clobber (match_scratch:SI 3 "=q"))])]
7e69e155 8906 "TARGET_STRING && TARGET_POWER"
b7ff3d82
DE		 8907 "{stsi|stswi} %2,%P1,%O0"
8908 [(set_attr "type" "store")])
d14a6d05 8909
e46e3130 8910(define_insn "*stmsi8"
d14a6d05 8911 [(match_parallel 0 "store_multiple_operation"
e46e3130
DJ		 8912 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8913 (match_operand:SI 2 "gpc_reg_operand" "r"))
8914 (clobber (match_scratch:SI 3 "X"))
8915 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8916 (match_operand:SI 4 "gpc_reg_operand" "r"))
8917 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8918 (match_operand:SI 5 "gpc_reg_operand" "r"))
8919 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8920 (match_operand:SI 6 "gpc_reg_operand" "r"))
8921 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8922 (match_operand:SI 7 "gpc_reg_operand" "r"))
8923 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8924 (match_operand:SI 8 "gpc_reg_operand" "r"))
8925 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8926 (match_operand:SI 9 "gpc_reg_operand" "r"))
8927 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
8928 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
8929 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
8930 "{stsi|stswi} %2,%1,%O0"
8931 [(set_attr "type" "store")])
8932
8933(define_insn "*stmsi7"
8934 [(match_parallel 0 "store_multiple_operation"
8935 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8936 (match_operand:SI 2 "gpc_reg_operand" "r"))
8937 (clobber (match_scratch:SI 3 "X"))
8938 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8939 (match_operand:SI 4 "gpc_reg_operand" "r"))
8940 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8941 (match_operand:SI 5 "gpc_reg_operand" "r"))
8942 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8943 (match_operand:SI 6 "gpc_reg_operand" "r"))
8944 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8945 (match_operand:SI 7 "gpc_reg_operand" "r"))
8946 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8947 (match_operand:SI 8 "gpc_reg_operand" "r"))
8948 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
8949 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
8950 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
8951 "{stsi|stswi} %2,%1,%O0"
8952 [(set_attr "type" "store")])
8953
8954(define_insn "*stmsi6"
8955 [(match_parallel 0 "store_multiple_operation"
8956 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8957 (match_operand:SI 2 "gpc_reg_operand" "r"))
8958 (clobber (match_scratch:SI 3 "X"))
8959 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8960 (match_operand:SI 4 "gpc_reg_operand" "r"))
8961 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8962 (match_operand:SI 5 "gpc_reg_operand" "r"))
8963 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8964 (match_operand:SI 6 "gpc_reg_operand" "r"))
8965 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8966 (match_operand:SI 7 "gpc_reg_operand" "r"))
8967 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
8968 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
8969 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
8970 "{stsi|stswi} %2,%1,%O0"
8971 [(set_attr "type" "store")])
8972
8973(define_insn "*stmsi5"
8974 [(match_parallel 0 "store_multiple_operation"
8975 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8976 (match_operand:SI 2 "gpc_reg_operand" "r"))
8977 (clobber (match_scratch:SI 3 "X"))
8978 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8979 (match_operand:SI 4 "gpc_reg_operand" "r"))
8980 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8981 (match_operand:SI 5 "gpc_reg_operand" "r"))
8982 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8983 (match_operand:SI 6 "gpc_reg_operand" "r"))
8984 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8985 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
8986 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
8987 "{stsi|stswi} %2,%1,%O0"
8988 [(set_attr "type" "store")])
8989
8990(define_insn "*stmsi4"
8991 [(match_parallel 0 "store_multiple_operation"
8992 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8993 (match_operand:SI 2 "gpc_reg_operand" "r"))
8994 (clobber (match_scratch:SI 3 "X"))
8995 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8996 (match_operand:SI 4 "gpc_reg_operand" "r"))
8997 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8998 (match_operand:SI 5 "gpc_reg_operand" "r"))
8999 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9000 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9001 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
b7ff3d82
DE		 9002 "{stsi|stswi} %2,%1,%O0"
9003 [(set_attr "type" "store")])
7e69e155 9004
e46e3130
DJ		 9005(define_insn "*stmsi3"
9006 [(match_parallel 0 "store_multiple_operation"
9007 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9008 (match_operand:SI 2 "gpc_reg_operand" "r"))
9009 (clobber (match_scratch:SI 3 "X"))
9010 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9011 (match_operand:SI 4 "gpc_reg_operand" "r"))
9012 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9013 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9014 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9015 "{stsi|stswi} %2,%1,%O0"
9016 [(set_attr "type" "store")])
7e69e155
MM		 9017\f
9018;; String/block move insn.
9019;; Argument 0 is the destination
9020;; Argument 1 is the source
9021;; Argument 2 is the length
9022;; Argument 3 is the alignment
9023
9024(define_expand "movstrsi"
b6c9286a
MM		 9025 [(parallel [(set (match_operand:BLK 0 "" "")
9026 (match_operand:BLK 1 "" ""))
9027 (use (match_operand:SI 2 "" ""))
9028 (use (match_operand:SI 3 "" ""))])]
7e69e155
MM		 9029 ""
9030 "
9031{
9032 if (expand_block_move (operands))
9033 DONE;
9034 else
9035 FAIL;
9036}")
9037
9038;; Move up to 32 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9039;; register allocator doesn't have a clue about allocating 8 word registers.
9040;; rD/rS = r5 is preferred, efficient form.
7e69e155 9041(define_expand "movstrsi_8reg"
b6c9286a
MM		 9042 [(parallel [(set (match_operand 0 "" "")
9043 (match_operand 1 "" ""))
9044 (use (match_operand 2 "" ""))
9045 (use (match_operand 3 "" ""))
7e69e155
MM		 9046 (clobber (reg:SI 5))
9047 (clobber (reg:SI 6))
9048 (clobber (reg:SI 7))
9049 (clobber (reg:SI 8))
9050 (clobber (reg:SI 9))
9051 (clobber (reg:SI 10))
9052 (clobber (reg:SI 11))
9053 (clobber (reg:SI 12))
3c67b673 9054 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9055 "TARGET_STRING"
9056 "")
9057
9058(define_insn ""
52d3af72
DE		 9059 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9060 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9061 (use (match_operand:SI 2 "immediate_operand" "i"))
9062 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9063 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9064 (clobber (reg:SI 6))
9065 (clobber (reg:SI 7))
9066 (clobber (reg:SI 8))
9067 (clobber (reg:SI 9))
9068 (clobber (reg:SI 10))
9069 (clobber (reg:SI 11))
9070 (clobber (reg:SI 12))
3c67b673 9071 (clobber (match_scratch:SI 5 "=q"))]
7e69e155 9072 "TARGET_STRING && TARGET_POWER
f9562f27
DE		 9073 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9074 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9075 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9076 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9077 && REGNO (operands[4]) == 5"
9078 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9079 [(set_attr "type" "load")
9080 (set_attr "length" "8")])
7e69e155
MM		 9081
9082(define_insn ""
52d3af72
DE		 9083 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9084 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9085 (use (match_operand:SI 2 "immediate_operand" "i"))
9086 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9087 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9088 (clobber (reg:SI 6))
9089 (clobber (reg:SI 7))
9090 (clobber (reg:SI 8))
9091 (clobber (reg:SI 9))
9092 (clobber (reg:SI 10))
9093 (clobber (reg:SI 11))
9094 (clobber (reg:SI 12))
3c67b673 9095 (clobber (match_scratch:SI 5 "X"))]
0ad91047 9096 "TARGET_STRING && ! TARGET_POWER
f9562f27
DE		 9097 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9098 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9099 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9100 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9101 && REGNO (operands[4]) == 5"
9102 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9103 [(set_attr "type" "load")
9104 (set_attr "length" "8")])
7e69e155 9105
09a625f7
TR		 9106(define_insn ""
9107 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9108 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9109 (use (match_operand:SI 2 "immediate_operand" "i"))
9110 (use (match_operand:SI 3 "immediate_operand" "i"))
9111 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9112 (clobber (reg:SI 6))
9113 (clobber (reg:SI 7))
9114 (clobber (reg:SI 8))
9115 (clobber (reg:SI 9))
9116 (clobber (reg:SI 10))
9117 (clobber (reg:SI 11))
9118 (clobber (reg:SI 12))
9119 (clobber (match_scratch:SI 5 "X"))]
9120 "TARGET_STRING && TARGET_POWERPC64
9121 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9122 || INTVAL (operands[2]) == 0)
9123 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9124 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9125 && REGNO (operands[4]) == 5"
9126 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9127 [(set_attr "type" "load")
9128 (set_attr "length" "8")])
9129
7e69e155 9130;; Move up to 24 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9131;; register allocator doesn't have a clue about allocating 6 word registers.
9132;; rD/rS = r5 is preferred, efficient form.
7e69e155 9133(define_expand "movstrsi_6reg"
b6c9286a
MM		 9134 [(parallel [(set (match_operand 0 "" "")
9135 (match_operand 1 "" ""))
9136 (use (match_operand 2 "" ""))
9137 (use (match_operand 3 "" ""))
f9562f27
DE		 9138 (clobber (reg:SI 5))
9139 (clobber (reg:SI 6))
7e69e155
MM		 9140 (clobber (reg:SI 7))
9141 (clobber (reg:SI 8))
9142 (clobber (reg:SI 9))
9143 (clobber (reg:SI 10))
3c67b673 9144 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9145 "TARGET_STRING"
9146 "")
9147
9148(define_insn ""
52d3af72
DE		 9149 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9150 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9151 (use (match_operand:SI 2 "immediate_operand" "i"))
9152 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9153 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9154 (clobber (reg:SI 6))
9155 (clobber (reg:SI 7))
7e69e155
MM		 9156 (clobber (reg:SI 8))
9157 (clobber (reg:SI 9))
9158 (clobber (reg:SI 10))
3c67b673 9159 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9160 "TARGET_STRING && TARGET_POWER
9161 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
f9562f27
DE		 9162 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9163 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9164 && REGNO (operands[4]) == 5"
3c67b673 9165 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9166 [(set_attr "type" "load")
9167 (set_attr "length" "8")])
7e69e155
MM		 9168
9169(define_insn ""
52d3af72
DE		 9170 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9171 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9172 (use (match_operand:SI 2 "immediate_operand" "i"))
9173 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9174 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9175 (clobber (reg:SI 6))
9176 (clobber (reg:SI 7))
7e69e155
MM		 9177 (clobber (reg:SI 8))
9178 (clobber (reg:SI 9))
9179 (clobber (reg:SI 10))
3c67b673 9180 (clobber (match_scratch:SI 5 "X"))]
0ad91047 9181 "TARGET_STRING && ! TARGET_POWER
7e69e155 9182 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
f9562f27
DE		 9183 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9184 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9185 && REGNO (operands[4]) == 5"
3c67b673 9186 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9187 [(set_attr "type" "load")
9188 (set_attr "length" "8")])
7e69e155 9189
09a625f7
TR		 9190(define_insn ""
9191 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9192 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9193 (use (match_operand:SI 2 "immediate_operand" "i"))
9194 (use (match_operand:SI 3 "immediate_operand" "i"))
9195 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9196 (clobber (reg:SI 6))
9197 (clobber (reg:SI 7))
9198 (clobber (reg:SI 8))
9199 (clobber (reg:SI 9))
9200 (clobber (reg:SI 10))
9201 (clobber (match_scratch:SI 5 "X"))]
9202 "TARGET_STRING && TARGET_POWERPC64
9203 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9204 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9205 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9206 && REGNO (operands[4]) == 5"
9207 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9208 [(set_attr "type" "load")
9209 (set_attr "length" "8")])
9210
f9562f27
DE		 9211;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9212;; problems with TImode.
9213;; rD/rS = r5 is preferred, efficient form.
7e69e155 9214(define_expand "movstrsi_4reg"
b6c9286a
MM		 9215 [(parallel [(set (match_operand 0 "" "")
9216 (match_operand 1 "" ""))
9217 (use (match_operand 2 "" ""))
9218 (use (match_operand 3 "" ""))
f9562f27
DE		 9219 (clobber (reg:SI 5))
9220 (clobber (reg:SI 6))
9221 (clobber (reg:SI 7))
9222 (clobber (reg:SI 8))
3c67b673 9223 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9224 "TARGET_STRING"
9225 "")
9226
9227(define_insn ""
52d3af72
DE		 9228 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9229 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9230 (use (match_operand:SI 2 "immediate_operand" "i"))
9231 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9232 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9233 (clobber (reg:SI 6))
9234 (clobber (reg:SI 7))
9235 (clobber (reg:SI 8))
3c67b673 9236 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9237 "TARGET_STRING && TARGET_POWER
9238 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9239 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9240 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9241 && REGNO (operands[4]) == 5"
3c67b673 9242 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9243 [(set_attr "type" "load")
9244 (set_attr "length" "8")])
7e69e155
MM		 9245
9246(define_insn ""
52d3af72
DE		 9247 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9248 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9249 (use (match_operand:SI 2 "immediate_operand" "i"))
9250 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9251 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9252 (clobber (reg:SI 6))
9253 (clobber (reg:SI 7))
9254 (clobber (reg:SI 8))
3c67b673 9255 (clobber (match_scratch:SI 5 "X"))]
0ad91047 9256 "TARGET_STRING && ! TARGET_POWER
7e69e155 9257 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9258 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9259 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9260 && REGNO (operands[4]) == 5"
3c67b673 9261 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9262 [(set_attr "type" "load")
9263 (set_attr "length" "8")])
7e69e155 9264
09a625f7
TR		 9265(define_insn ""
9266 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9267 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9268 (use (match_operand:SI 2 "immediate_operand" "i"))
9269 (use (match_operand:SI 3 "immediate_operand" "i"))
9270 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9271 (clobber (reg:SI 6))
9272 (clobber (reg:SI 7))
9273 (clobber (reg:SI 8))
9274 (clobber (match_scratch:SI 5 "X"))]
9275 "TARGET_STRING && TARGET_POWERPC64
9276 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9277 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9278 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9279 && REGNO (operands[4]) == 5"
9280 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9281 [(set_attr "type" "load")
9282 (set_attr "length" "8")])
9283
7e69e155
MM		 9284;; Move up to 8 bytes at a time.
9285(define_expand "movstrsi_2reg"
b6c9286a
MM		 9286 [(parallel [(set (match_operand 0 "" "")
9287 (match_operand 1 "" ""))
9288 (use (match_operand 2 "" ""))
9289 (use (match_operand 3 "" ""))
3c67b673
RK		 9290 (clobber (match_scratch:DI 4 ""))
9291 (clobber (match_scratch:SI 5 ""))])]
f9562f27 9292 "TARGET_STRING && ! TARGET_POWERPC64"
7e69e155
MM		 9293 "")
9294
9295(define_insn ""
52d3af72
DE		 9296 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9297 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9298 (use (match_operand:SI 2 "immediate_operand" "i"))
9299 (use (match_operand:SI 3 "immediate_operand" "i"))
9300 (clobber (match_scratch:DI 4 "=&r"))
9301 (clobber (match_scratch:SI 5 "=q"))]
f9562f27 9302 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
3c67b673
RK		 9303 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9304 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9305 [(set_attr "type" "load")
9306 (set_attr "length" "8")])
7e69e155
MM		 9307
9308(define_insn ""
52d3af72
DE		 9309 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9310 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9311 (use (match_operand:SI 2 "immediate_operand" "i"))
9312 (use (match_operand:SI 3 "immediate_operand" "i"))
9313 (clobber (match_scratch:DI 4 "=&r"))
9314 (clobber (match_scratch:SI 5 "X"))]
f9562f27 9315 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
7e69e155 9316 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
3c67b673 9317 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9318 [(set_attr "type" "load")
9319 (set_attr "length" "8")])
7e69e155
MM		 9320
9321;; Move up to 4 bytes at a time.
9322(define_expand "movstrsi_1reg"
b6c9286a
MM		 9323 [(parallel [(set (match_operand 0 "" "")
9324 (match_operand 1 "" ""))
9325 (use (match_operand 2 "" ""))
9326 (use (match_operand 3 "" ""))
3c67b673
RK		 9327 (clobber (match_scratch:SI 4 ""))
9328 (clobber (match_scratch:SI 5 ""))])]
7e69e155
MM		 9329 "TARGET_STRING"
9330 "")
9331
9332(define_insn ""
52d3af72
DE		 9333 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9334 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9335 (use (match_operand:SI 2 "immediate_operand" "i"))
9336 (use (match_operand:SI 3 "immediate_operand" "i"))
9337 (clobber (match_scratch:SI 4 "=&r"))
9338 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9339 "TARGET_STRING && TARGET_POWER
9340 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
3c67b673 9341 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9342 [(set_attr "type" "load")
9343 (set_attr "length" "8")])
7e69e155
MM		 9344
9345(define_insn ""
52d3af72
DE		 9346 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9347 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9348 (use (match_operand:SI 2 "immediate_operand" "i"))
9349 (use (match_operand:SI 3 "immediate_operand" "i"))
9350 (clobber (match_scratch:SI 4 "=&r"))
9351 (clobber (match_scratch:SI 5 "X"))]
0ad91047 9352 "TARGET_STRING && ! TARGET_POWER
7e69e155 9353 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
09a625f7
TR		 9354 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9355 [(set_attr "type" "load")
9356 (set_attr "length" "8")])
9357
9358(define_insn ""
9359 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9360 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9361 (use (match_operand:SI 2 "immediate_operand" "i"))
9362 (use (match_operand:SI 3 "immediate_operand" "i"))
9363 (clobber (match_scratch:SI 4 "=&r"))
9364 (clobber (match_scratch:SI 5 "X"))]
9365 "TARGET_STRING && TARGET_POWERPC64
9366 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
3c67b673 9367 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
b7ff3d82
DE		 9368 [(set_attr "type" "load")
9369 (set_attr "length" "8")])
7e69e155 9370
1fd4e8c1 9371\f
7e69e155 9372;; Define insns that do load or store with update. Some of these we can
1fd4e8c1
RK		 9373;; get by using pre-decrement or pre-increment, but the hardware can also
9374;; do cases where the increment is not the size of the object.
9375;;
9376;; In all these cases, we use operands 0 and 1 for the register being
9377;; incremented because those are the operands that local-alloc will
9378;; tie and these are the pair most likely to be tieable (and the ones
9379;; that will benefit the most).
9380
38c1f2d7 9381(define_insn "*movdi_update1"
51b8fc2c 9382 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
ad8bd902 9383 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
768070a0 9384 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
51b8fc2c
RK		 9385 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9386 (plus:DI (match_dup 1) (match_dup 2)))]
38c1f2d7 9387 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9388 "@
9389 ldux %3,%0,%2
9390 ldu %3,%2(%0)"
b54cf83a 9391 [(set_attr "type" "load_ux,load_u")])
287f13ff 9392
4697a36c 9393(define_insn "movdi_update"
51b8fc2c 9394 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
768070a0 9395 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
51b8fc2c
RK		 9396 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9397 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9398 (plus:DI (match_dup 1) (match_dup 2)))]
38c1f2d7 9399 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9400 "@
9401 stdux %3,%0,%2
b7ff3d82 9402 stdu %3,%2(%0)"
b54cf83a 9403 [(set_attr "type" "store_ux,store_u")])
51b8fc2c 9404
38c1f2d7 9405(define_insn "*movsi_update1"
cd2b37d9
RK		 9406 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9407 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9408 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9409 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9410 (plus:SI (match_dup 1) (match_dup 2)))]
f7b3ab8a 9411 "TARGET_UPDATE"
1fd4e8c1 9412 "@
ca7f5001
RK		 9413 {lux|lwzux} %3,%0,%2
9414 {lu|lwzu} %3,%2(%0)"
b54cf83a
DE		 9415 [(set_attr "type" "load_ux,load_u")])
9416
9417(define_insn "*movsi_update2"
9418 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9419 (sign_extend:DI
9420 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9421 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9422 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9423 (plus:DI (match_dup 1) (match_dup 2)))]
9424 "TARGET_POWERPC64"
9425 "lwaux %3,%0,%2"
9426 [(set_attr "type" "load_ext_ux")])
1fd4e8c1 9427
4697a36c 9428(define_insn "movsi_update"
cd2b37d9 9429 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9430 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9431 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9432 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9433 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9434 "TARGET_UPDATE"
1fd4e8c1 9435 "@
ca7f5001 9436 {stux|stwux} %3,%0,%2
b7ff3d82 9437 {stu|stwu} %3,%2(%0)"
b54cf83a 9438 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9439
b54cf83a 9440(define_insn "*movhi_update1"
cd2b37d9
RK		 9441 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9442 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9443 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9444 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9445 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9446 "TARGET_UPDATE"
1fd4e8c1 9447 "@
5f243543
RK		 9448 lhzux %3,%0,%2
9449 lhzu %3,%2(%0)"
b54cf83a 9450 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9451
38c1f2d7 9452(define_insn "*movhi_update2"
cd2b37d9 9453 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9454 (zero_extend:SI
cd2b37d9 9455 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9456 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9457 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9458 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9459 "TARGET_UPDATE"
1fd4e8c1 9460 "@
5f243543
RK		 9461 lhzux %3,%0,%2
9462 lhzu %3,%2(%0)"
b54cf83a 9463 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9464
38c1f2d7 9465(define_insn "*movhi_update3"
cd2b37d9 9466 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9467 (sign_extend:SI
cd2b37d9 9468 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9469 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9470 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9471 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9472 "TARGET_UPDATE"
1fd4e8c1 9473 "@
5f243543
RK		 9474 lhaux %3,%0,%2
9475 lhau %3,%2(%0)"
b54cf83a 9476 [(set_attr "type" "load_ext_ux,load_ext_u")])
1fd4e8c1 9477
38c1f2d7 9478(define_insn "*movhi_update4"
cd2b37d9 9479 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9480 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9481 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9482 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9483 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9484 "TARGET_UPDATE"
1fd4e8c1 9485 "@
5f243543 9486 sthux %3,%0,%2
b7ff3d82 9487 sthu %3,%2(%0)"
b54cf83a 9488 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9489
38c1f2d7 9490(define_insn "*movqi_update1"
cd2b37d9
RK		 9491 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9492 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9493 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9494 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9495 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9496 "TARGET_UPDATE"
1fd4e8c1 9497 "@
5f243543
RK		 9498 lbzux %3,%0,%2
9499 lbzu %3,%2(%0)"
b54cf83a 9500 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9501
38c1f2d7 9502(define_insn "*movqi_update2"
cd2b37d9 9503 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9504 (zero_extend:SI
cd2b37d9 9505 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9506 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9507 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9508 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9509 "TARGET_UPDATE"
1fd4e8c1 9510 "@
5f243543
RK		 9511 lbzux %3,%0,%2
9512 lbzu %3,%2(%0)"
b54cf83a 9513 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9514
38c1f2d7 9515(define_insn "*movqi_update3"
cd2b37d9 9516 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9517 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9518 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9519 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9520 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9521 "TARGET_UPDATE"
1fd4e8c1 9522 "@
5f243543 9523 stbux %3,%0,%2
b7ff3d82 9524 stbu %3,%2(%0)"
b54cf83a 9525 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9526
38c1f2d7 9527(define_insn "*movsf_update1"
cd2b37d9 9528 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
df8b713c 9529 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9530 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9531 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9532 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9533 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 9534 "@
5f243543
RK		 9535 lfsux %3,%0,%2
9536 lfsu %3,%2(%0)"
b54cf83a 9537 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 9538
38c1f2d7 9539(define_insn "*movsf_update2"
cd2b37d9 9540 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9541 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9542 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9543 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9544 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9545 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 9546 "@
85fff2f3 9547 stfsux %3,%0,%2
b7ff3d82 9548 stfsu %3,%2(%0)"
b54cf83a 9549 [(set_attr "type" "fpstore_ux,fpstore_u")])
1fd4e8c1 9550
38c1f2d7
MM		 9551(define_insn "*movsf_update3"
9552 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9553 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9554 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9555 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9556 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9557 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 9558 "@
9559 {lux|lwzux} %3,%0,%2
9560 {lu|lwzu} %3,%2(%0)"
b54cf83a 9561 [(set_attr "type" "load_ux,load_u")])
38c1f2d7
MM		 9562
9563(define_insn "*movsf_update4"
9564 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9565 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9566 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9567 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9568 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9569 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 9570 "@
9571 {stux|stwux} %3,%0,%2
9572 {stu|stwu} %3,%2(%0)"
b54cf83a 9573 [(set_attr "type" "store_ux,store_u")])
38c1f2d7
MM		 9574
9575(define_insn "*movdf_update1"
cd2b37d9
RK		 9576 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9577 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9578 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9579 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9580 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9581 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 9582 "@
5f243543
RK		 9583 lfdux %3,%0,%2
9584 lfdu %3,%2(%0)"
b54cf83a 9585 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 9586
38c1f2d7 9587(define_insn "*movdf_update2"
cd2b37d9 9588 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9589 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9590 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9591 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9592 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 9593 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 9594 "@
5f243543 9595 stfdux %3,%0,%2
b7ff3d82 9596 stfdu %3,%2(%0)"
b54cf83a 9597 [(set_attr "type" "fpstore_ux,fpstore_u")])
4c70a4f3
RK		 9598
9599;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9600
9601(define_peephole
9602 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
9603 (match_operand:DF 1 "memory_operand" ""))
9604 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
9605 (match_operand:DF 3 "memory_operand" ""))]
9606 "TARGET_POWER2
a3170dc6 9607 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3
RK		 9608 && registers_ok_for_quad_peep (operands[0], operands[2])
9609 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
9610 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
9611 "lfq%U1%X1 %0,%1")
9612
9613(define_peephole
9614 [(set (match_operand:DF 0 "memory_operand" "")
9615 (match_operand:DF 1 "gpc_reg_operand" "f"))
9616 (set (match_operand:DF 2 "memory_operand" "")
9617 (match_operand:DF 3 "gpc_reg_operand" "f"))]
9618 "TARGET_POWER2
a3170dc6 9619 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3
RK		 9620 && registers_ok_for_quad_peep (operands[1], operands[3])
9621 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
9622 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
9623 "stfq%U0%X0 %1,%0")
1fd4e8c1 9624\f
c4501e62
JJ		 9625;; TLS support.
9626
9627;; "b" output constraint here and on tls_ld to support tls linker optimization.
9628(define_insn "tls_gd_32"
9629 [(set (match_operand:SI 0 "register_operand" "=b")
9630 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9631 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9632 UNSPEC_TLSGD))]
9633 "HAVE_AS_TLS && !TARGET_64BIT"
9634 "addi %0,%1,%2@got@tlsgd")
9635
9636(define_insn "tls_gd_64"
9637 [(set (match_operand:DI 0 "register_operand" "=b")
9638 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9639 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9640 UNSPEC_TLSGD))]
9641 "HAVE_AS_TLS && TARGET_64BIT"
9642 "addi %0,%1,%2@got@tlsgd")
9643
9644(define_insn "tls_ld_32"
9645 [(set (match_operand:SI 0 "register_operand" "=b")
9646 (unspec:SI [(match_operand:SI 1 "register_operand" "b")]
9647 UNSPEC_TLSLD))]
9648 "HAVE_AS_TLS && !TARGET_64BIT"
9649 "addi %0,%1,%&@got@tlsld")
9650
9651(define_insn "tls_ld_64"
9652 [(set (match_operand:DI 0 "register_operand" "=b")
9653 (unspec:DI [(match_operand:DI 1 "register_operand" "b")]
9654 UNSPEC_TLSLD))]
9655 "HAVE_AS_TLS && TARGET_64BIT"
9656 "addi %0,%1,%&@got@tlsld")
9657
9658(define_insn "tls_dtprel_32"
9659 [(set (match_operand:SI 0 "register_operand" "=r")
9660 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9661 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9662 UNSPEC_TLSDTPREL))]
9663 "HAVE_AS_TLS && !TARGET_64BIT"
9664 "addi %0,%1,%2@dtprel")
9665
9666(define_insn "tls_dtprel_64"
9667 [(set (match_operand:DI 0 "register_operand" "=r")
9668 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9669 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9670 UNSPEC_TLSDTPREL))]
9671 "HAVE_AS_TLS && TARGET_64BIT"
9672 "addi %0,%1,%2@dtprel")
9673
9674(define_insn "tls_dtprel_ha_32"
9675 [(set (match_operand:SI 0 "register_operand" "=r")
9676 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9677 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9678 UNSPEC_TLSDTPRELHA))]
9679 "HAVE_AS_TLS && !TARGET_64BIT"
9680 "addis %0,%1,%2@dtprel@ha")
9681
9682(define_insn "tls_dtprel_ha_64"
9683 [(set (match_operand:DI 0 "register_operand" "=r")
9684 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9685 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9686 UNSPEC_TLSDTPRELHA))]
9687 "HAVE_AS_TLS && TARGET_64BIT"
9688 "addis %0,%1,%2@dtprel@ha")
9689
9690(define_insn "tls_dtprel_lo_32"
9691 [(set (match_operand:SI 0 "register_operand" "=r")
9692 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9693 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9694 UNSPEC_TLSDTPRELLO))]
9695 "HAVE_AS_TLS && !TARGET_64BIT"
9696 "addi %0,%1,%2@dtprel@l")
9697
9698(define_insn "tls_dtprel_lo_64"
9699 [(set (match_operand:DI 0 "register_operand" "=r")
9700 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9701 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9702 UNSPEC_TLSDTPRELLO))]
9703 "HAVE_AS_TLS && TARGET_64BIT"
9704 "addi %0,%1,%2@dtprel@l")
9705
9706(define_insn "tls_got_dtprel_32"
9707 [(set (match_operand:SI 0 "register_operand" "=r")
9708 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9709 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9710 UNSPEC_TLSGOTDTPREL))]
9711 "HAVE_AS_TLS && !TARGET_64BIT"
9712 "lwz %0,%2@got@dtprel(%1)")
9713
9714(define_insn "tls_got_dtprel_64"
9715 [(set (match_operand:DI 0 "register_operand" "=r")
9716 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9717 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9718 UNSPEC_TLSGOTDTPREL))]
9719 "HAVE_AS_TLS && TARGET_64BIT"
9720 "ld %0,%2@got@dtprel(%1)")
9721
9722(define_insn "tls_tprel_32"
9723 [(set (match_operand:SI 0 "register_operand" "=r")
9724 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9725 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9726 UNSPEC_TLSTPREL))]
9727 "HAVE_AS_TLS && !TARGET_64BIT"
9728 "addi %0,%1,%2@tprel")
9729
9730(define_insn "tls_tprel_64"
9731 [(set (match_operand:DI 0 "register_operand" "=r")
9732 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9733 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9734 UNSPEC_TLSTPREL))]
9735 "HAVE_AS_TLS && TARGET_64BIT"
9736 "addi %0,%1,%2@tprel")
9737
9738(define_insn "tls_tprel_ha_32"
9739 [(set (match_operand:SI 0 "register_operand" "=r")
9740 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9741 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9742 UNSPEC_TLSTPRELHA))]
9743 "HAVE_AS_TLS && !TARGET_64BIT"
9744 "addis %0,%1,%2@tprel@ha")
9745
9746(define_insn "tls_tprel_ha_64"
9747 [(set (match_operand:DI 0 "register_operand" "=r")
9748 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9749 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9750 UNSPEC_TLSTPRELHA))]
9751 "HAVE_AS_TLS && TARGET_64BIT"
9752 "addis %0,%1,%2@tprel@ha")
9753
9754(define_insn "tls_tprel_lo_32"
9755 [(set (match_operand:SI 0 "register_operand" "=r")
9756 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9757 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9758 UNSPEC_TLSTPRELLO))]
9759 "HAVE_AS_TLS && !TARGET_64BIT"
9760 "addi %0,%1,%2@tprel@l")
9761
9762(define_insn "tls_tprel_lo_64"
9763 [(set (match_operand:DI 0 "register_operand" "=r")
9764 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9765 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9766 UNSPEC_TLSTPRELLO))]
9767 "HAVE_AS_TLS && TARGET_64BIT"
9768 "addi %0,%1,%2@tprel@l")
9769
c1207243 9770;; "b" output constraint here and on tls_tls input to support linker tls
c4501e62
JJ		 9771;; optimization. The linker may edit the instructions emitted by a
9772;; tls_got_tprel/tls_tls pair to addis,addi.
9773(define_insn "tls_got_tprel_32"
9774 [(set (match_operand:SI 0 "register_operand" "=b")
9775 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9776 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9777 UNSPEC_TLSGOTTPREL))]
9778 "HAVE_AS_TLS && !TARGET_64BIT"
9779 "lwz %0,%2@got@tprel(%1)")
9780
9781(define_insn "tls_got_tprel_64"
9782 [(set (match_operand:DI 0 "register_operand" "=b")
9783 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9784 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9785 UNSPEC_TLSGOTTPREL))]
9786 "HAVE_AS_TLS && TARGET_64BIT"
9787 "ld %0,%2@got@tprel(%1)")
9788
9789(define_insn "tls_tls_32"
9790 [(set (match_operand:SI 0 "register_operand" "=r")
9791 (unspec:SI [(match_operand:SI 1 "register_operand" "b")
9792 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9793 UNSPEC_TLSTLS))]
9794 "HAVE_AS_TLS && !TARGET_64BIT"
9795 "add %0,%1,%2@tls")
9796
9797(define_insn "tls_tls_64"
9798 [(set (match_operand:DI 0 "register_operand" "=r")
9799 (unspec:DI [(match_operand:DI 1 "register_operand" "b")
9800 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9801 UNSPEC_TLSTLS))]
9802 "HAVE_AS_TLS && TARGET_64BIT"
9803 "add %0,%1,%2@tls")
9804\f
1fd4e8c1
RK		 9805;; Next come insns related to the calling sequence.
9806;;
9807;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
7e69e155 9808;; We move the back-chain and decrement the stack pointer.
1fd4e8c1
RK		 9809
9810(define_expand "allocate_stack"
52d3af72 9811 [(set (match_operand 0 "gpc_reg_operand" "=r")
a260abc9
DE		 9812 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9813 (set (reg 1)
9814 (minus (reg 1) (match_dup 1)))]
1fd4e8c1
RK		 9815 ""
9816 "
4697a36c 9817{ rtx chain = gen_reg_rtx (Pmode);
39403d82 9818 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
4697a36c 9819 rtx neg_op0;
1fd4e8c1
RK		 9820
9821 emit_move_insn (chain, stack_bot);
4697a36c 9822
a157febd
GK		 9823 /* Check stack bounds if necessary. */
9824 if (current_function_limit_stack)
9825 {
9826 rtx available;
9827 available = expand_binop (Pmode, sub_optab,
9828 stack_pointer_rtx, stack_limit_rtx,
9829 NULL_RTX, 1, OPTAB_WIDEN);
9830 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9831 }
9832
e9a25f70
JL		 9833 if (GET_CODE (operands[1]) != CONST_INT
9834 || INTVAL (operands[1]) < -32767
9835 || INTVAL (operands[1]) > 32768)
4697a36c
MM		 9836 {
9837 neg_op0 = gen_reg_rtx (Pmode);
e6ca2c17 9838 if (TARGET_32BIT)
e9a25f70 9839 emit_insn (gen_negsi2 (neg_op0, operands[1]));
e6ca2c17 9840 else
e9a25f70 9841 emit_insn (gen_negdi2 (neg_op0, operands[1]));
4697a36c
MM		 9842 }
9843 else
e9a25f70 9844 neg_op0 = GEN_INT (- INTVAL (operands[1]));
4697a36c 9845
38c1f2d7
MM		 9846 if (TARGET_UPDATE)
9847 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
9848 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
4697a36c 9849
38c1f2d7
MM		 9850 else
9851 {
9852 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
9853 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
39403d82 9854 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
38c1f2d7 9855 }
e9a25f70
JL		 9856
9857 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
1fd4e8c1
RK		 9858 DONE;
9859}")
59257ff7
RK		 9860
9861;; These patterns say how to save and restore the stack pointer. We need not
9862;; save the stack pointer at function level since we are careful to
9863;; preserve the backchain. At block level, we have to restore the backchain
9864;; when we restore the stack pointer.
9865;;
9866;; For nonlocal gotos, we must save both the stack pointer and its
9867;; backchain and restore both. Note that in the nonlocal case, the
9868;; save area is a memory location.
9869
9870(define_expand "save_stack_function"
ff381587
MM		 9871 [(match_operand 0 "any_operand" "")
9872 (match_operand 1 "any_operand" "")]
59257ff7 9873 ""
ff381587 9874 "DONE;")
59257ff7
RK		 9875
9876(define_expand "restore_stack_function"
ff381587
MM		 9877 [(match_operand 0 "any_operand" "")
9878 (match_operand 1 "any_operand" "")]
59257ff7 9879 ""
ff381587 9880 "DONE;")
59257ff7
RK		 9881
9882(define_expand "restore_stack_block"
dfdfa60f
DE		 9883 [(use (match_operand 0 "register_operand" ""))
9884 (set (match_dup 2) (match_dup 3))
a260abc9 9885 (set (match_dup 0) (match_operand 1 "register_operand" ""))
dfdfa60f 9886 (set (match_dup 3) (match_dup 2))]
59257ff7
RK		 9887 ""
9888 "
dfdfa60f
DE		 9889{
9890 operands[2] = gen_reg_rtx (Pmode);
39403d82 9891 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
dfdfa60f 9892}")
59257ff7
RK		 9893
9894(define_expand "save_stack_nonlocal"
a260abc9
DE		 9895 [(match_operand 0 "memory_operand" "")
9896 (match_operand 1 "register_operand" "")]
59257ff7
RK		 9897 ""
9898 "
9899{
a260abc9 9900 rtx temp = gen_reg_rtx (Pmode);
11b25716 9901 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 9902
9903 /* Copy the backchain to the first word, sp to the second. */
39403d82 9904 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
39e453d7
DE		 9905 emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp);
9906 emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word),
a260abc9 9907 operands[1]);
59257ff7
RK		 9908 DONE;
9909}")
7e69e155 9910
59257ff7 9911(define_expand "restore_stack_nonlocal"
a260abc9
DE		 9912 [(match_operand 0 "register_operand" "")
9913 (match_operand 1 "memory_operand" "")]
59257ff7
RK		 9914 ""
9915 "
9916{
a260abc9 9917 rtx temp = gen_reg_rtx (Pmode);
11b25716 9918 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 9919
9920 /* Restore the backchain from the first word, sp from the second. */
a260abc9 9921 emit_move_insn (temp,
39e453d7 9922 adjust_address_nv (operands[1], Pmode, 0));
a260abc9 9923 emit_move_insn (operands[0],
39e453d7 9924 adjust_address_nv (operands[1], Pmode, units_per_word));
39403d82 9925 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
59257ff7
RK		 9926 DONE;
9927}")
9ebbca7d
GK		 9928\f
9929;; TOC register handling.
b6c9286a 9930
9ebbca7d 9931;; Code to initialize the TOC register...
f0f6a223 9932
9ebbca7d 9933(define_insn "load_toc_aix_si"
e72247f4 9934 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 9935 (unspec:SI [(const_int 0)] UNSPEC_TOC))
46aaf10d 9936 (use (reg:SI 2))])]
2bfcf297 9937 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
f0f6a223
RK		 9938 "*
9939{
9ebbca7d
GK		 9940 char buf[30];
9941 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
a8a05998 9942 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 9943 operands[2] = gen_rtx_REG (Pmode, 2);
9944 return \"{l|lwz} %0,%1(%2)\";
f0f6a223
RK		 9945}"
9946 [(set_attr "type" "load")])
9ebbca7d
GK		 9947
9948(define_insn "load_toc_aix_di"
e72247f4 9949 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
615158e2 9950 (unspec:DI [(const_int 0)] UNSPEC_TOC))
46aaf10d 9951 (use (reg:DI 2))])]
2bfcf297 9952 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9ebbca7d
GK		 9953 "*
9954{
9955 char buf[30];
f585a356
DE		 9956#ifdef TARGET_RELOCATABLE
9957 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
9958 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
9959#else
9ebbca7d 9960 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
f585a356 9961#endif
2bfcf297
DB		 9962 if (TARGET_ELF)
9963 strcat (buf, \"@toc\");
a8a05998 9964 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 9965 operands[2] = gen_rtx_REG (Pmode, 2);
9966 return \"ld %0,%1(%2)\";
9967}"
9968 [(set_attr "type" "load")])
9969
9970(define_insn "load_toc_v4_pic_si"
9971 [(set (match_operand:SI 0 "register_operand" "=l")
615158e2 9972 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
f607bc57 9973 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9ebbca7d
GK		 9974 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9975 [(set_attr "type" "branch")
9976 (set_attr "length" "4")])
9977
9ebbca7d
GK		 9978(define_insn "load_toc_v4_PIC_1"
9979 [(set (match_operand:SI 0 "register_operand" "=l")
9980 (match_operand:SI 1 "immediate_operand" "s"))
c4501e62 9981 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
20b71b17 9982 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
df7a8989 9983 "bcl 20,31,%1\\n%1:"
9ebbca7d
GK		 9984 [(set_attr "type" "branch")
9985 (set_attr "length" "4")])
9986
9987(define_insn "load_toc_v4_PIC_1b"
9988 [(set (match_operand:SI 0 "register_operand" "=l")
9989 (match_operand:SI 1 "immediate_operand" "s"))
c4501e62
JJ		 9990 (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")]
9991 UNSPEC_TOCPTR))]
20b71b17 9992 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
c4501e62 9993 "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1"
9ebbca7d
GK		 9994 [(set_attr "type" "branch")
9995 (set_attr "length" "8")])
9996
9997(define_insn "load_toc_v4_PIC_2"
f585a356 9998 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
a2900460 9999 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9ebbca7d
GK		 10000 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10001 (match_operand:SI 3 "immediate_operand" "s")))))]
20b71b17 10002 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9ebbca7d
GK		 10003 "{l|lwz} %0,%2-%3(%1)"
10004 [(set_attr "type" "load")])
10005
ee890fe2
SS		 10006(define_insn "load_macho_picbase"
10007 [(set (match_operand:SI 0 "register_operand" "=l")
615158e2
JJ		 10008 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10009 UNSPEC_LD_MPIC))]
ee890fe2 10010 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
f51eee6a 10011 "bcl 20,31,%1\\n%1:"
ee890fe2
SS		 10012 [(set_attr "type" "branch")
10013 (set_attr "length" "4")])
10014
f51eee6a
GK		 10015(define_insn "macho_correct_pic"
10016 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8291cc0e 10017 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
f51eee6a
GK		 10018 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
10019 (match_operand:SI 3 "immediate_operand" "s")]
615158e2 10020 UNSPEC_MPIC_CORRECT)))]
f51eee6a 10021 "DEFAULT_ABI == ABI_DARWIN"
8291cc0e 10022 "addis %0,%1,ha16(%2-%3)\n\taddi %0,%0,lo16(%2-%3)"
f51eee6a
GK		 10023 [(set_attr "length" "8")])
10024
9ebbca7d
GK		 10025;; If the TOC is shared over a translation unit, as happens with all
10026;; the kinds of PIC that we support, we need to restore the TOC
10027;; pointer only when jumping over units of translation.
f51eee6a 10028;; On Darwin, we need to reload the picbase.
9ebbca7d
GK		 10029
10030(define_expand "builtin_setjmp_receiver"
10031 [(use (label_ref (match_operand 0 "" "")))]
f607bc57 10032 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
f51eee6a
GK		 10033 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10034 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9ebbca7d
GK		 10035 "
10036{
84d7dd4a 10037#if TARGET_MACHO
f51eee6a
GK		 10038 if (DEFAULT_ABI == ABI_DARWIN)
10039 {
d24652ee 10040 const char *picbase = machopic_function_base_name ();
485bad26 10041 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
f51eee6a
GK		 10042 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10043 rtx tmplabrtx;
10044 char tmplab[20];
10045
10046 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10047 CODE_LABEL_NUMBER (operands[0]));
485bad26 10048 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
f51eee6a
GK		 10049
10050 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10051 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10052 }
10053 else
84d7dd4a 10054#endif
f51eee6a 10055 rs6000_emit_load_toc_table (FALSE);
9ebbca7d
GK		 10056 DONE;
10057}")
10058\f
10059;; A function pointer under AIX is a pointer to a data area whose first word
10060;; contains the actual address of the function, whose second word contains a
b6c9286a
MM		 10061;; pointer to its TOC, and whose third word contains a value to place in the
10062;; static chain register (r11). Note that if we load the static chain, our
1fd4e8c1 10063;; "trampoline" need not have any executable code.
b6c9286a 10064
cccf3bdc
DE		 10065(define_expand "call_indirect_aix32"
10066 [(set (match_dup 2)
10067 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10068 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10069 (reg:SI 2))
10070 (set (reg:SI 2)
10071 (mem:SI (plus:SI (match_dup 0)
10072 (const_int 4))))
10073 (set (reg:SI 11)
10074 (mem:SI (plus:SI (match_dup 0)
10075 (const_int 8))))
10076 (parallel [(call (mem:SI (match_dup 2))
10077 (match_operand 1 "" ""))
10078 (use (reg:SI 2))
10079 (use (reg:SI 11))
10080 (set (reg:SI 2)
10081 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10082 (clobber (scratch:SI))])]
10083 "TARGET_32BIT"
10084 "
10085{ operands[2] = gen_reg_rtx (SImode); }")
b6c9286a 10086
cccf3bdc
DE		 10087(define_expand "call_indirect_aix64"
10088 [(set (match_dup 2)
10089 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10090 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10091 (reg:DI 2))
10092 (set (reg:DI 2)
10093 (mem:DI (plus:DI (match_dup 0)
10094 (const_int 8))))
10095 (set (reg:DI 11)
10096 (mem:DI (plus:DI (match_dup 0)
10097 (const_int 16))))
10098 (parallel [(call (mem:SI (match_dup 2))
10099 (match_operand 1 "" ""))
10100 (use (reg:DI 2))
10101 (use (reg:DI 11))
10102 (set (reg:DI 2)
10103 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10104 (clobber (scratch:SI))])]
10105 "TARGET_64BIT"
10106 "
10107{ operands[2] = gen_reg_rtx (DImode); }")
b6c9286a 10108
cccf3bdc
DE		 10109(define_expand "call_value_indirect_aix32"
10110 [(set (match_dup 3)
10111 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10112 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10113 (reg:SI 2))
10114 (set (reg:SI 2)
10115 (mem:SI (plus:SI (match_dup 1)
10116 (const_int 4))))
10117 (set (reg:SI 11)
10118 (mem:SI (plus:SI (match_dup 1)
10119 (const_int 8))))
10120 (parallel [(set (match_operand 0 "" "")
10121 (call (mem:SI (match_dup 3))
10122 (match_operand 2 "" "")))
10123 (use (reg:SI 2))
10124 (use (reg:SI 11))
10125 (set (reg:SI 2)
10126 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10127 (clobber (scratch:SI))])]
10128 "TARGET_32BIT"
10129 "
10130{ operands[3] = gen_reg_rtx (SImode); }")
b6c9286a 10131
cccf3bdc
DE		 10132(define_expand "call_value_indirect_aix64"
10133 [(set (match_dup 3)
10134 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10135 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10136 (reg:DI 2))
10137 (set (reg:DI 2)
10138 (mem:DI (plus:DI (match_dup 1)
10139 (const_int 8))))
10140 (set (reg:DI 11)
10141 (mem:DI (plus:DI (match_dup 1)
10142 (const_int 16))))
10143 (parallel [(set (match_operand 0 "" "")
10144 (call (mem:SI (match_dup 3))
10145 (match_operand 2 "" "")))
10146 (use (reg:DI 2))
10147 (use (reg:DI 11))
10148 (set (reg:DI 2)
10149 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10150 (clobber (scratch:SI))])]
10151 "TARGET_64BIT"
10152 "
10153{ operands[3] = gen_reg_rtx (DImode); }")
1fd4e8c1 10154
b6c9286a 10155;; Now the definitions for the call and call_value insns
1fd4e8c1 10156(define_expand "call"
a260abc9 10157 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
1fd4e8c1 10158 (match_operand 1 "" ""))
4697a36c 10159 (use (match_operand 2 "" ""))
1fd4e8c1
RK		 10160 (clobber (scratch:SI))])]
10161 ""
10162 "
10163{
ee890fe2 10164#if TARGET_MACHO
ab82a49f 10165 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10166 operands[0] = machopic_indirect_call_target (operands[0]);
10167#endif
10168
1fd4e8c1
RK		 10169 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10170 abort ();
10171
10172 operands[0] = XEXP (operands[0], 0);
7509c759 10173
6a4cee5f 10174 if (GET_CODE (operands[0]) != SYMBOL_REF
473f51b6 10175 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
efdba735 10176 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
1fd4e8c1 10177 {
6a4cee5f
MM		 10178 if (INTVAL (operands[2]) & CALL_LONG)
10179 operands[0] = rs6000_longcall_ref (operands[0]);
10180
cccf3bdc 10181 if (DEFAULT_ABI == ABI_V4
f607bc57 10182 || DEFAULT_ABI == ABI_DARWIN)
bbf294a5 10183 operands[0] = force_reg (Pmode, operands[0]);
1fd4e8c1 10184
cccf3bdc
DE		 10185 else if (DEFAULT_ABI == ABI_AIX)
10186 {
10187 /* AIX function pointers are really pointers to a three word
10188 area. */
10189 emit_call_insn (TARGET_32BIT
10190 ? gen_call_indirect_aix32 (force_reg (SImode,
10191 operands[0]),
10192 operands[1])
10193 : gen_call_indirect_aix64 (force_reg (DImode,
10194 operands[0]),
10195 operands[1]));
10196 DONE;
b6c9286a 10197 }
cccf3bdc
DE		 10198 else
10199 abort ();
1fd4e8c1
RK		 10200 }
10201}")
10202
10203(define_expand "call_value"
10204 [(parallel [(set (match_operand 0 "" "")
a260abc9 10205 (call (mem:SI (match_operand 1 "address_operand" ""))
1fd4e8c1 10206 (match_operand 2 "" "")))
4697a36c 10207 (use (match_operand 3 "" ""))
1fd4e8c1
RK		 10208 (clobber (scratch:SI))])]
10209 ""
10210 "
10211{
ee890fe2 10212#if TARGET_MACHO
ab82a49f 10213 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10214 operands[1] = machopic_indirect_call_target (operands[1]);
10215#endif
10216
1fd4e8c1
RK		 10217 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10218 abort ();
10219
10220 operands[1] = XEXP (operands[1], 0);
7509c759 10221
6a4cee5f 10222 if (GET_CODE (operands[1]) != SYMBOL_REF
473f51b6 10223 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
efdba735 10224 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
1fd4e8c1 10225 {
6756293c 10226 if (INTVAL (operands[3]) & CALL_LONG)
6a4cee5f
MM		 10227 operands[1] = rs6000_longcall_ref (operands[1]);
10228
cccf3bdc 10229 if (DEFAULT_ABI == ABI_V4
f607bc57 10230 || DEFAULT_ABI == ABI_DARWIN)
bbf294a5 10231 operands[1] = force_reg (Pmode, operands[1]);
1fd4e8c1 10232
cccf3bdc
DE		 10233 else if (DEFAULT_ABI == ABI_AIX)
10234 {
10235 /* AIX function pointers are really pointers to a three word
10236 area. */
10237 emit_call_insn (TARGET_32BIT
10238 ? gen_call_value_indirect_aix32 (operands[0],
10239 force_reg (SImode,
10240 operands[1]),
10241 operands[2])
10242 : gen_call_value_indirect_aix64 (operands[0],
10243 force_reg (DImode,
10244 operands[1]),
10245 operands[2]));
10246 DONE;
b6c9286a 10247 }
cccf3bdc
DE		 10248 else
10249 abort ();
1fd4e8c1
RK		 10250 }
10251}")
10252
04780ee7 10253;; Call to function in current module. No TOC pointer reload needed.
a0ab749a 10254;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10255;; either the function was not prototyped, or it was prototyped as a
10256;; variable argument function. It is > 0 if FP registers were passed
10257;; and < 0 if they were not.
04780ee7 10258
a260abc9 10259(define_insn "*call_local32"
4697a36c
MM		 10260 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10261 (match_operand 1 "" "g,g"))
10262 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10263 (clobber (match_scratch:SI 3 "=l,l"))]
5a19791c 10264 "(INTVAL (operands[2]) & CALL_LONG) == 0"
4697a36c
MM		 10265 "*
10266{
6a4cee5f
MM		 10267 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10268 output_asm_insn (\"crxor 6,6,6\", operands);
10269
10270 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10271 output_asm_insn (\"creqv 6,6,6\", operands);
4697a36c 10272
a226df46 10273 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
4697a36c 10274}"
b7ff3d82
DE		 10275 [(set_attr "type" "branch")
10276 (set_attr "length" "4,8")])
04780ee7 10277
a260abc9
DE		 10278(define_insn "*call_local64"
10279 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10280 (match_operand 1 "" "g,g"))
10281 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10282 (clobber (match_scratch:SI 3 "=l,l"))]
10283 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10284 "*
10285{
10286 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10287 output_asm_insn (\"crxor 6,6,6\", operands);
10288
10289 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10290 output_asm_insn (\"creqv 6,6,6\", operands);
10291
10292 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10293}"
10294 [(set_attr "type" "branch")
10295 (set_attr "length" "4,8")])
10296
cccf3bdc 10297(define_insn "*call_value_local32"
d18dba68 10298 [(set (match_operand 0 "" "")
a260abc9
DE		 10299 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10300 (match_operand 2 "" "g,g")))
10301 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10302 (clobber (match_scratch:SI 4 "=l,l"))]
10303 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10304 "*
10305{
10306 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10307 output_asm_insn (\"crxor 6,6,6\", operands);
10308
10309 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10310 output_asm_insn (\"creqv 6,6,6\", operands);
10311
10312 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10313}"
10314 [(set_attr "type" "branch")
10315 (set_attr "length" "4,8")])
10316
10317
cccf3bdc 10318(define_insn "*call_value_local64"
d18dba68 10319 [(set (match_operand 0 "" "")
a260abc9
DE		 10320 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10321 (match_operand 2 "" "g,g")))
10322 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10323 (clobber (match_scratch:SI 4 "=l,l"))]
10324 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10325 "*
10326{
10327 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10328 output_asm_insn (\"crxor 6,6,6\", operands);
10329
10330 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10331 output_asm_insn (\"creqv 6,6,6\", operands);
10332
10333 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10334}"
10335 [(set_attr "type" "branch")
10336 (set_attr "length" "4,8")])
10337
04780ee7 10338;; Call to function which may be in another module. Restore the TOC
911f679c 10339;; pointer (r2) after the call unless this is System V.
a0ab749a 10340;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10341;; either the function was not prototyped, or it was prototyped as a
10342;; variable argument function. It is > 0 if FP registers were passed
10343;; and < 0 if they were not.
04780ee7 10344
cccf3bdc
DE		 10345(define_insn "*call_indirect_nonlocal_aix32"
10346 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10347 (match_operand 1 "" "g"))
10348 (use (reg:SI 2))
10349 (use (reg:SI 11))
10350 (set (reg:SI 2)
10351 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
c77e04ae 10352 (clobber (match_scratch:SI 2 "=l"))]
cccf3bdc
DE		 10353 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10354 "b%T0l\;{l|lwz} 2,20(1)"
10355 [(set_attr "type" "jmpreg")
10356 (set_attr "length" "8")])
10357
a260abc9 10358(define_insn "*call_nonlocal_aix32"
cc4d5fec 10359 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10360 (match_operand 1 "" "g"))
10361 (use (match_operand:SI 2 "immediate_operand" "O"))
10362 (clobber (match_scratch:SI 3 "=l"))]
10363 "TARGET_32BIT
10364 && DEFAULT_ABI == ABI_AIX
5a19791c 10365 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 10366 "bl %z0\;%."
b7ff3d82 10367 [(set_attr "type" "branch")
cccf3bdc
DE		 10368 (set_attr "length" "8")])
10369
10370(define_insn "*call_indirect_nonlocal_aix64"
10371 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10372 (match_operand 1 "" "g"))
10373 (use (reg:DI 2))
10374 (use (reg:DI 11))
10375 (set (reg:DI 2)
10376 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
c77e04ae 10377 (clobber (match_scratch:SI 2 "=l"))]
cccf3bdc
DE		 10378 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10379 "b%T0l\;ld 2,40(1)"
10380 [(set_attr "type" "jmpreg")
10381 (set_attr "length" "8")])
59313e4e 10382
a260abc9 10383(define_insn "*call_nonlocal_aix64"
cc4d5fec 10384 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10385 (match_operand 1 "" "g"))
10386 (use (match_operand:SI 2 "immediate_operand" "O"))
10387 (clobber (match_scratch:SI 3 "=l"))]
9ebbca7d
GK		 10388 "TARGET_64BIT
10389 && DEFAULT_ABI == ABI_AIX
a260abc9 10390 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 10391 "bl %z0\;%."
a260abc9 10392 [(set_attr "type" "branch")
cccf3bdc 10393 (set_attr "length" "8")])
7509c759 10394
cccf3bdc 10395(define_insn "*call_value_indirect_nonlocal_aix32"
d18dba68 10396 [(set (match_operand 0 "" "")
cccf3bdc
DE		 10397 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10398 (match_operand 2 "" "g")))
10399 (use (reg:SI 2))
10400 (use (reg:SI 11))
10401 (set (reg:SI 2)
10402 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10403 (clobber (match_scratch:SI 3 "=l"))]
10404 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10405 "b%T1l\;{l|lwz} 2,20(1)"
10406 [(set_attr "type" "jmpreg")
10407 (set_attr "length" "8")])
1fd4e8c1 10408
cccf3bdc 10409(define_insn "*call_value_nonlocal_aix32"
d18dba68 10410 [(set (match_operand 0 "" "")
cc4d5fec 10411 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10412 (match_operand 2 "" "g")))
10413 (use (match_operand:SI 3 "immediate_operand" "O"))
10414 (clobber (match_scratch:SI 4 "=l"))]
10415 "TARGET_32BIT
10416 && DEFAULT_ABI == ABI_AIX
a260abc9 10417 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc 10418 "bl %z1\;%."
b7ff3d82 10419 [(set_attr "type" "branch")
cccf3bdc 10420 (set_attr "length" "8")])
04780ee7 10421
cccf3bdc 10422(define_insn "*call_value_indirect_nonlocal_aix64"
d18dba68 10423 [(set (match_operand 0 "" "")
cccf3bdc
DE		 10424 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10425 (match_operand 2 "" "g")))
10426 (use (reg:DI 2))
10427 (use (reg:DI 11))
10428 (set (reg:DI 2)
10429 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10430 (clobber (match_scratch:SI 3 "=l"))]
10431 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10432 "b%T1l\;ld 2,40(1)"
10433 [(set_attr "type" "jmpreg")
10434 (set_attr "length" "8")])
10435
10436(define_insn "*call_value_nonlocal_aix64"
d18dba68 10437 [(set (match_operand 0 "" "")
cc4d5fec 10438 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10439 (match_operand 2 "" "g")))
10440 (use (match_operand:SI 3 "immediate_operand" "O"))
10441 (clobber (match_scratch:SI 4 "=l"))]
9ebbca7d
GK		 10442 "TARGET_64BIT
10443 && DEFAULT_ABI == ABI_AIX
5a19791c 10444 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc
DE		 10445 "bl %z1\;%."
10446 [(set_attr "type" "branch")
10447 (set_attr "length" "8")])
10448
10449;; A function pointer under System V is just a normal pointer
10450;; operands[0] is the function pointer
10451;; operands[1] is the stack size to clean up
10452;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10453;; which indicates how to set cr1
10454
a5c76ee6
ZW		 10455(define_insn "*call_indirect_nonlocal_sysv"
10456 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10457 (match_operand 1 "" "g,g"))
10458 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10459 (clobber (match_scratch:SI 3 "=l,l"))]
50d440bc 10460 "DEFAULT_ABI == ABI_V4
f607bc57 10461 || DEFAULT_ABI == ABI_DARWIN"
911f679c 10462{
cccf3bdc 10463 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 10464 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f 10465
cccf3bdc 10466 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 10467 output_asm_insn ("creqv 6,6,6", operands);
7509c759 10468
a5c76ee6
ZW		 10469 return "b%T0l";
10470}
10471 [(set_attr "type" "jmpreg,jmpreg")
10472 (set_attr "length" "4,8")])
cccf3bdc 10473
a5c76ee6
ZW		 10474(define_insn "*call_nonlocal_sysv"
10475 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10476 (match_operand 1 "" "g,g"))
10477 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10478 (clobber (match_scratch:SI 3 "=l,l"))]
efdba735
SH		 10479 "(DEFAULT_ABI == ABI_DARWIN
10480 || (DEFAULT_ABI == ABI_V4
10481 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 10482{
10483 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10484 output_asm_insn ("crxor 6,6,6", operands);
10485
10486 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10487 output_asm_insn ("creqv 6,6,6", operands);
10488
c989f2f7 10489#if TARGET_MACHO
efdba735
SH		 10490 return output_call(insn, operands, 0, 2);
10491#else
a5c76ee6 10492 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
efdba735 10493#endif
a5c76ee6
ZW		 10494}
10495 [(set_attr "type" "branch,branch")
10496 (set_attr "length" "4,8")])
10497
10498(define_insn "*call_value_indirect_nonlocal_sysv"
d18dba68 10499 [(set (match_operand 0 "" "")
a5c76ee6
ZW		 10500 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10501 (match_operand 2 "" "g,g")))
10502 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10503 (clobber (match_scratch:SI 4 "=l,l"))]
50d440bc 10504 "DEFAULT_ABI == ABI_V4
f607bc57 10505 || DEFAULT_ABI == ABI_DARWIN"
b6c9286a 10506{
6a4cee5f 10507 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 10508 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f
MM		 10509
10510 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 10511 output_asm_insn ("creqv 6,6,6", operands);
7509c759 10512
a5c76ee6
ZW		 10513 return "b%T1l";
10514}
10515 [(set_attr "type" "jmpreg,jmpreg")
10516 (set_attr "length" "4,8")])
10517
10518(define_insn "*call_value_nonlocal_sysv"
10519 [(set (match_operand 0 "" "")
10520 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10521 (match_operand 2 "" "g,g")))
10522 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10523 (clobber (match_scratch:SI 4 "=l,l"))]
efdba735
SH		 10524 "(DEFAULT_ABI == ABI_DARWIN
10525 || (DEFAULT_ABI == ABI_V4
10526 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 10527{
10528 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10529 output_asm_insn ("crxor 6,6,6", operands);
10530
10531 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10532 output_asm_insn ("creqv 6,6,6", operands);
10533
c989f2f7 10534#if TARGET_MACHO
efdba735
SH		 10535 return output_call(insn, operands, 1, 3);
10536#else
a5c76ee6 10537 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
efdba735 10538#endif
a5c76ee6
ZW		 10539}
10540 [(set_attr "type" "branch,branch")
10541 (set_attr "length" "4,8")])
e6f948e3
RK		 10542
10543;; Call subroutine returning any type.
e6f948e3
RK		 10544(define_expand "untyped_call"
10545 [(parallel [(call (match_operand 0 "" "")
10546 (const_int 0))
10547 (match_operand 1 "" "")
10548 (match_operand 2 "" "")])]
10549 ""
10550 "
10551{
10552 int i;
10553
7d70b8b2 10554 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
e6f948e3
RK		 10555
10556 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10557 {
10558 rtx set = XVECEXP (operands[2], 0, i);
10559 emit_move_insn (SET_DEST (set), SET_SRC (set));
10560 }
10561
10562 /* The optimizer does not know that the call sets the function value
10563 registers we stored in the result block. We avoid problems by
10564 claiming that all hard registers are used and clobbered at this
10565 point. */
10566 emit_insn (gen_blockage ());
10567
10568 DONE;
10569}")
10570
5e1bf043
DJ		 10571;; sibling call patterns
10572(define_expand "sibcall"
10573 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10574 (match_operand 1 "" ""))
10575 (use (match_operand 2 "" ""))
fe352c29 10576 (use (match_operand 3 "" ""))
5e1bf043
DJ		 10577 (return)])]
10578 ""
10579 "
10580{
10581#if TARGET_MACHO
ab82a49f 10582 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 10583 operands[0] = machopic_indirect_call_target (operands[0]);
10584#endif
10585
10586 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10587 abort ();
10588
10589 operands[0] = XEXP (operands[0], 0);
fe352c29 10590 operands[3] = gen_reg_rtx (SImode);
5e1bf043
DJ		 10591
10592}")
10593
10594;; this and similar patterns must be marked as using LR, otherwise
10595;; dataflow will try to delete the store into it. This is true
10596;; even when the actual reg to jump to is in CTR, when LR was
10597;; saved and restored around the PIC-setting BCL.
10598(define_insn "*sibcall_local32"
10599 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10600 (match_operand 1 "" "g,g"))
10601 (use (match_operand:SI 2 "immediate_operand" "O,n"))
fe352c29 10602 (use (match_operand:SI 3 "register_operand" "l,l"))
5e1bf043
DJ		 10603 (return)]
10604 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10605 "*
10606{
10607 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10608 output_asm_insn (\"crxor 6,6,6\", operands);
10609
10610 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10611 output_asm_insn (\"creqv 6,6,6\", operands);
10612
10613 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10614}"
10615 [(set_attr "type" "branch")
10616 (set_attr "length" "4,8")])
10617
10618(define_insn "*sibcall_local64"
10619 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10620 (match_operand 1 "" "g,g"))
10621 (use (match_operand:SI 2 "immediate_operand" "O,n"))
fe352c29 10622 (use (match_operand:SI 3 "register_operand" "l,l"))
5e1bf043
DJ		 10623 (return)]
10624 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10625 "*
10626{
10627 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10628 output_asm_insn (\"crxor 6,6,6\", operands);
10629
10630 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10631 output_asm_insn (\"creqv 6,6,6\", operands);
10632
10633 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10634}"
10635 [(set_attr "type" "branch")
10636 (set_attr "length" "4,8")])
10637
10638(define_insn "*sibcall_value_local32"
10639 [(set (match_operand 0 "" "")
10640 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10641 (match_operand 2 "" "g,g")))
10642 (use (match_operand:SI 3 "immediate_operand" "O,n"))
fe352c29 10643 (use (match_operand:SI 4 "register_operand" "l,l"))
5e1bf043
DJ		 10644 (return)]
10645 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10646 "*
10647{
10648 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10649 output_asm_insn (\"crxor 6,6,6\", operands);
10650
10651 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10652 output_asm_insn (\"creqv 6,6,6\", operands);
10653
10654 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10655}"
10656 [(set_attr "type" "branch")
10657 (set_attr "length" "4,8")])
10658
10659
10660(define_insn "*sibcall_value_local64"
10661 [(set (match_operand 0 "" "")
10662 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10663 (match_operand 2 "" "g,g")))
10664 (use (match_operand:SI 3 "immediate_operand" "O,n"))
fe352c29 10665 (use (match_operand:SI 4 "register_operand" "l,l"))
5e1bf043
DJ		 10666 (return)]
10667 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10668 "*
10669{
10670 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10671 output_asm_insn (\"crxor 6,6,6\", operands);
10672
10673 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10674 output_asm_insn (\"creqv 6,6,6\", operands);
10675
10676 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10677}"
10678 [(set_attr "type" "branch")
10679 (set_attr "length" "4,8")])
10680
10681(define_insn "*sibcall_nonlocal_aix32"
10682 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10683 (match_operand 1 "" "g"))
10684 (use (match_operand:SI 2 "immediate_operand" "O"))
fe352c29 10685 (use (match_operand:SI 3 "register_operand" "l"))
5e1bf043
DJ		 10686 (return)]
10687 "TARGET_32BIT
10688 && DEFAULT_ABI == ABI_AIX
10689 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10690 "b %z0"
10691 [(set_attr "type" "branch")
10692 (set_attr "length" "4")])
10693
10694(define_insn "*sibcall_nonlocal_aix64"
10695 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10696 (match_operand 1 "" "g"))
10697 (use (match_operand:SI 2 "immediate_operand" "O"))
fe352c29 10698 (use (match_operand:SI 3 "register_operand" "l"))
5e1bf043
DJ		 10699 (return)]
10700 "TARGET_64BIT
10701 && DEFAULT_ABI == ABI_AIX
10702 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10703 "b %z0"
10704 [(set_attr "type" "branch")
10705 (set_attr "length" "4")])
10706
10707(define_insn "*sibcall_value_nonlocal_aix32"
10708 [(set (match_operand 0 "" "")
10709 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10710 (match_operand 2 "" "g")))
10711 (use (match_operand:SI 3 "immediate_operand" "O"))
fe352c29 10712 (use (match_operand:SI 4 "register_operand" "l"))
5e1bf043
DJ		 10713 (return)]
10714 "TARGET_32BIT
10715 && DEFAULT_ABI == ABI_AIX
10716 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10717 "b %z1"
10718 [(set_attr "type" "branch")
10719 (set_attr "length" "4")])
10720
10721(define_insn "*sibcall_value_nonlocal_aix64"
10722 [(set (match_operand 0 "" "")
10723 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10724 (match_operand 2 "" "g")))
10725 (use (match_operand:SI 3 "immediate_operand" "O"))
fe352c29 10726 (use (match_operand:SI 4 "register_operand" "l"))
5e1bf043
DJ		 10727 (return)]
10728 "TARGET_64BIT
10729 && DEFAULT_ABI == ABI_AIX
10730 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10731 "b %z1"
10732 [(set_attr "type" "branch")
10733 (set_attr "length" "4")])
10734
10735(define_insn "*sibcall_nonlocal_sysv"
10736 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10737 (match_operand 1 "" ""))
10738 (use (match_operand 2 "immediate_operand" "O,n"))
fe352c29 10739 (use (match_operand:SI 3 "register_operand" "l,l"))
5e1bf043
DJ		 10740 (return)]
10741 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 10742 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 10743 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10744 "*
10745{
10746 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10747 output_asm_insn (\"crxor 6,6,6\", operands);
10748
10749 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10750 output_asm_insn (\"creqv 6,6,6\", operands);
10751
10752 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
10753}"
10754 [(set_attr "type" "branch,branch")
10755 (set_attr "length" "4,8")])
10756
10757(define_expand "sibcall_value"
10758 [(parallel [(set (match_operand 0 "register_operand" "")
10759 (call (mem:SI (match_operand 1 "address_operand" ""))
10760 (match_operand 2 "" "")))
10761 (use (match_operand 3 "" ""))
fe352c29 10762 (use (match_operand 4 "" ""))
5e1bf043
DJ		 10763 (return)])]
10764 ""
10765 "
10766{
10767#if TARGET_MACHO
ab82a49f 10768 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 10769 operands[1] = machopic_indirect_call_target (operands[1]);
10770#endif
10771
10772 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10773 abort ();
10774
10775 operands[1] = XEXP (operands[1], 0);
fe352c29 10776 operands[4] = gen_reg_rtx (SImode);
5e1bf043
DJ		 10777
10778}")
10779
10780(define_insn "*sibcall_value_nonlocal_sysv"
10781 [(set (match_operand 0 "" "")
10782 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10783 (match_operand 2 "" "")))
10784 (use (match_operand:SI 3 "immediate_operand" "O,n"))
fe352c29 10785 (use (match_operand:SI 4 "register_operand" "l,l"))
5e1bf043
DJ		 10786 (return)]
10787 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 10788 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 10789 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10790 "*
10791{
10792 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10793 output_asm_insn (\"crxor 6,6,6\", operands);
10794
10795 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10796 output_asm_insn (\"creqv 6,6,6\", operands);
10797
10798 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
10799}"
10800 [(set_attr "type" "branch,branch")
10801 (set_attr "length" "4,8")])
10802
10803(define_expand "sibcall_epilogue"
10804 [(use (const_int 0))]
10805 "TARGET_SCHED_PROLOG"
10806 "
10807{
10808 rs6000_emit_epilogue (TRUE);
10809 DONE;
10810}")
10811
e6f948e3
RK		 10812;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10813;; all of memory. This blocks insns from being moved across this point.
10814
10815(define_insn "blockage"
615158e2 10816 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
e6f948e3
RK		 10817 ""
10818 "")
1fd4e8c1
RK		 10819\f
10820;; Compare insns are next. Note that the RS/6000 has two types of compares,
7e69e155 10821;; signed & unsigned, and one type of branch.
1fd4e8c1
RK		 10822;;
10823;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10824;; insns, and branches. We store the operands of compares until we see
10825;; how it is used.
10826(define_expand "cmpsi"
10827 [(set (cc0)
cd2b37d9 10828 (compare (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 10829 (match_operand:SI 1 "reg_or_short_operand" "")))]
10830 ""
10831 "
10832{
10833 /* Take care of the possibility that operands[1] might be negative but
10834 this might be a logical operation. That insn doesn't exist. */
10835 if (GET_CODE (operands[1]) == CONST_INT
10836 && INTVAL (operands[1]) < 0)
10837 operands[1] = force_reg (SImode, operands[1]);
10838
10839 rs6000_compare_op0 = operands[0];
10840 rs6000_compare_op1 = operands[1];
10841 rs6000_compare_fp_p = 0;
10842 DONE;
10843}")
10844
266eb58a
DE		 10845(define_expand "cmpdi"
10846 [(set (cc0)
10847 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10848 (match_operand:DI 1 "reg_or_short_operand" "")))]
10849 "TARGET_POWERPC64"
10850 "
10851{
10852 /* Take care of the possibility that operands[1] might be negative but
10853 this might be a logical operation. That insn doesn't exist. */
10854 if (GET_CODE (operands[1]) == CONST_INT
10855 && INTVAL (operands[1]) < 0)
10856 operands[1] = force_reg (DImode, operands[1]);
10857
10858 rs6000_compare_op0 = operands[0];
10859 rs6000_compare_op1 = operands[1];
10860 rs6000_compare_fp_p = 0;
10861 DONE;
10862}")
10863
1fd4e8c1 10864(define_expand "cmpsf"
cd2b37d9
RK		 10865 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10866 (match_operand:SF 1 "gpc_reg_operand" "")))]
d14a6d05 10867 "TARGET_HARD_FLOAT"
1fd4e8c1
RK		 10868 "
10869{
10870 rs6000_compare_op0 = operands[0];
10871 rs6000_compare_op1 = operands[1];
10872 rs6000_compare_fp_p = 1;
10873 DONE;
10874}")
10875
10876(define_expand "cmpdf"
cd2b37d9
RK		 10877 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10878 (match_operand:DF 1 "gpc_reg_operand" "")))]
a3170dc6 10879 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 10880 "
10881{
10882 rs6000_compare_op0 = operands[0];
10883 rs6000_compare_op1 = operands[1];
10884 rs6000_compare_fp_p = 1;
10885 DONE;
10886}")
10887
d6f99ca4 10888(define_expand "cmptf"
e7a4130e
DE		 10889 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
10890 (match_operand:TF 1 "gpc_reg_operand" "")))]
39e63627
GK		 10891 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10892 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
d6f99ca4
DE		 10893 "
10894{
10895 rs6000_compare_op0 = operands[0];
10896 rs6000_compare_op1 = operands[1];
10897 rs6000_compare_fp_p = 1;
10898 DONE;
10899}")
10900
1fd4e8c1 10901(define_expand "beq"
39a10a29 10902 [(use (match_operand 0 "" ""))]
1fd4e8c1 10903 ""
39a10a29 10904 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 10905
10906(define_expand "bne"
39a10a29 10907 [(use (match_operand 0 "" ""))]
1fd4e8c1 10908 ""
39a10a29 10909 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
1fd4e8c1 10910
39a10a29
GK		 10911(define_expand "bge"
10912 [(use (match_operand 0 "" ""))]
1fd4e8c1 10913 ""
39a10a29 10914 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
1fd4e8c1
RK		 10915
10916(define_expand "bgt"
39a10a29 10917 [(use (match_operand 0 "" ""))]
1fd4e8c1 10918 ""
39a10a29 10919 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
1fd4e8c1
RK		 10920
10921(define_expand "ble"
39a10a29 10922 [(use (match_operand 0 "" ""))]
1fd4e8c1 10923 ""
39a10a29 10924 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
1fd4e8c1 10925
39a10a29
GK		 10926(define_expand "blt"
10927 [(use (match_operand 0 "" ""))]
1fd4e8c1 10928 ""
39a10a29 10929 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
1fd4e8c1 10930
39a10a29
GK		 10931(define_expand "bgeu"
10932 [(use (match_operand 0 "" ""))]
1fd4e8c1 10933 ""
39a10a29 10934 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
1fd4e8c1 10935
39a10a29
GK		 10936(define_expand "bgtu"
10937 [(use (match_operand 0 "" ""))]
1fd4e8c1 10938 ""
39a10a29 10939 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
1fd4e8c1 10940
39a10a29
GK		 10941(define_expand "bleu"
10942 [(use (match_operand 0 "" ""))]
1fd4e8c1 10943 ""
39a10a29 10944 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
1fd4e8c1 10945
39a10a29
GK		 10946(define_expand "bltu"
10947 [(use (match_operand 0 "" ""))]
1fd4e8c1 10948 ""
39a10a29 10949 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
1fd4e8c1 10950
1c882ea4 10951(define_expand "bunordered"
39a10a29 10952 [(use (match_operand 0 "" ""))]
1c882ea4 10953 ""
39a10a29 10954 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
1c882ea4
GK		 10955
10956(define_expand "bordered"
39a10a29 10957 [(use (match_operand 0 "" ""))]
1c882ea4 10958 ""
39a10a29 10959 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
1c882ea4
GK		 10960
10961(define_expand "buneq"
39a10a29 10962 [(use (match_operand 0 "" ""))]
1c882ea4 10963 ""
39a10a29 10964 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
1c882ea4
GK		 10965
10966(define_expand "bunge"
39a10a29 10967 [(use (match_operand 0 "" ""))]
1c882ea4 10968 ""
39a10a29 10969 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
1c882ea4
GK		 10970
10971(define_expand "bungt"
39a10a29 10972 [(use (match_operand 0 "" ""))]
1c882ea4 10973 ""
39a10a29 10974 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
1c882ea4
GK		 10975
10976(define_expand "bunle"
39a10a29 10977 [(use (match_operand 0 "" ""))]
1c882ea4 10978 ""
39a10a29 10979 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
1c882ea4
GK		 10980
10981(define_expand "bunlt"
39a10a29 10982 [(use (match_operand 0 "" ""))]
1c882ea4 10983 ""
39a10a29 10984 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
1c882ea4
GK		 10985
10986(define_expand "bltgt"
39a10a29 10987 [(use (match_operand 0 "" ""))]
1c882ea4 10988 ""
39a10a29 10989 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
1c882ea4 10990
1fd4e8c1
RK		 10991;; For SNE, we would prefer that the xor/abs sequence be used for integers.
10992;; For SEQ, likewise, except that comparisons with zero should be done
10993;; with an scc insns. However, due to the order that combine see the
10994;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
10995;; the cases we don't want to handle.
10996(define_expand "seq"
39a10a29 10997 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 10998 ""
39a10a29 10999 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 11000
11001(define_expand "sne"
39a10a29 11002 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11003 ""
11004 "
39a10a29
GK		 11005{
11006 if (! rs6000_compare_fp_p)
1fd4e8c1
RK		 11007 FAIL;
11008
39a10a29
GK		 11009 rs6000_emit_sCOND (NE, operands[0]);
11010 DONE;
1fd4e8c1
RK		 11011}")
11012
b7053a3f
GK		 11013;; A >= 0 is best done the portable way for A an integer.
11014(define_expand "sge"
39a10a29 11015 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11016 ""
11017 "
5638268e
DE		 11018{
11019 if (! rs6000_compare_fp_p
11020 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
1fd4e8c1
RK		 11021 FAIL;
11022
b7053a3f 11023 rs6000_emit_sCOND (GE, operands[0]);
39a10a29 11024 DONE;
1fd4e8c1
RK		 11025}")
11026
b7053a3f
GK		 11027;; A > 0 is best done using the portable sequence, so fail in that case.
11028(define_expand "sgt"
39a10a29 11029 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11030 ""
11031 "
5638268e 11032{
b7053a3f 11033 if (! rs6000_compare_fp_p
5638268e 11034 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
1fd4e8c1
RK		 11035 FAIL;
11036
b7053a3f 11037 rs6000_emit_sCOND (GT, operands[0]);
39a10a29 11038 DONE;
1fd4e8c1
RK		 11039}")
11040
b7053a3f
GK		 11041;; A <= 0 is best done the portable way for A an integer.
11042(define_expand "sle"
39a10a29 11043 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11044 ""
5638268e
DE		 11045 "
11046{
11047 if (! rs6000_compare_fp_p
11048 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11049 FAIL;
11050
b7053a3f 11051 rs6000_emit_sCOND (LE, operands[0]);
5638268e
DE		 11052 DONE;
11053}")
1fd4e8c1 11054
b7053a3f
GK		 11055;; A < 0 is best done in the portable way for A an integer.
11056(define_expand "slt"
39a10a29 11057 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11058 ""
11059 "
5638268e 11060{
b7053a3f 11061 if (! rs6000_compare_fp_p
5638268e 11062 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
1fd4e8c1
RK		 11063 FAIL;
11064
b7053a3f 11065 rs6000_emit_sCOND (LT, operands[0]);
39a10a29 11066 DONE;
1fd4e8c1
RK		 11067}")
11068
b7053a3f
GK		 11069(define_expand "sgeu"
11070 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11071 ""
11072 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11073
1fd4e8c1 11074(define_expand "sgtu"
39a10a29 11075 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11076 ""
39a10a29 11077 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
1fd4e8c1 11078
b7053a3f
GK		 11079(define_expand "sleu"
11080 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11081 ""
11082 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11083
1fd4e8c1 11084(define_expand "sltu"
39a10a29 11085 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11086 ""
39a10a29 11087 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
1fd4e8c1 11088
b7053a3f 11089(define_expand "sunordered"
39a10a29 11090 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11091 ""
b7053a3f 11092 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
1fd4e8c1 11093
b7053a3f 11094(define_expand "sordered"
39a10a29 11095 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11096 ""
b7053a3f
GK		 11097 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11098
11099(define_expand "suneq"
11100 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11101 ""
11102 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11103
11104(define_expand "sunge"
11105 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11106 ""
11107 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11108
11109(define_expand "sungt"
11110 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11111 ""
11112 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11113
11114(define_expand "sunle"
11115 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11116 ""
11117 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11118
11119(define_expand "sunlt"
11120 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11121 ""
11122 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11123
11124(define_expand "sltgt"
11125 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11126 ""
11127 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11128
1fd4e8c1
RK		 11129\f
11130;; Here are the actual compare insns.
acad7ed3 11131(define_insn "*cmpsi_internal1"
1fd4e8c1 11132 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
cd2b37d9 11133 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 11134 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11135 ""
7f340546 11136 "{cmp%I2|cmpw%I2} %0,%1,%2"
b54cf83a 11137 [(set_attr "type" "cmp")])
1fd4e8c1 11138
acad7ed3 11139(define_insn "*cmpdi_internal1"
266eb58a
DE		 11140 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11141 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11142 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11143 "TARGET_POWERPC64"
11144 "cmpd%I2 %0,%1,%2"
b54cf83a 11145 [(set_attr "type" "cmp")])
266eb58a 11146
f357808b
RK		 11147;; If we are comparing a register for equality with a large constant,
11148;; we can do this with an XOR followed by a compare. But we need a scratch
11149;; register for the result of the XOR.
11150
11151(define_split
11152 [(set (match_operand:CC 0 "cc_reg_operand" "")
cd2b37d9 11153 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
f357808b 11154 (match_operand:SI 2 "non_short_cint_operand" "")))
cd2b37d9 11155 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
f357808b
RK		 11156 "find_single_use (operands[0], insn, 0)
11157 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11158 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11159 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11160 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11161 "
11162{
11163 /* Get the constant we are comparing against, C, and see what it looks like
11164 sign-extended to 16 bits. Then see what constant could be XOR'ed
11165 with C to get the sign-extended value. */
11166
5f59ecb7 11167 HOST_WIDE_INT c = INTVAL (operands[2]);
a65c591c 11168 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
5f59ecb7 11169 HOST_WIDE_INT xorv = c ^ sextc;
f357808b 11170
89e9f3a8
MM		 11171 operands[4] = GEN_INT (xorv);
11172 operands[5] = GEN_INT (sextc);
f357808b
RK		 11173}")
11174
acad7ed3 11175(define_insn "*cmpsi_internal2"
1fd4e8c1 11176 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
cd2b37d9 11177 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9ebbca7d 11178 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
1fd4e8c1 11179 ""
e2c953b6 11180 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
b54cf83a 11181 [(set_attr "type" "cmp")])
1fd4e8c1 11182
acad7ed3 11183(define_insn "*cmpdi_internal2"
266eb58a
DE		 11184 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11185 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
9ebbca7d 11186 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
266eb58a 11187 ""
e2c953b6 11188 "cmpld%I2 %0,%1,%b2"
b54cf83a 11189 [(set_attr "type" "cmp")])
266eb58a 11190
1fd4e8c1
RK		 11191;; The following two insns don't exist as single insns, but if we provide
11192;; them, we can swap an add and compare, which will enable us to overlap more
11193;; of the required delay between a compare and branch. We generate code for
11194;; them by splitting.
11195
11196(define_insn ""
11197 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
cd2b37d9 11198 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11199 (match_operand:SI 2 "short_cint_operand" "i")))
cd2b37d9 11200 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11201 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11202 ""
baf97f86
RK		 11203 "#"
11204 [(set_attr "length" "8")])
7e69e155 11205
1fd4e8c1
RK		 11206(define_insn ""
11207 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
cd2b37d9 11208 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11209 (match_operand:SI 2 "u_short_cint_operand" "i")))
cd2b37d9 11210 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11211 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11212 ""
baf97f86
RK		 11213 "#"
11214 [(set_attr "length" "8")])
7e69e155 11215
1fd4e8c1
RK		 11216(define_split
11217 [(set (match_operand:CC 3 "cc_reg_operand" "")
cd2b37d9 11218 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11219 (match_operand:SI 2 "short_cint_operand" "")))
cd2b37d9 11220 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11221 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11222 ""
11223 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11224 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11225
11226(define_split
11227 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
cd2b37d9 11228 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11229 (match_operand:SI 2 "u_short_cint_operand" "")))
cd2b37d9 11230 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11231 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11232 ""
11233 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11234 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11235
acad7ed3 11236(define_insn "*cmpsf_internal1"
1fd4e8c1 11237 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11238 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11239 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 11240 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11241 "fcmpu %0,%1,%2"
11242 [(set_attr "type" "fpcompare")])
11243
acad7ed3 11244(define_insn "*cmpdf_internal1"
1fd4e8c1 11245 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11246 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11247 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 11248 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11249 "fcmpu %0,%1,%2"
11250 [(set_attr "type" "fpcompare")])
d6f99ca4
DE		 11251
11252;; Only need to compare second words if first words equal
11253(define_insn "*cmptf_internal1"
11254 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11255 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11256 (match_operand:TF 2 "gpc_reg_operand" "f")))]
39e63627
GK		 11257 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11258 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 11259 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
d6f99ca4
DE		 11260 [(set_attr "type" "fpcompare")
11261 (set_attr "length" "12")])
1fd4e8c1
RK		 11262\f
11263;; Now we have the scc insns. We can do some combinations because of the
11264;; way the machine works.
11265;;
11266;; Note that this is probably faster if we can put an insn between the
c5defebb
RK		 11267;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11268;; cases the insns below which don't use an intermediate CR field will
11269;; be used instead.
1fd4e8c1 11270(define_insn ""
cd2b37d9 11271 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11272 (match_operator:SI 1 "scc_comparison_operator"
11273 [(match_operand 2 "cc_reg_operand" "y")
11274 (const_int 0)]))]
11275 ""
2c4a9cff
DE		 11276 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11277 [(set (attr "type")
11278 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11279 (const_string "mfcrf")
11280 ]
11281 (const_string "mfcr")))
309323c2 11282 (set_attr "length" "12")])
1fd4e8c1 11283
a3170dc6
AH		 11284;; Same as above, but get the OV/ORDERED bit.
11285(define_insn "move_from_CR_ov_bit"
11286 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 11287 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
a3170dc6 11288 "TARGET_ISEL"
b7053a3f 11289 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
b54cf83a
DE		 11290 [(set_attr "type" "mfcr")
11291 (set_attr "length" "12")])
a3170dc6 11292
1fd4e8c1 11293(define_insn ""
9ebbca7d
GK		 11294 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11295 (match_operator:DI 1 "scc_comparison_operator"
11296 [(match_operand 2 "cc_reg_operand" "y")
11297 (const_int 0)]))]
11298 "TARGET_POWERPC64"
2c4a9cff
DE		 11299 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11300 [(set (attr "type")
11301 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11302 (const_string "mfcrf")
11303 ]
11304 (const_string "mfcr")))
309323c2 11305 (set_attr "length" "12")])
9ebbca7d
GK		 11306
11307(define_insn ""
11308 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 11309 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 11310 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1
RK		 11311 (const_int 0)])
11312 (const_int 0)))
9ebbca7d 11313 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 11314 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 11315 "TARGET_32BIT"
9ebbca7d 11316 "@
2c4a9cff 11317 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
9ebbca7d 11318 #"
b19003d8 11319 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 11320 (set_attr "length" "12,16")])
11321
11322(define_split
11323 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11324 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11325 [(match_operand 2 "cc_reg_operand" "")
11326 (const_int 0)])
11327 (const_int 0)))
11328 (set (match_operand:SI 3 "gpc_reg_operand" "")
11329 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 11330 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 11331 [(set (match_dup 3)
11332 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11333 (set (match_dup 0)
11334 (compare:CC (match_dup 3)
11335 (const_int 0)))]
11336 "")
1fd4e8c1
RK		 11337
11338(define_insn ""
cd2b37d9 11339 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11340 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11341 [(match_operand 2 "cc_reg_operand" "y")
11342 (const_int 0)])
11343 (match_operand:SI 3 "const_int_operand" "n")))]
11344 ""
11345 "*
11346{
11347 int is_bit = ccr_bit (operands[1], 1);
11348 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11349 int count;
11350
11351 if (is_bit >= put_bit)
11352 count = is_bit - put_bit;
11353 else
11354 count = 32 - (put_bit - is_bit);
11355
89e9f3a8
MM		 11356 operands[4] = GEN_INT (count);
11357 operands[5] = GEN_INT (put_bit);
1fd4e8c1 11358
2c4a9cff 11359 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
b19003d8 11360}"
2c4a9cff
DE		 11361 [(set (attr "type")
11362 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11363 (const_string "mfcrf")
11364 ]
11365 (const_string "mfcr")))
309323c2 11366 (set_attr "length" "12")])
1fd4e8c1
RK		 11367
11368(define_insn ""
9ebbca7d 11369 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 11370 (compare:CC
11371 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 11372 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1 11373 (const_int 0)])
9ebbca7d 11374 (match_operand:SI 3 "const_int_operand" "n,n"))
1fd4e8c1 11375 (const_int 0)))
9ebbca7d 11376 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 11377 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11378 (match_dup 3)))]
ce71f754 11379 ""
1fd4e8c1
RK		 11380 "*
11381{
11382 int is_bit = ccr_bit (operands[1], 1);
11383 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11384 int count;
11385
9ebbca7d
GK		 11386 /* Force split for non-cc0 compare. */
11387 if (which_alternative == 1)
11388 return \"#\";
11389
1fd4e8c1
RK		 11390 if (is_bit >= put_bit)
11391 count = is_bit - put_bit;
11392 else
11393 count = 32 - (put_bit - is_bit);
11394
89e9f3a8
MM		 11395 operands[5] = GEN_INT (count);
11396 operands[6] = GEN_INT (put_bit);
1fd4e8c1 11397
2c4a9cff 11398 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
1fd4e8c1 11399}"
b19003d8 11400 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 11401 (set_attr "length" "12,16")])
11402
11403(define_split
11404 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11405 (compare:CC
11406 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11407 [(match_operand 2 "cc_reg_operand" "")
11408 (const_int 0)])
11409 (match_operand:SI 3 "const_int_operand" ""))
11410 (const_int 0)))
11411 (set (match_operand:SI 4 "gpc_reg_operand" "")
11412 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11413 (match_dup 3)))]
ce71f754 11414 "reload_completed"
9ebbca7d
GK		 11415 [(set (match_dup 4)
11416 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11417 (match_dup 3)))
11418 (set (match_dup 0)
11419 (compare:CC (match_dup 4)
11420 (const_int 0)))]
11421 "")
1fd4e8c1 11422
c5defebb
RK		 11423;; There is a 3 cycle delay between consecutive mfcr instructions
11424;; so it is useful to combine 2 scc instructions to use only one mfcr.
11425
11426(define_peephole
cd2b37d9 11427 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
c5defebb
RK		 11428 (match_operator:SI 1 "scc_comparison_operator"
11429 [(match_operand 2 "cc_reg_operand" "y")
11430 (const_int 0)]))
cd2b37d9 11431 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
c5defebb
RK		 11432 (match_operator:SI 4 "scc_comparison_operator"
11433 [(match_operand 5 "cc_reg_operand" "y")
11434 (const_int 0)]))]
309323c2 11435 "REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 11436 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 11437 [(set_attr "type" "mfcr")
309323c2 11438 (set_attr "length" "20")])
c5defebb 11439
9ebbca7d
GK		 11440(define_peephole
11441 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11442 (match_operator:DI 1 "scc_comparison_operator"
11443 [(match_operand 2 "cc_reg_operand" "y")
11444 (const_int 0)]))
11445 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11446 (match_operator:DI 4 "scc_comparison_operator"
11447 [(match_operand 5 "cc_reg_operand" "y")
11448 (const_int 0)]))]
309323c2 11449 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 11450 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 11451 [(set_attr "type" "mfcr")
309323c2 11452 (set_attr "length" "20")])
9ebbca7d 11453
1fd4e8c1
RK		 11454;; There are some scc insns that can be done directly, without a compare.
11455;; These are faster because they don't involve the communications between
11456;; the FXU and branch units. In fact, we will be replacing all of the
11457;; integer scc insns here or in the portable methods in emit_store_flag.
11458;;
11459;; Also support (neg (scc ..)) since that construct is used to replace
11460;; branches, (plus (scc ..) ..) since that construct is common and
11461;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11462;; cases where it is no more expensive than (neg (scc ..)).
11463
11464;; Have reload force a constant into a register for the simple insns that
11465;; otherwise won't accept constants. We do this because it is faster than
11466;; the cmp/mfcr sequence we would otherwise generate.
11467
11468(define_insn ""
cd2b37d9
RK		 11469 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11470 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5f59ecb7 11471 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
1fd4e8c1 11472 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
683bdff7 11473 "TARGET_32BIT"
1fd4e8c1 11474 "@
ca7f5001 11475 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
71d2371f 11476 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
ca7f5001
RK		 11477 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11478 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11479 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
b19003d8 11480 [(set_attr "length" "12,8,12,12,12")])
1fd4e8c1 11481
a260abc9
DE		 11482(define_insn ""
11483 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11484 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11485 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11486 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
683bdff7 11487 "TARGET_64BIT"
a260abc9
DE		 11488 "@
11489 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11490 subfic %3,%1,0\;adde %0,%3,%1
11491 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11492 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11493 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11494 [(set_attr "length" "12,8,12,12,12")])
11495
1fd4e8c1 11496(define_insn ""
9ebbca7d 11497 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 11498 (compare:CC
9ebbca7d
GK		 11499 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11500 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
1fd4e8c1 11501 (const_int 0)))
9ebbca7d 11502 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
1fd4e8c1 11503 (eq:SI (match_dup 1) (match_dup 2)))
9ebbca7d 11504 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
683bdff7 11505 "TARGET_32BIT"
1fd4e8c1 11506 "@
ca7f5001
RK		 11507 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11508 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11509 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11510 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
9ebbca7d
GK		 11511 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11512 #
11513 #
11514 #
11515 #
11516 #"
b19003d8 11517 [(set_attr "type" "compare")
9ebbca7d
GK		 11518 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11519
11520(define_split
11521 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11522 (compare:CC
11523 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11524 (match_operand:SI 2 "reg_or_cint_operand" ""))
11525 (const_int 0)))
11526 (set (match_operand:SI 0 "gpc_reg_operand" "")
11527 (eq:SI (match_dup 1) (match_dup 2)))
11528 (clobber (match_scratch:SI 3 ""))]
683bdff7 11529 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 11530 [(parallel [(set (match_dup 0)
11531 (eq:SI (match_dup 1) (match_dup 2)))
11532 (clobber (match_dup 3))])
11533 (set (match_dup 4)
11534 (compare:CC (match_dup 0)
11535 (const_int 0)))]
11536 "")
b19003d8 11537
a260abc9 11538(define_insn ""
9ebbca7d 11539 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
a260abc9 11540 (compare:CC
9ebbca7d
GK		 11541 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11542 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
a260abc9 11543 (const_int 0)))
9ebbca7d 11544 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
a260abc9 11545 (eq:DI (match_dup 1) (match_dup 2)))
9ebbca7d 11546 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
683bdff7 11547 "TARGET_64BIT"
a260abc9
DE		 11548 "@
11549 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11550 subfic %3,%1,0\;adde. %0,%3,%1
11551 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11552 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
9ebbca7d
GK		 11553 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11554 #
11555 #
11556 #
11557 #
11558 #"
a260abc9 11559 [(set_attr "type" "compare")
9ebbca7d
GK		 11560 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11561
11562(define_split
11563 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11564 (compare:CC
11565 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11566 (match_operand:DI 2 "reg_or_cint_operand" ""))
11567 (const_int 0)))
11568 (set (match_operand:DI 0 "gpc_reg_operand" "")
11569 (eq:DI (match_dup 1) (match_dup 2)))
11570 (clobber (match_scratch:DI 3 ""))]
683bdff7 11571 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 11572 [(parallel [(set (match_dup 0)
11573 (eq:DI (match_dup 1) (match_dup 2)))
11574 (clobber (match_dup 3))])
11575 (set (match_dup 4)
11576 (compare:CC (match_dup 0)
11577 (const_int 0)))]
11578 "")
a260abc9 11579
b19003d8
RK		 11580;; We have insns of the form shown by the first define_insn below. If
11581;; there is something inside the comparison operation, we must split it.
11582(define_split
11583 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11584 (plus:SI (match_operator 1 "comparison_operator"
11585 [(match_operand:SI 2 "" "")
11586 (match_operand:SI 3
11587 "reg_or_cint_operand" "")])
11588 (match_operand:SI 4 "gpc_reg_operand" "")))
11589 (clobber (match_operand:SI 5 "register_operand" ""))]
11590 "! gpc_reg_operand (operands[2], SImode)"
11591 [(set (match_dup 5) (match_dup 2))
11592 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11593 (match_dup 4)))])
1fd4e8c1
RK		 11594
11595(define_insn ""
5276df18 11596 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
cd2b37d9 11597 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5f59ecb7 11598 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
5276df18 11599 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
683bdff7 11600 "TARGET_32BIT"
1fd4e8c1 11601 "@
5276df18
DE		 11602 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11603 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11604 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11605 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11606 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
b19003d8 11607 [(set_attr "length" "12,8,12,12,12")])
1fd4e8c1
RK		 11608
11609(define_insn ""
9ebbca7d 11610 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 11611 (compare:CC
1fd4e8c1 11612 (plus:SI
9ebbca7d
GK		 11613 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11614 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11615 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 11616 (const_int 0)))
9ebbca7d 11617 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
683bdff7 11618 "TARGET_32BIT"
1fd4e8c1 11619 "@
ca7f5001 11620 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
19378cf8 11621 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
ca7f5001
RK		 11622 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11623 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 11624 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11625 #
11626 #
11627 #
11628 #
11629 #"
b19003d8 11630 [(set_attr "type" "compare")
9ebbca7d
GK		 11631 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11632
11633(define_split
11634 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11635 (compare:CC
11636 (plus:SI
11637 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11638 (match_operand:SI 2 "reg_or_cint_operand" ""))
11639 (match_operand:SI 3 "gpc_reg_operand" ""))
11640 (const_int 0)))
11641 (clobber (match_scratch:SI 4 ""))]
683bdff7 11642 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 11643 [(set (match_dup 4)
11644 (plus:SI (eq:SI (match_dup 1)
11645 (match_dup 2))
11646 (match_dup 3)))
11647 (set (match_dup 0)
11648 (compare:CC (match_dup 4)
11649 (const_int 0)))]
11650 "")
1fd4e8c1
RK		 11651
11652(define_insn ""
0387639b 11653 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 11654 (compare:CC
1fd4e8c1 11655 (plus:SI
9ebbca7d
GK		 11656 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11657 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11658 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 11659 (const_int 0)))
0387639b
DE		 11660 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
11661 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 11662 "TARGET_32BIT"
1fd4e8c1 11663 "@
0387639b
DE		 11664 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11665 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
11666 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11667 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
11668 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 11669 #
11670 #
11671 #
11672 #
11673 #"
11674 [(set_attr "type" "compare")
11675 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11676
11677(define_split
0387639b 11678 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 11679 (compare:CC
11680 (plus:SI
11681 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11682 (match_operand:SI 2 "reg_or_cint_operand" ""))
11683 (match_operand:SI 3 "gpc_reg_operand" ""))
11684 (const_int 0)))
11685 (set (match_operand:SI 0 "gpc_reg_operand" "")
0387639b 11686 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 11687 "TARGET_32BIT && reload_completed"
0387639b 11688 [(set (match_dup 0)
9ebbca7d 11689 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
0387639b 11690 (set (match_dup 4)
9ebbca7d
GK		 11691 (compare:CC (match_dup 0)
11692 (const_int 0)))]
11693 "")
11694
1fd4e8c1 11695(define_insn ""
cd2b37d9 11696 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
deb9225a 11697 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5f59ecb7 11698 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
683bdff7 11699 "TARGET_32BIT"
1fd4e8c1 11700 "@
ca7f5001
RK		 11701 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11702 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11703 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11704 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11705 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 11706 [(set_attr "length" "12,8,12,12,12")])
1fd4e8c1 11707
ea9be077
MM		 11708;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11709;; since it nabs/sr is just as fast.
463b558b 11710(define_insn "*ne0"
b4e95693 11711 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
ea9be077
MM		 11712 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11713 (const_int 31)))
11714 (clobber (match_scratch:SI 2 "=&r"))]
683bdff7 11715 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
ea9be077
MM		 11716 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11717 [(set_attr "length" "8")])
11718
a260abc9
DE		 11719(define_insn ""
11720 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11721 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11722 (const_int 63)))
11723 (clobber (match_scratch:DI 2 "=&r"))]
683bdff7 11724 "TARGET_64BIT"
a260abc9
DE		 11725 "addic %2,%1,-1\;subfe %0,%2,%1"
11726 [(set_attr "length" "8")])
11727
1fd4e8c1
RK		 11728;; This is what (plus (ne X (const_int 0)) Y) looks like.
11729(define_insn ""
cd2b37d9 11730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 11731 (plus:SI (lshiftrt:SI
cd2b37d9 11732 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1fd4e8c1 11733 (const_int 31))
cd2b37d9 11734 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1 11735 (clobber (match_scratch:SI 3 "=&r"))]
683bdff7 11736 "TARGET_32BIT"
ca7f5001 11737 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
b19003d8 11738 [(set_attr "length" "8")])
1fd4e8c1 11739
a260abc9
DE		 11740(define_insn ""
11741 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11742 (plus:DI (lshiftrt:DI
11743 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11744 (const_int 63))
11745 (match_operand:DI 2 "gpc_reg_operand" "r")))
11746 (clobber (match_scratch:DI 3 "=&r"))]
683bdff7 11747 "TARGET_64BIT"
a260abc9
DE		 11748 "addic %3,%1,-1\;addze %0,%2"
11749 [(set_attr "length" "8")])
11750
1fd4e8c1 11751(define_insn ""
9ebbca7d 11752 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 11753 (compare:CC
11754 (plus:SI (lshiftrt:SI
9ebbca7d 11755 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 11756 (const_int 31))
9ebbca7d 11757 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 11758 (const_int 0)))
889b90a1
GK		 11759 (clobber (match_scratch:SI 3 "=&r,&r"))
11760 (clobber (match_scratch:SI 4 "=X,&r"))]
683bdff7 11761 "TARGET_32BIT"
9ebbca7d
GK		 11762 "@
11763 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11764 #"
b19003d8 11765 [(set_attr "type" "compare")
9ebbca7d
GK		 11766 (set_attr "length" "8,12")])
11767
11768(define_split
11769 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11770 (compare:CC
11771 (plus:SI (lshiftrt:SI
11772 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11773 (const_int 31))
11774 (match_operand:SI 2 "gpc_reg_operand" ""))
11775 (const_int 0)))
889b90a1
GK		 11776 (clobber (match_scratch:SI 3 ""))
11777 (clobber (match_scratch:SI 4 ""))]
683bdff7 11778 "TARGET_32BIT && reload_completed"
889b90a1 11779 [(parallel [(set (match_dup 3)
ce71f754
AM		 11780 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
11781 (const_int 31))
11782 (match_dup 2)))
889b90a1 11783 (clobber (match_dup 4))])
9ebbca7d
GK		 11784 (set (match_dup 0)
11785 (compare:CC (match_dup 3)
11786 (const_int 0)))]
11787 "")
1fd4e8c1 11788
a260abc9 11789(define_insn ""
9ebbca7d 11790 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 11791 (compare:CC
11792 (plus:DI (lshiftrt:DI
9ebbca7d 11793 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 11794 (const_int 63))
9ebbca7d 11795 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 11796 (const_int 0)))
9ebbca7d 11797 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 11798 "TARGET_64BIT"
9ebbca7d
GK		 11799 "@
11800 addic %3,%1,-1\;addze. %3,%2
11801 #"
a260abc9 11802 [(set_attr "type" "compare")
9ebbca7d
GK		 11803 (set_attr "length" "8,12")])
11804
11805(define_split
11806 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11807 (compare:CC
11808 (plus:DI (lshiftrt:DI
11809 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11810 (const_int 63))
11811 (match_operand:DI 2 "gpc_reg_operand" ""))
11812 (const_int 0)))
11813 (clobber (match_scratch:DI 3 ""))]
683bdff7 11814 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 11815 [(set (match_dup 3)
11816 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
11817 (const_int 63))
11818 (match_dup 2)))
11819 (set (match_dup 0)
11820 (compare:CC (match_dup 3)
11821 (const_int 0)))]
11822 "")
a260abc9 11823
1fd4e8c1 11824(define_insn ""
9ebbca7d 11825 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 11826 (compare:CC
11827 (plus:SI (lshiftrt:SI
9ebbca7d 11828 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 11829 (const_int 31))
9ebbca7d 11830 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 11831 (const_int 0)))
9ebbca7d 11832 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 11833 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11834 (match_dup 2)))
9ebbca7d 11835 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 11836 "TARGET_32BIT"
9ebbca7d
GK		 11837 "@
11838 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11839 #"
b19003d8 11840 [(set_attr "type" "compare")
9ebbca7d
GK		 11841 (set_attr "length" "8,12")])
11842
11843(define_split
11844 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11845 (compare:CC
11846 (plus:SI (lshiftrt:SI
11847 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11848 (const_int 31))
11849 (match_operand:SI 2 "gpc_reg_operand" ""))
11850 (const_int 0)))
11851 (set (match_operand:SI 0 "gpc_reg_operand" "")
11852 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11853 (match_dup 2)))
11854 (clobber (match_scratch:SI 3 ""))]
683bdff7 11855 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 11856 [(parallel [(set (match_dup 0)
11857 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11858 (match_dup 2)))
11859 (clobber (match_dup 3))])
11860 (set (match_dup 4)
11861 (compare:CC (match_dup 0)
11862 (const_int 0)))]
11863 "")
1fd4e8c1 11864
a260abc9 11865(define_insn ""
9ebbca7d 11866 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9
DE		 11867 (compare:CC
11868 (plus:DI (lshiftrt:DI
9ebbca7d 11869 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 11870 (const_int 63))
9ebbca7d 11871 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 11872 (const_int 0)))
9ebbca7d 11873 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 11874 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11875 (match_dup 2)))
9ebbca7d 11876 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 11877 "TARGET_64BIT"
9ebbca7d
GK		 11878 "@
11879 addic %3,%1,-1\;addze. %0,%2
11880 #"
a260abc9 11881 [(set_attr "type" "compare")
9ebbca7d
GK		 11882 (set_attr "length" "8,12")])
11883
11884(define_split
11885 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11886 (compare:CC
11887 (plus:DI (lshiftrt:DI
11888 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11889 (const_int 63))
11890 (match_operand:DI 2 "gpc_reg_operand" ""))
11891 (const_int 0)))
11892 (set (match_operand:DI 0 "gpc_reg_operand" "")
11893 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11894 (match_dup 2)))
11895 (clobber (match_scratch:DI 3 ""))]
683bdff7 11896 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 11897 [(parallel [(set (match_dup 0)
11898 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11899 (match_dup 2)))
11900 (clobber (match_dup 3))])
11901 (set (match_dup 4)
11902 (compare:CC (match_dup 0)
11903 (const_int 0)))]
11904 "")
a260abc9 11905
1fd4e8c1 11906(define_insn ""
cd2b37d9
RK		 11907 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11908 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 11909 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11910 (clobber (match_scratch:SI 3 "=r,X"))]
ca7f5001 11911 "TARGET_POWER"
1fd4e8c1 11912 "@
ca7f5001 11913 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
7f340546 11914 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 11915 [(set_attr "length" "12")])
1fd4e8c1
RK		 11916
11917(define_insn ""
9ebbca7d 11918 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 11919 (compare:CC
9ebbca7d
GK		 11920 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11921 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
1fd4e8c1 11922 (const_int 0)))
9ebbca7d 11923 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 11924 (le:SI (match_dup 1) (match_dup 2)))
9ebbca7d 11925 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
ca7f5001 11926 "TARGET_POWER"
1fd4e8c1 11927 "@
ca7f5001 11928 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
9ebbca7d
GK		 11929 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11930 #
11931 #"
11932 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
11933 (set_attr "length" "12,12,16,16")])
11934
11935(define_split
11936 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11937 (compare:CC
11938 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11939 (match_operand:SI 2 "reg_or_short_operand" ""))
11940 (const_int 0)))
11941 (set (match_operand:SI 0 "gpc_reg_operand" "")
11942 (le:SI (match_dup 1) (match_dup 2)))
11943 (clobber (match_scratch:SI 3 ""))]
11944 "TARGET_POWER && reload_completed"
11945 [(parallel [(set (match_dup 0)
11946 (le:SI (match_dup 1) (match_dup 2)))
11947 (clobber (match_dup 3))])
11948 (set (match_dup 4)
11949 (compare:CC (match_dup 0)
11950 (const_int 0)))]
11951 "")
1fd4e8c1
RK		 11952
11953(define_insn ""
097657c3 11954 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
cd2b37d9 11955 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 11956 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
097657c3 11957 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
ca7f5001 11958 "TARGET_POWER"
1fd4e8c1 11959 "@
097657c3
AM		 11960 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11961 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
b19003d8 11962 [(set_attr "length" "12")])
1fd4e8c1
RK		 11963
11964(define_insn ""
9ebbca7d 11965 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 11966 (compare:CC
9ebbca7d
GK		 11967 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11968 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11969 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 11970 (const_int 0)))
9ebbca7d 11971 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
ca7f5001 11972 "TARGET_POWER"
1fd4e8c1 11973 "@
ca7f5001 11974 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 11975 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11976 #
11977 #"
b19003d8 11978 [(set_attr "type" "compare")
9ebbca7d
GK		 11979 (set_attr "length" "12,12,16,16")])
11980
11981(define_split
11982 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11983 (compare:CC
11984 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
11985 (match_operand:SI 2 "reg_or_short_operand" ""))
11986 (match_operand:SI 3 "gpc_reg_operand" ""))
11987 (const_int 0)))
11988 (clobber (match_scratch:SI 4 ""))]
11989 "TARGET_POWER && reload_completed"
11990 [(set (match_dup 4)
11991 (plus:SI (le:SI (match_dup 1) (match_dup 2))
097657c3 11992 (match_dup 3)))
9ebbca7d
GK		 11993 (set (match_dup 0)
11994 (compare:CC (match_dup 4)
11995 (const_int 0)))]
11996 "")
1fd4e8c1
RK		 11997
11998(define_insn ""
097657c3 11999 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12000 (compare:CC
9ebbca7d
GK		 12001 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12002 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12003 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12004 (const_int 0)))
097657c3
AM		 12005 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12006 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12007 "TARGET_POWER"
1fd4e8c1 12008 "@
097657c3
AM		 12009 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12010 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12011 #
12012 #"
b19003d8 12013 [(set_attr "type" "compare")
9ebbca7d
GK		 12014 (set_attr "length" "12,12,16,16")])
12015
12016(define_split
097657c3 12017 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12018 (compare:CC
12019 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12020 (match_operand:SI 2 "reg_or_short_operand" ""))
12021 (match_operand:SI 3 "gpc_reg_operand" ""))
12022 (const_int 0)))
12023 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12024 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12025 "TARGET_POWER && reload_completed"
097657c3 12026 [(set (match_dup 0)
9ebbca7d 12027 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12028 (set (match_dup 4)
9ebbca7d
GK		 12029 (compare:CC (match_dup 0)
12030 (const_int 0)))]
12031 "")
1fd4e8c1
RK		 12032
12033(define_insn ""
cd2b37d9
RK		 12034 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12035 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12036 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
ca7f5001 12037 "TARGET_POWER"
1fd4e8c1 12038 "@
ca7f5001
RK		 12039 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12040 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 12041 [(set_attr "length" "12")])
1fd4e8c1
RK		 12042
12043(define_insn ""
cd2b37d9
RK		 12044 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12045 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12046 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
4b8a63d6 12047 "TARGET_32BIT"
ca7f5001 12048 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
b19003d8 12049 [(set_attr "length" "12")])
1fd4e8c1 12050
f9562f27
DE		 12051(define_insn ""
12052 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12053 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12054 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
683bdff7 12055 "TARGET_64BIT"
f9562f27
DE		 12056 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12057 [(set_attr "length" "12")])
12058
12059(define_insn ""
9ebbca7d 12060 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 12061 (compare:CC
9ebbca7d
GK		 12062 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12063 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
f9562f27 12064 (const_int 0)))
9ebbca7d 12065 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
f9562f27 12066 (leu:DI (match_dup 1) (match_dup 2)))]
683bdff7 12067 "TARGET_64BIT"
9ebbca7d
GK		 12068 "@
12069 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12070 #"
f9562f27 12071 [(set_attr "type" "compare")
9ebbca7d
GK		 12072 (set_attr "length" "12,16")])
12073
12074(define_split
12075 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12076 (compare:CC
12077 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12078 (match_operand:DI 2 "reg_or_short_operand" ""))
12079 (const_int 0)))
12080 (set (match_operand:DI 0 "gpc_reg_operand" "")
12081 (leu:DI (match_dup 1) (match_dup 2)))]
683bdff7 12082 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12083 [(set (match_dup 0)
12084 (leu:DI (match_dup 1) (match_dup 2)))
12085 (set (match_dup 3)
12086 (compare:CC (match_dup 0)
12087 (const_int 0)))]
12088 "")
f9562f27 12089
1fd4e8c1 12090(define_insn ""
9ebbca7d 12091 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 12092 (compare:CC
9ebbca7d
GK		 12093 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12094 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12095 (const_int 0)))
9ebbca7d 12096 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 12097 (leu:SI (match_dup 1) (match_dup 2)))]
683bdff7 12098 "TARGET_32BIT"
9ebbca7d
GK		 12099 "@
12100 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12101 #"
b19003d8 12102 [(set_attr "type" "compare")
9ebbca7d
GK		 12103 (set_attr "length" "12,16")])
12104
12105(define_split
12106 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12107 (compare:CC
12108 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12109 (match_operand:SI 2 "reg_or_short_operand" ""))
12110 (const_int 0)))
12111 (set (match_operand:SI 0 "gpc_reg_operand" "")
12112 (leu:SI (match_dup 1) (match_dup 2)))]
683bdff7 12113 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12114 [(set (match_dup 0)
12115 (leu:SI (match_dup 1) (match_dup 2)))
12116 (set (match_dup 3)
12117 (compare:CC (match_dup 0)
12118 (const_int 0)))]
12119 "")
1fd4e8c1
RK		 12120
12121(define_insn ""
80103f96 12122 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 12123 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12124 (match_operand:SI 2 "reg_or_short_operand" "rI"))
80103f96 12125 (match_operand:SI 3 "gpc_reg_operand" "r")))]
683bdff7 12126 "TARGET_32BIT"
80103f96 12127 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
b19003d8 12128 [(set_attr "length" "8")])
1fd4e8c1
RK		 12129
12130(define_insn ""
9ebbca7d 12131 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12132 (compare:CC
9ebbca7d
GK		 12133 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12134 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12135 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12136 (const_int 0)))
9ebbca7d 12137 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12138 "TARGET_32BIT"
9ebbca7d
GK		 12139 "@
12140 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12141 #"
b19003d8 12142 [(set_attr "type" "compare")
9ebbca7d
GK		 12143 (set_attr "length" "8,12")])
12144
12145(define_split
12146 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12147 (compare:CC
12148 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12149 (match_operand:SI 2 "reg_or_short_operand" ""))
12150 (match_operand:SI 3 "gpc_reg_operand" ""))
12151 (const_int 0)))
12152 (clobber (match_scratch:SI 4 ""))]
683bdff7 12153 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12154 [(set (match_dup 4)
12155 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12156 (match_dup 3)))
12157 (set (match_dup 0)
12158 (compare:CC (match_dup 4)
12159 (const_int 0)))]
12160 "")
1fd4e8c1
RK		 12161
12162(define_insn ""
097657c3 12163 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12164 (compare:CC
9ebbca7d
GK		 12165 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12166 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12167 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12168 (const_int 0)))
097657c3
AM		 12169 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12170 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12171 "TARGET_32BIT"
9ebbca7d 12172 "@
097657c3 12173 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
9ebbca7d 12174 #"
b19003d8 12175 [(set_attr "type" "compare")
9ebbca7d
GK		 12176 (set_attr "length" "8,12")])
12177
12178(define_split
097657c3 12179 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12180 (compare:CC
12181 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12182 (match_operand:SI 2 "reg_or_short_operand" ""))
12183 (match_operand:SI 3 "gpc_reg_operand" ""))
12184 (const_int 0)))
12185 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12186 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12187 "TARGET_32BIT && reload_completed"
097657c3 12188 [(set (match_dup 0)
9ebbca7d 12189 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12190 (set (match_dup 4)
9ebbca7d
GK		 12191 (compare:CC (match_dup 0)
12192 (const_int 0)))]
12193 "")
1fd4e8c1
RK		 12194
12195(define_insn ""
cd2b37d9
RK		 12196 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12197 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12198 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
683bdff7 12199 "TARGET_32BIT"
ca7f5001 12200 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
b19003d8 12201 [(set_attr "length" "12")])
1fd4e8c1
RK		 12202
12203(define_insn ""
097657c3 12204 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
1fd4e8c1 12205 (and:SI (neg:SI
cd2b37d9 12206 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12207 (match_operand:SI 2 "reg_or_short_operand" "rI")))
097657c3 12208 (match_operand:SI 3 "gpc_reg_operand" "r")))]
683bdff7 12209 "TARGET_32BIT"
097657c3 12210 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
b19003d8 12211 [(set_attr "length" "12")])
1fd4e8c1
RK		 12212
12213(define_insn ""
9ebbca7d 12214 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12215 (compare:CC
12216 (and:SI (neg:SI
9ebbca7d
GK		 12217 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12218 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12219 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12220 (const_int 0)))
9ebbca7d 12221 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12222 "TARGET_32BIT"
9ebbca7d
GK		 12223 "@
12224 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12225 #"
12226 [(set_attr "type" "compare")
12227 (set_attr "length" "12,16")])
12228
12229(define_split
12230 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12231 (compare:CC
12232 (and:SI (neg:SI
12233 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12234 (match_operand:SI 2 "reg_or_short_operand" "")))
12235 (match_operand:SI 3 "gpc_reg_operand" ""))
12236 (const_int 0)))
12237 (clobber (match_scratch:SI 4 ""))]
683bdff7 12238 "TARGET_32BIT && reload_completed"
9ebbca7d 12239 [(set (match_dup 4)
097657c3
AM		 12240 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12241 (match_dup 3)))
9ebbca7d
GK		 12242 (set (match_dup 0)
12243 (compare:CC (match_dup 4)
12244 (const_int 0)))]
12245 "")
1fd4e8c1
RK		 12246
12247(define_insn ""
097657c3 12248 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12249 (compare:CC
12250 (and:SI (neg:SI
9ebbca7d
GK		 12251 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12252 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12253 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12254 (const_int 0)))
097657c3
AM		 12255 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12256 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 12257 "TARGET_32BIT"
9ebbca7d 12258 "@
097657c3 12259 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d 12260 #"
b19003d8 12261 [(set_attr "type" "compare")
9ebbca7d
GK		 12262 (set_attr "length" "12,16")])
12263
12264(define_split
097657c3 12265 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12266 (compare:CC
12267 (and:SI (neg:SI
12268 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12269 (match_operand:SI 2 "reg_or_short_operand" "")))
12270 (match_operand:SI 3 "gpc_reg_operand" ""))
12271 (const_int 0)))
12272 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12273 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 12274 "TARGET_32BIT && reload_completed"
097657c3
AM		 12275 [(set (match_dup 0)
12276 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12277 (match_dup 3)))
12278 (set (match_dup 4)
9ebbca7d
GK		 12279 (compare:CC (match_dup 0)
12280 (const_int 0)))]
12281 "")
1fd4e8c1
RK		 12282
12283(define_insn ""
cd2b37d9
RK		 12284 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12285 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12286 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
ca7f5001 12287 "TARGET_POWER"
7f340546 12288 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12289 [(set_attr "length" "12")])
1fd4e8c1
RK		 12290
12291(define_insn ""
9ebbca7d 12292 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 12293 (compare:CC
9ebbca7d
GK		 12294 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12295 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12296 (const_int 0)))
9ebbca7d 12297 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 12298 (lt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 12299 "TARGET_POWER"
9ebbca7d
GK		 12300 "@
12301 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12302 #"
29ae5b89 12303 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 12304 (set_attr "length" "12,16")])
12305
12306(define_split
12307 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12308 (compare:CC
12309 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12310 (match_operand:SI 2 "reg_or_short_operand" ""))
12311 (const_int 0)))
12312 (set (match_operand:SI 0 "gpc_reg_operand" "")
12313 (lt:SI (match_dup 1) (match_dup 2)))]
12314 "TARGET_POWER && reload_completed"
12315 [(set (match_dup 0)
12316 (lt:SI (match_dup 1) (match_dup 2)))
12317 (set (match_dup 3)
12318 (compare:CC (match_dup 0)
12319 (const_int 0)))]
12320 "")
1fd4e8c1
RK		 12321
12322(define_insn ""
097657c3 12323 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 12324 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12325 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 12326 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 12327 "TARGET_POWER"
097657c3 12328 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 12329 [(set_attr "length" "12")])
1fd4e8c1
RK		 12330
12331(define_insn ""
9ebbca7d 12332 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12333 (compare:CC
9ebbca7d
GK		 12334 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12335 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12336 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12337 (const_int 0)))
9ebbca7d 12338 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 12339 "TARGET_POWER"
9ebbca7d
GK		 12340 "@
12341 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12342 #"
b19003d8 12343 [(set_attr "type" "compare")
9ebbca7d
GK		 12344 (set_attr "length" "12,16")])
12345
12346(define_split
12347 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12348 (compare:CC
12349 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12350 (match_operand:SI 2 "reg_or_short_operand" ""))
12351 (match_operand:SI 3 "gpc_reg_operand" ""))
12352 (const_int 0)))
12353 (clobber (match_scratch:SI 4 ""))]
12354 "TARGET_POWER && reload_completed"
12355 [(set (match_dup 4)
12356 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
097657c3 12357 (match_dup 3)))
9ebbca7d
GK		 12358 (set (match_dup 0)
12359 (compare:CC (match_dup 4)
12360 (const_int 0)))]
12361 "")
1fd4e8c1
RK		 12362
12363(define_insn ""
097657c3 12364 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12365 (compare:CC
9ebbca7d
GK		 12366 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12367 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12368 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12369 (const_int 0)))
097657c3
AM		 12370 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12371 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12372 "TARGET_POWER"
9ebbca7d 12373 "@
097657c3 12374 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 12375 #"
b19003d8 12376 [(set_attr "type" "compare")
9ebbca7d
GK		 12377 (set_attr "length" "12,16")])
12378
12379(define_split
097657c3 12380 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12381 (compare:CC
12382 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12383 (match_operand:SI 2 "reg_or_short_operand" ""))
12384 (match_operand:SI 3 "gpc_reg_operand" ""))
12385 (const_int 0)))
12386 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12387 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12388 "TARGET_POWER && reload_completed"
097657c3 12389 [(set (match_dup 0)
9ebbca7d 12390 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12391 (set (match_dup 4)
9ebbca7d
GK		 12392 (compare:CC (match_dup 0)
12393 (const_int 0)))]
12394 "")
1fd4e8c1
RK		 12395
12396(define_insn ""
cd2b37d9
RK		 12397 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12398 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12399 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 12400 "TARGET_POWER"
12401 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 12402 [(set_attr "length" "12")])
1fd4e8c1
RK		 12403
12404(define_insn ""
cd2b37d9
RK		 12405 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12406 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12407 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
683bdff7 12408 "TARGET_32BIT"
1fd4e8c1 12409 "@
ca7f5001
RK		 12410 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
12411 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
b19003d8 12412 [(set_attr "length" "12")])
1fd4e8c1
RK		 12413
12414(define_insn ""
9ebbca7d 12415 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12416 (compare:CC
9ebbca7d
GK		 12417 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12418 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 12419 (const_int 0)))
9ebbca7d 12420 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 12421 (ltu:SI (match_dup 1) (match_dup 2)))]
683bdff7 12422 "TARGET_32BIT"
1fd4e8c1 12423 "@
ca7f5001 12424 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
9ebbca7d
GK		 12425 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12426 #
12427 #"
b19003d8 12428 [(set_attr "type" "compare")
9ebbca7d
GK		 12429 (set_attr "length" "12,12,16,16")])
12430
12431(define_split
12432 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12433 (compare:CC
12434 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12435 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12436 (const_int 0)))
12437 (set (match_operand:SI 0 "gpc_reg_operand" "")
12438 (ltu:SI (match_dup 1) (match_dup 2)))]
683bdff7 12439 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12440 [(set (match_dup 0)
12441 (ltu:SI (match_dup 1) (match_dup 2)))
12442 (set (match_dup 3)
12443 (compare:CC (match_dup 0)
12444 (const_int 0)))]
12445 "")
1fd4e8c1
RK		 12446
12447(define_insn ""
80103f96 12448 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
19378cf8
MM		 12449 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12450 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
80103f96 12451 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
683bdff7 12452 "TARGET_32BIT"
1fd4e8c1 12453 "@
80103f96
FS		 12454 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
12455 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
b19003d8 12456 [(set_attr "length" "12")])
1fd4e8c1
RK		 12457
12458(define_insn ""
9ebbca7d 12459 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12460 (compare:CC
9ebbca7d
GK		 12461 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12462 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12463 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12464 (const_int 0)))
9ebbca7d 12465 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 12466 "TARGET_32BIT"
1fd4e8c1 12467 "@
ca7f5001 12468 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
9ebbca7d
GK		 12469 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12470 #
12471 #"
b19003d8 12472 [(set_attr "type" "compare")
9ebbca7d
GK		 12473 (set_attr "length" "12,12,16,16")])
12474
12475(define_split
12476 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12477 (compare:CC
12478 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12479 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12480 (match_operand:SI 3 "gpc_reg_operand" ""))
12481 (const_int 0)))
12482 (clobber (match_scratch:SI 4 ""))]
683bdff7 12483 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12484 [(set (match_dup 4)
12485 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
097657c3 12486 (match_dup 3)))
9ebbca7d
GK		 12487 (set (match_dup 0)
12488 (compare:CC (match_dup 4)
12489 (const_int 0)))]
12490 "")
1fd4e8c1
RK		 12491
12492(define_insn ""
097657c3 12493 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12494 (compare:CC
9ebbca7d
GK		 12495 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12496 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12497 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12498 (const_int 0)))
097657c3
AM		 12499 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12500 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12501 "TARGET_32BIT"
1fd4e8c1 12502 "@
097657c3
AM		 12503 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12504 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
9ebbca7d
GK		 12505 #
12506 #"
b19003d8 12507 [(set_attr "type" "compare")
9ebbca7d
GK		 12508 (set_attr "length" "12,12,16,16")])
12509
12510(define_split
097657c3 12511 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12512 (compare:CC
12513 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12514 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12515 (match_operand:SI 3 "gpc_reg_operand" ""))
12516 (const_int 0)))
12517 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12518 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12519 "TARGET_32BIT && reload_completed"
097657c3 12520 [(set (match_dup 0)
9ebbca7d 12521 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12522 (set (match_dup 4)
9ebbca7d
GK		 12523 (compare:CC (match_dup 0)
12524 (const_int 0)))]
12525 "")
1fd4e8c1
RK		 12526
12527(define_insn ""
cd2b37d9
RK		 12528 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12529 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12530 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
683bdff7 12531 "TARGET_32BIT"
1fd4e8c1 12532 "@
ca7f5001
RK		 12533 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12534 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
b19003d8 12535 [(set_attr "length" "8")])
1fd4e8c1
RK		 12536
12537(define_insn ""
cd2b37d9
RK		 12538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12539 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 12540 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12541 (clobber (match_scratch:SI 3 "=r"))]
ca7f5001
RK		 12542 "TARGET_POWER"
12543 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
b19003d8 12544 [(set_attr "length" "12")])
1fd4e8c1 12545
9ebbca7d
GK		 12546(define_insn ""
12547 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12548 (compare:CC
9ebbca7d
GK		 12549 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12550 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12551 (const_int 0)))
9ebbca7d 12552 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 12553 (ge:SI (match_dup 1) (match_dup 2)))
9ebbca7d 12554 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 12555 "TARGET_POWER"
9ebbca7d
GK		 12556 "@
12557 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12558 #"
12559 [(set_attr "type" "compare")
12560 (set_attr "length" "12,16")])
12561
12562(define_split
12563 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12564 (compare:CC
12565 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12566 (match_operand:SI 2 "reg_or_short_operand" ""))
12567 (const_int 0)))
12568 (set (match_operand:SI 0 "gpc_reg_operand" "")
12569 (ge:SI (match_dup 1) (match_dup 2)))
12570 (clobber (match_scratch:SI 3 ""))]
12571 "TARGET_POWER && reload_completed"
12572 [(parallel [(set (match_dup 0)
097657c3
AM		 12573 (ge:SI (match_dup 1) (match_dup 2)))
12574 (clobber (match_dup 3))])
9ebbca7d
GK		 12575 (set (match_dup 4)
12576 (compare:CC (match_dup 0)
12577 (const_int 0)))]
12578 "")
12579
1fd4e8c1 12580(define_insn ""
097657c3 12581 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 12582 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12583 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 12584 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 12585 "TARGET_POWER"
097657c3 12586 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
b19003d8 12587 [(set_attr "length" "12")])
1fd4e8c1
RK		 12588
12589(define_insn ""
9ebbca7d 12590 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12591 (compare:CC
9ebbca7d
GK		 12592 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12593 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12594 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12595 (const_int 0)))
9ebbca7d 12596 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 12597 "TARGET_POWER"
9ebbca7d
GK		 12598 "@
12599 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12600 #"
b19003d8 12601 [(set_attr "type" "compare")
9ebbca7d
GK		 12602 (set_attr "length" "12,16")])
12603
12604(define_split
12605 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12606 (compare:CC
12607 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12608 (match_operand:SI 2 "reg_or_short_operand" ""))
12609 (match_operand:SI 3 "gpc_reg_operand" ""))
12610 (const_int 0)))
12611 (clobber (match_scratch:SI 4 ""))]
12612 "TARGET_POWER && reload_completed"
12613 [(set (match_dup 4)
12614 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
097657c3 12615 (match_dup 3)))
9ebbca7d
GK		 12616 (set (match_dup 0)
12617 (compare:CC (match_dup 4)
12618 (const_int 0)))]
12619 "")
1fd4e8c1
RK		 12620
12621(define_insn ""
097657c3 12622 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12623 (compare:CC
9ebbca7d
GK		 12624 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12625 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12626 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12627 (const_int 0)))
097657c3
AM		 12628 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12629 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12630 "TARGET_POWER"
9ebbca7d 12631 "@
097657c3 12632 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d 12633 #"
b19003d8 12634 [(set_attr "type" "compare")
9ebbca7d
GK		 12635 (set_attr "length" "12,16")])
12636
12637(define_split
097657c3 12638 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12639 (compare:CC
12640 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12641 (match_operand:SI 2 "reg_or_short_operand" ""))
12642 (match_operand:SI 3 "gpc_reg_operand" ""))
12643 (const_int 0)))
12644 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12645 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12646 "TARGET_POWER && reload_completed"
097657c3 12647 [(set (match_dup 0)
9ebbca7d 12648 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12649 (set (match_dup 4)
9ebbca7d
GK		 12650 (compare:CC (match_dup 0)
12651 (const_int 0)))]
12652 "")
1fd4e8c1
RK		 12653
12654(define_insn ""
cd2b37d9
RK		 12655 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12656 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12657 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 12658 "TARGET_POWER"
12659 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 12660 [(set_attr "length" "12")])
1fd4e8c1 12661
1fd4e8c1 12662(define_insn ""
cd2b37d9
RK		 12663 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12664 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12665 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
683bdff7 12666 "TARGET_32BIT"
1fd4e8c1 12667 "@
ca7f5001
RK		 12668 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12669 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
b19003d8 12670 [(set_attr "length" "12")])
1fd4e8c1 12671
f9562f27
DE		 12672(define_insn ""
12673 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12674 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12675 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
683bdff7 12676 "TARGET_64BIT"
f9562f27
DE		 12677 "@
12678 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
12679 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
12680 [(set_attr "length" "12")])
12681
1fd4e8c1 12682(define_insn ""
9ebbca7d 12683 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12684 (compare:CC
9ebbca7d
GK		 12685 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12686 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 12687 (const_int 0)))
9ebbca7d 12688 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 12689 (geu:SI (match_dup 1) (match_dup 2)))]
683bdff7 12690 "TARGET_32BIT"
1fd4e8c1 12691 "@
ca7f5001 12692 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
9ebbca7d
GK		 12693 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12694 #
12695 #"
b19003d8 12696 [(set_attr "type" "compare")
9ebbca7d
GK		 12697 (set_attr "length" "12,12,16,16")])
12698
12699(define_split
12700 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12701 (compare:CC
12702 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12703 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12704 (const_int 0)))
12705 (set (match_operand:SI 0 "gpc_reg_operand" "")
12706 (geu:SI (match_dup 1) (match_dup 2)))]
683bdff7 12707 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12708 [(set (match_dup 0)
12709 (geu:SI (match_dup 1) (match_dup 2)))
12710 (set (match_dup 3)
12711 (compare:CC (match_dup 0)
12712 (const_int 0)))]
12713 "")
1fd4e8c1 12714
f9562f27 12715(define_insn ""
9ebbca7d 12716 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 12717 (compare:CC
9ebbca7d
GK		 12718 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12719 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
f9562f27 12720 (const_int 0)))
9ebbca7d 12721 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
f9562f27 12722 (geu:DI (match_dup 1) (match_dup 2)))]
683bdff7 12723 "TARGET_64BIT"
f9562f27
DE		 12724 "@
12725 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
9ebbca7d
GK		 12726 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
12727 #
12728 #"
f9562f27 12729 [(set_attr "type" "compare")
9ebbca7d
GK		 12730 (set_attr "length" "12,12,16,16")])
12731
12732(define_split
12733 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12734 (compare:CC
12735 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12736 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
12737 (const_int 0)))
12738 (set (match_operand:DI 0 "gpc_reg_operand" "")
12739 (geu:DI (match_dup 1) (match_dup 2)))]
683bdff7 12740 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12741 [(set (match_dup 0)
12742 (geu:DI (match_dup 1) (match_dup 2)))
12743 (set (match_dup 3)
12744 (compare:CC (match_dup 0)
12745 (const_int 0)))]
12746 "")
f9562f27 12747
1fd4e8c1 12748(define_insn ""
80103f96 12749 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
cd2b37d9 12750 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12751 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
80103f96 12752 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
683bdff7 12753 "TARGET_32BIT"
1fd4e8c1 12754 "@
80103f96
FS		 12755 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
12756 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
b19003d8 12757 [(set_attr "length" "8")])
1fd4e8c1
RK		 12758
12759(define_insn ""
9ebbca7d 12760 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12761 (compare:CC
9ebbca7d
GK		 12762 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12763 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12764 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12765 (const_int 0)))
9ebbca7d 12766 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 12767 "TARGET_32BIT"
1fd4e8c1 12768 "@
ca7f5001 12769 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12770 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12771 #
12772 #"
b19003d8 12773 [(set_attr "type" "compare")
9ebbca7d
GK		 12774 (set_attr "length" "8,8,12,12")])
12775
12776(define_split
12777 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12778 (compare:CC
12779 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12780 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12781 (match_operand:SI 3 "gpc_reg_operand" ""))
12782 (const_int 0)))
12783 (clobber (match_scratch:SI 4 ""))]
683bdff7 12784 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12785 [(set (match_dup 4)
12786 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
12787 (match_dup 3)))
12788 (set (match_dup 0)
12789 (compare:CC (match_dup 4)
12790 (const_int 0)))]
12791 "")
1fd4e8c1
RK		 12792
12793(define_insn ""
097657c3 12794 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12795 (compare:CC
9ebbca7d
GK		 12796 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12797 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12798 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12799 (const_int 0)))
097657c3
AM		 12800 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12801 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12802 "TARGET_32BIT"
1fd4e8c1 12803 "@
097657c3
AM		 12804 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
12805 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12806 #
12807 #"
b19003d8 12808 [(set_attr "type" "compare")
9ebbca7d
GK		 12809 (set_attr "length" "8,8,12,12")])
12810
12811(define_split
097657c3 12812 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12813 (compare:CC
12814 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12815 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12816 (match_operand:SI 3 "gpc_reg_operand" ""))
12817 (const_int 0)))
12818 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12819 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12820 "TARGET_32BIT && reload_completed"
097657c3 12821 [(set (match_dup 0)
9ebbca7d 12822 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12823 (set (match_dup 4)
9ebbca7d
GK		 12824 (compare:CC (match_dup 0)
12825 (const_int 0)))]
12826 "")
1fd4e8c1
RK		 12827
12828(define_insn ""
cd2b37d9
RK		 12829 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12830 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12831 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
683bdff7 12832 "TARGET_32BIT"
1fd4e8c1 12833 "@
ca7f5001 12834 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
8106dc08 12835 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
b19003d8 12836 [(set_attr "length" "12")])
1fd4e8c1
RK		 12837
12838(define_insn ""
097657c3 12839 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
1fd4e8c1 12840 (and:SI (neg:SI
cd2b37d9 12841 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12842 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
097657c3 12843 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
683bdff7 12844 "TARGET_32BIT"
1fd4e8c1 12845 "@
097657c3
AM		 12846 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
12847 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
b19003d8 12848 [(set_attr "length" "12")])
1fd4e8c1
RK		 12849
12850(define_insn ""
9ebbca7d 12851 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 12852 (compare:CC
12853 (and:SI (neg:SI
9ebbca7d
GK		 12854 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12855 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12856 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12857 (const_int 0)))
9ebbca7d 12858 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 12859 "TARGET_32BIT"
1fd4e8c1 12860 "@
ca7f5001 12861 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
9ebbca7d
GK		 12862 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12863 #
12864 #"
b19003d8 12865 [(set_attr "type" "compare")
9ebbca7d
GK		 12866 (set_attr "length" "12,12,16,16")])
12867
12868(define_split
12869 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12870 (compare:CC
12871 (and:SI (neg:SI
12872 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12873 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12874 (match_operand:SI 3 "gpc_reg_operand" ""))
12875 (const_int 0)))
12876 (clobber (match_scratch:SI 4 ""))]
683bdff7 12877 "TARGET_32BIT && reload_completed"
9ebbca7d 12878 [(set (match_dup 4)
097657c3
AM		 12879 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
12880 (match_dup 3)))
9ebbca7d
GK		 12881 (set (match_dup 0)
12882 (compare:CC (match_dup 4)
12883 (const_int 0)))]
12884 "")
1fd4e8c1
RK		 12885
12886(define_insn ""
097657c3 12887 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 12888 (compare:CC
12889 (and:SI (neg:SI
9ebbca7d
GK		 12890 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12891 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12892 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12893 (const_int 0)))
097657c3
AM		 12894 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12895 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 12896 "TARGET_32BIT"
1fd4e8c1 12897 "@
097657c3
AM		 12898 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12899 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d
GK		 12900 #
12901 #"
b19003d8 12902 [(set_attr "type" "compare")
9ebbca7d
GK		 12903 (set_attr "length" "12,12,16,16")])
12904
12905(define_split
097657c3 12906 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12907 (compare:CC
12908 (and:SI (neg:SI
12909 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12910 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
12911 (match_operand:SI 3 "gpc_reg_operand" ""))
12912 (const_int 0)))
12913 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12914 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 12915 "TARGET_32BIT && reload_completed"
097657c3 12916 [(set (match_dup 0)
9ebbca7d 12917 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
097657c3 12918 (set (match_dup 4)
9ebbca7d
GK		 12919 (compare:CC (match_dup 0)
12920 (const_int 0)))]
12921 "")
1fd4e8c1
RK		 12922
12923(define_insn ""
cd2b37d9
RK		 12924 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12925 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12926 (const_int 0)))]
683bdff7 12927 "TARGET_32BIT"
ca7f5001 12928 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12929 [(set_attr "length" "12")])
1fd4e8c1 12930
f9562f27
DE		 12931(define_insn ""
12932 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12933 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12934 (const_int 0)))]
683bdff7 12935 "TARGET_64BIT"
f9562f27
DE		 12936 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
12937 [(set_attr "length" "12")])
12938
1fd4e8c1 12939(define_insn ""
9ebbca7d 12940 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1fd4e8c1 12941 (compare:CC
9ebbca7d 12942 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 12943 (const_int 0))
12944 (const_int 0)))
9ebbca7d 12945 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 12946 (gt:SI (match_dup 1) (const_int 0)))]
683bdff7 12947 "TARGET_32BIT"
9ebbca7d
GK		 12948 "@
12949 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
12950 #"
29ae5b89 12951 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 12952 (set_attr "length" "12,16")])
12953
12954(define_split
12955 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12956 (compare:CC
12957 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12958 (const_int 0))
12959 (const_int 0)))
12960 (set (match_operand:SI 0 "gpc_reg_operand" "")
12961 (gt:SI (match_dup 1) (const_int 0)))]
683bdff7 12962 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12963 [(set (match_dup 0)
12964 (gt:SI (match_dup 1) (const_int 0)))
12965 (set (match_dup 2)
12966 (compare:CC (match_dup 0)
12967 (const_int 0)))]
12968 "")
1fd4e8c1 12969
f9562f27 12970(define_insn ""
9ebbca7d 12971 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
f9562f27 12972 (compare:CC
9ebbca7d 12973 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27
DE		 12974 (const_int 0))
12975 (const_int 0)))
9ebbca7d 12976 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
f9562f27 12977 (gt:DI (match_dup 1) (const_int 0)))]
683bdff7 12978 "TARGET_64BIT"
9ebbca7d
GK		 12979 "@
12980 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
12981 #"
f9562f27 12982 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 12983 (set_attr "length" "12,16")])
12984
12985(define_split
12986 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
12987 (compare:CC
12988 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
12989 (const_int 0))
12990 (const_int 0)))
12991 (set (match_operand:DI 0 "gpc_reg_operand" "")
12992 (gt:DI (match_dup 1) (const_int 0)))]
683bdff7 12993 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12994 [(set (match_dup 0)
12995 (gt:DI (match_dup 1) (const_int 0)))
12996 (set (match_dup 2)
12997 (compare:CC (match_dup 0)
12998 (const_int 0)))]
12999 "")
f9562f27 13000
1fd4e8c1 13001(define_insn ""
cd2b37d9
RK		 13002 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13003 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13004 (match_operand:SI 2 "reg_or_short_operand" "r")))]
ca7f5001
RK		 13005 "TARGET_POWER"
13006 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13007 [(set_attr "length" "12")])
1fd4e8c1
RK		 13008
13009(define_insn ""
9ebbca7d 13010 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13011 (compare:CC
9ebbca7d
GK		 13012 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13013 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
1fd4e8c1 13014 (const_int 0)))
9ebbca7d 13015 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13016 (gt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13017 "TARGET_POWER"
9ebbca7d
GK		 13018 "@
13019 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13020 #"
29ae5b89 13021 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13022 (set_attr "length" "12,16")])
13023
13024(define_split
13025 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13026 (compare:CC
13027 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13028 (match_operand:SI 2 "reg_or_short_operand" ""))
13029 (const_int 0)))
13030 (set (match_operand:SI 0 "gpc_reg_operand" "")
13031 (gt:SI (match_dup 1) (match_dup 2)))]
13032 "TARGET_POWER && reload_completed"
13033 [(set (match_dup 0)
13034 (gt:SI (match_dup 1) (match_dup 2)))
13035 (set (match_dup 3)
13036 (compare:CC (match_dup 0)
13037 (const_int 0)))]
13038 "")
1fd4e8c1
RK		 13039
13040(define_insn ""
80103f96 13041 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13042 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13043 (const_int 0))
80103f96 13044 (match_operand:SI 2 "gpc_reg_operand" "r")))]
683bdff7 13045 "TARGET_32BIT"
80103f96 13046 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
b19003d8 13047 [(set_attr "length" "12")])
1fd4e8c1 13048
f9562f27 13049(define_insn ""
097657c3 13050 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
f9562f27
DE		 13051 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13052 (const_int 0))
097657c3 13053 (match_operand:DI 2 "gpc_reg_operand" "r")))]
683bdff7 13054 "TARGET_64BIT"
097657c3 13055 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
f9562f27
DE		 13056 [(set_attr "length" "12")])
13057
1fd4e8c1 13058(define_insn ""
9ebbca7d 13059 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13060 (compare:CC
9ebbca7d 13061 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 13062 (const_int 0))
9ebbca7d 13063 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 13064 (const_int 0)))
9ebbca7d 13065 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 13066 "TARGET_32BIT"
9ebbca7d
GK		 13067 "@
13068 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13069 #"
b19003d8 13070 [(set_attr "type" "compare")
9ebbca7d
GK		 13071 (set_attr "length" "12,16")])
13072
13073(define_split
13074 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13075 (compare:CC
13076 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13077 (const_int 0))
13078 (match_operand:SI 2 "gpc_reg_operand" ""))
13079 (const_int 0)))
13080 (clobber (match_scratch:SI 3 ""))]
683bdff7 13081 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13082 [(set (match_dup 3)
13083 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13084 (match_dup 2)))
13085 (set (match_dup 0)
13086 (compare:CC (match_dup 3)
13087 (const_int 0)))]
13088 "")
1fd4e8c1 13089
f9562f27 13090(define_insn ""
9ebbca7d 13091 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
f9562f27 13092 (compare:CC
9ebbca7d 13093 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13094 (const_int 0))
9ebbca7d 13095 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13096 (const_int 0)))
9ebbca7d 13097 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 13098 "TARGET_64BIT"
9ebbca7d
GK		 13099 "@
13100 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13101 #"
f9562f27 13102 [(set_attr "type" "compare")
9ebbca7d
GK		 13103 (set_attr "length" "12,16")])
13104
13105(define_split
13106 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13107 (compare:CC
13108 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13109 (const_int 0))
13110 (match_operand:DI 2 "gpc_reg_operand" ""))
13111 (const_int 0)))
13112 (clobber (match_scratch:DI 3 ""))]
683bdff7 13113 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13114 [(set (match_dup 3)
13115 (plus:DI (gt:DI (match_dup 1) (const_int 0))
097657c3 13116 (match_dup 2)))
9ebbca7d
GK		 13117 (set (match_dup 0)
13118 (compare:CC (match_dup 3)
13119 (const_int 0)))]
13120 "")
f9562f27 13121
1fd4e8c1 13122(define_insn ""
097657c3 13123 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9ebbca7d
GK		 13124 (compare:CC
13125 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13126 (const_int 0))
13127 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13128 (const_int 0)))
097657c3
AM		 13129 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13130 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13131 "TARGET_32BIT"
9ebbca7d 13132 "@
097657c3 13133 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
9ebbca7d
GK		 13134 #"
13135 [(set_attr "type" "compare")
13136 (set_attr "length" "12,16")])
13137
13138(define_split
097657c3 13139 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1fd4e8c1 13140 (compare:CC
9ebbca7d 13141 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 13142 (const_int 0))
9ebbca7d 13143 (match_operand:SI 2 "gpc_reg_operand" ""))
1fd4e8c1 13144 (const_int 0)))
9ebbca7d 13145 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13146 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13147 "TARGET_32BIT && reload_completed"
097657c3 13148 [(set (match_dup 0)
9ebbca7d 13149 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13150 (set (match_dup 3)
9ebbca7d
GK		 13151 (compare:CC (match_dup 0)
13152 (const_int 0)))]
13153 "")
1fd4e8c1 13154
f9562f27 13155(define_insn ""
097657c3 13156 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 13157 (compare:CC
9ebbca7d 13158 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13159 (const_int 0))
9ebbca7d 13160 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13161 (const_int 0)))
097657c3
AM		 13162 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13163 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13164 "TARGET_64BIT"
9ebbca7d 13165 "@
097657c3 13166 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
9ebbca7d 13167 #"
f9562f27 13168 [(set_attr "type" "compare")
9ebbca7d
GK		 13169 (set_attr "length" "12,16")])
13170
13171(define_split
097657c3 13172 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13173 (compare:CC
13174 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13175 (const_int 0))
13176 (match_operand:DI 2 "gpc_reg_operand" ""))
13177 (const_int 0)))
13178 (set (match_operand:DI 0 "gpc_reg_operand" "")
097657c3 13179 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13180 "TARGET_64BIT && reload_completed"
097657c3 13181 [(set (match_dup 0)
9ebbca7d 13182 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13183 (set (match_dup 3)
9ebbca7d
GK		 13184 (compare:CC (match_dup 0)
13185 (const_int 0)))]
13186 "")
f9562f27 13187
1fd4e8c1 13188(define_insn ""
097657c3 13189 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13190 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13191 (match_operand:SI 2 "reg_or_short_operand" "r"))
097657c3 13192 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13193 "TARGET_POWER"
097657c3 13194 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13195 [(set_attr "length" "12")])
1fd4e8c1
RK		 13196
13197(define_insn ""
9ebbca7d 13198 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13199 (compare:CC
9ebbca7d
GK		 13200 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13201 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13202 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13203 (const_int 0)))
9ebbca7d 13204 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13205 "TARGET_POWER"
9ebbca7d
GK		 13206 "@
13207 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13208 #"
b19003d8 13209 [(set_attr "type" "compare")
9ebbca7d
GK		 13210 (set_attr "length" "12,16")])
13211
13212(define_split
13213 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13214 (compare:CC
13215 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13216 (match_operand:SI 2 "reg_or_short_operand" ""))
13217 (match_operand:SI 3 "gpc_reg_operand" ""))
13218 (const_int 0)))
13219 (clobber (match_scratch:SI 4 ""))]
13220 "TARGET_POWER && reload_completed"
13221 [(set (match_dup 4)
097657c3 13222 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9ebbca7d
GK		 13223 (set (match_dup 0)
13224 (compare:CC (match_dup 4)
13225 (const_int 0)))]
13226 "")
1fd4e8c1
RK		 13227
13228(define_insn ""
097657c3 13229 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13230 (compare:CC
9ebbca7d
GK		 13231 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13232 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13233 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13234 (const_int 0)))
097657c3
AM		 13235 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13236 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13237 "TARGET_POWER"
9ebbca7d 13238 "@
097657c3 13239 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13240 #"
b19003d8 13241 [(set_attr "type" "compare")
9ebbca7d
GK		 13242 (set_attr "length" "12,16")])
13243
13244(define_split
097657c3 13245 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13246 (compare:CC
13247 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13248 (match_operand:SI 2 "reg_or_short_operand" ""))
13249 (match_operand:SI 3 "gpc_reg_operand" ""))
13250 (const_int 0)))
13251 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13252 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13253 "TARGET_POWER && reload_completed"
097657c3 13254 [(set (match_dup 0)
9ebbca7d 13255 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13256 (set (match_dup 4)
9ebbca7d
GK		 13257 (compare:CC (match_dup 0)
13258 (const_int 0)))]
13259 "")
1fd4e8c1
RK		 13260
13261(define_insn ""
cd2b37d9
RK		 13262 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13263 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13264 (const_int 0))))]
683bdff7 13265 "TARGET_32BIT"
ca7f5001 13266 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13267 [(set_attr "length" "12")])
1fd4e8c1 13268
f9562f27
DE		 13269(define_insn ""
13270 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13271 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13272 (const_int 0))))]
683bdff7 13273 "TARGET_64BIT"
8377288b 13274 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
f9562f27
DE		 13275 [(set_attr "length" "12")])
13276
1fd4e8c1 13277(define_insn ""
cd2b37d9
RK		 13278 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13279 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13280 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
ca7f5001
RK		 13281 "TARGET_POWER"
13282 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13283 [(set_attr "length" "12")])
1fd4e8c1
RK		 13284
13285(define_insn ""
cd2b37d9
RK		 13286 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13287 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13288 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
683bdff7 13289 "TARGET_32BIT"
ca7f5001 13290 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
b19003d8 13291 [(set_attr "length" "12")])
1fd4e8c1 13292
f9562f27
DE		 13293(define_insn ""
13294 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13295 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13296 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
683bdff7 13297 "TARGET_64BIT"
f9562f27
DE		 13298 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
13299 [(set_attr "length" "12")])
13300
1fd4e8c1 13301(define_insn ""
9ebbca7d 13302 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13303 (compare:CC
9ebbca7d
GK		 13304 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13305 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13306 (const_int 0)))
9ebbca7d 13307 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13308 (gtu:SI (match_dup 1) (match_dup 2)))]
683bdff7 13309 "TARGET_32BIT"
9ebbca7d
GK		 13310 "@
13311 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13312 #"
b19003d8 13313 [(set_attr "type" "compare")
9ebbca7d
GK		 13314 (set_attr "length" "12,16")])
13315
13316(define_split
13317 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13318 (compare:CC
13319 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13320 (match_operand:SI 2 "reg_or_short_operand" ""))
13321 (const_int 0)))
13322 (set (match_operand:SI 0 "gpc_reg_operand" "")
13323 (gtu:SI (match_dup 1) (match_dup 2)))]
683bdff7 13324 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13325 [(set (match_dup 0)
13326 (gtu:SI (match_dup 1) (match_dup 2)))
13327 (set (match_dup 3)
13328 (compare:CC (match_dup 0)
13329 (const_int 0)))]
13330 "")
1fd4e8c1 13331
f9562f27 13332(define_insn ""
9ebbca7d 13333 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 13334 (compare:CC
9ebbca7d
GK		 13335 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13336 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
f9562f27 13337 (const_int 0)))
9ebbca7d 13338 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
f9562f27 13339 (gtu:DI (match_dup 1) (match_dup 2)))]
683bdff7 13340 "TARGET_64BIT"
9ebbca7d
GK		 13341 "@
13342 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13343 #"
f9562f27 13344 [(set_attr "type" "compare")
9ebbca7d
GK		 13345 (set_attr "length" "12,16")])
13346
13347(define_split
13348 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13349 (compare:CC
13350 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13351 (match_operand:DI 2 "reg_or_short_operand" ""))
13352 (const_int 0)))
13353 (set (match_operand:DI 0 "gpc_reg_operand" "")
13354 (gtu:DI (match_dup 1) (match_dup 2)))]
683bdff7 13355 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13356 [(set (match_dup 0)
13357 (gtu:DI (match_dup 1) (match_dup 2)))
13358 (set (match_dup 3)
13359 (compare:CC (match_dup 0)
13360 (const_int 0)))]
13361 "")
f9562f27 13362
1fd4e8c1 13363(define_insn ""
80103f96 13364 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
19378cf8
MM		 13365 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13366 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
80103f96 13367 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
683bdff7 13368 "TARGET_32BIT"
00751805 13369 "@
80103f96
FS		 13370 {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
13371 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
19378cf8 13372 [(set_attr "length" "8,12")])
1fd4e8c1 13373
f9562f27 13374(define_insn ""
097657c3 13375 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
f9562f27
DE		 13376 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13377 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
097657c3 13378 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
683bdff7 13379 "TARGET_64BIT"
f9562f27 13380 "@
097657c3
AM		 13381 addic %0,%1,%k2\;addze %0,%3
13382 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
f9562f27
DE		 13383 [(set_attr "length" "8,12")])
13384
1fd4e8c1 13385(define_insn ""
9ebbca7d 13386 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13387 (compare:CC
9ebbca7d
GK		 13388 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13389 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13390 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13391 (const_int 0)))
9ebbca7d 13392 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13393 "TARGET_32BIT"
00751805 13394 "@
19378cf8 13395 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
9ebbca7d
GK		 13396 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
13397 #
13398 #"
b19003d8 13399 [(set_attr "type" "compare")
9ebbca7d
GK		 13400 (set_attr "length" "8,12,12,16")])
13401
13402(define_split
13403 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13404 (compare:CC
13405 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13406 (match_operand:SI 2 "reg_or_short_operand" ""))
13407 (match_operand:SI 3 "gpc_reg_operand" ""))
13408 (const_int 0)))
13409 (clobber (match_scratch:SI 4 ""))]
683bdff7 13410 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13411 [(set (match_dup 4)
13412 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
097657c3 13413 (match_dup 3)))
9ebbca7d
GK		 13414 (set (match_dup 0)
13415 (compare:CC (match_dup 4)
13416 (const_int 0)))]
13417 "")
1fd4e8c1 13418
f9562f27 13419(define_insn ""
9ebbca7d 13420 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 13421 (compare:CC
9ebbca7d
GK		 13422 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13423 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13424 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
f9562f27 13425 (const_int 0)))
9ebbca7d 13426 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
683bdff7 13427 "TARGET_64BIT"
f9562f27
DE		 13428 "@
13429 addic %4,%1,%k2\;addze. %4,%3
9ebbca7d
GK		 13430 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
13431 #
13432 #"
f9562f27 13433 [(set_attr "type" "compare")
9ebbca7d
GK		 13434 (set_attr "length" "8,12,12,16")])
13435
13436(define_split
13437 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13438 (compare:CC
13439 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13440 (match_operand:DI 2 "reg_or_short_operand" ""))
13441 (match_operand:DI 3 "gpc_reg_operand" ""))
13442 (const_int 0)))
13443 (clobber (match_scratch:DI 4 ""))]
683bdff7 13444 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13445 [(set (match_dup 4)
13446 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13447 (match_dup 3)))
13448 (set (match_dup 0)
13449 (compare:CC (match_dup 4)
13450 (const_int 0)))]
13451 "")
f9562f27 13452
1fd4e8c1 13453(define_insn ""
097657c3 13454 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13455 (compare:CC
9ebbca7d
GK		 13456 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13457 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13458 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13459 (const_int 0)))
097657c3
AM		 13460 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13461 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13462 "TARGET_32BIT"
00751805 13463 "@
097657c3
AM		 13464 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13465 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
9ebbca7d
GK		 13466 #
13467 #"
b19003d8 13468 [(set_attr "type" "compare")
9ebbca7d
GK		 13469 (set_attr "length" "8,12,12,16")])
13470
13471(define_split
097657c3 13472 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13473 (compare:CC
13474 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13475 (match_operand:SI 2 "reg_or_short_operand" ""))
13476 (match_operand:SI 3 "gpc_reg_operand" ""))
13477 (const_int 0)))
13478 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13479 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13480 "TARGET_32BIT && reload_completed"
097657c3 13481 [(set (match_dup 0)
9ebbca7d 13482 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13483 (set (match_dup 4)
9ebbca7d
GK		 13484 (compare:CC (match_dup 0)
13485 (const_int 0)))]
13486 "")
1fd4e8c1 13487
f9562f27 13488(define_insn ""
097657c3 13489 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 13490 (compare:CC
9ebbca7d
GK		 13491 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13492 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13493 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
f9562f27 13494 (const_int 0)))
097657c3
AM		 13495 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13496 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13497 "TARGET_64BIT"
f9562f27 13498 "@
097657c3
AM		 13499 addic %0,%1,%k2\;addze. %0,%3
13500 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
9ebbca7d
GK		 13501 #
13502 #"
f9562f27 13503 [(set_attr "type" "compare")
9ebbca7d
GK		 13504 (set_attr "length" "8,12,12,16")])
13505
13506(define_split
097657c3 13507 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13508 (compare:CC
13509 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13510 (match_operand:DI 2 "reg_or_short_operand" ""))
13511 (match_operand:DI 3 "gpc_reg_operand" ""))
13512 (const_int 0)))
13513 (set (match_operand:DI 0 "gpc_reg_operand" "")
097657c3 13514 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13515 "TARGET_64BIT && reload_completed"
097657c3 13516 [(set (match_dup 0)
9ebbca7d 13517 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13518 (set (match_dup 4)
9ebbca7d
GK		 13519 (compare:CC (match_dup 0)
13520 (const_int 0)))]
13521 "")
f9562f27 13522
1fd4e8c1 13523(define_insn ""
cd2b37d9
RK		 13524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13525 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13526 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
683bdff7 13527 "TARGET_32BIT"
ca7f5001 13528 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
b19003d8 13529 [(set_attr "length" "8")])
f9562f27
DE		 13530
13531(define_insn ""
13532 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13533 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13534 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
683bdff7 13535 "TARGET_64BIT"
f9562f27
DE		 13536 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13537 [(set_attr "length" "8")])
1fd4e8c1
RK		 13538\f
13539;; Define both directions of branch and return. If we need a reload
13540;; register, we'd rather use CR0 since it is much easier to copy a
13541;; register CC value to there.
13542
13543(define_insn ""
13544 [(set (pc)
13545 (if_then_else (match_operator 1 "branch_comparison_operator"
13546 [(match_operand 2
b54cf83a 13547 "cc_reg_operand" "y")
1fd4e8c1
RK		 13548 (const_int 0)])
13549 (label_ref (match_operand 0 "" ""))
13550 (pc)))]
13551 ""
b19003d8
RK		 13552 "*
13553{
12a4e8c5 13554 return output_cbranch (operands[1], \"%l0\", 0, insn);
b19003d8
RK		 13555}"
13556 [(set_attr "type" "branch")])
13557
1fd4e8c1
RK		 13558(define_insn ""
13559 [(set (pc)
13560 (if_then_else (match_operator 0 "branch_comparison_operator"
13561 [(match_operand 1
b54cf83a 13562 "cc_reg_operand" "y")
1fd4e8c1
RK		 13563 (const_int 0)])
13564 (return)
13565 (pc)))]
13566 "direct_return ()"
12a4e8c5
GK		 13567 "*
13568{
13569 return output_cbranch (operands[0], NULL, 0, insn);
13570}"
b7ff3d82 13571 [(set_attr "type" "branch")
39a10a29 13572 (set_attr "length" "4")])
1fd4e8c1
RK		 13573
13574(define_insn ""
13575 [(set (pc)
13576 (if_then_else (match_operator 1 "branch_comparison_operator"
13577 [(match_operand 2
b54cf83a 13578 "cc_reg_operand" "y")
1fd4e8c1
RK		 13579 (const_int 0)])
13580 (pc)
13581 (label_ref (match_operand 0 "" ""))))]
13582 ""
b19003d8
RK		 13583 "*
13584{
12a4e8c5 13585 return output_cbranch (operands[1], \"%l0\", 1, insn);
b19003d8
RK		 13586}"
13587 [(set_attr "type" "branch")])
1fd4e8c1
RK		 13588
13589(define_insn ""
13590 [(set (pc)
13591 (if_then_else (match_operator 0 "branch_comparison_operator"
13592 [(match_operand 1
b54cf83a 13593 "cc_reg_operand" "y")
1fd4e8c1
RK		 13594 (const_int 0)])
13595 (pc)
13596 (return)))]
13597 "direct_return ()"
12a4e8c5
GK		 13598 "*
13599{
13600 return output_cbranch (operands[0], NULL, 1, insn);
13601}"
b7ff3d82 13602 [(set_attr "type" "branch")
39a10a29
GK		 13603 (set_attr "length" "4")])
13604
13605;; Logic on condition register values.
13606
13607; This pattern matches things like
13608; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13609; (eq:SI (reg:CCFP 68) (const_int 0)))
13610; (const_int 1)))
13611; which are generated by the branch logic.
b54cf83a 13612; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
39a10a29
GK		 13613
13614(define_insn ""
b54cf83a 13615 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13616 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
b54cf83a 13617 [(match_operator:SI 2
39a10a29
GK		 13618 "branch_positive_comparison_operator"
13619 [(match_operand 3
b54cf83a 13620 "cc_reg_operand" "y,y")
39a10a29 13621 (const_int 0)])
b54cf83a 13622 (match_operator:SI 4
39a10a29
GK		 13623 "branch_positive_comparison_operator"
13624 [(match_operand 5
b54cf83a 13625 "cc_reg_operand" "0,y")
39a10a29
GK		 13626 (const_int 0)])])
13627 (const_int 1)))]
13628 ""
13629 "cr%q1 %E0,%j2,%j4"
b54cf83a 13630 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 13631
13632; Why is the constant -1 here, but 1 in the previous pattern?
13633; Because ~1 has all but the low bit set.
13634(define_insn ""
b54cf83a 13635 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13636 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
b54cf83a 13637 [(not:SI (match_operator:SI 2
39a10a29
GK		 13638 "branch_positive_comparison_operator"
13639 [(match_operand 3
b54cf83a 13640 "cc_reg_operand" "y,y")
39a10a29
GK		 13641 (const_int 0)]))
13642 (match_operator:SI 4
13643 "branch_positive_comparison_operator"
13644 [(match_operand 5
b54cf83a 13645 "cc_reg_operand" "0,y")
39a10a29
GK		 13646 (const_int 0)])])
13647 (const_int -1)))]
13648 ""
13649 "cr%q1 %E0,%j2,%j4"
b54cf83a 13650 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 13651
13652(define_insn ""
b54cf83a 13653 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
6c873122 13654 (compare:CCEQ (match_operator:SI 1
39a10a29 13655 "branch_positive_comparison_operator"
6c873122 13656 [(match_operand 2
b54cf83a 13657 "cc_reg_operand" "0,y")
39a10a29
GK		 13658 (const_int 0)])
13659 (const_int 0)))]
fe6b547a 13660 "!TARGET_SPE"
251b3667 13661 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
b54cf83a 13662 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 13663
13664;; If we are comparing the result of two comparisons, this can be done
13665;; using creqv or crxor.
13666
13667(define_insn_and_split ""
13668 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13669 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13670 [(match_operand 2 "cc_reg_operand" "y")
13671 (const_int 0)])
13672 (match_operator 3 "branch_comparison_operator"
13673 [(match_operand 4 "cc_reg_operand" "y")
13674 (const_int 0)])))]
13675 ""
13676 "#"
13677 ""
13678 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13679 (match_dup 5)))]
13680 "
13681{
13682 int positive_1, positive_2;
13683
13684 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
13685 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
13686
13687 if (! positive_1)
1c563bed 13688 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
39a10a29 13689 GET_CODE (operands[1])),
2d4368e6
DE		 13690 SImode,
13691 operands[2], const0_rtx);
39a10a29 13692 else if (GET_MODE (operands[1]) != SImode)
1c563bed 13693 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
2d4368e6
DE		 13694 SImode,
13695 operands[2], const0_rtx);
39a10a29
GK		 13696
13697 if (! positive_2)
1c563bed 13698 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
39a10a29 13699 GET_CODE (operands[3])),
2d4368e6
DE		 13700 SImode,
13701 operands[4], const0_rtx);
39a10a29 13702 else if (GET_MODE (operands[3]) != SImode)
1c563bed 13703 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]),
2d4368e6
DE		 13704 SImode,
13705 operands[4], const0_rtx);
39a10a29
GK		 13706
13707 if (positive_1 == positive_2)
251b3667
DE		 13708 {
13709 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13710 operands[5] = constm1_rtx;
13711 }
13712 else
13713 {
13714 operands[5] = const1_rtx;
13715 }
39a10a29 13716}")
1fd4e8c1
RK		 13717
13718;; Unconditional branch and return.
13719
13720(define_insn "jump"
13721 [(set (pc)
13722 (label_ref (match_operand 0 "" "")))]
13723 ""
b7ff3d82
DE		 13724 "b %l0"
13725 [(set_attr "type" "branch")])
1fd4e8c1
RK		 13726
13727(define_insn "return"
13728 [(return)]
13729 "direct_return ()"
324e52cc
TG		 13730 "{br|blr}"
13731 [(set_attr "type" "jmpreg")])
1fd4e8c1 13732
0ad91047
DE		 13733(define_expand "indirect_jump"
13734 [(set (pc) (match_operand 0 "register_operand" ""))]
1fd4e8c1 13735 ""
0ad91047
DE		 13736 "
13737{
13738 if (TARGET_32BIT)
13739 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
13740 else
13741 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
13742 DONE;
13743}")
13744
13745(define_insn "indirect_jumpsi"
b92b324d 13746 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
0ad91047 13747 "TARGET_32BIT"
b92b324d
DE		 13748 "@
13749 bctr
13750 {br|blr}"
324e52cc 13751 [(set_attr "type" "jmpreg")])
1fd4e8c1 13752
0ad91047 13753(define_insn "indirect_jumpdi"
b92b324d 13754 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
0ad91047 13755 "TARGET_64BIT"
b92b324d
DE		 13756 "@
13757 bctr
13758 blr"
266eb58a
DE		 13759 [(set_attr "type" "jmpreg")])
13760
1fd4e8c1
RK		 13761;; Table jump for switch statements:
13762(define_expand "tablejump"
e6ca2c17
DE		 13763 [(use (match_operand 0 "" ""))
13764 (use (label_ref (match_operand 1 "" "")))]
13765 ""
13766 "
13767{
13768 if (TARGET_32BIT)
13769 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13770 else
13771 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13772 DONE;
13773}")
13774
13775(define_expand "tablejumpsi"
1fd4e8c1
RK		 13776 [(set (match_dup 3)
13777 (plus:SI (match_operand:SI 0 "" "")
13778 (match_dup 2)))
13779 (parallel [(set (pc) (match_dup 3))
13780 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 13781 "TARGET_32BIT"
1fd4e8c1
RK		 13782 "
13783{ operands[0] = force_reg (SImode, operands[0]);
c5c76735 13784 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
1fd4e8c1
RK		 13785 operands[3] = gen_reg_rtx (SImode);
13786}")
13787
e6ca2c17 13788(define_expand "tablejumpdi"
9ebbca7d
GK		 13789 [(set (match_dup 4)
13790 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13791 (set (match_dup 3)
13792 (plus:DI (match_dup 4)
e6ca2c17
DE		 13793 (match_dup 2)))
13794 (parallel [(set (pc) (match_dup 3))
13795 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 13796 "TARGET_64BIT"
e6ca2c17 13797 "
9ebbca7d 13798{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
e6ca2c17 13799 operands[3] = gen_reg_rtx (DImode);
9ebbca7d 13800 operands[4] = gen_reg_rtx (DImode);
e6ca2c17
DE		 13801}")
13802
1fd4e8c1
RK		 13803(define_insn ""
13804 [(set (pc)
c859cda6 13805 (match_operand:SI 0 "register_operand" "c,*l"))
1fd4e8c1 13806 (use (label_ref (match_operand 1 "" "")))]
0ad91047 13807 "TARGET_32BIT"
c859cda6
DJ		 13808 "@
13809 bctr
13810 {br|blr}"
a6845123 13811 [(set_attr "type" "jmpreg")])
1fd4e8c1 13812
266eb58a
DE		 13813(define_insn ""
13814 [(set (pc)
c859cda6 13815 (match_operand:DI 0 "register_operand" "c,*l"))
266eb58a 13816 (use (label_ref (match_operand 1 "" "")))]
0ad91047 13817 "TARGET_64BIT"
c859cda6
DJ		 13818 "@
13819 bctr
13820 blr"
266eb58a
DE		 13821 [(set_attr "type" "jmpreg")])
13822
1fd4e8c1
RK		 13823(define_insn "nop"
13824 [(const_int 0)]
13825 ""
ca7f5001 13826 "{cror 0,0,0|nop}")
1fd4e8c1 13827\f
7e69e155 13828;; Define the subtract-one-and-jump insns, starting with the template
c225ba7b
RK		 13829;; so loop.c knows what to generate.
13830
5527bf14
RH		 13831(define_expand "doloop_end"
13832 [(use (match_operand 0 "" "")) ; loop pseudo
13833 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13834 (use (match_operand 2 "" "")) ; max iterations
13835 (use (match_operand 3 "" "")) ; loop level
13836 (use (match_operand 4 "" ""))] ; label
0ad91047
DE		 13837 ""
13838 "
13839{
5527bf14
RH		 13840 /* Only use this on innermost loops. */
13841 if (INTVAL (operands[3]) > 1)
13842 FAIL;
683bdff7 13843 if (TARGET_64BIT)
5527bf14
RH		 13844 {
13845 if (GET_MODE (operands[0]) != DImode)
13846 FAIL;
13847 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13848 }
0ad91047 13849 else
5527bf14
RH		 13850 {
13851 if (GET_MODE (operands[0]) != SImode)
13852 FAIL;
13853 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13854 }
0ad91047
DE		 13855 DONE;
13856}")
13857
13858(define_expand "ctrsi"
3cb999d8
DE		 13859 [(parallel [(set (pc)
13860 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
13861 (const_int 1))
13862 (label_ref (match_operand 1 "" ""))
13863 (pc)))
b6c9286a
MM		 13864 (set (match_dup 0)
13865 (plus:SI (match_dup 0)
13866 (const_int -1)))
5f81043f
RK		 13867 (clobber (match_scratch:CC 2 ""))
13868 (clobber (match_scratch:SI 3 ""))])]
683bdff7 13869 "TARGET_32BIT"
0ad91047
DE		 13870 "")
13871
13872(define_expand "ctrdi"
3cb999d8
DE		 13873 [(parallel [(set (pc)
13874 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
13875 (const_int 1))
13876 (label_ref (match_operand 1 "" ""))
13877 (pc)))
0ad91047
DE		 13878 (set (match_dup 0)
13879 (plus:DI (match_dup 0)
13880 (const_int -1)))
13881 (clobber (match_scratch:CC 2 ""))
61c07d3c 13882 (clobber (match_scratch:DI 3 ""))])]
683bdff7 13883 "TARGET_64BIT"
61c07d3c 13884 "")
c225ba7b 13885
1fd4e8c1
RK		 13886;; We need to be able to do this for any operand, including MEM, or we
13887;; will cause reload to blow up since we don't allow output reloads on
7e69e155 13888;; JUMP_INSNs.
0ad91047 13889;; For the length attribute to be calculated correctly, the
5f81043f
RK		 13890;; label MUST be operand 0.
13891
0ad91047 13892(define_insn "*ctrsi_internal1"
1fd4e8c1 13893 [(set (pc)
43b68ce5 13894 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
1fd4e8c1 13895 (const_int 1))
a6845123 13896 (label_ref (match_operand 0 "" ""))
1fd4e8c1 13897 (pc)))
43b68ce5 13898 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
5f81043f
RK		 13899 (plus:SI (match_dup 1)
13900 (const_int -1)))
43b68ce5
DE		 13901 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13902 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
683bdff7 13903 "TARGET_32BIT"
b19003d8
RK		 13904 "*
13905{
af87a13e 13906 if (which_alternative != 0)
b19003d8 13907 return \"#\";
856a6884 13908 else if (get_attr_length (insn) == 4)
a6845123 13909 return \"{bdn|bdnz} %l0\";
b19003d8 13910 else
f607bc57 13911 return \"bdz $+8\;b %l0\";
b19003d8 13912}"
baf97f86 13913 [(set_attr "type" "branch")
5a195cb5 13914 (set_attr "length" "*,12,16,16")])
7e69e155 13915
0ad91047 13916(define_insn "*ctrsi_internal2"
5f81043f 13917 [(set (pc)
43b68ce5 13918 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
5f81043f
RK		 13919 (const_int 1))
13920 (pc)
13921 (label_ref (match_operand 0 "" ""))))
43b68ce5 13922 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
5f81043f
RK		 13923 (plus:SI (match_dup 1)
13924 (const_int -1)))
43b68ce5
DE		 13925 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13926 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
683bdff7 13927 "TARGET_32BIT"
0ad91047
DE		 13928 "*
13929{
13930 if (which_alternative != 0)
13931 return \"#\";
856a6884 13932 else if (get_attr_length (insn) == 4)
0ad91047
DE		 13933 return \"bdz %l0\";
13934 else
f607bc57 13935 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 13936}"
13937 [(set_attr "type" "branch")
5a195cb5 13938 (set_attr "length" "*,12,16,16")])
0ad91047
DE		 13939
13940(define_insn "*ctrdi_internal1"
13941 [(set (pc)
43b68ce5 13942 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 13943 (const_int 1))
13944 (label_ref (match_operand 0 "" ""))
13945 (pc)))
43b68ce5 13946 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
0ad91047
DE		 13947 (plus:DI (match_dup 1)
13948 (const_int -1)))
43b68ce5
DE		 13949 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13950 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
683bdff7 13951 "TARGET_64BIT"
0ad91047
DE		 13952 "*
13953{
13954 if (which_alternative != 0)
13955 return \"#\";
856a6884 13956 else if (get_attr_length (insn) == 4)
0ad91047
DE		 13957 return \"{bdn|bdnz} %l0\";
13958 else
f607bc57 13959 return \"bdz $+8\;b %l0\";
0ad91047
DE		 13960}"
13961 [(set_attr "type" "branch")
5a195cb5 13962 (set_attr "length" "*,12,16,16")])
0ad91047
DE		 13963
13964(define_insn "*ctrdi_internal2"
13965 [(set (pc)
43b68ce5 13966 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 13967 (const_int 1))
13968 (pc)
13969 (label_ref (match_operand 0 "" ""))))
43b68ce5 13970 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
0ad91047
DE		 13971 (plus:DI (match_dup 1)
13972 (const_int -1)))
43b68ce5
DE		 13973 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13974 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
683bdff7 13975 "TARGET_64BIT"
5f81043f
RK		 13976 "*
13977{
13978 if (which_alternative != 0)
13979 return \"#\";
856a6884 13980 else if (get_attr_length (insn) == 4)
5f81043f
RK		 13981 return \"bdz %l0\";
13982 else
f607bc57 13983 return \"{bdn|bdnz} $+8\;b %l0\";
5f81043f
RK		 13984}"
13985 [(set_attr "type" "branch")
5a195cb5 13986 (set_attr "length" "*,12,16,16")])
5f81043f 13987
c225ba7b 13988;; Similar, but we can use GE since we have a REG_NONNEG.
0ad91047
DE		 13989
13990(define_insn "*ctrsi_internal3"
1fd4e8c1 13991 [(set (pc)
43b68ce5 13992 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
1fd4e8c1 13993 (const_int 0))
a6845123 13994 (label_ref (match_operand 0 "" ""))
1fd4e8c1 13995 (pc)))
43b68ce5 13996 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
5f81043f
RK		 13997 (plus:SI (match_dup 1)
13998 (const_int -1)))
43b68ce5
DE		 13999 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14000 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
683bdff7 14001 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
b19003d8
RK		 14002 "*
14003{
af87a13e 14004 if (which_alternative != 0)
b19003d8 14005 return \"#\";
856a6884 14006 else if (get_attr_length (insn) == 4)
a6845123 14007 return \"{bdn|bdnz} %l0\";
b19003d8 14008 else
f607bc57 14009 return \"bdz $+8\;b %l0\";
b19003d8 14010}"
baf97f86 14011 [(set_attr "type" "branch")
5a195cb5 14012 (set_attr "length" "*,12,16,16")])
7e69e155 14013
0ad91047 14014(define_insn "*ctrsi_internal4"
1fd4e8c1 14015 [(set (pc)
43b68ce5 14016 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
5f81043f
RK		 14017 (const_int 0))
14018 (pc)
14019 (label_ref (match_operand 0 "" ""))))
43b68ce5 14020 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
5f81043f
RK		 14021 (plus:SI (match_dup 1)
14022 (const_int -1)))
43b68ce5
DE		 14023 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14024 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
683bdff7 14025 "TARGET_32BIT && find_reg_note (insn, REG_NONNEG, 0)"
5f81043f
RK		 14026 "*
14027{
14028 if (which_alternative != 0)
14029 return \"#\";
856a6884 14030 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14031 return \"bdz %l0\";
14032 else
f607bc57 14033 return \"{bdn|bdnz} $+8\;b %l0\";
5f81043f
RK		 14034}"
14035 [(set_attr "type" "branch")
5a195cb5 14036 (set_attr "length" "*,12,16,16")])
5f81043f 14037
0ad91047
DE		 14038(define_insn "*ctrdi_internal3"
14039 [(set (pc)
43b68ce5 14040 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14041 (const_int 0))
14042 (label_ref (match_operand 0 "" ""))
14043 (pc)))
43b68ce5 14044 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
0ad91047
DE		 14045 (plus:DI (match_dup 1)
14046 (const_int -1)))
43b68ce5
DE		 14047 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14048 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
683bdff7 14049 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
0ad91047
DE		 14050 "*
14051{
14052 if (which_alternative != 0)
14053 return \"#\";
856a6884 14054 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14055 return \"{bdn|bdnz} %l0\";
14056 else
f607bc57 14057 return \"bdz $+8\;b %l0\";
0ad91047
DE		 14058}"
14059 [(set_attr "type" "branch")
5a195cb5 14060 (set_attr "length" "*,12,16,16")])
0ad91047
DE		 14061
14062(define_insn "*ctrdi_internal4"
14063 [(set (pc)
43b68ce5 14064 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14065 (const_int 0))
14066 (pc)
14067 (label_ref (match_operand 0 "" ""))))
43b68ce5 14068 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
0ad91047
DE		 14069 (plus:DI (match_dup 1)
14070 (const_int -1)))
43b68ce5
DE		 14071 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14072 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
683bdff7 14073 "TARGET_64BIT && find_reg_note (insn, REG_NONNEG, 0)"
0ad91047
DE		 14074 "*
14075{
14076 if (which_alternative != 0)
14077 return \"#\";
856a6884 14078 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14079 return \"bdz %l0\";
14080 else
f607bc57 14081 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 14082}"
14083 [(set_attr "type" "branch")
5a195cb5 14084 (set_attr "length" "*,12,16,16")])
0ad91047
DE		 14085
14086;; Similar but use EQ
14087
14088(define_insn "*ctrsi_internal5"
5f81043f 14089 [(set (pc)
43b68ce5 14090 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
1fd4e8c1 14091 (const_int 1))
a6845123 14092 (label_ref (match_operand 0 "" ""))
1fd4e8c1 14093 (pc)))
43b68ce5 14094 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
5f81043f
RK		 14095 (plus:SI (match_dup 1)
14096 (const_int -1)))
43b68ce5
DE		 14097 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14098 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
683bdff7 14099 "TARGET_32BIT"
b19003d8
RK		 14100 "*
14101{
af87a13e 14102 if (which_alternative != 0)
b19003d8 14103 return \"#\";
856a6884 14104 else if (get_attr_length (insn) == 4)
a6845123 14105 return \"bdz %l0\";
b19003d8 14106 else
f607bc57 14107 return \"{bdn|bdnz} $+8\;b %l0\";
b19003d8 14108}"
baf97f86 14109 [(set_attr "type" "branch")
5a195cb5 14110 (set_attr "length" "*,12,16,16")])
1fd4e8c1 14111
0ad91047 14112(define_insn "*ctrsi_internal6"
5f81043f 14113 [(set (pc)
43b68ce5 14114 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r")
5f81043f
RK		 14115 (const_int 1))
14116 (pc)
14117 (label_ref (match_operand 0 "" ""))))
43b68ce5 14118 (set (match_operand:SI 2 "register_operand" "=1,*r,m,*q*c*l")
5f81043f
RK		 14119 (plus:SI (match_dup 1)
14120 (const_int -1)))
43b68ce5
DE		 14121 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14122 (clobber (match_scratch:SI 4 "=X,X,&r,r"))]
683bdff7 14123 "TARGET_32BIT"
0ad91047
DE		 14124 "*
14125{
14126 if (which_alternative != 0)
14127 return \"#\";
856a6884 14128 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14129 return \"{bdn|bdnz} %l0\";
14130 else
f607bc57 14131 return \"bdz $+8\;b %l0\";
0ad91047
DE		 14132}"
14133 [(set_attr "type" "branch")
5a195cb5 14134 (set_attr "length" "*,12,16,16")])
0ad91047
DE		 14135
14136(define_insn "*ctrdi_internal5"
14137 [(set (pc)
43b68ce5 14138 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14139 (const_int 1))
14140 (label_ref (match_operand 0 "" ""))
14141 (pc)))
43b68ce5 14142 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
0ad91047
DE		 14143 (plus:DI (match_dup 1)
14144 (const_int -1)))
43b68ce5
DE		 14145 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14146 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
683bdff7 14147 "TARGET_64BIT"
0ad91047
DE		 14148 "*
14149{
14150 if (which_alternative != 0)
14151 return \"#\";
856a6884 14152 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14153 return \"bdz %l0\";
14154 else
f607bc57 14155 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 14156}"
14157 [(set_attr "type" "branch")
5a195cb5 14158 (set_attr "length" "*,12,16,16")])
0ad91047
DE		 14159
14160(define_insn "*ctrdi_internal6"
14161 [(set (pc)
43b68ce5 14162 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14163 (const_int 1))
14164 (pc)
14165 (label_ref (match_operand 0 "" ""))))
43b68ce5 14166 (set (match_operand:DI 2 "register_operand" "=1,*r,m,*c*l")
0ad91047
DE		 14167 (plus:DI (match_dup 1)
14168 (const_int -1)))
43b68ce5
DE		 14169 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
14170 (clobber (match_scratch:DI 4 "=X,X,&r,r"))]
683bdff7 14171 "TARGET_64BIT"
5f81043f
RK		 14172 "*
14173{
14174 if (which_alternative != 0)
14175 return \"#\";
856a6884 14176 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14177 return \"{bdn|bdnz} %l0\";
14178 else
f607bc57 14179 return \"bdz $+8\;b %l0\";
5f81043f
RK		 14180}"
14181 [(set_attr "type" "branch")
5a195cb5 14182 (set_attr "length" "*,12,16,16")])
5f81043f 14183
0ad91047
DE		 14184;; Now the splitters if we could not allocate the CTR register
14185
1fd4e8c1
RK		 14186(define_split
14187 [(set (pc)
14188 (if_then_else (match_operator 2 "comparison_operator"
cd2b37d9 14189 [(match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 14190 (const_int 1)])
14191 (match_operand 5 "" "")
14192 (match_operand 6 "" "")))
cd2b37d9 14193 (set (match_operand:SI 0 "gpc_reg_operand" "")
5f81043f
RK		 14194 (plus:SI (match_dup 1)
14195 (const_int -1)))
1fd4e8c1
RK		 14196 (clobber (match_scratch:CC 3 ""))
14197 (clobber (match_scratch:SI 4 ""))]
4b8a63d6 14198 "TARGET_32BIT && reload_completed"
1fd4e8c1 14199 [(parallel [(set (match_dup 3)
5f81043f
RK		 14200 (compare:CC (plus:SI (match_dup 1)
14201 (const_int -1))
1fd4e8c1 14202 (const_int 0)))
5f81043f
RK		 14203 (set (match_dup 0)
14204 (plus:SI (match_dup 1)
14205 (const_int -1)))])
14206 (set (pc) (if_then_else (match_dup 7)
14207 (match_dup 5)
14208 (match_dup 6)))]
1fd4e8c1 14209 "
1c563bed 14210{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, operands[3],
1fd4e8c1
RK		 14211 const0_rtx); }")
14212
14213(define_split
14214 [(set (pc)
14215 (if_then_else (match_operator 2 "comparison_operator"
cd2b37d9 14216 [(match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 14217 (const_int 1)])
14218 (match_operand 5 "" "")
14219 (match_operand 6 "" "")))
9ebbca7d 14220 (set (match_operand:SI 0 "nonimmediate_operand" "")
1fd4e8c1
RK		 14221 (plus:SI (match_dup 1) (const_int -1)))
14222 (clobber (match_scratch:CC 3 ""))
14223 (clobber (match_scratch:SI 4 ""))]
4b8a63d6 14224 "TARGET_32BIT && reload_completed
0ad91047 14225 && ! gpc_reg_operand (operands[0], SImode)"
1fd4e8c1 14226 [(parallel [(set (match_dup 3)
5f81043f
RK		 14227 (compare:CC (plus:SI (match_dup 1)
14228 (const_int -1))
1fd4e8c1 14229 (const_int 0)))
5f81043f
RK		 14230 (set (match_dup 4)
14231 (plus:SI (match_dup 1)
14232 (const_int -1)))])
14233 (set (match_dup 0)
14234 (match_dup 4))
14235 (set (pc) (if_then_else (match_dup 7)
14236 (match_dup 5)
14237 (match_dup 6)))]
1fd4e8c1 14238 "
1c563bed 14239{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, operands[3],
1fd4e8c1 14240 const0_rtx); }")
0ad91047
DE		 14241(define_split
14242 [(set (pc)
14243 (if_then_else (match_operator 2 "comparison_operator"
14244 [(match_operand:DI 1 "gpc_reg_operand" "")
14245 (const_int 1)])
61c07d3c
DE		 14246 (match_operand 5 "" "")
14247 (match_operand 6 "" "")))
0ad91047
DE		 14248 (set (match_operand:DI 0 "gpc_reg_operand" "")
14249 (plus:DI (match_dup 1)
14250 (const_int -1)))
14251 (clobber (match_scratch:CC 3 ""))
61c07d3c 14252 (clobber (match_scratch:DI 4 ""))]
683bdff7 14253 "TARGET_64BIT && reload_completed"
0ad91047
DE		 14254 [(parallel [(set (match_dup 3)
14255 (compare:CC (plus:DI (match_dup 1)
14256 (const_int -1))
14257 (const_int 0)))
14258 (set (match_dup 0)
14259 (plus:DI (match_dup 1)
14260 (const_int -1)))])
61c07d3c
DE		 14261 (set (pc) (if_then_else (match_dup 7)
14262 (match_dup 5)
14263 (match_dup 6)))]
0ad91047 14264 "
1c563bed 14265{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, operands[3],
0ad91047
DE		 14266 const0_rtx); }")
14267
14268(define_split
14269 [(set (pc)
14270 (if_then_else (match_operator 2 "comparison_operator"
14271 [(match_operand:DI 1 "gpc_reg_operand" "")
14272 (const_int 1)])
61c07d3c
DE		 14273 (match_operand 5 "" "")
14274 (match_operand 6 "" "")))
9ebbca7d 14275 (set (match_operand:DI 0 "nonimmediate_operand" "")
0ad91047
DE		 14276 (plus:DI (match_dup 1) (const_int -1)))
14277 (clobber (match_scratch:CC 3 ""))
61c07d3c 14278 (clobber (match_scratch:DI 4 ""))]
683bdff7 14279 "TARGET_64BIT && reload_completed
0ad91047
DE		 14280 && ! gpc_reg_operand (operands[0], DImode)"
14281 [(parallel [(set (match_dup 3)
14282 (compare:CC (plus:DI (match_dup 1)
14283 (const_int -1))
14284 (const_int 0)))
14285 (set (match_dup 4)
14286 (plus:DI (match_dup 1)
14287 (const_int -1)))])
14288 (set (match_dup 0)
14289 (match_dup 4))
61c07d3c
DE		 14290 (set (pc) (if_then_else (match_dup 7)
14291 (match_dup 5)
14292 (match_dup 6)))]
0ad91047 14293 "
1c563bed 14294{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, operands[3],
0ad91047 14295 const0_rtx); }")
e0cd0770
JC		 14296\f
14297(define_insn "trap"
14298 [(trap_if (const_int 1) (const_int 0))]
14299 ""
14300 "{t 31,0,0|trap}")
14301
14302(define_expand "conditional_trap"
14303 [(trap_if (match_operator 0 "trap_comparison_operator"
14304 [(match_dup 2) (match_dup 3)])
14305 (match_operand 1 "const_int_operand" ""))]
14306 ""
14307 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14308 operands[2] = rs6000_compare_op0;
14309 operands[3] = rs6000_compare_op1;")
14310
14311(define_insn ""
14312 [(trap_if (match_operator 0 "trap_comparison_operator"
14313 [(match_operand:SI 1 "register_operand" "r")
14314 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14315 (const_int 0))]
14316 ""
a157febd
GK		 14317 "{t|tw}%V0%I2 %1,%2")
14318
14319(define_insn ""
14320 [(trap_if (match_operator 0 "trap_comparison_operator"
14321 [(match_operand:DI 1 "register_operand" "r")
14322 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14323 (const_int 0))]
14324 "TARGET_POWERPC64"
14325 "td%V0%I2 %1,%2")
9ebbca7d
GK		 14326\f
14327;; Insns related to generating the function prologue and epilogue.
14328
14329(define_expand "prologue"
14330 [(use (const_int 0))]
14331 "TARGET_SCHED_PROLOG"
14332 "
14333{
14334 rs6000_emit_prologue ();
14335 DONE;
14336}")
14337
2c4a9cff
DE		 14338(define_insn "*movesi_from_cr_one"
14339 [(match_parallel 0 "mfcr_operation"
14340 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14341 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14342 (match_operand 3 "immediate_operand" "n")]
14343 UNSPEC_MOVESI_FROM_CR))])]
14344 "TARGET_MFCRF"
14345 "*
14346{
14347 int mask = 0;
14348 int i;
14349 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14350 {
14351 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14352 operands[4] = GEN_INT (mask);
14353 output_asm_insn (\"mfcr %1,%4\", operands);
14354 }
14355 return \"\";
14356}"
14357 [(set_attr "type" "mfcrf")])
14358
9ebbca7d
GK		 14359(define_insn "movesi_from_cr"
14360 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14361 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
615158e2
JJ		 14362 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14363 UNSPEC_MOVESI_FROM_CR))]
9ebbca7d 14364 ""
309323c2 14365 "mfcr %0"
b54cf83a 14366 [(set_attr "type" "mfcr")])
9ebbca7d
GK		 14367
14368(define_insn "*stmw"
e033a023
DE		 14369 [(match_parallel 0 "stmw_operation"
14370 [(set (match_operand:SI 1 "memory_operand" "=m")
14371 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14372 "TARGET_MULTIPLE"
14373 "{stm|stmw} %2,%1")
9ebbca7d
GK		 14374
14375(define_insn "*save_fpregs_si"
e033a023
DE		 14376 [(match_parallel 0 "any_operand"
14377 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14378 (use (match_operand:SI 2 "call_operand" "s"))
14379 (set (match_operand:DF 3 "memory_operand" "=m")
14380 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14381 "TARGET_32BIT"
14382 "bl %z2"
14383 [(set_attr "type" "branch")
14384 (set_attr "length" "4")])
9ebbca7d
GK		 14385
14386(define_insn "*save_fpregs_di"
e033a023
DE		 14387 [(match_parallel 0 "any_operand"
14388 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14389 (use (match_operand:DI 2 "call_operand" "s"))
14390 (set (match_operand:DF 3 "memory_operand" "=m")
14391 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14392 "TARGET_64BIT"
14393 "bl %z2"
14394 [(set_attr "type" "branch")
14395 (set_attr "length" "4")])
9ebbca7d
GK		 14396
14397; These are to explain that changes to the stack pointer should
14398; not be moved over stores to stack memory.
14399(define_insn "stack_tie"
14400 [(set (match_operand:BLK 0 "memory_operand" "+m")
615158e2 14401 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9ebbca7d
GK		 14402 ""
14403 ""
14404 [(set_attr "length" "0")])
14405
14406
14407(define_expand "epilogue"
14408 [(use (const_int 0))]
14409 "TARGET_SCHED_PROLOG"
14410 "
14411{
14412 rs6000_emit_epilogue (FALSE);
14413 DONE;
14414}")
14415
14416; On some processors, doing the mtcrf one CC register at a time is
14417; faster (like on the 604e). On others, doing them all at once is
14418; faster; for instance, on the 601 and 750.
14419
14420(define_expand "movsi_to_cr_one"
35aba846
DE		 14421 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14422 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
615158e2 14423 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
35aba846
DE		 14424 ""
14425 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
9ebbca7d
GK		 14426
14427(define_insn "*movsi_to_cr"
35aba846
DE		 14428 [(match_parallel 0 "mtcrf_operation"
14429 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14430 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14431 (match_operand 3 "immediate_operand" "n")]
615158e2 14432 UNSPEC_MOVESI_TO_CR))])]
9ebbca7d 14433 ""
e35b9579
GK		 14434 "*
14435{
14436 int mask = 0;
14437 int i;
14438 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14439 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14440 operands[4] = GEN_INT (mask);
14441 return \"mtcrf %4,%2\";
309323c2 14442}"
b54cf83a 14443 [(set_attr "type" "mtcr")])
9ebbca7d 14444
b54cf83a 14445(define_insn "*mtcrfsi"
309323c2
DE		 14446 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14447 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
615158e2
JJ		 14448 (match_operand 2 "immediate_operand" "n")]
14449 UNSPEC_MOVESI_TO_CR))]
309323c2
DE		 14450 "GET_CODE (operands[0]) == REG
14451 && CR_REGNO_P (REGNO (operands[0]))
14452 && GET_CODE (operands[2]) == CONST_INT
14453 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14454 "mtcrf %R0,%1"
b54cf83a 14455 [(set_attr "type" "mtcr")])
9ebbca7d
GK		 14456
14457; The load-multiple instructions have similar properties.
14458; Note that "load_multiple" is a name known to the machine-independent
14459; code that actually corresponds to the powerpc load-string.
14460
14461(define_insn "*lmw"
35aba846
DE		 14462 [(match_parallel 0 "lmw_operation"
14463 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14464 (match_operand:SI 2 "memory_operand" "m"))])]
14465 "TARGET_MULTIPLE"
14466 "{lm|lmw} %1,%2")
9ebbca7d
GK		 14467
14468(define_insn "*return_internal_si"
e35b9579
GK		 14469 [(return)
14470 (use (match_operand:SI 0 "register_operand" "lc"))]
9ebbca7d 14471 "TARGET_32BIT"
cccf3bdc 14472 "b%T0"
9ebbca7d
GK		 14473 [(set_attr "type" "jmpreg")])
14474
14475(define_insn "*return_internal_di"
e35b9579
GK		 14476 [(return)
14477 (use (match_operand:DI 0 "register_operand" "lc"))]
9ebbca7d 14478 "TARGET_64BIT"
cccf3bdc 14479 "b%T0"
9ebbca7d
GK		 14480 [(set_attr "type" "jmpreg")])
14481
14482; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14483; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
14484
14485(define_insn "*return_and_restore_fpregs_si"
14486 [(match_parallel 0 "any_operand"
e35b9579
GK		 14487 [(return)
14488 (use (match_operand:SI 1 "register_operand" "l"))
9ebbca7d
GK		 14489 (use (match_operand:SI 2 "call_operand" "s"))
14490 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14491 (match_operand:DF 4 "memory_operand" "m"))])]
14492 "TARGET_32BIT"
14493 "b %z2")
14494
14495(define_insn "*return_and_restore_fpregs_di"
14496 [(match_parallel 0 "any_operand"
e35b9579
GK		 14497 [(return)
14498 (use (match_operand:DI 1 "register_operand" "l"))
9ebbca7d
GK		 14499 (use (match_operand:DI 2 "call_operand" "s"))
14500 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14501 (match_operand:DF 4 "memory_operand" "m"))])]
14502 "TARGET_64BIT"
14503 "b %z2")
14504
83720594
RH		 14505; This is used in compiling the unwind routines.
14506(define_expand "eh_return"
34dc173c 14507 [(use (match_operand 0 "general_operand" ""))]
9ebbca7d
GK		 14508 ""
14509 "
14510{
83720594 14511 if (TARGET_32BIT)
34dc173c 14512 emit_insn (gen_eh_set_lr_si (operands[0]));
9ebbca7d 14513 else
34dc173c 14514 emit_insn (gen_eh_set_lr_di (operands[0]));
9ebbca7d
GK		 14515 DONE;
14516}")
14517
83720594
RH		 14518; We can't expand this before we know where the link register is stored.
14519(define_insn "eh_set_lr_si"
615158e2
JJ		 14520 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14521 UNSPECV_EH_RR)
466eb3e0 14522 (clobber (match_scratch:SI 1 "=&b"))]
83720594
RH		 14523 "TARGET_32BIT"
14524 "#")
14525
14526(define_insn "eh_set_lr_di"
615158e2
JJ		 14527 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")]
14528 UNSPECV_EH_RR)
466eb3e0 14529 (clobber (match_scratch:DI 1 "=&b"))]
83720594
RH		 14530 "TARGET_64BIT"
14531 "#")
9ebbca7d
GK		 14532
14533(define_split
615158e2 14534 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
83720594
RH		 14535 (clobber (match_scratch 1 ""))]
14536 "reload_completed"
14537 [(const_int 0)]
9ebbca7d
GK		 14538 "
14539{
d1d0c603 14540 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
83720594
RH		 14541 DONE;
14542}")
0ac081f6 14543
01a2ccd0
DE		 14544(define_insn "prefetch"
14545 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
6041bf2f
DE		 14546 (match_operand:SI 1 "const_int_operand" "n")
14547 (match_operand:SI 2 "const_int_operand" "n"))]
01a2ccd0 14548 "TARGET_POWERPC"
6041bf2f
DE		 14549 "*
14550{
01a2ccd0
DE		 14551 if (GET_CODE (operands[0]) == REG)
14552 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14553 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
6041bf2f
DE		 14554}"
14555 [(set_attr "type" "load")])
a3170dc6 14556
10ed84db 14557(include "altivec.md")
a3170dc6 14558(include "spe.md")
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