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re PR libfortran/32841 (HUGE(1.0_16) output as +Infinity on ppc-darwin8 (gfortran...
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
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996a5f59 1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
d24652ee 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
8ef65e3d 3;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
602ea4d3 4;; Free Software Foundation, Inc.
996a5f59 5;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
1fd4e8c1 6
5de601cf 7;; This file is part of GCC.
1fd4e8c1 8
5de601cf
NC		 9;; GCC is free software; you can redistribute it and/or modify it
10;; under the terms of the GNU General Public License as published
2f83c7d6 11;; by the Free Software Foundation; either version 3, or (at your
5de601cf 12;; option) any later version.
1fd4e8c1 13
5de601cf
NC		 14;; GCC is distributed in the hope that it will be useful, but WITHOUT
15;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17;; License for more details.
1fd4e8c1
RK		 18
19;; You should have received a copy of the GNU General Public License
2f83c7d6
NC		 20;; along with GCC; see the file COPYING3. If not see
21;; <http://www.gnu.org/licenses/>.
1fd4e8c1
RK		 22
23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
9ebbca7d 24
1de43f85
DE		 25;;
26;; REGNOS
27;;
28
29(define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
51
615158e2
JJ		 52;;
53;; UNSPEC usage
54;;
55
56(define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
63 (UNSPEC_FCTIWZ 10)
9719f3b7
DE		 64 (UNSPEC_FRIM 11)
65 (UNSPEC_FRIN 12)
66 (UNSPEC_FRIP 13)
67 (UNSPEC_FRIZ 14)
615158e2
JJ		 68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
70 (UNSPEC_TLSGD 17)
71 (UNSPEC_TLSLD 18)
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
74 (UNSPEC_TLSDTPREL 21)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
78 (UNSPEC_TLSTPREL 25)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
82 (UNSPEC_TLSTLS 29)
ecb62ae7 83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
cef6b86c 84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
da4c340c 85 (UNSPEC_STFIWX 32)
9f0076e5
DE		 86 (UNSPEC_POPCNTB 33)
87 (UNSPEC_FRES 34)
88 (UNSPEC_SP_SET 35)
89 (UNSPEC_SP_TEST 36)
90 (UNSPEC_SYNC 37)
91 (UNSPEC_LWSYNC 38)
92 (UNSPEC_ISYNC 39)
93 (UNSPEC_SYNC_OP 40)
94 (UNSPEC_ATOMIC 41)
95 (UNSPEC_CMPXCHG 42)
96 (UNSPEC_XCHG 43)
97 (UNSPEC_AND 44)
716019c0
JM		 98 (UNSPEC_DLMZB 45)
99 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47)
9c78b944 101 (UNSPEC_RSQRT 48)
615158e2
JJ		 102 ])
103
104;;
105;; UNSPEC_VOLATILE usage
106;;
107
108(define_constants
109 [(UNSPECV_BLOCK 0)
b52110d4
DE		 110 (UNSPECV_LL 1) ; load-locked
111 (UNSPECV_SC 2) ; store-conditional
615158e2
JJ		 112 (UNSPECV_EH_RR 9) ; eh_reg_restore
113 ])
1fd4e8c1
RK		 114\f
115;; Define an insn type attribute. This is used in function unit delay
116;; computations.
44cd321e 117(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
1fd4e8c1
RK		 118 (const_string "integer"))
119
b19003d8 120;; Length (in bytes).
6ae08853 121; '(pc)' in the following doesn't include the instruction itself; it is
6cbadf36 122; calculated as if the instruction had zero size.
b19003d8
RK		 123(define_attr "length" ""
124 (if_then_else (eq_attr "type" "branch")
6cbadf36 125 (if_then_else (and (ge (minus (match_dup 0) (pc))
b19003d8 126 (const_int -32768))
6cbadf36
GK		 127 (lt (minus (match_dup 0) (pc))
128 (const_int 32764)))
39a10a29
GK		 129 (const_int 4)
130 (const_int 8))
b19003d8
RK		 131 (const_int 4)))
132
cfb557c4
RK		 133;; Processor type -- this attribute must exactly match the processor_type
134;; enumeration in rs6000.h.
135
d296e02e 136(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5,power6,cell"
cfb557c4
RK		 137 (const (symbol_ref "rs6000_cpu_attr")))
138
d296e02e
AP		 139
140;; If this instruction is microcoded on the CELL processor
141; The default for load and stores is conditional
142; The default for load extended and the recorded instructions is always microcoded
143(define_attr "cell_micro" "not,conditional,always"
144 (if_then_else (ior (ior (eq_attr "type" "load")
145 (eq_attr "type" "store"))
146 (ior (eq_attr "type" "fpload")
147 (eq_attr "type" "fpstore")))
148 (const_string "conditional")
149 (if_then_else (ior (eq_attr "type" "load_ext")
150 (ior (eq_attr "type" "compare")
151 (eq_attr "type" "delayed_compare")))
152 (const_string "always")
153 (const_string "not"))))
154
155
b54cf83a
DE		 156(automata_option "ndfa")
157
158(include "rios1.md")
159(include "rios2.md")
160(include "rs64.md")
161(include "mpc.md")
162(include "40x.md")
02ca7595 163(include "440.md")
b54cf83a
DE		 164(include "603.md")
165(include "6xx.md")
166(include "7xx.md")
167(include "7450.md")
5e8006fa 168(include "8540.md")
b54cf83a 169(include "power4.md")
ec507f2d 170(include "power5.md")
44cd321e 171(include "power6.md")
d296e02e 172(include "cell.md")
48d72335
DE		 173
174(include "predicates.md")
279bb624 175(include "constraints.md")
48d72335 176
ac9e2cff 177(include "darwin.md")
309323c2 178
1fd4e8c1 179\f
3abcb3a7 180;; Mode iterators
915167f5 181
3abcb3a7 182; This mode iterator allows :GPR to be used to indicate the allowable size
915167f5 183; of whole values in GPRs.
3abcb3a7 184(define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
915167f5 185
0354e5d8 186; Any supported integer mode.
3abcb3a7 187(define_mode_iterator INT [QI HI SI DI TI])
915167f5 188
0354e5d8 189; Any supported integer mode that fits in one register.
3abcb3a7 190(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
915167f5 191
b5568f07 192; extend modes for DImode
3abcb3a7 193(define_mode_iterator QHSI [QI HI SI])
b5568f07 194
0354e5d8 195; SImode or DImode, even if DImode doesn't fit in GPRs.
3abcb3a7 196(define_mode_iterator SDI [SI DI])
0354e5d8
GK		 197
198; The size of a pointer. Also, the size of the value that a record-condition
199; (one with a '.') will compare.
3abcb3a7 200(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
2e6c9641 201
4ae234b0 202; Any hardware-supported floating-point mode
3abcb3a7 203(define_mode_iterator FP [(SF "TARGET_HARD_FLOAT")
4ae234b0 204 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
602ea4d3 205 (TF "!TARGET_IEEEQUAD
17caeff2
JM		 206 && TARGET_HARD_FLOAT
207 && (TARGET_FPRS || TARGET_E500_DOUBLE)
6ef9a246
JJ		 208 && TARGET_LONG_DOUBLE_128")
209 (DD "TARGET_DFP")
210 (TD "TARGET_DFP")])
4ae234b0 211
915167f5 212; Various instructions that come in SI and DI forms.
0354e5d8 213; A generic w/d attribute, for things like cmpw/cmpd.
b5568f07
DE		 214(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
215
216; DImode bits
217(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
915167f5
GK		 218
219\f
1fd4e8c1
RK		 220;; Start with fixed-point load and store insns. Here we put only the more
221;; complex forms. Basic data transfer is done later.
222
b5568f07 223(define_expand "zero_extend<mode>di2"
51b8fc2c 224 [(set (match_operand:DI 0 "gpc_reg_operand" "")
b5568f07 225 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
51b8fc2c
RK		 226 "TARGET_POWERPC64"
227 "")
228
b5568f07 229(define_insn "*zero_extend<mode>di2_internal1"
51b8fc2c 230 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
b5568f07 231 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
51b8fc2c
RK		 232 "TARGET_POWERPC64"
233 "@
b5568f07
DE		 234 l<wd>z%U1%X1 %0,%1
235 rldicl %0,%1,0,<dbits>"
51b8fc2c
RK		 236 [(set_attr "type" "load,*")])
237
b5568f07 238(define_insn "*zero_extend<mode>di2_internal2"
9ebbca7d 239 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
b5568f07 240 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
815cdc52 241 (const_int 0)))
9ebbca7d 242 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 243 "TARGET_64BIT"
9ebbca7d 244 "@
b5568f07 245 rldicl. %2,%1,0,<dbits>
9ebbca7d
GK		 246 #"
247 [(set_attr "type" "compare")
248 (set_attr "length" "4,8")])
249
250(define_split
251 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
b5568f07 252 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 253 (const_int 0)))
254 (clobber (match_scratch:DI 2 ""))]
255 "TARGET_POWERPC64 && reload_completed"
256 [(set (match_dup 2)
257 (zero_extend:DI (match_dup 1)))
258 (set (match_dup 0)
259 (compare:CC (match_dup 2)
260 (const_int 0)))]
261 "")
51b8fc2c 262
b5568f07 263(define_insn "*zero_extend<mode>di2_internal3"
9ebbca7d 264 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
b5568f07 265 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 266 (const_int 0)))
9ebbca7d 267 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 268 (zero_extend:DI (match_dup 1)))]
683bdff7 269 "TARGET_64BIT"
9ebbca7d 270 "@
b5568f07 271 rldicl. %0,%1,0,<dbits>
9ebbca7d
GK		 272 #"
273 [(set_attr "type" "compare")
274 (set_attr "length" "4,8")])
275
276(define_split
277 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
b5568f07 278 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 279 (const_int 0)))
280 (set (match_operand:DI 0 "gpc_reg_operand" "")
281 (zero_extend:DI (match_dup 1)))]
282 "TARGET_POWERPC64 && reload_completed"
283 [(set (match_dup 0)
284 (zero_extend:DI (match_dup 1)))
285 (set (match_dup 2)
286 (compare:CC (match_dup 0)
287 (const_int 0)))]
288 "")
51b8fc2c 289
2bee0449
RK		 290(define_insn "extendqidi2"
291 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
292 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 293 "TARGET_POWERPC64"
44cd321e
PS		 294 "extsb %0,%1"
295 [(set_attr "type" "exts")])
51b8fc2c
RK		 296
297(define_insn ""
9ebbca7d
GK		 298 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
299 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 300 (const_int 0)))
9ebbca7d 301 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 302 "TARGET_64BIT"
9ebbca7d
GK		 303 "@
304 extsb. %2,%1
305 #"
306 [(set_attr "type" "compare")
307 (set_attr "length" "4,8")])
308
309(define_split
310 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
311 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
312 (const_int 0)))
313 (clobber (match_scratch:DI 2 ""))]
314 "TARGET_POWERPC64 && reload_completed"
315 [(set (match_dup 2)
316 (sign_extend:DI (match_dup 1)))
317 (set (match_dup 0)
318 (compare:CC (match_dup 2)
319 (const_int 0)))]
320 "")
51b8fc2c
RK		 321
322(define_insn ""
9ebbca7d
GK		 323 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
324 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 325 (const_int 0)))
9ebbca7d 326 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 327 (sign_extend:DI (match_dup 1)))]
683bdff7 328 "TARGET_64BIT"
9ebbca7d
GK		 329 "@
330 extsb. %0,%1
331 #"
332 [(set_attr "type" "compare")
333 (set_attr "length" "4,8")])
334
335(define_split
336 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
337 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
338 (const_int 0)))
339 (set (match_operand:DI 0 "gpc_reg_operand" "")
340 (sign_extend:DI (match_dup 1)))]
341 "TARGET_POWERPC64 && reload_completed"
342 [(set (match_dup 0)
343 (sign_extend:DI (match_dup 1)))
344 (set (match_dup 2)
345 (compare:CC (match_dup 0)
346 (const_int 0)))]
347 "")
51b8fc2c 348
51b8fc2c
RK		 349(define_expand "extendhidi2"
350 [(set (match_operand:DI 0 "gpc_reg_operand" "")
351 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
352 "TARGET_POWERPC64"
353 "")
354
355(define_insn ""
356 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
357 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
358 "TARGET_POWERPC64"
359 "@
360 lha%U1%X1 %0,%1
361 extsh %0,%1"
44cd321e 362 [(set_attr "type" "load_ext,exts")])
51b8fc2c
RK		 363
364(define_insn ""
9ebbca7d
GK		 365 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
366 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 367 (const_int 0)))
9ebbca7d 368 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 369 "TARGET_64BIT"
9ebbca7d
GK		 370 "@
371 extsh. %2,%1
372 #"
373 [(set_attr "type" "compare")
374 (set_attr "length" "4,8")])
375
376(define_split
377 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
378 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
379 (const_int 0)))
380 (clobber (match_scratch:DI 2 ""))]
381 "TARGET_POWERPC64 && reload_completed"
382 [(set (match_dup 2)
383 (sign_extend:DI (match_dup 1)))
384 (set (match_dup 0)
385 (compare:CC (match_dup 2)
386 (const_int 0)))]
387 "")
51b8fc2c
RK		 388
389(define_insn ""
9ebbca7d
GK		 390 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
391 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 392 (const_int 0)))
9ebbca7d 393 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 394 (sign_extend:DI (match_dup 1)))]
683bdff7 395 "TARGET_64BIT"
9ebbca7d
GK		 396 "@
397 extsh. %0,%1
398 #"
399 [(set_attr "type" "compare")
400 (set_attr "length" "4,8")])
401
402(define_split
403 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
404 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
405 (const_int 0)))
406 (set (match_operand:DI 0 "gpc_reg_operand" "")
407 (sign_extend:DI (match_dup 1)))]
408 "TARGET_POWERPC64 && reload_completed"
409 [(set (match_dup 0)
410 (sign_extend:DI (match_dup 1)))
411 (set (match_dup 2)
412 (compare:CC (match_dup 0)
413 (const_int 0)))]
414 "")
51b8fc2c 415
51b8fc2c
RK		 416(define_expand "extendsidi2"
417 [(set (match_operand:DI 0 "gpc_reg_operand" "")
418 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
419 "TARGET_POWERPC64"
420 "")
421
422(define_insn ""
423 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
287f13ff 424 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
51b8fc2c
RK		 425 "TARGET_POWERPC64"
426 "@
427 lwa%U1%X1 %0,%1
428 extsw %0,%1"
44cd321e 429 [(set_attr "type" "load_ext,exts")])
51b8fc2c
RK		 430
431(define_insn ""
9ebbca7d
GK		 432 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
433 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 434 (const_int 0)))
9ebbca7d 435 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 436 "TARGET_64BIT"
9ebbca7d
GK		 437 "@
438 extsw. %2,%1
439 #"
440 [(set_attr "type" "compare")
441 (set_attr "length" "4,8")])
442
443(define_split
444 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
445 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
446 (const_int 0)))
447 (clobber (match_scratch:DI 2 ""))]
448 "TARGET_POWERPC64 && reload_completed"
449 [(set (match_dup 2)
450 (sign_extend:DI (match_dup 1)))
451 (set (match_dup 0)
452 (compare:CC (match_dup 2)
453 (const_int 0)))]
454 "")
51b8fc2c
RK		 455
456(define_insn ""
9ebbca7d
GK		 457 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
458 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 459 (const_int 0)))
9ebbca7d 460 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 461 (sign_extend:DI (match_dup 1)))]
683bdff7 462 "TARGET_64BIT"
9ebbca7d
GK		 463 "@
464 extsw. %0,%1
465 #"
466 [(set_attr "type" "compare")
467 (set_attr "length" "4,8")])
468
469(define_split
470 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
471 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
472 (const_int 0)))
473 (set (match_operand:DI 0 "gpc_reg_operand" "")
474 (sign_extend:DI (match_dup 1)))]
475 "TARGET_POWERPC64 && reload_completed"
476 [(set (match_dup 0)
477 (sign_extend:DI (match_dup 1)))
478 (set (match_dup 2)
479 (compare:CC (match_dup 0)
480 (const_int 0)))]
481 "")
51b8fc2c 482
1fd4e8c1 483(define_expand "zero_extendqisi2"
cd2b37d9
RK		 484 [(set (match_operand:SI 0 "gpc_reg_operand" "")
485 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 486 ""
487 "")
488
489(define_insn ""
cd2b37d9 490 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 491 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
492 ""
493 "@
494 lbz%U1%X1 %0,%1
005a35b9 495 {rlinm|rlwinm} %0,%1,0,0xff"
1fd4e8c1
RK		 496 [(set_attr "type" "load,*")])
497
498(define_insn ""
9ebbca7d
GK		 499 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
500 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 501 (const_int 0)))
9ebbca7d 502 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 503 ""
9ebbca7d
GK		 504 "@
505 {andil.|andi.} %2,%1,0xff
506 #"
507 [(set_attr "type" "compare")
508 (set_attr "length" "4,8")])
509
510(define_split
511 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
512 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
513 (const_int 0)))
514 (clobber (match_scratch:SI 2 ""))]
515 "reload_completed"
516 [(set (match_dup 2)
517 (zero_extend:SI (match_dup 1)))
518 (set (match_dup 0)
519 (compare:CC (match_dup 2)
520 (const_int 0)))]
521 "")
1fd4e8c1
RK		 522
523(define_insn ""
9ebbca7d
GK		 524 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
525 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 526 (const_int 0)))
9ebbca7d 527 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 528 (zero_extend:SI (match_dup 1)))]
529 ""
9ebbca7d
GK		 530 "@
531 {andil.|andi.} %0,%1,0xff
532 #"
533 [(set_attr "type" "compare")
534 (set_attr "length" "4,8")])
535
536(define_split
537 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
538 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
539 (const_int 0)))
540 (set (match_operand:SI 0 "gpc_reg_operand" "")
541 (zero_extend:SI (match_dup 1)))]
542 "reload_completed"
543 [(set (match_dup 0)
544 (zero_extend:SI (match_dup 1)))
545 (set (match_dup 2)
546 (compare:CC (match_dup 0)
547 (const_int 0)))]
548 "")
1fd4e8c1 549
51b8fc2c
RK		 550(define_expand "extendqisi2"
551 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
552 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
553 ""
554 "
555{
556 if (TARGET_POWERPC)
557 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
558 else if (TARGET_POWER)
559 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
560 else
561 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
562 DONE;
563}")
564
565(define_insn "extendqisi2_ppc"
2bee0449
RK		 566 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
567 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 568 "TARGET_POWERPC"
44cd321e
PS		 569 "extsb %0,%1"
570 [(set_attr "type" "exts")])
51b8fc2c
RK		 571
572(define_insn ""
9ebbca7d
GK		 573 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
574 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 575 (const_int 0)))
9ebbca7d 576 (clobber (match_scratch:SI 2 "=r,r"))]
51b8fc2c 577 "TARGET_POWERPC"
9ebbca7d
GK		 578 "@
579 extsb. %2,%1
580 #"
581 [(set_attr "type" "compare")
582 (set_attr "length" "4,8")])
583
584(define_split
585 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
586 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
587 (const_int 0)))
588 (clobber (match_scratch:SI 2 ""))]
589 "TARGET_POWERPC && reload_completed"
590 [(set (match_dup 2)
591 (sign_extend:SI (match_dup 1)))
592 (set (match_dup 0)
593 (compare:CC (match_dup 2)
594 (const_int 0)))]
595 "")
51b8fc2c
RK		 596
597(define_insn ""
9ebbca7d
GK		 598 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
599 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 600 (const_int 0)))
9ebbca7d 601 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 602 (sign_extend:SI (match_dup 1)))]
603 "TARGET_POWERPC"
9ebbca7d
GK		 604 "@
605 extsb. %0,%1
606 #"
607 [(set_attr "type" "compare")
608 (set_attr "length" "4,8")])
609
610(define_split
611 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
612 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
613 (const_int 0)))
614 (set (match_operand:SI 0 "gpc_reg_operand" "")
615 (sign_extend:SI (match_dup 1)))]
616 "TARGET_POWERPC && reload_completed"
617 [(set (match_dup 0)
618 (sign_extend:SI (match_dup 1)))
619 (set (match_dup 2)
620 (compare:CC (match_dup 0)
621 (const_int 0)))]
622 "")
51b8fc2c
RK		 623
624(define_expand "extendqisi2_power"
625 [(parallel [(set (match_dup 2)
626 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
627 (const_int 24)))
628 (clobber (scratch:SI))])
629 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
630 (ashiftrt:SI (match_dup 2)
631 (const_int 24)))
632 (clobber (scratch:SI))])]
633 "TARGET_POWER"
634 "
635{ operands[1] = gen_lowpart (SImode, operands[1]);
636 operands[2] = gen_reg_rtx (SImode); }")
637
638(define_expand "extendqisi2_no_power"
639 [(set (match_dup 2)
640 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
641 (const_int 24)))
642 (set (match_operand:SI 0 "gpc_reg_operand" "")
643 (ashiftrt:SI (match_dup 2)
644 (const_int 24)))]
645 "! TARGET_POWER && ! TARGET_POWERPC"
646 "
647{ operands[1] = gen_lowpart (SImode, operands[1]);
648 operands[2] = gen_reg_rtx (SImode); }")
649
1fd4e8c1 650(define_expand "zero_extendqihi2"
cd2b37d9
RK		 651 [(set (match_operand:HI 0 "gpc_reg_operand" "")
652 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 653 ""
654 "")
655
656(define_insn ""
cd2b37d9 657 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 658 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
659 ""
660 "@
661 lbz%U1%X1 %0,%1
005a35b9 662 {rlinm|rlwinm} %0,%1,0,0xff"
51b8fc2c
RK		 663 [(set_attr "type" "load,*")])
664
665(define_insn ""
9ebbca7d
GK		 666 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
667 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 668 (const_int 0)))
9ebbca7d 669 (clobber (match_scratch:HI 2 "=r,r"))]
51b8fc2c 670 ""
9ebbca7d
GK		 671 "@
672 {andil.|andi.} %2,%1,0xff
673 #"
674 [(set_attr "type" "compare")
675 (set_attr "length" "4,8")])
676
677(define_split
678 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
679 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
680 (const_int 0)))
681 (clobber (match_scratch:HI 2 ""))]
682 "reload_completed"
683 [(set (match_dup 2)
684 (zero_extend:HI (match_dup 1)))
685 (set (match_dup 0)
686 (compare:CC (match_dup 2)
687 (const_int 0)))]
688 "")
1fd4e8c1 689
51b8fc2c 690(define_insn ""
9ebbca7d
GK		 691 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
692 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 693 (const_int 0)))
9ebbca7d 694 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 695 (zero_extend:HI (match_dup 1)))]
696 ""
9ebbca7d
GK		 697 "@
698 {andil.|andi.} %0,%1,0xff
699 #"
700 [(set_attr "type" "compare")
701 (set_attr "length" "4,8")])
702
703(define_split
704 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
705 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
706 (const_int 0)))
707 (set (match_operand:HI 0 "gpc_reg_operand" "")
708 (zero_extend:HI (match_dup 1)))]
709 "reload_completed"
710 [(set (match_dup 0)
711 (zero_extend:HI (match_dup 1)))
712 (set (match_dup 2)
713 (compare:CC (match_dup 0)
714 (const_int 0)))]
715 "")
815cdc52
MM		 716
717(define_expand "extendqihi2"
718 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
719 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
720 ""
721 "
722{
723 if (TARGET_POWERPC)
724 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
725 else if (TARGET_POWER)
726 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
727 else
728 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
729 DONE;
730}")
731
732(define_insn "extendqihi2_ppc"
733 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
734 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
735 "TARGET_POWERPC"
44cd321e
PS		 736 "extsb %0,%1"
737 [(set_attr "type" "exts")])
815cdc52
MM		 738
739(define_insn ""
9ebbca7d
GK		 740 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
741 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815cdc52 742 (const_int 0)))
9ebbca7d 743 (clobber (match_scratch:HI 2 "=r,r"))]
815cdc52 744 "TARGET_POWERPC"
9ebbca7d
GK		 745 "@
746 extsb. %2,%1
747 #"
748 [(set_attr "type" "compare")
749 (set_attr "length" "4,8")])
750
751(define_split
752 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
753 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
754 (const_int 0)))
755 (clobber (match_scratch:HI 2 ""))]
756 "TARGET_POWERPC && reload_completed"
757 [(set (match_dup 2)
758 (sign_extend:HI (match_dup 1)))
759 (set (match_dup 0)
760 (compare:CC (match_dup 2)
761 (const_int 0)))]
762 "")
815cdc52
MM		 763
764(define_insn ""
9ebbca7d
GK		 765 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
766 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 767 (const_int 0)))
9ebbca7d 768 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 769 (sign_extend:HI (match_dup 1)))]
770 "TARGET_POWERPC"
9ebbca7d
GK		 771 "@
772 extsb. %0,%1
773 #"
774 [(set_attr "type" "compare")
775 (set_attr "length" "4,8")])
776
777(define_split
778 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
779 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
780 (const_int 0)))
781 (set (match_operand:HI 0 "gpc_reg_operand" "")
782 (sign_extend:HI (match_dup 1)))]
783 "TARGET_POWERPC && reload_completed"
784 [(set (match_dup 0)
785 (sign_extend:HI (match_dup 1)))
786 (set (match_dup 2)
787 (compare:CC (match_dup 0)
788 (const_int 0)))]
789 "")
51b8fc2c
RK		 790
791(define_expand "extendqihi2_power"
792 [(parallel [(set (match_dup 2)
793 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
794 (const_int 24)))
795 (clobber (scratch:SI))])
796 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
797 (ashiftrt:SI (match_dup 2)
798 (const_int 24)))
799 (clobber (scratch:SI))])]
800 "TARGET_POWER"
801 "
802{ operands[0] = gen_lowpart (SImode, operands[0]);
803 operands[1] = gen_lowpart (SImode, operands[1]);
804 operands[2] = gen_reg_rtx (SImode); }")
805
806(define_expand "extendqihi2_no_power"
807 [(set (match_dup 2)
808 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
809 (const_int 24)))
810 (set (match_operand:HI 0 "gpc_reg_operand" "")
811 (ashiftrt:SI (match_dup 2)
812 (const_int 24)))]
813 "! TARGET_POWER && ! TARGET_POWERPC"
814 "
815{ operands[0] = gen_lowpart (SImode, operands[0]);
816 operands[1] = gen_lowpart (SImode, operands[1]);
817 operands[2] = gen_reg_rtx (SImode); }")
818
1fd4e8c1 819(define_expand "zero_extendhisi2"
5f243543 820 [(set (match_operand:SI 0 "gpc_reg_operand" "")
cd2b37d9 821 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 822 ""
823 "")
824
825(define_insn ""
cd2b37d9 826 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 827 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
828 ""
829 "@
830 lhz%U1%X1 %0,%1
005a35b9 831 {rlinm|rlwinm} %0,%1,0,0xffff"
1fd4e8c1
RK		 832 [(set_attr "type" "load,*")])
833
834(define_insn ""
9ebbca7d
GK		 835 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
836 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 837 (const_int 0)))
9ebbca7d 838 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 839 ""
9ebbca7d
GK		 840 "@
841 {andil.|andi.} %2,%1,0xffff
842 #"
843 [(set_attr "type" "compare")
844 (set_attr "length" "4,8")])
845
846(define_split
847 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
848 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
849 (const_int 0)))
850 (clobber (match_scratch:SI 2 ""))]
851 "reload_completed"
852 [(set (match_dup 2)
853 (zero_extend:SI (match_dup 1)))
854 (set (match_dup 0)
855 (compare:CC (match_dup 2)
856 (const_int 0)))]
857 "")
1fd4e8c1
RK		 858
859(define_insn ""
9ebbca7d
GK		 860 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
861 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 862 (const_int 0)))
9ebbca7d 863 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 864 (zero_extend:SI (match_dup 1)))]
865 ""
9ebbca7d
GK		 866 "@
867 {andil.|andi.} %0,%1,0xffff
868 #"
869 [(set_attr "type" "compare")
870 (set_attr "length" "4,8")])
871
872(define_split
873 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
874 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
875 (const_int 0)))
876 (set (match_operand:SI 0 "gpc_reg_operand" "")
877 (zero_extend:SI (match_dup 1)))]
878 "reload_completed"
879 [(set (match_dup 0)
880 (zero_extend:SI (match_dup 1)))
881 (set (match_dup 2)
882 (compare:CC (match_dup 0)
883 (const_int 0)))]
884 "")
1fd4e8c1
RK		 885
886(define_expand "extendhisi2"
cd2b37d9
RK		 887 [(set (match_operand:SI 0 "gpc_reg_operand" "")
888 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 889 ""
890 "")
891
892(define_insn ""
cd2b37d9 893 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 894 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
895 ""
896 "@
897 lha%U1%X1 %0,%1
ca7f5001 898 {exts|extsh} %0,%1"
44cd321e 899 [(set_attr "type" "load_ext,exts")])
1fd4e8c1
RK		 900
901(define_insn ""
9ebbca7d
GK		 902 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
903 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 904 (const_int 0)))
9ebbca7d 905 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 906 ""
9ebbca7d
GK		 907 "@
908 {exts.|extsh.} %2,%1
909 #"
910 [(set_attr "type" "compare")
911 (set_attr "length" "4,8")])
912
913(define_split
914 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
915 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
916 (const_int 0)))
917 (clobber (match_scratch:SI 2 ""))]
918 "reload_completed"
919 [(set (match_dup 2)
920 (sign_extend:SI (match_dup 1)))
921 (set (match_dup 0)
922 (compare:CC (match_dup 2)
923 (const_int 0)))]
924 "")
1fd4e8c1
RK		 925
926(define_insn ""
9ebbca7d
GK		 927 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
928 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 929 (const_int 0)))
9ebbca7d 930 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 931 (sign_extend:SI (match_dup 1)))]
932 ""
9ebbca7d
GK		 933 "@
934 {exts.|extsh.} %0,%1
935 #"
936 [(set_attr "type" "compare")
937 (set_attr "length" "4,8")])
1fd4e8c1 938\f
131aeb82
JM		 939;; IBM 405 and 440 half-word multiplication operations.
940
941(define_insn "*macchwc"
942 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
943 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
944 (match_operand:SI 2 "gpc_reg_operand" "r")
945 (const_int 16))
946 (sign_extend:SI
947 (match_operand:HI 1 "gpc_reg_operand" "r")))
948 (match_operand:SI 4 "gpc_reg_operand" "0"))
949 (const_int 0)))
950 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
951 (plus:SI (mult:SI (ashiftrt:SI
952 (match_dup 2)
953 (const_int 16))
954 (sign_extend:SI
955 (match_dup 1)))
956 (match_dup 4)))]
957 "TARGET_MULHW"
958 "macchw. %0, %1, %2"
959 [(set_attr "type" "imul3")])
960
961(define_insn "*macchw"
962 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
963 (plus:SI (mult:SI (ashiftrt:SI
964 (match_operand:SI 2 "gpc_reg_operand" "r")
965 (const_int 16))
966 (sign_extend:SI
967 (match_operand:HI 1 "gpc_reg_operand" "r")))
968 (match_operand:SI 3 "gpc_reg_operand" "0")))]
969 "TARGET_MULHW"
970 "macchw %0, %1, %2"
971 [(set_attr "type" "imul3")])
972
973(define_insn "*macchwuc"
974 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
975 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
976 (match_operand:SI 2 "gpc_reg_operand" "r")
977 (const_int 16))
978 (zero_extend:SI
979 (match_operand:HI 1 "gpc_reg_operand" "r")))
980 (match_operand:SI 4 "gpc_reg_operand" "0"))
981 (const_int 0)))
982 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
983 (plus:SI (mult:SI (lshiftrt:SI
984 (match_dup 2)
985 (const_int 16))
986 (zero_extend:SI
987 (match_dup 1)))
988 (match_dup 4)))]
989 "TARGET_MULHW"
990 "macchwu. %0, %1, %2"
991 [(set_attr "type" "imul3")])
992
993(define_insn "*macchwu"
994 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
995 (plus:SI (mult:SI (lshiftrt:SI
996 (match_operand:SI 2 "gpc_reg_operand" "r")
997 (const_int 16))
998 (zero_extend:SI
999 (match_operand:HI 1 "gpc_reg_operand" "r")))
1000 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1001 "TARGET_MULHW"
1002 "macchwu %0, %1, %2"
1003 [(set_attr "type" "imul3")])
1004
1005(define_insn "*machhwc"
1006 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1007 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1008 (match_operand:SI 1 "gpc_reg_operand" "%r")
1009 (const_int 16))
1010 (ashiftrt:SI
1011 (match_operand:SI 2 "gpc_reg_operand" "r")
1012 (const_int 16)))
1013 (match_operand:SI 4 "gpc_reg_operand" "0"))
1014 (const_int 0)))
1015 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1016 (plus:SI (mult:SI (ashiftrt:SI
1017 (match_dup 1)
1018 (const_int 16))
1019 (ashiftrt:SI
1020 (match_dup 2)
1021 (const_int 16)))
1022 (match_dup 4)))]
1023 "TARGET_MULHW"
1024 "machhw. %0, %1, %2"
1025 [(set_attr "type" "imul3")])
1026
1027(define_insn "*machhw"
1028 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1029 (plus:SI (mult:SI (ashiftrt:SI
1030 (match_operand:SI 1 "gpc_reg_operand" "%r")
1031 (const_int 16))
1032 (ashiftrt:SI
1033 (match_operand:SI 2 "gpc_reg_operand" "r")
1034 (const_int 16)))
1035 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1036 "TARGET_MULHW"
1037 "machhw %0, %1, %2"
1038 [(set_attr "type" "imul3")])
1039
1040(define_insn "*machhwuc"
1041 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1042 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1043 (match_operand:SI 1 "gpc_reg_operand" "%r")
1044 (const_int 16))
1045 (lshiftrt:SI
1046 (match_operand:SI 2 "gpc_reg_operand" "r")
1047 (const_int 16)))
1048 (match_operand:SI 4 "gpc_reg_operand" "0"))
1049 (const_int 0)))
1050 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1051 (plus:SI (mult:SI (lshiftrt:SI
1052 (match_dup 1)
1053 (const_int 16))
1054 (lshiftrt:SI
1055 (match_dup 2)
1056 (const_int 16)))
1057 (match_dup 4)))]
1058 "TARGET_MULHW"
1059 "machhwu. %0, %1, %2"
1060 [(set_attr "type" "imul3")])
1061
1062(define_insn "*machhwu"
1063 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1064 (plus:SI (mult:SI (lshiftrt:SI
1065 (match_operand:SI 1 "gpc_reg_operand" "%r")
1066 (const_int 16))
1067 (lshiftrt:SI
1068 (match_operand:SI 2 "gpc_reg_operand" "r")
1069 (const_int 16)))
1070 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1071 "TARGET_MULHW"
1072 "machhwu %0, %1, %2"
1073 [(set_attr "type" "imul3")])
1074
1075(define_insn "*maclhwc"
1076 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1077 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1078 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1079 (sign_extend:SI
1080 (match_operand:HI 2 "gpc_reg_operand" "r")))
1081 (match_operand:SI 4 "gpc_reg_operand" "0"))
1082 (const_int 0)))
1083 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1084 (plus:SI (mult:SI (sign_extend:SI
1085 (match_dup 1))
1086 (sign_extend:SI
1087 (match_dup 2)))
1088 (match_dup 4)))]
1089 "TARGET_MULHW"
1090 "maclhw. %0, %1, %2"
1091 [(set_attr "type" "imul3")])
1092
1093(define_insn "*maclhw"
1094 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1095 (plus:SI (mult:SI (sign_extend:SI
1096 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1097 (sign_extend:SI
1098 (match_operand:HI 2 "gpc_reg_operand" "r")))
1099 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1100 "TARGET_MULHW"
1101 "maclhw %0, %1, %2"
1102 [(set_attr "type" "imul3")])
1103
1104(define_insn "*maclhwuc"
1105 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1106 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1107 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1108 (zero_extend:SI
1109 (match_operand:HI 2 "gpc_reg_operand" "r")))
1110 (match_operand:SI 4 "gpc_reg_operand" "0"))
1111 (const_int 0)))
1112 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1113 (plus:SI (mult:SI (zero_extend:SI
1114 (match_dup 1))
1115 (zero_extend:SI
1116 (match_dup 2)))
1117 (match_dup 4)))]
1118 "TARGET_MULHW"
1119 "maclhwu. %0, %1, %2"
1120 [(set_attr "type" "imul3")])
1121
1122(define_insn "*maclhwu"
1123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1124 (plus:SI (mult:SI (zero_extend:SI
1125 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1126 (zero_extend:SI
1127 (match_operand:HI 2 "gpc_reg_operand" "r")))
1128 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1129 "TARGET_MULHW"
1130 "maclhwu %0, %1, %2"
1131 [(set_attr "type" "imul3")])
1132
1133(define_insn "*nmacchwc"
1134 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1135 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1136 (mult:SI (ashiftrt:SI
1137 (match_operand:SI 2 "gpc_reg_operand" "r")
1138 (const_int 16))
1139 (sign_extend:SI
1140 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1141 (const_int 0)))
1142 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1143 (minus:SI (match_dup 4)
1144 (mult:SI (ashiftrt:SI
1145 (match_dup 2)
1146 (const_int 16))
1147 (sign_extend:SI
1148 (match_dup 1)))))]
1149 "TARGET_MULHW"
1150 "nmacchw. %0, %1, %2"
1151 [(set_attr "type" "imul3")])
1152
1153(define_insn "*nmacchw"
1154 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1155 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1156 (mult:SI (ashiftrt:SI
1157 (match_operand:SI 2 "gpc_reg_operand" "r")
1158 (const_int 16))
1159 (sign_extend:SI
1160 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1161 "TARGET_MULHW"
1162 "nmacchw %0, %1, %2"
1163 [(set_attr "type" "imul3")])
1164
1165(define_insn "*nmachhwc"
1166 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1167 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1168 (mult:SI (ashiftrt:SI
1169 (match_operand:SI 1 "gpc_reg_operand" "%r")
1170 (const_int 16))
1171 (ashiftrt:SI
1172 (match_operand:SI 2 "gpc_reg_operand" "r")
1173 (const_int 16))))
1174 (const_int 0)))
1175 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1176 (minus:SI (match_dup 4)
1177 (mult:SI (ashiftrt:SI
1178 (match_dup 1)
1179 (const_int 16))
1180 (ashiftrt:SI
1181 (match_dup 2)
1182 (const_int 16)))))]
1183 "TARGET_MULHW"
1184 "nmachhw. %0, %1, %2"
1185 [(set_attr "type" "imul3")])
1186
1187(define_insn "*nmachhw"
1188 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1189 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1190 (mult:SI (ashiftrt:SI
1191 (match_operand:SI 1 "gpc_reg_operand" "%r")
1192 (const_int 16))
1193 (ashiftrt:SI
1194 (match_operand:SI 2 "gpc_reg_operand" "r")
1195 (const_int 16)))))]
1196 "TARGET_MULHW"
1197 "nmachhw %0, %1, %2"
1198 [(set_attr "type" "imul3")])
1199
1200(define_insn "*nmaclhwc"
1201 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1202 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1203 (mult:SI (sign_extend:SI
1204 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1205 (sign_extend:SI
1206 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1207 (const_int 0)))
1208 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1209 (minus:SI (match_dup 4)
1210 (mult:SI (sign_extend:SI
1211 (match_dup 1))
1212 (sign_extend:SI
1213 (match_dup 2)))))]
1214 "TARGET_MULHW"
1215 "nmaclhw. %0, %1, %2"
1216 [(set_attr "type" "imul3")])
1217
1218(define_insn "*nmaclhw"
1219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1220 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1221 (mult:SI (sign_extend:SI
1222 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1223 (sign_extend:SI
1224 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1225 "TARGET_MULHW"
1226 "nmaclhw %0, %1, %2"
1227 [(set_attr "type" "imul3")])
1228
1229(define_insn "*mulchwc"
1230 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1231 (compare:CC (mult:SI (ashiftrt:SI
1232 (match_operand:SI 2 "gpc_reg_operand" "r")
1233 (const_int 16))
1234 (sign_extend:SI
1235 (match_operand:HI 1 "gpc_reg_operand" "r")))
1236 (const_int 0)))
1237 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1238 (mult:SI (ashiftrt:SI
1239 (match_dup 2)
1240 (const_int 16))
1241 (sign_extend:SI
1242 (match_dup 1))))]
1243 "TARGET_MULHW"
1244 "mulchw. %0, %1, %2"
1245 [(set_attr "type" "imul3")])
1246
1247(define_insn "*mulchw"
1248 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1249 (mult:SI (ashiftrt:SI
1250 (match_operand:SI 2 "gpc_reg_operand" "r")
1251 (const_int 16))
1252 (sign_extend:SI
1253 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1254 "TARGET_MULHW"
1255 "mulchw %0, %1, %2"
1256 [(set_attr "type" "imul3")])
1257
1258(define_insn "*mulchwuc"
1259 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1260 (compare:CC (mult:SI (lshiftrt:SI
1261 (match_operand:SI 2 "gpc_reg_operand" "r")
1262 (const_int 16))
1263 (zero_extend:SI
1264 (match_operand:HI 1 "gpc_reg_operand" "r")))
1265 (const_int 0)))
1266 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1267 (mult:SI (lshiftrt:SI
1268 (match_dup 2)
1269 (const_int 16))
1270 (zero_extend:SI
1271 (match_dup 1))))]
1272 "TARGET_MULHW"
1273 "mulchwu. %0, %1, %2"
1274 [(set_attr "type" "imul3")])
1275
1276(define_insn "*mulchwu"
1277 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1278 (mult:SI (lshiftrt:SI
1279 (match_operand:SI 2 "gpc_reg_operand" "r")
1280 (const_int 16))
1281 (zero_extend:SI
1282 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1283 "TARGET_MULHW"
1284 "mulchwu %0, %1, %2"
1285 [(set_attr "type" "imul3")])
1286
1287(define_insn "*mulhhwc"
1288 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1289 (compare:CC (mult:SI (ashiftrt:SI
1290 (match_operand:SI 1 "gpc_reg_operand" "%r")
1291 (const_int 16))
1292 (ashiftrt:SI
1293 (match_operand:SI 2 "gpc_reg_operand" "r")
1294 (const_int 16)))
1295 (const_int 0)))
1296 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1297 (mult:SI (ashiftrt:SI
1298 (match_dup 1)
1299 (const_int 16))
1300 (ashiftrt:SI
1301 (match_dup 2)
1302 (const_int 16))))]
1303 "TARGET_MULHW"
1304 "mulhhw. %0, %1, %2"
1305 [(set_attr "type" "imul3")])
1306
1307(define_insn "*mulhhw"
1308 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1309 (mult:SI (ashiftrt:SI
1310 (match_operand:SI 1 "gpc_reg_operand" "%r")
1311 (const_int 16))
1312 (ashiftrt:SI
1313 (match_operand:SI 2 "gpc_reg_operand" "r")
1314 (const_int 16))))]
1315 "TARGET_MULHW"
1316 "mulhhw %0, %1, %2"
1317 [(set_attr "type" "imul3")])
1318
1319(define_insn "*mulhhwuc"
1320 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1321 (compare:CC (mult:SI (lshiftrt:SI
1322 (match_operand:SI 1 "gpc_reg_operand" "%r")
1323 (const_int 16))
1324 (lshiftrt:SI
1325 (match_operand:SI 2 "gpc_reg_operand" "r")
1326 (const_int 16)))
1327 (const_int 0)))
1328 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1329 (mult:SI (lshiftrt:SI
1330 (match_dup 1)
1331 (const_int 16))
1332 (lshiftrt:SI
1333 (match_dup 2)
1334 (const_int 16))))]
1335 "TARGET_MULHW"
1336 "mulhhwu. %0, %1, %2"
1337 [(set_attr "type" "imul3")])
1338
1339(define_insn "*mulhhwu"
1340 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1341 (mult:SI (lshiftrt:SI
1342 (match_operand:SI 1 "gpc_reg_operand" "%r")
1343 (const_int 16))
1344 (lshiftrt:SI
1345 (match_operand:SI 2 "gpc_reg_operand" "r")
1346 (const_int 16))))]
1347 "TARGET_MULHW"
1348 "mulhhwu %0, %1, %2"
1349 [(set_attr "type" "imul3")])
1350
1351(define_insn "*mullhwc"
1352 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1353 (compare:CC (mult:SI (sign_extend:SI
1354 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1355 (sign_extend:SI
1356 (match_operand:HI 2 "gpc_reg_operand" "r")))
1357 (const_int 0)))
1358 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1359 (mult:SI (sign_extend:SI
1360 (match_dup 1))
1361 (sign_extend:SI
1362 (match_dup 2))))]
1363 "TARGET_MULHW"
1364 "mullhw. %0, %1, %2"
1365 [(set_attr "type" "imul3")])
1366
1367(define_insn "*mullhw"
1368 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1369 (mult:SI (sign_extend:SI
1370 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1371 (sign_extend:SI
1372 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1373 "TARGET_MULHW"
1374 "mullhw %0, %1, %2"
1375 [(set_attr "type" "imul3")])
1376
1377(define_insn "*mullhwuc"
1378 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1379 (compare:CC (mult:SI (zero_extend:SI
1380 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1381 (zero_extend:SI
1382 (match_operand:HI 2 "gpc_reg_operand" "r")))
1383 (const_int 0)))
1384 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1385 (mult:SI (zero_extend:SI
1386 (match_dup 1))
1387 (zero_extend:SI
1388 (match_dup 2))))]
1389 "TARGET_MULHW"
1390 "mullhwu. %0, %1, %2"
1391 [(set_attr "type" "imul3")])
1392
1393(define_insn "*mullhwu"
1394 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1395 (mult:SI (zero_extend:SI
1396 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1397 (zero_extend:SI
1398 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1399 "TARGET_MULHW"
1400 "mullhwu %0, %1, %2"
1401 [(set_attr "type" "imul3")])
1402\f
716019c0
JM		 1403;; IBM 405 and 440 string-search dlmzb instruction support.
1404(define_insn "dlmzb"
1405 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1406 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1407 (match_operand:SI 2 "gpc_reg_operand" "r")]
1408 UNSPEC_DLMZB_CR))
1409 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1410 (unspec:SI [(match_dup 1)
1411 (match_dup 2)]
1412 UNSPEC_DLMZB))]
1413 "TARGET_DLMZB"
1414 "dlmzb. %0, %1, %2")
1415
1416(define_expand "strlensi"
1417 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1418 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1419 (match_operand:QI 2 "const_int_operand" "")
1420 (match_operand 3 "const_int_operand" "")]
1421 UNSPEC_DLMZB_STRLEN))
1422 (clobber (match_scratch:CC 4 "=x"))]
1423 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1424{
1425 rtx result = operands[0];
1426 rtx src = operands[1];
1427 rtx search_char = operands[2];
1428 rtx align = operands[3];
1429 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1430 rtx loop_label, end_label, mem, cr0, cond;
1431 if (search_char != const0_rtx
1432 || GET_CODE (align) != CONST_INT
1433 || INTVAL (align) < 8)
1434 FAIL;
1435 word1 = gen_reg_rtx (SImode);
1436 word2 = gen_reg_rtx (SImode);
1437 scratch_dlmzb = gen_reg_rtx (SImode);
1438 scratch_string = gen_reg_rtx (Pmode);
1439 loop_label = gen_label_rtx ();
1440 end_label = gen_label_rtx ();
1441 addr = force_reg (Pmode, XEXP (src, 0));
1442 emit_move_insn (scratch_string, addr);
1443 emit_label (loop_label);
1444 mem = change_address (src, SImode, scratch_string);
1445 emit_move_insn (word1, mem);
1446 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1447 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1448 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1449 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1450 emit_jump_insn (gen_rtx_SET (VOIDmode,
1451 pc_rtx,
1452 gen_rtx_IF_THEN_ELSE (VOIDmode,
1453 cond,
1454 gen_rtx_LABEL_REF
1455 (VOIDmode,
1456 end_label),
1457 pc_rtx)));
1458 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1459 emit_jump_insn (gen_rtx_SET (VOIDmode,
1460 pc_rtx,
1461 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
ea5bd0d8 1462 emit_barrier ();
716019c0
JM		 1463 emit_label (end_label);
1464 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1465 emit_insn (gen_subsi3 (result, scratch_string, addr));
1466 emit_insn (gen_subsi3 (result, result, const1_rtx));
1467 DONE;
1468})
1469\f
9ebbca7d
GK		 1470(define_split
1471 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1472 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1473 (const_int 0)))
1474 (set (match_operand:SI 0 "gpc_reg_operand" "")
1475 (sign_extend:SI (match_dup 1)))]
1476 "reload_completed"
1477 [(set (match_dup 0)
1478 (sign_extend:SI (match_dup 1)))
1479 (set (match_dup 2)
1480 (compare:CC (match_dup 0)
1481 (const_int 0)))]
1482 "")
1483
1fd4e8c1 1484;; Fixed-point arithmetic insns.
deb9225a 1485
0354e5d8
GK		 1486(define_expand "add<mode>3"
1487 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1488 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
4ae234b0 1489 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
7cd5235b 1490 ""
7cd5235b 1491{
0354e5d8
GK		 1492 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1493 {
1494 if (non_short_cint_operand (operands[2], DImode))
1495 FAIL;
1496 }
1497 else if (GET_CODE (operands[2]) == CONST_INT
1498 && ! add_operand (operands[2], <MODE>mode))
7cd5235b 1499 {
b3a13419
ILT		 1500 rtx tmp = ((!can_create_pseudo_p ()
1501 || rtx_equal_p (operands[0], operands[1]))
0354e5d8 1502 ? operands[0] : gen_reg_rtx (<MODE>mode));
7cd5235b 1503
2bfcf297 1504 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1505 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8
GK		 1506 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1507
279bb624 1508 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
0354e5d8 1509 FAIL;
7cd5235b 1510
9ebbca7d
GK		 1511 /* The ordering here is important for the prolog expander.
1512 When space is allocated from the stack, adding 'low' first may
1513 produce a temporary deallocation (which would be bad). */
0354e5d8
GK		 1514 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1515 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
7cd5235b
MM		 1516 DONE;
1517 }
279bb624 1518})
7cd5235b 1519
0354e5d8
GK		 1520;; Discourage ai/addic because of carry but provide it in an alternative
1521;; allowing register zero as source.
1522(define_insn "*add<mode>3_internal1"
1523 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1524 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1525 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
7393f7f8 1526 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1fd4e8c1 1527 "@
deb9225a
RK		 1528 {cax|add} %0,%1,%2
1529 {cal %0,%2(%1)|addi %0,%1,%2}
1530 {ai|addic} %0,%1,%2
7cd5235b
MM		 1531 {cau|addis} %0,%1,%v2"
1532 [(set_attr "length" "4,4,4,4")])
1fd4e8c1 1533
ee890fe2
SS		 1534(define_insn "addsi3_high"
1535 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1536 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1537 (high:SI (match_operand 2 "" ""))))]
1538 "TARGET_MACHO && !TARGET_64BIT"
1539 "{cau|addis} %0,%1,ha16(%2)"
1540 [(set_attr "length" "4")])
1541
0354e5d8 1542(define_insn "*add<mode>3_internal2"
cb8cc086 1543 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1544 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1545 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1546 (const_int 0)))
0354e5d8
GK		 1547 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1548 ""
deb9225a
RK		 1549 "@
1550 {cax.|add.} %3,%1,%2
cb8cc086
MM		 1551 {ai.|addic.} %3,%1,%2
1552 #
1553 #"
a62bfff2 1554 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1555 (set_attr "length" "4,4,8,8")])
1556
1557(define_split
1558 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1559 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1560 (match_operand:GPR 2 "reg_or_short_operand" ""))
cb8cc086 1561 (const_int 0)))
0354e5d8
GK		 1562 (clobber (match_scratch:GPR 3 ""))]
1563 "reload_completed"
cb8cc086 1564 [(set (match_dup 3)
0354e5d8 1565 (plus:GPR (match_dup 1)
cb8cc086
MM		 1566 (match_dup 2)))
1567 (set (match_dup 0)
1568 (compare:CC (match_dup 3)
1569 (const_int 0)))]
1570 "")
7e69e155 1571
0354e5d8 1572(define_insn "*add<mode>3_internal3"
cb8cc086 1573 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1574 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1575 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1576 (const_int 0)))
0354e5d8
GK		 1577 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1578 (plus:P (match_dup 1)
1579 (match_dup 2)))]
1580 ""
deb9225a
RK		 1581 "@
1582 {cax.|add.} %0,%1,%2
cb8cc086
MM		 1583 {ai.|addic.} %0,%1,%2
1584 #
1585 #"
a62bfff2 1586 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1587 (set_attr "length" "4,4,8,8")])
1588
1589(define_split
1590 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1591 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1592 (match_operand:P 2 "reg_or_short_operand" ""))
cb8cc086 1593 (const_int 0)))
0354e5d8
GK		 1594 (set (match_operand:P 0 "gpc_reg_operand" "")
1595 (plus:P (match_dup 1) (match_dup 2)))]
1596 "reload_completed"
cb8cc086 1597 [(set (match_dup 0)
0354e5d8
GK		 1598 (plus:P (match_dup 1)
1599 (match_dup 2)))
cb8cc086
MM		 1600 (set (match_dup 3)
1601 (compare:CC (match_dup 0)
1602 (const_int 0)))]
1603 "")
7e69e155 1604
f357808b
RK		 1605;; Split an add that we can't do in one insn into two insns, each of which
1606;; does one 16-bit part. This is used by combine. Note that the low-order
1607;; add should be last in case the result gets used in an address.
1608
1609(define_split
0354e5d8
GK		 1610 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1611 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1612 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1fd4e8c1 1613 ""
0354e5d8
GK		 1614 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1615 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1fd4e8c1 1616{
2bfcf297 1617 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1618 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8 1619 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1fd4e8c1 1620
e6ca2c17 1621 operands[4] = GEN_INT (low);
279bb624 1622 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
0354e5d8 1623 operands[3] = GEN_INT (rest);
b3a13419 1624 else if (can_create_pseudo_p ())
0354e5d8
GK		 1625 {
1626 operands[3] = gen_reg_rtx (DImode);
1627 emit_move_insn (operands[3], operands[2]);
1628 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1629 DONE;
1630 }
1631 else
1632 FAIL;
279bb624 1633})
1fd4e8c1 1634
0354e5d8
GK		 1635(define_insn "one_cmpl<mode>2"
1636 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1637 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1 1638 ""
ca7f5001
RK		 1639 "nor %0,%1,%1")
1640
1641(define_insn ""
52d3af72 1642 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 1643 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
ca7f5001 1644 (const_int 0)))
0354e5d8
GK		 1645 (clobber (match_scratch:P 2 "=r,r"))]
1646 ""
52d3af72
DE		 1647 "@
1648 nor. %2,%1,%1
1649 #"
1650 [(set_attr "type" "compare")
1651 (set_attr "length" "4,8")])
1652
1653(define_split
1654 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 1655 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1656 (const_int 0)))
0354e5d8
GK		 1657 (clobber (match_scratch:P 2 ""))]
1658 "reload_completed"
52d3af72 1659 [(set (match_dup 2)
0354e5d8 1660 (not:P (match_dup 1)))
52d3af72
DE		 1661 (set (match_dup 0)
1662 (compare:CC (match_dup 2)
1663 (const_int 0)))]
1664 "")
ca7f5001
RK		 1665
1666(define_insn ""
52d3af72 1667 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 1668 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 1669 (const_int 0)))
0354e5d8
GK		 1670 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1671 (not:P (match_dup 1)))]
1672 ""
52d3af72
DE		 1673 "@
1674 nor. %0,%1,%1
1675 #"
1676 [(set_attr "type" "compare")
1677 (set_attr "length" "4,8")])
1678
1679(define_split
1680 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 1681 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1682 (const_int 0)))
0354e5d8
GK		 1683 (set (match_operand:P 0 "gpc_reg_operand" "")
1684 (not:P (match_dup 1)))]
1685 "reload_completed"
52d3af72 1686 [(set (match_dup 0)
0354e5d8 1687 (not:P (match_dup 1)))
52d3af72
DE		 1688 (set (match_dup 2)
1689 (compare:CC (match_dup 0)
1690 (const_int 0)))]
1691 "")
1fd4e8c1
RK		 1692
1693(define_insn ""
3d91674b
RK		 1694 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1695 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1696 (match_operand:SI 2 "gpc_reg_operand" "r")))]
deb9225a 1697 "! TARGET_POWERPC"
ca7f5001 1698 "{sf%I1|subf%I1c} %0,%2,%1")
1fd4e8c1 1699
deb9225a 1700(define_insn ""
0354e5d8
GK		 1701 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1702 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1703 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
deb9225a
RK		 1704 "TARGET_POWERPC"
1705 "@
1706 subf %0,%2,%1
1707 subfic %0,%2,%1")
1708
1fd4e8c1 1709(define_insn ""
cb8cc086
MM		 1710 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1711 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1712 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1713 (const_int 0)))
cb8cc086 1714 (clobber (match_scratch:SI 3 "=r,r"))]
deb9225a 1715 "! TARGET_POWERPC"
cb8cc086
MM		 1716 "@
1717 {sf.|subfc.} %3,%2,%1
1718 #"
1719 [(set_attr "type" "compare")
1720 (set_attr "length" "4,8")])
1fd4e8c1 1721
deb9225a 1722(define_insn ""
cb8cc086 1723 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1724 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1725 (match_operand:P 2 "gpc_reg_operand" "r,r"))
deb9225a 1726 (const_int 0)))
0354e5d8
GK		 1727 (clobber (match_scratch:P 3 "=r,r"))]
1728 "TARGET_POWERPC"
cb8cc086
MM		 1729 "@
1730 subf. %3,%2,%1
1731 #"
a62bfff2 1732 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1733 (set_attr "length" "4,8")])
1734
1735(define_split
1736 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1737 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1738 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1739 (const_int 0)))
0354e5d8
GK		 1740 (clobber (match_scratch:P 3 ""))]
1741 "reload_completed"
cb8cc086 1742 [(set (match_dup 3)
0354e5d8 1743 (minus:P (match_dup 1)
cb8cc086
MM		 1744 (match_dup 2)))
1745 (set (match_dup 0)
1746 (compare:CC (match_dup 3)
1747 (const_int 0)))]
1748 "")
deb9225a 1749
1fd4e8c1 1750(define_insn ""
cb8cc086
MM		 1751 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1752 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1753 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1754 (const_int 0)))
cb8cc086 1755 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 1756 (minus:SI (match_dup 1) (match_dup 2)))]
deb9225a 1757 "! TARGET_POWERPC"
cb8cc086
MM		 1758 "@
1759 {sf.|subfc.} %0,%2,%1
1760 #"
1761 [(set_attr "type" "compare")
1762 (set_attr "length" "4,8")])
815cdc52 1763
29ae5b89 1764(define_insn ""
cb8cc086 1765 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1766 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1767 (match_operand:P 2 "gpc_reg_operand" "r,r"))
815cdc52 1768 (const_int 0)))
0354e5d8
GK		 1769 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1770 (minus:P (match_dup 1)
cb8cc086 1771 (match_dup 2)))]
0354e5d8 1772 "TARGET_POWERPC"
90612787
DE		 1773 "@
1774 subf. %0,%2,%1
1775 #"
a62bfff2 1776 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1777 (set_attr "length" "4,8")])
1778
1779(define_split
1780 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1781 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1782 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1783 (const_int 0)))
0354e5d8
GK		 1784 (set (match_operand:P 0 "gpc_reg_operand" "")
1785 (minus:P (match_dup 1)
cb8cc086 1786 (match_dup 2)))]
0354e5d8 1787 "reload_completed"
cb8cc086 1788 [(set (match_dup 0)
0354e5d8 1789 (minus:P (match_dup 1)
cb8cc086
MM		 1790 (match_dup 2)))
1791 (set (match_dup 3)
1792 (compare:CC (match_dup 0)
1793 (const_int 0)))]
1794 "")
deb9225a 1795
0354e5d8
GK		 1796(define_expand "sub<mode>3"
1797 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1798 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
4ae234b0 1799 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1fd4e8c1 1800 ""
a0044fb1
RK		 1801 "
1802{
1803 if (GET_CODE (operands[2]) == CONST_INT)
1804 {
0354e5d8
GK		 1805 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1806 negate_rtx (<MODE>mode, operands[2])));
a0044fb1
RK		 1807 DONE;
1808 }
1809}")
1fd4e8c1
RK		 1810
1811;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1812;; instruction and some auxiliary computations. Then we just have a single
95ac8e67
RK		 1813;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1814;; combine.
1fd4e8c1
RK		 1815
1816(define_expand "sminsi3"
1817 [(set (match_dup 3)
cd2b37d9 1818 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1819 (match_operand:SI 2 "reg_or_short_operand" ""))
1820 (const_int 0)
1821 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1822 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1823 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1824 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1825 "
a3170dc6
AH		 1826{
1827 if (TARGET_ISEL)
1828 {
1829 operands[2] = force_reg (SImode, operands[2]);
1830 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1831 DONE;
1832 }
1833
1834 operands[3] = gen_reg_rtx (SImode);
1835}")
1fd4e8c1 1836
95ac8e67
RK		 1837(define_split
1838 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1839 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1840 (match_operand:SI 2 "reg_or_short_operand" "")))
1841 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1842 "TARGET_POWER"
95ac8e67
RK		 1843 [(set (match_dup 3)
1844 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1845 (const_int 0)
1846 (minus:SI (match_dup 2) (match_dup 1))))
1847 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1848 "")
1849
1fd4e8c1
RK		 1850(define_expand "smaxsi3"
1851 [(set (match_dup 3)
cd2b37d9 1852 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1853 (match_operand:SI 2 "reg_or_short_operand" ""))
1854 (const_int 0)
1855 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1856 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1857 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1858 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1859 "
a3170dc6
AH		 1860{
1861 if (TARGET_ISEL)
1862 {
1863 operands[2] = force_reg (SImode, operands[2]);
1864 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1865 DONE;
1866 }
1867 operands[3] = gen_reg_rtx (SImode);
1868}")
1fd4e8c1 1869
95ac8e67
RK		 1870(define_split
1871 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1872 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1873 (match_operand:SI 2 "reg_or_short_operand" "")))
1874 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1875 "TARGET_POWER"
95ac8e67
RK		 1876 [(set (match_dup 3)
1877 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1878 (const_int 0)
1879 (minus:SI (match_dup 2) (match_dup 1))))
1880 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1881 "")
1882
1fd4e8c1 1883(define_expand "uminsi3"
cd2b37d9 1884 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1885 (match_dup 5)))
cd2b37d9 1886 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1887 (match_dup 5)))
1fd4e8c1
RK		 1888 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1889 (const_int 0)
1890 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1891 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1892 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1893 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1894 "
bb68ff55 1895{
a3170dc6
AH		 1896 if (TARGET_ISEL)
1897 {
1898 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1899 DONE;
1900 }
bb68ff55
MM		 1901 operands[3] = gen_reg_rtx (SImode);
1902 operands[4] = gen_reg_rtx (SImode);
1903 operands[5] = GEN_INT (-2147483647 - 1);
1904}")
1fd4e8c1
RK		 1905
1906(define_expand "umaxsi3"
cd2b37d9 1907 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1908 (match_dup 5)))
cd2b37d9 1909 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1910 (match_dup 5)))
1fd4e8c1
RK		 1911 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1912 (const_int 0)
1913 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1914 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1915 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1916 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1917 "
bb68ff55 1918{
a3170dc6
AH		 1919 if (TARGET_ISEL)
1920 {
1921 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1922 DONE;
1923 }
bb68ff55
MM		 1924 operands[3] = gen_reg_rtx (SImode);
1925 operands[4] = gen_reg_rtx (SImode);
1926 operands[5] = GEN_INT (-2147483647 - 1);
1927}")
1fd4e8c1
RK		 1928
1929(define_insn ""
cd2b37d9
RK		 1930 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1931 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
5c23c401 1932 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 1933 (const_int 0)
1934 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1935 "TARGET_POWER"
1fd4e8c1
RK		 1936 "doz%I2 %0,%1,%2")
1937
1938(define_insn ""
9ebbca7d 1939 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 1940 (compare:CC
9ebbca7d
GK		 1941 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1942 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1943 (const_int 0)
1944 (minus:SI (match_dup 2) (match_dup 1)))
1945 (const_int 0)))
9ebbca7d 1946 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 1947 "TARGET_POWER"
9ebbca7d
GK		 1948 "@
1949 doz%I2. %3,%1,%2
1950 #"
1951 [(set_attr "type" "delayed_compare")
1952 (set_attr "length" "4,8")])
1953
1954(define_split
1955 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1956 (compare:CC
1957 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1958 (match_operand:SI 2 "reg_or_short_operand" ""))
1959 (const_int 0)
1960 (minus:SI (match_dup 2) (match_dup 1)))
1961 (const_int 0)))
1962 (clobber (match_scratch:SI 3 ""))]
1963 "TARGET_POWER && reload_completed"
1964 [(set (match_dup 3)
1965 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1966 (const_int 0)
1967 (minus:SI (match_dup 2) (match_dup 1))))
1968 (set (match_dup 0)
1969 (compare:CC (match_dup 3)
1970 (const_int 0)))]
1971 "")
1fd4e8c1
RK		 1972
1973(define_insn ""
9ebbca7d 1974 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 1975 (compare:CC
9ebbca7d
GK		 1976 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1977 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1978 (const_int 0)
1979 (minus:SI (match_dup 2) (match_dup 1)))
1980 (const_int 0)))
9ebbca7d 1981 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 1982 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1983 (const_int 0)
1984 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1985 "TARGET_POWER"
9ebbca7d
GK		 1986 "@
1987 doz%I2. %0,%1,%2
1988 #"
1989 [(set_attr "type" "delayed_compare")
1990 (set_attr "length" "4,8")])
1991
1992(define_split
1993 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1994 (compare:CC
1995 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1996 (match_operand:SI 2 "reg_or_short_operand" ""))
1997 (const_int 0)
1998 (minus:SI (match_dup 2) (match_dup 1)))
1999 (const_int 0)))
2000 (set (match_operand:SI 0 "gpc_reg_operand" "")
2001 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2002 (const_int 0)
2003 (minus:SI (match_dup 2) (match_dup 1))))]
2004 "TARGET_POWER && reload_completed"
2005 [(set (match_dup 0)
2006 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2007 (const_int 0)
2008 (minus:SI (match_dup 2) (match_dup 1))))
2009 (set (match_dup 3)
2010 (compare:CC (match_dup 0)
2011 (const_int 0)))]
2012 "")
1fd4e8c1
RK		 2013
2014;; We don't need abs with condition code because such comparisons should
2015;; never be done.
ea9be077
MM		 2016(define_expand "abssi2"
2017 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2018 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2019 ""
2020 "
2021{
a3170dc6
AH		 2022 if (TARGET_ISEL)
2023 {
2024 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2025 DONE;
2026 }
2027 else if (! TARGET_POWER)
ea9be077
MM		 2028 {
2029 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2030 DONE;
2031 }
2032}")
2033
ea112fc4 2034(define_insn "*abssi2_power"
cd2b37d9
RK		 2035 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2036 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
ca7f5001 2037 "TARGET_POWER"
1fd4e8c1
RK		 2038 "abs %0,%1")
2039
a3170dc6
AH		 2040(define_insn_and_split "abssi2_isel"
2041 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2042 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8c48b6f5 2043 (clobber (match_scratch:SI 2 "=&b"))
a3170dc6
AH		 2044 (clobber (match_scratch:CC 3 "=y"))]
2045 "TARGET_ISEL"
2046 "#"
2047 "&& reload_completed"
2048 [(set (match_dup 2) (neg:SI (match_dup 1)))
2049 (set (match_dup 3)
2050 (compare:CC (match_dup 1)
2051 (const_int 0)))
2052 (set (match_dup 0)
2053 (if_then_else:SI (ge (match_dup 3)
2054 (const_int 0))
2055 (match_dup 1)
2056 (match_dup 2)))]
2057 "")
2058
ea112fc4 2059(define_insn_and_split "abssi2_nopower"
ea9be077 2060 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2061 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
ea9be077 2062 (clobber (match_scratch:SI 2 "=&r,&r"))]
a3170dc6 2063 "! TARGET_POWER && ! TARGET_ISEL"
ea112fc4
DE		 2064 "#"
2065 "&& reload_completed"
ea9be077
MM		 2066 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2067 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2068 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
ea9be077
MM		 2069 "")
2070
463b558b 2071(define_insn "*nabs_power"
cd2b37d9
RK		 2072 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2073 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
ca7f5001 2074 "TARGET_POWER"
1fd4e8c1
RK		 2075 "nabs %0,%1")
2076
ea112fc4 2077(define_insn_and_split "*nabs_nopower"
ea9be077 2078 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2079 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
ea9be077 2080 (clobber (match_scratch:SI 2 "=&r,&r"))]
0ad91047 2081 "! TARGET_POWER"
ea112fc4
DE		 2082 "#"
2083 "&& reload_completed"
ea9be077
MM		 2084 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2085 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2086 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
ea9be077
MM		 2087 "")
2088
0354e5d8
GK		 2089(define_expand "neg<mode>2"
2090 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2091 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2092 ""
2093 "")
2094
2095(define_insn "*neg<mode>2_internal"
2096 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2097 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1
RK		 2098 ""
2099 "neg %0,%1")
2100
2101(define_insn ""
9ebbca7d 2102 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 2103 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 2104 (const_int 0)))
0354e5d8
GK		 2105 (clobber (match_scratch:P 2 "=r,r"))]
2106 ""
9ebbca7d
GK		 2107 "@
2108 neg. %2,%1
2109 #"
a62bfff2 2110 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2111 (set_attr "length" "4,8")])
2112
2113(define_split
2114 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 2115 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2116 (const_int 0)))
0354e5d8
GK		 2117 (clobber (match_scratch:P 2 ""))]
2118 "reload_completed"
9ebbca7d 2119 [(set (match_dup 2)
0354e5d8 2120 (neg:P (match_dup 1)))
9ebbca7d
GK		 2121 (set (match_dup 0)
2122 (compare:CC (match_dup 2)
2123 (const_int 0)))]
2124 "")
1fd4e8c1
RK		 2125
2126(define_insn ""
9ebbca7d 2127 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 2128 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 2129 (const_int 0)))
0354e5d8
GK		 2130 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2131 (neg:P (match_dup 1)))]
2132 ""
9ebbca7d
GK		 2133 "@
2134 neg. %0,%1
2135 #"
a62bfff2 2136 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2137 (set_attr "length" "4,8")])
2138
2139(define_split
2140 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 2141 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2142 (const_int 0)))
0354e5d8
GK		 2143 (set (match_operand:P 0 "gpc_reg_operand" "")
2144 (neg:P (match_dup 1)))]
66859ace 2145 "reload_completed"
9ebbca7d 2146 [(set (match_dup 0)
0354e5d8 2147 (neg:P (match_dup 1)))
9ebbca7d
GK		 2148 (set (match_dup 2)
2149 (compare:CC (match_dup 0)
2150 (const_int 0)))]
2151 "")
1fd4e8c1 2152
0354e5d8
GK		 2153(define_insn "clz<mode>2"
2154 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2155 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1b1edcfa 2156 ""
44cd321e
PS		 2157 "{cntlz|cntlz<wd>} %0,%1"
2158 [(set_attr "type" "cntlz")])
1b1edcfa 2159
0354e5d8 2160(define_expand "ctz<mode>2"
4977bab6 2161 [(set (match_dup 2)
e42ac3de 2162 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2163 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2164 (match_dup 2)))
1b1edcfa 2165 (clobber (scratch:CC))])
0354e5d8 2166 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2167 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2168 (minus:GPR (match_dup 5) (match_dup 4)))]
1fd4e8c1 2169 ""
4977bab6 2170 {
0354e5d8
GK		 2171 operands[2] = gen_reg_rtx (<MODE>mode);
2172 operands[3] = gen_reg_rtx (<MODE>mode);
2173 operands[4] = gen_reg_rtx (<MODE>mode);
2174 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
4977bab6 2175 })
6ae08853 2176
0354e5d8 2177(define_expand "ffs<mode>2"
1b1edcfa 2178 [(set (match_dup 2)
e42ac3de 2179 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2180 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2181 (match_dup 2)))
1b1edcfa 2182 (clobber (scratch:CC))])
0354e5d8 2183 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2184 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2185 (minus:GPR (match_dup 5) (match_dup 4)))]
4977bab6 2186 ""
1b1edcfa 2187 {
0354e5d8
GK		 2188 operands[2] = gen_reg_rtx (<MODE>mode);
2189 operands[3] = gen_reg_rtx (<MODE>mode);
2190 operands[4] = gen_reg_rtx (<MODE>mode);
2191 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1b1edcfa 2192 })
6ae08853 2193
432218ba
DE		 2194(define_insn "popcntb<mode>2"
2195 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2196 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2197 UNSPEC_POPCNTB))]
2198 "TARGET_POPCNTB"
2199 "popcntb %0,%1")
2200
565ef4ba 2201(define_expand "popcount<mode>2"
e42ac3de
RS		 2202 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2203 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
565ef4ba
RS		 2204 "TARGET_POPCNTB"
2205 {
2206 rs6000_emit_popcount (operands[0], operands[1]);
2207 DONE;
2208 })
2209
2210(define_expand "parity<mode>2"
e42ac3de
RS		 2211 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2212 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
565ef4ba
RS		 2213 "TARGET_POPCNTB"
2214 {
2215 rs6000_emit_parity (operands[0], operands[1]);
2216 DONE;
2217 })
2218
03f79051
DE		 2219(define_insn "bswapsi2"
2220 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2221 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2222 ""
2223 "@
2224 {lbrx|lwbrx} %0,%y1
2225 {stbrx|stwbrx} %1,%y0
2226 #"
2227 [(set_attr "length" "4,4,12")])
2228
2229(define_split
2230 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2231 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2232 "reload_completed"
2233 [(set (match_dup 0)
2234 (rotate:SI (match_dup 1) (const_int 8)))
2235 (set (zero_extract:SI (match_dup 0)
2236 (const_int 8)
2237 (const_int 0))
2238 (match_dup 1))
2239 (set (zero_extract:SI (match_dup 0)
2240 (const_int 8)
2241 (const_int 16))
2242 (rotate:SI (match_dup 1)
2243 (const_int 16)))]
2244 "")
2245
ca7f5001
RK		 2246(define_expand "mulsi3"
2247 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2248 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2249 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2250 ""
2251 "
2252{
2253 if (TARGET_POWER)
68b40e7e 2254 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
ca7f5001 2255 else
68b40e7e 2256 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
ca7f5001
RK		 2257 DONE;
2258}")
2259
68b40e7e 2260(define_insn "mulsi3_mq"
cd2b37d9
RK		 2261 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2262 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1fd4e8c1
RK		 2263 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2264 (clobber (match_scratch:SI 3 "=q,q"))]
ca7f5001
RK		 2265 "TARGET_POWER"
2266 "@
2267 {muls|mullw} %0,%1,%2
2268 {muli|mulli} %0,%1,%2"
6ae08853 2269 [(set (attr "type")
c859cda6
DJ		 2270 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2271 (const_string "imul3")
6ae08853 2272 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2273 (const_string "imul2")]
2274 (const_string "imul")))])
ca7f5001 2275
68b40e7e 2276(define_insn "mulsi3_no_mq"
ca7f5001
RK		 2277 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2278 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2279 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
68b40e7e 2280 "! TARGET_POWER"
1fd4e8c1 2281 "@
d904e9ed
RK		 2282 {muls|mullw} %0,%1,%2
2283 {muli|mulli} %0,%1,%2"
6ae08853 2284 [(set (attr "type")
c859cda6
DJ		 2285 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2286 (const_string "imul3")
6ae08853 2287 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2288 (const_string "imul2")]
2289 (const_string "imul")))])
1fd4e8c1 2290
9259f3b0 2291(define_insn "*mulsi3_mq_internal1"
9ebbca7d
GK		 2292 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2293 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2294 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2295 (const_int 0)))
9ebbca7d
GK		 2296 (clobber (match_scratch:SI 3 "=r,r"))
2297 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2298 "TARGET_POWER"
9ebbca7d
GK		 2299 "@
2300 {muls.|mullw.} %3,%1,%2
2301 #"
9259f3b0 2302 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2303 (set_attr "length" "4,8")])
2304
2305(define_split
2306 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2307 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2308 (match_operand:SI 2 "gpc_reg_operand" ""))
2309 (const_int 0)))
2310 (clobber (match_scratch:SI 3 ""))
2311 (clobber (match_scratch:SI 4 ""))]
2312 "TARGET_POWER && reload_completed"
2313 [(parallel [(set (match_dup 3)
2314 (mult:SI (match_dup 1) (match_dup 2)))
2315 (clobber (match_dup 4))])
2316 (set (match_dup 0)
2317 (compare:CC (match_dup 3)
2318 (const_int 0)))]
2319 "")
ca7f5001 2320
9259f3b0 2321(define_insn "*mulsi3_no_mq_internal1"
9ebbca7d
GK		 2322 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2323 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2324 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2325 (const_int 0)))
9ebbca7d 2326 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 2327 "! TARGET_POWER"
9ebbca7d
GK		 2328 "@
2329 {muls.|mullw.} %3,%1,%2
2330 #"
9259f3b0 2331 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2332 (set_attr "length" "4,8")])
2333
2334(define_split
2335 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2336 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2337 (match_operand:SI 2 "gpc_reg_operand" ""))
2338 (const_int 0)))
2339 (clobber (match_scratch:SI 3 ""))]
2340 "! TARGET_POWER && reload_completed"
2341 [(set (match_dup 3)
2342 (mult:SI (match_dup 1) (match_dup 2)))
2343 (set (match_dup 0)
2344 (compare:CC (match_dup 3)
2345 (const_int 0)))]
2346 "")
1fd4e8c1 2347
9259f3b0 2348(define_insn "*mulsi3_mq_internal2"
9ebbca7d
GK		 2349 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2350 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2351 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2352 (const_int 0)))
9ebbca7d 2353 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
29ae5b89 2354 (mult:SI (match_dup 1) (match_dup 2)))
9ebbca7d 2355 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2356 "TARGET_POWER"
9ebbca7d
GK		 2357 "@
2358 {muls.|mullw.} %0,%1,%2
2359 #"
9259f3b0 2360 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2361 (set_attr "length" "4,8")])
2362
2363(define_split
2364 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2365 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2366 (match_operand:SI 2 "gpc_reg_operand" ""))
2367 (const_int 0)))
2368 (set (match_operand:SI 0 "gpc_reg_operand" "")
2369 (mult:SI (match_dup 1) (match_dup 2)))
2370 (clobber (match_scratch:SI 4 ""))]
2371 "TARGET_POWER && reload_completed"
2372 [(parallel [(set (match_dup 0)
2373 (mult:SI (match_dup 1) (match_dup 2)))
2374 (clobber (match_dup 4))])
2375 (set (match_dup 3)
2376 (compare:CC (match_dup 0)
2377 (const_int 0)))]
2378 "")
ca7f5001 2379
9259f3b0 2380(define_insn "*mulsi3_no_mq_internal2"
9ebbca7d
GK		 2381 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2382 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2383 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2384 (const_int 0)))
9ebbca7d 2385 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 2386 (mult:SI (match_dup 1) (match_dup 2)))]
25c341fa 2387 "! TARGET_POWER"
9ebbca7d
GK		 2388 "@
2389 {muls.|mullw.} %0,%1,%2
2390 #"
9259f3b0 2391 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2392 (set_attr "length" "4,8")])
2393
2394(define_split
2395 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2396 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2397 (match_operand:SI 2 "gpc_reg_operand" ""))
2398 (const_int 0)))
2399 (set (match_operand:SI 0 "gpc_reg_operand" "")
2400 (mult:SI (match_dup 1) (match_dup 2)))]
2401 "! TARGET_POWER && reload_completed"
2402 [(set (match_dup 0)
2403 (mult:SI (match_dup 1) (match_dup 2)))
2404 (set (match_dup 3)
2405 (compare:CC (match_dup 0)
2406 (const_int 0)))]
2407 "")
1fd4e8c1
RK		 2408
2409;; Operand 1 is divided by operand 2; quotient goes to operand
2410;; 0 and remainder to operand 3.
2411;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2412
8ffd9c51
RK		 2413(define_expand "divmodsi4"
2414 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2415 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2416 (match_operand:SI 2 "gpc_reg_operand" "")))
bb157ff4 2417 (set (match_operand:SI 3 "register_operand" "")
8ffd9c51
RK		 2418 (mod:SI (match_dup 1) (match_dup 2)))])]
2419 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2420 "
2421{
2422 if (! TARGET_POWER && ! TARGET_POWERPC)
2423 {
39403d82
DE		 2424 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2425 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2426 emit_insn (gen_divss_call ());
39403d82
DE		 2427 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2428 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
8ffd9c51
RK		 2429 DONE;
2430 }
2431}")
deb9225a 2432
bb157ff4 2433(define_insn "*divmodsi4_internal"
cd2b37d9
RK		 2434 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2435 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2436 (match_operand:SI 2 "gpc_reg_operand" "r")))
bb157ff4 2437 (set (match_operand:SI 3 "register_operand" "=q")
1fd4e8c1 2438 (mod:SI (match_dup 1) (match_dup 2)))]
ca7f5001 2439 "TARGET_POWER"
cfb557c4
RK		 2440 "divs %0,%1,%2"
2441 [(set_attr "type" "idiv")])
1fd4e8c1 2442
4ae234b0
GK		 2443(define_expand "udiv<mode>3"
2444 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2445 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2446 (match_operand:GPR 2 "gpc_reg_operand" "")))]
8ffd9c51
RK		 2447 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2448 "
2449{
2450 if (! TARGET_POWER && ! TARGET_POWERPC)
2451 {
39403d82
DE		 2452 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2453 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2454 emit_insn (gen_quous_call ());
39403d82 2455 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2456 DONE;
2457 }
f192bf8b
DE		 2458 else if (TARGET_POWER)
2459 {
2460 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2461 DONE;
2462 }
8ffd9c51 2463}")
deb9225a 2464
f192bf8b
DE		 2465(define_insn "udivsi3_mq"
2466 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2467 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2468 (match_operand:SI 2 "gpc_reg_operand" "r")))
2469 (clobber (match_scratch:SI 3 "=q"))]
2470 "TARGET_POWERPC && TARGET_POWER"
2471 "divwu %0,%1,%2"
2472 [(set_attr "type" "idiv")])
2473
2474(define_insn "*udivsi3_no_mq"
4ae234b0
GK		 2475 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2476 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2477 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2478 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2479 "div<wd>u %0,%1,%2"
44cd321e
PS		 2480 [(set (attr "type")
2481 (cond [(match_operand:SI 0 "" "")
2482 (const_string "idiv")]
2483 (const_string "ldiv")))])
2484
ca7f5001 2485
1fd4e8c1 2486;; For powers of two we can do srai/aze for divide and then adjust for
ca7f5001 2487;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
8ffd9c51
RK		 2488;; used; for PowerPC, force operands into register and do a normal divide;
2489;; for AIX common-mode, use quoss call on register operands.
4ae234b0
GK		 2490(define_expand "div<mode>3"
2491 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2492 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2493 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
1fd4e8c1
RK		 2494 ""
2495 "
2496{
ca7f5001 2497 if (GET_CODE (operands[2]) == CONST_INT
2bfcf297 2498 && INTVAL (operands[2]) > 0
ca7f5001
RK		 2499 && exact_log2 (INTVAL (operands[2])) >= 0)
2500 ;
b6c9286a 2501 else if (TARGET_POWERPC)
f192bf8b 2502 {
99e8e649 2503 operands[2] = force_reg (<MODE>mode, operands[2]);
f192bf8b
DE		 2504 if (TARGET_POWER)
2505 {
2506 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2507 DONE;
2508 }
2509 }
b6c9286a 2510 else if (TARGET_POWER)
1fd4e8c1 2511 FAIL;
405c5495 2512 else
8ffd9c51 2513 {
39403d82
DE		 2514 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2515 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2516 emit_insn (gen_quoss_call ());
39403d82 2517 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2518 DONE;
2519 }
1fd4e8c1
RK		 2520}")
2521
f192bf8b
DE		 2522(define_insn "divsi3_mq"
2523 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2524 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2525 (match_operand:SI 2 "gpc_reg_operand" "r")))
2526 (clobber (match_scratch:SI 3 "=q"))]
2527 "TARGET_POWERPC && TARGET_POWER"
2528 "divw %0,%1,%2"
2529 [(set_attr "type" "idiv")])
2530
4ae234b0
GK		 2531(define_insn "*div<mode>3_no_mq"
2532 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2533 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2534 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2535 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2536 "div<wd> %0,%1,%2"
44cd321e
PS		 2537 [(set (attr "type")
2538 (cond [(match_operand:SI 0 "" "")
2539 (const_string "idiv")]
2540 (const_string "ldiv")))])
f192bf8b 2541
4ae234b0
GK		 2542(define_expand "mod<mode>3"
2543 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2544 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2545 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
39b52ba2 2546 ""
1fd4e8c1
RK		 2547 "
2548{
481c7efa 2549 int i;
39b52ba2
RK		 2550 rtx temp1;
2551 rtx temp2;
2552
2bfcf297 2553 if (GET_CODE (operands[2]) != CONST_INT
a65c591c 2554 || INTVAL (operands[2]) <= 0
2bfcf297 2555 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
39b52ba2
RK		 2556 FAIL;
2557
4ae234b0
GK		 2558 temp1 = gen_reg_rtx (<MODE>mode);
2559 temp2 = gen_reg_rtx (<MODE>mode);
1fd4e8c1 2560
4ae234b0
GK		 2561 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2562 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2563 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
85644414 2564 DONE;
1fd4e8c1
RK		 2565}")
2566
2567(define_insn ""
4ae234b0
GK		 2568 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2569 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2570 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2bfcf297 2571 ""
4ae234b0 2572 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
943c15ed
DE		 2573 [(set_attr "type" "two")
2574 (set_attr "length" "8")])
1fd4e8c1
RK		 2575
2576(define_insn ""
9ebbca7d 2577 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2578 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2579 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2580 (const_int 0)))
4ae234b0 2581 (clobber (match_scratch:P 3 "=r,r"))]
2bfcf297 2582 ""
9ebbca7d 2583 "@
4ae234b0 2584 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
9ebbca7d 2585 #"
b19003d8 2586 [(set_attr "type" "compare")
9ebbca7d
GK		 2587 (set_attr "length" "8,12")])
2588
2589(define_split
2590 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2591 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2592 (match_operand:GPR 2 "exact_log2_cint_operand"
2593 ""))
9ebbca7d 2594 (const_int 0)))
4ae234b0 2595 (clobber (match_scratch:GPR 3 ""))]
2bfcf297 2596 "reload_completed"
9ebbca7d 2597 [(set (match_dup 3)
4ae234b0 2598 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2599 (set (match_dup 0)
2600 (compare:CC (match_dup 3)
2601 (const_int 0)))]
2602 "")
1fd4e8c1
RK		 2603
2604(define_insn ""
9ebbca7d 2605 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2606 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2607 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2608 (const_int 0)))
4ae234b0
GK		 2609 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2610 (div:P (match_dup 1) (match_dup 2)))]
2bfcf297 2611 ""
9ebbca7d 2612 "@
4ae234b0 2613 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
9ebbca7d 2614 #"
b19003d8 2615 [(set_attr "type" "compare")
9ebbca7d
GK		 2616 (set_attr "length" "8,12")])
2617
2618(define_split
2619 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2620 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2621 (match_operand:GPR 2 "exact_log2_cint_operand"
2622 ""))
9ebbca7d 2623 (const_int 0)))
4ae234b0
GK		 2624 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2625 (div:GPR (match_dup 1) (match_dup 2)))]
2bfcf297 2626 "reload_completed"
9ebbca7d 2627 [(set (match_dup 0)
4ae234b0 2628 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2629 (set (match_dup 3)
2630 (compare:CC (match_dup 0)
2631 (const_int 0)))]
2632 "")
1fd4e8c1
RK		 2633
2634(define_insn ""
cd2b37d9 2635 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 2636 (udiv:SI
996a5f59 2637 (plus:DI (ashift:DI
cd2b37d9 2638 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 2639 (const_int 32))
23a900dc 2640 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
cd2b37d9 2641 (match_operand:SI 3 "gpc_reg_operand" "r")))
740ab4a2 2642 (set (match_operand:SI 2 "register_operand" "=*q")
1fd4e8c1 2643 (umod:SI
996a5f59 2644 (plus:DI (ashift:DI
1fd4e8c1 2645 (zero_extend:DI (match_dup 1)) (const_int 32))
740ab4a2 2646 (zero_extend:DI (match_dup 4)))
1fd4e8c1 2647 (match_dup 3)))]
ca7f5001 2648 "TARGET_POWER"
cfb557c4
RK		 2649 "div %0,%1,%3"
2650 [(set_attr "type" "idiv")])
1fd4e8c1
RK		 2651
2652;; To do unsigned divide we handle the cases of the divisor looking like a
2653;; negative number. If it is a constant that is less than 2**31, we don't
2654;; have to worry about the branches. So make a few subroutines here.
2655;;
2656;; First comes the normal case.
2657(define_expand "udivmodsi4_normal"
2658 [(set (match_dup 4) (const_int 0))
2659 (parallel [(set (match_operand:SI 0 "" "")
996a5f59 2660 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2661 (const_int 32))
2662 (zero_extend:DI (match_operand:SI 1 "" "")))
2663 (match_operand:SI 2 "" "")))
2664 (set (match_operand:SI 3 "" "")
996a5f59 2665 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2666 (const_int 32))
2667 (zero_extend:DI (match_dup 1)))
2668 (match_dup 2)))])]
ca7f5001 2669 "TARGET_POWER"
1fd4e8c1
RK		 2670 "
2671{ operands[4] = gen_reg_rtx (SImode); }")
2672
2673;; This handles the branches.
2674(define_expand "udivmodsi4_tests"
2675 [(set (match_operand:SI 0 "" "") (const_int 0))
2676 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2677 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2678 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2679 (label_ref (match_operand:SI 4 "" "")) (pc)))
2680 (set (match_dup 0) (const_int 1))
2681 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2682 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2683 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2684 (label_ref (match_dup 4)) (pc)))]
ca7f5001 2685 "TARGET_POWER"
1fd4e8c1
RK		 2686 "
2687{ operands[5] = gen_reg_rtx (CCUNSmode);
2688 operands[6] = gen_reg_rtx (CCmode);
2689}")
2690
2691(define_expand "udivmodsi4"
cd2b37d9
RK		 2692 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2693 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 2694 (match_operand:SI 2 "reg_or_cint_operand" "")))
cd2b37d9 2695 (set (match_operand:SI 3 "gpc_reg_operand" "")
1fd4e8c1 2696 (umod:SI (match_dup 1) (match_dup 2)))])]
8ffd9c51 2697 ""
1fd4e8c1
RK		 2698 "
2699{
2700 rtx label = 0;
2701
8ffd9c51 2702 if (! TARGET_POWER)
c4d38ccb
MM		 2703 {
2704 if (! TARGET_POWERPC)
2705 {
39403d82
DE		 2706 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2707 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
c4d38ccb 2708 emit_insn (gen_divus_call ());
39403d82
DE		 2709 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2710 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
c4d38ccb
MM		 2711 DONE;
2712 }
2713 else
2714 FAIL;
2715 }
0081a354 2716
1fd4e8c1
RK		 2717 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2718 {
2719 operands[2] = force_reg (SImode, operands[2]);
2720 label = gen_label_rtx ();
2721 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2722 operands[3], label));
2723 }
2724 else
2725 operands[2] = force_reg (SImode, operands[2]);
2726
2727 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2728 operands[3]));
2729 if (label)
2730 emit_label (label);
2731
2732 DONE;
2733}")
0081a354 2734
fada905b
MM		 2735;; AIX architecture-independent common-mode multiply (DImode),
2736;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2737;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2738;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2739;; assumed unused if generating common-mode, so ignore.
2740(define_insn "mulh_call"
2741 [(set (reg:SI 3)
2742 (truncate:SI
2743 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2744 (sign_extend:DI (reg:SI 4)))
2745 (const_int 32))))
1de43f85 2746 (clobber (reg:SI LR_REGNO))]
fada905b 2747 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2748 "bla __mulh"
2749 [(set_attr "type" "imul")])
fada905b
MM		 2750
2751(define_insn "mull_call"
2752 [(set (reg:DI 3)
2753 (mult:DI (sign_extend:DI (reg:SI 3))
2754 (sign_extend:DI (reg:SI 4))))
1de43f85 2755 (clobber (reg:SI LR_REGNO))
fada905b
MM		 2756 (clobber (reg:SI 0))]
2757 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2758 "bla __mull"
2759 [(set_attr "type" "imul")])
fada905b
MM		 2760
2761(define_insn "divss_call"
2762 [(set (reg:SI 3)
2763 (div:SI (reg:SI 3) (reg:SI 4)))
2764 (set (reg:SI 4)
2765 (mod:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2766 (clobber (reg:SI LR_REGNO))
fada905b
MM		 2767 (clobber (reg:SI 0))]
2768 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2769 "bla __divss"
2770 [(set_attr "type" "idiv")])
fada905b
MM		 2771
2772(define_insn "divus_call"
8ffd9c51
RK		 2773 [(set (reg:SI 3)
2774 (udiv:SI (reg:SI 3) (reg:SI 4)))
2775 (set (reg:SI 4)
2776 (umod:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2777 (clobber (reg:SI LR_REGNO))
fada905b 2778 (clobber (reg:SI 0))
e65a3857 2779 (clobber (match_scratch:CC 0 "=x"))
1de43f85 2780 (clobber (reg:CC CR1_REGNO))]
fada905b 2781 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2782 "bla __divus"
2783 [(set_attr "type" "idiv")])
fada905b
MM		 2784
2785(define_insn "quoss_call"
2786 [(set (reg:SI 3)
2787 (div:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2788 (clobber (reg:SI LR_REGNO))]
8ffd9c51 2789 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2790 "bla __quoss"
2791 [(set_attr "type" "idiv")])
0081a354 2792
fada905b
MM		 2793(define_insn "quous_call"
2794 [(set (reg:SI 3)
2795 (udiv:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2796 (clobber (reg:SI LR_REGNO))
fada905b 2797 (clobber (reg:SI 0))
e65a3857 2798 (clobber (match_scratch:CC 0 "=x"))
1de43f85 2799 (clobber (reg:CC CR1_REGNO))]
fada905b 2800 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2801 "bla __quous"
2802 [(set_attr "type" "idiv")])
8ffd9c51 2803\f
bb21487f 2804;; Logical instructions
dfbdccdb
GK		 2805;; The logical instructions are mostly combined by using match_operator,
2806;; but the plain AND insns are somewhat different because there is no
2807;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2808;; those rotate-and-mask operations. Thus, the AND insns come first.
2809
29ae5b89
JL		 2810(define_insn "andsi3"
2811 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2812 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
5f59ecb7 2813 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
29ae5b89 2814 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1fd4e8c1
RK		 2815 ""
2816 "@
2817 and %0,%1,%2
ca7f5001
RK		 2818 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2819 {andil.|andi.} %0,%1,%b2
520308bc
DE		 2820 {andiu.|andis.} %0,%1,%u2"
2821 [(set_attr "type" "*,*,compare,compare")])
52d3af72
DE		 2822
2823;; Note to set cr's other than cr0 we do the and immediate and then
0ba1b2ff 2824;; the test again -- this avoids a mfcr which on the higher end
52d3af72 2825;; machines causes an execution serialization
1fd4e8c1 2826
7cd5235b 2827(define_insn "*andsi3_internal2"
52d3af72
DE		 2828 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2829 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2830 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
1fd4e8c1 2831 (const_int 0)))
52d3af72
DE		 2832 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2833 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2834 "TARGET_32BIT"
1fd4e8c1
RK		 2835 "@
2836 and. %3,%1,%2
ca7f5001
RK		 2837 {andil.|andi.} %3,%1,%b2
2838 {andiu.|andis.} %3,%1,%u2
52d3af72
DE		 2839 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2840 #
2841 #
2842 #
2843 #"
2844 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2845 (set_attr "length" "4,4,4,4,8,8,8,8")])
1fd4e8c1 2846
0ba1b2ff
AM		 2847(define_insn "*andsi3_internal3"
2848 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2849 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2850 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2851 (const_int 0)))
2852 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2853 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2854 "TARGET_64BIT"
0ba1b2ff
AM		 2855 "@
2856 #
2857 {andil.|andi.} %3,%1,%b2
2858 {andiu.|andis.} %3,%1,%u2
2859 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2860 #
2861 #
2862 #
2863 #"
2864 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2865 (set_attr "length" "8,4,4,4,8,8,8,8")])
2866
52d3af72
DE		 2867(define_split
2868 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2869 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2870 (match_operand:GPR 2 "and_operand" ""))
1fd4e8c1 2871 (const_int 0)))
4ae234b0 2872 (clobber (match_scratch:GPR 3 ""))
52d3af72 2873 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2874 "reload_completed"
52d3af72 2875 [(parallel [(set (match_dup 3)
4ae234b0
GK		 2876 (and:<MODE> (match_dup 1)
2877 (match_dup 2)))
52d3af72
DE		 2878 (clobber (match_dup 4))])
2879 (set (match_dup 0)
2880 (compare:CC (match_dup 3)
2881 (const_int 0)))]
2882 "")
2883
0ba1b2ff
AM		 2884;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2885;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2886
2887(define_split
2888 [(set (match_operand:CC 0 "cc_reg_operand" "")
2889 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2890 (match_operand:SI 2 "gpc_reg_operand" ""))
2891 (const_int 0)))
2892 (clobber (match_scratch:SI 3 ""))
2893 (clobber (match_scratch:CC 4 ""))]
2894 "TARGET_POWERPC64 && reload_completed"
2895 [(parallel [(set (match_dup 3)
2896 (and:SI (match_dup 1)
2897 (match_dup 2)))
2898 (clobber (match_dup 4))])
2899 (set (match_dup 0)
2900 (compare:CC (match_dup 3)
2901 (const_int 0)))]
2902 "")
2903
2904(define_insn "*andsi3_internal4"
52d3af72
DE		 2905 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2906 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2907 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
52d3af72
DE		 2908 (const_int 0)))
2909 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2910 (and:SI (match_dup 1)
2911 (match_dup 2)))
2912 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2913 "TARGET_32BIT"
1fd4e8c1
RK		 2914 "@
2915 and. %0,%1,%2
ca7f5001
RK		 2916 {andil.|andi.} %0,%1,%b2
2917 {andiu.|andis.} %0,%1,%u2
52d3af72
DE		 2918 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2919 #
2920 #
2921 #
2922 #"
2923 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2924 (set_attr "length" "4,4,4,4,8,8,8,8")])
2925
0ba1b2ff
AM		 2926(define_insn "*andsi3_internal5"
2927 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2928 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2929 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2930 (const_int 0)))
2931 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2932 (and:SI (match_dup 1)
2933 (match_dup 2)))
2934 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2935 "TARGET_64BIT"
0ba1b2ff
AM		 2936 "@
2937 #
2938 {andil.|andi.} %0,%1,%b2
2939 {andiu.|andis.} %0,%1,%u2
2940 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2941 #
2942 #
2943 #
2944 #"
2945 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2946 (set_attr "length" "8,4,4,4,8,8,8,8")])
2947
52d3af72
DE		 2948(define_split
2949 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2950 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2951 (match_operand:SI 2 "and_operand" ""))
2952 (const_int 0)))
2953 (set (match_operand:SI 0 "gpc_reg_operand" "")
2954 (and:SI (match_dup 1)
2955 (match_dup 2)))
2956 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2957 "reload_completed"
52d3af72
DE		 2958 [(parallel [(set (match_dup 0)
2959 (and:SI (match_dup 1)
2960 (match_dup 2)))
2961 (clobber (match_dup 4))])
2962 (set (match_dup 3)
2963 (compare:CC (match_dup 0)
2964 (const_int 0)))]
2965 "")
1fd4e8c1 2966
0ba1b2ff
AM		 2967(define_split
2968 [(set (match_operand:CC 3 "cc_reg_operand" "")
2969 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2970 (match_operand:SI 2 "gpc_reg_operand" ""))
2971 (const_int 0)))
2972 (set (match_operand:SI 0 "gpc_reg_operand" "")
2973 (and:SI (match_dup 1)
2974 (match_dup 2)))
2975 (clobber (match_scratch:CC 4 ""))]
2976 "TARGET_POWERPC64 && reload_completed"
2977 [(parallel [(set (match_dup 0)
2978 (and:SI (match_dup 1)
2979 (match_dup 2)))
2980 (clobber (match_dup 4))])
2981 (set (match_dup 3)
2982 (compare:CC (match_dup 0)
2983 (const_int 0)))]
2984 "")
2985
2986;; Handle the PowerPC64 rlwinm corner case
2987
2988(define_insn_and_split "*andsi3_internal6"
2989 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2990 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2991 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2992 "TARGET_POWERPC64"
2993 "#"
2994 "TARGET_POWERPC64"
2995 [(set (match_dup 0)
2996 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2997 (match_dup 4)))
2998 (set (match_dup 0)
2999 (rotate:SI (match_dup 0) (match_dup 5)))]
3000 "
3001{
3002 int mb = extract_MB (operands[2]);
3003 int me = extract_ME (operands[2]);
3004 operands[3] = GEN_INT (me + 1);
3005 operands[5] = GEN_INT (32 - (me + 1));
3006 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3007}"
3008 [(set_attr "length" "8")])
3009
7cd5235b 3010(define_expand "iorsi3"
cd2b37d9 3011 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 3012 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 3013 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
7cd5235b 3014 ""
f357808b
RK		 3015 "
3016{
7cd5235b 3017 if (GET_CODE (operands[2]) == CONST_INT
677a9668 3018 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 3019 {
3020 HOST_WIDE_INT value = INTVAL (operands[2]);
b3a13419
ILT		 3021 rtx tmp = ((!can_create_pseudo_p ()
3022 || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 3023 ? operands[0] : gen_reg_rtx (SImode));
3024
a260abc9
DE		 3025 emit_insn (gen_iorsi3 (tmp, operands[1],
3026 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3027 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 3028 DONE;
3029 }
f357808b
RK		 3030}")
3031
7cd5235b 3032(define_expand "xorsi3"
cd2b37d9 3033 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 3034 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 3035 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
1fd4e8c1 3036 ""
7cd5235b 3037 "
1fd4e8c1 3038{
7cd5235b 3039 if (GET_CODE (operands[2]) == CONST_INT
677a9668 3040 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 3041 {
3042 HOST_WIDE_INT value = INTVAL (operands[2]);
b3a13419
ILT		 3043 rtx tmp = ((!can_create_pseudo_p ()
3044 || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 3045 ? operands[0] : gen_reg_rtx (SImode));
3046
a260abc9
DE		 3047 emit_insn (gen_xorsi3 (tmp, operands[1],
3048 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3049 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 3050 DONE;
3051 }
1fd4e8c1
RK		 3052}")
3053
dfbdccdb 3054(define_insn "*boolsi3_internal1"
7cd5235b 3055 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 3056 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3057 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3058 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
1fd4e8c1
RK		 3059 ""
3060 "@
dfbdccdb
GK		 3061 %q3 %0,%1,%2
3062 {%q3il|%q3i} %0,%1,%b2
3063 {%q3iu|%q3is} %0,%1,%u2")
1fd4e8c1 3064
dfbdccdb 3065(define_insn "*boolsi3_internal2"
52d3af72 3066 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 3067 (compare:CC (match_operator:SI 4 "boolean_or_operator"
dfbdccdb
GK		 3068 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3069 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3070 (const_int 0)))
52d3af72 3071 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3072 "TARGET_32BIT"
52d3af72 3073 "@
dfbdccdb 3074 %q4. %3,%1,%2
52d3af72
DE		 3075 #"
3076 [(set_attr "type" "compare")
3077 (set_attr "length" "4,8")])
3078
3079(define_split
3080 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3081 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3082 [(match_operand:SI 1 "gpc_reg_operand" "")
3083 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3084 (const_int 0)))
52d3af72 3085 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3086 "TARGET_32BIT && reload_completed"
dfbdccdb 3087 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3088 (set (match_dup 0)
3089 (compare:CC (match_dup 3)
3090 (const_int 0)))]
3091 "")
815cdc52 3092
dfbdccdb 3093(define_insn "*boolsi3_internal3"
52d3af72 3094 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3095 (compare:CC (match_operator:SI 4 "boolean_operator"
3096 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3097 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3098 (const_int 0)))
52d3af72 3099 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3100 (match_dup 4))]
4b8a63d6 3101 "TARGET_32BIT"
52d3af72 3102 "@
dfbdccdb 3103 %q4. %0,%1,%2
52d3af72
DE		 3104 #"
3105 [(set_attr "type" "compare")
3106 (set_attr "length" "4,8")])
3107
3108(define_split
e72247f4 3109 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3110 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3111 [(match_operand:SI 1 "gpc_reg_operand" "")
3112 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3113 (const_int 0)))
75540af0 3114 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3115 (match_dup 4))]
4b8a63d6 3116 "TARGET_32BIT && reload_completed"
dfbdccdb 3117 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3118 (set (match_dup 3)
3119 (compare:CC (match_dup 0)
3120 (const_int 0)))]
3121 "")
1fd4e8c1 3122
6ae08853 3123;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 3124;; each of which does one 16-bit part. This is used by combine.
a260abc9
DE		 3125
3126(define_split
3127 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1d328b19 3128 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3129 [(match_operand:SI 1 "gpc_reg_operand" "")
3130 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
a260abc9 3131 ""
dfbdccdb
GK		 3132 [(set (match_dup 0) (match_dup 4))
3133 (set (match_dup 0) (match_dup 5))]
a260abc9
DE		 3134"
3135{
dfbdccdb
GK		 3136 rtx i;
3137 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
1c563bed 3138 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3139 operands[1], i);
dfbdccdb 3140 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
1c563bed 3141 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3142 operands[0], i);
a260abc9
DE		 3143}")
3144
dfbdccdb 3145(define_insn "*boolcsi3_internal1"
cd2b37d9 3146 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3147 (match_operator:SI 3 "boolean_operator"
3148 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3149 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
1fd4e8c1 3150 ""
dfbdccdb 3151 "%q3 %0,%2,%1")
1fd4e8c1 3152
dfbdccdb 3153(define_insn "*boolcsi3_internal2"
52d3af72 3154 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3155 (compare:CC (match_operator:SI 4 "boolean_operator"
3156 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3157 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3158 (const_int 0)))
52d3af72 3159 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3160 "TARGET_32BIT"
52d3af72 3161 "@
dfbdccdb 3162 %q4. %3,%2,%1
52d3af72
DE		 3163 #"
3164 [(set_attr "type" "compare")
3165 (set_attr "length" "4,8")])
3166
3167(define_split
3168 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3169 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3170 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3171 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3172 (const_int 0)))
52d3af72 3173 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3174 "TARGET_32BIT && reload_completed"
dfbdccdb 3175 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3176 (set (match_dup 0)
3177 (compare:CC (match_dup 3)
3178 (const_int 0)))]
3179 "")
1fd4e8c1 3180
dfbdccdb 3181(define_insn "*boolcsi3_internal3"
52d3af72 3182 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3183 (compare:CC (match_operator:SI 4 "boolean_operator"
3184 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3185 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3186 (const_int 0)))
52d3af72 3187 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3188 (match_dup 4))]
4b8a63d6 3189 "TARGET_32BIT"
52d3af72 3190 "@
dfbdccdb 3191 %q4. %0,%2,%1
52d3af72
DE		 3192 #"
3193 [(set_attr "type" "compare")
3194 (set_attr "length" "4,8")])
3195
3196(define_split
e72247f4 3197 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3198 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3199 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3200 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3201 (const_int 0)))
75540af0 3202 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3203 (match_dup 4))]
4b8a63d6 3204 "TARGET_32BIT && reload_completed"
dfbdccdb 3205 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3206 (set (match_dup 3)
3207 (compare:CC (match_dup 0)
3208 (const_int 0)))]
3209 "")
3210
dfbdccdb 3211(define_insn "*boolccsi3_internal1"
cd2b37d9 3212 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3213 (match_operator:SI 3 "boolean_operator"
3214 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3215 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
1fd4e8c1 3216 ""
dfbdccdb 3217 "%q3 %0,%1,%2")
1fd4e8c1 3218
dfbdccdb 3219(define_insn "*boolccsi3_internal2"
52d3af72 3220 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3221 (compare:CC (match_operator:SI 4 "boolean_operator"
3222 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3223 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3224 (const_int 0)))
52d3af72 3225 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3226 "TARGET_32BIT"
52d3af72 3227 "@
dfbdccdb 3228 %q4. %3,%1,%2
52d3af72
DE		 3229 #"
3230 [(set_attr "type" "compare")
3231 (set_attr "length" "4,8")])
3232
3233(define_split
3234 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3235 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3236 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3237 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3238 (const_int 0)))
52d3af72 3239 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3240 "TARGET_32BIT && reload_completed"
dfbdccdb 3241 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3242 (set (match_dup 0)
3243 (compare:CC (match_dup 3)
3244 (const_int 0)))]
3245 "")
1fd4e8c1 3246
dfbdccdb 3247(define_insn "*boolccsi3_internal3"
52d3af72 3248 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3249 (compare:CC (match_operator:SI 4 "boolean_operator"
3250 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3251 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3252 (const_int 0)))
52d3af72 3253 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3254 (match_dup 4))]
4b8a63d6 3255 "TARGET_32BIT"
52d3af72 3256 "@
dfbdccdb 3257 %q4. %0,%1,%2
52d3af72
DE		 3258 #"
3259 [(set_attr "type" "compare")
3260 (set_attr "length" "4,8")])
3261
3262(define_split
e72247f4 3263 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3264 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3265 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3266 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3267 (const_int 0)))
75540af0 3268 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3269 (match_dup 4))]
4b8a63d6 3270 "TARGET_32BIT && reload_completed"
dfbdccdb 3271 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3272 (set (match_dup 3)
3273 (compare:CC (match_dup 0)
3274 (const_int 0)))]
3275 "")
1fd4e8c1
RK		 3276
3277;; maskir insn. We need four forms because things might be in arbitrary
3278;; orders. Don't define forms that only set CR fields because these
3279;; would modify an input register.
3280
7cd5235b 3281(define_insn "*maskir_internal1"
cd2b37d9 3282 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3283 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3284 (match_operand:SI 1 "gpc_reg_operand" "0"))
3285 (and:SI (match_dup 2)
cd2b37d9 3286 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
ca7f5001 3287 "TARGET_POWER"
01def764 3288 "maskir %0,%3,%2")
1fd4e8c1 3289
7cd5235b 3290(define_insn "*maskir_internal2"
242e8072 3291 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3292 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3293 (match_operand:SI 1 "gpc_reg_operand" "0"))
cd2b37d9 3294 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764 3295 (match_dup 2))))]
ca7f5001 3296 "TARGET_POWER"
01def764 3297 "maskir %0,%3,%2")
1fd4e8c1 3298
7cd5235b 3299(define_insn "*maskir_internal3"
cd2b37d9 3300 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764 3301 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
cd2b37d9 3302 (match_operand:SI 3 "gpc_reg_operand" "r"))
01def764
RK		 3303 (and:SI (not:SI (match_dup 2))
3304 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3305 "TARGET_POWER"
01def764 3306 "maskir %0,%3,%2")
1fd4e8c1 3307
7cd5235b 3308(define_insn "*maskir_internal4"
cd2b37d9
RK		 3309 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3310 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764
RK		 3311 (match_operand:SI 2 "gpc_reg_operand" "r"))
3312 (and:SI (not:SI (match_dup 2))
3313 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3314 "TARGET_POWER"
01def764 3315 "maskir %0,%3,%2")
1fd4e8c1 3316
7cd5235b 3317(define_insn "*maskir_internal5"
9ebbca7d 3318 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3319 (compare:CC
9ebbca7d
GK		 3320 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3321 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
01def764 3322 (and:SI (match_dup 2)
9ebbca7d 3323 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1fd4e8c1 3324 (const_int 0)))
9ebbca7d 3325 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3326 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3327 (and:SI (match_dup 2) (match_dup 3))))]
ca7f5001 3328 "TARGET_POWER"
9ebbca7d
GK		 3329 "@
3330 maskir. %0,%3,%2
3331 #"
3332 [(set_attr "type" "compare")
3333 (set_attr "length" "4,8")])
3334
3335(define_split
3336 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3337 (compare:CC
3338 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3339 (match_operand:SI 1 "gpc_reg_operand" ""))
3340 (and:SI (match_dup 2)
3341 (match_operand:SI 3 "gpc_reg_operand" "")))
3342 (const_int 0)))
3343 (set (match_operand:SI 0 "gpc_reg_operand" "")
3344 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3345 (and:SI (match_dup 2) (match_dup 3))))]
3346 "TARGET_POWER && reload_completed"
3347 [(set (match_dup 0)
3348 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3349 (and:SI (match_dup 2) (match_dup 3))))
3350 (set (match_dup 4)
3351 (compare:CC (match_dup 0)
3352 (const_int 0)))]
3353 "")
1fd4e8c1 3354
7cd5235b 3355(define_insn "*maskir_internal6"
9ebbca7d 3356 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3357 (compare:CC
9ebbca7d
GK		 3358 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3359 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3360 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
01def764 3361 (match_dup 2)))
1fd4e8c1 3362 (const_int 0)))
9ebbca7d 3363 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3364 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3365 (and:SI (match_dup 3) (match_dup 2))))]
ca7f5001 3366 "TARGET_POWER"
9ebbca7d
GK		 3367 "@
3368 maskir. %0,%3,%2
3369 #"
3370 [(set_attr "type" "compare")
3371 (set_attr "length" "4,8")])
3372
3373(define_split
3374 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3375 (compare:CC
3376 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3377 (match_operand:SI 1 "gpc_reg_operand" ""))
3378 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3379 (match_dup 2)))
3380 (const_int 0)))
3381 (set (match_operand:SI 0 "gpc_reg_operand" "")
3382 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3383 (and:SI (match_dup 3) (match_dup 2))))]
3384 "TARGET_POWER && reload_completed"
3385 [(set (match_dup 0)
3386 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3387 (and:SI (match_dup 3) (match_dup 2))))
3388 (set (match_dup 4)
3389 (compare:CC (match_dup 0)
3390 (const_int 0)))]
3391 "")
1fd4e8c1 3392
7cd5235b 3393(define_insn "*maskir_internal7"
9ebbca7d 3394 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
815cdc52 3395 (compare:CC
9ebbca7d
GK		 3396 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3397 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
815cdc52 3398 (and:SI (not:SI (match_dup 2))
9ebbca7d 3399 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
815cdc52 3400 (const_int 0)))
9ebbca7d 3401 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 3402 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3403 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3404 "TARGET_POWER"
9ebbca7d
GK		 3405 "@
3406 maskir. %0,%3,%2
3407 #"
3408 [(set_attr "type" "compare")
3409 (set_attr "length" "4,8")])
3410
3411(define_split
3412 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3413 (compare:CC
3414 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3415 (match_operand:SI 3 "gpc_reg_operand" ""))
3416 (and:SI (not:SI (match_dup 2))
3417 (match_operand:SI 1 "gpc_reg_operand" "")))
3418 (const_int 0)))
3419 (set (match_operand:SI 0 "gpc_reg_operand" "")
3420 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3421 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3422 "TARGET_POWER && reload_completed"
3423 [(set (match_dup 0)
3424 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3425 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3426 (set (match_dup 4)
3427 (compare:CC (match_dup 0)
3428 (const_int 0)))]
3429 "")
1fd4e8c1 3430
7cd5235b 3431(define_insn "*maskir_internal8"
9ebbca7d 3432 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3433 (compare:CC
9ebbca7d
GK		 3434 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3435 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
01def764 3436 (and:SI (not:SI (match_dup 2))
9ebbca7d 3437 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
1fd4e8c1 3438 (const_int 0)))
9ebbca7d 3439 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3440 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3441 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
ca7f5001 3442 "TARGET_POWER"
9ebbca7d
GK		 3443 "@
3444 maskir. %0,%3,%2
3445 #"
3446 [(set_attr "type" "compare")
3447 (set_attr "length" "4,8")])
fcce224d 3448
9ebbca7d
GK		 3449(define_split
3450 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3451 (compare:CC
3452 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3453 (match_operand:SI 2 "gpc_reg_operand" ""))
3454 (and:SI (not:SI (match_dup 2))
3455 (match_operand:SI 1 "gpc_reg_operand" "")))
3456 (const_int 0)))
3457 (set (match_operand:SI 0 "gpc_reg_operand" "")
3458 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3459 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3460 "TARGET_POWER && reload_completed"
3461 [(set (match_dup 0)
3462 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3463 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3464 (set (match_dup 4)
3465 (compare:CC (match_dup 0)
3466 (const_int 0)))]
3467 "")
fcce224d 3468\f
1fd4e8c1
RK		 3469;; Rotate and shift insns, in all their variants. These support shifts,
3470;; field inserts and extracts, and various combinations thereof.
034c1be0 3471(define_expand "insv"
0ad91047
DE		 3472 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3473 (match_operand:SI 1 "const_int_operand" "")
3474 (match_operand:SI 2 "const_int_operand" ""))
3475 (match_operand 3 "gpc_reg_operand" ""))]
034c1be0
MM		 3476 ""
3477 "
3478{
3479 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3480 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
14502dad
JM		 3481 compiler if the address of the structure is taken later. Likewise, do
3482 not handle invalid E500 subregs. */
034c1be0 3483 if (GET_CODE (operands[0]) == SUBREG
14502dad
JM		 3484 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3485 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3486 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
034c1be0 3487 FAIL;
a78e33fc
DE		 3488
3489 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3490 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3491 else
3492 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3493 DONE;
034c1be0
MM		 3494}")
3495
a78e33fc 3496(define_insn "insvsi"
cd2b37d9 3497 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1
RK		 3498 (match_operand:SI 1 "const_int_operand" "i")
3499 (match_operand:SI 2 "const_int_operand" "i"))
cd2b37d9 3500 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1fd4e8c1
RK		 3501 ""
3502 "*
3503{
3504 int start = INTVAL (operands[2]) & 31;
3505 int size = INTVAL (operands[1]) & 31;
3506
89e9f3a8
MM		 3507 operands[4] = GEN_INT (32 - start - size);
3508 operands[1] = GEN_INT (start + size - 1);
a66078ee 3509 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3510}"
3511 [(set_attr "type" "insert_word")])
1fd4e8c1 3512
a78e33fc 3513(define_insn "*insvsi_internal1"
d56d506a
RK		 3514 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3515 (match_operand:SI 1 "const_int_operand" "i")
3516 (match_operand:SI 2 "const_int_operand" "i"))
6d0a8091 3517 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
d56d506a 3518 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3519 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3520 "*
3521{
3522 int shift = INTVAL (operands[4]) & 31;
3523 int start = INTVAL (operands[2]) & 31;
3524 int size = INTVAL (operands[1]) & 31;
3525
89e9f3a8 3526 operands[4] = GEN_INT (shift - start - size);
6d0a8091 3527 operands[1] = GEN_INT (start + size - 1);
a66078ee 3528 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3529}"
3530 [(set_attr "type" "insert_word")])
d56d506a 3531
a78e33fc 3532(define_insn "*insvsi_internal2"
d56d506a
RK		 3533 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3534 (match_operand:SI 1 "const_int_operand" "i")
3535 (match_operand:SI 2 "const_int_operand" "i"))
3536 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3537 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3538 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3539 "*
3540{
3541 int shift = INTVAL (operands[4]) & 31;
3542 int start = INTVAL (operands[2]) & 31;
3543 int size = INTVAL (operands[1]) & 31;
3544
89e9f3a8
MM		 3545 operands[4] = GEN_INT (32 - shift - start - size);
3546 operands[1] = GEN_INT (start + size - 1);
a66078ee 3547 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3548}"
3549 [(set_attr "type" "insert_word")])
d56d506a 3550
a78e33fc 3551(define_insn "*insvsi_internal3"
d56d506a
RK		 3552 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3553 (match_operand:SI 1 "const_int_operand" "i")
3554 (match_operand:SI 2 "const_int_operand" "i"))
3555 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3556 (match_operand:SI 4 "const_int_operand" "i")))]
95e8f2f3 3557 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3558 "*
3559{
3560 int shift = INTVAL (operands[4]) & 31;
3561 int start = INTVAL (operands[2]) & 31;
3562 int size = INTVAL (operands[1]) & 31;
3563
89e9f3a8
MM		 3564 operands[4] = GEN_INT (32 - shift - start - size);
3565 operands[1] = GEN_INT (start + size - 1);
a66078ee 3566 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3567}"
3568 [(set_attr "type" "insert_word")])
d56d506a 3569
a78e33fc 3570(define_insn "*insvsi_internal4"
d56d506a
RK		 3571 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3572 (match_operand:SI 1 "const_int_operand" "i")
3573 (match_operand:SI 2 "const_int_operand" "i"))
3574 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3575 (match_operand:SI 4 "const_int_operand" "i")
3576 (match_operand:SI 5 "const_int_operand" "i")))]
3577 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3578 "*
3579{
3580 int extract_start = INTVAL (operands[5]) & 31;
3581 int extract_size = INTVAL (operands[4]) & 31;
3582 int insert_start = INTVAL (operands[2]) & 31;
3583 int insert_size = INTVAL (operands[1]) & 31;
3584
3585/* Align extract field with insert field */
3a598fbe 3586 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
89e9f3a8 3587 operands[1] = GEN_INT (insert_start + insert_size - 1);
a66078ee 3588 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
8e8238f1
DE		 3589}"
3590 [(set_attr "type" "insert_word")])
d56d506a 3591
f241bf89
EC		 3592;; combine patterns for rlwimi
3593(define_insn "*insvsi_internal5"
3594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3595 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3596 (match_operand:SI 1 "mask_operand" "i"))
3597 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3598 (match_operand:SI 2 "const_int_operand" "i"))
3599 (match_operand:SI 5 "mask_operand" "i"))))]
3600 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3601 "*
3602{
3603 int me = extract_ME(operands[5]);
3604 int mb = extract_MB(operands[5]);
3605 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3606 operands[2] = GEN_INT(mb);
3607 operands[1] = GEN_INT(me);
3608 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3609}"
3610 [(set_attr "type" "insert_word")])
3611
3612(define_insn "*insvsi_internal6"
3613 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3614 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3615 (match_operand:SI 2 "const_int_operand" "i"))
3616 (match_operand:SI 5 "mask_operand" "i"))
3617 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3618 (match_operand:SI 1 "mask_operand" "i"))))]
3619 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3620 "*
3621{
3622 int me = extract_ME(operands[5]);
3623 int mb = extract_MB(operands[5]);
3624 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3625 operands[2] = GEN_INT(mb);
3626 operands[1] = GEN_INT(me);
3627 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3628}"
3629 [(set_attr "type" "insert_word")])
3630
a78e33fc 3631(define_insn "insvdi"
685f3906 3632 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
a78e33fc
DE		 3633 (match_operand:SI 1 "const_int_operand" "i")
3634 (match_operand:SI 2 "const_int_operand" "i"))
685f3906
DE		 3635 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3636 "TARGET_POWERPC64"
3637 "*
3638{
3639 int start = INTVAL (operands[2]) & 63;
3640 int size = INTVAL (operands[1]) & 63;
3641
a78e33fc
DE		 3642 operands[1] = GEN_INT (64 - start - size);
3643 return \"rldimi %0,%3,%H1,%H2\";
44cd321e
PS		 3644}"
3645 [(set_attr "type" "insert_dword")])
685f3906 3646
11ac38b2
DE		 3647(define_insn "*insvdi_internal2"
3648 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3649 (match_operand:SI 1 "const_int_operand" "i")
3650 (match_operand:SI 2 "const_int_operand" "i"))
3651 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3652 (match_operand:SI 4 "const_int_operand" "i")))]
3653 "TARGET_POWERPC64
3654 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3655 "*
3656{
3657 int shift = INTVAL (operands[4]) & 63;
3658 int start = (INTVAL (operands[2]) & 63) - 32;
3659 int size = INTVAL (operands[1]) & 63;
3660
3661 operands[4] = GEN_INT (64 - shift - start - size);
3662 operands[2] = GEN_INT (start);
3663 operands[1] = GEN_INT (start + size - 1);
3664 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3665}")
3666
3667(define_insn "*insvdi_internal3"
3668 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3669 (match_operand:SI 1 "const_int_operand" "i")
3670 (match_operand:SI 2 "const_int_operand" "i"))
3671 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3672 (match_operand:SI 4 "const_int_operand" "i")))]
3673 "TARGET_POWERPC64
3674 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3675 "*
3676{
3677 int shift = INTVAL (operands[4]) & 63;
3678 int start = (INTVAL (operands[2]) & 63) - 32;
3679 int size = INTVAL (operands[1]) & 63;
3680
3681 operands[4] = GEN_INT (64 - shift - start - size);
3682 operands[2] = GEN_INT (start);
3683 operands[1] = GEN_INT (start + size - 1);
3684 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3685}")
3686
034c1be0 3687(define_expand "extzv"
0ad91047
DE		 3688 [(set (match_operand 0 "gpc_reg_operand" "")
3689 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3690 (match_operand:SI 2 "const_int_operand" "")
3691 (match_operand:SI 3 "const_int_operand" "")))]
034c1be0
MM		 3692 ""
3693 "
3694{
3695 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3696 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3697 compiler if the address of the structure is taken later. */
3698 if (GET_CODE (operands[0]) == SUBREG
3699 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3700 FAIL;
a78e33fc
DE		 3701
3702 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3703 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3704 else
3705 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3706 DONE;
034c1be0
MM		 3707}")
3708
a78e33fc 3709(define_insn "extzvsi"
cd2b37d9
RK		 3710 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3711 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3712 (match_operand:SI 2 "const_int_operand" "i")
3713 (match_operand:SI 3 "const_int_operand" "i")))]
3714 ""
3715 "*
3716{
3717 int start = INTVAL (operands[3]) & 31;
3718 int size = INTVAL (operands[2]) & 31;
3719
3720 if (start + size >= 32)
3721 operands[3] = const0_rtx;
3722 else
89e9f3a8 3723 operands[3] = GEN_INT (start + size);
ca7f5001 3724 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
1fd4e8c1
RK		 3725}")
3726
a78e33fc 3727(define_insn "*extzvsi_internal1"
9ebbca7d
GK		 3728 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3729 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3730 (match_operand:SI 2 "const_int_operand" "i,i")
3731 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3732 (const_int 0)))
9ebbca7d 3733 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3734 ""
1fd4e8c1
RK		 3735 "*
3736{
3737 int start = INTVAL (operands[3]) & 31;
3738 int size = INTVAL (operands[2]) & 31;
3739
9ebbca7d
GK		 3740 /* Force split for non-cc0 compare. */
3741 if (which_alternative == 1)
3742 return \"#\";
3743
43a88a8c 3744 /* If the bit-field being tested fits in the upper or lower half of a
a7a975e1
RK		 3745 word, it is possible to use andiu. or andil. to test it. This is
3746 useful because the condition register set-use delay is smaller for
3747 andi[ul]. than for rlinm. This doesn't work when the starting bit
3748 position is 0 because the LT and GT bits may be set wrong. */
3749
3750 if ((start > 0 && start + size <= 16) || start >= 16)
df031c43 3751 {
3a598fbe 3752 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
df031c43
RK		 3753 - (1 << (16 - (start & 15) - size))));
3754 if (start < 16)
ca7f5001 3755 return \"{andiu.|andis.} %4,%1,%3\";
df031c43 3756 else
ca7f5001 3757 return \"{andil.|andi.} %4,%1,%3\";
df031c43 3758 }
7e69e155 3759
1fd4e8c1
RK		 3760 if (start + size >= 32)
3761 operands[3] = const0_rtx;
3762 else
89e9f3a8 3763 operands[3] = GEN_INT (start + size);
ca7f5001 3764 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
1fd4e8c1 3765}"
44cd321e 3766 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3767 (set_attr "length" "4,8")])
3768
3769(define_split
3770 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3771 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3772 (match_operand:SI 2 "const_int_operand" "")
3773 (match_operand:SI 3 "const_int_operand" ""))
3774 (const_int 0)))
3775 (clobber (match_scratch:SI 4 ""))]
ce71f754 3776 "reload_completed"
9ebbca7d
GK		 3777 [(set (match_dup 4)
3778 (zero_extract:SI (match_dup 1) (match_dup 2)
3779 (match_dup 3)))
3780 (set (match_dup 0)
3781 (compare:CC (match_dup 4)
3782 (const_int 0)))]
3783 "")
1fd4e8c1 3784
a78e33fc 3785(define_insn "*extzvsi_internal2"
9ebbca7d
GK		 3786 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3787 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3788 (match_operand:SI 2 "const_int_operand" "i,i")
3789 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3790 (const_int 0)))
9ebbca7d 3791 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3792 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3793 ""
1fd4e8c1
RK		 3794 "*
3795{
3796 int start = INTVAL (operands[3]) & 31;
3797 int size = INTVAL (operands[2]) & 31;
3798
9ebbca7d
GK		 3799 /* Force split for non-cc0 compare. */
3800 if (which_alternative == 1)
3801 return \"#\";
3802
bc401279 3803 /* Since we are using the output value, we can't ignore any need for
43a88a8c 3804 a shift. The bit-field must end at the LSB. */
bc401279 3805 if (start >= 16 && start + size == 32)
df031c43 3806 {
bc401279
AM		 3807 operands[3] = GEN_INT ((1 << size) - 1);
3808 return \"{andil.|andi.} %0,%1,%3\";
df031c43 3809 }
7e69e155 3810
1fd4e8c1
RK		 3811 if (start + size >= 32)
3812 operands[3] = const0_rtx;
3813 else
89e9f3a8 3814 operands[3] = GEN_INT (start + size);
ca7f5001 3815 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
1fd4e8c1 3816}"
44cd321e 3817 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3818 (set_attr "length" "4,8")])
3819
3820(define_split
3821 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3822 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3823 (match_operand:SI 2 "const_int_operand" "")
3824 (match_operand:SI 3 "const_int_operand" ""))
3825 (const_int 0)))
3826 (set (match_operand:SI 0 "gpc_reg_operand" "")
3827 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3828 "reload_completed"
9ebbca7d
GK		 3829 [(set (match_dup 0)
3830 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3831 (set (match_dup 4)
3832 (compare:CC (match_dup 0)
3833 (const_int 0)))]
3834 "")
1fd4e8c1 3835
a78e33fc 3836(define_insn "extzvdi"
685f3906
DE		 3837 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3838 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3839 (match_operand:SI 2 "const_int_operand" "i")
3840 (match_operand:SI 3 "const_int_operand" "i")))]
685f3906
DE		 3841 "TARGET_POWERPC64"
3842 "*
3843{
3844 int start = INTVAL (operands[3]) & 63;
3845 int size = INTVAL (operands[2]) & 63;
3846
3847 if (start + size >= 64)
3848 operands[3] = const0_rtx;
3849 else
89e9f3a8
MM		 3850 operands[3] = GEN_INT (start + size);
3851 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3852 return \"rldicl %0,%1,%3,%2\";
3853}")
3854
a78e33fc 3855(define_insn "*extzvdi_internal1"
29ae5b89
JL		 3856 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3857 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3858 (match_operand:SI 2 "const_int_operand" "i")
3859 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3860 (const_int 0)))
29ae5b89 3861 (clobber (match_scratch:DI 4 "=r"))]
683bdff7 3862 "TARGET_64BIT"
685f3906
DE		 3863 "*
3864{
3865 int start = INTVAL (operands[3]) & 63;
3866 int size = INTVAL (operands[2]) & 63;
3867
3868 if (start + size >= 64)
3869 operands[3] = const0_rtx;
3870 else
89e9f3a8
MM		 3871 operands[3] = GEN_INT (start + size);
3872 operands[2] = GEN_INT (64 - size);
685f3906 3873 return \"rldicl. %4,%1,%3,%2\";
9a3c428b
DE		 3874}"
3875 [(set_attr "type" "compare")])
685f3906 3876
a78e33fc 3877(define_insn "*extzvdi_internal2"
29ae5b89
JL		 3878 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3879 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3880 (match_operand:SI 2 "const_int_operand" "i")
3881 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3882 (const_int 0)))
29ae5b89 3883 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
685f3906 3884 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
683bdff7 3885 "TARGET_64BIT"
685f3906
DE		 3886 "*
3887{
3888 int start = INTVAL (operands[3]) & 63;
3889 int size = INTVAL (operands[2]) & 63;
3890
3891 if (start + size >= 64)
3892 operands[3] = const0_rtx;
3893 else
89e9f3a8
MM		 3894 operands[3] = GEN_INT (start + size);
3895 operands[2] = GEN_INT (64 - size);
685f3906 3896 return \"rldicl. %0,%1,%3,%2\";
9a3c428b
DE		 3897}"
3898 [(set_attr "type" "compare")])
685f3906 3899
1fd4e8c1 3900(define_insn "rotlsi3"
44cd321e
PS		 3901 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3902 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3903 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
1fd4e8c1 3904 ""
44cd321e
PS		 3905 "@
3906 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3907 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3908 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 3909
a260abc9 3910(define_insn "*rotlsi3_internal2"
44cd321e
PS		 3911 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3912 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3913 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3914 (const_int 0)))
44cd321e 3915 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
ce71f754 3916 ""
9ebbca7d 3917 "@
44cd321e
PS		 3918 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3919 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3920 #
9ebbca7d 3921 #"
44cd321e
PS		 3922 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3923 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3924
3925(define_split
3926 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3927 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3928 (match_operand:SI 2 "reg_or_cint_operand" ""))
3929 (const_int 0)))
3930 (clobber (match_scratch:SI 3 ""))]
ce71f754 3931 "reload_completed"
9ebbca7d
GK		 3932 [(set (match_dup 3)
3933 (rotate:SI (match_dup 1) (match_dup 2)))
3934 (set (match_dup 0)
3935 (compare:CC (match_dup 3)
3936 (const_int 0)))]
3937 "")
1fd4e8c1 3938
a260abc9 3939(define_insn "*rotlsi3_internal3"
44cd321e
PS		 3940 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3941 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3942 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3943 (const_int 0)))
44cd321e 3944 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 3945 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3946 ""
9ebbca7d 3947 "@
44cd321e
PS		 3948 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3949 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3950 #
9ebbca7d 3951 #"
44cd321e
PS		 3952 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3953 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3954
3955(define_split
3956 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3957 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3958 (match_operand:SI 2 "reg_or_cint_operand" ""))
3959 (const_int 0)))
3960 (set (match_operand:SI 0 "gpc_reg_operand" "")
3961 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3962 "reload_completed"
9ebbca7d
GK		 3963 [(set (match_dup 0)
3964 (rotate:SI (match_dup 1) (match_dup 2)))
3965 (set (match_dup 3)
3966 (compare:CC (match_dup 0)
3967 (const_int 0)))]
3968 "")
1fd4e8c1 3969
a260abc9 3970(define_insn "*rotlsi3_internal4"
44cd321e
PS		 3971 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3972 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3973 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3974 (match_operand:SI 3 "mask_operand" "n,n")))]
1fd4e8c1 3975 ""
44cd321e
PS		 3976 "@
3977 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3978 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3979 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 3980
a260abc9 3981(define_insn "*rotlsi3_internal5"
44cd321e 3982 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 3983 (compare:CC (and:SI
44cd321e
PS		 3984 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3985 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3986 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 3987 (const_int 0)))
44cd321e 3988 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
ce71f754 3989 ""
9ebbca7d 3990 "@
44cd321e
PS		 3991 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3992 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3993 #
9ebbca7d 3994 #"
44cd321e
PS		 3995 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3996 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3997
3998(define_split
3999 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4000 (compare:CC (and:SI
4001 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4002 (match_operand:SI 2 "reg_or_cint_operand" ""))
4003 (match_operand:SI 3 "mask_operand" ""))
4004 (const_int 0)))
4005 (clobber (match_scratch:SI 4 ""))]
ce71f754 4006 "reload_completed"
9ebbca7d
GK		 4007 [(set (match_dup 4)
4008 (and:SI (rotate:SI (match_dup 1)
4009 (match_dup 2))
4010 (match_dup 3)))
4011 (set (match_dup 0)
4012 (compare:CC (match_dup 4)
4013 (const_int 0)))]
4014 "")
1fd4e8c1 4015
a260abc9 4016(define_insn "*rotlsi3_internal6"
44cd321e 4017 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 4018 (compare:CC (and:SI
44cd321e
PS		 4019 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4020 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4021 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 4022 (const_int 0)))
44cd321e 4023 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4024 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4025 ""
9ebbca7d 4026 "@
44cd321e
PS		 4027 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4028 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4029 #
9ebbca7d 4030 #"
44cd321e
PS		 4031 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4032 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4033
4034(define_split
4035 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4036 (compare:CC (and:SI
4037 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4038 (match_operand:SI 2 "reg_or_cint_operand" ""))
4039 (match_operand:SI 3 "mask_operand" ""))
4040 (const_int 0)))
4041 (set (match_operand:SI 0 "gpc_reg_operand" "")
4042 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4043 "reload_completed"
9ebbca7d
GK		 4044 [(set (match_dup 0)
4045 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4046 (set (match_dup 4)
4047 (compare:CC (match_dup 0)
4048 (const_int 0)))]
4049 "")
1fd4e8c1 4050
a260abc9 4051(define_insn "*rotlsi3_internal7"
cd2b37d9 4052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4053 (zero_extend:SI
4054 (subreg:QI
cd2b37d9 4055 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4056 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4057 ""
ca7f5001 4058 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
1fd4e8c1 4059
a260abc9 4060(define_insn "*rotlsi3_internal8"
44cd321e 4061 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4062 (compare:CC (zero_extend:SI
4063 (subreg:QI
44cd321e
PS		 4064 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4065 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4066 (const_int 0)))
44cd321e 4067 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4068 ""
9ebbca7d 4069 "@
44cd321e
PS		 4070 {rlnm.|rlwnm.} %3,%1,%2,0xff
4071 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4072 #
9ebbca7d 4073 #"
44cd321e
PS		 4074 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4075 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4076
4077(define_split
4078 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4079 (compare:CC (zero_extend:SI
4080 (subreg:QI
4081 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4082 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4083 (const_int 0)))
4084 (clobber (match_scratch:SI 3 ""))]
4085 "reload_completed"
4086 [(set (match_dup 3)
4087 (zero_extend:SI (subreg:QI
4088 (rotate:SI (match_dup 1)
4089 (match_dup 2)) 0)))
4090 (set (match_dup 0)
4091 (compare:CC (match_dup 3)
4092 (const_int 0)))]
4093 "")
1fd4e8c1 4094
a260abc9 4095(define_insn "*rotlsi3_internal9"
44cd321e 4096 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4097 (compare:CC (zero_extend:SI
4098 (subreg:QI
44cd321e
PS		 4099 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4100 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4101 (const_int 0)))
44cd321e 4102 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4103 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4104 ""
9ebbca7d 4105 "@
44cd321e
PS		 4106 {rlnm.|rlwnm.} %0,%1,%2,0xff
4107 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4108 #
9ebbca7d 4109 #"
44cd321e
PS		 4110 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4111 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4112
4113(define_split
4114 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4115 (compare:CC (zero_extend:SI
4116 (subreg:QI
4117 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4118 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4119 (const_int 0)))
4120 (set (match_operand:SI 0 "gpc_reg_operand" "")
4121 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4122 "reload_completed"
4123 [(set (match_dup 0)
4124 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4125 (set (match_dup 3)
4126 (compare:CC (match_dup 0)
4127 (const_int 0)))]
4128 "")
1fd4e8c1 4129
a260abc9 4130(define_insn "*rotlsi3_internal10"
44cd321e 4131 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 4132 (zero_extend:SI
4133 (subreg:HI
44cd321e
PS		 4134 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4135 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
1fd4e8c1 4136 ""
44cd321e
PS		 4137 "@
4138 {rlnm|rlwnm} %0,%1,%2,0xffff
4139 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4140 [(set_attr "type" "var_shift_rotate,integer")])
4141
1fd4e8c1 4142
a260abc9 4143(define_insn "*rotlsi3_internal11"
44cd321e 4144 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4145 (compare:CC (zero_extend:SI
4146 (subreg:HI
44cd321e
PS		 4147 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4148 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4149 (const_int 0)))
44cd321e 4150 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4151 ""
9ebbca7d 4152 "@
44cd321e
PS		 4153 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4154 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4155 #
9ebbca7d 4156 #"
44cd321e
PS		 4157 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4158 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4159
4160(define_split
4161 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4162 (compare:CC (zero_extend:SI
4163 (subreg:HI
4164 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4165 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4166 (const_int 0)))
4167 (clobber (match_scratch:SI 3 ""))]
4168 "reload_completed"
4169 [(set (match_dup 3)
4170 (zero_extend:SI (subreg:HI
4171 (rotate:SI (match_dup 1)
4172 (match_dup 2)) 0)))
4173 (set (match_dup 0)
4174 (compare:CC (match_dup 3)
4175 (const_int 0)))]
4176 "")
1fd4e8c1 4177
a260abc9 4178(define_insn "*rotlsi3_internal12"
44cd321e 4179 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4180 (compare:CC (zero_extend:SI
4181 (subreg:HI
44cd321e
PS		 4182 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4183 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4184 (const_int 0)))
44cd321e 4185 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4186 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4187 ""
9ebbca7d 4188 "@
44cd321e
PS		 4189 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4190 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4191 #
9ebbca7d 4192 #"
44cd321e
PS		 4193 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4194 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4195
4196(define_split
4197 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4198 (compare:CC (zero_extend:SI
4199 (subreg:HI
4200 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4201 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4202 (const_int 0)))
4203 (set (match_operand:SI 0 "gpc_reg_operand" "")
4204 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4205 "reload_completed"
4206 [(set (match_dup 0)
4207 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4208 (set (match_dup 3)
4209 (compare:CC (match_dup 0)
4210 (const_int 0)))]
4211 "")
1fd4e8c1
RK		 4212
4213;; Note that we use "sle." instead of "sl." so that we can set
4214;; SHIFT_COUNT_TRUNCATED.
4215
ca7f5001
RK		 4216(define_expand "ashlsi3"
4217 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4218 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4219 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4220 ""
4221 "
4222{
4223 if (TARGET_POWER)
4224 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4225 else
25c341fa 4226 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4227 DONE;
4228}")
4229
4230(define_insn "ashlsi3_power"
cd2b37d9
RK		 4231 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4232 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4233 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4234 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4235 "TARGET_POWER"
1fd4e8c1
RK		 4236 "@
4237 sle %0,%1,%2
9ebbca7d 4238 {sli|slwi} %0,%1,%h2")
ca7f5001 4239
25c341fa 4240(define_insn "ashlsi3_no_power"
44cd321e
PS		 4241 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4242 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4243 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4244 "! TARGET_POWER"
44cd321e
PS		 4245 "@
4246 {sl|slw} %0,%1,%2
4247 {sli|slwi} %0,%1,%h2"
4248 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 4249
4250(define_insn ""
9ebbca7d
GK		 4251 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4252 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4253 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4254 (const_int 0)))
9ebbca7d
GK		 4255 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4256 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4257 "TARGET_POWER"
1fd4e8c1
RK		 4258 "@
4259 sle. %3,%1,%2
9ebbca7d
GK		 4260 {sli.|slwi.} %3,%1,%h2
4261 #
4262 #"
4263 [(set_attr "type" "delayed_compare")
4264 (set_attr "length" "4,4,8,8")])
4265
4266(define_split
4267 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4268 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4269 (match_operand:SI 2 "reg_or_cint_operand" ""))
4270 (const_int 0)))
4271 (clobber (match_scratch:SI 3 ""))
4272 (clobber (match_scratch:SI 4 ""))]
4273 "TARGET_POWER && reload_completed"
4274 [(parallel [(set (match_dup 3)
4275 (ashift:SI (match_dup 1) (match_dup 2)))
4276 (clobber (match_dup 4))])
4277 (set (match_dup 0)
4278 (compare:CC (match_dup 3)
4279 (const_int 0)))]
4280 "")
25c341fa 4281
ca7f5001 4282(define_insn ""
44cd321e
PS		 4283 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4284 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4285 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4286 (const_int 0)))
44cd321e 4287 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4b8a63d6 4288 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4289 "@
44cd321e
PS		 4290 {sl.|slw.} %3,%1,%2
4291 {sli.|slwi.} %3,%1,%h2
4292 #
9ebbca7d 4293 #"
44cd321e
PS		 4294 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4295 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4296
4297(define_split
4298 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4299 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4300 (match_operand:SI 2 "reg_or_cint_operand" ""))
4301 (const_int 0)))
4302 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4303 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4304 [(set (match_dup 3)
4305 (ashift:SI (match_dup 1) (match_dup 2)))
4306 (set (match_dup 0)
4307 (compare:CC (match_dup 3)
4308 (const_int 0)))]
4309 "")
1fd4e8c1
RK		 4310
4311(define_insn ""
9ebbca7d
GK		 4312 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4313 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4314 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4315 (const_int 0)))
9ebbca7d 4316 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4317 (ashift:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4318 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4319 "TARGET_POWER"
1fd4e8c1
RK		 4320 "@
4321 sle. %0,%1,%2
9ebbca7d
GK		 4322 {sli.|slwi.} %0,%1,%h2
4323 #
4324 #"
4325 [(set_attr "type" "delayed_compare")
4326 (set_attr "length" "4,4,8,8")])
4327
4328(define_split
4329 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4330 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4331 (match_operand:SI 2 "reg_or_cint_operand" ""))
4332 (const_int 0)))
4333 (set (match_operand:SI 0 "gpc_reg_operand" "")
4334 (ashift:SI (match_dup 1) (match_dup 2)))
4335 (clobber (match_scratch:SI 4 ""))]
4336 "TARGET_POWER && reload_completed"
4337 [(parallel [(set (match_dup 0)
4338 (ashift:SI (match_dup 1) (match_dup 2)))
4339 (clobber (match_dup 4))])
4340 (set (match_dup 3)
4341 (compare:CC (match_dup 0)
4342 (const_int 0)))]
4343 "")
25c341fa 4344
ca7f5001 4345(define_insn ""
44cd321e
PS		 4346 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4347 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4348 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4349 (const_int 0)))
44cd321e 4350 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 4351 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4352 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4353 "@
44cd321e
PS		 4354 {sl.|slw.} %0,%1,%2
4355 {sli.|slwi.} %0,%1,%h2
4356 #
9ebbca7d 4357 #"
44cd321e
PS		 4358 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4359 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4360
4361(define_split
4362 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4363 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4364 (match_operand:SI 2 "reg_or_cint_operand" ""))
4365 (const_int 0)))
4366 (set (match_operand:SI 0 "gpc_reg_operand" "")
4367 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4368 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4369 [(set (match_dup 0)
4370 (ashift:SI (match_dup 1) (match_dup 2)))
4371 (set (match_dup 3)
4372 (compare:CC (match_dup 0)
4373 (const_int 0)))]
4374 "")
1fd4e8c1 4375
915167f5 4376(define_insn "rlwinm"
cd2b37d9
RK		 4377 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4378 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4379 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4380 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4381 "includes_lshift_p (operands[2], operands[3])"
d56d506a 4382 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
1fd4e8c1
RK		 4383
4384(define_insn ""
9ebbca7d 4385 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4386 (compare:CC
9ebbca7d
GK		 4387 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4388 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4389 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4390 (const_int 0)))
9ebbca7d 4391 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4392 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4393 "@
4394 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4395 #"
4396 [(set_attr "type" "delayed_compare")
4397 (set_attr "length" "4,8")])
4398
4399(define_split
4400 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4401 (compare:CC
4402 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4403 (match_operand:SI 2 "const_int_operand" ""))
4404 (match_operand:SI 3 "mask_operand" ""))
4405 (const_int 0)))
4406 (clobber (match_scratch:SI 4 ""))]
ce71f754 4407 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4408 [(set (match_dup 4)
4409 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4410 (match_dup 3)))
4411 (set (match_dup 0)
4412 (compare:CC (match_dup 4)
4413 (const_int 0)))]
4414 "")
1fd4e8c1
RK		 4415
4416(define_insn ""
9ebbca7d 4417 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4418 (compare:CC
9ebbca7d
GK		 4419 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4420 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4421 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4422 (const_int 0)))
9ebbca7d 4423 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4424 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4425 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4426 "@
4427 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4428 #"
4429 [(set_attr "type" "delayed_compare")
4430 (set_attr "length" "4,8")])
4431
4432(define_split
4433 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4434 (compare:CC
4435 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4436 (match_operand:SI 2 "const_int_operand" ""))
4437 (match_operand:SI 3 "mask_operand" ""))
4438 (const_int 0)))
4439 (set (match_operand:SI 0 "gpc_reg_operand" "")
4440 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4441 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4442 [(set (match_dup 0)
4443 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4444 (set (match_dup 4)
4445 (compare:CC (match_dup 0)
4446 (const_int 0)))]
4447 "")
1fd4e8c1 4448
ca7f5001 4449;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5c23c401 4450;; "sli x,x,0".
ca7f5001
RK		 4451(define_expand "lshrsi3"
4452 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4453 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4454 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4455 ""
4456 "
4457{
4458 if (TARGET_POWER)
4459 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4460 else
25c341fa 4461 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4462 DONE;
4463}")
4464
4465(define_insn "lshrsi3_power"
bdf423cb
MM		 4466 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4467 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4468 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4469 (clobber (match_scratch:SI 3 "=q,X,X"))]
ca7f5001 4470 "TARGET_POWER"
1fd4e8c1
RK		 4471 "@
4472 sre %0,%1,%2
bdf423cb 4473 mr %0,%1
ca7f5001
RK		 4474 {s%A2i|s%A2wi} %0,%1,%h2")
4475
25c341fa 4476(define_insn "lshrsi3_no_power"
44cd321e
PS		 4477 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4478 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4479 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
25c341fa 4480 "! TARGET_POWER"
bdf423cb
MM		 4481 "@
4482 mr %0,%1
44cd321e
PS		 4483 {sr|srw} %0,%1,%2
4484 {sri|srwi} %0,%1,%h2"
4485 [(set_attr "type" "integer,var_shift_rotate,shift")])
1fd4e8c1
RK		 4486
4487(define_insn ""
9ebbca7d
GK		 4488 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4489 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4490 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4491 (const_int 0)))
9ebbca7d
GK		 4492 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4493 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4494 "TARGET_POWER"
1fd4e8c1 4495 "@
29ae5b89
JL		 4496 sre. %3,%1,%2
4497 mr. %1,%1
9ebbca7d
GK		 4498 {s%A2i.|s%A2wi.} %3,%1,%h2
4499 #
4500 #
4501 #"
4502 [(set_attr "type" "delayed_compare")
4503 (set_attr "length" "4,4,4,8,8,8")])
4504
4505(define_split
4506 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4507 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4508 (match_operand:SI 2 "reg_or_cint_operand" ""))
4509 (const_int 0)))
4510 (clobber (match_scratch:SI 3 ""))
4511 (clobber (match_scratch:SI 4 ""))]
4512 "TARGET_POWER && reload_completed"
4513 [(parallel [(set (match_dup 3)
4514 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4515 (clobber (match_dup 4))])
4516 (set (match_dup 0)
4517 (compare:CC (match_dup 3)
4518 (const_int 0)))]
4519 "")
ca7f5001
RK		 4520
4521(define_insn ""
44cd321e
PS		 4522 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4523 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4524 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
ca7f5001 4525 (const_int 0)))
44cd321e 4526 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4b8a63d6 4527 "! TARGET_POWER && TARGET_32BIT"
bdf423cb
MM		 4528 "@
4529 mr. %1,%1
44cd321e
PS		 4530 {sr.|srw.} %3,%1,%2
4531 {sri.|srwi.} %3,%1,%h2
4532 #
9ebbca7d
GK		 4533 #
4534 #"
44cd321e
PS		 4535 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4536 (set_attr "length" "4,4,4,8,8,8")])
1fd4e8c1 4537
9ebbca7d
GK		 4538(define_split
4539 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4540 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4541 (match_operand:SI 2 "reg_or_cint_operand" ""))
4542 (const_int 0)))
4543 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4544 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4545 [(set (match_dup 3)
4546 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4547 (set (match_dup 0)
4548 (compare:CC (match_dup 3)
4549 (const_int 0)))]
4550 "")
4551
4552(define_insn ""
4553 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4554 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4555 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4556 (const_int 0)))
9ebbca7d 4557 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
1fd4e8c1 4558 (lshiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4559 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4560 "TARGET_POWER"
1fd4e8c1 4561 "@
29ae5b89
JL		 4562 sre. %0,%1,%2
4563 mr. %0,%1
9ebbca7d
GK		 4564 {s%A2i.|s%A2wi.} %0,%1,%h2
4565 #
4566 #
4567 #"
4568 [(set_attr "type" "delayed_compare")
4569 (set_attr "length" "4,4,4,8,8,8")])
4570
4571(define_split
4572 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4573 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4574 (match_operand:SI 2 "reg_or_cint_operand" ""))
4575 (const_int 0)))
4576 (set (match_operand:SI 0 "gpc_reg_operand" "")
4577 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4578 (clobber (match_scratch:SI 4 ""))]
4579 "TARGET_POWER && reload_completed"
4580 [(parallel [(set (match_dup 0)
4581 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4582 (clobber (match_dup 4))])
4583 (set (match_dup 3)
4584 (compare:CC (match_dup 0)
4585 (const_int 0)))]
4586 "")
ca7f5001
RK		 4587
4588(define_insn ""
44cd321e
PS		 4589 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4590 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4591 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
815cdc52 4592 (const_int 0)))
44cd321e 4593 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
29ae5b89 4594 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4595 "! TARGET_POWER && TARGET_32BIT"
29ae5b89
JL		 4596 "@
4597 mr. %0,%1
44cd321e
PS		 4598 {sr.|srw.} %0,%1,%2
4599 {sri.|srwi.} %0,%1,%h2
4600 #
9ebbca7d
GK		 4601 #
4602 #"
44cd321e
PS		 4603 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4604 (set_attr "length" "4,4,4,8,8,8")])
9ebbca7d
GK		 4605
4606(define_split
4607 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4608 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4609 (match_operand:SI 2 "reg_or_cint_operand" ""))
4610 (const_int 0)))
4611 (set (match_operand:SI 0 "gpc_reg_operand" "")
4612 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4613 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4614 [(set (match_dup 0)
4615 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4616 (set (match_dup 3)
4617 (compare:CC (match_dup 0)
4618 (const_int 0)))]
4619 "")
1fd4e8c1
RK		 4620
4621(define_insn ""
cd2b37d9
RK		 4622 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4623 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4624 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4625 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4626 "includes_rshift_p (operands[2], operands[3])"
ca7f5001 4627 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
1fd4e8c1
RK		 4628
4629(define_insn ""
9ebbca7d 4630 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4631 (compare:CC
9ebbca7d
GK		 4632 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4633 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4634 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4635 (const_int 0)))
9ebbca7d 4636 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4637 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4638 "@
4639 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4640 #"
4641 [(set_attr "type" "delayed_compare")
4642 (set_attr "length" "4,8")])
4643
4644(define_split
4645 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4646 (compare:CC
4647 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4648 (match_operand:SI 2 "const_int_operand" ""))
4649 (match_operand:SI 3 "mask_operand" ""))
4650 (const_int 0)))
4651 (clobber (match_scratch:SI 4 ""))]
ce71f754 4652 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4653 [(set (match_dup 4)
4654 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4655 (match_dup 3)))
4656 (set (match_dup 0)
4657 (compare:CC (match_dup 4)
4658 (const_int 0)))]
4659 "")
1fd4e8c1
RK		 4660
4661(define_insn ""
9ebbca7d 4662 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4663 (compare:CC
9ebbca7d
GK		 4664 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4665 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4666 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4667 (const_int 0)))
9ebbca7d 4668 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4669 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4670 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4671 "@
4672 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4673 #"
4674 [(set_attr "type" "delayed_compare")
4675 (set_attr "length" "4,8")])
4676
4677(define_split
4678 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4679 (compare:CC
4680 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4681 (match_operand:SI 2 "const_int_operand" ""))
4682 (match_operand:SI 3 "mask_operand" ""))
4683 (const_int 0)))
4684 (set (match_operand:SI 0 "gpc_reg_operand" "")
4685 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4686 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4687 [(set (match_dup 0)
4688 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4689 (set (match_dup 4)
4690 (compare:CC (match_dup 0)
4691 (const_int 0)))]
4692 "")
1fd4e8c1
RK		 4693
4694(define_insn ""
cd2b37d9 4695 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4696 (zero_extend:SI
4697 (subreg:QI
cd2b37d9 4698 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4699 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4700 "includes_rshift_p (operands[2], GEN_INT (255))"
ca7f5001 4701 "{rlinm|rlwinm} %0,%1,%s2,0xff")
1fd4e8c1
RK		 4702
4703(define_insn ""
9ebbca7d 4704 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4705 (compare:CC
4706 (zero_extend:SI
4707 (subreg:QI
9ebbca7d
GK		 4708 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4709 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4710 (const_int 0)))
9ebbca7d 4711 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4712 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4713 "@
4714 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4715 #"
4716 [(set_attr "type" "delayed_compare")
4717 (set_attr "length" "4,8")])
4718
4719(define_split
4720 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4721 (compare:CC
4722 (zero_extend:SI
4723 (subreg:QI
4724 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4725 (match_operand:SI 2 "const_int_operand" "")) 0))
4726 (const_int 0)))
4727 (clobber (match_scratch:SI 3 ""))]
4728 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4729 [(set (match_dup 3)
4730 (zero_extend:SI (subreg:QI
4731 (lshiftrt:SI (match_dup 1)
4732 (match_dup 2)) 0)))
4733 (set (match_dup 0)
4734 (compare:CC (match_dup 3)
4735 (const_int 0)))]
4736 "")
1fd4e8c1
RK		 4737
4738(define_insn ""
9ebbca7d 4739 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4740 (compare:CC
4741 (zero_extend:SI
4742 (subreg:QI
9ebbca7d
GK		 4743 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4744 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4745 (const_int 0)))
9ebbca7d 4746 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4747 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4748 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4749 "@
4750 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4751 #"
4752 [(set_attr "type" "delayed_compare")
4753 (set_attr "length" "4,8")])
4754
4755(define_split
4756 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4757 (compare:CC
4758 (zero_extend:SI
4759 (subreg:QI
4760 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4761 (match_operand:SI 2 "const_int_operand" "")) 0))
4762 (const_int 0)))
4763 (set (match_operand:SI 0 "gpc_reg_operand" "")
4764 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4765 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4766 [(set (match_dup 0)
4767 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4768 (set (match_dup 3)
4769 (compare:CC (match_dup 0)
4770 (const_int 0)))]
4771 "")
1fd4e8c1
RK		 4772
4773(define_insn ""
cd2b37d9 4774 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4775 (zero_extend:SI
4776 (subreg:HI
cd2b37d9 4777 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4778 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4779 "includes_rshift_p (operands[2], GEN_INT (65535))"
ca7f5001 4780 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
1fd4e8c1
RK		 4781
4782(define_insn ""
9ebbca7d 4783 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4784 (compare:CC
4785 (zero_extend:SI
4786 (subreg:HI
9ebbca7d
GK		 4787 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4788 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4789 (const_int 0)))
9ebbca7d 4790 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4791 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4792 "@
4793 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4794 #"
4795 [(set_attr "type" "delayed_compare")
4796 (set_attr "length" "4,8")])
4797
4798(define_split
4799 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4800 (compare:CC
4801 (zero_extend:SI
4802 (subreg:HI
4803 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4804 (match_operand:SI 2 "const_int_operand" "")) 0))
4805 (const_int 0)))
4806 (clobber (match_scratch:SI 3 ""))]
4807 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4808 [(set (match_dup 3)
4809 (zero_extend:SI (subreg:HI
4810 (lshiftrt:SI (match_dup 1)
4811 (match_dup 2)) 0)))
4812 (set (match_dup 0)
4813 (compare:CC (match_dup 3)
4814 (const_int 0)))]
4815 "")
1fd4e8c1
RK		 4816
4817(define_insn ""
9ebbca7d 4818 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4819 (compare:CC
4820 (zero_extend:SI
4821 (subreg:HI
9ebbca7d
GK		 4822 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4823 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4824 (const_int 0)))
9ebbca7d 4825 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4826 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4827 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4828 "@
4829 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4830 #"
4831 [(set_attr "type" "delayed_compare")
4832 (set_attr "length" "4,8")])
4833
4834(define_split
4835 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4836 (compare:CC
4837 (zero_extend:SI
4838 (subreg:HI
4839 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4840 (match_operand:SI 2 "const_int_operand" "")) 0))
4841 (const_int 0)))
4842 (set (match_operand:SI 0 "gpc_reg_operand" "")
4843 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4844 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4845 [(set (match_dup 0)
4846 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4847 (set (match_dup 3)
4848 (compare:CC (match_dup 0)
4849 (const_int 0)))]
4850 "")
1fd4e8c1
RK		 4851
4852(define_insn ""
cd2b37d9 4853 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4854 (const_int 1)
cd2b37d9
RK		 4855 (match_operand:SI 1 "gpc_reg_operand" "r"))
4856 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4857 (const_int 31)))]
ca7f5001 4858 "TARGET_POWER"
1fd4e8c1
RK		 4859 "rrib %0,%1,%2")
4860
4861(define_insn ""
cd2b37d9 4862 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4863 (const_int 1)
cd2b37d9
RK		 4864 (match_operand:SI 1 "gpc_reg_operand" "r"))
4865 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4866 (const_int 31)))]
ca7f5001 4867 "TARGET_POWER"
1fd4e8c1
RK		 4868 "rrib %0,%1,%2")
4869
4870(define_insn ""
cd2b37d9 4871 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4872 (const_int 1)
cd2b37d9
RK		 4873 (match_operand:SI 1 "gpc_reg_operand" "r"))
4874 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4875 (const_int 1)
4876 (const_int 0)))]
ca7f5001 4877 "TARGET_POWER"
1fd4e8c1
RK		 4878 "rrib %0,%1,%2")
4879
ca7f5001
RK		 4880(define_expand "ashrsi3"
4881 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4882 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4883 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4884 ""
4885 "
4886{
4887 if (TARGET_POWER)
4888 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4889 else
25c341fa 4890 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4891 DONE;
4892}")
4893
4894(define_insn "ashrsi3_power"
cd2b37d9
RK		 4895 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4896 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4897 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4898 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4899 "TARGET_POWER"
1fd4e8c1
RK		 4900 "@
4901 srea %0,%1,%2
44cd321e
PS		 4902 {srai|srawi} %0,%1,%h2"
4903 [(set_attr "type" "shift")])
ca7f5001 4904
25c341fa 4905(define_insn "ashrsi3_no_power"
44cd321e
PS		 4906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4907 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4908 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4909 "! TARGET_POWER"
44cd321e
PS		 4910 "@
4911 {sra|sraw} %0,%1,%2
4912 {srai|srawi} %0,%1,%h2"
4913 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 4914
4915(define_insn ""
9ebbca7d
GK		 4916 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4917 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4918 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4919 (const_int 0)))
9ebbca7d
GK		 4920 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4921 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4922 "TARGET_POWER"
1fd4e8c1
RK		 4923 "@
4924 srea. %3,%1,%2
9ebbca7d
GK		 4925 {srai.|srawi.} %3,%1,%h2
4926 #
4927 #"
4928 [(set_attr "type" "delayed_compare")
4929 (set_attr "length" "4,4,8,8")])
4930
4931(define_split
4932 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4933 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4934 (match_operand:SI 2 "reg_or_cint_operand" ""))
4935 (const_int 0)))
4936 (clobber (match_scratch:SI 3 ""))
4937 (clobber (match_scratch:SI 4 ""))]
4938 "TARGET_POWER && reload_completed"
4939 [(parallel [(set (match_dup 3)
4940 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4941 (clobber (match_dup 4))])
4942 (set (match_dup 0)
4943 (compare:CC (match_dup 3)
4944 (const_int 0)))]
4945 "")
ca7f5001
RK		 4946
4947(define_insn ""
44cd321e
PS		 4948 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4949 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4950 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4951 (const_int 0)))
44cd321e 4952 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
25c341fa 4953 "! TARGET_POWER"
9ebbca7d 4954 "@
44cd321e
PS		 4955 {sra.|sraw.} %3,%1,%2
4956 {srai.|srawi.} %3,%1,%h2
4957 #
9ebbca7d 4958 #"
44cd321e
PS		 4959 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4960 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4961
4962(define_split
4963 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4964 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4965 (match_operand:SI 2 "reg_or_cint_operand" ""))
4966 (const_int 0)))
4967 (clobber (match_scratch:SI 3 ""))]
4968 "! TARGET_POWER && reload_completed"
4969 [(set (match_dup 3)
4970 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4971 (set (match_dup 0)
4972 (compare:CC (match_dup 3)
4973 (const_int 0)))]
4974 "")
1fd4e8c1
RK		 4975
4976(define_insn ""
9ebbca7d
GK		 4977 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4978 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4979 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4980 (const_int 0)))
9ebbca7d 4981 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4982 (ashiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4983 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4984 "TARGET_POWER"
1fd4e8c1
RK		 4985 "@
4986 srea. %0,%1,%2
9ebbca7d
GK		 4987 {srai.|srawi.} %0,%1,%h2
4988 #
4989 #"
4990 [(set_attr "type" "delayed_compare")
4991 (set_attr "length" "4,4,8,8")])
4992
4993(define_split
4994 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4995 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4996 (match_operand:SI 2 "reg_or_cint_operand" ""))
4997 (const_int 0)))
4998 (set (match_operand:SI 0 "gpc_reg_operand" "")
4999 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5000 (clobber (match_scratch:SI 4 ""))]
5001 "TARGET_POWER && reload_completed"
5002 [(parallel [(set (match_dup 0)
5003 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5004 (clobber (match_dup 4))])
5005 (set (match_dup 3)
5006 (compare:CC (match_dup 0)
5007 (const_int 0)))]
5008 "")
1fd4e8c1 5009
ca7f5001 5010(define_insn ""
44cd321e
PS		 5011 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5012 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5013 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 5014 (const_int 0)))
44cd321e 5015 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 5016 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
25c341fa 5017 "! TARGET_POWER"
9ebbca7d 5018 "@
44cd321e
PS		 5019 {sra.|sraw.} %0,%1,%2
5020 {srai.|srawi.} %0,%1,%h2
5021 #
9ebbca7d 5022 #"
44cd321e
PS		 5023 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5024 (set_attr "length" "4,4,8,8")])
1fd4e8c1 5025\f
9ebbca7d
GK		 5026(define_split
5027 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5028 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5029 (match_operand:SI 2 "reg_or_cint_operand" ""))
5030 (const_int 0)))
5031 (set (match_operand:SI 0 "gpc_reg_operand" "")
5032 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5033 "! TARGET_POWER && reload_completed"
5034 [(set (match_dup 0)
5035 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5036 (set (match_dup 3)
5037 (compare:CC (match_dup 0)
5038 (const_int 0)))]
5039 "")
5040
1fd4e8c1
RK		 5041;; Floating-point insns, excluding normal data motion.
5042;;
ca7f5001
RK		 5043;; PowerPC has a full set of single-precision floating point instructions.
5044;;
5045;; For the POWER architecture, we pretend that we have both SFmode and
5046;; DFmode insns, while, in fact, all fp insns are actually done in double.
5047;; The only conversions we will do will be when storing to memory. In that
5048;; case, we will use the "frsp" instruction before storing.
1fd4e8c1
RK		 5049;;
5050;; Note that when we store into a single-precision memory location, we need to
5051;; use the frsp insn first. If the register being stored isn't dead, we
5052;; need a scratch register for the frsp. But this is difficult when the store
5053;; is done by reload. It is not incorrect to do the frsp on the register in
5054;; this case, we just lose precision that we would have otherwise gotten but
5055;; is not guaranteed. Perhaps this should be tightened up at some point.
5056
99176a91
AH		 5057(define_expand "extendsfdf2"
5058 [(set (match_operand:DF 0 "gpc_reg_operand" "")
97c54d9a 5059 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
99176a91
AH		 5060 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5061 "")
5062
5063(define_insn_and_split "*extendsfdf2_fpr"
97c54d9a
DE		 5064 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5065 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
a3170dc6 5066 "TARGET_HARD_FLOAT && TARGET_FPRS"
11ac38b2
DE		 5067 "@
5068 #
97c54d9a
DE		 5069 fmr %0,%1
5070 lfs%U1%X1 %0,%1"
d7b1468b 5071 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
11ac38b2 5072 [(const_int 0)]
5c30aff8 5073{
11ac38b2
DE		 5074 emit_note (NOTE_INSN_DELETED);
5075 DONE;
5076}
97c54d9a 5077 [(set_attr "type" "fp,fp,fpload")])
1fd4e8c1 5078
7a2f7870
AH		 5079(define_expand "truncdfsf2"
5080 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5081 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5082 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5083 "")
5084
99176a91 5085(define_insn "*truncdfsf2_fpr"
cd2b37d9
RK		 5086 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5087 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5088 "TARGET_HARD_FLOAT && TARGET_FPRS"
dcac138d 5089 "frsp %0,%1"
1fd4e8c1
RK		 5090 [(set_attr "type" "fp")])
5091
455350f4
RK		 5092(define_insn "aux_truncdfsf2"
5093 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
615158e2 5094 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
a3170dc6 5095 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
455350f4
RK		 5096 "frsp %0,%1"
5097 [(set_attr "type" "fp")])
5098
a3170dc6
AH		 5099(define_expand "negsf2"
5100 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5101 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5102 "TARGET_HARD_FLOAT"
5103 "")
5104
5105(define_insn "*negsf2"
cd2b37d9
RK		 5106 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5107 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5108 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5109 "fneg %0,%1"
5110 [(set_attr "type" "fp")])
5111
a3170dc6
AH		 5112(define_expand "abssf2"
5113 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5114 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5115 "TARGET_HARD_FLOAT"
5116 "")
5117
5118(define_insn "*abssf2"
cd2b37d9
RK		 5119 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5120 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5121 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5122 "fabs %0,%1"
5123 [(set_attr "type" "fp")])
5124
5125(define_insn ""
cd2b37d9
RK		 5126 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5127 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
a3170dc6 5128 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5129 "fnabs %0,%1"
5130 [(set_attr "type" "fp")])
5131
ca7f5001
RK		 5132(define_expand "addsf3"
5133 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5134 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5135 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5136 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5137 "")
5138
5139(define_insn ""
cd2b37d9
RK		 5140 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5141 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5142 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5143 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5144 "fadds %0,%1,%2"
ca7f5001
RK		 5145 [(set_attr "type" "fp")])
5146
5147(define_insn ""
5148 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5149 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5150 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5151 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5152 "{fa|fadd} %0,%1,%2"
ca7f5001
RK		 5153 [(set_attr "type" "fp")])
5154
5155(define_expand "subsf3"
5156 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5157 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5158 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5159 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5160 "")
5161
5162(define_insn ""
5163 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5164 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5165 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5166 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5167 "fsubs %0,%1,%2"
1fd4e8c1
RK		 5168 [(set_attr "type" "fp")])
5169
ca7f5001 5170(define_insn ""
cd2b37d9
RK		 5171 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5172 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5173 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5174 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5175 "{fs|fsub} %0,%1,%2"
ca7f5001
RK		 5176 [(set_attr "type" "fp")])
5177
5178(define_expand "mulsf3"
5179 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5180 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5181 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5182 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5183 "")
5184
5185(define_insn ""
5186 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5187 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5188 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5189 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5190 "fmuls %0,%1,%2"
1fd4e8c1
RK		 5191 [(set_attr "type" "fp")])
5192
ca7f5001 5193(define_insn ""
cd2b37d9
RK		 5194 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5195 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5196 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5197 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5198 "{fm|fmul} %0,%1,%2"
0780f386 5199 [(set_attr "type" "dmul")])
1fd4e8c1 5200
ca7f5001
RK		 5201(define_expand "divsf3"
5202 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5203 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5204 (match_operand:SF 2 "gpc_reg_operand" "")))]
d14a6d05 5205 "TARGET_HARD_FLOAT"
9c78b944 5206 "")
ca7f5001
RK		 5207
5208(define_insn ""
cd2b37d9
RK		 5209 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5210 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5211 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5212 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5213 "fdivs %0,%1,%2"
ca7f5001
RK		 5214 [(set_attr "type" "sdiv")])
5215
5216(define_insn ""
5217 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5218 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5219 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 5220 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5221 "{fd|fdiv} %0,%1,%2"
0780f386 5222 [(set_attr "type" "ddiv")])
1fd4e8c1 5223
9c78b944
DE		 5224(define_expand "recipsf3"
5225 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5226 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5227 (match_operand:SF 2 "gpc_reg_operand" "f")]
5228 UNSPEC_FRES))]
5229 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5230 && flag_finite_math_only && !flag_trapping_math"
5231{
5232 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5233 DONE;
5234})
5235
5236(define_insn "fres"
5237 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5238 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5239 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5240 "fres %0,%1"
5241 [(set_attr "type" "fp")])
5242
1fd4e8c1 5243(define_insn ""
cd2b37d9
RK		 5244 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5245 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5246 (match_operand:SF 2 "gpc_reg_operand" "f"))
5247 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5248 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5249 "fmadds %0,%1,%2,%3"
ca7f5001
RK		 5250 [(set_attr "type" "fp")])
5251
5252(define_insn ""
5253 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5254 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5255 (match_operand:SF 2 "gpc_reg_operand" "f"))
5256 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5257 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5258 "{fma|fmadd} %0,%1,%2,%3"
cf27b467 5259 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5260
5261(define_insn ""
cd2b37d9
RK		 5262 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5263 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5264 (match_operand:SF 2 "gpc_reg_operand" "f"))
5265 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5266 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5267 "fmsubs %0,%1,%2,%3"
ca7f5001
RK		 5268 [(set_attr "type" "fp")])
5269
5270(define_insn ""
5271 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5272 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5273 (match_operand:SF 2 "gpc_reg_operand" "f"))
5274 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5275 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5276 "{fms|fmsub} %0,%1,%2,%3"
cf27b467 5277 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5278
5279(define_insn ""
cd2b37d9
RK		 5280 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5281 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5282 (match_operand:SF 2 "gpc_reg_operand" "f"))
5283 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5284 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5285 && HONOR_SIGNED_ZEROS (SFmode)"
5286 "fnmadds %0,%1,%2,%3"
5287 [(set_attr "type" "fp")])
5288
5289(define_insn ""
5290 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5291 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5292 (match_operand:SF 2 "gpc_reg_operand" "f"))
5293 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5294 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5295 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5296 "fnmadds %0,%1,%2,%3"
ca7f5001
RK		 5297 [(set_attr "type" "fp")])
5298
5299(define_insn ""
5300 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5301 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5302 (match_operand:SF 2 "gpc_reg_operand" "f"))
5303 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 5304 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5305 "{fnma|fnmadd} %0,%1,%2,%3"
cf27b467 5306 [(set_attr "type" "dmul")])
1fd4e8c1 5307
16823694
GK		 5308(define_insn ""
5309 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5310 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5311 (match_operand:SF 2 "gpc_reg_operand" "f"))
5312 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5313 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5314 && ! HONOR_SIGNED_ZEROS (SFmode)"
5315 "{fnma|fnmadd} %0,%1,%2,%3"
5316 [(set_attr "type" "dmul")])
5317
1fd4e8c1 5318(define_insn ""
cd2b37d9
RK		 5319 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5320 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5321 (match_operand:SF 2 "gpc_reg_operand" "f"))
5322 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5323 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5324 && HONOR_SIGNED_ZEROS (SFmode)"
5325 "fnmsubs %0,%1,%2,%3"
5326 [(set_attr "type" "fp")])
5327
5328(define_insn ""
5329 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5330 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5331 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5332 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5333 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5334 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5335 "fnmsubs %0,%1,%2,%3"
ca7f5001
RK		 5336 [(set_attr "type" "fp")])
5337
5338(define_insn ""
5339 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5340 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5341 (match_operand:SF 2 "gpc_reg_operand" "f"))
5342 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
a3170dc6 5343 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5344 "{fnms|fnmsub} %0,%1,%2,%3"
cf27b467 5345 [(set_attr "type" "dmul")])
1fd4e8c1 5346
16823694
GK		 5347(define_insn ""
5348 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5349 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5350 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5351 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5352 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5353 && ! HONOR_SIGNED_ZEROS (SFmode)"
5354 "{fnms|fnmsub} %0,%1,%2,%3"
9c6fdb46 5355 [(set_attr "type" "dmul")])
16823694 5356
ca7f5001
RK		 5357(define_expand "sqrtsf2"
5358 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5359 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
a3170dc6 5360 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5361 "")
5362
5363(define_insn ""
5364 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5365 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5366 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5367 "fsqrts %0,%1"
5368 [(set_attr "type" "ssqrt")])
5369
5370(define_insn ""
5371 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5372 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
a3170dc6 5373 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5374 "fsqrt %0,%1"
5375 [(set_attr "type" "dsqrt")])
5376
9c78b944
DE		 5377(define_expand "rsqrtsf2"
5378 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5379 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5380 UNSPEC_RSQRT))]
5381 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5382 && flag_finite_math_only && !flag_trapping_math"
5383{
5384 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5385 DONE;
5386})
5387
5388(define_insn "*rsqrt_internal1"
5389 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5390 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5391 UNSPEC_RSQRT))]
5392 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5393 "frsqrte %0,%1"
5394 [(set_attr "type" "fp")])
5395
0530bc70
AP		 5396(define_expand "copysignsf3"
5397 [(set (match_dup 3)
5398 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5399 (set (match_dup 4)
5400 (neg:SF (abs:SF (match_dup 1))))
5401 (set (match_operand:SF 0 "gpc_reg_operand" "")
5402 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5403 (match_dup 5))
5404 (match_dup 3)
5405 (match_dup 4)))]
5406 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
bb8df8a6 5407 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
0530bc70
AP		 5408 {
5409 operands[3] = gen_reg_rtx (SFmode);
5410 operands[4] = gen_reg_rtx (SFmode);
5411 operands[5] = CONST0_RTX (SFmode);
5412 })
5413
5414(define_expand "copysigndf3"
5415 [(set (match_dup 3)
5416 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5417 (set (match_dup 4)
5418 (neg:DF (abs:DF (match_dup 1))))
5419 (set (match_operand:DF 0 "gpc_reg_operand" "")
5420 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5421 (match_dup 5))
5422 (match_dup 3)
5423 (match_dup 4)))]
5424 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5425 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5426 {
5427 operands[3] = gen_reg_rtx (DFmode);
5428 operands[4] = gen_reg_rtx (DFmode);
5429 operands[5] = CONST0_RTX (DFmode);
5430 })
5431
94d7001a
RK		 5432;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5433;; fsel instruction and some auxiliary computations. Then we just have a
5434;; single DEFINE_INSN for fsel and the define_splits to make them if made by
8e871c05 5435;; combine.
7ae4d8d4 5436(define_expand "smaxsf3"
8e871c05 5437 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5438 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5439 (match_operand:SF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5440 (match_dup 1)
5441 (match_dup 2)))]
89e73849 5442 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5443 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
2f607b94 5444
7ae4d8d4 5445(define_expand "sminsf3"
50a0b056
GK		 5446 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5447 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5448 (match_operand:SF 2 "gpc_reg_operand" ""))
5449 (match_dup 2)
5450 (match_dup 1)))]
89e73849 5451 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5452 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
2f607b94 5453
8e871c05
RK		 5454(define_split
5455 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5456 (match_operator:SF 3 "min_max_operator"
5457 [(match_operand:SF 1 "gpc_reg_operand" "")
5458 (match_operand:SF 2 "gpc_reg_operand" "")]))]
89e73849 5459 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056
GK		 5460 [(const_int 0)]
5461 "
6ae08853 5462{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5463 operands[1], operands[2]);
5464 DONE;
5465}")
2f607b94 5466
a3170dc6
AH		 5467(define_expand "movsicc"
5468 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5469 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5470 (match_operand:SI 2 "gpc_reg_operand" "")
5471 (match_operand:SI 3 "gpc_reg_operand" "")))]
5472 "TARGET_ISEL"
5473 "
5474{
5475 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5476 DONE;
5477 else
5478 FAIL;
5479}")
5480
5481;; We use the BASE_REGS for the isel input operands because, if rA is
5482;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5483;; because we may switch the operands and rB may end up being rA.
5484;;
5485;; We need 2 patterns: an unsigned and a signed pattern. We could
5486;; leave out the mode in operand 4 and use one pattern, but reload can
5487;; change the mode underneath our feet and then gets confused trying
5488;; to reload the value.
5489(define_insn "isel_signed"
5490 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5491 (if_then_else:SI
5492 (match_operator 1 "comparison_operator"
5493 [(match_operand:CC 4 "cc_reg_operand" "y")
5494 (const_int 0)])
5495 (match_operand:SI 2 "gpc_reg_operand" "b")
5496 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5497 "TARGET_ISEL"
5498 "*
5499{ return output_isel (operands); }"
5500 [(set_attr "length" "4")])
5501
5502(define_insn "isel_unsigned"
5503 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5504 (if_then_else:SI
5505 (match_operator 1 "comparison_operator"
5506 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5507 (const_int 0)])
5508 (match_operand:SI 2 "gpc_reg_operand" "b")
5509 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5510 "TARGET_ISEL"
5511 "*
5512{ return output_isel (operands); }"
5513 [(set_attr "length" "4")])
5514
94d7001a 5515(define_expand "movsfcc"
0ad91047 5516 [(set (match_operand:SF 0 "gpc_reg_operand" "")
94d7001a 5517 (if_then_else:SF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5518 (match_operand:SF 2 "gpc_reg_operand" "")
5519 (match_operand:SF 3 "gpc_reg_operand" "")))]
a3170dc6 5520 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5521 "
5522{
50a0b056
GK		 5523 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5524 DONE;
94d7001a 5525 else
50a0b056 5526 FAIL;
94d7001a 5527}")
d56d506a 5528
50a0b056 5529(define_insn "*fselsfsf4"
8e871c05
RK		 5530 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5531 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5532 (match_operand:SF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5533 (match_operand:SF 2 "gpc_reg_operand" "f")
5534 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5535 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 5536 "fsel %0,%1,%2,%3"
5537 [(set_attr "type" "fp")])
2f607b94 5538
50a0b056 5539(define_insn "*fseldfsf4"
94d7001a
RK		 5540 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5541 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
d365ba42 5542 (match_operand:DF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5543 (match_operand:SF 2 "gpc_reg_operand" "f")
5544 (match_operand:SF 3 "gpc_reg_operand" "f")))]
a3170dc6 5545 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5546 "fsel %0,%1,%2,%3"
5547 [(set_attr "type" "fp")])
d56d506a 5548
7a2f7870
AH		 5549(define_expand "negdf2"
5550 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5551 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5552 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5553 "")
5554
99176a91 5555(define_insn "*negdf2_fpr"
cd2b37d9
RK		 5556 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5557 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5558 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5559 "fneg %0,%1"
5560 [(set_attr "type" "fp")])
5561
7a2f7870
AH		 5562(define_expand "absdf2"
5563 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5564 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5565 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5566 "")
5567
99176a91 5568(define_insn "*absdf2_fpr"
cd2b37d9
RK		 5569 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5570 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5571 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5572 "fabs %0,%1"
5573 [(set_attr "type" "fp")])
5574
99176a91 5575(define_insn "*nabsdf2_fpr"
cd2b37d9
RK		 5576 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5577 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
a3170dc6 5578 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5579 "fnabs %0,%1"
5580 [(set_attr "type" "fp")])
5581
7a2f7870
AH		 5582(define_expand "adddf3"
5583 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5584 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5585 (match_operand:DF 2 "gpc_reg_operand" "")))]
5586 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5587 "")
5588
99176a91 5589(define_insn "*adddf3_fpr"
cd2b37d9
RK		 5590 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5591 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5592 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5593 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5594 "{fa|fadd} %0,%1,%2"
1fd4e8c1
RK		 5595 [(set_attr "type" "fp")])
5596
7a2f7870
AH		 5597(define_expand "subdf3"
5598 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5599 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5600 (match_operand:DF 2 "gpc_reg_operand" "")))]
5601 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5602 "")
5603
99176a91 5604(define_insn "*subdf3_fpr"
cd2b37d9
RK		 5605 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5606 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5607 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5608 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5609 "{fs|fsub} %0,%1,%2"
1fd4e8c1
RK		 5610 [(set_attr "type" "fp")])
5611
7a2f7870
AH		 5612(define_expand "muldf3"
5613 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5614 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5615 (match_operand:DF 2 "gpc_reg_operand" "")))]
5616 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5617 "")
5618
99176a91 5619(define_insn "*muldf3_fpr"
cd2b37d9
RK		 5620 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5621 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5622 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5623 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5624 "{fm|fmul} %0,%1,%2"
cfb557c4 5625 [(set_attr "type" "dmul")])
1fd4e8c1 5626
7a2f7870
AH		 5627(define_expand "divdf3"
5628 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5629 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5630 (match_operand:DF 2 "gpc_reg_operand" "")))]
5631 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
9c78b944 5632 "")
7a2f7870 5633
99176a91 5634(define_insn "*divdf3_fpr"
cd2b37d9
RK		 5635 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5636 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5637 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 5638 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5639 "{fd|fdiv} %0,%1,%2"
cfb557c4 5640 [(set_attr "type" "ddiv")])
1fd4e8c1 5641
9c78b944
DE		 5642(define_expand "recipdf3"
5643 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5644 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")
5645 (match_operand:DF 2 "gpc_reg_operand" "f")]
5646 UNSPEC_FRES))]
5647 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
5648 && flag_finite_math_only && !flag_trapping_math"
5649{
5650 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5651 DONE;
5652})
5653
5654(define_insn "fred"
5655 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5656 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5657 "TARGET_POPCNTB && flag_finite_math_only"
5658 "fre %0,%1"
5659 [(set_attr "type" "fp")])
5660
1fd4e8c1 5661(define_insn ""
cd2b37d9
RK		 5662 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5663 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5664 (match_operand:DF 2 "gpc_reg_operand" "f"))
5665 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5666 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 5667 "{fma|fmadd} %0,%1,%2,%3"
cfb557c4 5668 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5669
5670(define_insn ""
cd2b37d9
RK		 5671 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5672 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5673 (match_operand:DF 2 "gpc_reg_operand" "f"))
5674 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5675 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 5676 "{fms|fmsub} %0,%1,%2,%3"
cfb557c4 5677 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5678
5679(define_insn ""
cd2b37d9
RK		 5680 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5681 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5682 (match_operand:DF 2 "gpc_reg_operand" "f"))
5683 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5684 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5685 && HONOR_SIGNED_ZEROS (DFmode)"
5686 "{fnma|fnmadd} %0,%1,%2,%3"
5687 [(set_attr "type" "dmul")])
5688
5689(define_insn ""
5690 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5691 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5692 (match_operand:DF 2 "gpc_reg_operand" "f"))
5693 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5694 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5695 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5696 "{fnma|fnmadd} %0,%1,%2,%3"
cfb557c4 5697 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5698
5699(define_insn ""
cd2b37d9
RK		 5700 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5701 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5702 (match_operand:DF 2 "gpc_reg_operand" "f"))
5703 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
16823694
GK		 5704 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5705 && HONOR_SIGNED_ZEROS (DFmode)"
5706 "{fnms|fnmsub} %0,%1,%2,%3"
5707 [(set_attr "type" "dmul")])
5708
5709(define_insn ""
5710 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5711 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5712 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5713 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
6ae08853 5714 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
16823694 5715 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5716 "{fnms|fnmsub} %0,%1,%2,%3"
cfb557c4 5717 [(set_attr "type" "dmul")])
ca7f5001
RK		 5718
5719(define_insn "sqrtdf2"
5720 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5721 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 5722 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5723 "fsqrt %0,%1"
5724 [(set_attr "type" "dsqrt")])
b77dfefc 5725
50a0b056 5726;; The conditional move instructions allow us to perform max and min
6ae08853 5727;; operations even when
b77dfefc 5728
7ae4d8d4 5729(define_expand "smaxdf3"
8e871c05 5730 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5731 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5732 (match_operand:DF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5733 (match_dup 1)
5734 (match_dup 2)))]
89e73849 5735 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5736 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
b77dfefc 5737
7ae4d8d4 5738(define_expand "smindf3"
50a0b056
GK		 5739 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5740 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5741 (match_operand:DF 2 "gpc_reg_operand" ""))
5742 (match_dup 2)
5743 (match_dup 1)))]
89e73849 5744 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5745 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
b77dfefc 5746
8e871c05
RK		 5747(define_split
5748 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5749 (match_operator:DF 3 "min_max_operator"
5750 [(match_operand:DF 1 "gpc_reg_operand" "")
5751 (match_operand:DF 2 "gpc_reg_operand" "")]))]
89e73849 5752 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056
GK		 5753 [(const_int 0)]
5754 "
6ae08853 5755{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5756 operands[1], operands[2]);
5757 DONE;
5758}")
b77dfefc 5759
94d7001a 5760(define_expand "movdfcc"
0ad91047 5761 [(set (match_operand:DF 0 "gpc_reg_operand" "")
94d7001a 5762 (if_then_else:DF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5763 (match_operand:DF 2 "gpc_reg_operand" "")
5764 (match_operand:DF 3 "gpc_reg_operand" "")))]
a3170dc6 5765 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5766 "
5767{
50a0b056
GK		 5768 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5769 DONE;
94d7001a 5770 else
50a0b056 5771 FAIL;
94d7001a 5772}")
d56d506a 5773
50a0b056 5774(define_insn "*fseldfdf4"
8e871c05
RK		 5775 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5776 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
50a0b056 5777 (match_operand:DF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5778 (match_operand:DF 2 "gpc_reg_operand" "f")
5779 (match_operand:DF 3 "gpc_reg_operand" "f")))]
a3170dc6 5780 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 5781 "fsel %0,%1,%2,%3"
5782 [(set_attr "type" "fp")])
d56d506a 5783
50a0b056 5784(define_insn "*fselsfdf4"
94d7001a
RK		 5785 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5786 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5787 (match_operand:SF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5788 (match_operand:DF 2 "gpc_reg_operand" "f")
5789 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5790 "TARGET_PPC_GFXOPT"
5791 "fsel %0,%1,%2,%3"
5792 [(set_attr "type" "fp")])
1fd4e8c1 5793\f
d095928f
AH		 5794;; Conversions to and from floating-point.
5795
5796(define_expand "fixuns_truncsfsi2"
5797 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5798 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5799 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5800 "")
5801
5802(define_expand "fix_truncsfsi2"
5803 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5804 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5805 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5806 "")
5807
9ebbca7d
GK		 5808; For each of these conversions, there is a define_expand, a define_insn
5809; with a '#' template, and a define_split (with C code). The idea is
5810; to allow constant folding with the template of the define_insn,
5811; then to have the insns split later (between sched1 and final).
5812
1fd4e8c1 5813(define_expand "floatsidf2"
802a0058
MM		 5814 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5815 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5816 (use (match_dup 2))
5817 (use (match_dup 3))
208c89ce 5818 (clobber (match_dup 4))
a7df97e6 5819 (clobber (match_dup 5))
9ebbca7d 5820 (clobber (match_dup 6))])]
17caeff2 5821 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5822 "
5823{
99176a91
AH		 5824 if (TARGET_E500_DOUBLE)
5825 {
5826 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5827 DONE;
5828 }
44cd321e
PS		 5829 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS)
5830 {
5831 rtx t1 = gen_reg_rtx (DImode);
5832 emit_insn (gen_floatsidf_ppc64_mfpgpr (operands[0], operands[1], t1));
5833 DONE;
5834 }
05d49501
AM		 5835 if (TARGET_POWERPC64)
5836 {
5837 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5838 rtx t1 = gen_reg_rtx (DImode);
5839 rtx t2 = gen_reg_rtx (DImode);
5840 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5841 DONE;
5842 }
5843
802a0058 5844 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5845 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
9ebbca7d
GK		 5846 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5847 operands[5] = gen_reg_rtx (DFmode);
5848 operands[6] = gen_reg_rtx (SImode);
1fd4e8c1
RK		 5849}")
5850
230215f5 5851(define_insn_and_split "*floatsidf2_internal"
802a0058
MM		 5852 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5853 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5854 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5855 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
b0d6c7d8 5856 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6f9c81f5
DJ		 5857 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5858 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
a3170dc6 5859 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5860 "#"
b3a13419 5861 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
230215f5 5862 [(pc)]
208c89ce
MM		 5863 "
5864{
9ebbca7d 5865 rtx lowword, highword;
230215f5
GK		 5866 gcc_assert (MEM_P (operands[4]));
5867 highword = adjust_address (operands[4], SImode, 0);
5868 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d
GK		 5869 if (! WORDS_BIG_ENDIAN)
5870 {
5871 rtx tmp;
5872 tmp = highword; highword = lowword; lowword = tmp;
5873 }
5874
6ae08853 5875 emit_insn (gen_xorsi3 (operands[6], operands[1],
9ebbca7d 5876 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
230215f5
GK		 5877 emit_move_insn (lowword, operands[6]);
5878 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 5879 emit_move_insn (operands[5], operands[4]);
5880 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5881 DONE;
230215f5
GK		 5882}"
5883 [(set_attr "length" "24")])
802a0058 5884
a3170dc6
AH		 5885(define_expand "floatunssisf2"
5886 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5887 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5888 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5889 "")
5890
802a0058
MM		 5891(define_expand "floatunssidf2"
5892 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5893 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5894 (use (match_dup 2))
5895 (use (match_dup 3))
a7df97e6 5896 (clobber (match_dup 4))
9ebbca7d 5897 (clobber (match_dup 5))])]
99176a91 5898 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5899 "
5900{
99176a91
AH		 5901 if (TARGET_E500_DOUBLE)
5902 {
5903 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5904 DONE;
5905 }
05d49501
AM		 5906 if (TARGET_POWERPC64)
5907 {
5908 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5909 rtx t1 = gen_reg_rtx (DImode);
5910 rtx t2 = gen_reg_rtx (DImode);
5911 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5912 t1, t2));
5913 DONE;
5914 }
5915
802a0058 5916 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5917 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
9ebbca7d
GK		 5918 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5919 operands[5] = gen_reg_rtx (DFmode);
1fd4e8c1
RK		 5920}")
5921
230215f5 5922(define_insn_and_split "*floatunssidf2_internal"
802a0058
MM		 5923 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5924 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5925 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5926 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
b0d6c7d8 5927 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6f9c81f5 5928 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
a3170dc6 5929 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5930 "#"
b3a13419 5931 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
230215f5 5932 [(pc)]
9ebbca7d 5933 "
802a0058 5934{
9ebbca7d 5935 rtx lowword, highword;
230215f5
GK		 5936 gcc_assert (MEM_P (operands[4]));
5937 highword = adjust_address (operands[4], SImode, 0);
5938 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d 5939 if (! WORDS_BIG_ENDIAN)
f6968f59 5940 {
9ebbca7d
GK		 5941 rtx tmp;
5942 tmp = highword; highword = lowword; lowword = tmp;
f6968f59 5943 }
802a0058 5944
230215f5
GK		 5945 emit_move_insn (lowword, operands[1]);
5946 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 5947 emit_move_insn (operands[5], operands[4]);
5948 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5949 DONE;
230215f5
GK		 5950}"
5951 [(set_attr "length" "20")])
1fd4e8c1 5952
1fd4e8c1 5953(define_expand "fix_truncdfsi2"
045a8eb3 5954 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
802a0058
MM		 5955 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5956 (clobber (match_dup 2))
9ebbca7d 5957 (clobber (match_dup 3))])]
99176a91
AH		 5958 "(TARGET_POWER2 || TARGET_POWERPC)
5959 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5960 "
5961{
99176a91
AH		 5962 if (TARGET_E500_DOUBLE)
5963 {
5964 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5965 DONE;
5966 }
802a0058 5967 operands[2] = gen_reg_rtx (DImode);
44cd321e
PS		 5968 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5969 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5970 {
5971 operands[3] = gen_reg_rtx (DImode);
5972 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5973 operands[2], operands[3]));
5974 DONE;
5975 }
da4c340c
GK		 5976 if (TARGET_PPC_GFXOPT)
5977 {
5978 rtx orig_dest = operands[0];
045a8eb3 5979 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
da4c340c
GK		 5980 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5981 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5982 operands[2]));
5983 if (operands[0] != orig_dest)
5984 emit_move_insn (orig_dest, operands[0]);
5985 DONE;
5986 }
9ebbca7d 5987 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
1fd4e8c1
RK		 5988}")
5989
da4c340c 5990(define_insn_and_split "*fix_truncdfsi2_internal"
802a0058
MM		 5991 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5992 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
e3485bbc 5993 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
b0d6c7d8 5994 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
a3170dc6 5995 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5996 "#"
b3a13419 5997 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
da4c340c 5998 [(pc)]
9ebbca7d 5999 "
802a0058 6000{
9ebbca7d 6001 rtx lowword;
230215f5
GK		 6002 gcc_assert (MEM_P (operands[3]));
6003 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
802a0058 6004
9ebbca7d
GK		 6005 emit_insn (gen_fctiwz (operands[2], operands[1]));
6006 emit_move_insn (operands[3], operands[2]);
230215f5 6007 emit_move_insn (operands[0], lowword);
9ebbca7d 6008 DONE;
da4c340c
GK		 6009}"
6010 [(set_attr "length" "16")])
6011
6012(define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6013 [(set (match_operand:SI 0 "memory_operand" "=Z")
6014 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6015 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
6016 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6017 && TARGET_PPC_GFXOPT"
6018 "#"
6019 "&& 1"
6020 [(pc)]
6021 "
6022{
6023 emit_insn (gen_fctiwz (operands[2], operands[1]));
6024 emit_insn (gen_stfiwx (operands[0], operands[2]));
6025 DONE;
6026}"
6027 [(set_attr "length" "16")])
802a0058 6028
44cd321e
PS		 6029(define_insn_and_split "fix_truncdfsi2_mfpgpr"
6030 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6031 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6032 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6033 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6034 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6035 "#"
6036 "&& 1"
6037 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6038 (set (match_dup 3) (match_dup 2))
6039 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6040 ""
6041 [(set_attr "length" "12")])
6042
615158e2 6043; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
9ebbca7d
GK		 6044; rather than (set (subreg:SI (reg)) (fix:SI ...))
6045; because the first makes it clear that operand 0 is not live
6046; before the instruction.
6047(define_insn "fctiwz"
da4c340c 6048 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
615158e2
JJ		 6049 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
6050 UNSPEC_FCTIWZ))]
a3170dc6 6051 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
a260abc9
DE		 6052 "{fcirz|fctiwz} %0,%1"
6053 [(set_attr "type" "fp")])
6054
9719f3b7
DE		 6055(define_insn "btruncdf2"
6056 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6057 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6058 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6059 "friz %0,%1"
6060 [(set_attr "type" "fp")])
6061
6062(define_insn "btruncsf2"
6063 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6064 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6065 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6066 "friz %0,%1"
9719f3b7
DE		 6067 [(set_attr "type" "fp")])
6068
6069(define_insn "ceildf2"
6070 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6071 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6072 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6073 "frip %0,%1"
6074 [(set_attr "type" "fp")])
6075
6076(define_insn "ceilsf2"
833126ad 6077 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9719f3b7
DE		 6078 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6079 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6080 "frip %0,%1"
9719f3b7
DE		 6081 [(set_attr "type" "fp")])
6082
6083(define_insn "floordf2"
6084 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6085 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6086 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6087 "frim %0,%1"
6088 [(set_attr "type" "fp")])
6089
6090(define_insn "floorsf2"
6091 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6092 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6093 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6094 "frim %0,%1"
9719f3b7
DE		 6095 [(set_attr "type" "fp")])
6096
6097(define_insn "rounddf2"
6098 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6099 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6100 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
6101 "frin %0,%1"
6102 [(set_attr "type" "fp")])
6103
6104(define_insn "roundsf2"
6105 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6106 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6107 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6108 "frin %0,%1"
9719f3b7
DE		 6109 [(set_attr "type" "fp")])
6110
da4c340c
GK		 6111; An UNSPEC is used so we don't have to support SImode in FP registers.
6112(define_insn "stfiwx"
6113 [(set (match_operand:SI 0 "memory_operand" "=Z")
6114 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6115 UNSPEC_STFIWX))]
6116 "TARGET_PPC_GFXOPT"
6117 "stfiwx %1,%y0"
6118 [(set_attr "type" "fpstore")])
6119
a3170dc6
AH		 6120(define_expand "floatsisf2"
6121 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6122 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6123 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6124 "")
6125
a473029f
RK		 6126(define_insn "floatdidf2"
6127 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
61c07d3c 6128 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
a3170dc6 6129 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 6130 "fcfid %0,%1"
6131 [(set_attr "type" "fp")])
6132
44cd321e
PS		 6133(define_insn_and_split "floatsidf_ppc64_mfpgpr"
6134 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6135 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6136 (clobber (match_operand:DI 2 "gpc_reg_operand" "=r"))]
6137 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
6138 "#"
6139 "&& 1"
6140 [(set (match_dup 2) (sign_extend:DI (match_dup 1)))
6141 (set (match_dup 0) (float:DF (match_dup 2)))]
6142 "")
6143
05d49501
AM		 6144(define_insn_and_split "floatsidf_ppc64"
6145 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6146 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
b0d6c7d8 6147 (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))
05d49501
AM		 6148 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6149 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
44cd321e 6150 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501 6151 "#"
ecb62ae7 6152 "&& 1"
05d49501
AM		 6153 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
6154 (set (match_dup 2) (match_dup 3))
6155 (set (match_dup 4) (match_dup 2))
6156 (set (match_dup 0) (float:DF (match_dup 4)))]
6157 "")
6158
6159(define_insn_and_split "floatunssidf_ppc64"
6160 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6161 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
b0d6c7d8 6162 (clobber (match_operand:DI 2 "offsettable_mem_operand" "=o"))
05d49501
AM		 6163 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
6164 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
a3170dc6 6165 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
05d49501 6166 "#"
ecb62ae7 6167 "&& 1"
05d49501
AM		 6168 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
6169 (set (match_dup 2) (match_dup 3))
6170 (set (match_dup 4) (match_dup 2))
6171 (set (match_dup 0) (float:DF (match_dup 4)))]
6172 "")
6173
a473029f 6174(define_insn "fix_truncdfdi2"
61c07d3c 6175 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
a473029f 6176 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
a3170dc6 6177 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 6178 "fctidz %0,%1"
6179 [(set_attr "type" "fp")])
ea112fc4 6180
678b7733
AM		 6181(define_expand "floatdisf2"
6182 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6183 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
994cf173 6184 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 6185 "
6186{
994cf173 6187 rtx val = operands[1];
678b7733
AM		 6188 if (!flag_unsafe_math_optimizations)
6189 {
6190 rtx label = gen_label_rtx ();
994cf173
AM		 6191 val = gen_reg_rtx (DImode);
6192 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
678b7733
AM		 6193 emit_label (label);
6194 }
994cf173 6195 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
678b7733
AM		 6196 DONE;
6197}")
6198
6199;; This is not IEEE compliant if rounding mode is "round to nearest".
6200;; If the DI->DF conversion is inexact, then it's possible to suffer
6201;; from double rounding.
6202(define_insn_and_split "floatdisf2_internal1"
ea112fc4 6203 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
61c07d3c 6204 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
ea112fc4 6205 (clobber (match_scratch:DF 2 "=f"))]
678b7733 6206 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
ea112fc4
DE		 6207 "#"
6208 "&& reload_completed"
6209 [(set (match_dup 2)
6210 (float:DF (match_dup 1)))
6211 (set (match_dup 0)
6212 (float_truncate:SF (match_dup 2)))]
6213 "")
678b7733
AM		 6214
6215;; Twiddles bits to avoid double rounding.
b6d08ca1 6216;; Bits that might be truncated when converting to DFmode are replaced
678b7733
AM		 6217;; by a bit that won't be lost at that stage, but is below the SFmode
6218;; rounding position.
6219(define_expand "floatdisf2_internal2"
994cf173
AM		 6220 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6221 (const_int 53)))
6222 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6223 (const_int 2047)))
6224 (clobber (scratch:CC))])
6225 (set (match_dup 3) (plus:DI (match_dup 3)
6226 (const_int 1)))
6227 (set (match_dup 0) (plus:DI (match_dup 0)
6228 (const_int 2047)))
6229 (set (match_dup 4) (compare:CCUNS (match_dup 3)
c22e62a6 6230 (const_int 2)))
994cf173
AM		 6231 (set (match_dup 0) (ior:DI (match_dup 0)
6232 (match_dup 1)))
6233 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6234 (const_int -2048)))
6235 (clobber (scratch:CC))])
6236 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6237 (label_ref (match_operand:DI 2 "" ""))
678b7733 6238 (pc)))
994cf173
AM		 6239 (set (match_dup 0) (match_dup 1))]
6240 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 6241 "
6242{
678b7733 6243 operands[3] = gen_reg_rtx (DImode);
994cf173 6244 operands[4] = gen_reg_rtx (CCUNSmode);
678b7733 6245}")
1fd4e8c1
RK		 6246\f
6247;; Define the DImode operations that can be done in a small number
a6ec530c
RK		 6248;; of instructions. The & constraints are to prevent the register
6249;; allocator from allocating registers that overlap with the inputs
6250;; (for example, having an input in 7,8 and an output in 6,7). We
38e01259 6251;; also allow for the output being the same as one of the inputs.
a6ec530c 6252
266eb58a 6253(define_insn "*adddi3_noppc64"
a6ec530c
RK		 6254 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6255 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6256 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
e1f83b4d 6257 "! TARGET_POWERPC64"
0f645302
MM		 6258 "*
6259{
6260 if (WORDS_BIG_ENDIAN)
6261 return (GET_CODE (operands[2])) != CONST_INT
6262 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6263 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6264 else
6265 return (GET_CODE (operands[2])) != CONST_INT
6266 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6267 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6268}"
943c15ed
DE		 6269 [(set_attr "type" "two")
6270 (set_attr "length" "8")])
1fd4e8c1 6271
266eb58a 6272(define_insn "*subdi3_noppc64"
e7e5df70
RK		 6273 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6274 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6275 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
266eb58a 6276 "! TARGET_POWERPC64"
5502823b
RK		 6277 "*
6278{
0f645302
MM		 6279 if (WORDS_BIG_ENDIAN)
6280 return (GET_CODE (operands[1]) != CONST_INT)
6281 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6282 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6283 else
6284 return (GET_CODE (operands[1]) != CONST_INT)
6285 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6286 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5502823b 6287}"
943c15ed
DE		 6288 [(set_attr "type" "two")
6289 (set_attr "length" "8")])
ca7f5001 6290
266eb58a 6291(define_insn "*negdi2_noppc64"
a6ec530c
RK		 6292 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6293 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
51b8fc2c 6294 "! TARGET_POWERPC64"
5502823b
RK		 6295 "*
6296{
6297 return (WORDS_BIG_ENDIAN)
6298 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6299 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6300}"
943c15ed
DE		 6301 [(set_attr "type" "two")
6302 (set_attr "length" "8")])
ca7f5001 6303
8ffd9c51
RK		 6304(define_expand "mulsidi3"
6305 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6306 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6307 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
a2f270cc 6308 "! TARGET_POWERPC64"
8ffd9c51
RK		 6309 "
6310{
6311 if (! TARGET_POWER && ! TARGET_POWERPC)
6312 {
39403d82
DE		 6313 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6314 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6315 emit_insn (gen_mull_call ());
cf27b467 6316 if (WORDS_BIG_ENDIAN)
39403d82 6317 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
cf27b467
MM		 6318 else
6319 {
6320 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
39403d82 6321 gen_rtx_REG (SImode, 3));
cf27b467 6322 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
39403d82 6323 gen_rtx_REG (SImode, 4));
cf27b467 6324 }
8ffd9c51
RK		 6325 DONE;
6326 }
6327 else if (TARGET_POWER)
6328 {
6329 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6330 DONE;
6331 }
6332}")
deb9225a 6333
8ffd9c51 6334(define_insn "mulsidi3_mq"
cd2b37d9 6335 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8ffd9c51 6336 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
cd2b37d9 6337 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1fd4e8c1 6338 (clobber (match_scratch:SI 3 "=q"))]
ca7f5001 6339 "TARGET_POWER"
b19003d8 6340 "mul %0,%1,%2\;mfmq %L0"
8ffd9c51
RK		 6341 [(set_attr "type" "imul")
6342 (set_attr "length" "8")])
deb9225a 6343
f192bf8b 6344(define_insn "*mulsidi3_no_mq"
425c176f 6345 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
8ffd9c51
RK		 6346 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6347 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6348 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5502823b
RK		 6349 "*
6350{
6351 return (WORDS_BIG_ENDIAN)
6352 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6353 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6354}"
8ffd9c51
RK		 6355 [(set_attr "type" "imul")
6356 (set_attr "length" "8")])
deb9225a 6357
ebedb4dd
MM		 6358(define_split
6359 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6360 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6361 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6362 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6363 [(set (match_dup 3)
6364 (truncate:SI
6365 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6366 (sign_extend:DI (match_dup 2)))
6367 (const_int 32))))
6368 (set (match_dup 4)
6369 (mult:SI (match_dup 1)
6370 (match_dup 2)))]
6371 "
6372{
6373 int endian = (WORDS_BIG_ENDIAN == 0);
6374 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6375 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6376}")
6377
f192bf8b
DE		 6378(define_expand "umulsidi3"
6379 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6380 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6381 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6382 "TARGET_POWERPC && ! TARGET_POWERPC64"
6383 "
6384{
6385 if (TARGET_POWER)
6386 {
6387 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6388 DONE;
6389 }
6390}")
6391
6392(define_insn "umulsidi3_mq"
6393 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6394 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6395 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6396 (clobber (match_scratch:SI 3 "=q"))]
6397 "TARGET_POWERPC && TARGET_POWER"
6398 "*
6399{
6400 return (WORDS_BIG_ENDIAN)
6401 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6402 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6403}"
6404 [(set_attr "type" "imul")
6405 (set_attr "length" "8")])
6406
6407(define_insn "*umulsidi3_no_mq"
8106dc08
MM		 6408 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6409 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6410 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6411 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
8106dc08
MM		 6412 "*
6413{
6414 return (WORDS_BIG_ENDIAN)
6415 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6416 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6417}"
6418 [(set_attr "type" "imul")
6419 (set_attr "length" "8")])
6420
ebedb4dd
MM		 6421(define_split
6422 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6423 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6424 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6425 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6426 [(set (match_dup 3)
6427 (truncate:SI
6428 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6429 (zero_extend:DI (match_dup 2)))
6430 (const_int 32))))
6431 (set (match_dup 4)
6432 (mult:SI (match_dup 1)
6433 (match_dup 2)))]
6434 "
6435{
6436 int endian = (WORDS_BIG_ENDIAN == 0);
6437 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6438 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6439}")
6440
8ffd9c51
RK		 6441(define_expand "smulsi3_highpart"
6442 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6443 (truncate:SI
6444 (lshiftrt:DI (mult:DI (sign_extend:DI
e42ac3de 6445 (match_operand:SI 1 "gpc_reg_operand" ""))
8ffd9c51 6446 (sign_extend:DI
e42ac3de 6447 (match_operand:SI 2 "gpc_reg_operand" "")))
8ffd9c51
RK		 6448 (const_int 32))))]
6449 ""
6450 "
6451{
6452 if (! TARGET_POWER && ! TARGET_POWERPC)
6453 {
39403d82
DE		 6454 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6455 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6456 emit_insn (gen_mulh_call ());
39403d82 6457 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 6458 DONE;
6459 }
6460 else if (TARGET_POWER)
6461 {
6462 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6463 DONE;
6464 }
6465}")
deb9225a 6466
8ffd9c51
RK		 6467(define_insn "smulsi3_highpart_mq"
6468 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6469 (truncate:SI
fada905b
MM		 6470 (lshiftrt:DI (mult:DI (sign_extend:DI
6471 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6472 (sign_extend:DI
6473 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51
RK		 6474 (const_int 32))))
6475 (clobber (match_scratch:SI 3 "=q"))]
6476 "TARGET_POWER"
6477 "mul %0,%1,%2"
6478 [(set_attr "type" "imul")])
deb9225a 6479
f192bf8b 6480(define_insn "*smulsi3_highpart_no_mq"
8ffd9c51
RK		 6481 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6482 (truncate:SI
fada905b
MM		 6483 (lshiftrt:DI (mult:DI (sign_extend:DI
6484 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6485 (sign_extend:DI
6486 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51 6487 (const_int 32))))]
f192bf8b 6488 "TARGET_POWERPC && ! TARGET_POWER"
8ffd9c51
RK		 6489 "mulhw %0,%1,%2"
6490 [(set_attr "type" "imul")])
deb9225a 6491
f192bf8b
DE		 6492(define_expand "umulsi3_highpart"
6493 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6494 (truncate:SI
6495 (lshiftrt:DI (mult:DI (zero_extend:DI
6496 (match_operand:SI 1 "gpc_reg_operand" ""))
6497 (zero_extend:DI
6498 (match_operand:SI 2 "gpc_reg_operand" "")))
6499 (const_int 32))))]
6500 "TARGET_POWERPC"
6501 "
6502{
6503 if (TARGET_POWER)
6504 {
6505 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6506 DONE;
6507 }
6508}")
6509
6510(define_insn "umulsi3_highpart_mq"
6511 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6512 (truncate:SI
6513 (lshiftrt:DI (mult:DI (zero_extend:DI
6514 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6515 (zero_extend:DI
6516 (match_operand:SI 2 "gpc_reg_operand" "r")))
6517 (const_int 32))))
6518 (clobber (match_scratch:SI 3 "=q"))]
6519 "TARGET_POWERPC && TARGET_POWER"
6520 "mulhwu %0,%1,%2"
6521 [(set_attr "type" "imul")])
6522
6523(define_insn "*umulsi3_highpart_no_mq"
266eb58a
DE		 6524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6525 (truncate:SI
6526 (lshiftrt:DI (mult:DI (zero_extend:DI
6527 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6528 (zero_extend:DI
6529 (match_operand:SI 2 "gpc_reg_operand" "r")))
6530 (const_int 32))))]
f192bf8b 6531 "TARGET_POWERPC && ! TARGET_POWER"
266eb58a
DE		 6532 "mulhwu %0,%1,%2"
6533 [(set_attr "type" "imul")])
6534
6535;; If operands 0 and 2 are in the same register, we have a problem. But
6536;; operands 0 and 1 (the usual case) can be in the same register. That's
6537;; why we have the strange constraints below.
6538(define_insn "ashldi3_power"
6539 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6540 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6541 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6542 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6543 "TARGET_POWER"
6544 "@
6545 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6546 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6547 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6548 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6549 [(set_attr "length" "8")])
6550
6551(define_insn "lshrdi3_power"
47ad8c61 6552 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
266eb58a
DE		 6553 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6554 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6555 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6556 "TARGET_POWER"
6557 "@
47ad8c61 6558 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
266eb58a
DE		 6559 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6560 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6561 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6562 [(set_attr "length" "8")])
6563
6564;; Shift by a variable amount is too complex to be worth open-coding. We
6565;; just handle shifts by constants.
6566(define_insn "ashrdi3_power"
7093ddee 6567 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
266eb58a
DE		 6568 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6569 (match_operand:SI 2 "const_int_operand" "M,i")))
6570 (clobber (match_scratch:SI 3 "=X,q"))]
6571 "TARGET_POWER"
6572 "@
6573 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6574 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
44cd321e
PS		 6575 [(set_attr "type" "shift")
6576 (set_attr "length" "8")])
4aa74a4f
FS		 6577
6578(define_insn "ashrdi3_no_power"
6579 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6580 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6581 (match_operand:SI 2 "const_int_operand" "M,i")))]
97727e85 6582 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
4aa74a4f
FS		 6583 "@
6584 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6585 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
943c15ed
DE		 6586 [(set_attr "type" "two,three")
6587 (set_attr "length" "8,12")])
683bdff7
FJ		 6588
6589(define_insn "*ashrdisi3_noppc64"
6590 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6ae08853 6591 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
683bdff7
FJ		 6592 (const_int 32)) 4))]
6593 "TARGET_32BIT && !TARGET_POWERPC64"
6594 "*
6595{
6596 if (REGNO (operands[0]) == REGNO (operands[1]))
6597 return \"\";
6598 else
6599 return \"mr %0,%1\";
6600}"
6ae08853 6601 [(set_attr "length" "4")])
683bdff7 6602
266eb58a
DE		 6603\f
6604;; PowerPC64 DImode operations.
6605
ea112fc4 6606(define_insn_and_split "absdi2"
266eb58a 6607 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6608 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
266eb58a
DE		 6609 (clobber (match_scratch:DI 2 "=&r,&r"))]
6610 "TARGET_POWERPC64"
ea112fc4
DE		 6611 "#"
6612 "&& reload_completed"
a260abc9 6613 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6614 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
a238cd8b 6615 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
266eb58a
DE		 6616 "")
6617
ea112fc4 6618(define_insn_and_split "*nabsdi2"
266eb58a 6619 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6620 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
266eb58a
DE		 6621 (clobber (match_scratch:DI 2 "=&r,&r"))]
6622 "TARGET_POWERPC64"
ea112fc4
DE		 6623 "#"
6624 "&& reload_completed"
a260abc9 6625 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6626 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
19ba8161 6627 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
266eb58a
DE		 6628 "")
6629
266eb58a 6630(define_insn "muldi3"
c9692532
DE		 6631 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6632 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6633 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
266eb58a 6634 "TARGET_POWERPC64"
c9692532
DE		 6635 "@
6636 mulld %0,%1,%2
6637 mulli %0,%1,%2"
6638 [(set (attr "type")
6639 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6640 (const_string "imul3")
6641 (match_operand:SI 2 "short_cint_operand" "")
6642 (const_string "imul2")]
6643 (const_string "lmul")))])
266eb58a 6644
9259f3b0
DE		 6645(define_insn "*muldi3_internal1"
6646 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6647 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6648 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6649 (const_int 0)))
6650 (clobber (match_scratch:DI 3 "=r,r"))]
6651 "TARGET_POWERPC64"
6652 "@
6653 mulld. %3,%1,%2
6654 #"
6655 [(set_attr "type" "lmul_compare")
6656 (set_attr "length" "4,8")])
6657
6658(define_split
6659 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6660 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6661 (match_operand:DI 2 "gpc_reg_operand" ""))
6662 (const_int 0)))
6663 (clobber (match_scratch:DI 3 ""))]
6664 "TARGET_POWERPC64 && reload_completed"
6665 [(set (match_dup 3)
6666 (mult:DI (match_dup 1) (match_dup 2)))
6667 (set (match_dup 0)
6668 (compare:CC (match_dup 3)
6669 (const_int 0)))]
6670 "")
6671
6672(define_insn "*muldi3_internal2"
6673 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6674 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6675 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6676 (const_int 0)))
6677 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6678 (mult:DI (match_dup 1) (match_dup 2)))]
6679 "TARGET_POWERPC64"
6680 "@
6681 mulld. %0,%1,%2
6682 #"
6683 [(set_attr "type" "lmul_compare")
6684 (set_attr "length" "4,8")])
6685
6686(define_split
6687 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6688 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6689 (match_operand:DI 2 "gpc_reg_operand" ""))
6690 (const_int 0)))
6691 (set (match_operand:DI 0 "gpc_reg_operand" "")
6692 (mult:DI (match_dup 1) (match_dup 2)))]
6693 "TARGET_POWERPC64 && reload_completed"
6694 [(set (match_dup 0)
6695 (mult:DI (match_dup 1) (match_dup 2)))
6696 (set (match_dup 3)
6697 (compare:CC (match_dup 0)
6698 (const_int 0)))]
6699 "")
6700
266eb58a
DE		 6701(define_insn "smuldi3_highpart"
6702 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6703 (truncate:DI
6704 (lshiftrt:TI (mult:TI (sign_extend:TI
6705 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6706 (sign_extend:TI
6707 (match_operand:DI 2 "gpc_reg_operand" "r")))
6708 (const_int 64))))]
6709 "TARGET_POWERPC64"
6710 "mulhd %0,%1,%2"
3cb999d8 6711 [(set_attr "type" "lmul")])
266eb58a
DE		 6712
6713(define_insn "umuldi3_highpart"
6714 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6715 (truncate:DI
6716 (lshiftrt:TI (mult:TI (zero_extend:TI
6717 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6718 (zero_extend:TI
6719 (match_operand:DI 2 "gpc_reg_operand" "r")))
6720 (const_int 64))))]
6721 "TARGET_POWERPC64"
6722 "mulhdu %0,%1,%2"
3cb999d8 6723 [(set_attr "type" "lmul")])
266eb58a 6724
266eb58a 6725(define_insn "rotldi3"
44cd321e
PS		 6726 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6727 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6728 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 6729 "TARGET_POWERPC64"
44cd321e
PS		 6730 "@
6731 rldcl %0,%1,%2,0
6732 rldicl %0,%1,%H2,0"
6733 [(set_attr "type" "var_shift_rotate,integer")])
266eb58a 6734
a260abc9 6735(define_insn "*rotldi3_internal2"
44cd321e
PS		 6736 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6737 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6738 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6739 (const_int 0)))
44cd321e 6740 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6741 "TARGET_64BIT"
9ebbca7d 6742 "@
44cd321e
PS		 6743 rldcl. %3,%1,%2,0
6744 rldicl. %3,%1,%H2,0
6745 #
9ebbca7d 6746 #"
44cd321e
PS		 6747 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6748 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6749
6750(define_split
6751 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6752 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6753 (match_operand:DI 2 "reg_or_cint_operand" ""))
6754 (const_int 0)))
6755 (clobber (match_scratch:DI 3 ""))]
6756 "TARGET_POWERPC64 && reload_completed"
6757 [(set (match_dup 3)
6758 (rotate:DI (match_dup 1) (match_dup 2)))
6759 (set (match_dup 0)
6760 (compare:CC (match_dup 3)
6761 (const_int 0)))]
6762 "")
266eb58a 6763
a260abc9 6764(define_insn "*rotldi3_internal3"
44cd321e
PS		 6765 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6766 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6767 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6768 (const_int 0)))
44cd321e 6769 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 6770 (rotate:DI (match_dup 1) (match_dup 2)))]
683bdff7 6771 "TARGET_64BIT"
9ebbca7d 6772 "@
44cd321e
PS		 6773 rldcl. %0,%1,%2,0
6774 rldicl. %0,%1,%H2,0
6775 #
9ebbca7d 6776 #"
44cd321e
PS		 6777 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6778 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6779
6780(define_split
6781 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6782 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6783 (match_operand:DI 2 "reg_or_cint_operand" ""))
6784 (const_int 0)))
6785 (set (match_operand:DI 0 "gpc_reg_operand" "")
6786 (rotate:DI (match_dup 1) (match_dup 2)))]
6787 "TARGET_POWERPC64 && reload_completed"
6788 [(set (match_dup 0)
6789 (rotate:DI (match_dup 1) (match_dup 2)))
6790 (set (match_dup 3)
6791 (compare:CC (match_dup 0)
6792 (const_int 0)))]
6793 "")
266eb58a 6794
a260abc9 6795(define_insn "*rotldi3_internal4"
44cd321e
PS		 6796 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6797 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6798 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6799 (match_operand:DI 3 "mask64_operand" "n,n")))]
a260abc9 6800 "TARGET_POWERPC64"
44cd321e
PS		 6801 "@
6802 rldc%B3 %0,%1,%2,%S3
6803 rldic%B3 %0,%1,%H2,%S3"
6804 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6805
6806(define_insn "*rotldi3_internal5"
44cd321e 6807 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6808 (compare:CC (and:DI
44cd321e
PS		 6809 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6810 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6811 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6812 (const_int 0)))
44cd321e 6813 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
683bdff7 6814 "TARGET_64BIT"
9ebbca7d 6815 "@
44cd321e
PS		 6816 rldc%B3. %4,%1,%2,%S3
6817 rldic%B3. %4,%1,%H2,%S3
6818 #
9ebbca7d 6819 #"
44cd321e
PS		 6820 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6821 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6822
6823(define_split
6824 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6825 (compare:CC (and:DI
6826 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6827 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6828 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6829 (const_int 0)))
6830 (clobber (match_scratch:DI 4 ""))]
6831 "TARGET_POWERPC64 && reload_completed"
6832 [(set (match_dup 4)
6833 (and:DI (rotate:DI (match_dup 1)
6834 (match_dup 2))
6835 (match_dup 3)))
6836 (set (match_dup 0)
6837 (compare:CC (match_dup 4)
6838 (const_int 0)))]
6839 "")
a260abc9
DE		 6840
6841(define_insn "*rotldi3_internal6"
44cd321e 6842 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6843 (compare:CC (and:DI
44cd321e
PS		 6844 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6845 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6846 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6847 (const_int 0)))
44cd321e 6848 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6849 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6850 "TARGET_64BIT"
9ebbca7d 6851 "@
44cd321e
PS		 6852 rldc%B3. %0,%1,%2,%S3
6853 rldic%B3. %0,%1,%H2,%S3
6854 #
9ebbca7d 6855 #"
44cd321e
PS		 6856 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6857 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6858
6859(define_split
6860 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6861 (compare:CC (and:DI
6862 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6863 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6864 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6865 (const_int 0)))
6866 (set (match_operand:DI 0 "gpc_reg_operand" "")
6867 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6868 "TARGET_POWERPC64 && reload_completed"
6869 [(set (match_dup 0)
6870 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6871 (set (match_dup 4)
6872 (compare:CC (match_dup 0)
6873 (const_int 0)))]
6874 "")
a260abc9
DE		 6875
6876(define_insn "*rotldi3_internal7"
44cd321e 6877 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6878 (zero_extend:DI
6879 (subreg:QI
44cd321e
PS		 6880 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6881 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6882 "TARGET_POWERPC64"
44cd321e
PS		 6883 "@
6884 rldcl %0,%1,%2,56
6885 rldicl %0,%1,%H2,56"
6886 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6887
6888(define_insn "*rotldi3_internal8"
44cd321e 6889 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6890 (compare:CC (zero_extend:DI
6891 (subreg:QI
44cd321e
PS		 6892 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6893 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6894 (const_int 0)))
44cd321e 6895 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6896 "TARGET_64BIT"
9ebbca7d 6897 "@
44cd321e
PS		 6898 rldcl. %3,%1,%2,56
6899 rldicl. %3,%1,%H2,56
6900 #
9ebbca7d 6901 #"
44cd321e
PS		 6902 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6903 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6904
6905(define_split
6906 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6907 (compare:CC (zero_extend:DI
6908 (subreg:QI
6909 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6910 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6911 (const_int 0)))
6912 (clobber (match_scratch:DI 3 ""))]
6913 "TARGET_POWERPC64 && reload_completed"
6914 [(set (match_dup 3)
6915 (zero_extend:DI (subreg:QI
6916 (rotate:DI (match_dup 1)
6917 (match_dup 2)) 0)))
6918 (set (match_dup 0)
6919 (compare:CC (match_dup 3)
6920 (const_int 0)))]
6921 "")
a260abc9
DE		 6922
6923(define_insn "*rotldi3_internal9"
44cd321e 6924 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6925 (compare:CC (zero_extend:DI
6926 (subreg:QI
44cd321e
PS		 6927 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6928 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6929 (const_int 0)))
44cd321e 6930 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6931 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6932 "TARGET_64BIT"
9ebbca7d 6933 "@
44cd321e
PS		 6934 rldcl. %0,%1,%2,56
6935 rldicl. %0,%1,%H2,56
6936 #
9ebbca7d 6937 #"
44cd321e
PS		 6938 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6939 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6940
6941(define_split
6942 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6943 (compare:CC (zero_extend:DI
6944 (subreg:QI
6945 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6946 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6947 (const_int 0)))
6948 (set (match_operand:DI 0 "gpc_reg_operand" "")
6949 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6950 "TARGET_POWERPC64 && reload_completed"
6951 [(set (match_dup 0)
6952 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6953 (set (match_dup 3)
6954 (compare:CC (match_dup 0)
6955 (const_int 0)))]
6956 "")
a260abc9
DE		 6957
6958(define_insn "*rotldi3_internal10"
44cd321e 6959 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6960 (zero_extend:DI
6961 (subreg:HI
44cd321e
PS		 6962 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6963 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6964 "TARGET_POWERPC64"
44cd321e
PS		 6965 "@
6966 rldcl %0,%1,%2,48
6967 rldicl %0,%1,%H2,48"
6968 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6969
6970(define_insn "*rotldi3_internal11"
44cd321e 6971 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6972 (compare:CC (zero_extend:DI
6973 (subreg:HI
44cd321e
PS		 6974 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6975 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6976 (const_int 0)))
44cd321e 6977 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6978 "TARGET_64BIT"
9ebbca7d 6979 "@
44cd321e
PS		 6980 rldcl. %3,%1,%2,48
6981 rldicl. %3,%1,%H2,48
6982 #
9ebbca7d 6983 #"
44cd321e
PS		 6984 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6985 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6986
6987(define_split
6988 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6989 (compare:CC (zero_extend:DI
6990 (subreg:HI
6991 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6992 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6993 (const_int 0)))
6994 (clobber (match_scratch:DI 3 ""))]
6995 "TARGET_POWERPC64 && reload_completed"
6996 [(set (match_dup 3)
6997 (zero_extend:DI (subreg:HI
6998 (rotate:DI (match_dup 1)
6999 (match_dup 2)) 0)))
7000 (set (match_dup 0)
7001 (compare:CC (match_dup 3)
7002 (const_int 0)))]
7003 "")
a260abc9
DE		 7004
7005(define_insn "*rotldi3_internal12"
44cd321e 7006 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7007 (compare:CC (zero_extend:DI
7008 (subreg:HI
44cd321e
PS		 7009 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7010 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7011 (const_int 0)))
44cd321e 7012 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 7013 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 7014 "TARGET_64BIT"
9ebbca7d 7015 "@
44cd321e
PS		 7016 rldcl. %0,%1,%2,48
7017 rldicl. %0,%1,%H2,48
7018 #
9ebbca7d 7019 #"
44cd321e
PS		 7020 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7021 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7022
7023(define_split
7024 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7025 (compare:CC (zero_extend:DI
7026 (subreg:HI
7027 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7028 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7029 (const_int 0)))
7030 (set (match_operand:DI 0 "gpc_reg_operand" "")
7031 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7032 "TARGET_POWERPC64 && reload_completed"
7033 [(set (match_dup 0)
7034 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7035 (set (match_dup 3)
7036 (compare:CC (match_dup 0)
7037 (const_int 0)))]
7038 "")
a260abc9
DE		 7039
7040(define_insn "*rotldi3_internal13"
44cd321e 7041 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 7042 (zero_extend:DI
7043 (subreg:SI
44cd321e
PS		 7044 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7045 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 7046 "TARGET_POWERPC64"
44cd321e
PS		 7047 "@
7048 rldcl %0,%1,%2,32
7049 rldicl %0,%1,%H2,32"
7050 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 7051
7052(define_insn "*rotldi3_internal14"
44cd321e 7053 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7054 (compare:CC (zero_extend:DI
7055 (subreg:SI
44cd321e
PS		 7056 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7057 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7058 (const_int 0)))
44cd321e 7059 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7060 "TARGET_64BIT"
9ebbca7d 7061 "@
44cd321e
PS		 7062 rldcl. %3,%1,%2,32
7063 rldicl. %3,%1,%H2,32
7064 #
9ebbca7d 7065 #"
44cd321e
PS		 7066 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7067 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7068
7069(define_split
7070 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7071 (compare:CC (zero_extend:DI
7072 (subreg:SI
7073 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7074 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7075 (const_int 0)))
7076 (clobber (match_scratch:DI 3 ""))]
7077 "TARGET_POWERPC64 && reload_completed"
7078 [(set (match_dup 3)
7079 (zero_extend:DI (subreg:SI
7080 (rotate:DI (match_dup 1)
7081 (match_dup 2)) 0)))
7082 (set (match_dup 0)
7083 (compare:CC (match_dup 3)
7084 (const_int 0)))]
7085 "")
a260abc9
DE		 7086
7087(define_insn "*rotldi3_internal15"
44cd321e 7088 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7089 (compare:CC (zero_extend:DI
7090 (subreg:SI
44cd321e
PS		 7091 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7092 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7093 (const_int 0)))
44cd321e 7094 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 7095 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 7096 "TARGET_64BIT"
9ebbca7d 7097 "@
44cd321e
PS		 7098 rldcl. %0,%1,%2,32
7099 rldicl. %0,%1,%H2,32
7100 #
9ebbca7d 7101 #"
44cd321e
PS		 7102 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7103 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7104
7105(define_split
7106 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7107 (compare:CC (zero_extend:DI
7108 (subreg:SI
7109 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7110 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7111 (const_int 0)))
7112 (set (match_operand:DI 0 "gpc_reg_operand" "")
7113 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7114 "TARGET_POWERPC64 && reload_completed"
7115 [(set (match_dup 0)
7116 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7117 (set (match_dup 3)
7118 (compare:CC (match_dup 0)
7119 (const_int 0)))]
7120 "")
a260abc9 7121
266eb58a
DE		 7122(define_expand "ashldi3"
7123 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7124 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7125 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7126 "TARGET_POWERPC64 || TARGET_POWER"
7127 "
7128{
7129 if (TARGET_POWERPC64)
7130 ;
7131 else if (TARGET_POWER)
7132 {
7133 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7134 DONE;
7135 }
7136 else
7137 FAIL;
7138}")
7139
e2c953b6 7140(define_insn "*ashldi3_internal1"
44cd321e
PS		 7141 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7142 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7143 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7144 "TARGET_POWERPC64"
44cd321e
PS		 7145 "@
7146 sld %0,%1,%2
7147 sldi %0,%1,%H2"
7148 [(set_attr "type" "var_shift_rotate,shift")])
6ae08853 7149
e2c953b6 7150(define_insn "*ashldi3_internal2"
44cd321e
PS		 7151 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7152 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7153 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7154 (const_int 0)))
44cd321e 7155 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7156 "TARGET_64BIT"
9ebbca7d 7157 "@
44cd321e
PS		 7158 sld. %3,%1,%2
7159 sldi. %3,%1,%H2
7160 #
9ebbca7d 7161 #"
44cd321e
PS		 7162 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7163 (set_attr "length" "4,4,8,8")])
6ae08853 7164
9ebbca7d
GK		 7165(define_split
7166 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7167 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7168 (match_operand:SI 2 "reg_or_cint_operand" ""))
7169 (const_int 0)))
7170 (clobber (match_scratch:DI 3 ""))]
7171 "TARGET_POWERPC64 && reload_completed"
7172 [(set (match_dup 3)
7173 (ashift:DI (match_dup 1) (match_dup 2)))
7174 (set (match_dup 0)
7175 (compare:CC (match_dup 3)
7176 (const_int 0)))]
7177 "")
7178
e2c953b6 7179(define_insn "*ashldi3_internal3"
44cd321e
PS		 7180 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7181 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7182 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7183 (const_int 0)))
44cd321e 7184 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7185 (ashift:DI (match_dup 1) (match_dup 2)))]
683bdff7 7186 "TARGET_64BIT"
9ebbca7d 7187 "@
44cd321e
PS		 7188 sld. %0,%1,%2
7189 sldi. %0,%1,%H2
7190 #
9ebbca7d 7191 #"
44cd321e
PS		 7192 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7193 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7194
7195(define_split
7196 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7197 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7198 (match_operand:SI 2 "reg_or_cint_operand" ""))
7199 (const_int 0)))
7200 (set (match_operand:DI 0 "gpc_reg_operand" "")
7201 (ashift:DI (match_dup 1) (match_dup 2)))]
7202 "TARGET_POWERPC64 && reload_completed"
7203 [(set (match_dup 0)
7204 (ashift:DI (match_dup 1) (match_dup 2)))
7205 (set (match_dup 3)
7206 (compare:CC (match_dup 0)
7207 (const_int 0)))]
7208 "")
266eb58a 7209
e2c953b6 7210(define_insn "*ashldi3_internal4"
3cb999d8
DE		 7211 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7212 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7213 (match_operand:SI 2 "const_int_operand" "i"))
c5059423
AM		 7214 (match_operand:DI 3 "const_int_operand" "n")))]
7215 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
e2c953b6 7216 "rldic %0,%1,%H2,%W3")
3cb999d8 7217
e2c953b6 7218(define_insn "ashldi3_internal5"
9ebbca7d 7219 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3cb999d8 7220 (compare:CC
9ebbca7d
GK		 7221 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7222 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7223 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7224 (const_int 0)))
9ebbca7d 7225 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7226 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7227 "@
e2c953b6 7228 rldic. %4,%1,%H2,%W3
9ebbca7d 7229 #"
9c6fdb46 7230 [(set_attr "type" "compare")
9ebbca7d
GK		 7231 (set_attr "length" "4,8")])
7232
7233(define_split
7234 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7235 (compare:CC
7236 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7237 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7238 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7239 (const_int 0)))
7240 (clobber (match_scratch:DI 4 ""))]
c5059423
AM		 7241 "TARGET_POWERPC64 && reload_completed
7242 && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 7243 [(set (match_dup 4)
7244 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
e2c953b6 7245 (match_dup 3)))
9ebbca7d
GK		 7246 (set (match_dup 0)
7247 (compare:CC (match_dup 4)
7248 (const_int 0)))]
7249 "")
3cb999d8 7250
e2c953b6 7251(define_insn "*ashldi3_internal6"
9ebbca7d 7252 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3cb999d8 7253 (compare:CC
9ebbca7d
GK		 7254 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7255 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7256 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7257 (const_int 0)))
9ebbca7d 7258 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3cb999d8 7259 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7260 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7261 "@
e2c953b6 7262 rldic. %0,%1,%H2,%W3
9ebbca7d 7263 #"
9c6fdb46 7264 [(set_attr "type" "compare")
9ebbca7d
GK		 7265 (set_attr "length" "4,8")])
7266
7267(define_split
7268 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7269 (compare:CC
7270 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7271 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7272 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7273 (const_int 0)))
7274 (set (match_operand:DI 0 "gpc_reg_operand" "")
7275 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
c5059423
AM		 7276 "TARGET_POWERPC64 && reload_completed
7277 && includes_rldic_lshift_p (operands[2], operands[3])"
7278 [(set (match_dup 0)
7279 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7280 (match_dup 3)))
7281 (set (match_dup 4)
7282 (compare:CC (match_dup 0)
7283 (const_int 0)))]
7284 "")
7285
7286(define_insn "*ashldi3_internal7"
7287 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7288 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7289 (match_operand:SI 2 "const_int_operand" "i"))
1990cd79 7290 (match_operand:DI 3 "mask64_operand" "n")))]
c5059423
AM		 7291 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7292 "rldicr %0,%1,%H2,%S3")
7293
7294(define_insn "ashldi3_internal8"
7295 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7296 (compare:CC
7297 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7298 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7299 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7300 (const_int 0)))
7301 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7302 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7303 "@
7304 rldicr. %4,%1,%H2,%S3
7305 #"
9c6fdb46 7306 [(set_attr "type" "compare")
c5059423
AM		 7307 (set_attr "length" "4,8")])
7308
7309(define_split
7310 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7311 (compare:CC
7312 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7313 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7314 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7315 (const_int 0)))
7316 (clobber (match_scratch:DI 4 ""))]
7317 "TARGET_POWERPC64 && reload_completed
7318 && includes_rldicr_lshift_p (operands[2], operands[3])"
7319 [(set (match_dup 4)
7320 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7321 (match_dup 3)))
7322 (set (match_dup 0)
7323 (compare:CC (match_dup 4)
7324 (const_int 0)))]
7325 "")
7326
7327(define_insn "*ashldi3_internal9"
7328 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7329 (compare:CC
7330 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7331 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7332 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7333 (const_int 0)))
7334 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7335 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7336 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7337 "@
7338 rldicr. %0,%1,%H2,%S3
7339 #"
9c6fdb46 7340 [(set_attr "type" "compare")
c5059423
AM		 7341 (set_attr "length" "4,8")])
7342
7343(define_split
7344 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7345 (compare:CC
7346 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7347 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7348 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7349 (const_int 0)))
7350 (set (match_operand:DI 0 "gpc_reg_operand" "")
7351 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7352 "TARGET_POWERPC64 && reload_completed
7353 && includes_rldicr_lshift_p (operands[2], operands[3])"
9ebbca7d 7354 [(set (match_dup 0)
e2c953b6
DE		 7355 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7356 (match_dup 3)))
9ebbca7d
GK		 7357 (set (match_dup 4)
7358 (compare:CC (match_dup 0)
7359 (const_int 0)))]
7360 "")
7361
7362(define_expand "lshrdi3"
266eb58a
DE		 7363 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7364 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7365 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7366 "TARGET_POWERPC64 || TARGET_POWER"
7367 "
7368{
7369 if (TARGET_POWERPC64)
7370 ;
7371 else if (TARGET_POWER)
7372 {
7373 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7374 DONE;
7375 }
7376 else
7377 FAIL;
7378}")
7379
e2c953b6 7380(define_insn "*lshrdi3_internal1"
44cd321e
PS		 7381 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7382 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7383 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7384 "TARGET_POWERPC64"
44cd321e
PS		 7385 "@
7386 srd %0,%1,%2
7387 srdi %0,%1,%H2"
7388 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7389
e2c953b6 7390(define_insn "*lshrdi3_internal2"
44cd321e
PS		 7391 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7392 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7393 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
29ae5b89 7394 (const_int 0)))
44cd321e 7395 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7396 "TARGET_64BIT "
9ebbca7d 7397 "@
44cd321e
PS		 7398 srd. %3,%1,%2
7399 srdi. %3,%1,%H2
7400 #
9ebbca7d 7401 #"
44cd321e
PS		 7402 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7403 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7404
7405(define_split
7406 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7407 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7408 (match_operand:SI 2 "reg_or_cint_operand" ""))
7409 (const_int 0)))
7410 (clobber (match_scratch:DI 3 ""))]
7411 "TARGET_POWERPC64 && reload_completed"
7412 [(set (match_dup 3)
7413 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7414 (set (match_dup 0)
7415 (compare:CC (match_dup 3)
7416 (const_int 0)))]
7417 "")
266eb58a 7418
e2c953b6 7419(define_insn "*lshrdi3_internal3"
44cd321e
PS		 7420 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7421 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7422 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7423 (const_int 0)))
44cd321e 7424 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
29ae5b89 7425 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7426 "TARGET_64BIT"
9ebbca7d 7427 "@
44cd321e
PS		 7428 srd. %0,%1,%2
7429 srdi. %0,%1,%H2
7430 #
9ebbca7d 7431 #"
44cd321e
PS		 7432 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7433 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7434
7435(define_split
7436 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7437 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7438 (match_operand:SI 2 "reg_or_cint_operand" ""))
7439 (const_int 0)))
7440 (set (match_operand:DI 0 "gpc_reg_operand" "")
7441 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7442 "TARGET_POWERPC64 && reload_completed"
7443 [(set (match_dup 0)
7444 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7445 (set (match_dup 3)
7446 (compare:CC (match_dup 0)
7447 (const_int 0)))]
7448 "")
266eb58a
DE		 7449
7450(define_expand "ashrdi3"
7451 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7452 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7453 (match_operand:SI 2 "reg_or_cint_operand" "")))]
97727e85 7454 "WORDS_BIG_ENDIAN"
266eb58a
DE		 7455 "
7456{
7457 if (TARGET_POWERPC64)
7458 ;
7459 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7460 {
7461 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7462 DONE;
7463 }
97727e85
AH		 7464 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7465 && WORDS_BIG_ENDIAN)
4aa74a4f
FS		 7466 {
7467 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7468 DONE;
7469 }
266eb58a
DE		 7470 else
7471 FAIL;
7472}")
7473
e2c953b6 7474(define_insn "*ashrdi3_internal1"
44cd321e
PS		 7475 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7476 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7477 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7478 "TARGET_POWERPC64"
44cd321e
PS		 7479 "@
7480 srad %0,%1,%2
7481 sradi %0,%1,%H2"
7482 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7483
e2c953b6 7484(define_insn "*ashrdi3_internal2"
44cd321e
PS		 7485 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7486 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7487 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7488 (const_int 0)))
44cd321e 7489 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7490 "TARGET_64BIT"
9ebbca7d 7491 "@
44cd321e
PS		 7492 srad. %3,%1,%2
7493 sradi. %3,%1,%H2
7494 #
9ebbca7d 7495 #"
44cd321e
PS		 7496 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7497 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7498
7499(define_split
7500 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7501 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7502 (match_operand:SI 2 "reg_or_cint_operand" ""))
7503 (const_int 0)))
7504 (clobber (match_scratch:DI 3 ""))]
7505 "TARGET_POWERPC64 && reload_completed"
7506 [(set (match_dup 3)
7507 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7508 (set (match_dup 0)
7509 (compare:CC (match_dup 3)
7510 (const_int 0)))]
7511 "")
266eb58a 7512
e2c953b6 7513(define_insn "*ashrdi3_internal3"
44cd321e
PS		 7514 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7515 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7516 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7517 (const_int 0)))
44cd321e 7518 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7519 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7520 "TARGET_64BIT"
9ebbca7d 7521 "@
44cd321e
PS		 7522 srad. %0,%1,%2
7523 sradi. %0,%1,%H2
7524 #
9ebbca7d 7525 #"
44cd321e
PS		 7526 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7527 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7528
7529(define_split
7530 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7531 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7532 (match_operand:SI 2 "reg_or_cint_operand" ""))
7533 (const_int 0)))
7534 (set (match_operand:DI 0 "gpc_reg_operand" "")
7535 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7536 "TARGET_POWERPC64 && reload_completed"
7537 [(set (match_dup 0)
7538 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7539 (set (match_dup 3)
7540 (compare:CC (match_dup 0)
7541 (const_int 0)))]
7542 "")
815cdc52 7543
29ae5b89 7544(define_insn "anddi3"
e1e2e653
NS		 7545 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7546 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7547 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7548 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6ffc8580 7549 "TARGET_POWERPC64"
266eb58a
DE		 7550 "@
7551 and %0,%1,%2
29ae5b89 7552 rldic%B2 %0,%1,0,%S2
e1e2e653 7553 rlwinm %0,%1,0,%m2,%M2
29ae5b89 7554 andi. %0,%1,%b2
0ba1b2ff
AM		 7555 andis. %0,%1,%u2
7556 #"
e1e2e653
NS		 7557 [(set_attr "type" "*,*,*,compare,compare,*")
7558 (set_attr "length" "4,4,4,4,4,8")])
0ba1b2ff
AM		 7559
7560(define_split
7561 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7562 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7563 (match_operand:DI 2 "mask64_2_operand" "")))
7564 (clobber (match_scratch:CC 3 ""))]
7565 "TARGET_POWERPC64
7566 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7567 && !mask_operand (operands[2], DImode)
7568 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7569 [(set (match_dup 0)
7570 (and:DI (rotate:DI (match_dup 1)
7571 (match_dup 4))
7572 (match_dup 5)))
7573 (set (match_dup 0)
7574 (and:DI (rotate:DI (match_dup 0)
7575 (match_dup 6))
7576 (match_dup 7)))]
0ba1b2ff
AM		 7577{
7578 build_mask64_2_operands (operands[2], &operands[4]);
e1e2e653 7579})
266eb58a 7580
a260abc9 7581(define_insn "*anddi3_internal2"
1990cd79
AM		 7582 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7583 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7584 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7585 (const_int 0)))
1990cd79
AM		 7586 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7587 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7588 "TARGET_64BIT"
266eb58a
DE		 7589 "@
7590 and. %3,%1,%2
6c873122 7591 rldic%B2. %3,%1,0,%S2
1990cd79 7592 rlwinm. %3,%1,0,%m2,%M2
6ffc8580
MM		 7593 andi. %3,%1,%b2
7594 andis. %3,%1,%u2
9ebbca7d
GK		 7595 #
7596 #
7597 #
0ba1b2ff
AM		 7598 #
7599 #
1990cd79 7600 #
9ebbca7d 7601 #"
44cd321e 7602 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
1990cd79 7603 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d 7604
0ba1b2ff
AM		 7605(define_split
7606 [(set (match_operand:CC 0 "cc_reg_operand" "")
7607 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7608 (match_operand:DI 2 "mask64_2_operand" ""))
7609 (const_int 0)))
7610 (clobber (match_scratch:DI 3 ""))
7611 (clobber (match_scratch:CC 4 ""))]
1990cd79 7612 "TARGET_64BIT && reload_completed
0ba1b2ff 7613 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7614 && !mask_operand (operands[2], DImode)
7615 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7616 [(set (match_dup 3)
7617 (and:DI (rotate:DI (match_dup 1)
7618 (match_dup 5))
7619 (match_dup 6)))
7620 (parallel [(set (match_dup 0)
7621 (compare:CC (and:DI (rotate:DI (match_dup 3)
7622 (match_dup 7))
7623 (match_dup 8))
7624 (const_int 0)))
7625 (clobber (match_dup 3))])]
7626 "
7627{
7628 build_mask64_2_operands (operands[2], &operands[5]);
7629}")
7630
a260abc9 7631(define_insn "*anddi3_internal3"
1990cd79
AM		 7632 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7633 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7634 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7635 (const_int 0)))
1990cd79 7636 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
9ebbca7d 7637 (and:DI (match_dup 1) (match_dup 2)))
1990cd79 7638 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7639 "TARGET_64BIT"
266eb58a
DE		 7640 "@
7641 and. %0,%1,%2
6c873122 7642 rldic%B2. %0,%1,0,%S2
1990cd79 7643 rlwinm. %0,%1,0,%m2,%M2
6ffc8580
MM		 7644 andi. %0,%1,%b2
7645 andis. %0,%1,%u2
9ebbca7d
GK		 7646 #
7647 #
7648 #
0ba1b2ff
AM		 7649 #
7650 #
1990cd79 7651 #
9ebbca7d 7652 #"
44cd321e 7653 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
1990cd79 7654 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d
GK		 7655
7656(define_split
7657 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7658 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
1990cd79 7659 (match_operand:DI 2 "and64_2_operand" ""))
9ebbca7d
GK		 7660 (const_int 0)))
7661 (set (match_operand:DI 0 "gpc_reg_operand" "")
7662 (and:DI (match_dup 1) (match_dup 2)))
7663 (clobber (match_scratch:CC 4 ""))]
1990cd79 7664 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 7665 [(parallel [(set (match_dup 0)
7666 (and:DI (match_dup 1) (match_dup 2)))
7667 (clobber (match_dup 4))])
7668 (set (match_dup 3)
7669 (compare:CC (match_dup 0)
7670 (const_int 0)))]
7671 "")
266eb58a 7672
0ba1b2ff
AM		 7673(define_split
7674 [(set (match_operand:CC 3 "cc_reg_operand" "")
7675 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7676 (match_operand:DI 2 "mask64_2_operand" ""))
7677 (const_int 0)))
7678 (set (match_operand:DI 0 "gpc_reg_operand" "")
7679 (and:DI (match_dup 1) (match_dup 2)))
7680 (clobber (match_scratch:CC 4 ""))]
1990cd79 7681 "TARGET_64BIT && reload_completed
0ba1b2ff 7682 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7683 && !mask_operand (operands[2], DImode)
7684 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7685 [(set (match_dup 0)
7686 (and:DI (rotate:DI (match_dup 1)
7687 (match_dup 5))
7688 (match_dup 6)))
7689 (parallel [(set (match_dup 3)
7690 (compare:CC (and:DI (rotate:DI (match_dup 0)
7691 (match_dup 7))
7692 (match_dup 8))
7693 (const_int 0)))
7694 (set (match_dup 0)
7695 (and:DI (rotate:DI (match_dup 0)
7696 (match_dup 7))
7697 (match_dup 8)))])]
7698 "
7699{
7700 build_mask64_2_operands (operands[2], &operands[5]);
7701}")
7702
a260abc9 7703(define_expand "iordi3"
266eb58a 7704 [(set (match_operand:DI 0 "gpc_reg_operand" "")
a260abc9 7705 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7706 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
266eb58a 7707 "TARGET_POWERPC64"
266eb58a
DE		 7708 "
7709{
dfbdccdb 7710 if (non_logical_cint_operand (operands[2], DImode))
266eb58a 7711 {
dfbdccdb 7712 HOST_WIDE_INT value;
b3a13419
ILT		 7713 rtx tmp = ((!can_create_pseudo_p ()
7714 || rtx_equal_p (operands[0], operands[1]))
a260abc9 7715 ? operands[0] : gen_reg_rtx (DImode));
266eb58a 7716
dfbdccdb
GK		 7717 if (GET_CODE (operands[2]) == CONST_INT)
7718 {
7719 value = INTVAL (operands[2]);
7720 emit_insn (gen_iordi3 (tmp, operands[1],
7721 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7722 }
e2c953b6 7723 else
dfbdccdb
GK		 7724 {
7725 value = CONST_DOUBLE_LOW (operands[2]);
7726 emit_insn (gen_iordi3 (tmp, operands[1],
7727 immed_double_const (value
7728 & (~ (HOST_WIDE_INT) 0xffff),
7729 0, DImode)));
7730 }
e2c953b6 7731
9ebbca7d
GK		 7732 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7733 DONE;
7734 }
266eb58a
DE		 7735}")
7736
a260abc9
DE		 7737(define_expand "xordi3"
7738 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7739 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7740 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
a260abc9
DE		 7741 "TARGET_POWERPC64"
7742 "
7743{
dfbdccdb 7744 if (non_logical_cint_operand (operands[2], DImode))
a260abc9 7745 {
dfbdccdb 7746 HOST_WIDE_INT value;
b3a13419
ILT		 7747 rtx tmp = ((!can_create_pseudo_p ()
7748 || rtx_equal_p (operands[0], operands[1]))
a260abc9
DE		 7749 ? operands[0] : gen_reg_rtx (DImode));
7750
dfbdccdb
GK		 7751 if (GET_CODE (operands[2]) == CONST_INT)
7752 {
7753 value = INTVAL (operands[2]);
7754 emit_insn (gen_xordi3 (tmp, operands[1],
7755 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7756 }
e2c953b6 7757 else
dfbdccdb
GK		 7758 {
7759 value = CONST_DOUBLE_LOW (operands[2]);
7760 emit_insn (gen_xordi3 (tmp, operands[1],
7761 immed_double_const (value
7762 & (~ (HOST_WIDE_INT) 0xffff),
7763 0, DImode)));
7764 }
e2c953b6 7765
9ebbca7d
GK		 7766 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7767 DONE;
7768 }
a260abc9
DE		 7769}")
7770
dfbdccdb 7771(define_insn "*booldi3_internal1"
266eb58a 7772 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 7773 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7774 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7775 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
266eb58a 7776 "TARGET_POWERPC64"
1fd4e8c1 7777 "@
dfbdccdb
GK		 7778 %q3 %0,%1,%2
7779 %q3i %0,%1,%b2
7780 %q3is %0,%1,%u2")
1fd4e8c1 7781
dfbdccdb 7782(define_insn "*booldi3_internal2"
9ebbca7d 7783 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 7784 (compare:CC (match_operator:DI 4 "boolean_or_operator"
dfbdccdb
GK		 7785 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7786 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7787 (const_int 0)))
9ebbca7d 7788 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7789 "TARGET_64BIT"
9ebbca7d 7790 "@
dfbdccdb 7791 %q4. %3,%1,%2
9ebbca7d
GK		 7792 #"
7793 [(set_attr "type" "compare")
7794 (set_attr "length" "4,8")])
7795
7796(define_split
7797 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7798 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7799 [(match_operand:DI 1 "gpc_reg_operand" "")
7800 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7801 (const_int 0)))
9ebbca7d
GK		 7802 (clobber (match_scratch:DI 3 ""))]
7803 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7804 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7805 (set (match_dup 0)
7806 (compare:CC (match_dup 3)
7807 (const_int 0)))]
7808 "")
1fd4e8c1 7809
dfbdccdb 7810(define_insn "*booldi3_internal3"
9ebbca7d 7811 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7812 (compare:CC (match_operator:DI 4 "boolean_operator"
7813 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7814 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7815 (const_int 0)))
9ebbca7d 7816 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7817 (match_dup 4))]
683bdff7 7818 "TARGET_64BIT"
9ebbca7d 7819 "@
dfbdccdb 7820 %q4. %0,%1,%2
9ebbca7d
GK		 7821 #"
7822 [(set_attr "type" "compare")
7823 (set_attr "length" "4,8")])
7824
7825(define_split
e72247f4 7826 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7827 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7828 [(match_operand:DI 1 "gpc_reg_operand" "")
7829 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7830 (const_int 0)))
75540af0 7831 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7832 (match_dup 4))]
9ebbca7d 7833 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7834 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7835 (set (match_dup 3)
7836 (compare:CC (match_dup 0)
7837 (const_int 0)))]
7838 "")
1fd4e8c1 7839
6ae08853 7840;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 7841;; each of which does one 16-bit part. This is used by combine.
266eb58a
DE		 7842
7843(define_split
7844 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1d328b19 7845 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7846 [(match_operand:DI 1 "gpc_reg_operand" "")
7847 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
266eb58a 7848 "TARGET_POWERPC64"
dfbdccdb
GK		 7849 [(set (match_dup 0) (match_dup 4))
7850 (set (match_dup 0) (match_dup 5))]
266eb58a
DE		 7851"
7852{
dfbdccdb 7853 rtx i3,i4;
6ae08853 7854
9ebbca7d
GK		 7855 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7856 {
7857 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
dfbdccdb 7858 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
9ebbca7d 7859 0, DImode);
dfbdccdb 7860 i4 = GEN_INT (value & 0xffff);
9ebbca7d
GK		 7861 }
7862 else
7863 {
dfbdccdb 7864 i3 = GEN_INT (INTVAL (operands[2])
9ebbca7d 7865 & (~ (HOST_WIDE_INT) 0xffff));
dfbdccdb 7866 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
9ebbca7d 7867 }
1c563bed 7868 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7869 operands[1], i3);
1c563bed 7870 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7871 operands[0], i4);
1fd4e8c1
RK		 7872}")
7873
dfbdccdb 7874(define_insn "*boolcdi3_internal1"
9ebbca7d 7875 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7876 (match_operator:DI 3 "boolean_operator"
7877 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7878 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
a473029f 7879 "TARGET_POWERPC64"
1d328b19 7880 "%q3 %0,%2,%1")
a473029f 7881
dfbdccdb 7882(define_insn "*boolcdi3_internal2"
9ebbca7d 7883 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7884 (compare:CC (match_operator:DI 4 "boolean_operator"
7885 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7886 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7887 (const_int 0)))
9ebbca7d 7888 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7889 "TARGET_64BIT"
9ebbca7d 7890 "@
1d328b19 7891 %q4. %3,%2,%1
9ebbca7d
GK		 7892 #"
7893 [(set_attr "type" "compare")
7894 (set_attr "length" "4,8")])
7895
7896(define_split
7897 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7898 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7899 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7900 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7901 (const_int 0)))
9ebbca7d
GK		 7902 (clobber (match_scratch:DI 3 ""))]
7903 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7904 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7905 (set (match_dup 0)
7906 (compare:CC (match_dup 3)
7907 (const_int 0)))]
7908 "")
a473029f 7909
dfbdccdb 7910(define_insn "*boolcdi3_internal3"
9ebbca7d 7911 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7912 (compare:CC (match_operator:DI 4 "boolean_operator"
7913 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7914 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7915 (const_int 0)))
9ebbca7d 7916 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7917 (match_dup 4))]
683bdff7 7918 "TARGET_64BIT"
9ebbca7d 7919 "@
1d328b19 7920 %q4. %0,%2,%1
9ebbca7d
GK		 7921 #"
7922 [(set_attr "type" "compare")
7923 (set_attr "length" "4,8")])
7924
7925(define_split
e72247f4 7926 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7927 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7928 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7929 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7930 (const_int 0)))
75540af0 7931 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7932 (match_dup 4))]
9ebbca7d 7933 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7934 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7935 (set (match_dup 3)
7936 (compare:CC (match_dup 0)
7937 (const_int 0)))]
7938 "")
266eb58a 7939
dfbdccdb 7940(define_insn "*boolccdi3_internal1"
a473029f 7941 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7942 (match_operator:DI 3 "boolean_operator"
7943 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7944 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
a473029f 7945 "TARGET_POWERPC64"
dfbdccdb 7946 "%q3 %0,%1,%2")
a473029f 7947
dfbdccdb 7948(define_insn "*boolccdi3_internal2"
9ebbca7d 7949 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7950 (compare:CC (match_operator:DI 4 "boolean_operator"
7951 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7952 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7953 (const_int 0)))
9ebbca7d 7954 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7955 "TARGET_64BIT"
9ebbca7d 7956 "@
dfbdccdb 7957 %q4. %3,%1,%2
9ebbca7d
GK		 7958 #"
7959 [(set_attr "type" "compare")
7960 (set_attr "length" "4,8")])
7961
7962(define_split
7963 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7964 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7965 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7966 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7967 (const_int 0)))
9ebbca7d
GK		 7968 (clobber (match_scratch:DI 3 ""))]
7969 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7970 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7971 (set (match_dup 0)
7972 (compare:CC (match_dup 3)
7973 (const_int 0)))]
7974 "")
266eb58a 7975
dfbdccdb 7976(define_insn "*boolccdi3_internal3"
9ebbca7d 7977 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7978 (compare:CC (match_operator:DI 4 "boolean_operator"
7979 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7980 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7981 (const_int 0)))
9ebbca7d 7982 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7983 (match_dup 4))]
683bdff7 7984 "TARGET_64BIT"
9ebbca7d 7985 "@
dfbdccdb 7986 %q4. %0,%1,%2
9ebbca7d
GK		 7987 #"
7988 [(set_attr "type" "compare")
7989 (set_attr "length" "4,8")])
7990
7991(define_split
e72247f4 7992 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7993 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7994 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7995 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7996 (const_int 0)))
75540af0 7997 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7998 (match_dup 4))]
9ebbca7d 7999 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 8000 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 8001 (set (match_dup 3)
8002 (compare:CC (match_dup 0)
8003 (const_int 0)))]
8004 "")
dfbdccdb 8005\f
1fd4e8c1 8006;; Now define ways of moving data around.
4697a36c 8007
766a866c
MM		 8008;; Set up a register with a value from the GOT table
8009
8010(define_expand "movsi_got"
52d3af72 8011 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 8012 (unspec:SI [(match_operand:SI 1 "got_operand" "")
615158e2 8013 (match_dup 2)] UNSPEC_MOVSI_GOT))]
f607bc57 8014 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 8015 "
8016{
38c1f2d7
MM		 8017 if (GET_CODE (operands[1]) == CONST)
8018 {
8019 rtx offset = const0_rtx;
8020 HOST_WIDE_INT value;
8021
8022 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8023 value = INTVAL (offset);
8024 if (value != 0)
8025 {
b3a13419
ILT		 8026 rtx tmp = (!can_create_pseudo_p ()
8027 ? operands[0]
8028 : gen_reg_rtx (Pmode));
38c1f2d7
MM		 8029 emit_insn (gen_movsi_got (tmp, operands[1]));
8030 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8031 DONE;
8032 }
8033 }
8034
c4c40373 8035 operands[2] = rs6000_got_register (operands[1]);
766a866c
MM		 8036}")
8037
84f414bc 8038(define_insn "*movsi_got_internal"
52d3af72 8039 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9ebbca7d 8040 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 8041 (match_operand:SI 2 "gpc_reg_operand" "b")]
8042 UNSPEC_MOVSI_GOT))]
f607bc57 8043 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 8044 "{l|lwz} %0,%a1@got(%2)"
8045 [(set_attr "type" "load")])
8046
b22b9b3e
JL		 8047;; Used by sched, shorten_branches and final when the GOT pseudo reg
8048;; didn't get allocated to a hard register.
6ae08853 8049(define_split
75540af0 8050 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 8051 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 8052 (match_operand:SI 2 "memory_operand" "")]
8053 UNSPEC_MOVSI_GOT))]
f607bc57 8054 "DEFAULT_ABI == ABI_V4
b22b9b3e
JL		 8055 && flag_pic == 1
8056 && (reload_in_progress || reload_completed)"
8057 [(set (match_dup 0) (match_dup 2))
615158e2
JJ		 8058 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8059 UNSPEC_MOVSI_GOT))]
b22b9b3e
JL		 8060 "")
8061
1fd4e8c1
RK		 8062;; For SI, we special-case integers that can't be loaded in one insn. We
8063;; do the load 16-bits at a time. We could do this by loading from memory,
8064;; and this is even supposed to be faster, but it is simpler not to get
8065;; integers in the TOC.
ee890fe2
SS		 8066(define_insn "movsi_low"
8067 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
f585a356 8068 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
ee890fe2
SS		 8069 (match_operand 2 "" ""))))]
8070 "TARGET_MACHO && ! TARGET_64BIT"
8071 "{l|lwz} %0,lo16(%2)(%1)"
8072 [(set_attr "type" "load")
8073 (set_attr "length" "4")])
8074
acad7ed3 8075(define_insn "*movsi_internal1"
165a5bad 8076 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
a004eb82 8077 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
19d5775a
RK		 8078 "gpc_reg_operand (operands[0], SImode)
8079 || gpc_reg_operand (operands[1], SImode)"
1fd4e8c1 8080 "@
deb9225a 8081 mr %0,%1
b9442c72 8082 {cal|la} %0,%a1
ca7f5001
RK		 8083 {l%U1%X1|lwz%U1%X1} %0,%1
8084 {st%U0%X0|stw%U0%X0} %1,%0
19d5775a 8085 {lil|li} %0,%1
802a0058 8086 {liu|lis} %0,%v1
beaec479 8087 #
aee86b38 8088 {cal|la} %0,%a1
1fd4e8c1 8089 mf%1 %0
5c23c401 8090 mt%0 %1
e76e75bb 8091 mt%0 %1
a004eb82 8092 mt%0 %1
e34eaae5 8093 {cror 0,0,0|nop}"
02ca7595 8094 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
a004eb82 8095 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
1fd4e8c1 8096
77fa0940
RK		 8097;; Split a load of a large constant into the appropriate two-insn
8098;; sequence.
8099
8100(define_split
8101 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8102 (match_operand:SI 1 "const_int_operand" ""))]
bb21487f 8103 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
77fa0940
RK		 8104 && (INTVAL (operands[1]) & 0xffff) != 0"
8105 [(set (match_dup 0)
8106 (match_dup 2))
8107 (set (match_dup 0)
8108 (ior:SI (match_dup 0)
8109 (match_dup 3)))]
8110 "
af8cb5c5
DE		 8111{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8112
8113 if (tem == operands[0])
8114 DONE;
8115 else
8116 FAIL;
77fa0940
RK		 8117}")
8118
4ae234b0 8119(define_insn "*mov<mode>_internal2"
bb84cb12 8120 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
4ae234b0 8121 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
1fd4e8c1 8122 (const_int 0)))
4ae234b0
GK		 8123 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8124 ""
9ebbca7d 8125 "@
4ae234b0 8126 {cmpi|cmp<wd>i} %2,%0,0
9ebbca7d
GK		 8127 mr. %0,%1
8128 #"
bb84cb12
DE		 8129 [(set_attr "type" "cmp,compare,cmp")
8130 (set_attr "length" "4,4,8")])
8131
9ebbca7d
GK		 8132(define_split
8133 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
4ae234b0 8134 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9ebbca7d 8135 (const_int 0)))
4ae234b0
GK		 8136 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8137 "reload_completed"
9ebbca7d
GK		 8138 [(set (match_dup 0) (match_dup 1))
8139 (set (match_dup 2)
8140 (compare:CC (match_dup 0)
8141 (const_int 0)))]
8142 "")
bb84cb12 8143\f
e34eaae5 8144(define_insn "*movhi_internal"
fb81d7ce
RK		 8145 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8146 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8147 "gpc_reg_operand (operands[0], HImode)
8148 || gpc_reg_operand (operands[1], HImode)"
1fd4e8c1 8149 "@
deb9225a 8150 mr %0,%1
1fd4e8c1
RK		 8151 lhz%U1%X1 %0,%1
8152 sth%U0%X0 %1,%0
19d5775a 8153 {lil|li} %0,%w1
1fd4e8c1 8154 mf%1 %0
e76e75bb 8155 mt%0 %1
fb81d7ce 8156 mt%0 %1
e34eaae5 8157 {cror 0,0,0|nop}"
02ca7595 8158 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1 8159
4ae234b0
GK		 8160(define_expand "mov<mode>"
8161 [(set (match_operand:INT 0 "general_operand" "")
8162 (match_operand:INT 1 "any_operand" ""))]
1fd4e8c1 8163 ""
4ae234b0 8164 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
1fd4e8c1 8165
e34eaae5 8166(define_insn "*movqi_internal"
fb81d7ce
RK		 8167 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8168 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8169 "gpc_reg_operand (operands[0], QImode)
8170 || gpc_reg_operand (operands[1], QImode)"
1fd4e8c1 8171 "@
deb9225a 8172 mr %0,%1
1fd4e8c1
RK		 8173 lbz%U1%X1 %0,%1
8174 stb%U0%X0 %1,%0
19d5775a 8175 {lil|li} %0,%1
1fd4e8c1 8176 mf%1 %0
e76e75bb 8177 mt%0 %1
fb81d7ce 8178 mt%0 %1
e34eaae5 8179 {cror 0,0,0|nop}"
02ca7595 8180 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1
RK		 8181\f
8182;; Here is how to move condition codes around. When we store CC data in
8183;; an integer register or memory, we store just the high-order 4 bits.
8184;; This lets us not shift in the most common case of CR0.
8185(define_expand "movcc"
8186 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8187 (match_operand:CC 1 "nonimmediate_operand" ""))]
8188 ""
8189 "")
8190
a65c591c 8191(define_insn "*movcc_internal1"
4eb585a4
DE		 8192 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8193 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
1fd4e8c1
RK		 8194 "register_operand (operands[0], CCmode)
8195 || register_operand (operands[1], CCmode)"
8196 "@
8197 mcrf %0,%1
8198 mtcrf 128,%1
ca7f5001 8199 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
4eb585a4 8200 crxor %0,%0,%0
2c4a9cff
DE		 8201 mfcr %0%Q1
8202 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
deb9225a 8203 mr %0,%1
4eb585a4 8204 {lil|li} %0,%1
b54cf83a 8205 mf%1 %0
b991a865
GK		 8206 mt%0 %1
8207 mt%0 %1
ca7f5001
RK		 8208 {l%U1%X1|lwz%U1%X1} %0,%1
8209 {st%U0%U1|stw%U0%U1} %1,%0"
2c4a9cff 8210 [(set (attr "type")
4eb585a4 8211 (cond [(eq_attr "alternative" "0,3")
2c4a9cff
DE		 8212 (const_string "cr_logical")
8213 (eq_attr "alternative" "1,2")
8214 (const_string "mtcr")
4eb585a4 8215 (eq_attr "alternative" "6,7,9")
2c4a9cff 8216 (const_string "integer")
2c4a9cff 8217 (eq_attr "alternative" "8")
4eb585a4
DE		 8218 (const_string "mfjmpr")
8219 (eq_attr "alternative" "10")
2c4a9cff 8220 (const_string "mtjmpr")
4eb585a4 8221 (eq_attr "alternative" "11")
2c4a9cff 8222 (const_string "load")
4eb585a4 8223 (eq_attr "alternative" "12")
2c4a9cff
DE		 8224 (const_string "store")
8225 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8226 (const_string "mfcrf")
8227 ]
8228 (const_string "mfcr")))
4eb585a4 8229 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
1fd4e8c1 8230\f
e52e05ca
MM		 8231;; For floating-point, we normally deal with the floating-point registers
8232;; unless -msoft-float is used. The sole exception is that parameter passing
8233;; can produce floating-point values in fixed-point registers. Unless the
8234;; value is a simple constant or already in memory, we deal with this by
8235;; allocating memory and copying the value explicitly via that memory location.
1fd4e8c1
RK		 8236(define_expand "movsf"
8237 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8238 (match_operand:SF 1 "any_operand" ""))]
8239 ""
fb4d4348 8240 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
1fd4e8c1 8241
1fd4e8c1 8242(define_split
cd2b37d9 8243 [(set (match_operand:SF 0 "gpc_reg_operand" "")
c4c40373 8244 (match_operand:SF 1 "const_double_operand" ""))]
f99f88e0 8245 "reload_completed
5ae4759c
MM		 8246 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8247 || (GET_CODE (operands[0]) == SUBREG
8248 && GET_CODE (SUBREG_REG (operands[0])) == REG
8249 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373 8250 [(set (match_dup 2) (match_dup 3))]
685f3906
DE		 8251 "
8252{
8253 long l;
8254 REAL_VALUE_TYPE rv;
8255
8256 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8257 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
c4c40373 8258
f99f88e0
DE		 8259 if (! TARGET_POWERPC64)
8260 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8261 else
8262 operands[2] = gen_lowpart (SImode, operands[0]);
a260abc9 8263
2496c7bd 8264 operands[3] = gen_int_mode (l, SImode);
a260abc9
DE		 8265}")
8266
c4c40373 8267(define_insn "*movsf_hardfloat"
fb3249ef 8268 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
ae6669e7 8269 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
d14a6d05 8270 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 8271 || gpc_reg_operand (operands[1], SFmode))
8272 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
1fd4e8c1 8273 "@
f99f88e0
DE		 8274 mr %0,%1
8275 {l%U1%X1|lwz%U1%X1} %0,%1
8276 {st%U0%X0|stw%U0%X0} %1,%0
1fd4e8c1
RK		 8277 fmr %0,%1
8278 lfs%U1%X1 %0,%1
c4c40373 8279 stfs%U0%X0 %1,%0
b991a865
GK		 8280 mt%0 %1
8281 mt%0 %1
8282 mf%1 %0
e0740893 8283 {cror 0,0,0|nop}
c4c40373
MM		 8284 #
8285 #"
9c6fdb46 8286 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
ae6669e7 8287 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
d14a6d05 8288
c4c40373 8289(define_insn "*movsf_softfloat"
dd0fbae2
MK		 8290 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8291 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
d14a6d05 8292 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 8293 || gpc_reg_operand (operands[1], SFmode))
8294 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
d14a6d05
MM		 8295 "@
8296 mr %0,%1
b991a865
GK		 8297 mt%0 %1
8298 mt%0 %1
8299 mf%1 %0
d14a6d05
MM		 8300 {l%U1%X1|lwz%U1%X1} %0,%1
8301 {st%U0%X0|stw%U0%X0} %1,%0
8302 {lil|li} %0,%1
802a0058 8303 {liu|lis} %0,%v1
aee86b38 8304 {cal|la} %0,%a1
c4c40373 8305 #
dd0fbae2
MK		 8306 #
8307 {cror 0,0,0|nop}"
9c6fdb46 8308 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
dd0fbae2 8309 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
d14a6d05 8310
1fd4e8c1
RK		 8311\f
8312(define_expand "movdf"
8313 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8314 (match_operand:DF 1 "any_operand" ""))]
8315 ""
fb4d4348 8316 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
1fd4e8c1
RK		 8317
8318(define_split
cd2b37d9 8319 [(set (match_operand:DF 0 "gpc_reg_operand" "")
c4c40373 8320 (match_operand:DF 1 "const_int_operand" ""))]
a260abc9 8321 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8322 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8323 || (GET_CODE (operands[0]) == SUBREG
8324 && GET_CODE (SUBREG_REG (operands[0])) == REG
8325 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8326 [(set (match_dup 2) (match_dup 4))
8327 (set (match_dup 3) (match_dup 1))]
8328 "
8329{
5ae4759c 8330 int endian = (WORDS_BIG_ENDIAN == 0);
5f59ecb7
DE		 8331 HOST_WIDE_INT value = INTVAL (operands[1]);
8332
5ae4759c
MM		 8333 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8334 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5f59ecb7
DE		 8335#if HOST_BITS_PER_WIDE_INT == 32
8336 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8337#else
8338 operands[4] = GEN_INT (value >> 32);
a65c591c 8339 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
5f59ecb7 8340#endif
c4c40373
MM		 8341}")
8342
c4c40373
MM		 8343(define_split
8344 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8345 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8346 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8347 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8348 || (GET_CODE (operands[0]) == SUBREG
8349 && GET_CODE (SUBREG_REG (operands[0])) == REG
8350 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8351 [(set (match_dup 2) (match_dup 4))
8352 (set (match_dup 3) (match_dup 5))]
8353 "
8354{
5ae4759c 8355 int endian = (WORDS_BIG_ENDIAN == 0);
47ad8c61
MM		 8356 long l[2];
8357 REAL_VALUE_TYPE rv;
8358
8359 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8360 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8361
5ae4759c
MM		 8362 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8363 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
2496c7bd
LB		 8364 operands[4] = gen_int_mode (l[endian], SImode);
8365 operands[5] = gen_int_mode (l[1 - endian], SImode);
c4c40373
MM		 8366}")
8367
efc08378
DE		 8368(define_split
8369 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8308679f 8370 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8371 "TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8372 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8373 || (GET_CODE (operands[0]) == SUBREG
8374 && GET_CODE (SUBREG_REG (operands[0])) == REG
8375 && REGNO (SUBREG_REG (operands[0])) <= 31))"
a260abc9 8376 [(set (match_dup 2) (match_dup 3))]
5ae4759c 8377 "
a260abc9
DE		 8378{
8379 int endian = (WORDS_BIG_ENDIAN == 0);
8380 long l[2];
8381 REAL_VALUE_TYPE rv;
4977bab6 8382#if HOST_BITS_PER_WIDE_INT >= 64
5b029315 8383 HOST_WIDE_INT val;
4977bab6 8384#endif
a260abc9
DE		 8385
8386 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8387 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8388
8389 operands[2] = gen_lowpart (DImode, operands[0]);
8390 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
5b029315 8391#if HOST_BITS_PER_WIDE_INT >= 64
a2419b96
DE		 8392 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8393 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
5b029315 8394
f5264b52 8395 operands[3] = gen_int_mode (val, DImode);
5b029315 8396#else
a260abc9 8397 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
5b029315 8398#endif
a260abc9 8399}")
efc08378 8400
4eae5fe1 8401;; Don't have reload use general registers to load a constant. First,
1427100a 8402;; it might not work if the output operand is the equivalent of
4eae5fe1
RK		 8403;; a non-offsettable memref, but also it is less efficient than loading
8404;; the constant into an FP register, since it will probably be used there.
8405;; The "??" is a kludge until we can figure out a more reasonable way
8406;; of handling these non-offsettable values.
c4c40373 8407(define_insn "*movdf_hardfloat32"
914a7297
DE		 8408 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8409 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
a3170dc6 8410 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8411 && (gpc_reg_operand (operands[0], DFmode)
8412 || gpc_reg_operand (operands[1], DFmode))"
e7113111
RK		 8413 "*
8414{
8415 switch (which_alternative)
8416 {
a260abc9 8417 default:
37409796 8418 gcc_unreachable ();
e7113111
RK		 8419 case 0:
8420 /* We normally copy the low-numbered register first. However, if
000034eb
DE		 8421 the first register operand 0 is the same as the second register
8422 of operand 1, we must copy in the opposite order. */
e7113111 8423 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
deb9225a 8424 return \"mr %L0,%L1\;mr %0,%1\";
e7113111 8425 else
deb9225a 8426 return \"mr %0,%1\;mr %L0,%L1\";
e7113111 8427 case 1:
d04b6e6e
EB		 8428 if (rs6000_offsettable_memref_p (operands[1])
8429 || (GET_CODE (operands[1]) == MEM
8430 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8431 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
6fb5fa3c
DB		 8432 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8433 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
000034eb
DE		 8434 {
8435 /* If the low-address word is used in the address, we must load
8436 it last. Otherwise, load it first. Note that we cannot have
8437 auto-increment in that case since the address register is
8438 known to be dead. */
8439 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8440 operands[1], 0))
8441 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8442 else
6fb5fa3c 8443 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
000034eb 8444 }
e7113111 8445 else
000034eb
DE		 8446 {
8447 rtx addreg;
8448
000034eb
DE		 8449 addreg = find_addr_reg (XEXP (operands[1], 0));
8450 if (refers_to_regno_p (REGNO (operands[0]),
8451 REGNO (operands[0]) + 1,
8452 operands[1], 0))
8453 {
8454 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8455 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb 8456 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
2284bd2b 8457 return \"{l%X1|lwz%X1} %0,%1\";
000034eb
DE		 8458 }
8459 else
8460 {
2284bd2b 8461 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
000034eb 8462 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8463 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb
DE		 8464 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8465 return \"\";
8466 }
8467 }
e7113111 8468 case 2:
d04b6e6e
EB		 8469 if (rs6000_offsettable_memref_p (operands[0])
8470 || (GET_CODE (operands[0]) == MEM
8471 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8472 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
6fb5fa3c
DB		 8473 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8474 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8475 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
000034eb
DE		 8476 else
8477 {
8478 rtx addreg;
8479
000034eb 8480 addreg = find_addr_reg (XEXP (operands[0], 0));
2284bd2b 8481 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
000034eb 8482 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8483 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
000034eb
DE		 8484 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8485 return \"\";
8486 }
e7113111 8487 case 3:
914a7297 8488 return \"fmr %0,%1\";
e7113111 8489 case 4:
914a7297 8490 return \"lfd%U1%X1 %0,%1\";
e7113111 8491 case 5:
914a7297 8492 return \"stfd%U0%X0 %1,%0\";
e7113111 8493 case 6:
c4c40373 8494 case 7:
c4c40373 8495 case 8:
914a7297 8496 return \"#\";
e7113111
RK		 8497 }
8498}"
943c15ed 8499 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
914a7297 8500 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
51b8fc2c 8501
c4c40373 8502(define_insn "*movdf_softfloat32"
1427100a
DE		 8503 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8504 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7a2f7870 8505 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
52d3af72
DE		 8506 && (gpc_reg_operand (operands[0], DFmode)
8507 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca
MM		 8508 "*
8509{
8510 switch (which_alternative)
8511 {
a260abc9 8512 default:
37409796 8513 gcc_unreachable ();
dc4f83ca
MM		 8514 case 0:
8515 /* We normally copy the low-numbered register first. However, if
8516 the first register operand 0 is the same as the second register of
8517 operand 1, we must copy in the opposite order. */
8518 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8519 return \"mr %L0,%L1\;mr %0,%1\";
8520 else
8521 return \"mr %0,%1\;mr %L0,%L1\";
8522 case 1:
3cb999d8
DE		 8523 /* If the low-address word is used in the address, we must load
8524 it last. Otherwise, load it first. Note that we cannot have
8525 auto-increment in that case since the address register is
8526 known to be dead. */
dc4f83ca 8527 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3cb999d8 8528 operands[1], 0))
dc4f83ca
MM		 8529 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8530 else
6fb5fa3c 8531 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
dc4f83ca 8532 case 2:
6fb5fa3c 8533 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
dc4f83ca 8534 case 3:
c4c40373
MM		 8535 case 4:
8536 case 5:
dc4f83ca
MM		 8537 return \"#\";
8538 }
8539}"
943c15ed 8540 [(set_attr "type" "two,load,store,*,*,*")
c4c40373 8541 (set_attr "length" "8,8,8,8,12,16")])
dc4f83ca 8542
44cd321e
PS		 8543; ld/std require word-aligned displacements -> 'Y' constraint.
8544; List Y->r and r->Y before r->r for reload.
8545(define_insn "*movdf_hardfloat64_mfpgpr"
8546 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8547 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
8548 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8549 && (gpc_reg_operand (operands[0], DFmode)
8550 || gpc_reg_operand (operands[1], DFmode))"
8551 "@
8552 std%U0%X0 %1,%0
8553 ld%U1%X1 %0,%1
8554 mr %0,%1
8555 fmr %0,%1
8556 lfd%U1%X1 %0,%1
8557 stfd%U0%X0 %1,%0
8558 mt%0 %1
8559 mf%1 %0
8560 {cror 0,0,0|nop}
8561 #
8562 #
8563 #
8564 mftgpr %0,%1
8565 mffgpr %0,%1"
8566 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8567 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8568
d2288d5d
HP		 8569; ld/std require word-aligned displacements -> 'Y' constraint.
8570; List Y->r and r->Y before r->r for reload.
c4c40373 8571(define_insn "*movdf_hardfloat64"
fb3249ef 8572 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
ae6669e7 8573 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
44cd321e 8574 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8575 && (gpc_reg_operand (operands[0], DFmode)
8576 || gpc_reg_operand (operands[1], DFmode))"
51b8fc2c 8577 "@
96bb8ed3 8578 std%U0%X0 %1,%0
3364872d
FJ		 8579 ld%U1%X1 %0,%1
8580 mr %0,%1
3d5570cb 8581 fmr %0,%1
f63184ac 8582 lfd%U1%X1 %0,%1
914a7297
DE		 8583 stfd%U0%X0 %1,%0
8584 mt%0 %1
8585 mf%1 %0
e0740893 8586 {cror 0,0,0|nop}
914a7297
DE		 8587 #
8588 #
8589 #"
9c6fdb46 8590 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
ae6669e7 8591 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
dc4f83ca 8592
c4c40373 8593(define_insn "*movdf_softfloat64"
d2288d5d
HP		 8594 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8595 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
a3170dc6 8596 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
52d3af72
DE		 8597 && (gpc_reg_operand (operands[0], DFmode)
8598 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca 8599 "@
d2288d5d
HP		 8600 ld%U1%X1 %0,%1
8601 std%U0%X0 %1,%0
dc4f83ca 8602 mr %0,%1
914a7297
DE		 8603 mt%0 %1
8604 mf%1 %0
c4c40373
MM		 8605 #
8606 #
e2d0915c 8607 #
e0740893 8608 {cror 0,0,0|nop}"
9c6fdb46 8609 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
e2d0915c 8610 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
1fd4e8c1 8611\f
06f4e019
DE		 8612(define_expand "movtf"
8613 [(set (match_operand:TF 0 "general_operand" "")
8614 (match_operand:TF 1 "any_operand" ""))]
8521c414 8615 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8616 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8617
a9baceb1
GK		 8618; It's important to list the o->f and f->o moves before f->f because
8619; otherwise reload, given m->f, will try to pick f->f and reload it,
409f61cd 8620; which doesn't make progress. Likewise r->Y must be before r->r.
a9baceb1 8621(define_insn_and_split "*movtf_internal"
409f61cd
AM		 8622 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8623 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
602ea4d3 8624 "!TARGET_IEEEQUAD
39e63627 8625 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
06f4e019
DE		 8626 && (gpc_reg_operand (operands[0], TFmode)
8627 || gpc_reg_operand (operands[1], TFmode))"
a9baceb1 8628 "#"
ecb62ae7 8629 "&& reload_completed"
a9baceb1
GK		 8630 [(pc)]
8631{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
112ccb83 8632 [(set_attr "length" "8,8,8,20,20,16")])
06f4e019 8633
8521c414 8634(define_insn_and_split "*movtf_softfloat"
17caeff2 8635 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8521c414
JM		 8636 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8637 "!TARGET_IEEEQUAD
8638 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8639 && (gpc_reg_operand (operands[0], TFmode)
8640 || gpc_reg_operand (operands[1], TFmode))"
8641 "#"
8642 "&& reload_completed"
8643 [(pc)]
8644{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8645 [(set_attr "length" "20,20,16")])
8646
ecb62ae7 8647(define_expand "extenddftf2"
17caeff2
JM		 8648 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8649 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8650 "!TARGET_IEEEQUAD
8651 && TARGET_HARD_FLOAT
8652 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8653 && TARGET_LONG_DOUBLE_128"
8654{
8655 if (TARGET_E500_DOUBLE)
8656 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8657 else
8658 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8659 DONE;
8660})
8661
8662(define_expand "extenddftf2_fprs"
ecb62ae7
GK		 8663 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8664 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8665 (use (match_dup 2))])]
602ea4d3 8666 "!TARGET_IEEEQUAD
39e63627 8667 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8668{
ecb62ae7 8669 operands[2] = CONST0_RTX (DFmode);
aa9cf005
DE		 8670 /* Generate GOT reference early for SVR4 PIC. */
8671 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8672 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
ecb62ae7 8673})
06f4e019 8674
ecb62ae7
GK		 8675(define_insn_and_split "*extenddftf2_internal"
8676 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8677 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
97c54d9a 8678 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
602ea4d3 8679 "!TARGET_IEEEQUAD
39e63627 8680 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8681 "#"
8682 "&& reload_completed"
8683 [(pc)]
06f4e019 8684{
ecb62ae7
GK		 8685 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8686 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8687 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8688 operands[1]);
8689 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8690 operands[2]);
8691 DONE;
6ae08853 8692})
ecb62ae7
GK		 8693
8694(define_expand "extendsftf2"
8695 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8696 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
602ea4d3 8697 "!TARGET_IEEEQUAD
17caeff2
JM		 8698 && TARGET_HARD_FLOAT
8699 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8700 && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8701{
8702 rtx tmp = gen_reg_rtx (DFmode);
8703 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8704 emit_insn (gen_extenddftf2 (operands[0], tmp));
8705 DONE;
8706})
06f4e019 8707
8cb320b8 8708(define_expand "trunctfdf2"
589b3fda
DE		 8709 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8710 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 8711 "!TARGET_IEEEQUAD
17caeff2
JM		 8712 && TARGET_HARD_FLOAT
8713 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8714 && TARGET_LONG_DOUBLE_128"
589b3fda 8715 "")
8cb320b8
DE		 8716
8717(define_insn_and_split "trunctfdf2_internal1"
8718 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8719 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
602ea4d3 8720 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8cb320b8
DE		 8721 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8722 "@
8723 #
8724 fmr %0,%1"
8725 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8726 [(const_int 0)]
8727{
8728 emit_note (NOTE_INSN_DELETED);
8729 DONE;
8730}
8731 [(set_attr "type" "fp")])
8732
8733(define_insn "trunctfdf2_internal2"
8734 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8735 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
602ea4d3 8736 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8cb320b8 8737 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8738 "fadd %0,%1,%L1"
8cb320b8 8739 [(set_attr "type" "fp")])
06f4e019 8740
17caeff2
JM		 8741(define_expand "trunctfsf2"
8742 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8743 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8744 "!TARGET_IEEEQUAD
8745 && TARGET_HARD_FLOAT
8746 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8747 && TARGET_LONG_DOUBLE_128"
8748{
8749 if (TARGET_E500_DOUBLE)
8750 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8751 else
8752 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8753 DONE;
8754})
8755
8756(define_insn_and_split "trunctfsf2_fprs"
06f4e019 8757 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
ea112fc4
DE		 8758 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8759 (clobber (match_scratch:DF 2 "=f"))]
602ea4d3 8760 "!TARGET_IEEEQUAD
39e63627 8761 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8762 "#"
ea112fc4 8763 "&& reload_completed"
06f4e019
DE		 8764 [(set (match_dup 2)
8765 (float_truncate:DF (match_dup 1)))
8766 (set (match_dup 0)
8767 (float_truncate:SF (match_dup 2)))]
ea112fc4 8768 "")
06f4e019 8769
0c90aa3c 8770(define_expand "floatsitf2"
d29b7f64
DE		 8771 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8772 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
602ea4d3 8773 "!TARGET_IEEEQUAD
17caeff2
JM		 8774 && TARGET_HARD_FLOAT
8775 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8776 && TARGET_LONG_DOUBLE_128"
0c90aa3c
GK		 8777{
8778 rtx tmp = gen_reg_rtx (DFmode);
8779 expand_float (tmp, operands[1], false);
8780 emit_insn (gen_extenddftf2 (operands[0], tmp));
8781 DONE;
8782})
06f4e019 8783
ecb62ae7
GK		 8784; fadd, but rounding towards zero.
8785; This is probably not the optimal code sequence.
8786(define_insn "fix_trunc_helper"
8787 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8788 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8789 UNSPEC_FIX_TRUNC_TF))
8790 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8791 "TARGET_HARD_FLOAT && TARGET_FPRS"
8792 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8793 [(set_attr "type" "fp")
8794 (set_attr "length" "20")])
8795
0c90aa3c 8796(define_expand "fix_trunctfsi2"
17caeff2
JM		 8797 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8798 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8799 "!TARGET_IEEEQUAD
8800 && (TARGET_POWER2 || TARGET_POWERPC)
8801 && TARGET_HARD_FLOAT
8802 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8803 && TARGET_LONG_DOUBLE_128"
8804{
8805 if (TARGET_E500_DOUBLE)
8806 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8807 else
8808 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8809 DONE;
8810})
8811
8812(define_expand "fix_trunctfsi2_fprs"
ecb62ae7
GK		 8813 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8814 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8815 (clobber (match_dup 2))
8816 (clobber (match_dup 3))
8817 (clobber (match_dup 4))
8818 (clobber (match_dup 5))])]
602ea4d3 8819 "!TARGET_IEEEQUAD
ecb62ae7
GK		 8820 && (TARGET_POWER2 || TARGET_POWERPC)
8821 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8822{
8823 operands[2] = gen_reg_rtx (DFmode);
8824 operands[3] = gen_reg_rtx (DFmode);
8825 operands[4] = gen_reg_rtx (DImode);
8826 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8827})
8828
8829(define_insn_and_split "*fix_trunctfsi2_internal"
61c07d3c 8830 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
ecb62ae7
GK		 8831 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8832 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8833 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8834 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
b0d6c7d8 8835 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
602ea4d3 8836 "!TARGET_IEEEQUAD
39e63627 8837 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 8838 "#"
b3a13419 8839 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
ecb62ae7 8840 [(pc)]
0c90aa3c 8841{
ecb62ae7
GK		 8842 rtx lowword;
8843 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8844
230215f5
GK		 8845 gcc_assert (MEM_P (operands[5]));
8846 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
ecb62ae7
GK		 8847
8848 emit_insn (gen_fctiwz (operands[4], operands[2]));
8849 emit_move_insn (operands[5], operands[4]);
230215f5 8850 emit_move_insn (operands[0], lowword);
0c90aa3c
GK		 8851 DONE;
8852})
06f4e019 8853
17caeff2
JM		 8854(define_expand "negtf2"
8855 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8856 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8857 "!TARGET_IEEEQUAD
8858 && TARGET_HARD_FLOAT
8859 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8860 && TARGET_LONG_DOUBLE_128"
8861 "")
8862
8863(define_insn "negtf2_internal"
06f4e019
DE		 8864 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8865 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
602ea4d3 8866 "!TARGET_IEEEQUAD
39e63627 8867 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8868 "*
8869{
8870 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8871 return \"fneg %L0,%L1\;fneg %0,%1\";
8872 else
8873 return \"fneg %0,%1\;fneg %L0,%L1\";
8874}"
8875 [(set_attr "type" "fp")
8876 (set_attr "length" "8")])
8877
1a402dc1 8878(define_expand "abstf2"
17caeff2
JM		 8879 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8880 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 8881 "!TARGET_IEEEQUAD
17caeff2
JM		 8882 && TARGET_HARD_FLOAT
8883 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8884 && TARGET_LONG_DOUBLE_128"
1a402dc1 8885 "
06f4e019 8886{
1a402dc1 8887 rtx label = gen_label_rtx ();
17caeff2
JM		 8888 if (TARGET_E500_DOUBLE)
8889 {
8890 if (flag_unsafe_math_optimizations)
8891 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8892 else
8893 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8894 }
8895 else
8896 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
1a402dc1
AM		 8897 emit_label (label);
8898 DONE;
8899}")
06f4e019 8900
1a402dc1 8901(define_expand "abstf2_internal"
e42ac3de
RS		 8902 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8903 (match_operand:TF 1 "gpc_reg_operand" ""))
1a402dc1
AM		 8904 (set (match_dup 3) (match_dup 5))
8905 (set (match_dup 5) (abs:DF (match_dup 5)))
8906 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8907 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8908 (label_ref (match_operand 2 "" ""))
8909 (pc)))
8910 (set (match_dup 6) (neg:DF (match_dup 6)))]
602ea4d3 8911 "!TARGET_IEEEQUAD
39e63627 8912 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
1a402dc1 8913 "
06f4e019 8914{
1a402dc1
AM		 8915 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8916 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8917 operands[3] = gen_reg_rtx (DFmode);
8918 operands[4] = gen_reg_rtx (CCFPmode);
8919 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8920 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8921}")
06f4e019 8922\f
1fd4e8c1
RK		 8923;; Next come the multi-word integer load and store and the load and store
8924;; multiple insns.
1fd4e8c1 8925
112ccb83
GK		 8926; List r->r after r->"o<>", otherwise reload will try to reload a
8927; non-offsettable address by using r->r which won't make progress.
acad7ed3 8928(define_insn "*movdi_internal32"
17caeff2 8929 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
112ccb83 8930 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
a260abc9 8931 "! TARGET_POWERPC64
4e74d8ec
MM		 8932 && (gpc_reg_operand (operands[0], DImode)
8933 || gpc_reg_operand (operands[1], DImode))"
112ccb83
GK		 8934 "@
8935 #
8936 #
8937 #
8938 fmr %0,%1
8939 lfd%U1%X1 %0,%1
8940 stfd%U0%X0 %1,%0
8941 #"
8942 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
4e74d8ec
MM		 8943
8944(define_split
8945 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8946 (match_operand:DI 1 "const_int_operand" ""))]
a260abc9 8947 "! TARGET_POWERPC64 && reload_completed"
4e74d8ec
MM		 8948 [(set (match_dup 2) (match_dup 4))
8949 (set (match_dup 3) (match_dup 1))]
8950 "
8951{
5f59ecb7 8952 HOST_WIDE_INT value = INTVAL (operands[1]);
bdaa0181
GK		 8953 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8954 DImode);
8955 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8956 DImode);
75d39459 8957#if HOST_BITS_PER_WIDE_INT == 32
5f59ecb7 8958 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
75d39459 8959#else
5f59ecb7 8960 operands[4] = GEN_INT (value >> 32);
a65c591c 8961 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
75d39459 8962#endif
4e74d8ec
MM		 8963}")
8964
3a1f863f 8965(define_split
17caeff2 8966 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
3a1f863f 8967 (match_operand:DI 1 "input_operand" ""))]
6ae08853 8968 "reload_completed && !TARGET_POWERPC64
3a1f863f 8969 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 8970 [(pc)]
8971{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
3a1f863f 8972
44cd321e
PS		 8973(define_insn "*movdi_mfpgpr"
8974 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8975 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8976 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8977 && (gpc_reg_operand (operands[0], DImode)
8978 || gpc_reg_operand (operands[1], DImode))"
8979 "@
8980 mr %0,%1
8981 ld%U1%X1 %0,%1
8982 std%U0%X0 %1,%0
8983 li %0,%1
8984 lis %0,%v1
8985 #
8986 {cal|la} %0,%a1
8987 fmr %0,%1
8988 lfd%U1%X1 %0,%1
8989 stfd%U0%X0 %1,%0
8990 mf%1 %0
8991 mt%0 %1
8992 {cror 0,0,0|nop}
8993 mftgpr %0,%1
8994 mffgpr %0,%1"
8995 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8996 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8997
acad7ed3 8998(define_insn "*movdi_internal64"
343f6bbf 8999 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
9615f239 9000 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
44cd321e 9001 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
4e74d8ec
MM		 9002 && (gpc_reg_operand (operands[0], DImode)
9003 || gpc_reg_operand (operands[1], DImode))"
51b8fc2c 9004 "@
3d5570cb
RK		 9005 mr %0,%1
9006 ld%U1%X1 %0,%1
96bb8ed3 9007 std%U0%X0 %1,%0
3d5570cb 9008 li %0,%1
802a0058 9009 lis %0,%v1
e6ca2c17 9010 #
aee86b38 9011 {cal|la} %0,%a1
3d5570cb
RK		 9012 fmr %0,%1
9013 lfd%U1%X1 %0,%1
9014 stfd%U0%X0 %1,%0
9015 mf%1 %0
08075ead 9016 mt%0 %1
e34eaae5 9017 {cror 0,0,0|nop}"
02ca7595 9018 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
e6ca2c17
DE		 9019 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9020
5f59ecb7 9021;; immediate value valid for a single instruction hiding in a const_double
a260abc9
DE		 9022(define_insn ""
9023 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9024 (match_operand:DI 1 "const_double_operand" "F"))]
5f59ecb7
DE		 9025 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9026 && GET_CODE (operands[1]) == CONST_DOUBLE
a260abc9
DE		 9027 && num_insns_constant (operands[1], DImode) == 1"
9028 "*
9029{
9030 return ((unsigned HOST_WIDE_INT)
9031 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9032 ? \"li %0,%1\" : \"lis %0,%v1\";
9033}")
9034
a260abc9
DE		 9035;; Generate all one-bits and clear left or right.
9036;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9037(define_split
9038 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1990cd79 9039 (match_operand:DI 1 "mask64_operand" ""))]
a260abc9
DE		 9040 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9041 [(set (match_dup 0) (const_int -1))
e6ca2c17 9042 (set (match_dup 0)
a260abc9
DE		 9043 (and:DI (rotate:DI (match_dup 0)
9044 (const_int 0))
9045 (match_dup 1)))]
9046 "")
9047
9048;; Split a load of a large constant into the appropriate five-instruction
9049;; sequence. Handle anything in a constant number of insns.
9050;; When non-easy constants can go in the TOC, this should use
9051;; easy_fp_constant predicate.
9052(define_split
9053 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 9054 (match_operand:DI 1 "const_int_operand" ""))]
9055 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9056 [(set (match_dup 0) (match_dup 2))
9057 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
e6ca2c17 9058 "
2bfcf297
DB		 9059{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9060
9061 if (tem == operands[0])
9062 DONE;
e8d791dd 9063 else
2bfcf297 9064 FAIL;
5f59ecb7 9065}")
e6ca2c17 9066
5f59ecb7
DE		 9067(define_split
9068 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 9069 (match_operand:DI 1 "const_double_operand" ""))]
9070 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9071 [(set (match_dup 0) (match_dup 2))
9072 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5f59ecb7 9073 "
2bfcf297
DB		 9074{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9075
9076 if (tem == operands[0])
9077 DONE;
9078 else
9079 FAIL;
e6ca2c17 9080}")
acad7ed3 9081\f
1fd4e8c1
RK		 9082;; TImode is similar, except that we usually want to compute the address into
9083;; a register and use lsi/stsi (the exception is during reload). MQ is also
ca7f5001 9084;; clobbered in stsi for POWER, so we need a SCRATCH for it.
1fd4e8c1
RK		 9085
9086;; We say that MQ is clobbered in the last alternative because the first
9087;; alternative would never get used otherwise since it would need a reload
9088;; while the 2nd alternative would not. We put memory cases first so they
9089;; are preferred. Otherwise, we'd try to reload the output instead of
9090;; giving the SCRATCH mq.
3a1f863f 9091
a260abc9 9092(define_insn "*movti_power"
7f514158
AM		 9093 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9094 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9095 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
6ae08853 9096 "TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca 9097 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
1fd4e8c1
RK		 9098 "*
9099{
9100 switch (which_alternative)
9101 {
dc4f83ca 9102 default:
37409796 9103 gcc_unreachable ();
dc4f83ca 9104
1fd4e8c1 9105 case 0:
3a1f863f
DE		 9106 if (TARGET_STRING)
9107 return \"{stsi|stswi} %1,%P0,16\";
1fd4e8c1 9108 case 1:
1fd4e8c1 9109 case 2:
3a1f863f 9110 return \"#\";
1fd4e8c1
RK		 9111 case 3:
9112 /* If the address is not used in the output, we can use lsi. Otherwise,
9113 fall through to generating four loads. */
e876481c
DE		 9114 if (TARGET_STRING
9115 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
ca7f5001 9116 return \"{lsi|lswi} %0,%P1,16\";
82e41834 9117 /* ... fall through ... */
1fd4e8c1 9118 case 4:
7f514158 9119 case 5:
3a1f863f 9120 return \"#\";
1fd4e8c1
RK		 9121 }
9122}"
7f514158 9123 [(set_attr "type" "store,store,*,load,load,*")])
51b8fc2c 9124
a260abc9 9125(define_insn "*movti_string"
7f514158
AM		 9126 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9127 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
3a1f863f 9128 "! TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca
MM		 9129 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9130 "*
9131{
9132 switch (which_alternative)
9133 {
9134 default:
37409796 9135 gcc_unreachable ();
dc4f83ca 9136 case 0:
3a1f863f
DE		 9137 if (TARGET_STRING)
9138 return \"{stsi|stswi} %1,%P0,16\";
dc4f83ca 9139 case 1:
cd1d3445 9140 case 2:
3a1f863f 9141 return \"#\";
cd1d3445
DE		 9142 case 3:
9143 /* If the address is not used in the output, we can use lsi. Otherwise,
9144 fall through to generating four loads. */
6ae08853 9145 if (TARGET_STRING
3a1f863f 9146 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
cd1d3445
DE		 9147 return \"{lsi|lswi} %0,%P1,16\";
9148 /* ... fall through ... */
9149 case 4:
7f514158 9150 case 5:
3a1f863f 9151 return \"#\";
dc4f83ca
MM		 9152 }
9153}"
9c6fdb46 9154 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
dc4f83ca 9155
a260abc9 9156(define_insn "*movti_ppc64"
112ccb83
GK		 9157 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9158 (match_operand:TI 1 "input_operand" "r,r,m"))]
51b8fc2c
RK		 9159 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9160 || gpc_reg_operand (operands[1], TImode))"
112ccb83 9161 "#"
3a1f863f
DE		 9162 [(set_attr "type" "*,load,store")])
9163
7f514158
AM		 9164(define_split
9165 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9166 (match_operand:TI 1 "const_double_operand" ""))]
9167 "TARGET_POWERPC64"
9168 [(set (match_dup 2) (match_dup 4))
9169 (set (match_dup 3) (match_dup 5))]
9170 "
9171{
9172 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9173 TImode);
9174 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9175 TImode);
9176 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9177 {
9178 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9179 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9180 }
9181 else if (GET_CODE (operands[1]) == CONST_INT)
9182 {
9183 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9184 operands[5] = operands[1];
9185 }
9186 else
9187 FAIL;
9188}")
9189
3a1f863f
DE		 9190(define_split
9191 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9192 (match_operand:TI 1 "input_operand" ""))]
a9baceb1 9193 "reload_completed
3a1f863f 9194 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 9195 [(pc)]
9196{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
1fd4e8c1
RK		 9197\f
9198(define_expand "load_multiple"
2f622005
RK		 9199 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9200 (match_operand:SI 1 "" ""))
9201 (use (match_operand:SI 2 "" ""))])]
09a625f7 9202 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9203 "
9204{
9205 int regno;
9206 int count;
792760b9 9207 rtx op1;
1fd4e8c1
RK		 9208 int i;
9209
9210 /* Support only loading a constant number of fixed-point registers from
9211 memory and only bother with this if more than two; the machine
9212 doesn't support more than eight. */
9213 if (GET_CODE (operands[2]) != CONST_INT
9214 || INTVAL (operands[2]) <= 2
9215 || INTVAL (operands[2]) > 8
9216 || GET_CODE (operands[1]) != MEM
9217 || GET_CODE (operands[0]) != REG
9218 || REGNO (operands[0]) >= 32)
9219 FAIL;
9220
9221 count = INTVAL (operands[2]);
9222 regno = REGNO (operands[0]);
9223
39403d82 9224 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
792760b9
RK		 9225 op1 = replace_equiv_address (operands[1],
9226 force_reg (SImode, XEXP (operands[1], 0)));
1fd4e8c1
RK		 9227
9228 for (i = 0; i < count; i++)
9229 XVECEXP (operands[3], 0, i)
39403d82 9230 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
7ef788f0 9231 adjust_address_nv (op1, SImode, i * 4));
1fd4e8c1
RK		 9232}")
9233
9caa3eb2 9234(define_insn "*ldmsi8"
1fd4e8c1 9235 [(match_parallel 0 "load_multiple_operation"
9caa3eb2
DE		 9236 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9237 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9238 (set (match_operand:SI 3 "gpc_reg_operand" "")
9239 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9240 (set (match_operand:SI 4 "gpc_reg_operand" "")
9241 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9242 (set (match_operand:SI 5 "gpc_reg_operand" "")
9243 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9244 (set (match_operand:SI 6 "gpc_reg_operand" "")
9245 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9246 (set (match_operand:SI 7 "gpc_reg_operand" "")
9247 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9248 (set (match_operand:SI 8 "gpc_reg_operand" "")
9249 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9250 (set (match_operand:SI 9 "gpc_reg_operand" "")
9251 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9252 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
1fd4e8c1 9253 "*
9caa3eb2 9254{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9255 [(set_attr "type" "load_ux")
9caa3eb2 9256 (set_attr "length" "32")])
1fd4e8c1 9257
9caa3eb2
DE		 9258(define_insn "*ldmsi7"
9259 [(match_parallel 0 "load_multiple_operation"
9260 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9261 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9262 (set (match_operand:SI 3 "gpc_reg_operand" "")
9263 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9264 (set (match_operand:SI 4 "gpc_reg_operand" "")
9265 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9266 (set (match_operand:SI 5 "gpc_reg_operand" "")
9267 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9268 (set (match_operand:SI 6 "gpc_reg_operand" "")
9269 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9270 (set (match_operand:SI 7 "gpc_reg_operand" "")
9271 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9272 (set (match_operand:SI 8 "gpc_reg_operand" "")
9273 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9274 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9275 "*
9276{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9277 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9278 (set_attr "length" "32")])
9279
9280(define_insn "*ldmsi6"
9281 [(match_parallel 0 "load_multiple_operation"
9282 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9283 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9284 (set (match_operand:SI 3 "gpc_reg_operand" "")
9285 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9286 (set (match_operand:SI 4 "gpc_reg_operand" "")
9287 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9288 (set (match_operand:SI 5 "gpc_reg_operand" "")
9289 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9290 (set (match_operand:SI 6 "gpc_reg_operand" "")
9291 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9292 (set (match_operand:SI 7 "gpc_reg_operand" "")
9293 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9294 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9295 "*
9296{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9297 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9298 (set_attr "length" "32")])
9299
9300(define_insn "*ldmsi5"
9301 [(match_parallel 0 "load_multiple_operation"
9302 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9303 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9304 (set (match_operand:SI 3 "gpc_reg_operand" "")
9305 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9306 (set (match_operand:SI 4 "gpc_reg_operand" "")
9307 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9308 (set (match_operand:SI 5 "gpc_reg_operand" "")
9309 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9310 (set (match_operand:SI 6 "gpc_reg_operand" "")
9311 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9312 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9313 "*
9314{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9315 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9316 (set_attr "length" "32")])
9317
9318(define_insn "*ldmsi4"
9319 [(match_parallel 0 "load_multiple_operation"
9320 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9321 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9322 (set (match_operand:SI 3 "gpc_reg_operand" "")
9323 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9324 (set (match_operand:SI 4 "gpc_reg_operand" "")
9325 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9326 (set (match_operand:SI 5 "gpc_reg_operand" "")
9327 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9328 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9329 "*
9330{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9331 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9332 (set_attr "length" "32")])
9333
9334(define_insn "*ldmsi3"
9335 [(match_parallel 0 "load_multiple_operation"
9336 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9337 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9338 (set (match_operand:SI 3 "gpc_reg_operand" "")
9339 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9340 (set (match_operand:SI 4 "gpc_reg_operand" "")
9341 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9342 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9343 "*
9344{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9345 [(set_attr "type" "load_ux")
e82ee4cc 9346 (set_attr "length" "32")])
b19003d8 9347
1fd4e8c1 9348(define_expand "store_multiple"
2f622005
RK		 9349 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9350 (match_operand:SI 1 "" ""))
9351 (clobber (scratch:SI))
9352 (use (match_operand:SI 2 "" ""))])]
09a625f7 9353 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9354 "
9355{
9356 int regno;
9357 int count;
9358 rtx to;
792760b9 9359 rtx op0;
1fd4e8c1
RK		 9360 int i;
9361
9362 /* Support only storing a constant number of fixed-point registers to
9363 memory and only bother with this if more than two; the machine
9364 doesn't support more than eight. */
9365 if (GET_CODE (operands[2]) != CONST_INT
9366 || INTVAL (operands[2]) <= 2
9367 || INTVAL (operands[2]) > 8
9368 || GET_CODE (operands[0]) != MEM
9369 || GET_CODE (operands[1]) != REG
9370 || REGNO (operands[1]) >= 32)
9371 FAIL;
9372
9373 count = INTVAL (operands[2]);
9374 regno = REGNO (operands[1]);
9375
39403d82 9376 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
1fd4e8c1 9377 to = force_reg (SImode, XEXP (operands[0], 0));
792760b9 9378 op0 = replace_equiv_address (operands[0], to);
1fd4e8c1
RK		 9379
9380 XVECEXP (operands[3], 0, 0)
7ef788f0 9381 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
39403d82 9382 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
c5c76735 9383 gen_rtx_SCRATCH (SImode));
1fd4e8c1
RK		 9384
9385 for (i = 1; i < count; i++)
9386 XVECEXP (operands[3], 0, i + 1)
39403d82 9387 = gen_rtx_SET (VOIDmode,
7ef788f0 9388 adjust_address_nv (op0, SImode, i * 4),
c5c76735 9389 gen_rtx_REG (SImode, regno + i));
1fd4e8c1
RK		 9390}")
9391
e46e3130 9392(define_insn "*stmsi8"
d14a6d05 9393 [(match_parallel 0 "store_multiple_operation"
e46e3130
DJ		 9394 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9395 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9396 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9397 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9398 (match_operand:SI 4 "gpc_reg_operand" "r"))
9399 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9400 (match_operand:SI 5 "gpc_reg_operand" "r"))
9401 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9402 (match_operand:SI 6 "gpc_reg_operand" "r"))
9403 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9404 (match_operand:SI 7 "gpc_reg_operand" "r"))
9405 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9406 (match_operand:SI 8 "gpc_reg_operand" "r"))
9407 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9408 (match_operand:SI 9 "gpc_reg_operand" "r"))
9409 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9410 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9411 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9412 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9413 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9414
9415(define_insn "*stmsi7"
9416 [(match_parallel 0 "store_multiple_operation"
9417 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9418 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9419 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9420 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9421 (match_operand:SI 4 "gpc_reg_operand" "r"))
9422 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9423 (match_operand:SI 5 "gpc_reg_operand" "r"))
9424 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9425 (match_operand:SI 6 "gpc_reg_operand" "r"))
9426 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9427 (match_operand:SI 7 "gpc_reg_operand" "r"))
9428 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9429 (match_operand:SI 8 "gpc_reg_operand" "r"))
9430 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9431 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9432 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9433 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9434 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9435
9436(define_insn "*stmsi6"
9437 [(match_parallel 0 "store_multiple_operation"
9438 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9439 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9440 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9441 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9442 (match_operand:SI 4 "gpc_reg_operand" "r"))
9443 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9444 (match_operand:SI 5 "gpc_reg_operand" "r"))
9445 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9446 (match_operand:SI 6 "gpc_reg_operand" "r"))
9447 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9448 (match_operand:SI 7 "gpc_reg_operand" "r"))
9449 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9450 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9451 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9452 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9453 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9454
9455(define_insn "*stmsi5"
9456 [(match_parallel 0 "store_multiple_operation"
9457 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9458 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9459 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9460 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9461 (match_operand:SI 4 "gpc_reg_operand" "r"))
9462 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9463 (match_operand:SI 5 "gpc_reg_operand" "r"))
9464 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9465 (match_operand:SI 6 "gpc_reg_operand" "r"))
9466 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9467 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9468 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9469 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9470 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9471
9472(define_insn "*stmsi4"
9473 [(match_parallel 0 "store_multiple_operation"
9474 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9475 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9476 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9477 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9478 (match_operand:SI 4 "gpc_reg_operand" "r"))
9479 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9480 (match_operand:SI 5 "gpc_reg_operand" "r"))
9481 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9482 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9483 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
b7ff3d82 9484 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9485 [(set_attr "type" "store_ux")])
7e69e155 9486
e46e3130
DJ		 9487(define_insn "*stmsi3"
9488 [(match_parallel 0 "store_multiple_operation"
9489 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9490 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9491 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9492 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9493 (match_operand:SI 4 "gpc_reg_operand" "r"))
9494 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9495 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9496 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9497 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9498 [(set_attr "type" "store_ux")])
d2894ab5
DE		 9499
9500(define_insn "*stmsi8_power"
9501 [(match_parallel 0 "store_multiple_operation"
9502 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9503 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9504 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9505 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9506 (match_operand:SI 4 "gpc_reg_operand" "r"))
9507 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9508 (match_operand:SI 5 "gpc_reg_operand" "r"))
9509 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9510 (match_operand:SI 6 "gpc_reg_operand" "r"))
9511 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9512 (match_operand:SI 7 "gpc_reg_operand" "r"))
9513 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9514 (match_operand:SI 8 "gpc_reg_operand" "r"))
9515 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9516 (match_operand:SI 9 "gpc_reg_operand" "r"))
9517 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9518 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9519 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9520 "{stsi|stswi} %2,%1,%O0"
9521 [(set_attr "type" "store_ux")])
9522
9523(define_insn "*stmsi7_power"
9524 [(match_parallel 0 "store_multiple_operation"
9525 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9526 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9527 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9528 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9529 (match_operand:SI 4 "gpc_reg_operand" "r"))
9530 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9531 (match_operand:SI 5 "gpc_reg_operand" "r"))
9532 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9533 (match_operand:SI 6 "gpc_reg_operand" "r"))
9534 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9535 (match_operand:SI 7 "gpc_reg_operand" "r"))
9536 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9537 (match_operand:SI 8 "gpc_reg_operand" "r"))
9538 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9539 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9540 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9541 "{stsi|stswi} %2,%1,%O0"
9542 [(set_attr "type" "store_ux")])
9543
9544(define_insn "*stmsi6_power"
9545 [(match_parallel 0 "store_multiple_operation"
9546 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9547 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9548 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9549 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9550 (match_operand:SI 4 "gpc_reg_operand" "r"))
9551 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9552 (match_operand:SI 5 "gpc_reg_operand" "r"))
9553 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9554 (match_operand:SI 6 "gpc_reg_operand" "r"))
9555 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9556 (match_operand:SI 7 "gpc_reg_operand" "r"))
9557 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9558 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9559 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9560 "{stsi|stswi} %2,%1,%O0"
9561 [(set_attr "type" "store_ux")])
9562
9563(define_insn "*stmsi5_power"
9564 [(match_parallel 0 "store_multiple_operation"
9565 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9566 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9567 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9568 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9569 (match_operand:SI 4 "gpc_reg_operand" "r"))
9570 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9571 (match_operand:SI 5 "gpc_reg_operand" "r"))
9572 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9573 (match_operand:SI 6 "gpc_reg_operand" "r"))
9574 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9575 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9576 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9577 "{stsi|stswi} %2,%1,%O0"
9578 [(set_attr "type" "store_ux")])
9579
9580(define_insn "*stmsi4_power"
9581 [(match_parallel 0 "store_multiple_operation"
9582 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9583 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9584 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9585 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9586 (match_operand:SI 4 "gpc_reg_operand" "r"))
9587 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9588 (match_operand:SI 5 "gpc_reg_operand" "r"))
9589 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9590 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9591 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9592 "{stsi|stswi} %2,%1,%O0"
9593 [(set_attr "type" "store_ux")])
9594
9595(define_insn "*stmsi3_power"
9596 [(match_parallel 0 "store_multiple_operation"
9597 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9598 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9599 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9600 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9601 (match_operand:SI 4 "gpc_reg_operand" "r"))
9602 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9603 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9604 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9605 "{stsi|stswi} %2,%1,%O0"
9606 [(set_attr "type" "store_ux")])
7e69e155 9607\f
57e84f18 9608(define_expand "setmemsi"
fba73eb1 9609 [(parallel [(set (match_operand:BLK 0 "" "")
98843c92 9610 (match_operand 2 "const_int_operand" ""))
fba73eb1 9611 (use (match_operand:SI 1 "" ""))
57e84f18 9612 (use (match_operand:SI 3 "" ""))])]
fba73eb1
DE		 9613 ""
9614 "
9615{
57e84f18 9616 /* If value to set is not zero, use the library routine. */
a05be2e0 9617 if (operands[2] != const0_rtx)
57e84f18
AS		 9618 FAIL;
9619
fba73eb1
DE		 9620 if (expand_block_clear (operands))
9621 DONE;
9622 else
9623 FAIL;
9624}")
9625
7e69e155
MM		 9626;; String/block move insn.
9627;; Argument 0 is the destination
9628;; Argument 1 is the source
9629;; Argument 2 is the length
9630;; Argument 3 is the alignment
9631
70128ad9 9632(define_expand "movmemsi"
b6c9286a
MM		 9633 [(parallel [(set (match_operand:BLK 0 "" "")
9634 (match_operand:BLK 1 "" ""))
9635 (use (match_operand:SI 2 "" ""))
9636 (use (match_operand:SI 3 "" ""))])]
7e69e155
MM		 9637 ""
9638 "
9639{
9640 if (expand_block_move (operands))
9641 DONE;
9642 else
9643 FAIL;
9644}")
9645
9646;; Move up to 32 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9647;; register allocator doesn't have a clue about allocating 8 word registers.
9648;; rD/rS = r5 is preferred, efficient form.
70128ad9 9649(define_expand "movmemsi_8reg"
b6c9286a
MM		 9650 [(parallel [(set (match_operand 0 "" "")
9651 (match_operand 1 "" ""))
9652 (use (match_operand 2 "" ""))
9653 (use (match_operand 3 "" ""))
7e69e155
MM		 9654 (clobber (reg:SI 5))
9655 (clobber (reg:SI 6))
9656 (clobber (reg:SI 7))
9657 (clobber (reg:SI 8))
9658 (clobber (reg:SI 9))
9659 (clobber (reg:SI 10))
9660 (clobber (reg:SI 11))
9661 (clobber (reg:SI 12))
3c67b673 9662 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9663 "TARGET_STRING"
9664 "")
9665
9666(define_insn ""
52d3af72
DE		 9667 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9668 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9669 (use (match_operand:SI 2 "immediate_operand" "i"))
9670 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9671 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9672 (clobber (reg:SI 6))
9673 (clobber (reg:SI 7))
9674 (clobber (reg:SI 8))
9675 (clobber (reg:SI 9))
9676 (clobber (reg:SI 10))
9677 (clobber (reg:SI 11))
9678 (clobber (reg:SI 12))
3c67b673 9679 (clobber (match_scratch:SI 5 "=q"))]
7e69e155 9680 "TARGET_STRING && TARGET_POWER
f9562f27
DE		 9681 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9682 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9683 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9684 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9685 && REGNO (operands[4]) == 5"
9686 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9687 [(set_attr "type" "store_ux")
b7ff3d82 9688 (set_attr "length" "8")])
7e69e155
MM		 9689
9690(define_insn ""
4ae234b0
GK		 9691 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9692 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9693 (use (match_operand:SI 2 "immediate_operand" "i"))
9694 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9695 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
7e69e155
MM		 9696 (clobber (reg:SI 6))
9697 (clobber (reg:SI 7))
9698 (clobber (reg:SI 8))
9699 (clobber (reg:SI 9))
9700 (clobber (reg:SI 10))
9701 (clobber (reg:SI 11))
9702 (clobber (reg:SI 12))
edd54d25 9703 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9704 "TARGET_STRING && ! TARGET_POWER
f9562f27
DE		 9705 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9706 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9707 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9708 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9709 && REGNO (operands[4]) == 5"
9710 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9711 [(set_attr "type" "store_ux")
b7ff3d82 9712 (set_attr "length" "8")])
7e69e155
MM		 9713
9714;; Move up to 24 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9715;; register allocator doesn't have a clue about allocating 6 word registers.
9716;; rD/rS = r5 is preferred, efficient form.
70128ad9 9717(define_expand "movmemsi_6reg"
b6c9286a
MM		 9718 [(parallel [(set (match_operand 0 "" "")
9719 (match_operand 1 "" ""))
9720 (use (match_operand 2 "" ""))
9721 (use (match_operand 3 "" ""))
f9562f27
DE		 9722 (clobber (reg:SI 5))
9723 (clobber (reg:SI 6))
7e69e155
MM		 9724 (clobber (reg:SI 7))
9725 (clobber (reg:SI 8))
9726 (clobber (reg:SI 9))
9727 (clobber (reg:SI 10))
3c67b673 9728 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9729 "TARGET_STRING"
9730 "")
9731
9732(define_insn ""
52d3af72
DE		 9733 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9734 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9735 (use (match_operand:SI 2 "immediate_operand" "i"))
9736 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9737 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9738 (clobber (reg:SI 6))
9739 (clobber (reg:SI 7))
7e69e155
MM		 9740 (clobber (reg:SI 8))
9741 (clobber (reg:SI 9))
9742 (clobber (reg:SI 10))
3c67b673 9743 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9744 "TARGET_STRING && TARGET_POWER
9745 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
f9562f27
DE		 9746 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9747 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9748 && REGNO (operands[4]) == 5"
3c67b673 9749 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9750 [(set_attr "type" "store_ux")
b7ff3d82 9751 (set_attr "length" "8")])
7e69e155
MM		 9752
9753(define_insn ""
4ae234b0
GK		 9754 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9755 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9756 (use (match_operand:SI 2 "immediate_operand" "i"))
9757 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9758 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9759 (clobber (reg:SI 6))
9760 (clobber (reg:SI 7))
7e69e155
MM		 9761 (clobber (reg:SI 8))
9762 (clobber (reg:SI 9))
9763 (clobber (reg:SI 10))
edd54d25 9764 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9765 "TARGET_STRING && ! TARGET_POWER
7e69e155 9766 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
f9562f27
DE		 9767 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9768 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9769 && REGNO (operands[4]) == 5"
3c67b673 9770 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9771 [(set_attr "type" "store_ux")
b7ff3d82 9772 (set_attr "length" "8")])
7e69e155 9773
f9562f27
DE		 9774;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9775;; problems with TImode.
9776;; rD/rS = r5 is preferred, efficient form.
70128ad9 9777(define_expand "movmemsi_4reg"
b6c9286a
MM		 9778 [(parallel [(set (match_operand 0 "" "")
9779 (match_operand 1 "" ""))
9780 (use (match_operand 2 "" ""))
9781 (use (match_operand 3 "" ""))
f9562f27
DE		 9782 (clobber (reg:SI 5))
9783 (clobber (reg:SI 6))
9784 (clobber (reg:SI 7))
9785 (clobber (reg:SI 8))
3c67b673 9786 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9787 "TARGET_STRING"
9788 "")
9789
9790(define_insn ""
52d3af72
DE		 9791 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9792 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9793 (use (match_operand:SI 2 "immediate_operand" "i"))
9794 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9795 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9796 (clobber (reg:SI 6))
9797 (clobber (reg:SI 7))
9798 (clobber (reg:SI 8))
3c67b673 9799 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9800 "TARGET_STRING && TARGET_POWER
9801 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9802 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9803 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9804 && REGNO (operands[4]) == 5"
3c67b673 9805 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9806 [(set_attr "type" "store_ux")
b7ff3d82 9807 (set_attr "length" "8")])
7e69e155
MM		 9808
9809(define_insn ""
4ae234b0
GK		 9810 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9811 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9812 (use (match_operand:SI 2 "immediate_operand" "i"))
9813 (use (match_operand:SI 3 "immediate_operand" "i"))
52d3af72 9814 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
f9562f27
DE		 9815 (clobber (reg:SI 6))
9816 (clobber (reg:SI 7))
9817 (clobber (reg:SI 8))
edd54d25 9818 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9819 "TARGET_STRING && ! TARGET_POWER
7e69e155 9820 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9821 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9822 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9823 && REGNO (operands[4]) == 5"
3c67b673 9824 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9825 [(set_attr "type" "store_ux")
b7ff3d82 9826 (set_attr "length" "8")])
7e69e155
MM		 9827
9828;; Move up to 8 bytes at a time.
70128ad9 9829(define_expand "movmemsi_2reg"
b6c9286a
MM		 9830 [(parallel [(set (match_operand 0 "" "")
9831 (match_operand 1 "" ""))
9832 (use (match_operand 2 "" ""))
9833 (use (match_operand 3 "" ""))
3c67b673
RK		 9834 (clobber (match_scratch:DI 4 ""))
9835 (clobber (match_scratch:SI 5 ""))])]
f9562f27 9836 "TARGET_STRING && ! TARGET_POWERPC64"
7e69e155
MM		 9837 "")
9838
9839(define_insn ""
52d3af72
DE		 9840 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9841 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9842 (use (match_operand:SI 2 "immediate_operand" "i"))
9843 (use (match_operand:SI 3 "immediate_operand" "i"))
9844 (clobber (match_scratch:DI 4 "=&r"))
9845 (clobber (match_scratch:SI 5 "=q"))]
f9562f27 9846 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
3c67b673
RK		 9847 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9848 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9849 [(set_attr "type" "store_ux")
b7ff3d82 9850 (set_attr "length" "8")])
7e69e155
MM		 9851
9852(define_insn ""
52d3af72
DE		 9853 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9854 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9855 (use (match_operand:SI 2 "immediate_operand" "i"))
9856 (use (match_operand:SI 3 "immediate_operand" "i"))
9857 (clobber (match_scratch:DI 4 "=&r"))
edd54d25 9858 (clobber (match_scratch:SI 5 "=X"))]
f9562f27 9859 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
7e69e155 9860 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
3c67b673 9861 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9862 [(set_attr "type" "store_ux")
b7ff3d82 9863 (set_attr "length" "8")])
7e69e155
MM		 9864
9865;; Move up to 4 bytes at a time.
70128ad9 9866(define_expand "movmemsi_1reg"
b6c9286a
MM		 9867 [(parallel [(set (match_operand 0 "" "")
9868 (match_operand 1 "" ""))
9869 (use (match_operand 2 "" ""))
9870 (use (match_operand 3 "" ""))
3c67b673
RK		 9871 (clobber (match_scratch:SI 4 ""))
9872 (clobber (match_scratch:SI 5 ""))])]
7e69e155
MM		 9873 "TARGET_STRING"
9874 "")
9875
9876(define_insn ""
52d3af72
DE		 9877 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9878 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9879 (use (match_operand:SI 2 "immediate_operand" "i"))
9880 (use (match_operand:SI 3 "immediate_operand" "i"))
9881 (clobber (match_scratch:SI 4 "=&r"))
9882 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9883 "TARGET_STRING && TARGET_POWER
9884 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
3c67b673 9885 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9886 [(set_attr "type" "store_ux")
b7ff3d82 9887 (set_attr "length" "8")])
7e69e155
MM		 9888
9889(define_insn ""
4ae234b0
GK		 9890 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9891 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9892 (use (match_operand:SI 2 "immediate_operand" "i"))
9893 (use (match_operand:SI 3 "immediate_operand" "i"))
9894 (clobber (match_scratch:SI 4 "=&r"))
edd54d25 9895 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9896 "TARGET_STRING && ! TARGET_POWER
7e69e155 9897 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
09a625f7 9898 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9899 [(set_attr "type" "store_ux")
09a625f7 9900 (set_attr "length" "8")])
1fd4e8c1 9901\f
7e69e155 9902;; Define insns that do load or store with update. Some of these we can
1fd4e8c1
RK		 9903;; get by using pre-decrement or pre-increment, but the hardware can also
9904;; do cases where the increment is not the size of the object.
9905;;
9906;; In all these cases, we use operands 0 and 1 for the register being
9907;; incremented because those are the operands that local-alloc will
9908;; tie and these are the pair most likely to be tieable (and the ones
9909;; that will benefit the most).
9910
38c1f2d7 9911(define_insn "*movdi_update1"
51b8fc2c 9912 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
ad8bd902 9913 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
768070a0 9914 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
51b8fc2c
RK		 9915 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9916 (plus:DI (match_dup 1) (match_dup 2)))]
38c1f2d7 9917 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9918 "@
9919 ldux %3,%0,%2
9920 ldu %3,%2(%0)"
b54cf83a 9921 [(set_attr "type" "load_ux,load_u")])
287f13ff 9922
2e6c9641
FJ		 9923(define_insn "movdi_<mode>_update"
9924 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9925 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
51b8fc2c 9926 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
2e6c9641
FJ		 9927 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9928 (plus:P (match_dup 1) (match_dup 2)))]
38c1f2d7 9929 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9930 "@
9931 stdux %3,%0,%2
b7ff3d82 9932 stdu %3,%2(%0)"
b54cf83a 9933 [(set_attr "type" "store_ux,store_u")])
51b8fc2c 9934
38c1f2d7 9935(define_insn "*movsi_update1"
cd2b37d9
RK		 9936 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9937 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9938 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9939 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9940 (plus:SI (match_dup 1) (match_dup 2)))]
f7b3ab8a 9941 "TARGET_UPDATE"
1fd4e8c1 9942 "@
ca7f5001
RK		 9943 {lux|lwzux} %3,%0,%2
9944 {lu|lwzu} %3,%2(%0)"
b54cf83a
DE		 9945 [(set_attr "type" "load_ux,load_u")])
9946
9947(define_insn "*movsi_update2"
9948 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9949 (sign_extend:DI
9950 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9951 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9952 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9953 (plus:DI (match_dup 1) (match_dup 2)))]
9954 "TARGET_POWERPC64"
9955 "lwaux %3,%0,%2"
9956 [(set_attr "type" "load_ext_ux")])
1fd4e8c1 9957
4697a36c 9958(define_insn "movsi_update"
cd2b37d9 9959 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9960 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9961 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9962 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9963 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9964 "TARGET_UPDATE"
1fd4e8c1 9965 "@
ca7f5001 9966 {stux|stwux} %3,%0,%2
b7ff3d82 9967 {stu|stwu} %3,%2(%0)"
b54cf83a 9968 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9969
b54cf83a 9970(define_insn "*movhi_update1"
cd2b37d9
RK		 9971 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9972 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9973 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9974 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9975 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9976 "TARGET_UPDATE"
1fd4e8c1 9977 "@
5f243543
RK		 9978 lhzux %3,%0,%2
9979 lhzu %3,%2(%0)"
b54cf83a 9980 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9981
38c1f2d7 9982(define_insn "*movhi_update2"
cd2b37d9 9983 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9984 (zero_extend:SI
cd2b37d9 9985 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9986 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9987 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9988 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9989 "TARGET_UPDATE"
1fd4e8c1 9990 "@
5f243543
RK		 9991 lhzux %3,%0,%2
9992 lhzu %3,%2(%0)"
b54cf83a 9993 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9994
38c1f2d7 9995(define_insn "*movhi_update3"
cd2b37d9 9996 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9997 (sign_extend:SI
cd2b37d9 9998 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9999 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 10000 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10001 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 10002 "TARGET_UPDATE"
1fd4e8c1 10003 "@
5f243543
RK		 10004 lhaux %3,%0,%2
10005 lhau %3,%2(%0)"
b54cf83a 10006 [(set_attr "type" "load_ext_ux,load_ext_u")])
1fd4e8c1 10007
38c1f2d7 10008(define_insn "*movhi_update4"
cd2b37d9 10009 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10010 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10011 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10012 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10013 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 10014 "TARGET_UPDATE"
1fd4e8c1 10015 "@
5f243543 10016 sthux %3,%0,%2
b7ff3d82 10017 sthu %3,%2(%0)"
b54cf83a 10018 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 10019
38c1f2d7 10020(define_insn "*movqi_update1"
cd2b37d9
RK		 10021 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10022 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10023 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10024 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10025 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 10026 "TARGET_UPDATE"
1fd4e8c1 10027 "@
5f243543
RK		 10028 lbzux %3,%0,%2
10029 lbzu %3,%2(%0)"
b54cf83a 10030 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 10031
38c1f2d7 10032(define_insn "*movqi_update2"
cd2b37d9 10033 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 10034 (zero_extend:SI
cd2b37d9 10035 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10036 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 10037 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10038 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 10039 "TARGET_UPDATE"
1fd4e8c1 10040 "@
5f243543
RK		 10041 lbzux %3,%0,%2
10042 lbzu %3,%2(%0)"
b54cf83a 10043 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 10044
38c1f2d7 10045(define_insn "*movqi_update3"
cd2b37d9 10046 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10047 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10048 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10049 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10050 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 10051 "TARGET_UPDATE"
1fd4e8c1 10052 "@
5f243543 10053 stbux %3,%0,%2
b7ff3d82 10054 stbu %3,%2(%0)"
b54cf83a 10055 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 10056
38c1f2d7 10057(define_insn "*movsf_update1"
cd2b37d9 10058 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
df8b713c 10059 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10060 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10061 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10062 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10063 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10064 "@
5f243543
RK		 10065 lfsux %3,%0,%2
10066 lfsu %3,%2(%0)"
b54cf83a 10067 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10068
38c1f2d7 10069(define_insn "*movsf_update2"
cd2b37d9 10070 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10071 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10072 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10073 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10074 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10075 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10076 "@
85fff2f3 10077 stfsux %3,%0,%2
b7ff3d82 10078 stfsu %3,%2(%0)"
b54cf83a 10079 [(set_attr "type" "fpstore_ux,fpstore_u")])
1fd4e8c1 10080
38c1f2d7
MM		 10081(define_insn "*movsf_update3"
10082 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10083 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10084 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10085 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10086 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10087 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 10088 "@
10089 {lux|lwzux} %3,%0,%2
10090 {lu|lwzu} %3,%2(%0)"
b54cf83a 10091 [(set_attr "type" "load_ux,load_u")])
38c1f2d7
MM		 10092
10093(define_insn "*movsf_update4"
10094 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10095 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10096 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10097 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10098 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10099 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 10100 "@
10101 {stux|stwux} %3,%0,%2
10102 {stu|stwu} %3,%2(%0)"
b54cf83a 10103 [(set_attr "type" "store_ux,store_u")])
38c1f2d7
MM		 10104
10105(define_insn "*movdf_update1"
cd2b37d9
RK		 10106 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10107 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10108 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10109 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10110 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10111 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10112 "@
5f243543
RK		 10113 lfdux %3,%0,%2
10114 lfdu %3,%2(%0)"
b54cf83a 10115 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10116
38c1f2d7 10117(define_insn "*movdf_update2"
cd2b37d9 10118 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10119 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10120 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10121 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10122 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10123 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10124 "@
5f243543 10125 stfdux %3,%0,%2
b7ff3d82 10126 stfdu %3,%2(%0)"
b54cf83a 10127 [(set_attr "type" "fpstore_ux,fpstore_u")])
4c70a4f3
RK		 10128
10129;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10130
90f81f99 10131(define_insn "*lfq_power2"
bb8df8a6
EC		 10132 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10133 (match_operand:V2DF 1 "memory_operand" ""))]
90f81f99
AP		 10134 "TARGET_POWER2
10135 && TARGET_HARD_FLOAT && TARGET_FPRS"
bb8df8a6 10136 "lfq%U1%X1 %0,%1")
90f81f99
AP		 10137
10138(define_peephole2
10139 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4c70a4f3 10140 (match_operand:DF 1 "memory_operand" ""))
90f81f99 10141 (set (match_operand:DF 2 "gpc_reg_operand" "")
4c70a4f3
RK		 10142 (match_operand:DF 3 "memory_operand" ""))]
10143 "TARGET_POWER2
a3170dc6 10144 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3 10145 && registers_ok_for_quad_peep (operands[0], operands[2])
90f81f99
AP		 10146 && mems_ok_for_quad_peep (operands[1], operands[3])"
10147 [(set (match_dup 0)
bb8df8a6
EC		 10148 (match_dup 1))]
10149 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10150 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
4c70a4f3 10151
90f81f99 10152(define_insn "*stfq_power2"
bb8df8a6
EC		 10153 [(set (match_operand:V2DF 0 "memory_operand" "")
10154 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
90f81f99
AP		 10155 "TARGET_POWER2
10156 && TARGET_HARD_FLOAT && TARGET_FPRS"
10157 "stfq%U0%X0 %1,%0")
10158
10159
10160(define_peephole2
4c70a4f3 10161 [(set (match_operand:DF 0 "memory_operand" "")
90f81f99 10162 (match_operand:DF 1 "gpc_reg_operand" ""))
4c70a4f3 10163 (set (match_operand:DF 2 "memory_operand" "")
90f81f99 10164 (match_operand:DF 3 "gpc_reg_operand" ""))]
4c70a4f3 10165 "TARGET_POWER2
a3170dc6 10166 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3 10167 && registers_ok_for_quad_peep (operands[1], operands[3])
90f81f99
AP		 10168 && mems_ok_for_quad_peep (operands[0], operands[2])"
10169 [(set (match_dup 0)
10170 (match_dup 1))]
bb8df8a6
EC		 10171 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10172 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
2f4d9502 10173
036aadfc 10174;; After inserting conditional returns we can sometimes have
2f4d9502
NS		 10175;; unnecessary register moves. Unfortunately we cannot have a
10176;; modeless peephole here, because some single SImode sets have early
10177;; clobber outputs. Although those sets expand to multi-ppc-insn
10178;; sequences, using get_attr_length here will smash the operands
10179;; array. Neither is there an early_cobbler_p predicate.
036aadfc 10180;; Disallow subregs for E500 so we don't munge frob_di_df_2.
2f4d9502
NS		 10181(define_peephole2
10182 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10183 (match_operand:DF 1 "any_operand" ""))
10184 (set (match_operand:DF 2 "gpc_reg_operand" "")
10185 (match_dup 0))]
036aadfc
AM		 10186 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10187 && peep2_reg_dead_p (2, operands[0])"
2f4d9502
NS		 10188 [(set (match_dup 2) (match_dup 1))])
10189
10190(define_peephole2
10191 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10192 (match_operand:SF 1 "any_operand" ""))
10193 (set (match_operand:SF 2 "gpc_reg_operand" "")
10194 (match_dup 0))]
10195 "peep2_reg_dead_p (2, operands[0])"
10196 [(set (match_dup 2) (match_dup 1))])
10197
1fd4e8c1 10198\f
c4501e62
JJ		 10199;; TLS support.
10200
10201;; "b" output constraint here and on tls_ld to support tls linker optimization.
10202(define_insn "tls_gd_32"
b150f4f3
DE		 10203 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10204 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10205 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10206 UNSPEC_TLSGD))]
10207 "HAVE_AS_TLS && !TARGET_64BIT"
10208 "addi %0,%1,%2@got@tlsgd")
10209
10210(define_insn "tls_gd_64"
b150f4f3
DE		 10211 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10212 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10213 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10214 UNSPEC_TLSGD))]
10215 "HAVE_AS_TLS && TARGET_64BIT"
10216 "addi %0,%1,%2@got@tlsgd")
10217
10218(define_insn "tls_ld_32"
b150f4f3
DE		 10219 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10220 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
c4501e62
JJ		 10221 UNSPEC_TLSLD))]
10222 "HAVE_AS_TLS && !TARGET_64BIT"
10223 "addi %0,%1,%&@got@tlsld")
10224
10225(define_insn "tls_ld_64"
b150f4f3
DE		 10226 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10227 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
c4501e62
JJ		 10228 UNSPEC_TLSLD))]
10229 "HAVE_AS_TLS && TARGET_64BIT"
10230 "addi %0,%1,%&@got@tlsld")
10231
10232(define_insn "tls_dtprel_32"
b150f4f3
DE		 10233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10234 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10235 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10236 UNSPEC_TLSDTPREL))]
10237 "HAVE_AS_TLS && !TARGET_64BIT"
10238 "addi %0,%1,%2@dtprel")
10239
10240(define_insn "tls_dtprel_64"
b150f4f3
DE		 10241 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10242 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10243 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10244 UNSPEC_TLSDTPREL))]
10245 "HAVE_AS_TLS && TARGET_64BIT"
10246 "addi %0,%1,%2@dtprel")
10247
10248(define_insn "tls_dtprel_ha_32"
b150f4f3
DE		 10249 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10250 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10251 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10252 UNSPEC_TLSDTPRELHA))]
10253 "HAVE_AS_TLS && !TARGET_64BIT"
10254 "addis %0,%1,%2@dtprel@ha")
10255
10256(define_insn "tls_dtprel_ha_64"
b150f4f3
DE		 10257 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10258 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10259 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10260 UNSPEC_TLSDTPRELHA))]
10261 "HAVE_AS_TLS && TARGET_64BIT"
10262 "addis %0,%1,%2@dtprel@ha")
10263
10264(define_insn "tls_dtprel_lo_32"
b150f4f3
DE		 10265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10266 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10267 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10268 UNSPEC_TLSDTPRELLO))]
10269 "HAVE_AS_TLS && !TARGET_64BIT"
10270 "addi %0,%1,%2@dtprel@l")
10271
10272(define_insn "tls_dtprel_lo_64"
b150f4f3
DE		 10273 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10274 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10275 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10276 UNSPEC_TLSDTPRELLO))]
10277 "HAVE_AS_TLS && TARGET_64BIT"
10278 "addi %0,%1,%2@dtprel@l")
10279
10280(define_insn "tls_got_dtprel_32"
b150f4f3
DE		 10281 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10282 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10283 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10284 UNSPEC_TLSGOTDTPREL))]
10285 "HAVE_AS_TLS && !TARGET_64BIT"
10286 "lwz %0,%2@got@dtprel(%1)")
10287
10288(define_insn "tls_got_dtprel_64"
b150f4f3
DE		 10289 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10290 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10291 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10292 UNSPEC_TLSGOTDTPREL))]
10293 "HAVE_AS_TLS && TARGET_64BIT"
10294 "ld %0,%2@got@dtprel(%1)")
10295
10296(define_insn "tls_tprel_32"
b150f4f3
DE		 10297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10298 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10299 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10300 UNSPEC_TLSTPREL))]
10301 "HAVE_AS_TLS && !TARGET_64BIT"
10302 "addi %0,%1,%2@tprel")
10303
10304(define_insn "tls_tprel_64"
b150f4f3
DE		 10305 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10306 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10307 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10308 UNSPEC_TLSTPREL))]
10309 "HAVE_AS_TLS && TARGET_64BIT"
10310 "addi %0,%1,%2@tprel")
10311
10312(define_insn "tls_tprel_ha_32"
b150f4f3
DE		 10313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10314 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10315 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10316 UNSPEC_TLSTPRELHA))]
10317 "HAVE_AS_TLS && !TARGET_64BIT"
10318 "addis %0,%1,%2@tprel@ha")
10319
10320(define_insn "tls_tprel_ha_64"
b150f4f3
DE		 10321 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10322 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10323 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10324 UNSPEC_TLSTPRELHA))]
10325 "HAVE_AS_TLS && TARGET_64BIT"
10326 "addis %0,%1,%2@tprel@ha")
10327
10328(define_insn "tls_tprel_lo_32"
b150f4f3
DE		 10329 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10330 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10331 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10332 UNSPEC_TLSTPRELLO))]
10333 "HAVE_AS_TLS && !TARGET_64BIT"
10334 "addi %0,%1,%2@tprel@l")
10335
10336(define_insn "tls_tprel_lo_64"
b150f4f3
DE		 10337 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10338 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10339 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10340 UNSPEC_TLSTPRELLO))]
10341 "HAVE_AS_TLS && TARGET_64BIT"
10342 "addi %0,%1,%2@tprel@l")
10343
c1207243 10344;; "b" output constraint here and on tls_tls input to support linker tls
c4501e62
JJ		 10345;; optimization. The linker may edit the instructions emitted by a
10346;; tls_got_tprel/tls_tls pair to addis,addi.
10347(define_insn "tls_got_tprel_32"
b150f4f3
DE		 10348 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10349 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10350 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10351 UNSPEC_TLSGOTTPREL))]
10352 "HAVE_AS_TLS && !TARGET_64BIT"
10353 "lwz %0,%2@got@tprel(%1)")
10354
10355(define_insn "tls_got_tprel_64"
b150f4f3
DE		 10356 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
10357 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10358 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10359 UNSPEC_TLSGOTTPREL))]
10360 "HAVE_AS_TLS && TARGET_64BIT"
10361 "ld %0,%2@got@tprel(%1)")
10362
10363(define_insn "tls_tls_32"
b150f4f3
DE		 10364 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10365 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10366 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
10367 UNSPEC_TLSTLS))]
10368 "HAVE_AS_TLS && !TARGET_64BIT"
10369 "add %0,%1,%2@tls")
10370
10371(define_insn "tls_tls_64"
b150f4f3
DE		 10372 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10373 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
c4501e62
JJ		 10374 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
10375 UNSPEC_TLSTLS))]
10376 "HAVE_AS_TLS && TARGET_64BIT"
10377 "add %0,%1,%2@tls")
10378\f
1fd4e8c1
RK		 10379;; Next come insns related to the calling sequence.
10380;;
10381;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
7e69e155 10382;; We move the back-chain and decrement the stack pointer.
1fd4e8c1
RK		 10383
10384(define_expand "allocate_stack"
e42ac3de 10385 [(set (match_operand 0 "gpc_reg_operand" "")
a260abc9
DE		 10386 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10387 (set (reg 1)
10388 (minus (reg 1) (match_dup 1)))]
1fd4e8c1
RK		 10389 ""
10390 "
4697a36c 10391{ rtx chain = gen_reg_rtx (Pmode);
39403d82 10392 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
4697a36c 10393 rtx neg_op0;
1fd4e8c1
RK		 10394
10395 emit_move_insn (chain, stack_bot);
4697a36c 10396
a157febd
GK		 10397 /* Check stack bounds if necessary. */
10398 if (current_function_limit_stack)
10399 {
10400 rtx available;
6ae08853 10401 available = expand_binop (Pmode, sub_optab,
a157febd
GK		 10402 stack_pointer_rtx, stack_limit_rtx,
10403 NULL_RTX, 1, OPTAB_WIDEN);
10404 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10405 }
10406
e9a25f70
JL		 10407 if (GET_CODE (operands[1]) != CONST_INT
10408 || INTVAL (operands[1]) < -32767
10409 || INTVAL (operands[1]) > 32768)
4697a36c
MM		 10410 {
10411 neg_op0 = gen_reg_rtx (Pmode);
e6ca2c17 10412 if (TARGET_32BIT)
e9a25f70 10413 emit_insn (gen_negsi2 (neg_op0, operands[1]));
e6ca2c17 10414 else
e9a25f70 10415 emit_insn (gen_negdi2 (neg_op0, operands[1]));
4697a36c
MM		 10416 }
10417 else
e9a25f70 10418 neg_op0 = GEN_INT (- INTVAL (operands[1]));
4697a36c 10419
38c1f2d7 10420 if (TARGET_UPDATE)
2e6c9641 10421 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
38c1f2d7 10422 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
4697a36c 10423
38c1f2d7
MM		 10424 else
10425 {
10426 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10427 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
39403d82 10428 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
38c1f2d7 10429 }
e9a25f70
JL		 10430
10431 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
1fd4e8c1
RK		 10432 DONE;
10433}")
59257ff7
RK		 10434
10435;; These patterns say how to save and restore the stack pointer. We need not
10436;; save the stack pointer at function level since we are careful to
10437;; preserve the backchain. At block level, we have to restore the backchain
10438;; when we restore the stack pointer.
10439;;
10440;; For nonlocal gotos, we must save both the stack pointer and its
10441;; backchain and restore both. Note that in the nonlocal case, the
10442;; save area is a memory location.
10443
10444(define_expand "save_stack_function"
ff381587
MM		 10445 [(match_operand 0 "any_operand" "")
10446 (match_operand 1 "any_operand" "")]
59257ff7 10447 ""
ff381587 10448 "DONE;")
59257ff7
RK		 10449
10450(define_expand "restore_stack_function"
ff381587
MM		 10451 [(match_operand 0 "any_operand" "")
10452 (match_operand 1 "any_operand" "")]
59257ff7 10453 ""
ff381587 10454 "DONE;")
59257ff7 10455
2eef28ec
AM		 10456;; Adjust stack pointer (op0) to a new value (op1).
10457;; First copy old stack backchain to new location, and ensure that the
10458;; scheduler won't reorder the sp assignment before the backchain write.
59257ff7 10459(define_expand "restore_stack_block"
2eef28ec
AM		 10460 [(set (match_dup 2) (match_dup 3))
10461 (set (match_dup 4) (match_dup 2))
10462 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10463 (set (match_operand 0 "register_operand" "")
10464 (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10465 ""
10466 "
dfdfa60f 10467{
583da60a 10468 operands[1] = force_reg (Pmode, operands[1]);
dfdfa60f 10469 operands[2] = gen_reg_rtx (Pmode);
2eef28ec
AM		 10470 operands[3] = gen_frame_mem (Pmode, operands[0]);
10471 operands[4] = gen_frame_mem (Pmode, operands[1]);
10472 operands[5] = gen_frame_mem (BLKmode, operands[0]);
dfdfa60f 10473}")
59257ff7
RK		 10474
10475(define_expand "save_stack_nonlocal"
2eef28ec
AM		 10476 [(set (match_dup 3) (match_dup 4))
10477 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10478 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10479 ""
10480 "
10481{
11b25716 10482 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10483
10484 /* Copy the backchain to the first word, sp to the second. */
2eef28ec
AM		 10485 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10486 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10487 operands[3] = gen_reg_rtx (Pmode);
10488 operands[4] = gen_frame_mem (Pmode, operands[1]);
59257ff7 10489}")
7e69e155 10490
59257ff7 10491(define_expand "restore_stack_nonlocal"
2eef28ec
AM		 10492 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10493 (set (match_dup 3) (match_dup 4))
10494 (set (match_dup 5) (match_dup 2))
10495 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10496 (set (match_operand 0 "register_operand" "") (match_dup 3))]
59257ff7
RK		 10497 ""
10498 "
10499{
11b25716 10500 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10501
10502 /* Restore the backchain from the first word, sp from the second. */
2eef28ec
AM		 10503 operands[2] = gen_reg_rtx (Pmode);
10504 operands[3] = gen_reg_rtx (Pmode);
10505 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10506 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10507 operands[5] = gen_frame_mem (Pmode, operands[3]);
10508 operands[6] = gen_frame_mem (BLKmode, operands[0]);
59257ff7 10509}")
9ebbca7d
GK		 10510\f
10511;; TOC register handling.
b6c9286a 10512
9ebbca7d 10513;; Code to initialize the TOC register...
f0f6a223 10514
9ebbca7d 10515(define_insn "load_toc_aix_si"
e72247f4 10516 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 10517 (unspec:SI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10518 (use (reg:SI 2))])]
2bfcf297 10519 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
f0f6a223
RK		 10520 "*
10521{
9ebbca7d
GK		 10522 char buf[30];
10523 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
a8a05998 10524 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10525 operands[2] = gen_rtx_REG (Pmode, 2);
10526 return \"{l|lwz} %0,%1(%2)\";
f0f6a223
RK		 10527}"
10528 [(set_attr "type" "load")])
9ebbca7d
GK		 10529
10530(define_insn "load_toc_aix_di"
e72247f4 10531 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
615158e2 10532 (unspec:DI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10533 (use (reg:DI 2))])]
2bfcf297 10534 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9ebbca7d
GK		 10535 "*
10536{
10537 char buf[30];
f585a356
DE		 10538#ifdef TARGET_RELOCATABLE
10539 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10540 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10541#else
9ebbca7d 10542 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
f585a356 10543#endif
2bfcf297
DB		 10544 if (TARGET_ELF)
10545 strcat (buf, \"@toc\");
a8a05998 10546 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10547 operands[2] = gen_rtx_REG (Pmode, 2);
10548 return \"ld %0,%1(%2)\";
10549}"
10550 [(set_attr "type" "load")])
10551
10552(define_insn "load_toc_v4_pic_si"
1de43f85 10553 [(set (reg:SI LR_REGNO)
615158e2 10554 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
f607bc57 10555 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9ebbca7d
GK		 10556 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10557 [(set_attr "type" "branch")
10558 (set_attr "length" "4")])
10559
9ebbca7d 10560(define_insn "load_toc_v4_PIC_1"
1de43f85 10561 [(set (reg:SI LR_REGNO)
e65a3857
DE		 10562 (match_operand:SI 0 "immediate_operand" "s"))
10563 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
7f970b70
AM		 10564 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10565 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
e65a3857 10566 "bcl 20,31,%0\\n%0:"
9ebbca7d
GK		 10567 [(set_attr "type" "branch")
10568 (set_attr "length" "4")])
10569
10570(define_insn "load_toc_v4_PIC_1b"
1de43f85 10571 [(set (reg:SI LR_REGNO)
e65a3857 10572 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
c4501e62 10573 UNSPEC_TOCPTR))]
20b71b17 10574 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
e65a3857 10575 "bcl 20,31,$+8\\n\\t.long %0-$"
9ebbca7d
GK		 10576 [(set_attr "type" "branch")
10577 (set_attr "length" "8")])
10578
10579(define_insn "load_toc_v4_PIC_2"
f585a356 10580 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
a2900460 10581 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9ebbca7d
GK		 10582 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10583 (match_operand:SI 3 "immediate_operand" "s")))))]
20b71b17 10584 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9ebbca7d
GK		 10585 "{l|lwz} %0,%2-%3(%1)"
10586 [(set_attr "type" "load")])
10587
7f970b70
AM		 10588(define_insn "load_toc_v4_PIC_3b"
10589 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10590 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10591 (high:SI
10592 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10593 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10594 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10595 "{cau|addis} %0,%1,%2-%3@ha")
10596
10597(define_insn "load_toc_v4_PIC_3c"
10598 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10599 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10600 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10601 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10602 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10603 "{cal|addi} %0,%1,%2-%3@l")
f51eee6a 10604
9ebbca7d
GK		 10605;; If the TOC is shared over a translation unit, as happens with all
10606;; the kinds of PIC that we support, we need to restore the TOC
10607;; pointer only when jumping over units of translation.
f51eee6a 10608;; On Darwin, we need to reload the picbase.
9ebbca7d
GK		 10609
10610(define_expand "builtin_setjmp_receiver"
10611 [(use (label_ref (match_operand 0 "" "")))]
f607bc57 10612 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
f51eee6a
GK		 10613 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10614 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9ebbca7d
GK		 10615 "
10616{
84d7dd4a 10617#if TARGET_MACHO
f51eee6a
GK		 10618 if (DEFAULT_ABI == ABI_DARWIN)
10619 {
d24652ee 10620 const char *picbase = machopic_function_base_name ();
485bad26 10621 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
f51eee6a
GK		 10622 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10623 rtx tmplabrtx;
10624 char tmplab[20];
10625
10626 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10627 CODE_LABEL_NUMBER (operands[0]));
485bad26 10628 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
f51eee6a 10629
316fbf19 10630 emit_insn (gen_load_macho_picbase (tmplabrtx));
1de43f85 10631 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
b8a55285 10632 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
f51eee6a
GK		 10633 }
10634 else
84d7dd4a 10635#endif
f51eee6a 10636 rs6000_emit_load_toc_table (FALSE);
9ebbca7d
GK		 10637 DONE;
10638}")
7f970b70
AM		 10639
10640;; Elf specific ways of loading addresses for non-PIC code.
10641;; The output of this could be r0, but we make a very strong
10642;; preference for a base register because it will usually
10643;; be needed there.
10644(define_insn "elf_high"
10645 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10646 (high:SI (match_operand 1 "" "")))]
10647 "TARGET_ELF && ! TARGET_64BIT"
10648 "{liu|lis} %0,%1@ha")
10649
10650(define_insn "elf_low"
10651 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10652 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10653 (match_operand 2 "" "")))]
10654 "TARGET_ELF && ! TARGET_64BIT"
10655 "@
10656 {cal|la} %0,%2@l(%1)
10657 {ai|addic} %0,%1,%K2")
9ebbca7d
GK		 10658\f
10659;; A function pointer under AIX is a pointer to a data area whose first word
10660;; contains the actual address of the function, whose second word contains a
b6c9286a
MM		 10661;; pointer to its TOC, and whose third word contains a value to place in the
10662;; static chain register (r11). Note that if we load the static chain, our
1fd4e8c1 10663;; "trampoline" need not have any executable code.
b6c9286a 10664
cccf3bdc
DE		 10665(define_expand "call_indirect_aix32"
10666 [(set (match_dup 2)
10667 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10668 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10669 (reg:SI 2))
10670 (set (reg:SI 2)
10671 (mem:SI (plus:SI (match_dup 0)
10672 (const_int 4))))
10673 (set (reg:SI 11)
10674 (mem:SI (plus:SI (match_dup 0)
10675 (const_int 8))))
10676 (parallel [(call (mem:SI (match_dup 2))
10677 (match_operand 1 "" ""))
10678 (use (reg:SI 2))
10679 (use (reg:SI 11))
10680 (set (reg:SI 2)
10681 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 10682 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10683 "TARGET_32BIT"
10684 "
10685{ operands[2] = gen_reg_rtx (SImode); }")
b6c9286a 10686
cccf3bdc
DE		 10687(define_expand "call_indirect_aix64"
10688 [(set (match_dup 2)
10689 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10690 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10691 (reg:DI 2))
10692 (set (reg:DI 2)
10693 (mem:DI (plus:DI (match_dup 0)
10694 (const_int 8))))
10695 (set (reg:DI 11)
10696 (mem:DI (plus:DI (match_dup 0)
10697 (const_int 16))))
10698 (parallel [(call (mem:SI (match_dup 2))
10699 (match_operand 1 "" ""))
10700 (use (reg:DI 2))
10701 (use (reg:DI 11))
10702 (set (reg:DI 2)
10703 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 10704 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10705 "TARGET_64BIT"
10706 "
10707{ operands[2] = gen_reg_rtx (DImode); }")
b6c9286a 10708
cccf3bdc
DE		 10709(define_expand "call_value_indirect_aix32"
10710 [(set (match_dup 3)
10711 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10712 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10713 (reg:SI 2))
10714 (set (reg:SI 2)
10715 (mem:SI (plus:SI (match_dup 1)
10716 (const_int 4))))
10717 (set (reg:SI 11)
10718 (mem:SI (plus:SI (match_dup 1)
10719 (const_int 8))))
10720 (parallel [(set (match_operand 0 "" "")
10721 (call (mem:SI (match_dup 3))
10722 (match_operand 2 "" "")))
10723 (use (reg:SI 2))
10724 (use (reg:SI 11))
10725 (set (reg:SI 2)
10726 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 10727 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10728 "TARGET_32BIT"
10729 "
10730{ operands[3] = gen_reg_rtx (SImode); }")
b6c9286a 10731
cccf3bdc
DE		 10732(define_expand "call_value_indirect_aix64"
10733 [(set (match_dup 3)
10734 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10735 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10736 (reg:DI 2))
10737 (set (reg:DI 2)
10738 (mem:DI (plus:DI (match_dup 1)
10739 (const_int 8))))
10740 (set (reg:DI 11)
10741 (mem:DI (plus:DI (match_dup 1)
10742 (const_int 16))))
10743 (parallel [(set (match_operand 0 "" "")
10744 (call (mem:SI (match_dup 3))
10745 (match_operand 2 "" "")))
10746 (use (reg:DI 2))
10747 (use (reg:DI 11))
10748 (set (reg:DI 2)
10749 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 10750 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10751 "TARGET_64BIT"
10752 "
10753{ operands[3] = gen_reg_rtx (DImode); }")
1fd4e8c1 10754
b6c9286a 10755;; Now the definitions for the call and call_value insns
1fd4e8c1 10756(define_expand "call"
a260abc9 10757 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
1fd4e8c1 10758 (match_operand 1 "" ""))
4697a36c 10759 (use (match_operand 2 "" ""))
1de43f85 10760 (clobber (reg:SI LR_REGNO))])]
1fd4e8c1
RK		 10761 ""
10762 "
10763{
ee890fe2 10764#if TARGET_MACHO
ab82a49f 10765 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10766 operands[0] = machopic_indirect_call_target (operands[0]);
10767#endif
10768
37409796
NS		 10769 gcc_assert (GET_CODE (operands[0]) == MEM);
10770 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
1fd4e8c1
RK		 10771
10772 operands[0] = XEXP (operands[0], 0);
7509c759 10773
7f970b70
AM		 10774 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10775 && flag_pic
10776 && GET_CODE (operands[0]) == SYMBOL_REF
10777 && !SYMBOL_REF_LOCAL_P (operands[0]))
10778 {
10779 rtx call;
10780 rtvec tmp;
10781
10782 tmp = gen_rtvec (3,
10783 gen_rtx_CALL (VOIDmode,
10784 gen_rtx_MEM (SImode, operands[0]),
10785 operands[1]),
10786 gen_rtx_USE (VOIDmode, operands[2]),
ee05ef56 10787 gen_rtx_CLOBBER (VOIDmode,
1de43f85 10788 gen_rtx_REG (Pmode, LR_REGNO)));
7f970b70
AM		 10789 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10790 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10791 DONE;
10792 }
10793
6a4cee5f 10794 if (GET_CODE (operands[0]) != SYMBOL_REF
473f51b6 10795 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
efdba735 10796 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
1fd4e8c1 10797 {
6a4cee5f
MM		 10798 if (INTVAL (operands[2]) & CALL_LONG)
10799 operands[0] = rs6000_longcall_ref (operands[0]);
10800
37409796
NS		 10801 switch (DEFAULT_ABI)
10802 {
10803 case ABI_V4:
10804 case ABI_DARWIN:
10805 operands[0] = force_reg (Pmode, operands[0]);
10806 break;
1fd4e8c1 10807
37409796 10808 case ABI_AIX:
cccf3bdc
DE		 10809 /* AIX function pointers are really pointers to a three word
10810 area. */
10811 emit_call_insn (TARGET_32BIT
10812 ? gen_call_indirect_aix32 (force_reg (SImode,
10813 operands[0]),
10814 operands[1])
10815 : gen_call_indirect_aix64 (force_reg (DImode,
10816 operands[0]),
10817 operands[1]));
10818 DONE;
37409796
NS		 10819
10820 default:
10821 gcc_unreachable ();
b6c9286a 10822 }
1fd4e8c1
RK		 10823 }
10824}")
10825
10826(define_expand "call_value"
10827 [(parallel [(set (match_operand 0 "" "")
a260abc9 10828 (call (mem:SI (match_operand 1 "address_operand" ""))
1fd4e8c1 10829 (match_operand 2 "" "")))
4697a36c 10830 (use (match_operand 3 "" ""))
1de43f85 10831 (clobber (reg:SI LR_REGNO))])]
1fd4e8c1
RK		 10832 ""
10833 "
10834{
ee890fe2 10835#if TARGET_MACHO
ab82a49f 10836 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10837 operands[1] = machopic_indirect_call_target (operands[1]);
10838#endif
10839
37409796
NS		 10840 gcc_assert (GET_CODE (operands[1]) == MEM);
10841 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
1fd4e8c1
RK		 10842
10843 operands[1] = XEXP (operands[1], 0);
7509c759 10844
7f970b70
AM		 10845 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10846 && flag_pic
10847 && GET_CODE (operands[1]) == SYMBOL_REF
10848 && !SYMBOL_REF_LOCAL_P (operands[1]))
10849 {
10850 rtx call;
10851 rtvec tmp;
10852
10853 tmp = gen_rtvec (3,
10854 gen_rtx_SET (VOIDmode,
10855 operands[0],
10856 gen_rtx_CALL (VOIDmode,
10857 gen_rtx_MEM (SImode,
10858 operands[1]),
10859 operands[2])),
10860 gen_rtx_USE (VOIDmode, operands[3]),
ee05ef56 10861 gen_rtx_CLOBBER (VOIDmode,
1de43f85 10862 gen_rtx_REG (Pmode, LR_REGNO)));
7f970b70
AM		 10863 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10864 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10865 DONE;
10866 }
10867
6a4cee5f 10868 if (GET_CODE (operands[1]) != SYMBOL_REF
473f51b6 10869 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
efdba735 10870 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
1fd4e8c1 10871 {
6756293c 10872 if (INTVAL (operands[3]) & CALL_LONG)
6a4cee5f
MM		 10873 operands[1] = rs6000_longcall_ref (operands[1]);
10874
37409796
NS		 10875 switch (DEFAULT_ABI)
10876 {
10877 case ABI_V4:
10878 case ABI_DARWIN:
10879 operands[1] = force_reg (Pmode, operands[1]);
10880 break;
1fd4e8c1 10881
37409796 10882 case ABI_AIX:
cccf3bdc
DE		 10883 /* AIX function pointers are really pointers to a three word
10884 area. */
10885 emit_call_insn (TARGET_32BIT
10886 ? gen_call_value_indirect_aix32 (operands[0],
10887 force_reg (SImode,
10888 operands[1]),
10889 operands[2])
10890 : gen_call_value_indirect_aix64 (operands[0],
10891 force_reg (DImode,
10892 operands[1]),
10893 operands[2]));
10894 DONE;
37409796
NS		 10895
10896 default:
10897 gcc_unreachable ();
b6c9286a 10898 }
1fd4e8c1
RK		 10899 }
10900}")
10901
04780ee7 10902;; Call to function in current module. No TOC pointer reload needed.
a0ab749a 10903;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10904;; either the function was not prototyped, or it was prototyped as a
10905;; variable argument function. It is > 0 if FP registers were passed
10906;; and < 0 if they were not.
04780ee7 10907
a260abc9 10908(define_insn "*call_local32"
4697a36c
MM		 10909 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10910 (match_operand 1 "" "g,g"))
10911 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 10912 (clobber (reg:SI LR_REGNO))]
5a19791c 10913 "(INTVAL (operands[2]) & CALL_LONG) == 0"
4697a36c
MM		 10914 "*
10915{
6a4cee5f
MM		 10916 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10917 output_asm_insn (\"crxor 6,6,6\", operands);
10918
10919 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10920 output_asm_insn (\"creqv 6,6,6\", operands);
4697a36c 10921
a226df46 10922 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
4697a36c 10923}"
b7ff3d82
DE		 10924 [(set_attr "type" "branch")
10925 (set_attr "length" "4,8")])
04780ee7 10926
a260abc9
DE		 10927(define_insn "*call_local64"
10928 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10929 (match_operand 1 "" "g,g"))
10930 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 10931 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 10932 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10933 "*
10934{
10935 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10936 output_asm_insn (\"crxor 6,6,6\", operands);
10937
10938 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10939 output_asm_insn (\"creqv 6,6,6\", operands);
10940
10941 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10942}"
10943 [(set_attr "type" "branch")
10944 (set_attr "length" "4,8")])
10945
cccf3bdc 10946(define_insn "*call_value_local32"
d18dba68 10947 [(set (match_operand 0 "" "")
a260abc9
DE		 10948 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10949 (match_operand 2 "" "g,g")))
10950 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 10951 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 10952 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10953 "*
10954{
10955 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10956 output_asm_insn (\"crxor 6,6,6\", operands);
10957
10958 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10959 output_asm_insn (\"creqv 6,6,6\", operands);
10960
10961 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10962}"
10963 [(set_attr "type" "branch")
10964 (set_attr "length" "4,8")])
10965
10966
cccf3bdc 10967(define_insn "*call_value_local64"
d18dba68 10968 [(set (match_operand 0 "" "")
a260abc9
DE		 10969 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10970 (match_operand 2 "" "g,g")))
10971 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 10972 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 10973 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10974 "*
10975{
10976 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10977 output_asm_insn (\"crxor 6,6,6\", operands);
10978
10979 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10980 output_asm_insn (\"creqv 6,6,6\", operands);
10981
10982 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10983}"
10984 [(set_attr "type" "branch")
10985 (set_attr "length" "4,8")])
10986
04780ee7 10987;; Call to function which may be in another module. Restore the TOC
911f679c 10988;; pointer (r2) after the call unless this is System V.
a0ab749a 10989;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10990;; either the function was not prototyped, or it was prototyped as a
10991;; variable argument function. It is > 0 if FP registers were passed
10992;; and < 0 if they were not.
04780ee7 10993
cccf3bdc 10994(define_insn "*call_indirect_nonlocal_aix32"
70ae0191
DE		 10995 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10996 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 10997 (use (reg:SI 2))
10998 (use (reg:SI 11))
10999 (set (reg:SI 2)
11000 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 11001 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11002 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11003 "b%T0l\;{l|lwz} 2,20(1)"
11004 [(set_attr "type" "jmpreg")
11005 (set_attr "length" "8")])
11006
a260abc9 11007(define_insn "*call_nonlocal_aix32"
cc4d5fec 11008 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11009 (match_operand 1 "" "g"))
11010 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11011 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11012 "TARGET_32BIT
11013 && DEFAULT_ABI == ABI_AIX
5a19791c 11014 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 11015 "bl %z0\;%."
b7ff3d82 11016 [(set_attr "type" "branch")
cccf3bdc
DE		 11017 (set_attr "length" "8")])
11018
11019(define_insn "*call_indirect_nonlocal_aix64"
70ae0191
DE		 11020 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11021 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 11022 (use (reg:DI 2))
11023 (use (reg:DI 11))
11024 (set (reg:DI 2)
11025 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 11026 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11027 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11028 "b%T0l\;ld 2,40(1)"
11029 [(set_attr "type" "jmpreg")
11030 (set_attr "length" "8")])
59313e4e 11031
a260abc9 11032(define_insn "*call_nonlocal_aix64"
cc4d5fec 11033 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11034 (match_operand 1 "" "g"))
11035 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11036 (clobber (reg:SI LR_REGNO))]
6ae08853 11037 "TARGET_64BIT
9ebbca7d 11038 && DEFAULT_ABI == ABI_AIX
a260abc9 11039 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 11040 "bl %z0\;%."
a260abc9 11041 [(set_attr "type" "branch")
cccf3bdc 11042 (set_attr "length" "8")])
7509c759 11043
cccf3bdc 11044(define_insn "*call_value_indirect_nonlocal_aix32"
d18dba68 11045 [(set (match_operand 0 "" "")
70ae0191
DE		 11046 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11047 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 11048 (use (reg:SI 2))
11049 (use (reg:SI 11))
11050 (set (reg:SI 2)
11051 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 11052 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11053 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11054 "b%T1l\;{l|lwz} 2,20(1)"
11055 [(set_attr "type" "jmpreg")
11056 (set_attr "length" "8")])
1fd4e8c1 11057
cccf3bdc 11058(define_insn "*call_value_nonlocal_aix32"
d18dba68 11059 [(set (match_operand 0 "" "")
cc4d5fec 11060 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11061 (match_operand 2 "" "g")))
11062 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11063 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11064 "TARGET_32BIT
11065 && DEFAULT_ABI == ABI_AIX
a260abc9 11066 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc 11067 "bl %z1\;%."
b7ff3d82 11068 [(set_attr "type" "branch")
cccf3bdc 11069 (set_attr "length" "8")])
04780ee7 11070
cccf3bdc 11071(define_insn "*call_value_indirect_nonlocal_aix64"
d18dba68 11072 [(set (match_operand 0 "" "")
70ae0191
DE		 11073 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11074 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 11075 (use (reg:DI 2))
11076 (use (reg:DI 11))
11077 (set (reg:DI 2)
11078 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 11079 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11080 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11081 "b%T1l\;ld 2,40(1)"
11082 [(set_attr "type" "jmpreg")
11083 (set_attr "length" "8")])
11084
11085(define_insn "*call_value_nonlocal_aix64"
d18dba68 11086 [(set (match_operand 0 "" "")
cc4d5fec 11087 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11088 (match_operand 2 "" "g")))
11089 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11090 (clobber (reg:SI LR_REGNO))]
6ae08853 11091 "TARGET_64BIT
9ebbca7d 11092 && DEFAULT_ABI == ABI_AIX
5a19791c 11093 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc
DE		 11094 "bl %z1\;%."
11095 [(set_attr "type" "branch")
11096 (set_attr "length" "8")])
11097
11098;; A function pointer under System V is just a normal pointer
11099;; operands[0] is the function pointer
11100;; operands[1] is the stack size to clean up
11101;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11102;; which indicates how to set cr1
11103
9613eaff
SH		 11104(define_insn "*call_indirect_nonlocal_sysv<mode>"
11105 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11106 (match_operand 1 "" "g,g,g,g"))
11107 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
1de43f85 11108 (clobber (reg:SI LR_REGNO))]
50d440bc 11109 "DEFAULT_ABI == ABI_V4
f607bc57 11110 || DEFAULT_ABI == ABI_DARWIN"
911f679c 11111{
cccf3bdc 11112 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11113 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f 11114
cccf3bdc 11115 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11116 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11117
a5c76ee6
ZW		 11118 return "b%T0l";
11119}
6d0a8091
DJ		 11120 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11121 (set_attr "length" "4,4,8,8")])
cccf3bdc 11122
9613eaff
SH		 11123(define_insn "*call_nonlocal_sysv<mode>"
11124 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11125 (match_operand 1 "" "g,g"))
11126 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11127 (clobber (reg:SI LR_REGNO))]
efdba735
SH		 11128 "(DEFAULT_ABI == ABI_DARWIN
11129 || (DEFAULT_ABI == ABI_V4
11130 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11131{
11132 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11133 output_asm_insn ("crxor 6,6,6", operands);
11134
11135 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11136 output_asm_insn ("creqv 6,6,6", operands);
11137
c989f2f7 11138#if TARGET_MACHO
efdba735
SH		 11139 return output_call(insn, operands, 0, 2);
11140#else
7f970b70
AM		 11141 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11142 {
11143 if (TARGET_SECURE_PLT && flag_pic == 2)
11144 /* The magic 32768 offset here and in the other sysv call insns
11145 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11146 See sysv4.h:toc_section. */
11147 return "bl %z0+32768@plt";
11148 else
11149 return "bl %z0@plt";
11150 }
11151 else
11152 return "bl %z0";
6ae08853 11153#endif
a5c76ee6
ZW		 11154}
11155 [(set_attr "type" "branch,branch")
11156 (set_attr "length" "4,8")])
11157
9613eaff 11158(define_insn "*call_value_indirect_nonlocal_sysv<mode>"
d18dba68 11159 [(set (match_operand 0 "" "")
9613eaff 11160 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11161 (match_operand 2 "" "g,g,g,g")))
11162 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
1de43f85 11163 (clobber (reg:SI LR_REGNO))]
50d440bc 11164 "DEFAULT_ABI == ABI_V4
f607bc57 11165 || DEFAULT_ABI == ABI_DARWIN"
b6c9286a 11166{
6a4cee5f 11167 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11168 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f
MM		 11169
11170 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11171 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11172
a5c76ee6
ZW		 11173 return "b%T1l";
11174}
6d0a8091
DJ		 11175 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11176 (set_attr "length" "4,4,8,8")])
a5c76ee6 11177
9613eaff 11178(define_insn "*call_value_nonlocal_sysv<mode>"
a5c76ee6 11179 [(set (match_operand 0 "" "")
9613eaff 11180 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11181 (match_operand 2 "" "g,g")))
11182 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11183 (clobber (reg:SI LR_REGNO))]
efdba735
SH		 11184 "(DEFAULT_ABI == ABI_DARWIN
11185 || (DEFAULT_ABI == ABI_V4
11186 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11187{
11188 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11189 output_asm_insn ("crxor 6,6,6", operands);
11190
11191 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11192 output_asm_insn ("creqv 6,6,6", operands);
11193
c989f2f7 11194#if TARGET_MACHO
efdba735
SH		 11195 return output_call(insn, operands, 1, 3);
11196#else
7f970b70
AM		 11197 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11198 {
11199 if (TARGET_SECURE_PLT && flag_pic == 2)
11200 return "bl %z1+32768@plt";
11201 else
11202 return "bl %z1@plt";
11203 }
11204 else
11205 return "bl %z1";
6ae08853 11206#endif
a5c76ee6
ZW		 11207}
11208 [(set_attr "type" "branch,branch")
11209 (set_attr "length" "4,8")])
e6f948e3
RK		 11210
11211;; Call subroutine returning any type.
e6f948e3
RK		 11212(define_expand "untyped_call"
11213 [(parallel [(call (match_operand 0 "" "")
11214 (const_int 0))
11215 (match_operand 1 "" "")
11216 (match_operand 2 "" "")])]
11217 ""
11218 "
11219{
11220 int i;
11221
7d70b8b2 11222 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
e6f948e3
RK		 11223
11224 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11225 {
11226 rtx set = XVECEXP (operands[2], 0, i);
11227 emit_move_insn (SET_DEST (set), SET_SRC (set));
11228 }
11229
11230 /* The optimizer does not know that the call sets the function value
11231 registers we stored in the result block. We avoid problems by
11232 claiming that all hard registers are used and clobbered at this
11233 point. */
11234 emit_insn (gen_blockage ());
11235
11236 DONE;
11237}")
11238
5e1bf043
DJ		 11239;; sibling call patterns
11240(define_expand "sibcall"
11241 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11242 (match_operand 1 "" ""))
11243 (use (match_operand 2 "" ""))
1de43f85 11244 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11245 (return)])]
11246 ""
11247 "
11248{
11249#if TARGET_MACHO
ab82a49f 11250 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11251 operands[0] = machopic_indirect_call_target (operands[0]);
11252#endif
11253
37409796
NS		 11254 gcc_assert (GET_CODE (operands[0]) == MEM);
11255 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
5e1bf043
DJ		 11256
11257 operands[0] = XEXP (operands[0], 0);
5e1bf043
DJ		 11258}")
11259
11260;; this and similar patterns must be marked as using LR, otherwise
11261;; dataflow will try to delete the store into it. This is true
11262;; even when the actual reg to jump to is in CTR, when LR was
11263;; saved and restored around the PIC-setting BCL.
11264(define_insn "*sibcall_local32"
11265 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11266 (match_operand 1 "" "g,g"))
11267 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11268 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11269 (return)]
11270 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11271 "*
11272{
11273 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11274 output_asm_insn (\"crxor 6,6,6\", operands);
11275
11276 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11277 output_asm_insn (\"creqv 6,6,6\", operands);
11278
11279 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11280}"
11281 [(set_attr "type" "branch")
11282 (set_attr "length" "4,8")])
11283
11284(define_insn "*sibcall_local64"
11285 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11286 (match_operand 1 "" "g,g"))
11287 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11288 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11289 (return)]
11290 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11291 "*
11292{
11293 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11294 output_asm_insn (\"crxor 6,6,6\", operands);
11295
11296 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11297 output_asm_insn (\"creqv 6,6,6\", operands);
11298
11299 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11300}"
11301 [(set_attr "type" "branch")
11302 (set_attr "length" "4,8")])
11303
11304(define_insn "*sibcall_value_local32"
11305 [(set (match_operand 0 "" "")
11306 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11307 (match_operand 2 "" "g,g")))
11308 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11309 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11310 (return)]
11311 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11312 "*
11313{
11314 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11315 output_asm_insn (\"crxor 6,6,6\", operands);
11316
11317 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11318 output_asm_insn (\"creqv 6,6,6\", operands);
11319
11320 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11321}"
11322 [(set_attr "type" "branch")
11323 (set_attr "length" "4,8")])
11324
11325
11326(define_insn "*sibcall_value_local64"
11327 [(set (match_operand 0 "" "")
11328 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11329 (match_operand 2 "" "g,g")))
11330 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11331 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11332 (return)]
11333 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11334 "*
11335{
11336 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11337 output_asm_insn (\"crxor 6,6,6\", operands);
11338
11339 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11340 output_asm_insn (\"creqv 6,6,6\", operands);
11341
11342 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11343}"
11344 [(set_attr "type" "branch")
11345 (set_attr "length" "4,8")])
11346
11347(define_insn "*sibcall_nonlocal_aix32"
11348 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11349 (match_operand 1 "" "g"))
11350 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11351 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11352 (return)]
11353 "TARGET_32BIT
11354 && DEFAULT_ABI == ABI_AIX
11355 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11356 "b %z0"
11357 [(set_attr "type" "branch")
11358 (set_attr "length" "4")])
11359
11360(define_insn "*sibcall_nonlocal_aix64"
11361 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11362 (match_operand 1 "" "g"))
11363 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11364 (use (reg:SI LR_REGNO))
5e1bf043 11365 (return)]
6ae08853 11366 "TARGET_64BIT
5e1bf043
DJ		 11367 && DEFAULT_ABI == ABI_AIX
11368 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11369 "b %z0"
11370 [(set_attr "type" "branch")
11371 (set_attr "length" "4")])
11372
11373(define_insn "*sibcall_value_nonlocal_aix32"
11374 [(set (match_operand 0 "" "")
11375 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11376 (match_operand 2 "" "g")))
11377 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11378 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11379 (return)]
11380 "TARGET_32BIT
11381 && DEFAULT_ABI == ABI_AIX
11382 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11383 "b %z1"
11384 [(set_attr "type" "branch")
11385 (set_attr "length" "4")])
11386
11387(define_insn "*sibcall_value_nonlocal_aix64"
11388 [(set (match_operand 0 "" "")
11389 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11390 (match_operand 2 "" "g")))
11391 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11392 (use (reg:SI LR_REGNO))
5e1bf043 11393 (return)]
6ae08853 11394 "TARGET_64BIT
5e1bf043
DJ		 11395 && DEFAULT_ABI == ABI_AIX
11396 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11397 "b %z1"
11398 [(set_attr "type" "branch")
11399 (set_attr "length" "4")])
11400
9613eaff
SH		 11401(define_insn "*sibcall_nonlocal_sysv<mode>"
11402 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11403 (match_operand 1 "" ""))
11404 (use (match_operand 2 "immediate_operand" "O,n"))
1de43f85 11405 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11406 (return)]
11407 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11408 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11409 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11410 "*
11411{
11412 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11413 output_asm_insn (\"crxor 6,6,6\", operands);
11414
11415 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11416 output_asm_insn (\"creqv 6,6,6\", operands);
11417
7f970b70
AM		 11418 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11419 {
11420 if (TARGET_SECURE_PLT && flag_pic == 2)
11421 return \"b %z0+32768@plt\";
11422 else
11423 return \"b %z0@plt\";
11424 }
11425 else
11426 return \"b %z0\";
5e1bf043
DJ		 11427}"
11428 [(set_attr "type" "branch,branch")
11429 (set_attr "length" "4,8")])
11430
11431(define_expand "sibcall_value"
11432 [(parallel [(set (match_operand 0 "register_operand" "")
11433 (call (mem:SI (match_operand 1 "address_operand" ""))
11434 (match_operand 2 "" "")))
11435 (use (match_operand 3 "" ""))
1de43f85 11436 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11437 (return)])]
11438 ""
11439 "
11440{
11441#if TARGET_MACHO
ab82a49f 11442 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11443 operands[1] = machopic_indirect_call_target (operands[1]);
11444#endif
11445
37409796
NS		 11446 gcc_assert (GET_CODE (operands[1]) == MEM);
11447 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
5e1bf043
DJ		 11448
11449 operands[1] = XEXP (operands[1], 0);
5e1bf043
DJ		 11450}")
11451
9613eaff 11452(define_insn "*sibcall_value_nonlocal_sysv<mode>"
5e1bf043 11453 [(set (match_operand 0 "" "")
9613eaff 11454 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11455 (match_operand 2 "" "")))
11456 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11457 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11458 (return)]
11459 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11460 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11461 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11462 "*
11463{
11464 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11465 output_asm_insn (\"crxor 6,6,6\", operands);
11466
11467 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11468 output_asm_insn (\"creqv 6,6,6\", operands);
11469
7f970b70
AM		 11470 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11471 {
11472 if (TARGET_SECURE_PLT && flag_pic == 2)
11473 return \"b %z1+32768@plt\";
11474 else
11475 return \"b %z1@plt\";
11476 }
11477 else
11478 return \"b %z1\";
5e1bf043
DJ		 11479}"
11480 [(set_attr "type" "branch,branch")
11481 (set_attr "length" "4,8")])
11482
11483(define_expand "sibcall_epilogue"
11484 [(use (const_int 0))]
11485 "TARGET_SCHED_PROLOG"
11486 "
11487{
11488 rs6000_emit_epilogue (TRUE);
11489 DONE;
11490}")
11491
e6f948e3
RK		 11492;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11493;; all of memory. This blocks insns from being moved across this point.
11494
11495(define_insn "blockage"
615158e2 11496 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
e6f948e3
RK		 11497 ""
11498 "")
1fd4e8c1
RK		 11499\f
11500;; Compare insns are next. Note that the RS/6000 has two types of compares,
7e69e155 11501;; signed & unsigned, and one type of branch.
1fd4e8c1
RK		 11502;;
11503;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11504;; insns, and branches. We store the operands of compares until we see
11505;; how it is used.
4ae234b0 11506(define_expand "cmp<mode>"
1fd4e8c1 11507 [(set (cc0)
4ae234b0
GK		 11508 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11509 (match_operand:GPR 1 "reg_or_short_operand" "")))]
1fd4e8c1
RK		 11510 ""
11511 "
11512{
11513 /* Take care of the possibility that operands[1] might be negative but
11514 this might be a logical operation. That insn doesn't exist. */
11515 if (GET_CODE (operands[1]) == CONST_INT
11516 && INTVAL (operands[1]) < 0)
4ae234b0 11517 operands[1] = force_reg (<MODE>mode, operands[1]);
1fd4e8c1
RK		 11518
11519 rs6000_compare_op0 = operands[0];
11520 rs6000_compare_op1 = operands[1];
11521 rs6000_compare_fp_p = 0;
11522 DONE;
11523}")
11524
4ae234b0
GK		 11525(define_expand "cmp<mode>"
11526 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11527 (match_operand:FP 1 "gpc_reg_operand" "")))]
11528 ""
d6f99ca4
DE		 11529 "
11530{
11531 rs6000_compare_op0 = operands[0];
11532 rs6000_compare_op1 = operands[1];
11533 rs6000_compare_fp_p = 1;
11534 DONE;
11535}")
11536
1fd4e8c1 11537(define_expand "beq"
39a10a29 11538 [(use (match_operand 0 "" ""))]
1fd4e8c1 11539 ""
39a10a29 11540 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 11541
11542(define_expand "bne"
39a10a29 11543 [(use (match_operand 0 "" ""))]
1fd4e8c1 11544 ""
39a10a29 11545 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
1fd4e8c1 11546
39a10a29
GK		 11547(define_expand "bge"
11548 [(use (match_operand 0 "" ""))]
1fd4e8c1 11549 ""
39a10a29 11550 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
1fd4e8c1
RK		 11551
11552(define_expand "bgt"
39a10a29 11553 [(use (match_operand 0 "" ""))]
1fd4e8c1 11554 ""
39a10a29 11555 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
1fd4e8c1
RK		 11556
11557(define_expand "ble"
39a10a29 11558 [(use (match_operand 0 "" ""))]
1fd4e8c1 11559 ""
39a10a29 11560 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
1fd4e8c1 11561
39a10a29
GK		 11562(define_expand "blt"
11563 [(use (match_operand 0 "" ""))]
1fd4e8c1 11564 ""
39a10a29 11565 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
1fd4e8c1 11566
39a10a29
GK		 11567(define_expand "bgeu"
11568 [(use (match_operand 0 "" ""))]
1fd4e8c1 11569 ""
39a10a29 11570 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
1fd4e8c1 11571
39a10a29
GK		 11572(define_expand "bgtu"
11573 [(use (match_operand 0 "" ""))]
1fd4e8c1 11574 ""
39a10a29 11575 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
1fd4e8c1 11576
39a10a29
GK		 11577(define_expand "bleu"
11578 [(use (match_operand 0 "" ""))]
1fd4e8c1 11579 ""
39a10a29 11580 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
1fd4e8c1 11581
39a10a29
GK		 11582(define_expand "bltu"
11583 [(use (match_operand 0 "" ""))]
1fd4e8c1 11584 ""
39a10a29 11585 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
1fd4e8c1 11586
1c882ea4 11587(define_expand "bunordered"
39a10a29 11588 [(use (match_operand 0 "" ""))]
8ef65e3d 11589 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11590 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
1c882ea4
GK		 11591
11592(define_expand "bordered"
39a10a29 11593 [(use (match_operand 0 "" ""))]
8ef65e3d 11594 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11595 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
1c882ea4
GK		 11596
11597(define_expand "buneq"
39a10a29 11598 [(use (match_operand 0 "" ""))]
b26941b4 11599 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11600 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
1c882ea4
GK		 11601
11602(define_expand "bunge"
39a10a29 11603 [(use (match_operand 0 "" ""))]
b26941b4 11604 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11605 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
1c882ea4
GK		 11606
11607(define_expand "bungt"
39a10a29 11608 [(use (match_operand 0 "" ""))]
b26941b4 11609 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11610 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
1c882ea4
GK		 11611
11612(define_expand "bunle"
39a10a29 11613 [(use (match_operand 0 "" ""))]
b26941b4 11614 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11615 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
1c882ea4
GK		 11616
11617(define_expand "bunlt"
39a10a29 11618 [(use (match_operand 0 "" ""))]
b26941b4 11619 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11620 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
1c882ea4
GK		 11621
11622(define_expand "bltgt"
39a10a29 11623 [(use (match_operand 0 "" ""))]
1c882ea4 11624 ""
39a10a29 11625 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
1c882ea4 11626
1fd4e8c1
RK		 11627;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11628;; For SEQ, likewise, except that comparisons with zero should be done
11629;; with an scc insns. However, due to the order that combine see the
11630;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11631;; the cases we don't want to handle.
11632(define_expand "seq"
39a10a29 11633 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11634 ""
39a10a29 11635 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 11636
11637(define_expand "sne"
39a10a29 11638 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11639 ""
11640 "
6ae08853 11641{
39a10a29 11642 if (! rs6000_compare_fp_p)
1fd4e8c1
RK		 11643 FAIL;
11644
6ae08853 11645 rs6000_emit_sCOND (NE, operands[0]);
39a10a29 11646 DONE;
1fd4e8c1
RK		 11647}")
11648
b7053a3f
GK		 11649;; A >= 0 is best done the portable way for A an integer.
11650(define_expand "sge"
39a10a29 11651 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11652 ""
11653 "
5638268e 11654{
e56d7409 11655 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11656 FAIL;
11657
b7053a3f 11658 rs6000_emit_sCOND (GE, operands[0]);
39a10a29 11659 DONE;
1fd4e8c1
RK		 11660}")
11661
b7053a3f
GK		 11662;; A > 0 is best done using the portable sequence, so fail in that case.
11663(define_expand "sgt"
39a10a29 11664 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11665 ""
11666 "
5638268e 11667{
e56d7409 11668 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11669 FAIL;
11670
6ae08853 11671 rs6000_emit_sCOND (GT, operands[0]);
39a10a29 11672 DONE;
1fd4e8c1
RK		 11673}")
11674
b7053a3f
GK		 11675;; A <= 0 is best done the portable way for A an integer.
11676(define_expand "sle"
39a10a29 11677 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11678 ""
5638268e
DE		 11679 "
11680{
e56d7409 11681 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
5638268e
DE		 11682 FAIL;
11683
6ae08853 11684 rs6000_emit_sCOND (LE, operands[0]);
5638268e
DE		 11685 DONE;
11686}")
1fd4e8c1 11687
b7053a3f
GK		 11688;; A < 0 is best done in the portable way for A an integer.
11689(define_expand "slt"
39a10a29 11690 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11691 ""
11692 "
5638268e 11693{
e56d7409 11694 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11695 FAIL;
11696
6ae08853 11697 rs6000_emit_sCOND (LT, operands[0]);
39a10a29 11698 DONE;
1fd4e8c1
RK		 11699}")
11700
b7053a3f
GK		 11701(define_expand "sgeu"
11702 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11703 ""
11704 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11705
1fd4e8c1 11706(define_expand "sgtu"
39a10a29 11707 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11708 ""
39a10a29 11709 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
1fd4e8c1 11710
b7053a3f
GK		 11711(define_expand "sleu"
11712 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11713 ""
11714 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11715
1fd4e8c1 11716(define_expand "sltu"
39a10a29 11717 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11718 ""
39a10a29 11719 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
1fd4e8c1 11720
b7053a3f 11721(define_expand "sunordered"
39a10a29 11722 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
8ef65e3d 11723 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f 11724 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
1fd4e8c1 11725
b7053a3f 11726(define_expand "sordered"
39a10a29 11727 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
8ef65e3d 11728 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11729 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11730
11731(define_expand "suneq"
11732 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11733 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11734 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11735
11736(define_expand "sunge"
11737 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11738 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11739 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11740
11741(define_expand "sungt"
11742 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11743 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11744 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11745
11746(define_expand "sunle"
11747 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11748 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11749 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11750
11751(define_expand "sunlt"
11752 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11753 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11754 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11755
11756(define_expand "sltgt"
11757 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11758 ""
11759 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11760
3aebbe5f
JJ		 11761(define_expand "stack_protect_set"
11762 [(match_operand 0 "memory_operand" "")
11763 (match_operand 1 "memory_operand" "")]
11764 ""
11765{
77008252
JJ		 11766#ifdef TARGET_THREAD_SSP_OFFSET
11767 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11768 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11769 operands[1] = gen_rtx_MEM (Pmode, addr);
11770#endif
3aebbe5f
JJ		 11771 if (TARGET_64BIT)
11772 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11773 else
11774 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11775 DONE;
11776})
11777
11778(define_insn "stack_protect_setsi"
11779 [(set (match_operand:SI 0 "memory_operand" "=m")
11780 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11781 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11782 "TARGET_32BIT"
11783 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11784 [(set_attr "type" "three")
11785 (set_attr "length" "12")])
11786
11787(define_insn "stack_protect_setdi"
11788 [(set (match_operand:DI 0 "memory_operand" "=m")
11789 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11790 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11791 "TARGET_64BIT"
11792 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11793 [(set_attr "type" "three")
11794 (set_attr "length" "12")])
11795
11796(define_expand "stack_protect_test"
11797 [(match_operand 0 "memory_operand" "")
11798 (match_operand 1 "memory_operand" "")
11799 (match_operand 2 "" "")]
11800 ""
11801{
77008252
JJ		 11802#ifdef TARGET_THREAD_SSP_OFFSET
11803 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11804 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11805 operands[1] = gen_rtx_MEM (Pmode, addr);
11806#endif
3aebbe5f
JJ		 11807 rs6000_compare_op0 = operands[0];
11808 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11809 UNSPEC_SP_TEST);
11810 rs6000_compare_fp_p = 0;
11811 emit_jump_insn (gen_beq (operands[2]));
11812 DONE;
11813})
11814
11815(define_insn "stack_protect_testsi"
11816 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11817 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11818 (match_operand:SI 2 "memory_operand" "m,m")]
11819 UNSPEC_SP_TEST))
41f12ed0
JJ		 11820 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11821 (clobber (match_scratch:SI 3 "=&r,&r"))]
3aebbe5f
JJ		 11822 "TARGET_32BIT"
11823 "@
11824 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11825 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11826 [(set_attr "length" "16,20")])
11827
11828(define_insn "stack_protect_testdi"
11829 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11830 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11831 (match_operand:DI 2 "memory_operand" "m,m")]
11832 UNSPEC_SP_TEST))
41f12ed0
JJ		 11833 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11834 (clobber (match_scratch:DI 3 "=&r,&r"))]
3aebbe5f
JJ		 11835 "TARGET_64BIT"
11836 "@
11837 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11838 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11839 [(set_attr "length" "16,20")])
11840
1fd4e8c1
RK		 11841\f
11842;; Here are the actual compare insns.
4ae234b0 11843(define_insn "*cmp<mode>_internal1"
1fd4e8c1 11844 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
4ae234b0
GK		 11845 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11846 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
1fd4e8c1 11847 ""
4ae234b0 11848 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
b54cf83a 11849 [(set_attr "type" "cmp")])
266eb58a 11850
f357808b 11851;; If we are comparing a register for equality with a large constant,
28d0e143
PB		 11852;; we can do this with an XOR followed by a compare. But this is profitable
11853;; only if the large constant is only used for the comparison (and in this
11854;; case we already have a register to reuse as scratch).
130869aa
PB		 11855;;
11856;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11857;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
f357808b 11858
28d0e143 11859(define_peephole2
130869aa 11860 [(set (match_operand:SI 0 "register_operand")
410c459d 11861 (match_operand:SI 1 "logical_const_operand" ""))
130869aa 11862 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
28d0e143 11863 [(match_dup 0)
410c459d 11864 (match_operand:SI 2 "logical_const_operand" "")]))
28d0e143 11865 (set (match_operand:CC 4 "cc_reg_operand" "")
130869aa 11866 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
28d0e143
PB		 11867 (match_dup 0)))
11868 (set (pc)
11869 (if_then_else (match_operator 6 "equality_operator"
11870 [(match_dup 4) (const_int 0)])
11871 (match_operand 7 "" "")
11872 (match_operand 8 "" "")))]
130869aa
PB		 11873 "peep2_reg_dead_p (3, operands[0])
11874 && peep2_reg_dead_p (4, operands[4])"
11875 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
28d0e143
PB		 11876 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11877 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11878
11879{
11880 /* Get the constant we are comparing against, and see what it looks like
11881 when sign-extended from 16 to 32 bits. Then see what constant we could
11882 XOR with SEXTC to get the sign-extended value. */
11883 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
130869aa 11884 SImode,
28d0e143
PB		 11885 operands[1], operands[2]);
11886 HOST_WIDE_INT c = INTVAL (cnst);
a65c591c 11887 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
5f59ecb7 11888 HOST_WIDE_INT xorv = c ^ sextc;
f357808b 11889
28d0e143
PB		 11890 operands[9] = GEN_INT (xorv);
11891 operands[10] = GEN_INT (sextc);
11892})
f357808b 11893
acad7ed3 11894(define_insn "*cmpsi_internal2"
1fd4e8c1 11895 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
cd2b37d9 11896 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9ebbca7d 11897 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
1fd4e8c1 11898 ""
e2c953b6 11899 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
b54cf83a 11900 [(set_attr "type" "cmp")])
1fd4e8c1 11901
acad7ed3 11902(define_insn "*cmpdi_internal2"
266eb58a
DE		 11903 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11904 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
9ebbca7d 11905 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
266eb58a 11906 ""
e2c953b6 11907 "cmpld%I2 %0,%1,%b2"
b54cf83a 11908 [(set_attr "type" "cmp")])
266eb58a 11909
1fd4e8c1
RK		 11910;; The following two insns don't exist as single insns, but if we provide
11911;; them, we can swap an add and compare, which will enable us to overlap more
11912;; of the required delay between a compare and branch. We generate code for
11913;; them by splitting.
11914
11915(define_insn ""
11916 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
cd2b37d9 11917 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11918 (match_operand:SI 2 "short_cint_operand" "i")))
cd2b37d9 11919 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11920 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11921 ""
baf97f86
RK		 11922 "#"
11923 [(set_attr "length" "8")])
7e69e155 11924
1fd4e8c1
RK		 11925(define_insn ""
11926 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
cd2b37d9 11927 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11928 (match_operand:SI 2 "u_short_cint_operand" "i")))
cd2b37d9 11929 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11930 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11931 ""
baf97f86
RK		 11932 "#"
11933 [(set_attr "length" "8")])
7e69e155 11934
1fd4e8c1
RK		 11935(define_split
11936 [(set (match_operand:CC 3 "cc_reg_operand" "")
cd2b37d9 11937 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11938 (match_operand:SI 2 "short_cint_operand" "")))
cd2b37d9 11939 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11940 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11941 ""
11942 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11943 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11944
11945(define_split
11946 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
cd2b37d9 11947 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11948 (match_operand:SI 2 "u_short_cint_operand" "")))
cd2b37d9 11949 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11950 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11951 ""
11952 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11953 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11954
acad7ed3 11955(define_insn "*cmpsf_internal1"
1fd4e8c1 11956 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11957 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11958 (match_operand:SF 2 "gpc_reg_operand" "f")))]
a3170dc6 11959 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11960 "fcmpu %0,%1,%2"
11961 [(set_attr "type" "fpcompare")])
11962
acad7ed3 11963(define_insn "*cmpdf_internal1"
1fd4e8c1 11964 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11965 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11966 (match_operand:DF 2 "gpc_reg_operand" "f")))]
a3170dc6 11967 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11968 "fcmpu %0,%1,%2"
11969 [(set_attr "type" "fpcompare")])
d6f99ca4
DE		 11970
11971;; Only need to compare second words if first words equal
11972(define_insn "*cmptf_internal1"
11973 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11974 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11975 (match_operand:TF 2 "gpc_reg_operand" "f")))]
602ea4d3 11976 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
39e63627 11977 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 11978 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
d6f99ca4
DE		 11979 [(set_attr "type" "fpcompare")
11980 (set_attr "length" "12")])
de17c25f
DE		 11981
11982(define_insn_and_split "*cmptf_internal2"
11983 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11984 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11985 (match_operand:TF 2 "gpc_reg_operand" "f")))
11986 (clobber (match_scratch:DF 3 "=f"))
11987 (clobber (match_scratch:DF 4 "=f"))
11988 (clobber (match_scratch:DF 5 "=f"))
11989 (clobber (match_scratch:DF 6 "=f"))
11990 (clobber (match_scratch:DF 7 "=f"))
11991 (clobber (match_scratch:DF 8 "=f"))
11992 (clobber (match_scratch:DF 9 "=f"))
11993 (clobber (match_scratch:DF 10 "=f"))]
602ea4d3 11994 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
de17c25f
DE		 11995 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11996 "#"
11997 "&& reload_completed"
11998 [(set (match_dup 3) (match_dup 13))
11999 (set (match_dup 4) (match_dup 14))
12000 (set (match_dup 9) (abs:DF (match_dup 5)))
12001 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12002 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12003 (label_ref (match_dup 11))
12004 (pc)))
12005 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12006 (set (pc) (label_ref (match_dup 12)))
12007 (match_dup 11)
12008 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12009 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12010 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12011 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
12012 (match_dup 12)]
12013{
12014 REAL_VALUE_TYPE rv;
12015 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12016 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12017
12018 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12019 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12020 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12021 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12022 operands[11] = gen_label_rtx ();
12023 operands[12] = gen_label_rtx ();
12024 real_inf (&rv);
12025 operands[13] = force_const_mem (DFmode,
12026 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12027 operands[14] = force_const_mem (DFmode,
12028 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12029 DFmode));
12030 if (TARGET_TOC)
12031 {
12032 operands[13] = gen_const_mem (DFmode,
12033 create_TOC_reference (XEXP (operands[13], 0)));
12034 operands[14] = gen_const_mem (DFmode,
12035 create_TOC_reference (XEXP (operands[14], 0)));
12036 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12037 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12038 }
12039})
1fd4e8c1
RK		 12040\f
12041;; Now we have the scc insns. We can do some combinations because of the
12042;; way the machine works.
12043;;
12044;; Note that this is probably faster if we can put an insn between the
c5defebb
RK		 12045;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12046;; cases the insns below which don't use an intermediate CR field will
12047;; be used instead.
1fd4e8c1 12048(define_insn ""
cd2b37d9 12049 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12050 (match_operator:SI 1 "scc_comparison_operator"
12051 [(match_operand 2 "cc_reg_operand" "y")
12052 (const_int 0)]))]
12053 ""
2c4a9cff
DE		 12054 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12055 [(set (attr "type")
12056 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12057 (const_string "mfcrf")
12058 ]
12059 (const_string "mfcr")))
c1618c0c 12060 (set_attr "length" "8")])
1fd4e8c1 12061
423c1189 12062;; Same as above, but get the GT bit.
64022b5d 12063(define_insn "move_from_CR_gt_bit"
423c1189 12064 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
64022b5d 12065 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
423c1189 12066 "TARGET_E500"
64022b5d 12067 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
423c1189 12068 [(set_attr "type" "mfcr")
c1618c0c 12069 (set_attr "length" "8")])
423c1189 12070
a3170dc6
AH		 12071;; Same as above, but get the OV/ORDERED bit.
12072(define_insn "move_from_CR_ov_bit"
12073 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 12074 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
a3170dc6 12075 "TARGET_ISEL"
b7053a3f 12076 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
b54cf83a 12077 [(set_attr "type" "mfcr")
c1618c0c 12078 (set_attr "length" "8")])
a3170dc6 12079
1fd4e8c1 12080(define_insn ""
9ebbca7d
GK		 12081 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12082 (match_operator:DI 1 "scc_comparison_operator"
12083 [(match_operand 2 "cc_reg_operand" "y")
12084 (const_int 0)]))]
12085 "TARGET_POWERPC64"
2c4a9cff
DE		 12086 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12087 [(set (attr "type")
12088 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12089 (const_string "mfcrf")
12090 ]
12091 (const_string "mfcr")))
c1618c0c 12092 (set_attr "length" "8")])
9ebbca7d
GK		 12093
12094(define_insn ""
12095 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12096 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12097 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1
RK		 12098 (const_int 0)])
12099 (const_int 0)))
9ebbca7d 12100 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 12101 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12102 "TARGET_32BIT"
9ebbca7d 12103 "@
2c4a9cff 12104 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
9ebbca7d 12105 #"
b19003d8 12106 [(set_attr "type" "delayed_compare")
c1618c0c 12107 (set_attr "length" "8,16")])
9ebbca7d
GK		 12108
12109(define_split
12110 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12111 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12112 [(match_operand 2 "cc_reg_operand" "")
12113 (const_int 0)])
12114 (const_int 0)))
12115 (set (match_operand:SI 3 "gpc_reg_operand" "")
12116 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12117 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12118 [(set (match_dup 3)
12119 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12120 (set (match_dup 0)
12121 (compare:CC (match_dup 3)
12122 (const_int 0)))]
12123 "")
1fd4e8c1
RK		 12124
12125(define_insn ""
cd2b37d9 12126 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12127 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12128 [(match_operand 2 "cc_reg_operand" "y")
12129 (const_int 0)])
12130 (match_operand:SI 3 "const_int_operand" "n")))]
12131 ""
12132 "*
12133{
12134 int is_bit = ccr_bit (operands[1], 1);
12135 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12136 int count;
12137
12138 if (is_bit >= put_bit)
12139 count = is_bit - put_bit;
12140 else
12141 count = 32 - (put_bit - is_bit);
12142
89e9f3a8
MM		 12143 operands[4] = GEN_INT (count);
12144 operands[5] = GEN_INT (put_bit);
1fd4e8c1 12145
2c4a9cff 12146 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
b19003d8 12147}"
2c4a9cff
DE		 12148 [(set (attr "type")
12149 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12150 (const_string "mfcrf")
12151 ]
12152 (const_string "mfcr")))
c1618c0c 12153 (set_attr "length" "8")])
1fd4e8c1
RK		 12154
12155(define_insn ""
9ebbca7d 12156 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12157 (compare:CC
12158 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12159 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1 12160 (const_int 0)])
9ebbca7d 12161 (match_operand:SI 3 "const_int_operand" "n,n"))
1fd4e8c1 12162 (const_int 0)))
9ebbca7d 12163 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12164 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12165 (match_dup 3)))]
ce71f754 12166 ""
1fd4e8c1
RK		 12167 "*
12168{
12169 int is_bit = ccr_bit (operands[1], 1);
12170 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12171 int count;
12172
9ebbca7d
GK		 12173 /* Force split for non-cc0 compare. */
12174 if (which_alternative == 1)
12175 return \"#\";
12176
1fd4e8c1
RK		 12177 if (is_bit >= put_bit)
12178 count = is_bit - put_bit;
12179 else
12180 count = 32 - (put_bit - is_bit);
12181
89e9f3a8
MM		 12182 operands[5] = GEN_INT (count);
12183 operands[6] = GEN_INT (put_bit);
1fd4e8c1 12184
2c4a9cff 12185 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
1fd4e8c1 12186}"
b19003d8 12187 [(set_attr "type" "delayed_compare")
c1618c0c 12188 (set_attr "length" "8,16")])
9ebbca7d
GK		 12189
12190(define_split
12191 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12192 (compare:CC
12193 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12194 [(match_operand 2 "cc_reg_operand" "")
12195 (const_int 0)])
12196 (match_operand:SI 3 "const_int_operand" ""))
12197 (const_int 0)))
12198 (set (match_operand:SI 4 "gpc_reg_operand" "")
12199 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12200 (match_dup 3)))]
ce71f754 12201 "reload_completed"
9ebbca7d
GK		 12202 [(set (match_dup 4)
12203 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12204 (match_dup 3)))
12205 (set (match_dup 0)
12206 (compare:CC (match_dup 4)
12207 (const_int 0)))]
12208 "")
1fd4e8c1 12209
c5defebb
RK		 12210;; There is a 3 cycle delay between consecutive mfcr instructions
12211;; so it is useful to combine 2 scc instructions to use only one mfcr.
12212
12213(define_peephole
cd2b37d9 12214 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
c5defebb
RK		 12215 (match_operator:SI 1 "scc_comparison_operator"
12216 [(match_operand 2 "cc_reg_operand" "y")
12217 (const_int 0)]))
cd2b37d9 12218 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
c5defebb
RK		 12219 (match_operator:SI 4 "scc_comparison_operator"
12220 [(match_operand 5 "cc_reg_operand" "y")
12221 (const_int 0)]))]
309323c2 12222 "REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12223 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12224 [(set_attr "type" "mfcr")
c1618c0c 12225 (set_attr "length" "12")])
c5defebb 12226
9ebbca7d
GK		 12227(define_peephole
12228 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12229 (match_operator:DI 1 "scc_comparison_operator"
12230 [(match_operand 2 "cc_reg_operand" "y")
12231 (const_int 0)]))
12232 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12233 (match_operator:DI 4 "scc_comparison_operator"
12234 [(match_operand 5 "cc_reg_operand" "y")
12235 (const_int 0)]))]
309323c2 12236 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12237 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12238 [(set_attr "type" "mfcr")
c1618c0c 12239 (set_attr "length" "12")])
9ebbca7d 12240
1fd4e8c1
RK		 12241;; There are some scc insns that can be done directly, without a compare.
12242;; These are faster because they don't involve the communications between
12243;; the FXU and branch units. In fact, we will be replacing all of the
12244;; integer scc insns here or in the portable methods in emit_store_flag.
12245;;
12246;; Also support (neg (scc ..)) since that construct is used to replace
12247;; branches, (plus (scc ..) ..) since that construct is common and
12248;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12249;; cases where it is no more expensive than (neg (scc ..)).
12250
12251;; Have reload force a constant into a register for the simple insns that
12252;; otherwise won't accept constants. We do this because it is faster than
12253;; the cmp/mfcr sequence we would otherwise generate.
12254
e9441276
DE		 12255(define_mode_attr scc_eq_op2 [(SI "rKLI")
12256 (DI "rKJI")])
a260abc9 12257
e9441276
DE		 12258(define_insn_and_split "*eq<mode>"
12259 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12260 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
d0515b39 12261 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
27f0fe7f 12262 "!TARGET_POWER"
e9441276 12263 "#"
27f0fe7f 12264 "!TARGET_POWER"
d0515b39
DE		 12265 [(set (match_dup 0)
12266 (clz:GPR (match_dup 3)))
70ae0191 12267 (set (match_dup 0)
d0515b39 12268 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
70ae0191 12269 {
e9441276
DE		 12270 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12271 {
d0515b39
DE		 12272 /* Use output operand as intermediate. */
12273 operands[3] = operands[0];
12274
e9441276 12275 if (logical_operand (operands[2], <MODE>mode))
d0515b39 12276 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12277 gen_rtx_XOR (<MODE>mode,
12278 operands[1], operands[2])));
12279 else
d0515b39 12280 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12281 gen_rtx_PLUS (<MODE>mode, operands[1],
12282 negate_rtx (<MODE>mode,
12283 operands[2]))));
12284 }
12285 else
d0515b39 12286 operands[3] = operands[1];
9ebbca7d 12287
d0515b39 12288 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
e9441276 12289 })
a260abc9 12290
e9441276 12291(define_insn_and_split "*eq<mode>_compare"
d0515b39 12292 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
70ae0191 12293 (compare:CC
1fa5c709
DE		 12294 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12295 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
70ae0191 12296 (const_int 0)))
1fa5c709 12297 (set (match_operand:P 0 "gpc_reg_operand" "=r")
d0515b39 12298 (eq:P (match_dup 1) (match_dup 2)))]
27f0fe7f 12299 "!TARGET_POWER && optimize_size"
e9441276 12300 "#"
27f0fe7f 12301 "!TARGET_POWER && optimize_size"
d0515b39 12302 [(set (match_dup 0)
1fa5c709 12303 (clz:P (match_dup 4)))
d0515b39
DE		 12304 (parallel [(set (match_dup 3)
12305 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
70ae0191
DE		 12306 (const_int 0)))
12307 (set (match_dup 0)
d0515b39 12308 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
70ae0191 12309 {
e9441276
DE		 12310 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12311 {
d0515b39
DE		 12312 /* Use output operand as intermediate. */
12313 operands[4] = operands[0];
12314
e9441276
DE		 12315 if (logical_operand (operands[2], <MODE>mode))
12316 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12317 gen_rtx_XOR (<MODE>mode,
12318 operands[1], operands[2])));
12319 else
12320 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12321 gen_rtx_PLUS (<MODE>mode, operands[1],
12322 negate_rtx (<MODE>mode,
12323 operands[2]))));
12324 }
12325 else
12326 operands[4] = operands[1];
12327
d0515b39 12328 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
70ae0191
DE		 12329 })
12330
05f68097
DE		 12331(define_insn "*eqsi_power"
12332 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12333 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12334 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12335 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12336 "TARGET_POWER"
12337 "@
12338 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12339 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12340 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12341 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12342 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12343 [(set_attr "type" "three,two,three,three,three")
12344 (set_attr "length" "12,8,12,12,12")])
12345
b19003d8
RK		 12346;; We have insns of the form shown by the first define_insn below. If
12347;; there is something inside the comparison operation, we must split it.
12348(define_split
12349 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12350 (plus:SI (match_operator 1 "comparison_operator"
12351 [(match_operand:SI 2 "" "")
12352 (match_operand:SI 3
12353 "reg_or_cint_operand" "")])
12354 (match_operand:SI 4 "gpc_reg_operand" "")))
12355 (clobber (match_operand:SI 5 "register_operand" ""))]
12356 "! gpc_reg_operand (operands[2], SImode)"
12357 [(set (match_dup 5) (match_dup 2))
12358 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12359 (match_dup 4)))])
1fd4e8c1 12360
297abd0d 12361(define_insn "*plus_eqsi"
5276df18 12362 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
cd2b37d9 12363 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
56fc483e 12364 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
5276df18 12365 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
59d6560b 12366 "TARGET_32BIT"
1fd4e8c1 12367 "@
5276df18
DE		 12368 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12369 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12370 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12371 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12372 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
943c15ed
DE		 12373 [(set_attr "type" "three,two,three,three,three")
12374 (set_attr "length" "12,8,12,12,12")])
1fd4e8c1 12375
297abd0d 12376(define_insn "*compare_plus_eqsi"
9ebbca7d 12377 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12378 (compare:CC
1fd4e8c1 12379 (plus:SI
9ebbca7d 12380 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12381 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12382 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12383 (const_int 0)))
9ebbca7d 12384 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
297abd0d 12385 "TARGET_32BIT && optimize_size"
1fd4e8c1 12386 "@
ca7f5001 12387 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
19378cf8 12388 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
ca7f5001
RK		 12389 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12390 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12391 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12392 #
12393 #
12394 #
12395 #
12396 #"
b19003d8 12397 [(set_attr "type" "compare")
9ebbca7d
GK		 12398 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12399
12400(define_split
12401 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12402 (compare:CC
12403 (plus:SI
12404 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12405 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12406 (match_operand:SI 3 "gpc_reg_operand" ""))
12407 (const_int 0)))
12408 (clobber (match_scratch:SI 4 ""))]
297abd0d 12409 "TARGET_32BIT && optimize_size && reload_completed"
9ebbca7d
GK		 12410 [(set (match_dup 4)
12411 (plus:SI (eq:SI (match_dup 1)
12412 (match_dup 2))
12413 (match_dup 3)))
12414 (set (match_dup 0)
12415 (compare:CC (match_dup 4)
12416 (const_int 0)))]
12417 "")
1fd4e8c1 12418
297abd0d 12419(define_insn "*plus_eqsi_compare"
0387639b 12420 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12421 (compare:CC
1fd4e8c1 12422 (plus:SI
9ebbca7d 12423 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12424 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12425 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12426 (const_int 0)))
0387639b
DE		 12427 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12428 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12429 "TARGET_32BIT && optimize_size"
1fd4e8c1 12430 "@
0387639b
DE		 12431 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12432 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12433 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12434 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12435 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12436 #
12437 #
12438 #
12439 #
12440 #"
12441 [(set_attr "type" "compare")
12442 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12443
12444(define_split
0387639b 12445 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12446 (compare:CC
12447 (plus:SI
12448 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12449 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12450 (match_operand:SI 3 "gpc_reg_operand" ""))
12451 (const_int 0)))
12452 (set (match_operand:SI 0 "gpc_reg_operand" "")
0387639b 12453 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12454 "TARGET_32BIT && optimize_size && reload_completed"
0387639b 12455 [(set (match_dup 0)
9ebbca7d 12456 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
0387639b 12457 (set (match_dup 4)
9ebbca7d
GK		 12458 (compare:CC (match_dup 0)
12459 (const_int 0)))]
12460 "")
12461
d0515b39
DE		 12462(define_insn "*neg_eq0<mode>"
12463 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12464 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12465 (const_int 0))))]
59d6560b 12466 ""
d0515b39
DE		 12467 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12468 [(set_attr "type" "two")
12469 (set_attr "length" "8")])
12470
12471(define_insn_and_split "*neg_eq<mode>"
12472 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12473 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12474 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
59d6560b 12475 ""
d0515b39 12476 "#"
59d6560b 12477 ""
d0515b39
DE		 12478 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12479 {
12480 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12481 {
12482 /* Use output operand as intermediate. */
12483 operands[3] = operands[0];
12484
12485 if (logical_operand (operands[2], <MODE>mode))
12486 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12487 gen_rtx_XOR (<MODE>mode,
12488 operands[1], operands[2])));
12489 else
12490 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12491 gen_rtx_PLUS (<MODE>mode, operands[1],
12492 negate_rtx (<MODE>mode,
12493 operands[2]))));
12494 }
12495 else
12496 operands[3] = operands[1];
12497 })
1fd4e8c1 12498
ea9be077
MM		 12499;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12500;; since it nabs/sr is just as fast.
ce45ef46 12501(define_insn "*ne0si"
b4e95693 12502 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
ea9be077
MM		 12503 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12504 (const_int 31)))
12505 (clobber (match_scratch:SI 2 "=&r"))]
683bdff7 12506 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
ea9be077 12507 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
943c15ed
DE		 12508 [(set_attr "type" "two")
12509 (set_attr "length" "8")])
ea9be077 12510
ce45ef46 12511(define_insn "*ne0di"
a260abc9
DE		 12512 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12513 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12514 (const_int 63)))
12515 (clobber (match_scratch:DI 2 "=&r"))]
683bdff7 12516 "TARGET_64BIT"
a260abc9 12517 "addic %2,%1,-1\;subfe %0,%2,%1"
943c15ed
DE		 12518 [(set_attr "type" "two")
12519 (set_attr "length" "8")])
a260abc9 12520
1fd4e8c1 12521;; This is what (plus (ne X (const_int 0)) Y) looks like.
297abd0d 12522(define_insn "*plus_ne0si"
cd2b37d9 12523 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 12524 (plus:SI (lshiftrt:SI
cd2b37d9 12525 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1fd4e8c1 12526 (const_int 31))
cd2b37d9 12527 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1 12528 (clobber (match_scratch:SI 3 "=&r"))]
683bdff7 12529 "TARGET_32BIT"
ca7f5001 12530 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
943c15ed
DE		 12531 [(set_attr "type" "two")
12532 (set_attr "length" "8")])
1fd4e8c1 12533
297abd0d 12534(define_insn "*plus_ne0di"
a260abc9
DE		 12535 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12536 (plus:DI (lshiftrt:DI
12537 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12538 (const_int 63))
12539 (match_operand:DI 2 "gpc_reg_operand" "r")))
12540 (clobber (match_scratch:DI 3 "=&r"))]
683bdff7 12541 "TARGET_64BIT"
a260abc9 12542 "addic %3,%1,-1\;addze %0,%2"
943c15ed
DE		 12543 [(set_attr "type" "two")
12544 (set_attr "length" "8")])
a260abc9 12545
297abd0d 12546(define_insn "*compare_plus_ne0si"
9ebbca7d 12547 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12548 (compare:CC
12549 (plus:SI (lshiftrt:SI
9ebbca7d 12550 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12551 (const_int 31))
9ebbca7d 12552 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12553 (const_int 0)))
889b90a1
GK		 12554 (clobber (match_scratch:SI 3 "=&r,&r"))
12555 (clobber (match_scratch:SI 4 "=X,&r"))]
683bdff7 12556 "TARGET_32BIT"
9ebbca7d
GK		 12557 "@
12558 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12559 #"
b19003d8 12560 [(set_attr "type" "compare")
9ebbca7d
GK		 12561 (set_attr "length" "8,12")])
12562
12563(define_split
12564 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12565 (compare:CC
12566 (plus:SI (lshiftrt:SI
12567 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12568 (const_int 31))
12569 (match_operand:SI 2 "gpc_reg_operand" ""))
12570 (const_int 0)))
889b90a1
GK		 12571 (clobber (match_scratch:SI 3 ""))
12572 (clobber (match_scratch:SI 4 ""))]
683bdff7 12573 "TARGET_32BIT && reload_completed"
889b90a1 12574 [(parallel [(set (match_dup 3)
ce71f754
AM		 12575 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12576 (const_int 31))
12577 (match_dup 2)))
889b90a1 12578 (clobber (match_dup 4))])
9ebbca7d
GK		 12579 (set (match_dup 0)
12580 (compare:CC (match_dup 3)
12581 (const_int 0)))]
12582 "")
1fd4e8c1 12583
297abd0d 12584(define_insn "*compare_plus_ne0di"
9ebbca7d 12585 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12586 (compare:CC
12587 (plus:DI (lshiftrt:DI
9ebbca7d 12588 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12589 (const_int 63))
9ebbca7d 12590 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12591 (const_int 0)))
9ebbca7d 12592 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12593 "TARGET_64BIT"
9ebbca7d
GK		 12594 "@
12595 addic %3,%1,-1\;addze. %3,%2
12596 #"
a260abc9 12597 [(set_attr "type" "compare")
9ebbca7d
GK		 12598 (set_attr "length" "8,12")])
12599
12600(define_split
12601 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12602 (compare:CC
12603 (plus:DI (lshiftrt:DI
12604 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12605 (const_int 63))
12606 (match_operand:DI 2 "gpc_reg_operand" ""))
12607 (const_int 0)))
12608 (clobber (match_scratch:DI 3 ""))]
683bdff7 12609 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12610 [(set (match_dup 3)
12611 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12612 (const_int 63))
12613 (match_dup 2)))
12614 (set (match_dup 0)
12615 (compare:CC (match_dup 3)
12616 (const_int 0)))]
12617 "")
a260abc9 12618
297abd0d 12619(define_insn "*plus_ne0si_compare"
9ebbca7d 12620 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12621 (compare:CC
12622 (plus:SI (lshiftrt:SI
9ebbca7d 12623 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12624 (const_int 31))
9ebbca7d 12625 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12626 (const_int 0)))
9ebbca7d 12627 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12628 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12629 (match_dup 2)))
9ebbca7d 12630 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 12631 "TARGET_32BIT"
9ebbca7d
GK		 12632 "@
12633 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12634 #"
b19003d8 12635 [(set_attr "type" "compare")
9ebbca7d
GK		 12636 (set_attr "length" "8,12")])
12637
12638(define_split
12639 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12640 (compare:CC
12641 (plus:SI (lshiftrt:SI
12642 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12643 (const_int 31))
12644 (match_operand:SI 2 "gpc_reg_operand" ""))
12645 (const_int 0)))
12646 (set (match_operand:SI 0 "gpc_reg_operand" "")
12647 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12648 (match_dup 2)))
12649 (clobber (match_scratch:SI 3 ""))]
683bdff7 12650 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12651 [(parallel [(set (match_dup 0)
12652 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12653 (match_dup 2)))
12654 (clobber (match_dup 3))])
12655 (set (match_dup 4)
12656 (compare:CC (match_dup 0)
12657 (const_int 0)))]
12658 "")
1fd4e8c1 12659
297abd0d 12660(define_insn "*plus_ne0di_compare"
9ebbca7d 12661 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12662 (compare:CC
12663 (plus:DI (lshiftrt:DI
9ebbca7d 12664 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12665 (const_int 63))
9ebbca7d 12666 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12667 (const_int 0)))
9ebbca7d 12668 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 12669 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12670 (match_dup 2)))
9ebbca7d 12671 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12672 "TARGET_64BIT"
9ebbca7d
GK		 12673 "@
12674 addic %3,%1,-1\;addze. %0,%2
12675 #"
a260abc9 12676 [(set_attr "type" "compare")
9ebbca7d
GK		 12677 (set_attr "length" "8,12")])
12678
12679(define_split
12680 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12681 (compare:CC
12682 (plus:DI (lshiftrt:DI
12683 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12684 (const_int 63))
12685 (match_operand:DI 2 "gpc_reg_operand" ""))
12686 (const_int 0)))
12687 (set (match_operand:DI 0 "gpc_reg_operand" "")
12688 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12689 (match_dup 2)))
12690 (clobber (match_scratch:DI 3 ""))]
683bdff7 12691 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12692 [(parallel [(set (match_dup 0)
12693 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12694 (match_dup 2)))
12695 (clobber (match_dup 3))])
12696 (set (match_dup 4)
12697 (compare:CC (match_dup 0)
12698 (const_int 0)))]
12699 "")
a260abc9 12700
1fd4e8c1 12701(define_insn ""
cd2b37d9
RK		 12702 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12703 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 12704 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12705 (clobber (match_scratch:SI 3 "=r,X"))]
ca7f5001 12706 "TARGET_POWER"
1fd4e8c1 12707 "@
ca7f5001 12708 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
7f340546 12709 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12710 [(set_attr "length" "12")])
1fd4e8c1
RK		 12711
12712(define_insn ""
9ebbca7d 12713 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12714 (compare:CC
9ebbca7d
GK		 12715 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12716 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
1fd4e8c1 12717 (const_int 0)))
9ebbca7d 12718 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 12719 (le:SI (match_dup 1) (match_dup 2)))
9ebbca7d 12720 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
ca7f5001 12721 "TARGET_POWER"
1fd4e8c1 12722 "@
ca7f5001 12723 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
9ebbca7d
GK		 12724 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12725 #
12726 #"
12727 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12728 (set_attr "length" "12,12,16,16")])
12729
12730(define_split
12731 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12732 (compare:CC
12733 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12734 (match_operand:SI 2 "reg_or_short_operand" ""))
12735 (const_int 0)))
12736 (set (match_operand:SI 0 "gpc_reg_operand" "")
12737 (le:SI (match_dup 1) (match_dup 2)))
12738 (clobber (match_scratch:SI 3 ""))]
12739 "TARGET_POWER && reload_completed"
12740 [(parallel [(set (match_dup 0)
12741 (le:SI (match_dup 1) (match_dup 2)))
12742 (clobber (match_dup 3))])
12743 (set (match_dup 4)
12744 (compare:CC (match_dup 0)
12745 (const_int 0)))]
12746 "")
1fd4e8c1
RK		 12747
12748(define_insn ""
097657c3 12749 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
cd2b37d9 12750 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12751 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
097657c3 12752 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
ca7f5001 12753 "TARGET_POWER"
1fd4e8c1 12754 "@
097657c3
AM		 12755 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12756 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
b19003d8 12757 [(set_attr "length" "12")])
1fd4e8c1
RK		 12758
12759(define_insn ""
9ebbca7d 12760 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12761 (compare:CC
9ebbca7d
GK		 12762 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12763 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12764 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12765 (const_int 0)))
9ebbca7d 12766 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
ca7f5001 12767 "TARGET_POWER"
1fd4e8c1 12768 "@
ca7f5001 12769 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12770 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12771 #
12772 #"
b19003d8 12773 [(set_attr "type" "compare")
9ebbca7d
GK		 12774 (set_attr "length" "12,12,16,16")])
12775
12776(define_split
12777 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12778 (compare:CC
12779 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12780 (match_operand:SI 2 "reg_or_short_operand" ""))
12781 (match_operand:SI 3 "gpc_reg_operand" ""))
12782 (const_int 0)))
12783 (clobber (match_scratch:SI 4 ""))]
12784 "TARGET_POWER && reload_completed"
12785 [(set (match_dup 4)
12786 (plus:SI (le:SI (match_dup 1) (match_dup 2))
097657c3 12787 (match_dup 3)))
9ebbca7d
GK		 12788 (set (match_dup 0)
12789 (compare:CC (match_dup 4)
12790 (const_int 0)))]
12791 "")
1fd4e8c1
RK		 12792
12793(define_insn ""
097657c3 12794 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12795 (compare:CC
9ebbca7d
GK		 12796 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12797 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12798 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12799 (const_int 0)))
097657c3
AM		 12800 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12801 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12802 "TARGET_POWER"
1fd4e8c1 12803 "@
097657c3
AM		 12804 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12805 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12806 #
12807 #"
b19003d8 12808 [(set_attr "type" "compare")
9ebbca7d
GK		 12809 (set_attr "length" "12,12,16,16")])
12810
12811(define_split
097657c3 12812 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12813 (compare:CC
12814 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12815 (match_operand:SI 2 "reg_or_short_operand" ""))
12816 (match_operand:SI 3 "gpc_reg_operand" ""))
12817 (const_int 0)))
12818 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12819 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12820 "TARGET_POWER && reload_completed"
097657c3 12821 [(set (match_dup 0)
9ebbca7d 12822 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12823 (set (match_dup 4)
9ebbca7d
GK		 12824 (compare:CC (match_dup 0)
12825 (const_int 0)))]
12826 "")
1fd4e8c1
RK		 12827
12828(define_insn ""
cd2b37d9
RK		 12829 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12830 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12831 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
ca7f5001 12832 "TARGET_POWER"
1fd4e8c1 12833 "@
ca7f5001
RK		 12834 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12835 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 12836 [(set_attr "length" "12")])
1fd4e8c1 12837
a2dba291
DE		 12838(define_insn "*leu<mode>"
12839 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12840 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12841 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12842 ""
ca7f5001 12843 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 12844 [(set_attr "type" "three")
12845 (set_attr "length" "12")])
1fd4e8c1 12846
a2dba291 12847(define_insn "*leu<mode>_compare"
9ebbca7d 12848 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 12849 (compare:CC
a2dba291
DE		 12850 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12851 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12852 (const_int 0)))
a2dba291
DE		 12853 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12854 (leu:P (match_dup 1) (match_dup 2)))]
12855 ""
9ebbca7d
GK		 12856 "@
12857 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12858 #"
b19003d8 12859 [(set_attr "type" "compare")
9ebbca7d
GK		 12860 (set_attr "length" "12,16")])
12861
12862(define_split
12863 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12864 (compare:CC
a2dba291
DE		 12865 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12866 (match_operand:P 2 "reg_or_short_operand" ""))
9ebbca7d 12867 (const_int 0)))
a2dba291
DE		 12868 (set (match_operand:P 0 "gpc_reg_operand" "")
12869 (leu:P (match_dup 1) (match_dup 2)))]
12870 "reload_completed"
9ebbca7d 12871 [(set (match_dup 0)
a2dba291 12872 (leu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 12873 (set (match_dup 3)
12874 (compare:CC (match_dup 0)
12875 (const_int 0)))]
12876 "")
1fd4e8c1 12877
a2dba291
DE		 12878(define_insn "*plus_leu<mode>"
12879 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12880 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12881 (match_operand:P 2 "reg_or_short_operand" "rI"))
12882 (match_operand:P 3 "gpc_reg_operand" "r")))]
12883 ""
80103f96 12884 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
943c15ed
DE		 12885 [(set_attr "type" "two")
12886 (set_attr "length" "8")])
1fd4e8c1
RK		 12887
12888(define_insn ""
9ebbca7d 12889 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12890 (compare:CC
9ebbca7d
GK		 12891 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12892 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12893 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12894 (const_int 0)))
9ebbca7d 12895 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12896 "TARGET_32BIT"
9ebbca7d
GK		 12897 "@
12898 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12899 #"
b19003d8 12900 [(set_attr "type" "compare")
9ebbca7d
GK		 12901 (set_attr "length" "8,12")])
12902
12903(define_split
12904 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12905 (compare:CC
12906 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12907 (match_operand:SI 2 "reg_or_short_operand" ""))
12908 (match_operand:SI 3 "gpc_reg_operand" ""))
12909 (const_int 0)))
12910 (clobber (match_scratch:SI 4 ""))]
683bdff7 12911 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12912 [(set (match_dup 4)
12913 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12914 (match_dup 3)))
12915 (set (match_dup 0)
12916 (compare:CC (match_dup 4)
12917 (const_int 0)))]
12918 "")
1fd4e8c1
RK		 12919
12920(define_insn ""
097657c3 12921 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12922 (compare:CC
9ebbca7d
GK		 12923 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12924 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12925 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12926 (const_int 0)))
097657c3
AM		 12927 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12928 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12929 "TARGET_32BIT"
9ebbca7d 12930 "@
097657c3 12931 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
9ebbca7d 12932 #"
b19003d8 12933 [(set_attr "type" "compare")
9ebbca7d
GK		 12934 (set_attr "length" "8,12")])
12935
12936(define_split
097657c3 12937 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12938 (compare:CC
12939 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12940 (match_operand:SI 2 "reg_or_short_operand" ""))
12941 (match_operand:SI 3 "gpc_reg_operand" ""))
12942 (const_int 0)))
12943 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12944 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12945 "TARGET_32BIT && reload_completed"
097657c3 12946 [(set (match_dup 0)
9ebbca7d 12947 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12948 (set (match_dup 4)
9ebbca7d
GK		 12949 (compare:CC (match_dup 0)
12950 (const_int 0)))]
12951 "")
1fd4e8c1 12952
a2dba291
DE		 12953(define_insn "*neg_leu<mode>"
12954 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12955 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12956 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12957 ""
ca7f5001 12958 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
943c15ed
DE		 12959 [(set_attr "type" "three")
12960 (set_attr "length" "12")])
1fd4e8c1 12961
a2dba291
DE		 12962(define_insn "*and_neg_leu<mode>"
12963 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12964 (and:P (neg:P
12965 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12966 (match_operand:P 2 "reg_or_short_operand" "rI")))
12967 (match_operand:P 3 "gpc_reg_operand" "r")))]
12968 ""
097657c3 12969 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 12970 [(set_attr "type" "three")
12971 (set_attr "length" "12")])
1fd4e8c1
RK		 12972
12973(define_insn ""
9ebbca7d 12974 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12975 (compare:CC
12976 (and:SI (neg:SI
9ebbca7d
GK		 12977 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12978 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12979 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12980 (const_int 0)))
9ebbca7d 12981 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12982 "TARGET_32BIT"
9ebbca7d
GK		 12983 "@
12984 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12985 #"
12986 [(set_attr "type" "compare")
12987 (set_attr "length" "12,16")])
12988
12989(define_split
12990 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12991 (compare:CC
12992 (and:SI (neg:SI
12993 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12994 (match_operand:SI 2 "reg_or_short_operand" "")))
12995 (match_operand:SI 3 "gpc_reg_operand" ""))
12996 (const_int 0)))
12997 (clobber (match_scratch:SI 4 ""))]
683bdff7 12998 "TARGET_32BIT && reload_completed"
9ebbca7d 12999 [(set (match_dup 4)
097657c3
AM		 13000 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13001 (match_dup 3)))
9ebbca7d
GK		 13002 (set (match_dup 0)
13003 (compare:CC (match_dup 4)
13004 (const_int 0)))]
13005 "")
1fd4e8c1
RK		 13006
13007(define_insn ""
097657c3 13008 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 13009 (compare:CC
13010 (and:SI (neg:SI
9ebbca7d
GK		 13011 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13012 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13013 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13014 (const_int 0)))
097657c3
AM		 13015 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13016 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13017 "TARGET_32BIT"
9ebbca7d 13018 "@
097657c3 13019 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d 13020 #"
b19003d8 13021 [(set_attr "type" "compare")
9ebbca7d
GK		 13022 (set_attr "length" "12,16")])
13023
13024(define_split
097657c3 13025 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13026 (compare:CC
13027 (and:SI (neg:SI
13028 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13029 (match_operand:SI 2 "reg_or_short_operand" "")))
13030 (match_operand:SI 3 "gpc_reg_operand" ""))
13031 (const_int 0)))
13032 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13033 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13034 "TARGET_32BIT && reload_completed"
097657c3
AM		 13035 [(set (match_dup 0)
13036 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13037 (match_dup 3)))
13038 (set (match_dup 4)
9ebbca7d
GK		 13039 (compare:CC (match_dup 0)
13040 (const_int 0)))]
13041 "")
1fd4e8c1
RK		 13042
13043(define_insn ""
cd2b37d9
RK		 13044 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13045 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13046 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
ca7f5001 13047 "TARGET_POWER"
7f340546 13048 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13049 [(set_attr "length" "12")])
1fd4e8c1
RK		 13050
13051(define_insn ""
9ebbca7d 13052 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13053 (compare:CC
9ebbca7d
GK		 13054 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13055 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13056 (const_int 0)))
9ebbca7d 13057 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13058 (lt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13059 "TARGET_POWER"
9ebbca7d
GK		 13060 "@
13061 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13062 #"
29ae5b89 13063 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13064 (set_attr "length" "12,16")])
13065
13066(define_split
13067 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13068 (compare:CC
13069 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13070 (match_operand:SI 2 "reg_or_short_operand" ""))
13071 (const_int 0)))
13072 (set (match_operand:SI 0 "gpc_reg_operand" "")
13073 (lt:SI (match_dup 1) (match_dup 2)))]
13074 "TARGET_POWER && reload_completed"
13075 [(set (match_dup 0)
13076 (lt:SI (match_dup 1) (match_dup 2)))
13077 (set (match_dup 3)
13078 (compare:CC (match_dup 0)
13079 (const_int 0)))]
13080 "")
1fd4e8c1
RK		 13081
13082(define_insn ""
097657c3 13083 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13084 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13085 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13086 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13087 "TARGET_POWER"
097657c3 13088 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13089 [(set_attr "length" "12")])
1fd4e8c1
RK		 13090
13091(define_insn ""
9ebbca7d 13092 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13093 (compare:CC
9ebbca7d
GK		 13094 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13095 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13096 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13097 (const_int 0)))
9ebbca7d 13098 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13099 "TARGET_POWER"
9ebbca7d
GK		 13100 "@
13101 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13102 #"
b19003d8 13103 [(set_attr "type" "compare")
9ebbca7d
GK		 13104 (set_attr "length" "12,16")])
13105
13106(define_split
13107 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13108 (compare:CC
13109 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13110 (match_operand:SI 2 "reg_or_short_operand" ""))
13111 (match_operand:SI 3 "gpc_reg_operand" ""))
13112 (const_int 0)))
13113 (clobber (match_scratch:SI 4 ""))]
13114 "TARGET_POWER && reload_completed"
13115 [(set (match_dup 4)
13116 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
097657c3 13117 (match_dup 3)))
9ebbca7d
GK		 13118 (set (match_dup 0)
13119 (compare:CC (match_dup 4)
13120 (const_int 0)))]
13121 "")
1fd4e8c1
RK		 13122
13123(define_insn ""
097657c3 13124 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13125 (compare:CC
9ebbca7d
GK		 13126 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13127 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13128 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13129 (const_int 0)))
097657c3
AM		 13130 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13131 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13132 "TARGET_POWER"
9ebbca7d 13133 "@
097657c3 13134 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13135 #"
b19003d8 13136 [(set_attr "type" "compare")
9ebbca7d
GK		 13137 (set_attr "length" "12,16")])
13138
13139(define_split
097657c3 13140 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13141 (compare:CC
13142 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13143 (match_operand:SI 2 "reg_or_short_operand" ""))
13144 (match_operand:SI 3 "gpc_reg_operand" ""))
13145 (const_int 0)))
13146 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13147 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13148 "TARGET_POWER && reload_completed"
097657c3 13149 [(set (match_dup 0)
9ebbca7d 13150 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13151 (set (match_dup 4)
9ebbca7d
GK		 13152 (compare:CC (match_dup 0)
13153 (const_int 0)))]
13154 "")
1fd4e8c1
RK		 13155
13156(define_insn ""
cd2b37d9
RK		 13157 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13158 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13159 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13160 "TARGET_POWER"
13161 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13162 [(set_attr "length" "12")])
1fd4e8c1 13163
ce45ef46
DE		 13164(define_insn_and_split "*ltu<mode>"
13165 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13166 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13167 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13168 ""
c0600ecd 13169 "#"
ce45ef46
DE		 13170 ""
13171 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13172 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 13173 "")
1fd4e8c1 13174
1e24ce83 13175(define_insn_and_split "*ltu<mode>_compare"
9ebbca7d 13176 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13177 (compare:CC
a2dba291
DE		 13178 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13179 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13180 (const_int 0)))
a2dba291
DE		 13181 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13182 (ltu:P (match_dup 1) (match_dup 2)))]
13183 ""
1e24ce83
DE		 13184 "#"
13185 ""
13186 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13187 (parallel [(set (match_dup 3)
13188 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13189 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 13190 "")
1fd4e8c1 13191
a2dba291
DE		 13192(define_insn_and_split "*plus_ltu<mode>"
13193 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13194 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13195 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
1e24ce83 13196 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
a2dba291 13197 ""
c0600ecd 13198 "#"
04fa46cf 13199 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 13200 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13201 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 13202 "")
1fd4e8c1 13203
1e24ce83 13204(define_insn_and_split "*plus_ltu<mode>_compare"
097657c3 13205 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13206 (compare:CC
1e24ce83
DE		 13207 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13208 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13209 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13210 (const_int 0)))
1e24ce83
DE		 13211 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13212 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13213 ""
13214 "#"
13215 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13216 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13217 (parallel [(set (match_dup 4)
13218 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13219 (const_int 0)))
13220 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 13221 "")
1fd4e8c1 13222
ce45ef46
DE		 13223(define_insn "*neg_ltu<mode>"
13224 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13225 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13226 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13227 ""
c0600ecd
DE		 13228 "@
13229 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13230 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
943c15ed 13231 [(set_attr "type" "two")
c0600ecd 13232 (set_attr "length" "8")])
1fd4e8c1
RK		 13233
13234(define_insn ""
cd2b37d9
RK		 13235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13236 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 13237 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13238 (clobber (match_scratch:SI 3 "=r"))]
ca7f5001
RK		 13239 "TARGET_POWER"
13240 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
b19003d8 13241 [(set_attr "length" "12")])
1fd4e8c1 13242
9ebbca7d
GK		 13243(define_insn ""
13244 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13245 (compare:CC
9ebbca7d
GK		 13246 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13247 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13248 (const_int 0)))
9ebbca7d 13249 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13250 (ge:SI (match_dup 1) (match_dup 2)))
9ebbca7d 13251 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 13252 "TARGET_POWER"
9ebbca7d
GK		 13253 "@
13254 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13255 #"
13256 [(set_attr "type" "compare")
13257 (set_attr "length" "12,16")])
13258
13259(define_split
13260 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13261 (compare:CC
13262 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13263 (match_operand:SI 2 "reg_or_short_operand" ""))
13264 (const_int 0)))
13265 (set (match_operand:SI 0 "gpc_reg_operand" "")
13266 (ge:SI (match_dup 1) (match_dup 2)))
13267 (clobber (match_scratch:SI 3 ""))]
13268 "TARGET_POWER && reload_completed"
13269 [(parallel [(set (match_dup 0)
097657c3
AM		 13270 (ge:SI (match_dup 1) (match_dup 2)))
13271 (clobber (match_dup 3))])
9ebbca7d
GK		 13272 (set (match_dup 4)
13273 (compare:CC (match_dup 0)
13274 (const_int 0)))]
13275 "")
13276
1fd4e8c1 13277(define_insn ""
097657c3 13278 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13279 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13280 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13281 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13282 "TARGET_POWER"
097657c3 13283 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
b19003d8 13284 [(set_attr "length" "12")])
1fd4e8c1
RK		 13285
13286(define_insn ""
9ebbca7d 13287 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13288 (compare:CC
9ebbca7d
GK		 13289 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13290 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13291 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13292 (const_int 0)))
9ebbca7d 13293 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13294 "TARGET_POWER"
9ebbca7d
GK		 13295 "@
13296 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13297 #"
b19003d8 13298 [(set_attr "type" "compare")
9ebbca7d
GK		 13299 (set_attr "length" "12,16")])
13300
13301(define_split
13302 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13303 (compare:CC
13304 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13305 (match_operand:SI 2 "reg_or_short_operand" ""))
13306 (match_operand:SI 3 "gpc_reg_operand" ""))
13307 (const_int 0)))
13308 (clobber (match_scratch:SI 4 ""))]
13309 "TARGET_POWER && reload_completed"
13310 [(set (match_dup 4)
13311 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
097657c3 13312 (match_dup 3)))
9ebbca7d
GK		 13313 (set (match_dup 0)
13314 (compare:CC (match_dup 4)
13315 (const_int 0)))]
13316 "")
1fd4e8c1
RK		 13317
13318(define_insn ""
097657c3 13319 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13320 (compare:CC
9ebbca7d
GK		 13321 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13322 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13323 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13324 (const_int 0)))
097657c3
AM		 13325 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13326 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13327 "TARGET_POWER"
9ebbca7d 13328 "@
097657c3 13329 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d 13330 #"
b19003d8 13331 [(set_attr "type" "compare")
9ebbca7d
GK		 13332 (set_attr "length" "12,16")])
13333
13334(define_split
097657c3 13335 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13336 (compare:CC
13337 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13338 (match_operand:SI 2 "reg_or_short_operand" ""))
13339 (match_operand:SI 3 "gpc_reg_operand" ""))
13340 (const_int 0)))
13341 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13342 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13343 "TARGET_POWER && reload_completed"
097657c3 13344 [(set (match_dup 0)
9ebbca7d 13345 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13346 (set (match_dup 4)
9ebbca7d
GK		 13347 (compare:CC (match_dup 0)
13348 (const_int 0)))]
13349 "")
1fd4e8c1
RK		 13350
13351(define_insn ""
cd2b37d9
RK		 13352 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13353 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13354 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13355 "TARGET_POWER"
13356 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 13357 [(set_attr "length" "12")])
1fd4e8c1 13358
a2dba291
DE		 13359(define_insn "*geu<mode>"
13360 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13361 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13362 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13363 ""
1fd4e8c1 13364 "@
ca7f5001
RK		 13365 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13366 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 13367 [(set_attr "type" "three")
13368 (set_attr "length" "12")])
1fd4e8c1 13369
a2dba291 13370(define_insn "*geu<mode>_compare"
9ebbca7d 13371 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13372 (compare:CC
a2dba291
DE		 13373 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13374 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13375 (const_int 0)))
a2dba291
DE		 13376 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13377 (geu:P (match_dup 1) (match_dup 2)))]
13378 ""
1fd4e8c1 13379 "@
ca7f5001 13380 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
9ebbca7d
GK		 13381 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13382 #
13383 #"
b19003d8 13384 [(set_attr "type" "compare")
9ebbca7d
GK		 13385 (set_attr "length" "12,12,16,16")])
13386
13387(define_split
13388 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13389 (compare:CC
a2dba291
DE		 13390 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13391 (match_operand:P 2 "reg_or_neg_short_operand" ""))
9ebbca7d 13392 (const_int 0)))
a2dba291
DE		 13393 (set (match_operand:P 0 "gpc_reg_operand" "")
13394 (geu:P (match_dup 1) (match_dup 2)))]
13395 "reload_completed"
9ebbca7d 13396 [(set (match_dup 0)
a2dba291 13397 (geu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 13398 (set (match_dup 3)
13399 (compare:CC (match_dup 0)
13400 (const_int 0)))]
13401 "")
f9562f27 13402
a2dba291
DE		 13403(define_insn "*plus_geu<mode>"
13404 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13405 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13406 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13407 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13408 ""
1fd4e8c1 13409 "@
80103f96
FS		 13410 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13411 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
943c15ed
DE		 13412 [(set_attr "type" "two")
13413 (set_attr "length" "8")])
1fd4e8c1
RK		 13414
13415(define_insn ""
9ebbca7d 13416 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13417 (compare:CC
9ebbca7d
GK		 13418 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13419 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13420 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13421 (const_int 0)))
9ebbca7d 13422 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13423 "TARGET_32BIT"
1fd4e8c1 13424 "@
ca7f5001 13425 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
9ebbca7d
GK		 13426 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13427 #
13428 #"
b19003d8 13429 [(set_attr "type" "compare")
9ebbca7d
GK		 13430 (set_attr "length" "8,8,12,12")])
13431
13432(define_split
13433 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13434 (compare:CC
13435 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13436 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13437 (match_operand:SI 3 "gpc_reg_operand" ""))
13438 (const_int 0)))
13439 (clobber (match_scratch:SI 4 ""))]
683bdff7 13440 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13441 [(set (match_dup 4)
13442 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13443 (match_dup 3)))
13444 (set (match_dup 0)
13445 (compare:CC (match_dup 4)
13446 (const_int 0)))]
13447 "")
1fd4e8c1
RK		 13448
13449(define_insn ""
097657c3 13450 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13451 (compare:CC
9ebbca7d
GK		 13452 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13453 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13454 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13455 (const_int 0)))
097657c3
AM		 13456 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13457 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13458 "TARGET_32BIT"
1fd4e8c1 13459 "@
097657c3
AM		 13460 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13461 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
9ebbca7d
GK		 13462 #
13463 #"
b19003d8 13464 [(set_attr "type" "compare")
9ebbca7d
GK		 13465 (set_attr "length" "8,8,12,12")])
13466
13467(define_split
097657c3 13468 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13469 (compare:CC
13470 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13471 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13472 (match_operand:SI 3 "gpc_reg_operand" ""))
13473 (const_int 0)))
13474 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13475 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13476 "TARGET_32BIT && reload_completed"
097657c3 13477 [(set (match_dup 0)
9ebbca7d 13478 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13479 (set (match_dup 4)
9ebbca7d
GK		 13480 (compare:CC (match_dup 0)
13481 (const_int 0)))]
13482 "")
1fd4e8c1 13483
a2dba291
DE		 13484(define_insn "*neg_geu<mode>"
13485 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13486 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13487 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13488 ""
1fd4e8c1 13489 "@
ca7f5001 13490 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
8106dc08 13491 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
943c15ed
DE		 13492 [(set_attr "type" "three")
13493 (set_attr "length" "12")])
1fd4e8c1 13494
a2dba291
DE		 13495(define_insn "*and_neg_geu<mode>"
13496 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13497 (and:P (neg:P
13498 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13499 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13500 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13501 ""
1fd4e8c1 13502 "@
097657c3
AM		 13503 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13504 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 13505 [(set_attr "type" "three")
13506 (set_attr "length" "12")])
1fd4e8c1
RK		 13507
13508(define_insn ""
9ebbca7d 13509 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13510 (compare:CC
13511 (and:SI (neg:SI
9ebbca7d
GK		 13512 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13513 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13514 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13515 (const_int 0)))
9ebbca7d 13516 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13517 "TARGET_32BIT"
1fd4e8c1 13518 "@
ca7f5001 13519 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
9ebbca7d
GK		 13520 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13521 #
13522 #"
b19003d8 13523 [(set_attr "type" "compare")
9ebbca7d
GK		 13524 (set_attr "length" "12,12,16,16")])
13525
13526(define_split
13527 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13528 (compare:CC
13529 (and:SI (neg:SI
13530 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13531 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13532 (match_operand:SI 3 "gpc_reg_operand" ""))
13533 (const_int 0)))
13534 (clobber (match_scratch:SI 4 ""))]
683bdff7 13535 "TARGET_32BIT && reload_completed"
9ebbca7d 13536 [(set (match_dup 4)
097657c3
AM		 13537 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13538 (match_dup 3)))
9ebbca7d
GK		 13539 (set (match_dup 0)
13540 (compare:CC (match_dup 4)
13541 (const_int 0)))]
13542 "")
1fd4e8c1
RK		 13543
13544(define_insn ""
097657c3 13545 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13546 (compare:CC
13547 (and:SI (neg:SI
9ebbca7d
GK		 13548 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13549 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13550 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13551 (const_int 0)))
097657c3
AM		 13552 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13553 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13554 "TARGET_32BIT"
1fd4e8c1 13555 "@
097657c3
AM		 13556 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13557 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d
GK		 13558 #
13559 #"
b19003d8 13560 [(set_attr "type" "compare")
9ebbca7d
GK		 13561 (set_attr "length" "12,12,16,16")])
13562
13563(define_split
097657c3 13564 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13565 (compare:CC
13566 (and:SI (neg:SI
13567 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13568 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13569 (match_operand:SI 3 "gpc_reg_operand" ""))
13570 (const_int 0)))
13571 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13572 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13573 "TARGET_32BIT && reload_completed"
097657c3 13574 [(set (match_dup 0)
9ebbca7d 13575 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
097657c3 13576 (set (match_dup 4)
9ebbca7d
GK		 13577 (compare:CC (match_dup 0)
13578 (const_int 0)))]
13579 "")
1fd4e8c1 13580
1fd4e8c1 13581(define_insn ""
cd2b37d9
RK		 13582 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13583 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13584 (match_operand:SI 2 "reg_or_short_operand" "r")))]
ca7f5001
RK		 13585 "TARGET_POWER"
13586 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13587 [(set_attr "length" "12")])
1fd4e8c1
RK		 13588
13589(define_insn ""
9ebbca7d 13590 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13591 (compare:CC
9ebbca7d
GK		 13592 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13593 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
1fd4e8c1 13594 (const_int 0)))
9ebbca7d 13595 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13596 (gt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13597 "TARGET_POWER"
9ebbca7d
GK		 13598 "@
13599 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13600 #"
29ae5b89 13601 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13602 (set_attr "length" "12,16")])
13603
13604(define_split
13605 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13606 (compare:CC
13607 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13608 (match_operand:SI 2 "reg_or_short_operand" ""))
13609 (const_int 0)))
13610 (set (match_operand:SI 0 "gpc_reg_operand" "")
13611 (gt:SI (match_dup 1) (match_dup 2)))]
13612 "TARGET_POWER && reload_completed"
13613 [(set (match_dup 0)
13614 (gt:SI (match_dup 1) (match_dup 2)))
13615 (set (match_dup 3)
13616 (compare:CC (match_dup 0)
13617 (const_int 0)))]
13618 "")
1fd4e8c1 13619
d0515b39 13620(define_insn "*plus_gt0<mode>"
a2dba291
DE		 13621 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13622 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13623 (const_int 0))
13624 (match_operand:P 2 "gpc_reg_operand" "r")))]
13625 ""
80103f96 13626 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
943c15ed
DE		 13627 [(set_attr "type" "three")
13628 (set_attr "length" "12")])
1fd4e8c1
RK		 13629
13630(define_insn ""
9ebbca7d 13631 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13632 (compare:CC
9ebbca7d 13633 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 13634 (const_int 0))
9ebbca7d 13635 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 13636 (const_int 0)))
9ebbca7d 13637 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 13638 "TARGET_32BIT"
9ebbca7d
GK		 13639 "@
13640 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13641 #"
b19003d8 13642 [(set_attr "type" "compare")
9ebbca7d
GK		 13643 (set_attr "length" "12,16")])
13644
13645(define_split
13646 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13647 (compare:CC
13648 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13649 (const_int 0))
13650 (match_operand:SI 2 "gpc_reg_operand" ""))
13651 (const_int 0)))
13652 (clobber (match_scratch:SI 3 ""))]
683bdff7 13653 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13654 [(set (match_dup 3)
13655 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13656 (match_dup 2)))
13657 (set (match_dup 0)
13658 (compare:CC (match_dup 3)
13659 (const_int 0)))]
13660 "")
1fd4e8c1 13661
f9562f27 13662(define_insn ""
9ebbca7d 13663 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
f9562f27 13664 (compare:CC
9ebbca7d 13665 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13666 (const_int 0))
9ebbca7d 13667 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13668 (const_int 0)))
9ebbca7d 13669 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 13670 "TARGET_64BIT"
9ebbca7d
GK		 13671 "@
13672 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13673 #"
f9562f27 13674 [(set_attr "type" "compare")
9ebbca7d
GK		 13675 (set_attr "length" "12,16")])
13676
13677(define_split
13678 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13679 (compare:CC
13680 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13681 (const_int 0))
13682 (match_operand:DI 2 "gpc_reg_operand" ""))
13683 (const_int 0)))
13684 (clobber (match_scratch:DI 3 ""))]
683bdff7 13685 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13686 [(set (match_dup 3)
13687 (plus:DI (gt:DI (match_dup 1) (const_int 0))
097657c3 13688 (match_dup 2)))
9ebbca7d
GK		 13689 (set (match_dup 0)
13690 (compare:CC (match_dup 3)
13691 (const_int 0)))]
13692 "")
f9562f27 13693
1fd4e8c1 13694(define_insn ""
097657c3 13695 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9ebbca7d
GK		 13696 (compare:CC
13697 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13698 (const_int 0))
13699 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13700 (const_int 0)))
097657c3
AM		 13701 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13702 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13703 "TARGET_32BIT"
9ebbca7d 13704 "@
097657c3 13705 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
9ebbca7d
GK		 13706 #"
13707 [(set_attr "type" "compare")
13708 (set_attr "length" "12,16")])
13709
13710(define_split
097657c3 13711 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1fd4e8c1 13712 (compare:CC
9ebbca7d 13713 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 13714 (const_int 0))
9ebbca7d 13715 (match_operand:SI 2 "gpc_reg_operand" ""))
1fd4e8c1 13716 (const_int 0)))
9ebbca7d 13717 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13718 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13719 "TARGET_32BIT && reload_completed"
097657c3 13720 [(set (match_dup 0)
9ebbca7d 13721 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13722 (set (match_dup 3)
9ebbca7d
GK		 13723 (compare:CC (match_dup 0)
13724 (const_int 0)))]
13725 "")
1fd4e8c1 13726
f9562f27 13727(define_insn ""
097657c3 13728 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 13729 (compare:CC
9ebbca7d 13730 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13731 (const_int 0))
9ebbca7d 13732 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13733 (const_int 0)))
097657c3
AM		 13734 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13735 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13736 "TARGET_64BIT"
9ebbca7d 13737 "@
097657c3 13738 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
9ebbca7d 13739 #"
f9562f27 13740 [(set_attr "type" "compare")
9ebbca7d
GK		 13741 (set_attr "length" "12,16")])
13742
13743(define_split
097657c3 13744 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13745 (compare:CC
13746 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13747 (const_int 0))
13748 (match_operand:DI 2 "gpc_reg_operand" ""))
13749 (const_int 0)))
13750 (set (match_operand:DI 0 "gpc_reg_operand" "")
097657c3 13751 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13752 "TARGET_64BIT && reload_completed"
097657c3 13753 [(set (match_dup 0)
9ebbca7d 13754 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13755 (set (match_dup 3)
9ebbca7d
GK		 13756 (compare:CC (match_dup 0)
13757 (const_int 0)))]
13758 "")
f9562f27 13759
1fd4e8c1 13760(define_insn ""
097657c3 13761 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13762 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13763 (match_operand:SI 2 "reg_or_short_operand" "r"))
097657c3 13764 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13765 "TARGET_POWER"
097657c3 13766 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13767 [(set_attr "length" "12")])
1fd4e8c1
RK		 13768
13769(define_insn ""
9ebbca7d 13770 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13771 (compare:CC
9ebbca7d
GK		 13772 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13773 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13774 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13775 (const_int 0)))
9ebbca7d 13776 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13777 "TARGET_POWER"
9ebbca7d
GK		 13778 "@
13779 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13780 #"
b19003d8 13781 [(set_attr "type" "compare")
9ebbca7d
GK		 13782 (set_attr "length" "12,16")])
13783
13784(define_split
13785 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13786 (compare:CC
13787 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13788 (match_operand:SI 2 "reg_or_short_operand" ""))
13789 (match_operand:SI 3 "gpc_reg_operand" ""))
13790 (const_int 0)))
13791 (clobber (match_scratch:SI 4 ""))]
13792 "TARGET_POWER && reload_completed"
13793 [(set (match_dup 4)
097657c3 13794 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9ebbca7d
GK		 13795 (set (match_dup 0)
13796 (compare:CC (match_dup 4)
13797 (const_int 0)))]
13798 "")
1fd4e8c1
RK		 13799
13800(define_insn ""
097657c3 13801 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13802 (compare:CC
9ebbca7d
GK		 13803 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13804 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13805 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13806 (const_int 0)))
097657c3
AM		 13807 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13808 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13809 "TARGET_POWER"
9ebbca7d 13810 "@
097657c3 13811 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13812 #"
b19003d8 13813 [(set_attr "type" "compare")
9ebbca7d
GK		 13814 (set_attr "length" "12,16")])
13815
13816(define_split
097657c3 13817 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13818 (compare:CC
13819 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13820 (match_operand:SI 2 "reg_or_short_operand" ""))
13821 (match_operand:SI 3 "gpc_reg_operand" ""))
13822 (const_int 0)))
13823 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13824 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13825 "TARGET_POWER && reload_completed"
097657c3 13826 [(set (match_dup 0)
9ebbca7d 13827 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13828 (set (match_dup 4)
9ebbca7d
GK		 13829 (compare:CC (match_dup 0)
13830 (const_int 0)))]
13831 "")
1fd4e8c1 13832
1fd4e8c1 13833(define_insn ""
cd2b37d9
RK		 13834 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13835 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13836 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
ca7f5001
RK		 13837 "TARGET_POWER"
13838 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13839 [(set_attr "length" "12")])
1fd4e8c1 13840
ce45ef46
DE		 13841(define_insn_and_split "*gtu<mode>"
13842 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13843 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13844 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13845 ""
c0600ecd 13846 "#"
ce45ef46
DE		 13847 ""
13848 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13849 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 13850 "")
f9562f27 13851
1e24ce83 13852(define_insn_and_split "*gtu<mode>_compare"
9ebbca7d 13853 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13854 (compare:CC
a2dba291
DE		 13855 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13856 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13857 (const_int 0)))
a2dba291
DE		 13858 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13859 (gtu:P (match_dup 1) (match_dup 2)))]
13860 ""
1e24ce83
DE		 13861 "#"
13862 ""
13863 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13864 (parallel [(set (match_dup 3)
13865 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13866 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 13867 "")
f9562f27 13868
1e24ce83 13869(define_insn_and_split "*plus_gtu<mode>"
a2dba291
DE		 13870 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13871 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13872 (match_operand:P 2 "reg_or_short_operand" "rI"))
13873 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13874 ""
c0600ecd 13875 "#"
04fa46cf 13876 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 13877 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13878 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 13879 "")
f9562f27 13880
1e24ce83 13881(define_insn_and_split "*plus_gtu<mode>_compare"
097657c3 13882 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 13883 (compare:CC
1e24ce83
DE		 13884 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13885 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13886 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
f9562f27 13887 (const_int 0)))
1e24ce83
DE		 13888 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13889 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13890 ""
13891 "#"
13892 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13893 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13894 (parallel [(set (match_dup 4)
13895 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13896 (const_int 0)))
13897 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 13898 "")
f9562f27 13899
ce45ef46
DE		 13900(define_insn "*neg_gtu<mode>"
13901 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13902 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13903 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13904 ""
ca7f5001 13905 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
943c15ed 13906 [(set_attr "type" "two")
c0600ecd 13907 (set_attr "length" "8")])
f9562f27 13908
1fd4e8c1
RK		 13909\f
13910;; Define both directions of branch and return. If we need a reload
13911;; register, we'd rather use CR0 since it is much easier to copy a
13912;; register CC value to there.
13913
13914(define_insn ""
13915 [(set (pc)
13916 (if_then_else (match_operator 1 "branch_comparison_operator"
13917 [(match_operand 2
b54cf83a 13918 "cc_reg_operand" "y")
1fd4e8c1
RK		 13919 (const_int 0)])
13920 (label_ref (match_operand 0 "" ""))
13921 (pc)))]
13922 ""
b19003d8
RK		 13923 "*
13924{
12a4e8c5 13925 return output_cbranch (operands[1], \"%l0\", 0, insn);
b19003d8
RK		 13926}"
13927 [(set_attr "type" "branch")])
13928
1fd4e8c1
RK		 13929(define_insn ""
13930 [(set (pc)
13931 (if_then_else (match_operator 0 "branch_comparison_operator"
13932 [(match_operand 1
b54cf83a 13933 "cc_reg_operand" "y")
1fd4e8c1
RK		 13934 (const_int 0)])
13935 (return)
13936 (pc)))]
13937 "direct_return ()"
12a4e8c5
GK		 13938 "*
13939{
13940 return output_cbranch (operands[0], NULL, 0, insn);
13941}"
9c6fdb46 13942 [(set_attr "type" "jmpreg")
39a10a29 13943 (set_attr "length" "4")])
1fd4e8c1
RK		 13944
13945(define_insn ""
13946 [(set (pc)
13947 (if_then_else (match_operator 1 "branch_comparison_operator"
13948 [(match_operand 2
b54cf83a 13949 "cc_reg_operand" "y")
1fd4e8c1
RK		 13950 (const_int 0)])
13951 (pc)
13952 (label_ref (match_operand 0 "" ""))))]
13953 ""
b19003d8
RK		 13954 "*
13955{
12a4e8c5 13956 return output_cbranch (operands[1], \"%l0\", 1, insn);
b19003d8
RK		 13957}"
13958 [(set_attr "type" "branch")])
1fd4e8c1
RK		 13959
13960(define_insn ""
13961 [(set (pc)
13962 (if_then_else (match_operator 0 "branch_comparison_operator"
13963 [(match_operand 1
b54cf83a 13964 "cc_reg_operand" "y")
1fd4e8c1
RK		 13965 (const_int 0)])
13966 (pc)
13967 (return)))]
13968 "direct_return ()"
12a4e8c5
GK		 13969 "*
13970{
13971 return output_cbranch (operands[0], NULL, 1, insn);
13972}"
9c6fdb46 13973 [(set_attr "type" "jmpreg")
39a10a29
GK		 13974 (set_attr "length" "4")])
13975
13976;; Logic on condition register values.
13977
13978; This pattern matches things like
13979; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13980; (eq:SI (reg:CCFP 68) (const_int 0)))
13981; (const_int 1)))
13982; which are generated by the branch logic.
b54cf83a 13983; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
39a10a29 13984
423c1189 13985(define_insn "*cceq_ior_compare"
b54cf83a 13986 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13987 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
b54cf83a 13988 [(match_operator:SI 2
39a10a29
GK		 13989 "branch_positive_comparison_operator"
13990 [(match_operand 3
b54cf83a 13991 "cc_reg_operand" "y,y")
39a10a29 13992 (const_int 0)])
b54cf83a 13993 (match_operator:SI 4
39a10a29
GK		 13994 "branch_positive_comparison_operator"
13995 [(match_operand 5
b54cf83a 13996 "cc_reg_operand" "0,y")
39a10a29
GK		 13997 (const_int 0)])])
13998 (const_int 1)))]
24fab1d3 13999 ""
39a10a29 14000 "cr%q1 %E0,%j2,%j4"
b54cf83a 14001 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 14002
14003; Why is the constant -1 here, but 1 in the previous pattern?
14004; Because ~1 has all but the low bit set.
14005(define_insn ""
b54cf83a 14006 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 14007 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
b54cf83a 14008 [(not:SI (match_operator:SI 2
39a10a29
GK		 14009 "branch_positive_comparison_operator"
14010 [(match_operand 3
b54cf83a 14011 "cc_reg_operand" "y,y")
39a10a29
GK		 14012 (const_int 0)]))
14013 (match_operator:SI 4
14014 "branch_positive_comparison_operator"
14015 [(match_operand 5
b54cf83a 14016 "cc_reg_operand" "0,y")
39a10a29
GK		 14017 (const_int 0)])])
14018 (const_int -1)))]
14019 ""
14020 "cr%q1 %E0,%j2,%j4"
b54cf83a 14021 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29 14022
423c1189 14023(define_insn "*cceq_rev_compare"
b54cf83a 14024 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
6c873122 14025 (compare:CCEQ (match_operator:SI 1
39a10a29 14026 "branch_positive_comparison_operator"
6c873122 14027 [(match_operand 2
b54cf83a 14028 "cc_reg_operand" "0,y")
39a10a29
GK		 14029 (const_int 0)])
14030 (const_int 0)))]
423c1189 14031 ""
251b3667 14032 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
b54cf83a 14033 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 14034
14035;; If we are comparing the result of two comparisons, this can be done
14036;; using creqv or crxor.
14037
14038(define_insn_and_split ""
14039 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14040 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14041 [(match_operand 2 "cc_reg_operand" "y")
14042 (const_int 0)])
14043 (match_operator 3 "branch_comparison_operator"
14044 [(match_operand 4 "cc_reg_operand" "y")
14045 (const_int 0)])))]
14046 ""
14047 "#"
14048 ""
14049 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14050 (match_dup 5)))]
14051 "
14052{
14053 int positive_1, positive_2;
14054
364849ee
DE		 14055 positive_1 = branch_positive_comparison_operator (operands[1],
14056 GET_MODE (operands[1]));
14057 positive_2 = branch_positive_comparison_operator (operands[3],
14058 GET_MODE (operands[3]));
39a10a29
GK		 14059
14060 if (! positive_1)
1c563bed 14061 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
0f4c242b
KH		 14062 GET_CODE (operands[1])),
14063 SImode,
14064 operands[2], const0_rtx);
39a10a29 14065 else if (GET_MODE (operands[1]) != SImode)
0f4c242b
KH		 14066 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14067 operands[2], const0_rtx);
39a10a29
GK		 14068
14069 if (! positive_2)
1c563bed 14070 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
0f4c242b
KH		 14071 GET_CODE (operands[3])),
14072 SImode,
14073 operands[4], const0_rtx);
39a10a29 14074 else if (GET_MODE (operands[3]) != SImode)
0f4c242b
KH		 14075 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14076 operands[4], const0_rtx);
39a10a29
GK		 14077
14078 if (positive_1 == positive_2)
251b3667
DE		 14079 {
14080 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14081 operands[5] = constm1_rtx;
14082 }
14083 else
14084 {
14085 operands[5] = const1_rtx;
14086 }
39a10a29 14087}")
1fd4e8c1
RK		 14088
14089;; Unconditional branch and return.
14090
14091(define_insn "jump"
14092 [(set (pc)
14093 (label_ref (match_operand 0 "" "")))]
14094 ""
b7ff3d82
DE		 14095 "b %l0"
14096 [(set_attr "type" "branch")])
1fd4e8c1
RK		 14097
14098(define_insn "return"
14099 [(return)]
14100 "direct_return ()"
324e52cc
TG		 14101 "{br|blr}"
14102 [(set_attr "type" "jmpreg")])
1fd4e8c1 14103
0ad91047 14104(define_expand "indirect_jump"
4ae234b0 14105 [(set (pc) (match_operand 0 "register_operand" ""))])
0ad91047 14106
4ae234b0
GK		 14107(define_insn "*indirect_jump<mode>"
14108 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14109 ""
b92b324d
DE		 14110 "@
14111 bctr
14112 {br|blr}"
324e52cc 14113 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14114
14115;; Table jump for switch statements:
14116(define_expand "tablejump"
e6ca2c17
DE		 14117 [(use (match_operand 0 "" ""))
14118 (use (label_ref (match_operand 1 "" "")))]
14119 ""
14120 "
14121{
14122 if (TARGET_32BIT)
14123 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14124 else
14125 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14126 DONE;
14127}")
14128
14129(define_expand "tablejumpsi"
1fd4e8c1
RK		 14130 [(set (match_dup 3)
14131 (plus:SI (match_operand:SI 0 "" "")
14132 (match_dup 2)))
14133 (parallel [(set (pc) (match_dup 3))
14134 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14135 "TARGET_32BIT"
1fd4e8c1
RK		 14136 "
14137{ operands[0] = force_reg (SImode, operands[0]);
c5c76735 14138 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
1fd4e8c1
RK		 14139 operands[3] = gen_reg_rtx (SImode);
14140}")
14141
e6ca2c17 14142(define_expand "tablejumpdi"
6ae08853 14143 [(set (match_dup 4)
e42ac3de 14144 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
9ebbca7d
GK		 14145 (set (match_dup 3)
14146 (plus:DI (match_dup 4)
e6ca2c17
DE		 14147 (match_dup 2)))
14148 (parallel [(set (pc) (match_dup 3))
14149 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14150 "TARGET_64BIT"
e6ca2c17 14151 "
9ebbca7d 14152{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
e6ca2c17 14153 operands[3] = gen_reg_rtx (DImode);
9ebbca7d 14154 operands[4] = gen_reg_rtx (DImode);
e6ca2c17
DE		 14155}")
14156
ce45ef46 14157(define_insn "*tablejump<mode>_internal1"
1fd4e8c1 14158 [(set (pc)
4ae234b0 14159 (match_operand:P 0 "register_operand" "c,*l"))
1fd4e8c1 14160 (use (label_ref (match_operand 1 "" "")))]
4ae234b0 14161 ""
c859cda6
DJ		 14162 "@
14163 bctr
14164 {br|blr}"
a6845123 14165 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14166
14167(define_insn "nop"
14168 [(const_int 0)]
14169 ""
ca7f5001 14170 "{cror 0,0,0|nop}")
1fd4e8c1 14171\f
7e69e155 14172;; Define the subtract-one-and-jump insns, starting with the template
c225ba7b
RK		 14173;; so loop.c knows what to generate.
14174
5527bf14
RH		 14175(define_expand "doloop_end"
14176 [(use (match_operand 0 "" "")) ; loop pseudo
14177 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14178 (use (match_operand 2 "" "")) ; max iterations
14179 (use (match_operand 3 "" "")) ; loop level
14180 (use (match_operand 4 "" ""))] ; label
0ad91047
DE		 14181 ""
14182 "
14183{
5527bf14
RH		 14184 /* Only use this on innermost loops. */
14185 if (INTVAL (operands[3]) > 1)
14186 FAIL;
683bdff7 14187 if (TARGET_64BIT)
5527bf14
RH		 14188 {
14189 if (GET_MODE (operands[0]) != DImode)
14190 FAIL;
14191 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14192 }
0ad91047 14193 else
5527bf14
RH		 14194 {
14195 if (GET_MODE (operands[0]) != SImode)
14196 FAIL;
14197 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14198 }
0ad91047
DE		 14199 DONE;
14200}")
14201
4ae234b0 14202(define_expand "ctr<mode>"
3cb999d8 14203 [(parallel [(set (pc)
4ae234b0 14204 (if_then_else (ne (match_operand:P 0 "register_operand" "")
3cb999d8
DE		 14205 (const_int 1))
14206 (label_ref (match_operand 1 "" ""))
14207 (pc)))
b6c9286a 14208 (set (match_dup 0)
4ae234b0 14209 (plus:P (match_dup 0)
b6c9286a 14210 (const_int -1)))
5f81043f 14211 (clobber (match_scratch:CC 2 ""))
4ae234b0
GK		 14212 (clobber (match_scratch:P 3 ""))])]
14213 ""
61c07d3c 14214 "")
c225ba7b 14215
1fd4e8c1
RK		 14216;; We need to be able to do this for any operand, including MEM, or we
14217;; will cause reload to blow up since we don't allow output reloads on
7e69e155 14218;; JUMP_INSNs.
0ad91047 14219;; For the length attribute to be calculated correctly, the
5f81043f
RK		 14220;; label MUST be operand 0.
14221
4ae234b0 14222(define_insn "*ctr<mode>_internal1"
0ad91047 14223 [(set (pc)
4ae234b0 14224 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14225 (const_int 1))
14226 (label_ref (match_operand 0 "" ""))
14227 (pc)))
4ae234b0
GK		 14228 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14229 (plus:P (match_dup 1)
0ad91047 14230 (const_int -1)))
43b68ce5 14231 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14232 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14233 ""
0ad91047
DE		 14234 "*
14235{
14236 if (which_alternative != 0)
14237 return \"#\";
856a6884 14238 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14239 return \"{bdn|bdnz} %l0\";
14240 else
f607bc57 14241 return \"bdz $+8\;b %l0\";
0ad91047
DE		 14242}"
14243 [(set_attr "type" "branch")
5a195cb5 14244 (set_attr "length" "*,12,16,16")])
0ad91047 14245
4ae234b0 14246(define_insn "*ctr<mode>_internal2"
0ad91047 14247 [(set (pc)
4ae234b0 14248 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14249 (const_int 1))
14250 (pc)
14251 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14252 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14253 (plus:P (match_dup 1)
0ad91047 14254 (const_int -1)))
43b68ce5 14255 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14256 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14257 ""
5f81043f
RK		 14258 "*
14259{
14260 if (which_alternative != 0)
14261 return \"#\";
856a6884 14262 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14263 return \"bdz %l0\";
14264 else
f607bc57 14265 return \"{bdn|bdnz} $+8\;b %l0\";
5f81043f
RK		 14266}"
14267 [(set_attr "type" "branch")
5a195cb5 14268 (set_attr "length" "*,12,16,16")])
5f81043f 14269
0ad91047
DE		 14270;; Similar but use EQ
14271
4ae234b0 14272(define_insn "*ctr<mode>_internal5"
5f81043f 14273 [(set (pc)
4ae234b0 14274 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
1fd4e8c1 14275 (const_int 1))
a6845123 14276 (label_ref (match_operand 0 "" ""))
1fd4e8c1 14277 (pc)))
4ae234b0
GK		 14278 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14279 (plus:P (match_dup 1)
0ad91047 14280 (const_int -1)))
43b68ce5 14281 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14282 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14283 ""
0ad91047
DE		 14284 "*
14285{
14286 if (which_alternative != 0)
14287 return \"#\";
856a6884 14288 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14289 return \"bdz %l0\";
14290 else
f607bc57 14291 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 14292}"
14293 [(set_attr "type" "branch")
5a195cb5 14294 (set_attr "length" "*,12,16,16")])
0ad91047 14295
4ae234b0 14296(define_insn "*ctr<mode>_internal6"
0ad91047 14297 [(set (pc)
4ae234b0 14298 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14299 (const_int 1))
14300 (pc)
14301 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14302 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14303 (plus:P (match_dup 1)
0ad91047 14304 (const_int -1)))
43b68ce5 14305 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14306 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14307 ""
5f81043f
RK		 14308 "*
14309{
14310 if (which_alternative != 0)
14311 return \"#\";
856a6884 14312 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14313 return \"{bdn|bdnz} %l0\";
14314 else
f607bc57 14315 return \"bdz $+8\;b %l0\";
5f81043f
RK		 14316}"
14317 [(set_attr "type" "branch")
5a195cb5 14318 (set_attr "length" "*,12,16,16")])
5f81043f 14319
0ad91047
DE		 14320;; Now the splitters if we could not allocate the CTR register
14321
1fd4e8c1
RK		 14322(define_split
14323 [(set (pc)
14324 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14325 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14326 (const_int 1)])
61c07d3c
DE		 14327 (match_operand 5 "" "")
14328 (match_operand 6 "" "")))
4ae234b0
GK		 14329 (set (match_operand:P 0 "gpc_reg_operand" "")
14330 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14331 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14332 (clobber (match_scratch:P 4 ""))]
14333 "reload_completed"
0ad91047 14334 [(parallel [(set (match_dup 3)
4ae234b0 14335 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14336 (const_int -1))
14337 (const_int 0)))
14338 (set (match_dup 0)
4ae234b0 14339 (plus:P (match_dup 1)
0ad91047 14340 (const_int -1)))])
61c07d3c
DE		 14341 (set (pc) (if_then_else (match_dup 7)
14342 (match_dup 5)
14343 (match_dup 6)))]
0ad91047 14344 "
0f4c242b
KH		 14345{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14346 operands[3], const0_rtx); }")
0ad91047
DE		 14347
14348(define_split
14349 [(set (pc)
14350 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14351 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14352 (const_int 1)])
61c07d3c
DE		 14353 (match_operand 5 "" "")
14354 (match_operand 6 "" "")))
4ae234b0
GK		 14355 (set (match_operand:P 0 "nonimmediate_operand" "")
14356 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14357 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14358 (clobber (match_scratch:P 4 ""))]
14359 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
0ad91047 14360 [(parallel [(set (match_dup 3)
4ae234b0 14361 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14362 (const_int -1))
14363 (const_int 0)))
14364 (set (match_dup 4)
4ae234b0 14365 (plus:P (match_dup 1)
0ad91047
DE		 14366 (const_int -1)))])
14367 (set (match_dup 0)
14368 (match_dup 4))
61c07d3c
DE		 14369 (set (pc) (if_then_else (match_dup 7)
14370 (match_dup 5)
14371 (match_dup 6)))]
0ad91047 14372 "
0f4c242b
KH		 14373{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14374 operands[3], const0_rtx); }")
e0cd0770
JC		 14375\f
14376(define_insn "trap"
14377 [(trap_if (const_int 1) (const_int 0))]
14378 ""
44cd321e
PS		 14379 "{t 31,0,0|trap}"
14380 [(set_attr "type" "trap")])
e0cd0770
JC		 14381
14382(define_expand "conditional_trap"
14383 [(trap_if (match_operator 0 "trap_comparison_operator"
14384 [(match_dup 2) (match_dup 3)])
14385 (match_operand 1 "const_int_operand" ""))]
14386 ""
14387 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14388 operands[2] = rs6000_compare_op0;
14389 operands[3] = rs6000_compare_op1;")
14390
14391(define_insn ""
14392 [(trap_if (match_operator 0 "trap_comparison_operator"
4ae234b0
GK		 14393 [(match_operand:GPR 1 "register_operand" "r")
14394 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
e0cd0770
JC		 14395 (const_int 0))]
14396 ""
44cd321e
PS		 14397 "{t|t<wd>}%V0%I2 %1,%2"
14398 [(set_attr "type" "trap")])
9ebbca7d
GK		 14399\f
14400;; Insns related to generating the function prologue and epilogue.
14401
14402(define_expand "prologue"
14403 [(use (const_int 0))]
14404 "TARGET_SCHED_PROLOG"
14405 "
14406{
14407 rs6000_emit_prologue ();
14408 DONE;
14409}")
14410
2c4a9cff
DE		 14411(define_insn "*movesi_from_cr_one"
14412 [(match_parallel 0 "mfcr_operation"
14413 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14414 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14415 (match_operand 3 "immediate_operand" "n")]
14416 UNSPEC_MOVESI_FROM_CR))])]
14417 "TARGET_MFCRF"
14418 "*
14419{
14420 int mask = 0;
14421 int i;
14422 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14423 {
14424 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14425 operands[4] = GEN_INT (mask);
14426 output_asm_insn (\"mfcr %1,%4\", operands);
14427 }
14428 return \"\";
14429}"
14430 [(set_attr "type" "mfcrf")])
14431
9ebbca7d
GK		 14432(define_insn "movesi_from_cr"
14433 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1de43f85
DE		 14434 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14435 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14436 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14437 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
615158e2 14438 UNSPEC_MOVESI_FROM_CR))]
9ebbca7d 14439 ""
309323c2 14440 "mfcr %0"
b54cf83a 14441 [(set_attr "type" "mfcr")])
9ebbca7d
GK		 14442
14443(define_insn "*stmw"
e033a023
DE		 14444 [(match_parallel 0 "stmw_operation"
14445 [(set (match_operand:SI 1 "memory_operand" "=m")
14446 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14447 "TARGET_MULTIPLE"
9c6fdb46
DE		 14448 "{stm|stmw} %2,%1"
14449 [(set_attr "type" "store_ux")])
6ae08853 14450
4ae234b0 14451(define_insn "*save_fpregs_<mode>"
85d346f1 14452 [(match_parallel 0 "any_parallel_operand"
e65a3857
DE		 14453 [(clobber (reg:P 65))
14454 (use (match_operand:P 1 "call_operand" "s"))
14455 (set (match_operand:DF 2 "memory_operand" "=m")
14456 (match_operand:DF 3 "gpc_reg_operand" "f"))])]
4ae234b0 14457 ""
e65a3857 14458 "bl %z1"
e033a023
DE		 14459 [(set_attr "type" "branch")
14460 (set_attr "length" "4")])
9ebbca7d
GK		 14461
14462; These are to explain that changes to the stack pointer should
14463; not be moved over stores to stack memory.
14464(define_insn "stack_tie"
14465 [(set (match_operand:BLK 0 "memory_operand" "+m")
615158e2 14466 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9ebbca7d
GK		 14467 ""
14468 ""
14469 [(set_attr "length" "0")])
14470
14471
14472(define_expand "epilogue"
14473 [(use (const_int 0))]
14474 "TARGET_SCHED_PROLOG"
14475 "
14476{
14477 rs6000_emit_epilogue (FALSE);
14478 DONE;
14479}")
14480
14481; On some processors, doing the mtcrf one CC register at a time is
14482; faster (like on the 604e). On others, doing them all at once is
14483; faster; for instance, on the 601 and 750.
14484
14485(define_expand "movsi_to_cr_one"
e42ac3de
RS		 14486 [(set (match_operand:CC 0 "cc_reg_operand" "")
14487 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
615158e2 14488 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
35aba846
DE		 14489 ""
14490 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
9ebbca7d
GK		 14491
14492(define_insn "*movsi_to_cr"
35aba846
DE		 14493 [(match_parallel 0 "mtcrf_operation"
14494 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14495 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14496 (match_operand 3 "immediate_operand" "n")]
615158e2 14497 UNSPEC_MOVESI_TO_CR))])]
9ebbca7d 14498 ""
e35b9579
GK		 14499 "*
14500{
14501 int mask = 0;
14502 int i;
14503 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14504 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14505 operands[4] = GEN_INT (mask);
14506 return \"mtcrf %4,%2\";
309323c2 14507}"
b54cf83a 14508 [(set_attr "type" "mtcr")])
9ebbca7d 14509
b54cf83a 14510(define_insn "*mtcrfsi"
309323c2
DE		 14511 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14512 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
615158e2
JJ		 14513 (match_operand 2 "immediate_operand" "n")]
14514 UNSPEC_MOVESI_TO_CR))]
6ae08853 14515 "GET_CODE (operands[0]) == REG
309323c2
DE		 14516 && CR_REGNO_P (REGNO (operands[0]))
14517 && GET_CODE (operands[2]) == CONST_INT
14518 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14519 "mtcrf %R0,%1"
b54cf83a 14520 [(set_attr "type" "mtcr")])
9ebbca7d
GK		 14521
14522; The load-multiple instructions have similar properties.
14523; Note that "load_multiple" is a name known to the machine-independent
9c6fdb46 14524; code that actually corresponds to the PowerPC load-string.
9ebbca7d
GK		 14525
14526(define_insn "*lmw"
35aba846
DE		 14527 [(match_parallel 0 "lmw_operation"
14528 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14529 (match_operand:SI 2 "memory_operand" "m"))])]
14530 "TARGET_MULTIPLE"
9c6fdb46
DE		 14531 "{lm|lmw} %1,%2"
14532 [(set_attr "type" "load_ux")])
6ae08853 14533
4ae234b0 14534(define_insn "*return_internal_<mode>"
e35b9579 14535 [(return)
4ae234b0
GK		 14536 (use (match_operand:P 0 "register_operand" "lc"))]
14537 ""
cccf3bdc 14538 "b%T0"
9ebbca7d
GK		 14539 [(set_attr "type" "jmpreg")])
14540
14541; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
85d346f1 14542; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
9ebbca7d 14543
4ae234b0 14544(define_insn "*return_and_restore_fpregs_<mode>"
85d346f1 14545 [(match_parallel 0 "any_parallel_operand"
e35b9579 14546 [(return)
e65a3857
DE		 14547 (use (reg:P 65))
14548 (use (match_operand:P 1 "call_operand" "s"))
14549 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
14550 (match_operand:DF 3 "memory_operand" "m"))])]
4ae234b0 14551 ""
e65a3857 14552 "b %z1")
9ebbca7d 14553
83720594
RH		 14554; This is used in compiling the unwind routines.
14555(define_expand "eh_return"
34dc173c 14556 [(use (match_operand 0 "general_operand" ""))]
9ebbca7d
GK		 14557 ""
14558 "
14559{
83720594 14560 if (TARGET_32BIT)
34dc173c 14561 emit_insn (gen_eh_set_lr_si (operands[0]));
9ebbca7d 14562 else
34dc173c 14563 emit_insn (gen_eh_set_lr_di (operands[0]));
9ebbca7d
GK		 14564 DONE;
14565}")
14566
83720594 14567; We can't expand this before we know where the link register is stored.
4ae234b0
GK		 14568(define_insn "eh_set_lr_<mode>"
14569 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
615158e2 14570 UNSPECV_EH_RR)
4ae234b0
GK		 14571 (clobber (match_scratch:P 1 "=&b"))]
14572 ""
83720594 14573 "#")
9ebbca7d
GK		 14574
14575(define_split
615158e2 14576 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
83720594
RH		 14577 (clobber (match_scratch 1 ""))]
14578 "reload_completed"
14579 [(const_int 0)]
9ebbca7d
GK		 14580 "
14581{
d1d0c603 14582 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
83720594
RH		 14583 DONE;
14584}")
0ac081f6 14585
01a2ccd0 14586(define_insn "prefetch"
3256a76e 14587 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
6041bf2f
DE		 14588 (match_operand:SI 1 "const_int_operand" "n")
14589 (match_operand:SI 2 "const_int_operand" "n"))]
01a2ccd0 14590 "TARGET_POWERPC"
6041bf2f
DE		 14591 "*
14592{
01a2ccd0
DE		 14593 if (GET_CODE (operands[0]) == REG)
14594 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14595 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
6041bf2f
DE		 14596}"
14597 [(set_attr "type" "load")])
915167f5 14598\f
a3170dc6 14599
f565b0a1 14600(include "sync.md")
10ed84db 14601(include "altivec.md")
a3170dc6 14602(include "spe.md")
7393f7f8 14603(include "dfp.md")
96038623 14604(include "paired.md")
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