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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
9ebbca7d | 2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
792760b9 | 3 | ;; 1999, 2000, 2001 Free Software Foundation, Inc. |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 RK |
5 | |
6 | ;; This file is part of GNU CC. | |
7 | ||
8 | ;; GNU CC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 2, or (at your option) | |
11 | ;; any later version. | |
12 | ||
13 | ;; GNU CC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GNU CC; see the file COPYING. If not, write to | |
3f63df56 RK |
20 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | ;; Boston, MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d GK |
24 | |
25 | ;; `unspec' values used in rs6000.md: | |
26 | ;; Number Use | |
27 | ;; 0 frsp for POWER machines | |
28 | ;; 0/v blockage | |
29 | ;; 5 used to tie the stack contents and the stack pointer | |
30 | ;; 6 address of a word pointing to the TOC | |
31 | ;; 7 address of the TOC (more-or-less) | |
32 | ;; 8 movsi_got | |
33 | ;; 9/v eh_reg_restore | |
34 | ;; 10 fctiwz | |
35 | ;; 19 movesi_from_cr | |
36 | ;; 20 movesi_to_cr | |
1fd4e8c1 RK |
37 | \f |
38 | ;; Define an insn type attribute. This is used in function unit delay | |
39 | ;; computations. | |
39a10a29 | 40 | (define_attr "type" "integer,load,store,fpload,fpstore,imul,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg" |
1fd4e8c1 RK |
41 | (const_string "integer")) |
42 | ||
b19003d8 | 43 | ;; Length (in bytes). |
6cbadf36 GK |
44 | ; '(pc)' in the following doesn't include the instruction itself; it is |
45 | ; calculated as if the instruction had zero size. | |
b19003d8 RK |
46 | (define_attr "length" "" |
47 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 48 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 49 | (const_int -32768)) |
6cbadf36 GK |
50 | (lt (minus (match_dup 0) (pc)) |
51 | (const_int 32764))) | |
39a10a29 GK |
52 | (const_int 4) |
53 | (const_int 8)) | |
b19003d8 RK |
54 | (const_int 4))) |
55 | ||
cfb557c4 RK |
56 | ;; Processor type -- this attribute must exactly match the processor_type |
57 | ;; enumeration in rs6000.h. | |
58 | ||
3cb999d8 | 59 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750" |
cfb557c4 RK |
60 | (const (symbol_ref "rs6000_cpu_attr"))) |
61 | ||
62 | ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY | |
63 | ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) | |
64 | ||
b7ff3d82 | 65 | ; Load/Store Unit -- pure PowerPC only |
51b8fc2c | 66 | ; (POWER and 601 use Integer Unit) |
cfb557c4 RK |
67 | (define_function_unit "lsu" 1 0 |
68 | (and (eq_attr "type" "load") | |
3cb999d8 | 69 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b6c9286a | 70 | 2 1) |
cfb557c4 RK |
71 | |
72 | (define_function_unit "lsu" 1 0 | |
b7ff3d82 | 73 | (and (eq_attr "type" "store,fpstore") |
3cb999d8 | 74 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b7ff3d82 | 75 | 1 1) |
b6c9286a MM |
76 | |
77 | (define_function_unit "lsu" 1 0 | |
78 | (and (eq_attr "type" "fpload") | |
bef84347 | 79 | (eq_attr "cpu" "mpccore,ppc603,ppc750")) |
b6c9286a | 80 | 2 1) |
cfb557c4 | 81 | |
b7ff3d82 DE |
82 | (define_function_unit "lsu" 1 0 |
83 | (and (eq_attr "type" "fpload") | |
3cb999d8 | 84 | (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 DE |
85 | 3 1) |
86 | ||
cfb557c4 RK |
87 | (define_function_unit "iu" 1 0 |
88 | (and (eq_attr "type" "load") | |
b7ff3d82 | 89 | (eq_attr "cpu" "rios1,ppc403,ppc601")) |
b6c9286a | 90 | 2 1) |
cfb557c4 RK |
91 | |
92 | (define_function_unit "iu" 1 0 | |
b7ff3d82 DE |
93 | (and (eq_attr "type" "store,fpstore") |
94 | (eq_attr "cpu" "rios1,ppc403,ppc601")) | |
95 | 1 1) | |
96 | ||
97 | (define_function_unit "fpu" 1 0 | |
98 | (and (eq_attr "type" "fpstore") | |
3624a679 | 99 | (eq_attr "cpu" "rios1,ppc601")) |
b7ff3d82 | 100 | 0 1) |
cfb557c4 | 101 | |
49a0b204 | 102 | (define_function_unit "iu" 1 0 |
b7ff3d82 | 103 | (and (eq_attr "type" "fpload") |
b6c9286a | 104 | (eq_attr "cpu" "rios1")) |
b7ff3d82 DE |
105 | 2 1) |
106 | ||
107 | (define_function_unit "iu" 1 0 | |
108 | (and (eq_attr "type" "fpload") | |
109 | (eq_attr "cpu" "ppc601")) | |
110 | 3 1) | |
111 | ||
112 | (define_function_unit "iu2" 2 0 | |
113 | (and (eq_attr "type" "load,fpload") | |
114 | (eq_attr "cpu" "rios2")) | |
115 | 2 1) | |
116 | ||
117 | (define_function_unit "iu2" 2 0 | |
118 | (and (eq_attr "type" "store,fpstore") | |
119 | (eq_attr "cpu" "rios2")) | |
120 | 1 1) | |
121 | ||
3cb999d8 | 122 | ; Integer Unit (RIOS1, PPC601, PPC603, RS64a) |
b7ff3d82 DE |
123 | (define_function_unit "iu" 1 0 |
124 | (and (eq_attr "type" "integer") | |
3cb999d8 | 125 | (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc601,ppc603")) |
b7ff3d82 | 126 | 1 1) |
49a0b204 | 127 | |
39a10a29 GK |
128 | (define_function_unit "iu" 1 0 |
129 | (and (eq_attr "type" "cr_logical") | |
5638268e | 130 | (eq_attr "cpu" "mpccore,ppc403,ppc601")) |
39a10a29 GK |
131 | 1 1) |
132 | ||
da0ae67f MM |
133 | (define_function_unit "iu" 1 0 |
134 | (and (eq_attr "type" "imul") | |
135 | (eq_attr "cpu" "ppc403")) | |
136 | 4 4) | |
137 | ||
cfb557c4 RK |
138 | (define_function_unit "iu" 1 0 |
139 | (and (eq_attr "type" "imul") | |
b7ff3d82 | 140 | (eq_attr "cpu" "rios1,ppc601,ppc603")) |
51b8fc2c | 141 | 5 5) |
cfb557c4 | 142 | |
3cb999d8 DE |
143 | (define_function_unit "iu" 1 0 |
144 | (and (eq_attr "type" "imul") | |
145 | (eq_attr "cpu" "rs64a")) | |
146 | 20 14) | |
147 | ||
148 | (define_function_unit "iu" 1 0 | |
149 | (and (eq_attr "type" "lmul") | |
150 | (eq_attr "cpu" "rs64a")) | |
151 | 34 34) | |
152 | ||
cfb557c4 RK |
153 | (define_function_unit "iu" 1 0 |
154 | (and (eq_attr "type" "idiv") | |
ca7f5001 | 155 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 156 | 19 19) |
cfb557c4 | 157 | |
3cb999d8 DE |
158 | (define_function_unit "iu" 1 0 |
159 | (and (eq_attr "type" "idiv") | |
160 | (eq_attr "cpu" "rs64a")) | |
161 | 66 66) | |
162 | ||
163 | (define_function_unit "iu" 1 0 | |
164 | (and (eq_attr "type" "ldiv") | |
165 | (eq_attr "cpu" "rs64a")) | |
166 | 66 66) | |
167 | ||
cfb557c4 RK |
168 | (define_function_unit "iu" 1 0 |
169 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
170 | (eq_attr "cpu" "ppc403")) |
171 | 33 33) | |
51b8fc2c | 172 | |
da0ae67f MM |
173 | (define_function_unit "iu" 1 0 |
174 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
175 | (eq_attr "cpu" "ppc601")) |
176 | 36 36) | |
da0ae67f | 177 | |
51b8fc2c RK |
178 | (define_function_unit "iu" 1 0 |
179 | (and (eq_attr "type" "idiv") | |
b7ff3d82 | 180 | (eq_attr "cpu" "ppc603")) |
51b8fc2c RK |
181 | 37 36) |
182 | ||
183 | ; RIOS2 has two integer units: a primary one which can perform all | |
184 | ; operations and a secondary one which is fed in lock step with the first | |
b6c9286a MM |
185 | ; and can perform "simple" integer operations. |
186 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
187 | ; for the complex insns. | |
51b8fc2c RK |
188 | (define_function_unit "iu2" 2 0 |
189 | (and (eq_attr "type" "integer") | |
190 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 191 | 1 1) |
b6c9286a MM |
192 | |
193 | (define_function_unit "iu2" 2 0 | |
194 | (and (eq_attr "type" "imul") | |
195 | (eq_attr "cpu" "rios2")) | |
196 | 2 2) | |
197 | ||
198 | (define_function_unit "iu2" 2 0 | |
199 | (and (eq_attr "type" "idiv") | |
200 | (eq_attr "cpu" "rios2")) | |
201 | 13 13) | |
51b8fc2c RK |
202 | |
203 | (define_function_unit "imuldiv" 1 0 | |
204 | (and (eq_attr "type" "imul") | |
205 | (eq_attr "cpu" "rios2")) | |
b6c9286a MM |
206 | 2 2) |
207 | ||
51b8fc2c RK |
208 | (define_function_unit "imuldiv" 1 0 |
209 | (and (eq_attr "type" "idiv") | |
210 | (eq_attr "cpu" "rios2")) | |
b6c9286a | 211 | 13 13) |
51b8fc2c | 212 | |
cf27b467 MM |
213 | ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions |
214 | ; Divide latency varies greatly from 2-11, use 6 as average | |
215 | (define_function_unit "imuldiv" 1 0 | |
216 | (and (eq_attr "type" "imul") | |
217 | (eq_attr "cpu" "mpccore")) | |
218 | 2 1) | |
219 | ||
220 | (define_function_unit "imuldiv" 1 0 | |
221 | (and (eq_attr "type" "idiv") | |
222 | (eq_attr "cpu" "mpccore")) | |
223 | 6 6) | |
224 | ||
cac8ce95 | 225 | ; PPC604{,e} has two units that perform integer operations |
b6c9286a MM |
226 | ; and one unit for divide/multiply operations (and move |
227 | ; from/to spr). | |
228 | (define_function_unit "iu2" 2 0 | |
51b8fc2c | 229 | (and (eq_attr "type" "integer") |
3cb999d8 | 230 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 231 | 1 1) |
51b8fc2c RK |
232 | |
233 | (define_function_unit "imuldiv" 1 0 | |
234 | (and (eq_attr "type" "imul") | |
3cb999d8 | 235 | (eq_attr "cpu" "ppc604")) |
b7ff3d82 | 236 | 4 2) |
51b8fc2c | 237 | |
3cb999d8 DE |
238 | (define_function_unit "imuldiv" 1 0 |
239 | (and (eq_attr "type" "imul") | |
240 | (eq_attr "cpu" "ppc620,ppc630")) | |
241 | 5 3) | |
242 | ||
243 | (define_function_unit "imuldiv" 1 0 | |
244 | (and (eq_attr "type" "lmul") | |
245 | (eq_attr "cpu" "ppc620,ppc630")) | |
246 | 5 3) | |
247 | ||
cac8ce95 DE |
248 | (define_function_unit "imuldiv" 1 0 |
249 | (and (eq_attr "type" "imul") | |
250 | (eq_attr "cpu" "ppc604e")) | |
251 | 2 1) | |
252 | ||
51b8fc2c RK |
253 | (define_function_unit "imuldiv" 1 0 |
254 | (and (eq_attr "type" "idiv") | |
3cb999d8 | 255 | (eq_attr "cpu" "ppc604,ppc604e")) |
b7ff3d82 | 256 | 20 19) |
cfb557c4 | 257 | |
3cb999d8 DE |
258 | (define_function_unit "imuldiv" 1 0 |
259 | (and (eq_attr "type" "idiv") | |
260 | (eq_attr "cpu" "ppc620")) | |
261 | 37 36) | |
262 | ||
263 | (define_function_unit "imuldiv" 1 0 | |
264 | (and (eq_attr "type" "idiv") | |
265 | (eq_attr "cpu" "ppc630")) | |
266 | 21 20) | |
267 | ||
268 | (define_function_unit "imuldiv" 1 0 | |
269 | (and (eq_attr "type" "ldiv") | |
270 | (eq_attr "cpu" "ppc620,ppc630")) | |
271 | 37 36) | |
272 | ||
bef84347 VM |
273 | ; PPC750 has two integer units: a primary one which can perform all |
274 | ; operations and a secondary one which is fed in lock step with the first | |
275 | ; and can perform "simple" integer operations. | |
276 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
277 | ; for the complex insns. | |
278 | (define_function_unit "iu2" 2 0 | |
279 | (and (eq_attr "type" "integer") | |
280 | (eq_attr "cpu" "ppc750")) | |
281 | 1 1) | |
282 | ||
283 | (define_function_unit "iu2" 2 0 | |
284 | (and (eq_attr "type" "imul") | |
285 | (eq_attr "cpu" "ppc750")) | |
286 | 4 2) | |
287 | ||
288 | (define_function_unit "imuldiv" 1 0 | |
289 | (and (eq_attr "type" "imul") | |
290 | (eq_attr "cpu" "ppc750")) | |
291 | 4 2) | |
292 | ||
293 | (define_function_unit "imuldiv" 1 0 | |
294 | (and (eq_attr "type" "idiv") | |
295 | (eq_attr "cpu" "ppc750")) | |
296 | 19 19) | |
297 | ||
39a10a29 GK |
298 | ; CR-logical operations are execute-serialized, that is they don't |
299 | ; start (and block the function unit) until all preceding operations | |
300 | ; have finished. They don't block dispatch of other insns, though. | |
301 | ; I've imitated this by giving them longer latency. | |
302 | (define_function_unit "sru" 1 0 | |
303 | (and (eq_attr "type" "cr_logical") | |
304 | (eq_attr "cpu" "ppc603,ppc750")) | |
305 | 3 2) | |
306 | ||
b6c9286a | 307 | ; compare is done on integer unit, but feeds insns which |
acc5239d | 308 | ; execute on the branch unit. |
b6c9286a MM |
309 | (define_function_unit "iu" 1 0 |
310 | (and (eq_attr "type" "compare") | |
b7ff3d82 DE |
311 | (eq_attr "cpu" "rios1")) |
312 | 4 1) | |
313 | ||
314 | (define_function_unit "iu" 1 0 | |
315 | (and (eq_attr "type" "delayed_compare") | |
316 | (eq_attr "cpu" "rios1")) | |
317 | 5 1) | |
318 | ||
319 | (define_function_unit "iu" 1 0 | |
320 | (and (eq_attr "type" "compare,delayed_compare") | |
3cb999d8 | 321 | (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b7ff3d82 | 322 | 3 1) |
b6c9286a MM |
323 | |
324 | (define_function_unit "iu2" 2 0 | |
b7ff3d82 | 325 | (and (eq_attr "type" "compare,delayed_compare") |
b6c9286a | 326 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 327 | 3 1) |
b6c9286a | 328 | |
b6c9286a | 329 | (define_function_unit "iu2" 2 0 |
b7ff3d82 | 330 | (and (eq_attr "type" "compare,delayed_compare") |
3cb999d8 | 331 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b6c9286a | 332 | 1 1) |
cfb557c4 | 333 | |
b6c9286a MM |
334 | ; fp compare uses fp unit |
335 | (define_function_unit "fpu" 1 0 | |
cfb557c4 | 336 | (and (eq_attr "type" "fpcompare") |
b6c9286a | 337 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 338 | 9 1) |
cfb557c4 | 339 | |
b6c9286a MM |
340 | ; rios1 and rios2 have different fpcompare delays |
341 | (define_function_unit "fpu2" 2 0 | |
cfb557c4 | 342 | (and (eq_attr "type" "fpcompare") |
3cb999d8 | 343 | (eq_attr "cpu" "rios2,ppc630")) |
b6c9286a MM |
344 | 5 1) |
345 | ||
346 | ; on ppc601 and ppc603, fpcompare takes also 2 cycles from | |
347 | ; the integer unit | |
348 | ; here we do not define delays, just occupy the unit. The dependencies | |
b7ff3d82 | 349 | ; will be assigned by the fpcompare definition in the fpu. |
b6c9286a MM |
350 | (define_function_unit "iu" 1 0 |
351 | (and (eq_attr "type" "fpcompare") | |
b7ff3d82 | 352 | (eq_attr "cpu" "ppc601,ppc603")) |
b6c9286a MM |
353 | 0 2) |
354 | ||
355 | ; fp compare uses fp unit | |
356 | (define_function_unit "fpu" 1 0 | |
357 | (and (eq_attr "type" "fpcompare") | |
5638268e | 358 | (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b6c9286a | 359 | 5 1) |
cfb557c4 | 360 | |
cf27b467 MM |
361 | (define_function_unit "fpu" 1 0 |
362 | (and (eq_attr "type" "fpcompare") | |
363 | (eq_attr "cpu" "mpccore")) | |
364 | 1 1) | |
365 | ||
cfb557c4 | 366 | (define_function_unit "bpu" 1 0 |
324e52cc | 367 | (and (eq_attr "type" "mtjmpr") |
3cb999d8 | 368 | (eq_attr "cpu" "rios1,rios2,rs64a")) |
b7ff3d82 | 369 | 5 1) |
cfb557c4 RK |
370 | |
371 | (define_function_unit "bpu" 1 0 | |
324e52cc | 372 | (and (eq_attr "type" "mtjmpr") |
5638268e | 373 | (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b7ff3d82 | 374 | 4 1) |
cfb557c4 | 375 | |
39a10a29 GK |
376 | (define_function_unit "bpu" 1 0 |
377 | (and (eq_attr "type" "cr_logical") | |
5638268e | 378 | (eq_attr "cpu" "rios1,rios2,ppc604")) |
39a10a29 GK |
379 | 4 1) |
380 | ||
381 | (define_function_unit "cru" 1 0 | |
382 | (and (eq_attr "type" "cr_logical") | |
5638268e DE |
383 | (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a")) |
384 | 1 1) | |
39a10a29 | 385 | |
b6c9286a MM |
386 | ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines. |
387 | (define_function_unit "bpu" 1 0 | |
388 | (eq_attr "type" "jmpreg") | |
b7ff3d82 | 389 | 1 1) |
b6c9286a MM |
390 | |
391 | (define_function_unit "bpu" 1 0 | |
392 | (eq_attr "type" "branch") | |
b7ff3d82 | 393 | 1 1) |
b6c9286a | 394 | |
cf27b467 | 395 | ; Floating Point Unit |
cfb557c4 | 396 | (define_function_unit "fpu" 1 0 |
51b8fc2c | 397 | (and (eq_attr "type" "fp,dmul") |
2661cdd9 | 398 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 399 | 2 1) |
cfb557c4 | 400 | |
cf27b467 MM |
401 | (define_function_unit "fpu" 1 0 |
402 | (and (eq_attr "type" "fp") | |
3cb999d8 DE |
403 | (eq_attr "cpu" "rs64a,mpccore")) |
404 | 4 2) | |
cf27b467 | 405 | |
cfb557c4 RK |
406 | (define_function_unit "fpu" 1 0 |
407 | (and (eq_attr "type" "fp") | |
51b8fc2c | 408 | (eq_attr "cpu" "ppc601")) |
b7ff3d82 | 409 | 4 1) |
cfb557c4 | 410 | |
51b8fc2c RK |
411 | (define_function_unit "fpu" 1 0 |
412 | (and (eq_attr "type" "fp") | |
3cb999d8 | 413 | (eq_attr "cpu" "ppc603,ppc750,ppc604,ppc604e,ppc620")) |
b6c9286a | 414 | 3 1) |
51b8fc2c | 415 | |
3cb999d8 DE |
416 | (define_function_unit "fpu" 1 0 |
417 | (and (eq_attr "type" "dmul") | |
418 | (eq_attr "cpu" "rs64a")) | |
419 | 7 2) | |
420 | ||
cf27b467 MM |
421 | (define_function_unit "fpu" 1 0 |
422 | (and (eq_attr "type" "dmul") | |
423 | (eq_attr "cpu" "mpccore")) | |
424 | 5 5) | |
425 | ||
cfb557c4 RK |
426 | (define_function_unit "fpu" 1 0 |
427 | (and (eq_attr "type" "dmul") | |
51b8fc2c | 428 | (eq_attr "cpu" "ppc601")) |
b6c9286a | 429 | 5 2) |
cfb557c4 | 430 | |
b6c9286a | 431 | ; is this true? |
cfb557c4 RK |
432 | (define_function_unit "fpu" 1 0 |
433 | (and (eq_attr "type" "dmul") | |
bef84347 | 434 | (eq_attr "cpu" "ppc603,ppc750")) |
51b8fc2c | 435 | 4 2) |
cfb557c4 RK |
436 | |
437 | (define_function_unit "fpu" 1 0 | |
51b8fc2c | 438 | (and (eq_attr "type" "dmul") |
cac8ce95 | 439 | (eq_attr "cpu" "ppc604,ppc604e,ppc620")) |
b6c9286a | 440 | 3 1) |
51b8fc2c RK |
441 | |
442 | (define_function_unit "fpu" 1 0 | |
443 | (and (eq_attr "type" "sdiv,ddiv") | |
2661cdd9 | 444 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 445 | 19 19) |
cfb557c4 | 446 | |
3cb999d8 DE |
447 | (define_function_unit "fpu" 1 0 |
448 | (and (eq_attr "type" "sdiv") | |
449 | (eq_attr "cpu" "rs64a")) | |
450 | 31 31) | |
451 | ||
cfb557c4 RK |
452 | (define_function_unit "fpu" 1 0 |
453 | (and (eq_attr "type" "sdiv") | |
51b8fc2c RK |
454 | (eq_attr "cpu" "ppc601")) |
455 | 17 17) | |
456 | ||
cf27b467 MM |
457 | (define_function_unit "fpu" 1 0 |
458 | (and (eq_attr "type" "sdiv") | |
459 | (eq_attr "cpu" "mpccore")) | |
460 | 10 10) | |
461 | ||
51b8fc2c RK |
462 | (define_function_unit "fpu" 1 0 |
463 | (and (eq_attr "type" "sdiv") | |
cac8ce95 | 464 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620")) |
51b8fc2c | 465 | 18 18) |
cfb557c4 | 466 | |
cf27b467 MM |
467 | (define_function_unit "fpu" 1 0 |
468 | (and (eq_attr "type" "ddiv") | |
469 | (eq_attr "cpu" "mpccore")) | |
470 | 17 17) | |
471 | ||
cfb557c4 RK |
472 | (define_function_unit "fpu" 1 0 |
473 | (and (eq_attr "type" "ddiv") | |
3cb999d8 | 474 | (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620")) |
51b8fc2c | 475 | 31 31) |
cfb557c4 RK |
476 | |
477 | (define_function_unit "fpu" 1 0 | |
478 | (and (eq_attr "type" "ddiv") | |
b7ff3d82 | 479 | (eq_attr "cpu" "ppc603")) |
51b8fc2c | 480 | 33 33) |
cfb557c4 RK |
481 | |
482 | (define_function_unit "fpu" 1 0 | |
483 | (and (eq_attr "type" "ssqrt") | |
a473029f | 484 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 485 | 31 31) |
cfb557c4 RK |
486 | |
487 | (define_function_unit "fpu" 1 0 | |
488 | (and (eq_attr "type" "dsqrt") | |
a473029f | 489 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 490 | 31 31) |
b73d04f2 | 491 | |
51b8fc2c | 492 | ; RIOS2 has two symmetric FPUs. |
cfb557c4 RK |
493 | (define_function_unit "fpu2" 2 0 |
494 | (and (eq_attr "type" "fp") | |
4652f1d4 | 495 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 496 | 2 1) |
cfb557c4 | 497 | |
3cb999d8 DE |
498 | (define_function_unit "fpu2" 2 0 |
499 | (and (eq_attr "type" "fp") | |
500 | (eq_attr "cpu" "ppc630")) | |
501 | 3 1) | |
502 | ||
cfb557c4 RK |
503 | (define_function_unit "fpu2" 2 0 |
504 | (and (eq_attr "type" "dmul") | |
505 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 506 | 2 1) |
cfb557c4 | 507 | |
3cb999d8 DE |
508 | (define_function_unit "fpu2" 2 0 |
509 | (and (eq_attr "type" "dmul") | |
510 | (eq_attr "cpu" "ppc630")) | |
511 | 3 1) | |
512 | ||
cfb557c4 | 513 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 514 | (and (eq_attr "type" "sdiv,ddiv") |
cfb557c4 | 515 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 516 | 17 17) |
ca7f5001 | 517 | |
3cb999d8 DE |
518 | (define_function_unit "fpu2" 2 0 |
519 | (and (eq_attr "type" "sdiv") | |
520 | (eq_attr "cpu" "ppc630")) | |
521 | 17 17) | |
522 | ||
523 | (define_function_unit "fpu2" 2 0 | |
524 | (and (eq_attr "type" "ddiv") | |
525 | (eq_attr "cpu" "ppc630")) | |
526 | 21 21) | |
527 | ||
ca7f5001 | 528 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 529 | (and (eq_attr "type" "ssqrt,dsqrt") |
ca7f5001 | 530 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 531 | 26 26) |
b6c9286a | 532 | |
3cb999d8 DE |
533 | (define_function_unit "fpu2" 2 0 |
534 | (and (eq_attr "type" "ssqrt") | |
535 | (eq_attr "cpu" "ppc630")) | |
536 | 18 18) | |
537 | ||
538 | (define_function_unit "fpu2" 2 0 | |
539 | (and (eq_attr "type" "dsqrt") | |
540 | (eq_attr "cpu" "ppc630")) | |
541 | 26 26) | |
542 | ||
1fd4e8c1 RK |
543 | \f |
544 | ;; Start with fixed-point load and store insns. Here we put only the more | |
545 | ;; complex forms. Basic data transfer is done later. | |
546 | ||
51b8fc2c RK |
547 | (define_expand "zero_extendqidi2" |
548 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
549 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
550 | "TARGET_POWERPC64" | |
551 | "") | |
552 | ||
553 | (define_insn "" | |
554 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
555 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
556 | "TARGET_POWERPC64" | |
557 | "@ | |
558 | lbz%U1%X1 %0,%1 | |
4371f8af | 559 | rldicl %0,%1,0,56" |
51b8fc2c RK |
560 | [(set_attr "type" "load,*")]) |
561 | ||
562 | (define_insn "" | |
9ebbca7d GK |
563 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
564 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 565 | (const_int 0))) |
9ebbca7d | 566 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 567 | "TARGET_POWERPC64" |
9ebbca7d GK |
568 | "@ |
569 | rldicl. %2,%1,0,56 | |
570 | #" | |
571 | [(set_attr "type" "compare") | |
572 | (set_attr "length" "4,8")]) | |
573 | ||
574 | (define_split | |
575 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
576 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
577 | (const_int 0))) | |
578 | (clobber (match_scratch:DI 2 ""))] | |
579 | "TARGET_POWERPC64 && reload_completed" | |
580 | [(set (match_dup 2) | |
581 | (zero_extend:DI (match_dup 1))) | |
582 | (set (match_dup 0) | |
583 | (compare:CC (match_dup 2) | |
584 | (const_int 0)))] | |
585 | "") | |
51b8fc2c RK |
586 | |
587 | (define_insn "" | |
9ebbca7d GK |
588 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
589 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 590 | (const_int 0))) |
9ebbca7d | 591 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 592 | (zero_extend:DI (match_dup 1)))] |
58e09803 | 593 | "TARGET_POWERPC64" |
9ebbca7d GK |
594 | "@ |
595 | rldicl. %0,%1,0,56 | |
596 | #" | |
597 | [(set_attr "type" "compare") | |
598 | (set_attr "length" "4,8")]) | |
599 | ||
600 | (define_split | |
601 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
602 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
603 | (const_int 0))) | |
604 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
605 | (zero_extend:DI (match_dup 1)))] | |
606 | "TARGET_POWERPC64 && reload_completed" | |
607 | [(set (match_dup 0) | |
608 | (zero_extend:DI (match_dup 1))) | |
609 | (set (match_dup 2) | |
610 | (compare:CC (match_dup 0) | |
611 | (const_int 0)))] | |
612 | "") | |
51b8fc2c | 613 | |
2bee0449 RK |
614 | (define_insn "extendqidi2" |
615 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
616 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 617 | "TARGET_POWERPC64" |
2bee0449 | 618 | "extsb %0,%1") |
51b8fc2c RK |
619 | |
620 | (define_insn "" | |
9ebbca7d GK |
621 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
622 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 623 | (const_int 0))) |
9ebbca7d | 624 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 625 | "TARGET_POWERPC64" |
9ebbca7d GK |
626 | "@ |
627 | extsb. %2,%1 | |
628 | #" | |
629 | [(set_attr "type" "compare") | |
630 | (set_attr "length" "4,8")]) | |
631 | ||
632 | (define_split | |
633 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
634 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
635 | (const_int 0))) | |
636 | (clobber (match_scratch:DI 2 ""))] | |
637 | "TARGET_POWERPC64 && reload_completed" | |
638 | [(set (match_dup 2) | |
639 | (sign_extend:DI (match_dup 1))) | |
640 | (set (match_dup 0) | |
641 | (compare:CC (match_dup 2) | |
642 | (const_int 0)))] | |
643 | "") | |
51b8fc2c RK |
644 | |
645 | (define_insn "" | |
9ebbca7d GK |
646 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
647 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 648 | (const_int 0))) |
9ebbca7d | 649 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
650 | (sign_extend:DI (match_dup 1)))] |
651 | "TARGET_POWERPC64" | |
9ebbca7d GK |
652 | "@ |
653 | extsb. %0,%1 | |
654 | #" | |
655 | [(set_attr "type" "compare") | |
656 | (set_attr "length" "4,8")]) | |
657 | ||
658 | (define_split | |
659 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
660 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
661 | (const_int 0))) | |
662 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
663 | (sign_extend:DI (match_dup 1)))] | |
664 | "TARGET_POWERPC64 && reload_completed" | |
665 | [(set (match_dup 0) | |
666 | (sign_extend:DI (match_dup 1))) | |
667 | (set (match_dup 2) | |
668 | (compare:CC (match_dup 0) | |
669 | (const_int 0)))] | |
670 | "") | |
51b8fc2c RK |
671 | |
672 | (define_expand "zero_extendhidi2" | |
673 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
674 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
675 | "TARGET_POWERPC64" | |
676 | "") | |
677 | ||
678 | (define_insn "" | |
679 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
680 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
681 | "TARGET_POWERPC64" | |
682 | "@ | |
683 | lhz%U1%X1 %0,%1 | |
4371f8af | 684 | rldicl %0,%1,0,48" |
51b8fc2c RK |
685 | [(set_attr "type" "load,*")]) |
686 | ||
687 | (define_insn "" | |
9ebbca7d GK |
688 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
689 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 690 | (const_int 0))) |
9ebbca7d | 691 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 692 | "TARGET_POWERPC64" |
9ebbca7d GK |
693 | "@ |
694 | rldicl. %2,%1,0,48 | |
695 | #" | |
696 | [(set_attr "type" "compare") | |
697 | (set_attr "length" "4,8")]) | |
698 | ||
699 | (define_split | |
700 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
701 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
702 | (const_int 0))) | |
703 | (clobber (match_scratch:DI 2 ""))] | |
704 | "TARGET_POWERPC64 && reload_completed" | |
705 | [(set (match_dup 2) | |
706 | (zero_extend:DI (match_dup 1))) | |
707 | (set (match_dup 0) | |
708 | (compare:CC (match_dup 2) | |
709 | (const_int 0)))] | |
710 | "") | |
51b8fc2c RK |
711 | |
712 | (define_insn "" | |
9ebbca7d GK |
713 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
714 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 715 | (const_int 0))) |
9ebbca7d | 716 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
717 | (zero_extend:DI (match_dup 1)))] |
718 | "TARGET_POWERPC64" | |
9ebbca7d GK |
719 | "@ |
720 | rldicl. %0,%1,0,48 | |
721 | #" | |
722 | [(set_attr "type" "compare") | |
723 | (set_attr "length" "4,8")]) | |
724 | ||
725 | (define_split | |
726 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
727 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
728 | (const_int 0))) | |
729 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
730 | (zero_extend:DI (match_dup 1)))] | |
731 | "TARGET_POWERPC64 && reload_completed" | |
732 | [(set (match_dup 0) | |
733 | (zero_extend:DI (match_dup 1))) | |
734 | (set (match_dup 2) | |
735 | (compare:CC (match_dup 0) | |
736 | (const_int 0)))] | |
737 | "") | |
51b8fc2c RK |
738 | |
739 | (define_expand "extendhidi2" | |
740 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
741 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
742 | "TARGET_POWERPC64" | |
743 | "") | |
744 | ||
745 | (define_insn "" | |
746 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
747 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
748 | "TARGET_POWERPC64" | |
749 | "@ | |
750 | lha%U1%X1 %0,%1 | |
751 | extsh %0,%1" | |
752 | [(set_attr "type" "load,*")]) | |
753 | ||
754 | (define_insn "" | |
9ebbca7d GK |
755 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
756 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 757 | (const_int 0))) |
9ebbca7d | 758 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 759 | "TARGET_POWERPC64" |
9ebbca7d GK |
760 | "@ |
761 | extsh. %2,%1 | |
762 | #" | |
763 | [(set_attr "type" "compare") | |
764 | (set_attr "length" "4,8")]) | |
765 | ||
766 | (define_split | |
767 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
768 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
769 | (const_int 0))) | |
770 | (clobber (match_scratch:DI 2 ""))] | |
771 | "TARGET_POWERPC64 && reload_completed" | |
772 | [(set (match_dup 2) | |
773 | (sign_extend:DI (match_dup 1))) | |
774 | (set (match_dup 0) | |
775 | (compare:CC (match_dup 2) | |
776 | (const_int 0)))] | |
777 | "") | |
51b8fc2c RK |
778 | |
779 | (define_insn "" | |
9ebbca7d GK |
780 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
781 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 782 | (const_int 0))) |
9ebbca7d | 783 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
784 | (sign_extend:DI (match_dup 1)))] |
785 | "TARGET_POWERPC64" | |
9ebbca7d GK |
786 | "@ |
787 | extsh. %0,%1 | |
788 | #" | |
789 | [(set_attr "type" "compare") | |
790 | (set_attr "length" "4,8")]) | |
791 | ||
792 | (define_split | |
793 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
794 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
795 | (const_int 0))) | |
796 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
797 | (sign_extend:DI (match_dup 1)))] | |
798 | "TARGET_POWERPC64 && reload_completed" | |
799 | [(set (match_dup 0) | |
800 | (sign_extend:DI (match_dup 1))) | |
801 | (set (match_dup 2) | |
802 | (compare:CC (match_dup 0) | |
803 | (const_int 0)))] | |
804 | "") | |
51b8fc2c RK |
805 | |
806 | (define_expand "zero_extendsidi2" | |
807 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
808 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
809 | "TARGET_POWERPC64" | |
810 | "") | |
811 | ||
812 | (define_insn "" | |
813 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
814 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
815 | "TARGET_POWERPC64" | |
816 | "@ | |
817 | lwz%U1%X1 %0,%1 | |
818 | rldicl %0,%1,0,32" | |
819 | [(set_attr "type" "load,*")]) | |
820 | ||
821 | (define_insn "" | |
9ebbca7d GK |
822 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
823 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 824 | (const_int 0))) |
9ebbca7d | 825 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 826 | "TARGET_POWERPC64" |
9ebbca7d GK |
827 | "@ |
828 | rldicl. %2,%1,0,32 | |
829 | #" | |
830 | [(set_attr "type" "compare") | |
831 | (set_attr "length" "4,8")]) | |
832 | ||
833 | (define_split | |
834 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
835 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
836 | (const_int 0))) | |
837 | (clobber (match_scratch:DI 2 ""))] | |
838 | "TARGET_POWERPC64 && reload_completed" | |
839 | [(set (match_dup 2) | |
840 | (zero_extend:DI (match_dup 1))) | |
841 | (set (match_dup 0) | |
842 | (compare:CC (match_dup 2) | |
843 | (const_int 0)))] | |
844 | "") | |
51b8fc2c RK |
845 | |
846 | (define_insn "" | |
9ebbca7d GK |
847 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
848 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 849 | (const_int 0))) |
9ebbca7d | 850 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
851 | (zero_extend:DI (match_dup 1)))] |
852 | "TARGET_POWERPC64" | |
9ebbca7d GK |
853 | "@ |
854 | rldicl. %0,%1,0,32 | |
855 | #" | |
856 | [(set_attr "type" "compare") | |
857 | (set_attr "length" "4,8")]) | |
858 | ||
859 | (define_split | |
860 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
861 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
862 | (const_int 0))) | |
863 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
864 | (zero_extend:DI (match_dup 1)))] | |
865 | "TARGET_POWERPC64 && reload_completed" | |
866 | [(set (match_dup 0) | |
867 | (zero_extend:DI (match_dup 1))) | |
868 | (set (match_dup 2) | |
869 | (compare:CC (match_dup 0) | |
870 | (const_int 0)))] | |
871 | "") | |
51b8fc2c RK |
872 | |
873 | (define_expand "extendsidi2" | |
874 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
875 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
876 | "TARGET_POWERPC64" | |
877 | "") | |
878 | ||
879 | (define_insn "" | |
880 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 881 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
882 | "TARGET_POWERPC64" |
883 | "@ | |
884 | lwa%U1%X1 %0,%1 | |
885 | extsw %0,%1" | |
886 | [(set_attr "type" "load,*")]) | |
887 | ||
888 | (define_insn "" | |
9ebbca7d GK |
889 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
890 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 891 | (const_int 0))) |
9ebbca7d | 892 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 893 | "TARGET_POWERPC64" |
9ebbca7d GK |
894 | "@ |
895 | extsw. %2,%1 | |
896 | #" | |
897 | [(set_attr "type" "compare") | |
898 | (set_attr "length" "4,8")]) | |
899 | ||
900 | (define_split | |
901 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
902 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
903 | (const_int 0))) | |
904 | (clobber (match_scratch:DI 2 ""))] | |
905 | "TARGET_POWERPC64 && reload_completed" | |
906 | [(set (match_dup 2) | |
907 | (sign_extend:DI (match_dup 1))) | |
908 | (set (match_dup 0) | |
909 | (compare:CC (match_dup 2) | |
910 | (const_int 0)))] | |
911 | "") | |
51b8fc2c RK |
912 | |
913 | (define_insn "" | |
9ebbca7d GK |
914 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
915 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 916 | (const_int 0))) |
9ebbca7d | 917 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
918 | (sign_extend:DI (match_dup 1)))] |
919 | "TARGET_POWERPC64" | |
9ebbca7d GK |
920 | "@ |
921 | extsw. %0,%1 | |
922 | #" | |
923 | [(set_attr "type" "compare") | |
924 | (set_attr "length" "4,8")]) | |
925 | ||
926 | (define_split | |
927 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
928 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
929 | (const_int 0))) | |
930 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
931 | (sign_extend:DI (match_dup 1)))] | |
932 | "TARGET_POWERPC64 && reload_completed" | |
933 | [(set (match_dup 0) | |
934 | (sign_extend:DI (match_dup 1))) | |
935 | (set (match_dup 2) | |
936 | (compare:CC (match_dup 0) | |
937 | (const_int 0)))] | |
938 | "") | |
51b8fc2c | 939 | |
1fd4e8c1 | 940 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
941 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
942 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
943 | "" |
944 | "") | |
945 | ||
946 | (define_insn "" | |
cd2b37d9 | 947 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
948 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
949 | "" | |
950 | "@ | |
951 | lbz%U1%X1 %0,%1 | |
005a35b9 | 952 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
953 | [(set_attr "type" "load,*")]) |
954 | ||
955 | (define_insn "" | |
9ebbca7d GK |
956 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
957 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 958 | (const_int 0))) |
9ebbca7d | 959 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 960 | "" |
9ebbca7d GK |
961 | "@ |
962 | {andil.|andi.} %2,%1,0xff | |
963 | #" | |
964 | [(set_attr "type" "compare") | |
965 | (set_attr "length" "4,8")]) | |
966 | ||
967 | (define_split | |
968 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
969 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
970 | (const_int 0))) | |
971 | (clobber (match_scratch:SI 2 ""))] | |
972 | "reload_completed" | |
973 | [(set (match_dup 2) | |
974 | (zero_extend:SI (match_dup 1))) | |
975 | (set (match_dup 0) | |
976 | (compare:CC (match_dup 2) | |
977 | (const_int 0)))] | |
978 | "") | |
1fd4e8c1 RK |
979 | |
980 | (define_insn "" | |
9ebbca7d GK |
981 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
982 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 983 | (const_int 0))) |
9ebbca7d | 984 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
985 | (zero_extend:SI (match_dup 1)))] |
986 | "" | |
9ebbca7d GK |
987 | "@ |
988 | {andil.|andi.} %0,%1,0xff | |
989 | #" | |
990 | [(set_attr "type" "compare") | |
991 | (set_attr "length" "4,8")]) | |
992 | ||
993 | (define_split | |
994 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
995 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
996 | (const_int 0))) | |
997 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
998 | (zero_extend:SI (match_dup 1)))] | |
999 | "reload_completed" | |
1000 | [(set (match_dup 0) | |
1001 | (zero_extend:SI (match_dup 1))) | |
1002 | (set (match_dup 2) | |
1003 | (compare:CC (match_dup 0) | |
1004 | (const_int 0)))] | |
1005 | "") | |
1fd4e8c1 | 1006 | |
51b8fc2c RK |
1007 | (define_expand "extendqisi2" |
1008 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1009 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
1010 | "" | |
1011 | " | |
1012 | { | |
1013 | if (TARGET_POWERPC) | |
1014 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
1015 | else if (TARGET_POWER) | |
1016 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
1017 | else | |
1018 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
1019 | DONE; | |
1020 | }") | |
1021 | ||
1022 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
1023 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1024 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 1025 | "TARGET_POWERPC" |
2bee0449 | 1026 | "extsb %0,%1") |
51b8fc2c RK |
1027 | |
1028 | (define_insn "" | |
9ebbca7d GK |
1029 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1030 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1031 | (const_int 0))) |
9ebbca7d | 1032 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 1033 | "TARGET_POWERPC" |
9ebbca7d GK |
1034 | "@ |
1035 | extsb. %2,%1 | |
1036 | #" | |
1037 | [(set_attr "type" "compare") | |
1038 | (set_attr "length" "4,8")]) | |
1039 | ||
1040 | (define_split | |
1041 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1042 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1043 | (const_int 0))) | |
1044 | (clobber (match_scratch:SI 2 ""))] | |
1045 | "TARGET_POWERPC && reload_completed" | |
1046 | [(set (match_dup 2) | |
1047 | (sign_extend:SI (match_dup 1))) | |
1048 | (set (match_dup 0) | |
1049 | (compare:CC (match_dup 2) | |
1050 | (const_int 0)))] | |
1051 | "") | |
51b8fc2c RK |
1052 | |
1053 | (define_insn "" | |
9ebbca7d GK |
1054 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1055 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1056 | (const_int 0))) |
9ebbca7d | 1057 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1058 | (sign_extend:SI (match_dup 1)))] |
1059 | "TARGET_POWERPC" | |
9ebbca7d GK |
1060 | "@ |
1061 | extsb. %0,%1 | |
1062 | #" | |
1063 | [(set_attr "type" "compare") | |
1064 | (set_attr "length" "4,8")]) | |
1065 | ||
1066 | (define_split | |
1067 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1068 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1069 | (const_int 0))) | |
1070 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1071 | (sign_extend:SI (match_dup 1)))] | |
1072 | "TARGET_POWERPC && reload_completed" | |
1073 | [(set (match_dup 0) | |
1074 | (sign_extend:SI (match_dup 1))) | |
1075 | (set (match_dup 2) | |
1076 | (compare:CC (match_dup 0) | |
1077 | (const_int 0)))] | |
1078 | "") | |
51b8fc2c RK |
1079 | |
1080 | (define_expand "extendqisi2_power" | |
1081 | [(parallel [(set (match_dup 2) | |
1082 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1083 | (const_int 24))) | |
1084 | (clobber (scratch:SI))]) | |
1085 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1086 | (ashiftrt:SI (match_dup 2) | |
1087 | (const_int 24))) | |
1088 | (clobber (scratch:SI))])] | |
1089 | "TARGET_POWER" | |
1090 | " | |
1091 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1092 | operands[2] = gen_reg_rtx (SImode); }") | |
1093 | ||
1094 | (define_expand "extendqisi2_no_power" | |
1095 | [(set (match_dup 2) | |
1096 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1097 | (const_int 24))) | |
1098 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1099 | (ashiftrt:SI (match_dup 2) | |
1100 | (const_int 24)))] | |
1101 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1102 | " | |
1103 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1104 | operands[2] = gen_reg_rtx (SImode); }") | |
1105 | ||
1fd4e8c1 | 1106 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
1107 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
1108 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1109 | "" |
1110 | "") | |
1111 | ||
1112 | (define_insn "" | |
cd2b37d9 | 1113 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1114 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
1115 | "" | |
1116 | "@ | |
1117 | lbz%U1%X1 %0,%1 | |
005a35b9 | 1118 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
1119 | [(set_attr "type" "load,*")]) |
1120 | ||
1121 | (define_insn "" | |
9ebbca7d GK |
1122 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1123 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1124 | (const_int 0))) |
9ebbca7d | 1125 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 1126 | "" |
9ebbca7d GK |
1127 | "@ |
1128 | {andil.|andi.} %2,%1,0xff | |
1129 | #" | |
1130 | [(set_attr "type" "compare") | |
1131 | (set_attr "length" "4,8")]) | |
1132 | ||
1133 | (define_split | |
1134 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1135 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1136 | (const_int 0))) | |
1137 | (clobber (match_scratch:HI 2 ""))] | |
1138 | "reload_completed" | |
1139 | [(set (match_dup 2) | |
1140 | (zero_extend:HI (match_dup 1))) | |
1141 | (set (match_dup 0) | |
1142 | (compare:CC (match_dup 2) | |
1143 | (const_int 0)))] | |
1144 | "") | |
1fd4e8c1 | 1145 | |
51b8fc2c | 1146 | (define_insn "" |
9ebbca7d GK |
1147 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1148 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1149 | (const_int 0))) |
9ebbca7d | 1150 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
1151 | (zero_extend:HI (match_dup 1)))] |
1152 | "" | |
9ebbca7d GK |
1153 | "@ |
1154 | {andil.|andi.} %0,%1,0xff | |
1155 | #" | |
1156 | [(set_attr "type" "compare") | |
1157 | (set_attr "length" "4,8")]) | |
1158 | ||
1159 | (define_split | |
1160 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1161 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1162 | (const_int 0))) | |
1163 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1164 | (zero_extend:HI (match_dup 1)))] | |
1165 | "reload_completed" | |
1166 | [(set (match_dup 0) | |
1167 | (zero_extend:HI (match_dup 1))) | |
1168 | (set (match_dup 2) | |
1169 | (compare:CC (match_dup 0) | |
1170 | (const_int 0)))] | |
1171 | "") | |
815cdc52 MM |
1172 | |
1173 | (define_expand "extendqihi2" | |
1174 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
1175 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
1176 | "" | |
1177 | " | |
1178 | { | |
1179 | if (TARGET_POWERPC) | |
1180 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
1181 | else if (TARGET_POWER) | |
1182 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
1183 | else | |
1184 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
1185 | DONE; | |
1186 | }") | |
1187 | ||
1188 | (define_insn "extendqihi2_ppc" | |
1189 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
1190 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
1191 | "TARGET_POWERPC" | |
1192 | "extsb %0,%1") | |
1193 | ||
1194 | (define_insn "" | |
9ebbca7d GK |
1195 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1196 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1197 | (const_int 0))) |
9ebbca7d | 1198 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 1199 | "TARGET_POWERPC" |
9ebbca7d GK |
1200 | "@ |
1201 | extsb. %2,%1 | |
1202 | #" | |
1203 | [(set_attr "type" "compare") | |
1204 | (set_attr "length" "4,8")]) | |
1205 | ||
1206 | (define_split | |
1207 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1208 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1209 | (const_int 0))) | |
1210 | (clobber (match_scratch:HI 2 ""))] | |
1211 | "TARGET_POWERPC && reload_completed" | |
1212 | [(set (match_dup 2) | |
1213 | (sign_extend:HI (match_dup 1))) | |
1214 | (set (match_dup 0) | |
1215 | (compare:CC (match_dup 2) | |
1216 | (const_int 0)))] | |
1217 | "") | |
815cdc52 MM |
1218 | |
1219 | (define_insn "" | |
9ebbca7d GK |
1220 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1221 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1222 | (const_int 0))) |
9ebbca7d | 1223 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1224 | (sign_extend:HI (match_dup 1)))] |
1225 | "TARGET_POWERPC" | |
9ebbca7d GK |
1226 | "@ |
1227 | extsb. %0,%1 | |
1228 | #" | |
1229 | [(set_attr "type" "compare") | |
1230 | (set_attr "length" "4,8")]) | |
1231 | ||
1232 | (define_split | |
1233 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1234 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1235 | (const_int 0))) | |
1236 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1237 | (sign_extend:HI (match_dup 1)))] | |
1238 | "TARGET_POWERPC && reload_completed" | |
1239 | [(set (match_dup 0) | |
1240 | (sign_extend:HI (match_dup 1))) | |
1241 | (set (match_dup 2) | |
1242 | (compare:CC (match_dup 0) | |
1243 | (const_int 0)))] | |
1244 | "") | |
51b8fc2c RK |
1245 | |
1246 | (define_expand "extendqihi2_power" | |
1247 | [(parallel [(set (match_dup 2) | |
1248 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1249 | (const_int 24))) | |
1250 | (clobber (scratch:SI))]) | |
1251 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
1252 | (ashiftrt:SI (match_dup 2) | |
1253 | (const_int 24))) | |
1254 | (clobber (scratch:SI))])] | |
1255 | "TARGET_POWER" | |
1256 | " | |
1257 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1258 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1259 | operands[2] = gen_reg_rtx (SImode); }") | |
1260 | ||
1261 | (define_expand "extendqihi2_no_power" | |
1262 | [(set (match_dup 2) | |
1263 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1264 | (const_int 24))) | |
1265 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1266 | (ashiftrt:SI (match_dup 2) | |
1267 | (const_int 24)))] | |
1268 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1269 | " | |
1270 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1271 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1272 | operands[2] = gen_reg_rtx (SImode); }") | |
1273 | ||
1fd4e8c1 | 1274 | (define_expand "zero_extendhisi2" |
5f243543 | 1275 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 1276 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
1277 | "" |
1278 | "") | |
1279 | ||
1280 | (define_insn "" | |
cd2b37d9 | 1281 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1282 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1283 | "" | |
1284 | "@ | |
1285 | lhz%U1%X1 %0,%1 | |
005a35b9 | 1286 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
1287 | [(set_attr "type" "load,*")]) |
1288 | ||
1289 | (define_insn "" | |
9ebbca7d GK |
1290 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1291 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1292 | (const_int 0))) |
9ebbca7d | 1293 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1294 | "" |
9ebbca7d GK |
1295 | "@ |
1296 | {andil.|andi.} %2,%1,0xffff | |
1297 | #" | |
1298 | [(set_attr "type" "compare") | |
1299 | (set_attr "length" "4,8")]) | |
1300 | ||
1301 | (define_split | |
1302 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1303 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1304 | (const_int 0))) | |
1305 | (clobber (match_scratch:SI 2 ""))] | |
1306 | "reload_completed" | |
1307 | [(set (match_dup 2) | |
1308 | (zero_extend:SI (match_dup 1))) | |
1309 | (set (match_dup 0) | |
1310 | (compare:CC (match_dup 2) | |
1311 | (const_int 0)))] | |
1312 | "") | |
1fd4e8c1 RK |
1313 | |
1314 | (define_insn "" | |
9ebbca7d GK |
1315 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1316 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1317 | (const_int 0))) |
9ebbca7d | 1318 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1319 | (zero_extend:SI (match_dup 1)))] |
1320 | "" | |
9ebbca7d GK |
1321 | "@ |
1322 | {andil.|andi.} %0,%1,0xffff | |
1323 | #" | |
1324 | [(set_attr "type" "compare") | |
1325 | (set_attr "length" "4,8")]) | |
1326 | ||
1327 | (define_split | |
1328 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1329 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1330 | (const_int 0))) | |
1331 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1332 | (zero_extend:SI (match_dup 1)))] | |
1333 | "reload_completed" | |
1334 | [(set (match_dup 0) | |
1335 | (zero_extend:SI (match_dup 1))) | |
1336 | (set (match_dup 2) | |
1337 | (compare:CC (match_dup 0) | |
1338 | (const_int 0)))] | |
1339 | "") | |
1fd4e8c1 RK |
1340 | |
1341 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
1342 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1343 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1344 | "" |
1345 | "") | |
1346 | ||
1347 | (define_insn "" | |
cd2b37d9 | 1348 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1349 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1350 | "" | |
1351 | "@ | |
1352 | lha%U1%X1 %0,%1 | |
ca7f5001 | 1353 | {exts|extsh} %0,%1" |
1fd4e8c1 RK |
1354 | [(set_attr "type" "load,*")]) |
1355 | ||
1356 | (define_insn "" | |
9ebbca7d GK |
1357 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1358 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1359 | (const_int 0))) |
9ebbca7d | 1360 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1361 | "" |
9ebbca7d GK |
1362 | "@ |
1363 | {exts.|extsh.} %2,%1 | |
1364 | #" | |
1365 | [(set_attr "type" "compare") | |
1366 | (set_attr "length" "4,8")]) | |
1367 | ||
1368 | (define_split | |
1369 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1370 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1371 | (const_int 0))) | |
1372 | (clobber (match_scratch:SI 2 ""))] | |
1373 | "reload_completed" | |
1374 | [(set (match_dup 2) | |
1375 | (sign_extend:SI (match_dup 1))) | |
1376 | (set (match_dup 0) | |
1377 | (compare:CC (match_dup 2) | |
1378 | (const_int 0)))] | |
1379 | "") | |
1fd4e8c1 RK |
1380 | |
1381 | (define_insn "" | |
9ebbca7d GK |
1382 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1383 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1384 | (const_int 0))) |
9ebbca7d | 1385 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1386 | (sign_extend:SI (match_dup 1)))] |
1387 | "" | |
9ebbca7d GK |
1388 | "@ |
1389 | {exts.|extsh.} %0,%1 | |
1390 | #" | |
1391 | [(set_attr "type" "compare") | |
1392 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1393 | \f |
9ebbca7d GK |
1394 | (define_split |
1395 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1396 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1397 | (const_int 0))) | |
1398 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1399 | (sign_extend:SI (match_dup 1)))] | |
1400 | "reload_completed" | |
1401 | [(set (match_dup 0) | |
1402 | (sign_extend:SI (match_dup 1))) | |
1403 | (set (match_dup 2) | |
1404 | (compare:CC (match_dup 0) | |
1405 | (const_int 0)))] | |
1406 | "") | |
1407 | ||
1fd4e8c1 | 1408 | ;; Fixed-point arithmetic insns. |
deb9225a RK |
1409 | |
1410 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
1411 | ;; allowing register zero as source. | |
7cd5235b MM |
1412 | (define_expand "addsi3" |
1413 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1414 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 1415 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
7cd5235b MM |
1416 | "" |
1417 | " | |
1418 | { | |
677a9668 DE |
1419 | if (GET_CODE (operands[2]) == CONST_INT |
1420 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 1421 | { |
677a9668 | 1422 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
1423 | ? operands[0] : gen_reg_rtx (SImode)); |
1424 | ||
1425 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; | |
1426 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
1427 | ||
1428 | if (low & 0x8000) | |
38886f37 AO |
1429 | { |
1430 | high = trunc_int_for_mode (high + 0x10000, SImode); | |
1431 | low = trunc_int_for_mode (low, HImode); | |
1432 | } | |
7cd5235b | 1433 | |
9ebbca7d GK |
1434 | /* The ordering here is important for the prolog expander. |
1435 | When space is allocated from the stack, adding 'low' first may | |
1436 | produce a temporary deallocation (which would be bad). */ | |
7cd5235b MM |
1437 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (high))); |
1438 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); | |
1439 | DONE; | |
1440 | } | |
1441 | }") | |
1442 | ||
1443 | (define_insn "*addsi3_internal1" | |
1444 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
1445 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 1446 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1447 | "" |
1448 | "@ | |
deb9225a RK |
1449 | {cax|add} %0,%1,%2 |
1450 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1451 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1452 | {cau|addis} %0,%1,%v2" |
1453 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1454 | |
ee890fe2 SS |
1455 | (define_insn "addsi3_high" |
1456 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1457 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1458 | (high:SI (match_operand 2 "" ""))))] | |
1459 | "TARGET_MACHO && !TARGET_64BIT" | |
1460 | "{cau|addis} %0,%1,ha16(%2)" | |
1461 | [(set_attr "length" "4")]) | |
1462 | ||
7cd5235b | 1463 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1464 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1465 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1466 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1467 | (const_int 0))) |
cb8cc086 | 1468 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
0ad91047 | 1469 | "! TARGET_POWERPC64" |
deb9225a RK |
1470 | "@ |
1471 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1472 | {ai.|addic.} %3,%1,%2 |
1473 | # | |
1474 | #" | |
1475 | [(set_attr "type" "compare") | |
1476 | (set_attr "length" "4,4,8,8")]) | |
1477 | ||
1478 | (define_split | |
1479 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1480 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1481 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1482 | (const_int 0))) | |
1483 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1484 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1485 | [(set (match_dup 3) |
1486 | (plus:SI (match_dup 1) | |
1487 | (match_dup 2))) | |
1488 | (set (match_dup 0) | |
1489 | (compare:CC (match_dup 3) | |
1490 | (const_int 0)))] | |
1491 | "") | |
7e69e155 | 1492 | |
7cd5235b | 1493 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1494 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1495 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1496 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1497 | (const_int 0))) |
cb8cc086 MM |
1498 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1499 | (plus:SI (match_dup 1) | |
1500 | (match_dup 2)))] | |
0ad91047 | 1501 | "! TARGET_POWERPC64" |
deb9225a RK |
1502 | "@ |
1503 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1504 | {ai.|addic.} %0,%1,%2 |
1505 | # | |
1506 | #" | |
1507 | [(set_attr "type" "compare") | |
1508 | (set_attr "length" "4,4,8,8")]) | |
1509 | ||
1510 | (define_split | |
1511 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1512 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1513 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1514 | (const_int 0))) | |
1515 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1516 | (plus:SI (match_dup 1) (match_dup 2)))] | |
0ad91047 | 1517 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1518 | [(set (match_dup 0) |
1519 | (plus:SI (match_dup 1) | |
1520 | (match_dup 2))) | |
1521 | (set (match_dup 3) | |
1522 | (compare:CC (match_dup 0) | |
1523 | (const_int 0)))] | |
1524 | "") | |
7e69e155 | 1525 | |
f357808b RK |
1526 | ;; Split an add that we can't do in one insn into two insns, each of which |
1527 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1528 | ;; add should be last in case the result gets used in an address. | |
1529 | ||
1530 | (define_split | |
cd2b37d9 RK |
1531 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1532 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1533 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1534 | "" |
f357808b RK |
1535 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1536 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1537 | " | |
1fd4e8c1 | 1538 | { |
e6ca2c17 DE |
1539 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; |
1540 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
1fd4e8c1 | 1541 | |
f357808b | 1542 | if (low & 0x8000) |
38886f37 AO |
1543 | { |
1544 | high = trunc_int_for_mode (high + 0x10000, SImode); | |
1545 | low = trunc_int_for_mode (low, HImode); | |
1546 | } | |
1fd4e8c1 | 1547 | |
e6ca2c17 DE |
1548 | operands[3] = GEN_INT (high); |
1549 | operands[4] = GEN_INT (low); | |
1fd4e8c1 RK |
1550 | }") |
1551 | ||
8de2a197 | 1552 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1553 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1554 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1555 | "" |
ca7f5001 RK |
1556 | "nor %0,%1,%1") |
1557 | ||
1558 | (define_insn "" | |
52d3af72 DE |
1559 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1560 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1561 | (const_int 0))) |
52d3af72 | 1562 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1563 | "! TARGET_POWERPC64" |
52d3af72 DE |
1564 | "@ |
1565 | nor. %2,%1,%1 | |
1566 | #" | |
1567 | [(set_attr "type" "compare") | |
1568 | (set_attr "length" "4,8")]) | |
1569 | ||
1570 | (define_split | |
1571 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1572 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1573 | (const_int 0))) | |
1574 | (clobber (match_scratch:SI 2 ""))] | |
0ad91047 | 1575 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1576 | [(set (match_dup 2) |
1577 | (not:SI (match_dup 1))) | |
1578 | (set (match_dup 0) | |
1579 | (compare:CC (match_dup 2) | |
1580 | (const_int 0)))] | |
1581 | "") | |
ca7f5001 RK |
1582 | |
1583 | (define_insn "" | |
52d3af72 DE |
1584 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1585 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1586 | (const_int 0))) |
52d3af72 | 1587 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1588 | (not:SI (match_dup 1)))] |
0ad91047 | 1589 | "! TARGET_POWERPC64" |
52d3af72 DE |
1590 | "@ |
1591 | nor. %0,%1,%1 | |
1592 | #" | |
1593 | [(set_attr "type" "compare") | |
1594 | (set_attr "length" "4,8")]) | |
1595 | ||
1596 | (define_split | |
1597 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1598 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1599 | (const_int 0))) | |
1600 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1601 | (not:SI (match_dup 1)))] | |
0ad91047 | 1602 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1603 | [(set (match_dup 0) |
1604 | (not:SI (match_dup 1))) | |
1605 | (set (match_dup 2) | |
1606 | (compare:CC (match_dup 0) | |
1607 | (const_int 0)))] | |
1608 | "") | |
1fd4e8c1 RK |
1609 | |
1610 | (define_insn "" | |
3d91674b RK |
1611 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1612 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1613 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1614 | "! TARGET_POWERPC" |
ca7f5001 | 1615 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1616 | |
deb9225a RK |
1617 | (define_insn "" |
1618 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1619 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1620 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1621 | "TARGET_POWERPC" | |
1622 | "@ | |
1623 | subf %0,%2,%1 | |
1624 | subfic %0,%2,%1") | |
1625 | ||
1fd4e8c1 | 1626 | (define_insn "" |
cb8cc086 MM |
1627 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1628 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1629 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1630 | (const_int 0))) |
cb8cc086 | 1631 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1632 | "! TARGET_POWERPC" |
cb8cc086 MM |
1633 | "@ |
1634 | {sf.|subfc.} %3,%2,%1 | |
1635 | #" | |
1636 | [(set_attr "type" "compare") | |
1637 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1638 | |
deb9225a | 1639 | (define_insn "" |
cb8cc086 MM |
1640 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1641 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1642 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1643 | (const_int 0))) |
cb8cc086 | 1644 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 1645 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
cb8cc086 MM |
1646 | "@ |
1647 | subf. %3,%2,%1 | |
1648 | #" | |
1649 | [(set_attr "type" "compare") | |
1650 | (set_attr "length" "4,8")]) | |
1651 | ||
1652 | (define_split | |
1653 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1654 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1655 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1656 | (const_int 0))) | |
1657 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1658 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1659 | [(set (match_dup 3) |
1660 | (minus:SI (match_dup 1) | |
1661 | (match_dup 2))) | |
1662 | (set (match_dup 0) | |
1663 | (compare:CC (match_dup 3) | |
1664 | (const_int 0)))] | |
1665 | "") | |
deb9225a | 1666 | |
1fd4e8c1 | 1667 | (define_insn "" |
cb8cc086 MM |
1668 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1669 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1670 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1671 | (const_int 0))) |
cb8cc086 | 1672 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1673 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1674 | "! TARGET_POWERPC" |
cb8cc086 MM |
1675 | "@ |
1676 | {sf.|subfc.} %0,%2,%1 | |
1677 | #" | |
1678 | [(set_attr "type" "compare") | |
1679 | (set_attr "length" "4,8")]) | |
815cdc52 | 1680 | |
29ae5b89 | 1681 | (define_insn "" |
cb8cc086 MM |
1682 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1683 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1684 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1685 | (const_int 0))) |
cb8cc086 MM |
1686 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1687 | (minus:SI (match_dup 1) | |
1688 | (match_dup 2)))] | |
0ad91047 | 1689 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
90612787 DE |
1690 | "@ |
1691 | subf. %0,%2,%1 | |
1692 | #" | |
cb8cc086 MM |
1693 | [(set_attr "type" "compare") |
1694 | (set_attr "length" "4,8")]) | |
1695 | ||
1696 | (define_split | |
1697 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1698 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1699 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1700 | (const_int 0))) | |
1701 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1702 | (minus:SI (match_dup 1) | |
1703 | (match_dup 2)))] | |
0ad91047 | 1704 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1705 | [(set (match_dup 0) |
1706 | (minus:SI (match_dup 1) | |
1707 | (match_dup 2))) | |
1708 | (set (match_dup 3) | |
1709 | (compare:CC (match_dup 0) | |
1710 | (const_int 0)))] | |
1711 | "") | |
deb9225a | 1712 | |
1fd4e8c1 | 1713 | (define_expand "subsi3" |
cd2b37d9 | 1714 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1715 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
f6bf7de2 | 1716 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
1fd4e8c1 | 1717 | "" |
a0044fb1 RK |
1718 | " |
1719 | { | |
1720 | if (GET_CODE (operands[2]) == CONST_INT) | |
1721 | { | |
1722 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1723 | negate_rtx (SImode, operands[2]))); | |
1724 | DONE; | |
1725 | } | |
1726 | }") | |
1fd4e8c1 RK |
1727 | |
1728 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1729 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1730 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1731 | ;; combine. | |
1fd4e8c1 RK |
1732 | |
1733 | (define_expand "sminsi3" | |
1734 | [(set (match_dup 3) | |
cd2b37d9 | 1735 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1736 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1737 | (const_int 0) | |
1738 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1739 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1740 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1741 | "TARGET_POWER" |
1fd4e8c1 RK |
1742 | " |
1743 | { operands[3] = gen_reg_rtx (SImode); }") | |
1744 | ||
95ac8e67 RK |
1745 | (define_split |
1746 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1747 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1748 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1749 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1750 | "TARGET_POWER" |
95ac8e67 RK |
1751 | [(set (match_dup 3) |
1752 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1753 | (const_int 0) | |
1754 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1755 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1756 | "") | |
1757 | ||
1fd4e8c1 RK |
1758 | (define_expand "smaxsi3" |
1759 | [(set (match_dup 3) | |
cd2b37d9 | 1760 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1761 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1762 | (const_int 0) | |
1763 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1764 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1765 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1766 | "TARGET_POWER" |
1fd4e8c1 RK |
1767 | " |
1768 | { operands[3] = gen_reg_rtx (SImode); }") | |
1769 | ||
95ac8e67 RK |
1770 | (define_split |
1771 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1772 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1773 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1774 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1775 | "TARGET_POWER" |
95ac8e67 RK |
1776 | [(set (match_dup 3) |
1777 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1778 | (const_int 0) | |
1779 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1780 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1781 | "") | |
1782 | ||
1fd4e8c1 | 1783 | (define_expand "uminsi3" |
cd2b37d9 | 1784 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1785 | (match_dup 5))) |
cd2b37d9 | 1786 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1787 | (match_dup 5))) |
1fd4e8c1 RK |
1788 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1789 | (const_int 0) | |
1790 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1791 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1792 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1793 | "TARGET_POWER" |
1fd4e8c1 | 1794 | " |
bb68ff55 MM |
1795 | { |
1796 | operands[3] = gen_reg_rtx (SImode); | |
1797 | operands[4] = gen_reg_rtx (SImode); | |
1798 | operands[5] = GEN_INT (-2147483647 - 1); | |
1799 | }") | |
1fd4e8c1 RK |
1800 | |
1801 | (define_expand "umaxsi3" | |
cd2b37d9 | 1802 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1803 | (match_dup 5))) |
cd2b37d9 | 1804 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1805 | (match_dup 5))) |
1fd4e8c1 RK |
1806 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1807 | (const_int 0) | |
1808 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1809 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1810 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1811 | "TARGET_POWER" |
1fd4e8c1 | 1812 | " |
bb68ff55 MM |
1813 | { |
1814 | operands[3] = gen_reg_rtx (SImode); | |
1815 | operands[4] = gen_reg_rtx (SImode); | |
1816 | operands[5] = GEN_INT (-2147483647 - 1); | |
1817 | }") | |
1fd4e8c1 RK |
1818 | |
1819 | (define_insn "" | |
cd2b37d9 RK |
1820 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1821 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1822 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1823 | (const_int 0) |
1824 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1825 | "TARGET_POWER" |
1fd4e8c1 RK |
1826 | "doz%I2 %0,%1,%2") |
1827 | ||
1828 | (define_insn "" | |
9ebbca7d | 1829 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1830 | (compare:CC |
9ebbca7d GK |
1831 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1832 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1833 | (const_int 0) |
1834 | (minus:SI (match_dup 2) (match_dup 1))) | |
1835 | (const_int 0))) | |
9ebbca7d | 1836 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 1837 | "TARGET_POWER" |
9ebbca7d GK |
1838 | "@ |
1839 | doz%I2. %3,%1,%2 | |
1840 | #" | |
1841 | [(set_attr "type" "delayed_compare") | |
1842 | (set_attr "length" "4,8")]) | |
1843 | ||
1844 | (define_split | |
1845 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1846 | (compare:CC | |
1847 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1848 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1849 | (const_int 0) | |
1850 | (minus:SI (match_dup 2) (match_dup 1))) | |
1851 | (const_int 0))) | |
1852 | (clobber (match_scratch:SI 3 ""))] | |
1853 | "TARGET_POWER && reload_completed" | |
1854 | [(set (match_dup 3) | |
1855 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1856 | (const_int 0) | |
1857 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1858 | (set (match_dup 0) | |
1859 | (compare:CC (match_dup 3) | |
1860 | (const_int 0)))] | |
1861 | "") | |
1fd4e8c1 RK |
1862 | |
1863 | (define_insn "" | |
9ebbca7d | 1864 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1865 | (compare:CC |
9ebbca7d GK |
1866 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1867 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1868 | (const_int 0) |
1869 | (minus:SI (match_dup 2) (match_dup 1))) | |
1870 | (const_int 0))) | |
9ebbca7d | 1871 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1872 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1873 | (const_int 0) | |
1874 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1875 | "TARGET_POWER" |
9ebbca7d GK |
1876 | "@ |
1877 | doz%I2. %0,%1,%2 | |
1878 | #" | |
1879 | [(set_attr "type" "delayed_compare") | |
1880 | (set_attr "length" "4,8")]) | |
1881 | ||
1882 | (define_split | |
1883 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1884 | (compare:CC | |
1885 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1886 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1887 | (const_int 0) | |
1888 | (minus:SI (match_dup 2) (match_dup 1))) | |
1889 | (const_int 0))) | |
1890 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1891 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1892 | (const_int 0) | |
1893 | (minus:SI (match_dup 2) (match_dup 1))))] | |
1894 | "TARGET_POWER && reload_completed" | |
1895 | [(set (match_dup 0) | |
1896 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1897 | (const_int 0) | |
1898 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1899 | (set (match_dup 3) | |
1900 | (compare:CC (match_dup 0) | |
1901 | (const_int 0)))] | |
1902 | "") | |
1fd4e8c1 RK |
1903 | |
1904 | ;; We don't need abs with condition code because such comparisons should | |
1905 | ;; never be done. | |
ea9be077 MM |
1906 | (define_expand "abssi2" |
1907 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1908 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1909 | "" | |
1910 | " | |
1911 | { | |
0ad91047 | 1912 | if (! TARGET_POWER) |
ea9be077 MM |
1913 | { |
1914 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1915 | DONE; | |
1916 | } | |
1917 | }") | |
1918 | ||
1919 | (define_insn "abssi2_power" | |
cd2b37d9 RK |
1920 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1921 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1922 | "TARGET_POWER" |
1fd4e8c1 RK |
1923 | "abs %0,%1") |
1924 | ||
ea9be077 MM |
1925 | (define_insn "abssi2_nopower" |
1926 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1927 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
1928 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1929 | "! TARGET_POWER" |
3595d104 MM |
1930 | "* |
1931 | { | |
1932 | return (TARGET_POWERPC) | |
1933 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\" | |
1934 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\"; | |
1935 | }" | |
ea9be077 MM |
1936 | [(set_attr "length" "12")]) |
1937 | ||
1938 | (define_split | |
1939 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1940 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
1941 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1942 | "! TARGET_POWER && reload_completed" |
ea9be077 MM |
1943 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1944 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1945 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1946 | "") |
1947 | ||
463b558b | 1948 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1949 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1950 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1951 | "TARGET_POWER" |
1fd4e8c1 RK |
1952 | "nabs %0,%1") |
1953 | ||
463b558b | 1954 | (define_insn "*nabs_no_power" |
ea9be077 MM |
1955 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
1956 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
1957 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1958 | "! TARGET_POWER" |
3595d104 MM |
1959 | "* |
1960 | { | |
1961 | return (TARGET_POWERPC) | |
1962 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\" | |
1963 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\"; | |
1964 | }" | |
ea9be077 MM |
1965 | [(set_attr "length" "12")]) |
1966 | ||
1967 | (define_split | |
1968 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1969 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
1970 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1971 | "! TARGET_POWER && reload_completed" |
ea9be077 MM |
1972 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1973 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1974 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1975 | "") |
1976 | ||
1fd4e8c1 | 1977 | (define_insn "negsi2" |
cd2b37d9 RK |
1978 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1979 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1980 | "" |
1981 | "neg %0,%1") | |
1982 | ||
1983 | (define_insn "" | |
9ebbca7d GK |
1984 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1985 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1986 | (const_int 0))) |
9ebbca7d | 1987 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1988 | "! TARGET_POWERPC64" |
9ebbca7d GK |
1989 | "@ |
1990 | neg. %2,%1 | |
1991 | #" | |
1992 | [(set_attr "type" "compare") | |
1993 | (set_attr "length" "4,8")]) | |
1994 | ||
1995 | (define_split | |
1996 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1997 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1998 | (const_int 0))) | |
1999 | (clobber (match_scratch:SI 2 ""))] | |
2000 | "! TARGET_POWERPC64 && reload_completed" | |
2001 | [(set (match_dup 2) | |
2002 | (neg:SI (match_dup 1))) | |
2003 | (set (match_dup 0) | |
2004 | (compare:CC (match_dup 2) | |
2005 | (const_int 0)))] | |
2006 | "") | |
1fd4e8c1 RK |
2007 | |
2008 | (define_insn "" | |
9ebbca7d GK |
2009 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
2010 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2011 | (const_int 0))) |
9ebbca7d | 2012 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 2013 | (neg:SI (match_dup 1)))] |
0ad91047 | 2014 | "! TARGET_POWERPC64" |
9ebbca7d GK |
2015 | "@ |
2016 | neg. %0,%1 | |
2017 | #" | |
2018 | [(set_attr "type" "compare") | |
2019 | (set_attr "length" "4,8")]) | |
2020 | ||
2021 | (define_split | |
2022 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
2023 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2024 | (const_int 0))) | |
2025 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2026 | (neg:SI (match_dup 1)))] | |
2027 | "! TARGET_POWERPC64 && reload_completed" | |
2028 | [(set (match_dup 0) | |
2029 | (neg:SI (match_dup 1))) | |
2030 | (set (match_dup 2) | |
2031 | (compare:CC (match_dup 0) | |
2032 | (const_int 0)))] | |
2033 | "") | |
1fd4e8c1 RK |
2034 | |
2035 | (define_insn "ffssi2" | |
242e8072 RK |
2036 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
2037 | (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 2038 | "" |
7f340546 | 2039 | "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" |
b19003d8 | 2040 | [(set_attr "length" "16")]) |
1fd4e8c1 | 2041 | |
ca7f5001 RK |
2042 | (define_expand "mulsi3" |
2043 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
2044 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
2045 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
2046 | "" | |
2047 | " | |
2048 | { | |
2049 | if (TARGET_POWER) | |
68b40e7e | 2050 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 2051 | else |
68b40e7e | 2052 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
2053 | DONE; |
2054 | }") | |
2055 | ||
68b40e7e | 2056 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
2057 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2058 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
2059 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
2060 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
2061 | "TARGET_POWER" |
2062 | "@ | |
2063 | {muls|mullw} %0,%1,%2 | |
2064 | {muli|mulli} %0,%1,%2" | |
2065 | [(set_attr "type" "imul")]) | |
2066 | ||
68b40e7e | 2067 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
2068 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2069 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2070 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 2071 | "! TARGET_POWER" |
1fd4e8c1 | 2072 | "@ |
d904e9ed RK |
2073 | {muls|mullw} %0,%1,%2 |
2074 | {muli|mulli} %0,%1,%2" | |
cfb557c4 | 2075 | [(set_attr "type" "imul")]) |
1fd4e8c1 RK |
2076 | |
2077 | (define_insn "" | |
9ebbca7d GK |
2078 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2079 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2080 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2081 | (const_int 0))) |
9ebbca7d GK |
2082 | (clobber (match_scratch:SI 3 "=r,r")) |
2083 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 2084 | "TARGET_POWER" |
9ebbca7d GK |
2085 | "@ |
2086 | {muls.|mullw.} %3,%1,%2 | |
2087 | #" | |
2088 | [(set_attr "type" "delayed_compare") | |
2089 | (set_attr "length" "4,8")]) | |
2090 | ||
2091 | (define_split | |
2092 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2093 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2094 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2095 | (const_int 0))) | |
2096 | (clobber (match_scratch:SI 3 "")) | |
2097 | (clobber (match_scratch:SI 4 ""))] | |
2098 | "TARGET_POWER && reload_completed" | |
2099 | [(parallel [(set (match_dup 3) | |
2100 | (mult:SI (match_dup 1) (match_dup 2))) | |
2101 | (clobber (match_dup 4))]) | |
2102 | (set (match_dup 0) | |
2103 | (compare:CC (match_dup 3) | |
2104 | (const_int 0)))] | |
2105 | "") | |
ca7f5001 RK |
2106 | |
2107 | (define_insn "" | |
9ebbca7d GK |
2108 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2109 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2110 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2111 | (const_int 0))) |
9ebbca7d | 2112 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 2113 | "! TARGET_POWER" |
9ebbca7d GK |
2114 | "@ |
2115 | {muls.|mullw.} %3,%1,%2 | |
2116 | #" | |
2117 | [(set_attr "type" "delayed_compare") | |
2118 | (set_attr "length" "4,8")]) | |
2119 | ||
2120 | (define_split | |
2121 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2122 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2123 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2124 | (const_int 0))) | |
2125 | (clobber (match_scratch:SI 3 ""))] | |
2126 | "! TARGET_POWER && reload_completed" | |
2127 | [(set (match_dup 3) | |
2128 | (mult:SI (match_dup 1) (match_dup 2))) | |
2129 | (set (match_dup 0) | |
2130 | (compare:CC (match_dup 3) | |
2131 | (const_int 0)))] | |
2132 | "") | |
1fd4e8c1 RK |
2133 | |
2134 | (define_insn "" | |
9ebbca7d GK |
2135 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2136 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2137 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2138 | (const_int 0))) |
9ebbca7d | 2139 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2140 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 2141 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 2142 | "TARGET_POWER" |
9ebbca7d GK |
2143 | "@ |
2144 | {muls.|mullw.} %0,%1,%2 | |
2145 | #" | |
2146 | [(set_attr "type" "delayed_compare") | |
2147 | (set_attr "length" "4,8")]) | |
2148 | ||
2149 | (define_split | |
2150 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2151 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2152 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2153 | (const_int 0))) | |
2154 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2155 | (mult:SI (match_dup 1) (match_dup 2))) | |
2156 | (clobber (match_scratch:SI 4 ""))] | |
2157 | "TARGET_POWER && reload_completed" | |
2158 | [(parallel [(set (match_dup 0) | |
2159 | (mult:SI (match_dup 1) (match_dup 2))) | |
2160 | (clobber (match_dup 4))]) | |
2161 | (set (match_dup 3) | |
2162 | (compare:CC (match_dup 0) | |
2163 | (const_int 0)))] | |
2164 | "") | |
ca7f5001 RK |
2165 | |
2166 | (define_insn "" | |
9ebbca7d GK |
2167 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2168 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2169 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2170 | (const_int 0))) |
9ebbca7d | 2171 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 2172 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 2173 | "! TARGET_POWER" |
9ebbca7d GK |
2174 | "@ |
2175 | {muls.|mullw.} %0,%1,%2 | |
2176 | #" | |
2177 | [(set_attr "type" "delayed_compare") | |
2178 | (set_attr "length" "4,8")]) | |
2179 | ||
2180 | (define_split | |
2181 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2182 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2183 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2184 | (const_int 0))) | |
2185 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2186 | (mult:SI (match_dup 1) (match_dup 2)))] | |
2187 | "! TARGET_POWER && reload_completed" | |
2188 | [(set (match_dup 0) | |
2189 | (mult:SI (match_dup 1) (match_dup 2))) | |
2190 | (set (match_dup 3) | |
2191 | (compare:CC (match_dup 0) | |
2192 | (const_int 0)))] | |
2193 | "") | |
1fd4e8c1 RK |
2194 | |
2195 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
2196 | ;; 0 and remainder to operand 3. | |
2197 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
2198 | ||
8ffd9c51 RK |
2199 | (define_expand "divmodsi4" |
2200 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2201 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2202 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2203 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
2204 | (mod:SI (match_dup 1) (match_dup 2)))])] | |
2205 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2206 | " | |
2207 | { | |
2208 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2209 | { | |
39403d82 DE |
2210 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2211 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2212 | emit_insn (gen_divss_call ()); |
39403d82 DE |
2213 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2214 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
2215 | DONE; |
2216 | } | |
2217 | }") | |
deb9225a | 2218 | |
fada905b | 2219 | (define_insn "" |
cd2b37d9 RK |
2220 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2221 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2222 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2223 | (set (match_operand:SI 3 "gpc_reg_operand" "=q") | |
1fd4e8c1 | 2224 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 2225 | "TARGET_POWER" |
cfb557c4 RK |
2226 | "divs %0,%1,%2" |
2227 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 2228 | |
8ffd9c51 RK |
2229 | (define_expand "udivsi3" |
2230 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2231 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2232 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
2233 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2234 | " | |
2235 | { | |
2236 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2237 | { | |
39403d82 DE |
2238 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2239 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2240 | emit_insn (gen_quous_call ()); |
39403d82 | 2241 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2242 | DONE; |
2243 | } | |
f192bf8b DE |
2244 | else if (TARGET_POWER) |
2245 | { | |
2246 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
2247 | DONE; | |
2248 | } | |
8ffd9c51 | 2249 | }") |
deb9225a | 2250 | |
f192bf8b DE |
2251 | (define_insn "udivsi3_mq" |
2252 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2253 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2254 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2255 | (clobber (match_scratch:SI 3 "=q"))] | |
2256 | "TARGET_POWERPC && TARGET_POWER" | |
2257 | "divwu %0,%1,%2" | |
2258 | [(set_attr "type" "idiv")]) | |
2259 | ||
2260 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
2261 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2262 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2263 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 2264 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 2265 | "divwu %0,%1,%2" |
ca7f5001 RK |
2266 | [(set_attr "type" "idiv")]) |
2267 | ||
1fd4e8c1 | 2268 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 2269 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
2270 | ;; used; for PowerPC, force operands into register and do a normal divide; |
2271 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 2272 | (define_expand "divsi3" |
cd2b37d9 RK |
2273 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2274 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
2275 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
2276 | "" | |
2277 | " | |
2278 | { | |
ca7f5001 RK |
2279 | if (GET_CODE (operands[2]) == CONST_INT |
2280 | && exact_log2 (INTVAL (operands[2])) >= 0) | |
2281 | ; | |
b6c9286a | 2282 | else if (TARGET_POWERPC) |
f192bf8b DE |
2283 | { |
2284 | operands[2] = force_reg (SImode, operands[2]); | |
2285 | if (TARGET_POWER) | |
2286 | { | |
2287 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
2288 | DONE; | |
2289 | } | |
2290 | } | |
b6c9286a | 2291 | else if (TARGET_POWER) |
1fd4e8c1 | 2292 | FAIL; |
405c5495 | 2293 | else |
8ffd9c51 | 2294 | { |
39403d82 DE |
2295 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2296 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2297 | emit_insn (gen_quoss_call ()); |
39403d82 | 2298 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2299 | DONE; |
2300 | } | |
1fd4e8c1 RK |
2301 | }") |
2302 | ||
f192bf8b DE |
2303 | (define_insn "divsi3_mq" |
2304 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2305 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2306 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2307 | (clobber (match_scratch:SI 3 "=q"))] | |
2308 | "TARGET_POWERPC && TARGET_POWER" | |
2309 | "divw %0,%1,%2" | |
2310 | [(set_attr "type" "idiv")]) | |
2311 | ||
2312 | (define_insn "*divsi3_no_mq" | |
2313 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2314 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2315 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
2316 | "TARGET_POWERPC && ! TARGET_POWER" | |
2317 | "divw %0,%1,%2" | |
2318 | [(set_attr "type" "idiv")]) | |
2319 | ||
1fd4e8c1 | 2320 | (define_expand "modsi3" |
85644414 RK |
2321 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
2322 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 2323 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 2324 | "" |
1fd4e8c1 RK |
2325 | " |
2326 | { | |
481c7efa | 2327 | int i; |
39b52ba2 RK |
2328 | rtx temp1; |
2329 | rtx temp2; | |
2330 | ||
481c7efa FS |
2331 | if (GET_CODE (operands[2]) != CONST_INT) |
2332 | FAIL; | |
2333 | ||
2334 | i = exact_log2 (INTVAL (operands[2])); | |
2335 | ||
2336 | if (i < 0) | |
39b52ba2 RK |
2337 | FAIL; |
2338 | ||
2339 | temp1 = gen_reg_rtx (SImode); | |
2340 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 2341 | |
85644414 | 2342 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 2343 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
2344 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
2345 | DONE; | |
1fd4e8c1 RK |
2346 | }") |
2347 | ||
2348 | (define_insn "" | |
cd2b37d9 RK |
2349 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2350 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2351 | (match_operand:SI 2 "const_int_operand" "N")))] |
2352 | "exact_log2 (INTVAL (operands[2])) >= 0" | |
ca7f5001 | 2353 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 2354 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
2355 | |
2356 | (define_insn "" | |
9ebbca7d GK |
2357 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2358 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2359 | (match_operand:SI 2 "const_int_operand" "N,N")) | |
b6b12107 | 2360 | (const_int 0))) |
9ebbca7d | 2361 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 2362 | "exact_log2 (INTVAL (operands[2])) >= 0" |
9ebbca7d GK |
2363 | "@ |
2364 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
2365 | #" | |
b19003d8 | 2366 | [(set_attr "type" "compare") |
9ebbca7d GK |
2367 | (set_attr "length" "8,12")]) |
2368 | ||
2369 | (define_split | |
2370 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2371 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2372 | (match_operand:SI 2 "const_int_operand" "")) | |
2373 | (const_int 0))) | |
2374 | (clobber (match_scratch:SI 3 ""))] | |
2375 | "exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed" | |
2376 | [(set (match_dup 3) | |
2377 | (div:SI (match_dup 1) (match_dup 2))) | |
2378 | (set (match_dup 0) | |
2379 | (compare:CC (match_dup 3) | |
2380 | (const_int 0)))] | |
2381 | "") | |
1fd4e8c1 RK |
2382 | |
2383 | (define_insn "" | |
9ebbca7d GK |
2384 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2385 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2386 | (match_operand:SI 2 "const_int_operand" "N,N")) | |
b6b12107 | 2387 | (const_int 0))) |
9ebbca7d | 2388 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2389 | (div:SI (match_dup 1) (match_dup 2)))] |
1fd4e8c1 | 2390 | "exact_log2 (INTVAL (operands[2])) >= 0" |
9ebbca7d GK |
2391 | "@ |
2392 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2393 | #" | |
b19003d8 | 2394 | [(set_attr "type" "compare") |
9ebbca7d GK |
2395 | (set_attr "length" "8,12")]) |
2396 | ||
2397 | (define_split | |
2398 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2399 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2400 | (match_operand:SI 2 "const_int_operand" "")) | |
2401 | (const_int 0))) | |
2402 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2403 | (div:SI (match_dup 1) (match_dup 2)))] | |
2404 | "exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed" | |
2405 | [(set (match_dup 0) | |
2406 | (div:SI (match_dup 1) (match_dup 2))) | |
2407 | (set (match_dup 3) | |
2408 | (compare:CC (match_dup 0) | |
2409 | (const_int 0)))] | |
2410 | "") | |
1fd4e8c1 RK |
2411 | |
2412 | (define_insn "" | |
cd2b37d9 | 2413 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2414 | (udiv:SI |
996a5f59 | 2415 | (plus:DI (ashift:DI |
cd2b37d9 | 2416 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2417 | (const_int 32)) |
23a900dc | 2418 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2419 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2420 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2421 | (umod:SI |
996a5f59 | 2422 | (plus:DI (ashift:DI |
1fd4e8c1 | 2423 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2424 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2425 | (match_dup 3)))] |
ca7f5001 | 2426 | "TARGET_POWER" |
cfb557c4 RK |
2427 | "div %0,%1,%3" |
2428 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2429 | |
2430 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2431 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2432 | ;; have to worry about the branches. So make a few subroutines here. | |
2433 | ;; | |
2434 | ;; First comes the normal case. | |
2435 | (define_expand "udivmodsi4_normal" | |
2436 | [(set (match_dup 4) (const_int 0)) | |
2437 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2438 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2439 | (const_int 32)) |
2440 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2441 | (match_operand:SI 2 "" ""))) | |
2442 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2443 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2444 | (const_int 32)) |
2445 | (zero_extend:DI (match_dup 1))) | |
2446 | (match_dup 2)))])] | |
ca7f5001 | 2447 | "TARGET_POWER" |
1fd4e8c1 RK |
2448 | " |
2449 | { operands[4] = gen_reg_rtx (SImode); }") | |
2450 | ||
2451 | ;; This handles the branches. | |
2452 | (define_expand "udivmodsi4_tests" | |
2453 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2454 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2455 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2456 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2457 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2458 | (set (match_dup 0) (const_int 1)) | |
2459 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2460 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2461 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2462 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2463 | "TARGET_POWER" |
1fd4e8c1 RK |
2464 | " |
2465 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2466 | operands[6] = gen_reg_rtx (CCmode); | |
2467 | }") | |
2468 | ||
2469 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2470 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2471 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2472 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2473 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2474 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2475 | "" |
1fd4e8c1 RK |
2476 | " |
2477 | { | |
2478 | rtx label = 0; | |
2479 | ||
8ffd9c51 | 2480 | if (! TARGET_POWER) |
c4d38ccb MM |
2481 | { |
2482 | if (! TARGET_POWERPC) | |
2483 | { | |
39403d82 DE |
2484 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2485 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2486 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2487 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2488 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2489 | DONE; |
2490 | } | |
2491 | else | |
2492 | FAIL; | |
2493 | } | |
0081a354 | 2494 | |
1fd4e8c1 RK |
2495 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2496 | { | |
2497 | operands[2] = force_reg (SImode, operands[2]); | |
2498 | label = gen_label_rtx (); | |
2499 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2500 | operands[3], label)); | |
2501 | } | |
2502 | else | |
2503 | operands[2] = force_reg (SImode, operands[2]); | |
2504 | ||
2505 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2506 | operands[3])); | |
2507 | if (label) | |
2508 | emit_label (label); | |
2509 | ||
2510 | DONE; | |
2511 | }") | |
0081a354 | 2512 | |
fada905b MM |
2513 | ;; AIX architecture-independent common-mode multiply (DImode), |
2514 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2515 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2516 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2517 | ;; assumed unused if generating common-mode, so ignore. | |
2518 | (define_insn "mulh_call" | |
2519 | [(set (reg:SI 3) | |
2520 | (truncate:SI | |
2521 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2522 | (sign_extend:DI (reg:SI 4))) | |
2523 | (const_int 32)))) | |
cf27b467 | 2524 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2525 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2526 | "bla __mulh" |
2527 | [(set_attr "type" "imul")]) | |
fada905b MM |
2528 | |
2529 | (define_insn "mull_call" | |
2530 | [(set (reg:DI 3) | |
2531 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2532 | (sign_extend:DI (reg:SI 4)))) | |
2533 | (clobber (match_scratch:SI 0 "=l")) | |
2534 | (clobber (reg:SI 0))] | |
2535 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2536 | "bla __mull" |
2537 | [(set_attr "type" "imul")]) | |
fada905b MM |
2538 | |
2539 | (define_insn "divss_call" | |
2540 | [(set (reg:SI 3) | |
2541 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2542 | (set (reg:SI 4) | |
2543 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2544 | (clobber (match_scratch:SI 0 "=l")) | |
2545 | (clobber (reg:SI 0))] | |
2546 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2547 | "bla __divss" |
2548 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2549 | |
2550 | (define_insn "divus_call" | |
8ffd9c51 RK |
2551 | [(set (reg:SI 3) |
2552 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2553 | (set (reg:SI 4) | |
2554 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2555 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2556 | (clobber (reg:SI 0)) |
2557 | (clobber (match_scratch:CC 1 "=x")) | |
2558 | (clobber (reg:CC 69))] | |
2559 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2560 | "bla __divus" |
2561 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2562 | |
2563 | (define_insn "quoss_call" | |
2564 | [(set (reg:SI 3) | |
2565 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2566 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2567 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2568 | "bla __quoss" |
2569 | [(set_attr "type" "idiv")]) | |
0081a354 | 2570 | |
fada905b MM |
2571 | (define_insn "quous_call" |
2572 | [(set (reg:SI 3) | |
2573 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2574 | (clobber (match_scratch:SI 0 "=l")) | |
2575 | (clobber (reg:SI 0)) | |
2576 | (clobber (match_scratch:CC 1 "=x")) | |
2577 | (clobber (reg:CC 69))] | |
2578 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2579 | "bla __quous" |
2580 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2581 | \f |
bb21487f | 2582 | ;; Logical instructions |
dfbdccdb GK |
2583 | ;; The logical instructions are mostly combined by using match_operator, |
2584 | ;; but the plain AND insns are somewhat different because there is no | |
2585 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2586 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2587 | ||
29ae5b89 JL |
2588 | (define_insn "andsi3" |
2589 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2590 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2591 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2592 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2593 | "" |
2594 | "@ | |
2595 | and %0,%1,%2 | |
ca7f5001 RK |
2596 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2597 | {andil.|andi.} %0,%1,%b2 | |
9ebbca7d | 2598 | {andiu.|andis.} %0,%1,%u2") |
52d3af72 DE |
2599 | |
2600 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
2601 | ;; the test again -- this avoids a mcrf which on the higher end | |
2602 | ;; machines causes an execution serialization | |
1fd4e8c1 | 2603 | |
7cd5235b | 2604 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2605 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2606 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2607 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2608 | (const_int 0))) |
52d3af72 DE |
2609 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2610 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2611 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2612 | "@ |
2613 | and. %3,%1,%2 | |
ca7f5001 RK |
2614 | {andil.|andi.} %3,%1,%b2 |
2615 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2616 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2617 | # | |
2618 | # | |
2619 | # | |
2620 | #" | |
2621 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2622 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2623 | |
52d3af72 DE |
2624 | (define_split |
2625 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2626 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2627 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 2628 | (const_int 0))) |
52d3af72 DE |
2629 | (clobber (match_scratch:SI 3 "")) |
2630 | (clobber (match_scratch:CC 4 ""))] | |
0ad91047 | 2631 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2632 | [(parallel [(set (match_dup 3) |
2633 | (and:SI (match_dup 1) | |
2634 | (match_dup 2))) | |
2635 | (clobber (match_dup 4))]) | |
2636 | (set (match_dup 0) | |
2637 | (compare:CC (match_dup 3) | |
2638 | (const_int 0)))] | |
2639 | "") | |
2640 | ||
2641 | (define_insn "*andsi3_internal3" | |
2642 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2643 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2644 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2645 | (const_int 0))) |
2646 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2647 | (and:SI (match_dup 1) | |
2648 | (match_dup 2))) | |
2649 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2650 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2651 | "@ |
2652 | and. %0,%1,%2 | |
ca7f5001 RK |
2653 | {andil.|andi.} %0,%1,%b2 |
2654 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2655 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2656 | # | |
2657 | # | |
2658 | # | |
2659 | #" | |
2660 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2661 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2662 | ||
2663 | (define_split | |
2664 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2665 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2666 | (match_operand:SI 2 "and_operand" "")) | |
2667 | (const_int 0))) | |
2668 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2669 | (and:SI (match_dup 1) | |
2670 | (match_dup 2))) | |
2671 | (clobber (match_scratch:CC 4 ""))] | |
0ad91047 | 2672 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2673 | [(parallel [(set (match_dup 0) |
2674 | (and:SI (match_dup 1) | |
2675 | (match_dup 2))) | |
2676 | (clobber (match_dup 4))]) | |
2677 | (set (match_dup 3) | |
2678 | (compare:CC (match_dup 0) | |
2679 | (const_int 0)))] | |
2680 | "") | |
1fd4e8c1 | 2681 | |
7cd5235b | 2682 | (define_expand "iorsi3" |
cd2b37d9 | 2683 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2684 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2685 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 2686 | "" |
f357808b RK |
2687 | " |
2688 | { | |
7cd5235b | 2689 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2690 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2691 | { |
2692 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2693 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2694 | ? operands[0] : gen_reg_rtx (SImode)); |
2695 | ||
a260abc9 DE |
2696 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2697 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2698 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2699 | DONE; |
2700 | } | |
f357808b RK |
2701 | }") |
2702 | ||
7cd5235b | 2703 | (define_expand "xorsi3" |
cd2b37d9 | 2704 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2705 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2706 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 2707 | "" |
7cd5235b | 2708 | " |
1fd4e8c1 | 2709 | { |
7cd5235b | 2710 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2711 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2712 | { |
2713 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2714 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2715 | ? operands[0] : gen_reg_rtx (SImode)); |
2716 | ||
a260abc9 DE |
2717 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2718 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2719 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2720 | DONE; |
2721 | } | |
1fd4e8c1 RK |
2722 | }") |
2723 | ||
dfbdccdb | 2724 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2725 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 2726 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2727 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
2728 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2729 | "" |
2730 | "@ | |
dfbdccdb GK |
2731 | %q3 %0,%1,%2 |
2732 | {%q3il|%q3i} %0,%1,%b2 | |
2733 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2734 | |
dfbdccdb | 2735 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2736 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 2737 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
2738 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
2739 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2740 | (const_int 0))) | |
52d3af72 | 2741 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2742 | "! TARGET_POWERPC64" |
52d3af72 | 2743 | "@ |
dfbdccdb | 2744 | %q4. %3,%1,%2 |
52d3af72 DE |
2745 | #" |
2746 | [(set_attr "type" "compare") | |
2747 | (set_attr "length" "4,8")]) | |
2748 | ||
2749 | (define_split | |
2750 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
2751 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2752 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2753 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2754 | (const_int 0))) | |
52d3af72 | 2755 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2756 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2757 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2758 | (set (match_dup 0) |
2759 | (compare:CC (match_dup 3) | |
2760 | (const_int 0)))] | |
2761 | "") | |
815cdc52 | 2762 | |
dfbdccdb | 2763 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2764 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2765 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2766 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2767 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2768 | (const_int 0))) | |
52d3af72 | 2769 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2770 | (match_dup 4))] |
0ad91047 | 2771 | "! TARGET_POWERPC64" |
52d3af72 | 2772 | "@ |
dfbdccdb | 2773 | %q4. %0,%1,%2 |
52d3af72 DE |
2774 | #" |
2775 | [(set_attr "type" "compare") | |
2776 | (set_attr "length" "4,8")]) | |
2777 | ||
2778 | (define_split | |
dfbdccdb GK |
2779 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2780 | (compare:CC (match_operator:SI 4 "boolean_operator" | |
2781 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2782 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2783 | (const_int 0))) | |
2784 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
2785 | (match_dup 4))] | |
0ad91047 | 2786 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2787 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2788 | (set (match_dup 3) |
2789 | (compare:CC (match_dup 0) | |
2790 | (const_int 0)))] | |
2791 | "") | |
1fd4e8c1 | 2792 | |
dfbdccdb GK |
2793 | ;; Split an logical operation that we can't do in one insn into two insns, |
2794 | ;; each of which does one 16-bit part. This is used by combine. | |
a260abc9 DE |
2795 | |
2796 | (define_split | |
2797 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 2798 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2799 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2800 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 2801 | "" |
dfbdccdb GK |
2802 | [(set (match_dup 0) (match_dup 4)) |
2803 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
2804 | " |
2805 | { | |
dfbdccdb GK |
2806 | rtx i; |
2807 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
2808 | operands[4] = gen_rtx (GET_CODE (operands[3]), SImode, | |
2809 | operands[1], i); | |
2810 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
2811 | operands[5] = gen_rtx (GET_CODE (operands[3]), SImode, | |
2812 | operands[0], i); | |
a260abc9 DE |
2813 | }") |
2814 | ||
dfbdccdb | 2815 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 2816 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2817 | (match_operator:SI 3 "boolean_operator" |
2818 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2819 | (match_operand:SI 2 "logical_operand" "r")]))] | |
1fd4e8c1 | 2820 | "" |
dfbdccdb | 2821 | "%q3 %0,%2,%1") |
1fd4e8c1 | 2822 | |
dfbdccdb | 2823 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 2824 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2825 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2826 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2827 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2828 | (const_int 0))) | |
52d3af72 | 2829 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2830 | "! TARGET_POWERPC64" |
52d3af72 | 2831 | "@ |
dfbdccdb | 2832 | %q4. %3,%2,%1 |
52d3af72 DE |
2833 | #" |
2834 | [(set_attr "type" "compare") | |
2835 | (set_attr "length" "4,8")]) | |
2836 | ||
2837 | (define_split | |
2838 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
2839 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2840 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2841 | (match_operand:SI 2 "gpc_reg_operand" "r")]) | |
2842 | (const_int 0))) | |
52d3af72 | 2843 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2844 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2845 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2846 | (set (match_dup 0) |
2847 | (compare:CC (match_dup 3) | |
2848 | (const_int 0)))] | |
2849 | "") | |
1fd4e8c1 | 2850 | |
dfbdccdb | 2851 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 2852 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2853 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2854 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2855 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2856 | (const_int 0))) | |
52d3af72 | 2857 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2858 | (match_dup 4))] |
0ad91047 | 2859 | "! TARGET_POWERPC64" |
52d3af72 | 2860 | "@ |
dfbdccdb | 2861 | %q4. %0,%2,%1 |
52d3af72 DE |
2862 | #" |
2863 | [(set_attr "type" "compare") | |
2864 | (set_attr "length" "4,8")]) | |
2865 | ||
2866 | (define_split | |
52d3af72 | 2867 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2868 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2869 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2870 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2871 | (const_int 0))) | |
52d3af72 | 2872 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2873 | (match_dup 4))] |
0ad91047 | 2874 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2875 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2876 | (set (match_dup 3) |
2877 | (compare:CC (match_dup 0) | |
2878 | (const_int 0)))] | |
2879 | "") | |
2880 | ||
dfbdccdb | 2881 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 2882 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2883 | (match_operator:SI 3 "boolean_operator" |
2884 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2885 | (not:SI (match_operand:SI 2 "logical_operand" "r"))]))] | |
1fd4e8c1 | 2886 | "" |
dfbdccdb | 2887 | "%q3 %0,%1,%2") |
1fd4e8c1 | 2888 | |
dfbdccdb | 2889 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 2890 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2891 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2892 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2893 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2894 | (const_int 0))) | |
52d3af72 | 2895 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2896 | "! TARGET_POWERPC64" |
52d3af72 | 2897 | "@ |
dfbdccdb | 2898 | %q4. %3,%1,%2 |
52d3af72 DE |
2899 | #" |
2900 | [(set_attr "type" "compare") | |
2901 | (set_attr "length" "4,8")]) | |
2902 | ||
2903 | (define_split | |
2904 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
2905 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2906 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2907 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]) | |
2908 | (const_int 0))) | |
52d3af72 | 2909 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2910 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2911 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2912 | (set (match_dup 0) |
2913 | (compare:CC (match_dup 3) | |
2914 | (const_int 0)))] | |
2915 | "") | |
1fd4e8c1 | 2916 | |
dfbdccdb | 2917 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 2918 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2919 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2920 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2921 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2922 | (const_int 0))) | |
52d3af72 | 2923 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2924 | (match_dup 4))] |
0ad91047 | 2925 | "! TARGET_POWERPC64" |
52d3af72 | 2926 | "@ |
dfbdccdb | 2927 | %q4. %0,%1,%2 |
52d3af72 DE |
2928 | #" |
2929 | [(set_attr "type" "compare") | |
2930 | (set_attr "length" "4,8")]) | |
2931 | ||
2932 | (define_split | |
52d3af72 | 2933 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2934 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2935 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2936 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2937 | (const_int 0))) | |
52d3af72 | 2938 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2939 | (match_dup 4))] |
0ad91047 | 2940 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2941 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2942 | (set (match_dup 3) |
2943 | (compare:CC (match_dup 0) | |
2944 | (const_int 0)))] | |
2945 | "") | |
1fd4e8c1 RK |
2946 | |
2947 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2948 | ;; orders. Don't define forms that only set CR fields because these | |
2949 | ;; would modify an input register. | |
2950 | ||
7cd5235b | 2951 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2952 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2953 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2954 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2955 | (and:SI (match_dup 2) | |
cd2b37d9 | 2956 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2957 | "TARGET_POWER" |
01def764 | 2958 | "maskir %0,%3,%2") |
1fd4e8c1 | 2959 | |
7cd5235b | 2960 | (define_insn "*maskir_internal2" |
242e8072 | 2961 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2962 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2963 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2964 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2965 | (match_dup 2))))] |
ca7f5001 | 2966 | "TARGET_POWER" |
01def764 | 2967 | "maskir %0,%3,%2") |
1fd4e8c1 | 2968 | |
7cd5235b | 2969 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2970 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2971 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2972 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2973 | (and:SI (not:SI (match_dup 2)) |
2974 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2975 | "TARGET_POWER" |
01def764 | 2976 | "maskir %0,%3,%2") |
1fd4e8c1 | 2977 | |
7cd5235b | 2978 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2979 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2980 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2981 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2982 | (and:SI (not:SI (match_dup 2)) | |
2983 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2984 | "TARGET_POWER" |
01def764 | 2985 | "maskir %0,%3,%2") |
1fd4e8c1 | 2986 | |
7cd5235b | 2987 | (define_insn "*maskir_internal5" |
9ebbca7d | 2988 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2989 | (compare:CC |
9ebbca7d GK |
2990 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2991 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 2992 | (and:SI (match_dup 2) |
9ebbca7d | 2993 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 2994 | (const_int 0))) |
9ebbca7d | 2995 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2996 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2997 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2998 | "TARGET_POWER" |
9ebbca7d GK |
2999 | "@ |
3000 | maskir. %0,%3,%2 | |
3001 | #" | |
3002 | [(set_attr "type" "compare") | |
3003 | (set_attr "length" "4,8")]) | |
3004 | ||
3005 | (define_split | |
3006 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3007 | (compare:CC | |
3008 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
3009 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
3010 | (and:SI (match_dup 2) | |
3011 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
3012 | (const_int 0))) | |
3013 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3014 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3015 | (and:SI (match_dup 2) (match_dup 3))))] | |
3016 | "TARGET_POWER && reload_completed" | |
3017 | [(set (match_dup 0) | |
3018 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3019 | (and:SI (match_dup 2) (match_dup 3)))) | |
3020 | (set (match_dup 4) | |
3021 | (compare:CC (match_dup 0) | |
3022 | (const_int 0)))] | |
3023 | "") | |
1fd4e8c1 | 3024 | |
7cd5235b | 3025 | (define_insn "*maskir_internal6" |
9ebbca7d | 3026 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3027 | (compare:CC |
9ebbca7d GK |
3028 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
3029 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
3030 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 3031 | (match_dup 2))) |
1fd4e8c1 | 3032 | (const_int 0))) |
9ebbca7d | 3033 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3034 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
3035 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 3036 | "TARGET_POWER" |
9ebbca7d GK |
3037 | "@ |
3038 | maskir. %0,%3,%2 | |
3039 | #" | |
3040 | [(set_attr "type" "compare") | |
3041 | (set_attr "length" "4,8")]) | |
3042 | ||
3043 | (define_split | |
3044 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3045 | (compare:CC | |
3046 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
3047 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
3048 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3049 | (match_dup 2))) | |
3050 | (const_int 0))) | |
3051 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3052 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3053 | (and:SI (match_dup 3) (match_dup 2))))] | |
3054 | "TARGET_POWER && reload_completed" | |
3055 | [(set (match_dup 0) | |
3056 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3057 | (and:SI (match_dup 3) (match_dup 2)))) | |
3058 | (set (match_dup 4) | |
3059 | (compare:CC (match_dup 0) | |
3060 | (const_int 0)))] | |
3061 | "") | |
1fd4e8c1 | 3062 | |
7cd5235b | 3063 | (define_insn "*maskir_internal7" |
9ebbca7d | 3064 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 3065 | (compare:CC |
9ebbca7d GK |
3066 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
3067 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 3068 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3069 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 3070 | (const_int 0))) |
9ebbca7d | 3071 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
3072 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
3073 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3074 | "TARGET_POWER" | |
9ebbca7d GK |
3075 | "@ |
3076 | maskir. %0,%3,%2 | |
3077 | #" | |
3078 | [(set_attr "type" "compare") | |
3079 | (set_attr "length" "4,8")]) | |
3080 | ||
3081 | (define_split | |
3082 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3083 | (compare:CC | |
3084 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
3085 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
3086 | (and:SI (not:SI (match_dup 2)) | |
3087 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3088 | (const_int 0))) | |
3089 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3090 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3091 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3092 | "TARGET_POWER && reload_completed" | |
3093 | [(set (match_dup 0) | |
3094 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3095 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3096 | (set (match_dup 4) | |
3097 | (compare:CC (match_dup 0) | |
3098 | (const_int 0)))] | |
3099 | "") | |
1fd4e8c1 | 3100 | |
7cd5235b | 3101 | (define_insn "*maskir_internal8" |
9ebbca7d | 3102 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3103 | (compare:CC |
9ebbca7d GK |
3104 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
3105 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 3106 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3107 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 3108 | (const_int 0))) |
9ebbca7d | 3109 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3110 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
3111 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 3112 | "TARGET_POWER" |
9ebbca7d GK |
3113 | "@ |
3114 | maskir. %0,%3,%2 | |
3115 | #" | |
3116 | [(set_attr "type" "compare") | |
3117 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 3118 | \f |
9ebbca7d GK |
3119 | (define_split |
3120 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3121 | (compare:CC | |
3122 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3123 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
3124 | (and:SI (not:SI (match_dup 2)) | |
3125 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3126 | (const_int 0))) | |
3127 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3128 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3129 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3130 | "TARGET_POWER && reload_completed" | |
3131 | [(set (match_dup 0) | |
3132 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3133 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3134 | (set (match_dup 4) | |
3135 | (compare:CC (match_dup 0) | |
3136 | (const_int 0)))] | |
3137 | "") | |
3138 | ||
1fd4e8c1 RK |
3139 | ;; Rotate and shift insns, in all their variants. These support shifts, |
3140 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 3141 | (define_expand "insv" |
0ad91047 DE |
3142 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
3143 | (match_operand:SI 1 "const_int_operand" "") | |
3144 | (match_operand:SI 2 "const_int_operand" "")) | |
3145 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
3146 | "" |
3147 | " | |
3148 | { | |
3149 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3150 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3151 | compiler if the address of the structure is taken later. */ | |
3152 | if (GET_CODE (operands[0]) == SUBREG | |
3153 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3154 | FAIL; | |
a78e33fc DE |
3155 | |
3156 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
3157 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
3158 | else | |
3159 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
3160 | DONE; | |
034c1be0 MM |
3161 | }") |
3162 | ||
a78e33fc | 3163 | (define_insn "insvsi" |
cd2b37d9 | 3164 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
3165 | (match_operand:SI 1 "const_int_operand" "i") |
3166 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 3167 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
3168 | "" |
3169 | "* | |
3170 | { | |
3171 | int start = INTVAL (operands[2]) & 31; | |
3172 | int size = INTVAL (operands[1]) & 31; | |
3173 | ||
89e9f3a8 MM |
3174 | operands[4] = GEN_INT (32 - start - size); |
3175 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3176 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
1fd4e8c1 RK |
3177 | }") |
3178 | ||
a78e33fc | 3179 | (define_insn "*insvsi_internal1" |
d56d506a RK |
3180 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3181 | (match_operand:SI 1 "const_int_operand" "i") | |
3182 | (match_operand:SI 2 "const_int_operand" "i")) | |
3183 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3184 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3185 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3186 | "* |
3187 | { | |
3188 | int shift = INTVAL (operands[4]) & 31; | |
3189 | int start = INTVAL (operands[2]) & 31; | |
3190 | int size = INTVAL (operands[1]) & 31; | |
3191 | ||
89e9f3a8 MM |
3192 | operands[4] = GEN_INT (shift - start - size); |
3193 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3194 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3195 | }") |
3196 | ||
a78e33fc | 3197 | (define_insn "*insvsi_internal2" |
d56d506a RK |
3198 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3199 | (match_operand:SI 1 "const_int_operand" "i") | |
3200 | (match_operand:SI 2 "const_int_operand" "i")) | |
3201 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3202 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3203 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3204 | "* |
3205 | { | |
3206 | int shift = INTVAL (operands[4]) & 31; | |
3207 | int start = INTVAL (operands[2]) & 31; | |
3208 | int size = INTVAL (operands[1]) & 31; | |
3209 | ||
89e9f3a8 MM |
3210 | operands[4] = GEN_INT (32 - shift - start - size); |
3211 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3212 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3213 | }") |
3214 | ||
a78e33fc | 3215 | (define_insn "*insvsi_internal3" |
d56d506a RK |
3216 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3217 | (match_operand:SI 1 "const_int_operand" "i") | |
3218 | (match_operand:SI 2 "const_int_operand" "i")) | |
3219 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3220 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 3221 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3222 | "* |
3223 | { | |
3224 | int shift = INTVAL (operands[4]) & 31; | |
3225 | int start = INTVAL (operands[2]) & 31; | |
3226 | int size = INTVAL (operands[1]) & 31; | |
3227 | ||
89e9f3a8 MM |
3228 | operands[4] = GEN_INT (32 - shift - start - size); |
3229 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3230 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3231 | }") |
3232 | ||
a78e33fc | 3233 | (define_insn "*insvsi_internal4" |
d56d506a RK |
3234 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3235 | (match_operand:SI 1 "const_int_operand" "i") | |
3236 | (match_operand:SI 2 "const_int_operand" "i")) | |
3237 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3238 | (match_operand:SI 4 "const_int_operand" "i") | |
3239 | (match_operand:SI 5 "const_int_operand" "i")))] | |
3240 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
3241 | "* | |
3242 | { | |
3243 | int extract_start = INTVAL (operands[5]) & 31; | |
3244 | int extract_size = INTVAL (operands[4]) & 31; | |
3245 | int insert_start = INTVAL (operands[2]) & 31; | |
3246 | int insert_size = INTVAL (operands[1]) & 31; | |
3247 | ||
3248 | /* Align extract field with insert field */ | |
3a598fbe | 3249 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 3250 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 3251 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
d56d506a RK |
3252 | }") |
3253 | ||
a78e33fc | 3254 | (define_insn "insvdi" |
685f3906 | 3255 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3256 | (match_operand:SI 1 "const_int_operand" "i") |
3257 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3258 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3259 | "TARGET_POWERPC64" | |
3260 | "* | |
3261 | { | |
3262 | int start = INTVAL (operands[2]) & 63; | |
3263 | int size = INTVAL (operands[1]) & 63; | |
3264 | ||
a78e33fc DE |
3265 | operands[1] = GEN_INT (64 - start - size); |
3266 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3267 | }") |
3268 | ||
034c1be0 | 3269 | (define_expand "extzv" |
0ad91047 DE |
3270 | [(set (match_operand 0 "gpc_reg_operand" "") |
3271 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3272 | (match_operand:SI 2 "const_int_operand" "") | |
3273 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3274 | "" |
3275 | " | |
3276 | { | |
3277 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3278 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3279 | compiler if the address of the structure is taken later. */ | |
3280 | if (GET_CODE (operands[0]) == SUBREG | |
3281 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3282 | FAIL; | |
a78e33fc DE |
3283 | |
3284 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3285 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3286 | else | |
3287 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3288 | DONE; | |
034c1be0 MM |
3289 | }") |
3290 | ||
a78e33fc | 3291 | (define_insn "extzvsi" |
cd2b37d9 RK |
3292 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3293 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3294 | (match_operand:SI 2 "const_int_operand" "i") |
3295 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3296 | "" | |
3297 | "* | |
3298 | { | |
3299 | int start = INTVAL (operands[3]) & 31; | |
3300 | int size = INTVAL (operands[2]) & 31; | |
3301 | ||
3302 | if (start + size >= 32) | |
3303 | operands[3] = const0_rtx; | |
3304 | else | |
89e9f3a8 | 3305 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3306 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3307 | }") |
3308 | ||
a78e33fc | 3309 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3310 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3311 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3312 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3313 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3314 | (const_int 0))) |
9ebbca7d | 3315 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3316 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
3317 | "* |
3318 | { | |
3319 | int start = INTVAL (operands[3]) & 31; | |
3320 | int size = INTVAL (operands[2]) & 31; | |
3321 | ||
9ebbca7d GK |
3322 | /* Force split for non-cc0 compare. */ |
3323 | if (which_alternative == 1) | |
3324 | return \"#\"; | |
3325 | ||
a7a975e1 RK |
3326 | /* If the bitfield being tested fits in the upper or lower half of a |
3327 | word, it is possible to use andiu. or andil. to test it. This is | |
3328 | useful because the condition register set-use delay is smaller for | |
3329 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3330 | position is 0 because the LT and GT bits may be set wrong. */ | |
3331 | ||
3332 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3333 | { |
3a598fbe | 3334 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3335 | - (1 << (16 - (start & 15) - size)))); |
3336 | if (start < 16) | |
ca7f5001 | 3337 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3338 | else |
ca7f5001 | 3339 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3340 | } |
7e69e155 | 3341 | |
1fd4e8c1 RK |
3342 | if (start + size >= 32) |
3343 | operands[3] = const0_rtx; | |
3344 | else | |
89e9f3a8 | 3345 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3346 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3347 | }" |
9ebbca7d GK |
3348 | [(set_attr "type" "compare") |
3349 | (set_attr "length" "4,8")]) | |
3350 | ||
3351 | (define_split | |
3352 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3353 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3354 | (match_operand:SI 2 "const_int_operand" "") | |
3355 | (match_operand:SI 3 "const_int_operand" "")) | |
3356 | (const_int 0))) | |
3357 | (clobber (match_scratch:SI 4 ""))] | |
3358 | "! TARGET_POWERPC64 && reload_completed" | |
3359 | [(set (match_dup 4) | |
3360 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3361 | (match_dup 3))) | |
3362 | (set (match_dup 0) | |
3363 | (compare:CC (match_dup 4) | |
3364 | (const_int 0)))] | |
3365 | "") | |
1fd4e8c1 | 3366 | |
a78e33fc | 3367 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3368 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3369 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3370 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3371 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3372 | (const_int 0))) |
9ebbca7d | 3373 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3374 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
0ad91047 | 3375 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
3376 | "* |
3377 | { | |
3378 | int start = INTVAL (operands[3]) & 31; | |
3379 | int size = INTVAL (operands[2]) & 31; | |
3380 | ||
9ebbca7d GK |
3381 | /* Force split for non-cc0 compare. */ |
3382 | if (which_alternative == 1) | |
3383 | return \"#\"; | |
3384 | ||
a7a975e1 | 3385 | if (start >= 16 && start + size == 32) |
df031c43 | 3386 | { |
89e9f3a8 | 3387 | operands[3] = GEN_INT ((1 << (32 - start)) - 1); |
ca7f5001 | 3388 | return \"{andil.|andi.} %0,%1,%3\"; |
df031c43 | 3389 | } |
7e69e155 | 3390 | |
1fd4e8c1 RK |
3391 | if (start + size >= 32) |
3392 | operands[3] = const0_rtx; | |
3393 | else | |
89e9f3a8 | 3394 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3395 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3396 | }" |
9ebbca7d GK |
3397 | [(set_attr "type" "delayed_compare") |
3398 | (set_attr "length" "4,8")]) | |
3399 | ||
3400 | (define_split | |
3401 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3402 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3403 | (match_operand:SI 2 "const_int_operand" "") | |
3404 | (match_operand:SI 3 "const_int_operand" "")) | |
3405 | (const_int 0))) | |
3406 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3407 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
3408 | "! TARGET_POWERPC64 && reload_completed" | |
3409 | [(set (match_dup 0) | |
3410 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3411 | (set (match_dup 4) | |
3412 | (compare:CC (match_dup 0) | |
3413 | (const_int 0)))] | |
3414 | "") | |
1fd4e8c1 | 3415 | |
a78e33fc | 3416 | (define_insn "extzvdi" |
685f3906 DE |
3417 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3418 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3419 | (match_operand:SI 2 "const_int_operand" "i") |
3420 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3421 | "TARGET_POWERPC64" |
3422 | "* | |
3423 | { | |
3424 | int start = INTVAL (operands[3]) & 63; | |
3425 | int size = INTVAL (operands[2]) & 63; | |
3426 | ||
3427 | if (start + size >= 64) | |
3428 | operands[3] = const0_rtx; | |
3429 | else | |
89e9f3a8 MM |
3430 | operands[3] = GEN_INT (start + size); |
3431 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3432 | return \"rldicl %0,%1,%3,%2\"; |
3433 | }") | |
3434 | ||
a78e33fc | 3435 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3436 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3437 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3438 | (match_operand:SI 2 "const_int_operand" "i") |
3439 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3440 | (const_int 0))) |
29ae5b89 | 3441 | (clobber (match_scratch:DI 4 "=r"))] |
685f3906 DE |
3442 | "TARGET_POWERPC64" |
3443 | "* | |
3444 | { | |
3445 | int start = INTVAL (operands[3]) & 63; | |
3446 | int size = INTVAL (operands[2]) & 63; | |
3447 | ||
3448 | if (start + size >= 64) | |
3449 | operands[3] = const0_rtx; | |
3450 | else | |
89e9f3a8 MM |
3451 | operands[3] = GEN_INT (start + size); |
3452 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3453 | return \"rldicl. %4,%1,%3,%2\"; |
3454 | }") | |
3455 | ||
a78e33fc | 3456 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3457 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3458 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3459 | (match_operand:SI 2 "const_int_operand" "i") |
3460 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3461 | (const_int 0))) |
29ae5b89 | 3462 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 DE |
3463 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
3464 | "TARGET_POWERPC64" | |
3465 | "* | |
3466 | { | |
3467 | int start = INTVAL (operands[3]) & 63; | |
3468 | int size = INTVAL (operands[2]) & 63; | |
3469 | ||
3470 | if (start + size >= 64) | |
3471 | operands[3] = const0_rtx; | |
3472 | else | |
89e9f3a8 MM |
3473 | operands[3] = GEN_INT (start + size); |
3474 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3475 | return \"rldicl. %0,%1,%3,%2\"; |
3476 | }") | |
3477 | ||
1fd4e8c1 | 3478 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3479 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3480 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3481 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3482 | "" | |
ca7f5001 | 3483 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3484 | |
a260abc9 | 3485 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3486 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3487 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3488 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3489 | (const_int 0))) |
9ebbca7d | 3490 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3491 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3492 | "@ |
3493 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3494 | #" | |
3495 | [(set_attr "type" "delayed_compare") | |
3496 | (set_attr "length" "4,8")]) | |
3497 | ||
3498 | (define_split | |
3499 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3500 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3501 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3502 | (const_int 0))) | |
3503 | (clobber (match_scratch:SI 3 ""))] | |
3504 | "! TARGET_POWERPC64 && reload_completed" | |
3505 | [(set (match_dup 3) | |
3506 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3507 | (set (match_dup 0) | |
3508 | (compare:CC (match_dup 3) | |
3509 | (const_int 0)))] | |
3510 | "") | |
1fd4e8c1 | 3511 | |
a260abc9 | 3512 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3513 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3514 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3515 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3516 | (const_int 0))) |
9ebbca7d | 3517 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3518 | (rotate:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3519 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3520 | "@ |
3521 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3522 | #" | |
3523 | [(set_attr "type" "delayed_compare") | |
3524 | (set_attr "length" "4,8")]) | |
3525 | ||
3526 | (define_split | |
3527 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3528 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3529 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3530 | (const_int 0))) | |
3531 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3532 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
3533 | "! TARGET_POWERPC64 && reload_completed" | |
3534 | [(set (match_dup 0) | |
3535 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3536 | (set (match_dup 3) | |
3537 | (compare:CC (match_dup 0) | |
3538 | (const_int 0)))] | |
3539 | "") | |
1fd4e8c1 | 3540 | |
a260abc9 | 3541 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3542 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3543 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3544 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
9615f239 | 3545 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 3546 | "" |
ca7f5001 | 3547 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3548 | |
a260abc9 | 3549 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3550 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3551 | (compare:CC (and:SI |
9ebbca7d GK |
3552 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3553 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
3554 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3555 | (const_int 0))) |
9ebbca7d | 3556 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3557 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3558 | "@ |
3559 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3560 | #" | |
3561 | [(set_attr "type" "delayed_compare") | |
3562 | (set_attr "length" "4,8")]) | |
3563 | ||
3564 | (define_split | |
3565 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3566 | (compare:CC (and:SI | |
3567 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3568 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3569 | (match_operand:SI 3 "mask_operand" "")) | |
3570 | (const_int 0))) | |
3571 | (clobber (match_scratch:SI 4 ""))] | |
3572 | "! TARGET_POWERPC64 && reload_completed" | |
3573 | [(set (match_dup 4) | |
3574 | (and:SI (rotate:SI (match_dup 1) | |
3575 | (match_dup 2)) | |
3576 | (match_dup 3))) | |
3577 | (set (match_dup 0) | |
3578 | (compare:CC (match_dup 4) | |
3579 | (const_int 0)))] | |
3580 | "") | |
1fd4e8c1 | 3581 | |
a260abc9 | 3582 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3583 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3584 | (compare:CC (and:SI |
9ebbca7d GK |
3585 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3586 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
3587 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3588 | (const_int 0))) |
9ebbca7d | 3589 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3590 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 3591 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3592 | "@ |
3593 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3594 | #" | |
3595 | [(set_attr "type" "delayed_compare") | |
3596 | (set_attr "length" "4,8")]) | |
3597 | ||
3598 | (define_split | |
3599 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3600 | (compare:CC (and:SI | |
3601 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3602 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3603 | (match_operand:SI 3 "mask_operand" "")) | |
3604 | (const_int 0))) | |
3605 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3606 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
3607 | "! TARGET_POWERPC64 && reload_completed" | |
3608 | [(set (match_dup 0) | |
3609 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3610 | (set (match_dup 4) | |
3611 | (compare:CC (match_dup 0) | |
3612 | (const_int 0)))] | |
3613 | "") | |
1fd4e8c1 | 3614 | |
a260abc9 | 3615 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3616 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3617 | (zero_extend:SI |
3618 | (subreg:QI | |
cd2b37d9 | 3619 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3620 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3621 | "" | |
ca7f5001 | 3622 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3623 | |
a260abc9 | 3624 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3625 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3626 | (compare:CC (zero_extend:SI |
3627 | (subreg:QI | |
9ebbca7d GK |
3628 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3629 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3630 | (const_int 0))) |
9ebbca7d | 3631 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3632 | "" |
9ebbca7d GK |
3633 | "@ |
3634 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3635 | #" | |
3636 | [(set_attr "type" "delayed_compare") | |
3637 | (set_attr "length" "4,8")]) | |
3638 | ||
3639 | (define_split | |
3640 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3641 | (compare:CC (zero_extend:SI | |
3642 | (subreg:QI | |
3643 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3644 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3645 | (const_int 0))) | |
3646 | (clobber (match_scratch:SI 3 ""))] | |
3647 | "reload_completed" | |
3648 | [(set (match_dup 3) | |
3649 | (zero_extend:SI (subreg:QI | |
3650 | (rotate:SI (match_dup 1) | |
3651 | (match_dup 2)) 0))) | |
3652 | (set (match_dup 0) | |
3653 | (compare:CC (match_dup 3) | |
3654 | (const_int 0)))] | |
3655 | "") | |
1fd4e8c1 | 3656 | |
a260abc9 | 3657 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3658 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3659 | (compare:CC (zero_extend:SI |
3660 | (subreg:QI | |
9ebbca7d GK |
3661 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3662 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3663 | (const_int 0))) |
9ebbca7d | 3664 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3665 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3666 | "" | |
9ebbca7d GK |
3667 | "@ |
3668 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3669 | #" | |
3670 | [(set_attr "type" "delayed_compare") | |
3671 | (set_attr "length" "4,8")]) | |
3672 | ||
3673 | (define_split | |
3674 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3675 | (compare:CC (zero_extend:SI | |
3676 | (subreg:QI | |
3677 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3678 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3679 | (const_int 0))) | |
3680 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3681 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3682 | "reload_completed" | |
3683 | [(set (match_dup 0) | |
3684 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3685 | (set (match_dup 3) | |
3686 | (compare:CC (match_dup 0) | |
3687 | (const_int 0)))] | |
3688 | "") | |
1fd4e8c1 | 3689 | |
a260abc9 | 3690 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3691 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3692 | (zero_extend:SI |
3693 | (subreg:HI | |
cd2b37d9 | 3694 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3695 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3696 | "" | |
ca7f5001 | 3697 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3698 | |
a260abc9 | 3699 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3700 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3701 | (compare:CC (zero_extend:SI |
3702 | (subreg:HI | |
9ebbca7d GK |
3703 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3704 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3705 | (const_int 0))) |
9ebbca7d | 3706 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3707 | "" |
9ebbca7d GK |
3708 | "@ |
3709 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3710 | #" | |
3711 | [(set_attr "type" "delayed_compare") | |
3712 | (set_attr "length" "4,8")]) | |
3713 | ||
3714 | (define_split | |
3715 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3716 | (compare:CC (zero_extend:SI | |
3717 | (subreg:HI | |
3718 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3719 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3720 | (const_int 0))) | |
3721 | (clobber (match_scratch:SI 3 ""))] | |
3722 | "reload_completed" | |
3723 | [(set (match_dup 3) | |
3724 | (zero_extend:SI (subreg:HI | |
3725 | (rotate:SI (match_dup 1) | |
3726 | (match_dup 2)) 0))) | |
3727 | (set (match_dup 0) | |
3728 | (compare:CC (match_dup 3) | |
3729 | (const_int 0)))] | |
3730 | "") | |
1fd4e8c1 | 3731 | |
a260abc9 | 3732 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3733 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3734 | (compare:CC (zero_extend:SI |
3735 | (subreg:HI | |
9ebbca7d GK |
3736 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3737 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3738 | (const_int 0))) |
9ebbca7d | 3739 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3740 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3741 | "" | |
9ebbca7d GK |
3742 | "@ |
3743 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3744 | #" | |
3745 | [(set_attr "type" "delayed_compare") | |
3746 | (set_attr "length" "4,8")]) | |
3747 | ||
3748 | (define_split | |
3749 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3750 | (compare:CC (zero_extend:SI | |
3751 | (subreg:HI | |
3752 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3753 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3754 | (const_int 0))) | |
3755 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3756 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3757 | "reload_completed" | |
3758 | [(set (match_dup 0) | |
3759 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3760 | (set (match_dup 3) | |
3761 | (compare:CC (match_dup 0) | |
3762 | (const_int 0)))] | |
3763 | "") | |
1fd4e8c1 RK |
3764 | |
3765 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3766 | ;; SHIFT_COUNT_TRUNCATED. | |
3767 | ||
ca7f5001 RK |
3768 | (define_expand "ashlsi3" |
3769 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3770 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3771 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3772 | "" | |
3773 | " | |
3774 | { | |
3775 | if (TARGET_POWER) | |
3776 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3777 | else | |
25c341fa | 3778 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3779 | DONE; |
3780 | }") | |
3781 | ||
3782 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3783 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3784 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3785 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3786 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3787 | "TARGET_POWER" |
1fd4e8c1 RK |
3788 | "@ |
3789 | sle %0,%1,%2 | |
9ebbca7d | 3790 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3791 | |
25c341fa | 3792 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3793 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3794 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3795 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3796 | "! TARGET_POWER" |
9ebbca7d | 3797 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3798 | |
3799 | (define_insn "" | |
9ebbca7d GK |
3800 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3801 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3802 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3803 | (const_int 0))) |
9ebbca7d GK |
3804 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
3805 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 3806 | "TARGET_POWER" |
1fd4e8c1 RK |
3807 | "@ |
3808 | sle. %3,%1,%2 | |
9ebbca7d GK |
3809 | {sli.|slwi.} %3,%1,%h2 |
3810 | # | |
3811 | #" | |
3812 | [(set_attr "type" "delayed_compare") | |
3813 | (set_attr "length" "4,4,8,8")]) | |
3814 | ||
3815 | (define_split | |
3816 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3817 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3818 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3819 | (const_int 0))) | |
3820 | (clobber (match_scratch:SI 3 "")) | |
3821 | (clobber (match_scratch:SI 4 ""))] | |
3822 | "TARGET_POWER && reload_completed" | |
3823 | [(parallel [(set (match_dup 3) | |
3824 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3825 | (clobber (match_dup 4))]) | |
3826 | (set (match_dup 0) | |
3827 | (compare:CC (match_dup 3) | |
3828 | (const_int 0)))] | |
3829 | "") | |
25c341fa | 3830 | |
ca7f5001 | 3831 | (define_insn "" |
9ebbca7d GK |
3832 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3833 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3834 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3835 | (const_int 0))) |
9ebbca7d | 3836 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3837 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
3838 | "@ |
3839 | {sl|slw}%I2. %3,%1,%h2 | |
3840 | #" | |
3841 | [(set_attr "type" "delayed_compare") | |
3842 | (set_attr "length" "4,8")]) | |
3843 | ||
3844 | (define_split | |
3845 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3846 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3847 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3848 | (const_int 0))) | |
3849 | (clobber (match_scratch:SI 3 ""))] | |
3850 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3851 | [(set (match_dup 3) | |
3852 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3853 | (set (match_dup 0) | |
3854 | (compare:CC (match_dup 3) | |
3855 | (const_int 0)))] | |
3856 | "") | |
1fd4e8c1 RK |
3857 | |
3858 | (define_insn "" | |
9ebbca7d GK |
3859 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3860 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3861 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3862 | (const_int 0))) |
9ebbca7d | 3863 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 3864 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3865 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 3866 | "TARGET_POWER" |
1fd4e8c1 RK |
3867 | "@ |
3868 | sle. %0,%1,%2 | |
9ebbca7d GK |
3869 | {sli.|slwi.} %0,%1,%h2 |
3870 | # | |
3871 | #" | |
3872 | [(set_attr "type" "delayed_compare") | |
3873 | (set_attr "length" "4,4,8,8")]) | |
3874 | ||
3875 | (define_split | |
3876 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3877 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3878 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3879 | (const_int 0))) | |
3880 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3881 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3882 | (clobber (match_scratch:SI 4 ""))] | |
3883 | "TARGET_POWER && reload_completed" | |
3884 | [(parallel [(set (match_dup 0) | |
3885 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3886 | (clobber (match_dup 4))]) | |
3887 | (set (match_dup 3) | |
3888 | (compare:CC (match_dup 0) | |
3889 | (const_int 0)))] | |
3890 | "") | |
25c341fa | 3891 | |
ca7f5001 | 3892 | (define_insn "" |
9ebbca7d GK |
3893 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3894 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3895 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3896 | (const_int 0))) |
9ebbca7d | 3897 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 3898 | (ashift:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3899 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
3900 | "@ |
3901 | {sl|slw}%I2. %0,%1,%h2 | |
3902 | #" | |
3903 | [(set_attr "type" "delayed_compare") | |
3904 | (set_attr "length" "4,8")]) | |
3905 | ||
3906 | (define_split | |
3907 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3908 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3909 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3910 | (const_int 0))) | |
3911 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3912 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
3913 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3914 | [(set (match_dup 0) | |
3915 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3916 | (set (match_dup 3) | |
3917 | (compare:CC (match_dup 0) | |
3918 | (const_int 0)))] | |
3919 | "") | |
1fd4e8c1 RK |
3920 | |
3921 | (define_insn "" | |
cd2b37d9 RK |
3922 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3923 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3924 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 3925 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 3926 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 3927 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3928 | |
3929 | (define_insn "" | |
9ebbca7d | 3930 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3931 | (compare:CC |
9ebbca7d GK |
3932 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3933 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
3934 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3935 | (const_int 0))) |
9ebbca7d | 3936 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3937 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3938 | "@ |
3939 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
3940 | #" | |
3941 | [(set_attr "type" "delayed_compare") | |
3942 | (set_attr "length" "4,8")]) | |
3943 | ||
3944 | (define_split | |
3945 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3946 | (compare:CC | |
3947 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3948 | (match_operand:SI 2 "const_int_operand" "")) | |
3949 | (match_operand:SI 3 "mask_operand" "")) | |
3950 | (const_int 0))) | |
3951 | (clobber (match_scratch:SI 4 ""))] | |
3952 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" | |
3953 | [(set (match_dup 4) | |
3954 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
3955 | (match_dup 3))) | |
3956 | (set (match_dup 0) | |
3957 | (compare:CC (match_dup 4) | |
3958 | (const_int 0)))] | |
3959 | "") | |
1fd4e8c1 RK |
3960 | |
3961 | (define_insn "" | |
9ebbca7d | 3962 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3963 | (compare:CC |
9ebbca7d GK |
3964 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3965 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
3966 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3967 | (const_int 0))) |
9ebbca7d | 3968 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3969 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 3970 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3971 | "@ |
3972 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
3973 | #" | |
3974 | [(set_attr "type" "delayed_compare") | |
3975 | (set_attr "length" "4,8")]) | |
3976 | ||
3977 | (define_split | |
3978 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3979 | (compare:CC | |
3980 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3981 | (match_operand:SI 2 "const_int_operand" "")) | |
3982 | (match_operand:SI 3 "mask_operand" "")) | |
3983 | (const_int 0))) | |
3984 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3985 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
3986 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" | |
3987 | [(set (match_dup 0) | |
3988 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3989 | (set (match_dup 4) | |
3990 | (compare:CC (match_dup 0) | |
3991 | (const_int 0)))] | |
3992 | "") | |
1fd4e8c1 | 3993 | |
ca7f5001 | 3994 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3995 | ;; "sli x,x,0". |
ca7f5001 RK |
3996 | (define_expand "lshrsi3" |
3997 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3998 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3999 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
4000 | "" | |
4001 | " | |
4002 | { | |
4003 | if (TARGET_POWER) | |
4004 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
4005 | else | |
25c341fa | 4006 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4007 | DONE; |
4008 | }") | |
4009 | ||
4010 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
4011 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
4012 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
4013 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
4014 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 4015 | "TARGET_POWER" |
1fd4e8c1 RK |
4016 | "@ |
4017 | sre %0,%1,%2 | |
bdf423cb | 4018 | mr %0,%1 |
ca7f5001 RK |
4019 | {s%A2i|s%A2wi} %0,%1,%h2") |
4020 | ||
25c341fa | 4021 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
4022 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4023 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4024 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 4025 | "! TARGET_POWER" |
bdf423cb MM |
4026 | "@ |
4027 | mr %0,%1 | |
4028 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
4029 | |
4030 | (define_insn "" | |
9ebbca7d GK |
4031 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
4032 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4033 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4034 | (const_int 0))) |
9ebbca7d GK |
4035 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
4036 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 4037 | "TARGET_POWER" |
1fd4e8c1 | 4038 | "@ |
29ae5b89 JL |
4039 | sre. %3,%1,%2 |
4040 | mr. %1,%1 | |
9ebbca7d GK |
4041 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
4042 | # | |
4043 | # | |
4044 | #" | |
4045 | [(set_attr "type" "delayed_compare") | |
4046 | (set_attr "length" "4,4,4,8,8,8")]) | |
4047 | ||
4048 | (define_split | |
4049 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4050 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4051 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4052 | (const_int 0))) | |
4053 | (clobber (match_scratch:SI 3 "")) | |
4054 | (clobber (match_scratch:SI 4 ""))] | |
4055 | "TARGET_POWER && reload_completed" | |
4056 | [(parallel [(set (match_dup 3) | |
4057 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4058 | (clobber (match_dup 4))]) | |
4059 | (set (match_dup 0) | |
4060 | (compare:CC (match_dup 3) | |
4061 | (const_int 0)))] | |
4062 | "") | |
ca7f5001 RK |
4063 | |
4064 | (define_insn "" | |
9ebbca7d GK |
4065 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4066 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4067 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 4068 | (const_int 0))) |
9ebbca7d | 4069 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
0ad91047 | 4070 | "! TARGET_POWER && ! TARGET_POWERPC64" |
bdf423cb MM |
4071 | "@ |
4072 | mr. %1,%1 | |
9ebbca7d GK |
4073 | {sr|srw}%I2. %3,%1,%h2 |
4074 | # | |
4075 | #" | |
4076 | [(set_attr "type" "delayed_compare") | |
4077 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 4078 | |
9ebbca7d GK |
4079 | (define_split |
4080 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4081 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4082 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4083 | (const_int 0))) | |
4084 | (clobber (match_scratch:SI 3 ""))] | |
4085 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4086 | [(set (match_dup 3) | |
4087 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4088 | (set (match_dup 0) | |
4089 | (compare:CC (match_dup 3) | |
4090 | (const_int 0)))] | |
4091 | "") | |
4092 | ||
4093 | (define_insn "" | |
4094 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
4095 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4096 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4097 | (const_int 0))) |
9ebbca7d | 4098 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 4099 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4100 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 4101 | "TARGET_POWER" |
1fd4e8c1 | 4102 | "@ |
29ae5b89 JL |
4103 | sre. %0,%1,%2 |
4104 | mr. %0,%1 | |
9ebbca7d GK |
4105 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
4106 | # | |
4107 | # | |
4108 | #" | |
4109 | [(set_attr "type" "delayed_compare") | |
4110 | (set_attr "length" "4,4,4,8,8,8")]) | |
4111 | ||
4112 | (define_split | |
4113 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4114 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4115 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4116 | (const_int 0))) | |
4117 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4118 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4119 | (clobber (match_scratch:SI 4 ""))] | |
4120 | "TARGET_POWER && reload_completed" | |
4121 | [(parallel [(set (match_dup 0) | |
4122 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4123 | (clobber (match_dup 4))]) | |
4124 | (set (match_dup 3) | |
4125 | (compare:CC (match_dup 0) | |
4126 | (const_int 0)))] | |
4127 | "") | |
ca7f5001 RK |
4128 | |
4129 | (define_insn "" | |
9ebbca7d GK |
4130 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4131 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4132 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 4133 | (const_int 0))) |
9ebbca7d | 4134 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 4135 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 4136 | "! TARGET_POWER && ! TARGET_POWERPC64" |
29ae5b89 JL |
4137 | "@ |
4138 | mr. %0,%1 | |
9ebbca7d GK |
4139 | {sr|srw}%I2. %0,%1,%h2 |
4140 | # | |
4141 | #" | |
4142 | [(set_attr "type" "delayed_compare") | |
4143 | (set_attr "length" "4,4,8,8")]) | |
4144 | ||
4145 | (define_split | |
4146 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4147 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4148 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4149 | (const_int 0))) | |
4150 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4151 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4152 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4153 | [(set (match_dup 0) | |
4154 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4155 | (set (match_dup 3) | |
4156 | (compare:CC (match_dup 0) | |
4157 | (const_int 0)))] | |
4158 | "") | |
1fd4e8c1 RK |
4159 | |
4160 | (define_insn "" | |
cd2b37d9 RK |
4161 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4162 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4163 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 4164 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 4165 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 4166 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
4167 | |
4168 | (define_insn "" | |
9ebbca7d | 4169 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4170 | (compare:CC |
9ebbca7d GK |
4171 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4172 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4173 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4174 | (const_int 0))) |
9ebbca7d | 4175 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 4176 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4177 | "@ |
4178 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
4179 | #" | |
4180 | [(set_attr "type" "delayed_compare") | |
4181 | (set_attr "length" "4,8")]) | |
4182 | ||
4183 | (define_split | |
4184 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4185 | (compare:CC | |
4186 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4187 | (match_operand:SI 2 "const_int_operand" "")) | |
4188 | (match_operand:SI 3 "mask_operand" "")) | |
4189 | (const_int 0))) | |
4190 | (clobber (match_scratch:SI 4 ""))] | |
4191 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" | |
4192 | [(set (match_dup 4) | |
4193 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
4194 | (match_dup 3))) | |
4195 | (set (match_dup 0) | |
4196 | (compare:CC (match_dup 4) | |
4197 | (const_int 0)))] | |
4198 | "") | |
1fd4e8c1 RK |
4199 | |
4200 | (define_insn "" | |
9ebbca7d | 4201 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4202 | (compare:CC |
9ebbca7d GK |
4203 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4204 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4205 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4206 | (const_int 0))) |
9ebbca7d | 4207 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4208 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 4209 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4210 | "@ |
4211 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
4212 | #" | |
4213 | [(set_attr "type" "delayed_compare") | |
4214 | (set_attr "length" "4,8")]) | |
4215 | ||
4216 | (define_split | |
4217 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4218 | (compare:CC | |
4219 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4220 | (match_operand:SI 2 "const_int_operand" "")) | |
4221 | (match_operand:SI 3 "mask_operand" "")) | |
4222 | (const_int 0))) | |
4223 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4224 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4225 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" | |
4226 | [(set (match_dup 0) | |
4227 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4228 | (set (match_dup 4) | |
4229 | (compare:CC (match_dup 0) | |
4230 | (const_int 0)))] | |
4231 | "") | |
1fd4e8c1 RK |
4232 | |
4233 | (define_insn "" | |
cd2b37d9 | 4234 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4235 | (zero_extend:SI |
4236 | (subreg:QI | |
cd2b37d9 | 4237 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4238 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4239 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4240 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4241 | |
4242 | (define_insn "" | |
9ebbca7d | 4243 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4244 | (compare:CC |
4245 | (zero_extend:SI | |
4246 | (subreg:QI | |
9ebbca7d GK |
4247 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4248 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4249 | (const_int 0))) |
9ebbca7d | 4250 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4251 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4252 | "@ |
4253 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4254 | #" | |
4255 | [(set_attr "type" "delayed_compare") | |
4256 | (set_attr "length" "4,8")]) | |
4257 | ||
4258 | (define_split | |
4259 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4260 | (compare:CC | |
4261 | (zero_extend:SI | |
4262 | (subreg:QI | |
4263 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4264 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4265 | (const_int 0))) | |
4266 | (clobber (match_scratch:SI 3 ""))] | |
4267 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4268 | [(set (match_dup 3) | |
4269 | (zero_extend:SI (subreg:QI | |
4270 | (lshiftrt:SI (match_dup 1) | |
4271 | (match_dup 2)) 0))) | |
4272 | (set (match_dup 0) | |
4273 | (compare:CC (match_dup 3) | |
4274 | (const_int 0)))] | |
4275 | "") | |
1fd4e8c1 RK |
4276 | |
4277 | (define_insn "" | |
9ebbca7d | 4278 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4279 | (compare:CC |
4280 | (zero_extend:SI | |
4281 | (subreg:QI | |
9ebbca7d GK |
4282 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4283 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4284 | (const_int 0))) |
9ebbca7d | 4285 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4286 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4287 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4288 | "@ |
4289 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4290 | #" | |
4291 | [(set_attr "type" "delayed_compare") | |
4292 | (set_attr "length" "4,8")]) | |
4293 | ||
4294 | (define_split | |
4295 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4296 | (compare:CC | |
4297 | (zero_extend:SI | |
4298 | (subreg:QI | |
4299 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4300 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4301 | (const_int 0))) | |
4302 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4303 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4304 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4305 | [(set (match_dup 0) | |
4306 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4307 | (set (match_dup 3) | |
4308 | (compare:CC (match_dup 0) | |
4309 | (const_int 0)))] | |
4310 | "") | |
1fd4e8c1 RK |
4311 | |
4312 | (define_insn "" | |
cd2b37d9 | 4313 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4314 | (zero_extend:SI |
4315 | (subreg:HI | |
cd2b37d9 | 4316 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4317 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4318 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4319 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4320 | |
4321 | (define_insn "" | |
9ebbca7d | 4322 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4323 | (compare:CC |
4324 | (zero_extend:SI | |
4325 | (subreg:HI | |
9ebbca7d GK |
4326 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4327 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4328 | (const_int 0))) |
9ebbca7d | 4329 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4330 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4331 | "@ |
4332 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4333 | #" | |
4334 | [(set_attr "type" "delayed_compare") | |
4335 | (set_attr "length" "4,8")]) | |
4336 | ||
4337 | (define_split | |
4338 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4339 | (compare:CC | |
4340 | (zero_extend:SI | |
4341 | (subreg:HI | |
4342 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4343 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4344 | (const_int 0))) | |
4345 | (clobber (match_scratch:SI 3 ""))] | |
4346 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4347 | [(set (match_dup 3) | |
4348 | (zero_extend:SI (subreg:HI | |
4349 | (lshiftrt:SI (match_dup 1) | |
4350 | (match_dup 2)) 0))) | |
4351 | (set (match_dup 0) | |
4352 | (compare:CC (match_dup 3) | |
4353 | (const_int 0)))] | |
4354 | "") | |
1fd4e8c1 RK |
4355 | |
4356 | (define_insn "" | |
9ebbca7d | 4357 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4358 | (compare:CC |
4359 | (zero_extend:SI | |
4360 | (subreg:HI | |
9ebbca7d GK |
4361 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4362 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4363 | (const_int 0))) |
9ebbca7d | 4364 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4365 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4366 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4367 | "@ |
4368 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4369 | #" | |
4370 | [(set_attr "type" "delayed_compare") | |
4371 | (set_attr "length" "4,8")]) | |
4372 | ||
4373 | (define_split | |
4374 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4375 | (compare:CC | |
4376 | (zero_extend:SI | |
4377 | (subreg:HI | |
4378 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4379 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4380 | (const_int 0))) | |
4381 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4382 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4383 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4384 | [(set (match_dup 0) | |
4385 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4386 | (set (match_dup 3) | |
4387 | (compare:CC (match_dup 0) | |
4388 | (const_int 0)))] | |
4389 | "") | |
1fd4e8c1 RK |
4390 | |
4391 | (define_insn "" | |
cd2b37d9 | 4392 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4393 | (const_int 1) |
cd2b37d9 RK |
4394 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4395 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4396 | (const_int 31)))] |
ca7f5001 | 4397 | "TARGET_POWER" |
1fd4e8c1 RK |
4398 | "rrib %0,%1,%2") |
4399 | ||
4400 | (define_insn "" | |
cd2b37d9 | 4401 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4402 | (const_int 1) |
cd2b37d9 RK |
4403 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4404 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4405 | (const_int 31)))] |
ca7f5001 | 4406 | "TARGET_POWER" |
1fd4e8c1 RK |
4407 | "rrib %0,%1,%2") |
4408 | ||
4409 | (define_insn "" | |
cd2b37d9 | 4410 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4411 | (const_int 1) |
cd2b37d9 RK |
4412 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4413 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4414 | (const_int 1) |
4415 | (const_int 0)))] | |
ca7f5001 | 4416 | "TARGET_POWER" |
1fd4e8c1 RK |
4417 | "rrib %0,%1,%2") |
4418 | ||
ca7f5001 RK |
4419 | (define_expand "ashrsi3" |
4420 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4421 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4422 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4423 | "" | |
4424 | " | |
4425 | { | |
4426 | if (TARGET_POWER) | |
4427 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4428 | else | |
25c341fa | 4429 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4430 | DONE; |
4431 | }") | |
4432 | ||
4433 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4434 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4435 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4436 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4437 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4438 | "TARGET_POWER" |
1fd4e8c1 RK |
4439 | "@ |
4440 | srea %0,%1,%2 | |
ca7f5001 RK |
4441 | {srai|srawi} %0,%1,%h2") |
4442 | ||
25c341fa | 4443 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4444 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4445 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4446 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4447 | "! TARGET_POWER" |
d904e9ed | 4448 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4449 | |
4450 | (define_insn "" | |
9ebbca7d GK |
4451 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4452 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4453 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4454 | (const_int 0))) |
9ebbca7d GK |
4455 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4456 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4457 | "TARGET_POWER" |
1fd4e8c1 RK |
4458 | "@ |
4459 | srea. %3,%1,%2 | |
9ebbca7d GK |
4460 | {srai.|srawi.} %3,%1,%h2 |
4461 | # | |
4462 | #" | |
4463 | [(set_attr "type" "delayed_compare") | |
4464 | (set_attr "length" "4,4,8,8")]) | |
4465 | ||
4466 | (define_split | |
4467 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4468 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4469 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4470 | (const_int 0))) | |
4471 | (clobber (match_scratch:SI 3 "")) | |
4472 | (clobber (match_scratch:SI 4 ""))] | |
4473 | "TARGET_POWER && reload_completed" | |
4474 | [(parallel [(set (match_dup 3) | |
4475 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4476 | (clobber (match_dup 4))]) | |
4477 | (set (match_dup 0) | |
4478 | (compare:CC (match_dup 3) | |
4479 | (const_int 0)))] | |
4480 | "") | |
ca7f5001 RK |
4481 | |
4482 | (define_insn "" | |
9ebbca7d GK |
4483 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4484 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4485 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4486 | (const_int 0))) |
9ebbca7d | 4487 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4488 | "! TARGET_POWER" |
9ebbca7d GK |
4489 | "@ |
4490 | {sra|sraw}%I2. %3,%1,%h2 | |
4491 | #" | |
4492 | [(set_attr "type" "delayed_compare") | |
4493 | (set_attr "length" "4,8")]) | |
4494 | ||
4495 | (define_split | |
4496 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4497 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4498 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4499 | (const_int 0))) | |
4500 | (clobber (match_scratch:SI 3 ""))] | |
4501 | "! TARGET_POWER && reload_completed" | |
4502 | [(set (match_dup 3) | |
4503 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4504 | (set (match_dup 0) | |
4505 | (compare:CC (match_dup 3) | |
4506 | (const_int 0)))] | |
4507 | "") | |
1fd4e8c1 RK |
4508 | |
4509 | (define_insn "" | |
9ebbca7d GK |
4510 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4511 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4512 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4513 | (const_int 0))) |
9ebbca7d | 4514 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4515 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4516 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4517 | "TARGET_POWER" |
1fd4e8c1 RK |
4518 | "@ |
4519 | srea. %0,%1,%2 | |
9ebbca7d GK |
4520 | {srai.|srawi.} %0,%1,%h2 |
4521 | # | |
4522 | #" | |
4523 | [(set_attr "type" "delayed_compare") | |
4524 | (set_attr "length" "4,4,8,8")]) | |
4525 | ||
4526 | (define_split | |
4527 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4528 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4529 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4530 | (const_int 0))) | |
4531 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4532 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4533 | (clobber (match_scratch:SI 4 ""))] | |
4534 | "TARGET_POWER && reload_completed" | |
4535 | [(parallel [(set (match_dup 0) | |
4536 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4537 | (clobber (match_dup 4))]) | |
4538 | (set (match_dup 3) | |
4539 | (compare:CC (match_dup 0) | |
4540 | (const_int 0)))] | |
4541 | "") | |
1fd4e8c1 | 4542 | |
ca7f5001 | 4543 | (define_insn "" |
9ebbca7d GK |
4544 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4545 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4546 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4547 | (const_int 0))) |
9ebbca7d | 4548 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4549 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4550 | "! TARGET_POWER" |
9ebbca7d GK |
4551 | "@ |
4552 | {sra|sraw}%I2. %0,%1,%h2 | |
4553 | #" | |
4554 | [(set_attr "type" "delayed_compare") | |
4555 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4556 | \f |
9ebbca7d GK |
4557 | (define_split |
4558 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4559 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4560 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4561 | (const_int 0))) | |
4562 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4563 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4564 | "! TARGET_POWER && reload_completed" | |
4565 | [(set (match_dup 0) | |
4566 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4567 | (set (match_dup 3) | |
4568 | (compare:CC (match_dup 0) | |
4569 | (const_int 0)))] | |
4570 | "") | |
4571 | ||
1fd4e8c1 RK |
4572 | ;; Floating-point insns, excluding normal data motion. |
4573 | ;; | |
ca7f5001 RK |
4574 | ;; PowerPC has a full set of single-precision floating point instructions. |
4575 | ;; | |
4576 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4577 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4578 | ;; The only conversions we will do will be when storing to memory. In that | |
4579 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4580 | ;; |
4581 | ;; Note that when we store into a single-precision memory location, we need to | |
4582 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4583 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4584 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4585 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4586 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4587 | ||
e8112008 | 4588 | (define_insn "extendsfdf2" |
cd2b37d9 | 4589 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
e8112008 | 4590 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] |
d14a6d05 | 4591 | "TARGET_HARD_FLOAT" |
e8112008 | 4592 | "* |
5c30aff8 | 4593 | { |
e8112008 RK |
4594 | if (REGNO (operands[0]) == REGNO (operands[1])) |
4595 | return \"\"; | |
4596 | else | |
4597 | return \"fmr %0,%1\"; | |
4598 | }" | |
4599 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4600 | |
4601 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
4602 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4603 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4604 | "TARGET_HARD_FLOAT" |
dcac138d | 4605 | "frsp %0,%1" |
1fd4e8c1 RK |
4606 | [(set_attr "type" "fp")]) |
4607 | ||
455350f4 RK |
4608 | (define_insn "aux_truncdfsf2" |
4609 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4610 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))] | |
4611 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" | |
4612 | "frsp %0,%1" | |
4613 | [(set_attr "type" "fp")]) | |
4614 | ||
1fd4e8c1 | 4615 | (define_insn "negsf2" |
cd2b37d9 RK |
4616 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4617 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4618 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4619 | "fneg %0,%1" |
4620 | [(set_attr "type" "fp")]) | |
4621 | ||
4622 | (define_insn "abssf2" | |
cd2b37d9 RK |
4623 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4624 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4625 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4626 | "fabs %0,%1" |
4627 | [(set_attr "type" "fp")]) | |
4628 | ||
4629 | (define_insn "" | |
cd2b37d9 RK |
4630 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4631 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 4632 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4633 | "fnabs %0,%1" |
4634 | [(set_attr "type" "fp")]) | |
4635 | ||
ca7f5001 RK |
4636 | (define_expand "addsf3" |
4637 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4638 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4639 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4640 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4641 | "") |
4642 | ||
4643 | (define_insn "" | |
cd2b37d9 RK |
4644 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4645 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4646 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4647 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4648 | "fadds %0,%1,%2" |
ca7f5001 RK |
4649 | [(set_attr "type" "fp")]) |
4650 | ||
4651 | (define_insn "" | |
4652 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4653 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4654 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4655 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4656 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4657 | [(set_attr "type" "fp")]) |
4658 | ||
4659 | (define_expand "subsf3" | |
4660 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4661 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4662 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4663 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4664 | "") |
4665 | ||
4666 | (define_insn "" | |
4667 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4668 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4669 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4670 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4671 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4672 | [(set_attr "type" "fp")]) |
4673 | ||
ca7f5001 | 4674 | (define_insn "" |
cd2b37d9 RK |
4675 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4676 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4677 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4678 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4679 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4680 | [(set_attr "type" "fp")]) |
4681 | ||
4682 | (define_expand "mulsf3" | |
4683 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4684 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4685 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4686 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4687 | "") |
4688 | ||
4689 | (define_insn "" | |
4690 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4691 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4692 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4693 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4694 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4695 | [(set_attr "type" "fp")]) |
4696 | ||
ca7f5001 | 4697 | (define_insn "" |
cd2b37d9 RK |
4698 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4699 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4700 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4701 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4702 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4703 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4704 | |
ca7f5001 RK |
4705 | (define_expand "divsf3" |
4706 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4707 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4708 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4709 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4710 | "") |
4711 | ||
4712 | (define_insn "" | |
cd2b37d9 RK |
4713 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4714 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4715 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4716 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4717 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4718 | [(set_attr "type" "sdiv")]) |
4719 | ||
4720 | (define_insn "" | |
4721 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4722 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4723 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4724 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4725 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4726 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4727 | |
4728 | (define_insn "" | |
cd2b37d9 RK |
4729 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4730 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4731 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4732 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4733 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4734 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4735 | [(set_attr "type" "fp")]) |
4736 | ||
4737 | (define_insn "" | |
4738 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4739 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4740 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4741 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4742 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4743 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4744 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4745 | |
4746 | (define_insn "" | |
cd2b37d9 RK |
4747 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4748 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4749 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4750 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4751 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4752 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4753 | [(set_attr "type" "fp")]) |
4754 | ||
4755 | (define_insn "" | |
4756 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4757 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4758 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4759 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4760 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4761 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4762 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4763 | |
4764 | (define_insn "" | |
cd2b37d9 RK |
4765 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4766 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4767 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4768 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4769 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4770 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4771 | [(set_attr "type" "fp")]) |
4772 | ||
4773 | (define_insn "" | |
4774 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4775 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4776 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4777 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4778 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4779 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4780 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4781 | |
4782 | (define_insn "" | |
cd2b37d9 RK |
4783 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4784 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4785 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4786 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4787 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4788 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4789 | [(set_attr "type" "fp")]) |
4790 | ||
4791 | (define_insn "" | |
4792 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4793 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4794 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4795 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4796 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4797 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 4798 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4799 | |
ca7f5001 RK |
4800 | (define_expand "sqrtsf2" |
4801 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4802 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 4803 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4804 | "") |
4805 | ||
4806 | (define_insn "" | |
4807 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4808 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4809 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4810 | "fsqrts %0,%1" |
4811 | [(set_attr "type" "ssqrt")]) | |
4812 | ||
4813 | (define_insn "" | |
4814 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4815 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4816 | "TARGET_POWER2 && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4817 | "fsqrt %0,%1" |
4818 | [(set_attr "type" "dsqrt")]) | |
4819 | ||
94d7001a RK |
4820 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4821 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4822 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
4823 | ;; combine. |
4824 | (define_expand "maxsf3" | |
8e871c05 | 4825 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4826 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
4827 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4828 | (match_dup 1) |
4829 | (match_dup 2)))] | |
50a0b056 GK |
4830 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
4831 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") | |
2f607b94 | 4832 | |
8e871c05 | 4833 | (define_expand "minsf3" |
50a0b056 GK |
4834 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
4835 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
4836 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
4837 | (match_dup 2) | |
4838 | (match_dup 1)))] | |
d14a6d05 | 4839 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 | 4840 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 4841 | |
8e871c05 RK |
4842 | (define_split |
4843 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4844 | (match_operator:SF 3 "min_max_operator" |
4845 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
4846 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
d14a6d05 | 4847 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 GK |
4848 | [(const_int 0)] |
4849 | " | |
4850 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
4851 | operands[1], operands[2]); | |
4852 | DONE; | |
4853 | }") | |
2f607b94 | 4854 | |
94d7001a | 4855 | (define_expand "movsfcc" |
0ad91047 | 4856 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 4857 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4858 | (match_operand:SF 2 "gpc_reg_operand" "") |
4859 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 4860 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
4861 | " |
4862 | { | |
50a0b056 GK |
4863 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4864 | DONE; | |
94d7001a | 4865 | else |
50a0b056 | 4866 | FAIL; |
94d7001a | 4867 | }") |
d56d506a | 4868 | |
50a0b056 | 4869 | (define_insn "*fselsfsf4" |
8e871c05 RK |
4870 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4871 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4872 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4873 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4874 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4875 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4876 | "fsel %0,%1,%2,%3" |
4877 | [(set_attr "type" "fp")]) | |
2f607b94 | 4878 | |
50a0b056 | 4879 | (define_insn "*fseldfsf4" |
94d7001a RK |
4880 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4881 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 4882 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4883 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4884 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4885 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
4886 | "fsel %0,%1,%2,%3" |
4887 | [(set_attr "type" "fp")]) | |
d56d506a | 4888 | |
1fd4e8c1 | 4889 | (define_insn "negdf2" |
cd2b37d9 RK |
4890 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4891 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4892 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4893 | "fneg %0,%1" |
4894 | [(set_attr "type" "fp")]) | |
4895 | ||
4896 | (define_insn "absdf2" | |
cd2b37d9 RK |
4897 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4898 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4899 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4900 | "fabs %0,%1" |
4901 | [(set_attr "type" "fp")]) | |
4902 | ||
4903 | (define_insn "" | |
cd2b37d9 RK |
4904 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4905 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 4906 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4907 | "fnabs %0,%1" |
4908 | [(set_attr "type" "fp")]) | |
4909 | ||
4910 | (define_insn "adddf3" | |
cd2b37d9 RK |
4911 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4912 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4913 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4914 | "TARGET_HARD_FLOAT" |
ca7f5001 | 4915 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
4916 | [(set_attr "type" "fp")]) |
4917 | ||
4918 | (define_insn "subdf3" | |
cd2b37d9 RK |
4919 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4920 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4921 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4922 | "TARGET_HARD_FLOAT" |
ca7f5001 | 4923 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
4924 | [(set_attr "type" "fp")]) |
4925 | ||
4926 | (define_insn "muldf3" | |
cd2b37d9 RK |
4927 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4928 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4929 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4930 | "TARGET_HARD_FLOAT" |
ca7f5001 | 4931 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 4932 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4933 | |
4934 | (define_insn "divdf3" | |
cd2b37d9 RK |
4935 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4936 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4937 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4938 | "TARGET_HARD_FLOAT" |
ca7f5001 | 4939 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 4940 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4941 | |
4942 | (define_insn "" | |
cd2b37d9 RK |
4943 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4944 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4945 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4946 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 4947 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 4948 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 4949 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4950 | |
4951 | (define_insn "" | |
cd2b37d9 RK |
4952 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4953 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4954 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4955 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 4956 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 4957 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 4958 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4959 | |
4960 | (define_insn "" | |
cd2b37d9 RK |
4961 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4962 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4963 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4964 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 4965 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 4966 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 4967 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4968 | |
4969 | (define_insn "" | |
cd2b37d9 RK |
4970 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4971 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4972 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4973 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 4974 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 4975 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 4976 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
4977 | |
4978 | (define_insn "sqrtdf2" | |
4979 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4980 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4981 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4982 | "fsqrt %0,%1" |
4983 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 4984 | |
50a0b056 GK |
4985 | ;; The conditional move instructions allow us to perform max and min |
4986 | ;; operations even when | |
b77dfefc | 4987 | |
8e871c05 | 4988 | (define_expand "maxdf3" |
8e871c05 | 4989 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4990 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
4991 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4992 | (match_dup 1) |
4993 | (match_dup 2)))] | |
50a0b056 GK |
4994 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
4995 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") | |
b77dfefc | 4996 | |
8e871c05 | 4997 | (define_expand "mindf3" |
50a0b056 GK |
4998 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
4999 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
5000 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
5001 | (match_dup 2) | |
5002 | (match_dup 1)))] | |
d14a6d05 | 5003 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 | 5004 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 5005 | |
8e871c05 RK |
5006 | (define_split |
5007 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
5008 | (match_operator:DF 3 "min_max_operator" |
5009 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
5010 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
d14a6d05 | 5011 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
50a0b056 GK |
5012 | [(const_int 0)] |
5013 | " | |
5014 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), | |
5015 | operands[1], operands[2]); | |
5016 | DONE; | |
5017 | }") | |
b77dfefc | 5018 | |
94d7001a | 5019 | (define_expand "movdfcc" |
0ad91047 | 5020 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 5021 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5022 | (match_operand:DF 2 "gpc_reg_operand" "") |
5023 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 5024 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
5025 | " |
5026 | { | |
50a0b056 GK |
5027 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5028 | DONE; | |
94d7001a | 5029 | else |
50a0b056 | 5030 | FAIL; |
94d7001a | 5031 | }") |
d56d506a | 5032 | |
50a0b056 | 5033 | (define_insn "*fseldfdf4" |
8e871c05 RK |
5034 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5035 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5036 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5037 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5038 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5039 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5040 | "fsel %0,%1,%2,%3" |
5041 | [(set_attr "type" "fp")]) | |
d56d506a | 5042 | |
50a0b056 | 5043 | (define_insn "*fselsfdf4" |
94d7001a RK |
5044 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5045 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5046 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5047 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5048 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5049 | "TARGET_PPC_GFXOPT" | |
5050 | "fsel %0,%1,%2,%3" | |
5051 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5052 | \f |
5053 | ;; Conversions to and from floating-point. | |
802a0058 | 5054 | |
9ebbca7d GK |
5055 | ; For each of these conversions, there is a define_expand, a define_insn |
5056 | ; with a '#' template, and a define_split (with C code). The idea is | |
5057 | ; to allow constant folding with the template of the define_insn, | |
5058 | ; then to have the insns split later (between sched1 and final). | |
5059 | ||
1fd4e8c1 | 5060 | (define_expand "floatsidf2" |
802a0058 MM |
5061 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5062 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5063 | (use (match_dup 2)) | |
5064 | (use (match_dup 3)) | |
208c89ce | 5065 | (clobber (match_dup 4)) |
a7df97e6 | 5066 | (clobber (match_dup 5)) |
9ebbca7d | 5067 | (clobber (match_dup 6))])] |
31bfaa0b | 5068 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5069 | " |
5070 | { | |
802a0058 MM |
5071 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5072 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); | |
9ebbca7d GK |
5073 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5074 | operands[5] = gen_reg_rtx (DFmode); | |
5075 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5076 | }") |
5077 | ||
802a0058 MM |
5078 | (define_insn "*floatsidf2_internal" |
5079 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5080 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5081 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5082 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d GK |
5083 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
5084 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=f")) | |
5085 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=r"))] | |
31bfaa0b | 5086 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 5087 | "#" |
a7df97e6 | 5088 | [(set_attr "length" "24")]) |
802a0058 MM |
5089 | |
5090 | (define_split | |
dbe3df29 | 5091 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
5092 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
5093 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5094 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5095 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5096 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5097 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
31bfaa0b | 5098 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5099 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5100 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5101 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5102 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5103 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5104 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5105 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
208c89ce MM |
5106 | " |
5107 | { | |
9ebbca7d GK |
5108 | rtx lowword, highword; |
5109 | if (GET_CODE (operands[4]) != MEM) | |
5110 | abort(); | |
5111 | highword = XEXP (operands[4], 0); | |
5112 | lowword = plus_constant (highword, 4); | |
5113 | if (! WORDS_BIG_ENDIAN) | |
5114 | { | |
5115 | rtx tmp; | |
5116 | tmp = highword; highword = lowword; lowword = tmp; | |
5117 | } | |
5118 | ||
5119 | emit_insn (gen_xorsi3 (operands[6], operands[1], | |
5120 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); | |
5121 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); | |
5122 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5123 | emit_move_insn (operands[5], operands[4]); | |
5124 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5125 | DONE; | |
208c89ce | 5126 | }") |
802a0058 MM |
5127 | |
5128 | (define_expand "floatunssidf2" | |
5129 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5130 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5131 | (use (match_dup 2)) | |
5132 | (use (match_dup 3)) | |
a7df97e6 | 5133 | (clobber (match_dup 4)) |
9ebbca7d | 5134 | (clobber (match_dup 5))])] |
31bfaa0b | 5135 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5136 | " |
5137 | { | |
802a0058 MM |
5138 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5139 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode)); | |
9ebbca7d GK |
5140 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5141 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5142 | }") |
5143 | ||
802a0058 MM |
5144 | (define_insn "*floatunssidf2_internal" |
5145 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5146 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5147 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5148 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d GK |
5149 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
5150 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))] | |
31bfaa0b | 5151 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 5152 | "#" |
a7df97e6 | 5153 | [(set_attr "length" "20")]) |
802a0058 MM |
5154 | |
5155 | (define_split | |
5156 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5157 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5158 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5159 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5160 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5161 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
31bfaa0b | 5162 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5163 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5164 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5165 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5166 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5167 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5168 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
5169 | " | |
802a0058 | 5170 | { |
9ebbca7d GK |
5171 | rtx lowword, highword; |
5172 | if (GET_CODE (operands[4]) != MEM) | |
5173 | abort(); | |
5174 | highword = XEXP (operands[4], 0); | |
5175 | lowword = plus_constant (highword, 4); | |
5176 | if (! WORDS_BIG_ENDIAN) | |
f6968f59 | 5177 | { |
9ebbca7d GK |
5178 | rtx tmp; |
5179 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5180 | } |
802a0058 | 5181 | |
9ebbca7d GK |
5182 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); |
5183 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5184 | emit_move_insn (operands[5], operands[4]); | |
5185 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5186 | DONE; | |
5187 | }") | |
1fd4e8c1 | 5188 | |
1fd4e8c1 | 5189 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
5190 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5191 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5192 | (clobber (match_dup 2)) | |
9ebbca7d | 5193 | (clobber (match_dup 3))])] |
9cb8fcaf | 5194 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5195 | " |
5196 | { | |
802a0058 | 5197 | operands[2] = gen_reg_rtx (DImode); |
9ebbca7d | 5198 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5199 | }") |
5200 | ||
802a0058 MM |
5201 | (define_insn "*fix_truncdfsi2_internal" |
5202 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5203 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5204 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) | |
9ebbca7d | 5205 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
9cb8fcaf | 5206 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
802a0058 | 5207 | "#" |
9ebbca7d | 5208 | [(set_attr "length" "16")]) |
802a0058 MM |
5209 | |
5210 | (define_split | |
5211 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5212 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5213 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) | |
9ebbca7d | 5214 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] |
9cb8fcaf | 5215 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5216 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5217 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5218 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) | |
5219 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] | |
5220 | " | |
802a0058 | 5221 | { |
9ebbca7d GK |
5222 | rtx lowword; |
5223 | if (GET_CODE (operands[3]) != MEM) | |
5224 | abort(); | |
5225 | lowword = XEXP (operands[3], 0); | |
5226 | if (WORDS_BIG_ENDIAN) | |
5227 | lowword = plus_constant (lowword, 4); | |
802a0058 | 5228 | |
9ebbca7d GK |
5229 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5230 | emit_move_insn (operands[3], operands[2]); | |
5231 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
5232 | DONE; | |
5233 | }") | |
802a0058 | 5234 | |
9ebbca7d GK |
5235 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10)) |
5236 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) | |
5237 | ; because the first makes it clear that operand 0 is not live | |
5238 | ; before the instruction. | |
5239 | (define_insn "fctiwz" | |
5240 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
5241 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))] | |
a260abc9 DE |
5242 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
5243 | "{fcirz|fctiwz} %0,%1" | |
5244 | [(set_attr "type" "fp")]) | |
5245 | ||
a473029f RK |
5246 | (define_insn "floatdidf2" |
5247 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5248 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5249 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
5250 | "fcfid %0,%1" |
5251 | [(set_attr "type" "fp")]) | |
5252 | ||
5253 | (define_insn "fix_truncdfdi2" | |
5254 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
5255 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5256 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
5257 | "fctidz %0,%1" |
5258 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5259 | \f |
5260 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5261 | ;; of instructions. The & constraints are to prevent the register |
5262 | ;; allocator from allocating registers that overlap with the inputs | |
5263 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5264 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5265 | |
266eb58a | 5266 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5267 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5268 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5269 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5270 | "! TARGET_POWERPC64" |
0f645302 MM |
5271 | "* |
5272 | { | |
5273 | if (WORDS_BIG_ENDIAN) | |
5274 | return (GET_CODE (operands[2])) != CONST_INT | |
5275 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5276 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5277 | else | |
5278 | return (GET_CODE (operands[2])) != CONST_INT | |
5279 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5280 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5281 | }" | |
b19003d8 | 5282 | [(set_attr "length" "8")]) |
1fd4e8c1 | 5283 | |
266eb58a | 5284 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5285 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5286 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5287 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5288 | "! TARGET_POWERPC64" |
5502823b RK |
5289 | "* |
5290 | { | |
0f645302 MM |
5291 | if (WORDS_BIG_ENDIAN) |
5292 | return (GET_CODE (operands[1]) != CONST_INT) | |
5293 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5294 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5295 | else | |
5296 | return (GET_CODE (operands[1]) != CONST_INT) | |
5297 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5298 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5299 | }" |
ca7f5001 RK |
5300 | [(set_attr "length" "8")]) |
5301 | ||
266eb58a | 5302 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5303 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5304 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5305 | "! TARGET_POWERPC64" |
5502823b RK |
5306 | "* |
5307 | { | |
5308 | return (WORDS_BIG_ENDIAN) | |
5309 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5310 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5311 | }" | |
ca7f5001 RK |
5312 | [(set_attr "length" "8")]) |
5313 | ||
8ffd9c51 RK |
5314 | (define_expand "mulsidi3" |
5315 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5316 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5317 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5318 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5319 | " |
5320 | { | |
5321 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5322 | { | |
39403d82 DE |
5323 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5324 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5325 | emit_insn (gen_mull_call ()); |
cf27b467 | 5326 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5327 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5328 | else |
5329 | { | |
5330 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5331 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5332 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5333 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5334 | } |
8ffd9c51 RK |
5335 | DONE; |
5336 | } | |
5337 | else if (TARGET_POWER) | |
5338 | { | |
5339 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5340 | DONE; | |
5341 | } | |
5342 | }") | |
deb9225a | 5343 | |
8ffd9c51 | 5344 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5345 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5346 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5347 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5348 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5349 | "TARGET_POWER" |
b19003d8 | 5350 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5351 | [(set_attr "type" "imul") |
5352 | (set_attr "length" "8")]) | |
deb9225a | 5353 | |
f192bf8b | 5354 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5355 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5356 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5357 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5358 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5359 | "* |
5360 | { | |
5361 | return (WORDS_BIG_ENDIAN) | |
5362 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5363 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5364 | }" | |
8ffd9c51 RK |
5365 | [(set_attr "type" "imul") |
5366 | (set_attr "length" "8")]) | |
deb9225a | 5367 | |
ebedb4dd MM |
5368 | (define_split |
5369 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5370 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5371 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5372 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5373 | [(set (match_dup 3) |
5374 | (truncate:SI | |
5375 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5376 | (sign_extend:DI (match_dup 2))) | |
5377 | (const_int 32)))) | |
5378 | (set (match_dup 4) | |
5379 | (mult:SI (match_dup 1) | |
5380 | (match_dup 2)))] | |
5381 | " | |
5382 | { | |
5383 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5384 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5385 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5386 | }") | |
5387 | ||
f192bf8b DE |
5388 | (define_expand "umulsidi3" |
5389 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5390 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5391 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5392 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5393 | " | |
5394 | { | |
5395 | if (TARGET_POWER) | |
5396 | { | |
5397 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5398 | DONE; | |
5399 | } | |
5400 | }") | |
5401 | ||
5402 | (define_insn "umulsidi3_mq" | |
5403 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5404 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5405 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5406 | (clobber (match_scratch:SI 3 "=q"))] | |
5407 | "TARGET_POWERPC && TARGET_POWER" | |
5408 | "* | |
5409 | { | |
5410 | return (WORDS_BIG_ENDIAN) | |
5411 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5412 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5413 | }" | |
5414 | [(set_attr "type" "imul") | |
5415 | (set_attr "length" "8")]) | |
5416 | ||
5417 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5418 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5419 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5420 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5421 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5422 | "* |
5423 | { | |
5424 | return (WORDS_BIG_ENDIAN) | |
5425 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5426 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5427 | }" | |
5428 | [(set_attr "type" "imul") | |
5429 | (set_attr "length" "8")]) | |
5430 | ||
ebedb4dd MM |
5431 | (define_split |
5432 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5433 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5434 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5435 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5436 | [(set (match_dup 3) |
5437 | (truncate:SI | |
5438 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5439 | (zero_extend:DI (match_dup 2))) | |
5440 | (const_int 32)))) | |
5441 | (set (match_dup 4) | |
5442 | (mult:SI (match_dup 1) | |
5443 | (match_dup 2)))] | |
5444 | " | |
5445 | { | |
5446 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5447 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5448 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5449 | }") | |
5450 | ||
8ffd9c51 RK |
5451 | (define_expand "smulsi3_highpart" |
5452 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5453 | (truncate:SI | |
5454 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5455 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5456 | (sign_extend:DI | |
5457 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5458 | (const_int 32))))] | |
5459 | "" | |
5460 | " | |
5461 | { | |
5462 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5463 | { | |
39403d82 DE |
5464 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5465 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5466 | emit_insn (gen_mulh_call ()); |
39403d82 | 5467 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5468 | DONE; |
5469 | } | |
5470 | else if (TARGET_POWER) | |
5471 | { | |
5472 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5473 | DONE; | |
5474 | } | |
5475 | }") | |
deb9225a | 5476 | |
8ffd9c51 RK |
5477 | (define_insn "smulsi3_highpart_mq" |
5478 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5479 | (truncate:SI | |
fada905b MM |
5480 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5481 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5482 | (sign_extend:DI | |
5483 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5484 | (const_int 32)))) |
5485 | (clobber (match_scratch:SI 3 "=q"))] | |
5486 | "TARGET_POWER" | |
5487 | "mul %0,%1,%2" | |
5488 | [(set_attr "type" "imul")]) | |
deb9225a | 5489 | |
f192bf8b | 5490 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5491 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5492 | (truncate:SI | |
fada905b MM |
5493 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5494 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5495 | (sign_extend:DI | |
5496 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5497 | (const_int 32))))] |
f192bf8b | 5498 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5499 | "mulhw %0,%1,%2" |
5500 | [(set_attr "type" "imul")]) | |
deb9225a | 5501 | |
f192bf8b DE |
5502 | (define_expand "umulsi3_highpart" |
5503 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5504 | (truncate:SI | |
5505 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5506 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5507 | (zero_extend:DI | |
5508 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5509 | (const_int 32))))] | |
5510 | "TARGET_POWERPC" | |
5511 | " | |
5512 | { | |
5513 | if (TARGET_POWER) | |
5514 | { | |
5515 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5516 | DONE; | |
5517 | } | |
5518 | }") | |
5519 | ||
5520 | (define_insn "umulsi3_highpart_mq" | |
5521 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5522 | (truncate:SI | |
5523 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5524 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5525 | (zero_extend:DI | |
5526 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5527 | (const_int 32)))) | |
5528 | (clobber (match_scratch:SI 3 "=q"))] | |
5529 | "TARGET_POWERPC && TARGET_POWER" | |
5530 | "mulhwu %0,%1,%2" | |
5531 | [(set_attr "type" "imul")]) | |
5532 | ||
5533 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5534 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5535 | (truncate:SI | |
5536 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5537 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5538 | (zero_extend:DI | |
5539 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5540 | (const_int 32))))] | |
f192bf8b | 5541 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5542 | "mulhwu %0,%1,%2" |
5543 | [(set_attr "type" "imul")]) | |
5544 | ||
5545 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5546 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5547 | ;; why we have the strange constraints below. | |
5548 | (define_insn "ashldi3_power" | |
5549 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5550 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5551 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5552 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5553 | "TARGET_POWER" | |
5554 | "@ | |
5555 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5556 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5557 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5558 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5559 | [(set_attr "length" "8")]) | |
5560 | ||
5561 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5562 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5563 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5564 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5565 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5566 | "TARGET_POWER" | |
5567 | "@ | |
47ad8c61 | 5568 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5569 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5570 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5571 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5572 | [(set_attr "length" "8")]) | |
5573 | ||
5574 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5575 | ;; just handle shifts by constants. | |
5576 | (define_insn "ashrdi3_power" | |
7093ddee | 5577 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5578 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5579 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5580 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5581 | "TARGET_POWER" | |
5582 | "@ | |
5583 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5584 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5585 | [(set_attr "length" "8")]) | |
5586 | \f | |
5587 | ;; PowerPC64 DImode operations. | |
5588 | ||
5589 | (define_expand "adddi3" | |
5590 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5591 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 5592 | (match_operand:DI 2 "reg_or_arith_cint_operand" "")))] |
266eb58a DE |
5593 | "" |
5594 | " | |
5595 | { | |
a260abc9 DE |
5596 | if (! TARGET_POWERPC64) |
5597 | { | |
5598 | if (non_short_cint_operand (operands[2], DImode)) | |
5599 | FAIL; | |
5600 | } | |
5601 | else | |
5602 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 5603 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 5604 | { |
677a9668 | 5605 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
5606 | ? operands[0] : gen_reg_rtx (DImode)); |
5607 | ||
5608 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; | |
5609 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
5610 | ||
5611 | if (low & 0x8000) | |
38886f37 AO |
5612 | { |
5613 | high = trunc_int_for_mode (high + 0x10000, SImode); | |
5614 | low = trunc_int_for_mode (low, HImode); | |
5615 | } | |
a260abc9 DE |
5616 | |
5617 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (high))); | |
5618 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); | |
5619 | DONE; | |
5620 | } | |
266eb58a DE |
5621 | }") |
5622 | ||
5623 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
5624 | ;; allowing register zero as source. | |
5625 | ||
a260abc9 | 5626 | (define_insn "*adddi3_internal1" |
266eb58a DE |
5627 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
5628 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 5629 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
5630 | "TARGET_POWERPC64" |
5631 | "@ | |
5632 | add %0,%1,%2 | |
5633 | addi %0,%1,%2 | |
5634 | addic %0,%1,%2 | |
802a0058 | 5635 | addis %0,%1,%v2") |
266eb58a | 5636 | |
a260abc9 | 5637 | (define_insn "*adddi3_internal2" |
9ebbca7d GK |
5638 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
5639 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5640 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5641 | (const_int 0))) |
9ebbca7d | 5642 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
266eb58a DE |
5643 | "TARGET_POWERPC64" |
5644 | "@ | |
5645 | add. %3,%1,%2 | |
9ebbca7d GK |
5646 | addic. %3,%1,%2 |
5647 | # | |
5648 | #" | |
5649 | [(set_attr "type" "compare") | |
5650 | (set_attr "length" "4,4,8,8")]) | |
5651 | ||
5652 | (define_split | |
5653 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5654 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5655 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5656 | (const_int 0))) | |
5657 | (clobber (match_scratch:DI 3 ""))] | |
5658 | "TARGET_POWERPC64 && reload_completed" | |
5659 | [(set (match_dup 3) | |
5660 | (plus:DI (match_dup 1) (match_dup 2))) | |
5661 | (set (match_dup 0) | |
5662 | (compare:CC (match_dup 3) | |
5663 | (const_int 0)))] | |
5664 | "") | |
266eb58a | 5665 | |
a260abc9 | 5666 | (define_insn "*adddi3_internal3" |
9ebbca7d GK |
5667 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
5668 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5669 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5670 | (const_int 0))) |
9ebbca7d | 5671 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
266eb58a DE |
5672 | (plus:DI (match_dup 1) (match_dup 2)))] |
5673 | "TARGET_POWERPC64" | |
5674 | "@ | |
5675 | add. %0,%1,%2 | |
9ebbca7d GK |
5676 | addic. %0,%1,%2 |
5677 | # | |
5678 | #" | |
5679 | [(set_attr "type" "compare") | |
5680 | (set_attr "length" "4,4,8,8")]) | |
5681 | ||
5682 | (define_split | |
5683 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5684 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5685 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5686 | (const_int 0))) | |
5687 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5688 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5689 | "TARGET_POWERPC64 && reload_completed" | |
5690 | [(set (match_dup 0) | |
5691 | (plus:DI (match_dup 1) (match_dup 2))) | |
5692 | (set (match_dup 3) | |
5693 | (compare:CC (match_dup 0) | |
5694 | (const_int 0)))] | |
5695 | "") | |
266eb58a DE |
5696 | |
5697 | ;; Split an add that we can't do in one insn into two insns, each of which | |
5698 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
5699 | ;; add should be last in case the result gets used in an address. | |
5700 | ||
5701 | (define_split | |
5702 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5703 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5704 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
5705 | "TARGET_POWERPC64" | |
5706 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
5707 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
5708 | " | |
5709 | { | |
e6ca2c17 DE |
5710 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; |
5711 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
266eb58a DE |
5712 | |
5713 | if (low & 0x8000) | |
38886f37 AO |
5714 | { |
5715 | high = trunc_int_for_mode (high + 0x10000, SImode); | |
5716 | low = trunc_int_for_mode (low, HImode); | |
5717 | } | |
266eb58a | 5718 | |
e6ca2c17 DE |
5719 | operands[3] = GEN_INT (high); |
5720 | operands[4] = GEN_INT (low); | |
266eb58a DE |
5721 | }") |
5722 | ||
5723 | (define_insn "one_cmpldi2" | |
5724 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5725 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5726 | "TARGET_POWERPC64" | |
5727 | "nor %0,%1,%1") | |
5728 | ||
5729 | (define_insn "" | |
9ebbca7d GK |
5730 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5731 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5732 | (const_int 0))) |
9ebbca7d | 5733 | (clobber (match_scratch:DI 2 "=r,r"))] |
266eb58a | 5734 | "TARGET_POWERPC64" |
9ebbca7d GK |
5735 | "@ |
5736 | nor. %2,%1,%1 | |
5737 | #" | |
5738 | [(set_attr "type" "compare") | |
5739 | (set_attr "length" "4,8")]) | |
5740 | ||
5741 | (define_split | |
5742 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5743 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5744 | (const_int 0))) | |
5745 | (clobber (match_scratch:DI 2 ""))] | |
5746 | "TARGET_POWERPC64 && reload_completed" | |
5747 | [(set (match_dup 2) | |
5748 | (not:DI (match_dup 1))) | |
5749 | (set (match_dup 0) | |
5750 | (compare:CC (match_dup 2) | |
5751 | (const_int 0)))] | |
5752 | "") | |
266eb58a DE |
5753 | |
5754 | (define_insn "" | |
9ebbca7d GK |
5755 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5756 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5757 | (const_int 0))) |
9ebbca7d | 5758 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
5759 | (not:DI (match_dup 1)))] |
5760 | "TARGET_POWERPC64" | |
9ebbca7d GK |
5761 | "@ |
5762 | nor. %0,%1,%1 | |
5763 | #" | |
5764 | [(set_attr "type" "compare") | |
5765 | (set_attr "length" "4,8")]) | |
5766 | ||
5767 | (define_split | |
5768 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5769 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5770 | (const_int 0))) | |
5771 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5772 | (not:DI (match_dup 1)))] | |
5773 | "TARGET_POWERPC64 && reload_completed" | |
5774 | [(set (match_dup 0) | |
5775 | (not:DI (match_dup 1))) | |
5776 | (set (match_dup 2) | |
5777 | (compare:CC (match_dup 0) | |
5778 | (const_int 0)))] | |
5779 | "") | |
266eb58a DE |
5780 | |
5781 | (define_insn "" | |
5782 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5783 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
5784 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
5785 | "TARGET_POWERPC64" | |
5786 | "@ | |
5787 | subf %0,%2,%1 | |
5788 | subfic %0,%2,%1") | |
5789 | ||
5790 | (define_insn "" | |
9ebbca7d GK |
5791 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5792 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5793 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5794 | (const_int 0))) |
9ebbca7d | 5795 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 5796 | "TARGET_POWERPC64" |
9ebbca7d GK |
5797 | "@ |
5798 | subf. %3,%2,%1 | |
5799 | #" | |
5800 | [(set_attr "type" "compare") | |
5801 | (set_attr "length" "4,8")]) | |
5802 | ||
5803 | (define_split | |
5804 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5805 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5806 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5807 | (const_int 0))) | |
5808 | (clobber (match_scratch:DI 3 ""))] | |
5809 | "TARGET_POWERPC64 && reload_completed" | |
5810 | [(set (match_dup 3) | |
5811 | (minus:DI (match_dup 1) (match_dup 2))) | |
5812 | (set (match_dup 0) | |
5813 | (compare:CC (match_dup 3) | |
5814 | (const_int 0)))] | |
5815 | "") | |
266eb58a DE |
5816 | |
5817 | (define_insn "" | |
9ebbca7d GK |
5818 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
5819 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5820 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5821 | (const_int 0))) |
9ebbca7d | 5822 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
5823 | (minus:DI (match_dup 1) (match_dup 2)))] |
5824 | "TARGET_POWERPC64" | |
9ebbca7d GK |
5825 | "@ |
5826 | subf. %0,%2,%1 | |
5827 | #" | |
5828 | [(set_attr "type" "compare") | |
5829 | (set_attr "length" "4,8")]) | |
5830 | ||
5831 | (define_split | |
5832 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5833 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5834 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5835 | (const_int 0))) | |
5836 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5837 | (minus:DI (match_dup 1) (match_dup 2)))] | |
5838 | "TARGET_POWERPC64 && reload_completed" | |
5839 | [(set (match_dup 0) | |
5840 | (minus:DI (match_dup 1) (match_dup 2))) | |
5841 | (set (match_dup 3) | |
5842 | (compare:CC (match_dup 0) | |
5843 | (const_int 0)))] | |
5844 | "") | |
266eb58a DE |
5845 | |
5846 | (define_expand "subdi3" | |
5847 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5848 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
f6bf7de2 | 5849 | (match_operand:DI 2 "reg_or_arith_cint_operand" "")))] |
266eb58a DE |
5850 | "" |
5851 | " | |
5852 | { | |
5853 | if (GET_CODE (operands[2]) == CONST_INT) | |
5854 | { | |
5855 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
5856 | negate_rtx (DImode, operands[2]))); | |
5857 | DONE; | |
5858 | } | |
5859 | }") | |
5860 | ||
5861 | (define_insn "absdi2" | |
5862 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
5863 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
5864 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
5865 | "TARGET_POWERPC64" | |
a260abc9 | 5866 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0" |
266eb58a DE |
5867 | [(set_attr "length" "12")]) |
5868 | ||
5869 | (define_split | |
5870 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
5871 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
5872 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
5873 | "TARGET_POWERPC64 && reload_completed" | |
a260abc9 | 5874 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5875 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 5876 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
5877 | "") |
5878 | ||
19ba8161 | 5879 | (define_insn "*nabsdi2" |
266eb58a DE |
5880 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5881 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
5882 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
5883 | "TARGET_POWERPC64" | |
a260abc9 | 5884 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2" |
266eb58a DE |
5885 | [(set_attr "length" "12")]) |
5886 | ||
5887 | (define_split | |
5888 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
5889 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
5890 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
5891 | "TARGET_POWERPC64 && reload_completed" | |
a260abc9 | 5892 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5893 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 5894 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
5895 | "") |
5896 | ||
5897 | (define_expand "negdi2" | |
5898 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5899 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
5900 | "" | |
5901 | "") | |
5902 | ||
5903 | (define_insn "" | |
5904 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5905 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5906 | "TARGET_POWERPC64" | |
5907 | "neg %0,%1") | |
5908 | ||
5909 | (define_insn "" | |
9ebbca7d GK |
5910 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5911 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5912 | (const_int 0))) |
9ebbca7d | 5913 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 5914 | "TARGET_POWERPC64" |
9ebbca7d GK |
5915 | "@ |
5916 | neg. %2,%1 | |
5917 | #" | |
5918 | [(set_attr "type" "compare") | |
5919 | (set_attr "length" "4,8")]) | |
5920 | ||
5921 | (define_split | |
5922 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5923 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5924 | (const_int 0))) | |
5925 | (clobber (match_scratch:DI 2 ""))] | |
5926 | "TARGET_POWERPC64 && reload_completed" | |
5927 | [(set (match_dup 2) | |
5928 | (neg:DI (match_dup 1))) | |
5929 | (set (match_dup 0) | |
5930 | (compare:CC (match_dup 2) | |
5931 | (const_int 0)))] | |
5932 | "") | |
815cdc52 | 5933 | |
29ae5b89 | 5934 | (define_insn "" |
9ebbca7d GK |
5935 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5936 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 5937 | (const_int 0))) |
9ebbca7d | 5938 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 5939 | (neg:DI (match_dup 1)))] |
29ae5b89 | 5940 | "TARGET_POWERPC64" |
9ebbca7d GK |
5941 | "@ |
5942 | neg. %0,%1 | |
5943 | #" | |
5944 | [(set_attr "type" "compare") | |
5945 | (set_attr "length" "4,8")]) | |
5946 | ||
5947 | (define_split | |
5948 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5949 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5950 | (const_int 0))) | |
5951 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5952 | (neg:DI (match_dup 1)))] | |
5953 | "TARGET_POWERPC64 && reload_completed" | |
5954 | [(set (match_dup 0) | |
5955 | (neg:DI (match_dup 1))) | |
5956 | (set (match_dup 2) | |
5957 | (compare:CC (match_dup 0) | |
5958 | (const_int 0)))] | |
5959 | "") | |
266eb58a DE |
5960 | |
5961 | (define_insn "ffsdi2" | |
5962 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5963 | (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5964 | "TARGET_POWERPC64" | |
5965 | "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64" | |
5966 | [(set_attr "length" "16")]) | |
5967 | ||
5968 | (define_insn "muldi3" | |
5969 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5970 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5971 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
5972 | "TARGET_POWERPC64" | |
5973 | "mulld %0,%1,%2" | |
3cb999d8 | 5974 | [(set_attr "type" "lmul")]) |
266eb58a DE |
5975 | |
5976 | (define_insn "smuldi3_highpart" | |
5977 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5978 | (truncate:DI | |
5979 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
5980 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5981 | (sign_extend:TI | |
5982 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
5983 | (const_int 64))))] | |
5984 | "TARGET_POWERPC64" | |
5985 | "mulhd %0,%1,%2" | |
3cb999d8 | 5986 | [(set_attr "type" "lmul")]) |
266eb58a DE |
5987 | |
5988 | (define_insn "umuldi3_highpart" | |
5989 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5990 | (truncate:DI | |
5991 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
5992 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5993 | (zero_extend:TI | |
5994 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
5995 | (const_int 64))))] | |
5996 | "TARGET_POWERPC64" | |
5997 | "mulhdu %0,%1,%2" | |
3cb999d8 | 5998 | [(set_attr "type" "lmul")]) |
266eb58a DE |
5999 | |
6000 | (define_expand "divdi3" | |
6001 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6002 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6003 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6004 | "TARGET_POWERPC64" | |
6005 | " | |
6006 | { | |
6007 | if (GET_CODE (operands[2]) == CONST_INT | |
6008 | && exact_log2 (INTVAL (operands[2])) >= 0) | |
6009 | ; | |
6010 | else | |
6011 | operands[2] = force_reg (DImode, operands[2]); | |
6012 | }") | |
6013 | ||
6014 | (define_expand "moddi3" | |
6015 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6016 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6017 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6018 | "TARGET_POWERPC64" | |
6019 | " | |
6020 | { | |
6021 | int i = exact_log2 (INTVAL (operands[2])); | |
6022 | rtx temp1; | |
6023 | rtx temp2; | |
6024 | ||
6025 | if (GET_CODE (operands[2]) != CONST_INT || i < 0) | |
6026 | FAIL; | |
6027 | ||
6028 | temp1 = gen_reg_rtx (DImode); | |
6029 | temp2 = gen_reg_rtx (DImode); | |
6030 | ||
6031 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6032 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6033 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6034 | DONE; | |
6035 | }") | |
6036 | ||
6037 | (define_insn "" | |
6038 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6039 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6040 | (match_operand:DI 2 "const_int_operand" "N")))] | |
6041 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" | |
6042 | "sradi %0,%1,%p2\;addze %0,%0" | |
6043 | [(set_attr "length" "8")]) | |
6044 | ||
6045 | (define_insn "" | |
9ebbca7d GK |
6046 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6047 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6048 | (match_operand:DI 2 "const_int_operand" "N,N")) | |
266eb58a | 6049 | (const_int 0))) |
9ebbca7d | 6050 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6051 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" |
9ebbca7d GK |
6052 | "@ |
6053 | sradi %3,%1,%p2\;addze. %3,%3 | |
6054 | #" | |
266eb58a | 6055 | [(set_attr "type" "compare") |
9ebbca7d GK |
6056 | (set_attr "length" "8,12")]) |
6057 | ||
6058 | (define_split | |
6059 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6060 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6061 | (match_operand:DI 2 "const_int_operand" "")) | |
6062 | (const_int 0))) | |
6063 | (clobber (match_scratch:DI 3 ""))] | |
6064 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed" | |
6065 | [(set (match_dup 3) | |
6066 | (div:DI (match_dup 1) (match_dup 2))) | |
6067 | (set (match_dup 0) | |
6068 | (compare:CC (match_dup 3) | |
6069 | (const_int 0)))] | |
6070 | "") | |
266eb58a DE |
6071 | |
6072 | (define_insn "" | |
9ebbca7d GK |
6073 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6074 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6075 | (match_operand:DI 2 "const_int_operand" "N,N")) | |
266eb58a | 6076 | (const_int 0))) |
9ebbca7d | 6077 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6078 | (div:DI (match_dup 1) (match_dup 2)))] |
6079 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" | |
9ebbca7d GK |
6080 | "@ |
6081 | sradi %0,%1,%p2\;addze. %0,%0 | |
6082 | #" | |
266eb58a | 6083 | [(set_attr "type" "compare") |
9ebbca7d | 6084 | (set_attr "length" "8,12")]) |
266eb58a | 6085 | |
9ebbca7d GK |
6086 | (define_split |
6087 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6088 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6089 | (match_operand:DI 2 "const_int_operand" "")) | |
6090 | (const_int 0))) | |
6091 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6092 | (div:DI (match_dup 1) (match_dup 2)))] | |
6093 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed" | |
6094 | [(set (match_dup 0) | |
6095 | (div:DI (match_dup 1) (match_dup 2))) | |
6096 | (set (match_dup 3) | |
6097 | (compare:CC (match_dup 0) | |
6098 | (const_int 0)))] | |
6099 | "") | |
6100 | ||
6101 | (define_insn "" | |
6102 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6103 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6104 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6105 | "TARGET_POWERPC64" |
6106 | "divd %0,%1,%2" | |
3cb999d8 | 6107 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6108 | |
6109 | (define_insn "udivdi3" | |
6110 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6111 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6112 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6113 | "TARGET_POWERPC64" | |
6114 | "divdu %0,%1,%2" | |
3cb999d8 | 6115 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6116 | |
6117 | (define_insn "rotldi3" | |
6118 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6119 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6120 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6121 | "TARGET_POWERPC64" | |
a66078ee | 6122 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6123 | |
a260abc9 | 6124 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6125 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6126 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6127 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6128 | (const_int 0))) |
9ebbca7d | 6129 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6130 | "TARGET_POWERPC64" |
9ebbca7d GK |
6131 | "@ |
6132 | rld%I2cl. %3,%1,%H2,0 | |
6133 | #" | |
6134 | [(set_attr "type" "delayed_compare") | |
6135 | (set_attr "length" "4,8")]) | |
6136 | ||
6137 | (define_split | |
6138 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6139 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6140 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6141 | (const_int 0))) | |
6142 | (clobber (match_scratch:DI 3 ""))] | |
6143 | "TARGET_POWERPC64 && reload_completed" | |
6144 | [(set (match_dup 3) | |
6145 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6146 | (set (match_dup 0) | |
6147 | (compare:CC (match_dup 3) | |
6148 | (const_int 0)))] | |
6149 | "") | |
266eb58a | 6150 | |
a260abc9 | 6151 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6152 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6153 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6154 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6155 | (const_int 0))) |
9ebbca7d | 6156 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6157 | (rotate:DI (match_dup 1) (match_dup 2)))] |
6158 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6159 | "@ |
6160 | rld%I2cl. %0,%1,%H2,0 | |
6161 | #" | |
6162 | [(set_attr "type" "delayed_compare") | |
6163 | (set_attr "length" "4,8")]) | |
6164 | ||
6165 | (define_split | |
6166 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6167 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6168 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6169 | (const_int 0))) | |
6170 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6171 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6172 | "TARGET_POWERPC64 && reload_completed" | |
6173 | [(set (match_dup 0) | |
6174 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6175 | (set (match_dup 3) | |
6176 | (compare:CC (match_dup 0) | |
6177 | (const_int 0)))] | |
6178 | "") | |
266eb58a | 6179 | |
a260abc9 DE |
6180 | (define_insn "*rotldi3_internal4" |
6181 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6182 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6183 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
6184 | (match_operand:DI 3 "mask64_operand" "S")))] | |
6185 | "TARGET_POWERPC64" | |
6186 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6187 | ||
6188 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6189 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6190 | (compare:CC (and:DI |
9ebbca7d GK |
6191 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6192 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
6193 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
a260abc9 | 6194 | (const_int 0))) |
9ebbca7d | 6195 | (clobber (match_scratch:DI 4 "=r,r"))] |
a260abc9 | 6196 | "TARGET_POWERPC64" |
9ebbca7d GK |
6197 | "@ |
6198 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6199 | #" | |
6200 | [(set_attr "type" "delayed_compare") | |
6201 | (set_attr "length" "4,8")]) | |
6202 | ||
6203 | (define_split | |
6204 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6205 | (compare:CC (and:DI | |
6206 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6207 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6208 | (match_operand:DI 3 "mask64_operand" "")) | |
6209 | (const_int 0))) | |
6210 | (clobber (match_scratch:DI 4 ""))] | |
6211 | "TARGET_POWERPC64 && reload_completed" | |
6212 | [(set (match_dup 4) | |
6213 | (and:DI (rotate:DI (match_dup 1) | |
6214 | (match_dup 2)) | |
6215 | (match_dup 3))) | |
6216 | (set (match_dup 0) | |
6217 | (compare:CC (match_dup 4) | |
6218 | (const_int 0)))] | |
6219 | "") | |
a260abc9 DE |
6220 | |
6221 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6222 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6223 | (compare:CC (and:DI |
9ebbca7d GK |
6224 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6225 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
6226 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
a260abc9 | 6227 | (const_int 0))) |
9ebbca7d | 6228 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6229 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
6230 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6231 | "@ |
6232 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6233 | #" | |
6234 | [(set_attr "type" "delayed_compare") | |
6235 | (set_attr "length" "4,8")]) | |
6236 | ||
6237 | (define_split | |
6238 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6239 | (compare:CC (and:DI | |
6240 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6241 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6242 | (match_operand:DI 3 "mask64_operand" "")) | |
6243 | (const_int 0))) | |
6244 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6245 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6246 | "TARGET_POWERPC64 && reload_completed" | |
6247 | [(set (match_dup 0) | |
6248 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6249 | (set (match_dup 4) | |
6250 | (compare:CC (match_dup 0) | |
6251 | (const_int 0)))] | |
6252 | "") | |
a260abc9 DE |
6253 | |
6254 | (define_insn "*rotldi3_internal7" | |
6255 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6256 | (zero_extend:DI | |
6257 | (subreg:QI | |
6258 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6259 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6260 | "TARGET_POWERPC64" | |
6261 | "rld%I2cl %0,%1,%H2,56") | |
6262 | ||
6263 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6264 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6265 | (compare:CC (zero_extend:DI |
6266 | (subreg:QI | |
9ebbca7d GK |
6267 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6268 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6269 | (const_int 0))) |
9ebbca7d | 6270 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6271 | "TARGET_POWERPC64" |
9ebbca7d GK |
6272 | "@ |
6273 | rld%I2cl. %3,%1,%H2,56 | |
6274 | #" | |
6275 | [(set_attr "type" "delayed_compare") | |
6276 | (set_attr "length" "4,8")]) | |
6277 | ||
6278 | (define_split | |
6279 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6280 | (compare:CC (zero_extend:DI | |
6281 | (subreg:QI | |
6282 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6283 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6284 | (const_int 0))) | |
6285 | (clobber (match_scratch:DI 3 ""))] | |
6286 | "TARGET_POWERPC64 && reload_completed" | |
6287 | [(set (match_dup 3) | |
6288 | (zero_extend:DI (subreg:QI | |
6289 | (rotate:DI (match_dup 1) | |
6290 | (match_dup 2)) 0))) | |
6291 | (set (match_dup 0) | |
6292 | (compare:CC (match_dup 3) | |
6293 | (const_int 0)))] | |
6294 | "") | |
a260abc9 DE |
6295 | |
6296 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6297 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6298 | (compare:CC (zero_extend:DI |
6299 | (subreg:QI | |
9ebbca7d GK |
6300 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6301 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6302 | (const_int 0))) |
9ebbca7d | 6303 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6304 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6305 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6306 | "@ |
6307 | rld%I2cl. %0,%1,%H2,56 | |
6308 | #" | |
6309 | [(set_attr "type" "delayed_compare") | |
6310 | (set_attr "length" "4,8")]) | |
6311 | ||
6312 | (define_split | |
6313 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6314 | (compare:CC (zero_extend:DI | |
6315 | (subreg:QI | |
6316 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6317 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6318 | (const_int 0))) | |
6319 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6320 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6321 | "TARGET_POWERPC64 && reload_completed" | |
6322 | [(set (match_dup 0) | |
6323 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6324 | (set (match_dup 3) | |
6325 | (compare:CC (match_dup 0) | |
6326 | (const_int 0)))] | |
6327 | "") | |
a260abc9 DE |
6328 | |
6329 | (define_insn "*rotldi3_internal10" | |
6330 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6331 | (zero_extend:DI | |
6332 | (subreg:HI | |
6333 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6334 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6335 | "TARGET_POWERPC64" | |
6336 | "rld%I2cl %0,%1,%H2,48") | |
6337 | ||
6338 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6339 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6340 | (compare:CC (zero_extend:DI |
6341 | (subreg:HI | |
9ebbca7d GK |
6342 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6343 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6344 | (const_int 0))) |
9ebbca7d | 6345 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6346 | "TARGET_POWERPC64" |
9ebbca7d GK |
6347 | "@ |
6348 | rld%I2cl. %3,%1,%H2,48 | |
6349 | #" | |
6350 | [(set_attr "type" "delayed_compare") | |
6351 | (set_attr "length" "4,8")]) | |
6352 | ||
6353 | (define_split | |
6354 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6355 | (compare:CC (zero_extend:DI | |
6356 | (subreg:HI | |
6357 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6358 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6359 | (const_int 0))) | |
6360 | (clobber (match_scratch:DI 3 ""))] | |
6361 | "TARGET_POWERPC64 && reload_completed" | |
6362 | [(set (match_dup 3) | |
6363 | (zero_extend:DI (subreg:HI | |
6364 | (rotate:DI (match_dup 1) | |
6365 | (match_dup 2)) 0))) | |
6366 | (set (match_dup 0) | |
6367 | (compare:CC (match_dup 3) | |
6368 | (const_int 0)))] | |
6369 | "") | |
a260abc9 DE |
6370 | |
6371 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6372 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6373 | (compare:CC (zero_extend:DI |
6374 | (subreg:HI | |
9ebbca7d GK |
6375 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6376 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6377 | (const_int 0))) |
9ebbca7d | 6378 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6379 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6380 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6381 | "@ |
6382 | rld%I2cl. %0,%1,%H2,48 | |
6383 | #" | |
6384 | [(set_attr "type" "delayed_compare") | |
6385 | (set_attr "length" "4,8")]) | |
6386 | ||
6387 | (define_split | |
6388 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6389 | (compare:CC (zero_extend:DI | |
6390 | (subreg:HI | |
6391 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6392 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6393 | (const_int 0))) | |
6394 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6395 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6396 | "TARGET_POWERPC64 && reload_completed" | |
6397 | [(set (match_dup 0) | |
6398 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6399 | (set (match_dup 3) | |
6400 | (compare:CC (match_dup 0) | |
6401 | (const_int 0)))] | |
6402 | "") | |
a260abc9 DE |
6403 | |
6404 | (define_insn "*rotldi3_internal13" | |
6405 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6406 | (zero_extend:DI | |
6407 | (subreg:SI | |
6408 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6409 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6410 | "TARGET_POWERPC64" | |
6411 | "rld%I2cl %0,%1,%H2,32") | |
6412 | ||
6413 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6414 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6415 | (compare:CC (zero_extend:DI |
6416 | (subreg:SI | |
9ebbca7d GK |
6417 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6418 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6419 | (const_int 0))) |
9ebbca7d | 6420 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6421 | "TARGET_POWERPC64" |
9ebbca7d GK |
6422 | "@ |
6423 | rld%I2cl. %3,%1,%H2,32 | |
6424 | #" | |
6425 | [(set_attr "type" "delayed_compare") | |
6426 | (set_attr "length" "4,8")]) | |
6427 | ||
6428 | (define_split | |
6429 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6430 | (compare:CC (zero_extend:DI | |
6431 | (subreg:SI | |
6432 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6433 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6434 | (const_int 0))) | |
6435 | (clobber (match_scratch:DI 3 ""))] | |
6436 | "TARGET_POWERPC64 && reload_completed" | |
6437 | [(set (match_dup 3) | |
6438 | (zero_extend:DI (subreg:SI | |
6439 | (rotate:DI (match_dup 1) | |
6440 | (match_dup 2)) 0))) | |
6441 | (set (match_dup 0) | |
6442 | (compare:CC (match_dup 3) | |
6443 | (const_int 0)))] | |
6444 | "") | |
a260abc9 DE |
6445 | |
6446 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6447 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6448 | (compare:CC (zero_extend:DI |
6449 | (subreg:SI | |
9ebbca7d GK |
6450 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6451 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6452 | (const_int 0))) |
9ebbca7d | 6453 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6454 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6455 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6456 | "@ |
6457 | rld%I2cl. %0,%1,%H2,32 | |
6458 | #" | |
6459 | [(set_attr "type" "delayed_compare") | |
6460 | (set_attr "length" "4,8")]) | |
6461 | ||
6462 | (define_split | |
6463 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6464 | (compare:CC (zero_extend:DI | |
6465 | (subreg:SI | |
6466 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6467 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6468 | (const_int 0))) | |
6469 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6470 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6471 | "TARGET_POWERPC64 && reload_completed" | |
6472 | [(set (match_dup 0) | |
6473 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6474 | (set (match_dup 3) | |
6475 | (compare:CC (match_dup 0) | |
6476 | (const_int 0)))] | |
6477 | "") | |
a260abc9 | 6478 | |
266eb58a DE |
6479 | (define_expand "ashldi3" |
6480 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6481 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6482 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6483 | "TARGET_POWERPC64 || TARGET_POWER" | |
6484 | " | |
6485 | { | |
6486 | if (TARGET_POWERPC64) | |
6487 | ; | |
6488 | else if (TARGET_POWER) | |
6489 | { | |
6490 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6491 | DONE; | |
6492 | } | |
6493 | else | |
6494 | FAIL; | |
6495 | }") | |
6496 | ||
e2c953b6 | 6497 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
6498 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6499 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6500 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6501 | "TARGET_POWERPC64" | |
a66078ee | 6502 | "sld%I2 %0,%1,%H2" |
266eb58a DE |
6503 | [(set_attr "length" "8")]) |
6504 | ||
e2c953b6 | 6505 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
6506 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6507 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6508 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6509 | (const_int 0))) |
9ebbca7d | 6510 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6511 | "TARGET_POWERPC64" |
9ebbca7d GK |
6512 | "@ |
6513 | sld%I2. %3,%1,%H2 | |
6514 | #" | |
6515 | [(set_attr "type" "delayed_compare") | |
6516 | (set_attr "length" "4,8")]) | |
29ae5b89 | 6517 | |
9ebbca7d GK |
6518 | (define_split |
6519 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6520 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6521 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6522 | (const_int 0))) | |
6523 | (clobber (match_scratch:DI 3 ""))] | |
6524 | "TARGET_POWERPC64 && reload_completed" | |
6525 | [(set (match_dup 3) | |
6526 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6527 | (set (match_dup 0) | |
6528 | (compare:CC (match_dup 3) | |
6529 | (const_int 0)))] | |
6530 | "") | |
6531 | ||
e2c953b6 | 6532 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
6533 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6534 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6535 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6536 | (const_int 0))) |
9ebbca7d | 6537 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6538 | (ashift:DI (match_dup 1) (match_dup 2)))] |
6539 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6540 | "@ |
6541 | sld%I2. %0,%1,%H2 | |
6542 | #" | |
6543 | [(set_attr "type" "delayed_compare") | |
6544 | (set_attr "length" "4,8")]) | |
6545 | ||
6546 | (define_split | |
6547 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6548 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6549 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6550 | (const_int 0))) | |
6551 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6552 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6553 | "TARGET_POWERPC64 && reload_completed" | |
6554 | [(set (match_dup 0) | |
6555 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6556 | (set (match_dup 3) | |
6557 | (compare:CC (match_dup 0) | |
6558 | (const_int 0)))] | |
6559 | "") | |
266eb58a | 6560 | |
e2c953b6 | 6561 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
6562 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6563 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6564 | (match_operand:SI 2 "const_int_operand" "i")) | |
e2c953b6 | 6565 | (match_operand:DI 3 "rldic_operand" "n")))] |
4264cf59 | 6566 | "TARGET_POWERPC64 && includes_lshift64_p (operands[2], operands[3])" |
e2c953b6 | 6567 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 6568 | |
e2c953b6 | 6569 | (define_insn "ashldi3_internal5" |
9ebbca7d | 6570 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6571 | (compare:CC |
9ebbca7d GK |
6572 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6573 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
e2c953b6 | 6574 | (match_operand:DI 3 "rldic_operand" "n,n")) |
3cb999d8 | 6575 | (const_int 0))) |
9ebbca7d | 6576 | (clobber (match_scratch:DI 4 "=r,r"))] |
4264cf59 | 6577 | "TARGET_POWERPC64 && includes_lshift64_p (operands[2], operands[3])" |
9ebbca7d | 6578 | "@ |
e2c953b6 | 6579 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
6580 | #" |
6581 | [(set_attr "type" "delayed_compare") | |
6582 | (set_attr "length" "4,8")]) | |
6583 | ||
6584 | (define_split | |
6585 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6586 | (compare:CC | |
6587 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6588 | (match_operand:SI 2 "const_int_operand" "")) | |
e2c953b6 | 6589 | (match_operand:DI 3 "rldic_operand" "")) |
9ebbca7d GK |
6590 | (const_int 0))) |
6591 | (clobber (match_scratch:DI 4 ""))] | |
4264cf59 | 6592 | "TARGET_POWERPC64 && includes_lshift64_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
6593 | [(set (match_dup 4) |
6594 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 6595 | (match_dup 3))) |
9ebbca7d GK |
6596 | (set (match_dup 0) |
6597 | (compare:CC (match_dup 4) | |
6598 | (const_int 0)))] | |
6599 | "") | |
3cb999d8 | 6600 | |
e2c953b6 | 6601 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 6602 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6603 | (compare:CC |
9ebbca7d GK |
6604 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6605 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
e2c953b6 | 6606 | (match_operand:DI 3 "rldic_operand" "n,n")) |
3cb999d8 | 6607 | (const_int 0))) |
9ebbca7d | 6608 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 6609 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
4264cf59 | 6610 | "TARGET_POWERPC64 && includes_lshift64_p (operands[2], operands[3])" |
9ebbca7d | 6611 | "@ |
e2c953b6 | 6612 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
6613 | #" |
6614 | [(set_attr "type" "delayed_compare") | |
6615 | (set_attr "length" "4,8")]) | |
6616 | ||
6617 | (define_split | |
6618 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6619 | (compare:CC | |
6620 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6621 | (match_operand:SI 2 "const_int_operand" "")) | |
e2c953b6 | 6622 | (match_operand:DI 3 "rldic_operand" "")) |
9ebbca7d GK |
6623 | (const_int 0))) |
6624 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6625 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4264cf59 | 6626 | "TARGET_POWERPC64 && includes_lshift64_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d | 6627 | [(set (match_dup 0) |
e2c953b6 DE |
6628 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
6629 | (match_dup 3))) | |
9ebbca7d GK |
6630 | (set (match_dup 4) |
6631 | (compare:CC (match_dup 0) | |
6632 | (const_int 0)))] | |
6633 | "") | |
6634 | ||
6635 | (define_expand "lshrdi3" | |
266eb58a DE |
6636 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6637 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6638 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6639 | "TARGET_POWERPC64 || TARGET_POWER" | |
6640 | " | |
6641 | { | |
6642 | if (TARGET_POWERPC64) | |
6643 | ; | |
6644 | else if (TARGET_POWER) | |
6645 | { | |
6646 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
6647 | DONE; | |
6648 | } | |
6649 | else | |
6650 | FAIL; | |
6651 | }") | |
6652 | ||
e2c953b6 | 6653 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
6654 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6655 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6656 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6657 | "TARGET_POWERPC64" | |
a66078ee | 6658 | "srd%I2 %0,%1,%H2") |
266eb58a | 6659 | |
e2c953b6 | 6660 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
6661 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6662 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6663 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 6664 | (const_int 0))) |
9ebbca7d | 6665 | (clobber (match_scratch:DI 3 "=r,r"))] |
29ae5b89 | 6666 | "TARGET_POWERPC64" |
9ebbca7d GK |
6667 | "@ |
6668 | srd%I2. %3,%1,%H2 | |
6669 | #" | |
6670 | [(set_attr "type" "delayed_compare") | |
6671 | (set_attr "length" "4,8")]) | |
6672 | ||
6673 | (define_split | |
6674 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6675 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6676 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6677 | (const_int 0))) | |
6678 | (clobber (match_scratch:DI 3 ""))] | |
6679 | "TARGET_POWERPC64 && reload_completed" | |
6680 | [(set (match_dup 3) | |
6681 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6682 | (set (match_dup 0) | |
6683 | (compare:CC (match_dup 3) | |
6684 | (const_int 0)))] | |
6685 | "") | |
266eb58a | 6686 | |
e2c953b6 | 6687 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
6688 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6689 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6690 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6691 | (const_int 0))) |
9ebbca7d | 6692 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 JL |
6693 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
6694 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6695 | "@ |
6696 | srd%I2. %0,%1,%H2 | |
6697 | #" | |
6698 | [(set_attr "type" "delayed_compare") | |
6699 | (set_attr "length" "4,8")]) | |
6700 | ||
6701 | (define_split | |
6702 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6703 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6704 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6705 | (const_int 0))) | |
6706 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6707 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
6708 | "TARGET_POWERPC64 && reload_completed" | |
6709 | [(set (match_dup 0) | |
6710 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6711 | (set (match_dup 3) | |
6712 | (compare:CC (match_dup 0) | |
6713 | (const_int 0)))] | |
6714 | "") | |
266eb58a DE |
6715 | |
6716 | (define_expand "ashrdi3" | |
6717 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6718 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6719 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6720 | "TARGET_POWERPC64 || TARGET_POWER" | |
6721 | " | |
6722 | { | |
6723 | if (TARGET_POWERPC64) | |
6724 | ; | |
6725 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
6726 | { | |
6727 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
6728 | DONE; | |
6729 | } | |
6730 | else | |
6731 | FAIL; | |
6732 | }") | |
6733 | ||
e2c953b6 | 6734 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
6735 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6736 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6737 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6738 | "TARGET_POWERPC64" | |
375490e0 | 6739 | "srad%I2 %0,%1,%H2") |
266eb58a | 6740 | |
e2c953b6 | 6741 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
6742 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6743 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6744 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6745 | (const_int 0))) |
9ebbca7d | 6746 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6747 | "TARGET_POWERPC64" |
9ebbca7d GK |
6748 | "@ |
6749 | srad%I2. %3,%1,%H2 | |
6750 | #" | |
6751 | [(set_attr "type" "delayed_compare") | |
6752 | (set_attr "length" "4,8")]) | |
6753 | ||
6754 | (define_split | |
6755 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6756 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6757 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6758 | (const_int 0))) | |
6759 | (clobber (match_scratch:DI 3 ""))] | |
6760 | "TARGET_POWERPC64 && reload_completed" | |
6761 | [(set (match_dup 3) | |
6762 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6763 | (set (match_dup 0) | |
6764 | (compare:CC (match_dup 3) | |
6765 | (const_int 0)))] | |
6766 | "") | |
266eb58a | 6767 | |
e2c953b6 | 6768 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
6769 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6770 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6771 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6772 | (const_int 0))) |
9ebbca7d | 6773 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6774 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6775 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6776 | "@ |
6777 | srad%I2. %0,%1,%H2 | |
6778 | #" | |
6779 | [(set_attr "type" "delayed_compare") | |
6780 | (set_attr "length" "4,8")]) | |
6781 | ||
6782 | (define_split | |
6783 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6784 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6785 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6786 | (const_int 0))) | |
6787 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6788 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
6789 | "TARGET_POWERPC64 && reload_completed" | |
6790 | [(set (match_dup 0) | |
6791 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6792 | (set (match_dup 3) | |
6793 | (compare:CC (match_dup 0) | |
6794 | (const_int 0)))] | |
6795 | "") | |
815cdc52 | 6796 | |
29ae5b89 JL |
6797 | (define_insn "anddi3" |
6798 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") | |
6799 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
6800 | (match_operand:DI 2 "and64_operand" "?r,S,K,J"))) | |
6801 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] | |
6ffc8580 | 6802 | "TARGET_POWERPC64" |
266eb58a DE |
6803 | "@ |
6804 | and %0,%1,%2 | |
29ae5b89 JL |
6805 | rldic%B2 %0,%1,0,%S2 |
6806 | andi. %0,%1,%b2 | |
6807 | andis. %0,%1,%u2") | |
266eb58a | 6808 | |
a260abc9 | 6809 | (define_insn "*anddi3_internal2" |
6c873122 | 6810 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y") |
9ebbca7d | 6811 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,") |
6c873122 | 6812 | (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J")) |
266eb58a | 6813 | (const_int 0))) |
9ebbca7d | 6814 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r")) |
6c873122 | 6815 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))] |
6ffc8580 | 6816 | "TARGET_POWERPC64" |
266eb58a DE |
6817 | "@ |
6818 | and. %3,%1,%2 | |
6c873122 | 6819 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
6820 | andi. %3,%1,%b2 |
6821 | andis. %3,%1,%u2 | |
9ebbca7d GK |
6822 | # |
6823 | # | |
6824 | # | |
6825 | #" | |
6c873122 | 6826 | [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare") |
9ebbca7d GK |
6827 | (set_attr "length" "4,4,4,4,8,8,8,8")]) |
6828 | ||
6829 | (define_split | |
6830 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6831 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6832 | (match_operand:DI 2 "and64_operand" "")) | |
6833 | (const_int 0))) | |
6834 | (clobber (match_scratch:DI 3 "")) | |
6835 | (clobber (match_scratch:CC 4 ""))] | |
6836 | "TARGET_POWERPC64 && reload_completed" | |
6837 | [(parallel [(set (match_dup 3) | |
6838 | (and:DI (match_dup 1) | |
6839 | (match_dup 2))) | |
6840 | (clobber (match_dup 4))]) | |
6841 | (set (match_dup 0) | |
6842 | (compare:CC (match_dup 3) | |
6843 | (const_int 0)))] | |
6844 | "") | |
266eb58a | 6845 | |
a260abc9 | 6846 | (define_insn "*anddi3_internal3" |
6c873122 | 6847 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y") |
9ebbca7d | 6848 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") |
6c873122 | 6849 | (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J")) |
266eb58a | 6850 | (const_int 0))) |
9ebbca7d GK |
6851 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") |
6852 | (and:DI (match_dup 1) (match_dup 2))) | |
6c873122 | 6853 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))] |
6ffc8580 | 6854 | "TARGET_POWERPC64" |
266eb58a DE |
6855 | "@ |
6856 | and. %0,%1,%2 | |
6c873122 | 6857 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
6858 | andi. %0,%1,%b2 |
6859 | andis. %0,%1,%u2 | |
9ebbca7d GK |
6860 | # |
6861 | # | |
6862 | # | |
6863 | #" | |
6c873122 | 6864 | [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare") |
9ebbca7d GK |
6865 | (set_attr "length" "4,4,4,4,8,8,8,8")]) |
6866 | ||
6867 | (define_split | |
6868 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6869 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6870 | (match_operand:DI 2 "and64_operand" "")) | |
6871 | (const_int 0))) | |
6872 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6873 | (and:DI (match_dup 1) (match_dup 2))) | |
6874 | (clobber (match_scratch:CC 4 ""))] | |
6875 | "TARGET_POWERPC64 && reload_completed" | |
6876 | [(parallel [(set (match_dup 0) | |
6877 | (and:DI (match_dup 1) (match_dup 2))) | |
6878 | (clobber (match_dup 4))]) | |
6879 | (set (match_dup 3) | |
6880 | (compare:CC (match_dup 0) | |
6881 | (const_int 0)))] | |
6882 | "") | |
266eb58a | 6883 | |
a260abc9 | 6884 | (define_expand "iordi3" |
266eb58a | 6885 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 6886 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 6887 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 6888 | "TARGET_POWERPC64" |
266eb58a DE |
6889 | " |
6890 | { | |
dfbdccdb | 6891 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 6892 | { |
dfbdccdb | 6893 | HOST_WIDE_INT value; |
677a9668 | 6894 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 6895 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 6896 | |
dfbdccdb GK |
6897 | if (GET_CODE (operands[2]) == CONST_INT) |
6898 | { | |
6899 | value = INTVAL (operands[2]); | |
6900 | emit_insn (gen_iordi3 (tmp, operands[1], | |
6901 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
6902 | } | |
e2c953b6 | 6903 | else |
dfbdccdb GK |
6904 | { |
6905 | value = CONST_DOUBLE_LOW (operands[2]); | |
6906 | emit_insn (gen_iordi3 (tmp, operands[1], | |
6907 | immed_double_const (value | |
6908 | & (~ (HOST_WIDE_INT) 0xffff), | |
6909 | 0, DImode))); | |
6910 | } | |
e2c953b6 | 6911 | |
9ebbca7d GK |
6912 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
6913 | DONE; | |
6914 | } | |
266eb58a DE |
6915 | }") |
6916 | ||
a260abc9 DE |
6917 | (define_expand "xordi3" |
6918 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6919 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 6920 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
6921 | "TARGET_POWERPC64" |
6922 | " | |
6923 | { | |
dfbdccdb | 6924 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 6925 | { |
dfbdccdb | 6926 | HOST_WIDE_INT value; |
677a9668 | 6927 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
6928 | ? operands[0] : gen_reg_rtx (DImode)); |
6929 | ||
dfbdccdb GK |
6930 | if (GET_CODE (operands[2]) == CONST_INT) |
6931 | { | |
6932 | value = INTVAL (operands[2]); | |
6933 | emit_insn (gen_xordi3 (tmp, operands[1], | |
6934 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
6935 | } | |
e2c953b6 | 6936 | else |
dfbdccdb GK |
6937 | { |
6938 | value = CONST_DOUBLE_LOW (operands[2]); | |
6939 | emit_insn (gen_xordi3 (tmp, operands[1], | |
6940 | immed_double_const (value | |
6941 | & (~ (HOST_WIDE_INT) 0xffff), | |
6942 | 0, DImode))); | |
6943 | } | |
e2c953b6 | 6944 | |
9ebbca7d GK |
6945 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
6946 | DONE; | |
6947 | } | |
a260abc9 DE |
6948 | }") |
6949 | ||
dfbdccdb | 6950 | (define_insn "*booldi3_internal1" |
266eb58a | 6951 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 6952 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
6953 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
6954 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 6955 | "TARGET_POWERPC64" |
1fd4e8c1 | 6956 | "@ |
dfbdccdb GK |
6957 | %q3 %0,%1,%2 |
6958 | %q3i %0,%1,%b2 | |
6959 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 6960 | |
dfbdccdb | 6961 | (define_insn "*booldi3_internal2" |
9ebbca7d | 6962 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 6963 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
6964 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
6965 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
6966 | (const_int 0))) | |
9ebbca7d | 6967 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6968 | "TARGET_POWERPC64" |
9ebbca7d | 6969 | "@ |
dfbdccdb | 6970 | %q4. %3,%1,%2 |
9ebbca7d GK |
6971 | #" |
6972 | [(set_attr "type" "compare") | |
6973 | (set_attr "length" "4,8")]) | |
6974 | ||
6975 | (define_split | |
6976 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
6977 | (compare:CC (match_operator:DI 4 "boolean_operator" |
6978 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6979 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
6980 | (const_int 0))) | |
9ebbca7d GK |
6981 | (clobber (match_scratch:DI 3 ""))] |
6982 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 6983 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
6984 | (set (match_dup 0) |
6985 | (compare:CC (match_dup 3) | |
6986 | (const_int 0)))] | |
6987 | "") | |
1fd4e8c1 | 6988 | |
dfbdccdb | 6989 | (define_insn "*booldi3_internal3" |
9ebbca7d | 6990 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
6991 | (compare:CC (match_operator:DI 4 "boolean_operator" |
6992 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6993 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
6994 | (const_int 0))) | |
9ebbca7d | 6995 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 6996 | (match_dup 4))] |
266eb58a | 6997 | "TARGET_POWERPC64" |
9ebbca7d | 6998 | "@ |
dfbdccdb | 6999 | %q4. %0,%1,%2 |
9ebbca7d GK |
7000 | #" |
7001 | [(set_attr "type" "compare") | |
7002 | (set_attr "length" "4,8")]) | |
7003 | ||
7004 | (define_split | |
dfbdccdb GK |
7005 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7006 | (compare:CC (match_operator:DI 4 "boolean_operator" | |
7007 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7008 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7009 | (const_int 0))) | |
7010 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
7011 | (match_dup 4))] | |
9ebbca7d | 7012 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7013 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7014 | (set (match_dup 3) |
7015 | (compare:CC (match_dup 0) | |
7016 | (const_int 0)))] | |
7017 | "") | |
1fd4e8c1 | 7018 | |
dfbdccdb GK |
7019 | ;; Split an logical operation that we can't do in one insn into two insns, |
7020 | ;; each of which does one 16-bit part. This is used by combine. | |
266eb58a DE |
7021 | |
7022 | (define_split | |
7023 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 7024 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7025 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7026 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7027 | "TARGET_POWERPC64" |
dfbdccdb GK |
7028 | [(set (match_dup 0) (match_dup 4)) |
7029 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7030 | " |
7031 | { | |
dfbdccdb GK |
7032 | rtx i3,i4; |
7033 | ||
9ebbca7d GK |
7034 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7035 | { | |
7036 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7037 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7038 | 0, DImode); |
dfbdccdb | 7039 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7040 | } |
7041 | else | |
7042 | { | |
dfbdccdb | 7043 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7044 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7045 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7046 | } |
dfbdccdb GK |
7047 | operands[4] = gen_rtx (GET_CODE (operands[3]), DImode, |
7048 | operands[1], i3); | |
7049 | operands[5] = gen_rtx (GET_CODE (operands[3]), DImode, | |
7050 | operands[0], i4); | |
1fd4e8c1 RK |
7051 | }") |
7052 | ||
dfbdccdb | 7053 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7054 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7055 | (match_operator:DI 3 "boolean_operator" |
7056 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7057 | (match_operand:DI 2 "logical_operand" "r")]))] | |
a473029f | 7058 | "TARGET_POWERPC64" |
1d328b19 | 7059 | "%q3 %0,%2,%1") |
a473029f | 7060 | |
dfbdccdb | 7061 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7062 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7063 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7064 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7065 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7066 | (const_int 0))) | |
9ebbca7d | 7067 | (clobber (match_scratch:DI 3 "=r,r"))] |
a473029f | 7068 | "TARGET_POWERPC64" |
9ebbca7d | 7069 | "@ |
1d328b19 | 7070 | %q4. %3,%2,%1 |
9ebbca7d GK |
7071 | #" |
7072 | [(set_attr "type" "compare") | |
7073 | (set_attr "length" "4,8")]) | |
7074 | ||
7075 | (define_split | |
7076 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
7077 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7078 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7079 | (match_operand:DI 2 "gpc_reg_operand" "r")]) | |
7080 | (const_int 0))) | |
9ebbca7d GK |
7081 | (clobber (match_scratch:DI 3 ""))] |
7082 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7083 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7084 | (set (match_dup 0) |
7085 | (compare:CC (match_dup 3) | |
7086 | (const_int 0)))] | |
7087 | "") | |
a473029f | 7088 | |
dfbdccdb | 7089 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7090 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7091 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7092 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7093 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7094 | (const_int 0))) | |
9ebbca7d | 7095 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7096 | (match_dup 4))] |
a473029f | 7097 | "TARGET_POWERPC64" |
9ebbca7d | 7098 | "@ |
1d328b19 | 7099 | %q4. %0,%2,%1 |
9ebbca7d GK |
7100 | #" |
7101 | [(set_attr "type" "compare") | |
7102 | (set_attr "length" "4,8")]) | |
7103 | ||
7104 | (define_split | |
9ebbca7d | 7105 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7106 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7107 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7108 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7109 | (const_int 0))) | |
9ebbca7d | 7110 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7111 | (match_dup 4))] |
9ebbca7d | 7112 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7113 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7114 | (set (match_dup 3) |
7115 | (compare:CC (match_dup 0) | |
7116 | (const_int 0)))] | |
7117 | "") | |
266eb58a | 7118 | |
dfbdccdb | 7119 | (define_insn "*boolccdi3_internal1" |
a473029f | 7120 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7121 | (match_operator:DI 3 "boolean_operator" |
7122 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7123 | (not:DI (match_operand:DI 2 "logical_operand" "r"))]))] | |
a473029f | 7124 | "TARGET_POWERPC64" |
dfbdccdb | 7125 | "%q3 %0,%1,%2") |
a473029f | 7126 | |
dfbdccdb | 7127 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7128 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7129 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7130 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7131 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7132 | (const_int 0))) | |
9ebbca7d | 7133 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7134 | "TARGET_POWERPC64" |
9ebbca7d | 7135 | "@ |
dfbdccdb | 7136 | %q4. %3,%1,%2 |
9ebbca7d GK |
7137 | #" |
7138 | [(set_attr "type" "compare") | |
7139 | (set_attr "length" "4,8")]) | |
7140 | ||
7141 | (define_split | |
7142 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
7143 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7144 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7145 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]) | |
7146 | (const_int 0))) | |
9ebbca7d GK |
7147 | (clobber (match_scratch:DI 3 ""))] |
7148 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7149 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7150 | (set (match_dup 0) |
7151 | (compare:CC (match_dup 3) | |
7152 | (const_int 0)))] | |
7153 | "") | |
266eb58a | 7154 | |
dfbdccdb | 7155 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7156 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7157 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7158 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7159 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7160 | (const_int 0))) | |
9ebbca7d | 7161 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7162 | (match_dup 4))] |
29ae5b89 | 7163 | "TARGET_POWERPC64" |
9ebbca7d | 7164 | "@ |
dfbdccdb | 7165 | %q4. %0,%1,%2 |
9ebbca7d GK |
7166 | #" |
7167 | [(set_attr "type" "compare") | |
7168 | (set_attr "length" "4,8")]) | |
7169 | ||
7170 | (define_split | |
9ebbca7d | 7171 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7172 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7173 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7174 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7175 | (const_int 0))) | |
9ebbca7d | 7176 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7177 | (match_dup 4))] |
9ebbca7d | 7178 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7179 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7180 | (set (match_dup 3) |
7181 | (compare:CC (match_dup 0) | |
7182 | (const_int 0)))] | |
7183 | "") | |
dfbdccdb | 7184 | \f |
1fd4e8c1 | 7185 | ;; Now define ways of moving data around. |
4697a36c MM |
7186 | |
7187 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
7188 | ;; The output of this could be r0, but we make a very strong |
7189 | ;; preference for a base register because it will usually | |
7190 | ;; be needed there. | |
4697a36c | 7191 | (define_insn "elf_high" |
9ebbca7d | 7192 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 7193 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 7194 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 7195 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
7196 | |
7197 | (define_insn "elf_low" | |
9ebbca7d GK |
7198 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
7199 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 7200 | (match_operand 2 "" "")))] |
0ad91047 | 7201 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
7202 | "@ |
7203 | {cal|la} %0,%2@l(%1) | |
81eace42 | 7204 | {ai|addic} %0,%1,%K2") |
4697a36c | 7205 | |
ee890fe2 SS |
7206 | ;; Mach-O PIC trickery. |
7207 | (define_insn "macho_high" | |
7208 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") | |
7209 | (high:SI (match_operand 1 "" "")))] | |
7210 | "TARGET_MACHO && ! TARGET_64BIT" | |
7211 | "{liu|lis} %0,ha16(%1)") | |
7212 | ||
7213 | (define_insn "macho_low" | |
7214 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
7215 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
7216 | (match_operand 2 "" "")))] | |
7217 | "TARGET_MACHO && ! TARGET_64BIT" | |
7218 | "@ | |
7219 | {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)} | |
7220 | {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}") | |
7221 | ||
766a866c MM |
7222 | ;; Set up a register with a value from the GOT table |
7223 | ||
7224 | (define_expand "movsi_got" | |
52d3af72 | 7225 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d GK |
7226 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
7227 | (match_dup 2)] 8))] | |
58307bcd | 7228 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
7229 | " |
7230 | { | |
38c1f2d7 MM |
7231 | if (GET_CODE (operands[1]) == CONST) |
7232 | { | |
7233 | rtx offset = const0_rtx; | |
7234 | HOST_WIDE_INT value; | |
7235 | ||
7236 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7237 | value = INTVAL (offset); | |
7238 | if (value != 0) | |
7239 | { | |
677a9668 | 7240 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7241 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7242 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7243 | DONE; | |
7244 | } | |
7245 | } | |
7246 | ||
c4c40373 | 7247 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7248 | }") |
7249 | ||
84f414bc | 7250 | (define_insn "*movsi_got_internal" |
52d3af72 | 7251 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d GK |
7252 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
7253 | (match_operand:SI 2 "gpc_reg_operand" "b")] 8))] | |
c81bebd7 | 7254 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
7255 | "{l|lwz} %0,%a1@got(%2)" |
7256 | [(set_attr "type" "load")]) | |
7257 | ||
b22b9b3e JL |
7258 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7259 | ;; didn't get allocated to a hard register. | |
7260 | (define_split | |
52d3af72 | 7261 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d GK |
7262 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
7263 | (match_operand:SI 2 "memory_operand" "m")] 8))] | |
b22b9b3e JL |
7264 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
7265 | && flag_pic == 1 | |
7266 | && (reload_in_progress || reload_completed)" | |
7267 | [(set (match_dup 0) (match_dup 2)) | |
9ebbca7d | 7268 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))] |
b22b9b3e JL |
7269 | "") |
7270 | ||
1fd4e8c1 RK |
7271 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7272 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7273 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7274 | ;; integers in the TOC. | |
7275 | (define_expand "movsi" | |
7276 | [(set (match_operand:SI 0 "general_operand" "") | |
7277 | (match_operand:SI 1 "any_operand" ""))] | |
7278 | "" | |
fb4d4348 | 7279 | "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") |
1fd4e8c1 | 7280 | |
ee890fe2 SS |
7281 | (define_insn "movsi_low" |
7282 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
7283 | (mem:SI (lo_sum:SI (match_operand:SI 1 "register_operand" "b") | |
7284 | (match_operand 2 "" ""))))] | |
7285 | "TARGET_MACHO && ! TARGET_64BIT" | |
7286 | "{l|lwz} %0,lo16(%2)(%1)" | |
7287 | [(set_attr "type" "load") | |
7288 | (set_attr "length" "4")]) | |
7289 | ||
acad7ed3 | 7290 | (define_insn "*movsi_internal1" |
a260abc9 | 7291 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h") |
9615f239 | 7292 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))] |
19d5775a RK |
7293 | "gpc_reg_operand (operands[0], SImode) |
7294 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7295 | "@ |
deb9225a | 7296 | mr %0,%1 |
b9442c72 | 7297 | {cal|la} %0,%a1 |
ca7f5001 RK |
7298 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7299 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7300 | {lil|li} %0,%1 |
802a0058 | 7301 | {liu|lis} %0,%v1 |
beaec479 | 7302 | # |
aee86b38 | 7303 | {cal|la} %0,%a1 |
1fd4e8c1 | 7304 | mf%1 %0 |
5c23c401 | 7305 | mt%0 %1 |
e76e75bb RK |
7306 | mt%0 %1 |
7307 | cror 0,0,0" | |
a260abc9 DE |
7308 | [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*") |
7309 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")]) | |
1fd4e8c1 | 7310 | |
77fa0940 RK |
7311 | ;; Split a load of a large constant into the appropriate two-insn |
7312 | ;; sequence. | |
7313 | ||
7314 | (define_split | |
7315 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7316 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7317 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7318 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7319 | [(set (match_dup 0) | |
7320 | (match_dup 2)) | |
7321 | (set (match_dup 0) | |
7322 | (ior:SI (match_dup 0) | |
7323 | (match_dup 3)))] | |
7324 | " | |
7325 | { | |
5f59ecb7 | 7326 | operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); |
89e9f3a8 | 7327 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); |
77fa0940 RK |
7328 | }") |
7329 | ||
acad7ed3 | 7330 | (define_insn "*movsi_internal2" |
9ebbca7d GK |
7331 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
7332 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 7333 | (const_int 0))) |
9ebbca7d | 7334 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
0ad91047 | 7335 | "! TARGET_POWERPC64" |
9ebbca7d GK |
7336 | "@ |
7337 | mr. %0,%1 | |
7338 | #" | |
7339 | [(set_attr "type" "compare") | |
7340 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 7341 | \f |
9ebbca7d GK |
7342 | (define_split |
7343 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
7344 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
7345 | (const_int 0))) | |
7346 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
7347 | "! TARGET_POWERPC64 && reload_completed" | |
7348 | [(set (match_dup 0) (match_dup 1)) | |
7349 | (set (match_dup 2) | |
7350 | (compare:CC (match_dup 0) | |
7351 | (const_int 0)))] | |
7352 | "") | |
7353 | ||
1fd4e8c1 RK |
7354 | (define_expand "movhi" |
7355 | [(set (match_operand:HI 0 "general_operand" "") | |
7356 | (match_operand:HI 1 "any_operand" ""))] | |
7357 | "" | |
fb4d4348 | 7358 | "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") |
1fd4e8c1 RK |
7359 | |
7360 | (define_insn "" | |
fb81d7ce RK |
7361 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7362 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7363 | "gpc_reg_operand (operands[0], HImode) |
7364 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7365 | "@ |
deb9225a | 7366 | mr %0,%1 |
1fd4e8c1 RK |
7367 | lhz%U1%X1 %0,%1 |
7368 | sth%U0%X0 %1,%0 | |
19d5775a | 7369 | {lil|li} %0,%w1 |
1fd4e8c1 | 7370 | mf%1 %0 |
e76e75bb | 7371 | mt%0 %1 |
fb81d7ce | 7372 | mt%0 %1 |
e76e75bb | 7373 | cror 0,0,0" |
b7ff3d82 | 7374 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7375 | |
7376 | (define_expand "movqi" | |
7377 | [(set (match_operand:QI 0 "general_operand" "") | |
7378 | (match_operand:QI 1 "any_operand" ""))] | |
7379 | "" | |
fb4d4348 | 7380 | "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") |
1fd4e8c1 RK |
7381 | |
7382 | (define_insn "" | |
fb81d7ce RK |
7383 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7384 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7385 | "gpc_reg_operand (operands[0], QImode) |
7386 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7387 | "@ |
deb9225a | 7388 | mr %0,%1 |
1fd4e8c1 RK |
7389 | lbz%U1%X1 %0,%1 |
7390 | stb%U0%X0 %1,%0 | |
19d5775a | 7391 | {lil|li} %0,%1 |
1fd4e8c1 | 7392 | mf%1 %0 |
e76e75bb | 7393 | mt%0 %1 |
fb81d7ce | 7394 | mt%0 %1 |
e76e75bb | 7395 | cror 0,0,0" |
b7ff3d82 | 7396 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7397 | \f |
7398 | ;; Here is how to move condition codes around. When we store CC data in | |
7399 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7400 | ;; This lets us not shift in the most common case of CR0. | |
7401 | (define_expand "movcc" | |
7402 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7403 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7404 | "" | |
7405 | "") | |
7406 | ||
7407 | (define_insn "" | |
7408 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") | |
7409 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] | |
7410 | "register_operand (operands[0], CCmode) | |
7411 | || register_operand (operands[1], CCmode)" | |
7412 | "@ | |
7413 | mcrf %0,%1 | |
7414 | mtcrf 128,%1 | |
ca7f5001 | 7415 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
1fd4e8c1 | 7416 | mfcr %0 |
ca7f5001 | 7417 | mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 |
deb9225a | 7418 | mr %0,%1 |
ca7f5001 RK |
7419 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7420 | {st%U0%U1|stw%U0%U1} %1,%0" | |
b7ff3d82 | 7421 | [(set_attr "type" "*,*,*,compare,*,*,load,store") |
b19003d8 | 7422 | (set_attr "length" "*,*,12,*,8,*,*,*")]) |
1fd4e8c1 | 7423 | \f |
e52e05ca MM |
7424 | ;; For floating-point, we normally deal with the floating-point registers |
7425 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7426 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7427 | ;; value is a simple constant or already in memory, we deal with this by | |
7428 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7429 | (define_expand "movsf" |
7430 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7431 | (match_operand:SF 1 "any_operand" ""))] | |
7432 | "" | |
fb4d4348 | 7433 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 7434 | |
1fd4e8c1 | 7435 | (define_split |
cd2b37d9 | 7436 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7437 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7438 | "reload_completed |
5ae4759c MM |
7439 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7440 | || (GET_CODE (operands[0]) == SUBREG | |
7441 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7442 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7443 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7444 | " |
7445 | { | |
7446 | long l; | |
7447 | REAL_VALUE_TYPE rv; | |
7448 | ||
7449 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7450 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7451 | |
f99f88e0 DE |
7452 | if (! TARGET_POWERPC64) |
7453 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7454 | else | |
7455 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7456 | |
38886f37 | 7457 | operands[3] = GEN_INT (trunc_int_for_mode (l, SImode)); |
a260abc9 DE |
7458 | }") |
7459 | ||
c4c40373 | 7460 | (define_insn "*movsf_hardfloat" |
f99f88e0 DE |
7461 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r") |
7462 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))] | |
d14a6d05 MM |
7463 | "(gpc_reg_operand (operands[0], SFmode) |
7464 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT" | |
1fd4e8c1 | 7465 | "@ |
f99f88e0 DE |
7466 | mr %0,%1 |
7467 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7468 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7469 | fmr %0,%1 |
7470 | lfs%U1%X1 %0,%1 | |
c4c40373 MM |
7471 | stfs%U0%X0 %1,%0 |
7472 | # | |
7473 | #" | |
f99f88e0 DE |
7474 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*") |
7475 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7476 | |
c4c40373 MM |
7477 | (define_insn "*movsf_softfloat" |
7478 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r") | |
9615f239 | 7479 | (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))] |
d14a6d05 MM |
7480 | "(gpc_reg_operand (operands[0], SFmode) |
7481 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT" | |
7482 | "@ | |
7483 | mr %0,%1 | |
7484 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7485 | {st%U0%X0|stw%U0%X0} %1,%0 | |
7486 | {lil|li} %0,%1 | |
802a0058 | 7487 | {liu|lis} %0,%v1 |
aee86b38 | 7488 | {cal|la} %0,%a1 |
c4c40373 MM |
7489 | # |
7490 | #" | |
7491 | [(set_attr "type" "*,load,store,*,*,*,*,*") | |
7492 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7493 | |
1fd4e8c1 RK |
7494 | \f |
7495 | (define_expand "movdf" | |
7496 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
7497 | (match_operand:DF 1 "any_operand" ""))] | |
7498 | "" | |
fb4d4348 | 7499 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
7500 | |
7501 | (define_split | |
cd2b37d9 | 7502 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 7503 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 7504 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7505 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7506 | || (GET_CODE (operands[0]) == SUBREG | |
7507 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7508 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7509 | [(set (match_dup 2) (match_dup 4)) |
7510 | (set (match_dup 3) (match_dup 1))] | |
7511 | " | |
7512 | { | |
5ae4759c | 7513 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
7514 | HOST_WIDE_INT value = INTVAL (operands[1]); |
7515 | ||
5ae4759c MM |
7516 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7517 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
7518 | #if HOST_BITS_PER_WIDE_INT == 32 |
7519 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
7520 | #else | |
7521 | operands[4] = GEN_INT (value >> 32); | |
7522 | operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
7523 | #endif | |
c4c40373 MM |
7524 | }") |
7525 | ||
c4c40373 MM |
7526 | (define_split |
7527 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
7528 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 7529 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7530 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7531 | || (GET_CODE (operands[0]) == SUBREG | |
7532 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7533 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7534 | [(set (match_dup 2) (match_dup 4)) |
7535 | (set (match_dup 3) (match_dup 5))] | |
7536 | " | |
7537 | { | |
5ae4759c | 7538 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
7539 | long l[2]; |
7540 | REAL_VALUE_TYPE rv; | |
7541 | ||
7542 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7543 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7544 | ||
5ae4759c MM |
7545 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7546 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
38886f37 AO |
7547 | operands[4] = GEN_INT (trunc_int_for_mode (l[endian], SImode)); |
7548 | operands[5] = GEN_INT (trunc_int_for_mode (l[1 - endian], SImode)); | |
c4c40373 MM |
7549 | }") |
7550 | ||
efc08378 DE |
7551 | (define_split |
7552 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 7553 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 7554 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7555 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7556 | || (GET_CODE (operands[0]) == SUBREG | |
7557 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7558 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 7559 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 7560 | " |
a260abc9 DE |
7561 | { |
7562 | int endian = (WORDS_BIG_ENDIAN == 0); | |
7563 | long l[2]; | |
7564 | REAL_VALUE_TYPE rv; | |
7565 | ||
7566 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7567 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7568 | ||
7569 | operands[2] = gen_lowpart (DImode, operands[0]); | |
7570 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
7571 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); | |
7572 | }") | |
efc08378 | 7573 | |
4eae5fe1 | 7574 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 7575 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
7576 | ;; a non-offsettable memref, but also it is less efficient than loading |
7577 | ;; the constant into an FP register, since it will probably be used there. | |
7578 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
7579 | ;; of handling these non-offsettable values. | |
c4c40373 | 7580 | (define_insn "*movdf_hardfloat32" |
000034eb DE |
7581 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
7582 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 7583 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
7584 | && (gpc_reg_operand (operands[0], DFmode) |
7585 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
7586 | "* |
7587 | { | |
7588 | switch (which_alternative) | |
7589 | { | |
a260abc9 | 7590 | default: |
a6c2a102 | 7591 | abort (); |
e7113111 RK |
7592 | case 0: |
7593 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
7594 | the first register operand 0 is the same as the second register |
7595 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 7596 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 7597 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 7598 | else |
deb9225a | 7599 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 7600 | case 1: |
2b97222d DE |
7601 | if (offsettable_memref_p (operands[1]) |
7602 | || (GET_CODE (operands[1]) == MEM | |
69f51a21 DE |
7603 | && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM |
7604 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC | |
7605 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))) | |
000034eb DE |
7606 | { |
7607 | /* If the low-address word is used in the address, we must load | |
7608 | it last. Otherwise, load it first. Note that we cannot have | |
7609 | auto-increment in that case since the address register is | |
7610 | known to be dead. */ | |
7611 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
7612 | operands[1], 0)) | |
7613 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
7614 | else | |
7615 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7616 | } | |
e7113111 | 7617 | else |
000034eb DE |
7618 | { |
7619 | rtx addreg; | |
7620 | ||
000034eb DE |
7621 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
7622 | if (refers_to_regno_p (REGNO (operands[0]), | |
7623 | REGNO (operands[0]) + 1, | |
7624 | operands[1], 0)) | |
7625 | { | |
7626 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 7627 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 7628 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 7629 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
7630 | } |
7631 | else | |
7632 | { | |
2b97222d | 7633 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 7634 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 7635 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
7636 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
7637 | return \"\"; | |
7638 | } | |
7639 | } | |
e7113111 | 7640 | case 2: |
2b97222d DE |
7641 | if (offsettable_memref_p (operands[0]) |
7642 | || (GET_CODE (operands[0]) == MEM | |
69f51a21 DE |
7643 | && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM |
7644 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC | |
7645 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))) | |
000034eb DE |
7646 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
7647 | else | |
7648 | { | |
7649 | rtx addreg; | |
7650 | ||
000034eb | 7651 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 7652 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 7653 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 7654 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
7655 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
7656 | return \"\"; | |
7657 | } | |
e7113111 | 7658 | case 3: |
e7113111 | 7659 | case 4: |
e7113111 | 7660 | case 5: |
c4c40373 | 7661 | return \"#\"; |
e7113111 | 7662 | case 6: |
c4c40373 MM |
7663 | return \"fmr %0,%1\"; |
7664 | case 7: | |
7665 | return \"lfd%U1%X1 %0,%1\"; | |
7666 | case 8: | |
e7113111 RK |
7667 | return \"stfd%U0%X0 %1,%0\"; |
7668 | } | |
7669 | }" | |
c4c40373 | 7670 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
2f76d42c | 7671 | (set_attr "length" "8,16,16,8,12,16,*,*,*")]) |
51b8fc2c | 7672 | |
c4c40373 | 7673 | (define_insn "*movdf_softfloat32" |
1427100a DE |
7674 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
7675 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 7676 | "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
7677 | && (gpc_reg_operand (operands[0], DFmode) |
7678 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
7679 | "* |
7680 | { | |
7681 | switch (which_alternative) | |
7682 | { | |
a260abc9 | 7683 | default: |
a6c2a102 | 7684 | abort (); |
dc4f83ca MM |
7685 | case 0: |
7686 | /* We normally copy the low-numbered register first. However, if | |
7687 | the first register operand 0 is the same as the second register of | |
7688 | operand 1, we must copy in the opposite order. */ | |
7689 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
7690 | return \"mr %L0,%L1\;mr %0,%1\"; | |
7691 | else | |
7692 | return \"mr %0,%1\;mr %L0,%L1\"; | |
7693 | case 1: | |
3cb999d8 DE |
7694 | /* If the low-address word is used in the address, we must load |
7695 | it last. Otherwise, load it first. Note that we cannot have | |
7696 | auto-increment in that case since the address register is | |
7697 | known to be dead. */ | |
dc4f83ca | 7698 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 7699 | operands[1], 0)) |
dc4f83ca MM |
7700 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
7701 | else | |
7702 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7703 | case 2: | |
7704 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
7705 | case 3: | |
c4c40373 MM |
7706 | case 4: |
7707 | case 5: | |
dc4f83ca MM |
7708 | return \"#\"; |
7709 | } | |
7710 | }" | |
c4c40373 MM |
7711 | [(set_attr "type" "*,load,store,*,*,*") |
7712 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 7713 | |
c4c40373 | 7714 | (define_insn "*movdf_hardfloat64" |
1427100a DE |
7715 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
7716 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 7717 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
7718 | && (gpc_reg_operand (operands[0], DFmode) |
7719 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 7720 | "@ |
3d5570cb RK |
7721 | mr %0,%1 |
7722 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 7723 | std%U0%X0 %1,%0 |
3d5570cb | 7724 | # |
c4c40373 MM |
7725 | # |
7726 | # | |
3d5570cb | 7727 | fmr %0,%1 |
f63184ac | 7728 | lfd%U1%X1 %0,%1 |
3d5570cb | 7729 | stfd%U0%X0 %1,%0" |
c4c40373 MM |
7730 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
7731 | (set_attr "length" "4,4,4,8,12,16,4,4,4")]) | |
dc4f83ca | 7732 | |
c4c40373 | 7733 | (define_insn "*movdf_softfloat64" |
1427100a DE |
7734 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
7735 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 7736 | "TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
7737 | && (gpc_reg_operand (operands[0], DFmode) |
7738 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
7739 | "@ |
7740 | mr %0,%1 | |
7741 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 7742 | std%U0%X0 %1,%0 |
c4c40373 MM |
7743 | # |
7744 | # | |
dc4f83ca | 7745 | #" |
c4c40373 MM |
7746 | [(set_attr "type" "*,load,store,*,*,*") |
7747 | (set_attr "length" "*,*,*,8,12,16")]) | |
1fd4e8c1 RK |
7748 | \f |
7749 | ;; Next come the multi-word integer load and store and the load and store | |
7750 | ;; multiple insns. | |
7751 | (define_expand "movdi" | |
7752 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 7753 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 | 7754 | "" |
fb4d4348 | 7755 | "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") |
1fd4e8c1 | 7756 | |
acad7ed3 | 7757 | (define_insn "*movdi_internal32" |
4e74d8ec MM |
7758 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") |
7759 | (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] | |
a260abc9 | 7760 | "! TARGET_POWERPC64 |
4e74d8ec MM |
7761 | && (gpc_reg_operand (operands[0], DImode) |
7762 | || gpc_reg_operand (operands[1], DImode))" | |
1fd4e8c1 RK |
7763 | "* |
7764 | { | |
7765 | switch (which_alternative) | |
7766 | { | |
a260abc9 | 7767 | default: |
a6c2a102 | 7768 | abort (); |
1fd4e8c1 RK |
7769 | case 0: |
7770 | /* We normally copy the low-numbered register first. However, if | |
7771 | the first register operand 0 is the same as the second register of | |
7772 | operand 1, we must copy in the opposite order. */ | |
7773 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 7774 | return \"mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 7775 | else |
deb9225a | 7776 | return \"mr %0,%1\;mr %L0,%L1\"; |
1fd4e8c1 RK |
7777 | case 1: |
7778 | /* If the low-address word is used in the address, we must load it | |
7779 | last. Otherwise, load it first. Note that we cannot have | |
7780 | auto-increment in that case since the address register is known to be | |
7781 | dead. */ | |
7782 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 7783 | operands[1], 0)) |
ca7f5001 | 7784 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
1fd4e8c1 | 7785 | else |
ca7f5001 | 7786 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 | 7787 | case 2: |
ca7f5001 | 7788 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8ffd9c51 RK |
7789 | case 3: |
7790 | return \"fmr %0,%1\"; | |
7791 | case 4: | |
7792 | return \"lfd%U1%X1 %0,%1\"; | |
7793 | case 5: | |
7794 | return \"stfd%U0%X0 %1,%0\"; | |
4e74d8ec MM |
7795 | case 6: |
7796 | case 7: | |
7797 | case 8: | |
7798 | case 9: | |
7799 | case 10: | |
7800 | return \"#\"; | |
1fd4e8c1 RK |
7801 | } |
7802 | }" | |
4e74d8ec MM |
7803 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*") |
7804 | (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")]) | |
7805 | ||
7806 | (define_split | |
7807 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7808 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 7809 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
7810 | [(set (match_dup 2) (match_dup 4)) |
7811 | (set (match_dup 3) (match_dup 1))] | |
7812 | " | |
7813 | { | |
5f59ecb7 | 7814 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
7815 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
7816 | DImode); | |
7817 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
7818 | DImode); | |
75d39459 | 7819 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 7820 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 7821 | #else |
5f59ecb7 DE |
7822 | operands[4] = GEN_INT (value >> 32); |
7823 | operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
75d39459 | 7824 | #endif |
4e74d8ec MM |
7825 | }") |
7826 | ||
4e74d8ec MM |
7827 | (define_split |
7828 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7829 | (match_operand:DI 1 "const_double_operand" ""))] | |
75d39459 | 7830 | "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
7831 | [(set (match_dup 2) (match_dup 4)) |
7832 | (set (match_dup 3) (match_dup 5))] | |
7833 | " | |
7834 | { | |
bdaa0181 GK |
7835 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
7836 | DImode); | |
7837 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
7838 | DImode); | |
f6968f59 MM |
7839 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
7840 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
4e74d8ec MM |
7841 | }") |
7842 | ||
acad7ed3 | 7843 | (define_insn "*movdi_internal64" |
e6ca2c17 | 7844 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h") |
9615f239 | 7845 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 7846 | "TARGET_POWERPC64 |
4e74d8ec MM |
7847 | && (gpc_reg_operand (operands[0], DImode) |
7848 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 7849 | "@ |
3d5570cb RK |
7850 | mr %0,%1 |
7851 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 7852 | std%U0%X0 %1,%0 |
3d5570cb | 7853 | li %0,%1 |
802a0058 | 7854 | lis %0,%v1 |
e6ca2c17 | 7855 | # |
aee86b38 | 7856 | {cal|la} %0,%a1 |
3d5570cb RK |
7857 | fmr %0,%1 |
7858 | lfd%U1%X1 %0,%1 | |
7859 | stfd%U0%X0 %1,%0 | |
7860 | mf%1 %0 | |
08075ead DE |
7861 | mt%0 %1 |
7862 | cror 0,0,0" | |
b7ff3d82 | 7863 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*") |
e6ca2c17 DE |
7864 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
7865 | ||
5f59ecb7 | 7866 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
7867 | (define_insn "" |
7868 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
7869 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
7870 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
7871 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
7872 | && num_insns_constant (operands[1], DImode) == 1" |
7873 | "* | |
7874 | { | |
7875 | return ((unsigned HOST_WIDE_INT) | |
7876 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
7877 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
7878 | }") | |
7879 | ||
5f59ecb7 | 7880 | ;; sign-extended 32-bit value |
a260abc9 DE |
7881 | (define_split |
7882 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7883 | (match_operand:DI 1 "const_int_operand" ""))] | |
7884 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
7885 | && num_insns_constant (operands[1], DImode) > 1" | |
7886 | [(set (match_dup 0) | |
7887 | (match_dup 2)) | |
7888 | (set (match_dup 0) | |
7889 | (ior:DI (match_dup 0) | |
7890 | (match_dup 3)))] | |
7891 | " | |
7892 | { | |
38886f37 | 7893 | operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); |
a260abc9 DE |
7894 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); |
7895 | }") | |
e6ca2c17 DE |
7896 | |
7897 | (define_split | |
7898 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7899 | (match_operand:DI 1 "const_double_operand" ""))] | |
a260abc9 DE |
7900 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
7901 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
7902 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
7903 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0) | |
5f59ecb7 | 7904 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 |
a260abc9 | 7905 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))" |
e6ca2c17 DE |
7906 | [(set (match_dup 0) |
7907 | (match_dup 2)) | |
7908 | (set (match_dup 0) | |
7909 | (ior:DI (match_dup 0) | |
a260abc9 DE |
7910 | (match_dup 3)))] |
7911 | " | |
7912 | { | |
38886f37 | 7913 | operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); |
a260abc9 DE |
7914 | operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff); |
7915 | }") | |
7916 | ||
5f59ecb7 DE |
7917 | (define_split |
7918 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7919 | (match_operand:DI 1 "const_int_operand" ""))] | |
7920 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
7921 | && GET_CODE (operands[1]) == CONST_INT | |
7922 | && (((INTVAL (operands[1]) >> 32) == 0 | |
7923 | && (INTVAL (operands[1]) & 0x80000000) == 0) | |
7924 | || ((INTVAL (operands[1]) >> 32) == -1 | |
7925 | && (INTVAL (operands[1]) & 0x80000000) != 0)) | |
7926 | && num_insns_constant (operands[1], DImode) > 1" | |
7927 | [(set (match_dup 0) | |
7928 | (match_dup 2)) | |
7929 | (set (match_dup 0) | |
7930 | (ior:DI (match_dup 0) | |
7931 | (match_dup 3)))] | |
7932 | " | |
7933 | { | |
38886f37 | 7934 | operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); |
5f59ecb7 DE |
7935 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); |
7936 | }") | |
7937 | ||
7938 | ;; zero-extended 32-bit value | |
a260abc9 DE |
7939 | (define_split |
7940 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7941 | (match_operand:DI 1 "const_double_operand" ""))] | |
7942 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
7943 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
7944 | && CONST_DOUBLE_HIGH (operands[1]) == 0 | |
7945 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0" | |
7946 | [(set (match_dup 0) | |
7947 | (match_dup 2)) | |
7948 | (set (match_dup 0) | |
e53ca51f | 7949 | (zero_extend:DI (match_dup 3)))] |
a260abc9 | 7950 | " |
e53ca51f GK |
7951 | { |
7952 | operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
7953 | operands[3] = gen_lowpart_common (SImode, operands[0]); | |
7954 | }") | |
a260abc9 | 7955 | |
5f59ecb7 DE |
7956 | (define_split |
7957 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7958 | (match_operand:DI 1 "const_int_operand" ""))] | |
7959 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
7960 | && GET_CODE (operands[1]) == CONST_INT | |
7961 | && INTVAL (operands[1]) >> 32 == 0 | |
7962 | && (INTVAL (operands[1]) & 0x80000000) != 0 | |
7963 | && num_insns_constant (operands[1], DImode) > 1" | |
7964 | [(set (match_dup 0) | |
7965 | (match_dup 2)) | |
7966 | (set (match_dup 0) | |
e53ca51f | 7967 | (zero_extend:DI (match_dup 3)))] |
5f59ecb7 | 7968 | " |
9ebbca7d GK |
7969 | { |
7970 | #if HOST_BITS_PER_WIDE_INT != 32 | |
78e1b90d | 7971 | operands[2] = GEN_INT ((INTVAL (operands[1]) ^ 0x80000000) - 0x80000000); |
9ebbca7d | 7972 | #endif |
e53ca51f | 7973 | operands[3] = gen_lowpart_common (SImode, operands[0]); |
9ebbca7d | 7974 | }") |
5f59ecb7 DE |
7975 | |
7976 | ;; 32-bit value in upper half of doubleword | |
a260abc9 DE |
7977 | (define_split |
7978 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7979 | (match_operand:DI 1 "const_double_operand" ""))] | |
7980 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
7981 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
7982 | && CONST_DOUBLE_LOW (operands[1]) == 0" | |
7983 | [(set (match_dup 0) | |
7984 | (match_dup 2)) | |
e6ca2c17 DE |
7985 | (set (match_dup 0) |
7986 | (ashift:DI (match_dup 0) | |
a260abc9 DE |
7987 | (const_int 32)))] |
7988 | " | |
7989 | { operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); }") | |
7990 | ||
5f59ecb7 DE |
7991 | (define_split |
7992 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7993 | (match_operand:DI 1 "const_int_operand" ""))] | |
7994 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
7995 | && GET_CODE (operands[1]) == CONST_INT | |
9ebbca7d | 7996 | && (INTVAL (operands[1]) & 0xffffffff) == 0" |
5f59ecb7 DE |
7997 | [(set (match_dup 0) |
7998 | (match_dup 2)) | |
7999 | (set (match_dup 0) | |
8000 | (ashift:DI (match_dup 0) | |
8001 | (const_int 32)))] | |
8002 | " | |
9ebbca7d GK |
8003 | { |
8004 | #if HOST_BITS_PER_WIDE_INT != 32 | |
8005 | operands[2] = GEN_INT (INTVAL (operands[1]) >> 32); | |
8006 | #endif | |
8007 | }") | |
5f59ecb7 | 8008 | |
a260abc9 DE |
8009 | ;; Generate all one-bits and clear left or right. |
8010 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8011 | (define_split | |
8012 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8013 | (match_operand:DI 1 "mask64_operand" ""))] | |
8014 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8015 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8016 | (set (match_dup 0) |
a260abc9 DE |
8017 | (and:DI (rotate:DI (match_dup 0) |
8018 | (const_int 0)) | |
8019 | (match_dup 1)))] | |
8020 | "") | |
8021 | ||
8022 | ;; Split a load of a large constant into the appropriate five-instruction | |
8023 | ;; sequence. Handle anything in a constant number of insns. | |
8024 | ;; When non-easy constants can go in the TOC, this should use | |
8025 | ;; easy_fp_constant predicate. | |
8026 | (define_split | |
8027 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8028 | (match_operand:DI 1 "const_double_operand" ""))] | |
5f59ecb7 DE |
8029 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8030 | && num_insns_constant (operands[1], DImode) > 1" | |
a260abc9 DE |
8031 | [(set (match_dup 0) |
8032 | (match_dup 2)) | |
8033 | (set (match_dup 0) | |
8034 | (ashift:DI (match_dup 0) | |
8035 | (const_int 32))) | |
e6ca2c17 DE |
8036 | (set (match_dup 0) |
8037 | (ior:DI (match_dup 0) | |
a260abc9 | 8038 | (match_dup 3)))] |
e6ca2c17 DE |
8039 | " |
8040 | { | |
e6ca2c17 DE |
8041 | if (GET_CODE (operands[1]) == CONST_DOUBLE) |
8042 | { | |
5f59ecb7 | 8043 | operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
9ebbca7d GK |
8044 | operands[3] = immed_double_const (CONST_DOUBLE_LOW (operands[1]), |
8045 | 0, DImode); | |
e6ca2c17 | 8046 | } |
e8d791dd | 8047 | else |
e6ca2c17 | 8048 | { |
5f59ecb7 DE |
8049 | HOST_WIDE_INT value = INTVAL (operands[1]); |
8050 | operands[2] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
9ebbca7d | 8051 | operands[3] = immed_double_const (value, 0, DImode); |
e6ca2c17 | 8052 | } |
5f59ecb7 | 8053 | }") |
e6ca2c17 | 8054 | |
5f59ecb7 DE |
8055 | (define_split |
8056 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8057 | (match_operand:DI 1 "const_int_operand" ""))] | |
8058 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
8059 | && num_insns_constant (operands[1], DImode) > 1" | |
8060 | [(set (match_dup 0) | |
8061 | (match_dup 2)) | |
8062 | (set (match_dup 0) | |
8063 | (ashift:DI (match_dup 0) | |
8064 | (const_int 32))) | |
8065 | (set (match_dup 0) | |
8066 | (ior:DI (match_dup 0) | |
8067 | (match_dup 3)))] | |
8068 | " | |
8069 | { | |
9ebbca7d | 8070 | #if HOST_BITS_PER_WIDE_INT != 32 |
5f59ecb7 DE |
8071 | HOST_WIDE_INT value = INTVAL (operands[1]); |
8072 | operands[2] = GEN_INT (value >> 32); | |
8073 | operands[3] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
9ebbca7d | 8074 | #endif |
e6ca2c17 | 8075 | }") |
08075ead | 8076 | |
acad7ed3 | 8077 | (define_insn "*movdi_internal2" |
9ebbca7d GK |
8078 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
8079 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
08075ead | 8080 | (const_int 0))) |
9ebbca7d | 8081 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
08075ead | 8082 | "TARGET_POWERPC64" |
9ebbca7d GK |
8083 | "@ |
8084 | mr. %0,%1 | |
8085 | #" | |
8086 | [(set_attr "type" "compare") | |
8087 | (set_attr "length" "4,8")]) | |
acad7ed3 | 8088 | |
9ebbca7d GK |
8089 | (define_split |
8090 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8091 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
8092 | (const_int 0))) | |
8093 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8094 | "TARGET_POWERPC64 && reload_completed" | |
8095 | [(set (match_dup 0) (match_dup 1)) | |
8096 | (set (match_dup 2) | |
8097 | (compare:CC (match_dup 0) | |
8098 | (const_int 0)))] | |
8099 | "") | |
acad7ed3 | 8100 | \f |
1fd4e8c1 RK |
8101 | ;; TImode is similar, except that we usually want to compute the address into |
8102 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8103 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8104 | (define_expand "movti" |
8105 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
8106 | (match_operand:TI 1 "general_operand" "")) | |
8107 | (clobber (scratch:SI))])] | |
7e69e155 | 8108 | "TARGET_STRING || TARGET_POWERPC64" |
fb4d4348 | 8109 | "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") |
1fd4e8c1 RK |
8110 | |
8111 | ;; We say that MQ is clobbered in the last alternative because the first | |
8112 | ;; alternative would never get used otherwise since it would need a reload | |
8113 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8114 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8115 | ;; giving the SCRATCH mq. | |
a260abc9 | 8116 | (define_insn "*movti_power" |
e1469d0d | 8117 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
8118 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
8119 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
7e69e155 | 8120 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8121 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8122 | "* |
8123 | { | |
8124 | switch (which_alternative) | |
8125 | { | |
dc4f83ca MM |
8126 | default: |
8127 | abort (); | |
8128 | ||
1fd4e8c1 | 8129 | case 0: |
ca7f5001 | 8130 | return \"{stsi|stswi} %1,%P0,16\"; |
1fd4e8c1 RK |
8131 | |
8132 | case 1: | |
ca7f5001 | 8133 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
1fd4e8c1 RK |
8134 | |
8135 | case 2: | |
8136 | /* Normally copy registers with lowest numbered register copied first. | |
8137 | But copy in the other order if the first register of the output | |
8138 | is the second, third, or fourth register in the input. */ | |
8139 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8140 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
deb9225a | 8141 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 8142 | else |
deb9225a | 8143 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; |
1fd4e8c1 RK |
8144 | case 3: |
8145 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8146 | fall through to generating four loads. */ | |
8147 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8148 | return \"{lsi|lswi} %0,%P1,16\"; |
1fd4e8c1 RK |
8149 | /* ... fall through ... */ |
8150 | case 4: | |
8151 | /* If the address register is the same as the register for the lowest- | |
8152 | addressed word, load it last. Similarly for the next two words. | |
8153 | Otherwise load lowest address to highest. */ | |
8154 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8155 | operands[1], 0)) | |
ca7f5001 | 8156 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; |
1fd4e8c1 RK |
8157 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, |
8158 | REGNO (operands[0]) + 2, operands[1], 0)) | |
ca7f5001 | 8159 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 RK |
8160 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, |
8161 | REGNO (operands[0]) + 3, operands[1], 0)) | |
ca7f5001 | 8162 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; |
1fd4e8c1 | 8163 | else |
ca7f5001 | 8164 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; |
1fd4e8c1 RK |
8165 | } |
8166 | }" | |
b7ff3d82 | 8167 | [(set_attr "type" "store,store,*,load,load") |
b19003d8 | 8168 | (set_attr "length" "*,16,16,*,16")]) |
51b8fc2c | 8169 | |
a260abc9 | 8170 | (define_insn "*movti_string" |
dc4f83ca MM |
8171 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r") |
8172 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,m")) | |
8173 | (clobber (match_scratch:SI 2 "=X,X,X"))] | |
0ad91047 | 8174 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8175 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8176 | "* | |
8177 | { | |
8178 | switch (which_alternative) | |
8179 | { | |
8180 | default: | |
8181 | abort (); | |
8182 | ||
8183 | case 0: | |
8184 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; | |
8185 | ||
8186 | case 1: | |
8187 | /* Normally copy registers with lowest numbered register copied first. | |
8188 | But copy in the other order if the first register of the output | |
8189 | is the second, third, or fourth register in the input. */ | |
8190 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8191 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
8192 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; | |
8193 | else | |
8194 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; | |
8195 | case 2: | |
8196 | /* If the address register is the same as the register for the lowest- | |
8197 | addressed word, load it last. Similarly for the next two words. | |
8198 | Otherwise load lowest address to highest. */ | |
8199 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8200 | operands[1], 0)) | |
8201 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; | |
8202 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, | |
8203 | REGNO (operands[0]) + 2, operands[1], 0)) | |
8204 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; | |
8205 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, | |
8206 | REGNO (operands[0]) + 3, operands[1], 0)) | |
8207 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; | |
8208 | else | |
8209 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; | |
8210 | } | |
8211 | }" | |
b7ff3d82 | 8212 | [(set_attr "type" "store,*,load") |
dc4f83ca MM |
8213 | (set_attr "length" "16,16,16")]) |
8214 | ||
a260abc9 | 8215 | (define_insn "*movti_ppc64" |
51b8fc2c RK |
8216 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") |
8217 | (match_operand:TI 1 "input_operand" "r,m,r"))] | |
8218 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) | |
8219 | || gpc_reg_operand (operands[1], TImode))" | |
8220 | "* | |
8221 | { | |
8222 | switch (which_alternative) | |
8223 | { | |
a260abc9 | 8224 | default: |
a6c2a102 | 8225 | abort (); |
51b8fc2c RK |
8226 | case 0: |
8227 | /* We normally copy the low-numbered register first. However, if | |
8228 | the first register operand 0 is the same as the second register of | |
8229 | operand 1, we must copy in the opposite order. */ | |
8230 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8231 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8232 | else | |
8233 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8234 | case 1: | |
8235 | /* If the low-address word is used in the address, we must load it | |
8236 | last. Otherwise, load it first. Note that we cannot have | |
8237 | auto-increment in that case since the address register is known to be | |
8238 | dead. */ | |
8239 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 8240 | operands[1], 0)) |
51b8fc2c RK |
8241 | return \"ld %L0,%L1\;ld %0,%1\"; |
8242 | else | |
8243 | return \"ld%U1 %0,%1\;ld %L0,%L1\"; | |
8244 | case 2: | |
8245 | return \"std%U0 %1,%0\;std %L1,%L0\"; | |
8246 | } | |
8247 | }" | |
b7ff3d82 | 8248 | [(set_attr "type" "*,load,store") |
51b8fc2c | 8249 | (set_attr "length" "8,8,8")]) |
1fd4e8c1 RK |
8250 | \f |
8251 | (define_expand "load_multiple" | |
2f622005 RK |
8252 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8253 | (match_operand:SI 1 "" "")) | |
8254 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 8255 | "TARGET_STRING" |
1fd4e8c1 RK |
8256 | " |
8257 | { | |
8258 | int regno; | |
8259 | int count; | |
792760b9 | 8260 | rtx op1; |
1fd4e8c1 RK |
8261 | int i; |
8262 | ||
8263 | /* Support only loading a constant number of fixed-point registers from | |
8264 | memory and only bother with this if more than two; the machine | |
8265 | doesn't support more than eight. */ | |
8266 | if (GET_CODE (operands[2]) != CONST_INT | |
8267 | || INTVAL (operands[2]) <= 2 | |
8268 | || INTVAL (operands[2]) > 8 | |
8269 | || GET_CODE (operands[1]) != MEM | |
8270 | || GET_CODE (operands[0]) != REG | |
8271 | || REGNO (operands[0]) >= 32) | |
8272 | FAIL; | |
8273 | ||
8274 | count = INTVAL (operands[2]); | |
8275 | regno = REGNO (operands[0]); | |
8276 | ||
39403d82 | 8277 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
8278 | op1 = replace_equiv_address (operands[1], |
8279 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
8280 | |
8281 | for (i = 0; i < count; i++) | |
8282 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8283 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
792760b9 | 8284 | adjust_address (op1, SImode, i * 4)); |
1fd4e8c1 RK |
8285 | }") |
8286 | ||
8287 | (define_insn "" | |
8288 | [(match_parallel 0 "load_multiple_operation" | |
cd2b37d9 | 8289 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") |
52d3af72 | 8290 | (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])] |
7e69e155 | 8291 | "TARGET_STRING" |
1fd4e8c1 RK |
8292 | "* |
8293 | { | |
8294 | /* We have to handle the case where the pseudo used to contain the address | |
e82ee4cc RK |
8295 | is assigned to one of the output registers. */ |
8296 | int i, j; | |
8297 | int words = XVECLEN (operands[0], 0); | |
8298 | rtx xop[10]; | |
8299 | ||
8300 | if (XVECLEN (operands[0], 0) == 1) | |
8301 | return \"{l|lwz} %1,0(%2)\"; | |
1fd4e8c1 | 8302 | |
e82ee4cc | 8303 | for (i = 0; i < words; i++) |
1fd4e8c1 RK |
8304 | if (refers_to_regno_p (REGNO (operands[1]) + i, |
8305 | REGNO (operands[1]) + i + 1, operands[2], 0)) | |
8306 | { | |
e82ee4cc RK |
8307 | if (i == words-1) |
8308 | { | |
8309 | xop[0] = operands[1]; | |
8310 | xop[1] = operands[2]; | |
8311 | xop[2] = GEN_INT (4 * (words-1)); | |
d89ddcfd | 8312 | output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop); |
e82ee4cc RK |
8313 | return \"\"; |
8314 | } | |
8315 | else if (i == 0) | |
8316 | { | |
8317 | xop[0] = operands[1]; | |
39403d82 | 8318 | xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
e82ee4cc RK |
8319 | xop[2] = GEN_INT (4 * (words-1)); |
8320 | output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop); | |
8321 | return \"\"; | |
8322 | } | |
8323 | else | |
8324 | { | |
8325 | for (j = 0; j < words; j++) | |
8326 | if (j != i) | |
8327 | { | |
39403d82 | 8328 | xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j); |
e82ee4cc RK |
8329 | xop[1] = operands[2]; |
8330 | xop[2] = GEN_INT (j * 4); | |
8331 | output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop); | |
8332 | } | |
8333 | xop[0] = operands[2]; | |
8334 | xop[1] = GEN_INT (i * 4); | |
8335 | output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop); | |
8336 | return \"\"; | |
8337 | } | |
1fd4e8c1 RK |
8338 | } |
8339 | ||
e82ee4cc | 8340 | return \"{lsi|lswi} %1,%2,%N0\"; |
1fd4e8c1 | 8341 | }" |
b19003d8 | 8342 | [(set_attr "type" "load") |
e82ee4cc | 8343 | (set_attr "length" "32")]) |
b19003d8 | 8344 | |
b7ff3d82 | 8345 | \f |
1fd4e8c1 | 8346 | (define_expand "store_multiple" |
2f622005 RK |
8347 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8348 | (match_operand:SI 1 "" "")) | |
8349 | (clobber (scratch:SI)) | |
8350 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 8351 | "TARGET_STRING" |
1fd4e8c1 RK |
8352 | " |
8353 | { | |
8354 | int regno; | |
8355 | int count; | |
8356 | rtx to; | |
792760b9 | 8357 | rtx op0; |
1fd4e8c1 RK |
8358 | int i; |
8359 | ||
8360 | /* Support only storing a constant number of fixed-point registers to | |
8361 | memory and only bother with this if more than two; the machine | |
8362 | doesn't support more than eight. */ | |
8363 | if (GET_CODE (operands[2]) != CONST_INT | |
8364 | || INTVAL (operands[2]) <= 2 | |
8365 | || INTVAL (operands[2]) > 8 | |
8366 | || GET_CODE (operands[0]) != MEM | |
8367 | || GET_CODE (operands[1]) != REG | |
8368 | || REGNO (operands[1]) >= 32) | |
8369 | FAIL; | |
8370 | ||
8371 | count = INTVAL (operands[2]); | |
8372 | regno = REGNO (operands[1]); | |
8373 | ||
39403d82 | 8374 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 8375 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 8376 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
8377 | |
8378 | XVECEXP (operands[3], 0, 0) | |
792760b9 | 8379 | = gen_rtx_SET (VOIDmode, op0, operands[1]); |
39403d82 | 8380 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8381 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8382 | |
8383 | for (i = 1; i < count; i++) | |
8384 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8385 | = gen_rtx_SET (VOIDmode, |
792760b9 | 8386 | adjust_address (op0, SImode, i * 4), |
c5c76735 | 8387 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
8388 | }") |
8389 | ||
8390 | (define_insn "" | |
8391 | [(match_parallel 0 "store_multiple_operation" | |
8392 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 8393 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 8394 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 8395 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
8396 | "{stsi|stswi} %2,%P1,%O0" |
8397 | [(set_attr "type" "store")]) | |
d14a6d05 MM |
8398 | |
8399 | (define_insn "" | |
8400 | [(match_parallel 0 "store_multiple_operation" | |
52d3af72 | 8401 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
d14a6d05 MM |
8402 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
8403 | (clobber (match_scratch:SI 3 "X"))])] | |
0ad91047 | 8404 | "TARGET_STRING && ! TARGET_POWER" |
b7ff3d82 DE |
8405 | "{stsi|stswi} %2,%1,%O0" |
8406 | [(set_attr "type" "store")]) | |
7e69e155 MM |
8407 | |
8408 | \f | |
8409 | ;; String/block move insn. | |
8410 | ;; Argument 0 is the destination | |
8411 | ;; Argument 1 is the source | |
8412 | ;; Argument 2 is the length | |
8413 | ;; Argument 3 is the alignment | |
8414 | ||
8415 | (define_expand "movstrsi" | |
b6c9286a MM |
8416 | [(parallel [(set (match_operand:BLK 0 "" "") |
8417 | (match_operand:BLK 1 "" "")) | |
8418 | (use (match_operand:SI 2 "" "")) | |
8419 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
8420 | "" |
8421 | " | |
8422 | { | |
8423 | if (expand_block_move (operands)) | |
8424 | DONE; | |
8425 | else | |
8426 | FAIL; | |
8427 | }") | |
8428 | ||
8429 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8430 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
8431 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8432 | (define_expand "movstrsi_8reg" |
b6c9286a MM |
8433 | [(parallel [(set (match_operand 0 "" "") |
8434 | (match_operand 1 "" "")) | |
8435 | (use (match_operand 2 "" "")) | |
8436 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
8437 | (clobber (reg:SI 5)) |
8438 | (clobber (reg:SI 6)) | |
8439 | (clobber (reg:SI 7)) | |
8440 | (clobber (reg:SI 8)) | |
8441 | (clobber (reg:SI 9)) | |
8442 | (clobber (reg:SI 10)) | |
8443 | (clobber (reg:SI 11)) | |
8444 | (clobber (reg:SI 12)) | |
3c67b673 | 8445 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8446 | "TARGET_STRING" |
8447 | "") | |
8448 | ||
8449 | (define_insn "" | |
52d3af72 DE |
8450 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8451 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8452 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8453 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8454 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8455 | (clobber (reg:SI 6)) |
8456 | (clobber (reg:SI 7)) | |
8457 | (clobber (reg:SI 8)) | |
8458 | (clobber (reg:SI 9)) | |
8459 | (clobber (reg:SI 10)) | |
8460 | (clobber (reg:SI 11)) | |
8461 | (clobber (reg:SI 12)) | |
3c67b673 | 8462 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 8463 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
8464 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8465 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8466 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8467 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8468 | && REGNO (operands[4]) == 5" |
8469 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8470 | [(set_attr "type" "load") |
8471 | (set_attr "length" "8")]) | |
7e69e155 MM |
8472 | |
8473 | (define_insn "" | |
52d3af72 DE |
8474 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8475 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8476 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8477 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8478 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8479 | (clobber (reg:SI 6)) |
8480 | (clobber (reg:SI 7)) | |
8481 | (clobber (reg:SI 8)) | |
8482 | (clobber (reg:SI 9)) | |
8483 | (clobber (reg:SI 10)) | |
8484 | (clobber (reg:SI 11)) | |
8485 | (clobber (reg:SI 12)) | |
3c67b673 | 8486 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8487 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
8488 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8489 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8490 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8491 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8492 | && REGNO (operands[4]) == 5" |
8493 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8494 | [(set_attr "type" "load") |
8495 | (set_attr "length" "8")]) | |
7e69e155 MM |
8496 | |
8497 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8498 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
8499 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8500 | (define_expand "movstrsi_6reg" |
b6c9286a MM |
8501 | [(parallel [(set (match_operand 0 "" "") |
8502 | (match_operand 1 "" "")) | |
8503 | (use (match_operand 2 "" "")) | |
8504 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
8505 | (clobber (reg:SI 5)) |
8506 | (clobber (reg:SI 6)) | |
7e69e155 MM |
8507 | (clobber (reg:SI 7)) |
8508 | (clobber (reg:SI 8)) | |
8509 | (clobber (reg:SI 9)) | |
8510 | (clobber (reg:SI 10)) | |
3c67b673 | 8511 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8512 | "TARGET_STRING" |
8513 | "") | |
8514 | ||
8515 | (define_insn "" | |
52d3af72 DE |
8516 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8517 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8518 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8519 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8520 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8521 | (clobber (reg:SI 6)) |
8522 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8523 | (clobber (reg:SI 8)) |
8524 | (clobber (reg:SI 9)) | |
8525 | (clobber (reg:SI 10)) | |
3c67b673 | 8526 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
8527 | "TARGET_STRING && TARGET_POWER |
8528 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
8529 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8530 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8531 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8532 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8533 | [(set_attr "type" "load") |
8534 | (set_attr "length" "8")]) | |
7e69e155 MM |
8535 | |
8536 | (define_insn "" | |
52d3af72 DE |
8537 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8538 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8539 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8540 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8541 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8542 | (clobber (reg:SI 6)) |
8543 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8544 | (clobber (reg:SI 8)) |
8545 | (clobber (reg:SI 9)) | |
8546 | (clobber (reg:SI 10)) | |
3c67b673 | 8547 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8548 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8549 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
8550 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8551 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8552 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8553 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8554 | [(set_attr "type" "load") |
8555 | (set_attr "length" "8")]) | |
7e69e155 | 8556 | |
f9562f27 DE |
8557 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
8558 | ;; problems with TImode. | |
8559 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8560 | (define_expand "movstrsi_4reg" |
b6c9286a MM |
8561 | [(parallel [(set (match_operand 0 "" "") |
8562 | (match_operand 1 "" "")) | |
8563 | (use (match_operand 2 "" "")) | |
8564 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
8565 | (clobber (reg:SI 5)) |
8566 | (clobber (reg:SI 6)) | |
8567 | (clobber (reg:SI 7)) | |
8568 | (clobber (reg:SI 8)) | |
3c67b673 | 8569 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8570 | "TARGET_STRING" |
8571 | "") | |
8572 | ||
8573 | (define_insn "" | |
52d3af72 DE |
8574 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8575 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8576 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8577 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8578 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8579 | (clobber (reg:SI 6)) |
8580 | (clobber (reg:SI 7)) | |
8581 | (clobber (reg:SI 8)) | |
3c67b673 | 8582 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
8583 | "TARGET_STRING && TARGET_POWER |
8584 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
8585 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
8586 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
8587 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8588 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8589 | [(set_attr "type" "load") |
8590 | (set_attr "length" "8")]) | |
7e69e155 MM |
8591 | |
8592 | (define_insn "" | |
52d3af72 DE |
8593 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8594 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8595 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8596 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8597 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8598 | (clobber (reg:SI 6)) |
8599 | (clobber (reg:SI 7)) | |
8600 | (clobber (reg:SI 8)) | |
3c67b673 | 8601 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8602 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8603 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
8604 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
8605 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
8606 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8607 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8608 | [(set_attr "type" "load") |
8609 | (set_attr "length" "8")]) | |
7e69e155 MM |
8610 | |
8611 | ;; Move up to 8 bytes at a time. | |
8612 | (define_expand "movstrsi_2reg" | |
b6c9286a MM |
8613 | [(parallel [(set (match_operand 0 "" "") |
8614 | (match_operand 1 "" "")) | |
8615 | (use (match_operand 2 "" "")) | |
8616 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
8617 | (clobber (match_scratch:DI 4 "")) |
8618 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 8619 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
8620 | "") |
8621 | ||
8622 | (define_insn "" | |
52d3af72 DE |
8623 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8624 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8625 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8626 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8627 | (clobber (match_scratch:DI 4 "=&r")) | |
8628 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 8629 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
8630 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
8631 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8632 | [(set_attr "type" "load") |
8633 | (set_attr "length" "8")]) | |
7e69e155 MM |
8634 | |
8635 | (define_insn "" | |
52d3af72 DE |
8636 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8637 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8638 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8639 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8640 | (clobber (match_scratch:DI 4 "=&r")) | |
8641 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 8642 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 8643 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 8644 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8645 | [(set_attr "type" "load") |
8646 | (set_attr "length" "8")]) | |
7e69e155 MM |
8647 | |
8648 | ;; Move up to 4 bytes at a time. | |
8649 | (define_expand "movstrsi_1reg" | |
b6c9286a MM |
8650 | [(parallel [(set (match_operand 0 "" "") |
8651 | (match_operand 1 "" "")) | |
8652 | (use (match_operand 2 "" "")) | |
8653 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
8654 | (clobber (match_scratch:SI 4 "")) |
8655 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
8656 | "TARGET_STRING" |
8657 | "") | |
8658 | ||
8659 | (define_insn "" | |
52d3af72 DE |
8660 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8661 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8662 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8663 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8664 | (clobber (match_scratch:SI 4 "=&r")) | |
8665 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
8666 | "TARGET_STRING && TARGET_POWER |
8667 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 8668 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8669 | [(set_attr "type" "load") |
8670 | (set_attr "length" "8")]) | |
7e69e155 MM |
8671 | |
8672 | (define_insn "" | |
52d3af72 DE |
8673 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8674 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8675 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8676 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8677 | (clobber (match_scratch:SI 4 "=&r")) | |
8678 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 8679 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8680 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
3c67b673 | 8681 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8682 | [(set_attr "type" "load") |
8683 | (set_attr "length" "8")]) | |
7e69e155 | 8684 | |
1fd4e8c1 | 8685 | \f |
7e69e155 | 8686 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
8687 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
8688 | ;; do cases where the increment is not the size of the object. | |
8689 | ;; | |
8690 | ;; In all these cases, we use operands 0 and 1 for the register being | |
8691 | ;; incremented because those are the operands that local-alloc will | |
8692 | ;; tie and these are the pair most likely to be tieable (and the ones | |
8693 | ;; that will benefit the most). | |
8694 | ||
38c1f2d7 | 8695 | (define_insn "*movdi_update1" |
51b8fc2c | 8696 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 8697 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
51b8fc2c RK |
8698 | (match_operand:DI 2 "reg_or_short_operand" "r,I")))) |
8699 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
8700 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 8701 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
8702 | "@ |
8703 | ldux %3,%0,%2 | |
8704 | ldu %3,%2(%0)" | |
8705 | [(set_attr "type" "load")]) | |
8706 | ||
38c1f2d7 | 8707 | (define_insn "*movdi_update2" |
287f13ff RK |
8708 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") |
8709 | (sign_extend:DI | |
8710 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
8711 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
8712 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
8713 | (plus:DI (match_dup 1) (match_dup 2)))] | |
8714 | "TARGET_POWERPC64" | |
8715 | "lwaux %3,%0,%2" | |
8716 | [(set_attr "type" "load")]) | |
8717 | ||
4697a36c | 8718 | (define_insn "movdi_update" |
51b8fc2c RK |
8719 | [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
8720 | (match_operand:DI 2 "reg_or_short_operand" "r,I"))) | |
8721 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) | |
8722 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
8723 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 8724 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
8725 | "@ |
8726 | stdux %3,%0,%2 | |
b7ff3d82 DE |
8727 | stdu %3,%2(%0)" |
8728 | [(set_attr "type" "store")]) | |
51b8fc2c | 8729 | |
38c1f2d7 | 8730 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
8731 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
8732 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8733 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8734 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
8735 | (plus:SI (match_dup 1) (match_dup 2)))] |
8736 | "" | |
8737 | "@ | |
ca7f5001 RK |
8738 | {lux|lwzux} %3,%0,%2 |
8739 | {lu|lwzu} %3,%2(%0)" | |
cfb557c4 | 8740 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8741 | |
4697a36c | 8742 | (define_insn "movsi_update" |
cd2b37d9 | 8743 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8744 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8745 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
8746 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8747 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8748 | "TARGET_UPDATE" |
1fd4e8c1 | 8749 | "@ |
ca7f5001 | 8750 | {stux|stwux} %3,%0,%2 |
b7ff3d82 DE |
8751 | {stu|stwu} %3,%2(%0)" |
8752 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 8753 | |
38c1f2d7 | 8754 | (define_insn "*movhi_update" |
cd2b37d9 RK |
8755 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
8756 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8757 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8758 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8759 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8760 | "TARGET_UPDATE" |
1fd4e8c1 | 8761 | "@ |
5f243543 RK |
8762 | lhzux %3,%0,%2 |
8763 | lhzu %3,%2(%0)" | |
cfb557c4 | 8764 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8765 | |
38c1f2d7 | 8766 | (define_insn "*movhi_update2" |
cd2b37d9 | 8767 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8768 | (zero_extend:SI |
cd2b37d9 | 8769 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8770 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8771 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8772 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8773 | "TARGET_UPDATE" |
1fd4e8c1 | 8774 | "@ |
5f243543 RK |
8775 | lhzux %3,%0,%2 |
8776 | lhzu %3,%2(%0)" | |
cfb557c4 | 8777 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8778 | |
38c1f2d7 | 8779 | (define_insn "*movhi_update3" |
cd2b37d9 | 8780 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8781 | (sign_extend:SI |
cd2b37d9 | 8782 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8783 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8784 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8785 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8786 | "TARGET_UPDATE" |
1fd4e8c1 | 8787 | "@ |
5f243543 RK |
8788 | lhaux %3,%0,%2 |
8789 | lhau %3,%2(%0)" | |
cfb557c4 | 8790 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8791 | |
38c1f2d7 | 8792 | (define_insn "*movhi_update4" |
cd2b37d9 | 8793 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8794 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8795 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
8796 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8797 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8798 | "TARGET_UPDATE" |
1fd4e8c1 | 8799 | "@ |
5f243543 | 8800 | sthux %3,%0,%2 |
b7ff3d82 DE |
8801 | sthu %3,%2(%0)" |
8802 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 8803 | |
38c1f2d7 | 8804 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
8805 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
8806 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8807 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8808 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8809 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8810 | "TARGET_UPDATE" |
1fd4e8c1 | 8811 | "@ |
5f243543 RK |
8812 | lbzux %3,%0,%2 |
8813 | lbzu %3,%2(%0)" | |
cfb557c4 | 8814 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8815 | |
38c1f2d7 | 8816 | (define_insn "*movqi_update2" |
cd2b37d9 | 8817 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8818 | (zero_extend:SI |
cd2b37d9 | 8819 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8820 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8821 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8822 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8823 | "TARGET_UPDATE" |
1fd4e8c1 | 8824 | "@ |
5f243543 RK |
8825 | lbzux %3,%0,%2 |
8826 | lbzu %3,%2(%0)" | |
cfb557c4 | 8827 | [(set_attr "type" "load")]) |
1fd4e8c1 | 8828 | |
38c1f2d7 | 8829 | (define_insn "*movqi_update3" |
cd2b37d9 | 8830 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8831 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8832 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
8833 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8834 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8835 | "TARGET_UPDATE" |
1fd4e8c1 | 8836 | "@ |
5f243543 | 8837 | stbux %3,%0,%2 |
b7ff3d82 DE |
8838 | stbu %3,%2(%0)" |
8839 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 8840 | |
38c1f2d7 | 8841 | (define_insn "*movsf_update1" |
cd2b37d9 | 8842 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 8843 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8844 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8845 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8846 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8847 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 8848 | "@ |
5f243543 RK |
8849 | lfsux %3,%0,%2 |
8850 | lfsu %3,%2(%0)" | |
cfb557c4 | 8851 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 8852 | |
38c1f2d7 | 8853 | (define_insn "*movsf_update2" |
cd2b37d9 | 8854 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8855 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8856 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
8857 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8858 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8859 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 8860 | "@ |
85fff2f3 | 8861 | stfsux %3,%0,%2 |
b7ff3d82 DE |
8862 | stfsu %3,%2(%0)" |
8863 | [(set_attr "type" "fpstore")]) | |
1fd4e8c1 | 8864 | |
38c1f2d7 MM |
8865 | (define_insn "*movsf_update3" |
8866 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
8867 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
8868 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
8869 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
8870 | (plus:SI (match_dup 1) (match_dup 2)))] | |
8871 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
8872 | "@ | |
8873 | {lux|lwzux} %3,%0,%2 | |
8874 | {lu|lwzu} %3,%2(%0)" | |
8875 | [(set_attr "type" "load")]) | |
8876 | ||
8877 | (define_insn "*movsf_update4" | |
8878 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
8879 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
8880 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
8881 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
8882 | (plus:SI (match_dup 1) (match_dup 2)))] | |
8883 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
8884 | "@ | |
8885 | {stux|stwux} %3,%0,%2 | |
8886 | {stu|stwu} %3,%2(%0)" | |
8887 | [(set_attr "type" "store")]) | |
8888 | ||
8889 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
8890 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
8891 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8892 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8893 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8894 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8895 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 8896 | "@ |
5f243543 RK |
8897 | lfdux %3,%0,%2 |
8898 | lfdu %3,%2(%0)" | |
cfb557c4 | 8899 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 8900 | |
38c1f2d7 | 8901 | (define_insn "*movdf_update2" |
cd2b37d9 | 8902 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8903 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8904 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
8905 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8906 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8907 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 8908 | "@ |
5f243543 | 8909 | stfdux %3,%0,%2 |
b7ff3d82 DE |
8910 | stfdu %3,%2(%0)" |
8911 | [(set_attr "type" "fpstore")]) | |
4c70a4f3 RK |
8912 | |
8913 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
8914 | ||
8915 | (define_peephole | |
8916 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8917 | (match_operand:DF 1 "memory_operand" "")) | |
8918 | (set (match_operand:DF 2 "gpc_reg_operand" "=f") | |
8919 | (match_operand:DF 3 "memory_operand" ""))] | |
8920 | "TARGET_POWER2 | |
d14a6d05 | 8921 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
8922 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
8923 | && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) | |
8924 | && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" | |
8925 | "lfq%U1%X1 %0,%1") | |
8926 | ||
8927 | (define_peephole | |
8928 | [(set (match_operand:DF 0 "memory_operand" "") | |
8929 | (match_operand:DF 1 "gpc_reg_operand" "f")) | |
8930 | (set (match_operand:DF 2 "memory_operand" "") | |
8931 | (match_operand:DF 3 "gpc_reg_operand" "f"))] | |
8932 | "TARGET_POWER2 | |
d14a6d05 | 8933 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
8934 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
8935 | && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) | |
8936 | && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" | |
8937 | "stfq%U0%X0 %1,%0") | |
1fd4e8c1 RK |
8938 | \f |
8939 | ;; Next come insns related to the calling sequence. | |
8940 | ;; | |
8941 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 8942 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
8943 | |
8944 | (define_expand "allocate_stack" | |
52d3af72 | 8945 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
8946 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
8947 | (set (reg 1) | |
8948 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
8949 | "" |
8950 | " | |
4697a36c | 8951 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 8952 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 8953 | rtx neg_op0; |
1fd4e8c1 RK |
8954 | |
8955 | emit_move_insn (chain, stack_bot); | |
4697a36c | 8956 | |
a157febd GK |
8957 | /* Check stack bounds if necessary. */ |
8958 | if (current_function_limit_stack) | |
8959 | { | |
8960 | rtx available; | |
8961 | available = expand_binop (Pmode, sub_optab, | |
8962 | stack_pointer_rtx, stack_limit_rtx, | |
8963 | NULL_RTX, 1, OPTAB_WIDEN); | |
8964 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
8965 | } | |
8966 | ||
e9a25f70 JL |
8967 | if (GET_CODE (operands[1]) != CONST_INT |
8968 | || INTVAL (operands[1]) < -32767 | |
8969 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
8970 | { |
8971 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 8972 | if (TARGET_32BIT) |
e9a25f70 | 8973 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 8974 | else |
e9a25f70 | 8975 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
8976 | } |
8977 | else | |
e9a25f70 | 8978 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 8979 | |
38c1f2d7 MM |
8980 | if (TARGET_UPDATE) |
8981 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) | |
8982 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); | |
4697a36c | 8983 | |
38c1f2d7 MM |
8984 | else |
8985 | { | |
8986 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
8987 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 8988 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 8989 | } |
e9a25f70 JL |
8990 | |
8991 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
8992 | DONE; |
8993 | }") | |
59257ff7 RK |
8994 | |
8995 | ;; These patterns say how to save and restore the stack pointer. We need not | |
8996 | ;; save the stack pointer at function level since we are careful to | |
8997 | ;; preserve the backchain. At block level, we have to restore the backchain | |
8998 | ;; when we restore the stack pointer. | |
8999 | ;; | |
9000 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9001 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9002 | ;; save area is a memory location. | |
9003 | ||
9004 | (define_expand "save_stack_function" | |
ff381587 MM |
9005 | [(match_operand 0 "any_operand" "") |
9006 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9007 | "" |
ff381587 | 9008 | "DONE;") |
59257ff7 RK |
9009 | |
9010 | (define_expand "restore_stack_function" | |
ff381587 MM |
9011 | [(match_operand 0 "any_operand" "") |
9012 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9013 | "" |
ff381587 | 9014 | "DONE;") |
59257ff7 RK |
9015 | |
9016 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
9017 | [(use (match_operand 0 "register_operand" "")) |
9018 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 9019 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 9020 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
9021 | "" |
9022 | " | |
dfdfa60f DE |
9023 | { |
9024 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 9025 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 9026 | }") |
59257ff7 RK |
9027 | |
9028 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
9029 | [(match_operand 0 "memory_operand" "") |
9030 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
9031 | "" |
9032 | " | |
9033 | { | |
a260abc9 | 9034 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
9035 | |
9036 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 9037 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
c5c76735 JL |
9038 | emit_move_insn (operand_subword (operands[0], 0, 0, |
9039 | (TARGET_32BIT ? DImode : TImode)), | |
a260abc9 DE |
9040 | temp); |
9041 | emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)), | |
9042 | operands[1]); | |
59257ff7 RK |
9043 | DONE; |
9044 | }") | |
7e69e155 | 9045 | |
59257ff7 | 9046 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
9047 | [(match_operand 0 "register_operand" "") |
9048 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
9049 | "" |
9050 | " | |
9051 | { | |
a260abc9 | 9052 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
9053 | |
9054 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 DE |
9055 | emit_move_insn (temp, |
9056 | operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode))); | |
9057 | emit_move_insn (operands[0], | |
c5c76735 JL |
9058 | operand_subword (operands[1], 1, 0, |
9059 | (TARGET_32BIT ? DImode : TImode))); | |
39403d82 | 9060 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
9061 | DONE; |
9062 | }") | |
9ebbca7d GK |
9063 | \f |
9064 | ;; TOC register handling. | |
b6c9286a | 9065 | |
9ebbca7d | 9066 | ;; Code to initialize the TOC register... |
f0f6a223 | 9067 | |
9ebbca7d GK |
9068 | (define_insn "load_toc_aix_si" |
9069 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9070 | (unspec:SI [(const_int 0)] 7))] | |
9071 | "! TARGET_ELF && TARGET_32BIT" | |
f0f6a223 RK |
9072 | "* |
9073 | { | |
9ebbca7d GK |
9074 | char buf[30]; |
9075 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 9076 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9077 | operands[2] = gen_rtx_REG (Pmode, 2); |
9078 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
9079 | }" |
9080 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
9081 | |
9082 | (define_insn "load_toc_aix_di" | |
9083 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9084 | (unspec:DI [(const_int 0)] 7))] | |
9085 | "! TARGET_ELF && TARGET_64BIT" | |
9086 | "* | |
9087 | { | |
9088 | char buf[30]; | |
9089 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 9090 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9091 | operands[2] = gen_rtx_REG (Pmode, 2); |
9092 | return \"ld %0,%1(%2)\"; | |
9093 | }" | |
9094 | [(set_attr "type" "load")]) | |
9095 | ||
9096 | (define_insn "load_toc_v4_pic_si" | |
9097 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9098 | (unspec:SI [(const_int 0)] 7))] | |
9099 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1 | |
9100 | && TARGET_32BIT" | |
9101 | "bl _GLOBAL_OFFSET_TABLE_@local-4" | |
9102 | [(set_attr "type" "branch") | |
9103 | (set_attr "length" "4")]) | |
9104 | ||
9105 | (define_insn "load_toc_v4_pic_di" | |
9106 | [(set (match_operand:DI 0 "register_operand" "=l") | |
9107 | (unspec:DI [(const_int 0)] 7))] | |
9108 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1 | |
9109 | && TARGET_64BIT" | |
9110 | "bl _GLOBAL_OFFSET_TABLE_@local-4" | |
9111 | [(set_attr "type" "branch") | |
9112 | (set_attr "length" "4")]) | |
9113 | ||
9114 | (define_insn "load_toc_v4_PIC_1" | |
9115 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9116 | (match_operand:SI 1 "immediate_operand" "s")) | |
9117 | (unspec [(match_dup 1)] 7)] | |
9118 | "TARGET_ELF && flag_pic == 2" | |
9119 | "bl %1\\n%1:" | |
9120 | [(set_attr "type" "branch") | |
9121 | (set_attr "length" "4")]) | |
9122 | ||
9123 | (define_insn "load_toc_v4_PIC_1b" | |
9124 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9125 | (match_operand:SI 1 "immediate_operand" "s")) | |
9126 | (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)] | |
9127 | "TARGET_ELF && flag_pic == 2" | |
9128 | "bl %1\\n\\t.long %2-%1+4\\n%1:" | |
9129 | [(set_attr "type" "branch") | |
9130 | (set_attr "length" "8")]) | |
9131 | ||
9132 | (define_insn "load_toc_v4_PIC_2" | |
9133 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9134 | (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") | |
9135 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") | |
9136 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
9137 | "TARGET_ELF && flag_pic == 2" | |
9138 | "{l|lwz} %0,%2-%3(%1)" | |
9139 | [(set_attr "type" "load")]) | |
9140 | ||
ee890fe2 SS |
9141 | (define_insn "load_macho_picbase" |
9142 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9143 | (unspec:SI [(const_int 0)] 15))] | |
9144 | "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" | |
9145 | "* | |
9146 | { | |
9147 | #if TARGET_MACHO | |
9148 | char *picbase = machopic_function_base_name (); | |
9149 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1)); | |
9150 | #endif | |
9151 | return \"bcl 20,31,%1\\n%1:\"; | |
9152 | }" | |
9153 | [(set_attr "type" "branch") | |
9154 | (set_attr "length" "4")]) | |
9155 | ||
9ebbca7d GK |
9156 | ;; If the TOC is shared over a translation unit, as happens with all |
9157 | ;; the kinds of PIC that we support, we need to restore the TOC | |
9158 | ;; pointer only when jumping over units of translation. | |
9159 | ||
9160 | (define_expand "builtin_setjmp_receiver" | |
9161 | [(use (label_ref (match_operand 0 "" "")))] | |
9162 | "((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1) | |
9163 | || (TARGET_TOC && TARGET_MINIMAL_TOC)" | |
9164 | " | |
9165 | { | |
9166 | rs6000_emit_load_toc_table (FALSE); | |
9167 | DONE; | |
9168 | }") | |
9169 | \f | |
9170 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
9171 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
9172 | ;; pointer to its TOC, and whose third word contains a value to place in the |
9173 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 9174 | ;; "trampoline" need not have any executable code. |
b6c9286a | 9175 | |
cccf3bdc DE |
9176 | (define_expand "call_indirect_aix32" |
9177 | [(set (match_dup 2) | |
9178 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
9179 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9180 | (reg:SI 2)) | |
9181 | (set (reg:SI 2) | |
9182 | (mem:SI (plus:SI (match_dup 0) | |
9183 | (const_int 4)))) | |
9184 | (set (reg:SI 11) | |
9185 | (mem:SI (plus:SI (match_dup 0) | |
9186 | (const_int 8)))) | |
9187 | (parallel [(call (mem:SI (match_dup 2)) | |
9188 | (match_operand 1 "" "")) | |
9189 | (use (reg:SI 2)) | |
9190 | (use (reg:SI 11)) | |
9191 | (set (reg:SI 2) | |
9192 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9193 | (clobber (scratch:SI))])] | |
9194 | "TARGET_32BIT" | |
9195 | " | |
9196 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9197 | |
cccf3bdc DE |
9198 | (define_expand "call_indirect_aix64" |
9199 | [(set (match_dup 2) | |
9200 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
9201 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9202 | (reg:DI 2)) | |
9203 | (set (reg:DI 2) | |
9204 | (mem:DI (plus:DI (match_dup 0) | |
9205 | (const_int 8)))) | |
9206 | (set (reg:DI 11) | |
9207 | (mem:DI (plus:DI (match_dup 0) | |
9208 | (const_int 16)))) | |
9209 | (parallel [(call (mem:SI (match_dup 2)) | |
9210 | (match_operand 1 "" "")) | |
9211 | (use (reg:DI 2)) | |
9212 | (use (reg:DI 11)) | |
9213 | (set (reg:DI 2) | |
9214 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9215 | (clobber (scratch:SI))])] | |
9216 | "TARGET_64BIT" | |
9217 | " | |
9218 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 9219 | |
cccf3bdc DE |
9220 | (define_expand "call_value_indirect_aix32" |
9221 | [(set (match_dup 3) | |
9222 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
9223 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9224 | (reg:SI 2)) | |
9225 | (set (reg:SI 2) | |
9226 | (mem:SI (plus:SI (match_dup 1) | |
9227 | (const_int 4)))) | |
9228 | (set (reg:SI 11) | |
9229 | (mem:SI (plus:SI (match_dup 1) | |
9230 | (const_int 8)))) | |
9231 | (parallel [(set (match_operand 0 "" "") | |
9232 | (call (mem:SI (match_dup 3)) | |
9233 | (match_operand 2 "" ""))) | |
9234 | (use (reg:SI 2)) | |
9235 | (use (reg:SI 11)) | |
9236 | (set (reg:SI 2) | |
9237 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9238 | (clobber (scratch:SI))])] | |
9239 | "TARGET_32BIT" | |
9240 | " | |
9241 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9242 | |
cccf3bdc DE |
9243 | (define_expand "call_value_indirect_aix64" |
9244 | [(set (match_dup 3) | |
9245 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
9246 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9247 | (reg:DI 2)) | |
9248 | (set (reg:DI 2) | |
9249 | (mem:DI (plus:DI (match_dup 1) | |
9250 | (const_int 8)))) | |
9251 | (set (reg:DI 11) | |
9252 | (mem:DI (plus:DI (match_dup 1) | |
9253 | (const_int 16)))) | |
9254 | (parallel [(set (match_operand 0 "" "") | |
9255 | (call (mem:SI (match_dup 3)) | |
9256 | (match_operand 2 "" ""))) | |
9257 | (use (reg:DI 2)) | |
9258 | (use (reg:DI 11)) | |
9259 | (set (reg:DI 2) | |
9260 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9261 | (clobber (scratch:SI))])] | |
9262 | "TARGET_64BIT" | |
9263 | " | |
9264 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 9265 | |
b6c9286a | 9266 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 9267 | (define_expand "call" |
a260abc9 | 9268 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 9269 | (match_operand 1 "" "")) |
4697a36c | 9270 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
9271 | (clobber (scratch:SI))])] |
9272 | "" | |
9273 | " | |
9274 | { | |
ee890fe2 SS |
9275 | #if TARGET_MACHO |
9276 | if (flag_pic) | |
9277 | operands[0] = machopic_indirect_call_target (operands[0]); | |
9278 | #endif | |
9279 | ||
1fd4e8c1 RK |
9280 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) |
9281 | abort (); | |
9282 | ||
9283 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 9284 | |
6a4cee5f MM |
9285 | if (GET_CODE (operands[0]) != SYMBOL_REF |
9286 | || (INTVAL (operands[2]) & CALL_LONG) != 0) | |
1fd4e8c1 | 9287 | { |
6a4cee5f MM |
9288 | if (INTVAL (operands[2]) & CALL_LONG) |
9289 | operands[0] = rs6000_longcall_ref (operands[0]); | |
9290 | ||
cccf3bdc DE |
9291 | if (DEFAULT_ABI == ABI_V4 |
9292 | || DEFAULT_ABI == ABI_AIX_NODESC | |
ee890fe2 | 9293 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc DE |
9294 | || DEFAULT_ABI == ABI_SOLARIS) |
9295 | operands[0] = force_reg (Pmode, operands[0]); | |
1fd4e8c1 | 9296 | |
cccf3bdc DE |
9297 | else if (DEFAULT_ABI == ABI_AIX) |
9298 | { | |
9299 | /* AIX function pointers are really pointers to a three word | |
9300 | area. */ | |
9301 | emit_call_insn (TARGET_32BIT | |
9302 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
9303 | operands[0]), | |
9304 | operands[1]) | |
9305 | : gen_call_indirect_aix64 (force_reg (DImode, | |
9306 | operands[0]), | |
9307 | operands[1])); | |
9308 | DONE; | |
b6c9286a | 9309 | } |
cccf3bdc DE |
9310 | else |
9311 | abort (); | |
1fd4e8c1 RK |
9312 | } |
9313 | }") | |
9314 | ||
9315 | (define_expand "call_value" | |
9316 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 9317 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 9318 | (match_operand 2 "" ""))) |
4697a36c | 9319 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
9320 | (clobber (scratch:SI))])] |
9321 | "" | |
9322 | " | |
9323 | { | |
ee890fe2 SS |
9324 | #if TARGET_MACHO |
9325 | if (flag_pic) | |
9326 | operands[1] = machopic_indirect_call_target (operands[1]); | |
9327 | #endif | |
9328 | ||
1fd4e8c1 RK |
9329 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) |
9330 | abort (); | |
9331 | ||
9332 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 9333 | |
6a4cee5f MM |
9334 | if (GET_CODE (operands[1]) != SYMBOL_REF |
9335 | || (INTVAL (operands[3]) & CALL_LONG) != 0) | |
1fd4e8c1 | 9336 | { |
6756293c | 9337 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
9338 | operands[1] = rs6000_longcall_ref (operands[1]); |
9339 | ||
cccf3bdc DE |
9340 | if (DEFAULT_ABI == ABI_V4 |
9341 | || DEFAULT_ABI == ABI_AIX_NODESC | |
ee890fe2 | 9342 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc DE |
9343 | || DEFAULT_ABI == ABI_SOLARIS) |
9344 | operands[0] = force_reg (Pmode, operands[0]); | |
1fd4e8c1 | 9345 | |
cccf3bdc DE |
9346 | else if (DEFAULT_ABI == ABI_AIX) |
9347 | { | |
9348 | /* AIX function pointers are really pointers to a three word | |
9349 | area. */ | |
9350 | emit_call_insn (TARGET_32BIT | |
9351 | ? gen_call_value_indirect_aix32 (operands[0], | |
9352 | force_reg (SImode, | |
9353 | operands[1]), | |
9354 | operands[2]) | |
9355 | : gen_call_value_indirect_aix64 (operands[0], | |
9356 | force_reg (DImode, | |
9357 | operands[1]), | |
9358 | operands[2])); | |
9359 | DONE; | |
b6c9286a | 9360 | } |
cccf3bdc DE |
9361 | else |
9362 | abort (); | |
1fd4e8c1 RK |
9363 | } |
9364 | }") | |
9365 | ||
04780ee7 | 9366 | ;; Call to function in current module. No TOC pointer reload needed. |
4697a36c MM |
9367 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
9368 | ;; either the function was not prototyped, or it was prototyped as a | |
9369 | ;; variable argument function. It is > 0 if FP registers were passed | |
9370 | ;; and < 0 if they were not. | |
04780ee7 | 9371 | |
a260abc9 | 9372 | (define_insn "*call_local32" |
4697a36c MM |
9373 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
9374 | (match_operand 1 "" "g,g")) | |
9375 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9376 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 9377 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
9378 | "* |
9379 | { | |
6a4cee5f MM |
9380 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
9381 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9382 | ||
9383 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9384 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 9385 | |
a226df46 | 9386 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 9387 | }" |
b7ff3d82 DE |
9388 | [(set_attr "type" "branch") |
9389 | (set_attr "length" "4,8")]) | |
04780ee7 | 9390 | |
a260abc9 DE |
9391 | (define_insn "*call_local64" |
9392 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
9393 | (match_operand 1 "" "g,g")) | |
9394 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9395 | (clobber (match_scratch:SI 3 "=l,l"))] | |
9396 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
9397 | "* | |
9398 | { | |
9399 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
9400 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9401 | ||
9402 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9403 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9404 | ||
9405 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
9406 | }" | |
9407 | [(set_attr "type" "branch") | |
9408 | (set_attr "length" "4,8")]) | |
9409 | ||
cccf3bdc | 9410 | (define_insn "*call_value_local32" |
a260abc9 DE |
9411 | [(set (match_operand 0 "" "=fg,fg") |
9412 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
9413 | (match_operand 2 "" "g,g"))) | |
9414 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9415 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9416 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
9417 | "* | |
9418 | { | |
9419 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9420 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9421 | ||
9422 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9423 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9424 | ||
9425 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9426 | }" | |
9427 | [(set_attr "type" "branch") | |
9428 | (set_attr "length" "4,8")]) | |
9429 | ||
9430 | ||
cccf3bdc | 9431 | (define_insn "*call_value_local64" |
a260abc9 DE |
9432 | [(set (match_operand 0 "" "=fg,fg") |
9433 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
9434 | (match_operand 2 "" "g,g"))) | |
9435 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9436 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9437 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
9438 | "* | |
9439 | { | |
9440 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9441 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9442 | ||
9443 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9444 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9445 | ||
9446 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9447 | }" | |
9448 | [(set_attr "type" "branch") | |
9449 | (set_attr "length" "4,8")]) | |
9450 | ||
04780ee7 | 9451 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 9452 | ;; pointer (r2) after the call unless this is System V. |
4697a36c MM |
9453 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
9454 | ;; either the function was not prototyped, or it was prototyped as a | |
9455 | ;; variable argument function. It is > 0 if FP registers were passed | |
9456 | ;; and < 0 if they were not. | |
04780ee7 | 9457 | |
cccf3bdc DE |
9458 | (define_insn "*call_indirect_nonlocal_aix32" |
9459 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) | |
9460 | (match_operand 1 "" "g")) | |
9461 | (use (reg:SI 2)) | |
9462 | (use (reg:SI 11)) | |
9463 | (set (reg:SI 2) | |
9464 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
c77e04ae | 9465 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
9466 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
9467 | "b%T0l\;{l|lwz} 2,20(1)" | |
9468 | [(set_attr "type" "jmpreg") | |
9469 | (set_attr "length" "8")]) | |
9470 | ||
a260abc9 | 9471 | (define_insn "*call_nonlocal_aix32" |
cccf3bdc DE |
9472 | [(call (mem:SI (match_operand:SI 0 "call_operand" "s")) |
9473 | (match_operand 1 "" "g")) | |
9474 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
9475 | (clobber (match_scratch:SI 3 "=l"))] | |
9476 | "TARGET_32BIT | |
9477 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 9478 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 9479 | "bl %z0\;%." |
b7ff3d82 | 9480 | [(set_attr "type" "branch") |
cccf3bdc DE |
9481 | (set_attr "length" "8")]) |
9482 | ||
9483 | (define_insn "*call_indirect_nonlocal_aix64" | |
9484 | [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) | |
9485 | (match_operand 1 "" "g")) | |
9486 | (use (reg:DI 2)) | |
9487 | (use (reg:DI 11)) | |
9488 | (set (reg:DI 2) | |
9489 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
c77e04ae | 9490 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
9491 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
9492 | "b%T0l\;ld 2,40(1)" | |
9493 | [(set_attr "type" "jmpreg") | |
9494 | (set_attr "length" "8")]) | |
59313e4e | 9495 | |
a260abc9 | 9496 | (define_insn "*call_nonlocal_aix64" |
cccf3bdc DE |
9497 | [(call (mem:SI (match_operand:DI 0 "call_operand" "s")) |
9498 | (match_operand 1 "" "g")) | |
9499 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
9500 | (clobber (match_scratch:SI 3 "=l"))] | |
9ebbca7d GK |
9501 | "TARGET_64BIT |
9502 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 9503 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 9504 | "bl %z0\;%." |
a260abc9 | 9505 | [(set_attr "type" "branch") |
cccf3bdc | 9506 | (set_attr "length" "8")]) |
7509c759 | 9507 | |
cccf3bdc DE |
9508 | (define_insn "*call_value_indirect_nonlocal_aix32" |
9509 | [(set (match_operand 0 "" "=fg") | |
9510 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) | |
9511 | (match_operand 2 "" "g"))) | |
9512 | (use (reg:SI 2)) | |
9513 | (use (reg:SI 11)) | |
9514 | (set (reg:SI 2) | |
9515 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9516 | (clobber (match_scratch:SI 3 "=l"))] | |
9517 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" | |
9518 | "b%T1l\;{l|lwz} 2,20(1)" | |
9519 | [(set_attr "type" "jmpreg") | |
9520 | (set_attr "length" "8")]) | |
1fd4e8c1 | 9521 | |
cccf3bdc DE |
9522 | (define_insn "*call_value_nonlocal_aix32" |
9523 | [(set (match_operand 0 "" "=fg") | |
9524 | (call (mem:SI (match_operand:SI 1 "call_operand" "s")) | |
9525 | (match_operand 2 "" "g"))) | |
9526 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
9527 | (clobber (match_scratch:SI 4 "=l"))] | |
9528 | "TARGET_32BIT | |
9529 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 9530 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 9531 | "bl %z1\;%." |
b7ff3d82 | 9532 | [(set_attr "type" "branch") |
cccf3bdc | 9533 | (set_attr "length" "8")]) |
04780ee7 | 9534 | |
cccf3bdc DE |
9535 | (define_insn "*call_value_indirect_nonlocal_aix64" |
9536 | [(set (match_operand 0 "" "=fg") | |
9537 | (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) | |
9538 | (match_operand 2 "" "g"))) | |
9539 | (use (reg:DI 2)) | |
9540 | (use (reg:DI 11)) | |
9541 | (set (reg:DI 2) | |
9542 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9543 | (clobber (match_scratch:SI 3 "=l"))] | |
9544 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" | |
9545 | "b%T1l\;ld 2,40(1)" | |
9546 | [(set_attr "type" "jmpreg") | |
9547 | (set_attr "length" "8")]) | |
9548 | ||
9549 | (define_insn "*call_value_nonlocal_aix64" | |
9550 | [(set (match_operand 0 "" "=fg") | |
9551 | (call (mem:SI (match_operand:DI 1 "call_operand" "s")) | |
9552 | (match_operand 2 "" "g"))) | |
9553 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
9554 | (clobber (match_scratch:SI 4 "=l"))] | |
9ebbca7d GK |
9555 | "TARGET_64BIT |
9556 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 9557 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
9558 | "bl %z1\;%." |
9559 | [(set_attr "type" "branch") | |
9560 | (set_attr "length" "8")]) | |
9561 | ||
9562 | ;; A function pointer under System V is just a normal pointer | |
9563 | ;; operands[0] is the function pointer | |
9564 | ;; operands[1] is the stack size to clean up | |
9565 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
9566 | ;; which indicates how to set cr1 | |
9567 | ||
9568 | (define_insn "*call_nonlocal_sysv" | |
9569 | [(call (mem:SI (match_operand:SI 0 "call_operand" "cl,cl,s,s")) | |
9570 | (match_operand 1 "" "g,g,g,g")) | |
9571 | (use (match_operand:SI 2 "immediate_operand" "O,n,O,n")) | |
9572 | (clobber (match_scratch:SI 3 "=l,l,l,l"))] | |
9573 | "DEFAULT_ABI == ABI_AIX_NODESC | |
9574 | || DEFAULT_ABI == ABI_V4 | |
ee890fe2 | 9575 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc | 9576 | || DEFAULT_ABI == ABI_SOLARIS" |
911f679c MM |
9577 | "* |
9578 | { | |
cccf3bdc | 9579 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
6a4cee5f MM |
9580 | output_asm_insn (\"crxor 6,6,6\", operands); |
9581 | ||
cccf3bdc | 9582 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
6a4cee5f | 9583 | output_asm_insn (\"creqv 6,6,6\", operands); |
7509c759 | 9584 | |
cccf3bdc DE |
9585 | switch (which_alternative) |
9586 | { | |
9587 | default: | |
9588 | abort (); | |
9589 | case 0: | |
9590 | case 1: | |
9591 | return \"b%T0l\"; | |
9592 | case 2: | |
9593 | case 3: | |
9594 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\"; | |
9595 | } | |
b6c9286a | 9596 | }" |
cccf3bdc DE |
9597 | [(set_attr "type" "jmpreg,jmpreg,branch,branch") |
9598 | (set_attr "length" "4,8,4,8")]) | |
9599 | ||
9600 | (define_insn "*call_value_nonlocal_sysv" | |
9601 | [(set (match_operand 0 "" "=fg,fg,fg,fg") | |
9602 | (call (mem:SI (match_operand:SI 1 "call_operand" "cl,cl,s,s")) | |
9603 | (match_operand 2 "" "g,g,g,g"))) | |
9604 | (use (match_operand:SI 3 "immediate_operand" "O,n,O,n")) | |
9605 | (clobber (match_scratch:SI 4 "=l,l,l,l"))] | |
9606 | "DEFAULT_ABI == ABI_AIX_NODESC | |
9607 | || DEFAULT_ABI == ABI_V4 | |
ee890fe2 | 9608 | || DEFAULT_ABI == ABI_DARWIN |
cccf3bdc | 9609 | || DEFAULT_ABI == ABI_SOLARIS" |
b6c9286a MM |
9610 | "* |
9611 | { | |
6a4cee5f MM |
9612 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
9613 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9614 | ||
9615 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9616 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 9617 | |
cccf3bdc DE |
9618 | switch (which_alternative) |
9619 | { | |
9620 | default: | |
9621 | abort (); | |
9622 | case 0: | |
9623 | case 1: | |
9624 | return \"b%T1l\"; | |
9625 | case 2: | |
9626 | case 3: | |
9627 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\"; | |
9628 | } | |
911f679c | 9629 | }" |
cccf3bdc DE |
9630 | [(set_attr "type" "jmpreg,jmpreg,branch,branch") |
9631 | (set_attr "length" "4,8,4,8")]) | |
e6f948e3 RK |
9632 | |
9633 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
9634 | (define_expand "untyped_call" |
9635 | [(parallel [(call (match_operand 0 "" "") | |
9636 | (const_int 0)) | |
9637 | (match_operand 1 "" "") | |
9638 | (match_operand 2 "" "")])] | |
9639 | "" | |
9640 | " | |
9641 | { | |
9642 | int i; | |
9643 | ||
7d70b8b2 | 9644 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
9645 | |
9646 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
9647 | { | |
9648 | rtx set = XVECEXP (operands[2], 0, i); | |
9649 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
9650 | } | |
9651 | ||
9652 | /* The optimizer does not know that the call sets the function value | |
9653 | registers we stored in the result block. We avoid problems by | |
9654 | claiming that all hard registers are used and clobbered at this | |
9655 | point. */ | |
9656 | emit_insn (gen_blockage ()); | |
9657 | ||
9658 | DONE; | |
9659 | }") | |
9660 | ||
9661 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
9662 | ;; all of memory. This blocks insns from being moved across this point. | |
9663 | ||
9664 | (define_insn "blockage" | |
9665 | [(unspec_volatile [(const_int 0)] 0)] | |
9666 | "" | |
9667 | "") | |
1fd4e8c1 RK |
9668 | \f |
9669 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 9670 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
9671 | ;; |
9672 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
9673 | ;; insns, and branches. We store the operands of compares until we see | |
9674 | ;; how it is used. | |
9675 | (define_expand "cmpsi" | |
9676 | [(set (cc0) | |
cd2b37d9 | 9677 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
9678 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
9679 | "" | |
9680 | " | |
9681 | { | |
9682 | /* Take care of the possibility that operands[1] might be negative but | |
9683 | this might be a logical operation. That insn doesn't exist. */ | |
9684 | if (GET_CODE (operands[1]) == CONST_INT | |
9685 | && INTVAL (operands[1]) < 0) | |
9686 | operands[1] = force_reg (SImode, operands[1]); | |
9687 | ||
9688 | rs6000_compare_op0 = operands[0]; | |
9689 | rs6000_compare_op1 = operands[1]; | |
9690 | rs6000_compare_fp_p = 0; | |
9691 | DONE; | |
9692 | }") | |
9693 | ||
266eb58a DE |
9694 | (define_expand "cmpdi" |
9695 | [(set (cc0) | |
9696 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
9697 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
9698 | "TARGET_POWERPC64" | |
9699 | " | |
9700 | { | |
9701 | /* Take care of the possibility that operands[1] might be negative but | |
9702 | this might be a logical operation. That insn doesn't exist. */ | |
9703 | if (GET_CODE (operands[1]) == CONST_INT | |
9704 | && INTVAL (operands[1]) < 0) | |
9705 | operands[1] = force_reg (DImode, operands[1]); | |
9706 | ||
9707 | rs6000_compare_op0 = operands[0]; | |
9708 | rs6000_compare_op1 = operands[1]; | |
9709 | rs6000_compare_fp_p = 0; | |
9710 | DONE; | |
9711 | }") | |
9712 | ||
1fd4e8c1 | 9713 | (define_expand "cmpsf" |
cd2b37d9 RK |
9714 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
9715 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 9716 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
9717 | " |
9718 | { | |
9719 | rs6000_compare_op0 = operands[0]; | |
9720 | rs6000_compare_op1 = operands[1]; | |
9721 | rs6000_compare_fp_p = 1; | |
9722 | DONE; | |
9723 | }") | |
9724 | ||
9725 | (define_expand "cmpdf" | |
cd2b37d9 RK |
9726 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
9727 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 9728 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
9729 | " |
9730 | { | |
9731 | rs6000_compare_op0 = operands[0]; | |
9732 | rs6000_compare_op1 = operands[1]; | |
9733 | rs6000_compare_fp_p = 1; | |
9734 | DONE; | |
9735 | }") | |
9736 | ||
9737 | (define_expand "beq" | |
39a10a29 | 9738 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9739 | "" |
39a10a29 | 9740 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
9741 | |
9742 | (define_expand "bne" | |
39a10a29 | 9743 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9744 | "" |
39a10a29 | 9745 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 9746 | |
39a10a29 GK |
9747 | (define_expand "bge" |
9748 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9749 | "" |
39a10a29 | 9750 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
9751 | |
9752 | (define_expand "bgt" | |
39a10a29 | 9753 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9754 | "" |
39a10a29 | 9755 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
9756 | |
9757 | (define_expand "ble" | |
39a10a29 | 9758 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 9759 | "" |
39a10a29 | 9760 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 9761 | |
39a10a29 GK |
9762 | (define_expand "blt" |
9763 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9764 | "" |
39a10a29 | 9765 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 9766 | |
39a10a29 GK |
9767 | (define_expand "bgeu" |
9768 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9769 | "" |
39a10a29 | 9770 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 9771 | |
39a10a29 GK |
9772 | (define_expand "bgtu" |
9773 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9774 | "" |
39a10a29 | 9775 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 9776 | |
39a10a29 GK |
9777 | (define_expand "bleu" |
9778 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9779 | "" |
39a10a29 | 9780 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 9781 | |
39a10a29 GK |
9782 | (define_expand "bltu" |
9783 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 9784 | "" |
39a10a29 | 9785 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 9786 | |
1c882ea4 | 9787 | (define_expand "bunordered" |
39a10a29 | 9788 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9789 | "" |
39a10a29 | 9790 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
9791 | |
9792 | (define_expand "bordered" | |
39a10a29 | 9793 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9794 | "" |
39a10a29 | 9795 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
9796 | |
9797 | (define_expand "buneq" | |
39a10a29 | 9798 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9799 | "" |
39a10a29 | 9800 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
9801 | |
9802 | (define_expand "bunge" | |
39a10a29 | 9803 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9804 | "" |
39a10a29 | 9805 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
9806 | |
9807 | (define_expand "bungt" | |
39a10a29 | 9808 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9809 | "" |
39a10a29 | 9810 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
9811 | |
9812 | (define_expand "bunle" | |
39a10a29 | 9813 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9814 | "" |
39a10a29 | 9815 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
9816 | |
9817 | (define_expand "bunlt" | |
39a10a29 | 9818 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9819 | "" |
39a10a29 | 9820 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
9821 | |
9822 | (define_expand "bltgt" | |
39a10a29 | 9823 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 9824 | "" |
39a10a29 | 9825 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 9826 | |
1fd4e8c1 RK |
9827 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
9828 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
9829 | ;; with an scc insns. However, due to the order that combine see the | |
9830 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
9831 | ;; the cases we don't want to handle. | |
9832 | (define_expand "seq" | |
39a10a29 | 9833 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9834 | "" |
39a10a29 | 9835 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
9836 | |
9837 | (define_expand "sne" | |
39a10a29 | 9838 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
9839 | "" |
9840 | " | |
39a10a29 GK |
9841 | { |
9842 | if (! rs6000_compare_fp_p) | |
1fd4e8c1 RK |
9843 | FAIL; |
9844 | ||
39a10a29 GK |
9845 | rs6000_emit_sCOND (NE, operands[0]); |
9846 | DONE; | |
1fd4e8c1 RK |
9847 | }") |
9848 | ||
9849 | ;; A > 0 is best done using the portable sequence, so fail in that case. | |
9850 | (define_expand "sgt" | |
39a10a29 | 9851 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
9852 | "" |
9853 | " | |
5638268e DE |
9854 | { |
9855 | if (! rs6000_compare_fp_p | |
9856 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
9857 | FAIL; |
9858 | ||
39a10a29 GK |
9859 | rs6000_emit_sCOND (GT, operands[0]); |
9860 | DONE; | |
1fd4e8c1 RK |
9861 | }") |
9862 | ||
9863 | ;; A < 0 is best done in the portable way for A an integer. | |
9864 | (define_expand "slt" | |
39a10a29 | 9865 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
9866 | "" |
9867 | " | |
5638268e DE |
9868 | { |
9869 | if (! rs6000_compare_fp_p | |
9870 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
9871 | FAIL; |
9872 | ||
39a10a29 GK |
9873 | rs6000_emit_sCOND (LT, operands[0]); |
9874 | DONE; | |
1fd4e8c1 RK |
9875 | }") |
9876 | ||
5638268e | 9877 | ;; A >= 0 is best done the portable way for A an integer. |
1fd4e8c1 | 9878 | (define_expand "sge" |
39a10a29 | 9879 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9880 | "" |
5638268e DE |
9881 | " |
9882 | { | |
9883 | if (! rs6000_compare_fp_p | |
9884 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
9885 | FAIL; | |
9886 | ||
9887 | rs6000_emit_sCOND (GE, operands[0]); | |
9888 | DONE; | |
9889 | }") | |
1fd4e8c1 RK |
9890 | |
9891 | ;; A <= 0 is best done the portable way for A an integer. | |
9892 | (define_expand "sle" | |
39a10a29 | 9893 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
9894 | "" |
9895 | " | |
5638268e DE |
9896 | { |
9897 | if (! rs6000_compare_fp_p | |
9898 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
9899 | FAIL; |
9900 | ||
39a10a29 GK |
9901 | rs6000_emit_sCOND (LE, operands[0]); |
9902 | DONE; | |
1fd4e8c1 RK |
9903 | }") |
9904 | ||
9905 | (define_expand "sgtu" | |
39a10a29 | 9906 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9907 | "" |
39a10a29 | 9908 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
9909 | |
9910 | (define_expand "sltu" | |
39a10a29 | 9911 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9912 | "" |
39a10a29 | 9913 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 RK |
9914 | |
9915 | (define_expand "sgeu" | |
39a10a29 | 9916 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9917 | "" |
39a10a29 | 9918 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
9919 | |
9920 | (define_expand "sleu" | |
39a10a29 | 9921 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 9922 | "" |
39a10a29 | 9923 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") |
1fd4e8c1 RK |
9924 | \f |
9925 | ;; Here are the actual compare insns. | |
acad7ed3 | 9926 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 9927 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 9928 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
9929 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
9930 | "" | |
7f340546 | 9931 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
1fd4e8c1 RK |
9932 | [(set_attr "type" "compare")]) |
9933 | ||
acad7ed3 | 9934 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
9935 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
9936 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
9937 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
9938 | "TARGET_POWERPC64" | |
9939 | "cmpd%I2 %0,%1,%2" | |
9940 | [(set_attr "type" "compare")]) | |
9941 | ||
f357808b RK |
9942 | ;; If we are comparing a register for equality with a large constant, |
9943 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
9944 | ;; register for the result of the XOR. | |
9945 | ||
9946 | (define_split | |
9947 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 9948 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 9949 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 9950 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
9951 | "find_single_use (operands[0], insn, 0) |
9952 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
9953 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
9954 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
9955 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
9956 | " | |
9957 | { | |
9958 | /* Get the constant we are comparing against, C, and see what it looks like | |
9959 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
9960 | with C to get the sign-extended value. */ | |
9961 | ||
5f59ecb7 DE |
9962 | HOST_WIDE_INT c = INTVAL (operands[2]); |
9963 | HOST_WIDE_INT sextc = (c & 0x7fff) - (c & 0x8000); | |
9964 | HOST_WIDE_INT xorv = c ^ sextc; | |
f357808b | 9965 | |
89e9f3a8 MM |
9966 | operands[4] = GEN_INT (xorv); |
9967 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
9968 | }") |
9969 | ||
acad7ed3 | 9970 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 9971 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 9972 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 9973 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 9974 | "" |
e2c953b6 | 9975 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
1fd4e8c1 RK |
9976 | [(set_attr "type" "compare")]) |
9977 | ||
acad7ed3 | 9978 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
9979 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
9980 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 9981 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 9982 | "" |
e2c953b6 | 9983 | "cmpld%I2 %0,%1,%b2" |
266eb58a DE |
9984 | [(set_attr "type" "compare")]) |
9985 | ||
1fd4e8c1 RK |
9986 | ;; The following two insns don't exist as single insns, but if we provide |
9987 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
9988 | ;; of the required delay between a compare and branch. We generate code for | |
9989 | ;; them by splitting. | |
9990 | ||
9991 | (define_insn "" | |
9992 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 9993 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 9994 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 9995 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9996 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
9997 | "" | |
baf97f86 RK |
9998 | "#" |
9999 | [(set_attr "length" "8")]) | |
7e69e155 | 10000 | |
1fd4e8c1 RK |
10001 | (define_insn "" |
10002 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 10003 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10004 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 10005 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10006 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
10007 | "" | |
baf97f86 RK |
10008 | "#" |
10009 | [(set_attr "length" "8")]) | |
7e69e155 | 10010 | |
1fd4e8c1 RK |
10011 | (define_split |
10012 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 10013 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10014 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 10015 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10016 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10017 | "" | |
10018 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
10019 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10020 | ||
10021 | (define_split | |
10022 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 10023 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10024 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 10025 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10026 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10027 | "" | |
10028 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
10029 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10030 | ||
acad7ed3 | 10031 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 10032 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10033 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
10034 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 10035 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10036 | "fcmpu %0,%1,%2" |
10037 | [(set_attr "type" "fpcompare")]) | |
10038 | ||
acad7ed3 | 10039 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 10040 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10041 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
10042 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 10043 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10044 | "fcmpu %0,%1,%2" |
10045 | [(set_attr "type" "fpcompare")]) | |
10046 | \f | |
10047 | ;; Now we have the scc insns. We can do some combinations because of the | |
10048 | ;; way the machine works. | |
10049 | ;; | |
10050 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
10051 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
10052 | ;; cases the insns below which don't use an intermediate CR field will | |
10053 | ;; be used instead. | |
1fd4e8c1 | 10054 | (define_insn "" |
cd2b37d9 | 10055 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10056 | (match_operator:SI 1 "scc_comparison_operator" |
10057 | [(match_operand 2 "cc_reg_operand" "y") | |
10058 | (const_int 0)]))] | |
10059 | "" | |
ca7f5001 | 10060 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" |
b19003d8 | 10061 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10062 | |
10063 | (define_insn "" | |
9ebbca7d GK |
10064 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
10065 | (match_operator:DI 1 "scc_comparison_operator" | |
10066 | [(match_operand 2 "cc_reg_operand" "y") | |
10067 | (const_int 0)]))] | |
10068 | "TARGET_POWERPC64" | |
10069 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" | |
10070 | [(set_attr "length" "12")]) | |
10071 | ||
10072 | (define_insn "" | |
10073 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 10074 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 10075 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
10076 | (const_int 0)]) |
10077 | (const_int 0))) | |
9ebbca7d | 10078 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10079 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
0ad91047 | 10080 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10081 | "@ |
10082 | %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1 | |
10083 | #" | |
b19003d8 | 10084 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
10085 | (set_attr "length" "12,16")]) |
10086 | ||
10087 | (define_split | |
10088 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10089 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
10090 | [(match_operand 2 "cc_reg_operand" "") | |
10091 | (const_int 0)]) | |
10092 | (const_int 0))) | |
10093 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
10094 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
10095 | "! TARGET_POWERPC64 && reload_completed" | |
10096 | [(set (match_dup 3) | |
10097 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
10098 | (set (match_dup 0) | |
10099 | (compare:CC (match_dup 3) | |
10100 | (const_int 0)))] | |
10101 | "") | |
1fd4e8c1 RK |
10102 | |
10103 | (define_insn "" | |
cd2b37d9 | 10104 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10105 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
10106 | [(match_operand 2 "cc_reg_operand" "y") | |
10107 | (const_int 0)]) | |
10108 | (match_operand:SI 3 "const_int_operand" "n")))] | |
10109 | "" | |
10110 | "* | |
10111 | { | |
10112 | int is_bit = ccr_bit (operands[1], 1); | |
10113 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
10114 | int count; | |
10115 | ||
10116 | if (is_bit >= put_bit) | |
10117 | count = is_bit - put_bit; | |
10118 | else | |
10119 | count = 32 - (put_bit - is_bit); | |
10120 | ||
89e9f3a8 MM |
10121 | operands[4] = GEN_INT (count); |
10122 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 10123 | |
ca7f5001 | 10124 | return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 RK |
10125 | }" |
10126 | [(set_attr "length" "12")]) | |
1fd4e8c1 RK |
10127 | |
10128 | (define_insn "" | |
9ebbca7d | 10129 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10130 | (compare:CC |
10131 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 10132 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 10133 | (const_int 0)]) |
9ebbca7d | 10134 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 10135 | (const_int 0))) |
9ebbca7d | 10136 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
10137 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
10138 | (match_dup 3)))] | |
9ebbca7d | 10139 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
10140 | "* |
10141 | { | |
10142 | int is_bit = ccr_bit (operands[1], 1); | |
10143 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
10144 | int count; | |
10145 | ||
9ebbca7d GK |
10146 | /* Force split for non-cc0 compare. */ |
10147 | if (which_alternative == 1) | |
10148 | return \"#\"; | |
10149 | ||
1fd4e8c1 RK |
10150 | if (is_bit >= put_bit) |
10151 | count = is_bit - put_bit; | |
10152 | else | |
10153 | count = 32 - (put_bit - is_bit); | |
10154 | ||
89e9f3a8 MM |
10155 | operands[5] = GEN_INT (count); |
10156 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 10157 | |
ca7f5001 | 10158 | return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 10159 | }" |
b19003d8 | 10160 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
10161 | (set_attr "length" "12,16")]) |
10162 | ||
10163 | (define_split | |
10164 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10165 | (compare:CC | |
10166 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
10167 | [(match_operand 2 "cc_reg_operand" "") | |
10168 | (const_int 0)]) | |
10169 | (match_operand:SI 3 "const_int_operand" "")) | |
10170 | (const_int 0))) | |
10171 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
10172 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
10173 | (match_dup 3)))] | |
10174 | "! TARGET_POWERPC64 && reload_completed" | |
10175 | [(set (match_dup 4) | |
10176 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
10177 | (match_dup 3))) | |
10178 | (set (match_dup 0) | |
10179 | (compare:CC (match_dup 4) | |
10180 | (const_int 0)))] | |
10181 | "") | |
1fd4e8c1 | 10182 | |
c5defebb RK |
10183 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
10184 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
10185 | ||
10186 | (define_peephole | |
cd2b37d9 | 10187 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
10188 | (match_operator:SI 1 "scc_comparison_operator" |
10189 | [(match_operand 2 "cc_reg_operand" "y") | |
10190 | (const_int 0)])) | |
cd2b37d9 | 10191 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
10192 | (match_operator:SI 4 "scc_comparison_operator" |
10193 | [(match_operand 5 "cc_reg_operand" "y") | |
10194 | (const_int 0)]))] | |
10195 | "REGNO (operands[2]) != REGNO (operands[5])" | |
ca7f5001 | 10196 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b19003d8 | 10197 | [(set_attr "length" "20")]) |
c5defebb | 10198 | |
9ebbca7d GK |
10199 | (define_peephole |
10200 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10201 | (match_operator:DI 1 "scc_comparison_operator" | |
10202 | [(match_operand 2 "cc_reg_operand" "y") | |
10203 | (const_int 0)])) | |
10204 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
10205 | (match_operator:DI 4 "scc_comparison_operator" | |
10206 | [(match_operand 5 "cc_reg_operand" "y") | |
10207 | (const_int 0)]))] | |
10208 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" | |
10209 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" | |
10210 | [(set_attr "length" "20")]) | |
10211 | ||
1fd4e8c1 RK |
10212 | ;; There are some scc insns that can be done directly, without a compare. |
10213 | ;; These are faster because they don't involve the communications between | |
10214 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
10215 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
10216 | ;; | |
10217 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
10218 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
10219 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
10220 | ;; cases where it is no more expensive than (neg (scc ..)). | |
10221 | ||
10222 | ;; Have reload force a constant into a register for the simple insns that | |
10223 | ;; otherwise won't accept constants. We do this because it is faster than | |
10224 | ;; the cmp/mfcr sequence we would otherwise generate. | |
10225 | ||
10226 | (define_insn "" | |
cd2b37d9 RK |
10227 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
10228 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 10229 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 10230 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
f9562f27 | 10231 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10232 | "@ |
ca7f5001 | 10233 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 10234 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
10235 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
10236 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
10237 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 10238 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 10239 | |
a260abc9 DE |
10240 | (define_insn "" |
10241 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
10242 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
10243 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
10244 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
10245 | "TARGET_POWERPC64" | |
10246 | "@ | |
10247 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
10248 | subfic %3,%1,0\;adde %0,%3,%1 | |
10249 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
10250 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
10251 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
10252 | [(set_attr "length" "12,8,12,12,12")]) | |
10253 | ||
1fd4e8c1 | 10254 | (define_insn "" |
9ebbca7d | 10255 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 10256 | (compare:CC |
9ebbca7d GK |
10257 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10258 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 10259 | (const_int 0))) |
9ebbca7d | 10260 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 10261 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 10262 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
f9562f27 | 10263 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10264 | "@ |
ca7f5001 RK |
10265 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
10266 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
10267 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
10268 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
10269 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
10270 | # | |
10271 | # | |
10272 | # | |
10273 | # | |
10274 | #" | |
b19003d8 | 10275 | [(set_attr "type" "compare") |
9ebbca7d GK |
10276 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
10277 | ||
10278 | (define_split | |
10279 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10280 | (compare:CC | |
10281 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10282 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
10283 | (const_int 0))) | |
10284 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10285 | (eq:SI (match_dup 1) (match_dup 2))) | |
10286 | (clobber (match_scratch:SI 3 ""))] | |
10287 | "! TARGET_POWERPC64 && reload_completed" | |
10288 | [(parallel [(set (match_dup 0) | |
10289 | (eq:SI (match_dup 1) (match_dup 2))) | |
10290 | (clobber (match_dup 3))]) | |
10291 | (set (match_dup 4) | |
10292 | (compare:CC (match_dup 0) | |
10293 | (const_int 0)))] | |
10294 | "") | |
b19003d8 | 10295 | |
a260abc9 | 10296 | (define_insn "" |
9ebbca7d | 10297 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 10298 | (compare:CC |
9ebbca7d GK |
10299 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10300 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 10301 | (const_int 0))) |
9ebbca7d | 10302 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 10303 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 10304 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
a260abc9 DE |
10305 | "TARGET_POWERPC64" |
10306 | "@ | |
10307 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
10308 | subfic %3,%1,0\;adde. %0,%3,%1 | |
10309 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
10310 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
10311 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
10312 | # | |
10313 | # | |
10314 | # | |
10315 | # | |
10316 | #" | |
a260abc9 | 10317 | [(set_attr "type" "compare") |
9ebbca7d GK |
10318 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
10319 | ||
10320 | (define_split | |
10321 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10322 | (compare:CC | |
10323 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
10324 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
10325 | (const_int 0))) | |
10326 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
10327 | (eq:DI (match_dup 1) (match_dup 2))) | |
10328 | (clobber (match_scratch:DI 3 ""))] | |
10329 | "TARGET_POWERPC64 && reload_completed" | |
10330 | [(parallel [(set (match_dup 0) | |
10331 | (eq:DI (match_dup 1) (match_dup 2))) | |
10332 | (clobber (match_dup 3))]) | |
10333 | (set (match_dup 4) | |
10334 | (compare:CC (match_dup 0) | |
10335 | (const_int 0)))] | |
10336 | "") | |
a260abc9 | 10337 | |
b19003d8 RK |
10338 | ;; We have insns of the form shown by the first define_insn below. If |
10339 | ;; there is something inside the comparison operation, we must split it. | |
10340 | (define_split | |
10341 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
10342 | (plus:SI (match_operator 1 "comparison_operator" | |
10343 | [(match_operand:SI 2 "" "") | |
10344 | (match_operand:SI 3 | |
10345 | "reg_or_cint_operand" "")]) | |
10346 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
10347 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
10348 | "! gpc_reg_operand (operands[2], SImode)" | |
10349 | [(set (match_dup 5) (match_dup 2)) | |
10350 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
10351 | (match_dup 4)))]) | |
1fd4e8c1 RK |
10352 | |
10353 | (define_insn "" | |
cd2b37d9 RK |
10354 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
10355 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 10356 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
cd2b37d9 | 10357 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) |
1fd4e8c1 | 10358 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
f9562f27 | 10359 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10360 | "@ |
ca7f5001 RK |
10361 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
10362 | {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3 | |
10363 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
10364 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
d9d934ef | 10365 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" |
b19003d8 | 10366 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
10367 | |
10368 | (define_insn "" | |
9ebbca7d | 10369 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 10370 | (compare:CC |
1fd4e8c1 | 10371 | (plus:SI |
9ebbca7d GK |
10372 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10373 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
10374 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 10375 | (const_int 0))) |
9ebbca7d | 10376 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 10377 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10378 | "@ |
ca7f5001 | 10379 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 10380 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
10381 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
10382 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
10383 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
10384 | # | |
10385 | # | |
10386 | # | |
10387 | # | |
10388 | #" | |
b19003d8 | 10389 | [(set_attr "type" "compare") |
9ebbca7d GK |
10390 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
10391 | ||
10392 | (define_split | |
10393 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10394 | (compare:CC | |
10395 | (plus:SI | |
10396 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10397 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
10398 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10399 | (const_int 0))) | |
10400 | (clobber (match_scratch:SI 4 ""))] | |
10401 | "! TARGET_POWERPC64 && reload_completed" | |
10402 | [(set (match_dup 4) | |
10403 | (plus:SI (eq:SI (match_dup 1) | |
10404 | (match_dup 2)) | |
10405 | (match_dup 3))) | |
10406 | (set (match_dup 0) | |
10407 | (compare:CC (match_dup 4) | |
10408 | (const_int 0)))] | |
10409 | "") | |
1fd4e8c1 RK |
10410 | |
10411 | (define_insn "" | |
9ebbca7d | 10412 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 10413 | (compare:CC |
1fd4e8c1 | 10414 | (plus:SI |
9ebbca7d GK |
10415 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
10416 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
10417 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 10418 | (const_int 0))) |
9ebbca7d | 10419 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 10420 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 10421 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 10422 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10423 | "@ |
ca7f5001 | 10424 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
19378cf8 | 10425 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3 |
ca7f5001 RK |
10426 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
10427 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
10428 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
10429 | # | |
10430 | # | |
10431 | # | |
10432 | # | |
10433 | #" | |
10434 | [(set_attr "type" "compare") | |
10435 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
10436 | ||
10437 | (define_split | |
10438 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
10439 | (compare:CC | |
10440 | (plus:SI | |
10441 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10442 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
10443 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10444 | (const_int 0))) | |
10445 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10446 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10447 | (clobber (match_scratch:SI 4 ""))] | |
10448 | "! TARGET_POWERPC64 && reload_completed" | |
10449 | [(parallel [(set (match_dup 0) | |
10450 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10451 | (clobber (match_dup 4))]) | |
10452 | (set (match_dup 5) | |
10453 | (compare:CC (match_dup 0) | |
10454 | (const_int 0)))] | |
10455 | "") | |
10456 | ||
1fd4e8c1 | 10457 | (define_insn "" |
cd2b37d9 | 10458 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 10459 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 10460 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
f9562f27 | 10461 | "! TARGET_POWERPC64" |
1fd4e8c1 | 10462 | "@ |
ca7f5001 RK |
10463 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
10464 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
10465 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
10466 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
10467 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 10468 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 10469 | |
ea9be077 MM |
10470 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
10471 | ;; since it nabs/sr is just as fast. | |
463b558b | 10472 | (define_insn "*ne0" |
b4e95693 | 10473 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
10474 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
10475 | (const_int 31))) | |
10476 | (clobber (match_scratch:SI 2 "=&r"))] | |
9ebbca7d | 10477 | "! TARGET_POWER && ! TARGET_POWERPC64" |
ea9be077 MM |
10478 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
10479 | [(set_attr "length" "8")]) | |
10480 | ||
a260abc9 DE |
10481 | (define_insn "" |
10482 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10483 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
10484 | (const_int 63))) | |
10485 | (clobber (match_scratch:DI 2 "=&r"))] | |
10486 | "TARGET_POWERPC64" | |
10487 | "addic %2,%1,-1\;subfe %0,%2,%1" | |
10488 | [(set_attr "length" "8")]) | |
10489 | ||
1fd4e8c1 RK |
10490 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
10491 | (define_insn "" | |
cd2b37d9 | 10492 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 10493 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 10494 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10495 | (const_int 31)) |
cd2b37d9 | 10496 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10497 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 10498 | "! TARGET_POWERPC64" |
ca7f5001 | 10499 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 10500 | [(set_attr "length" "8")]) |
1fd4e8c1 | 10501 | |
a260abc9 DE |
10502 | (define_insn "" |
10503 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10504 | (plus:DI (lshiftrt:DI | |
10505 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
10506 | (const_int 63)) | |
10507 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
10508 | (clobber (match_scratch:DI 3 "=&r"))] | |
10509 | "TARGET_POWERPC64" | |
10510 | "addic %3,%1,-1\;addze %0,%2" | |
10511 | [(set_attr "length" "8")]) | |
10512 | ||
1fd4e8c1 | 10513 | (define_insn "" |
9ebbca7d | 10514 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10515 | (compare:CC |
10516 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 10517 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 10518 | (const_int 31)) |
9ebbca7d | 10519 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 10520 | (const_int 0))) |
9ebbca7d | 10521 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 10522 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10523 | "@ |
10524 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
10525 | #" | |
b19003d8 | 10526 | [(set_attr "type" "compare") |
9ebbca7d GK |
10527 | (set_attr "length" "8,12")]) |
10528 | ||
10529 | (define_split | |
10530 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10531 | (compare:CC | |
10532 | (plus:SI (lshiftrt:SI | |
10533 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10534 | (const_int 31)) | |
10535 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
10536 | (const_int 0))) | |
10537 | (clobber (match_scratch:SI 3 ""))] | |
10538 | "! TARGET_POWERPC64 && reload_completed" | |
10539 | [(set (match_dup 3) | |
10540 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) | |
10541 | (const_int 31)) | |
10542 | (match_dup 2))) | |
10543 | (set (match_dup 0) | |
10544 | (compare:CC (match_dup 3) | |
10545 | (const_int 0)))] | |
10546 | "") | |
1fd4e8c1 | 10547 | |
a260abc9 | 10548 | (define_insn "" |
9ebbca7d | 10549 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
10550 | (compare:CC |
10551 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 10552 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 10553 | (const_int 63)) |
9ebbca7d | 10554 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 10555 | (const_int 0))) |
9ebbca7d | 10556 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 10557 | "TARGET_POWERPC64" |
9ebbca7d GK |
10558 | "@ |
10559 | addic %3,%1,-1\;addze. %3,%2 | |
10560 | #" | |
a260abc9 | 10561 | [(set_attr "type" "compare") |
9ebbca7d GK |
10562 | (set_attr "length" "8,12")]) |
10563 | ||
10564 | (define_split | |
10565 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10566 | (compare:CC | |
10567 | (plus:DI (lshiftrt:DI | |
10568 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10569 | (const_int 63)) | |
10570 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
10571 | (const_int 0))) | |
10572 | (clobber (match_scratch:DI 3 ""))] | |
10573 | "TARGET_POWERPC64 && reload_completed" | |
10574 | [(set (match_dup 3) | |
10575 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
10576 | (const_int 63)) | |
10577 | (match_dup 2))) | |
10578 | (set (match_dup 0) | |
10579 | (compare:CC (match_dup 3) | |
10580 | (const_int 0)))] | |
10581 | "") | |
a260abc9 | 10582 | |
1fd4e8c1 | 10583 | (define_insn "" |
9ebbca7d | 10584 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10585 | (compare:CC |
10586 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 10587 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 10588 | (const_int 31)) |
9ebbca7d | 10589 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 10590 | (const_int 0))) |
9ebbca7d | 10591 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
10592 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
10593 | (match_dup 2))) | |
9ebbca7d | 10594 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 10595 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10596 | "@ |
10597 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
10598 | #" | |
b19003d8 | 10599 | [(set_attr "type" "compare") |
9ebbca7d GK |
10600 | (set_attr "length" "8,12")]) |
10601 | ||
10602 | (define_split | |
10603 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10604 | (compare:CC | |
10605 | (plus:SI (lshiftrt:SI | |
10606 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10607 | (const_int 31)) | |
10608 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
10609 | (const_int 0))) | |
10610 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10611 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
10612 | (match_dup 2))) | |
10613 | (clobber (match_scratch:SI 3 ""))] | |
10614 | "! TARGET_POWERPC64 && reload_completed" | |
10615 | [(parallel [(set (match_dup 0) | |
10616 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
10617 | (match_dup 2))) | |
10618 | (clobber (match_dup 3))]) | |
10619 | (set (match_dup 4) | |
10620 | (compare:CC (match_dup 0) | |
10621 | (const_int 0)))] | |
10622 | "") | |
1fd4e8c1 | 10623 | |
a260abc9 | 10624 | (define_insn "" |
9ebbca7d | 10625 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
10626 | (compare:CC |
10627 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 10628 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 10629 | (const_int 63)) |
9ebbca7d | 10630 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 10631 | (const_int 0))) |
9ebbca7d | 10632 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
10633 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
10634 | (match_dup 2))) | |
9ebbca7d | 10635 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 10636 | "TARGET_POWERPC64" |
9ebbca7d GK |
10637 | "@ |
10638 | addic %3,%1,-1\;addze. %0,%2 | |
10639 | #" | |
a260abc9 | 10640 | [(set_attr "type" "compare") |
9ebbca7d GK |
10641 | (set_attr "length" "8,12")]) |
10642 | ||
10643 | (define_split | |
10644 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10645 | (compare:CC | |
10646 | (plus:DI (lshiftrt:DI | |
10647 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10648 | (const_int 63)) | |
10649 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
10650 | (const_int 0))) | |
10651 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
10652 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
10653 | (match_dup 2))) | |
10654 | (clobber (match_scratch:DI 3 ""))] | |
10655 | "TARGET_POWERPC64 && reload_completed" | |
10656 | [(parallel [(set (match_dup 0) | |
10657 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
10658 | (match_dup 2))) | |
10659 | (clobber (match_dup 3))]) | |
10660 | (set (match_dup 4) | |
10661 | (compare:CC (match_dup 0) | |
10662 | (const_int 0)))] | |
10663 | "") | |
a260abc9 | 10664 | |
1fd4e8c1 | 10665 | (define_insn "" |
cd2b37d9 RK |
10666 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
10667 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
10668 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
10669 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 10670 | "TARGET_POWER" |
1fd4e8c1 | 10671 | "@ |
ca7f5001 | 10672 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 10673 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 10674 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10675 | |
10676 | (define_insn "" | |
9ebbca7d | 10677 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 10678 | (compare:CC |
9ebbca7d GK |
10679 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
10680 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 10681 | (const_int 0))) |
9ebbca7d | 10682 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 10683 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 10684 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 10685 | "TARGET_POWER" |
1fd4e8c1 | 10686 | "@ |
ca7f5001 | 10687 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
10688 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
10689 | # | |
10690 | #" | |
10691 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
10692 | (set_attr "length" "12,12,16,16")]) | |
10693 | ||
10694 | (define_split | |
10695 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
10696 | (compare:CC | |
10697 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10698 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10699 | (const_int 0))) | |
10700 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10701 | (le:SI (match_dup 1) (match_dup 2))) | |
10702 | (clobber (match_scratch:SI 3 ""))] | |
10703 | "TARGET_POWER && reload_completed" | |
10704 | [(parallel [(set (match_dup 0) | |
10705 | (le:SI (match_dup 1) (match_dup 2))) | |
10706 | (clobber (match_dup 3))]) | |
10707 | (set (match_dup 4) | |
10708 | (compare:CC (match_dup 0) | |
10709 | (const_int 0)))] | |
10710 | "") | |
1fd4e8c1 RK |
10711 | |
10712 | (define_insn "" | |
cd2b37d9 RK |
10713 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
10714 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 10715 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
cd2b37d9 | 10716 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 10717 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 10718 | "TARGET_POWER" |
1fd4e8c1 | 10719 | "@ |
ca7f5001 RK |
10720 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
10721 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" | |
b19003d8 | 10722 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10723 | |
10724 | (define_insn "" | |
9ebbca7d | 10725 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 10726 | (compare:CC |
9ebbca7d GK |
10727 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
10728 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
10729 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 10730 | (const_int 0))) |
9ebbca7d | 10731 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 10732 | "TARGET_POWER" |
1fd4e8c1 | 10733 | "@ |
ca7f5001 | 10734 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
10735 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
10736 | # | |
10737 | #" | |
b19003d8 | 10738 | [(set_attr "type" "compare") |
9ebbca7d GK |
10739 | (set_attr "length" "12,12,16,16")]) |
10740 | ||
10741 | (define_split | |
10742 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10743 | (compare:CC | |
10744 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10745 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10746 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10747 | (const_int 0))) | |
10748 | (clobber (match_scratch:SI 4 ""))] | |
10749 | "TARGET_POWER && reload_completed" | |
10750 | [(set (match_dup 4) | |
10751 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
10752 | (match_dup 3))) | |
10753 | (set (match_dup 0) | |
10754 | (compare:CC (match_dup 4) | |
10755 | (const_int 0)))] | |
10756 | "") | |
1fd4e8c1 RK |
10757 | |
10758 | (define_insn "" | |
9ebbca7d | 10759 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 10760 | (compare:CC |
9ebbca7d GK |
10761 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
10762 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
10763 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 10764 | (const_int 0))) |
9ebbca7d | 10765 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 10766 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 10767 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 10768 | "TARGET_POWER" |
1fd4e8c1 | 10769 | "@ |
ca7f5001 | 10770 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
10771 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3 |
10772 | # | |
10773 | #" | |
b19003d8 | 10774 | [(set_attr "type" "compare") |
9ebbca7d GK |
10775 | (set_attr "length" "12,12,16,16")]) |
10776 | ||
10777 | (define_split | |
10778 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
10779 | (compare:CC | |
10780 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10781 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10782 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10783 | (const_int 0))) | |
10784 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10785 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10786 | (clobber (match_scratch:SI 4 ""))] | |
10787 | "TARGET_POWER && reload_completed" | |
10788 | [(parallel [(set (match_dup 0) | |
10789 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10790 | (clobber (match_dup 4))]) | |
10791 | (set (match_dup 5) | |
10792 | (compare:CC (match_dup 0) | |
10793 | (const_int 0)))] | |
10794 | "") | |
1fd4e8c1 RK |
10795 | |
10796 | (define_insn "" | |
cd2b37d9 RK |
10797 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
10798 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 10799 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 10800 | "TARGET_POWER" |
1fd4e8c1 | 10801 | "@ |
ca7f5001 RK |
10802 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
10803 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 10804 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10805 | |
10806 | (define_insn "" | |
cd2b37d9 RK |
10807 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10808 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10809 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 10810 | "! TARGET_POWERPC64" |
ca7f5001 | 10811 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 10812 | [(set_attr "length" "12")]) |
1fd4e8c1 | 10813 | |
f9562f27 DE |
10814 | (define_insn "" |
10815 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10816 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
10817 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
10818 | "TARGET_POWERPC64" | |
10819 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" | |
10820 | [(set_attr "length" "12")]) | |
10821 | ||
10822 | (define_insn "" | |
9ebbca7d | 10823 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 10824 | (compare:CC |
9ebbca7d GK |
10825 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
10826 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 10827 | (const_int 0))) |
9ebbca7d | 10828 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
10829 | (leu:DI (match_dup 1) (match_dup 2)))] |
10830 | "TARGET_POWERPC64" | |
9ebbca7d GK |
10831 | "@ |
10832 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
10833 | #" | |
f9562f27 | 10834 | [(set_attr "type" "compare") |
9ebbca7d GK |
10835 | (set_attr "length" "12,16")]) |
10836 | ||
10837 | (define_split | |
10838 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
10839 | (compare:CC | |
10840 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
10841 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
10842 | (const_int 0))) | |
10843 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
10844 | (leu:DI (match_dup 1) (match_dup 2)))] | |
10845 | "TARGET_POWERPC64 && reload_completed" | |
10846 | [(set (match_dup 0) | |
10847 | (leu:DI (match_dup 1) (match_dup 2))) | |
10848 | (set (match_dup 3) | |
10849 | (compare:CC (match_dup 0) | |
10850 | (const_int 0)))] | |
10851 | "") | |
f9562f27 | 10852 | |
1fd4e8c1 | 10853 | (define_insn "" |
9ebbca7d | 10854 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 10855 | (compare:CC |
9ebbca7d GK |
10856 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10857 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 10858 | (const_int 0))) |
9ebbca7d | 10859 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10860 | (leu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 10861 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10862 | "@ |
10863 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
10864 | #" | |
b19003d8 | 10865 | [(set_attr "type" "compare") |
9ebbca7d GK |
10866 | (set_attr "length" "12,16")]) |
10867 | ||
10868 | (define_split | |
10869 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
10870 | (compare:CC | |
10871 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10872 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10873 | (const_int 0))) | |
10874 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10875 | (leu:SI (match_dup 1) (match_dup 2)))] | |
10876 | "! TARGET_POWERPC64 && reload_completed" | |
10877 | [(set (match_dup 0) | |
10878 | (leu:SI (match_dup 1) (match_dup 2))) | |
10879 | (set (match_dup 3) | |
10880 | (compare:CC (match_dup 0) | |
10881 | (const_int 0)))] | |
10882 | "") | |
1fd4e8c1 | 10883 | |
f9562f27 | 10884 | (define_insn "" |
9ebbca7d | 10885 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 10886 | (compare:CC |
9ebbca7d GK |
10887 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
10888 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 10889 | (const_int 0))) |
9ebbca7d | 10890 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
10891 | (leu:DI (match_dup 1) (match_dup 2)))] |
10892 | "TARGET_POWERPC64" | |
9ebbca7d GK |
10893 | "@ |
10894 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
10895 | #" | |
f9562f27 | 10896 | [(set_attr "type" "compare") |
9ebbca7d | 10897 | (set_attr "length" "12,16")]) |
f9562f27 | 10898 | |
1fd4e8c1 | 10899 | (define_insn "" |
cd2b37d9 RK |
10900 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10901 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10902 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 10903 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10904 | (clobber (match_scratch:SI 4 "=&r"))] |
f9562f27 | 10905 | "! TARGET_POWERPC64" |
ca7f5001 | 10906 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 10907 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
10908 | |
10909 | (define_insn "" | |
9ebbca7d | 10910 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 10911 | (compare:CC |
9ebbca7d GK |
10912 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10913 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
10914 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 10915 | (const_int 0))) |
9ebbca7d | 10916 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 10917 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10918 | "@ |
10919 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
10920 | #" | |
b19003d8 | 10921 | [(set_attr "type" "compare") |
9ebbca7d GK |
10922 | (set_attr "length" "8,12")]) |
10923 | ||
10924 | (define_split | |
10925 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10926 | (compare:CC | |
10927 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10928 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10929 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10930 | (const_int 0))) | |
10931 | (clobber (match_scratch:SI 4 ""))] | |
10932 | "! TARGET_POWERPC64 && reload_completed" | |
10933 | [(set (match_dup 4) | |
10934 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
10935 | (match_dup 3))) | |
10936 | (set (match_dup 0) | |
10937 | (compare:CC (match_dup 4) | |
10938 | (const_int 0)))] | |
10939 | "") | |
1fd4e8c1 RK |
10940 | |
10941 | (define_insn "" | |
9ebbca7d | 10942 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 10943 | (compare:CC |
9ebbca7d GK |
10944 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10945 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
10946 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 10947 | (const_int 0))) |
9ebbca7d | 10948 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10949 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 10950 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 10951 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10952 | "@ |
10953 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3 | |
10954 | #" | |
b19003d8 | 10955 | [(set_attr "type" "compare") |
9ebbca7d GK |
10956 | (set_attr "length" "8,12")]) |
10957 | ||
10958 | (define_split | |
10959 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
10960 | (compare:CC | |
10961 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
10962 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
10963 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
10964 | (const_int 0))) | |
10965 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
10966 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10967 | (clobber (match_scratch:SI 4 ""))] | |
10968 | "! TARGET_POWERPC64 && reload_completed" | |
10969 | [(parallel [(set (match_dup 0) | |
10970 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
10971 | (clobber (match_dup 4))]) | |
10972 | (set (match_dup 5) | |
10973 | (compare:CC (match_dup 0) | |
10974 | (const_int 0)))] | |
10975 | "") | |
1fd4e8c1 RK |
10976 | |
10977 | (define_insn "" | |
cd2b37d9 RK |
10978 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10979 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10980 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 10981 | "! TARGET_POWERPC64" |
ca7f5001 | 10982 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 10983 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10984 | |
10985 | (define_insn "" | |
cd2b37d9 | 10986 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 10987 | (and:SI (neg:SI |
cd2b37d9 | 10988 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10989 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
cd2b37d9 | 10990 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10991 | (clobber (match_scratch:SI 4 "=&r"))] |
f9562f27 | 10992 | "! TARGET_POWERPC64" |
ca7f5001 | 10993 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" |
b19003d8 | 10994 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10995 | |
10996 | (define_insn "" | |
9ebbca7d | 10997 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10998 | (compare:CC |
10999 | (and:SI (neg:SI | |
9ebbca7d GK |
11000 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11001 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11002 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11003 | (const_int 0))) |
9ebbca7d | 11004 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11005 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11006 | "@ |
11007 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
11008 | #" | |
11009 | [(set_attr "type" "compare") | |
11010 | (set_attr "length" "12,16")]) | |
11011 | ||
11012 | (define_split | |
11013 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11014 | (compare:CC | |
11015 | (and:SI (neg:SI | |
11016 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11017 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11018 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11019 | (const_int 0))) | |
11020 | (clobber (match_scratch:SI 4 ""))] | |
11021 | "! TARGET_POWERPC64 && reload_completed" | |
11022 | [(set (match_dup 4) | |
11023 | (and:SI (neg:SI (leu:SI (match_dup 1) | |
11024 | (match_dup 2))) | |
11025 | (match_dup 3))) | |
11026 | (set (match_dup 0) | |
11027 | (compare:CC (match_dup 4) | |
11028 | (const_int 0)))] | |
11029 | "") | |
1fd4e8c1 RK |
11030 | |
11031 | (define_insn "" | |
9ebbca7d | 11032 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11033 | (compare:CC |
11034 | (and:SI (neg:SI | |
9ebbca7d GK |
11035 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11036 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11037 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11038 | (const_int 0))) |
9ebbca7d | 11039 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11040 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
9ebbca7d | 11041 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11042 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11043 | "@ |
11044 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 | |
11045 | #" | |
b19003d8 | 11046 | [(set_attr "type" "compare") |
9ebbca7d GK |
11047 | (set_attr "length" "12,16")]) |
11048 | ||
11049 | (define_split | |
11050 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11051 | (compare:CC | |
11052 | (and:SI (neg:SI | |
11053 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11054 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11055 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11056 | (const_int 0))) | |
11057 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11058 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11059 | (clobber (match_scratch:SI 4 ""))] | |
11060 | "! TARGET_POWERPC64 && reload_completed" | |
11061 | [(parallel [(set (match_dup 0) | |
11062 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11063 | (clobber (match_dup 4))]) | |
11064 | (set (match_dup 5) | |
11065 | (compare:CC (match_dup 0) | |
11066 | (const_int 0)))] | |
11067 | "") | |
1fd4e8c1 RK |
11068 | |
11069 | (define_insn "" | |
cd2b37d9 RK |
11070 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11071 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11072 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 11073 | "TARGET_POWER" |
7f340546 | 11074 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11075 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11076 | |
11077 | (define_insn "" | |
9ebbca7d | 11078 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11079 | (compare:CC |
9ebbca7d GK |
11080 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11081 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11082 | (const_int 0))) |
9ebbca7d | 11083 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11084 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 11085 | "TARGET_POWER" |
9ebbca7d GK |
11086 | "@ |
11087 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
11088 | #" | |
29ae5b89 | 11089 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11090 | (set_attr "length" "12,16")]) |
11091 | ||
11092 | (define_split | |
11093 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11094 | (compare:CC | |
11095 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11096 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11097 | (const_int 0))) | |
11098 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11099 | (lt:SI (match_dup 1) (match_dup 2)))] | |
11100 | "TARGET_POWER && reload_completed" | |
11101 | [(set (match_dup 0) | |
11102 | (lt:SI (match_dup 1) (match_dup 2))) | |
11103 | (set (match_dup 3) | |
11104 | (compare:CC (match_dup 0) | |
11105 | (const_int 0)))] | |
11106 | "") | |
1fd4e8c1 RK |
11107 | |
11108 | (define_insn "" | |
cd2b37d9 RK |
11109 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11110 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11111 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 11112 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11113 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
11114 | "TARGET_POWER" |
11115 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 11116 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11117 | |
11118 | (define_insn "" | |
9ebbca7d | 11119 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11120 | (compare:CC |
9ebbca7d GK |
11121 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11122 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11123 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11124 | (const_int 0))) |
9ebbca7d | 11125 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11126 | "TARGET_POWER" |
9ebbca7d GK |
11127 | "@ |
11128 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
11129 | #" | |
b19003d8 | 11130 | [(set_attr "type" "compare") |
9ebbca7d GK |
11131 | (set_attr "length" "12,16")]) |
11132 | ||
11133 | (define_split | |
11134 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11135 | (compare:CC | |
11136 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11137 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11138 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11139 | (const_int 0))) | |
11140 | (clobber (match_scratch:SI 4 ""))] | |
11141 | "TARGET_POWER && reload_completed" | |
11142 | [(set (match_dup 4) | |
11143 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
11144 | (match_dup 3))) | |
11145 | (set (match_dup 0) | |
11146 | (compare:CC (match_dup 4) | |
11147 | (const_int 0)))] | |
11148 | "") | |
1fd4e8c1 RK |
11149 | |
11150 | (define_insn "" | |
9ebbca7d | 11151 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11152 | (compare:CC |
9ebbca7d GK |
11153 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11154 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11155 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11156 | (const_int 0))) |
9ebbca7d | 11157 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11158 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11159 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11160 | "TARGET_POWER" |
9ebbca7d GK |
11161 | "@ |
11162 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 | |
11163 | #" | |
b19003d8 | 11164 | [(set_attr "type" "compare") |
9ebbca7d GK |
11165 | (set_attr "length" "12,16")]) |
11166 | ||
11167 | (define_split | |
11168 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11169 | (compare:CC | |
11170 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11171 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11172 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11173 | (const_int 0))) | |
11174 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11175 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11176 | (clobber (match_scratch:SI 4 ""))] | |
11177 | "TARGET_POWER && reload_completed" | |
11178 | [(parallel [(set (match_dup 0) | |
11179 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11180 | (clobber (match_dup 4))]) | |
11181 | (set (match_dup 5) | |
11182 | (compare:CC (match_dup 0) | |
11183 | (const_int 0)))] | |
11184 | "") | |
1fd4e8c1 RK |
11185 | |
11186 | (define_insn "" | |
cd2b37d9 RK |
11187 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11188 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11189 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
11190 | "TARGET_POWER" |
11191 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 11192 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11193 | |
11194 | (define_insn "" | |
cd2b37d9 RK |
11195 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11196 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11197 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 11198 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11199 | "@ |
ca7f5001 RK |
11200 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
11201 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 11202 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11203 | |
11204 | (define_insn "" | |
9ebbca7d | 11205 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11206 | (compare:CC |
9ebbca7d GK |
11207 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11208 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 11209 | (const_int 0))) |
9ebbca7d | 11210 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11211 | (ltu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11212 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11213 | "@ |
ca7f5001 | 11214 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
11215 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
11216 | # | |
11217 | #" | |
b19003d8 | 11218 | [(set_attr "type" "compare") |
9ebbca7d GK |
11219 | (set_attr "length" "12,12,16,16")]) |
11220 | ||
11221 | (define_split | |
11222 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11223 | (compare:CC | |
11224 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11225 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11226 | (const_int 0))) | |
11227 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11228 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
11229 | "! TARGET_POWERPC64 && reload_completed" | |
11230 | [(set (match_dup 0) | |
11231 | (ltu:SI (match_dup 1) (match_dup 2))) | |
11232 | (set (match_dup 3) | |
11233 | (compare:CC (match_dup 0) | |
11234 | (const_int 0)))] | |
11235 | "") | |
1fd4e8c1 RK |
11236 | |
11237 | (define_insn "" | |
19378cf8 MM |
11238 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11239 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
11240 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
11241 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI"))) | |
11242 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
f9562f27 | 11243 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11244 | "@ |
ca7f5001 | 11245 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 |
04be6346 | 11246 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
b19003d8 | 11247 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11248 | |
11249 | (define_insn "" | |
9ebbca7d | 11250 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11251 | (compare:CC |
9ebbca7d GK |
11252 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11253 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11254 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11255 | (const_int 0))) |
9ebbca7d | 11256 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11257 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11258 | "@ |
ca7f5001 | 11259 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
9ebbca7d GK |
11260 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
11261 | # | |
11262 | #" | |
b19003d8 | 11263 | [(set_attr "type" "compare") |
9ebbca7d GK |
11264 | (set_attr "length" "12,12,16,16")]) |
11265 | ||
11266 | (define_split | |
11267 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11268 | (compare:CC | |
11269 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11270 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11271 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11272 | (const_int 0))) | |
11273 | (clobber (match_scratch:SI 4 ""))] | |
11274 | "! TARGET_POWERPC64 && reload_completed" | |
11275 | [(set (match_dup 4) | |
11276 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
11277 | (match_dup 3))) | |
11278 | (set (match_dup 0) | |
11279 | (compare:CC (match_dup 4) | |
11280 | (const_int 0)))] | |
11281 | "") | |
1fd4e8c1 RK |
11282 | |
11283 | (define_insn "" | |
9ebbca7d | 11284 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11285 | (compare:CC |
9ebbca7d GK |
11286 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11287 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11288 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11289 | (const_int 0))) |
9ebbca7d | 11290 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11291 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11292 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11293 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11294 | "@ |
ca7f5001 | 11295 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
9ebbca7d GK |
11296 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
11297 | # | |
11298 | #" | |
b19003d8 | 11299 | [(set_attr "type" "compare") |
9ebbca7d GK |
11300 | (set_attr "length" "12,12,16,16")]) |
11301 | ||
11302 | (define_split | |
11303 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11304 | (compare:CC | |
11305 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11306 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11307 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11308 | (const_int 0))) | |
11309 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11310 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11311 | (clobber (match_scratch:SI 4 ""))] | |
11312 | "! TARGET_POWERPC64 && reload_completed" | |
11313 | [(parallel [(set (match_dup 0) | |
11314 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11315 | (clobber (match_dup 4))]) | |
11316 | (set (match_dup 5) | |
11317 | (compare:CC (match_dup 0) | |
11318 | (const_int 0)))] | |
11319 | "") | |
1fd4e8c1 RK |
11320 | |
11321 | (define_insn "" | |
cd2b37d9 RK |
11322 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11323 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11324 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
f9562f27 | 11325 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11326 | "@ |
ca7f5001 RK |
11327 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
11328 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11329 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
11330 | |
11331 | (define_insn "" | |
cd2b37d9 RK |
11332 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11333 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
11334 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
11335 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
11336 | "TARGET_POWER" |
11337 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 11338 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11339 | |
9ebbca7d GK |
11340 | (define_insn "" |
11341 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 11342 | (compare:CC |
9ebbca7d GK |
11343 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11344 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11345 | (const_int 0))) |
9ebbca7d | 11346 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11347 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11348 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 11349 | "TARGET_POWER" |
9ebbca7d GK |
11350 | "@ |
11351 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
11352 | #" | |
11353 | [(set_attr "type" "compare") | |
11354 | (set_attr "length" "12,16")]) | |
11355 | ||
11356 | (define_split | |
11357 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11358 | (compare:CC | |
11359 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11360 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11361 | (const_int 0))) | |
11362 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11363 | (ge:SI (match_dup 1) (match_dup 2))) | |
11364 | (clobber (match_scratch:SI 3 ""))] | |
11365 | "TARGET_POWER && reload_completed" | |
11366 | [(parallel [(set (match_dup 0) | |
11367 | (ge:SI (match_dup 1) (match_dup 2))) | |
11368 | (clobber (match_dup 3))]) | |
11369 | (set (match_dup 4) | |
11370 | (compare:CC (match_dup 0) | |
11371 | (const_int 0)))] | |
11372 | "") | |
11373 | ||
1fd4e8c1 | 11374 | (define_insn "" |
cd2b37d9 RK |
11375 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11376 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11377 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 11378 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11379 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
11380 | "TARGET_POWER" |
11381 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" | |
b19003d8 | 11382 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11383 | |
11384 | (define_insn "" | |
9ebbca7d | 11385 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11386 | (compare:CC |
9ebbca7d GK |
11387 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11388 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11389 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11390 | (const_int 0))) |
9ebbca7d | 11391 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11392 | "TARGET_POWER" |
9ebbca7d GK |
11393 | "@ |
11394 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
11395 | #" | |
b19003d8 | 11396 | [(set_attr "type" "compare") |
9ebbca7d GK |
11397 | (set_attr "length" "12,16")]) |
11398 | ||
11399 | (define_split | |
11400 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11401 | (compare:CC | |
11402 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11403 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11404 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11405 | (const_int 0))) | |
11406 | (clobber (match_scratch:SI 4 ""))] | |
11407 | "TARGET_POWER && reload_completed" | |
11408 | [(set (match_dup 4) | |
11409 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
11410 | (match_dup 3))) | |
11411 | (set (match_dup 0) | |
11412 | (compare:CC (match_dup 4) | |
11413 | (const_int 0)))] | |
11414 | "") | |
1fd4e8c1 RK |
11415 | |
11416 | (define_insn "" | |
9ebbca7d | 11417 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11418 | (compare:CC |
9ebbca7d GK |
11419 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11420 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11421 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11422 | (const_int 0))) |
9ebbca7d | 11423 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11424 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11425 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11426 | "TARGET_POWER" |
9ebbca7d GK |
11427 | "@ |
11428 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
11429 | #" | |
b19003d8 | 11430 | [(set_attr "type" "compare") |
9ebbca7d GK |
11431 | (set_attr "length" "12,16")]) |
11432 | ||
11433 | (define_split | |
11434 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11435 | (compare:CC | |
11436 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11437 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11438 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11439 | (const_int 0))) | |
11440 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11441 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11442 | (clobber (match_scratch:SI 4 ""))] | |
11443 | "TARGET_POWER && reload_completed" | |
11444 | [(parallel [(set (match_dup 0) | |
11445 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11446 | (clobber (match_dup 4))]) | |
11447 | (set (match_dup 5) | |
11448 | (compare:CC (match_dup 0) | |
11449 | (const_int 0)))] | |
11450 | "") | |
1fd4e8c1 RK |
11451 | |
11452 | (define_insn "" | |
cd2b37d9 RK |
11453 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11454 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11455 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
11456 | "TARGET_POWER" |
11457 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11458 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11459 | |
1fd4e8c1 | 11460 | (define_insn "" |
cd2b37d9 RK |
11461 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11462 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11463 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 11464 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11465 | "@ |
ca7f5001 RK |
11466 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
11467 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 11468 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11469 | |
f9562f27 DE |
11470 | (define_insn "" |
11471 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
11472 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
11473 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
11474 | "TARGET_POWERPC64" | |
11475 | "@ | |
11476 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
11477 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
11478 | [(set_attr "length" "12")]) | |
11479 | ||
1fd4e8c1 | 11480 | (define_insn "" |
9ebbca7d | 11481 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11482 | (compare:CC |
9ebbca7d GK |
11483 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11484 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 11485 | (const_int 0))) |
9ebbca7d | 11486 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11487 | (geu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11488 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11489 | "@ |
ca7f5001 | 11490 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
11491 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
11492 | # | |
11493 | #" | |
b19003d8 | 11494 | [(set_attr "type" "compare") |
9ebbca7d GK |
11495 | (set_attr "length" "12,12,16,16")]) |
11496 | ||
11497 | (define_split | |
11498 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11499 | (compare:CC | |
11500 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11501 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11502 | (const_int 0))) | |
11503 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11504 | (geu:SI (match_dup 1) (match_dup 2)))] | |
11505 | "! TARGET_POWERPC64 && reload_completed" | |
11506 | [(set (match_dup 0) | |
11507 | (geu:SI (match_dup 1) (match_dup 2))) | |
11508 | (set (match_dup 3) | |
11509 | (compare:CC (match_dup 0) | |
11510 | (const_int 0)))] | |
11511 | "") | |
1fd4e8c1 | 11512 | |
f9562f27 | 11513 | (define_insn "" |
9ebbca7d | 11514 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 11515 | (compare:CC |
9ebbca7d GK |
11516 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
11517 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 11518 | (const_int 0))) |
9ebbca7d | 11519 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 DE |
11520 | (geu:DI (match_dup 1) (match_dup 2)))] |
11521 | "TARGET_POWERPC64" | |
11522 | "@ | |
11523 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
11524 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
11525 | # | |
11526 | #" | |
f9562f27 | 11527 | [(set_attr "type" "compare") |
9ebbca7d GK |
11528 | (set_attr "length" "12,12,16,16")]) |
11529 | ||
11530 | (define_split | |
11531 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11532 | (compare:CC | |
11533 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11534 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
11535 | (const_int 0))) | |
11536 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11537 | (geu:DI (match_dup 1) (match_dup 2)))] | |
11538 | "TARGET_POWERPC64 && reload_completed" | |
11539 | [(set (match_dup 0) | |
11540 | (geu:DI (match_dup 1) (match_dup 2))) | |
11541 | (set (match_dup 3) | |
11542 | (compare:CC (match_dup 0) | |
11543 | (const_int 0)))] | |
11544 | "") | |
f9562f27 | 11545 | |
1fd4e8c1 | 11546 | (define_insn "" |
cd2b37d9 RK |
11547 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11548 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11549 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
cd2b37d9 | 11550 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11551 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11552 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11553 | "@ |
ca7f5001 RK |
11554 | {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3 |
11555 | {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 11556 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
11557 | |
11558 | (define_insn "" | |
9ebbca7d | 11559 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11560 | (compare:CC |
9ebbca7d GK |
11561 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11562 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11563 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11564 | (const_int 0))) |
9ebbca7d | 11565 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11566 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11567 | "@ |
ca7f5001 | 11568 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
11569 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
11570 | # | |
11571 | #" | |
b19003d8 | 11572 | [(set_attr "type" "compare") |
9ebbca7d GK |
11573 | (set_attr "length" "8,8,12,12")]) |
11574 | ||
11575 | (define_split | |
11576 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11577 | (compare:CC | |
11578 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11579 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11580 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11581 | (const_int 0))) | |
11582 | (clobber (match_scratch:SI 4 ""))] | |
11583 | "! TARGET_POWERPC64 && reload_completed" | |
11584 | [(set (match_dup 4) | |
11585 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
11586 | (match_dup 3))) | |
11587 | (set (match_dup 0) | |
11588 | (compare:CC (match_dup 4) | |
11589 | (const_int 0)))] | |
11590 | "") | |
1fd4e8c1 RK |
11591 | |
11592 | (define_insn "" | |
9ebbca7d | 11593 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11594 | (compare:CC |
9ebbca7d GK |
11595 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11596 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
11597 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11598 | (const_int 0))) |
9ebbca7d | 11599 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11600 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11601 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11602 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11603 | "@ |
ca7f5001 | 11604 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
11605 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3 |
11606 | # | |
11607 | #" | |
b19003d8 | 11608 | [(set_attr "type" "compare") |
9ebbca7d GK |
11609 | (set_attr "length" "8,8,12,12")]) |
11610 | ||
11611 | (define_split | |
11612 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11613 | (compare:CC | |
11614 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11615 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
11616 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11617 | (const_int 0))) | |
11618 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11619 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11620 | (clobber (match_scratch:SI 4 ""))] | |
11621 | "! TARGET_POWERPC64 && reload_completed" | |
11622 | [(parallel [(set (match_dup 0) | |
11623 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11624 | (clobber (match_dup 4))]) | |
11625 | (set (match_dup 5) | |
11626 | (compare:CC (match_dup 0) | |
11627 | (const_int 0)))] | |
11628 | "") | |
1fd4e8c1 RK |
11629 | |
11630 | (define_insn "" | |
cd2b37d9 RK |
11631 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11632 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11633 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
f9562f27 | 11634 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11635 | "@ |
ca7f5001 | 11636 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 11637 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 11638 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11639 | |
11640 | (define_insn "" | |
cd2b37d9 | 11641 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11642 | (and:SI (neg:SI |
cd2b37d9 | 11643 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 11644 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
cd2b37d9 | 11645 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11646 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11647 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11648 | "@ |
ca7f5001 RK |
11649 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 |
11650 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" | |
b19003d8 | 11651 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11652 | |
11653 | (define_insn "" | |
9ebbca7d | 11654 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
11655 | (compare:CC |
11656 | (and:SI (neg:SI | |
9ebbca7d GK |
11657 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11658 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
11659 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11660 | (const_int 0))) |
9ebbca7d | 11661 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11662 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11663 | "@ |
ca7f5001 | 11664 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
11665 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
11666 | # | |
11667 | #" | |
b19003d8 | 11668 | [(set_attr "type" "compare") |
9ebbca7d GK |
11669 | (set_attr "length" "12,12,16,16")]) |
11670 | ||
11671 | (define_split | |
11672 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11673 | (compare:CC | |
11674 | (and:SI (neg:SI | |
11675 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11676 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
11677 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11678 | (const_int 0))) | |
11679 | (clobber (match_scratch:SI 4 ""))] | |
11680 | "! TARGET_POWERPC64 && reload_completed" | |
11681 | [(set (match_dup 4) | |
11682 | (and:SI (neg:SI (geu:SI (match_dup 1) | |
11683 | (match_dup 2))) | |
11684 | (match_dup 3))) | |
11685 | (set (match_dup 0) | |
11686 | (compare:CC (match_dup 4) | |
11687 | (const_int 0)))] | |
11688 | "") | |
1fd4e8c1 RK |
11689 | |
11690 | (define_insn "" | |
9ebbca7d | 11691 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
11692 | (compare:CC |
11693 | (and:SI (neg:SI | |
9ebbca7d GK |
11694 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11695 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
11696 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11697 | (const_int 0))) |
9ebbca7d | 11698 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11699 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
9ebbca7d | 11700 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 11701 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11702 | "@ |
ca7f5001 | 11703 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
9ebbca7d GK |
11704 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
11705 | # | |
11706 | #" | |
b19003d8 | 11707 | [(set_attr "type" "compare") |
9ebbca7d GK |
11708 | (set_attr "length" "12,12,16,16")]) |
11709 | ||
11710 | (define_split | |
11711 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11712 | (compare:CC | |
11713 | (and:SI (neg:SI | |
11714 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11715 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
11716 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11717 | (const_int 0))) | |
11718 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11719 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11720 | (clobber (match_scratch:SI 4 ""))] | |
11721 | "! TARGET_POWERPC64 && reload_completed" | |
11722 | [(parallel [(set (match_dup 0) | |
11723 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11724 | (clobber (match_dup 4))]) | |
11725 | (set (match_dup 5) | |
11726 | (compare:CC (match_dup 0) | |
11727 | (const_int 0)))] | |
11728 | "") | |
1fd4e8c1 RK |
11729 | |
11730 | (define_insn "" | |
cd2b37d9 RK |
11731 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11732 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11733 | (const_int 0)))] |
f9562f27 | 11734 | "! TARGET_POWERPC64" |
ca7f5001 | 11735 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11736 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11737 | |
f9562f27 DE |
11738 | (define_insn "" |
11739 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11740 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
11741 | (const_int 0)))] | |
11742 | "TARGET_POWERPC64" | |
11743 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" | |
11744 | [(set_attr "length" "12")]) | |
11745 | ||
1fd4e8c1 | 11746 | (define_insn "" |
9ebbca7d | 11747 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11748 | (compare:CC |
9ebbca7d | 11749 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
11750 | (const_int 0)) |
11751 | (const_int 0))) | |
9ebbca7d | 11752 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11753 | (gt:SI (match_dup 1) (const_int 0)))] |
f9562f27 | 11754 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11755 | "@ |
11756 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
11757 | #" | |
29ae5b89 | 11758 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11759 | (set_attr "length" "12,16")]) |
11760 | ||
11761 | (define_split | |
11762 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
11763 | (compare:CC | |
11764 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11765 | (const_int 0)) | |
11766 | (const_int 0))) | |
11767 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11768 | (gt:SI (match_dup 1) (const_int 0)))] | |
11769 | "! TARGET_POWERPC64 && reload_completed" | |
11770 | [(set (match_dup 0) | |
11771 | (gt:SI (match_dup 1) (const_int 0))) | |
11772 | (set (match_dup 2) | |
11773 | (compare:CC (match_dup 0) | |
11774 | (const_int 0)))] | |
11775 | "") | |
1fd4e8c1 | 11776 | |
f9562f27 | 11777 | (define_insn "" |
9ebbca7d | 11778 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 11779 | (compare:CC |
9ebbca7d | 11780 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
11781 | (const_int 0)) |
11782 | (const_int 0))) | |
9ebbca7d | 11783 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
11784 | (gt:DI (match_dup 1) (const_int 0)))] |
11785 | "TARGET_POWERPC64" | |
9ebbca7d GK |
11786 | "@ |
11787 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
11788 | #" | |
f9562f27 | 11789 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11790 | (set_attr "length" "12,16")]) |
11791 | ||
11792 | (define_split | |
11793 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
11794 | (compare:CC | |
11795 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11796 | (const_int 0)) | |
11797 | (const_int 0))) | |
11798 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11799 | (gt:DI (match_dup 1) (const_int 0)))] | |
11800 | "TARGET_POWERPC64 && reload_completed" | |
11801 | [(set (match_dup 0) | |
11802 | (gt:DI (match_dup 1) (const_int 0))) | |
11803 | (set (match_dup 2) | |
11804 | (compare:CC (match_dup 0) | |
11805 | (const_int 0)))] | |
11806 | "") | |
f9562f27 | 11807 | |
1fd4e8c1 | 11808 | (define_insn "" |
cd2b37d9 RK |
11809 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11810 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11811 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
11812 | "TARGET_POWER" |
11813 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 11814 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11815 | |
11816 | (define_insn "" | |
9ebbca7d | 11817 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11818 | (compare:CC |
9ebbca7d GK |
11819 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11820 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 11821 | (const_int 0))) |
9ebbca7d | 11822 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11823 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 11824 | "TARGET_POWER" |
9ebbca7d GK |
11825 | "@ |
11826 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
11827 | #" | |
29ae5b89 | 11828 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11829 | (set_attr "length" "12,16")]) |
11830 | ||
11831 | (define_split | |
11832 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11833 | (compare:CC | |
11834 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11835 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11836 | (const_int 0))) | |
11837 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11838 | (gt:SI (match_dup 1) (match_dup 2)))] | |
11839 | "TARGET_POWER && reload_completed" | |
11840 | [(set (match_dup 0) | |
11841 | (gt:SI (match_dup 1) (match_dup 2))) | |
11842 | (set (match_dup 3) | |
11843 | (compare:CC (match_dup 0) | |
11844 | (const_int 0)))] | |
11845 | "") | |
1fd4e8c1 RK |
11846 | |
11847 | (define_insn "" | |
cd2b37d9 RK |
11848 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11849 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11850 | (const_int 0)) |
cd2b37d9 | 11851 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11852 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 11853 | "! TARGET_POWERPC64" |
ca7f5001 | 11854 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2" |
b19003d8 | 11855 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11856 | |
f9562f27 DE |
11857 | (define_insn "" |
11858 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11859 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
11860 | (const_int 0)) | |
11861 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11862 | (clobber (match_scratch:DI 3 "=&r"))] | |
11863 | "TARGET_POWERPC64" | |
11864 | "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2" | |
11865 | [(set_attr "length" "12")]) | |
11866 | ||
1fd4e8c1 | 11867 | (define_insn "" |
9ebbca7d | 11868 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11869 | (compare:CC |
9ebbca7d | 11870 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 11871 | (const_int 0)) |
9ebbca7d | 11872 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11873 | (const_int 0))) |
9ebbca7d | 11874 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 11875 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11876 | "@ |
11877 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
11878 | #" | |
b19003d8 | 11879 | [(set_attr "type" "compare") |
9ebbca7d GK |
11880 | (set_attr "length" "12,16")]) |
11881 | ||
11882 | (define_split | |
11883 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11884 | (compare:CC | |
11885 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11886 | (const_int 0)) | |
11887 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11888 | (const_int 0))) | |
11889 | (clobber (match_scratch:SI 3 ""))] | |
11890 | "! TARGET_POWERPC64 && reload_completed" | |
11891 | [(set (match_dup 3) | |
11892 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
11893 | (match_dup 2))) | |
11894 | (set (match_dup 0) | |
11895 | (compare:CC (match_dup 3) | |
11896 | (const_int 0)))] | |
11897 | "") | |
1fd4e8c1 | 11898 | |
f9562f27 | 11899 | (define_insn "" |
9ebbca7d | 11900 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 11901 | (compare:CC |
9ebbca7d | 11902 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 11903 | (const_int 0)) |
9ebbca7d | 11904 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 11905 | (const_int 0))) |
9ebbca7d | 11906 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 11907 | "TARGET_POWERPC64" |
9ebbca7d GK |
11908 | "@ |
11909 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
11910 | #" | |
f9562f27 | 11911 | [(set_attr "type" "compare") |
9ebbca7d GK |
11912 | (set_attr "length" "12,16")]) |
11913 | ||
11914 | (define_split | |
11915 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11916 | (compare:CC | |
11917 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11918 | (const_int 0)) | |
11919 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11920 | (const_int 0))) | |
11921 | (clobber (match_scratch:DI 3 ""))] | |
11922 | "TARGET_POWERPC64 && reload_completed" | |
11923 | [(set (match_dup 3) | |
11924 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
11925 | (match_dup 2))) | |
11926 | (set (match_dup 0) | |
11927 | (compare:CC (match_dup 3) | |
11928 | (const_int 0)))] | |
11929 | "") | |
f9562f27 | 11930 | |
1fd4e8c1 | 11931 | (define_insn "" |
9ebbca7d GK |
11932 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
11933 | (compare:CC | |
11934 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
11935 | (const_int 0)) | |
11936 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
11937 | (const_int 0))) | |
11938 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
11939 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) | |
11940 | (clobber (match_scratch:SI 3 "=&r,&r"))] | |
11941 | "! TARGET_POWERPC64" | |
11942 | "@ | |
11943 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2 | |
11944 | #" | |
11945 | [(set_attr "type" "compare") | |
11946 | (set_attr "length" "12,16")]) | |
11947 | ||
11948 | (define_split | |
11949 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
1fd4e8c1 | 11950 | (compare:CC |
9ebbca7d | 11951 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11952 | (const_int 0)) |
9ebbca7d | 11953 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 11954 | (const_int 0))) |
9ebbca7d | 11955 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 11956 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
9ebbca7d GK |
11957 | (clobber (match_scratch:SI 3 ""))] |
11958 | "! TARGET_POWERPC64 && reload_completed" | |
11959 | [(parallel [(set (match_dup 0) | |
11960 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) | |
11961 | (clobber (match_dup 3))]) | |
11962 | (set (match_dup 4) | |
11963 | (compare:CC (match_dup 0) | |
11964 | (const_int 0)))] | |
11965 | "") | |
1fd4e8c1 | 11966 | |
f9562f27 | 11967 | (define_insn "" |
9ebbca7d | 11968 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
f9562f27 | 11969 | (compare:CC |
9ebbca7d | 11970 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 11971 | (const_int 0)) |
9ebbca7d | 11972 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 11973 | (const_int 0))) |
9ebbca7d | 11974 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 11975 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
9ebbca7d | 11976 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 11977 | "TARGET_POWERPC64" |
9ebbca7d GK |
11978 | "@ |
11979 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2 | |
11980 | #" | |
f9562f27 | 11981 | [(set_attr "type" "compare") |
9ebbca7d GK |
11982 | (set_attr "length" "12,16")]) |
11983 | ||
11984 | (define_split | |
11985 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11986 | (compare:CC | |
11987 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11988 | (const_int 0)) | |
11989 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11990 | (const_int 0))) | |
11991 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11992 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) | |
11993 | (clobber (match_scratch:DI 3 ""))] | |
11994 | "TARGET_POWERPC64 && reload_completed" | |
11995 | [(parallel [(set (match_dup 0) | |
11996 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) | |
11997 | (clobber (match_dup 3))]) | |
11998 | (set (match_dup 4) | |
11999 | (compare:CC (match_dup 0) | |
12000 | (const_int 0)))] | |
12001 | "") | |
f9562f27 | 12002 | |
1fd4e8c1 | 12003 | (define_insn "" |
cd2b37d9 RK |
12004 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12005 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12006 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
cd2b37d9 | 12007 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 12008 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
12009 | "TARGET_POWER" |
12010 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 12011 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12012 | |
12013 | (define_insn "" | |
9ebbca7d | 12014 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12015 | (compare:CC |
9ebbca7d GK |
12016 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12017 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
12018 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12019 | (const_int 0))) |
9ebbca7d | 12020 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12021 | "TARGET_POWER" |
9ebbca7d GK |
12022 | "@ |
12023 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12024 | #" | |
b19003d8 | 12025 | [(set_attr "type" "compare") |
9ebbca7d GK |
12026 | (set_attr "length" "12,16")]) |
12027 | ||
12028 | (define_split | |
12029 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12030 | (compare:CC | |
12031 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12032 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12033 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12034 | (const_int 0))) | |
12035 | (clobber (match_scratch:SI 4 ""))] | |
12036 | "TARGET_POWER && reload_completed" | |
12037 | [(set (match_dup 4) | |
12038 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) | |
12039 | (match_dup 3))) | |
12040 | (set (match_dup 0) | |
12041 | (compare:CC (match_dup 4) | |
12042 | (const_int 0)))] | |
12043 | "") | |
1fd4e8c1 RK |
12044 | |
12045 | (define_insn "" | |
9ebbca7d | 12046 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12047 | (compare:CC |
9ebbca7d GK |
12048 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12049 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
12050 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12051 | (const_int 0))) |
9ebbca7d | 12052 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12053 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12054 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12055 | "TARGET_POWER" |
9ebbca7d GK |
12056 | "@ |
12057 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 | |
12058 | #" | |
b19003d8 | 12059 | [(set_attr "type" "compare") |
9ebbca7d GK |
12060 | (set_attr "length" "12,16")]) |
12061 | ||
12062 | (define_split | |
12063 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12064 | (compare:CC | |
12065 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12066 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12067 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12068 | (const_int 0))) | |
12069 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12070 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12071 | (clobber (match_scratch:SI 4 ""))] | |
12072 | "TARGET_POWER && reload_completed" | |
12073 | [(parallel [(set (match_dup 0) | |
12074 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12075 | (clobber (match_dup 4))]) | |
12076 | (set (match_dup 5) | |
12077 | (compare:CC (match_dup 0) | |
12078 | (const_int 0)))] | |
12079 | "") | |
1fd4e8c1 RK |
12080 | |
12081 | (define_insn "" | |
cd2b37d9 RK |
12082 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12083 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12084 | (const_int 0))))] |
f9562f27 | 12085 | "! TARGET_POWERPC64" |
ca7f5001 | 12086 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 12087 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12088 | |
f9562f27 DE |
12089 | (define_insn "" |
12090 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12091 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12092 | (const_int 0))))] | |
12093 | "TARGET_POWERPC64" | |
12094 | "subfic %0,%1,0\;addme %0,%0\;sradi} %0,%0,63" | |
12095 | [(set_attr "length" "12")]) | |
12096 | ||
1fd4e8c1 | 12097 | (define_insn "" |
cd2b37d9 RK |
12098 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12099 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12100 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
12101 | "TARGET_POWER" |
12102 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12103 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12104 | |
12105 | (define_insn "" | |
cd2b37d9 RK |
12106 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12107 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12108 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 12109 | "! TARGET_POWERPC64" |
ca7f5001 | 12110 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 12111 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12112 | |
f9562f27 DE |
12113 | (define_insn "" |
12114 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12115 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12116 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
12117 | "TARGET_POWERPC64" | |
12118 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0" | |
12119 | [(set_attr "length" "12")]) | |
12120 | ||
1fd4e8c1 | 12121 | (define_insn "" |
9ebbca7d | 12122 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12123 | (compare:CC |
9ebbca7d GK |
12124 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12125 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12126 | (const_int 0))) |
9ebbca7d | 12127 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12128 | (gtu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 12129 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12130 | "@ |
12131 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
12132 | #" | |
b19003d8 | 12133 | [(set_attr "type" "compare") |
9ebbca7d GK |
12134 | (set_attr "length" "12,16")]) |
12135 | ||
12136 | (define_split | |
12137 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12138 | (compare:CC | |
12139 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12140 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12141 | (const_int 0))) | |
12142 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12143 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
12144 | "! TARGET_POWERPC64 && reload_completed" | |
12145 | [(set (match_dup 0) | |
12146 | (gtu:SI (match_dup 1) (match_dup 2))) | |
12147 | (set (match_dup 3) | |
12148 | (compare:CC (match_dup 0) | |
12149 | (const_int 0)))] | |
12150 | "") | |
1fd4e8c1 | 12151 | |
f9562f27 | 12152 | (define_insn "" |
9ebbca7d | 12153 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12154 | (compare:CC |
9ebbca7d GK |
12155 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12156 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 12157 | (const_int 0))) |
9ebbca7d | 12158 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
12159 | (gtu:DI (match_dup 1) (match_dup 2)))] |
12160 | "TARGET_POWERPC64" | |
9ebbca7d GK |
12161 | "@ |
12162 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
12163 | #" | |
f9562f27 | 12164 | [(set_attr "type" "compare") |
9ebbca7d GK |
12165 | (set_attr "length" "12,16")]) |
12166 | ||
12167 | (define_split | |
12168 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12169 | (compare:CC | |
12170 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12171 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12172 | (const_int 0))) | |
12173 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12174 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
12175 | "TARGET_POWERPC64 && reload_completed" | |
12176 | [(set (match_dup 0) | |
12177 | (gtu:DI (match_dup 1) (match_dup 2))) | |
12178 | (set (match_dup 3) | |
12179 | (compare:CC (match_dup 0) | |
12180 | (const_int 0)))] | |
12181 | "") | |
f9562f27 | 12182 | |
1fd4e8c1 | 12183 | (define_insn "" |
19378cf8 MM |
12184 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12185 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12186 | (match_operand:SI 2 "reg_or_short_operand" "I,rI")) | |
12187 | (match_operand:SI 3 "reg_or_short_operand" "r,rI"))) | |
12188 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
f9562f27 | 12189 | "! TARGET_POWERPC64" |
00751805 | 12190 | "@ |
ca7f5001 | 12191 | {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3 |
ca7f5001 | 12192 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
19378cf8 | 12193 | [(set_attr "length" "8,12")]) |
1fd4e8c1 | 12194 | |
f9562f27 DE |
12195 | (define_insn "" |
12196 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12197 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12198 | (match_operand:DI 2 "reg_or_short_operand" "I,rI")) | |
12199 | (match_operand:DI 3 "reg_or_short_operand" "r,rI"))) | |
12200 | (clobber (match_scratch:DI 4 "=&r,&r"))] | |
12201 | "TARGET_POWERPC64" | |
12202 | "@ | |
12203 | addic %4,%1,%k2\;addze %0,%3 | |
12204 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3" | |
12205 | [(set_attr "length" "8,12")]) | |
12206 | ||
1fd4e8c1 | 12207 | (define_insn "" |
9ebbca7d | 12208 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12209 | (compare:CC |
9ebbca7d GK |
12210 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12211 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
12212 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12213 | (const_int 0))) |
9ebbca7d | 12214 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12215 | "! TARGET_POWERPC64" |
00751805 | 12216 | "@ |
19378cf8 | 12217 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12218 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
12219 | # | |
12220 | #" | |
b19003d8 | 12221 | [(set_attr "type" "compare") |
9ebbca7d GK |
12222 | (set_attr "length" "8,12,12,16")]) |
12223 | ||
12224 | (define_split | |
12225 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12226 | (compare:CC | |
12227 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12228 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12229 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12230 | (const_int 0))) | |
12231 | (clobber (match_scratch:SI 4 ""))] | |
12232 | "! TARGET_POWERPC64 && reload_completed" | |
12233 | [(set (match_dup 4) | |
12234 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
12235 | (match_dup 3))) | |
12236 | (set (match_dup 0) | |
12237 | (compare:CC (match_dup 4) | |
12238 | (const_int 0)))] | |
12239 | "") | |
1fd4e8c1 | 12240 | |
f9562f27 | 12241 | (define_insn "" |
9ebbca7d | 12242 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12243 | (compare:CC |
9ebbca7d GK |
12244 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12245 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
12246 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 12247 | (const_int 0))) |
9ebbca7d | 12248 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
12249 | "TARGET_POWERPC64" |
12250 | "@ | |
12251 | addic %4,%1,%k2\;addze. %4,%3 | |
9ebbca7d GK |
12252 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3 |
12253 | # | |
12254 | #" | |
f9562f27 | 12255 | [(set_attr "type" "compare") |
9ebbca7d GK |
12256 | (set_attr "length" "8,12,12,16")]) |
12257 | ||
12258 | (define_split | |
12259 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12260 | (compare:CC | |
12261 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12262 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12263 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
12264 | (const_int 0))) | |
12265 | (clobber (match_scratch:DI 4 ""))] | |
12266 | "TARGET_POWERPC64 && reload_completed" | |
12267 | [(set (match_dup 4) | |
12268 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
12269 | (match_dup 3))) | |
12270 | (set (match_dup 0) | |
12271 | (compare:CC (match_dup 4) | |
12272 | (const_int 0)))] | |
12273 | "") | |
f9562f27 | 12274 | |
1fd4e8c1 | 12275 | (define_insn "" |
9ebbca7d | 12276 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12277 | (compare:CC |
9ebbca7d GK |
12278 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12279 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
12280 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12281 | (const_int 0))) |
9ebbca7d | 12282 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12283 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12284 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12285 | "! TARGET_POWERPC64" |
00751805 | 12286 | "@ |
ca7f5001 | 12287 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
12288 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
12289 | # | |
12290 | #" | |
b19003d8 | 12291 | [(set_attr "type" "compare") |
9ebbca7d GK |
12292 | (set_attr "length" "8,12,12,16")]) |
12293 | ||
12294 | (define_split | |
12295 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12296 | (compare:CC | |
12297 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12298 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12299 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12300 | (const_int 0))) | |
12301 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12302 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12303 | (clobber (match_scratch:SI 4 ""))] | |
12304 | "! TARGET_POWERPC64 && reload_completed" | |
12305 | [(parallel [(set (match_dup 0) | |
12306 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12307 | (clobber (match_dup 4))]) | |
12308 | (set (match_dup 5) | |
12309 | (compare:CC (match_dup 0) | |
12310 | (const_int 0)))] | |
12311 | "") | |
1fd4e8c1 | 12312 | |
f9562f27 | 12313 | (define_insn "" |
9ebbca7d | 12314 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12315 | (compare:CC |
9ebbca7d GK |
12316 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12317 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
12318 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 12319 | (const_int 0))) |
9ebbca7d | 12320 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 | 12321 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12322 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
12323 | "TARGET_POWERPC64" |
12324 | "@ | |
12325 | addic %4,%1,%k2\;addze. %0,%3 | |
9ebbca7d GK |
12326 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3 |
12327 | # | |
12328 | #" | |
f9562f27 | 12329 | [(set_attr "type" "compare") |
9ebbca7d GK |
12330 | (set_attr "length" "8,12,12,16")]) |
12331 | ||
12332 | (define_split | |
12333 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12334 | (compare:CC | |
12335 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12336 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12337 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
12338 | (const_int 0))) | |
12339 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12340 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12341 | (clobber (match_scratch:DI 4 ""))] | |
12342 | "TARGET_POWERPC64 && reload_completed" | |
12343 | [(parallel [(set (match_dup 0) | |
12344 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12345 | (clobber (match_dup 4))]) | |
12346 | (set (match_dup 5) | |
12347 | (compare:CC (match_dup 0) | |
12348 | (const_int 0)))] | |
12349 | "") | |
f9562f27 | 12350 | |
1fd4e8c1 | 12351 | (define_insn "" |
cd2b37d9 RK |
12352 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12353 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12354 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 12355 | "! TARGET_POWERPC64" |
ca7f5001 | 12356 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 12357 | [(set_attr "length" "8")]) |
f9562f27 DE |
12358 | |
12359 | (define_insn "" | |
12360 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12361 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12362 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
12363 | "TARGET_POWERPC64" | |
12364 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" | |
12365 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
12366 | \f |
12367 | ;; Define both directions of branch and return. If we need a reload | |
12368 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
12369 | ;; register CC value to there. | |
12370 | ||
12371 | (define_insn "" | |
12372 | [(set (pc) | |
12373 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
12374 | [(match_operand 2 | |
12375 | "cc_reg_operand" "x,?y") | |
12376 | (const_int 0)]) | |
12377 | (label_ref (match_operand 0 "" "")) | |
12378 | (pc)))] | |
12379 | "" | |
b19003d8 RK |
12380 | "* |
12381 | { | |
12a4e8c5 | 12382 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
12383 | }" |
12384 | [(set_attr "type" "branch")]) | |
12385 | ||
1fd4e8c1 RK |
12386 | (define_insn "" |
12387 | [(set (pc) | |
12388 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
12389 | [(match_operand 1 | |
12390 | "cc_reg_operand" "x,?y") | |
12391 | (const_int 0)]) | |
12392 | (return) | |
12393 | (pc)))] | |
12394 | "direct_return ()" | |
12a4e8c5 GK |
12395 | "* |
12396 | { | |
12397 | return output_cbranch (operands[0], NULL, 0, insn); | |
12398 | }" | |
b7ff3d82 | 12399 | [(set_attr "type" "branch") |
39a10a29 | 12400 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
12401 | |
12402 | (define_insn "" | |
12403 | [(set (pc) | |
12404 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
12405 | [(match_operand 2 | |
12406 | "cc_reg_operand" "x,?y") | |
12407 | (const_int 0)]) | |
12408 | (pc) | |
12409 | (label_ref (match_operand 0 "" ""))))] | |
12410 | "" | |
b19003d8 RK |
12411 | "* |
12412 | { | |
12a4e8c5 | 12413 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
12414 | }" |
12415 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
12416 | |
12417 | (define_insn "" | |
12418 | [(set (pc) | |
12419 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
12420 | [(match_operand 1 | |
12421 | "cc_reg_operand" "x,?y") | |
12422 | (const_int 0)]) | |
12423 | (pc) | |
12424 | (return)))] | |
12425 | "direct_return ()" | |
12a4e8c5 GK |
12426 | "* |
12427 | { | |
12428 | return output_cbranch (operands[0], NULL, 1, insn); | |
12429 | }" | |
b7ff3d82 | 12430 | [(set_attr "type" "branch") |
39a10a29 GK |
12431 | (set_attr "length" "4")]) |
12432 | ||
12433 | ;; Logic on condition register values. | |
12434 | ||
12435 | ; This pattern matches things like | |
12436 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
12437 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
12438 | ; (const_int 1))) | |
12439 | ; which are generated by the branch logic. | |
12440 | ||
12441 | (define_insn "" | |
12442 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12443 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" | |
12444 | [(match_operator:SI 2 | |
12445 | "branch_positive_comparison_operator" | |
12446 | [(match_operand 3 | |
12447 | "cc_reg_operand" "y") | |
12448 | (const_int 0)]) | |
12449 | (match_operator:SI 4 | |
12450 | "branch_positive_comparison_operator" | |
12451 | [(match_operand 5 | |
12452 | "cc_reg_operand" "y") | |
12453 | (const_int 0)])]) | |
12454 | (const_int 1)))] | |
12455 | "" | |
12456 | "cr%q1 %E0,%j2,%j4" | |
12457 | [(set_attr "type" "cr_logical")]) | |
12458 | ||
12459 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
12460 | ; Because ~1 has all but the low bit set. | |
12461 | (define_insn "" | |
12462 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12463 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" | |
12464 | [(not:SI (match_operator:SI 2 | |
12465 | "branch_positive_comparison_operator" | |
12466 | [(match_operand 3 | |
12467 | "cc_reg_operand" "y") | |
12468 | (const_int 0)])) | |
12469 | (match_operator:SI 4 | |
12470 | "branch_positive_comparison_operator" | |
12471 | [(match_operand 5 | |
12472 | "cc_reg_operand" "y") | |
12473 | (const_int 0)])]) | |
12474 | (const_int -1)))] | |
12475 | "" | |
12476 | "cr%q1 %E0,%j2,%j4" | |
12477 | [(set_attr "type" "cr_logical")]) | |
12478 | ||
12479 | (define_insn "" | |
12480 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
6c873122 | 12481 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 12482 | "branch_positive_comparison_operator" |
6c873122 | 12483 | [(match_operand 2 |
39a10a29 GK |
12484 | "cc_reg_operand" "y") |
12485 | (const_int 0)]) | |
12486 | (const_int 0)))] | |
12487 | "" | |
251b3667 | 12488 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
39a10a29 GK |
12489 | [(set_attr "type" "cr_logical")]) |
12490 | ||
12491 | ;; If we are comparing the result of two comparisons, this can be done | |
12492 | ;; using creqv or crxor. | |
12493 | ||
12494 | (define_insn_and_split "" | |
12495 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
12496 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
12497 | [(match_operand 2 "cc_reg_operand" "y") | |
12498 | (const_int 0)]) | |
12499 | (match_operator 3 "branch_comparison_operator" | |
12500 | [(match_operand 4 "cc_reg_operand" "y") | |
12501 | (const_int 0)])))] | |
12502 | "" | |
12503 | "#" | |
12504 | "" | |
12505 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
12506 | (match_dup 5)))] | |
12507 | " | |
12508 | { | |
12509 | int positive_1, positive_2; | |
12510 | ||
12511 | positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode); | |
12512 | positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode); | |
12513 | ||
12514 | if (! positive_1) | |
12515 | operands[1] = gen_rtx (SImode, | |
12516 | rs6000_reverse_condition (GET_MODE (operands[2]), | |
12517 | GET_CODE (operands[1])), | |
12518 | operands[2]); | |
12519 | else if (GET_MODE (operands[1]) != SImode) | |
12520 | operands[1] = gen_rtx (SImode, | |
12521 | GET_CODE (operands[1]), | |
12522 | operands[2]); | |
12523 | ||
12524 | if (! positive_2) | |
12525 | operands[3] = gen_rtx (SImode, | |
12526 | rs6000_reverse_condition (GET_MODE (operands[4]), | |
12527 | GET_CODE (operands[3])), | |
12528 | operands[4]); | |
12529 | else if (GET_MODE (operands[3]) != SImode) | |
12530 | operands[3] = gen_rtx (SImode, | |
12531 | GET_CODE (operands[3]), | |
12532 | operands[4]); | |
12533 | ||
12534 | if (positive_1 == positive_2) | |
251b3667 DE |
12535 | { |
12536 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
12537 | operands[5] = constm1_rtx; | |
12538 | } | |
12539 | else | |
12540 | { | |
12541 | operands[5] = const1_rtx; | |
12542 | } | |
39a10a29 | 12543 | }") |
1fd4e8c1 RK |
12544 | |
12545 | ;; Unconditional branch and return. | |
12546 | ||
12547 | (define_insn "jump" | |
12548 | [(set (pc) | |
12549 | (label_ref (match_operand 0 "" "")))] | |
12550 | "" | |
b7ff3d82 DE |
12551 | "b %l0" |
12552 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
12553 | |
12554 | (define_insn "return" | |
12555 | [(return)] | |
12556 | "direct_return ()" | |
324e52cc TG |
12557 | "{br|blr}" |
12558 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 12559 | |
0ad91047 DE |
12560 | (define_expand "indirect_jump" |
12561 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 12562 | "" |
0ad91047 DE |
12563 | " |
12564 | { | |
12565 | if (TARGET_32BIT) | |
12566 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
12567 | else | |
12568 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
12569 | DONE; | |
12570 | }") | |
12571 | ||
12572 | (define_insn "indirect_jumpsi" | |
cccf3bdc | 12573 | [(set (pc) (match_operand:SI 0 "register_operand" "cl"))] |
0ad91047 | 12574 | "TARGET_32BIT" |
cccf3bdc | 12575 | "b%T0" |
324e52cc | 12576 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 12577 | |
0ad91047 | 12578 | (define_insn "indirect_jumpdi" |
cccf3bdc | 12579 | [(set (pc) (match_operand:DI 0 "register_operand" "cl"))] |
0ad91047 | 12580 | "TARGET_64BIT" |
cccf3bdc | 12581 | "b%T0" |
266eb58a DE |
12582 | [(set_attr "type" "jmpreg")]) |
12583 | ||
1fd4e8c1 RK |
12584 | ;; Table jump for switch statements: |
12585 | (define_expand "tablejump" | |
e6ca2c17 DE |
12586 | [(use (match_operand 0 "" "")) |
12587 | (use (label_ref (match_operand 1 "" "")))] | |
12588 | "" | |
12589 | " | |
12590 | { | |
12591 | if (TARGET_32BIT) | |
12592 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
12593 | else | |
12594 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
12595 | DONE; | |
12596 | }") | |
12597 | ||
12598 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
12599 | [(set (match_dup 3) |
12600 | (plus:SI (match_operand:SI 0 "" "") | |
12601 | (match_dup 2))) | |
12602 | (parallel [(set (pc) (match_dup 3)) | |
12603 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 12604 | "TARGET_32BIT" |
1fd4e8c1 RK |
12605 | " |
12606 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 12607 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
12608 | operands[3] = gen_reg_rtx (SImode); |
12609 | }") | |
12610 | ||
e6ca2c17 | 12611 | (define_expand "tablejumpdi" |
9ebbca7d GK |
12612 | [(set (match_dup 4) |
12613 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) | |
12614 | (set (match_dup 3) | |
12615 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
12616 | (match_dup 2))) |
12617 | (parallel [(set (pc) (match_dup 3)) | |
12618 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 12619 | "TARGET_64BIT" |
e6ca2c17 | 12620 | " |
9ebbca7d | 12621 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 12622 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 12623 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
12624 | }") |
12625 | ||
1fd4e8c1 RK |
12626 | (define_insn "" |
12627 | [(set (pc) | |
cccf3bdc | 12628 | (match_operand:SI 0 "register_operand" "cl")) |
1fd4e8c1 | 12629 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 12630 | "TARGET_32BIT" |
cccf3bdc | 12631 | "b%T0" |
a6845123 | 12632 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 12633 | |
266eb58a DE |
12634 | (define_insn "" |
12635 | [(set (pc) | |
cccf3bdc | 12636 | (match_operand:DI 0 "register_operand" "cl")) |
266eb58a | 12637 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 12638 | "TARGET_64BIT" |
cccf3bdc | 12639 | "b%T0" |
266eb58a DE |
12640 | [(set_attr "type" "jmpreg")]) |
12641 | ||
1fd4e8c1 RK |
12642 | (define_insn "nop" |
12643 | [(const_int 0)] | |
12644 | "" | |
ca7f5001 | 12645 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 12646 | \f |
7e69e155 | 12647 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
12648 | ;; so loop.c knows what to generate. |
12649 | ||
5527bf14 RH |
12650 | (define_expand "doloop_end" |
12651 | [(use (match_operand 0 "" "")) ; loop pseudo | |
12652 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
12653 | (use (match_operand 2 "" "")) ; max iterations | |
12654 | (use (match_operand 3 "" "")) ; loop level | |
12655 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
12656 | "" |
12657 | " | |
12658 | { | |
5527bf14 RH |
12659 | /* Only use this on innermost loops. */ |
12660 | if (INTVAL (operands[3]) > 1) | |
12661 | FAIL; | |
0ad91047 | 12662 | if (TARGET_POWERPC64) |
5527bf14 RH |
12663 | { |
12664 | if (GET_MODE (operands[0]) != DImode) | |
12665 | FAIL; | |
12666 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
12667 | } | |
0ad91047 | 12668 | else |
5527bf14 RH |
12669 | { |
12670 | if (GET_MODE (operands[0]) != SImode) | |
12671 | FAIL; | |
12672 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
12673 | } | |
0ad91047 DE |
12674 | DONE; |
12675 | }") | |
12676 | ||
12677 | (define_expand "ctrsi" | |
3cb999d8 DE |
12678 | [(parallel [(set (pc) |
12679 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
12680 | (const_int 1)) | |
12681 | (label_ref (match_operand 1 "" "")) | |
12682 | (pc))) | |
b6c9286a MM |
12683 | (set (match_dup 0) |
12684 | (plus:SI (match_dup 0) | |
12685 | (const_int -1))) | |
5f81043f RK |
12686 | (clobber (match_scratch:CC 2 "")) |
12687 | (clobber (match_scratch:SI 3 ""))])] | |
0ad91047 DE |
12688 | "! TARGET_POWERPC64" |
12689 | "") | |
12690 | ||
12691 | (define_expand "ctrdi" | |
3cb999d8 DE |
12692 | [(parallel [(set (pc) |
12693 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
12694 | (const_int 1)) | |
12695 | (label_ref (match_operand 1 "" "")) | |
12696 | (pc))) | |
0ad91047 DE |
12697 | (set (match_dup 0) |
12698 | (plus:DI (match_dup 0) | |
12699 | (const_int -1))) | |
12700 | (clobber (match_scratch:CC 2 "")) | |
12701 | (clobber (match_scratch:DI 3 ""))])] | |
12702 | "TARGET_POWERPC64" | |
c225ba7b RK |
12703 | "") |
12704 | ||
1fd4e8c1 RK |
12705 | ;; We need to be able to do this for any operand, including MEM, or we |
12706 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 12707 | ;; JUMP_INSNs. |
0ad91047 | 12708 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
12709 | ;; label MUST be operand 0. |
12710 | ||
0ad91047 | 12711 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 12712 | [(set (pc) |
5f81043f | 12713 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 12714 | (const_int 1)) |
a6845123 | 12715 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 12716 | (pc))) |
5f81043f RK |
12717 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
12718 | (plus:SI (match_dup 1) | |
12719 | (const_int -1))) | |
1fd4e8c1 RK |
12720 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
12721 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 12722 | "! TARGET_POWERPC64" |
b19003d8 RK |
12723 | "* |
12724 | { | |
af87a13e | 12725 | if (which_alternative != 0) |
b19003d8 | 12726 | return \"#\"; |
856a6884 | 12727 | else if (get_attr_length (insn) == 4) |
a6845123 | 12728 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 12729 | else |
c81bebd7 | 12730 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 12731 | }" |
baf97f86 RK |
12732 | [(set_attr "type" "branch") |
12733 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 12734 | |
0ad91047 | 12735 | (define_insn "*ctrsi_internal2" |
5f81043f RK |
12736 | [(set (pc) |
12737 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") | |
12738 | (const_int 1)) | |
12739 | (pc) | |
12740 | (label_ref (match_operand 0 "" "")))) | |
12741 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
12742 | (plus:SI (match_dup 1) | |
12743 | (const_int -1))) | |
12744 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12745 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
12746 | "! TARGET_POWERPC64" |
12747 | "* | |
12748 | { | |
12749 | if (which_alternative != 0) | |
12750 | return \"#\"; | |
856a6884 | 12751 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12752 | return \"bdz %l0\"; |
12753 | else | |
12754 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
12755 | }" | |
12756 | [(set_attr "type" "branch") | |
12757 | (set_attr "length" "*,12,16")]) | |
12758 | ||
12759 | (define_insn "*ctrdi_internal1" | |
12760 | [(set (pc) | |
12761 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12762 | (const_int 1)) | |
12763 | (label_ref (match_operand 0 "" "")) | |
12764 | (pc))) | |
12765 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12766 | (plus:DI (match_dup 1) | |
12767 | (const_int -1))) | |
12768 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12769 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12770 | "TARGET_POWERPC64" | |
12771 | "* | |
12772 | { | |
12773 | if (which_alternative != 0) | |
12774 | return \"#\"; | |
856a6884 | 12775 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12776 | return \"{bdn|bdnz} %l0\"; |
12777 | else | |
12778 | return \"bdz %$+8\;b %l0\"; | |
12779 | }" | |
12780 | [(set_attr "type" "branch") | |
12781 | (set_attr "length" "*,12,16")]) | |
12782 | ||
12783 | (define_insn "*ctrdi_internal2" | |
12784 | [(set (pc) | |
12785 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12786 | (const_int 1)) | |
12787 | (pc) | |
12788 | (label_ref (match_operand 0 "" "")))) | |
12789 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12790 | (plus:DI (match_dup 1) | |
12791 | (const_int -1))) | |
12792 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12793 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12794 | "TARGET_POWERPC64" | |
5f81043f RK |
12795 | "* |
12796 | { | |
12797 | if (which_alternative != 0) | |
12798 | return \"#\"; | |
856a6884 | 12799 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
12800 | return \"bdz %l0\"; |
12801 | else | |
c81bebd7 | 12802 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
12803 | }" |
12804 | [(set_attr "type" "branch") | |
12805 | (set_attr "length" "*,12,16")]) | |
12806 | ||
c225ba7b | 12807 | ;; Similar, but we can use GE since we have a REG_NONNEG. |
0ad91047 DE |
12808 | |
12809 | (define_insn "*ctrsi_internal3" | |
1fd4e8c1 | 12810 | [(set (pc) |
5f81043f | 12811 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 12812 | (const_int 0)) |
a6845123 | 12813 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 12814 | (pc))) |
5f81043f RK |
12815 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
12816 | (plus:SI (match_dup 1) | |
12817 | (const_int -1))) | |
1fd4e8c1 RK |
12818 | (clobber (match_scratch:CC 3 "=X,&x,&X")) |
12819 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 12820 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
b19003d8 RK |
12821 | "* |
12822 | { | |
af87a13e | 12823 | if (which_alternative != 0) |
b19003d8 | 12824 | return \"#\"; |
856a6884 | 12825 | else if (get_attr_length (insn) == 4) |
a6845123 | 12826 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 12827 | else |
c81bebd7 | 12828 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 12829 | }" |
baf97f86 RK |
12830 | [(set_attr "type" "branch") |
12831 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 12832 | |
0ad91047 | 12833 | (define_insn "*ctrsi_internal4" |
1fd4e8c1 | 12834 | [(set (pc) |
5f81043f RK |
12835 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
12836 | (const_int 0)) | |
12837 | (pc) | |
12838 | (label_ref (match_operand 0 "" "")))) | |
12839 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
12840 | (plus:SI (match_dup 1) | |
12841 | (const_int -1))) | |
12842 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
12843 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 12844 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
5f81043f RK |
12845 | "* |
12846 | { | |
12847 | if (which_alternative != 0) | |
12848 | return \"#\"; | |
856a6884 | 12849 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
12850 | return \"bdz %l0\"; |
12851 | else | |
c81bebd7 | 12852 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
12853 | }" |
12854 | [(set_attr "type" "branch") | |
12855 | (set_attr "length" "*,12,16")]) | |
12856 | ||
0ad91047 DE |
12857 | (define_insn "*ctrdi_internal3" |
12858 | [(set (pc) | |
12859 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12860 | (const_int 0)) | |
12861 | (label_ref (match_operand 0 "" "")) | |
12862 | (pc))) | |
12863 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12864 | (plus:DI (match_dup 1) | |
12865 | (const_int -1))) | |
12866 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
12867 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12868 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" | |
12869 | "* | |
12870 | { | |
12871 | if (which_alternative != 0) | |
12872 | return \"#\"; | |
856a6884 | 12873 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12874 | return \"{bdn|bdnz} %l0\"; |
12875 | else | |
12876 | return \"bdz %$+8\;b %l0\"; | |
12877 | }" | |
12878 | [(set_attr "type" "branch") | |
12879 | (set_attr "length" "*,12,16")]) | |
12880 | ||
12881 | (define_insn "*ctrdi_internal4" | |
12882 | [(set (pc) | |
12883 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12884 | (const_int 0)) | |
12885 | (pc) | |
12886 | (label_ref (match_operand 0 "" "")))) | |
12887 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12888 | (plus:DI (match_dup 1) | |
12889 | (const_int -1))) | |
12890 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
12891 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12892 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" | |
12893 | "* | |
12894 | { | |
12895 | if (which_alternative != 0) | |
12896 | return \"#\"; | |
856a6884 | 12897 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12898 | return \"bdz %l0\"; |
12899 | else | |
12900 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
12901 | }" | |
12902 | [(set_attr "type" "branch") | |
12903 | (set_attr "length" "*,12,16")]) | |
12904 | ||
12905 | ;; Similar but use EQ | |
12906 | ||
12907 | (define_insn "*ctrsi_internal5" | |
5f81043f RK |
12908 | [(set (pc) |
12909 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
1fd4e8c1 | 12910 | (const_int 1)) |
a6845123 | 12911 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 12912 | (pc))) |
5f81043f RK |
12913 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
12914 | (plus:SI (match_dup 1) | |
12915 | (const_int -1))) | |
1fd4e8c1 RK |
12916 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
12917 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 12918 | "! TARGET_POWERPC64" |
b19003d8 RK |
12919 | "* |
12920 | { | |
af87a13e | 12921 | if (which_alternative != 0) |
b19003d8 | 12922 | return \"#\"; |
856a6884 | 12923 | else if (get_attr_length (insn) == 4) |
a6845123 | 12924 | return \"bdz %l0\"; |
b19003d8 | 12925 | else |
c81bebd7 | 12926 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
b19003d8 | 12927 | }" |
baf97f86 RK |
12928 | [(set_attr "type" "branch") |
12929 | (set_attr "length" "*,12,16")]) | |
1fd4e8c1 | 12930 | |
0ad91047 | 12931 | (define_insn "*ctrsi_internal6" |
5f81043f RK |
12932 | [(set (pc) |
12933 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
12934 | (const_int 1)) | |
12935 | (pc) | |
12936 | (label_ref (match_operand 0 "" "")))) | |
12937 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
12938 | (plus:SI (match_dup 1) | |
12939 | (const_int -1))) | |
12940 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12941 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
12942 | "! TARGET_POWERPC64" |
12943 | "* | |
12944 | { | |
12945 | if (which_alternative != 0) | |
12946 | return \"#\"; | |
856a6884 | 12947 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12948 | return \"{bdn|bdnz} %l0\"; |
12949 | else | |
12950 | return \"bdz %$+8\;b %l0\"; | |
12951 | }" | |
12952 | [(set_attr "type" "branch") | |
12953 | (set_attr "length" "*,12,16")]) | |
12954 | ||
12955 | (define_insn "*ctrdi_internal5" | |
12956 | [(set (pc) | |
12957 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12958 | (const_int 1)) | |
12959 | (label_ref (match_operand 0 "" "")) | |
12960 | (pc))) | |
12961 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12962 | (plus:DI (match_dup 1) | |
12963 | (const_int -1))) | |
12964 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12965 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12966 | "TARGET_POWERPC64" | |
12967 | "* | |
12968 | { | |
12969 | if (which_alternative != 0) | |
12970 | return \"#\"; | |
856a6884 | 12971 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
12972 | return \"bdz %l0\"; |
12973 | else | |
12974 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
12975 | }" | |
12976 | [(set_attr "type" "branch") | |
12977 | (set_attr "length" "*,12,16")]) | |
12978 | ||
12979 | (define_insn "*ctrdi_internal6" | |
12980 | [(set (pc) | |
12981 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") | |
12982 | (const_int 1)) | |
12983 | (pc) | |
12984 | (label_ref (match_operand 0 "" "")))) | |
12985 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
12986 | (plus:DI (match_dup 1) | |
12987 | (const_int -1))) | |
12988 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
12989 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
12990 | "TARGET_POWERPC64" | |
5f81043f RK |
12991 | "* |
12992 | { | |
12993 | if (which_alternative != 0) | |
12994 | return \"#\"; | |
856a6884 | 12995 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
12996 | return \"{bdn|bdnz} %l0\"; |
12997 | else | |
c81bebd7 | 12998 | return \"bdz %$+8\;b %l0\"; |
5f81043f RK |
12999 | }" |
13000 | [(set_attr "type" "branch") | |
13001 | (set_attr "length" "*,12,16")]) | |
13002 | ||
0ad91047 DE |
13003 | ;; Now the splitters if we could not allocate the CTR register |
13004 | ||
1fd4e8c1 RK |
13005 | (define_split |
13006 | [(set (pc) | |
13007 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 13008 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
13009 | (const_int 1)]) |
13010 | (match_operand 5 "" "") | |
13011 | (match_operand 6 "" ""))) | |
cd2b37d9 | 13012 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
13013 | (plus:SI (match_dup 1) |
13014 | (const_int -1))) | |
1fd4e8c1 RK |
13015 | (clobber (match_scratch:CC 3 "")) |
13016 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 | 13017 | "! TARGET_POWERPC64 && reload_completed" |
1fd4e8c1 | 13018 | [(parallel [(set (match_dup 3) |
5f81043f RK |
13019 | (compare:CC (plus:SI (match_dup 1) |
13020 | (const_int -1)) | |
1fd4e8c1 | 13021 | (const_int 0))) |
5f81043f RK |
13022 | (set (match_dup 0) |
13023 | (plus:SI (match_dup 1) | |
13024 | (const_int -1)))]) | |
13025 | (set (pc) (if_then_else (match_dup 7) | |
13026 | (match_dup 5) | |
13027 | (match_dup 6)))] | |
1fd4e8c1 RK |
13028 | " |
13029 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13030 | const0_rtx); }") | |
13031 | ||
13032 | (define_split | |
13033 | [(set (pc) | |
13034 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 13035 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
13036 | (const_int 1)]) |
13037 | (match_operand 5 "" "") | |
13038 | (match_operand 6 "" ""))) | |
9ebbca7d | 13039 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
13040 | (plus:SI (match_dup 1) (const_int -1))) |
13041 | (clobber (match_scratch:CC 3 "")) | |
13042 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 DE |
13043 | "! TARGET_POWERPC64 && reload_completed |
13044 | && ! gpc_reg_operand (operands[0], SImode)" | |
1fd4e8c1 | 13045 | [(parallel [(set (match_dup 3) |
5f81043f RK |
13046 | (compare:CC (plus:SI (match_dup 1) |
13047 | (const_int -1)) | |
1fd4e8c1 | 13048 | (const_int 0))) |
5f81043f RK |
13049 | (set (match_dup 4) |
13050 | (plus:SI (match_dup 1) | |
13051 | (const_int -1)))]) | |
13052 | (set (match_dup 0) | |
13053 | (match_dup 4)) | |
13054 | (set (pc) (if_then_else (match_dup 7) | |
13055 | (match_dup 5) | |
13056 | (match_dup 6)))] | |
1fd4e8c1 RK |
13057 | " |
13058 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13059 | const0_rtx); }") | |
0ad91047 DE |
13060 | (define_split |
13061 | [(set (pc) | |
13062 | (if_then_else (match_operator 2 "comparison_operator" | |
13063 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
13064 | (const_int 1)]) | |
13065 | (match_operand 5 "" "") | |
13066 | (match_operand 6 "" ""))) | |
13067 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13068 | (plus:DI (match_dup 1) | |
13069 | (const_int -1))) | |
13070 | (clobber (match_scratch:CC 3 "")) | |
13071 | (clobber (match_scratch:DI 4 ""))] | |
13072 | "TARGET_POWERPC64 && reload_completed" | |
13073 | [(parallel [(set (match_dup 3) | |
13074 | (compare:CC (plus:DI (match_dup 1) | |
13075 | (const_int -1)) | |
13076 | (const_int 0))) | |
13077 | (set (match_dup 0) | |
13078 | (plus:DI (match_dup 1) | |
13079 | (const_int -1)))]) | |
13080 | (set (pc) (if_then_else (match_dup 7) | |
13081 | (match_dup 5) | |
13082 | (match_dup 6)))] | |
13083 | " | |
13084 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13085 | const0_rtx); }") | |
13086 | ||
13087 | (define_split | |
13088 | [(set (pc) | |
13089 | (if_then_else (match_operator 2 "comparison_operator" | |
13090 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
13091 | (const_int 1)]) | |
13092 | (match_operand 5 "" "") | |
13093 | (match_operand 6 "" ""))) | |
9ebbca7d | 13094 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
13095 | (plus:DI (match_dup 1) (const_int -1))) |
13096 | (clobber (match_scratch:CC 3 "")) | |
13097 | (clobber (match_scratch:DI 4 ""))] | |
13098 | "TARGET_POWERPC64 && reload_completed | |
13099 | && ! gpc_reg_operand (operands[0], DImode)" | |
13100 | [(parallel [(set (match_dup 3) | |
13101 | (compare:CC (plus:DI (match_dup 1) | |
13102 | (const_int -1)) | |
13103 | (const_int 0))) | |
13104 | (set (match_dup 4) | |
13105 | (plus:DI (match_dup 1) | |
13106 | (const_int -1)))]) | |
13107 | (set (match_dup 0) | |
13108 | (match_dup 4)) | |
13109 | (set (pc) (if_then_else (match_dup 7) | |
13110 | (match_dup 5) | |
13111 | (match_dup 6)))] | |
13112 | " | |
13113 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13114 | const0_rtx); }") | |
e0cd0770 JC |
13115 | \f |
13116 | (define_insn "trap" | |
13117 | [(trap_if (const_int 1) (const_int 0))] | |
13118 | "" | |
13119 | "{t 31,0,0|trap}") | |
13120 | ||
13121 | (define_expand "conditional_trap" | |
13122 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
13123 | [(match_dup 2) (match_dup 3)]) | |
13124 | (match_operand 1 "const_int_operand" ""))] | |
13125 | "" | |
13126 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
13127 | operands[2] = rs6000_compare_op0; | |
13128 | operands[3] = rs6000_compare_op1;") | |
13129 | ||
13130 | (define_insn "" | |
13131 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
13132 | [(match_operand:SI 1 "register_operand" "r") | |
13133 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
13134 | (const_int 0))] | |
13135 | "" | |
a157febd GK |
13136 | "{t|tw}%V0%I2 %1,%2") |
13137 | ||
13138 | (define_insn "" | |
13139 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
13140 | [(match_operand:DI 1 "register_operand" "r") | |
13141 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
13142 | (const_int 0))] | |
13143 | "TARGET_POWERPC64" | |
13144 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
13145 | \f |
13146 | ;; Insns related to generating the function prologue and epilogue. | |
13147 | ||
13148 | (define_expand "prologue" | |
13149 | [(use (const_int 0))] | |
13150 | "TARGET_SCHED_PROLOG" | |
13151 | " | |
13152 | { | |
13153 | rs6000_emit_prologue (); | |
13154 | DONE; | |
13155 | }") | |
13156 | ||
13157 | (define_insn "movesi_from_cr" | |
13158 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
13159 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) | |
13160 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))] | |
13161 | "" | |
13162 | "mfcr %0") | |
13163 | ||
13164 | (define_insn "*stmw" | |
13165 | [(match_parallel 0 "stmw_operation" | |
13166 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
13167 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
13168 | "TARGET_MULTIPLE" | |
13169 | "{stm|stmw} %2,%1") | |
13170 | ||
13171 | (define_insn "*save_fpregs_si" | |
13172 | [(match_parallel 0 "any_operand" | |
13173 | [(clobber (match_operand:SI 1 "register_operand" "=l")) | |
13174 | (use (match_operand:SI 2 "call_operand" "s")) | |
13175 | (set (match_operand:DF 3 "memory_operand" "=m") | |
13176 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
13177 | "TARGET_32BIT" | |
13178 | "bl %z2") | |
13179 | ||
13180 | (define_insn "*save_fpregs_di" | |
13181 | [(match_parallel 0 "any_operand" | |
13182 | [(clobber (match_operand:DI 1 "register_operand" "=l")) | |
13183 | (use (match_operand:DI 2 "call_operand" "s")) | |
13184 | (set (match_operand:DF 3 "memory_operand" "=m") | |
13185 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
13186 | "TARGET_64BIT" | |
13187 | "bl %z2") | |
13188 | ||
13189 | ; These are to explain that changes to the stack pointer should | |
13190 | ; not be moved over stores to stack memory. | |
13191 | (define_insn "stack_tie" | |
13192 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
13193 | (unspec:BLK [(match_dup 0)] 5))] | |
13194 | "" | |
13195 | "" | |
13196 | [(set_attr "length" "0")]) | |
13197 | ||
13198 | ||
13199 | (define_expand "epilogue" | |
13200 | [(use (const_int 0))] | |
13201 | "TARGET_SCHED_PROLOG" | |
13202 | " | |
13203 | { | |
13204 | rs6000_emit_epilogue (FALSE); | |
13205 | DONE; | |
13206 | }") | |
13207 | ||
13208 | ; On some processors, doing the mtcrf one CC register at a time is | |
13209 | ; faster (like on the 604e). On others, doing them all at once is | |
13210 | ; faster; for instance, on the 601 and 750. | |
13211 | ||
13212 | (define_expand "movsi_to_cr_one" | |
13213 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
13214 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
13215 | (match_dup 2)] 20))] | |
13216 | "" | |
13217 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
13218 | ||
13219 | (define_insn "*movsi_to_cr" | |
13220 | [(match_parallel 0 "mtcrf_operation" | |
e35b9579 GK |
13221 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") |
13222 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
13223 | (match_operand 3 "immediate_operand" "n")] | |
9ebbca7d GK |
13224 | 20))])] |
13225 | "" | |
e35b9579 GK |
13226 | "* |
13227 | { | |
13228 | int mask = 0; | |
13229 | int i; | |
13230 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
13231 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
13232 | operands[4] = GEN_INT (mask); | |
13233 | return \"mtcrf %4,%2\"; | |
13234 | }") | |
9ebbca7d GK |
13235 | |
13236 | (define_insn "" | |
13237 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
13238 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
13239 | (match_operand 2 "immediate_operand" "n")] 20))] | |
13240 | "GET_CODE (operands[0]) == REG | |
13241 | && CR_REGNO_P (REGNO (operands[0])) | |
13242 | && GET_CODE (operands[2]) == CONST_INT | |
13243 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
13244 | "mtcrf %R0,%1") | |
13245 | ||
13246 | ; The load-multiple instructions have similar properties. | |
13247 | ; Note that "load_multiple" is a name known to the machine-independent | |
13248 | ; code that actually corresponds to the powerpc load-string. | |
13249 | ||
13250 | (define_insn "*lmw" | |
13251 | [(match_parallel 0 "lmw_operation" | |
13252 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
13253 | (match_operand:SI 2 "memory_operand" "m"))])] | |
13254 | "TARGET_MULTIPLE" | |
13255 | "{lm|lmw} %1,%2") | |
13256 | ||
13257 | (define_insn "*return_internal_si" | |
e35b9579 GK |
13258 | [(return) |
13259 | (use (match_operand:SI 0 "register_operand" "lc"))] | |
9ebbca7d | 13260 | "TARGET_32BIT" |
cccf3bdc | 13261 | "b%T0" |
9ebbca7d GK |
13262 | [(set_attr "type" "jmpreg")]) |
13263 | ||
13264 | (define_insn "*return_internal_di" | |
e35b9579 GK |
13265 | [(return) |
13266 | (use (match_operand:DI 0 "register_operand" "lc"))] | |
9ebbca7d | 13267 | "TARGET_64BIT" |
cccf3bdc | 13268 | "b%T0" |
9ebbca7d GK |
13269 | [(set_attr "type" "jmpreg")]) |
13270 | ||
13271 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
13272 | ; stuff was in GCC. Oh, and "any_operand" is a bit flexible... | |
13273 | ||
13274 | (define_insn "*return_and_restore_fpregs_si" | |
13275 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
13276 | [(return) |
13277 | (use (match_operand:SI 1 "register_operand" "l")) | |
9ebbca7d GK |
13278 | (use (match_operand:SI 2 "call_operand" "s")) |
13279 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
13280 | (match_operand:DF 4 "memory_operand" "m"))])] | |
13281 | "TARGET_32BIT" | |
13282 | "b %z2") | |
13283 | ||
13284 | (define_insn "*return_and_restore_fpregs_di" | |
13285 | [(match_parallel 0 "any_operand" | |
e35b9579 GK |
13286 | [(return) |
13287 | (use (match_operand:DI 1 "register_operand" "l")) | |
9ebbca7d GK |
13288 | (use (match_operand:DI 2 "call_operand" "s")) |
13289 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
13290 | (match_operand:DF 4 "memory_operand" "m"))])] | |
13291 | "TARGET_64BIT" | |
13292 | "b %z2") | |
13293 | ||
83720594 RH |
13294 | ; This is used in compiling the unwind routines. |
13295 | (define_expand "eh_return" | |
13296 | [(use (match_operand 0 "general_operand" "")) | |
13297 | (use (match_operand 1 "general_operand" ""))] | |
9ebbca7d GK |
13298 | "" |
13299 | " | |
13300 | { | |
3553b09d | 13301 | #if TARGET_AIX |
83720594 | 13302 | rs6000_emit_eh_toc_restore (operands[0]); |
3553b09d | 13303 | #endif |
83720594 RH |
13304 | if (TARGET_32BIT) |
13305 | emit_insn (gen_eh_set_lr_si (operands[1])); | |
9ebbca7d | 13306 | else |
83720594 RH |
13307 | emit_insn (gen_eh_set_lr_di (operands[1])); |
13308 | emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]); | |
9ebbca7d GK |
13309 | DONE; |
13310 | }") | |
13311 | ||
83720594 RH |
13312 | ; We can't expand this before we know where the link register is stored. |
13313 | (define_insn "eh_set_lr_si" | |
13314 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9) | |
13315 | (clobber (match_scratch:SI 1 "=&r"))] | |
13316 | "TARGET_32BIT" | |
13317 | "#") | |
13318 | ||
13319 | (define_insn "eh_set_lr_di" | |
13320 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9) | |
13321 | (clobber (match_scratch:DI 1 "=&r"))] | |
13322 | "TARGET_64BIT" | |
13323 | "#") | |
9ebbca7d GK |
13324 | |
13325 | (define_split | |
83720594 RH |
13326 | [(unspec_volatile [(match_operand 0 "register_operand" "")] 9) |
13327 | (clobber (match_scratch 1 ""))] | |
13328 | "reload_completed" | |
13329 | [(const_int 0)] | |
9ebbca7d GK |
13330 | " |
13331 | { | |
83720594 | 13332 | rs6000_stack_t *info = rs6000_stack_info (); |
9ebbca7d | 13333 | |
83720594 RH |
13334 | if (info->lr_save_p) |
13335 | { | |
13336 | rtx frame_rtx = stack_pointer_rtx; | |
13337 | int sp_offset = 0; | |
13338 | rtx tmp; | |
9ebbca7d | 13339 | |
83720594 RH |
13340 | if (frame_pointer_needed |
13341 | || current_function_calls_alloca | |
13342 | || info->total_size > 32767) | |
13343 | { | |
13344 | emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx)); | |
13345 | frame_rtx = operands[1]; | |
13346 | } | |
13347 | else if (info->push_p) | |
13348 | sp_offset = info->total_size; | |
9ebbca7d | 13349 | |
83720594 RH |
13350 | tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset); |
13351 | tmp = gen_rtx_MEM (Pmode, tmp); | |
13352 | emit_move_insn (tmp, operands[0]); | |
13353 | } | |
13354 | else | |
13355 | emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]); | |
13356 | DONE; | |
13357 | }") |