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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
34792e82 | 2 | ;; Copyright (C) 1990, 91-98, 1999 Free Software Foundation, Inc. |
996a5f59 | 3 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 RK |
4 | |
5 | ;; This file is part of GNU CC. | |
6 | ||
7 | ;; GNU CC is free software; you can redistribute it and/or modify | |
8 | ;; it under the terms of the GNU General Public License as published by | |
9 | ;; the Free Software Foundation; either version 2, or (at your option) | |
10 | ;; any later version. | |
11 | ||
12 | ;; GNU CC is distributed in the hope that it will be useful, | |
13 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ;; GNU General Public License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GNU CC; see the file COPYING. If not, write to | |
3f63df56 RK |
19 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | ;; Boston, MA 02111-1307, USA. | |
1fd4e8c1 RK |
21 | |
22 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
23 | \f | |
24 | ;; Define an insn type attribute. This is used in function unit delay | |
25 | ;; computations. | |
3cb999d8 | 26 | (define_attr "type" "integer,load,store,fpload,fpstore,imul,lmul,idiv,ldiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg" |
1fd4e8c1 RK |
27 | (const_string "integer")) |
28 | ||
b19003d8 RK |
29 | ;; Length (in bytes). |
30 | (define_attr "length" "" | |
31 | (if_then_else (eq_attr "type" "branch") | |
32 | (if_then_else (and (ge (minus (pc) (match_dup 0)) | |
33 | (const_int -32768)) | |
34 | (lt (minus (pc) (match_dup 0)) | |
35 | (const_int 32767))) | |
36 | (const_int 8) | |
37 | (const_int 12)) | |
38 | (const_int 4))) | |
39 | ||
cfb557c4 RK |
40 | ;; Processor type -- this attribute must exactly match the processor_type |
41 | ;; enumeration in rs6000.h. | |
42 | ||
3cb999d8 | 43 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750" |
cfb557c4 RK |
44 | (const (symbol_ref "rs6000_cpu_attr"))) |
45 | ||
46 | ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY | |
47 | ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) | |
48 | ||
b7ff3d82 | 49 | ; Load/Store Unit -- pure PowerPC only |
51b8fc2c | 50 | ; (POWER and 601 use Integer Unit) |
cfb557c4 RK |
51 | (define_function_unit "lsu" 1 0 |
52 | (and (eq_attr "type" "load") | |
3cb999d8 | 53 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b6c9286a | 54 | 2 1) |
cfb557c4 RK |
55 | |
56 | (define_function_unit "lsu" 1 0 | |
b7ff3d82 | 57 | (and (eq_attr "type" "store,fpstore") |
3cb999d8 | 58 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b7ff3d82 | 59 | 1 1) |
b6c9286a MM |
60 | |
61 | (define_function_unit "lsu" 1 0 | |
62 | (and (eq_attr "type" "fpload") | |
bef84347 | 63 | (eq_attr "cpu" "mpccore,ppc603,ppc750")) |
b6c9286a | 64 | 2 1) |
cfb557c4 | 65 | |
b7ff3d82 DE |
66 | (define_function_unit "lsu" 1 0 |
67 | (and (eq_attr "type" "fpload") | |
3cb999d8 | 68 | (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 DE |
69 | 3 1) |
70 | ||
cfb557c4 RK |
71 | (define_function_unit "iu" 1 0 |
72 | (and (eq_attr "type" "load") | |
b7ff3d82 | 73 | (eq_attr "cpu" "rios1,ppc403,ppc601")) |
b6c9286a | 74 | 2 1) |
cfb557c4 RK |
75 | |
76 | (define_function_unit "iu" 1 0 | |
b7ff3d82 DE |
77 | (and (eq_attr "type" "store,fpstore") |
78 | (eq_attr "cpu" "rios1,ppc403,ppc601")) | |
79 | 1 1) | |
80 | ||
81 | (define_function_unit "fpu" 1 0 | |
82 | (and (eq_attr "type" "fpstore") | |
3624a679 | 83 | (eq_attr "cpu" "rios1,ppc601")) |
b7ff3d82 | 84 | 0 1) |
cfb557c4 | 85 | |
49a0b204 | 86 | (define_function_unit "iu" 1 0 |
b7ff3d82 | 87 | (and (eq_attr "type" "fpload") |
b6c9286a | 88 | (eq_attr "cpu" "rios1")) |
b7ff3d82 DE |
89 | 2 1) |
90 | ||
91 | (define_function_unit "iu" 1 0 | |
92 | (and (eq_attr "type" "fpload") | |
93 | (eq_attr "cpu" "ppc601")) | |
94 | 3 1) | |
95 | ||
96 | (define_function_unit "iu2" 2 0 | |
97 | (and (eq_attr "type" "load,fpload") | |
98 | (eq_attr "cpu" "rios2")) | |
99 | 2 1) | |
100 | ||
101 | (define_function_unit "iu2" 2 0 | |
102 | (and (eq_attr "type" "store,fpstore") | |
103 | (eq_attr "cpu" "rios2")) | |
104 | 1 1) | |
105 | ||
3cb999d8 | 106 | ; Integer Unit (RIOS1, PPC601, PPC603, RS64a) |
b7ff3d82 DE |
107 | (define_function_unit "iu" 1 0 |
108 | (and (eq_attr "type" "integer") | |
3cb999d8 | 109 | (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc601,ppc603")) |
b7ff3d82 | 110 | 1 1) |
49a0b204 | 111 | |
da0ae67f MM |
112 | (define_function_unit "iu" 1 0 |
113 | (and (eq_attr "type" "imul") | |
114 | (eq_attr "cpu" "ppc403")) | |
115 | 4 4) | |
116 | ||
cfb557c4 RK |
117 | (define_function_unit "iu" 1 0 |
118 | (and (eq_attr "type" "imul") | |
b7ff3d82 | 119 | (eq_attr "cpu" "rios1,ppc601,ppc603")) |
51b8fc2c | 120 | 5 5) |
cfb557c4 | 121 | |
3cb999d8 DE |
122 | (define_function_unit "iu" 1 0 |
123 | (and (eq_attr "type" "imul") | |
124 | (eq_attr "cpu" "rs64a")) | |
125 | 20 14) | |
126 | ||
127 | (define_function_unit "iu" 1 0 | |
128 | (and (eq_attr "type" "lmul") | |
129 | (eq_attr "cpu" "rs64a")) | |
130 | 34 34) | |
131 | ||
cfb557c4 RK |
132 | (define_function_unit "iu" 1 0 |
133 | (and (eq_attr "type" "idiv") | |
ca7f5001 | 134 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 135 | 19 19) |
cfb557c4 | 136 | |
3cb999d8 DE |
137 | (define_function_unit "iu" 1 0 |
138 | (and (eq_attr "type" "idiv") | |
139 | (eq_attr "cpu" "rs64a")) | |
140 | 66 66) | |
141 | ||
142 | (define_function_unit "iu" 1 0 | |
143 | (and (eq_attr "type" "ldiv") | |
144 | (eq_attr "cpu" "rs64a")) | |
145 | 66 66) | |
146 | ||
cfb557c4 RK |
147 | (define_function_unit "iu" 1 0 |
148 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
149 | (eq_attr "cpu" "ppc403")) |
150 | 33 33) | |
51b8fc2c | 151 | |
da0ae67f MM |
152 | (define_function_unit "iu" 1 0 |
153 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
154 | (eq_attr "cpu" "ppc601")) |
155 | 36 36) | |
da0ae67f | 156 | |
51b8fc2c RK |
157 | (define_function_unit "iu" 1 0 |
158 | (and (eq_attr "type" "idiv") | |
b7ff3d82 | 159 | (eq_attr "cpu" "ppc603")) |
51b8fc2c RK |
160 | 37 36) |
161 | ||
162 | ; RIOS2 has two integer units: a primary one which can perform all | |
163 | ; operations and a secondary one which is fed in lock step with the first | |
b6c9286a MM |
164 | ; and can perform "simple" integer operations. |
165 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
166 | ; for the complex insns. | |
51b8fc2c RK |
167 | (define_function_unit "iu2" 2 0 |
168 | (and (eq_attr "type" "integer") | |
169 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 170 | 1 1) |
b6c9286a MM |
171 | |
172 | (define_function_unit "iu2" 2 0 | |
173 | (and (eq_attr "type" "imul") | |
174 | (eq_attr "cpu" "rios2")) | |
175 | 2 2) | |
176 | ||
177 | (define_function_unit "iu2" 2 0 | |
178 | (and (eq_attr "type" "idiv") | |
179 | (eq_attr "cpu" "rios2")) | |
180 | 13 13) | |
51b8fc2c RK |
181 | |
182 | (define_function_unit "imuldiv" 1 0 | |
183 | (and (eq_attr "type" "imul") | |
184 | (eq_attr "cpu" "rios2")) | |
b6c9286a MM |
185 | 2 2) |
186 | ||
51b8fc2c RK |
187 | (define_function_unit "imuldiv" 1 0 |
188 | (and (eq_attr "type" "idiv") | |
189 | (eq_attr "cpu" "rios2")) | |
b6c9286a | 190 | 13 13) |
51b8fc2c | 191 | |
cf27b467 MM |
192 | ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions |
193 | ; Divide latency varies greatly from 2-11, use 6 as average | |
194 | (define_function_unit "imuldiv" 1 0 | |
195 | (and (eq_attr "type" "imul") | |
196 | (eq_attr "cpu" "mpccore")) | |
197 | 2 1) | |
198 | ||
199 | (define_function_unit "imuldiv" 1 0 | |
200 | (and (eq_attr "type" "idiv") | |
201 | (eq_attr "cpu" "mpccore")) | |
202 | 6 6) | |
203 | ||
cac8ce95 | 204 | ; PPC604{,e} has two units that perform integer operations |
b6c9286a MM |
205 | ; and one unit for divide/multiply operations (and move |
206 | ; from/to spr). | |
207 | (define_function_unit "iu2" 2 0 | |
51b8fc2c | 208 | (and (eq_attr "type" "integer") |
3cb999d8 | 209 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 210 | 1 1) |
51b8fc2c RK |
211 | |
212 | (define_function_unit "imuldiv" 1 0 | |
213 | (and (eq_attr "type" "imul") | |
3cb999d8 | 214 | (eq_attr "cpu" "ppc604")) |
b7ff3d82 | 215 | 4 2) |
51b8fc2c | 216 | |
3cb999d8 DE |
217 | (define_function_unit "imuldiv" 1 0 |
218 | (and (eq_attr "type" "imul") | |
219 | (eq_attr "cpu" "ppc620,ppc630")) | |
220 | 5 3) | |
221 | ||
222 | (define_function_unit "imuldiv" 1 0 | |
223 | (and (eq_attr "type" "lmul") | |
224 | (eq_attr "cpu" "ppc620,ppc630")) | |
225 | 5 3) | |
226 | ||
cac8ce95 DE |
227 | (define_function_unit "imuldiv" 1 0 |
228 | (and (eq_attr "type" "imul") | |
229 | (eq_attr "cpu" "ppc604e")) | |
230 | 2 1) | |
231 | ||
51b8fc2c RK |
232 | (define_function_unit "imuldiv" 1 0 |
233 | (and (eq_attr "type" "idiv") | |
3cb999d8 | 234 | (eq_attr "cpu" "ppc604,ppc604e")) |
b7ff3d82 | 235 | 20 19) |
cfb557c4 | 236 | |
3cb999d8 DE |
237 | (define_function_unit "imuldiv" 1 0 |
238 | (and (eq_attr "type" "idiv") | |
239 | (eq_attr "cpu" "ppc620")) | |
240 | 37 36) | |
241 | ||
242 | (define_function_unit "imuldiv" 1 0 | |
243 | (and (eq_attr "type" "idiv") | |
244 | (eq_attr "cpu" "ppc630")) | |
245 | 21 20) | |
246 | ||
247 | (define_function_unit "imuldiv" 1 0 | |
248 | (and (eq_attr "type" "ldiv") | |
249 | (eq_attr "cpu" "ppc620,ppc630")) | |
250 | 37 36) | |
251 | ||
bef84347 VM |
252 | ; PPC750 has two integer units: a primary one which can perform all |
253 | ; operations and a secondary one which is fed in lock step with the first | |
254 | ; and can perform "simple" integer operations. | |
255 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
256 | ; for the complex insns. | |
257 | (define_function_unit "iu2" 2 0 | |
258 | (and (eq_attr "type" "integer") | |
259 | (eq_attr "cpu" "ppc750")) | |
260 | 1 1) | |
261 | ||
262 | (define_function_unit "iu2" 2 0 | |
263 | (and (eq_attr "type" "imul") | |
264 | (eq_attr "cpu" "ppc750")) | |
265 | 4 2) | |
266 | ||
267 | (define_function_unit "imuldiv" 1 0 | |
268 | (and (eq_attr "type" "imul") | |
269 | (eq_attr "cpu" "ppc750")) | |
270 | 4 2) | |
271 | ||
272 | (define_function_unit "imuldiv" 1 0 | |
273 | (and (eq_attr "type" "idiv") | |
274 | (eq_attr "cpu" "ppc750")) | |
275 | 19 19) | |
276 | ||
b6c9286a | 277 | ; compare is done on integer unit, but feeds insns which |
acc5239d | 278 | ; execute on the branch unit. |
b6c9286a MM |
279 | (define_function_unit "iu" 1 0 |
280 | (and (eq_attr "type" "compare") | |
b7ff3d82 DE |
281 | (eq_attr "cpu" "rios1")) |
282 | 4 1) | |
283 | ||
284 | (define_function_unit "iu" 1 0 | |
285 | (and (eq_attr "type" "delayed_compare") | |
286 | (eq_attr "cpu" "rios1")) | |
287 | 5 1) | |
288 | ||
289 | (define_function_unit "iu" 1 0 | |
290 | (and (eq_attr "type" "compare,delayed_compare") | |
3cb999d8 | 291 | (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b7ff3d82 | 292 | 3 1) |
b6c9286a MM |
293 | |
294 | (define_function_unit "iu2" 2 0 | |
b7ff3d82 | 295 | (and (eq_attr "type" "compare,delayed_compare") |
b6c9286a | 296 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 297 | 3 1) |
b6c9286a | 298 | |
b6c9286a | 299 | (define_function_unit "iu2" 2 0 |
b7ff3d82 | 300 | (and (eq_attr "type" "compare,delayed_compare") |
3cb999d8 | 301 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b6c9286a | 302 | 1 1) |
cfb557c4 | 303 | |
b6c9286a MM |
304 | ; fp compare uses fp unit |
305 | (define_function_unit "fpu" 1 0 | |
cfb557c4 | 306 | (and (eq_attr "type" "fpcompare") |
b6c9286a | 307 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 308 | 9 1) |
cfb557c4 | 309 | |
b6c9286a MM |
310 | ; rios1 and rios2 have different fpcompare delays |
311 | (define_function_unit "fpu2" 2 0 | |
cfb557c4 | 312 | (and (eq_attr "type" "fpcompare") |
3cb999d8 | 313 | (eq_attr "cpu" "rios2,ppc630")) |
b6c9286a MM |
314 | 5 1) |
315 | ||
316 | ; on ppc601 and ppc603, fpcompare takes also 2 cycles from | |
317 | ; the integer unit | |
318 | ; here we do not define delays, just occupy the unit. The dependencies | |
b7ff3d82 | 319 | ; will be assigned by the fpcompare definition in the fpu. |
b6c9286a MM |
320 | (define_function_unit "iu" 1 0 |
321 | (and (eq_attr "type" "fpcompare") | |
b7ff3d82 | 322 | (eq_attr "cpu" "ppc601,ppc603")) |
b6c9286a MM |
323 | 0 2) |
324 | ||
325 | ; fp compare uses fp unit | |
326 | (define_function_unit "fpu" 1 0 | |
327 | (and (eq_attr "type" "fpcompare") | |
3cb999d8 | 328 | (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b6c9286a | 329 | 5 1) |
cfb557c4 | 330 | |
cf27b467 MM |
331 | (define_function_unit "fpu" 1 0 |
332 | (and (eq_attr "type" "fpcompare") | |
333 | (eq_attr "cpu" "mpccore")) | |
334 | 1 1) | |
335 | ||
cfb557c4 | 336 | (define_function_unit "bpu" 1 0 |
324e52cc | 337 | (and (eq_attr "type" "mtjmpr") |
3cb999d8 | 338 | (eq_attr "cpu" "rios1,rios2,rs64a")) |
b7ff3d82 | 339 | 5 1) |
cfb557c4 RK |
340 | |
341 | (define_function_unit "bpu" 1 0 | |
324e52cc | 342 | (and (eq_attr "type" "mtjmpr") |
3cb999d8 | 343 | (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b7ff3d82 | 344 | 4 1) |
cfb557c4 | 345 | |
b6c9286a MM |
346 | ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines. |
347 | (define_function_unit "bpu" 1 0 | |
348 | (eq_attr "type" "jmpreg") | |
b7ff3d82 | 349 | 1 1) |
b6c9286a MM |
350 | |
351 | (define_function_unit "bpu" 1 0 | |
352 | (eq_attr "type" "branch") | |
b7ff3d82 | 353 | 1 1) |
b6c9286a | 354 | |
cf27b467 | 355 | ; Floating Point Unit |
cfb557c4 | 356 | (define_function_unit "fpu" 1 0 |
51b8fc2c | 357 | (and (eq_attr "type" "fp,dmul") |
2661cdd9 | 358 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 359 | 2 1) |
cfb557c4 | 360 | |
cf27b467 MM |
361 | (define_function_unit "fpu" 1 0 |
362 | (and (eq_attr "type" "fp") | |
3cb999d8 DE |
363 | (eq_attr "cpu" "rs64a,mpccore")) |
364 | 4 2) | |
cf27b467 | 365 | |
cfb557c4 RK |
366 | (define_function_unit "fpu" 1 0 |
367 | (and (eq_attr "type" "fp") | |
51b8fc2c | 368 | (eq_attr "cpu" "ppc601")) |
b7ff3d82 | 369 | 4 1) |
cfb557c4 | 370 | |
51b8fc2c RK |
371 | (define_function_unit "fpu" 1 0 |
372 | (and (eq_attr "type" "fp") | |
3cb999d8 | 373 | (eq_attr "cpu" "ppc603,ppc750,ppc604,ppc604e,ppc620")) |
b6c9286a | 374 | 3 1) |
51b8fc2c | 375 | |
3cb999d8 DE |
376 | (define_function_unit "fpu" 1 0 |
377 | (and (eq_attr "type" "dmul") | |
378 | (eq_attr "cpu" "rs64a")) | |
379 | 7 2) | |
380 | ||
cf27b467 MM |
381 | (define_function_unit "fpu" 1 0 |
382 | (and (eq_attr "type" "dmul") | |
383 | (eq_attr "cpu" "mpccore")) | |
384 | 5 5) | |
385 | ||
cfb557c4 RK |
386 | (define_function_unit "fpu" 1 0 |
387 | (and (eq_attr "type" "dmul") | |
51b8fc2c | 388 | (eq_attr "cpu" "ppc601")) |
b6c9286a | 389 | 5 2) |
cfb557c4 | 390 | |
b6c9286a | 391 | ; is this true? |
cfb557c4 RK |
392 | (define_function_unit "fpu" 1 0 |
393 | (and (eq_attr "type" "dmul") | |
bef84347 | 394 | (eq_attr "cpu" "ppc603,ppc750")) |
51b8fc2c | 395 | 4 2) |
cfb557c4 RK |
396 | |
397 | (define_function_unit "fpu" 1 0 | |
51b8fc2c | 398 | (and (eq_attr "type" "dmul") |
cac8ce95 | 399 | (eq_attr "cpu" "ppc604,ppc604e,ppc620")) |
b6c9286a | 400 | 3 1) |
51b8fc2c RK |
401 | |
402 | (define_function_unit "fpu" 1 0 | |
403 | (and (eq_attr "type" "sdiv,ddiv") | |
2661cdd9 | 404 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 405 | 19 19) |
cfb557c4 | 406 | |
3cb999d8 DE |
407 | (define_function_unit "fpu" 1 0 |
408 | (and (eq_attr "type" "sdiv") | |
409 | (eq_attr "cpu" "rs64a")) | |
410 | 31 31) | |
411 | ||
cfb557c4 RK |
412 | (define_function_unit "fpu" 1 0 |
413 | (and (eq_attr "type" "sdiv") | |
51b8fc2c RK |
414 | (eq_attr "cpu" "ppc601")) |
415 | 17 17) | |
416 | ||
cf27b467 MM |
417 | (define_function_unit "fpu" 1 0 |
418 | (and (eq_attr "type" "sdiv") | |
419 | (eq_attr "cpu" "mpccore")) | |
420 | 10 10) | |
421 | ||
51b8fc2c RK |
422 | (define_function_unit "fpu" 1 0 |
423 | (and (eq_attr "type" "sdiv") | |
cac8ce95 | 424 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620")) |
51b8fc2c | 425 | 18 18) |
cfb557c4 | 426 | |
cf27b467 MM |
427 | (define_function_unit "fpu" 1 0 |
428 | (and (eq_attr "type" "ddiv") | |
429 | (eq_attr "cpu" "mpccore")) | |
430 | 17 17) | |
431 | ||
cfb557c4 RK |
432 | (define_function_unit "fpu" 1 0 |
433 | (and (eq_attr "type" "ddiv") | |
3cb999d8 | 434 | (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620")) |
51b8fc2c | 435 | 31 31) |
cfb557c4 RK |
436 | |
437 | (define_function_unit "fpu" 1 0 | |
438 | (and (eq_attr "type" "ddiv") | |
b7ff3d82 | 439 | (eq_attr "cpu" "ppc603")) |
51b8fc2c | 440 | 33 33) |
cfb557c4 RK |
441 | |
442 | (define_function_unit "fpu" 1 0 | |
443 | (and (eq_attr "type" "ssqrt") | |
a473029f | 444 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 445 | 31 31) |
cfb557c4 RK |
446 | |
447 | (define_function_unit "fpu" 1 0 | |
448 | (and (eq_attr "type" "dsqrt") | |
a473029f | 449 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 450 | 31 31) |
b73d04f2 | 451 | |
51b8fc2c | 452 | ; RIOS2 has two symmetric FPUs. |
cfb557c4 RK |
453 | (define_function_unit "fpu2" 2 0 |
454 | (and (eq_attr "type" "fp") | |
4652f1d4 | 455 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 456 | 2 1) |
cfb557c4 | 457 | |
3cb999d8 DE |
458 | (define_function_unit "fpu2" 2 0 |
459 | (and (eq_attr "type" "fp") | |
460 | (eq_attr "cpu" "ppc630")) | |
461 | 3 1) | |
462 | ||
cfb557c4 RK |
463 | (define_function_unit "fpu2" 2 0 |
464 | (and (eq_attr "type" "dmul") | |
465 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 466 | 2 1) |
cfb557c4 | 467 | |
3cb999d8 DE |
468 | (define_function_unit "fpu2" 2 0 |
469 | (and (eq_attr "type" "dmul") | |
470 | (eq_attr "cpu" "ppc630")) | |
471 | 3 1) | |
472 | ||
cfb557c4 | 473 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 474 | (and (eq_attr "type" "sdiv,ddiv") |
cfb557c4 | 475 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 476 | 17 17) |
ca7f5001 | 477 | |
3cb999d8 DE |
478 | (define_function_unit "fpu2" 2 0 |
479 | (and (eq_attr "type" "sdiv") | |
480 | (eq_attr "cpu" "ppc630")) | |
481 | 17 17) | |
482 | ||
483 | (define_function_unit "fpu2" 2 0 | |
484 | (and (eq_attr "type" "ddiv") | |
485 | (eq_attr "cpu" "ppc630")) | |
486 | 21 21) | |
487 | ||
ca7f5001 | 488 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 489 | (and (eq_attr "type" "ssqrt,dsqrt") |
ca7f5001 | 490 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 491 | 26 26) |
b6c9286a | 492 | |
3cb999d8 DE |
493 | (define_function_unit "fpu2" 2 0 |
494 | (and (eq_attr "type" "ssqrt") | |
495 | (eq_attr "cpu" "ppc630")) | |
496 | 18 18) | |
497 | ||
498 | (define_function_unit "fpu2" 2 0 | |
499 | (and (eq_attr "type" "dsqrt") | |
500 | (eq_attr "cpu" "ppc630")) | |
501 | 26 26) | |
502 | ||
1fd4e8c1 RK |
503 | \f |
504 | ;; Start with fixed-point load and store insns. Here we put only the more | |
505 | ;; complex forms. Basic data transfer is done later. | |
506 | ||
51b8fc2c RK |
507 | (define_expand "zero_extendqidi2" |
508 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
509 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
510 | "TARGET_POWERPC64" | |
511 | "") | |
512 | ||
513 | (define_insn "" | |
514 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
515 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
516 | "TARGET_POWERPC64" | |
517 | "@ | |
518 | lbz%U1%X1 %0,%1 | |
4371f8af | 519 | rldicl %0,%1,0,56" |
51b8fc2c RK |
520 | [(set_attr "type" "load,*")]) |
521 | ||
522 | (define_insn "" | |
29ae5b89 JL |
523 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
524 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
815cdc52 MM |
525 | (const_int 0))) |
526 | (clobber (match_scratch:DI 2 "=r"))] | |
29ae5b89 JL |
527 | "TARGET_POWERPC64" |
528 | "rldicl. %2,%1,0,56" | |
529 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
530 | |
531 | (define_insn "" | |
29ae5b89 JL |
532 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
533 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 534 | (const_int 0))) |
29ae5b89 | 535 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c | 536 | (zero_extend:DI (match_dup 1)))] |
58e09803 | 537 | "TARGET_POWERPC64" |
29ae5b89 JL |
538 | "rldicl. %0,%1,0,56" |
539 | [(set_attr "type" "compare")]) | |
51b8fc2c | 540 | |
2bee0449 RK |
541 | (define_insn "extendqidi2" |
542 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
543 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 544 | "TARGET_POWERPC64" |
2bee0449 | 545 | "extsb %0,%1") |
51b8fc2c RK |
546 | |
547 | (define_insn "" | |
29ae5b89 JL |
548 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
549 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 550 | (const_int 0))) |
29ae5b89 | 551 | (clobber (match_scratch:DI 2 "=r"))] |
51b8fc2c | 552 | "TARGET_POWERPC64" |
29ae5b89 JL |
553 | "extsb. %2,%1" |
554 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
555 | |
556 | (define_insn "" | |
29ae5b89 JL |
557 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
558 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 559 | (const_int 0))) |
29ae5b89 | 560 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
561 | (sign_extend:DI (match_dup 1)))] |
562 | "TARGET_POWERPC64" | |
29ae5b89 JL |
563 | "extsb. %0,%1" |
564 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
565 | |
566 | (define_expand "zero_extendhidi2" | |
567 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
568 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
569 | "TARGET_POWERPC64" | |
570 | "") | |
571 | ||
572 | (define_insn "" | |
573 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
574 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
575 | "TARGET_POWERPC64" | |
576 | "@ | |
577 | lhz%U1%X1 %0,%1 | |
4371f8af | 578 | rldicl %0,%1,0,48" |
51b8fc2c RK |
579 | [(set_attr "type" "load,*")]) |
580 | ||
581 | (define_insn "" | |
29ae5b89 JL |
582 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
583 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 584 | (const_int 0))) |
29ae5b89 | 585 | (clobber (match_scratch:DI 2 "=r"))] |
51b8fc2c | 586 | "TARGET_POWERPC64" |
29ae5b89 JL |
587 | "rldicl. %2,%1,0,48" |
588 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
589 | |
590 | (define_insn "" | |
29ae5b89 JL |
591 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
592 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 593 | (const_int 0))) |
29ae5b89 | 594 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
595 | (zero_extend:DI (match_dup 1)))] |
596 | "TARGET_POWERPC64" | |
29ae5b89 JL |
597 | "rldicl. %0,%1,0,48" |
598 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
599 | |
600 | (define_expand "extendhidi2" | |
601 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
602 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
603 | "TARGET_POWERPC64" | |
604 | "") | |
605 | ||
606 | (define_insn "" | |
607 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
608 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
609 | "TARGET_POWERPC64" | |
610 | "@ | |
611 | lha%U1%X1 %0,%1 | |
612 | extsh %0,%1" | |
613 | [(set_attr "type" "load,*")]) | |
614 | ||
615 | (define_insn "" | |
29ae5b89 JL |
616 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
617 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 618 | (const_int 0))) |
29ae5b89 | 619 | (clobber (match_scratch:DI 2 "=r"))] |
51b8fc2c | 620 | "TARGET_POWERPC64" |
29ae5b89 JL |
621 | "extsh. %2,%1" |
622 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
623 | |
624 | (define_insn "" | |
29ae5b89 JL |
625 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
626 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 627 | (const_int 0))) |
29ae5b89 | 628 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
629 | (sign_extend:DI (match_dup 1)))] |
630 | "TARGET_POWERPC64" | |
29ae5b89 JL |
631 | "extsh. %0,%1" |
632 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
633 | |
634 | (define_expand "zero_extendsidi2" | |
635 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
636 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
637 | "TARGET_POWERPC64" | |
638 | "") | |
639 | ||
640 | (define_insn "" | |
641 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
642 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
643 | "TARGET_POWERPC64" | |
644 | "@ | |
645 | lwz%U1%X1 %0,%1 | |
646 | rldicl %0,%1,0,32" | |
647 | [(set_attr "type" "load,*")]) | |
648 | ||
649 | (define_insn "" | |
29ae5b89 JL |
650 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
651 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 652 | (const_int 0))) |
29ae5b89 | 653 | (clobber (match_scratch:DI 2 "=r"))] |
51b8fc2c | 654 | "TARGET_POWERPC64" |
29ae5b89 JL |
655 | "rldicl. %2,%1,0,32" |
656 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
657 | |
658 | (define_insn "" | |
29ae5b89 JL |
659 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
660 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 661 | (const_int 0))) |
29ae5b89 | 662 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
663 | (zero_extend:DI (match_dup 1)))] |
664 | "TARGET_POWERPC64" | |
29ae5b89 JL |
665 | "rldicl. %0,%1,0,32" |
666 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
667 | |
668 | (define_expand "extendsidi2" | |
669 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
670 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
671 | "TARGET_POWERPC64" | |
672 | "") | |
673 | ||
674 | (define_insn "" | |
675 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 676 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
677 | "TARGET_POWERPC64" |
678 | "@ | |
679 | lwa%U1%X1 %0,%1 | |
680 | extsw %0,%1" | |
681 | [(set_attr "type" "load,*")]) | |
682 | ||
683 | (define_insn "" | |
29ae5b89 JL |
684 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
685 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 686 | (const_int 0))) |
29ae5b89 | 687 | (clobber (match_scratch:DI 2 "=r"))] |
51b8fc2c | 688 | "TARGET_POWERPC64" |
29ae5b89 JL |
689 | "extsw. %2,%1" |
690 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
691 | |
692 | (define_insn "" | |
29ae5b89 JL |
693 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
694 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 695 | (const_int 0))) |
29ae5b89 | 696 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
697 | (sign_extend:DI (match_dup 1)))] |
698 | "TARGET_POWERPC64" | |
29ae5b89 JL |
699 | "extsw. %0,%1" |
700 | [(set_attr "type" "compare")]) | |
51b8fc2c | 701 | |
1fd4e8c1 | 702 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
703 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
704 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
705 | "" |
706 | "") | |
707 | ||
708 | (define_insn "" | |
cd2b37d9 | 709 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
710 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
711 | "" | |
712 | "@ | |
713 | lbz%U1%X1 %0,%1 | |
005a35b9 | 714 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
715 | [(set_attr "type" "load,*")]) |
716 | ||
717 | (define_insn "" | |
29ae5b89 JL |
718 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
719 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 720 | (const_int 0))) |
29ae5b89 | 721 | (clobber (match_scratch:SI 2 "=r"))] |
1fd4e8c1 | 722 | "" |
29ae5b89 JL |
723 | "{andil.|andi.} %2,%1,0xff" |
724 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
725 | |
726 | (define_insn "" | |
29ae5b89 JL |
727 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
728 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 729 | (const_int 0))) |
29ae5b89 | 730 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
731 | (zero_extend:SI (match_dup 1)))] |
732 | "" | |
29ae5b89 JL |
733 | "{andil.|andi.} %0,%1,0xff" |
734 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 735 | |
51b8fc2c RK |
736 | (define_expand "extendqisi2" |
737 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
738 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
739 | "" | |
740 | " | |
741 | { | |
742 | if (TARGET_POWERPC) | |
743 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
744 | else if (TARGET_POWER) | |
745 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
746 | else | |
747 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
748 | DONE; | |
749 | }") | |
750 | ||
751 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
752 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
753 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 754 | "TARGET_POWERPC" |
2bee0449 | 755 | "extsb %0,%1") |
51b8fc2c RK |
756 | |
757 | (define_insn "" | |
29ae5b89 JL |
758 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
759 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 760 | (const_int 0))) |
29ae5b89 | 761 | (clobber (match_scratch:SI 2 "=r"))] |
51b8fc2c | 762 | "TARGET_POWERPC" |
29ae5b89 JL |
763 | "extsb. %2,%1" |
764 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
765 | |
766 | (define_insn "" | |
29ae5b89 JL |
767 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
768 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 769 | (const_int 0))) |
29ae5b89 | 770 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
771 | (sign_extend:SI (match_dup 1)))] |
772 | "TARGET_POWERPC" | |
29ae5b89 JL |
773 | "extsb. %0,%1" |
774 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
775 | |
776 | (define_expand "extendqisi2_power" | |
777 | [(parallel [(set (match_dup 2) | |
778 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
779 | (const_int 24))) | |
780 | (clobber (scratch:SI))]) | |
781 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
782 | (ashiftrt:SI (match_dup 2) | |
783 | (const_int 24))) | |
784 | (clobber (scratch:SI))])] | |
785 | "TARGET_POWER" | |
786 | " | |
787 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
788 | operands[2] = gen_reg_rtx (SImode); }") | |
789 | ||
790 | (define_expand "extendqisi2_no_power" | |
791 | [(set (match_dup 2) | |
792 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
793 | (const_int 24))) | |
794 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
795 | (ashiftrt:SI (match_dup 2) | |
796 | (const_int 24)))] | |
797 | "! TARGET_POWER && ! TARGET_POWERPC" | |
798 | " | |
799 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
800 | operands[2] = gen_reg_rtx (SImode); }") | |
801 | ||
1fd4e8c1 | 802 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
803 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
804 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
805 | "" |
806 | "") | |
807 | ||
808 | (define_insn "" | |
cd2b37d9 | 809 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
810 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
811 | "" | |
812 | "@ | |
813 | lbz%U1%X1 %0,%1 | |
005a35b9 | 814 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
815 | [(set_attr "type" "load,*")]) |
816 | ||
817 | (define_insn "" | |
29ae5b89 JL |
818 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
819 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 820 | (const_int 0))) |
29ae5b89 | 821 | (clobber (match_scratch:HI 2 "=r"))] |
51b8fc2c | 822 | "" |
29ae5b89 JL |
823 | "{andil.|andi.} %2,%1,0xff" |
824 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 825 | |
51b8fc2c | 826 | (define_insn "" |
29ae5b89 JL |
827 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
828 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 829 | (const_int 0))) |
29ae5b89 | 830 | (set (match_operand:HI 0 "gpc_reg_operand" "=r") |
815cdc52 MM |
831 | (zero_extend:HI (match_dup 1)))] |
832 | "" | |
29ae5b89 JL |
833 | "{andil.|andi.} %0,%1,0xff" |
834 | [(set_attr "type" "compare")]) | |
815cdc52 MM |
835 | |
836 | (define_expand "extendqihi2" | |
837 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
838 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
839 | "" | |
840 | " | |
841 | { | |
842 | if (TARGET_POWERPC) | |
843 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
844 | else if (TARGET_POWER) | |
845 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
846 | else | |
847 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
848 | DONE; | |
849 | }") | |
850 | ||
851 | (define_insn "extendqihi2_ppc" | |
852 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
853 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
854 | "TARGET_POWERPC" | |
855 | "extsb %0,%1") | |
856 | ||
857 | (define_insn "" | |
29ae5b89 JL |
858 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
859 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
815cdc52 | 860 | (const_int 0))) |
29ae5b89 | 861 | (clobber (match_scratch:HI 2 "=r"))] |
815cdc52 | 862 | "TARGET_POWERPC" |
29ae5b89 JL |
863 | "extsb. %2,%1" |
864 | [(set_attr "type" "compare")]) | |
815cdc52 MM |
865 | |
866 | (define_insn "" | |
29ae5b89 JL |
867 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
868 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 869 | (const_int 0))) |
29ae5b89 | 870 | (set (match_operand:HI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
871 | (sign_extend:HI (match_dup 1)))] |
872 | "TARGET_POWERPC" | |
29ae5b89 JL |
873 | "extsb. %0,%1" |
874 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
875 | |
876 | (define_expand "extendqihi2_power" | |
877 | [(parallel [(set (match_dup 2) | |
878 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
879 | (const_int 24))) | |
880 | (clobber (scratch:SI))]) | |
881 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
882 | (ashiftrt:SI (match_dup 2) | |
883 | (const_int 24))) | |
884 | (clobber (scratch:SI))])] | |
885 | "TARGET_POWER" | |
886 | " | |
887 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
888 | operands[1] = gen_lowpart (SImode, operands[1]); | |
889 | operands[2] = gen_reg_rtx (SImode); }") | |
890 | ||
891 | (define_expand "extendqihi2_no_power" | |
892 | [(set (match_dup 2) | |
893 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
894 | (const_int 24))) | |
895 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
896 | (ashiftrt:SI (match_dup 2) | |
897 | (const_int 24)))] | |
898 | "! TARGET_POWER && ! TARGET_POWERPC" | |
899 | " | |
900 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
901 | operands[1] = gen_lowpart (SImode, operands[1]); | |
902 | operands[2] = gen_reg_rtx (SImode); }") | |
903 | ||
1fd4e8c1 | 904 | (define_expand "zero_extendhisi2" |
5f243543 | 905 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 906 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
907 | "" |
908 | "") | |
909 | ||
910 | (define_insn "" | |
cd2b37d9 | 911 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
912 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
913 | "" | |
914 | "@ | |
915 | lhz%U1%X1 %0,%1 | |
005a35b9 | 916 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
917 | [(set_attr "type" "load,*")]) |
918 | ||
919 | (define_insn "" | |
29ae5b89 JL |
920 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
921 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 922 | (const_int 0))) |
29ae5b89 | 923 | (clobber (match_scratch:SI 2 "=r"))] |
1fd4e8c1 | 924 | "" |
29ae5b89 JL |
925 | "{andil.|andi.} %2,%1,0xffff" |
926 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
927 | |
928 | (define_insn "" | |
29ae5b89 JL |
929 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
930 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 931 | (const_int 0))) |
29ae5b89 | 932 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
933 | (zero_extend:SI (match_dup 1)))] |
934 | "" | |
29ae5b89 JL |
935 | "{andil.|andi.} %0,%1,0xffff" |
936 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
937 | |
938 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
939 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
940 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
941 | "" |
942 | "") | |
943 | ||
944 | (define_insn "" | |
cd2b37d9 | 945 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
946 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
947 | "" | |
948 | "@ | |
949 | lha%U1%X1 %0,%1 | |
ca7f5001 | 950 | {exts|extsh} %0,%1" |
1fd4e8c1 RK |
951 | [(set_attr "type" "load,*")]) |
952 | ||
953 | (define_insn "" | |
29ae5b89 JL |
954 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
955 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 956 | (const_int 0))) |
29ae5b89 | 957 | (clobber (match_scratch:SI 2 "=r"))] |
1fd4e8c1 | 958 | "" |
29ae5b89 JL |
959 | "{exts.|extsh.} %2,%1" |
960 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
961 | |
962 | (define_insn "" | |
29ae5b89 JL |
963 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
964 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 965 | (const_int 0))) |
29ae5b89 | 966 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
967 | (sign_extend:SI (match_dup 1)))] |
968 | "" | |
29ae5b89 JL |
969 | "{exts.|extsh.} %0,%1" |
970 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
971 | \f |
972 | ;; Fixed-point arithmetic insns. | |
deb9225a RK |
973 | |
974 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
975 | ;; allowing register zero as source. | |
7cd5235b MM |
976 | (define_expand "addsi3" |
977 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
978 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
979 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
980 | "" | |
981 | " | |
982 | { | |
677a9668 DE |
983 | if (GET_CODE (operands[2]) == CONST_INT |
984 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 985 | { |
677a9668 | 986 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
987 | ? operands[0] : gen_reg_rtx (SImode)); |
988 | ||
989 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; | |
990 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
991 | ||
992 | if (low & 0x8000) | |
993 | high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16; | |
994 | ||
995 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (high))); | |
996 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); | |
997 | DONE; | |
998 | } | |
999 | }") | |
1000 | ||
1001 | (define_insn "*addsi3_internal1" | |
1002 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
1003 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 1004 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1005 | "" |
1006 | "@ | |
deb9225a RK |
1007 | {cax|add} %0,%1,%2 |
1008 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1009 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1010 | {cau|addis} %0,%1,%v2" |
1011 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1012 | |
7cd5235b | 1013 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1014 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1015 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1016 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1017 | (const_int 0))) |
cb8cc086 | 1018 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
0ad91047 | 1019 | "! TARGET_POWERPC64" |
deb9225a RK |
1020 | "@ |
1021 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1022 | {ai.|addic.} %3,%1,%2 |
1023 | # | |
1024 | #" | |
1025 | [(set_attr "type" "compare") | |
1026 | (set_attr "length" "4,4,8,8")]) | |
1027 | ||
1028 | (define_split | |
1029 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1030 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1031 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1032 | (const_int 0))) | |
1033 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1034 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1035 | [(set (match_dup 3) |
1036 | (plus:SI (match_dup 1) | |
1037 | (match_dup 2))) | |
1038 | (set (match_dup 0) | |
1039 | (compare:CC (match_dup 3) | |
1040 | (const_int 0)))] | |
1041 | "") | |
7e69e155 | 1042 | |
7cd5235b | 1043 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1044 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1045 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1046 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1047 | (const_int 0))) |
cb8cc086 MM |
1048 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1049 | (plus:SI (match_dup 1) | |
1050 | (match_dup 2)))] | |
0ad91047 | 1051 | "! TARGET_POWERPC64" |
deb9225a RK |
1052 | "@ |
1053 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1054 | {ai.|addic.} %0,%1,%2 |
1055 | # | |
1056 | #" | |
1057 | [(set_attr "type" "compare") | |
1058 | (set_attr "length" "4,4,8,8")]) | |
1059 | ||
1060 | (define_split | |
1061 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1062 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1063 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1064 | (const_int 0))) | |
1065 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1066 | (plus:SI (match_dup 1) (match_dup 2)))] | |
0ad91047 | 1067 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1068 | [(set (match_dup 0) |
1069 | (plus:SI (match_dup 1) | |
1070 | (match_dup 2))) | |
1071 | (set (match_dup 3) | |
1072 | (compare:CC (match_dup 0) | |
1073 | (const_int 0)))] | |
1074 | "") | |
7e69e155 | 1075 | |
f357808b RK |
1076 | ;; Split an add that we can't do in one insn into two insns, each of which |
1077 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1078 | ;; add should be last in case the result gets used in an address. | |
1079 | ||
1080 | (define_split | |
cd2b37d9 RK |
1081 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1082 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1083 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1084 | "" |
f357808b RK |
1085 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1086 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1087 | " | |
1fd4e8c1 | 1088 | { |
e6ca2c17 DE |
1089 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; |
1090 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
1fd4e8c1 | 1091 | |
f357808b | 1092 | if (low & 0x8000) |
e6ca2c17 | 1093 | high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16; |
1fd4e8c1 | 1094 | |
e6ca2c17 DE |
1095 | operands[3] = GEN_INT (high); |
1096 | operands[4] = GEN_INT (low); | |
1fd4e8c1 RK |
1097 | }") |
1098 | ||
8de2a197 | 1099 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1100 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1101 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1102 | "" |
ca7f5001 RK |
1103 | "nor %0,%1,%1") |
1104 | ||
1105 | (define_insn "" | |
52d3af72 DE |
1106 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1107 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1108 | (const_int 0))) |
52d3af72 | 1109 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1110 | "! TARGET_POWERPC64" |
52d3af72 DE |
1111 | "@ |
1112 | nor. %2,%1,%1 | |
1113 | #" | |
1114 | [(set_attr "type" "compare") | |
1115 | (set_attr "length" "4,8")]) | |
1116 | ||
1117 | (define_split | |
1118 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1119 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1120 | (const_int 0))) | |
1121 | (clobber (match_scratch:SI 2 ""))] | |
0ad91047 | 1122 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1123 | [(set (match_dup 2) |
1124 | (not:SI (match_dup 1))) | |
1125 | (set (match_dup 0) | |
1126 | (compare:CC (match_dup 2) | |
1127 | (const_int 0)))] | |
1128 | "") | |
ca7f5001 RK |
1129 | |
1130 | (define_insn "" | |
52d3af72 DE |
1131 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1132 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1133 | (const_int 0))) |
52d3af72 | 1134 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1135 | (not:SI (match_dup 1)))] |
0ad91047 | 1136 | "! TARGET_POWERPC64" |
52d3af72 DE |
1137 | "@ |
1138 | nor. %0,%1,%1 | |
1139 | #" | |
1140 | [(set_attr "type" "compare") | |
1141 | (set_attr "length" "4,8")]) | |
1142 | ||
1143 | (define_split | |
1144 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1145 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1146 | (const_int 0))) | |
1147 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1148 | (not:SI (match_dup 1)))] | |
0ad91047 | 1149 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1150 | [(set (match_dup 0) |
1151 | (not:SI (match_dup 1))) | |
1152 | (set (match_dup 2) | |
1153 | (compare:CC (match_dup 0) | |
1154 | (const_int 0)))] | |
1155 | "") | |
1fd4e8c1 RK |
1156 | |
1157 | (define_insn "" | |
3d91674b RK |
1158 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1159 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1160 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1161 | "! TARGET_POWERPC" |
ca7f5001 | 1162 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1163 | |
deb9225a RK |
1164 | (define_insn "" |
1165 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1166 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1167 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1168 | "TARGET_POWERPC" | |
1169 | "@ | |
1170 | subf %0,%2,%1 | |
1171 | subfic %0,%2,%1") | |
1172 | ||
1fd4e8c1 | 1173 | (define_insn "" |
cb8cc086 MM |
1174 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1175 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1176 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1177 | (const_int 0))) |
cb8cc086 | 1178 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1179 | "! TARGET_POWERPC" |
cb8cc086 MM |
1180 | "@ |
1181 | {sf.|subfc.} %3,%2,%1 | |
1182 | #" | |
1183 | [(set_attr "type" "compare") | |
1184 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1185 | |
deb9225a | 1186 | (define_insn "" |
cb8cc086 MM |
1187 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1188 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1189 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1190 | (const_int 0))) |
cb8cc086 | 1191 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 1192 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
cb8cc086 MM |
1193 | "@ |
1194 | subf. %3,%2,%1 | |
1195 | #" | |
1196 | [(set_attr "type" "compare") | |
1197 | (set_attr "length" "4,8")]) | |
1198 | ||
1199 | (define_split | |
1200 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1201 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1202 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1203 | (const_int 0))) | |
1204 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1205 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1206 | [(set (match_dup 3) |
1207 | (minus:SI (match_dup 1) | |
1208 | (match_dup 2))) | |
1209 | (set (match_dup 0) | |
1210 | (compare:CC (match_dup 3) | |
1211 | (const_int 0)))] | |
1212 | "") | |
deb9225a | 1213 | |
1fd4e8c1 | 1214 | (define_insn "" |
cb8cc086 MM |
1215 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1216 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1217 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1218 | (const_int 0))) |
cb8cc086 | 1219 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1220 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1221 | "! TARGET_POWERPC" |
cb8cc086 MM |
1222 | "@ |
1223 | {sf.|subfc.} %0,%2,%1 | |
1224 | #" | |
1225 | [(set_attr "type" "compare") | |
1226 | (set_attr "length" "4,8")]) | |
815cdc52 | 1227 | |
29ae5b89 | 1228 | (define_insn "" |
cb8cc086 MM |
1229 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1230 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1231 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1232 | (const_int 0))) |
cb8cc086 MM |
1233 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1234 | (minus:SI (match_dup 1) | |
1235 | (match_dup 2)))] | |
0ad91047 | 1236 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
90612787 DE |
1237 | "@ |
1238 | subf. %0,%2,%1 | |
1239 | #" | |
cb8cc086 MM |
1240 | [(set_attr "type" "compare") |
1241 | (set_attr "length" "4,8")]) | |
1242 | ||
1243 | (define_split | |
1244 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1245 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1246 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1247 | (const_int 0))) | |
1248 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1249 | (minus:SI (match_dup 1) | |
1250 | (match_dup 2)))] | |
0ad91047 | 1251 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1252 | [(set (match_dup 0) |
1253 | (minus:SI (match_dup 1) | |
1254 | (match_dup 2))) | |
1255 | (set (match_dup 3) | |
1256 | (compare:CC (match_dup 0) | |
1257 | (const_int 0)))] | |
1258 | "") | |
deb9225a | 1259 | |
1fd4e8c1 | 1260 | (define_expand "subsi3" |
cd2b37d9 | 1261 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1262 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
1263 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
1264 | "" | |
a0044fb1 RK |
1265 | " |
1266 | { | |
1267 | if (GET_CODE (operands[2]) == CONST_INT) | |
1268 | { | |
1269 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1270 | negate_rtx (SImode, operands[2]))); | |
1271 | DONE; | |
1272 | } | |
1273 | }") | |
1fd4e8c1 RK |
1274 | |
1275 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1276 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1277 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1278 | ;; combine. | |
1fd4e8c1 RK |
1279 | |
1280 | (define_expand "sminsi3" | |
1281 | [(set (match_dup 3) | |
cd2b37d9 | 1282 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1283 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1284 | (const_int 0) | |
1285 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1286 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1287 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1288 | "TARGET_POWER" |
1fd4e8c1 RK |
1289 | " |
1290 | { operands[3] = gen_reg_rtx (SImode); }") | |
1291 | ||
95ac8e67 RK |
1292 | (define_split |
1293 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1294 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1295 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1296 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1297 | "TARGET_POWER" |
95ac8e67 RK |
1298 | [(set (match_dup 3) |
1299 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1300 | (const_int 0) | |
1301 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1302 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1303 | "") | |
1304 | ||
1fd4e8c1 RK |
1305 | (define_expand "smaxsi3" |
1306 | [(set (match_dup 3) | |
cd2b37d9 | 1307 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1308 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1309 | (const_int 0) | |
1310 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1311 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1312 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1313 | "TARGET_POWER" |
1fd4e8c1 RK |
1314 | " |
1315 | { operands[3] = gen_reg_rtx (SImode); }") | |
1316 | ||
95ac8e67 RK |
1317 | (define_split |
1318 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1319 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1320 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1321 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1322 | "TARGET_POWER" |
95ac8e67 RK |
1323 | [(set (match_dup 3) |
1324 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1325 | (const_int 0) | |
1326 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1327 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1328 | "") | |
1329 | ||
1fd4e8c1 | 1330 | (define_expand "uminsi3" |
cd2b37d9 | 1331 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1332 | (match_dup 5))) |
cd2b37d9 | 1333 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1334 | (match_dup 5))) |
1fd4e8c1 RK |
1335 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1336 | (const_int 0) | |
1337 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1338 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1339 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1340 | "TARGET_POWER" |
1fd4e8c1 | 1341 | " |
bb68ff55 MM |
1342 | { |
1343 | operands[3] = gen_reg_rtx (SImode); | |
1344 | operands[4] = gen_reg_rtx (SImode); | |
1345 | operands[5] = GEN_INT (-2147483647 - 1); | |
1346 | }") | |
1fd4e8c1 RK |
1347 | |
1348 | (define_expand "umaxsi3" | |
cd2b37d9 | 1349 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1350 | (match_dup 5))) |
cd2b37d9 | 1351 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1352 | (match_dup 5))) |
1fd4e8c1 RK |
1353 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1354 | (const_int 0) | |
1355 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1356 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1357 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1358 | "TARGET_POWER" |
1fd4e8c1 | 1359 | " |
bb68ff55 MM |
1360 | { |
1361 | operands[3] = gen_reg_rtx (SImode); | |
1362 | operands[4] = gen_reg_rtx (SImode); | |
1363 | operands[5] = GEN_INT (-2147483647 - 1); | |
1364 | }") | |
1fd4e8c1 RK |
1365 | |
1366 | (define_insn "" | |
cd2b37d9 RK |
1367 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1368 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1369 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1370 | (const_int 0) |
1371 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1372 | "TARGET_POWER" |
1fd4e8c1 RK |
1373 | "doz%I2 %0,%1,%2") |
1374 | ||
1375 | (define_insn "" | |
29ae5b89 | 1376 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 1377 | (compare:CC |
29ae5b89 JL |
1378 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") |
1379 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 RK |
1380 | (const_int 0) |
1381 | (minus:SI (match_dup 2) (match_dup 1))) | |
1382 | (const_int 0))) | |
29ae5b89 | 1383 | (clobber (match_scratch:SI 3 "=r"))] |
ca7f5001 | 1384 | "TARGET_POWER" |
29ae5b89 JL |
1385 | "doz%I2. %3,%1,%2" |
1386 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
1387 | |
1388 | (define_insn "" | |
29ae5b89 | 1389 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 | 1390 | (compare:CC |
29ae5b89 JL |
1391 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") |
1392 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 RK |
1393 | (const_int 0) |
1394 | (minus:SI (match_dup 2) (match_dup 1))) | |
1395 | (const_int 0))) | |
29ae5b89 | 1396 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1397 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1398 | (const_int 0) | |
1399 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1400 | "TARGET_POWER" |
29ae5b89 | 1401 | "doz%I2. %0,%1,%2" |
1fd4e8c1 RK |
1402 | [(set_attr "type" "delayed_compare")]) |
1403 | ||
1404 | ;; We don't need abs with condition code because such comparisons should | |
1405 | ;; never be done. | |
ea9be077 MM |
1406 | (define_expand "abssi2" |
1407 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1408 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1409 | "" | |
1410 | " | |
1411 | { | |
0ad91047 | 1412 | if (! TARGET_POWER) |
ea9be077 MM |
1413 | { |
1414 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1415 | DONE; | |
1416 | } | |
1417 | }") | |
1418 | ||
1419 | (define_insn "abssi2_power" | |
cd2b37d9 RK |
1420 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1421 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1422 | "TARGET_POWER" |
1fd4e8c1 RK |
1423 | "abs %0,%1") |
1424 | ||
ea9be077 MM |
1425 | (define_insn "abssi2_nopower" |
1426 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1427 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
1428 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1429 | "! TARGET_POWER" |
3595d104 MM |
1430 | "* |
1431 | { | |
1432 | return (TARGET_POWERPC) | |
1433 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\" | |
1434 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\"; | |
1435 | }" | |
ea9be077 MM |
1436 | [(set_attr "length" "12")]) |
1437 | ||
1438 | (define_split | |
1439 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1440 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
1441 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1442 | "! TARGET_POWER && reload_completed" |
ea9be077 MM |
1443 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1444 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1445 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1446 | "") |
1447 | ||
463b558b | 1448 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1449 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1450 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1451 | "TARGET_POWER" |
1fd4e8c1 RK |
1452 | "nabs %0,%1") |
1453 | ||
463b558b | 1454 | (define_insn "*nabs_no_power" |
ea9be077 MM |
1455 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
1456 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
1457 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1458 | "! TARGET_POWER" |
3595d104 MM |
1459 | "* |
1460 | { | |
1461 | return (TARGET_POWERPC) | |
1462 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\" | |
1463 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\"; | |
1464 | }" | |
ea9be077 MM |
1465 | [(set_attr "length" "12")]) |
1466 | ||
1467 | (define_split | |
1468 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1469 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
1470 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1471 | "! TARGET_POWER && reload_completed" |
ea9be077 MM |
1472 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1473 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1474 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1475 | "") |
1476 | ||
1fd4e8c1 | 1477 | (define_insn "negsi2" |
cd2b37d9 RK |
1478 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1479 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1480 | "" |
1481 | "neg %0,%1") | |
1482 | ||
1483 | (define_insn "" | |
29ae5b89 JL |
1484 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1485 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 1486 | (const_int 0))) |
29ae5b89 | 1487 | (clobber (match_scratch:SI 2 "=r"))] |
0ad91047 | 1488 | "! TARGET_POWERPC64" |
29ae5b89 JL |
1489 | "neg. %2,%1" |
1490 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
1491 | |
1492 | (define_insn "" | |
29ae5b89 JL |
1493 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
1494 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
815cdc52 MM |
1495 | (const_int 0))) |
1496 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1497 | (neg:SI (match_dup 1)))] | |
0ad91047 | 1498 | "! TARGET_POWERPC64" |
29ae5b89 JL |
1499 | "neg. %0,%1" |
1500 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
1501 | |
1502 | (define_insn "ffssi2" | |
242e8072 RK |
1503 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
1504 | (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1505 | "" |
7f340546 | 1506 | "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" |
b19003d8 | 1507 | [(set_attr "length" "16")]) |
1fd4e8c1 | 1508 | |
ca7f5001 RK |
1509 | (define_expand "mulsi3" |
1510 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1511 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
1512 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
1513 | "" | |
1514 | " | |
1515 | { | |
1516 | if (TARGET_POWER) | |
68b40e7e | 1517 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 1518 | else |
68b40e7e | 1519 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
1520 | DONE; |
1521 | }") | |
1522 | ||
68b40e7e | 1523 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
1524 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1525 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
1526 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
1527 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
1528 | "TARGET_POWER" |
1529 | "@ | |
1530 | {muls|mullw} %0,%1,%2 | |
1531 | {muli|mulli} %0,%1,%2" | |
1532 | [(set_attr "type" "imul")]) | |
1533 | ||
68b40e7e | 1534 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
1535 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1536 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1537 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 1538 | "! TARGET_POWER" |
1fd4e8c1 | 1539 | "@ |
d904e9ed RK |
1540 | {muls|mullw} %0,%1,%2 |
1541 | {muli|mulli} %0,%1,%2" | |
cfb557c4 | 1542 | [(set_attr "type" "imul")]) |
1fd4e8c1 RK |
1543 | |
1544 | (define_insn "" | |
29ae5b89 JL |
1545 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1546 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1547 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 1548 | (const_int 0))) |
29ae5b89 JL |
1549 | (clobber (match_scratch:SI 3 "=r")) |
1550 | (clobber (match_scratch:SI 4 "=q"))] | |
ca7f5001 | 1551 | "TARGET_POWER" |
29ae5b89 JL |
1552 | "{muls.|mullw.} %3,%1,%2" |
1553 | [(set_attr "type" "delayed_compare")]) | |
ca7f5001 RK |
1554 | |
1555 | (define_insn "" | |
29ae5b89 JL |
1556 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1557 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1558 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
ca7f5001 | 1559 | (const_int 0))) |
29ae5b89 | 1560 | (clobber (match_scratch:SI 3 "=r"))] |
25c341fa | 1561 | "! TARGET_POWER" |
29ae5b89 JL |
1562 | "{muls.|mullw.} %3,%1,%2" |
1563 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
1564 | |
1565 | (define_insn "" | |
29ae5b89 JL |
1566 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1567 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1568 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 1569 | (const_int 0))) |
29ae5b89 JL |
1570 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1571 | (mult:SI (match_dup 1) (match_dup 2))) | |
1572 | (clobber (match_scratch:SI 4 "=q"))] | |
ca7f5001 | 1573 | "TARGET_POWER" |
29ae5b89 JL |
1574 | "{muls.|mullw.} %0,%1,%2" |
1575 | [(set_attr "type" "delayed_compare")]) | |
ca7f5001 RK |
1576 | |
1577 | (define_insn "" | |
29ae5b89 JL |
1578 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1579 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1580 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
ca7f5001 | 1581 | (const_int 0))) |
29ae5b89 | 1582 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ca7f5001 | 1583 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 1584 | "! TARGET_POWER" |
29ae5b89 JL |
1585 | "{muls.|mullw.} %0,%1,%2" |
1586 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
1587 | |
1588 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
1589 | ;; 0 and remainder to operand 3. | |
1590 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
1591 | ||
8ffd9c51 RK |
1592 | (define_expand "divmodsi4" |
1593 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1594 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1595 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
1596 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
1597 | (mod:SI (match_dup 1) (match_dup 2)))])] | |
1598 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1599 | " | |
1600 | { | |
1601 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1602 | { | |
39403d82 DE |
1603 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1604 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1605 | emit_insn (gen_divss_call ()); |
39403d82 DE |
1606 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1607 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
1608 | DONE; |
1609 | } | |
1610 | }") | |
deb9225a | 1611 | |
fada905b | 1612 | (define_insn "" |
cd2b37d9 RK |
1613 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1614 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1615 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1616 | (set (match_operand:SI 3 "gpc_reg_operand" "=q") | |
1fd4e8c1 | 1617 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 1618 | "TARGET_POWER" |
cfb557c4 RK |
1619 | "divs %0,%1,%2" |
1620 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 1621 | |
8ffd9c51 RK |
1622 | (define_expand "udivsi3" |
1623 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1624 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1625 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
1626 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1627 | " | |
1628 | { | |
1629 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1630 | { | |
39403d82 DE |
1631 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1632 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1633 | emit_insn (gen_quous_call ()); |
39403d82 | 1634 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1635 | DONE; |
1636 | } | |
f192bf8b DE |
1637 | else if (TARGET_POWER) |
1638 | { | |
1639 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
1640 | DONE; | |
1641 | } | |
8ffd9c51 | 1642 | }") |
deb9225a | 1643 | |
f192bf8b DE |
1644 | (define_insn "udivsi3_mq" |
1645 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1646 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1647 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1648 | (clobber (match_scratch:SI 3 "=q"))] | |
1649 | "TARGET_POWERPC && TARGET_POWER" | |
1650 | "divwu %0,%1,%2" | |
1651 | [(set_attr "type" "idiv")]) | |
1652 | ||
1653 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
1654 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1655 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1656 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 1657 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 1658 | "divwu %0,%1,%2" |
ca7f5001 RK |
1659 | [(set_attr "type" "idiv")]) |
1660 | ||
1fd4e8c1 | 1661 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 1662 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
1663 | ;; used; for PowerPC, force operands into register and do a normal divide; |
1664 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 1665 | (define_expand "divsi3" |
cd2b37d9 RK |
1666 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1667 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
1668 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
1669 | "" | |
1670 | " | |
1671 | { | |
ca7f5001 RK |
1672 | if (GET_CODE (operands[2]) == CONST_INT |
1673 | && exact_log2 (INTVAL (operands[2])) >= 0) | |
1674 | ; | |
b6c9286a | 1675 | else if (TARGET_POWERPC) |
f192bf8b DE |
1676 | { |
1677 | operands[2] = force_reg (SImode, operands[2]); | |
1678 | if (TARGET_POWER) | |
1679 | { | |
1680 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
1681 | DONE; | |
1682 | } | |
1683 | } | |
b6c9286a | 1684 | else if (TARGET_POWER) |
1fd4e8c1 | 1685 | FAIL; |
405c5495 | 1686 | else |
8ffd9c51 | 1687 | { |
39403d82 DE |
1688 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1689 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1690 | emit_insn (gen_quoss_call ()); |
39403d82 | 1691 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1692 | DONE; |
1693 | } | |
1fd4e8c1 RK |
1694 | }") |
1695 | ||
f192bf8b DE |
1696 | (define_insn "divsi3_mq" |
1697 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1698 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1699 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1700 | (clobber (match_scratch:SI 3 "=q"))] | |
1701 | "TARGET_POWERPC && TARGET_POWER" | |
1702 | "divw %0,%1,%2" | |
1703 | [(set_attr "type" "idiv")]) | |
1704 | ||
1705 | (define_insn "*divsi3_no_mq" | |
1706 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1707 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1708 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1709 | "TARGET_POWERPC && ! TARGET_POWER" | |
1710 | "divw %0,%1,%2" | |
1711 | [(set_attr "type" "idiv")]) | |
1712 | ||
1fd4e8c1 | 1713 | (define_expand "modsi3" |
85644414 RK |
1714 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
1715 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 1716 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 1717 | "" |
1fd4e8c1 RK |
1718 | " |
1719 | { | |
39b52ba2 RK |
1720 | int i = exact_log2 (INTVAL (operands[2])); |
1721 | rtx temp1; | |
1722 | rtx temp2; | |
1723 | ||
405c5495 | 1724 | if (GET_CODE (operands[2]) != CONST_INT || i < 0) |
39b52ba2 RK |
1725 | FAIL; |
1726 | ||
1727 | temp1 = gen_reg_rtx (SImode); | |
1728 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 1729 | |
85644414 | 1730 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 1731 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
1732 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
1733 | DONE; | |
1fd4e8c1 RK |
1734 | }") |
1735 | ||
1736 | (define_insn "" | |
cd2b37d9 RK |
1737 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1738 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
1739 | (match_operand:SI 2 "const_int_operand" "N")))] |
1740 | "exact_log2 (INTVAL (operands[2])) >= 0" | |
ca7f5001 | 1741 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 1742 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
1743 | |
1744 | (define_insn "" | |
29ae5b89 JL |
1745 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1746 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1747 | (match_operand:SI 2 "const_int_operand" "N")) | |
b6b12107 | 1748 | (const_int 0))) |
29ae5b89 | 1749 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 1750 | "exact_log2 (INTVAL (operands[2])) >= 0" |
29ae5b89 | 1751 | "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3" |
b19003d8 | 1752 | [(set_attr "type" "compare") |
29ae5b89 | 1753 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
1754 | |
1755 | (define_insn "" | |
29ae5b89 JL |
1756 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1757 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1758 | (match_operand:SI 2 "const_int_operand" "N")) | |
b6b12107 | 1759 | (const_int 0))) |
29ae5b89 JL |
1760 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1761 | (div:SI (match_dup 1) (match_dup 2)))] | |
1fd4e8c1 | 1762 | "exact_log2 (INTVAL (operands[2])) >= 0" |
29ae5b89 | 1763 | "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0" |
b19003d8 | 1764 | [(set_attr "type" "compare") |
29ae5b89 | 1765 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
1766 | |
1767 | (define_insn "" | |
cd2b37d9 | 1768 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 1769 | (udiv:SI |
996a5f59 | 1770 | (plus:DI (ashift:DI |
cd2b37d9 | 1771 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 1772 | (const_int 32)) |
23a900dc | 1773 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 1774 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 1775 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 1776 | (umod:SI |
996a5f59 | 1777 | (plus:DI (ashift:DI |
1fd4e8c1 | 1778 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 1779 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 1780 | (match_dup 3)))] |
ca7f5001 | 1781 | "TARGET_POWER" |
cfb557c4 RK |
1782 | "div %0,%1,%3" |
1783 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
1784 | |
1785 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
1786 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
1787 | ;; have to worry about the branches. So make a few subroutines here. | |
1788 | ;; | |
1789 | ;; First comes the normal case. | |
1790 | (define_expand "udivmodsi4_normal" | |
1791 | [(set (match_dup 4) (const_int 0)) | |
1792 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 1793 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
1794 | (const_int 32)) |
1795 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
1796 | (match_operand:SI 2 "" ""))) | |
1797 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 1798 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
1799 | (const_int 32)) |
1800 | (zero_extend:DI (match_dup 1))) | |
1801 | (match_dup 2)))])] | |
ca7f5001 | 1802 | "TARGET_POWER" |
1fd4e8c1 RK |
1803 | " |
1804 | { operands[4] = gen_reg_rtx (SImode); }") | |
1805 | ||
1806 | ;; This handles the branches. | |
1807 | (define_expand "udivmodsi4_tests" | |
1808 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
1809 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
1810 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
1811 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
1812 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
1813 | (set (match_dup 0) (const_int 1)) | |
1814 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
1815 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
1816 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
1817 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 1818 | "TARGET_POWER" |
1fd4e8c1 RK |
1819 | " |
1820 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
1821 | operands[6] = gen_reg_rtx (CCmode); | |
1822 | }") | |
1823 | ||
1824 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
1825 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1826 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 1827 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 1828 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 1829 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 1830 | "" |
1fd4e8c1 RK |
1831 | " |
1832 | { | |
1833 | rtx label = 0; | |
1834 | ||
8ffd9c51 | 1835 | if (! TARGET_POWER) |
c4d38ccb MM |
1836 | { |
1837 | if (! TARGET_POWERPC) | |
1838 | { | |
39403d82 DE |
1839 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1840 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 1841 | emit_insn (gen_divus_call ()); |
39403d82 DE |
1842 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1843 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
1844 | DONE; |
1845 | } | |
1846 | else | |
1847 | FAIL; | |
1848 | } | |
0081a354 | 1849 | |
1fd4e8c1 RK |
1850 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
1851 | { | |
1852 | operands[2] = force_reg (SImode, operands[2]); | |
1853 | label = gen_label_rtx (); | |
1854 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
1855 | operands[3], label)); | |
1856 | } | |
1857 | else | |
1858 | operands[2] = force_reg (SImode, operands[2]); | |
1859 | ||
1860 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
1861 | operands[3])); | |
1862 | if (label) | |
1863 | emit_label (label); | |
1864 | ||
1865 | DONE; | |
1866 | }") | |
0081a354 | 1867 | |
fada905b MM |
1868 | ;; AIX architecture-independent common-mode multiply (DImode), |
1869 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
1870 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
1871 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
1872 | ;; assumed unused if generating common-mode, so ignore. | |
1873 | (define_insn "mulh_call" | |
1874 | [(set (reg:SI 3) | |
1875 | (truncate:SI | |
1876 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
1877 | (sign_extend:DI (reg:SI 4))) | |
1878 | (const_int 32)))) | |
cf27b467 | 1879 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 1880 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
1881 | "bla __mulh" |
1882 | [(set_attr "type" "imul")]) | |
fada905b MM |
1883 | |
1884 | (define_insn "mull_call" | |
1885 | [(set (reg:DI 3) | |
1886 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
1887 | (sign_extend:DI (reg:SI 4)))) | |
1888 | (clobber (match_scratch:SI 0 "=l")) | |
1889 | (clobber (reg:SI 0))] | |
1890 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
1891 | "bla __mull" |
1892 | [(set_attr "type" "imul")]) | |
fada905b MM |
1893 | |
1894 | (define_insn "divss_call" | |
1895 | [(set (reg:SI 3) | |
1896 | (div:SI (reg:SI 3) (reg:SI 4))) | |
1897 | (set (reg:SI 4) | |
1898 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
1899 | (clobber (match_scratch:SI 0 "=l")) | |
1900 | (clobber (reg:SI 0))] | |
1901 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
1902 | "bla __divss" |
1903 | [(set_attr "type" "idiv")]) | |
fada905b MM |
1904 | |
1905 | (define_insn "divus_call" | |
8ffd9c51 RK |
1906 | [(set (reg:SI 3) |
1907 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
1908 | (set (reg:SI 4) | |
1909 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
1910 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
1911 | (clobber (reg:SI 0)) |
1912 | (clobber (match_scratch:CC 1 "=x")) | |
1913 | (clobber (reg:CC 69))] | |
1914 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
1915 | "bla __divus" |
1916 | [(set_attr "type" "idiv")]) | |
fada905b MM |
1917 | |
1918 | (define_insn "quoss_call" | |
1919 | [(set (reg:SI 3) | |
1920 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 1921 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 1922 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
1923 | "bla __quoss" |
1924 | [(set_attr "type" "idiv")]) | |
0081a354 | 1925 | |
fada905b MM |
1926 | (define_insn "quous_call" |
1927 | [(set (reg:SI 3) | |
1928 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
1929 | (clobber (match_scratch:SI 0 "=l")) | |
1930 | (clobber (reg:SI 0)) | |
1931 | (clobber (match_scratch:CC 1 "=x")) | |
1932 | (clobber (reg:CC 69))] | |
1933 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
1934 | "bla __quous" |
1935 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 1936 | \f |
bb21487f | 1937 | ;; Logical instructions |
29ae5b89 JL |
1938 | (define_insn "andsi3" |
1939 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
1940 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 1941 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 1942 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
1943 | "" |
1944 | "@ | |
1945 | and %0,%1,%2 | |
ca7f5001 RK |
1946 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
1947 | {andil.|andi.} %0,%1,%b2 | |
29ae5b89 | 1948 | {andiu.|andis.} %0,%1,%u2" |
52d3af72 DE |
1949 | [(set_attr "length" "4")]) |
1950 | ||
1951 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
1952 | ;; the test again -- this avoids a mcrf which on the higher end | |
1953 | ;; machines causes an execution serialization | |
1fd4e8c1 | 1954 | |
7cd5235b | 1955 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
1956 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
1957 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 1958 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 1959 | (const_int 0))) |
52d3af72 DE |
1960 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
1961 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 1962 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
1963 | "@ |
1964 | and. %3,%1,%2 | |
ca7f5001 RK |
1965 | {andil.|andi.} %3,%1,%b2 |
1966 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
1967 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
1968 | # | |
1969 | # | |
1970 | # | |
1971 | #" | |
1972 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
1973 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 1974 | |
52d3af72 DE |
1975 | (define_split |
1976 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1977 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1978 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 1979 | (const_int 0))) |
52d3af72 DE |
1980 | (clobber (match_scratch:SI 3 "")) |
1981 | (clobber (match_scratch:CC 4 ""))] | |
0ad91047 | 1982 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1983 | [(parallel [(set (match_dup 3) |
1984 | (and:SI (match_dup 1) | |
1985 | (match_dup 2))) | |
1986 | (clobber (match_dup 4))]) | |
1987 | (set (match_dup 0) | |
1988 | (compare:CC (match_dup 3) | |
1989 | (const_int 0)))] | |
1990 | "") | |
1991 | ||
1992 | (define_insn "*andsi3_internal3" | |
1993 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
1994 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 1995 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
1996 | (const_int 0))) |
1997 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
1998 | (and:SI (match_dup 1) | |
1999 | (match_dup 2))) | |
2000 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2001 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2002 | "@ |
2003 | and. %0,%1,%2 | |
ca7f5001 RK |
2004 | {andil.|andi.} %0,%1,%b2 |
2005 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2006 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2007 | # | |
2008 | # | |
2009 | # | |
2010 | #" | |
2011 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2012 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2013 | ||
2014 | (define_split | |
2015 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2016 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2017 | (match_operand:SI 2 "and_operand" "")) | |
2018 | (const_int 0))) | |
2019 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2020 | (and:SI (match_dup 1) | |
2021 | (match_dup 2))) | |
2022 | (clobber (match_scratch:CC 4 ""))] | |
0ad91047 | 2023 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2024 | [(parallel [(set (match_dup 0) |
2025 | (and:SI (match_dup 1) | |
2026 | (match_dup 2))) | |
2027 | (clobber (match_dup 4))]) | |
2028 | (set (match_dup 3) | |
2029 | (compare:CC (match_dup 0) | |
2030 | (const_int 0)))] | |
2031 | "") | |
1fd4e8c1 | 2032 | |
7cd5235b | 2033 | (define_expand "iorsi3" |
cd2b37d9 | 2034 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b MM |
2035 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
2036 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
2037 | "" | |
f357808b RK |
2038 | " |
2039 | { | |
7cd5235b | 2040 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2041 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2042 | { |
2043 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2044 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2045 | ? operands[0] : gen_reg_rtx (SImode)); |
2046 | ||
a260abc9 DE |
2047 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2048 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2049 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2050 | DONE; |
2051 | } | |
f357808b RK |
2052 | }") |
2053 | ||
7cd5235b MM |
2054 | (define_insn "*iorsi3_internal1" |
2055 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") | |
2056 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") | |
5f59ecb7 | 2057 | (match_operand:SI 2 "logical_operand" "r,K,L")))] |
1fd4e8c1 RK |
2058 | "" |
2059 | "@ | |
2060 | or %0,%1,%2 | |
ca7f5001 | 2061 | {oril|ori} %0,%1,%b2 |
7cd5235b MM |
2062 | {oriu|oris} %0,%1,%u2" |
2063 | [(set_attr "length" "4,4,4")]) | |
1fd4e8c1 | 2064 | |
7cd5235b | 2065 | (define_insn "*iorsi3_internal2" |
52d3af72 DE |
2066 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2067 | (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2068 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2069 | (const_int 0))) |
52d3af72 | 2070 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2071 | "! TARGET_POWERPC64" |
52d3af72 DE |
2072 | "@ |
2073 | or. %3,%1,%2 | |
2074 | #" | |
2075 | [(set_attr "type" "compare") | |
2076 | (set_attr "length" "4,8")]) | |
2077 | ||
2078 | (define_split | |
2079 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2080 | (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2081 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2082 | (const_int 0))) | |
2083 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 2084 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2085 | [(set (match_dup 3) |
2086 | (ior:SI (match_dup 1) | |
2087 | (match_dup 2))) | |
2088 | (set (match_dup 0) | |
2089 | (compare:CC (match_dup 3) | |
2090 | (const_int 0)))] | |
2091 | "") | |
1fd4e8c1 | 2092 | |
7cd5235b | 2093 | (define_insn "*iorsi3_internal3" |
52d3af72 DE |
2094 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2095 | (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2096 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2097 | (const_int 0))) |
52d3af72 DE |
2098 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2099 | (ior:SI (match_dup 1) | |
2100 | (match_dup 2)))] | |
0ad91047 | 2101 | "! TARGET_POWERPC64" |
52d3af72 DE |
2102 | "@ |
2103 | or. %0,%1,%2 | |
2104 | #" | |
2105 | [(set_attr "type" "compare") | |
2106 | (set_attr "length" "4,8")]) | |
2107 | ||
2108 | (define_split | |
2109 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2110 | (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2111 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2112 | (const_int 0))) | |
2113 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2114 | (ior:SI (match_dup 1) (match_dup 2)))] | |
0ad91047 | 2115 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2116 | [(set (match_dup 0) |
2117 | (ior:SI (match_dup 1) | |
2118 | (match_dup 2))) | |
2119 | (set (match_dup 3) | |
2120 | (compare:CC (match_dup 0) | |
2121 | (const_int 0)))] | |
2122 | "") | |
1fd4e8c1 | 2123 | |
a260abc9 DE |
2124 | ;; Split an IOR that we can't do in one insn into two insns, each of which |
2125 | ;; does one 16-bit part. This is used by combine. | |
2126 | ||
2127 | (define_split | |
2128 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2129 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2130 | (match_operand:SI 2 "non_logical_cint_operand" "")))] | |
2131 | "" | |
2132 | [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3))) | |
2133 | (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))] | |
2134 | " | |
2135 | { | |
2136 | operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
2137 | operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
2138 | }") | |
2139 | ||
7cd5235b | 2140 | (define_expand "xorsi3" |
cd2b37d9 | 2141 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b MM |
2142 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
2143 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
1fd4e8c1 | 2144 | "" |
7cd5235b | 2145 | " |
1fd4e8c1 | 2146 | { |
7cd5235b | 2147 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2148 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2149 | { |
2150 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2151 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2152 | ? operands[0] : gen_reg_rtx (SImode)); |
2153 | ||
a260abc9 DE |
2154 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2155 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2156 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2157 | DONE; |
2158 | } | |
1fd4e8c1 RK |
2159 | }") |
2160 | ||
7cd5235b MM |
2161 | (define_insn "*xorsi3_internal1" |
2162 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") | |
2163 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") | |
5f59ecb7 | 2164 | (match_operand:SI 2 "logical_operand" "r,K,L")))] |
1fd4e8c1 RK |
2165 | "" |
2166 | "@ | |
2167 | xor %0,%1,%2 | |
ca7f5001 | 2168 | {xoril|xori} %0,%1,%b2 |
7cd5235b MM |
2169 | {xoriu|xoris} %0,%1,%u2" |
2170 | [(set_attr "length" "4,4,4")]) | |
1fd4e8c1 | 2171 | |
7cd5235b | 2172 | (define_insn "*xorsi3_internal2" |
52d3af72 DE |
2173 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2174 | (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2175 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2176 | (const_int 0))) |
52d3af72 | 2177 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2178 | "! TARGET_POWERPC64" |
52d3af72 DE |
2179 | "@ |
2180 | xor. %3,%1,%2 | |
2181 | #" | |
2182 | [(set_attr "type" "compare") | |
2183 | (set_attr "length" "4,8")]) | |
2184 | ||
2185 | (define_split | |
2186 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2187 | (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2188 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2189 | (const_int 0))) | |
2190 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 2191 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2192 | [(set (match_dup 3) |
2193 | (xor:SI (match_dup 1) | |
2194 | (match_dup 2))) | |
2195 | (set (match_dup 0) | |
2196 | (compare:CC (match_dup 3) | |
2197 | (const_int 0)))] | |
2198 | "") | |
815cdc52 | 2199 | |
29ae5b89 | 2200 | (define_insn "*xorsi3_internal3" |
52d3af72 DE |
2201 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2202 | (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2203 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2204 | (const_int 0))) |
52d3af72 DE |
2205 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2206 | (xor:SI (match_dup 1) | |
2207 | (match_dup 2)))] | |
0ad91047 | 2208 | "! TARGET_POWERPC64" |
52d3af72 DE |
2209 | "@ |
2210 | xor. %0,%1,%2 | |
2211 | #" | |
2212 | [(set_attr "type" "compare") | |
2213 | (set_attr "length" "4,8")]) | |
2214 | ||
2215 | (define_split | |
2216 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2217 | (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2218 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2219 | (const_int 0))) | |
2220 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2221 | (xor:SI (match_dup 1) (match_dup 2)))] | |
0ad91047 | 2222 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2223 | [(set (match_dup 0) |
2224 | (xor:SI (match_dup 1) | |
2225 | (match_dup 2))) | |
2226 | (set (match_dup 3) | |
2227 | (compare:CC (match_dup 0) | |
2228 | (const_int 0)))] | |
2229 | "") | |
1fd4e8c1 | 2230 | |
a260abc9 DE |
2231 | ;; Split an XOR that we can't do in one insn into two insns, each of which |
2232 | ;; does one 16-bit part. This is used by combine. | |
2233 | ||
2234 | (define_split | |
2235 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2236 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2237 | (match_operand:SI 2 "non_logical_cint_operand" "")))] | |
2238 | "" | |
2239 | [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3))) | |
2240 | (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))] | |
2241 | " | |
2242 | { | |
2243 | operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
2244 | operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
2245 | }") | |
2246 | ||
2247 | (define_insn "*eqvsi3_internal1" | |
cd2b37d9 RK |
2248 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2249 | (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
2250 | (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
1fd4e8c1 RK |
2251 | "" |
2252 | "eqv %0,%1,%2") | |
2253 | ||
a260abc9 | 2254 | (define_insn "*eqvsi3_internal2" |
52d3af72 DE |
2255 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2256 | (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2257 | (match_operand:SI 2 "gpc_reg_operand" "r,r"))) | |
1fd4e8c1 | 2258 | (const_int 0))) |
52d3af72 | 2259 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2260 | "! TARGET_POWERPC64" |
52d3af72 DE |
2261 | "@ |
2262 | eqv. %3,%1,%2 | |
2263 | #" | |
2264 | [(set_attr "type" "compare") | |
2265 | (set_attr "length" "4,8")]) | |
2266 | ||
2267 | (define_split | |
2268 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2269 | (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2270 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2271 | (const_int 0))) | |
2272 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 2273 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2274 | [(set (match_dup 3) |
2275 | (not:SI (xor:SI (match_dup 1) | |
2276 | (match_dup 2)))) | |
2277 | (set (match_dup 0) | |
2278 | (compare:CC (match_dup 3) | |
2279 | (const_int 0)))] | |
2280 | "") | |
1fd4e8c1 | 2281 | |
a260abc9 | 2282 | (define_insn "*eqvsi3_internal3" |
52d3af72 DE |
2283 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2284 | (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2285 | (match_operand:SI 2 "gpc_reg_operand" "r,r"))) | |
1fd4e8c1 | 2286 | (const_int 0))) |
52d3af72 | 2287 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 2288 | (not:SI (xor:SI (match_dup 1) (match_dup 2))))] |
0ad91047 | 2289 | "! TARGET_POWERPC64" |
52d3af72 DE |
2290 | "@ |
2291 | eqv. %0,%1,%2 | |
2292 | #" | |
2293 | [(set_attr "type" "compare") | |
2294 | (set_attr "length" "4,8")]) | |
2295 | ||
2296 | (define_split | |
2297 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2298 | (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2299 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
2300 | (const_int 0))) | |
2301 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2302 | (not:SI (xor:SI (match_dup 1) | |
2303 | (match_dup 2))))] | |
0ad91047 | 2304 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2305 | [(set (match_dup 0) |
2306 | (not:SI (xor:SI (match_dup 1) | |
2307 | (match_dup 2)))) | |
2308 | (set (match_dup 3) | |
2309 | (compare:CC (match_dup 0) | |
2310 | (const_int 0)))] | |
2311 | "") | |
1fd4e8c1 | 2312 | |
a260abc9 | 2313 | (define_insn "*andcsi3_internal1" |
cd2b37d9 RK |
2314 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2315 | (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2316 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
2317 | "" |
2318 | "andc %0,%2,%1") | |
2319 | ||
a260abc9 | 2320 | (define_insn "*andcsi3_internal2" |
52d3af72 DE |
2321 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2322 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2323 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2324 | (const_int 0))) |
52d3af72 | 2325 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2326 | "! TARGET_POWERPC64" |
52d3af72 DE |
2327 | "@ |
2328 | andc. %3,%2,%1 | |
2329 | #" | |
2330 | [(set_attr "type" "compare") | |
2331 | (set_attr "length" "4,8")]) | |
2332 | ||
2333 | (define_split | |
2334 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2335 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2336 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2337 | (const_int 0))) | |
2338 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 2339 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2340 | [(set (match_dup 3) |
2341 | (and:SI (not:SI (match_dup 1)) | |
2342 | (match_dup 2))) | |
2343 | (set (match_dup 0) | |
2344 | (compare:CC (match_dup 3) | |
2345 | (const_int 0)))] | |
2346 | "") | |
1fd4e8c1 | 2347 | |
a260abc9 | 2348 | (define_insn "*andcsi3_internal3" |
52d3af72 DE |
2349 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2350 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2351 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2352 | (const_int 0))) |
52d3af72 DE |
2353 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2354 | (and:SI (not:SI (match_dup 1)) | |
2355 | (match_dup 2)))] | |
0ad91047 | 2356 | "! TARGET_POWERPC64" |
52d3af72 DE |
2357 | "@ |
2358 | andc. %0,%2,%1 | |
2359 | #" | |
2360 | [(set_attr "type" "compare") | |
2361 | (set_attr "length" "4,8")]) | |
2362 | ||
2363 | (define_split | |
2364 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2365 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2366 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2367 | (const_int 0))) | |
2368 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2369 | (and:SI (not:SI (match_dup 1)) | |
2370 | (match_dup 2)))] | |
0ad91047 | 2371 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2372 | [(set (match_dup 0) |
2373 | (and:SI (not:SI (match_dup 1)) | |
2374 | (match_dup 2))) | |
2375 | (set (match_dup 3) | |
2376 | (compare:CC (match_dup 0) | |
2377 | (const_int 0)))] | |
2378 | "") | |
1fd4e8c1 | 2379 | |
a260abc9 | 2380 | (define_insn "*iorcsi3_internal1" |
cd2b37d9 RK |
2381 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2382 | (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2383 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
2384 | "" |
2385 | "orc %0,%2,%1") | |
2386 | ||
a260abc9 | 2387 | (define_insn "*iorcsi3_internal2" |
52d3af72 DE |
2388 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2389 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2390 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2391 | (const_int 0))) |
52d3af72 | 2392 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2393 | "! TARGET_POWERPC64" |
52d3af72 DE |
2394 | "@ |
2395 | orc. %3,%2,%1 | |
2396 | #" | |
2397 | [(set_attr "type" "compare") | |
2398 | (set_attr "length" "4,8")]) | |
2399 | ||
2400 | (define_split | |
2401 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2402 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2403 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2404 | (const_int 0))) | |
2405 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 2406 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2407 | [(set (match_dup 3) |
2408 | (ior:SI (not:SI (match_dup 1)) | |
2409 | (match_dup 2))) | |
2410 | (set (match_dup 0) | |
2411 | (compare:CC (match_dup 3) | |
2412 | (const_int 0)))] | |
2413 | "") | |
1fd4e8c1 | 2414 | |
a260abc9 | 2415 | (define_insn "*iorcsi3_internal3" |
52d3af72 DE |
2416 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2417 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2418 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2419 | (const_int 0))) |
52d3af72 | 2420 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 2421 | (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] |
0ad91047 | 2422 | "! TARGET_POWERPC64" |
52d3af72 DE |
2423 | "@ |
2424 | orc. %0,%2,%1 | |
2425 | #" | |
1fd4e8c1 RK |
2426 | [(set_attr "type" "compare")]) |
2427 | ||
52d3af72 DE |
2428 | (define_split |
2429 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2430 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2431 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2432 | (const_int 0))) | |
2433 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2434 | (ior:SI (not:SI (match_dup 1)) | |
2435 | (match_dup 2)))] | |
0ad91047 | 2436 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2437 | [(set (match_dup 0) |
2438 | (ior:SI (not:SI (match_dup 1)) | |
2439 | (match_dup 2))) | |
2440 | (set (match_dup 3) | |
2441 | (compare:CC (match_dup 0) | |
2442 | (const_int 0)))] | |
2443 | "") | |
2444 | ||
a260abc9 | 2445 | (define_insn "*nandsi3_internal1" |
cd2b37d9 | 2446 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
29ae5b89 | 2447 | (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 2448 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] |
1fd4e8c1 RK |
2449 | "" |
2450 | "nand %0,%1,%2") | |
2451 | ||
a260abc9 | 2452 | (define_insn "*nandsi3_internal2" |
52d3af72 DE |
2453 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2454 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2455 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) | |
1fd4e8c1 | 2456 | (const_int 0))) |
52d3af72 | 2457 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2458 | "! TARGET_POWERPC64" |
52d3af72 DE |
2459 | "@ |
2460 | nand. %3,%1,%2 | |
2461 | #" | |
2462 | [(set_attr "type" "compare") | |
2463 | (set_attr "length" "4,8")]) | |
2464 | ||
2465 | (define_split | |
2466 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2467 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2468 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2469 | (const_int 0))) | |
2470 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 2471 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2472 | [(set (match_dup 3) |
2473 | (ior:SI (not:SI (match_dup 1)) | |
2474 | (not:SI (match_dup 2)))) | |
2475 | (set (match_dup 0) | |
2476 | (compare:CC (match_dup 3) | |
2477 | (const_int 0)))] | |
2478 | "") | |
1fd4e8c1 | 2479 | |
a260abc9 | 2480 | (define_insn "*nandsi3_internal3" |
52d3af72 DE |
2481 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2482 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2483 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) | |
1fd4e8c1 | 2484 | (const_int 0))) |
52d3af72 DE |
2485 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2486 | (ior:SI (not:SI (match_dup 1)) | |
2487 | (not:SI (match_dup 2))))] | |
0ad91047 | 2488 | "! TARGET_POWERPC64" |
52d3af72 DE |
2489 | "@ |
2490 | nand. %0,%1,%2 | |
2491 | #" | |
2492 | [(set_attr "type" "compare") | |
2493 | (set_attr "length" "4,8")]) | |
2494 | ||
2495 | (define_split | |
2496 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2497 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2498 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2499 | (const_int 0))) | |
2500 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2501 | (ior:SI (not:SI (match_dup 1)) | |
2502 | (not:SI (match_dup 2))))] | |
0ad91047 | 2503 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2504 | [(set (match_dup 0) |
2505 | (ior:SI (not:SI (match_dup 1)) | |
2506 | (not:SI (match_dup 2)))) | |
2507 | (set (match_dup 3) | |
2508 | (compare:CC (match_dup 0) | |
2509 | (const_int 0)))] | |
2510 | "") | |
1fd4e8c1 | 2511 | |
a260abc9 | 2512 | (define_insn "*norsi3_internal1" |
cd2b37d9 | 2513 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
29ae5b89 | 2514 | (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 2515 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] |
1fd4e8c1 RK |
2516 | "" |
2517 | "nor %0,%1,%2") | |
2518 | ||
a260abc9 | 2519 | (define_insn "*norsi3_internal2" |
52d3af72 DE |
2520 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2521 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2522 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) | |
1fd4e8c1 | 2523 | (const_int 0))) |
52d3af72 | 2524 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2525 | "! TARGET_POWERPC64" |
52d3af72 DE |
2526 | "@ |
2527 | nor. %3,%1,%2 | |
2528 | #" | |
2529 | [(set_attr "type" "compare") | |
2530 | (set_attr "length" "4,8")]) | |
2531 | ||
2532 | (define_split | |
2533 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2534 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2535 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2536 | (const_int 0))) | |
2537 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 2538 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2539 | [(set (match_dup 3) |
2540 | (and:SI (not:SI (match_dup 1)) | |
2541 | (not:SI (match_dup 2)))) | |
2542 | (set (match_dup 0) | |
2543 | (compare:CC (match_dup 3) | |
2544 | (const_int 0)))] | |
2545 | "") | |
1fd4e8c1 | 2546 | |
a260abc9 | 2547 | (define_insn "*norsi3_internal3" |
52d3af72 DE |
2548 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2549 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2550 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) | |
1fd4e8c1 | 2551 | (const_int 0))) |
52d3af72 DE |
2552 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2553 | (and:SI (not:SI (match_dup 1)) | |
2554 | (not:SI (match_dup 2))))] | |
0ad91047 | 2555 | "! TARGET_POWERPC64" |
52d3af72 DE |
2556 | "@ |
2557 | nor. %0,%1,%2 | |
2558 | #" | |
2559 | [(set_attr "type" "compare") | |
2560 | (set_attr "length" "4,8")]) | |
2561 | ||
2562 | (define_split | |
2563 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2564 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2565 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2566 | (const_int 0))) | |
2567 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2568 | (and:SI (not:SI (match_dup 1)) | |
2569 | (not:SI (match_dup 2))))] | |
0ad91047 | 2570 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2571 | [(set (match_dup 0) |
2572 | (and:SI (not:SI (match_dup 1)) | |
2573 | (not:SI (match_dup 2)))) | |
2574 | (set (match_dup 3) | |
2575 | (compare:CC (match_dup 0) | |
2576 | (const_int 0)))] | |
2577 | "") | |
1fd4e8c1 RK |
2578 | |
2579 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2580 | ;; orders. Don't define forms that only set CR fields because these | |
2581 | ;; would modify an input register. | |
2582 | ||
7cd5235b | 2583 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2584 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2585 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2586 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2587 | (and:SI (match_dup 2) | |
cd2b37d9 | 2588 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2589 | "TARGET_POWER" |
01def764 | 2590 | "maskir %0,%3,%2") |
1fd4e8c1 | 2591 | |
7cd5235b | 2592 | (define_insn "*maskir_internal2" |
242e8072 | 2593 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2594 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2595 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2596 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2597 | (match_dup 2))))] |
ca7f5001 | 2598 | "TARGET_POWER" |
01def764 | 2599 | "maskir %0,%3,%2") |
1fd4e8c1 | 2600 | |
7cd5235b | 2601 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2602 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2603 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2604 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2605 | (and:SI (not:SI (match_dup 2)) |
2606 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2607 | "TARGET_POWER" |
01def764 | 2608 | "maskir %0,%3,%2") |
1fd4e8c1 | 2609 | |
7cd5235b | 2610 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2611 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2612 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2613 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2614 | (and:SI (not:SI (match_dup 2)) | |
2615 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2616 | "TARGET_POWER" |
01def764 | 2617 | "maskir %0,%3,%2") |
1fd4e8c1 | 2618 | |
7cd5235b | 2619 | (define_insn "*maskir_internal5" |
29ae5b89 | 2620 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 2621 | (compare:CC |
29ae5b89 JL |
2622 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2623 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
01def764 | 2624 | (and:SI (match_dup 2) |
29ae5b89 | 2625 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 2626 | (const_int 0))) |
29ae5b89 | 2627 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2628 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2629 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2630 | "TARGET_POWER" |
29ae5b89 JL |
2631 | "maskir. %0,%3,%2" |
2632 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2633 | |
7cd5235b | 2634 | (define_insn "*maskir_internal6" |
29ae5b89 | 2635 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 2636 | (compare:CC |
29ae5b89 JL |
2637 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2638 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2639 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 | 2640 | (match_dup 2))) |
1fd4e8c1 | 2641 | (const_int 0))) |
29ae5b89 | 2642 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2643 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2644 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 2645 | "TARGET_POWER" |
29ae5b89 JL |
2646 | "maskir. %0,%3,%2" |
2647 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2648 | |
7cd5235b | 2649 | (define_insn "*maskir_internal7" |
29ae5b89 | 2650 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
815cdc52 | 2651 | (compare:CC |
29ae5b89 JL |
2652 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
2653 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
815cdc52 | 2654 | (and:SI (not:SI (match_dup 2)) |
29ae5b89 | 2655 | (match_operand:SI 1 "gpc_reg_operand" "0"))) |
815cdc52 | 2656 | (const_int 0))) |
29ae5b89 | 2657 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
815cdc52 MM |
2658 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
2659 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2660 | "TARGET_POWER" | |
29ae5b89 JL |
2661 | "maskir. %0,%3,%2" |
2662 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2663 | |
7cd5235b | 2664 | (define_insn "*maskir_internal8" |
29ae5b89 | 2665 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 2666 | (compare:CC |
29ae5b89 JL |
2667 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
2668 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
01def764 | 2669 | (and:SI (not:SI (match_dup 2)) |
29ae5b89 | 2670 | (match_operand:SI 1 "gpc_reg_operand" "0"))) |
1fd4e8c1 | 2671 | (const_int 0))) |
29ae5b89 | 2672 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2673 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
2674 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 2675 | "TARGET_POWER" |
29ae5b89 JL |
2676 | "maskir. %0,%3,%2" |
2677 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
2678 | \f |
2679 | ;; Rotate and shift insns, in all their variants. These support shifts, | |
2680 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 2681 | (define_expand "insv" |
0ad91047 DE |
2682 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
2683 | (match_operand:SI 1 "const_int_operand" "") | |
2684 | (match_operand:SI 2 "const_int_operand" "")) | |
2685 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
2686 | "" |
2687 | " | |
2688 | { | |
2689 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2690 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2691 | compiler if the address of the structure is taken later. */ | |
2692 | if (GET_CODE (operands[0]) == SUBREG | |
2693 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2694 | FAIL; | |
a78e33fc DE |
2695 | |
2696 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
2697 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
2698 | else | |
2699 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
2700 | DONE; | |
034c1be0 MM |
2701 | }") |
2702 | ||
a78e33fc | 2703 | (define_insn "insvsi" |
cd2b37d9 | 2704 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
2705 | (match_operand:SI 1 "const_int_operand" "i") |
2706 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 2707 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
2708 | "" |
2709 | "* | |
2710 | { | |
2711 | int start = INTVAL (operands[2]) & 31; | |
2712 | int size = INTVAL (operands[1]) & 31; | |
2713 | ||
89e9f3a8 MM |
2714 | operands[4] = GEN_INT (32 - start - size); |
2715 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2716 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
1fd4e8c1 RK |
2717 | }") |
2718 | ||
a78e33fc | 2719 | (define_insn "*insvsi_internal1" |
d56d506a RK |
2720 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2721 | (match_operand:SI 1 "const_int_operand" "i") | |
2722 | (match_operand:SI 2 "const_int_operand" "i")) | |
2723 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2724 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2725 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2726 | "* |
2727 | { | |
2728 | int shift = INTVAL (operands[4]) & 31; | |
2729 | int start = INTVAL (operands[2]) & 31; | |
2730 | int size = INTVAL (operands[1]) & 31; | |
2731 | ||
89e9f3a8 MM |
2732 | operands[4] = GEN_INT (shift - start - size); |
2733 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2734 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
2735 | }") |
2736 | ||
a78e33fc | 2737 | (define_insn "*insvsi_internal2" |
d56d506a RK |
2738 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2739 | (match_operand:SI 1 "const_int_operand" "i") | |
2740 | (match_operand:SI 2 "const_int_operand" "i")) | |
2741 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2742 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2743 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2744 | "* |
2745 | { | |
2746 | int shift = INTVAL (operands[4]) & 31; | |
2747 | int start = INTVAL (operands[2]) & 31; | |
2748 | int size = INTVAL (operands[1]) & 31; | |
2749 | ||
89e9f3a8 MM |
2750 | operands[4] = GEN_INT (32 - shift - start - size); |
2751 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2752 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
2753 | }") |
2754 | ||
a78e33fc | 2755 | (define_insn "*insvsi_internal3" |
d56d506a RK |
2756 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2757 | (match_operand:SI 1 "const_int_operand" "i") | |
2758 | (match_operand:SI 2 "const_int_operand" "i")) | |
2759 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2760 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 2761 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2762 | "* |
2763 | { | |
2764 | int shift = INTVAL (operands[4]) & 31; | |
2765 | int start = INTVAL (operands[2]) & 31; | |
2766 | int size = INTVAL (operands[1]) & 31; | |
2767 | ||
89e9f3a8 MM |
2768 | operands[4] = GEN_INT (32 - shift - start - size); |
2769 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2770 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
2771 | }") |
2772 | ||
a78e33fc | 2773 | (define_insn "*insvsi_internal4" |
d56d506a RK |
2774 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2775 | (match_operand:SI 1 "const_int_operand" "i") | |
2776 | (match_operand:SI 2 "const_int_operand" "i")) | |
2777 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2778 | (match_operand:SI 4 "const_int_operand" "i") | |
2779 | (match_operand:SI 5 "const_int_operand" "i")))] | |
2780 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
2781 | "* | |
2782 | { | |
2783 | int extract_start = INTVAL (operands[5]) & 31; | |
2784 | int extract_size = INTVAL (operands[4]) & 31; | |
2785 | int insert_start = INTVAL (operands[2]) & 31; | |
2786 | int insert_size = INTVAL (operands[1]) & 31; | |
2787 | ||
2788 | /* Align extract field with insert field */ | |
3a598fbe | 2789 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 2790 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 2791 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
d56d506a RK |
2792 | }") |
2793 | ||
a78e33fc | 2794 | (define_insn "insvdi" |
685f3906 | 2795 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
2796 | (match_operand:SI 1 "const_int_operand" "i") |
2797 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
2798 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
2799 | "TARGET_POWERPC64" | |
2800 | "* | |
2801 | { | |
2802 | int start = INTVAL (operands[2]) & 63; | |
2803 | int size = INTVAL (operands[1]) & 63; | |
2804 | ||
a78e33fc DE |
2805 | operands[1] = GEN_INT (64 - start - size); |
2806 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
2807 | }") |
2808 | ||
034c1be0 | 2809 | (define_expand "extzv" |
0ad91047 DE |
2810 | [(set (match_operand 0 "gpc_reg_operand" "") |
2811 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
2812 | (match_operand:SI 2 "const_int_operand" "") | |
2813 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
2814 | "" |
2815 | " | |
2816 | { | |
2817 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2818 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2819 | compiler if the address of the structure is taken later. */ | |
2820 | if (GET_CODE (operands[0]) == SUBREG | |
2821 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2822 | FAIL; | |
a78e33fc DE |
2823 | |
2824 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
2825 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
2826 | else | |
2827 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
2828 | DONE; | |
034c1be0 MM |
2829 | }") |
2830 | ||
a78e33fc | 2831 | (define_insn "extzvsi" |
cd2b37d9 RK |
2832 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2833 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2834 | (match_operand:SI 2 "const_int_operand" "i") |
2835 | (match_operand:SI 3 "const_int_operand" "i")))] | |
2836 | "" | |
2837 | "* | |
2838 | { | |
2839 | int start = INTVAL (operands[3]) & 31; | |
2840 | int size = INTVAL (operands[2]) & 31; | |
2841 | ||
2842 | if (start + size >= 32) | |
2843 | operands[3] = const0_rtx; | |
2844 | else | |
89e9f3a8 | 2845 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 2846 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
2847 | }") |
2848 | ||
a78e33fc | 2849 | (define_insn "*extzvsi_internal1" |
29ae5b89 JL |
2850 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
2851 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2852 | (match_operand:SI 2 "const_int_operand" "i") | |
2853 | (match_operand:SI 3 "const_int_operand" "i")) | |
1fd4e8c1 | 2854 | (const_int 0))) |
29ae5b89 | 2855 | (clobber (match_scratch:SI 4 "=r"))] |
0ad91047 | 2856 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2857 | "* |
2858 | { | |
2859 | int start = INTVAL (operands[3]) & 31; | |
2860 | int size = INTVAL (operands[2]) & 31; | |
2861 | ||
a7a975e1 RK |
2862 | /* If the bitfield being tested fits in the upper or lower half of a |
2863 | word, it is possible to use andiu. or andil. to test it. This is | |
2864 | useful because the condition register set-use delay is smaller for | |
2865 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
2866 | position is 0 because the LT and GT bits may be set wrong. */ | |
2867 | ||
2868 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 2869 | { |
3a598fbe | 2870 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
2871 | - (1 << (16 - (start & 15) - size)))); |
2872 | if (start < 16) | |
ca7f5001 | 2873 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 2874 | else |
ca7f5001 | 2875 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 2876 | } |
7e69e155 | 2877 | |
1fd4e8c1 RK |
2878 | if (start + size >= 32) |
2879 | operands[3] = const0_rtx; | |
2880 | else | |
89e9f3a8 | 2881 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 2882 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 2883 | }" |
29ae5b89 | 2884 | [(set_attr "type" "compare")]) |
1fd4e8c1 | 2885 | |
a78e33fc | 2886 | (define_insn "*extzvsi_internal2" |
29ae5b89 JL |
2887 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
2888 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2889 | (match_operand:SI 2 "const_int_operand" "i") | |
2890 | (match_operand:SI 3 "const_int_operand" "i")) | |
1fd4e8c1 | 2891 | (const_int 0))) |
29ae5b89 | 2892 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2893 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
0ad91047 | 2894 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2895 | "* |
2896 | { | |
2897 | int start = INTVAL (operands[3]) & 31; | |
2898 | int size = INTVAL (operands[2]) & 31; | |
2899 | ||
a7a975e1 | 2900 | if (start >= 16 && start + size == 32) |
df031c43 | 2901 | { |
89e9f3a8 | 2902 | operands[3] = GEN_INT ((1 << (32 - start)) - 1); |
ca7f5001 | 2903 | return \"{andil.|andi.} %0,%1,%3\"; |
df031c43 | 2904 | } |
7e69e155 | 2905 | |
1fd4e8c1 RK |
2906 | if (start + size >= 32) |
2907 | operands[3] = const0_rtx; | |
2908 | else | |
89e9f3a8 | 2909 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 2910 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
2911 | }" |
2912 | [(set_attr "type" "delayed_compare")]) | |
2913 | ||
a78e33fc | 2914 | (define_insn "extzvdi" |
685f3906 DE |
2915 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
2916 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
2917 | (match_operand:SI 2 "const_int_operand" "i") |
2918 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
2919 | "TARGET_POWERPC64" |
2920 | "* | |
2921 | { | |
2922 | int start = INTVAL (operands[3]) & 63; | |
2923 | int size = INTVAL (operands[2]) & 63; | |
2924 | ||
2925 | if (start + size >= 64) | |
2926 | operands[3] = const0_rtx; | |
2927 | else | |
89e9f3a8 MM |
2928 | operands[3] = GEN_INT (start + size); |
2929 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
2930 | return \"rldicl %0,%1,%3,%2\"; |
2931 | }") | |
2932 | ||
a78e33fc | 2933 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
2934 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
2935 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
2936 | (match_operand:SI 2 "const_int_operand" "i") |
2937 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 2938 | (const_int 0))) |
29ae5b89 | 2939 | (clobber (match_scratch:DI 4 "=r"))] |
685f3906 DE |
2940 | "TARGET_POWERPC64" |
2941 | "* | |
2942 | { | |
2943 | int start = INTVAL (operands[3]) & 63; | |
2944 | int size = INTVAL (operands[2]) & 63; | |
2945 | ||
2946 | if (start + size >= 64) | |
2947 | operands[3] = const0_rtx; | |
2948 | else | |
89e9f3a8 MM |
2949 | operands[3] = GEN_INT (start + size); |
2950 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
2951 | return \"rldicl. %4,%1,%3,%2\"; |
2952 | }") | |
2953 | ||
a78e33fc | 2954 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
2955 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
2956 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
2957 | (match_operand:SI 2 "const_int_operand" "i") |
2958 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 2959 | (const_int 0))) |
29ae5b89 | 2960 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 DE |
2961 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
2962 | "TARGET_POWERPC64" | |
2963 | "* | |
2964 | { | |
2965 | int start = INTVAL (operands[3]) & 63; | |
2966 | int size = INTVAL (operands[2]) & 63; | |
2967 | ||
2968 | if (start + size >= 64) | |
2969 | operands[3] = const0_rtx; | |
2970 | else | |
89e9f3a8 MM |
2971 | operands[3] = GEN_INT (start + size); |
2972 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
2973 | return \"rldicl. %0,%1,%3,%2\"; |
2974 | }") | |
2975 | ||
1fd4e8c1 | 2976 | (define_insn "rotlsi3" |
cd2b37d9 RK |
2977 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2978 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2979 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
2980 | "" | |
ca7f5001 | 2981 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 2982 | |
a260abc9 | 2983 | (define_insn "*rotlsi3_internal2" |
29ae5b89 JL |
2984 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
2985 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2986 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
1fd4e8c1 | 2987 | (const_int 0))) |
29ae5b89 | 2988 | (clobber (match_scratch:SI 3 "=r"))] |
0ad91047 | 2989 | "! TARGET_POWERPC64" |
29ae5b89 JL |
2990 | "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff" |
2991 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 2992 | |
a260abc9 | 2993 | (define_insn "*rotlsi3_internal3" |
29ae5b89 JL |
2994 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
2995 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2996 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
1fd4e8c1 | 2997 | (const_int 0))) |
29ae5b89 | 2998 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2999 | (rotate:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3000 | "! TARGET_POWERPC64" |
29ae5b89 JL |
3001 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff" |
3002 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 3003 | |
a260abc9 | 3004 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3005 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3006 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3007 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
9615f239 | 3008 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 3009 | "" |
ca7f5001 | 3010 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3011 | |
a260abc9 | 3012 | (define_insn "*rotlsi3_internal5" |
29ae5b89 | 3013 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 3014 | (compare:CC (and:SI |
29ae5b89 JL |
3015 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3016 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
9615f239 | 3017 | (match_operand:SI 3 "mask_operand" "T")) |
1fd4e8c1 | 3018 | (const_int 0))) |
29ae5b89 | 3019 | (clobber (match_scratch:SI 4 "=r"))] |
0ad91047 | 3020 | "! TARGET_POWERPC64" |
29ae5b89 JL |
3021 | "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3" |
3022 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 3023 | |
a260abc9 | 3024 | (define_insn "*rotlsi3_internal6" |
29ae5b89 | 3025 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 3026 | (compare:CC (and:SI |
29ae5b89 JL |
3027 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3028 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
9615f239 | 3029 | (match_operand:SI 3 "mask_operand" "T")) |
1fd4e8c1 | 3030 | (const_int 0))) |
29ae5b89 | 3031 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 3032 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 3033 | "! TARGET_POWERPC64" |
29ae5b89 JL |
3034 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3" |
3035 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 3036 | |
a260abc9 | 3037 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3038 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3039 | (zero_extend:SI |
3040 | (subreg:QI | |
cd2b37d9 | 3041 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3042 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3043 | "" | |
ca7f5001 | 3044 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3045 | |
a260abc9 | 3046 | (define_insn "*rotlsi3_internal8" |
29ae5b89 | 3047 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
3048 | (compare:CC (zero_extend:SI |
3049 | (subreg:QI | |
29ae5b89 JL |
3050 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3051 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) | |
1fd4e8c1 | 3052 | (const_int 0))) |
29ae5b89 | 3053 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 3054 | "" |
29ae5b89 JL |
3055 | "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff" |
3056 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 3057 | |
a260abc9 | 3058 | (define_insn "*rotlsi3_internal9" |
29ae5b89 | 3059 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
3060 | (compare:CC (zero_extend:SI |
3061 | (subreg:QI | |
29ae5b89 JL |
3062 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3063 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) | |
1fd4e8c1 | 3064 | (const_int 0))) |
29ae5b89 | 3065 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3066 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3067 | "" | |
29ae5b89 JL |
3068 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff" |
3069 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 3070 | |
a260abc9 | 3071 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3072 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3073 | (zero_extend:SI |
3074 | (subreg:HI | |
cd2b37d9 | 3075 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3076 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3077 | "" | |
ca7f5001 | 3078 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3079 | |
a260abc9 | 3080 | (define_insn "*rotlsi3_internal11" |
29ae5b89 | 3081 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
3082 | (compare:CC (zero_extend:SI |
3083 | (subreg:HI | |
29ae5b89 JL |
3084 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3085 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) | |
1fd4e8c1 | 3086 | (const_int 0))) |
29ae5b89 | 3087 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 3088 | "" |
29ae5b89 JL |
3089 | "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff" |
3090 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 3091 | |
a260abc9 | 3092 | (define_insn "*rotlsi3_internal12" |
29ae5b89 | 3093 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
3094 | (compare:CC (zero_extend:SI |
3095 | (subreg:HI | |
29ae5b89 JL |
3096 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3097 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) | |
1fd4e8c1 | 3098 | (const_int 0))) |
29ae5b89 | 3099 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3100 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3101 | "" | |
29ae5b89 JL |
3102 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff" |
3103 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3104 | |
3105 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3106 | ;; SHIFT_COUNT_TRUNCATED. | |
3107 | ||
ca7f5001 RK |
3108 | (define_expand "ashlsi3" |
3109 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3110 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3111 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3112 | "" | |
3113 | " | |
3114 | { | |
3115 | if (TARGET_POWER) | |
3116 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3117 | else | |
25c341fa | 3118 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3119 | DONE; |
3120 | }") | |
3121 | ||
3122 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3123 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3124 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3125 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3126 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3127 | "TARGET_POWER" |
1fd4e8c1 RK |
3128 | "@ |
3129 | sle %0,%1,%2 | |
ca7f5001 RK |
3130 | {sli|slwi} %0,%1,%h2" |
3131 | [(set_attr "length" "8")]) | |
3132 | ||
25c341fa | 3133 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3134 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3135 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3136 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3137 | "! TARGET_POWER" |
d904e9ed | 3138 | "{sl|slw}%I2 %0,%1,%h2" |
b19003d8 | 3139 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
3140 | |
3141 | (define_insn "" | |
29ae5b89 JL |
3142 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
3143 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3144 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) | |
1fd4e8c1 | 3145 | (const_int 0))) |
29ae5b89 JL |
3146 | (clobber (match_scratch:SI 3 "=r,r")) |
3147 | (clobber (match_scratch:SI 4 "=q,X"))] | |
ca7f5001 | 3148 | "TARGET_POWER" |
1fd4e8c1 RK |
3149 | "@ |
3150 | sle. %3,%1,%2 | |
29ae5b89 JL |
3151 | {sli.|slwi.} %3,%1,%h2" |
3152 | [(set_attr "type" "delayed_compare")]) | |
25c341fa | 3153 | |
ca7f5001 | 3154 | (define_insn "" |
29ae5b89 JL |
3155 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
3156 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3157 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
ca7f5001 | 3158 | (const_int 0))) |
29ae5b89 | 3159 | (clobber (match_scratch:SI 3 "=r"))] |
0ad91047 | 3160 | "! TARGET_POWER && ! TARGET_POWERPC64" |
29ae5b89 JL |
3161 | "{sl|slw}%I2. %3,%1,%h2" |
3162 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3163 | |
3164 | (define_insn "" | |
29ae5b89 JL |
3165 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
3166 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3167 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) | |
1fd4e8c1 | 3168 | (const_int 0))) |
29ae5b89 | 3169 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3170 | (ashift:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 3171 | (clobber (match_scratch:SI 4 "=q,X"))] |
ca7f5001 | 3172 | "TARGET_POWER" |
1fd4e8c1 RK |
3173 | "@ |
3174 | sle. %0,%1,%2 | |
29ae5b89 | 3175 | {sli.|slwi.} %0,%1,%h2" |
ca7f5001 | 3176 | [(set_attr "type" "delayed_compare")]) |
25c341fa | 3177 | |
ca7f5001 | 3178 | (define_insn "" |
29ae5b89 JL |
3179 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
3180 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3181 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
ca7f5001 | 3182 | (const_int 0))) |
29ae5b89 | 3183 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ca7f5001 | 3184 | (ashift:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3185 | "! TARGET_POWER && ! TARGET_POWERPC64" |
d904e9ed | 3186 | "{sl|slw}%I2. %0,%1,%h2" |
1fd4e8c1 RK |
3187 | [(set_attr "type" "delayed_compare")]) |
3188 | ||
3189 | (define_insn "" | |
cd2b37d9 RK |
3190 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3191 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3192 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 3193 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 3194 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 3195 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3196 | |
3197 | (define_insn "" | |
29ae5b89 | 3198 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 3199 | (compare:CC |
29ae5b89 JL |
3200 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3201 | (match_operand:SI 2 "const_int_operand" "i")) | |
9615f239 | 3202 | (match_operand:SI 3 "mask_operand" "T")) |
1fd4e8c1 | 3203 | (const_int 0))) |
29ae5b89 | 3204 | (clobber (match_scratch:SI 4 "=r"))] |
0ad91047 | 3205 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
29ae5b89 | 3206 | "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3" |
1fd4e8c1 RK |
3207 | [(set_attr "type" "delayed_compare")]) |
3208 | ||
3209 | (define_insn "" | |
29ae5b89 | 3210 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 3211 | (compare:CC |
29ae5b89 JL |
3212 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3213 | (match_operand:SI 2 "const_int_operand" "i")) | |
9615f239 | 3214 | (match_operand:SI 3 "mask_operand" "T")) |
1fd4e8c1 | 3215 | (const_int 0))) |
29ae5b89 | 3216 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 3217 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 3218 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
29ae5b89 | 3219 | "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3" |
1fd4e8c1 RK |
3220 | [(set_attr "type" "delayed_compare")]) |
3221 | ||
ca7f5001 | 3222 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3223 | ;; "sli x,x,0". |
ca7f5001 RK |
3224 | (define_expand "lshrsi3" |
3225 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3226 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3227 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3228 | "" | |
3229 | " | |
3230 | { | |
3231 | if (TARGET_POWER) | |
3232 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
3233 | else | |
25c341fa | 3234 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3235 | DONE; |
3236 | }") | |
3237 | ||
3238 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
3239 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
3240 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3241 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
3242 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 3243 | "TARGET_POWER" |
1fd4e8c1 RK |
3244 | "@ |
3245 | sre %0,%1,%2 | |
bdf423cb | 3246 | mr %0,%1 |
ca7f5001 RK |
3247 | {s%A2i|s%A2wi} %0,%1,%h2") |
3248 | ||
25c341fa | 3249 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
3250 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3251 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3252 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 3253 | "! TARGET_POWER" |
bdf423cb MM |
3254 | "@ |
3255 | mr %0,%1 | |
3256 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
3257 | |
3258 | (define_insn "" | |
29ae5b89 JL |
3259 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x") |
3260 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3261 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")) | |
1fd4e8c1 | 3262 | (const_int 0))) |
29ae5b89 JL |
3263 | (clobber (match_scratch:SI 3 "=r,X,r")) |
3264 | (clobber (match_scratch:SI 4 "=q,X,X"))] | |
ca7f5001 | 3265 | "TARGET_POWER" |
1fd4e8c1 | 3266 | "@ |
29ae5b89 JL |
3267 | sre. %3,%1,%2 |
3268 | mr. %1,%1 | |
3269 | {s%A2i.|s%A2wi.} %3,%1,%h2" | |
3270 | [(set_attr "type" "delayed_compare")]) | |
ca7f5001 RK |
3271 | |
3272 | (define_insn "" | |
29ae5b89 JL |
3273 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
3274 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3275 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")) | |
ca7f5001 | 3276 | (const_int 0))) |
29ae5b89 | 3277 | (clobber (match_scratch:SI 3 "=X,r"))] |
0ad91047 | 3278 | "! TARGET_POWER && ! TARGET_POWERPC64" |
bdf423cb MM |
3279 | "@ |
3280 | mr. %1,%1 | |
29ae5b89 JL |
3281 | {sr|srw}%I2. %3,%1,%h2" |
3282 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3283 | |
3284 | (define_insn "" | |
29ae5b89 JL |
3285 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x") |
3286 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3287 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")) | |
1fd4e8c1 | 3288 | (const_int 0))) |
29ae5b89 | 3289 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1fd4e8c1 | 3290 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 3291 | (clobber (match_scratch:SI 4 "=q,X,X"))] |
ca7f5001 | 3292 | "TARGET_POWER" |
1fd4e8c1 | 3293 | "@ |
29ae5b89 JL |
3294 | sre. %0,%1,%2 |
3295 | mr. %0,%1 | |
3296 | {s%A2i.|s%A2wi.} %0,%1,%h2" | |
3297 | [(set_attr "type" "delayed_compare")]) | |
ca7f5001 RK |
3298 | |
3299 | (define_insn "" | |
29ae5b89 JL |
3300 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
3301 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3302 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")) | |
815cdc52 | 3303 | (const_int 0))) |
29ae5b89 JL |
3304 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3305 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
0ad91047 | 3306 | "! TARGET_POWER && ! TARGET_POWERPC64" |
29ae5b89 JL |
3307 | "@ |
3308 | mr. %0,%1 | |
3309 | {sr|srw}%I2. %0,%1,%h2" | |
3310 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3311 | |
3312 | (define_insn "" | |
cd2b37d9 RK |
3313 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3314 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3315 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 3316 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 3317 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 3318 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
3319 | |
3320 | (define_insn "" | |
29ae5b89 | 3321 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 3322 | (compare:CC |
29ae5b89 JL |
3323 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3324 | (match_operand:SI 2 "const_int_operand" "i")) | |
9615f239 | 3325 | (match_operand:SI 3 "mask_operand" "T")) |
1fd4e8c1 | 3326 | (const_int 0))) |
29ae5b89 | 3327 | (clobber (match_scratch:SI 4 "=r"))] |
0ad91047 | 3328 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
29ae5b89 JL |
3329 | "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3" |
3330 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3331 | |
3332 | (define_insn "" | |
29ae5b89 | 3333 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 3334 | (compare:CC |
29ae5b89 JL |
3335 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3336 | (match_operand:SI 2 "const_int_operand" "i")) | |
9615f239 | 3337 | (match_operand:SI 3 "mask_operand" "T")) |
1fd4e8c1 | 3338 | (const_int 0))) |
29ae5b89 | 3339 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 3340 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 3341 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
29ae5b89 JL |
3342 | "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3" |
3343 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3344 | |
3345 | (define_insn "" | |
cd2b37d9 | 3346 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3347 | (zero_extend:SI |
3348 | (subreg:QI | |
cd2b37d9 | 3349 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 3350 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 3351 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 3352 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
3353 | |
3354 | (define_insn "" | |
29ae5b89 | 3355 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
3356 | (compare:CC |
3357 | (zero_extend:SI | |
3358 | (subreg:QI | |
29ae5b89 JL |
3359 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3360 | (match_operand:SI 2 "const_int_operand" "i")) 0)) | |
1fd4e8c1 | 3361 | (const_int 0))) |
29ae5b89 | 3362 | (clobber (match_scratch:SI 3 "=r"))] |
89e9f3a8 | 3363 | "includes_rshift_p (operands[2], GEN_INT (255))" |
29ae5b89 JL |
3364 | "{rlinm.|rlwinm.} %3,%1,%s2,0xff" |
3365 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3366 | |
3367 | (define_insn "" | |
29ae5b89 | 3368 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
3369 | (compare:CC |
3370 | (zero_extend:SI | |
3371 | (subreg:QI | |
29ae5b89 JL |
3372 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3373 | (match_operand:SI 2 "const_int_operand" "i")) 0)) | |
1fd4e8c1 | 3374 | (const_int 0))) |
29ae5b89 | 3375 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 3376 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 3377 | "includes_rshift_p (operands[2], GEN_INT (255))" |
29ae5b89 JL |
3378 | "{rlinm.|rlwinm.} %0,%1,%s2,0xff" |
3379 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3380 | |
3381 | (define_insn "" | |
cd2b37d9 | 3382 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3383 | (zero_extend:SI |
3384 | (subreg:HI | |
cd2b37d9 | 3385 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 3386 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 3387 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 3388 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
3389 | |
3390 | (define_insn "" | |
29ae5b89 | 3391 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
3392 | (compare:CC |
3393 | (zero_extend:SI | |
3394 | (subreg:HI | |
29ae5b89 JL |
3395 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3396 | (match_operand:SI 2 "const_int_operand" "i")) 0)) | |
1fd4e8c1 | 3397 | (const_int 0))) |
29ae5b89 | 3398 | (clobber (match_scratch:SI 3 "=r"))] |
89e9f3a8 | 3399 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
29ae5b89 JL |
3400 | "{rlinm.|rlwinm.} %3,%1,%s2,0xffff" |
3401 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3402 | |
3403 | (define_insn "" | |
29ae5b89 | 3404 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
3405 | (compare:CC |
3406 | (zero_extend:SI | |
3407 | (subreg:HI | |
29ae5b89 JL |
3408 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3409 | (match_operand:SI 2 "const_int_operand" "i")) 0)) | |
1fd4e8c1 | 3410 | (const_int 0))) |
29ae5b89 | 3411 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 3412 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 3413 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 3414 | "{rlinm.|rlwinm.} %0,%1,%s2,0xffff" |
1fd4e8c1 RK |
3415 | [(set_attr "type" "delayed_compare")]) |
3416 | ||
3417 | (define_insn "" | |
cd2b37d9 | 3418 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 3419 | (const_int 1) |
cd2b37d9 RK |
3420 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
3421 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3422 | (const_int 31)))] |
ca7f5001 | 3423 | "TARGET_POWER" |
1fd4e8c1 RK |
3424 | "rrib %0,%1,%2") |
3425 | ||
3426 | (define_insn "" | |
cd2b37d9 | 3427 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 3428 | (const_int 1) |
cd2b37d9 RK |
3429 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
3430 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3431 | (const_int 31)))] |
ca7f5001 | 3432 | "TARGET_POWER" |
1fd4e8c1 RK |
3433 | "rrib %0,%1,%2") |
3434 | ||
3435 | (define_insn "" | |
cd2b37d9 | 3436 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 3437 | (const_int 1) |
cd2b37d9 RK |
3438 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
3439 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3440 | (const_int 1) |
3441 | (const_int 0)))] | |
ca7f5001 | 3442 | "TARGET_POWER" |
1fd4e8c1 RK |
3443 | "rrib %0,%1,%2") |
3444 | ||
ca7f5001 RK |
3445 | (define_expand "ashrsi3" |
3446 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
3447 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3448 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
3449 | "" | |
3450 | " | |
3451 | { | |
3452 | if (TARGET_POWER) | |
3453 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
3454 | else | |
25c341fa | 3455 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3456 | DONE; |
3457 | }") | |
3458 | ||
3459 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
3460 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3461 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3462 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3463 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3464 | "TARGET_POWER" |
1fd4e8c1 RK |
3465 | "@ |
3466 | srea %0,%1,%2 | |
ca7f5001 RK |
3467 | {srai|srawi} %0,%1,%h2") |
3468 | ||
25c341fa | 3469 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
3470 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3471 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3472 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3473 | "! TARGET_POWER" |
d904e9ed | 3474 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3475 | |
3476 | (define_insn "" | |
29ae5b89 JL |
3477 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
3478 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3479 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) | |
1fd4e8c1 | 3480 | (const_int 0))) |
29ae5b89 JL |
3481 | (clobber (match_scratch:SI 3 "=r,r")) |
3482 | (clobber (match_scratch:SI 4 "=q,X"))] | |
ca7f5001 | 3483 | "TARGET_POWER" |
1fd4e8c1 RK |
3484 | "@ |
3485 | srea. %3,%1,%2 | |
29ae5b89 JL |
3486 | {srai.|srawi.} %3,%1,%h2" |
3487 | [(set_attr "type" "delayed_compare")]) | |
ca7f5001 RK |
3488 | |
3489 | (define_insn "" | |
29ae5b89 JL |
3490 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
3491 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3492 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
ca7f5001 | 3493 | (const_int 0))) |
29ae5b89 | 3494 | (clobber (match_scratch:SI 3 "=r"))] |
25c341fa | 3495 | "! TARGET_POWER" |
29ae5b89 JL |
3496 | "{sra|sraw}%I2. %3,%1,%h2" |
3497 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3498 | |
3499 | (define_insn "" | |
29ae5b89 JL |
3500 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
3501 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3502 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) | |
1fd4e8c1 | 3503 | (const_int 0))) |
29ae5b89 | 3504 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3505 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 3506 | (clobber (match_scratch:SI 4 "=q,X"))] |
ca7f5001 | 3507 | "TARGET_POWER" |
1fd4e8c1 RK |
3508 | "@ |
3509 | srea. %0,%1,%2 | |
29ae5b89 JL |
3510 | {srai.|srawi.} %0,%1,%h2" |
3511 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 3512 | |
ca7f5001 | 3513 | (define_insn "" |
29ae5b89 JL |
3514 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
3515 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3516 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
ca7f5001 | 3517 | (const_int 0))) |
29ae5b89 | 3518 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ca7f5001 | 3519 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 3520 | "! TARGET_POWER" |
29ae5b89 JL |
3521 | "{sra|sraw}%I2. %0,%1,%h2" |
3522 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3523 | \f |
3524 | ;; Floating-point insns, excluding normal data motion. | |
3525 | ;; | |
ca7f5001 RK |
3526 | ;; PowerPC has a full set of single-precision floating point instructions. |
3527 | ;; | |
3528 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
3529 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
3530 | ;; The only conversions we will do will be when storing to memory. In that | |
3531 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
3532 | ;; |
3533 | ;; Note that when we store into a single-precision memory location, we need to | |
3534 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
3535 | ;; need a scratch register for the frsp. But this is difficult when the store | |
3536 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
3537 | ;; this case, we just lose precision that we would have otherwise gotten but | |
3538 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
3539 | ||
e8112008 | 3540 | (define_insn "extendsfdf2" |
cd2b37d9 | 3541 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
e8112008 | 3542 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] |
d14a6d05 | 3543 | "TARGET_HARD_FLOAT" |
e8112008 | 3544 | "* |
5c30aff8 | 3545 | { |
e8112008 RK |
3546 | if (REGNO (operands[0]) == REGNO (operands[1])) |
3547 | return \"\"; | |
3548 | else | |
3549 | return \"fmr %0,%1\"; | |
3550 | }" | |
3551 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
3552 | |
3553 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
3554 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3555 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3556 | "TARGET_HARD_FLOAT" |
dcac138d | 3557 | "frsp %0,%1" |
1fd4e8c1 RK |
3558 | [(set_attr "type" "fp")]) |
3559 | ||
455350f4 RK |
3560 | (define_insn "aux_truncdfsf2" |
3561 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3562 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))] | |
3563 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" | |
3564 | "frsp %0,%1" | |
3565 | [(set_attr "type" "fp")]) | |
3566 | ||
1fd4e8c1 | 3567 | (define_insn "negsf2" |
cd2b37d9 RK |
3568 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3569 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3570 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3571 | "fneg %0,%1" |
3572 | [(set_attr "type" "fp")]) | |
3573 | ||
3574 | (define_insn "abssf2" | |
cd2b37d9 RK |
3575 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3576 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3577 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3578 | "fabs %0,%1" |
3579 | [(set_attr "type" "fp")]) | |
3580 | ||
3581 | (define_insn "" | |
cd2b37d9 RK |
3582 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3583 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 3584 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3585 | "fnabs %0,%1" |
3586 | [(set_attr "type" "fp")]) | |
3587 | ||
ca7f5001 RK |
3588 | (define_expand "addsf3" |
3589 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3590 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
3591 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 3592 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
3593 | "") |
3594 | ||
3595 | (define_insn "" | |
cd2b37d9 RK |
3596 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3597 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3598 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3599 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3600 | "fadds %0,%1,%2" |
ca7f5001 RK |
3601 | [(set_attr "type" "fp")]) |
3602 | ||
3603 | (define_insn "" | |
3604 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3605 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3606 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3607 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3608 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
3609 | [(set_attr "type" "fp")]) |
3610 | ||
3611 | (define_expand "subsf3" | |
3612 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3613 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
3614 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 3615 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
3616 | "") |
3617 | ||
3618 | (define_insn "" | |
3619 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3620 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
3621 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3622 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3623 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
3624 | [(set_attr "type" "fp")]) |
3625 | ||
ca7f5001 | 3626 | (define_insn "" |
cd2b37d9 RK |
3627 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3628 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
3629 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3630 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3631 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
3632 | [(set_attr "type" "fp")]) |
3633 | ||
3634 | (define_expand "mulsf3" | |
3635 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3636 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
3637 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 3638 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
3639 | "") |
3640 | ||
3641 | (define_insn "" | |
3642 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3643 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3644 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3645 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3646 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
3647 | [(set_attr "type" "fp")]) |
3648 | ||
ca7f5001 | 3649 | (define_insn "" |
cd2b37d9 RK |
3650 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3651 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3652 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3653 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3654 | "{fm|fmul} %0,%1,%2" |
0780f386 | 3655 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 3656 | |
ca7f5001 RK |
3657 | (define_expand "divsf3" |
3658 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3659 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
3660 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 3661 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
3662 | "") |
3663 | ||
3664 | (define_insn "" | |
cd2b37d9 RK |
3665 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3666 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
3667 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3668 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3669 | "fdivs %0,%1,%2" |
ca7f5001 RK |
3670 | [(set_attr "type" "sdiv")]) |
3671 | ||
3672 | (define_insn "" | |
3673 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3674 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
3675 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3676 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3677 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 3678 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
3679 | |
3680 | (define_insn "" | |
cd2b37d9 RK |
3681 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3682 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3683 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3684 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 3685 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3686 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
3687 | [(set_attr "type" "fp")]) |
3688 | ||
3689 | (define_insn "" | |
3690 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3691 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3692 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3693 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 3694 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3695 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 3696 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3697 | |
3698 | (define_insn "" | |
cd2b37d9 RK |
3699 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3700 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3701 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3702 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 3703 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3704 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
3705 | [(set_attr "type" "fp")]) |
3706 | ||
3707 | (define_insn "" | |
3708 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3709 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3710 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3711 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 3712 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3713 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 3714 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3715 | |
3716 | (define_insn "" | |
cd2b37d9 RK |
3717 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3718 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3719 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3720 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 3721 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3722 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
3723 | [(set_attr "type" "fp")]) |
3724 | ||
3725 | (define_insn "" | |
3726 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3727 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3728 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3729 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 3730 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3731 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 3732 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3733 | |
3734 | (define_insn "" | |
cd2b37d9 RK |
3735 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3736 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3737 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3738 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 3739 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3740 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
3741 | [(set_attr "type" "fp")]) |
3742 | ||
3743 | (define_insn "" | |
3744 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3745 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3746 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3747 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 3748 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3749 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 3750 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 3751 | |
ca7f5001 RK |
3752 | (define_expand "sqrtsf2" |
3753 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3754 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 3755 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
3756 | "") |
3757 | ||
3758 | (define_insn "" | |
3759 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3760 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3761 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT" |
ca7f5001 RK |
3762 | "fsqrts %0,%1" |
3763 | [(set_attr "type" "ssqrt")]) | |
3764 | ||
3765 | (define_insn "" | |
3766 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3767 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3768 | "TARGET_POWER2 && TARGET_HARD_FLOAT" |
ca7f5001 RK |
3769 | "fsqrt %0,%1" |
3770 | [(set_attr "type" "dsqrt")]) | |
3771 | ||
94d7001a RK |
3772 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
3773 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
3774 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
3775 | ;; combine. |
3776 | (define_expand "maxsf3" | |
3777 | [(set (match_dup 3) | |
3778 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
3779 | (match_operand:SF 2 "gpc_reg_operand" ""))) | |
3780 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
3781 | (if_then_else:SF (ge (match_dup 3) | |
3782 | (const_int 0)) | |
3783 | (match_dup 1) | |
3784 | (match_dup 2)))] | |
d14a6d05 | 3785 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3786 | " |
3787 | { operands[3] = gen_reg_rtx (SFmode); }") | |
2f607b94 | 3788 | |
8e871c05 RK |
3789 | (define_split |
3790 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3791 | (smax:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
f63184ac | 3792 | (match_operand:SF 2 "gpc_reg_operand" ""))) |
8e871c05 | 3793 | (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 3794 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3795 | [(set (match_dup 3) |
3796 | (minus:SF (match_dup 1) (match_dup 2))) | |
a81bd72f | 3797 | (set (match_dup 0) |
8e871c05 RK |
3798 | (if_then_else:SF (ge (match_dup 3) |
3799 | (const_int 0)) | |
3800 | (match_dup 1) | |
3801 | (match_dup 2)))] | |
3802 | "") | |
2f607b94 | 3803 | |
8e871c05 RK |
3804 | (define_expand "minsf3" |
3805 | [(set (match_dup 3) | |
3806 | (minus:SF (match_operand:SF 2 "gpc_reg_operand" "") | |
3807 | (match_operand:SF 1 "gpc_reg_operand" ""))) | |
3808 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
3809 | (if_then_else:SF (ge (match_dup 3) | |
3810 | (const_int 0)) | |
3811 | (match_dup 1) | |
3812 | (match_dup 2)))] | |
d14a6d05 | 3813 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3814 | " |
3815 | { operands[3] = gen_reg_rtx (SFmode); }") | |
2f607b94 | 3816 | |
8e871c05 RK |
3817 | (define_split |
3818 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3819 | (smin:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
f63184ac | 3820 | (match_operand:SF 2 "gpc_reg_operand" ""))) |
8e871c05 | 3821 | (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 3822 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3823 | [(set (match_dup 3) |
3824 | (minus:SF (match_dup 2) (match_dup 1))) | |
a81bd72f | 3825 | (set (match_dup 0) |
8e871c05 RK |
3826 | (if_then_else:SF (ge (match_dup 3) |
3827 | (const_int 0)) | |
3828 | (match_dup 1) | |
3829 | (match_dup 2)))] | |
3830 | "") | |
2f607b94 | 3831 | |
94d7001a | 3832 | (define_expand "movsfcc" |
0ad91047 | 3833 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 3834 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
3835 | (match_operand:SF 2 "gpc_reg_operand" "") |
3836 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 3837 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
3838 | " |
3839 | { | |
3840 | rtx temp, op0, op1; | |
3841 | enum rtx_code code = GET_CODE (operands[1]); | |
3842 | if (! rs6000_compare_fp_p) | |
3843 | FAIL; | |
3844 | switch (code) | |
3845 | { | |
3846 | case GE: case EQ: case NE: | |
3847 | op0 = rs6000_compare_op0; | |
3848 | op1 = rs6000_compare_op1; | |
3849 | break; | |
3850 | case GT: | |
3851 | op0 = rs6000_compare_op1; | |
3852 | op1 = rs6000_compare_op0; | |
3853 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
3854 | break; | |
3855 | case LE: | |
3856 | op0 = rs6000_compare_op1; | |
3857 | op1 = rs6000_compare_op0; | |
3858 | break; | |
3859 | case LT: | |
3860 | op0 = rs6000_compare_op0; | |
3861 | op1 = rs6000_compare_op1; | |
3862 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
3863 | break; | |
3864 | default: | |
3865 | FAIL; | |
3866 | } | |
3867 | if (GET_MODE (rs6000_compare_op0) == DFmode) | |
3868 | { | |
3869 | temp = gen_reg_rtx (DFmode); | |
3870 | emit_insn (gen_subdf3 (temp, op0, op1)); | |
3871 | emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3])); | |
3872 | if (code == EQ) | |
3873 | { | |
3874 | emit_insn (gen_negdf2 (temp, temp)); | |
3875 | emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3])); | |
3876 | } | |
a6c2a102 | 3877 | else if (code == NE) |
94d7001a RK |
3878 | { |
3879 | emit_insn (gen_negdf2 (temp, temp)); | |
3880 | emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0])); | |
3881 | } | |
3882 | } | |
3883 | else | |
3884 | { | |
3885 | temp = gen_reg_rtx (SFmode); | |
3886 | emit_insn (gen_subsf3 (temp, op0, op1)); | |
3887 | emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3])); | |
3888 | if (code == EQ) | |
3889 | { | |
3890 | emit_insn (gen_negsf2 (temp, temp)); | |
3891 | emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3])); | |
3892 | } | |
a6c2a102 | 3893 | else if (code == NE) |
94d7001a RK |
3894 | { |
3895 | emit_insn (gen_negsf2 (temp, temp)); | |
3896 | emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0])); | |
3897 | } | |
3898 | } | |
3899 | DONE; | |
3900 | }") | |
d56d506a | 3901 | |
94d7001a | 3902 | (define_insn "fselsfsf4" |
8e871c05 RK |
3903 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3904 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
3905 | (const_int 0)) | |
3906 | (match_operand:SF 2 "gpc_reg_operand" "f") | |
3907 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3908 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3909 | "fsel %0,%1,%2,%3" |
3910 | [(set_attr "type" "fp")]) | |
2f607b94 | 3911 | |
94d7001a RK |
3912 | (define_insn "fseldfsf4" |
3913 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3914 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
3915 | (const_int 0)) | |
3916 | (match_operand:SF 2 "gpc_reg_operand" "f") | |
3917 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3918 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
3919 | "fsel %0,%1,%2,%3" |
3920 | [(set_attr "type" "fp")]) | |
d56d506a | 3921 | |
1fd4e8c1 | 3922 | (define_insn "negdf2" |
cd2b37d9 RK |
3923 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3924 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3925 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3926 | "fneg %0,%1" |
3927 | [(set_attr "type" "fp")]) | |
3928 | ||
3929 | (define_insn "absdf2" | |
cd2b37d9 RK |
3930 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3931 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3932 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3933 | "fabs %0,%1" |
3934 | [(set_attr "type" "fp")]) | |
3935 | ||
3936 | (define_insn "" | |
cd2b37d9 RK |
3937 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3938 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 3939 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3940 | "fnabs %0,%1" |
3941 | [(set_attr "type" "fp")]) | |
3942 | ||
3943 | (define_insn "adddf3" | |
cd2b37d9 RK |
3944 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3945 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3946 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3947 | "TARGET_HARD_FLOAT" |
ca7f5001 | 3948 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
3949 | [(set_attr "type" "fp")]) |
3950 | ||
3951 | (define_insn "subdf3" | |
cd2b37d9 RK |
3952 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3953 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
3954 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3955 | "TARGET_HARD_FLOAT" |
ca7f5001 | 3956 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
3957 | [(set_attr "type" "fp")]) |
3958 | ||
3959 | (define_insn "muldf3" | |
cd2b37d9 RK |
3960 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3961 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3962 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3963 | "TARGET_HARD_FLOAT" |
ca7f5001 | 3964 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 3965 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3966 | |
3967 | (define_insn "divdf3" | |
cd2b37d9 RK |
3968 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3969 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
3970 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3971 | "TARGET_HARD_FLOAT" |
ca7f5001 | 3972 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 3973 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
3974 | |
3975 | (define_insn "" | |
cd2b37d9 RK |
3976 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3977 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3978 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
3979 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 3980 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 3981 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 3982 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3983 | |
3984 | (define_insn "" | |
cd2b37d9 RK |
3985 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3986 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3987 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
3988 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 3989 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 3990 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 3991 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3992 | |
3993 | (define_insn "" | |
cd2b37d9 RK |
3994 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3995 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3996 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
3997 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 3998 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 3999 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 4000 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4001 | |
4002 | (define_insn "" | |
cd2b37d9 RK |
4003 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4004 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4005 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4006 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 4007 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 4008 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 4009 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
4010 | |
4011 | (define_insn "sqrtdf2" | |
4012 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4013 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4014 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4015 | "fsqrt %0,%1" |
4016 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 4017 | |
94d7001a RK |
4018 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4019 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4020 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 | 4021 | ;; combine. |
b77dfefc | 4022 | |
8e871c05 RK |
4023 | (define_expand "maxdf3" |
4024 | [(set (match_dup 3) | |
4025 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4026 | (match_operand:DF 2 "gpc_reg_operand" ""))) | |
4027 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
4028 | (if_then_else:DF (ge (match_dup 3) | |
4029 | (const_int 0)) | |
4030 | (match_dup 1) | |
4031 | (match_dup 2)))] | |
d14a6d05 | 4032 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4033 | " |
4034 | { operands[3] = gen_reg_rtx (DFmode); }") | |
b77dfefc | 4035 | |
8e871c05 RK |
4036 | (define_split |
4037 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4038 | (smax:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
f63184ac | 4039 | (match_operand:DF 2 "gpc_reg_operand" ""))) |
8e871c05 | 4040 | (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 4041 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4042 | [(set (match_dup 3) |
4043 | (minus:DF (match_dup 1) (match_dup 2))) | |
a81bd72f | 4044 | (set (match_dup 0) |
8e871c05 RK |
4045 | (if_then_else:DF (ge (match_dup 3) |
4046 | (const_int 0)) | |
4047 | (match_dup 1) | |
4048 | (match_dup 2)))] | |
4049 | "") | |
b77dfefc | 4050 | |
8e871c05 RK |
4051 | (define_expand "mindf3" |
4052 | [(set (match_dup 3) | |
4053 | (minus:DF (match_operand:DF 2 "gpc_reg_operand" "") | |
4054 | (match_operand:DF 1 "gpc_reg_operand" ""))) | |
4055 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
4056 | (if_then_else:DF (ge (match_dup 3) | |
4057 | (const_int 0)) | |
4058 | (match_dup 1) | |
4059 | (match_dup 2)))] | |
d14a6d05 | 4060 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4061 | " |
4062 | { operands[3] = gen_reg_rtx (DFmode); }") | |
b77dfefc | 4063 | |
8e871c05 RK |
4064 | (define_split |
4065 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4066 | (smin:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
f63184ac | 4067 | (match_operand:DF 2 "gpc_reg_operand" ""))) |
8e871c05 | 4068 | (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 4069 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4070 | [(set (match_dup 3) |
4071 | (minus:DF (match_dup 2) (match_dup 1))) | |
a81bd72f | 4072 | (set (match_dup 0) |
8e871c05 RK |
4073 | (if_then_else:DF (ge (match_dup 3) |
4074 | (const_int 0)) | |
4075 | (match_dup 1) | |
4076 | (match_dup 2)))] | |
4077 | "") | |
b77dfefc | 4078 | |
94d7001a | 4079 | (define_expand "movdfcc" |
0ad91047 | 4080 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 4081 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4082 | (match_operand:DF 2 "gpc_reg_operand" "") |
4083 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 4084 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
4085 | " |
4086 | { | |
4087 | rtx temp, op0, op1; | |
4088 | enum rtx_code code = GET_CODE (operands[1]); | |
4089 | if (! rs6000_compare_fp_p) | |
4090 | FAIL; | |
4091 | switch (code) | |
4092 | { | |
4093 | case GE: case EQ: case NE: | |
4094 | op0 = rs6000_compare_op0; | |
4095 | op1 = rs6000_compare_op1; | |
4096 | break; | |
4097 | case GT: | |
4098 | op0 = rs6000_compare_op1; | |
4099 | op1 = rs6000_compare_op0; | |
4100 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
4101 | break; | |
4102 | case LE: | |
4103 | op0 = rs6000_compare_op1; | |
4104 | op1 = rs6000_compare_op0; | |
4105 | break; | |
4106 | case LT: | |
4107 | op0 = rs6000_compare_op0; | |
4108 | op1 = rs6000_compare_op1; | |
4109 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
4110 | break; | |
4111 | default: | |
4112 | FAIL; | |
4113 | } | |
4114 | if (GET_MODE (rs6000_compare_op0) == DFmode) | |
4115 | { | |
4116 | temp = gen_reg_rtx (DFmode); | |
4117 | emit_insn (gen_subdf3 (temp, op0, op1)); | |
4118 | emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3])); | |
4119 | if (code == EQ) | |
4120 | { | |
4121 | emit_insn (gen_negdf2 (temp, temp)); | |
4122 | emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3])); | |
4123 | } | |
a6c2a102 | 4124 | else if (code == NE) |
94d7001a RK |
4125 | { |
4126 | emit_insn (gen_negdf2 (temp, temp)); | |
4127 | emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0])); | |
4128 | } | |
4129 | } | |
4130 | else | |
4131 | { | |
4132 | temp = gen_reg_rtx (SFmode); | |
4133 | emit_insn (gen_subsf3 (temp, op0, op1)); | |
4134 | emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3])); | |
4135 | if (code == EQ) | |
4136 | { | |
4137 | emit_insn (gen_negsf2 (temp, temp)); | |
4138 | emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3])); | |
4139 | } | |
a6c2a102 | 4140 | else if (code == NE) |
94d7001a RK |
4141 | { |
4142 | emit_insn (gen_negsf2 (temp, temp)); | |
4143 | emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0])); | |
4144 | } | |
4145 | } | |
4146 | DONE; | |
4147 | }") | |
d56d506a | 4148 | |
94d7001a | 4149 | (define_insn "fseldfdf4" |
8e871c05 RK |
4150 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4151 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
4152 | (const_int 0)) | |
4153 | (match_operand:DF 2 "gpc_reg_operand" "f") | |
4154 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4155 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4156 | "fsel %0,%1,%2,%3" |
4157 | [(set_attr "type" "fp")]) | |
d56d506a | 4158 | |
94d7001a RK |
4159 | (define_insn "fselsfdf4" |
4160 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4161 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
4162 | (const_int 0)) | |
4163 | (match_operand:DF 2 "gpc_reg_operand" "f") | |
4164 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
4165 | "TARGET_PPC_GFXOPT" | |
4166 | "fsel %0,%1,%2,%3" | |
4167 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4168 | \f |
4169 | ;; Conversions to and from floating-point. | |
802a0058 | 4170 | |
1fd4e8c1 | 4171 | (define_expand "floatsidf2" |
802a0058 MM |
4172 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
4173 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
4174 | (use (match_dup 2)) | |
4175 | (use (match_dup 3)) | |
208c89ce | 4176 | (clobber (match_dup 4)) |
a7df97e6 | 4177 | (clobber (match_dup 5)) |
802a0058 | 4178 | (clobber (reg:DF 76))])] |
31bfaa0b | 4179 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4180 | " |
4181 | { | |
802a0058 MM |
4182 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
4183 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); | |
208c89ce | 4184 | operands[4] = gen_reg_rtx (SImode); |
a7df97e6 | 4185 | operands[5] = gen_reg_rtx (Pmode); |
1fd4e8c1 RK |
4186 | }") |
4187 | ||
802a0058 MM |
4188 | (define_insn "*floatsidf2_internal" |
4189 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
4190 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
4191 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
4192 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
208c89ce | 4193 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
a260abc9 | 4194 | (clobber (match_operand 5 "gpc_reg_operand" "=b")) |
802a0058 | 4195 | (clobber (reg:DF 76))] |
31bfaa0b | 4196 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 4197 | "#" |
a7df97e6 | 4198 | [(set_attr "length" "24")]) |
802a0058 MM |
4199 | |
4200 | (define_split | |
dbe3df29 | 4201 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
4202 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
4203 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
4204 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
208c89ce | 4205 | (clobber (match_operand:SI 4 "gpc_reg_operand" "")) |
a260abc9 | 4206 | (clobber (match_operand 5 "gpc_reg_operand" "")) |
802a0058 | 4207 | (clobber (reg:DF 76))] |
31bfaa0b | 4208 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 4209 | [(set (match_dup 4) |
208c89ce | 4210 | (xor:SI (match_dup 1) |
a7df97e6 MM |
4211 | (match_dup 6))) |
4212 | (set (match_dup 5) | |
4213 | (unspec [(const_int 0)] 11)) | |
4214 | (set (match_dup 7) | |
4215 | (unspec [(match_dup 4) | |
4216 | (match_dup 5)] 12)) ;; low word | |
4217 | (set (match_dup 7) | |
4218 | (unspec [(match_dup 2) | |
4219 | (match_dup 5) | |
4220 | (match_dup 7)] 13)) ;; high word | |
802a0058 | 4221 | (set (match_dup 0) |
a7df97e6 MM |
4222 | (unspec [(match_dup 7) |
4223 | (match_dup 5)] 14)) | |
802a0058 MM |
4224 | (set (match_dup 0) |
4225 | (minus:DF (match_dup 0) | |
4226 | (match_dup 3)))] | |
208c89ce MM |
4227 | " |
4228 | { | |
5f59ecb7 | 4229 | operands[6] = GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff); |
39403d82 | 4230 | operands[7] = gen_rtx_REG (DFmode, FPMEM_REGNUM); |
208c89ce | 4231 | }") |
802a0058 MM |
4232 | |
4233 | (define_expand "floatunssidf2" | |
4234 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4235 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
4236 | (use (match_dup 2)) | |
4237 | (use (match_dup 3)) | |
a7df97e6 | 4238 | (clobber (match_dup 4)) |
802a0058 | 4239 | (clobber (reg:DF 76))])] |
31bfaa0b | 4240 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4241 | " |
4242 | { | |
802a0058 MM |
4243 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
4244 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode)); | |
a7df97e6 | 4245 | operands[4] = gen_reg_rtx (Pmode); |
1fd4e8c1 RK |
4246 | }") |
4247 | ||
802a0058 MM |
4248 | (define_insn "*floatunssidf2_internal" |
4249 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
4250 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
4251 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
4252 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
a260abc9 | 4253 | (clobber (match_operand 4 "gpc_reg_operand" "=b")) |
802a0058 | 4254 | (clobber (reg:DF 76))] |
31bfaa0b | 4255 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 4256 | "#" |
a7df97e6 | 4257 | [(set_attr "length" "20")]) |
802a0058 MM |
4258 | |
4259 | (define_split | |
4260 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4261 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
4262 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
4263 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
955fc2e7 | 4264 | (clobber (match_operand 4 "gpc_reg_operand" "")) |
802a0058 | 4265 | (clobber (reg:DF 76))] |
31bfaa0b | 4266 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 4267 | [(set (match_dup 4) |
a7df97e6 MM |
4268 | (unspec [(const_int 0)] 11)) |
4269 | (set (match_dup 5) | |
4270 | (unspec [(match_dup 1) | |
4271 | (match_dup 4)] 12)) ;; low word | |
4272 | (set (match_dup 5) | |
4273 | (unspec [(match_dup 2) | |
4274 | (match_dup 4) | |
4275 | (match_dup 5)] 13)) ;; high word | |
802a0058 | 4276 | (set (match_dup 0) |
a7df97e6 | 4277 | (unspec [(match_dup 5) |
955fc2e7 | 4278 | (match_dup 4)] 14)) |
802a0058 MM |
4279 | (set (match_dup 0) |
4280 | (minus:DF (match_dup 0) | |
4281 | (match_dup 3)))] | |
39403d82 | 4282 | "operands[5] = gen_rtx_REG (DFmode, FPMEM_REGNUM);") |
802a0058 | 4283 | |
a7df97e6 MM |
4284 | ;; Load up scratch register with base address + offset if needed |
4285 | (define_insn "*floatsidf2_loadaddr" | |
a260abc9 | 4286 | [(set (match_operand 0 "gpc_reg_operand" "=b") |
a7df97e6 MM |
4287 | (unspec [(const_int 0)] 11))] |
4288 | "TARGET_HARD_FLOAT" | |
4289 | "* | |
4290 | { | |
4291 | if (rs6000_fpmem_offset > 32760) | |
4292 | { | |
4293 | rtx xop[3]; | |
4294 | ||
4295 | xop[0] = operands[0]; | |
4296 | xop[1] = (frame_pointer_needed) ? frame_pointer_rtx : stack_pointer_rtx; | |
170e0690 | 4297 | xop[2] = GEN_INT ((rs6000_fpmem_offset >> 16) + ((rs6000_fpmem_offset & 0x8000) >> 15)); |
538bb158 | 4298 | output_asm_insn (\"{cau|addis} %0,%1,%2\", xop); |
a7df97e6 | 4299 | } |
a7df97e6 MM |
4300 | |
4301 | return \"\"; | |
4302 | }" | |
4303 | [(set_attr "length" "4")]) | |
802a0058 MM |
4304 | |
4305 | (define_insn "*floatsidf2_store1" | |
4306 | [(set (reg:DF 76) | |
4307 | (unspec [(match_operand:SI 0 "gpc_reg_operand" "r") | |
a260abc9 DE |
4308 | (match_operand 1 "gpc_reg_operand" "b")] 12))] |
4309 | "TARGET_HARD_FLOAT" | |
802a0058 | 4310 | "* |
dbe3df29 | 4311 | { |
a7df97e6 MM |
4312 | rtx indx; |
4313 | ||
4314 | if (rs6000_fpmem_offset > 32760) | |
4315 | indx = operands[1]; | |
4316 | else if (frame_pointer_needed) | |
4317 | indx = frame_pointer_rtx; | |
4318 | else | |
4319 | indx = stack_pointer_rtx; | |
4320 | ||
c5c76735 JL |
4321 | operands[2] |
4322 | = gen_rtx_MEM (SImode, | |
4323 | plus_constant (indx, | |
4324 | (((rs6000_fpmem_offset & 0xffff) ^ 0x8000) | |
4325 | - 0x8000) | |
4326 | + ((WORDS_BIG_ENDIAN != 0) * 4))); | |
c283c989 | 4327 | |
a7df97e6 | 4328 | return \"{st|stw} %0,%2\"; |
802a0058 MM |
4329 | }" |
4330 | [(set_attr "type" "store")]) | |
4331 | ||
4332 | (define_insn "*floatsidf2_store2" | |
4333 | [(set (reg:DF 76) | |
4334 | (unspec [(match_operand:SI 0 "gpc_reg_operand" "r") | |
a260abc9 | 4335 | (match_operand 1 "gpc_reg_operand" "b") |
a7df97e6 | 4336 | (reg:DF 76)] 13))] |
a260abc9 | 4337 | "TARGET_HARD_FLOAT" |
802a0058 MM |
4338 | "* |
4339 | { | |
a7df97e6 MM |
4340 | rtx indx; |
4341 | ||
4342 | if (rs6000_fpmem_offset > 32760) | |
4343 | indx = operands[1]; | |
4344 | else if (frame_pointer_needed) | |
4345 | indx = frame_pointer_rtx; | |
4346 | else | |
4347 | indx = stack_pointer_rtx; | |
4348 | ||
c5c76735 JL |
4349 | operands[2] |
4350 | = gen_rtx_MEM (SImode, | |
4351 | plus_constant (indx, | |
4352 | (((rs6000_fpmem_offset & 0xffff) ^ 0x8000) | |
4353 | - 0x8000) | |
4354 | + ((WORDS_BIG_ENDIAN == 0) * 4))); | |
802a0058 | 4355 | |
a7df97e6 | 4356 | return \"{st|stw} %0,%2\"; |
802a0058 MM |
4357 | }" |
4358 | [(set_attr "type" "store")]) | |
4359 | ||
4360 | (define_insn "*floatsidf2_load" | |
4361 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4362 | (unspec [(reg:DF 76) | |
a260abc9 DE |
4363 | (match_operand 1 "gpc_reg_operand" "b")] 14))] |
4364 | "TARGET_HARD_FLOAT" | |
802a0058 MM |
4365 | "* |
4366 | { | |
a7df97e6 | 4367 | rtx indx; |
f6968f59 | 4368 | HOST_WIDE_INT offset = rs6000_fpmem_offset; |
a7df97e6 MM |
4369 | |
4370 | if (rs6000_fpmem_offset > 32760) | |
f6968f59 MM |
4371 | { |
4372 | indx = operands[1]; | |
170e0690 | 4373 | offset = (((offset & 0xffff) ^ 0x8000) - 0x8000); |
f6968f59 | 4374 | } |
a7df97e6 MM |
4375 | else if (frame_pointer_needed) |
4376 | indx = frame_pointer_rtx; | |
4377 | else | |
4378 | indx = stack_pointer_rtx; | |
4379 | ||
c5c76735 | 4380 | operands[2] = gen_rtx_MEM (SImode, plus_constant (indx, offset)); |
802a0058 | 4381 | |
a7df97e6 | 4382 | return \"lfd %0,%2\"; |
802a0058 MM |
4383 | }" |
4384 | [(set_attr "type" "fpload")]) | |
1fd4e8c1 | 4385 | |
1fd4e8c1 | 4386 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
4387 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
4388 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
4389 | (clobber (match_dup 2)) | |
a7df97e6 MM |
4390 | (clobber (match_dup 3)) |
4391 | (clobber (match_dup 4))])] | |
d14a6d05 | 4392 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4393 | " |
4394 | { | |
31bfaa0b | 4395 | if (! TARGET_POWER2 && ! TARGET_POWERPC) |
8ffd9c51 RK |
4396 | { |
4397 | emit_insn (gen_trunc_call (operands[0], operands[1], | |
39403d82 | 4398 | gen_rtx_SYMBOL_REF (Pmode, RS6000_ITRUNC))); |
8ffd9c51 RK |
4399 | DONE; |
4400 | } | |
802a0058 MM |
4401 | |
4402 | operands[2] = gen_reg_rtx (DImode); | |
a7df97e6 | 4403 | operands[3] = gen_reg_rtx (Pmode); |
39403d82 | 4404 | operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM); |
1fd4e8c1 RK |
4405 | }") |
4406 | ||
802a0058 MM |
4407 | (define_insn "*fix_truncdfsi2_internal" |
4408 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4409 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
4410 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) | |
a260abc9 | 4411 | (clobber (match_operand 3 "gpc_reg_operand" "=b")) |
802a0058 MM |
4412 | (clobber (reg:DI 76))] |
4413 | "TARGET_HARD_FLOAT" | |
4414 | "#" | |
4415 | [(set_attr "length" "12")]) | |
4416 | ||
4417 | (define_split | |
4418 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4419 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
4420 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) | |
a260abc9 | 4421 | (clobber (match_operand 3 "gpc_reg_operand" "")) |
802a0058 MM |
4422 | (clobber (reg:DI 76))] |
4423 | "TARGET_HARD_FLOAT" | |
a8af0321 RH |
4424 | [(clobber (match_dup 2)) |
4425 | (set (subreg:SI (match_dup 2) 0) | |
31bfaa0b | 4426 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
802a0058 | 4427 | (set (match_dup 3) |
a7df97e6 MM |
4428 | (unspec [(const_int 0)] 11)) |
4429 | (set (match_dup 4) | |
802a0058 | 4430 | (unspec [(match_dup 2) |
a7df97e6 | 4431 | (match_dup 3)] 15)) |
802a0058 | 4432 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
a7df97e6 MM |
4433 | (unspec [(match_dup 4) |
4434 | (match_dup 3)] 16))] | |
39403d82 | 4435 | "operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM);") |
802a0058 | 4436 | |
802a0058 MM |
4437 | (define_insn "*fix_truncdfsi2_store" |
4438 | [(set (reg:DI 76) | |
4439 | (unspec [(match_operand:DI 0 "gpc_reg_operand" "f") | |
a260abc9 | 4440 | (match_operand 1 "gpc_reg_operand" "b")] 15))] |
802a0058 MM |
4441 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
4442 | "* | |
4443 | { | |
a7df97e6 MM |
4444 | rtx indx; |
4445 | ||
4446 | if (rs6000_fpmem_offset > 32760) | |
4447 | indx = operands[1]; | |
4448 | else if (frame_pointer_needed) | |
4449 | indx = frame_pointer_rtx; | |
4450 | else | |
4451 | indx = stack_pointer_rtx; | |
4452 | ||
39403d82 | 4453 | operands[2] = gen_rtx_MEM (DFmode, |
c5c76735 JL |
4454 | plus_constant (indx, |
4455 | (((rs6000_fpmem_offset & 0xffff) | |
4456 | ^ 0x8000) - 0x8000))); | |
802a0058 | 4457 | |
1427100a | 4458 | return \"stfd %0,%2\"; |
802a0058 MM |
4459 | }" |
4460 | [(set_attr "type" "fpstore")]) | |
4461 | ||
4462 | (define_insn "*fix_truncdfsi2_load" | |
4463 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4464 | (unspec [(reg:DI 76) | |
a260abc9 | 4465 | (match_operand 1 "gpc_reg_operand" "b")] 16))] |
802a0058 MM |
4466 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
4467 | "* | |
4468 | { | |
a7df97e6 MM |
4469 | rtx indx; |
4470 | ||
4471 | if (rs6000_fpmem_offset > 32760) | |
4472 | indx = operands[1]; | |
4473 | else if (frame_pointer_needed) | |
4474 | indx = frame_pointer_rtx; | |
4475 | else | |
4476 | indx = stack_pointer_rtx; | |
4477 | ||
c5c76735 JL |
4478 | operands[2] |
4479 | = gen_rtx_MEM (DFmode, | |
4480 | plus_constant (indx, | |
4481 | (((rs6000_fpmem_offset & 0xffff) ^ 0x8000) | |
4482 | - 0x8000) | |
4483 | + ((WORDS_BIG_ENDIAN) ? 4 : 0))); | |
802a0058 | 4484 | |
a7df97e6 | 4485 | return \"{l|lwz} %0,%2\"; |
802a0058 MM |
4486 | }" |
4487 | [(set_attr "type" "load")]) | |
4488 | ||
1fd4e8c1 | 4489 | (define_expand "fixuns_truncdfsi2" |
cd2b37d9 | 4490 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
b542afe9 | 4491 | (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] |
d14a6d05 | 4492 | "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4493 | " |
4494 | { | |
4495 | emit_insn (gen_trunc_call (operands[0], operands[1], | |
39403d82 | 4496 | gen_rtx_SYMBOL_REF (Pmode, RS6000_UITRUNC))); |
1fd4e8c1 RK |
4497 | DONE; |
4498 | }") | |
4499 | ||
1fd4e8c1 RK |
4500 | (define_expand "trunc_call" |
4501 | [(parallel [(set (match_operand:SI 0 "" "") | |
b542afe9 | 4502 | (fix:SI (match_operand:DF 1 "" ""))) |
1fd4e8c1 | 4503 | (use (match_operand:SI 2 "" ""))])] |
d14a6d05 | 4504 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4505 | " |
4506 | { | |
4507 | rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]); | |
4508 | rtx first = XVECEXP (insns, 0, 0); | |
4509 | rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1); | |
4510 | ||
39403d82 | 4511 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, |
c5c76735 | 4512 | REG_NOTES (first)); |
39403d82 | 4513 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last)); |
1fd4e8c1 RK |
4514 | |
4515 | emit_insn (insns); | |
4516 | DONE; | |
4517 | }") | |
4518 | ||
4519 | (define_expand "trunc_call_rtl" | |
cd2b37d9 | 4520 | [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" "")) |
1fd4e8c1 RK |
4521 | (use (reg:DF 33)) |
4522 | (parallel [(set (reg:SI 3) | |
4523 | (call (mem:SI (match_operand 2 "" "")) (const_int 0))) | |
4697a36c | 4524 | (use (const_int 0)) |
1fd4e8c1 | 4525 | (clobber (scratch:SI))]) |
cd2b37d9 | 4526 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 4527 | (reg:SI 3))] |
d14a6d05 | 4528 | "TARGET_HARD_FLOAT" |
1fd4e8c1 | 4529 | " |
7e69e155 | 4530 | { |
1fd4e8c1 RK |
4531 | rs6000_trunc_used = 1; |
4532 | }") | |
a473029f | 4533 | |
a260abc9 | 4534 | (define_insn "*fctiwz" |
31bfaa0b DE |
4535 | [(set (subreg:SI (match_operand:DI 0 "gpc_reg_operand" "=f") 0) |
4536 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a260abc9 DE |
4537 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
4538 | "{fcirz|fctiwz} %0,%1" | |
4539 | [(set_attr "type" "fp")]) | |
4540 | ||
a473029f RK |
4541 | (define_insn "floatdidf2" |
4542 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4543 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4544 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
4545 | "fcfid %0,%1" |
4546 | [(set_attr "type" "fp")]) | |
4547 | ||
4548 | (define_insn "fix_truncdfdi2" | |
4549 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
4550 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4551 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
4552 | "fctidz %0,%1" |
4553 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4554 | \f |
4555 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
4556 | ;; of instructions. The & constraints are to prevent the register |
4557 | ;; allocator from allocating registers that overlap with the inputs | |
4558 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 4559 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 4560 | |
266eb58a | 4561 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
4562 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
4563 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
4564 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 4565 | "! TARGET_POWERPC64" |
0f645302 MM |
4566 | "* |
4567 | { | |
4568 | if (WORDS_BIG_ENDIAN) | |
4569 | return (GET_CODE (operands[2])) != CONST_INT | |
4570 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
4571 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
4572 | else | |
4573 | return (GET_CODE (operands[2])) != CONST_INT | |
4574 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
4575 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
4576 | }" | |
b19003d8 | 4577 | [(set_attr "length" "8")]) |
1fd4e8c1 | 4578 | |
266eb58a | 4579 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
4580 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
4581 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
4582 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 4583 | "! TARGET_POWERPC64" |
5502823b RK |
4584 | "* |
4585 | { | |
0f645302 MM |
4586 | if (WORDS_BIG_ENDIAN) |
4587 | return (GET_CODE (operands[1]) != CONST_INT) | |
4588 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
4589 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
4590 | else | |
4591 | return (GET_CODE (operands[1]) != CONST_INT) | |
4592 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
4593 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 4594 | }" |
ca7f5001 RK |
4595 | [(set_attr "length" "8")]) |
4596 | ||
266eb58a | 4597 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
4598 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
4599 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 4600 | "! TARGET_POWERPC64" |
5502823b RK |
4601 | "* |
4602 | { | |
4603 | return (WORDS_BIG_ENDIAN) | |
4604 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
4605 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
4606 | }" | |
ca7f5001 RK |
4607 | [(set_attr "length" "8")]) |
4608 | ||
8ffd9c51 RK |
4609 | (define_expand "mulsidi3" |
4610 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4611 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
4612 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 4613 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
4614 | " |
4615 | { | |
4616 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
4617 | { | |
39403d82 DE |
4618 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
4619 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 4620 | emit_insn (gen_mull_call ()); |
cf27b467 | 4621 | if (WORDS_BIG_ENDIAN) |
39403d82 | 4622 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
4623 | else |
4624 | { | |
4625 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 4626 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 4627 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 4628 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 4629 | } |
8ffd9c51 RK |
4630 | DONE; |
4631 | } | |
4632 | else if (TARGET_POWER) | |
4633 | { | |
4634 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
4635 | DONE; | |
4636 | } | |
4637 | }") | |
deb9225a | 4638 | |
8ffd9c51 | 4639 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 4640 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 4641 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 4642 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 4643 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 4644 | "TARGET_POWER" |
b19003d8 | 4645 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
4646 | [(set_attr "type" "imul") |
4647 | (set_attr "length" "8")]) | |
deb9225a | 4648 | |
f192bf8b | 4649 | (define_insn "*mulsidi3_no_mq" |
425c176f | 4650 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
4651 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
4652 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 4653 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
4654 | "* |
4655 | { | |
4656 | return (WORDS_BIG_ENDIAN) | |
4657 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
4658 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
4659 | }" | |
8ffd9c51 RK |
4660 | [(set_attr "type" "imul") |
4661 | (set_attr "length" "8")]) | |
deb9225a | 4662 | |
ebedb4dd MM |
4663 | (define_split |
4664 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4665 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
4666 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 4667 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
4668 | [(set (match_dup 3) |
4669 | (truncate:SI | |
4670 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
4671 | (sign_extend:DI (match_dup 2))) | |
4672 | (const_int 32)))) | |
4673 | (set (match_dup 4) | |
4674 | (mult:SI (match_dup 1) | |
4675 | (match_dup 2)))] | |
4676 | " | |
4677 | { | |
4678 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4679 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
4680 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
4681 | }") | |
4682 | ||
f192bf8b DE |
4683 | (define_expand "umulsidi3" |
4684 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4685 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
4686 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
4687 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
4688 | " | |
4689 | { | |
4690 | if (TARGET_POWER) | |
4691 | { | |
4692 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
4693 | DONE; | |
4694 | } | |
4695 | }") | |
4696 | ||
4697 | (define_insn "umulsidi3_mq" | |
4698 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
4699 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4700 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
4701 | (clobber (match_scratch:SI 3 "=q"))] | |
4702 | "TARGET_POWERPC && TARGET_POWER" | |
4703 | "* | |
4704 | { | |
4705 | return (WORDS_BIG_ENDIAN) | |
4706 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
4707 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
4708 | }" | |
4709 | [(set_attr "type" "imul") | |
4710 | (set_attr "length" "8")]) | |
4711 | ||
4712 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
4713 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
4714 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4715 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 4716 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
4717 | "* |
4718 | { | |
4719 | return (WORDS_BIG_ENDIAN) | |
4720 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
4721 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
4722 | }" | |
4723 | [(set_attr "type" "imul") | |
4724 | (set_attr "length" "8")]) | |
4725 | ||
ebedb4dd MM |
4726 | (define_split |
4727 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4728 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
4729 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 4730 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
4731 | [(set (match_dup 3) |
4732 | (truncate:SI | |
4733 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
4734 | (zero_extend:DI (match_dup 2))) | |
4735 | (const_int 32)))) | |
4736 | (set (match_dup 4) | |
4737 | (mult:SI (match_dup 1) | |
4738 | (match_dup 2)))] | |
4739 | " | |
4740 | { | |
4741 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4742 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
4743 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
4744 | }") | |
4745 | ||
8ffd9c51 RK |
4746 | (define_expand "smulsi3_highpart" |
4747 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4748 | (truncate:SI | |
4749 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
4750 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4751 | (sign_extend:DI | |
4752 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
4753 | (const_int 32))))] | |
4754 | "" | |
4755 | " | |
4756 | { | |
4757 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
4758 | { | |
39403d82 DE |
4759 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
4760 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 4761 | emit_insn (gen_mulh_call ()); |
39403d82 | 4762 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
4763 | DONE; |
4764 | } | |
4765 | else if (TARGET_POWER) | |
4766 | { | |
4767 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
4768 | DONE; | |
4769 | } | |
4770 | }") | |
deb9225a | 4771 | |
8ffd9c51 RK |
4772 | (define_insn "smulsi3_highpart_mq" |
4773 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4774 | (truncate:SI | |
fada905b MM |
4775 | (lshiftrt:DI (mult:DI (sign_extend:DI |
4776 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4777 | (sign_extend:DI | |
4778 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
4779 | (const_int 32)))) |
4780 | (clobber (match_scratch:SI 3 "=q"))] | |
4781 | "TARGET_POWER" | |
4782 | "mul %0,%1,%2" | |
4783 | [(set_attr "type" "imul")]) | |
deb9225a | 4784 | |
f192bf8b | 4785 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
4786 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4787 | (truncate:SI | |
fada905b MM |
4788 | (lshiftrt:DI (mult:DI (sign_extend:DI |
4789 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4790 | (sign_extend:DI | |
4791 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 4792 | (const_int 32))))] |
f192bf8b | 4793 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
4794 | "mulhw %0,%1,%2" |
4795 | [(set_attr "type" "imul")]) | |
deb9225a | 4796 | |
f192bf8b DE |
4797 | (define_expand "umulsi3_highpart" |
4798 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4799 | (truncate:SI | |
4800 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
4801 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
4802 | (zero_extend:DI | |
4803 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
4804 | (const_int 32))))] | |
4805 | "TARGET_POWERPC" | |
4806 | " | |
4807 | { | |
4808 | if (TARGET_POWER) | |
4809 | { | |
4810 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
4811 | DONE; | |
4812 | } | |
4813 | }") | |
4814 | ||
4815 | (define_insn "umulsi3_highpart_mq" | |
4816 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4817 | (truncate:SI | |
4818 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
4819 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4820 | (zero_extend:DI | |
4821 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
4822 | (const_int 32)))) | |
4823 | (clobber (match_scratch:SI 3 "=q"))] | |
4824 | "TARGET_POWERPC && TARGET_POWER" | |
4825 | "mulhwu %0,%1,%2" | |
4826 | [(set_attr "type" "imul")]) | |
4827 | ||
4828 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
4829 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4830 | (truncate:SI | |
4831 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
4832 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4833 | (zero_extend:DI | |
4834 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
4835 | (const_int 32))))] | |
f192bf8b | 4836 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
4837 | "mulhwu %0,%1,%2" |
4838 | [(set_attr "type" "imul")]) | |
4839 | ||
4840 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
4841 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
4842 | ;; why we have the strange constraints below. | |
4843 | (define_insn "ashldi3_power" | |
4844 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
4845 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
4846 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
4847 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
4848 | "TARGET_POWER" | |
4849 | "@ | |
4850 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
4851 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
4852 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
4853 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
4854 | [(set_attr "length" "8")]) | |
4855 | ||
4856 | (define_insn "lshrdi3_power" | |
47ad8c61 | 4857 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
4858 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
4859 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
4860 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
4861 | "TARGET_POWER" | |
4862 | "@ | |
47ad8c61 | 4863 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
4864 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
4865 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
4866 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
4867 | [(set_attr "length" "8")]) | |
4868 | ||
4869 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
4870 | ;; just handle shifts by constants. | |
4871 | (define_insn "ashrdi3_power" | |
7093ddee | 4872 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
4873 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
4874 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
4875 | (clobber (match_scratch:SI 3 "=X,q"))] | |
4876 | "TARGET_POWER" | |
4877 | "@ | |
4878 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
4879 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
4880 | [(set_attr "length" "8")]) | |
4881 | \f | |
4882 | ;; PowerPC64 DImode operations. | |
4883 | ||
4884 | (define_expand "adddi3" | |
4885 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4886 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
a260abc9 | 4887 | (match_operand:DI 2 "reg_or_cint_operand" "")))] |
266eb58a DE |
4888 | "" |
4889 | " | |
4890 | { | |
a260abc9 DE |
4891 | if (! TARGET_POWERPC64) |
4892 | { | |
4893 | if (non_short_cint_operand (operands[2], DImode)) | |
4894 | FAIL; | |
4895 | } | |
4896 | else | |
4897 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 4898 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 4899 | { |
677a9668 | 4900 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
4901 | ? operands[0] : gen_reg_rtx (DImode)); |
4902 | ||
4903 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; | |
4904 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
4905 | ||
4906 | if (low & 0x8000) | |
4907 | high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16; | |
4908 | ||
4909 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (high))); | |
4910 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); | |
4911 | DONE; | |
4912 | } | |
266eb58a DE |
4913 | }") |
4914 | ||
4915 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
4916 | ;; allowing register zero as source. | |
4917 | ||
a260abc9 | 4918 | (define_insn "*adddi3_internal1" |
266eb58a DE |
4919 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
4920 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 4921 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
4922 | "TARGET_POWERPC64" |
4923 | "@ | |
4924 | add %0,%1,%2 | |
4925 | addi %0,%1,%2 | |
4926 | addic %0,%1,%2 | |
802a0058 | 4927 | addis %0,%1,%v2") |
266eb58a | 4928 | |
a260abc9 | 4929 | (define_insn "*adddi3_internal2" |
29ae5b89 JL |
4930 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
4931 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
4932 | (match_operand:DI 2 "reg_or_short_operand" "r,I")) | |
266eb58a | 4933 | (const_int 0))) |
29ae5b89 | 4934 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a DE |
4935 | "TARGET_POWERPC64" |
4936 | "@ | |
4937 | add. %3,%1,%2 | |
29ae5b89 JL |
4938 | addic. %3,%1,%2" |
4939 | [(set_attr "type" "compare")]) | |
266eb58a | 4940 | |
a260abc9 | 4941 | (define_insn "*adddi3_internal3" |
29ae5b89 JL |
4942 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
4943 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
4944 | (match_operand:DI 2 "reg_or_short_operand" "r,I")) | |
266eb58a | 4945 | (const_int 0))) |
29ae5b89 | 4946 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
4947 | (plus:DI (match_dup 1) (match_dup 2)))] |
4948 | "TARGET_POWERPC64" | |
4949 | "@ | |
4950 | add. %0,%1,%2 | |
29ae5b89 JL |
4951 | addic. %0,%1,%2" |
4952 | [(set_attr "type" "compare")]) | |
266eb58a DE |
4953 | |
4954 | ;; Split an add that we can't do in one insn into two insns, each of which | |
4955 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
4956 | ;; add should be last in case the result gets used in an address. | |
4957 | ||
4958 | (define_split | |
4959 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4960 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
4961 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
4962 | "TARGET_POWERPC64" | |
4963 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
4964 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
4965 | " | |
4966 | { | |
e6ca2c17 DE |
4967 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; |
4968 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
266eb58a DE |
4969 | |
4970 | if (low & 0x8000) | |
e6ca2c17 | 4971 | high+=0x10000, low |= ((HOST_WIDE_INT) -1) << 16; |
266eb58a | 4972 | |
e6ca2c17 DE |
4973 | operands[3] = GEN_INT (high); |
4974 | operands[4] = GEN_INT (low); | |
266eb58a DE |
4975 | }") |
4976 | ||
4977 | (define_insn "one_cmpldi2" | |
4978 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4979 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
4980 | "TARGET_POWERPC64" | |
4981 | "nor %0,%1,%1") | |
4982 | ||
4983 | (define_insn "" | |
29ae5b89 JL |
4984 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
4985 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
266eb58a | 4986 | (const_int 0))) |
29ae5b89 | 4987 | (clobber (match_scratch:DI 2 "=r"))] |
266eb58a DE |
4988 | "TARGET_POWERPC64" |
4989 | "nor. %2,%1,%1" | |
29ae5b89 | 4990 | [(set_attr "type" "compare")]) |
266eb58a DE |
4991 | |
4992 | (define_insn "" | |
29ae5b89 JL |
4993 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
4994 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
266eb58a | 4995 | (const_int 0))) |
29ae5b89 | 4996 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
4997 | (not:DI (match_dup 1)))] |
4998 | "TARGET_POWERPC64" | |
d944f453 | 4999 | "nor. %0,%1,%1" |
266eb58a DE |
5000 | [(set_attr "type" "compare")]) |
5001 | ||
5002 | (define_insn "" | |
5003 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5004 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
5005 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
5006 | "TARGET_POWERPC64" | |
5007 | "@ | |
5008 | subf %0,%2,%1 | |
5009 | subfic %0,%2,%1") | |
5010 | ||
5011 | (define_insn "" | |
29ae5b89 JL |
5012 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5013 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5014 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5015 | (const_int 0))) |
29ae5b89 | 5016 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a DE |
5017 | "TARGET_POWERPC64" |
5018 | "subf. %3,%2,%1" | |
29ae5b89 | 5019 | [(set_attr "type" "compare")]) |
266eb58a DE |
5020 | |
5021 | (define_insn "" | |
29ae5b89 JL |
5022 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5023 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5024 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5025 | (const_int 0))) |
29ae5b89 | 5026 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5027 | (minus:DI (match_dup 1) (match_dup 2)))] |
5028 | "TARGET_POWERPC64" | |
5029 | "subf. %0,%2,%1" | |
5030 | [(set_attr "type" "compare")]) | |
5031 | ||
5032 | (define_expand "subdi3" | |
5033 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5034 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
5035 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
5036 | "" | |
5037 | " | |
5038 | { | |
5039 | if (GET_CODE (operands[2]) == CONST_INT) | |
5040 | { | |
5041 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
5042 | negate_rtx (DImode, operands[2]))); | |
5043 | DONE; | |
5044 | } | |
5045 | }") | |
5046 | ||
5047 | (define_insn "absdi2" | |
5048 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
5049 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
5050 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
5051 | "TARGET_POWERPC64" | |
a260abc9 | 5052 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0" |
266eb58a DE |
5053 | [(set_attr "length" "12")]) |
5054 | ||
5055 | (define_split | |
5056 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
5057 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
5058 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
5059 | "TARGET_POWERPC64 && reload_completed" | |
a260abc9 | 5060 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5061 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 5062 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
5063 | "") |
5064 | ||
19ba8161 | 5065 | (define_insn "*nabsdi2" |
266eb58a DE |
5066 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5067 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
5068 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
5069 | "TARGET_POWERPC64" | |
a260abc9 | 5070 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2" |
266eb58a DE |
5071 | [(set_attr "length" "12")]) |
5072 | ||
5073 | (define_split | |
5074 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
5075 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
5076 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
5077 | "TARGET_POWERPC64 && reload_completed" | |
a260abc9 | 5078 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5079 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 5080 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
5081 | "") |
5082 | ||
5083 | (define_expand "negdi2" | |
5084 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5085 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
5086 | "" | |
5087 | "") | |
5088 | ||
5089 | (define_insn "" | |
5090 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5091 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5092 | "TARGET_POWERPC64" | |
5093 | "neg %0,%1") | |
5094 | ||
5095 | (define_insn "" | |
29ae5b89 JL |
5096 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5097 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
266eb58a | 5098 | (const_int 0))) |
29ae5b89 JL |
5099 | (clobber (match_scratch:DI 2 "=r"))] |
5100 | "TARGET_POWERPC64" | |
5101 | "neg. %2,%1" | |
5102 | [(set_attr "type" "compare")]) | |
815cdc52 | 5103 | |
29ae5b89 JL |
5104 | (define_insn "" |
5105 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
5106 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
815cdc52 | 5107 | (const_int 0))) |
29ae5b89 | 5108 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
815cdc52 | 5109 | (neg:DI (match_dup 1)))] |
29ae5b89 JL |
5110 | "TARGET_POWERPC64" |
5111 | "neg. %0,%1" | |
5112 | [(set_attr "type" "compare")]) | |
266eb58a DE |
5113 | |
5114 | (define_insn "ffsdi2" | |
5115 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5116 | (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5117 | "TARGET_POWERPC64" | |
5118 | "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64" | |
5119 | [(set_attr "length" "16")]) | |
5120 | ||
5121 | (define_insn "muldi3" | |
5122 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5123 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5124 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
5125 | "TARGET_POWERPC64" | |
5126 | "mulld %0,%1,%2" | |
3cb999d8 | 5127 | [(set_attr "type" "lmul")]) |
266eb58a DE |
5128 | |
5129 | (define_insn "smuldi3_highpart" | |
5130 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5131 | (truncate:DI | |
5132 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
5133 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5134 | (sign_extend:TI | |
5135 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
5136 | (const_int 64))))] | |
5137 | "TARGET_POWERPC64" | |
5138 | "mulhd %0,%1,%2" | |
3cb999d8 | 5139 | [(set_attr "type" "lmul")]) |
266eb58a DE |
5140 | |
5141 | (define_insn "umuldi3_highpart" | |
5142 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5143 | (truncate:DI | |
5144 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
5145 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5146 | (zero_extend:TI | |
5147 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
5148 | (const_int 64))))] | |
5149 | "TARGET_POWERPC64" | |
5150 | "mulhdu %0,%1,%2" | |
3cb999d8 | 5151 | [(set_attr "type" "lmul")]) |
266eb58a DE |
5152 | |
5153 | (define_expand "divdi3" | |
5154 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5155 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5156 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
5157 | "TARGET_POWERPC64" | |
5158 | " | |
5159 | { | |
5160 | if (GET_CODE (operands[2]) == CONST_INT | |
5161 | && exact_log2 (INTVAL (operands[2])) >= 0) | |
5162 | ; | |
5163 | else | |
5164 | operands[2] = force_reg (DImode, operands[2]); | |
5165 | }") | |
5166 | ||
5167 | (define_expand "moddi3" | |
5168 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
5169 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
5170 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
5171 | "TARGET_POWERPC64" | |
5172 | " | |
5173 | { | |
5174 | int i = exact_log2 (INTVAL (operands[2])); | |
5175 | rtx temp1; | |
5176 | rtx temp2; | |
5177 | ||
5178 | if (GET_CODE (operands[2]) != CONST_INT || i < 0) | |
5179 | FAIL; | |
5180 | ||
5181 | temp1 = gen_reg_rtx (DImode); | |
5182 | temp2 = gen_reg_rtx (DImode); | |
5183 | ||
5184 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
5185 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
5186 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
5187 | DONE; | |
5188 | }") | |
5189 | ||
5190 | (define_insn "" | |
5191 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5192 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5193 | (match_operand:DI 2 "const_int_operand" "N")))] | |
5194 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" | |
5195 | "sradi %0,%1,%p2\;addze %0,%0" | |
5196 | [(set_attr "length" "8")]) | |
5197 | ||
5198 | (define_insn "" | |
29ae5b89 JL |
5199 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5200 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5201 | (match_operand:DI 2 "const_int_operand" "N")) | |
266eb58a | 5202 | (const_int 0))) |
29ae5b89 | 5203 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5204 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" |
29ae5b89 | 5205 | "sradi %3,%1,%p2\;addze. %3,%3" |
266eb58a | 5206 | [(set_attr "type" "compare") |
29ae5b89 | 5207 | (set_attr "length" "8")]) |
266eb58a DE |
5208 | |
5209 | (define_insn "" | |
29ae5b89 JL |
5210 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5211 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5212 | (match_operand:DI 2 "const_int_operand" "N")) | |
266eb58a | 5213 | (const_int 0))) |
29ae5b89 | 5214 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5215 | (div:DI (match_dup 1) (match_dup 2)))] |
5216 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" | |
29ae5b89 | 5217 | "sradi %0,%1,%p2\;addze. %0,%0" |
266eb58a | 5218 | [(set_attr "type" "compare") |
29ae5b89 | 5219 | (set_attr "length" "8")]) |
266eb58a DE |
5220 | |
5221 | (define_insn "" | |
5222 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5223 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a260abc9 | 5224 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
5225 | "TARGET_POWERPC64" |
5226 | "divd %0,%1,%2" | |
3cb999d8 | 5227 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
5228 | |
5229 | (define_insn "udivdi3" | |
5230 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5231 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5232 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
5233 | "TARGET_POWERPC64" | |
5234 | "divdu %0,%1,%2" | |
3cb999d8 | 5235 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
5236 | |
5237 | (define_insn "rotldi3" | |
5238 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5239 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5240 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
5241 | "TARGET_POWERPC64" | |
a66078ee | 5242 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 5243 | |
a260abc9 | 5244 | (define_insn "*rotldi3_internal2" |
29ae5b89 JL |
5245 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5246 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5247 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5248 | (const_int 0))) |
29ae5b89 | 5249 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5250 | "TARGET_POWERPC64" |
29ae5b89 JL |
5251 | "rld%I2cl. %3,%1,%H2,0" |
5252 | [(set_attr "type" "delayed_compare")]) | |
266eb58a | 5253 | |
a260abc9 | 5254 | (define_insn "*rotldi3_internal3" |
29ae5b89 JL |
5255 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5256 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5257 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5258 | (const_int 0))) |
29ae5b89 | 5259 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5260 | (rotate:DI (match_dup 1) (match_dup 2)))] |
5261 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5262 | "rld%I2cl. %0,%1,%H2,0" |
5263 | [(set_attr "type" "delayed_compare")]) | |
266eb58a | 5264 | |
a260abc9 DE |
5265 | (define_insn "*rotldi3_internal4" |
5266 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5267 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5268 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
5269 | (match_operand:DI 3 "mask64_operand" "S")))] | |
5270 | "TARGET_POWERPC64" | |
5271 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
5272 | ||
5273 | (define_insn "*rotldi3_internal5" | |
29ae5b89 | 5274 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
a260abc9 | 5275 | (compare:CC (and:DI |
29ae5b89 JL |
5276 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5277 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
5278 | (match_operand:DI 3 "mask64_operand" "S")) | |
a260abc9 | 5279 | (const_int 0))) |
29ae5b89 | 5280 | (clobber (match_scratch:DI 4 "=r"))] |
a260abc9 | 5281 | "TARGET_POWERPC64" |
29ae5b89 JL |
5282 | "rld%I2c%B3. %4,%1,%H2,%S3" |
5283 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
5284 | |
5285 | (define_insn "*rotldi3_internal6" | |
29ae5b89 | 5286 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
a260abc9 | 5287 | (compare:CC (and:DI |
29ae5b89 JL |
5288 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5289 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
5290 | (match_operand:DI 3 "mask64_operand" "S")) | |
a260abc9 | 5291 | (const_int 0))) |
29ae5b89 | 5292 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
5293 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
5294 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5295 | "rld%I2c%B3. %0,%1,%H2,%S3" |
5296 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
5297 | |
5298 | (define_insn "*rotldi3_internal7" | |
5299 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5300 | (zero_extend:DI | |
5301 | (subreg:QI | |
5302 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5303 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
5304 | "TARGET_POWERPC64" | |
5305 | "rld%I2cl %0,%1,%H2,56") | |
5306 | ||
5307 | (define_insn "*rotldi3_internal8" | |
29ae5b89 | 5308 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
a260abc9 DE |
5309 | (compare:CC (zero_extend:DI |
5310 | (subreg:QI | |
29ae5b89 JL |
5311 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5312 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 5313 | (const_int 0))) |
29ae5b89 | 5314 | (clobber (match_scratch:DI 3 "=r"))] |
a260abc9 | 5315 | "TARGET_POWERPC64" |
29ae5b89 JL |
5316 | "rld%I2cl. %3,%1,%H2,56" |
5317 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
5318 | |
5319 | (define_insn "*rotldi3_internal9" | |
29ae5b89 | 5320 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
a260abc9 DE |
5321 | (compare:CC (zero_extend:DI |
5322 | (subreg:QI | |
29ae5b89 JL |
5323 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5324 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 5325 | (const_int 0))) |
29ae5b89 | 5326 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
5327 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
5328 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5329 | "rld%I2cl. %0,%1,%H2,56" |
5330 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
5331 | |
5332 | (define_insn "*rotldi3_internal10" | |
5333 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5334 | (zero_extend:DI | |
5335 | (subreg:HI | |
5336 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5337 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
5338 | "TARGET_POWERPC64" | |
5339 | "rld%I2cl %0,%1,%H2,48") | |
5340 | ||
5341 | (define_insn "*rotldi3_internal11" | |
29ae5b89 | 5342 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
a260abc9 DE |
5343 | (compare:CC (zero_extend:DI |
5344 | (subreg:HI | |
29ae5b89 JL |
5345 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5346 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 5347 | (const_int 0))) |
29ae5b89 | 5348 | (clobber (match_scratch:DI 3 "=r"))] |
a260abc9 | 5349 | "TARGET_POWERPC64" |
29ae5b89 JL |
5350 | "rld%I2cl. %3,%1,%H2,48" |
5351 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
5352 | |
5353 | (define_insn "*rotldi3_internal12" | |
29ae5b89 | 5354 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
a260abc9 DE |
5355 | (compare:CC (zero_extend:DI |
5356 | (subreg:HI | |
29ae5b89 JL |
5357 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5358 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 5359 | (const_int 0))) |
29ae5b89 | 5360 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
5361 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
5362 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5363 | "rld%I2cl. %0,%1,%H2,48" |
5364 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
5365 | |
5366 | (define_insn "*rotldi3_internal13" | |
5367 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5368 | (zero_extend:DI | |
5369 | (subreg:SI | |
5370 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5371 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
5372 | "TARGET_POWERPC64" | |
5373 | "rld%I2cl %0,%1,%H2,32") | |
5374 | ||
5375 | (define_insn "*rotldi3_internal14" | |
29ae5b89 | 5376 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
a260abc9 DE |
5377 | (compare:CC (zero_extend:DI |
5378 | (subreg:SI | |
29ae5b89 JL |
5379 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5380 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 5381 | (const_int 0))) |
29ae5b89 | 5382 | (clobber (match_scratch:DI 3 "=r"))] |
a260abc9 | 5383 | "TARGET_POWERPC64" |
29ae5b89 JL |
5384 | "rld%I2cl. %3,%1,%H2,32" |
5385 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
5386 | |
5387 | (define_insn "*rotldi3_internal15" | |
29ae5b89 | 5388 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
a260abc9 DE |
5389 | (compare:CC (zero_extend:DI |
5390 | (subreg:SI | |
29ae5b89 JL |
5391 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5392 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 5393 | (const_int 0))) |
29ae5b89 | 5394 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
5395 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
5396 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5397 | "rld%I2cl. %0,%1,%H2,32" |
5398 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 | 5399 | |
266eb58a DE |
5400 | (define_expand "ashldi3" |
5401 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5402 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5403 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
5404 | "TARGET_POWERPC64 || TARGET_POWER" | |
5405 | " | |
5406 | { | |
5407 | if (TARGET_POWERPC64) | |
5408 | ; | |
5409 | else if (TARGET_POWER) | |
5410 | { | |
5411 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
5412 | DONE; | |
5413 | } | |
5414 | else | |
5415 | FAIL; | |
5416 | }") | |
5417 | ||
5418 | (define_insn "" | |
5419 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5420 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5421 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
5422 | "TARGET_POWERPC64" | |
a66078ee | 5423 | "sld%I2 %0,%1,%H2" |
266eb58a DE |
5424 | [(set_attr "length" "8")]) |
5425 | ||
5426 | (define_insn "" | |
29ae5b89 JL |
5427 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5428 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5429 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5430 | (const_int 0))) |
29ae5b89 | 5431 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5432 | "TARGET_POWERPC64" |
29ae5b89 JL |
5433 | "sld%I2. %3,%1,%H2" |
5434 | [(set_attr "type" "delayed_compare")]) | |
5435 | ||
266eb58a | 5436 | (define_insn "" |
29ae5b89 JL |
5437 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5438 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5439 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5440 | (const_int 0))) |
29ae5b89 | 5441 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5442 | (ashift:DI (match_dup 1) (match_dup 2)))] |
5443 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5444 | "sld%I2. %0,%1,%H2" |
5445 | [(set_attr "type" "delayed_compare")]) | |
266eb58a | 5446 | |
3cb999d8 DE |
5447 | (define_insn "" |
5448 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5449 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5450 | (match_operand:SI 2 "const_int_operand" "i")) | |
5451 | (match_operand:DI 3 "mask64_operand" "S")))] | |
5452 | "((GET_CODE (operands[3]) == CONST_INT | |
5453 | ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1" | |
5454 | "rldic %0,%1,%H2,%S3") | |
5455 | ||
5456 | (define_insn "" | |
5457 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
5458 | (compare:CC | |
5459 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5460 | (match_operand:SI 2 "const_int_operand" "i")) | |
5461 | (match_operand:DI 3 "mask64_operand" "S")) | |
5462 | (const_int 0))) | |
5463 | (clobber (match_scratch:DI 4 "=r"))] | |
5464 | "((GET_CODE (operands[3]) == CONST_INT | |
5465 | ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1" | |
5466 | "rldic. %0,%1,%H2,%S3" | |
5467 | [(set_attr "type" "delayed_compare")]) | |
5468 | ||
5469 | (define_insn "" | |
5470 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") | |
5471 | (compare:CC | |
5472 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5473 | (match_operand:SI 2 "const_int_operand" "i")) | |
5474 | (match_operand:DI 3 "mask64_operand" "S")) | |
5475 | (const_int 0))) | |
5476 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5477 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
5478 | "((GET_CODE (operands[3]) == CONST_INT | |
5479 | ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1" | |
5480 | "rldic. %0,%1,%H2,%S3" | |
5481 | [(set_attr "type" "delayed_compare")]) | |
5482 | ||
266eb58a DE |
5483 | (define_expand "lshrdi3" |
5484 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5485 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5486 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
5487 | "TARGET_POWERPC64 || TARGET_POWER" | |
5488 | " | |
5489 | { | |
5490 | if (TARGET_POWERPC64) | |
5491 | ; | |
5492 | else if (TARGET_POWER) | |
5493 | { | |
5494 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
5495 | DONE; | |
5496 | } | |
5497 | else | |
5498 | FAIL; | |
5499 | }") | |
5500 | ||
5501 | (define_insn "" | |
5502 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5503 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5504 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
5505 | "TARGET_POWERPC64" | |
a66078ee | 5506 | "srd%I2 %0,%1,%H2") |
266eb58a DE |
5507 | |
5508 | (define_insn "" | |
29ae5b89 JL |
5509 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5510 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5511 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
5512 | (const_int 0))) | |
5513 | (clobber (match_scratch:DI 3 "=r"))] | |
5514 | "TARGET_POWERPC64" | |
5515 | "srd%I2. %3,%1,%H2" | |
5516 | [(set_attr "type" "delayed_compare")]) | |
266eb58a | 5517 | |
29ae5b89 JL |
5518 | (define_insn "" |
5519 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
5520 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5521 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5522 | (const_int 0))) |
29ae5b89 JL |
5523 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
5524 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
5525 | "TARGET_POWERPC64" | |
5526 | "srd%I2. %0,%1,%H2" | |
5527 | [(set_attr "type" "delayed_compare")]) | |
266eb58a DE |
5528 | |
5529 | (define_expand "ashrdi3" | |
5530 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5531 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5532 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
5533 | "TARGET_POWERPC64 || TARGET_POWER" | |
5534 | " | |
5535 | { | |
5536 | if (TARGET_POWERPC64) | |
5537 | ; | |
5538 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
5539 | { | |
5540 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
5541 | DONE; | |
5542 | } | |
5543 | else | |
5544 | FAIL; | |
5545 | }") | |
5546 | ||
5547 | (define_insn "" | |
5548 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5549 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5550 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
5551 | "TARGET_POWERPC64" | |
375490e0 | 5552 | "srad%I2 %0,%1,%H2") |
266eb58a DE |
5553 | |
5554 | (define_insn "" | |
29ae5b89 JL |
5555 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5556 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5557 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5558 | (const_int 0))) |
29ae5b89 | 5559 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5560 | "TARGET_POWERPC64" |
29ae5b89 JL |
5561 | "srad%I2. %3,%1,%H2" |
5562 | [(set_attr "type" "delayed_compare")]) | |
266eb58a DE |
5563 | |
5564 | (define_insn "" | |
29ae5b89 JL |
5565 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5566 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5567 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5568 | (const_int 0))) |
29ae5b89 | 5569 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5570 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
5571 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5572 | "srad%I2. %0,%1,%H2" |
5573 | [(set_attr "type" "delayed_compare")]) | |
815cdc52 | 5574 | |
29ae5b89 JL |
5575 | (define_insn "anddi3" |
5576 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") | |
5577 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5578 | (match_operand:DI 2 "and64_operand" "?r,S,K,J"))) | |
5579 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] | |
6ffc8580 | 5580 | "TARGET_POWERPC64" |
266eb58a DE |
5581 | "@ |
5582 | and %0,%1,%2 | |
29ae5b89 JL |
5583 | rldic%B2 %0,%1,0,%S2 |
5584 | andi. %0,%1,%b2 | |
5585 | andis. %0,%1,%u2") | |
266eb58a | 5586 | |
a260abc9 | 5587 | (define_insn "*anddi3_internal2" |
29ae5b89 JL |
5588 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") |
5589 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5590 | (match_operand:DI 2 "and64_operand" "r,K,J,S")) | |
266eb58a | 5591 | (const_int 0))) |
29ae5b89 | 5592 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
6ffc8580 | 5593 | "TARGET_POWERPC64" |
266eb58a DE |
5594 | "@ |
5595 | and. %3,%1,%2 | |
6ffc8580 MM |
5596 | andi. %3,%1,%b2 |
5597 | andis. %3,%1,%u2 | |
29ae5b89 JL |
5598 | rldic%B2. %3,%1,0,%S2" |
5599 | [(set_attr "type" "compare,compare,compare,delayed_compare")]) | |
266eb58a | 5600 | |
a260abc9 | 5601 | (define_insn "*anddi3_internal3" |
29ae5b89 JL |
5602 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") |
5603 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5604 | (match_operand:DI 2 "and64_operand" "r,K,J,S")) | |
266eb58a | 5605 | (const_int 0))) |
29ae5b89 JL |
5606 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
5607 | (and:DI (match_dup 1) (match_dup 2)))] | |
6ffc8580 | 5608 | "TARGET_POWERPC64" |
266eb58a DE |
5609 | "@ |
5610 | and. %0,%1,%2 | |
6ffc8580 MM |
5611 | andi. %0,%1,%b2 |
5612 | andis. %0,%1,%u2 | |
9615f239 | 5613 | rldic%B2. %0,%1,0,%S2" |
29ae5b89 | 5614 | [(set_attr "type" "compare,compare,compare,delayed_compare")]) |
266eb58a | 5615 | |
a260abc9 | 5616 | (define_expand "iordi3" |
266eb58a | 5617 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 DE |
5618 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
5619 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
266eb58a | 5620 | "TARGET_POWERPC64" |
266eb58a DE |
5621 | " |
5622 | { | |
a260abc9 | 5623 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 5624 | && ! logical_operand (operands[2], DImode)) |
266eb58a | 5625 | { |
a260abc9 | 5626 | HOST_WIDE_INT value = INTVAL (operands[2]); |
677a9668 | 5627 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 5628 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 5629 | |
a260abc9 DE |
5630 | emit_insn (gen_iordi3 (tmp, operands[1], |
5631 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
5632 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
5633 | DONE; | |
266eb58a | 5634 | } |
266eb58a DE |
5635 | }") |
5636 | ||
a260abc9 | 5637 | (define_insn "*iordi3_internal1" |
266eb58a DE |
5638 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
5639 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r") | |
5640 | (match_operand:DI 2 "logical_operand" "r,K,J")))] | |
5641 | "TARGET_POWERPC64" | |
5642 | "@ | |
5643 | or %0,%1,%2 | |
5644 | ori %0,%1,%b2 | |
5645 | oris %0,%1,%u2") | |
5646 | ||
a260abc9 | 5647 | (define_insn "*iordi3_internal2" |
29ae5b89 JL |
5648 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5649 | (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5650 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5651 | (const_int 0))) |
29ae5b89 | 5652 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5653 | "TARGET_POWERPC64" |
29ae5b89 JL |
5654 | "or. %3,%1,%2" |
5655 | [(set_attr "type" "compare")]) | |
266eb58a | 5656 | |
a260abc9 | 5657 | (define_insn "*iordi3_internal3" |
29ae5b89 JL |
5658 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5659 | (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5660 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5661 | (const_int 0))) |
29ae5b89 | 5662 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5663 | (ior:DI (match_dup 1) (match_dup 2)))] |
5664 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5665 | "or. %0,%1,%2" |
5666 | [(set_attr "type" "compare")]) | |
266eb58a DE |
5667 | |
5668 | ;; Split an IOR that we can't do in one insn into two insns, each of which | |
5669 | ;; does one 16-bit part. This is used by combine. | |
5670 | ||
5671 | (define_split | |
5672 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5673 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5674 | (match_operand:DI 2 "non_logical_cint_operand" "")))] | |
5675 | "TARGET_POWERPC64" | |
5676 | [(set (match_dup 0) (ior:DI (match_dup 1) (match_dup 3))) | |
5677 | (set (match_dup 0) (ior:DI (match_dup 0) (match_dup 4)))] | |
5678 | " | |
5679 | { | |
3a598fbe | 5680 | operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); |
89e9f3a8 | 5681 | operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
266eb58a | 5682 | }") |
1fd4e8c1 | 5683 | |
a260abc9 DE |
5684 | (define_expand "xordi3" |
5685 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5686 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5687 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
5688 | "TARGET_POWERPC64" | |
5689 | " | |
5690 | { | |
5691 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 5692 | && ! logical_operand (operands[2], DImode)) |
a260abc9 DE |
5693 | { |
5694 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 5695 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
5696 | ? operands[0] : gen_reg_rtx (DImode)); |
5697 | ||
5698 | emit_insn (gen_xordi3 (tmp, operands[1], | |
5699 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
5700 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
5701 | DONE; | |
5702 | } | |
5703 | }") | |
5704 | ||
5705 | (define_insn "*xordi3_internal1" | |
266eb58a DE |
5706 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
5707 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r") | |
5708 | (match_operand:DI 2 "logical_operand" "r,K,J")))] | |
5709 | "TARGET_POWERPC64" | |
1fd4e8c1 | 5710 | "@ |
266eb58a DE |
5711 | xor %0,%1,%2 |
5712 | xori %0,%1,%b2 | |
5713 | xoris %0,%1,%u2") | |
1fd4e8c1 | 5714 | |
a260abc9 | 5715 | (define_insn "*xordi3_internal2" |
29ae5b89 JL |
5716 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5717 | (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5718 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5719 | (const_int 0))) |
29ae5b89 | 5720 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5721 | "TARGET_POWERPC64" |
29ae5b89 JL |
5722 | "xor. %3,%1,%2" |
5723 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 5724 | |
a260abc9 | 5725 | (define_insn "*xordi3_internal3" |
29ae5b89 JL |
5726 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5727 | (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5728 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5729 | (const_int 0))) |
29ae5b89 | 5730 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5731 | (xor:DI (match_dup 1) (match_dup 2)))] |
5732 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5733 | "xor. %0,%1,%2" |
5734 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 5735 | |
266eb58a DE |
5736 | ;; Split an XOR that we can't do in one insn into two insns, each of which |
5737 | ;; does one 16-bit part. This is used by combine. | |
5738 | ||
5739 | (define_split | |
5740 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
a260abc9 DE |
5741 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") |
5742 | (match_operand:DI 2 "non_logical_cint_operand" "")))] | |
266eb58a DE |
5743 | "TARGET_POWERPC64" |
5744 | [(set (match_dup 0) (xor:DI (match_dup 1) (match_dup 3))) | |
5745 | (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 4)))] | |
5746 | " | |
5747 | { | |
a260abc9 | 5748 | operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); |
89e9f3a8 | 5749 | operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
1fd4e8c1 RK |
5750 | }") |
5751 | ||
a260abc9 | 5752 | (define_insn "*eqvdi3_internal1" |
266eb58a DE |
5753 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
5754 | (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5755 | (match_operand:DI 2 "gpc_reg_operand" "r"))))] | |
5756 | "TARGET_POWERPC64" | |
5757 | "eqv %0,%1,%2") | |
a473029f | 5758 | |
a260abc9 | 5759 | (define_insn "*eqvdi3_internal2" |
29ae5b89 JL |
5760 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5761 | (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5762 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
815cdc52 | 5763 | (const_int 0))) |
29ae5b89 JL |
5764 | (clobber (match_scratch:DI 3 "=r"))] |
5765 | "TARGET_POWERPC64" | |
5766 | "eqv. %3,%1,%2" | |
5767 | [(set_attr "type" "compare")]) | |
a473029f | 5768 | |
a260abc9 | 5769 | (define_insn "*eqvdi3_internal3" |
29ae5b89 JL |
5770 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5771 | (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5772 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
266eb58a | 5773 | (const_int 0))) |
29ae5b89 | 5774 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a | 5775 | (not:DI (xor:DI (match_dup 1) (match_dup 2))))] |
29ae5b89 JL |
5776 | "TARGET_POWERPC64" |
5777 | "eqv. %0,%1,%2" | |
5778 | [(set_attr "type" "compare")]) | |
266eb58a | 5779 | |
a260abc9 | 5780 | (define_insn "*andcdi3_internal1" |
a473029f | 5781 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5782 | (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) |
5783 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
a473029f | 5784 | "TARGET_POWERPC64" |
266eb58a | 5785 | "andc %0,%2,%1") |
a473029f | 5786 | |
a260abc9 | 5787 | (define_insn "*andcdi3_internal2" |
29ae5b89 JL |
5788 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5789 | (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
5790 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5791 | (const_int 0))) |
29ae5b89 | 5792 | (clobber (match_scratch:DI 3 "=r"))] |
a473029f | 5793 | "TARGET_POWERPC64" |
29ae5b89 JL |
5794 | "andc. %3,%2,%1" |
5795 | [(set_attr "type" "compare")]) | |
a473029f | 5796 | |
a260abc9 | 5797 | (define_insn "*andcdi3_internal3" |
29ae5b89 JL |
5798 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5799 | (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
5800 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5801 | (const_int 0))) |
29ae5b89 | 5802 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a | 5803 | (and:DI (not:DI (match_dup 1)) (match_dup 2)))] |
a473029f | 5804 | "TARGET_POWERPC64" |
29ae5b89 JL |
5805 | "andc. %0,%2,%1" |
5806 | [(set_attr "type" "compare")]) | |
a473029f | 5807 | |
a260abc9 | 5808 | (define_insn "*iorcdi3_internal1" |
a473029f | 5809 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5810 | (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) |
5811 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
a473029f | 5812 | "TARGET_POWERPC64" |
266eb58a | 5813 | "orc %0,%2,%1") |
a473029f | 5814 | |
a260abc9 | 5815 | (define_insn "*iorcdi3_inernal2" |
29ae5b89 JL |
5816 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5817 | (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
5818 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5819 | (const_int 0))) |
29ae5b89 | 5820 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5821 | "TARGET_POWERPC64" |
29ae5b89 JL |
5822 | "orc. %3,%2,%1" |
5823 | [(set_attr "type" "compare")]) | |
266eb58a | 5824 | |
a260abc9 | 5825 | (define_insn "*iorcdi3_internal3" |
29ae5b89 JL |
5826 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5827 | (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
5828 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5829 | (const_int 0))) |
29ae5b89 | 5830 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5831 | (ior:DI (not:DI (match_dup 1)) (match_dup 2)))] |
5832 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5833 | "orc. %0,%2,%1" |
5834 | [(set_attr "type" "compare")]) | |
266eb58a | 5835 | |
a260abc9 | 5836 | (define_insn "*nanddi3_internal1" |
a473029f | 5837 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
29ae5b89 | 5838 | (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) |
266eb58a | 5839 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))] |
a473029f | 5840 | "TARGET_POWERPC64" |
266eb58a | 5841 | "nand %0,%1,%2") |
a473029f | 5842 | |
a260abc9 | 5843 | (define_insn "*nanddi3_internal2" |
29ae5b89 JL |
5844 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5845 | (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5846 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
266eb58a | 5847 | (const_int 0))) |
29ae5b89 | 5848 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5849 | "TARGET_POWERPC64" |
29ae5b89 JL |
5850 | "nand. %3,%1,%2" |
5851 | [(set_attr "type" "compare")]) | |
266eb58a | 5852 | |
a260abc9 | 5853 | (define_insn "*nanddi3_internal3" |
29ae5b89 JL |
5854 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5855 | (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5856 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
266eb58a | 5857 | (const_int 0))) |
29ae5b89 | 5858 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5859 | (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))] |
5860 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5861 | "nand. %0,%1,%2" |
5862 | [(set_attr "type" "compare")]) | |
266eb58a | 5863 | |
a260abc9 | 5864 | (define_insn "*nordi3_internal1" |
a473029f | 5865 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
29ae5b89 | 5866 | (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) |
266eb58a | 5867 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))] |
a473029f | 5868 | "TARGET_POWERPC64" |
266eb58a | 5869 | "nor %0,%1,%2") |
a473029f | 5870 | |
29ae5b89 JL |
5871 | (define_insn "*nordi3_internal2" |
5872 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
5873 | (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5874 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
815cdc52 | 5875 | (const_int 0))) |
29ae5b89 JL |
5876 | (clobber (match_scratch:DI 3 "=r"))] |
5877 | "TARGET_POWERPC64" | |
5878 | "nor. %3,%1,%2" | |
5879 | [(set_attr "type" "compare")]) | |
a473029f | 5880 | |
a260abc9 | 5881 | (define_insn "*nordi3_internal3" |
29ae5b89 JL |
5882 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5883 | (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5884 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
a473029f | 5885 | (const_int 0))) |
29ae5b89 | 5886 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a | 5887 | (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))] |
a473029f | 5888 | "TARGET_POWERPC64" |
29ae5b89 JL |
5889 | "nor. %0,%1,%2" |
5890 | [(set_attr "type" "compare")]) | |
a473029f | 5891 | \f |
1fd4e8c1 | 5892 | ;; Now define ways of moving data around. |
4697a36c MM |
5893 | |
5894 | ;; Elf specific ways of loading addresses for non-PIC code. | |
5895 | ;; The output of this could be r0, but we limit it to base | |
5896 | ;; registers, since almost all uses of this will need it | |
5897 | ;; in a base register shortly. | |
5898 | (define_insn "elf_high" | |
52d3af72 | 5899 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
4697a36c | 5900 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 5901 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 5902 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
5903 | |
5904 | (define_insn "elf_low" | |
52d3af72 DE |
5905 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5906 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
4697a36c | 5907 | (match_operand 2 "" "")))] |
0ad91047 | 5908 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 5909 | "{cal|la} %0,%2@l(%1)") |
4697a36c | 5910 | |
766a866c MM |
5911 | ;; Set up a register with a value from the GOT table |
5912 | ||
5913 | (define_expand "movsi_got" | |
52d3af72 | 5914 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
766a866c MM |
5915 | (unspec [(match_operand:SI 1 "got_operand" "") |
5916 | (match_dup 2)] 8))] | |
58307bcd | 5917 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
5918 | " |
5919 | { | |
38c1f2d7 MM |
5920 | if (GET_CODE (operands[1]) == CONST) |
5921 | { | |
5922 | rtx offset = const0_rtx; | |
5923 | HOST_WIDE_INT value; | |
5924 | ||
5925 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
5926 | value = INTVAL (offset); | |
5927 | if (value != 0) | |
5928 | { | |
677a9668 | 5929 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
5930 | emit_insn (gen_movsi_got (tmp, operands[1])); |
5931 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
5932 | DONE; | |
5933 | } | |
5934 | } | |
5935 | ||
c4c40373 | 5936 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
5937 | }") |
5938 | ||
84f414bc | 5939 | (define_insn "*movsi_got_internal" |
52d3af72 | 5940 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
38c1f2d7 | 5941 | (unspec [(match_operand:SI 1 "got_no_const_operand" "") |
52d3af72 | 5942 | (match_operand:SI 2 "gpc_reg_operand" "b")] 8))] |
c81bebd7 | 5943 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
5944 | "{l|lwz} %0,%a1@got(%2)" |
5945 | [(set_attr "type" "load")]) | |
5946 | ||
b22b9b3e JL |
5947 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
5948 | ;; didn't get allocated to a hard register. | |
5949 | (define_split | |
52d3af72 | 5950 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
b22b9b3e JL |
5951 | (unspec [(match_operand:SI 1 "got_no_const_operand" "") |
5952 | (match_operand:SI 2 "memory_operand" "m")] 8))] | |
5953 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
5954 | && flag_pic == 1 | |
5955 | && (reload_in_progress || reload_completed)" | |
5956 | [(set (match_dup 0) (match_dup 2)) | |
5957 | (set (match_dup 0) (unspec [(match_dup 1)(match_dup 0)] 8))] | |
5958 | "") | |
5959 | ||
1fd4e8c1 RK |
5960 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
5961 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
5962 | ;; and this is even supposed to be faster, but it is simpler not to get | |
5963 | ;; integers in the TOC. | |
5964 | (define_expand "movsi" | |
5965 | [(set (match_operand:SI 0 "general_operand" "") | |
5966 | (match_operand:SI 1 "any_operand" ""))] | |
5967 | "" | |
5968 | " | |
5969 | { | |
5970 | if (GET_CODE (operands[0]) != REG) | |
5971 | operands[1] = force_reg (SImode, operands[1]); | |
5972 | ||
ef0e171b RK |
5973 | /* Convert a move of a CONST_DOUBLE into a CONST_INT */ |
5974 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
5975 | operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
5976 | ||
34792e82 | 5977 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 5978 | if (GET_CODE (operands[1]) == CONSTANT_P_RTX) |
34792e82 JL |
5979 | { |
5980 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
5981 | DONE; | |
5982 | } | |
5983 | ||
88228c4b MM |
5984 | /* Use default pattern for address of ELF small data */ |
5985 | if (TARGET_ELF | |
c81bebd7 | 5986 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
88228c4b | 5987 | && (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST) |
e98bb982 | 5988 | && small_data_operand (operands[1], SImode)) |
88228c4b | 5989 | { |
39403d82 | 5990 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
88228c4b MM |
5991 | DONE; |
5992 | } | |
5993 | ||
c81bebd7 | 5994 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
84f414bc | 5995 | && flag_pic == 1 && got_operand (operands[1], SImode)) |
766a866c MM |
5996 | { |
5997 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
5998 | DONE; | |
5999 | } | |
6000 | ||
677a9668 DE |
6001 | if (TARGET_ELF && TARGET_NO_TOC && ! TARGET_64BIT |
6002 | && ! flag_pic | |
4697a36c MM |
6003 | && CONSTANT_P (operands[1]) |
6004 | && GET_CODE (operands[1]) != HIGH | |
34792e82 | 6005 | && GET_CODE (operands[1]) != CONST_INT) |
4697a36c | 6006 | { |
677a9668 | 6007 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (SImode)); |
4697a36c | 6008 | |
b6c9286a MM |
6009 | /* If this is a function address on -mcall-aixdesc or -mcall-nt, |
6010 | convert it to the address of the descriptor. */ | |
6011 | if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) | |
6012 | && GET_CODE (operands[1]) == SYMBOL_REF | |
6013 | && XSTR (operands[1], 0)[0] == '.') | |
6014 | { | |
6015 | char *name = XSTR (operands[1], 0); | |
6016 | rtx new_ref; | |
6017 | while (*name == '.') | |
6018 | name++; | |
39403d82 | 6019 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); |
c5c76735 JL |
6020 | CONSTANT_POOL_ADDRESS_P (new_ref) |
6021 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
b6c9286a MM |
6022 | SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]); |
6023 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); | |
6024 | operands[1] = new_ref; | |
6025 | } | |
6026 | ||
4697a36c MM |
6027 | emit_insn (gen_elf_high (target, operands[1])); |
6028 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
6029 | DONE; | |
6030 | } | |
6031 | ||
b6c9286a MM |
6032 | if (GET_CODE (operands[1]) == CONST |
6033 | && DEFAULT_ABI == ABI_NT | |
677a9668 | 6034 | && ! side_effects_p (operands[0])) |
b6c9286a MM |
6035 | { |
6036 | rtx const_term = const0_rtx; | |
6037 | rtx sym = eliminate_constant_term (XEXP (operands[1], 0), &const_term); | |
6038 | if (sym && GET_CODE (const_term) == CONST_INT | |
6039 | && (GET_CODE (sym) == SYMBOL_REF || GET_CODE (sym) == LABEL_REF)) | |
6040 | { | |
354b734b | 6041 | unsigned HOST_WIDE_INT value = INTVAL (const_term); |
677a9668 DE |
6042 | int new_reg_p = (flag_expensive_optimizations && ! no_new_pseudos); |
6043 | rtx tmp1 = ((new_reg_p && value != 0) | |
6044 | ? gen_reg_rtx (SImode) : operands[0]); | |
354b734b MM |
6045 | |
6046 | emit_insn (gen_movsi (tmp1, sym)); | |
b6c9286a | 6047 | if (INTVAL (const_term) != 0) |
38c1f2d7 | 6048 | emit_insn (gen_addsi3 (operands[0], tmp1, GEN_INT (value))); |
b6c9286a MM |
6049 | DONE; |
6050 | } | |
6051 | else | |
a6c2a102 | 6052 | rs6000_fatal_bad_address (operands[1]); |
b6c9286a MM |
6053 | } |
6054 | ||
677a9668 | 6055 | if ((! TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT) |
b6c9286a | 6056 | && CONSTANT_P (operands[1]) |
4697a36c MM |
6057 | && GET_CODE (operands[1]) != CONST_INT |
6058 | && GET_CODE (operands[1]) != HIGH | |
78b8d850 | 6059 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])) |
b45863ec | 6060 | { |
d302f4f2 MM |
6061 | /* Emit a USE operation so that the constant isn't deleted if |
6062 | expensive optimizations are turned on because nobody | |
e0350319 MM |
6063 | references it. This should only be done for operands that |
6064 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
6065 | This should not be done for operands that contain LABEL_REFs. | |
6066 | For now, we just handle the obvious case. */ | |
6067 | if (GET_CODE (operands[1]) != LABEL_REF) | |
39403d82 | 6068 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); |
d302f4f2 | 6069 | |
30a4619d RK |
6070 | /* If we are to limit the number of things we put in the TOC and |
6071 | this is a symbol plus a constant we can add in one insn, | |
abc95ed3 | 6072 | just put the symbol in the TOC and add the constant. Don't do |
30a4619d RK |
6073 | this if reload is in progress. */ |
6074 | if (GET_CODE (operands[1]) == CONST | |
6075 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
6076 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
6077 | && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode) | |
6078 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF | |
6079 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
6080 | && ! side_effects_p (operands[0])) | |
6081 | { | |
6082 | rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0)); | |
6083 | rtx other = XEXP (XEXP (operands[1], 0), 1); | |
6084 | ||
6085 | emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other)); | |
6086 | DONE; | |
6087 | } | |
6088 | ||
b45863ec RK |
6089 | operands[1] = force_const_mem (SImode, operands[1]); |
6090 | if (! memory_address_p (SImode, XEXP (operands[1], 0)) | |
6091 | && ! reload_in_progress) | |
6092 | operands[1] = change_address (operands[1], SImode, | |
6093 | XEXP (operands[1], 0)); | |
6094 | } | |
1fd4e8c1 RK |
6095 | }") |
6096 | ||
6097 | (define_insn "" | |
a260abc9 | 6098 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h") |
9615f239 | 6099 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))] |
19d5775a RK |
6100 | "gpc_reg_operand (operands[0], SImode) |
6101 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 6102 | "@ |
deb9225a | 6103 | mr %0,%1 |
b9442c72 | 6104 | {cal|la} %0,%a1 |
ca7f5001 RK |
6105 | {l%U1%X1|lwz%U1%X1} %0,%1 |
6106 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 6107 | {lil|li} %0,%1 |
802a0058 | 6108 | {liu|lis} %0,%v1 |
beaec479 | 6109 | # |
57fa6739 | 6110 | {cal|la} %0,%1(%*) |
1fd4e8c1 | 6111 | mf%1 %0 |
5c23c401 | 6112 | mt%0 %1 |
e76e75bb RK |
6113 | mt%0 %1 |
6114 | cror 0,0,0" | |
a260abc9 DE |
6115 | [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*") |
6116 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")]) | |
1fd4e8c1 | 6117 | |
77fa0940 RK |
6118 | ;; Split a load of a large constant into the appropriate two-insn |
6119 | ;; sequence. | |
6120 | ||
6121 | (define_split | |
6122 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
6123 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 6124 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
6125 | && (INTVAL (operands[1]) & 0xffff) != 0" |
6126 | [(set (match_dup 0) | |
6127 | (match_dup 2)) | |
6128 | (set (match_dup 0) | |
6129 | (ior:SI (match_dup 0) | |
6130 | (match_dup 3)))] | |
6131 | " | |
6132 | { | |
5f59ecb7 | 6133 | operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); |
89e9f3a8 | 6134 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); |
77fa0940 RK |
6135 | }") |
6136 | ||
1fd4e8c1 | 6137 | (define_insn "" |
29ae5b89 JL |
6138 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
6139 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 6140 | (const_int 0))) |
29ae5b89 | 6141 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] |
0ad91047 | 6142 | "! TARGET_POWERPC64" |
29ae5b89 | 6143 | "mr. %0,%1" |
1fd4e8c1 RK |
6144 | [(set_attr "type" "compare")]) |
6145 | \f | |
6146 | (define_expand "movhi" | |
6147 | [(set (match_operand:HI 0 "general_operand" "") | |
6148 | (match_operand:HI 1 "any_operand" ""))] | |
6149 | "" | |
6150 | " | |
6151 | { | |
6152 | if (GET_CODE (operands[0]) != REG) | |
6153 | operands[1] = force_reg (HImode, operands[1]); | |
6154 | ||
3345af62 | 6155 | if (CONSTANT_P (operands[1]) |
34792e82 | 6156 | && GET_CODE (operands[1]) != CONST_INT) |
b45863ec RK |
6157 | { |
6158 | operands[1] = force_const_mem (HImode, operands[1]); | |
6159 | if (! memory_address_p (HImode, XEXP (operands[1], 0)) | |
6160 | && ! reload_in_progress) | |
6161 | operands[1] = change_address (operands[1], HImode, | |
6162 | XEXP (operands[1], 0)); | |
6163 | } | |
1fd4e8c1 RK |
6164 | }") |
6165 | ||
6166 | (define_insn "" | |
fb81d7ce RK |
6167 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
6168 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
6169 | "gpc_reg_operand (operands[0], HImode) |
6170 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 6171 | "@ |
deb9225a | 6172 | mr %0,%1 |
1fd4e8c1 RK |
6173 | lhz%U1%X1 %0,%1 |
6174 | sth%U0%X0 %1,%0 | |
19d5775a | 6175 | {lil|li} %0,%w1 |
1fd4e8c1 | 6176 | mf%1 %0 |
e76e75bb | 6177 | mt%0 %1 |
fb81d7ce | 6178 | mt%0 %1 |
e76e75bb | 6179 | cror 0,0,0" |
b7ff3d82 | 6180 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
6181 | |
6182 | (define_expand "movqi" | |
6183 | [(set (match_operand:QI 0 "general_operand" "") | |
6184 | (match_operand:QI 1 "any_operand" ""))] | |
6185 | "" | |
6186 | " | |
6187 | { | |
6188 | if (GET_CODE (operands[0]) != REG) | |
6189 | operands[1] = force_reg (QImode, operands[1]); | |
6190 | ||
3345af62 | 6191 | if (CONSTANT_P (operands[1]) |
34792e82 | 6192 | && GET_CODE (operands[1]) != CONST_INT) |
b45863ec RK |
6193 | { |
6194 | operands[1] = force_const_mem (QImode, operands[1]); | |
6195 | if (! memory_address_p (QImode, XEXP (operands[1], 0)) | |
6196 | && ! reload_in_progress) | |
6197 | operands[1] = change_address (operands[1], QImode, | |
6198 | XEXP (operands[1], 0)); | |
6199 | } | |
1fd4e8c1 RK |
6200 | }") |
6201 | ||
6202 | (define_insn "" | |
fb81d7ce RK |
6203 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
6204 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
6205 | "gpc_reg_operand (operands[0], QImode) |
6206 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 6207 | "@ |
deb9225a | 6208 | mr %0,%1 |
1fd4e8c1 RK |
6209 | lbz%U1%X1 %0,%1 |
6210 | stb%U0%X0 %1,%0 | |
19d5775a | 6211 | {lil|li} %0,%1 |
1fd4e8c1 | 6212 | mf%1 %0 |
e76e75bb | 6213 | mt%0 %1 |
fb81d7ce | 6214 | mt%0 %1 |
e76e75bb | 6215 | cror 0,0,0" |
b7ff3d82 | 6216 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
6217 | \f |
6218 | ;; Here is how to move condition codes around. When we store CC data in | |
6219 | ;; an integer register or memory, we store just the high-order 4 bits. | |
6220 | ;; This lets us not shift in the most common case of CR0. | |
6221 | (define_expand "movcc" | |
6222 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
6223 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
6224 | "" | |
6225 | "") | |
6226 | ||
6227 | (define_insn "" | |
6228 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") | |
6229 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] | |
6230 | "register_operand (operands[0], CCmode) | |
6231 | || register_operand (operands[1], CCmode)" | |
6232 | "@ | |
6233 | mcrf %0,%1 | |
6234 | mtcrf 128,%1 | |
ca7f5001 | 6235 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
1fd4e8c1 | 6236 | mfcr %0 |
ca7f5001 | 6237 | mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 |
deb9225a | 6238 | mr %0,%1 |
ca7f5001 RK |
6239 | {l%U1%X1|lwz%U1%X1} %0,%1 |
6240 | {st%U0%U1|stw%U0%U1} %1,%0" | |
b7ff3d82 | 6241 | [(set_attr "type" "*,*,*,compare,*,*,load,store") |
b19003d8 | 6242 | (set_attr "length" "*,*,12,*,8,*,*,*")]) |
1fd4e8c1 | 6243 | \f |
e52e05ca MM |
6244 | ;; For floating-point, we normally deal with the floating-point registers |
6245 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
6246 | ;; can produce floating-point values in fixed-point registers. Unless the | |
6247 | ;; value is a simple constant or already in memory, we deal with this by | |
6248 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
6249 | (define_expand "movsf" |
6250 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
6251 | (match_operand:SF 1 "any_operand" ""))] | |
6252 | "" | |
6253 | " | |
6254 | { | |
6255 | /* If we are called from reload, we might be getting a SUBREG of a hard | |
6256 | reg. So expand it. */ | |
6257 | if (GET_CODE (operands[0]) == SUBREG | |
6258 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
6259 | && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER) | |
6260 | operands[0] = alter_subreg (operands[0]); | |
6261 | if (GET_CODE (operands[1]) == SUBREG | |
6262 | && GET_CODE (SUBREG_REG (operands[1])) == REG | |
6263 | && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER) | |
6264 | operands[1] = alter_subreg (operands[1]); | |
6265 | ||
f99f88e0 | 6266 | if (GET_CODE (operands[0]) == MEM) |
1fd4e8c1 | 6267 | { |
f99f88e0 DE |
6268 | /* If operands[1] is a register, it may have double-precision data |
6269 | in it, so truncate it to single precision. We need not do | |
6270 | this for POWERPC. */ | |
6271 | if (! TARGET_POWERPC && TARGET_HARD_FLOAT | |
6272 | && GET_CODE (operands[1]) == REG | |
6273 | && (FP_REGNO_P (REGNO (operands[1])) | |
6274 | || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)) | |
f2974b07 | 6275 | { |
677a9668 | 6276 | rtx newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (SFmode)); |
f99f88e0 DE |
6277 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); |
6278 | operands[1] = newreg; | |
f2974b07 RK |
6279 | } |
6280 | ||
f99f88e0 | 6281 | operands[1] = force_reg (SFmode, operands[1]); |
1fd4e8c1 RK |
6282 | } |
6283 | ||
22e228e7 JL |
6284 | if (CONSTANT_P (operands[1]) && TARGET_HARD_FLOAT |
6285 | && ! easy_fp_constant (operands[1], SFmode)) | |
1fd4e8c1 RK |
6286 | { |
6287 | operands[1] = force_const_mem (SFmode, operands[1]); | |
6288 | if (! memory_address_p (SFmode, XEXP (operands[1], 0)) | |
6289 | && ! reload_in_progress) | |
6290 | operands[1] = change_address (operands[1], SFmode, | |
6291 | XEXP (operands[1], 0)); | |
6292 | } | |
6293 | }") | |
6294 | ||
1fd4e8c1 | 6295 | (define_split |
cd2b37d9 | 6296 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 6297 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 6298 | "reload_completed |
5ae4759c MM |
6299 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
6300 | || (GET_CODE (operands[0]) == SUBREG | |
6301 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
6302 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 6303 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
6304 | " |
6305 | { | |
6306 | long l; | |
6307 | REAL_VALUE_TYPE rv; | |
6308 | ||
6309 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
6310 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 6311 | |
f99f88e0 DE |
6312 | if (! TARGET_POWERPC64) |
6313 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
6314 | else | |
6315 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 6316 | |
a260abc9 DE |
6317 | operands[3] = GEN_INT(l); |
6318 | }") | |
6319 | ||
c4c40373 | 6320 | (define_insn "*movsf_hardfloat" |
f99f88e0 DE |
6321 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r") |
6322 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))] | |
d14a6d05 MM |
6323 | "(gpc_reg_operand (operands[0], SFmode) |
6324 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT" | |
1fd4e8c1 | 6325 | "@ |
f99f88e0 DE |
6326 | mr %0,%1 |
6327 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
6328 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
6329 | fmr %0,%1 |
6330 | lfs%U1%X1 %0,%1 | |
c4c40373 MM |
6331 | stfs%U0%X0 %1,%0 |
6332 | # | |
6333 | #" | |
f99f88e0 DE |
6334 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*") |
6335 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 6336 | |
c4c40373 MM |
6337 | (define_insn "*movsf_softfloat" |
6338 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r") | |
9615f239 | 6339 | (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))] |
d14a6d05 MM |
6340 | "(gpc_reg_operand (operands[0], SFmode) |
6341 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT" | |
6342 | "@ | |
6343 | mr %0,%1 | |
6344 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
6345 | {st%U0%X0|stw%U0%X0} %1,%0 | |
6346 | {lil|li} %0,%1 | |
802a0058 | 6347 | {liu|lis} %0,%v1 |
c4c40373 MM |
6348 | {cal|la} %0,%1(%*) |
6349 | # | |
6350 | #" | |
6351 | [(set_attr "type" "*,load,store,*,*,*,*,*") | |
6352 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 6353 | |
1fd4e8c1 RK |
6354 | \f |
6355 | (define_expand "movdf" | |
6356 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
6357 | (match_operand:DF 1 "any_operand" ""))] | |
6358 | "" | |
6359 | " | |
6360 | { | |
e7113111 RK |
6361 | if (GET_CODE (operands[0]) != REG) |
6362 | operands[1] = force_reg (DFmode, operands[1]); | |
1fd4e8c1 | 6363 | |
e7113111 | 6364 | if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode)) |
1fd4e8c1 RK |
6365 | { |
6366 | operands[1] = force_const_mem (DFmode, operands[1]); | |
6367 | if (! memory_address_p (DFmode, XEXP (operands[1], 0)) | |
6368 | && ! reload_in_progress) | |
6369 | operands[1] = change_address (operands[1], DFmode, | |
6370 | XEXP (operands[1], 0)); | |
6371 | } | |
e7113111 | 6372 | }") |
1fd4e8c1 RK |
6373 | |
6374 | (define_split | |
cd2b37d9 | 6375 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 6376 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 6377 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
6378 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
6379 | || (GET_CODE (operands[0]) == SUBREG | |
6380 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
6381 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
6382 | [(set (match_dup 2) (match_dup 4)) |
6383 | (set (match_dup 3) (match_dup 1))] | |
6384 | " | |
6385 | { | |
5ae4759c | 6386 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
6387 | HOST_WIDE_INT value = INTVAL (operands[1]); |
6388 | ||
5ae4759c MM |
6389 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
6390 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
6391 | #if HOST_BITS_PER_WIDE_INT == 32 |
6392 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
6393 | #else | |
6394 | operands[4] = GEN_INT (value >> 32); | |
6395 | operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
6396 | #endif | |
c4c40373 MM |
6397 | }") |
6398 | ||
c4c40373 MM |
6399 | (define_split |
6400 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
6401 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 6402 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
6403 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
6404 | || (GET_CODE (operands[0]) == SUBREG | |
6405 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
6406 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
6407 | [(set (match_dup 2) (match_dup 4)) |
6408 | (set (match_dup 3) (match_dup 5))] | |
6409 | " | |
6410 | { | |
5ae4759c | 6411 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
6412 | long l[2]; |
6413 | REAL_VALUE_TYPE rv; | |
6414 | ||
6415 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
6416 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
6417 | ||
5ae4759c MM |
6418 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
6419 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
47ad8c61 MM |
6420 | operands[4] = GEN_INT (l[endian]); |
6421 | operands[5] = GEN_INT (l[1 - endian]); | |
c4c40373 MM |
6422 | }") |
6423 | ||
efc08378 DE |
6424 | (define_split |
6425 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 6426 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 6427 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
6428 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
6429 | || (GET_CODE (operands[0]) == SUBREG | |
6430 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
6431 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 6432 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 6433 | " |
a260abc9 DE |
6434 | { |
6435 | int endian = (WORDS_BIG_ENDIAN == 0); | |
6436 | long l[2]; | |
6437 | REAL_VALUE_TYPE rv; | |
6438 | ||
6439 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
6440 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
6441 | ||
6442 | operands[2] = gen_lowpart (DImode, operands[0]); | |
6443 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
6444 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); | |
6445 | }") | |
efc08378 | 6446 | |
4eae5fe1 | 6447 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 6448 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
6449 | ;; a non-offsettable memref, but also it is less efficient than loading |
6450 | ;; the constant into an FP register, since it will probably be used there. | |
6451 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
6452 | ;; of handling these non-offsettable values. | |
c4c40373 | 6453 | (define_insn "*movdf_hardfloat32" |
000034eb DE |
6454 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
6455 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 6456 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
6457 | && (gpc_reg_operand (operands[0], DFmode) |
6458 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
6459 | "* |
6460 | { | |
6461 | switch (which_alternative) | |
6462 | { | |
a260abc9 | 6463 | default: |
a6c2a102 | 6464 | abort (); |
e7113111 RK |
6465 | case 0: |
6466 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
6467 | the first register operand 0 is the same as the second register |
6468 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 6469 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 6470 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 6471 | else |
deb9225a | 6472 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 6473 | case 1: |
2b97222d DE |
6474 | if (offsettable_memref_p (operands[1]) |
6475 | || (GET_CODE (operands[1]) == MEM | |
69f51a21 DE |
6476 | && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM |
6477 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC | |
6478 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))) | |
000034eb DE |
6479 | { |
6480 | /* If the low-address word is used in the address, we must load | |
6481 | it last. Otherwise, load it first. Note that we cannot have | |
6482 | auto-increment in that case since the address register is | |
6483 | known to be dead. */ | |
6484 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
6485 | operands[1], 0)) | |
6486 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
6487 | else | |
6488 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
6489 | } | |
e7113111 | 6490 | else |
000034eb DE |
6491 | { |
6492 | rtx addreg; | |
6493 | ||
000034eb DE |
6494 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
6495 | if (refers_to_regno_p (REGNO (operands[0]), | |
6496 | REGNO (operands[0]) + 1, | |
6497 | operands[1], 0)) | |
6498 | { | |
6499 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 6500 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 6501 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 6502 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
6503 | } |
6504 | else | |
6505 | { | |
2b97222d | 6506 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 6507 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 6508 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
6509 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
6510 | return \"\"; | |
6511 | } | |
6512 | } | |
e7113111 | 6513 | case 2: |
2b97222d DE |
6514 | if (offsettable_memref_p (operands[0]) |
6515 | || (GET_CODE (operands[0]) == MEM | |
69f51a21 DE |
6516 | && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM |
6517 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC | |
6518 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))) | |
000034eb DE |
6519 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
6520 | else | |
6521 | { | |
6522 | rtx addreg; | |
6523 | ||
000034eb | 6524 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 6525 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 6526 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 6527 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
6528 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
6529 | return \"\"; | |
6530 | } | |
e7113111 | 6531 | case 3: |
e7113111 | 6532 | case 4: |
e7113111 | 6533 | case 5: |
c4c40373 | 6534 | return \"#\"; |
e7113111 | 6535 | case 6: |
c4c40373 MM |
6536 | return \"fmr %0,%1\"; |
6537 | case 7: | |
6538 | return \"lfd%U1%X1 %0,%1\"; | |
6539 | case 8: | |
e7113111 RK |
6540 | return \"stfd%U0%X0 %1,%0\"; |
6541 | } | |
6542 | }" | |
c4c40373 | 6543 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
2f76d42c | 6544 | (set_attr "length" "8,16,16,8,12,16,*,*,*")]) |
51b8fc2c | 6545 | |
c4c40373 | 6546 | (define_insn "*movdf_softfloat32" |
1427100a DE |
6547 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
6548 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 6549 | "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
6550 | && (gpc_reg_operand (operands[0], DFmode) |
6551 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
6552 | "* |
6553 | { | |
6554 | switch (which_alternative) | |
6555 | { | |
a260abc9 | 6556 | default: |
a6c2a102 | 6557 | abort (); |
dc4f83ca MM |
6558 | case 0: |
6559 | /* We normally copy the low-numbered register first. However, if | |
6560 | the first register operand 0 is the same as the second register of | |
6561 | operand 1, we must copy in the opposite order. */ | |
6562 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
6563 | return \"mr %L0,%L1\;mr %0,%1\"; | |
6564 | else | |
6565 | return \"mr %0,%1\;mr %L0,%L1\"; | |
6566 | case 1: | |
3cb999d8 DE |
6567 | /* If the low-address word is used in the address, we must load |
6568 | it last. Otherwise, load it first. Note that we cannot have | |
6569 | auto-increment in that case since the address register is | |
6570 | known to be dead. */ | |
dc4f83ca | 6571 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 6572 | operands[1], 0)) |
dc4f83ca MM |
6573 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
6574 | else | |
6575 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
6576 | case 2: | |
6577 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
6578 | case 3: | |
c4c40373 MM |
6579 | case 4: |
6580 | case 5: | |
dc4f83ca MM |
6581 | return \"#\"; |
6582 | } | |
6583 | }" | |
c4c40373 MM |
6584 | [(set_attr "type" "*,load,store,*,*,*") |
6585 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 6586 | |
c4c40373 | 6587 | (define_insn "*movdf_hardfloat64" |
1427100a DE |
6588 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
6589 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 6590 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
6591 | && (gpc_reg_operand (operands[0], DFmode) |
6592 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 6593 | "@ |
3d5570cb RK |
6594 | mr %0,%1 |
6595 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 6596 | std%U0%X0 %1,%0 |
3d5570cb | 6597 | # |
c4c40373 MM |
6598 | # |
6599 | # | |
3d5570cb | 6600 | fmr %0,%1 |
f63184ac | 6601 | lfd%U1%X1 %0,%1 |
3d5570cb | 6602 | stfd%U0%X0 %1,%0" |
c4c40373 MM |
6603 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
6604 | (set_attr "length" "4,4,4,8,12,16,4,4,4")]) | |
dc4f83ca | 6605 | |
c4c40373 | 6606 | (define_insn "*movdf_softfloat64" |
1427100a DE |
6607 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
6608 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 6609 | "TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
6610 | && (gpc_reg_operand (operands[0], DFmode) |
6611 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
6612 | "@ |
6613 | mr %0,%1 | |
6614 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 6615 | std%U0%X0 %1,%0 |
c4c40373 MM |
6616 | # |
6617 | # | |
dc4f83ca | 6618 | #" |
c4c40373 MM |
6619 | [(set_attr "type" "*,load,store,*,*,*") |
6620 | (set_attr "length" "*,*,*,8,12,16")]) | |
1fd4e8c1 RK |
6621 | \f |
6622 | ;; Next come the multi-word integer load and store and the load and store | |
6623 | ;; multiple insns. | |
6624 | (define_expand "movdi" | |
6625 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 6626 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 RK |
6627 | "" |
6628 | " | |
6629 | { | |
e6ca2c17 | 6630 | if (GET_CODE (operands[0]) != REG) |
6b6ccd10 RK |
6631 | operands[1] = force_reg (DImode, operands[1]); |
6632 | ||
a260abc9 DE |
6633 | /* Convert a move of a CONST_DOUBLE into a CONST_INT |
6634 | only if sign-extended lower-half for 32-bit host. */ | |
6635 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
e8d791dd | 6636 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
6637 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 |
6638 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0) | |
d330fd93 | 6639 | || (CONST_DOUBLE_HIGH (operands[1]) == (HOST_WIDE_INT) 0xffffffff |
a260abc9 | 6640 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0)) |
e8d791dd | 6641 | #endif |
a260abc9 DE |
6642 | ) |
6643 | operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
6b6ccd10 | 6644 | |
34792e82 | 6645 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 6646 | if (GET_CODE (operands[1]) == CONSTANT_P_RTX) |
34792e82 JL |
6647 | { |
6648 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
6649 | DONE; | |
6650 | } | |
6651 | ||
a260abc9 DE |
6652 | if (TARGET_64BIT |
6653 | && CONSTANT_P (operands[1]) | |
6654 | #if HOST_BITS_PER_WIDE_INT == 32 | |
6655 | && GET_CODE (operands[1]) != CONST_INT | |
6656 | #endif | |
6657 | && ! easy_fp_constant (operands[1], DImode) | |
6658 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])) | |
6659 | { | |
6660 | /* Emit a USE operation so that the constant isn't deleted if | |
6661 | expensive optimizations are turned on because nobody | |
6662 | references it. This should only be done for operands that | |
6663 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
6664 | This should not be done for operands that contain LABEL_REFs. | |
6665 | For now, we just handle the obvious case. */ | |
6666 | if (GET_CODE (operands[1]) != LABEL_REF) | |
39403d82 | 6667 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); |
062284d8 | 6668 | |
a260abc9 DE |
6669 | /* If we are to limit the number of things we put in the TOC and |
6670 | this is a symbol plus a constant we can add in one insn, | |
6671 | just put the symbol in the TOC and add the constant. Don't do | |
6672 | this if reload is in progress. */ | |
6673 | if (GET_CODE (operands[1]) == CONST | |
6674 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
6675 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
6676 | && add_operand (XEXP (XEXP (operands[1], 0), 1), DImode) | |
6677 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF | |
6678 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
6679 | && ! side_effects_p (operands[0])) | |
6680 | { | |
6681 | rtx sym = force_const_mem (DImode, XEXP (XEXP (operands[1], 0), 0)); | |
6682 | rtx other = XEXP (XEXP (operands[1], 0), 1); | |
a473029f | 6683 | |
a260abc9 DE |
6684 | emit_insn (gen_adddi3 (operands[0], force_reg (DImode, sym), other)); |
6685 | DONE; | |
6686 | } | |
a473029f | 6687 | |
a260abc9 DE |
6688 | operands[1] = force_const_mem (DImode, operands[1]); |
6689 | if (! memory_address_p (DImode, XEXP (operands[1], 0)) | |
6690 | && ! reload_in_progress) | |
6691 | operands[1] = change_address (operands[1], DImode, | |
6692 | XEXP (operands[1], 0)); | |
a473029f | 6693 | } |
1fd4e8c1 RK |
6694 | }") |
6695 | ||
c4c40373 | 6696 | (define_insn "*movdi_32" |
4e74d8ec MM |
6697 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") |
6698 | (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] | |
a260abc9 | 6699 | "! TARGET_POWERPC64 |
4e74d8ec MM |
6700 | && (gpc_reg_operand (operands[0], DImode) |
6701 | || gpc_reg_operand (operands[1], DImode))" | |
1fd4e8c1 RK |
6702 | "* |
6703 | { | |
6704 | switch (which_alternative) | |
6705 | { | |
a260abc9 | 6706 | default: |
a6c2a102 | 6707 | abort (); |
1fd4e8c1 RK |
6708 | case 0: |
6709 | /* We normally copy the low-numbered register first. However, if | |
6710 | the first register operand 0 is the same as the second register of | |
6711 | operand 1, we must copy in the opposite order. */ | |
6712 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 6713 | return \"mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 6714 | else |
deb9225a | 6715 | return \"mr %0,%1\;mr %L0,%L1\"; |
1fd4e8c1 RK |
6716 | case 1: |
6717 | /* If the low-address word is used in the address, we must load it | |
6718 | last. Otherwise, load it first. Note that we cannot have | |
6719 | auto-increment in that case since the address register is known to be | |
6720 | dead. */ | |
6721 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 6722 | operands[1], 0)) |
ca7f5001 | 6723 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
1fd4e8c1 | 6724 | else |
ca7f5001 | 6725 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 | 6726 | case 2: |
ca7f5001 | 6727 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8ffd9c51 RK |
6728 | case 3: |
6729 | return \"fmr %0,%1\"; | |
6730 | case 4: | |
6731 | return \"lfd%U1%X1 %0,%1\"; | |
6732 | case 5: | |
6733 | return \"stfd%U0%X0 %1,%0\"; | |
4e74d8ec MM |
6734 | case 6: |
6735 | case 7: | |
6736 | case 8: | |
6737 | case 9: | |
6738 | case 10: | |
6739 | return \"#\"; | |
1fd4e8c1 RK |
6740 | } |
6741 | }" | |
4e74d8ec MM |
6742 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*") |
6743 | (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")]) | |
6744 | ||
6745 | (define_split | |
6746 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6747 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 6748 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
6749 | [(set (match_dup 2) (match_dup 4)) |
6750 | (set (match_dup 3) (match_dup 1))] | |
6751 | " | |
6752 | { | |
5f59ecb7 | 6753 | HOST_WIDE_INT value = INTVAL (operands[1]); |
39403d82 DE |
6754 | operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0); |
6755 | operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0); | |
75d39459 | 6756 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 6757 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 6758 | #else |
5f59ecb7 DE |
6759 | operands[4] = GEN_INT (value >> 32); |
6760 | operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
75d39459 | 6761 | #endif |
4e74d8ec MM |
6762 | }") |
6763 | ||
4e74d8ec MM |
6764 | (define_split |
6765 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6766 | (match_operand:DI 1 "const_double_operand" ""))] | |
75d39459 | 6767 | "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
6768 | [(set (match_dup 2) (match_dup 4)) |
6769 | (set (match_dup 3) (match_dup 5))] | |
6770 | " | |
6771 | { | |
39403d82 DE |
6772 | operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0); |
6773 | operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0); | |
f6968f59 MM |
6774 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
6775 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
4e74d8ec MM |
6776 | }") |
6777 | ||
c4c40373 | 6778 | (define_insn "*movdi_64" |
e6ca2c17 | 6779 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h") |
9615f239 | 6780 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 6781 | "TARGET_POWERPC64 |
4e74d8ec MM |
6782 | && (gpc_reg_operand (operands[0], DImode) |
6783 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 6784 | "@ |
3d5570cb RK |
6785 | mr %0,%1 |
6786 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 6787 | std%U0%X0 %1,%0 |
3d5570cb | 6788 | li %0,%1 |
802a0058 | 6789 | lis %0,%v1 |
e6ca2c17 | 6790 | # |
57fa6739 | 6791 | {cal|la} %0,%1(%*) |
3d5570cb RK |
6792 | fmr %0,%1 |
6793 | lfd%U1%X1 %0,%1 | |
6794 | stfd%U0%X0 %1,%0 | |
6795 | mf%1 %0 | |
08075ead DE |
6796 | mt%0 %1 |
6797 | cror 0,0,0" | |
b7ff3d82 | 6798 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*") |
e6ca2c17 DE |
6799 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
6800 | ||
5f59ecb7 | 6801 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
6802 | (define_insn "" |
6803 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6804 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
6805 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
6806 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
6807 | && num_insns_constant (operands[1], DImode) == 1" |
6808 | "* | |
6809 | { | |
6810 | return ((unsigned HOST_WIDE_INT) | |
6811 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
6812 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
6813 | }") | |
6814 | ||
5f59ecb7 | 6815 | ;; sign-extended 32-bit value |
a260abc9 DE |
6816 | (define_split |
6817 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6818 | (match_operand:DI 1 "const_int_operand" ""))] | |
6819 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
6820 | && num_insns_constant (operands[1], DImode) > 1" | |
6821 | [(set (match_dup 0) | |
6822 | (match_dup 2)) | |
6823 | (set (match_dup 0) | |
6824 | (ior:DI (match_dup 0) | |
6825 | (match_dup 3)))] | |
6826 | " | |
6827 | { | |
6828 | operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000); | |
6829 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); | |
6830 | }") | |
e6ca2c17 DE |
6831 | |
6832 | (define_split | |
6833 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6834 | (match_operand:DI 1 "const_double_operand" ""))] | |
a260abc9 DE |
6835 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
6836 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
6837 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
6838 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0) | |
5f59ecb7 | 6839 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 |
a260abc9 | 6840 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))" |
e6ca2c17 DE |
6841 | [(set (match_dup 0) |
6842 | (match_dup 2)) | |
6843 | (set (match_dup 0) | |
6844 | (ior:DI (match_dup 0) | |
a260abc9 DE |
6845 | (match_dup 3)))] |
6846 | " | |
6847 | { | |
6848 | operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff0000); | |
6849 | operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff); | |
6850 | }") | |
6851 | ||
5f59ecb7 DE |
6852 | (define_split |
6853 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6854 | (match_operand:DI 1 "const_int_operand" ""))] | |
6855 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
6856 | && GET_CODE (operands[1]) == CONST_INT | |
6857 | && (((INTVAL (operands[1]) >> 32) == 0 | |
6858 | && (INTVAL (operands[1]) & 0x80000000) == 0) | |
6859 | || ((INTVAL (operands[1]) >> 32) == -1 | |
6860 | && (INTVAL (operands[1]) & 0x80000000) != 0)) | |
6861 | && num_insns_constant (operands[1], DImode) > 1" | |
6862 | [(set (match_dup 0) | |
6863 | (match_dup 2)) | |
6864 | (set (match_dup 0) | |
6865 | (ior:DI (match_dup 0) | |
6866 | (match_dup 3)))] | |
6867 | " | |
6868 | { | |
6869 | operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000); | |
6870 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); | |
6871 | }") | |
6872 | ||
6873 | ;; zero-extended 32-bit value | |
a260abc9 DE |
6874 | (define_split |
6875 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6876 | (match_operand:DI 1 "const_double_operand" ""))] | |
6877 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
6878 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
6879 | && CONST_DOUBLE_HIGH (operands[1]) == 0 | |
6880 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0" | |
6881 | [(set (match_dup 0) | |
6882 | (match_dup 2)) | |
6883 | (set (match_dup 0) | |
6884 | (zero_extend:DI (subreg:SI (match_dup 0) 0)))] | |
6885 | " | |
6886 | { operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); }") | |
6887 | ||
5f59ecb7 DE |
6888 | (define_split |
6889 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6890 | (match_operand:DI 1 "const_int_operand" ""))] | |
6891 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
6892 | && GET_CODE (operands[1]) == CONST_INT | |
6893 | && INTVAL (operands[1]) >> 32 == 0 | |
6894 | && (INTVAL (operands[1]) & 0x80000000) != 0 | |
6895 | && num_insns_constant (operands[1], DImode) > 1" | |
6896 | [(set (match_dup 0) | |
6897 | (match_dup 2)) | |
6898 | (set (match_dup 0) | |
6899 | (zero_extend:DI (subreg:SI (match_dup 0) 0)))] | |
6900 | " | |
6901 | { operands[2] = GEN_INT ((INTVAL (operands[1]) << 32) >> 32); }") | |
6902 | ||
6903 | ;; 32-bit value in upper half of doubleword | |
a260abc9 DE |
6904 | (define_split |
6905 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6906 | (match_operand:DI 1 "const_double_operand" ""))] | |
6907 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
6908 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
6909 | && CONST_DOUBLE_LOW (operands[1]) == 0" | |
6910 | [(set (match_dup 0) | |
6911 | (match_dup 2)) | |
e6ca2c17 DE |
6912 | (set (match_dup 0) |
6913 | (ashift:DI (match_dup 0) | |
a260abc9 DE |
6914 | (const_int 32)))] |
6915 | " | |
6916 | { operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); }") | |
6917 | ||
5f59ecb7 DE |
6918 | (define_split |
6919 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6920 | (match_operand:DI 1 "const_int_operand" ""))] | |
6921 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
6922 | && GET_CODE (operands[1]) == CONST_INT | |
6923 | && INTVAL (operands[1]) & 0xffffffff == 0" | |
6924 | [(set (match_dup 0) | |
6925 | (match_dup 2)) | |
6926 | (set (match_dup 0) | |
6927 | (ashift:DI (match_dup 0) | |
6928 | (const_int 32)))] | |
6929 | " | |
6930 | { operands[2] = GEN_INT (INTVAL (operands[1]) >> 32); }") | |
6931 | ||
a260abc9 DE |
6932 | ;; Generate all one-bits and clear left or right. |
6933 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
6934 | (define_split | |
6935 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6936 | (match_operand:DI 1 "mask64_operand" ""))] | |
6937 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
6938 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 6939 | (set (match_dup 0) |
a260abc9 DE |
6940 | (and:DI (rotate:DI (match_dup 0) |
6941 | (const_int 0)) | |
6942 | (match_dup 1)))] | |
6943 | "") | |
6944 | ||
6945 | ;; Split a load of a large constant into the appropriate five-instruction | |
6946 | ;; sequence. Handle anything in a constant number of insns. | |
6947 | ;; When non-easy constants can go in the TOC, this should use | |
6948 | ;; easy_fp_constant predicate. | |
6949 | (define_split | |
6950 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6951 | (match_operand:DI 1 "const_double_operand" ""))] | |
5f59ecb7 DE |
6952 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
6953 | && num_insns_constant (operands[1], DImode) > 1" | |
a260abc9 DE |
6954 | [(set (match_dup 0) |
6955 | (match_dup 2)) | |
6956 | (set (match_dup 0) | |
6957 | (ashift:DI (match_dup 0) | |
6958 | (const_int 32))) | |
e6ca2c17 DE |
6959 | (set (match_dup 0) |
6960 | (ior:DI (match_dup 0) | |
a260abc9 | 6961 | (match_dup 3)))] |
e6ca2c17 DE |
6962 | " |
6963 | { | |
e6ca2c17 DE |
6964 | if (GET_CODE (operands[1]) == CONST_DOUBLE) |
6965 | { | |
5f59ecb7 DE |
6966 | operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
6967 | operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
e6ca2c17 | 6968 | } |
e8d791dd | 6969 | else |
e6ca2c17 | 6970 | { |
5f59ecb7 DE |
6971 | HOST_WIDE_INT value = INTVAL (operands[1]); |
6972 | operands[2] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
6973 | operands[3] = operands[1]; | |
e6ca2c17 | 6974 | } |
5f59ecb7 | 6975 | }") |
e6ca2c17 | 6976 | |
5f59ecb7 DE |
6977 | (define_split |
6978 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6979 | (match_operand:DI 1 "const_int_operand" ""))] | |
6980 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
6981 | && num_insns_constant (operands[1], DImode) > 1" | |
6982 | [(set (match_dup 0) | |
6983 | (match_dup 2)) | |
6984 | (set (match_dup 0) | |
6985 | (ashift:DI (match_dup 0) | |
6986 | (const_int 32))) | |
6987 | (set (match_dup 0) | |
6988 | (ior:DI (match_dup 0) | |
6989 | (match_dup 3)))] | |
6990 | " | |
6991 | { | |
6992 | HOST_WIDE_INT value = INTVAL (operands[1]); | |
6993 | operands[2] = GEN_INT (value >> 32); | |
6994 | operands[3] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
e6ca2c17 | 6995 | }") |
08075ead DE |
6996 | |
6997 | (define_insn "" | |
29ae5b89 JL |
6998 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
6999 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
08075ead | 7000 | (const_int 0))) |
29ae5b89 | 7001 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] |
08075ead | 7002 | "TARGET_POWERPC64" |
29ae5b89 | 7003 | "mr. %0,%1" |
815cdc52 | 7004 | [(set_attr "type" "compare")]) |
1fd4e8c1 RK |
7005 | \f |
7006 | ;; TImode is similar, except that we usually want to compute the address into | |
7007 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 7008 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
7009 | (define_expand "movti" |
7010 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
7011 | (match_operand:TI 1 "general_operand" "")) | |
7012 | (clobber (scratch:SI))])] | |
7e69e155 | 7013 | "TARGET_STRING || TARGET_POWERPC64" |
1fd4e8c1 RK |
7014 | " |
7015 | { | |
7016 | if (GET_CODE (operands[0]) == MEM) | |
7017 | operands[1] = force_reg (TImode, operands[1]); | |
7018 | ||
7019 | if (GET_CODE (operands[0]) == MEM | |
7020 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
7021 | && ! reload_in_progress) | |
7022 | operands[0] = change_address (operands[0], TImode, | |
7023 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
7024 | ||
7025 | if (GET_CODE (operands[1]) == MEM | |
7026 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
7027 | && ! reload_in_progress) | |
7028 | operands[1] = change_address (operands[1], TImode, | |
7029 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
7030 | }") | |
7031 | ||
7032 | ;; We say that MQ is clobbered in the last alternative because the first | |
7033 | ;; alternative would never get used otherwise since it would need a reload | |
7034 | ;; while the 2nd alternative would not. We put memory cases first so they | |
7035 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
7036 | ;; giving the SCRATCH mq. | |
a260abc9 | 7037 | (define_insn "*movti_power" |
e1469d0d | 7038 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
7039 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
7040 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
7e69e155 | 7041 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 7042 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
7043 | "* |
7044 | { | |
7045 | switch (which_alternative) | |
7046 | { | |
dc4f83ca MM |
7047 | default: |
7048 | abort (); | |
7049 | ||
1fd4e8c1 | 7050 | case 0: |
ca7f5001 | 7051 | return \"{stsi|stswi} %1,%P0,16\"; |
1fd4e8c1 RK |
7052 | |
7053 | case 1: | |
ca7f5001 | 7054 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
1fd4e8c1 RK |
7055 | |
7056 | case 2: | |
7057 | /* Normally copy registers with lowest numbered register copied first. | |
7058 | But copy in the other order if the first register of the output | |
7059 | is the second, third, or fourth register in the input. */ | |
7060 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
7061 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
deb9225a | 7062 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 7063 | else |
deb9225a | 7064 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; |
1fd4e8c1 RK |
7065 | case 3: |
7066 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
7067 | fall through to generating four loads. */ | |
7068 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 7069 | return \"{lsi|lswi} %0,%P1,16\"; |
1fd4e8c1 RK |
7070 | /* ... fall through ... */ |
7071 | case 4: | |
7072 | /* If the address register is the same as the register for the lowest- | |
7073 | addressed word, load it last. Similarly for the next two words. | |
7074 | Otherwise load lowest address to highest. */ | |
7075 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
7076 | operands[1], 0)) | |
ca7f5001 | 7077 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; |
1fd4e8c1 RK |
7078 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, |
7079 | REGNO (operands[0]) + 2, operands[1], 0)) | |
ca7f5001 | 7080 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 RK |
7081 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, |
7082 | REGNO (operands[0]) + 3, operands[1], 0)) | |
ca7f5001 | 7083 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; |
1fd4e8c1 | 7084 | else |
ca7f5001 | 7085 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; |
1fd4e8c1 RK |
7086 | } |
7087 | }" | |
b7ff3d82 | 7088 | [(set_attr "type" "store,store,*,load,load") |
b19003d8 | 7089 | (set_attr "length" "*,16,16,*,16")]) |
51b8fc2c | 7090 | |
a260abc9 | 7091 | (define_insn "*movti_string" |
dc4f83ca MM |
7092 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r") |
7093 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,m")) | |
7094 | (clobber (match_scratch:SI 2 "=X,X,X"))] | |
0ad91047 | 7095 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
7096 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
7097 | "* | |
7098 | { | |
7099 | switch (which_alternative) | |
7100 | { | |
7101 | default: | |
7102 | abort (); | |
7103 | ||
7104 | case 0: | |
7105 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; | |
7106 | ||
7107 | case 1: | |
7108 | /* Normally copy registers with lowest numbered register copied first. | |
7109 | But copy in the other order if the first register of the output | |
7110 | is the second, third, or fourth register in the input. */ | |
7111 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
7112 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
7113 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; | |
7114 | else | |
7115 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; | |
7116 | case 2: | |
7117 | /* If the address register is the same as the register for the lowest- | |
7118 | addressed word, load it last. Similarly for the next two words. | |
7119 | Otherwise load lowest address to highest. */ | |
7120 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
7121 | operands[1], 0)) | |
7122 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; | |
7123 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, | |
7124 | REGNO (operands[0]) + 2, operands[1], 0)) | |
7125 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; | |
7126 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, | |
7127 | REGNO (operands[0]) + 3, operands[1], 0)) | |
7128 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; | |
7129 | else | |
7130 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; | |
7131 | } | |
7132 | }" | |
b7ff3d82 | 7133 | [(set_attr "type" "store,*,load") |
dc4f83ca MM |
7134 | (set_attr "length" "16,16,16")]) |
7135 | ||
a260abc9 | 7136 | (define_insn "*movti_ppc64" |
51b8fc2c RK |
7137 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") |
7138 | (match_operand:TI 1 "input_operand" "r,m,r"))] | |
7139 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) | |
7140 | || gpc_reg_operand (operands[1], TImode))" | |
7141 | "* | |
7142 | { | |
7143 | switch (which_alternative) | |
7144 | { | |
a260abc9 | 7145 | default: |
a6c2a102 | 7146 | abort (); |
51b8fc2c RK |
7147 | case 0: |
7148 | /* We normally copy the low-numbered register first. However, if | |
7149 | the first register operand 0 is the same as the second register of | |
7150 | operand 1, we must copy in the opposite order. */ | |
7151 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
7152 | return \"mr %L0,%L1\;mr %0,%1\"; | |
7153 | else | |
7154 | return \"mr %0,%1\;mr %L0,%L1\"; | |
7155 | case 1: | |
7156 | /* If the low-address word is used in the address, we must load it | |
7157 | last. Otherwise, load it first. Note that we cannot have | |
7158 | auto-increment in that case since the address register is known to be | |
7159 | dead. */ | |
7160 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 7161 | operands[1], 0)) |
51b8fc2c RK |
7162 | return \"ld %L0,%L1\;ld %0,%1\"; |
7163 | else | |
7164 | return \"ld%U1 %0,%1\;ld %L0,%L1\"; | |
7165 | case 2: | |
7166 | return \"std%U0 %1,%0\;std %L1,%L0\"; | |
7167 | } | |
7168 | }" | |
b7ff3d82 | 7169 | [(set_attr "type" "*,load,store") |
51b8fc2c | 7170 | (set_attr "length" "8,8,8")]) |
1fd4e8c1 RK |
7171 | \f |
7172 | (define_expand "load_multiple" | |
2f622005 RK |
7173 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
7174 | (match_operand:SI 1 "" "")) | |
7175 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 7176 | "TARGET_STRING" |
1fd4e8c1 RK |
7177 | " |
7178 | { | |
7179 | int regno; | |
7180 | int count; | |
7181 | rtx from; | |
7182 | int i; | |
7183 | ||
7184 | /* Support only loading a constant number of fixed-point registers from | |
7185 | memory and only bother with this if more than two; the machine | |
7186 | doesn't support more than eight. */ | |
7187 | if (GET_CODE (operands[2]) != CONST_INT | |
7188 | || INTVAL (operands[2]) <= 2 | |
7189 | || INTVAL (operands[2]) > 8 | |
7190 | || GET_CODE (operands[1]) != MEM | |
7191 | || GET_CODE (operands[0]) != REG | |
7192 | || REGNO (operands[0]) >= 32) | |
7193 | FAIL; | |
7194 | ||
7195 | count = INTVAL (operands[2]); | |
7196 | regno = REGNO (operands[0]); | |
7197 | ||
39403d82 | 7198 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
1fd4e8c1 RK |
7199 | from = force_reg (SImode, XEXP (operands[1], 0)); |
7200 | ||
7201 | for (i = 0; i < count; i++) | |
7202 | XVECEXP (operands[3], 0, i) | |
39403d82 | 7203 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
c5c76735 JL |
7204 | change_address (operands[1], SImode, |
7205 | plus_constant (from, i * 4))); | |
1fd4e8c1 RK |
7206 | }") |
7207 | ||
7208 | (define_insn "" | |
7209 | [(match_parallel 0 "load_multiple_operation" | |
cd2b37d9 | 7210 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") |
52d3af72 | 7211 | (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])] |
7e69e155 | 7212 | "TARGET_STRING" |
1fd4e8c1 RK |
7213 | "* |
7214 | { | |
7215 | /* We have to handle the case where the pseudo used to contain the address | |
e82ee4cc RK |
7216 | is assigned to one of the output registers. */ |
7217 | int i, j; | |
7218 | int words = XVECLEN (operands[0], 0); | |
7219 | rtx xop[10]; | |
7220 | ||
7221 | if (XVECLEN (operands[0], 0) == 1) | |
7222 | return \"{l|lwz} %1,0(%2)\"; | |
1fd4e8c1 | 7223 | |
e82ee4cc | 7224 | for (i = 0; i < words; i++) |
1fd4e8c1 RK |
7225 | if (refers_to_regno_p (REGNO (operands[1]) + i, |
7226 | REGNO (operands[1]) + i + 1, operands[2], 0)) | |
7227 | { | |
e82ee4cc RK |
7228 | if (i == words-1) |
7229 | { | |
7230 | xop[0] = operands[1]; | |
7231 | xop[1] = operands[2]; | |
7232 | xop[2] = GEN_INT (4 * (words-1)); | |
d89ddcfd | 7233 | output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop); |
e82ee4cc RK |
7234 | return \"\"; |
7235 | } | |
7236 | else if (i == 0) | |
7237 | { | |
7238 | xop[0] = operands[1]; | |
39403d82 | 7239 | xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
e82ee4cc RK |
7240 | xop[2] = GEN_INT (4 * (words-1)); |
7241 | output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop); | |
7242 | return \"\"; | |
7243 | } | |
7244 | else | |
7245 | { | |
7246 | for (j = 0; j < words; j++) | |
7247 | if (j != i) | |
7248 | { | |
39403d82 | 7249 | xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j); |
e82ee4cc RK |
7250 | xop[1] = operands[2]; |
7251 | xop[2] = GEN_INT (j * 4); | |
7252 | output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop); | |
7253 | } | |
7254 | xop[0] = operands[2]; | |
7255 | xop[1] = GEN_INT (i * 4); | |
7256 | output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop); | |
7257 | return \"\"; | |
7258 | } | |
1fd4e8c1 RK |
7259 | } |
7260 | ||
e82ee4cc | 7261 | return \"{lsi|lswi} %1,%2,%N0\"; |
1fd4e8c1 | 7262 | }" |
b19003d8 | 7263 | [(set_attr "type" "load") |
e82ee4cc | 7264 | (set_attr "length" "32")]) |
b19003d8 | 7265 | |
b7ff3d82 | 7266 | \f |
1fd4e8c1 | 7267 | (define_expand "store_multiple" |
2f622005 RK |
7268 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
7269 | (match_operand:SI 1 "" "")) | |
7270 | (clobber (scratch:SI)) | |
7271 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 7272 | "TARGET_STRING" |
1fd4e8c1 RK |
7273 | " |
7274 | { | |
7275 | int regno; | |
7276 | int count; | |
7277 | rtx to; | |
7278 | int i; | |
7279 | ||
7280 | /* Support only storing a constant number of fixed-point registers to | |
7281 | memory and only bother with this if more than two; the machine | |
7282 | doesn't support more than eight. */ | |
7283 | if (GET_CODE (operands[2]) != CONST_INT | |
7284 | || INTVAL (operands[2]) <= 2 | |
7285 | || INTVAL (operands[2]) > 8 | |
7286 | || GET_CODE (operands[0]) != MEM | |
7287 | || GET_CODE (operands[1]) != REG | |
7288 | || REGNO (operands[1]) >= 32) | |
7289 | FAIL; | |
7290 | ||
7291 | count = INTVAL (operands[2]); | |
7292 | regno = REGNO (operands[1]); | |
7293 | ||
39403d82 | 7294 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 RK |
7295 | to = force_reg (SImode, XEXP (operands[0], 0)); |
7296 | ||
7297 | XVECEXP (operands[3], 0, 0) | |
39403d82 | 7298 | = gen_rtx_SET (VOIDmode, change_address (operands[0], SImode, to), |
c5c76735 | 7299 | operands[1]); |
39403d82 | 7300 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 7301 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
7302 | |
7303 | for (i = 1; i < count; i++) | |
7304 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 7305 | = gen_rtx_SET (VOIDmode, |
c5c76735 JL |
7306 | change_address (operands[0], SImode, |
7307 | plus_constant (to, i * 4)), | |
7308 | gen_rtx_REG (SImode, regno + i)); | |
1fd4e8c1 RK |
7309 | }") |
7310 | ||
7311 | (define_insn "" | |
7312 | [(match_parallel 0 "store_multiple_operation" | |
7313 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 7314 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 7315 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 7316 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
7317 | "{stsi|stswi} %2,%P1,%O0" |
7318 | [(set_attr "type" "store")]) | |
d14a6d05 MM |
7319 | |
7320 | (define_insn "" | |
7321 | [(match_parallel 0 "store_multiple_operation" | |
52d3af72 | 7322 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
d14a6d05 MM |
7323 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
7324 | (clobber (match_scratch:SI 3 "X"))])] | |
0ad91047 | 7325 | "TARGET_STRING && ! TARGET_POWER" |
b7ff3d82 DE |
7326 | "{stsi|stswi} %2,%1,%O0" |
7327 | [(set_attr "type" "store")]) | |
7e69e155 MM |
7328 | |
7329 | \f | |
7330 | ;; String/block move insn. | |
7331 | ;; Argument 0 is the destination | |
7332 | ;; Argument 1 is the source | |
7333 | ;; Argument 2 is the length | |
7334 | ;; Argument 3 is the alignment | |
7335 | ||
7336 | (define_expand "movstrsi" | |
b6c9286a MM |
7337 | [(parallel [(set (match_operand:BLK 0 "" "") |
7338 | (match_operand:BLK 1 "" "")) | |
7339 | (use (match_operand:SI 2 "" "")) | |
7340 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
7341 | "" |
7342 | " | |
7343 | { | |
7344 | if (expand_block_move (operands)) | |
7345 | DONE; | |
7346 | else | |
7347 | FAIL; | |
7348 | }") | |
7349 | ||
7350 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
7351 | ;; register allocator doesn't have a clue about allocating 8 word registers | |
7352 | (define_expand "movstrsi_8reg" | |
b6c9286a MM |
7353 | [(parallel [(set (match_operand 0 "" "") |
7354 | (match_operand 1 "" "")) | |
7355 | (use (match_operand 2 "" "")) | |
7356 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
7357 | (clobber (reg:SI 5)) |
7358 | (clobber (reg:SI 6)) | |
7359 | (clobber (reg:SI 7)) | |
7360 | (clobber (reg:SI 8)) | |
7361 | (clobber (reg:SI 9)) | |
7362 | (clobber (reg:SI 10)) | |
7363 | (clobber (reg:SI 11)) | |
7364 | (clobber (reg:SI 12)) | |
3c67b673 | 7365 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
7366 | "TARGET_STRING" |
7367 | "") | |
7368 | ||
7369 | (define_insn "" | |
52d3af72 DE |
7370 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7371 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7372 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7373 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 7374 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
7375 | (clobber (reg:SI 6)) |
7376 | (clobber (reg:SI 7)) | |
7377 | (clobber (reg:SI 8)) | |
7378 | (clobber (reg:SI 9)) | |
7379 | (clobber (reg:SI 10)) | |
7380 | (clobber (reg:SI 11)) | |
7381 | (clobber (reg:SI 12)) | |
3c67b673 | 7382 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
7383 | "TARGET_STRING && TARGET_POWER |
7384 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0) | |
7385 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
7386 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
7387 | && REGNO (operands[4]) == 5" |
7388 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
7389 | [(set_attr "type" "load") |
7390 | (set_attr "length" "8")]) | |
7e69e155 MM |
7391 | |
7392 | (define_insn "" | |
52d3af72 DE |
7393 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7394 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7395 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7396 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 7397 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
7398 | (clobber (reg:SI 6)) |
7399 | (clobber (reg:SI 7)) | |
7400 | (clobber (reg:SI 8)) | |
7401 | (clobber (reg:SI 9)) | |
7402 | (clobber (reg:SI 10)) | |
7403 | (clobber (reg:SI 11)) | |
7404 | (clobber (reg:SI 12)) | |
3c67b673 | 7405 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 7406 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 MM |
7407 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0) |
7408 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
7409 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
7410 | && REGNO (operands[4]) == 5" |
7411 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
7412 | [(set_attr "type" "load") |
7413 | (set_attr "length" "8")]) | |
7e69e155 MM |
7414 | |
7415 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the | |
7416 | ;; register allocator doesn't have a clue about allocating 6 word registers | |
7417 | (define_expand "movstrsi_6reg" | |
b6c9286a MM |
7418 | [(parallel [(set (match_operand 0 "" "") |
7419 | (match_operand 1 "" "")) | |
7420 | (use (match_operand 2 "" "")) | |
7421 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
7422 | (clobber (reg:SI 7)) |
7423 | (clobber (reg:SI 8)) | |
7424 | (clobber (reg:SI 9)) | |
7425 | (clobber (reg:SI 10)) | |
7426 | (clobber (reg:SI 11)) | |
7427 | (clobber (reg:SI 12)) | |
3c67b673 | 7428 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
7429 | "TARGET_STRING" |
7430 | "") | |
7431 | ||
7432 | (define_insn "" | |
52d3af72 DE |
7433 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7434 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7435 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7436 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 7437 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
7438 | (clobber (reg:SI 8)) |
7439 | (clobber (reg:SI 9)) | |
7440 | (clobber (reg:SI 10)) | |
7441 | (clobber (reg:SI 11)) | |
7442 | (clobber (reg:SI 12)) | |
3c67b673 | 7443 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
7444 | "TARGET_STRING && TARGET_POWER |
7445 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
7446 | && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12) | |
7447 | && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
7448 | && REGNO (operands[4]) == 7" |
7449 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
7450 | [(set_attr "type" "load") |
7451 | (set_attr "length" "8")]) | |
7e69e155 MM |
7452 | |
7453 | (define_insn "" | |
52d3af72 DE |
7454 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7455 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7456 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7457 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 7458 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
7459 | (clobber (reg:SI 8)) |
7460 | (clobber (reg:SI 9)) | |
7461 | (clobber (reg:SI 10)) | |
7462 | (clobber (reg:SI 11)) | |
7463 | (clobber (reg:SI 12)) | |
3c67b673 | 7464 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 7465 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 MM |
7466 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
7467 | && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12) | |
7468 | && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
7469 | && REGNO (operands[4]) == 7" |
7470 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
7471 | [(set_attr "type" "load") |
7472 | (set_attr "length" "8")]) | |
7e69e155 MM |
7473 | |
7474 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill problems | |
7475 | ;; with TImode | |
7476 | (define_expand "movstrsi_4reg" | |
b6c9286a MM |
7477 | [(parallel [(set (match_operand 0 "" "") |
7478 | (match_operand 1 "" "")) | |
7479 | (use (match_operand 2 "" "")) | |
7480 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
7481 | (clobber (reg:SI 9)) |
7482 | (clobber (reg:SI 10)) | |
7483 | (clobber (reg:SI 11)) | |
7484 | (clobber (reg:SI 12)) | |
3c67b673 | 7485 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
7486 | "TARGET_STRING" |
7487 | "") | |
7488 | ||
7489 | (define_insn "" | |
52d3af72 DE |
7490 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7491 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7492 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7493 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 7494 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
7495 | (clobber (reg:SI 10)) |
7496 | (clobber (reg:SI 11)) | |
7497 | (clobber (reg:SI 12)) | |
3c67b673 | 7498 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
7499 | "TARGET_STRING && TARGET_POWER |
7500 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
7501 | && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12) | |
7502 | && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
7503 | && REGNO (operands[4]) == 9" |
7504 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
7505 | [(set_attr "type" "load") |
7506 | (set_attr "length" "8")]) | |
7e69e155 MM |
7507 | |
7508 | (define_insn "" | |
52d3af72 DE |
7509 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7510 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7511 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7512 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 7513 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
7514 | (clobber (reg:SI 10)) |
7515 | (clobber (reg:SI 11)) | |
7516 | (clobber (reg:SI 12)) | |
3c67b673 | 7517 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 7518 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 MM |
7519 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
7520 | && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12) | |
7521 | && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
7522 | && REGNO (operands[4]) == 9" |
7523 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
7524 | [(set_attr "type" "load") |
7525 | (set_attr "length" "8")]) | |
7e69e155 MM |
7526 | |
7527 | ;; Move up to 8 bytes at a time. | |
7528 | (define_expand "movstrsi_2reg" | |
b6c9286a MM |
7529 | [(parallel [(set (match_operand 0 "" "") |
7530 | (match_operand 1 "" "")) | |
7531 | (use (match_operand 2 "" "")) | |
7532 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
7533 | (clobber (match_scratch:DI 4 "")) |
7534 | (clobber (match_scratch:SI 5 ""))])] | |
0ad91047 | 7535 | "TARGET_STRING && ! TARGET_64BIT" |
7e69e155 MM |
7536 | "") |
7537 | ||
7538 | (define_insn "" | |
52d3af72 DE |
7539 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7540 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7541 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7542 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
7543 | (clobber (match_scratch:DI 4 "=&r")) | |
7544 | (clobber (match_scratch:SI 5 "=q"))] | |
0ad91047 | 7545 | "TARGET_STRING && TARGET_POWER && ! TARGET_64BIT |
3c67b673 RK |
7546 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
7547 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
7548 | [(set_attr "type" "load") |
7549 | (set_attr "length" "8")]) | |
7e69e155 MM |
7550 | |
7551 | (define_insn "" | |
52d3af72 DE |
7552 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7553 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7554 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7555 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
7556 | (clobber (match_scratch:DI 4 "=&r")) | |
7557 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 7558 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_64BIT |
7e69e155 | 7559 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 7560 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
7561 | [(set_attr "type" "load") |
7562 | (set_attr "length" "8")]) | |
7e69e155 MM |
7563 | |
7564 | ;; Move up to 4 bytes at a time. | |
7565 | (define_expand "movstrsi_1reg" | |
b6c9286a MM |
7566 | [(parallel [(set (match_operand 0 "" "") |
7567 | (match_operand 1 "" "")) | |
7568 | (use (match_operand 2 "" "")) | |
7569 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
7570 | (clobber (match_scratch:SI 4 "")) |
7571 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
7572 | "TARGET_STRING" |
7573 | "") | |
7574 | ||
7575 | (define_insn "" | |
52d3af72 DE |
7576 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7577 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7578 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7579 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
7580 | (clobber (match_scratch:SI 4 "=&r")) | |
7581 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
7582 | "TARGET_STRING && TARGET_POWER |
7583 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 7584 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
7585 | [(set_attr "type" "load") |
7586 | (set_attr "length" "8")]) | |
7e69e155 MM |
7587 | |
7588 | (define_insn "" | |
52d3af72 DE |
7589 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7590 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7591 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7592 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
7593 | (clobber (match_scratch:SI 4 "=&r")) | |
7594 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 7595 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 7596 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
3c67b673 | 7597 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
7598 | [(set_attr "type" "load") |
7599 | (set_attr "length" "8")]) | |
7e69e155 | 7600 | |
1fd4e8c1 | 7601 | \f |
7e69e155 | 7602 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
7603 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
7604 | ;; do cases where the increment is not the size of the object. | |
7605 | ;; | |
7606 | ;; In all these cases, we use operands 0 and 1 for the register being | |
7607 | ;; incremented because those are the operands that local-alloc will | |
7608 | ;; tie and these are the pair most likely to be tieable (and the ones | |
7609 | ;; that will benefit the most). | |
7610 | ||
38c1f2d7 | 7611 | (define_insn "*movdi_update1" |
51b8fc2c | 7612 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 7613 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
51b8fc2c RK |
7614 | (match_operand:DI 2 "reg_or_short_operand" "r,I")))) |
7615 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
7616 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 7617 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
7618 | "@ |
7619 | ldux %3,%0,%2 | |
7620 | ldu %3,%2(%0)" | |
7621 | [(set_attr "type" "load")]) | |
7622 | ||
38c1f2d7 | 7623 | (define_insn "*movdi_update2" |
287f13ff RK |
7624 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") |
7625 | (sign_extend:DI | |
7626 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
7627 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
7628 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
7629 | (plus:DI (match_dup 1) (match_dup 2)))] | |
7630 | "TARGET_POWERPC64" | |
7631 | "lwaux %3,%0,%2" | |
7632 | [(set_attr "type" "load")]) | |
7633 | ||
4697a36c | 7634 | (define_insn "movdi_update" |
51b8fc2c RK |
7635 | [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
7636 | (match_operand:DI 2 "reg_or_short_operand" "r,I"))) | |
7637 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) | |
7638 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
7639 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 7640 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
7641 | "@ |
7642 | stdux %3,%0,%2 | |
b7ff3d82 DE |
7643 | stdu %3,%2(%0)" |
7644 | [(set_attr "type" "store")]) | |
51b8fc2c | 7645 | |
38c1f2d7 | 7646 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
7647 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
7648 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 7649 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 7650 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
7651 | (plus:SI (match_dup 1) (match_dup 2)))] |
7652 | "" | |
7653 | "@ | |
ca7f5001 RK |
7654 | {lux|lwzux} %3,%0,%2 |
7655 | {lu|lwzu} %3,%2(%0)" | |
cfb557c4 | 7656 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7657 | |
4697a36c | 7658 | (define_insn "movsi_update" |
cd2b37d9 | 7659 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7660 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
7661 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
7662 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 7663 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7664 | "TARGET_UPDATE" |
1fd4e8c1 | 7665 | "@ |
ca7f5001 | 7666 | {stux|stwux} %3,%0,%2 |
b7ff3d82 DE |
7667 | {stu|stwu} %3,%2(%0)" |
7668 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 7669 | |
38c1f2d7 | 7670 | (define_insn "*movhi_update" |
cd2b37d9 RK |
7671 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
7672 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 7673 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 7674 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7675 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7676 | "TARGET_UPDATE" |
1fd4e8c1 | 7677 | "@ |
5f243543 RK |
7678 | lhzux %3,%0,%2 |
7679 | lhzu %3,%2(%0)" | |
cfb557c4 | 7680 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7681 | |
38c1f2d7 | 7682 | (define_insn "*movhi_update2" |
cd2b37d9 | 7683 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 7684 | (zero_extend:SI |
cd2b37d9 | 7685 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7686 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 7687 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7688 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7689 | "TARGET_UPDATE" |
1fd4e8c1 | 7690 | "@ |
5f243543 RK |
7691 | lhzux %3,%0,%2 |
7692 | lhzu %3,%2(%0)" | |
cfb557c4 | 7693 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7694 | |
38c1f2d7 | 7695 | (define_insn "*movhi_update3" |
cd2b37d9 | 7696 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 7697 | (sign_extend:SI |
cd2b37d9 | 7698 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7699 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 7700 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7701 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7702 | "TARGET_UPDATE" |
1fd4e8c1 | 7703 | "@ |
5f243543 RK |
7704 | lhaux %3,%0,%2 |
7705 | lhau %3,%2(%0)" | |
cfb557c4 | 7706 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7707 | |
38c1f2d7 | 7708 | (define_insn "*movhi_update4" |
cd2b37d9 | 7709 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7710 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
7711 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
7712 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 7713 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7714 | "TARGET_UPDATE" |
1fd4e8c1 | 7715 | "@ |
5f243543 | 7716 | sthux %3,%0,%2 |
b7ff3d82 DE |
7717 | sthu %3,%2(%0)" |
7718 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 7719 | |
38c1f2d7 | 7720 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
7721 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
7722 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 7723 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 7724 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7725 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7726 | "TARGET_UPDATE" |
1fd4e8c1 | 7727 | "@ |
5f243543 RK |
7728 | lbzux %3,%0,%2 |
7729 | lbzu %3,%2(%0)" | |
cfb557c4 | 7730 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7731 | |
38c1f2d7 | 7732 | (define_insn "*movqi_update2" |
cd2b37d9 | 7733 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 7734 | (zero_extend:SI |
cd2b37d9 | 7735 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7736 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 7737 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7738 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7739 | "TARGET_UPDATE" |
1fd4e8c1 | 7740 | "@ |
5f243543 RK |
7741 | lbzux %3,%0,%2 |
7742 | lbzu %3,%2(%0)" | |
cfb557c4 | 7743 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7744 | |
38c1f2d7 | 7745 | (define_insn "*movqi_update3" |
cd2b37d9 | 7746 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7747 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
7748 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
7749 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 7750 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7751 | "TARGET_UPDATE" |
1fd4e8c1 | 7752 | "@ |
5f243543 | 7753 | stbux %3,%0,%2 |
b7ff3d82 DE |
7754 | stbu %3,%2(%0)" |
7755 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 7756 | |
38c1f2d7 | 7757 | (define_insn "*movsf_update1" |
cd2b37d9 | 7758 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 7759 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7760 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 7761 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7762 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7763 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 7764 | "@ |
5f243543 RK |
7765 | lfsux %3,%0,%2 |
7766 | lfsu %3,%2(%0)" | |
cfb557c4 | 7767 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 7768 | |
38c1f2d7 | 7769 | (define_insn "*movsf_update2" |
cd2b37d9 | 7770 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7771 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
7772 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
7773 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 7774 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7775 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 7776 | "@ |
85fff2f3 | 7777 | stfsux %3,%0,%2 |
b7ff3d82 DE |
7778 | stfsu %3,%2(%0)" |
7779 | [(set_attr "type" "fpstore")]) | |
1fd4e8c1 | 7780 | |
38c1f2d7 MM |
7781 | (define_insn "*movsf_update3" |
7782 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
7783 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
7784 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
7785 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
7786 | (plus:SI (match_dup 1) (match_dup 2)))] | |
7787 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
7788 | "@ | |
7789 | {lux|lwzux} %3,%0,%2 | |
7790 | {lu|lwzu} %3,%2(%0)" | |
7791 | [(set_attr "type" "load")]) | |
7792 | ||
7793 | (define_insn "*movsf_update4" | |
7794 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
7795 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
7796 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
7797 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
7798 | (plus:SI (match_dup 1) (match_dup 2)))] | |
7799 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
7800 | "@ | |
7801 | {stux|stwux} %3,%0,%2 | |
7802 | {stu|stwu} %3,%2(%0)" | |
7803 | [(set_attr "type" "store")]) | |
7804 | ||
7805 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
7806 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
7807 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 7808 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 7809 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7810 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7811 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 7812 | "@ |
5f243543 RK |
7813 | lfdux %3,%0,%2 |
7814 | lfdu %3,%2(%0)" | |
cfb557c4 | 7815 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 7816 | |
38c1f2d7 | 7817 | (define_insn "*movdf_update2" |
cd2b37d9 | 7818 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7819 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
7820 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
7821 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 7822 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7823 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 7824 | "@ |
5f243543 | 7825 | stfdux %3,%0,%2 |
b7ff3d82 DE |
7826 | stfdu %3,%2(%0)" |
7827 | [(set_attr "type" "fpstore")]) | |
4c70a4f3 RK |
7828 | |
7829 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
7830 | ||
7831 | (define_peephole | |
7832 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
7833 | (match_operand:DF 1 "memory_operand" "")) | |
7834 | (set (match_operand:DF 2 "gpc_reg_operand" "=f") | |
7835 | (match_operand:DF 3 "memory_operand" ""))] | |
7836 | "TARGET_POWER2 | |
d14a6d05 | 7837 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
7838 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
7839 | && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) | |
7840 | && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" | |
7841 | "lfq%U1%X1 %0,%1") | |
7842 | ||
7843 | (define_peephole | |
7844 | [(set (match_operand:DF 0 "memory_operand" "") | |
7845 | (match_operand:DF 1 "gpc_reg_operand" "f")) | |
7846 | (set (match_operand:DF 2 "memory_operand" "") | |
7847 | (match_operand:DF 3 "gpc_reg_operand" "f"))] | |
7848 | "TARGET_POWER2 | |
d14a6d05 | 7849 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
7850 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
7851 | && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) | |
7852 | && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" | |
7853 | "stfq%U0%X0 %1,%0") | |
1fd4e8c1 RK |
7854 | \f |
7855 | ;; Next come insns related to the calling sequence. | |
7856 | ;; | |
7857 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 7858 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
7859 | |
7860 | (define_expand "allocate_stack" | |
52d3af72 | 7861 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
7862 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
7863 | (set (reg 1) | |
7864 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
7865 | "" |
7866 | " | |
4697a36c | 7867 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 7868 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 7869 | rtx neg_op0; |
1fd4e8c1 RK |
7870 | |
7871 | emit_move_insn (chain, stack_bot); | |
4697a36c | 7872 | |
e9a25f70 JL |
7873 | /* Under Windows NT, we need to add stack probes for large/variable |
7874 | allocations, so do it via a call to the external function alloca | |
7875 | instead of doing it inline. */ | |
979721f8 | 7876 | if (DEFAULT_ABI == ABI_NT |
e9a25f70 | 7877 | && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) > 4096)) |
979721f8 | 7878 | { |
a260abc9 | 7879 | rtx tmp = gen_reg_rtx (Pmode); |
c5c76735 JL |
7880 | emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, |
7881 | \"__allocate_stack\"), | |
a260abc9 | 7882 | tmp, 0, Pmode, 1, operands[1], Pmode); |
cea05fab | 7883 | emit_insn (gen_set_sp (tmp)); |
e9a25f70 | 7884 | emit_move_insn (operands[0], tmp); |
979721f8 MM |
7885 | DONE; |
7886 | } | |
7887 | ||
e9a25f70 JL |
7888 | if (GET_CODE (operands[1]) != CONST_INT |
7889 | || INTVAL (operands[1]) < -32767 | |
7890 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
7891 | { |
7892 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 7893 | if (TARGET_32BIT) |
e9a25f70 | 7894 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 7895 | else |
e9a25f70 | 7896 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
7897 | } |
7898 | else | |
e9a25f70 | 7899 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 7900 | |
38c1f2d7 MM |
7901 | if (TARGET_UPDATE) |
7902 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) | |
7903 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); | |
4697a36c | 7904 | |
38c1f2d7 MM |
7905 | else |
7906 | { | |
7907 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
7908 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 7909 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 7910 | } |
e9a25f70 JL |
7911 | |
7912 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
7913 | DONE; |
7914 | }") | |
59257ff7 | 7915 | |
cea05fab MM |
7916 | ;; Marker to indicate that the stack pointer was changed under NT in |
7917 | ;; ways not known to the compiler | |
7918 | ||
7919 | (define_insn "set_sp" | |
7920 | [(set (reg:SI 1) | |
7921 | (unspec [(match_operand:SI 0 "register_operand" "r")] 7))] | |
7922 | "" | |
7923 | "" | |
7924 | [(set_attr "length" "0")]) | |
7925 | ||
59257ff7 RK |
7926 | ;; These patterns say how to save and restore the stack pointer. We need not |
7927 | ;; save the stack pointer at function level since we are careful to | |
7928 | ;; preserve the backchain. At block level, we have to restore the backchain | |
7929 | ;; when we restore the stack pointer. | |
7930 | ;; | |
7931 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
7932 | ;; backchain and restore both. Note that in the nonlocal case, the | |
7933 | ;; save area is a memory location. | |
7934 | ||
7935 | (define_expand "save_stack_function" | |
ff381587 MM |
7936 | [(match_operand 0 "any_operand" "") |
7937 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 7938 | "" |
ff381587 | 7939 | "DONE;") |
59257ff7 RK |
7940 | |
7941 | (define_expand "restore_stack_function" | |
ff381587 MM |
7942 | [(match_operand 0 "any_operand" "") |
7943 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 7944 | "" |
ff381587 | 7945 | "DONE;") |
59257ff7 RK |
7946 | |
7947 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
7948 | [(use (match_operand 0 "register_operand" "")) |
7949 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 7950 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 7951 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
7952 | "" |
7953 | " | |
dfdfa60f DE |
7954 | { |
7955 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 7956 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 7957 | }") |
59257ff7 RK |
7958 | |
7959 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
7960 | [(match_operand 0 "memory_operand" "") |
7961 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
7962 | "" |
7963 | " | |
7964 | { | |
a260abc9 | 7965 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
7966 | |
7967 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 7968 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
c5c76735 JL |
7969 | emit_move_insn (operand_subword (operands[0], 0, 0, |
7970 | (TARGET_32BIT ? DImode : TImode)), | |
a260abc9 DE |
7971 | temp); |
7972 | emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)), | |
7973 | operands[1]); | |
59257ff7 RK |
7974 | DONE; |
7975 | }") | |
7e69e155 | 7976 | |
59257ff7 | 7977 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
7978 | [(match_operand 0 "register_operand" "") |
7979 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
7980 | "" |
7981 | " | |
7982 | { | |
a260abc9 | 7983 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
7984 | |
7985 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 DE |
7986 | emit_move_insn (temp, |
7987 | operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode))); | |
7988 | emit_move_insn (operands[0], | |
c5c76735 JL |
7989 | operand_subword (operands[1], 1, 0, |
7990 | (TARGET_32BIT ? DImode : TImode))); | |
39403d82 | 7991 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
7992 | DONE; |
7993 | }") | |
b6c9286a | 7994 | |
956d6950 | 7995 | ;; If we have -mminimal-toc, we need to reload r30 after a nonlocal goto. |
f0f6a223 RK |
7996 | |
7997 | (define_insn "nonlocal_goto_receiver" | |
7998 | [(unspec_volatile [(const_int 0)] 1)] | |
e9a25f70 | 7999 | "TARGET_TOC && TARGET_MINIMAL_TOC" |
f0f6a223 RK |
8000 | "* |
8001 | { | |
38c1f2d7 | 8002 | rs6000_output_load_toc_table (asm_out_file, 30); |
f0f6a223 RK |
8003 | return \"\"; |
8004 | }" | |
8005 | [(set_attr "type" "load")]) | |
b7ff3d82 | 8006 | \f |
b6c9286a MM |
8007 | ;; A function pointer under AIX is a pointer to a data area whose first word |
8008 | ;; contains the actual address of the function, whose second word contains a | |
8009 | ;; pointer to its TOC, and whose third word contains a value to place in the | |
8010 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 RK |
8011 | ;; "trampoline" need not have any executable code. |
8012 | ;; | |
b6c9286a MM |
8013 | ;; operands[0] is a register pointing to the 3 word descriptor (aka, the function address) |
8014 | ;; operands[1] is the stack size to clean up | |
8015 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for AIX) | |
8016 | ;; operands[3] is location to store the TOC | |
8017 | ;; operands[4] is the TOC register | |
8018 | ;; operands[5] is the static chain register | |
8019 | ;; | |
8020 | ;; We do not break this into separate insns, so that the scheduler will not try | |
8021 | ;; to move the load of the new TOC before any loads from the TOC. | |
8022 | ||
a260abc9 | 8023 | (define_insn "call_indirect_aix32" |
52d3af72 | 8024 | [(call (mem:SI (match_operand:SI 0 "gpc_reg_operand" "b")) |
b6c9286a | 8025 | (match_operand 1 "const_int_operand" "n")) |
6a4cee5f | 8026 | (use (match_operand 2 "const_int_operand" "n")) |
97f6e72f | 8027 | (use (match_operand 3 "offsettable_mem_operand" "o")) |
52d3af72 DE |
8028 | (use (match_operand 4 "gpc_reg_operand" "r")) |
8029 | (clobber (match_operand 5 "gpc_reg_operand" "=r")) | |
b6c9286a MM |
8030 | (clobber (match_scratch:SI 6 "=&r")) |
8031 | (clobber (match_scratch:SI 7 "=l"))] | |
6a4cee5f MM |
8032 | "DEFAULT_ABI == ABI_AIX |
8033 | && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)" | |
97f6e72f | 8034 | "{st|stw} %4,%3\;{l|lwz} %6,0(%0)\;{l|lwz} %4,4(%0)\;mt%7 %6\;{l|lwz} %5,8(%0)\;{brl|blrl}\;{l|lwz} %4,%3" |
b7ff3d82 DE |
8035 | [(set_attr "type" "load") |
8036 | (set_attr "length" "28")]) | |
b6c9286a | 8037 | |
a260abc9 | 8038 | (define_insn "call_indirect_aix64" |
52d3af72 | 8039 | [(call (mem:SI (match_operand:DI 0 "gpc_reg_operand" "b")) |
a260abc9 DE |
8040 | (match_operand 1 "const_int_operand" "n")) |
8041 | (use (match_operand 2 "const_int_operand" "n")) | |
97f6e72f | 8042 | (use (match_operand 3 "offsettable_mem_operand" "o")) |
52d3af72 DE |
8043 | (use (match_operand 4 "gpc_reg_operand" "r")) |
8044 | (clobber (match_operand 5 "gpc_reg_operand" "=r")) | |
a260abc9 DE |
8045 | (clobber (match_scratch:SI 6 "=&r")) |
8046 | (clobber (match_scratch:SI 7 "=l"))] | |
8047 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX | |
8048 | && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)" | |
97f6e72f | 8049 | "std %4,%3\;ld %6,0(%0)\;ld %4,8(%0)\;mt%7 %6\;ld %5,16(%0)\;blrl\;ld %4,%3" |
a260abc9 DE |
8050 | [(set_attr "type" "load") |
8051 | (set_attr "length" "28")]) | |
8052 | ||
8053 | (define_insn "call_value_indirect_aix32" | |
b6c9286a | 8054 | [(set (match_operand 0 "register_operand" "fg") |
52d3af72 | 8055 | (call (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
b6c9286a | 8056 | (match_operand 2 "const_int_operand" "n"))) |
6a4cee5f | 8057 | (use (match_operand 3 "const_int_operand" "n")) |
97f6e72f | 8058 | (use (match_operand 4 "offsettable_mem_operand" "o")) |
52d3af72 DE |
8059 | (use (match_operand 5 "gpc_reg_operand" "r")) |
8060 | (clobber (match_operand 6 "gpc_reg_operand" "=r")) | |
b6c9286a MM |
8061 | (clobber (match_scratch:SI 7 "=&r")) |
8062 | (clobber (match_scratch:SI 8 "=l"))] | |
6a4cee5f MM |
8063 | "DEFAULT_ABI == ABI_AIX |
8064 | && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)" | |
97f6e72f | 8065 | "{st|stw} %5,%4\;{l|lwz} %7,0(%1)\;{l|lwz} %5,4(%1)\;mt%8 %7\;{l|lwz} %6,8(%1)\;{brl|blrl}\;{l|lwz} %5,%4" |
a260abc9 DE |
8066 | [(set_attr "type" "load") |
8067 | (set_attr "length" "28")]) | |
8068 | ||
8069 | (define_insn "call_value_indirect_aix64" | |
8070 | [(set (match_operand 0 "register_operand" "fg") | |
52d3af72 | 8071 | (call (mem:SI (match_operand:DI 1 "gpc_reg_operand" "b")) |
a260abc9 DE |
8072 | (match_operand 2 "const_int_operand" "n"))) |
8073 | (use (match_operand 3 "const_int_operand" "n")) | |
97f6e72f | 8074 | (use (match_operand 4 "offsettable_mem_operand" "o")) |
52d3af72 DE |
8075 | (use (match_operand 5 "gpc_reg_operand" "r")) |
8076 | (clobber (match_operand 6 "gpc_reg_operand" "=r")) | |
a260abc9 DE |
8077 | (clobber (match_scratch:SI 7 "=&r")) |
8078 | (clobber (match_scratch:SI 8 "=l"))] | |
8079 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX | |
8080 | && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)" | |
97f6e72f | 8081 | "std %5,%4\;ld %7,0(%1)\;ld %5,8(%1)\;mt%8 %7\;ld %6,16(%1)\;blrl\;ld %5,%4" |
b7ff3d82 DE |
8082 | [(set_attr "type" "load") |
8083 | (set_attr "length" "28")]) | |
b6c9286a MM |
8084 | |
8085 | ;; A function pointer undef NT is a pointer to a data area whose first word | |
8086 | ;; contains the actual address of the function, whose second word contains a | |
8087 | ;; pointer to its TOC. The static chain is not stored under NT, which means | |
8088 | ;; that we need a trampoline. | |
8089 | ;; | |
8090 | ;; operands[0] is an SImode pseudo in which we place the address of the function. | |
8091 | ;; operands[1] is the stack size to clean up | |
8092 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for NT) | |
8093 | ;; operands[3] is location to store the TOC | |
8094 | ;; operands[4] is the TOC register | |
8095 | ;; | |
8096 | ;; We do not break this into separate insns, so that the scheduler will not try | |
8097 | ;; to move the load of the new TOC before any loads from the TOC. | |
8098 | ||
8099 | (define_insn "call_indirect_nt" | |
52d3af72 | 8100 | [(call (mem:SI (match_operand:SI 0 "gpc_reg_operand" "b")) |
b6c9286a | 8101 | (match_operand 1 "const_int_operand" "n")) |
6a4cee5f | 8102 | (use (match_operand 2 "const_int_operand" "n")) |
97f6e72f | 8103 | (use (match_operand 3 "offsettable_mem_operand" "o")) |
52d3af72 | 8104 | (use (match_operand 4 "gpc_reg_operand" "r")) |
b6c9286a MM |
8105 | (clobber (match_scratch:SI 5 "=&r")) |
8106 | (clobber (match_scratch:SI 6 "=l"))] | |
6a4cee5f MM |
8107 | "DEFAULT_ABI == ABI_NT |
8108 | && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)" | |
e1f83b4d | 8109 | "{st|stw} %4,%a3\;{l|lwz} %5,0(%0)\;{l|lwz} %4,4(%0)\;mt%6 %5\;{brl|blrl}\;{l|lwz} %4,%a3" |
b7ff3d82 DE |
8110 | [(set_attr "type" "load") |
8111 | (set_attr "length" "24")]) | |
b6c9286a MM |
8112 | |
8113 | (define_insn "call_value_indirect_nt" | |
8114 | [(set (match_operand 0 "register_operand" "fg") | |
52d3af72 | 8115 | (call (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
b6c9286a | 8116 | (match_operand 2 "const_int_operand" "n"))) |
6a4cee5f | 8117 | (use (match_operand 3 "const_int_operand" "n")) |
97f6e72f | 8118 | (use (match_operand 4 "offsettable_mem_operand" "o")) |
52d3af72 | 8119 | (use (match_operand 5 "gpc_reg_operand" "r")) |
b6c9286a MM |
8120 | (clobber (match_scratch:SI 6 "=&r")) |
8121 | (clobber (match_scratch:SI 7 "=l"))] | |
6a4cee5f MM |
8122 | "DEFAULT_ABI == ABI_NT |
8123 | && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)" | |
e1f83b4d | 8124 | "{st|stw} %5,%a4\;{l|lwz} %6,0(%1)\;{l|lwz} %5,4(%1)\;mt%7 %6\;{brl|blrl}\;{l|lwz} %5,%a4" |
b7ff3d82 DE |
8125 | [(set_attr "type" "load") |
8126 | (set_attr "length" "24")]) | |
b6c9286a MM |
8127 | |
8128 | ;; A function pointer under System V is just a normal pointer | |
8129 | ;; operands[0] is the function pointer | |
8130 | ;; operands[1] is the stack size to clean up | |
8131 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument which indicates how to set cr1 | |
8132 | ||
8133 | (define_insn "call_indirect_sysv" | |
8134 | [(call (mem:SI (match_operand:SI 0 "register_operand" "l,l")) | |
8135 | (match_operand 1 "const_int_operand" "n,n")) | |
8136 | (use (match_operand 2 "const_int_operand" "O,n")) | |
8137 | (clobber (match_scratch:SI 3 "=l,l"))] | |
c81bebd7 | 8138 | "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC" |
b6c9286a MM |
8139 | "* |
8140 | { | |
6a4cee5f MM |
8141 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
8142 | output_asm_insn (\"crxor 6,6,6\", operands); | |
1fd4e8c1 | 8143 | |
6a4cee5f MM |
8144 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
8145 | output_asm_insn (\"creqv 6,6,6\", operands); | |
b6c9286a MM |
8146 | |
8147 | return \"{brl|blrl}\"; | |
8148 | }" | |
b7ff3d82 DE |
8149 | [(set_attr "type" "jmpreg") |
8150 | (set_attr "length" "4,8")]) | |
b6c9286a MM |
8151 | |
8152 | (define_insn "call_value_indirect_sysv" | |
8153 | [(set (match_operand 0 "register_operand" "=fg,fg") | |
8154 | (call (mem:SI (match_operand:SI 1 "register_operand" "l,l")) | |
8155 | (match_operand 2 "const_int_operand" "n,n"))) | |
8156 | (use (match_operand 3 "const_int_operand" "O,n")) | |
8157 | (clobber (match_scratch:SI 4 "=l,l"))] | |
c81bebd7 | 8158 | "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC" |
b6c9286a MM |
8159 | "* |
8160 | { | |
6a4cee5f MM |
8161 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
8162 | output_asm_insn (\"crxor 6,6,6\", operands); | |
b6c9286a | 8163 | |
6a4cee5f MM |
8164 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) |
8165 | output_asm_insn (\"creqv 6,6,6\", operands); | |
b6c9286a MM |
8166 | |
8167 | return \"{brl|blrl}\"; | |
8168 | }" | |
b7ff3d82 DE |
8169 | [(set_attr "type" "jmpreg") |
8170 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 8171 | |
b6c9286a | 8172 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 8173 | (define_expand "call" |
a260abc9 | 8174 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 8175 | (match_operand 1 "" "")) |
4697a36c | 8176 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
8177 | (clobber (scratch:SI))])] |
8178 | "" | |
8179 | " | |
8180 | { | |
8181 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) | |
8182 | abort (); | |
8183 | ||
8184 | operands[0] = XEXP (operands[0], 0); | |
7509c759 MM |
8185 | |
8186 | /* Convert NT DLL imports into an indirect call. */ | |
8187 | if (GET_CODE (operands[0]) == SYMBOL_REF | |
6a4cee5f | 8188 | && (INTVAL (operands[2]) & CALL_NT_DLLIMPORT) != 0) |
7509c759 MM |
8189 | { |
8190 | operands[0] = rs6000_dll_import_ref (operands[0]); | |
8191 | operands[2] = GEN_INT ((int)CALL_NORMAL); | |
8192 | } | |
8193 | ||
6a4cee5f MM |
8194 | if (GET_CODE (operands[0]) != SYMBOL_REF |
8195 | || (INTVAL (operands[2]) & CALL_LONG) != 0) | |
1fd4e8c1 | 8196 | { |
6a4cee5f MM |
8197 | if (INTVAL (operands[2]) & CALL_LONG) |
8198 | operands[0] = rs6000_longcall_ref (operands[0]); | |
8199 | ||
c81bebd7 | 8200 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS) |
b6c9286a MM |
8201 | emit_call_insn (gen_call_indirect_sysv (force_reg (Pmode, operands[0]), |
8202 | operands[1], operands[2])); | |
8203 | else | |
8204 | { | |
39403d82 | 8205 | rtx toc_reg = gen_rtx_REG (Pmode, 2); |
b6c9286a | 8206 | rtx toc_addr = RS6000_SAVE_TOC; |
1fd4e8c1 | 8207 | |
b6c9286a MM |
8208 | if (DEFAULT_ABI == ABI_AIX) |
8209 | { | |
c5c76735 JL |
8210 | /* AIX function pointers are really pointers to a three word |
8211 | area. */ | |
39403d82 | 8212 | rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); |
a260abc9 DE |
8213 | emit_call_insn (TARGET_32BIT |
8214 | ? gen_call_indirect_aix32 (force_reg (Pmode, operands[0]), | |
8215 | operands[1], operands[2], | |
8216 | toc_addr, toc_reg, static_chain) | |
8217 | : gen_call_indirect_aix64 (force_reg (Pmode, operands[0]), | |
8218 | operands[1], operands[2], | |
8219 | toc_addr, toc_reg, static_chain)); | |
b6c9286a MM |
8220 | } |
8221 | else if (DEFAULT_ABI == ABI_NT) | |
8222 | { | |
8223 | /* NT function pointers are really pointers to a two word area */ | |
8224 | emit_call_insn (gen_call_indirect_nt (force_reg (Pmode, operands[0]), | |
8225 | operands[1], operands[2], | |
8226 | toc_addr, toc_reg)); | |
8227 | } | |
8228 | else | |
8229 | abort (); | |
8230 | } | |
8231 | DONE; | |
1fd4e8c1 RK |
8232 | } |
8233 | }") | |
8234 | ||
8235 | (define_expand "call_value" | |
8236 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 8237 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 8238 | (match_operand 2 "" ""))) |
4697a36c | 8239 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
8240 | (clobber (scratch:SI))])] |
8241 | "" | |
8242 | " | |
8243 | { | |
8244 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) | |
8245 | abort (); | |
8246 | ||
8247 | operands[1] = XEXP (operands[1], 0); | |
7509c759 MM |
8248 | |
8249 | /* Convert NT DLL imports into an indirect call. */ | |
8250 | if (GET_CODE (operands[1]) == SYMBOL_REF | |
6a4cee5f | 8251 | && (INTVAL (operands[3]) & CALL_NT_DLLIMPORT) != 0) |
7509c759 MM |
8252 | { |
8253 | operands[1] = rs6000_dll_import_ref (operands[1]); | |
8254 | operands[3] = GEN_INT ((int)CALL_NORMAL); | |
8255 | } | |
8256 | ||
6a4cee5f MM |
8257 | if (GET_CODE (operands[1]) != SYMBOL_REF |
8258 | || (INTVAL (operands[3]) & CALL_LONG) != 0) | |
1fd4e8c1 | 8259 | { |
6756293c | 8260 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
8261 | operands[1] = rs6000_longcall_ref (operands[1]); |
8262 | ||
c81bebd7 | 8263 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS) |
b6c9286a MM |
8264 | emit_call_insn (gen_call_value_indirect_sysv (operands[0], operands[1], |
8265 | operands[2], operands[3])); | |
8266 | else | |
8267 | { | |
39403d82 | 8268 | rtx toc_reg = gen_rtx_REG (Pmode, 2); |
b6c9286a | 8269 | rtx toc_addr = RS6000_SAVE_TOC; |
1fd4e8c1 | 8270 | |
b6c9286a MM |
8271 | if (DEFAULT_ABI == ABI_AIX) |
8272 | { | |
c5c76735 JL |
8273 | /* AIX function pointers are really pointers to a three word |
8274 | area. */ | |
39403d82 | 8275 | rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); |
a260abc9 DE |
8276 | emit_call_insn (TARGET_32BIT |
8277 | ? gen_call_value_indirect_aix32 (operands[0], | |
8278 | force_reg (Pmode, operands[1]), | |
8279 | operands[2], operands[3], | |
8280 | toc_addr, toc_reg, static_chain) | |
8281 | : gen_call_value_indirect_aix64 (operands[0], | |
8282 | force_reg (Pmode, operands[1]), | |
8283 | operands[2], operands[3], | |
8284 | toc_addr, toc_reg, static_chain)); | |
b6c9286a MM |
8285 | } |
8286 | else if (DEFAULT_ABI == ABI_NT) | |
8287 | { | |
8288 | /* NT function pointers are really pointers to a two word area */ | |
8289 | emit_call_insn (gen_call_value_indirect_nt (operands[0], | |
8290 | force_reg (Pmode, operands[1]), | |
8291 | operands[2], operands[3], | |
8292 | toc_addr, toc_reg)); | |
8293 | } | |
8294 | else | |
8295 | abort (); | |
8296 | } | |
8297 | DONE; | |
1fd4e8c1 RK |
8298 | } |
8299 | }") | |
8300 | ||
04780ee7 | 8301 | ;; Call to function in current module. No TOC pointer reload needed. |
4697a36c MM |
8302 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
8303 | ;; either the function was not prototyped, or it was prototyped as a | |
8304 | ;; variable argument function. It is > 0 if FP registers were passed | |
8305 | ;; and < 0 if they were not. | |
04780ee7 | 8306 | |
a260abc9 | 8307 | (define_insn "*call_local32" |
4697a36c MM |
8308 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
8309 | (match_operand 1 "" "g,g")) | |
8310 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
8311 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 8312 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
8313 | "* |
8314 | { | |
6a4cee5f MM |
8315 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
8316 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8317 | ||
8318 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
8319 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 8320 | |
a226df46 | 8321 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 8322 | }" |
b7ff3d82 DE |
8323 | [(set_attr "type" "branch") |
8324 | (set_attr "length" "4,8")]) | |
04780ee7 | 8325 | |
a260abc9 DE |
8326 | (define_insn "*call_local64" |
8327 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
8328 | (match_operand 1 "" "g,g")) | |
8329 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
8330 | (clobber (match_scratch:SI 3 "=l,l"))] | |
8331 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
8332 | "* | |
8333 | { | |
8334 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
8335 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8336 | ||
8337 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
8338 | output_asm_insn (\"creqv 6,6,6\", operands); | |
8339 | ||
8340 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
8341 | }" | |
8342 | [(set_attr "type" "branch") | |
8343 | (set_attr "length" "4,8")]) | |
8344 | ||
8345 | (define_insn "*ret_call_local32" | |
8346 | [(set (match_operand 0 "" "=fg,fg") | |
8347 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
8348 | (match_operand 2 "" "g,g"))) | |
8349 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
8350 | (clobber (match_scratch:SI 4 "=l,l"))] | |
8351 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
8352 | "* | |
8353 | { | |
8354 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
8355 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8356 | ||
8357 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
8358 | output_asm_insn (\"creqv 6,6,6\", operands); | |
8359 | ||
8360 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
8361 | }" | |
8362 | [(set_attr "type" "branch") | |
8363 | (set_attr "length" "4,8")]) | |
8364 | ||
8365 | ||
8366 | (define_insn "*ret_call_local64" | |
8367 | [(set (match_operand 0 "" "=fg,fg") | |
8368 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
8369 | (match_operand 2 "" "g,g"))) | |
8370 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
8371 | (clobber (match_scratch:SI 4 "=l,l"))] | |
8372 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
8373 | "* | |
8374 | { | |
8375 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
8376 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8377 | ||
8378 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
8379 | output_asm_insn (\"creqv 6,6,6\", operands); | |
8380 | ||
8381 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
8382 | }" | |
8383 | [(set_attr "type" "branch") | |
8384 | (set_attr "length" "4,8")]) | |
8385 | ||
04780ee7 | 8386 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 8387 | ;; pointer (r2) after the call unless this is System V. |
4697a36c MM |
8388 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
8389 | ;; either the function was not prototyped, or it was prototyped as a | |
8390 | ;; variable argument function. It is > 0 if FP registers were passed | |
8391 | ;; and < 0 if they were not. | |
04780ee7 | 8392 | |
a260abc9 | 8393 | (define_insn "*call_nonlocal_aix32" |
b6c9286a MM |
8394 | [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s")) |
8395 | (match_operand 1 "" "fg,fg")) | |
8396 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
8397 | (clobber (match_scratch:SI 3 "=l,l"))] | |
6a4cee5f | 8398 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) |
5a19791c | 8399 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
911f679c MM |
8400 | "* |
8401 | { | |
b6c9286a | 8402 | /* Indirect calls should go through call_indirect */ |
0f07e76c | 8403 | if (GET_CODE (operands[0]) == REG) |
b6c9286a | 8404 | abort (); |
911f679c | 8405 | |
6a4cee5f MM |
8406 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
8407 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8408 | ||
8409 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
8410 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 8411 | |
b6c9286a MM |
8412 | return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\"; |
8413 | }" | |
b7ff3d82 DE |
8414 | [(set_attr "type" "branch") |
8415 | (set_attr "length" "8,12")]) | |
59313e4e | 8416 | |
a260abc9 DE |
8417 | (define_insn "*call_nonlocal_aix64" |
8418 | [(call (mem:SI (match_operand:DI 0 "call_operand" "s,s")) | |
8419 | (match_operand 1 "" "fg,fg")) | |
8420 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
8421 | (clobber (match_scratch:SI 3 "=l,l"))] | |
8422 | "TARGET_64BIT && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) | |
8423 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
8424 | "* | |
8425 | { | |
8426 | /* Indirect calls should go through call_indirect */ | |
8427 | if (GET_CODE (operands[0]) == REG) | |
8428 | abort (); | |
8429 | ||
8430 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
8431 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8432 | ||
8433 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
8434 | output_asm_insn (\"creqv 6,6,6\", operands); | |
8435 | ||
8436 | return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\"; | |
8437 | }" | |
8438 | [(set_attr "type" "branch") | |
8439 | (set_attr "length" "8,12")]) | |
8440 | ||
8441 | (define_insn "*call_nonlocal_sysv" | |
b6c9286a MM |
8442 | [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s")) |
8443 | (match_operand 1 "" "fg,fg")) | |
8444 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
8445 | (clobber (match_scratch:SI 3 "=l,l"))] | |
c81bebd7 | 8446 | "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5a19791c | 8447 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
b6c9286a MM |
8448 | "* |
8449 | { | |
b6c9286a | 8450 | /* Indirect calls should go through call_indirect */ |
0f07e76c | 8451 | if (GET_CODE (operands[0]) == REG) |
b6c9286a | 8452 | abort (); |
59313e4e | 8453 | |
6a4cee5f MM |
8454 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
8455 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8456 | ||
8457 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
8458 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 8459 | |
a226df46 | 8460 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\"; |
911f679c | 8461 | }" |
b7ff3d82 DE |
8462 | [(set_attr "type" "branch") |
8463 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 8464 | |
a260abc9 | 8465 | (define_insn "*ret_call_nonlocal_aix32" |
4697a36c | 8466 | [(set (match_operand 0 "" "=fg,fg") |
a260abc9 DE |
8467 | (call (mem:SI (match_operand:SI 1 "call_operand" "s,s")) |
8468 | (match_operand 2 "" "fg,fg"))) | |
4697a36c MM |
8469 | (use (match_operand:SI 3 "immediate_operand" "O,n")) |
8470 | (clobber (match_scratch:SI 4 "=l,l"))] | |
a260abc9 DE |
8471 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) |
8472 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
4697a36c MM |
8473 | "* |
8474 | { | |
a260abc9 DE |
8475 | /* This should be handled by call_value_indirect */ |
8476 | if (GET_CODE (operands[1]) == REG) | |
8477 | abort (); | |
8478 | ||
6a4cee5f MM |
8479 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
8480 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8481 | ||
8482 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
8483 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 8484 | |
a260abc9 | 8485 | return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\"; |
4697a36c | 8486 | }" |
b7ff3d82 | 8487 | [(set_attr "type" "branch") |
a260abc9 | 8488 | (set_attr "length" "8,12")]) |
04780ee7 | 8489 | |
a260abc9 | 8490 | (define_insn "*ret_call_nonlocal_aix64" |
b6c9286a | 8491 | [(set (match_operand 0 "" "=fg,fg") |
a260abc9 | 8492 | (call (mem:SI (match_operand:DI 1 "call_operand" "s,s")) |
b6c9286a MM |
8493 | (match_operand 2 "" "fg,fg"))) |
8494 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
8495 | (clobber (match_scratch:SI 4 "=l,l"))] | |
a260abc9 | 8496 | "TARGET_64BIT && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) |
5a19791c | 8497 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
911f679c MM |
8498 | "* |
8499 | { | |
b6c9286a | 8500 | /* This should be handled by call_value_indirect */ |
59313e4e | 8501 | if (GET_CODE (operands[1]) == REG) |
b6c9286a MM |
8502 | abort (); |
8503 | ||
6a4cee5f MM |
8504 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
8505 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8506 | ||
8507 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
8508 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 8509 | |
b6c9286a MM |
8510 | return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\"; |
8511 | }" | |
b7ff3d82 DE |
8512 | [(set_attr "type" "branch") |
8513 | (set_attr "length" "8,12")]) | |
b6c9286a | 8514 | |
a260abc9 | 8515 | (define_insn "*ret_call_nonlocal_sysv" |
b6c9286a MM |
8516 | [(set (match_operand 0 "" "=fg,fg") |
8517 | (call (mem:SI (match_operand:SI 1 "call_operand" "s,s")) | |
8518 | (match_operand 2 "" "fg,fg"))) | |
8519 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
8520 | (clobber (match_scratch:SI 4 "=l,l"))] | |
c81bebd7 | 8521 | "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5a19791c | 8522 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
b6c9286a MM |
8523 | "* |
8524 | { | |
b6c9286a | 8525 | /* This should be handled by call_value_indirect */ |
59313e4e | 8526 | if (GET_CODE (operands[1]) == REG) |
b6c9286a | 8527 | abort (); |
59313e4e | 8528 | |
6a4cee5f MM |
8529 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
8530 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8531 | ||
8532 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
8533 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 8534 | |
a226df46 | 8535 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\"; |
911f679c | 8536 | }" |
b7ff3d82 DE |
8537 | [(set_attr "type" "branch") |
8538 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
8539 | |
8540 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
8541 | (define_expand "untyped_call" |
8542 | [(parallel [(call (match_operand 0 "" "") | |
8543 | (const_int 0)) | |
8544 | (match_operand 1 "" "") | |
8545 | (match_operand 2 "" "")])] | |
8546 | "" | |
8547 | " | |
8548 | { | |
8549 | int i; | |
8550 | ||
4697a36c | 8551 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
8552 | |
8553 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
8554 | { | |
8555 | rtx set = XVECEXP (operands[2], 0, i); | |
8556 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
8557 | } | |
8558 | ||
8559 | /* The optimizer does not know that the call sets the function value | |
8560 | registers we stored in the result block. We avoid problems by | |
8561 | claiming that all hard registers are used and clobbered at this | |
8562 | point. */ | |
8563 | emit_insn (gen_blockage ()); | |
8564 | ||
8565 | DONE; | |
8566 | }") | |
8567 | ||
8568 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
8569 | ;; all of memory. This blocks insns from being moved across this point. | |
8570 | ||
8571 | (define_insn "blockage" | |
8572 | [(unspec_volatile [(const_int 0)] 0)] | |
8573 | "" | |
8574 | "") | |
4697a36c | 8575 | |
766a866c MM |
8576 | ;; V.4 specific code to initialize the PIC register |
8577 | ||
8578 | (define_insn "init_v4_pic" | |
8579 | [(set (match_operand:SI 0 "register_operand" "=l") | |
8580 | (unspec [(const_int 0)] 7))] | |
c81bebd7 | 8581 | "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS" |
eaf1bcf1 | 8582 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
63d7d7a1 MM |
8583 | [(set_attr "type" "branch") |
8584 | (set_attr "length" "4")]) | |
766a866c | 8585 | |
1fd4e8c1 RK |
8586 | \f |
8587 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 8588 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
8589 | ;; |
8590 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
8591 | ;; insns, and branches. We store the operands of compares until we see | |
8592 | ;; how it is used. | |
8593 | (define_expand "cmpsi" | |
8594 | [(set (cc0) | |
cd2b37d9 | 8595 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8596 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
8597 | "" | |
8598 | " | |
8599 | { | |
8600 | /* Take care of the possibility that operands[1] might be negative but | |
8601 | this might be a logical operation. That insn doesn't exist. */ | |
8602 | if (GET_CODE (operands[1]) == CONST_INT | |
8603 | && INTVAL (operands[1]) < 0) | |
8604 | operands[1] = force_reg (SImode, operands[1]); | |
8605 | ||
8606 | rs6000_compare_op0 = operands[0]; | |
8607 | rs6000_compare_op1 = operands[1]; | |
8608 | rs6000_compare_fp_p = 0; | |
8609 | DONE; | |
8610 | }") | |
8611 | ||
266eb58a DE |
8612 | (define_expand "cmpdi" |
8613 | [(set (cc0) | |
8614 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
8615 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
8616 | "TARGET_POWERPC64" | |
8617 | " | |
8618 | { | |
8619 | /* Take care of the possibility that operands[1] might be negative but | |
8620 | this might be a logical operation. That insn doesn't exist. */ | |
8621 | if (GET_CODE (operands[1]) == CONST_INT | |
8622 | && INTVAL (operands[1]) < 0) | |
8623 | operands[1] = force_reg (DImode, operands[1]); | |
8624 | ||
8625 | rs6000_compare_op0 = operands[0]; | |
8626 | rs6000_compare_op1 = operands[1]; | |
8627 | rs6000_compare_fp_p = 0; | |
8628 | DONE; | |
8629 | }") | |
8630 | ||
1fd4e8c1 | 8631 | (define_expand "cmpsf" |
cd2b37d9 RK |
8632 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
8633 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 8634 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
8635 | " |
8636 | { | |
8637 | rs6000_compare_op0 = operands[0]; | |
8638 | rs6000_compare_op1 = operands[1]; | |
8639 | rs6000_compare_fp_p = 1; | |
8640 | DONE; | |
8641 | }") | |
8642 | ||
8643 | (define_expand "cmpdf" | |
cd2b37d9 RK |
8644 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
8645 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 8646 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
8647 | " |
8648 | { | |
8649 | rs6000_compare_op0 = operands[0]; | |
8650 | rs6000_compare_op1 = operands[1]; | |
8651 | rs6000_compare_fp_p = 1; | |
8652 | DONE; | |
8653 | }") | |
8654 | ||
8655 | (define_expand "beq" | |
8656 | [(set (match_dup 2) (match_dup 1)) | |
8657 | (set (pc) | |
8658 | (if_then_else (eq (match_dup 2) | |
8659 | (const_int 0)) | |
8660 | (label_ref (match_operand 0 "" "")) | |
8661 | (pc)))] | |
8662 | "" | |
8663 | " | |
8664 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8665 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 8666 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8667 | operands[2] = gen_reg_rtx (mode); |
8668 | }") | |
8669 | ||
8670 | (define_expand "bne" | |
8671 | [(set (match_dup 2) (match_dup 1)) | |
8672 | (set (pc) | |
8673 | (if_then_else (ne (match_dup 2) | |
8674 | (const_int 0)) | |
8675 | (label_ref (match_operand 0 "" "")) | |
8676 | (pc)))] | |
8677 | "" | |
8678 | " | |
8679 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8680 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 8681 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8682 | operands[2] = gen_reg_rtx (mode); |
8683 | }") | |
8684 | ||
8685 | (define_expand "blt" | |
8686 | [(set (match_dup 2) (match_dup 1)) | |
8687 | (set (pc) | |
8688 | (if_then_else (lt (match_dup 2) | |
8689 | (const_int 0)) | |
8690 | (label_ref (match_operand 0 "" "")) | |
8691 | (pc)))] | |
8692 | "" | |
8693 | " | |
8694 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8695 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 8696 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8697 | operands[2] = gen_reg_rtx (mode); |
8698 | }") | |
8699 | ||
8700 | (define_expand "bgt" | |
8701 | [(set (match_dup 2) (match_dup 1)) | |
8702 | (set (pc) | |
8703 | (if_then_else (gt (match_dup 2) | |
8704 | (const_int 0)) | |
8705 | (label_ref (match_operand 0 "" "")) | |
8706 | (pc)))] | |
8707 | "" | |
8708 | " | |
8709 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8710 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 8711 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8712 | operands[2] = gen_reg_rtx (mode); |
8713 | }") | |
8714 | ||
8715 | (define_expand "ble" | |
8716 | [(set (match_dup 2) (match_dup 1)) | |
8717 | (set (pc) | |
8718 | (if_then_else (le (match_dup 2) | |
8719 | (const_int 0)) | |
8720 | (label_ref (match_operand 0 "" "")) | |
8721 | (pc)))] | |
8722 | "" | |
8723 | " | |
8724 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8725 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 8726 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8727 | operands[2] = gen_reg_rtx (mode); |
8728 | }") | |
8729 | ||
8730 | (define_expand "bge" | |
8731 | [(set (match_dup 2) (match_dup 1)) | |
8732 | (set (pc) | |
8733 | (if_then_else (ge (match_dup 2) | |
8734 | (const_int 0)) | |
8735 | (label_ref (match_operand 0 "" "")) | |
8736 | (pc)))] | |
8737 | "" | |
8738 | " | |
8739 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8740 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 8741 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8742 | operands[2] = gen_reg_rtx (mode); |
8743 | }") | |
8744 | ||
8745 | (define_expand "bgtu" | |
8746 | [(set (match_dup 2) (match_dup 1)) | |
8747 | (set (pc) | |
8748 | (if_then_else (gtu (match_dup 2) | |
8749 | (const_int 0)) | |
8750 | (label_ref (match_operand 0 "" "")) | |
8751 | (pc)))] | |
8752 | "" | |
8753 | " | |
39403d82 | 8754 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
c5c76735 | 8755 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8756 | operands[2] = gen_reg_rtx (CCUNSmode); |
8757 | }") | |
8758 | ||
8759 | (define_expand "bltu" | |
8760 | [(set (match_dup 2) (match_dup 1)) | |
8761 | (set (pc) | |
8762 | (if_then_else (ltu (match_dup 2) | |
8763 | (const_int 0)) | |
8764 | (label_ref (match_operand 0 "" "")) | |
8765 | (pc)))] | |
8766 | "" | |
8767 | " | |
39403d82 | 8768 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
c5c76735 | 8769 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8770 | operands[2] = gen_reg_rtx (CCUNSmode); |
8771 | }") | |
8772 | ||
8773 | (define_expand "bgeu" | |
8774 | [(set (match_dup 2) (match_dup 1)) | |
8775 | (set (pc) | |
8776 | (if_then_else (geu (match_dup 2) | |
8777 | (const_int 0)) | |
8778 | (label_ref (match_operand 0 "" "")) | |
8779 | (pc)))] | |
8780 | "" | |
8781 | " | |
39403d82 | 8782 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
c5c76735 | 8783 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8784 | operands[2] = gen_reg_rtx (CCUNSmode); |
8785 | }") | |
8786 | ||
8787 | (define_expand "bleu" | |
8788 | [(set (match_dup 2) (match_dup 1)) | |
8789 | (set (pc) | |
8790 | (if_then_else (leu (match_dup 2) | |
8791 | (const_int 0)) | |
8792 | (label_ref (match_operand 0 "" "")) | |
8793 | (pc)))] | |
8794 | "" | |
8795 | " | |
39403d82 | 8796 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
c5c76735 | 8797 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8798 | operands[2] = gen_reg_rtx (CCUNSmode); |
8799 | }") | |
8800 | ||
8801 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. | |
8802 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
8803 | ;; with an scc insns. However, due to the order that combine see the | |
8804 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
8805 | ;; the cases we don't want to handle. | |
8806 | (define_expand "seq" | |
8807 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8808 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8809 | (eq:SI (match_dup 2) (const_int 0)))] |
8810 | "" | |
8811 | " | |
8812 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8813 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 8814 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8815 | operands[2] = gen_reg_rtx (mode); |
8816 | }") | |
8817 | ||
8818 | (define_expand "sne" | |
8819 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8820 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8821 | (ne:SI (match_dup 2) (const_int 0)))] |
8822 | "" | |
8823 | " | |
8824 | { if (! rs6000_compare_fp_p) | |
8825 | FAIL; | |
8826 | ||
39403d82 | 8827 | operands[1] = gen_rtx_COMPARE (CCFPmode, |
c5c76735 | 8828 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8829 | operands[2] = gen_reg_rtx (CCFPmode); |
8830 | }") | |
8831 | ||
8832 | ;; A > 0 is best done using the portable sequence, so fail in that case. | |
8833 | (define_expand "sgt" | |
8834 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8835 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8836 | (gt:SI (match_dup 2) (const_int 0)))] |
8837 | "" | |
8838 | " | |
8839 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
8840 | ||
8841 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
8842 | FAIL; | |
8843 | ||
39403d82 | 8844 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 8845 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8846 | operands[2] = gen_reg_rtx (mode); |
8847 | }") | |
8848 | ||
8849 | ;; A < 0 is best done in the portable way for A an integer. | |
8850 | (define_expand "slt" | |
8851 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8852 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8853 | (lt:SI (match_dup 2) (const_int 0)))] |
8854 | "" | |
8855 | " | |
8856 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
8857 | ||
8858 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
8859 | FAIL; | |
8860 | ||
39403d82 | 8861 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 8862 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8863 | operands[2] = gen_reg_rtx (mode); |
8864 | }") | |
8865 | ||
8866 | (define_expand "sge" | |
8867 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8868 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8869 | (ge:SI (match_dup 2) (const_int 0)))] |
8870 | "" | |
8871 | " | |
8872 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8873 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 8874 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8875 | operands[2] = gen_reg_rtx (mode); |
8876 | }") | |
8877 | ||
8878 | ;; A <= 0 is best done the portable way for A an integer. | |
8879 | (define_expand "sle" | |
8880 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8881 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8882 | (le:SI (match_dup 2) (const_int 0)))] |
8883 | "" | |
8884 | " | |
8885 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
8886 | ||
8887 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
8888 | FAIL; | |
8889 | ||
39403d82 | 8890 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 8891 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8892 | operands[2] = gen_reg_rtx (mode); |
8893 | }") | |
8894 | ||
8895 | (define_expand "sgtu" | |
8896 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8897 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8898 | (gtu:SI (match_dup 2) (const_int 0)))] |
8899 | "" | |
8900 | " | |
39403d82 | 8901 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
c5c76735 | 8902 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8903 | operands[2] = gen_reg_rtx (CCUNSmode); |
8904 | }") | |
8905 | ||
8906 | (define_expand "sltu" | |
8907 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8908 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8909 | (ltu:SI (match_dup 2) (const_int 0)))] |
8910 | "" | |
8911 | " | |
39403d82 | 8912 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
c5c76735 | 8913 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8914 | operands[2] = gen_reg_rtx (CCUNSmode); |
8915 | }") | |
8916 | ||
8917 | (define_expand "sgeu" | |
8918 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8919 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8920 | (geu:SI (match_dup 2) (const_int 0)))] |
8921 | "" | |
8922 | " | |
39403d82 | 8923 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
c5c76735 | 8924 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8925 | operands[2] = gen_reg_rtx (CCUNSmode); |
8926 | }") | |
8927 | ||
8928 | (define_expand "sleu" | |
8929 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8930 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8931 | (leu:SI (match_dup 2) (const_int 0)))] |
8932 | "" | |
8933 | " | |
39403d82 | 8934 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
c5c76735 | 8935 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
8936 | operands[2] = gen_reg_rtx (CCUNSmode); |
8937 | }") | |
8938 | \f | |
8939 | ;; Here are the actual compare insns. | |
8940 | (define_insn "" | |
8941 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
cd2b37d9 | 8942 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
8943 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
8944 | "" | |
7f340546 | 8945 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
1fd4e8c1 RK |
8946 | [(set_attr "type" "compare")]) |
8947 | ||
266eb58a DE |
8948 | (define_insn "" |
8949 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
8950 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
8951 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
8952 | "TARGET_POWERPC64" | |
8953 | "cmpd%I2 %0,%1,%2" | |
8954 | [(set_attr "type" "compare")]) | |
8955 | ||
f357808b RK |
8956 | ;; If we are comparing a register for equality with a large constant, |
8957 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
8958 | ;; register for the result of the XOR. | |
8959 | ||
8960 | (define_split | |
8961 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 8962 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 8963 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 8964 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
8965 | "find_single_use (operands[0], insn, 0) |
8966 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
8967 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
8968 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
8969 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
8970 | " | |
8971 | { | |
8972 | /* Get the constant we are comparing against, C, and see what it looks like | |
8973 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
8974 | with C to get the sign-extended value. */ | |
8975 | ||
5f59ecb7 DE |
8976 | HOST_WIDE_INT c = INTVAL (operands[2]); |
8977 | HOST_WIDE_INT sextc = (c & 0x7fff) - (c & 0x8000); | |
8978 | HOST_WIDE_INT xorv = c ^ sextc; | |
f357808b | 8979 | |
89e9f3a8 MM |
8980 | operands[4] = GEN_INT (xorv); |
8981 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
8982 | }") |
8983 | ||
1fd4e8c1 RK |
8984 | (define_insn "" |
8985 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") | |
cd2b37d9 | 8986 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
8987 | (match_operand:SI 2 "reg_or_u_short_operand" "rI")))] |
8988 | "" | |
7f340546 | 8989 | "{cmpl%I2|cmplw%I2} %0,%1,%W2" |
1fd4e8c1 RK |
8990 | [(set_attr "type" "compare")]) |
8991 | ||
266eb58a DE |
8992 | (define_insn "" |
8993 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") | |
8994 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
8995 | (match_operand:DI 2 "reg_or_u_short_operand" "rI")))] | |
8996 | "" | |
8997 | "cmpld%I2 %0,%1,%W2" | |
8998 | [(set_attr "type" "compare")]) | |
8999 | ||
1fd4e8c1 RK |
9000 | ;; The following two insns don't exist as single insns, but if we provide |
9001 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
9002 | ;; of the required delay between a compare and branch. We generate code for | |
9003 | ;; them by splitting. | |
9004 | ||
9005 | (define_insn "" | |
9006 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 9007 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 9008 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 9009 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9010 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
9011 | "" | |
baf97f86 RK |
9012 | "#" |
9013 | [(set_attr "length" "8")]) | |
7e69e155 | 9014 | |
1fd4e8c1 RK |
9015 | (define_insn "" |
9016 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 9017 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 9018 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 9019 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9020 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
9021 | "" | |
baf97f86 RK |
9022 | "#" |
9023 | [(set_attr "length" "8")]) | |
7e69e155 | 9024 | |
1fd4e8c1 RK |
9025 | (define_split |
9026 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 9027 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 9028 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 9029 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
9030 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
9031 | "" | |
9032 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
9033 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
9034 | ||
9035 | (define_split | |
9036 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 9037 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 9038 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 9039 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
9040 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
9041 | "" | |
9042 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
9043 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
9044 | ||
9045 | (define_insn "" | |
9046 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
cd2b37d9 RK |
9047 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
9048 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 9049 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
9050 | "fcmpu %0,%1,%2" |
9051 | [(set_attr "type" "fpcompare")]) | |
9052 | ||
9053 | (define_insn "" | |
9054 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
cd2b37d9 RK |
9055 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
9056 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 9057 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
9058 | "fcmpu %0,%1,%2" |
9059 | [(set_attr "type" "fpcompare")]) | |
9060 | \f | |
9061 | ;; Now we have the scc insns. We can do some combinations because of the | |
9062 | ;; way the machine works. | |
9063 | ;; | |
9064 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
9065 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
9066 | ;; cases the insns below which don't use an intermediate CR field will | |
9067 | ;; be used instead. | |
1fd4e8c1 | 9068 | (define_insn "" |
cd2b37d9 | 9069 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9070 | (match_operator:SI 1 "scc_comparison_operator" |
9071 | [(match_operand 2 "cc_reg_operand" "y") | |
9072 | (const_int 0)]))] | |
9073 | "" | |
ca7f5001 | 9074 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" |
b19003d8 | 9075 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9076 | |
9077 | (define_insn "" | |
9078 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
9079 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
9080 | [(match_operand 2 "cc_reg_operand" "y") | |
9081 | (const_int 0)]) | |
9082 | (const_int 0))) | |
cd2b37d9 | 9083 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9084 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
0ad91047 | 9085 | "! TARGET_POWERPC64" |
ca7f5001 | 9086 | "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1" |
b19003d8 RK |
9087 | [(set_attr "type" "delayed_compare") |
9088 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
9089 | |
9090 | (define_insn "" | |
cd2b37d9 | 9091 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9092 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
9093 | [(match_operand 2 "cc_reg_operand" "y") | |
9094 | (const_int 0)]) | |
9095 | (match_operand:SI 3 "const_int_operand" "n")))] | |
9096 | "" | |
9097 | "* | |
9098 | { | |
9099 | int is_bit = ccr_bit (operands[1], 1); | |
9100 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
9101 | int count; | |
9102 | ||
9103 | if (is_bit >= put_bit) | |
9104 | count = is_bit - put_bit; | |
9105 | else | |
9106 | count = 32 - (put_bit - is_bit); | |
9107 | ||
89e9f3a8 MM |
9108 | operands[4] = GEN_INT (count); |
9109 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 9110 | |
ca7f5001 | 9111 | return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 RK |
9112 | }" |
9113 | [(set_attr "length" "12")]) | |
1fd4e8c1 RK |
9114 | |
9115 | (define_insn "" | |
9116 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
9117 | (compare:CC | |
9118 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9119 | [(match_operand 2 "cc_reg_operand" "y") | |
9120 | (const_int 0)]) | |
9121 | (match_operand:SI 3 "const_int_operand" "n")) | |
9122 | (const_int 0))) | |
cd2b37d9 | 9123 | (set (match_operand:SI 4 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9124 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
9125 | (match_dup 3)))] | |
9126 | "" | |
9127 | "* | |
9128 | { | |
9129 | int is_bit = ccr_bit (operands[1], 1); | |
9130 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
9131 | int count; | |
9132 | ||
9133 | if (is_bit >= put_bit) | |
9134 | count = is_bit - put_bit; | |
9135 | else | |
9136 | count = 32 - (put_bit - is_bit); | |
9137 | ||
89e9f3a8 MM |
9138 | operands[5] = GEN_INT (count); |
9139 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 9140 | |
ca7f5001 | 9141 | return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 9142 | }" |
b19003d8 RK |
9143 | [(set_attr "type" "delayed_compare") |
9144 | (set_attr "length" "12")]) | |
1fd4e8c1 | 9145 | |
c5defebb RK |
9146 | ;; If we are comparing the result of two comparisons, this can be done |
9147 | ;; using creqv or crxor. | |
9148 | ||
9149 | (define_insn "" | |
9150 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
9151 | (compare:CCEQ (match_operator 1 "scc_comparison_operator" | |
9152 | [(match_operand 2 "cc_reg_operand" "y") | |
9153 | (const_int 0)]) | |
9154 | (match_operator 3 "scc_comparison_operator" | |
9155 | [(match_operand 4 "cc_reg_operand" "y") | |
9156 | (const_int 0)])))] | |
9157 | "REGNO (operands[2]) != REGNO (operands[4])" | |
9158 | "* | |
9159 | { | |
9160 | enum rtx_code code1, code2; | |
9161 | ||
9162 | code1 = GET_CODE (operands[1]); | |
9163 | code2 = GET_CODE (operands[3]); | |
9164 | ||
9165 | if ((code1 == EQ || code1 == LT || code1 == GT | |
9166 | || code1 == LTU || code1 == GTU | |
9167 | || (code1 != NE && GET_MODE (operands[2]) == CCFPmode)) | |
9168 | != | |
9169 | (code2 == EQ || code2 == LT || code2 == GT | |
9170 | || code2 == LTU || code2 == GTU | |
9171 | || (code2 != NE && GET_MODE (operands[4]) == CCFPmode))) | |
9172 | return \"%C1%C3crxor %E0,%j1,%j3\"; | |
9173 | else | |
9174 | return \"%C1%C3creqv %E0,%j1,%j3\"; | |
b19003d8 RK |
9175 | }" |
9176 | [(set_attr "length" "12")]) | |
c5defebb RK |
9177 | |
9178 | ;; There is a 3 cycle delay between consecutive mfcr instructions | |
9179 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
9180 | ||
9181 | (define_peephole | |
cd2b37d9 | 9182 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
9183 | (match_operator:SI 1 "scc_comparison_operator" |
9184 | [(match_operand 2 "cc_reg_operand" "y") | |
9185 | (const_int 0)])) | |
cd2b37d9 | 9186 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
9187 | (match_operator:SI 4 "scc_comparison_operator" |
9188 | [(match_operand 5 "cc_reg_operand" "y") | |
9189 | (const_int 0)]))] | |
9190 | "REGNO (operands[2]) != REGNO (operands[5])" | |
ca7f5001 | 9191 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b19003d8 | 9192 | [(set_attr "length" "20")]) |
c5defebb | 9193 | |
1fd4e8c1 RK |
9194 | ;; There are some scc insns that can be done directly, without a compare. |
9195 | ;; These are faster because they don't involve the communications between | |
9196 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
9197 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
9198 | ;; | |
9199 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
9200 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
9201 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
9202 | ;; cases where it is no more expensive than (neg (scc ..)). | |
9203 | ||
9204 | ;; Have reload force a constant into a register for the simple insns that | |
9205 | ;; otherwise won't accept constants. We do this because it is faster than | |
9206 | ;; the cmp/mfcr sequence we would otherwise generate. | |
9207 | ||
9208 | (define_insn "" | |
cd2b37d9 RK |
9209 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
9210 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 9211 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 RK |
9212 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
9213 | "" | |
9214 | "@ | |
ca7f5001 | 9215 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 9216 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
9217 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
9218 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
9219 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 9220 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 9221 | |
a260abc9 DE |
9222 | (define_insn "" |
9223 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
9224 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
9225 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
9226 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
9227 | "TARGET_POWERPC64" | |
9228 | "@ | |
9229 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
9230 | subfic %3,%1,0\;adde %0,%3,%1 | |
9231 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
9232 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
9233 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
9234 | [(set_attr "length" "12,8,12,12,12")]) | |
9235 | ||
1fd4e8c1 | 9236 | (define_insn "" |
29ae5b89 | 9237 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") |
7e69e155 | 9238 | (compare:CC |
29ae5b89 | 9239 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 9240 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
1fd4e8c1 | 9241 | (const_int 0))) |
29ae5b89 | 9242 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
1fd4e8c1 | 9243 | (eq:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 9244 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
1fd4e8c1 RK |
9245 | "" |
9246 | "@ | |
ca7f5001 RK |
9247 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
9248 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
9249 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9250 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
29ae5b89 | 9251 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0" |
b19003d8 | 9252 | [(set_attr "type" "compare") |
29ae5b89 | 9253 | (set_attr "length" "12,8,12,12,12")]) |
b19003d8 | 9254 | |
a260abc9 | 9255 | (define_insn "" |
29ae5b89 | 9256 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") |
a260abc9 | 9257 | (compare:CC |
29ae5b89 JL |
9258 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") |
9259 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")) | |
a260abc9 | 9260 | (const_int 0))) |
29ae5b89 | 9261 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") |
a260abc9 | 9262 | (eq:DI (match_dup 1) (match_dup 2))) |
29ae5b89 | 9263 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] |
a260abc9 DE |
9264 | "TARGET_POWERPC64" |
9265 | "@ | |
9266 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9267 | subfic %3,%1,0\;adde. %0,%3,%1 | |
9268 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9269 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
29ae5b89 | 9270 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0" |
a260abc9 | 9271 | [(set_attr "type" "compare") |
29ae5b89 | 9272 | (set_attr "length" "12,8,12,12,12")]) |
a260abc9 | 9273 | |
b19003d8 RK |
9274 | ;; We have insns of the form shown by the first define_insn below. If |
9275 | ;; there is something inside the comparison operation, we must split it. | |
9276 | (define_split | |
9277 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
9278 | (plus:SI (match_operator 1 "comparison_operator" | |
9279 | [(match_operand:SI 2 "" "") | |
9280 | (match_operand:SI 3 | |
9281 | "reg_or_cint_operand" "")]) | |
9282 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
9283 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
9284 | "! gpc_reg_operand (operands[2], SImode)" | |
9285 | [(set (match_dup 5) (match_dup 2)) | |
9286 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
9287 | (match_dup 4)))]) | |
1fd4e8c1 RK |
9288 | |
9289 | (define_insn "" | |
cd2b37d9 RK |
9290 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
9291 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 9292 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
cd2b37d9 | 9293 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) |
1fd4e8c1 RK |
9294 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
9295 | "" | |
9296 | "@ | |
ca7f5001 RK |
9297 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
9298 | {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3 | |
9299 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
9300 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
d9d934ef | 9301 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" |
b19003d8 | 9302 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
9303 | |
9304 | (define_insn "" | |
29ae5b89 | 9305 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x") |
7e69e155 | 9306 | (compare:CC |
1fd4e8c1 | 9307 | (plus:SI |
29ae5b89 | 9308 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 9309 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
29ae5b89 | 9310 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) |
1fd4e8c1 | 9311 | (const_int 0))) |
29ae5b89 | 9312 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
1fd4e8c1 RK |
9313 | "" |
9314 | "@ | |
ca7f5001 | 9315 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 9316 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
9317 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9318 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
29ae5b89 | 9319 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" |
b19003d8 | 9320 | [(set_attr "type" "compare") |
29ae5b89 | 9321 | (set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
9322 | |
9323 | (define_insn "" | |
29ae5b89 | 9324 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x") |
7e69e155 | 9325 | (compare:CC |
1fd4e8c1 | 9326 | (plus:SI |
29ae5b89 | 9327 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 9328 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
29ae5b89 | 9329 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) |
1fd4e8c1 | 9330 | (const_int 0))) |
29ae5b89 | 9331 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
1fd4e8c1 | 9332 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9333 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
1fd4e8c1 RK |
9334 | "" |
9335 | "@ | |
ca7f5001 | 9336 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
19378cf8 | 9337 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3 |
ca7f5001 RK |
9338 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
9339 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
29ae5b89 | 9340 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" |
b19003d8 | 9341 | [(set_attr "type" "compare") |
29ae5b89 | 9342 | (set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
9343 | |
9344 | (define_insn "" | |
cd2b37d9 | 9345 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 9346 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 9347 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
1fd4e8c1 RK |
9348 | "" |
9349 | "@ | |
ca7f5001 RK |
9350 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
9351 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
9352 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
9353 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
9354 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 9355 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 9356 | |
ea9be077 MM |
9357 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
9358 | ;; since it nabs/sr is just as fast. | |
463b558b | 9359 | (define_insn "*ne0" |
b4e95693 | 9360 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
9361 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
9362 | (const_int 31))) | |
9363 | (clobber (match_scratch:SI 2 "=&r"))] | |
31bfaa0b | 9364 | "! TARGET_POWER" |
ea9be077 MM |
9365 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
9366 | [(set_attr "length" "8")]) | |
9367 | ||
a260abc9 DE |
9368 | (define_insn "" |
9369 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
9370 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
9371 | (const_int 63))) | |
9372 | (clobber (match_scratch:DI 2 "=&r"))] | |
9373 | "TARGET_POWERPC64" | |
9374 | "addic %2,%1,-1\;subfe %0,%2,%1" | |
9375 | [(set_attr "length" "8")]) | |
9376 | ||
1fd4e8c1 RK |
9377 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
9378 | (define_insn "" | |
cd2b37d9 | 9379 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9380 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 9381 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 9382 | (const_int 31)) |
cd2b37d9 | 9383 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
9384 | (clobber (match_scratch:SI 3 "=&r"))] |
9385 | "" | |
ca7f5001 | 9386 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 9387 | [(set_attr "length" "8")]) |
1fd4e8c1 | 9388 | |
a260abc9 DE |
9389 | (define_insn "" |
9390 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
9391 | (plus:DI (lshiftrt:DI | |
9392 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
9393 | (const_int 63)) | |
9394 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
9395 | (clobber (match_scratch:DI 3 "=&r"))] | |
9396 | "TARGET_POWERPC64" | |
9397 | "addic %3,%1,-1\;addze %0,%2" | |
9398 | [(set_attr "length" "8")]) | |
9399 | ||
1fd4e8c1 | 9400 | (define_insn "" |
29ae5b89 | 9401 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9402 | (compare:CC |
9403 | (plus:SI (lshiftrt:SI | |
29ae5b89 | 9404 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 9405 | (const_int 31)) |
29ae5b89 | 9406 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9407 | (const_int 0))) |
29ae5b89 | 9408 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 9409 | "" |
29ae5b89 | 9410 | "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2" |
b19003d8 | 9411 | [(set_attr "type" "compare") |
29ae5b89 | 9412 | (set_attr "length" "8")]) |
1fd4e8c1 | 9413 | |
a260abc9 | 9414 | (define_insn "" |
29ae5b89 | 9415 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
a260abc9 DE |
9416 | (compare:CC |
9417 | (plus:DI (lshiftrt:DI | |
29ae5b89 | 9418 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) |
a260abc9 | 9419 | (const_int 63)) |
29ae5b89 | 9420 | (match_operand:DI 2 "gpc_reg_operand" "r")) |
a260abc9 | 9421 | (const_int 0))) |
29ae5b89 | 9422 | (clobber (match_scratch:DI 3 "=&r"))] |
a260abc9 | 9423 | "TARGET_POWERPC64" |
29ae5b89 | 9424 | "addic %3,%1,-1\;addze. %3,%2" |
a260abc9 | 9425 | [(set_attr "type" "compare") |
29ae5b89 | 9426 | (set_attr "length" "8")]) |
a260abc9 | 9427 | |
1fd4e8c1 | 9428 | (define_insn "" |
29ae5b89 | 9429 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9430 | (compare:CC |
9431 | (plus:SI (lshiftrt:SI | |
29ae5b89 | 9432 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 9433 | (const_int 31)) |
29ae5b89 | 9434 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9435 | (const_int 0))) |
29ae5b89 | 9436 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9437 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
9438 | (match_dup 2))) | |
29ae5b89 | 9439 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 9440 | "" |
29ae5b89 | 9441 | "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2" |
b19003d8 | 9442 | [(set_attr "type" "compare") |
29ae5b89 | 9443 | (set_attr "length" "8")]) |
1fd4e8c1 | 9444 | |
a260abc9 | 9445 | (define_insn "" |
29ae5b89 | 9446 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
a260abc9 DE |
9447 | (compare:CC |
9448 | (plus:DI (lshiftrt:DI | |
29ae5b89 | 9449 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) |
a260abc9 | 9450 | (const_int 63)) |
29ae5b89 | 9451 | (match_operand:DI 2 "gpc_reg_operand" "r")) |
a260abc9 | 9452 | (const_int 0))) |
29ae5b89 | 9453 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9454 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
9455 | (match_dup 2))) | |
29ae5b89 | 9456 | (clobber (match_scratch:DI 3 "=&r"))] |
a260abc9 | 9457 | "TARGET_POWERPC64" |
29ae5b89 | 9458 | "addic %3,%1,-1\;addze. %0,%2" |
a260abc9 | 9459 | [(set_attr "type" "compare") |
29ae5b89 | 9460 | (set_attr "length" "8")]) |
a260abc9 | 9461 | |
1fd4e8c1 | 9462 | (define_insn "" |
cd2b37d9 RK |
9463 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9464 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
9465 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
9466 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 9467 | "TARGET_POWER" |
1fd4e8c1 | 9468 | "@ |
ca7f5001 | 9469 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 9470 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 9471 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9472 | |
9473 | (define_insn "" | |
29ae5b89 | 9474 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9475 | (compare:CC |
29ae5b89 JL |
9476 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9477 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) | |
1fd4e8c1 | 9478 | (const_int 0))) |
29ae5b89 | 9479 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9480 | (le:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 9481 | (clobber (match_scratch:SI 3 "=r,X"))] |
ca7f5001 | 9482 | "TARGET_POWER" |
1fd4e8c1 | 9483 | "@ |
ca7f5001 | 9484 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
29ae5b89 JL |
9485 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31" |
9486 | [(set_attr "type" "compare,delayed_compare") | |
9487 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
9488 | |
9489 | (define_insn "" | |
cd2b37d9 RK |
9490 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9491 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 9492 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
cd2b37d9 | 9493 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 9494 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 9495 | "TARGET_POWER" |
1fd4e8c1 | 9496 | "@ |
ca7f5001 RK |
9497 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
9498 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" | |
b19003d8 | 9499 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9500 | |
9501 | (define_insn "" | |
29ae5b89 | 9502 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9503 | (compare:CC |
29ae5b89 JL |
9504 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9505 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) | |
9506 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9507 | (const_int 0))) |
29ae5b89 | 9508 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 9509 | "TARGET_POWER" |
1fd4e8c1 | 9510 | "@ |
ca7f5001 | 9511 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
29ae5b89 | 9512 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3" |
b19003d8 | 9513 | [(set_attr "type" "compare") |
29ae5b89 | 9514 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9515 | |
9516 | (define_insn "" | |
29ae5b89 | 9517 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9518 | (compare:CC |
29ae5b89 JL |
9519 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9520 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) | |
9521 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9522 | (const_int 0))) |
29ae5b89 | 9523 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9524 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9525 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 9526 | "TARGET_POWER" |
1fd4e8c1 | 9527 | "@ |
ca7f5001 | 9528 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
29ae5b89 | 9529 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3" |
b19003d8 | 9530 | [(set_attr "type" "compare") |
29ae5b89 | 9531 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9532 | |
9533 | (define_insn "" | |
cd2b37d9 RK |
9534 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9535 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 9536 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 9537 | "TARGET_POWER" |
1fd4e8c1 | 9538 | "@ |
ca7f5001 RK |
9539 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
9540 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 9541 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9542 | |
9543 | (define_insn "" | |
cd2b37d9 RK |
9544 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9545 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
9546 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
9547 | "" | |
ca7f5001 | 9548 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 9549 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9550 | |
9551 | (define_insn "" | |
29ae5b89 | 9552 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 | 9553 | (compare:CC |
29ae5b89 JL |
9554 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9555 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 | 9556 | (const_int 0))) |
29ae5b89 | 9557 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9558 | (leu:SI (match_dup 1) (match_dup 2)))] |
9559 | "" | |
29ae5b89 | 9560 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" |
b19003d8 | 9561 | [(set_attr "type" "compare") |
29ae5b89 | 9562 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9563 | |
9564 | (define_insn "" | |
cd2b37d9 RK |
9565 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9566 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9567 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 9568 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
9569 | (clobber (match_scratch:SI 4 "=&r"))] |
9570 | "" | |
ca7f5001 | 9571 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 9572 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
9573 | |
9574 | (define_insn "" | |
29ae5b89 | 9575 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 9576 | (compare:CC |
29ae5b89 JL |
9577 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9578 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9579 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9580 | (const_int 0))) |
29ae5b89 | 9581 | (clobber (match_scratch:SI 4 "=&r"))] |
1fd4e8c1 | 9582 | "" |
29ae5b89 | 9583 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3" |
b19003d8 | 9584 | [(set_attr "type" "compare") |
29ae5b89 | 9585 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9586 | |
9587 | (define_insn "" | |
29ae5b89 | 9588 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") |
1fd4e8c1 | 9589 | (compare:CC |
29ae5b89 JL |
9590 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9591 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9592 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9593 | (const_int 0))) |
29ae5b89 | 9594 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9595 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9596 | (clobber (match_scratch:SI 4 "=&r"))] |
1fd4e8c1 | 9597 | "" |
29ae5b89 | 9598 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3" |
b19003d8 | 9599 | [(set_attr "type" "compare") |
29ae5b89 | 9600 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9601 | |
9602 | (define_insn "" | |
cd2b37d9 RK |
9603 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9604 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
9605 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
9606 | "" | |
ca7f5001 | 9607 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 9608 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9609 | |
9610 | (define_insn "" | |
cd2b37d9 | 9611 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9612 | (and:SI (neg:SI |
cd2b37d9 | 9613 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 9614 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
cd2b37d9 | 9615 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
9616 | (clobber (match_scratch:SI 4 "=&r"))] |
9617 | "" | |
ca7f5001 | 9618 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" |
b19003d8 | 9619 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9620 | |
9621 | (define_insn "" | |
29ae5b89 | 9622 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9623 | (compare:CC |
9624 | (and:SI (neg:SI | |
29ae5b89 JL |
9625 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9626 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) | |
9627 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9628 | (const_int 0))) |
29ae5b89 | 9629 | (clobber (match_scratch:SI 4 "=&r"))] |
1fd4e8c1 | 9630 | "" |
29ae5b89 | 9631 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" |
b19003d8 | 9632 | [(set_attr "type" "compare") |
29ae5b89 | 9633 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9634 | |
9635 | (define_insn "" | |
29ae5b89 | 9636 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9637 | (compare:CC |
9638 | (and:SI (neg:SI | |
29ae5b89 JL |
9639 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9640 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) | |
9641 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9642 | (const_int 0))) |
29ae5b89 | 9643 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9644 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
29ae5b89 | 9645 | (clobber (match_scratch:SI 4 "=&r"))] |
1fd4e8c1 | 9646 | "" |
29ae5b89 | 9647 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" |
b19003d8 | 9648 | [(set_attr "type" "compare") |
29ae5b89 | 9649 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9650 | |
9651 | (define_insn "" | |
cd2b37d9 RK |
9652 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9653 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9654 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 9655 | "TARGET_POWER" |
7f340546 | 9656 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 9657 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9658 | |
9659 | (define_insn "" | |
29ae5b89 | 9660 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 | 9661 | (compare:CC |
29ae5b89 JL |
9662 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9663 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 | 9664 | (const_int 0))) |
29ae5b89 | 9665 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9666 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 9667 | "TARGET_POWER" |
29ae5b89 JL |
9668 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" |
9669 | [(set_attr "type" "delayed_compare") | |
9670 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
9671 | |
9672 | (define_insn "" | |
cd2b37d9 RK |
9673 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9674 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9675 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 9676 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 9677 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
9678 | "TARGET_POWER" |
9679 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 9680 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9681 | |
9682 | (define_insn "" | |
29ae5b89 | 9683 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 9684 | (compare:CC |
29ae5b89 JL |
9685 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9686 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9687 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9688 | (const_int 0))) |
29ae5b89 | 9689 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9690 | "TARGET_POWER" |
29ae5b89 | 9691 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" |
b19003d8 | 9692 | [(set_attr "type" "compare") |
29ae5b89 | 9693 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9694 | |
9695 | (define_insn "" | |
29ae5b89 | 9696 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") |
1fd4e8c1 | 9697 | (compare:CC |
29ae5b89 JL |
9698 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9699 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9700 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9701 | (const_int 0))) |
29ae5b89 | 9702 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9703 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9704 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9705 | "TARGET_POWER" |
29ae5b89 | 9706 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" |
b19003d8 | 9707 | [(set_attr "type" "compare") |
29ae5b89 | 9708 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9709 | |
9710 | (define_insn "" | |
cd2b37d9 RK |
9711 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9712 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9713 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
9714 | "TARGET_POWER" |
9715 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 9716 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9717 | |
9718 | (define_insn "" | |
cd2b37d9 RK |
9719 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9720 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
9721 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
9722 | "" | |
9723 | "@ | |
ca7f5001 RK |
9724 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
9725 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 9726 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9727 | |
9728 | (define_insn "" | |
29ae5b89 | 9729 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9730 | (compare:CC |
29ae5b89 JL |
9731 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9732 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
1fd4e8c1 | 9733 | (const_int 0))) |
29ae5b89 | 9734 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
9735 | (ltu:SI (match_dup 1) (match_dup 2)))] |
9736 | "" | |
9737 | "@ | |
ca7f5001 | 9738 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
29ae5b89 | 9739 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" |
b19003d8 | 9740 | [(set_attr "type" "compare") |
29ae5b89 | 9741 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9742 | |
9743 | (define_insn "" | |
19378cf8 MM |
9744 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9745 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
9746 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
9747 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI"))) | |
9748 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
1fd4e8c1 RK |
9749 | "" |
9750 | "@ | |
ca7f5001 | 9751 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 |
04be6346 | 9752 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
b19003d8 | 9753 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9754 | |
9755 | (define_insn "" | |
29ae5b89 | 9756 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9757 | (compare:CC |
29ae5b89 JL |
9758 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9759 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
9760 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9761 | (const_int 0))) |
29ae5b89 | 9762 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9763 | "" |
9764 | "@ | |
ca7f5001 | 9765 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
29ae5b89 | 9766 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3" |
b19003d8 | 9767 | [(set_attr "type" "compare") |
29ae5b89 | 9768 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9769 | |
9770 | (define_insn "" | |
29ae5b89 | 9771 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9772 | (compare:CC |
29ae5b89 JL |
9773 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9774 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
9775 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9776 | (const_int 0))) |
29ae5b89 | 9777 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9778 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9779 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9780 | "" |
9781 | "@ | |
ca7f5001 | 9782 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
29ae5b89 | 9783 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" |
b19003d8 | 9784 | [(set_attr "type" "compare") |
29ae5b89 | 9785 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9786 | |
9787 | (define_insn "" | |
cd2b37d9 RK |
9788 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9789 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
9790 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
9791 | "" | |
9792 | "@ | |
ca7f5001 RK |
9793 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
9794 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 9795 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
9796 | |
9797 | (define_insn "" | |
cd2b37d9 RK |
9798 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9799 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
9800 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
9801 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
9802 | "TARGET_POWER" |
9803 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 9804 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9805 | |
9806 | (define_insn "" | |
29ae5b89 | 9807 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 9808 | (compare:CC |
29ae5b89 JL |
9809 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9810 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 | 9811 | (const_int 0))) |
29ae5b89 | 9812 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9813 | (ge:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 9814 | (clobber (match_scratch:SI 3 "=r"))] |
ca7f5001 | 9815 | "TARGET_POWER" |
29ae5b89 | 9816 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3" |
b19003d8 | 9817 | [(set_attr "type" "compare") |
29ae5b89 | 9818 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9819 | |
9820 | (define_insn "" | |
cd2b37d9 RK |
9821 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9822 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9823 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 9824 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 9825 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
9826 | "TARGET_POWER" |
9827 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" | |
b19003d8 | 9828 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9829 | |
9830 | (define_insn "" | |
29ae5b89 | 9831 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 9832 | (compare:CC |
29ae5b89 JL |
9833 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9834 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9835 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9836 | (const_int 0))) |
29ae5b89 | 9837 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9838 | "TARGET_POWER" |
29ae5b89 | 9839 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" |
b19003d8 | 9840 | [(set_attr "type" "compare") |
29ae5b89 | 9841 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9842 | |
9843 | (define_insn "" | |
29ae5b89 | 9844 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") |
1fd4e8c1 | 9845 | (compare:CC |
29ae5b89 JL |
9846 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9847 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9848 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9849 | (const_int 0))) |
29ae5b89 | 9850 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9851 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9852 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9853 | "TARGET_POWER" |
29ae5b89 | 9854 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" |
b19003d8 | 9855 | [(set_attr "type" "compare") |
29ae5b89 | 9856 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9857 | |
9858 | (define_insn "" | |
cd2b37d9 RK |
9859 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9860 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9861 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
9862 | "TARGET_POWER" |
9863 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 9864 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9865 | |
9866 | ;; This is (and (neg (ge X (const_int 0))) Y). | |
9867 | (define_insn "" | |
cd2b37d9 | 9868 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9869 | (and:SI (neg:SI |
9870 | (lshiftrt:SI | |
cd2b37d9 | 9871 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9872 | (const_int 31))) |
cd2b37d9 | 9873 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
9874 | (clobber (match_scratch:SI 3 "=&r"))] |
9875 | "" | |
ca7f5001 | 9876 | "{srai|srawi} %3,%1,31\;andc %0,%2,%3" |
b19003d8 | 9877 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
9878 | |
9879 | (define_insn "" | |
29ae5b89 | 9880 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9881 | (compare:CC |
9882 | (and:SI (neg:SI | |
9883 | (lshiftrt:SI | |
29ae5b89 | 9884 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9885 | (const_int 31))) |
29ae5b89 | 9886 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9887 | (const_int 0))) |
29ae5b89 | 9888 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 9889 | "" |
29ae5b89 | 9890 | "{srai|srawi} %3,%1,31\;andc. %3,%2,%3" |
b19003d8 | 9891 | [(set_attr "type" "compare") |
29ae5b89 | 9892 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9893 | |
9894 | (define_insn "" | |
29ae5b89 | 9895 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9896 | (compare:CC |
9897 | (and:SI (neg:SI | |
9898 | (lshiftrt:SI | |
29ae5b89 | 9899 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9900 | (const_int 31))) |
29ae5b89 | 9901 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9902 | (const_int 0))) |
29ae5b89 | 9903 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9904 | (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) |
9905 | (const_int 31))) | |
9906 | (match_dup 2))) | |
29ae5b89 | 9907 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 9908 | "" |
29ae5b89 | 9909 | "{srai|srawi} %3,%1,31\;andc. %0,%2,%3" |
b19003d8 | 9910 | [(set_attr "type" "compare") |
29ae5b89 | 9911 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9912 | |
9913 | (define_insn "" | |
cd2b37d9 RK |
9914 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9915 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
9916 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
9917 | "" | |
9918 | "@ | |
ca7f5001 RK |
9919 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
9920 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 9921 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9922 | |
9923 | (define_insn "" | |
29ae5b89 | 9924 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9925 | (compare:CC |
29ae5b89 JL |
9926 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9927 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
1fd4e8c1 | 9928 | (const_int 0))) |
29ae5b89 | 9929 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
9930 | (geu:SI (match_dup 1) (match_dup 2)))] |
9931 | "" | |
9932 | "@ | |
ca7f5001 | 9933 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
29ae5b89 | 9934 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" |
b19003d8 | 9935 | [(set_attr "type" "compare") |
29ae5b89 | 9936 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9937 | |
9938 | (define_insn "" | |
cd2b37d9 RK |
9939 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9940 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 9941 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
cd2b37d9 | 9942 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 RK |
9943 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
9944 | "" | |
9945 | "@ | |
ca7f5001 RK |
9946 | {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3 |
9947 | {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 9948 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
9949 | |
9950 | (define_insn "" | |
29ae5b89 | 9951 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9952 | (compare:CC |
29ae5b89 JL |
9953 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9954 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
9955 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9956 | (const_int 0))) |
29ae5b89 | 9957 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9958 | "" |
9959 | "@ | |
ca7f5001 | 9960 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
29ae5b89 | 9961 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3" |
b19003d8 | 9962 | [(set_attr "type" "compare") |
29ae5b89 | 9963 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9964 | |
9965 | (define_insn "" | |
29ae5b89 | 9966 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9967 | (compare:CC |
29ae5b89 JL |
9968 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9969 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
9970 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9971 | (const_int 0))) |
29ae5b89 | 9972 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9973 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9974 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9975 | "" |
9976 | "@ | |
ca7f5001 | 9977 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 |
19378cf8 | 9978 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3" |
b19003d8 | 9979 | [(set_attr "type" "compare") |
29ae5b89 | 9980 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9981 | |
9982 | (define_insn "" | |
cd2b37d9 RK |
9983 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9984 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
9985 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
9986 | "" | |
9987 | "@ | |
ca7f5001 | 9988 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 9989 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 9990 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9991 | |
9992 | (define_insn "" | |
cd2b37d9 | 9993 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9994 | (and:SI (neg:SI |
cd2b37d9 | 9995 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 9996 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
cd2b37d9 | 9997 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 RK |
9998 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
9999 | "" | |
10000 | "@ | |
ca7f5001 RK |
10001 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 |
10002 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" | |
b19003d8 | 10003 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10004 | |
10005 | (define_insn "" | |
29ae5b89 | 10006 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 RK |
10007 | (compare:CC |
10008 | (and:SI (neg:SI | |
29ae5b89 JL |
10009 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10010 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) | |
10011 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 10012 | (const_int 0))) |
29ae5b89 | 10013 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
10014 | "" |
10015 | "@ | |
ca7f5001 | 10016 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
29ae5b89 | 10017 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" |
b19003d8 | 10018 | [(set_attr "type" "compare") |
29ae5b89 | 10019 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
10020 | |
10021 | (define_insn "" | |
29ae5b89 | 10022 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 RK |
10023 | (compare:CC |
10024 | (and:SI (neg:SI | |
29ae5b89 JL |
10025 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10026 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) | |
10027 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 10028 | (const_int 0))) |
29ae5b89 | 10029 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10030 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
29ae5b89 | 10031 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
10032 | "" |
10033 | "@ | |
ca7f5001 | 10034 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
29ae5b89 | 10035 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" |
b19003d8 | 10036 | [(set_attr "type" "compare") |
29ae5b89 | 10037 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
10038 | |
10039 | (define_insn "" | |
cd2b37d9 RK |
10040 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10041 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
10042 | (const_int 0)))] |
10043 | "" | |
ca7f5001 | 10044 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 10045 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10046 | |
10047 | (define_insn "" | |
29ae5b89 | 10048 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
1fd4e8c1 | 10049 | (compare:CC |
29ae5b89 | 10050 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
10051 | (const_int 0)) |
10052 | (const_int 0))) | |
29ae5b89 | 10053 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10054 | (gt:SI (match_dup 1) (const_int 0)))] |
10055 | "" | |
29ae5b89 JL |
10056 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31" |
10057 | [(set_attr "type" "delayed_compare") | |
10058 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
10059 | |
10060 | (define_insn "" | |
cd2b37d9 RK |
10061 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10062 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10063 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
10064 | "TARGET_POWER" |
10065 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 10066 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10067 | |
10068 | (define_insn "" | |
29ae5b89 | 10069 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 | 10070 | (compare:CC |
29ae5b89 JL |
10071 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
10072 | (match_operand:SI 2 "reg_or_short_operand" "r")) | |
1fd4e8c1 | 10073 | (const_int 0))) |
29ae5b89 | 10074 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 10075 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 10076 | "TARGET_POWER" |
29ae5b89 JL |
10077 | "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" |
10078 | [(set_attr "type" "delayed_compare") | |
10079 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
10080 | |
10081 | (define_insn "" | |
cd2b37d9 RK |
10082 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10083 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10084 | (const_int 0)) |
cd2b37d9 | 10085 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
10086 | (clobber (match_scratch:SI 3 "=&r"))] |
10087 | "" | |
ca7f5001 | 10088 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2" |
b19003d8 | 10089 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10090 | |
10091 | (define_insn "" | |
29ae5b89 | 10092 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 10093 | (compare:CC |
29ae5b89 | 10094 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10095 | (const_int 0)) |
29ae5b89 | 10096 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 10097 | (const_int 0))) |
29ae5b89 | 10098 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 10099 | "" |
19378cf8 | 10100 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2" |
b19003d8 | 10101 | [(set_attr "type" "compare") |
29ae5b89 | 10102 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
10103 | |
10104 | (define_insn "" | |
29ae5b89 | 10105 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 10106 | (compare:CC |
29ae5b89 | 10107 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10108 | (const_int 0)) |
29ae5b89 | 10109 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 10110 | (const_int 0))) |
29ae5b89 | 10111 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 10112 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
29ae5b89 | 10113 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 10114 | "" |
19378cf8 | 10115 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2" |
b19003d8 | 10116 | [(set_attr "type" "compare") |
29ae5b89 | 10117 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
10118 | |
10119 | (define_insn "" | |
cd2b37d9 RK |
10120 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10121 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10122 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
cd2b37d9 | 10123 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 10124 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
10125 | "TARGET_POWER" |
10126 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 10127 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10128 | |
10129 | (define_insn "" | |
29ae5b89 | 10130 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 10131 | (compare:CC |
29ae5b89 JL |
10132 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
10133 | (match_operand:SI 2 "reg_or_short_operand" "r")) | |
10134 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 10135 | (const_int 0))) |
29ae5b89 | 10136 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 10137 | "TARGET_POWER" |
29ae5b89 | 10138 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" |
b19003d8 | 10139 | [(set_attr "type" "compare") |
29ae5b89 | 10140 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
10141 | |
10142 | (define_insn "" | |
29ae5b89 | 10143 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") |
1fd4e8c1 | 10144 | (compare:CC |
29ae5b89 JL |
10145 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
10146 | (match_operand:SI 2 "reg_or_short_operand" "r")) | |
10147 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 10148 | (const_int 0))) |
29ae5b89 | 10149 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 10150 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 10151 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 10152 | "TARGET_POWER" |
29ae5b89 | 10153 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" |
b19003d8 | 10154 | [(set_attr "type" "compare") |
29ae5b89 | 10155 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
10156 | |
10157 | (define_insn "" | |
cd2b37d9 RK |
10158 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10159 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
10160 | (const_int 0))))] |
10161 | "" | |
ca7f5001 | 10162 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 10163 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10164 | |
10165 | (define_insn "" | |
cd2b37d9 RK |
10166 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10167 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 10168 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
10169 | "TARGET_POWER" |
10170 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 10171 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10172 | |
10173 | (define_insn "" | |
cd2b37d9 RK |
10174 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10175 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
10176 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
10177 | "" | |
ca7f5001 | 10178 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 10179 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10180 | |
10181 | (define_insn "" | |
29ae5b89 | 10182 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 | 10183 | (compare:CC |
29ae5b89 JL |
10184 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
10185 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 | 10186 | (const_int 0))) |
29ae5b89 | 10187 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10188 | (gtu:SI (match_dup 1) (match_dup 2)))] |
10189 | "" | |
29ae5b89 | 10190 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" |
b19003d8 | 10191 | [(set_attr "type" "compare") |
29ae5b89 | 10192 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
10193 | |
10194 | (define_insn "" | |
19378cf8 MM |
10195 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
10196 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
10197 | (match_operand:SI 2 "reg_or_short_operand" "I,rI")) | |
10198 | (match_operand:SI 3 "reg_or_short_operand" "r,rI"))) | |
10199 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
1fd4e8c1 | 10200 | "" |
00751805 | 10201 | "@ |
ca7f5001 | 10202 | {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3 |
ca7f5001 | 10203 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
19378cf8 | 10204 | [(set_attr "length" "8,12")]) |
1fd4e8c1 RK |
10205 | |
10206 | (define_insn "" | |
29ae5b89 | 10207 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 10208 | (compare:CC |
29ae5b89 JL |
10209 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10210 | (match_operand:SI 2 "reg_or_short_operand" "I,r")) | |
10211 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 10212 | (const_int 0))) |
29ae5b89 | 10213 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 | 10214 | "" |
00751805 | 10215 | "@ |
19378cf8 MM |
10216 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
10217 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3" | |
b19003d8 | 10218 | [(set_attr "type" "compare") |
29ae5b89 | 10219 | (set_attr "length" "8,12")]) |
1fd4e8c1 RK |
10220 | |
10221 | (define_insn "" | |
29ae5b89 | 10222 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 10223 | (compare:CC |
29ae5b89 JL |
10224 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
10225 | (match_operand:SI 2 "reg_or_short_operand" "I,r")) | |
10226 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 10227 | (const_int 0))) |
29ae5b89 | 10228 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10229 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 10230 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 | 10231 | "" |
00751805 | 10232 | "@ |
ca7f5001 | 10233 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 |
29ae5b89 | 10234 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" |
b19003d8 | 10235 | [(set_attr "type" "compare") |
29ae5b89 | 10236 | (set_attr "length" "8,12")]) |
1fd4e8c1 RK |
10237 | |
10238 | (define_insn "" | |
cd2b37d9 RK |
10239 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10240 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
10241 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
10242 | "" | |
ca7f5001 | 10243 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 10244 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
10245 | \f |
10246 | ;; Define both directions of branch and return. If we need a reload | |
10247 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
10248 | ;; register CC value to there. | |
10249 | ||
10250 | (define_insn "" | |
10251 | [(set (pc) | |
10252 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
10253 | [(match_operand 2 | |
10254 | "cc_reg_operand" "x,?y") | |
10255 | (const_int 0)]) | |
10256 | (label_ref (match_operand 0 "" "")) | |
10257 | (pc)))] | |
10258 | "" | |
b19003d8 RK |
10259 | "* |
10260 | { | |
10261 | if (get_attr_length (insn) == 8) | |
10262 | return \"%C1bc %t1,%j1,%l0\"; | |
10263 | else | |
c81bebd7 MM |
10264 | return \"%C1bc %T1,%j1,%$+8\;b %l0\"; |
10265 | ||
b19003d8 RK |
10266 | }" |
10267 | [(set_attr "type" "branch")]) | |
10268 | ||
1fd4e8c1 RK |
10269 | (define_insn "" |
10270 | [(set (pc) | |
10271 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
10272 | [(match_operand 1 | |
10273 | "cc_reg_operand" "x,?y") | |
10274 | (const_int 0)]) | |
10275 | (return) | |
10276 | (pc)))] | |
10277 | "direct_return ()" | |
ca7f5001 | 10278 | "{%C0bcr|%C0bclr} %t0,%j0" |
b7ff3d82 DE |
10279 | [(set_attr "type" "branch") |
10280 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
10281 | |
10282 | (define_insn "" | |
10283 | [(set (pc) | |
10284 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
10285 | [(match_operand 2 | |
10286 | "cc_reg_operand" "x,?y") | |
10287 | (const_int 0)]) | |
10288 | (pc) | |
10289 | (label_ref (match_operand 0 "" ""))))] | |
10290 | "" | |
b19003d8 RK |
10291 | "* |
10292 | { | |
10293 | if (get_attr_length (insn) == 8) | |
10294 | return \"%C1bc %T1,%j1,%l0\"; | |
10295 | else | |
c81bebd7 | 10296 | return \"%C1bc %t1,%j1,%$+8\;b %l0\"; |
b19003d8 RK |
10297 | }" |
10298 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
10299 | |
10300 | (define_insn "" | |
10301 | [(set (pc) | |
10302 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
10303 | [(match_operand 1 | |
10304 | "cc_reg_operand" "x,?y") | |
10305 | (const_int 0)]) | |
10306 | (pc) | |
10307 | (return)))] | |
10308 | "direct_return ()" | |
ca7f5001 | 10309 | "{%C0bcr|%C0bclr} %T0,%j0" |
b7ff3d82 DE |
10310 | [(set_attr "type" "branch") |
10311 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
10312 | |
10313 | ;; Unconditional branch and return. | |
10314 | ||
10315 | (define_insn "jump" | |
10316 | [(set (pc) | |
10317 | (label_ref (match_operand 0 "" "")))] | |
10318 | "" | |
b7ff3d82 DE |
10319 | "b %l0" |
10320 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
10321 | |
10322 | (define_insn "return" | |
10323 | [(return)] | |
10324 | "direct_return ()" | |
324e52cc TG |
10325 | "{br|blr}" |
10326 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 10327 | |
0ad91047 DE |
10328 | (define_expand "indirect_jump" |
10329 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 10330 | "" |
0ad91047 DE |
10331 | " |
10332 | { | |
10333 | if (TARGET_32BIT) | |
10334 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
10335 | else | |
10336 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
10337 | DONE; | |
10338 | }") | |
10339 | ||
10340 | (define_insn "indirect_jumpsi" | |
10341 | [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))] | |
10342 | "TARGET_32BIT" | |
1fd4e8c1 RK |
10343 | "@ |
10344 | bctr | |
324e52cc TG |
10345 | {br|blr}" |
10346 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 10347 | |
0ad91047 | 10348 | (define_insn "indirect_jumpdi" |
266eb58a | 10349 | [(set (pc) (match_operand:DI 0 "register_operand" "c,l"))] |
0ad91047 | 10350 | "TARGET_64BIT" |
266eb58a DE |
10351 | "@ |
10352 | bctr | |
10353 | {br|blr}" | |
10354 | [(set_attr "type" "jmpreg")]) | |
10355 | ||
1fd4e8c1 RK |
10356 | ;; Table jump for switch statements: |
10357 | (define_expand "tablejump" | |
e6ca2c17 DE |
10358 | [(use (match_operand 0 "" "")) |
10359 | (use (label_ref (match_operand 1 "" "")))] | |
10360 | "" | |
10361 | " | |
10362 | { | |
10363 | if (TARGET_32BIT) | |
10364 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
10365 | else | |
10366 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
10367 | DONE; | |
10368 | }") | |
10369 | ||
10370 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
10371 | [(set (match_dup 3) |
10372 | (plus:SI (match_operand:SI 0 "" "") | |
10373 | (match_dup 2))) | |
10374 | (parallel [(set (pc) (match_dup 3)) | |
10375 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 10376 | "TARGET_32BIT" |
1fd4e8c1 RK |
10377 | " |
10378 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 10379 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
10380 | operands[3] = gen_reg_rtx (SImode); |
10381 | }") | |
10382 | ||
e6ca2c17 DE |
10383 | (define_expand "tablejumpdi" |
10384 | [(set (match_dup 3) | |
10385 | (plus:DI (match_operand:DI 0 "" "") | |
10386 | (match_dup 2))) | |
10387 | (parallel [(set (pc) (match_dup 3)) | |
10388 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 10389 | "TARGET_64BIT" |
e6ca2c17 DE |
10390 | " |
10391 | { operands[0] = force_reg (DImode, operands[0]); | |
c5c76735 | 10392 | operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
e6ca2c17 DE |
10393 | operands[3] = gen_reg_rtx (DImode); |
10394 | }") | |
10395 | ||
1fd4e8c1 RK |
10396 | (define_insn "" |
10397 | [(set (pc) | |
740ab4a2 | 10398 | (match_operand:SI 0 "register_operand" "c,l")) |
1fd4e8c1 | 10399 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 10400 | "TARGET_32BIT" |
1fd4e8c1 RK |
10401 | "@ |
10402 | bctr | |
a6845123 RK |
10403 | {br|blr}" |
10404 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 10405 | |
266eb58a DE |
10406 | (define_insn "" |
10407 | [(set (pc) | |
10408 | (match_operand:DI 0 "register_operand" "c,l")) | |
10409 | (use (label_ref (match_operand 1 "" "")))] | |
0ad91047 | 10410 | "TARGET_64BIT" |
266eb58a DE |
10411 | "@ |
10412 | bctr | |
10413 | {br|blr}" | |
10414 | [(set_attr "type" "jmpreg")]) | |
10415 | ||
1fd4e8c1 RK |
10416 | (define_insn "nop" |
10417 | [(const_int 0)] | |
10418 | "" | |
ca7f5001 | 10419 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 10420 | \f |
7e69e155 | 10421 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
10422 | ;; so loop.c knows what to generate. |
10423 | ||
b6c9286a | 10424 | (define_expand "decrement_and_branch_on_count" |
0ad91047 DE |
10425 | [(use (match_operand 0 "register_operand" "")) |
10426 | (use (label_ref (match_operand 1 "" "")))] | |
10427 | "" | |
10428 | " | |
10429 | { | |
10430 | if (TARGET_POWERPC64) | |
10431 | emit_jump_insn (gen_ctrdi (operands[0], operands[1])); | |
10432 | else | |
10433 | emit_jump_insn (gen_ctrsi (operands[0], operands[1])); | |
10434 | DONE; | |
10435 | }") | |
10436 | ||
10437 | (define_expand "ctrsi" | |
3cb999d8 DE |
10438 | [(parallel [(set (pc) |
10439 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
10440 | (const_int 1)) | |
10441 | (label_ref (match_operand 1 "" "")) | |
10442 | (pc))) | |
b6c9286a MM |
10443 | (set (match_dup 0) |
10444 | (plus:SI (match_dup 0) | |
10445 | (const_int -1))) | |
5f81043f RK |
10446 | (clobber (match_scratch:CC 2 "")) |
10447 | (clobber (match_scratch:SI 3 ""))])] | |
0ad91047 DE |
10448 | "! TARGET_POWERPC64" |
10449 | "") | |
10450 | ||
10451 | (define_expand "ctrdi" | |
3cb999d8 DE |
10452 | [(parallel [(set (pc) |
10453 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
10454 | (const_int 1)) | |
10455 | (label_ref (match_operand 1 "" "")) | |
10456 | (pc))) | |
0ad91047 DE |
10457 | (set (match_dup 0) |
10458 | (plus:DI (match_dup 0) | |
10459 | (const_int -1))) | |
10460 | (clobber (match_scratch:CC 2 "")) | |
10461 | (clobber (match_scratch:DI 3 ""))])] | |
10462 | "TARGET_POWERPC64" | |
c225ba7b RK |
10463 | "") |
10464 | ||
1fd4e8c1 RK |
10465 | ;; We need to be able to do this for any operand, including MEM, or we |
10466 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 10467 | ;; JUMP_INSNs. |
0ad91047 | 10468 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
10469 | ;; label MUST be operand 0. |
10470 | ||
0ad91047 | 10471 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 10472 | [(set (pc) |
5f81043f | 10473 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 10474 | (const_int 1)) |
a6845123 | 10475 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 10476 | (pc))) |
5f81043f RK |
10477 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
10478 | (plus:SI (match_dup 1) | |
10479 | (const_int -1))) | |
1fd4e8c1 RK |
10480 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
10481 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 10482 | "! TARGET_POWERPC64" |
b19003d8 RK |
10483 | "* |
10484 | { | |
af87a13e | 10485 | if (which_alternative != 0) |
b19003d8 RK |
10486 | return \"#\"; |
10487 | else if (get_attr_length (insn) == 8) | |
a6845123 | 10488 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 10489 | else |
c81bebd7 | 10490 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 10491 | }" |
baf97f86 RK |
10492 | [(set_attr "type" "branch") |
10493 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 10494 | |
0ad91047 | 10495 | (define_insn "*ctrsi_internal2" |
5f81043f RK |
10496 | [(set (pc) |
10497 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") | |
10498 | (const_int 1)) | |
10499 | (pc) | |
10500 | (label_ref (match_operand 0 "" "")))) | |
10501 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
10502 | (plus:SI (match_dup 1) | |
10503 | (const_int -1))) | |
10504 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
10505 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
10506 | "! TARGET_POWERPC64" |
10507 | "* | |
10508 | { | |
10509 | if (which_alternative != 0) | |
10510 | return \"#\"; | |
10511 | else if (get_attr_length (insn) == 8) | |
10512 | return \"bdz %l0\"; | |
10513 | else | |
10514 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
10515 | }" | |
10516 | [(set_attr "type" "branch") | |
10517 | (set_attr "length" "*,12,16")]) | |
10518 | ||
10519 | (define_insn "*ctrdi_internal1" | |
10520 | [(set (pc) | |
10521 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") | |
10522 | (const_int 1)) | |
10523 | (label_ref (match_operand 0 "" "")) | |
10524 | (pc))) | |
10525 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
10526 | (plus:DI (match_dup 1) | |
10527 | (const_int -1))) | |
10528 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
10529 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
10530 | "TARGET_POWERPC64" | |
10531 | "* | |
10532 | { | |
10533 | if (which_alternative != 0) | |
10534 | return \"#\"; | |
10535 | else if (get_attr_length (insn) == 8) | |
10536 | return \"{bdn|bdnz} %l0\"; | |
10537 | else | |
10538 | return \"bdz %$+8\;b %l0\"; | |
10539 | }" | |
10540 | [(set_attr "type" "branch") | |
10541 | (set_attr "length" "*,12,16")]) | |
10542 | ||
10543 | (define_insn "*ctrdi_internal2" | |
10544 | [(set (pc) | |
10545 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") | |
10546 | (const_int 1)) | |
10547 | (pc) | |
10548 | (label_ref (match_operand 0 "" "")))) | |
10549 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
10550 | (plus:DI (match_dup 1) | |
10551 | (const_int -1))) | |
10552 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
10553 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
10554 | "TARGET_POWERPC64" | |
5f81043f RK |
10555 | "* |
10556 | { | |
10557 | if (which_alternative != 0) | |
10558 | return \"#\"; | |
10559 | else if (get_attr_length (insn) == 8) | |
10560 | return \"bdz %l0\"; | |
10561 | else | |
c81bebd7 | 10562 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
10563 | }" |
10564 | [(set_attr "type" "branch") | |
10565 | (set_attr "length" "*,12,16")]) | |
10566 | ||
c225ba7b | 10567 | ;; Similar, but we can use GE since we have a REG_NONNEG. |
0ad91047 DE |
10568 | |
10569 | (define_insn "*ctrsi_internal3" | |
1fd4e8c1 | 10570 | [(set (pc) |
5f81043f | 10571 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 10572 | (const_int 0)) |
a6845123 | 10573 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 10574 | (pc))) |
5f81043f RK |
10575 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
10576 | (plus:SI (match_dup 1) | |
10577 | (const_int -1))) | |
1fd4e8c1 RK |
10578 | (clobber (match_scratch:CC 3 "=X,&x,&X")) |
10579 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 10580 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
b19003d8 RK |
10581 | "* |
10582 | { | |
af87a13e | 10583 | if (which_alternative != 0) |
b19003d8 RK |
10584 | return \"#\"; |
10585 | else if (get_attr_length (insn) == 8) | |
a6845123 | 10586 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 10587 | else |
c81bebd7 | 10588 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 10589 | }" |
baf97f86 RK |
10590 | [(set_attr "type" "branch") |
10591 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 10592 | |
0ad91047 | 10593 | (define_insn "*ctrsi_internal4" |
1fd4e8c1 | 10594 | [(set (pc) |
5f81043f RK |
10595 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
10596 | (const_int 0)) | |
10597 | (pc) | |
10598 | (label_ref (match_operand 0 "" "")))) | |
10599 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
10600 | (plus:SI (match_dup 1) | |
10601 | (const_int -1))) | |
10602 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
10603 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 10604 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
5f81043f RK |
10605 | "* |
10606 | { | |
10607 | if (which_alternative != 0) | |
10608 | return \"#\"; | |
10609 | else if (get_attr_length (insn) == 8) | |
10610 | return \"bdz %l0\"; | |
10611 | else | |
c81bebd7 | 10612 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
10613 | }" |
10614 | [(set_attr "type" "branch") | |
10615 | (set_attr "length" "*,12,16")]) | |
10616 | ||
0ad91047 DE |
10617 | (define_insn "*ctrdi_internal3" |
10618 | [(set (pc) | |
10619 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") | |
10620 | (const_int 0)) | |
10621 | (label_ref (match_operand 0 "" "")) | |
10622 | (pc))) | |
10623 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
10624 | (plus:DI (match_dup 1) | |
10625 | (const_int -1))) | |
10626 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
10627 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
10628 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" | |
10629 | "* | |
10630 | { | |
10631 | if (which_alternative != 0) | |
10632 | return \"#\"; | |
10633 | else if (get_attr_length (insn) == 8) | |
10634 | return \"{bdn|bdnz} %l0\"; | |
10635 | else | |
10636 | return \"bdz %$+8\;b %l0\"; | |
10637 | }" | |
10638 | [(set_attr "type" "branch") | |
10639 | (set_attr "length" "*,12,16")]) | |
10640 | ||
10641 | (define_insn "*ctrdi_internal4" | |
10642 | [(set (pc) | |
10643 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") | |
10644 | (const_int 0)) | |
10645 | (pc) | |
10646 | (label_ref (match_operand 0 "" "")))) | |
10647 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
10648 | (plus:DI (match_dup 1) | |
10649 | (const_int -1))) | |
10650 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
10651 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
10652 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" | |
10653 | "* | |
10654 | { | |
10655 | if (which_alternative != 0) | |
10656 | return \"#\"; | |
10657 | else if (get_attr_length (insn) == 8) | |
10658 | return \"bdz %l0\"; | |
10659 | else | |
10660 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
10661 | }" | |
10662 | [(set_attr "type" "branch") | |
10663 | (set_attr "length" "*,12,16")]) | |
10664 | ||
10665 | ;; Similar but use EQ | |
10666 | ||
10667 | (define_insn "*ctrsi_internal5" | |
5f81043f RK |
10668 | [(set (pc) |
10669 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
1fd4e8c1 | 10670 | (const_int 1)) |
a6845123 | 10671 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 10672 | (pc))) |
5f81043f RK |
10673 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
10674 | (plus:SI (match_dup 1) | |
10675 | (const_int -1))) | |
1fd4e8c1 RK |
10676 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
10677 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 10678 | "! TARGET_POWERPC64" |
b19003d8 RK |
10679 | "* |
10680 | { | |
af87a13e | 10681 | if (which_alternative != 0) |
b19003d8 RK |
10682 | return \"#\"; |
10683 | else if (get_attr_length (insn) == 8) | |
a6845123 | 10684 | return \"bdz %l0\"; |
b19003d8 | 10685 | else |
c81bebd7 | 10686 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
b19003d8 | 10687 | }" |
baf97f86 RK |
10688 | [(set_attr "type" "branch") |
10689 | (set_attr "length" "*,12,16")]) | |
1fd4e8c1 | 10690 | |
0ad91047 | 10691 | (define_insn "*ctrsi_internal6" |
5f81043f RK |
10692 | [(set (pc) |
10693 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
10694 | (const_int 1)) | |
10695 | (pc) | |
10696 | (label_ref (match_operand 0 "" "")))) | |
10697 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
10698 | (plus:SI (match_dup 1) | |
10699 | (const_int -1))) | |
10700 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
10701 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
10702 | "! TARGET_POWERPC64" |
10703 | "* | |
10704 | { | |
10705 | if (which_alternative != 0) | |
10706 | return \"#\"; | |
10707 | else if (get_attr_length (insn) == 8) | |
10708 | return \"{bdn|bdnz} %l0\"; | |
10709 | else | |
10710 | return \"bdz %$+8\;b %l0\"; | |
10711 | }" | |
10712 | [(set_attr "type" "branch") | |
10713 | (set_attr "length" "*,12,16")]) | |
10714 | ||
10715 | (define_insn "*ctrdi_internal5" | |
10716 | [(set (pc) | |
10717 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") | |
10718 | (const_int 1)) | |
10719 | (label_ref (match_operand 0 "" "")) | |
10720 | (pc))) | |
10721 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
10722 | (plus:DI (match_dup 1) | |
10723 | (const_int -1))) | |
10724 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
10725 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
10726 | "TARGET_POWERPC64" | |
10727 | "* | |
10728 | { | |
10729 | if (which_alternative != 0) | |
10730 | return \"#\"; | |
10731 | else if (get_attr_length (insn) == 8) | |
10732 | return \"bdz %l0\"; | |
10733 | else | |
10734 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
10735 | }" | |
10736 | [(set_attr "type" "branch") | |
10737 | (set_attr "length" "*,12,16")]) | |
10738 | ||
10739 | (define_insn "*ctrdi_internal6" | |
10740 | [(set (pc) | |
10741 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") | |
10742 | (const_int 1)) | |
10743 | (pc) | |
10744 | (label_ref (match_operand 0 "" "")))) | |
10745 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
10746 | (plus:DI (match_dup 1) | |
10747 | (const_int -1))) | |
10748 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
10749 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
10750 | "TARGET_POWERPC64" | |
5f81043f RK |
10751 | "* |
10752 | { | |
10753 | if (which_alternative != 0) | |
10754 | return \"#\"; | |
10755 | else if (get_attr_length (insn) == 8) | |
10756 | return \"{bdn|bdnz} %l0\"; | |
10757 | else | |
c81bebd7 | 10758 | return \"bdz %$+8\;b %l0\"; |
5f81043f RK |
10759 | }" |
10760 | [(set_attr "type" "branch") | |
10761 | (set_attr "length" "*,12,16")]) | |
10762 | ||
0ad91047 DE |
10763 | ;; Now the splitters if we could not allocate the CTR register |
10764 | ||
1fd4e8c1 RK |
10765 | (define_split |
10766 | [(set (pc) | |
10767 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 10768 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10769 | (const_int 1)]) |
10770 | (match_operand 5 "" "") | |
10771 | (match_operand 6 "" ""))) | |
cd2b37d9 | 10772 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
10773 | (plus:SI (match_dup 1) |
10774 | (const_int -1))) | |
1fd4e8c1 RK |
10775 | (clobber (match_scratch:CC 3 "")) |
10776 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 | 10777 | "! TARGET_POWERPC64 && reload_completed" |
1fd4e8c1 | 10778 | [(parallel [(set (match_dup 3) |
5f81043f RK |
10779 | (compare:CC (plus:SI (match_dup 1) |
10780 | (const_int -1)) | |
1fd4e8c1 | 10781 | (const_int 0))) |
5f81043f RK |
10782 | (set (match_dup 0) |
10783 | (plus:SI (match_dup 1) | |
10784 | (const_int -1)))]) | |
10785 | (set (pc) (if_then_else (match_dup 7) | |
10786 | (match_dup 5) | |
10787 | (match_dup 6)))] | |
1fd4e8c1 RK |
10788 | " |
10789 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
10790 | const0_rtx); }") | |
10791 | ||
10792 | (define_split | |
10793 | [(set (pc) | |
10794 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 10795 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10796 | (const_int 1)]) |
10797 | (match_operand 5 "" "") | |
10798 | (match_operand 6 "" ""))) | |
10799 | (set (match_operand:SI 0 "general_operand" "") | |
10800 | (plus:SI (match_dup 1) (const_int -1))) | |
10801 | (clobber (match_scratch:CC 3 "")) | |
10802 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 DE |
10803 | "! TARGET_POWERPC64 && reload_completed |
10804 | && ! gpc_reg_operand (operands[0], SImode)" | |
1fd4e8c1 | 10805 | [(parallel [(set (match_dup 3) |
5f81043f RK |
10806 | (compare:CC (plus:SI (match_dup 1) |
10807 | (const_int -1)) | |
1fd4e8c1 | 10808 | (const_int 0))) |
5f81043f RK |
10809 | (set (match_dup 4) |
10810 | (plus:SI (match_dup 1) | |
10811 | (const_int -1)))]) | |
10812 | (set (match_dup 0) | |
10813 | (match_dup 4)) | |
10814 | (set (pc) (if_then_else (match_dup 7) | |
10815 | (match_dup 5) | |
10816 | (match_dup 6)))] | |
1fd4e8c1 RK |
10817 | " |
10818 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
10819 | const0_rtx); }") | |
0ad91047 DE |
10820 | (define_split |
10821 | [(set (pc) | |
10822 | (if_then_else (match_operator 2 "comparison_operator" | |
10823 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
10824 | (const_int 1)]) | |
10825 | (match_operand 5 "" "") | |
10826 | (match_operand 6 "" ""))) | |
10827 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
10828 | (plus:DI (match_dup 1) | |
10829 | (const_int -1))) | |
10830 | (clobber (match_scratch:CC 3 "")) | |
10831 | (clobber (match_scratch:DI 4 ""))] | |
10832 | "TARGET_POWERPC64 && reload_completed" | |
10833 | [(parallel [(set (match_dup 3) | |
10834 | (compare:CC (plus:DI (match_dup 1) | |
10835 | (const_int -1)) | |
10836 | (const_int 0))) | |
10837 | (set (match_dup 0) | |
10838 | (plus:DI (match_dup 1) | |
10839 | (const_int -1)))]) | |
10840 | (set (pc) (if_then_else (match_dup 7) | |
10841 | (match_dup 5) | |
10842 | (match_dup 6)))] | |
10843 | " | |
10844 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
10845 | const0_rtx); }") | |
10846 | ||
10847 | (define_split | |
10848 | [(set (pc) | |
10849 | (if_then_else (match_operator 2 "comparison_operator" | |
10850 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
10851 | (const_int 1)]) | |
10852 | (match_operand 5 "" "") | |
10853 | (match_operand 6 "" ""))) | |
10854 | (set (match_operand:DI 0 "general_operand" "") | |
10855 | (plus:DI (match_dup 1) (const_int -1))) | |
10856 | (clobber (match_scratch:CC 3 "")) | |
10857 | (clobber (match_scratch:DI 4 ""))] | |
10858 | "TARGET_POWERPC64 && reload_completed | |
10859 | && ! gpc_reg_operand (operands[0], DImode)" | |
10860 | [(parallel [(set (match_dup 3) | |
10861 | (compare:CC (plus:DI (match_dup 1) | |
10862 | (const_int -1)) | |
10863 | (const_int 0))) | |
10864 | (set (match_dup 4) | |
10865 | (plus:DI (match_dup 1) | |
10866 | (const_int -1)))]) | |
10867 | (set (match_dup 0) | |
10868 | (match_dup 4)) | |
10869 | (set (pc) (if_then_else (match_dup 7) | |
10870 | (match_dup 5) | |
10871 | (match_dup 6)))] | |
10872 | " | |
10873 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
10874 | const0_rtx); }") | |
e0cd0770 JC |
10875 | \f |
10876 | (define_insn "trap" | |
10877 | [(trap_if (const_int 1) (const_int 0))] | |
10878 | "" | |
10879 | "{t 31,0,0|trap}") | |
10880 | ||
10881 | (define_expand "conditional_trap" | |
10882 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
10883 | [(match_dup 2) (match_dup 3)]) | |
10884 | (match_operand 1 "const_int_operand" ""))] | |
10885 | "" | |
10886 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
10887 | operands[2] = rs6000_compare_op0; | |
10888 | operands[3] = rs6000_compare_op1;") | |
10889 | ||
10890 | (define_insn "" | |
10891 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
10892 | [(match_operand:SI 1 "register_operand" "r") | |
10893 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
10894 | (const_int 0))] | |
10895 | "" | |
10896 | "t%V0%I2 %1,%2") |