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Step 1 of VSX changes: Powerpc infrstructure changes
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
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996a5f59 1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
d24652ee 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
66647d44 3;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
602ea4d3 4;; Free Software Foundation, Inc.
996a5f59 5;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
1fd4e8c1 6
5de601cf 7;; This file is part of GCC.
1fd4e8c1 8
5de601cf
NC		 9;; GCC is free software; you can redistribute it and/or modify it
10;; under the terms of the GNU General Public License as published
2f83c7d6 11;; by the Free Software Foundation; either version 3, or (at your
5de601cf 12;; option) any later version.
1fd4e8c1 13
5de601cf
NC		 14;; GCC is distributed in the hope that it will be useful, but WITHOUT
15;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17;; License for more details.
1fd4e8c1
RK		 18
19;; You should have received a copy of the GNU General Public License
2f83c7d6
NC		 20;; along with GCC; see the file COPYING3. If not see
21;; <http://www.gnu.org/licenses/>.
1fd4e8c1
RK		 22
23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
9ebbca7d 24
1de43f85
DE		 25;;
26;; REGNOS
27;;
28
29(define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
51
615158e2
JJ		 52;;
53;; UNSPEC usage
54;;
55
56(define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
63 (UNSPEC_FCTIWZ 10)
9719f3b7
DE		 64 (UNSPEC_FRIM 11)
65 (UNSPEC_FRIN 12)
66 (UNSPEC_FRIP 13)
67 (UNSPEC_FRIZ 14)
615158e2
JJ		 68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
70 (UNSPEC_TLSGD 17)
71 (UNSPEC_TLSLD 18)
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
74 (UNSPEC_TLSDTPREL 21)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
78 (UNSPEC_TLSTPREL 25)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
82 (UNSPEC_TLSTLS 29)
ecb62ae7 83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
cef6b86c 84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
da4c340c 85 (UNSPEC_STFIWX 32)
9f0076e5
DE		 86 (UNSPEC_POPCNTB 33)
87 (UNSPEC_FRES 34)
88 (UNSPEC_SP_SET 35)
89 (UNSPEC_SP_TEST 36)
90 (UNSPEC_SYNC 37)
91 (UNSPEC_LWSYNC 38)
92 (UNSPEC_ISYNC 39)
93 (UNSPEC_SYNC_OP 40)
94 (UNSPEC_ATOMIC 41)
95 (UNSPEC_CMPXCHG 42)
96 (UNSPEC_XCHG 43)
97 (UNSPEC_AND 44)
716019c0
JM		 98 (UNSPEC_DLMZB 45)
99 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47)
9c78b944 101 (UNSPEC_RSQRT 48)
2e4316da 102 (UNSPEC_TOCREL 49)
08a6a74b 103 (UNSPEC_MACHOPIC_OFFSET 50)
615158e2
JJ		 104 ])
105
106;;
107;; UNSPEC_VOLATILE usage
108;;
109
110(define_constants
111 [(UNSPECV_BLOCK 0)
b52110d4
DE		 112 (UNSPECV_LL 1) ; load-locked
113 (UNSPECV_SC 2) ; store-conditional
615158e2
JJ		 114 (UNSPECV_EH_RR 9) ; eh_reg_restore
115 ])
1fd4e8c1
RK		 116\f
117;; Define an insn type attribute. This is used in function unit delay
118;; computations.
44cd321e 119(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
1fd4e8c1
RK		 120 (const_string "integer"))
121
0bb7b92e
ME		 122;; Define floating point instruction sub-types for use with Xfpu.md
123(define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
124
b19003d8 125;; Length (in bytes).
6ae08853 126; '(pc)' in the following doesn't include the instruction itself; it is
6cbadf36 127; calculated as if the instruction had zero size.
b19003d8
RK		 128(define_attr "length" ""
129 (if_then_else (eq_attr "type" "branch")
6cbadf36 130 (if_then_else (and (ge (minus (match_dup 0) (pc))
b19003d8 131 (const_int -32768))
6cbadf36
GK		 132 (lt (minus (match_dup 0) (pc))
133 (const_int 32764)))
39a10a29
GK		 134 (const_int 4)
135 (const_int 8))
b19003d8
RK		 136 (const_int 4)))
137
cfb557c4
RK		 138;; Processor type -- this attribute must exactly match the processor_type
139;; enumeration in rs6000.h.
140
cacf1ca8 141(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,power7,cell"
cfb557c4
RK		 142 (const (symbol_ref "rs6000_cpu_attr")))
143
d296e02e
AP		 144
145;; If this instruction is microcoded on the CELL processor
c921bad8 146; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
d296e02e 147(define_attr "cell_micro" "not,conditional,always"
f8f49aea
BE		 148 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
149 (const_string "always")
150 (const_string "not")))
d296e02e 151
b54cf83a
DE		 152(automata_option "ndfa")
153
154(include "rios1.md")
155(include "rios2.md")
156(include "rs64.md")
157(include "mpc.md")
158(include "40x.md")
02ca7595 159(include "440.md")
b54cf83a
DE		 160(include "603.md")
161(include "6xx.md")
162(include "7xx.md")
163(include "7450.md")
5e8006fa 164(include "8540.md")
fa41c305 165(include "e300c2c3.md")
edae5fe3 166(include "e500mc.md")
b54cf83a 167(include "power4.md")
ec507f2d 168(include "power5.md")
44cd321e 169(include "power6.md")
d296e02e 170(include "cell.md")
0bb7b92e 171(include "xfpu.md")
48d72335
DE		 172
173(include "predicates.md")
279bb624 174(include "constraints.md")
48d72335 175
ac9e2cff 176(include "darwin.md")
309323c2 177
1fd4e8c1 178\f
3abcb3a7 179;; Mode iterators
915167f5 180
3abcb3a7 181; This mode iterator allows :GPR to be used to indicate the allowable size
915167f5 182; of whole values in GPRs.
3abcb3a7 183(define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
915167f5 184
0354e5d8 185; Any supported integer mode.
3abcb3a7 186(define_mode_iterator INT [QI HI SI DI TI])
915167f5 187
0354e5d8 188; Any supported integer mode that fits in one register.
3abcb3a7 189(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
915167f5 190
b5568f07 191; extend modes for DImode
3abcb3a7 192(define_mode_iterator QHSI [QI HI SI])
b5568f07 193
0354e5d8 194; SImode or DImode, even if DImode doesn't fit in GPRs.
3abcb3a7 195(define_mode_iterator SDI [SI DI])
0354e5d8
GK		 196
197; The size of a pointer. Also, the size of the value that a record-condition
198; (one with a '.') will compare.
3abcb3a7 199(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
2e6c9641 200
4ae234b0 201; Any hardware-supported floating-point mode
696e45ba
ME		 202(define_mode_iterator FP [
203 (SF "TARGET_HARD_FLOAT
204 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
205 (DF "TARGET_HARD_FLOAT
206 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
602ea4d3 207 (TF "!TARGET_IEEEQUAD
17caeff2
JM		 208 && TARGET_HARD_FLOAT
209 && (TARGET_FPRS || TARGET_E500_DOUBLE)
6ef9a246
JJ		 210 && TARGET_LONG_DOUBLE_128")
211 (DD "TARGET_DFP")
212 (TD "TARGET_DFP")])
4ae234b0 213
915167f5 214; Various instructions that come in SI and DI forms.
0354e5d8 215; A generic w/d attribute, for things like cmpw/cmpd.
b5568f07
DE		 216(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
217
218; DImode bits
219(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
915167f5 220
cacf1ca8
MM		 221;; ISEL/ISEL64 target selection
222(define_mode_attr sel [(SI "") (DI "64")])
223
224;; Suffix for reload patterns
225(define_mode_attr ptrsize [(SI "32bit")
226 (DI "64bit")])
227
228(define_mode_attr tptrsize [(SI "TARGET_32BIT")
229 (DI "TARGET_64BIT")])
230
231(define_mode_attr mptrsize [(SI "si")
232 (DI "di")])
233
915167f5 234\f
1fd4e8c1
RK		 235;; Start with fixed-point load and store insns. Here we put only the more
236;; complex forms. Basic data transfer is done later.
237
b5568f07 238(define_expand "zero_extend<mode>di2"
51b8fc2c 239 [(set (match_operand:DI 0 "gpc_reg_operand" "")
b5568f07 240 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
51b8fc2c
RK		 241 "TARGET_POWERPC64"
242 "")
243
b5568f07 244(define_insn "*zero_extend<mode>di2_internal1"
51b8fc2c 245 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
b5568f07 246 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
51b8fc2c
RK		 247 "TARGET_POWERPC64"
248 "@
b5568f07
DE		 249 l<wd>z%U1%X1 %0,%1
250 rldicl %0,%1,0,<dbits>"
51b8fc2c
RK		 251 [(set_attr "type" "load,*")])
252
b5568f07 253(define_insn "*zero_extend<mode>di2_internal2"
9ebbca7d 254 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
b5568f07 255 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
815cdc52 256 (const_int 0)))
9ebbca7d 257 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 258 "TARGET_64BIT"
9ebbca7d 259 "@
b5568f07 260 rldicl. %2,%1,0,<dbits>
9ebbca7d
GK		 261 #"
262 [(set_attr "type" "compare")
263 (set_attr "length" "4,8")])
264
265(define_split
c921bad8 266 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
b5568f07 267 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 268 (const_int 0)))
269 (clobber (match_scratch:DI 2 ""))]
270 "TARGET_POWERPC64 && reload_completed"
271 [(set (match_dup 2)
272 (zero_extend:DI (match_dup 1)))
273 (set (match_dup 0)
274 (compare:CC (match_dup 2)
275 (const_int 0)))]
276 "")
51b8fc2c 277
b5568f07 278(define_insn "*zero_extend<mode>di2_internal3"
9ebbca7d 279 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
b5568f07 280 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 281 (const_int 0)))
9ebbca7d 282 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 283 (zero_extend:DI (match_dup 1)))]
683bdff7 284 "TARGET_64BIT"
9ebbca7d 285 "@
b5568f07 286 rldicl. %0,%1,0,<dbits>
9ebbca7d
GK		 287 #"
288 [(set_attr "type" "compare")
289 (set_attr "length" "4,8")])
290
291(define_split
c921bad8 292 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
b5568f07 293 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 294 (const_int 0)))
295 (set (match_operand:DI 0 "gpc_reg_operand" "")
296 (zero_extend:DI (match_dup 1)))]
297 "TARGET_POWERPC64 && reload_completed"
298 [(set (match_dup 0)
299 (zero_extend:DI (match_dup 1)))
300 (set (match_dup 2)
301 (compare:CC (match_dup 0)
302 (const_int 0)))]
303 "")
51b8fc2c 304
2bee0449
RK		 305(define_insn "extendqidi2"
306 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
307 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 308 "TARGET_POWERPC64"
44cd321e
PS		 309 "extsb %0,%1"
310 [(set_attr "type" "exts")])
51b8fc2c
RK		 311
312(define_insn ""
9ebbca7d
GK		 313 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
314 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 315 (const_int 0)))
9ebbca7d 316 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 317 "TARGET_64BIT"
9ebbca7d
GK		 318 "@
319 extsb. %2,%1
320 #"
321 [(set_attr "type" "compare")
322 (set_attr "length" "4,8")])
323
324(define_split
c921bad8 325 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 326 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
327 (const_int 0)))
328 (clobber (match_scratch:DI 2 ""))]
329 "TARGET_POWERPC64 && reload_completed"
330 [(set (match_dup 2)
331 (sign_extend:DI (match_dup 1)))
332 (set (match_dup 0)
333 (compare:CC (match_dup 2)
334 (const_int 0)))]
335 "")
51b8fc2c
RK		 336
337(define_insn ""
9ebbca7d
GK		 338 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
339 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 340 (const_int 0)))
9ebbca7d 341 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 342 (sign_extend:DI (match_dup 1)))]
683bdff7 343 "TARGET_64BIT"
9ebbca7d
GK		 344 "@
345 extsb. %0,%1
346 #"
347 [(set_attr "type" "compare")
348 (set_attr "length" "4,8")])
349
350(define_split
c921bad8 351 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 352 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
353 (const_int 0)))
354 (set (match_operand:DI 0 "gpc_reg_operand" "")
355 (sign_extend:DI (match_dup 1)))]
356 "TARGET_POWERPC64 && reload_completed"
357 [(set (match_dup 0)
358 (sign_extend:DI (match_dup 1)))
359 (set (match_dup 2)
360 (compare:CC (match_dup 0)
361 (const_int 0)))]
362 "")
51b8fc2c 363
51b8fc2c
RK		 364(define_expand "extendhidi2"
365 [(set (match_operand:DI 0 "gpc_reg_operand" "")
366 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
367 "TARGET_POWERPC64"
368 "")
369
370(define_insn ""
371 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
372 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
c921bad8 373 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
51b8fc2c
RK		 374 "@
375 lha%U1%X1 %0,%1
376 extsh %0,%1"
44cd321e 377 [(set_attr "type" "load_ext,exts")])
51b8fc2c 378
c921bad8
AP		 379(define_insn ""
380 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
381 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
382 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
383 "extsh %0,%1"
384 [(set_attr "type" "exts")])
385
51b8fc2c 386(define_insn ""
9ebbca7d
GK		 387 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
388 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 389 (const_int 0)))
9ebbca7d 390 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 391 "TARGET_64BIT"
9ebbca7d
GK		 392 "@
393 extsh. %2,%1
394 #"
395 [(set_attr "type" "compare")
396 (set_attr "length" "4,8")])
397
398(define_split
c921bad8 399 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 400 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
401 (const_int 0)))
402 (clobber (match_scratch:DI 2 ""))]
403 "TARGET_POWERPC64 && reload_completed"
404 [(set (match_dup 2)
405 (sign_extend:DI (match_dup 1)))
406 (set (match_dup 0)
407 (compare:CC (match_dup 2)
408 (const_int 0)))]
409 "")
51b8fc2c
RK		 410
411(define_insn ""
9ebbca7d
GK		 412 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
413 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 414 (const_int 0)))
9ebbca7d 415 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 416 (sign_extend:DI (match_dup 1)))]
683bdff7 417 "TARGET_64BIT"
9ebbca7d
GK		 418 "@
419 extsh. %0,%1
420 #"
421 [(set_attr "type" "compare")
422 (set_attr "length" "4,8")])
423
424(define_split
c921bad8 425 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 426 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
427 (const_int 0)))
428 (set (match_operand:DI 0 "gpc_reg_operand" "")
429 (sign_extend:DI (match_dup 1)))]
430 "TARGET_POWERPC64 && reload_completed"
431 [(set (match_dup 0)
432 (sign_extend:DI (match_dup 1)))
433 (set (match_dup 2)
434 (compare:CC (match_dup 0)
435 (const_int 0)))]
436 "")
51b8fc2c 437
51b8fc2c
RK		 438(define_expand "extendsidi2"
439 [(set (match_operand:DI 0 "gpc_reg_operand" "")
440 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
441 "TARGET_POWERPC64"
442 "")
443
444(define_insn ""
445 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
287f13ff 446 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
c921bad8 447 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
51b8fc2c
RK		 448 "@
449 lwa%U1%X1 %0,%1
450 extsw %0,%1"
44cd321e 451 [(set_attr "type" "load_ext,exts")])
51b8fc2c 452
c921bad8
AP		 453(define_insn ""
454 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
455 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
456 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
457 "extsw %0,%1"
458 [(set_attr "type" "exts")])
459
51b8fc2c 460(define_insn ""
9ebbca7d
GK		 461 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
462 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 463 (const_int 0)))
9ebbca7d 464 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 465 "TARGET_64BIT"
9ebbca7d
GK		 466 "@
467 extsw. %2,%1
468 #"
469 [(set_attr "type" "compare")
470 (set_attr "length" "4,8")])
471
472(define_split
c921bad8 473 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 474 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
475 (const_int 0)))
476 (clobber (match_scratch:DI 2 ""))]
477 "TARGET_POWERPC64 && reload_completed"
478 [(set (match_dup 2)
479 (sign_extend:DI (match_dup 1)))
480 (set (match_dup 0)
481 (compare:CC (match_dup 2)
482 (const_int 0)))]
483 "")
51b8fc2c
RK		 484
485(define_insn ""
9ebbca7d
GK		 486 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
487 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 488 (const_int 0)))
9ebbca7d 489 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 490 (sign_extend:DI (match_dup 1)))]
683bdff7 491 "TARGET_64BIT"
9ebbca7d
GK		 492 "@
493 extsw. %0,%1
494 #"
495 [(set_attr "type" "compare")
496 (set_attr "length" "4,8")])
497
498(define_split
c921bad8 499 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 500 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
501 (const_int 0)))
502 (set (match_operand:DI 0 "gpc_reg_operand" "")
503 (sign_extend:DI (match_dup 1)))]
504 "TARGET_POWERPC64 && reload_completed"
505 [(set (match_dup 0)
506 (sign_extend:DI (match_dup 1)))
507 (set (match_dup 2)
508 (compare:CC (match_dup 0)
509 (const_int 0)))]
510 "")
51b8fc2c 511
1fd4e8c1 512(define_expand "zero_extendqisi2"
cd2b37d9
RK		 513 [(set (match_operand:SI 0 "gpc_reg_operand" "")
514 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 515 ""
516 "")
517
518(define_insn ""
cd2b37d9 519 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 520 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
521 ""
522 "@
523 lbz%U1%X1 %0,%1
005a35b9 524 {rlinm|rlwinm} %0,%1,0,0xff"
1fd4e8c1
RK		 525 [(set_attr "type" "load,*")])
526
527(define_insn ""
9ebbca7d
GK		 528 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
529 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 530 (const_int 0)))
9ebbca7d 531 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 532 ""
9ebbca7d
GK		 533 "@
534 {andil.|andi.} %2,%1,0xff
535 #"
cacf1ca8 536 [(set_attr "type" "fast_compare,compare")
9ebbca7d
GK		 537 (set_attr "length" "4,8")])
538
539(define_split
c921bad8 540 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 541 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
542 (const_int 0)))
543 (clobber (match_scratch:SI 2 ""))]
544 "reload_completed"
545 [(set (match_dup 2)
546 (zero_extend:SI (match_dup 1)))
547 (set (match_dup 0)
548 (compare:CC (match_dup 2)
549 (const_int 0)))]
550 "")
1fd4e8c1
RK		 551
552(define_insn ""
9ebbca7d
GK		 553 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
554 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 555 (const_int 0)))
9ebbca7d 556 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 557 (zero_extend:SI (match_dup 1)))]
558 ""
9ebbca7d
GK		 559 "@
560 {andil.|andi.} %0,%1,0xff
561 #"
cacf1ca8 562 [(set_attr "type" "fast_compare,compare")
9ebbca7d
GK		 563 (set_attr "length" "4,8")])
564
565(define_split
c921bad8 566 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 567 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
568 (const_int 0)))
569 (set (match_operand:SI 0 "gpc_reg_operand" "")
570 (zero_extend:SI (match_dup 1)))]
571 "reload_completed"
572 [(set (match_dup 0)
573 (zero_extend:SI (match_dup 1)))
574 (set (match_dup 2)
575 (compare:CC (match_dup 0)
576 (const_int 0)))]
577 "")
1fd4e8c1 578
51b8fc2c
RK		 579(define_expand "extendqisi2"
580 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
581 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
582 ""
583 "
584{
585 if (TARGET_POWERPC)
586 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
587 else if (TARGET_POWER)
588 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
589 else
590 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
591 DONE;
592}")
593
594(define_insn "extendqisi2_ppc"
2bee0449
RK		 595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
596 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 597 "TARGET_POWERPC"
44cd321e
PS		 598 "extsb %0,%1"
599 [(set_attr "type" "exts")])
51b8fc2c
RK		 600
601(define_insn ""
9ebbca7d
GK		 602 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
603 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 604 (const_int 0)))
9ebbca7d 605 (clobber (match_scratch:SI 2 "=r,r"))]
51b8fc2c 606 "TARGET_POWERPC"
9ebbca7d
GK		 607 "@
608 extsb. %2,%1
609 #"
610 [(set_attr "type" "compare")
611 (set_attr "length" "4,8")])
612
613(define_split
c921bad8 614 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 615 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
616 (const_int 0)))
617 (clobber (match_scratch:SI 2 ""))]
618 "TARGET_POWERPC && reload_completed"
619 [(set (match_dup 2)
620 (sign_extend:SI (match_dup 1)))
621 (set (match_dup 0)
622 (compare:CC (match_dup 2)
623 (const_int 0)))]
624 "")
51b8fc2c
RK		 625
626(define_insn ""
9ebbca7d
GK		 627 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
628 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 629 (const_int 0)))
9ebbca7d 630 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 631 (sign_extend:SI (match_dup 1)))]
632 "TARGET_POWERPC"
9ebbca7d
GK		 633 "@
634 extsb. %0,%1
635 #"
636 [(set_attr "type" "compare")
637 (set_attr "length" "4,8")])
638
639(define_split
c921bad8 640 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 641 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
642 (const_int 0)))
643 (set (match_operand:SI 0 "gpc_reg_operand" "")
644 (sign_extend:SI (match_dup 1)))]
645 "TARGET_POWERPC && reload_completed"
646 [(set (match_dup 0)
647 (sign_extend:SI (match_dup 1)))
648 (set (match_dup 2)
649 (compare:CC (match_dup 0)
650 (const_int 0)))]
651 "")
51b8fc2c
RK		 652
653(define_expand "extendqisi2_power"
654 [(parallel [(set (match_dup 2)
655 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
656 (const_int 24)))
657 (clobber (scratch:SI))])
658 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
659 (ashiftrt:SI (match_dup 2)
660 (const_int 24)))
661 (clobber (scratch:SI))])]
662 "TARGET_POWER"
663 "
664{ operands[1] = gen_lowpart (SImode, operands[1]);
665 operands[2] = gen_reg_rtx (SImode); }")
666
667(define_expand "extendqisi2_no_power"
668 [(set (match_dup 2)
669 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
670 (const_int 24)))
671 (set (match_operand:SI 0 "gpc_reg_operand" "")
672 (ashiftrt:SI (match_dup 2)
673 (const_int 24)))]
674 "! TARGET_POWER && ! TARGET_POWERPC"
675 "
676{ operands[1] = gen_lowpart (SImode, operands[1]);
677 operands[2] = gen_reg_rtx (SImode); }")
678
1fd4e8c1 679(define_expand "zero_extendqihi2"
cd2b37d9
RK		 680 [(set (match_operand:HI 0 "gpc_reg_operand" "")
681 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 682 ""
683 "")
684
685(define_insn ""
cd2b37d9 686 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 687 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
688 ""
689 "@
690 lbz%U1%X1 %0,%1
005a35b9 691 {rlinm|rlwinm} %0,%1,0,0xff"
51b8fc2c
RK		 692 [(set_attr "type" "load,*")])
693
694(define_insn ""
9ebbca7d
GK		 695 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
696 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 697 (const_int 0)))
9ebbca7d 698 (clobber (match_scratch:HI 2 "=r,r"))]
51b8fc2c 699 ""
9ebbca7d
GK		 700 "@
701 {andil.|andi.} %2,%1,0xff
702 #"
cacf1ca8 703 [(set_attr "type" "fast_compare,compare")
9ebbca7d
GK		 704 (set_attr "length" "4,8")])
705
706(define_split
c921bad8 707 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 708 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
709 (const_int 0)))
710 (clobber (match_scratch:HI 2 ""))]
711 "reload_completed"
712 [(set (match_dup 2)
713 (zero_extend:HI (match_dup 1)))
714 (set (match_dup 0)
715 (compare:CC (match_dup 2)
716 (const_int 0)))]
717 "")
1fd4e8c1 718
51b8fc2c 719(define_insn ""
9ebbca7d
GK		 720 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
721 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 722 (const_int 0)))
9ebbca7d 723 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 724 (zero_extend:HI (match_dup 1)))]
725 ""
9ebbca7d
GK		 726 "@
727 {andil.|andi.} %0,%1,0xff
728 #"
cacf1ca8 729 [(set_attr "type" "fast_compare,compare")
9ebbca7d
GK		 730 (set_attr "length" "4,8")])
731
732(define_split
c921bad8 733 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 734 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
735 (const_int 0)))
736 (set (match_operand:HI 0 "gpc_reg_operand" "")
737 (zero_extend:HI (match_dup 1)))]
738 "reload_completed"
739 [(set (match_dup 0)
740 (zero_extend:HI (match_dup 1)))
741 (set (match_dup 2)
742 (compare:CC (match_dup 0)
743 (const_int 0)))]
744 "")
815cdc52
MM		 745
746(define_expand "extendqihi2"
747 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
748 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
749 ""
750 "
751{
752 if (TARGET_POWERPC)
753 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
754 else if (TARGET_POWER)
755 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
756 else
757 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
758 DONE;
759}")
760
761(define_insn "extendqihi2_ppc"
762 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
763 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
764 "TARGET_POWERPC"
44cd321e
PS		 765 "extsb %0,%1"
766 [(set_attr "type" "exts")])
815cdc52
MM		 767
768(define_insn ""
9ebbca7d
GK		 769 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
770 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815cdc52 771 (const_int 0)))
9ebbca7d 772 (clobber (match_scratch:HI 2 "=r,r"))]
815cdc52 773 "TARGET_POWERPC"
9ebbca7d
GK		 774 "@
775 extsb. %2,%1
776 #"
777 [(set_attr "type" "compare")
778 (set_attr "length" "4,8")])
779
780(define_split
c921bad8 781 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 782 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
783 (const_int 0)))
784 (clobber (match_scratch:HI 2 ""))]
785 "TARGET_POWERPC && reload_completed"
786 [(set (match_dup 2)
787 (sign_extend:HI (match_dup 1)))
788 (set (match_dup 0)
789 (compare:CC (match_dup 2)
790 (const_int 0)))]
791 "")
815cdc52
MM		 792
793(define_insn ""
9ebbca7d
GK		 794 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
795 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 796 (const_int 0)))
9ebbca7d 797 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 798 (sign_extend:HI (match_dup 1)))]
799 "TARGET_POWERPC"
9ebbca7d
GK		 800 "@
801 extsb. %0,%1
802 #"
803 [(set_attr "type" "compare")
804 (set_attr "length" "4,8")])
805
806(define_split
c921bad8 807 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 808 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
809 (const_int 0)))
810 (set (match_operand:HI 0 "gpc_reg_operand" "")
811 (sign_extend:HI (match_dup 1)))]
812 "TARGET_POWERPC && reload_completed"
813 [(set (match_dup 0)
814 (sign_extend:HI (match_dup 1)))
815 (set (match_dup 2)
816 (compare:CC (match_dup 0)
817 (const_int 0)))]
818 "")
51b8fc2c
RK		 819
820(define_expand "extendqihi2_power"
821 [(parallel [(set (match_dup 2)
822 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
823 (const_int 24)))
824 (clobber (scratch:SI))])
825 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
826 (ashiftrt:SI (match_dup 2)
827 (const_int 24)))
828 (clobber (scratch:SI))])]
829 "TARGET_POWER"
830 "
831{ operands[0] = gen_lowpart (SImode, operands[0]);
832 operands[1] = gen_lowpart (SImode, operands[1]);
833 operands[2] = gen_reg_rtx (SImode); }")
834
835(define_expand "extendqihi2_no_power"
836 [(set (match_dup 2)
837 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
838 (const_int 24)))
839 (set (match_operand:HI 0 "gpc_reg_operand" "")
840 (ashiftrt:SI (match_dup 2)
841 (const_int 24)))]
842 "! TARGET_POWER && ! TARGET_POWERPC"
843 "
844{ operands[0] = gen_lowpart (SImode, operands[0]);
845 operands[1] = gen_lowpart (SImode, operands[1]);
846 operands[2] = gen_reg_rtx (SImode); }")
847
1fd4e8c1 848(define_expand "zero_extendhisi2"
5f243543 849 [(set (match_operand:SI 0 "gpc_reg_operand" "")
cd2b37d9 850 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 851 ""
852 "")
853
854(define_insn ""
cd2b37d9 855 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 856 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
857 ""
858 "@
859 lhz%U1%X1 %0,%1
005a35b9 860 {rlinm|rlwinm} %0,%1,0,0xffff"
1fd4e8c1
RK		 861 [(set_attr "type" "load,*")])
862
863(define_insn ""
9ebbca7d
GK		 864 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
865 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 866 (const_int 0)))
9ebbca7d 867 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 868 ""
9ebbca7d
GK		 869 "@
870 {andil.|andi.} %2,%1,0xffff
871 #"
cacf1ca8 872 [(set_attr "type" "fast_compare,compare")
9ebbca7d
GK		 873 (set_attr "length" "4,8")])
874
875(define_split
c921bad8 876 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 877 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
878 (const_int 0)))
879 (clobber (match_scratch:SI 2 ""))]
880 "reload_completed"
881 [(set (match_dup 2)
882 (zero_extend:SI (match_dup 1)))
883 (set (match_dup 0)
884 (compare:CC (match_dup 2)
885 (const_int 0)))]
886 "")
1fd4e8c1
RK		 887
888(define_insn ""
9ebbca7d
GK		 889 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
890 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 891 (const_int 0)))
9ebbca7d 892 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 893 (zero_extend:SI (match_dup 1)))]
894 ""
9ebbca7d
GK		 895 "@
896 {andil.|andi.} %0,%1,0xffff
897 #"
cacf1ca8 898 [(set_attr "type" "fast_compare,compare")
9ebbca7d
GK		 899 (set_attr "length" "4,8")])
900
901(define_split
c921bad8 902 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 903 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
904 (const_int 0)))
905 (set (match_operand:SI 0 "gpc_reg_operand" "")
906 (zero_extend:SI (match_dup 1)))]
907 "reload_completed"
908 [(set (match_dup 0)
909 (zero_extend:SI (match_dup 1)))
910 (set (match_dup 2)
911 (compare:CC (match_dup 0)
912 (const_int 0)))]
913 "")
1fd4e8c1
RK		 914
915(define_expand "extendhisi2"
cd2b37d9
RK		 916 [(set (match_operand:SI 0 "gpc_reg_operand" "")
917 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 918 ""
919 "")
920
921(define_insn ""
cd2b37d9 922 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 923 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
c921bad8 924 "rs6000_gen_cell_microcode"
1fd4e8c1
RK		 925 "@
926 lha%U1%X1 %0,%1
ca7f5001 927 {exts|extsh} %0,%1"
44cd321e 928 [(set_attr "type" "load_ext,exts")])
1fd4e8c1 929
c921bad8
AP		 930(define_insn ""
931 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
932 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
933 "!rs6000_gen_cell_microcode"
934 "{exts|extsh} %0,%1"
935 [(set_attr "type" "exts")])
936
1fd4e8c1 937(define_insn ""
9ebbca7d
GK		 938 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
939 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 940 (const_int 0)))
9ebbca7d 941 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 942 ""
9ebbca7d
GK		 943 "@
944 {exts.|extsh.} %2,%1
945 #"
946 [(set_attr "type" "compare")
947 (set_attr "length" "4,8")])
948
949(define_split
c921bad8 950 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 951 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
952 (const_int 0)))
953 (clobber (match_scratch:SI 2 ""))]
954 "reload_completed"
955 [(set (match_dup 2)
956 (sign_extend:SI (match_dup 1)))
957 (set (match_dup 0)
958 (compare:CC (match_dup 2)
959 (const_int 0)))]
960 "")
1fd4e8c1
RK		 961
962(define_insn ""
9ebbca7d
GK		 963 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
964 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 965 (const_int 0)))
9ebbca7d 966 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 967 (sign_extend:SI (match_dup 1)))]
968 ""
9ebbca7d
GK		 969 "@
970 {exts.|extsh.} %0,%1
971 #"
972 [(set_attr "type" "compare")
973 (set_attr "length" "4,8")])
1fd4e8c1 974\f
4adf8008 975;; IBM 405, 440 and 464 half-word multiplication operations.
131aeb82
JM		 976
977(define_insn "*macchwc"
978 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
979 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
980 (match_operand:SI 2 "gpc_reg_operand" "r")
981 (const_int 16))
982 (sign_extend:SI
983 (match_operand:HI 1 "gpc_reg_operand" "r")))
984 (match_operand:SI 4 "gpc_reg_operand" "0"))
985 (const_int 0)))
986 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
987 (plus:SI (mult:SI (ashiftrt:SI
988 (match_dup 2)
989 (const_int 16))
990 (sign_extend:SI
991 (match_dup 1)))
992 (match_dup 4)))]
993 "TARGET_MULHW"
994 "macchw. %0, %1, %2"
995 [(set_attr "type" "imul3")])
996
997(define_insn "*macchw"
998 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
999 (plus:SI (mult:SI (ashiftrt:SI
1000 (match_operand:SI 2 "gpc_reg_operand" "r")
1001 (const_int 16))
1002 (sign_extend:SI
1003 (match_operand:HI 1 "gpc_reg_operand" "r")))
1004 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1005 "TARGET_MULHW"
1006 "macchw %0, %1, %2"
1007 [(set_attr "type" "imul3")])
1008
1009(define_insn "*macchwuc"
1010 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1011 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1012 (match_operand:SI 2 "gpc_reg_operand" "r")
1013 (const_int 16))
1014 (zero_extend:SI
1015 (match_operand:HI 1 "gpc_reg_operand" "r")))
1016 (match_operand:SI 4 "gpc_reg_operand" "0"))
1017 (const_int 0)))
1018 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1019 (plus:SI (mult:SI (lshiftrt:SI
1020 (match_dup 2)
1021 (const_int 16))
1022 (zero_extend:SI
1023 (match_dup 1)))
1024 (match_dup 4)))]
1025 "TARGET_MULHW"
1026 "macchwu. %0, %1, %2"
1027 [(set_attr "type" "imul3")])
1028
1029(define_insn "*macchwu"
1030 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1031 (plus:SI (mult:SI (lshiftrt:SI
1032 (match_operand:SI 2 "gpc_reg_operand" "r")
1033 (const_int 16))
1034 (zero_extend:SI
1035 (match_operand:HI 1 "gpc_reg_operand" "r")))
1036 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1037 "TARGET_MULHW"
1038 "macchwu %0, %1, %2"
1039 [(set_attr "type" "imul3")])
1040
1041(define_insn "*machhwc"
1042 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1043 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1044 (match_operand:SI 1 "gpc_reg_operand" "%r")
1045 (const_int 16))
1046 (ashiftrt:SI
1047 (match_operand:SI 2 "gpc_reg_operand" "r")
1048 (const_int 16)))
1049 (match_operand:SI 4 "gpc_reg_operand" "0"))
1050 (const_int 0)))
1051 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1052 (plus:SI (mult:SI (ashiftrt:SI
1053 (match_dup 1)
1054 (const_int 16))
1055 (ashiftrt:SI
1056 (match_dup 2)
1057 (const_int 16)))
1058 (match_dup 4)))]
1059 "TARGET_MULHW"
1060 "machhw. %0, %1, %2"
1061 [(set_attr "type" "imul3")])
1062
1063(define_insn "*machhw"
1064 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1065 (plus:SI (mult:SI (ashiftrt:SI
1066 (match_operand:SI 1 "gpc_reg_operand" "%r")
1067 (const_int 16))
1068 (ashiftrt:SI
1069 (match_operand:SI 2 "gpc_reg_operand" "r")
1070 (const_int 16)))
1071 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1072 "TARGET_MULHW"
1073 "machhw %0, %1, %2"
1074 [(set_attr "type" "imul3")])
1075
1076(define_insn "*machhwuc"
1077 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1078 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1079 (match_operand:SI 1 "gpc_reg_operand" "%r")
1080 (const_int 16))
1081 (lshiftrt:SI
1082 (match_operand:SI 2 "gpc_reg_operand" "r")
1083 (const_int 16)))
1084 (match_operand:SI 4 "gpc_reg_operand" "0"))
1085 (const_int 0)))
1086 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1087 (plus:SI (mult:SI (lshiftrt:SI
1088 (match_dup 1)
1089 (const_int 16))
1090 (lshiftrt:SI
1091 (match_dup 2)
1092 (const_int 16)))
1093 (match_dup 4)))]
1094 "TARGET_MULHW"
1095 "machhwu. %0, %1, %2"
1096 [(set_attr "type" "imul3")])
1097
1098(define_insn "*machhwu"
1099 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1100 (plus:SI (mult:SI (lshiftrt:SI
1101 (match_operand:SI 1 "gpc_reg_operand" "%r")
1102 (const_int 16))
1103 (lshiftrt:SI
1104 (match_operand:SI 2 "gpc_reg_operand" "r")
1105 (const_int 16)))
1106 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1107 "TARGET_MULHW"
1108 "machhwu %0, %1, %2"
1109 [(set_attr "type" "imul3")])
1110
1111(define_insn "*maclhwc"
1112 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1113 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1114 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1115 (sign_extend:SI
1116 (match_operand:HI 2 "gpc_reg_operand" "r")))
1117 (match_operand:SI 4 "gpc_reg_operand" "0"))
1118 (const_int 0)))
1119 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1120 (plus:SI (mult:SI (sign_extend:SI
1121 (match_dup 1))
1122 (sign_extend:SI
1123 (match_dup 2)))
1124 (match_dup 4)))]
1125 "TARGET_MULHW"
1126 "maclhw. %0, %1, %2"
1127 [(set_attr "type" "imul3")])
1128
1129(define_insn "*maclhw"
1130 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1131 (plus:SI (mult:SI (sign_extend:SI
1132 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1133 (sign_extend:SI
1134 (match_operand:HI 2 "gpc_reg_operand" "r")))
1135 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1136 "TARGET_MULHW"
1137 "maclhw %0, %1, %2"
1138 [(set_attr "type" "imul3")])
1139
1140(define_insn "*maclhwuc"
1141 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1142 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1143 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1144 (zero_extend:SI
1145 (match_operand:HI 2 "gpc_reg_operand" "r")))
1146 (match_operand:SI 4 "gpc_reg_operand" "0"))
1147 (const_int 0)))
1148 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1149 (plus:SI (mult:SI (zero_extend:SI
1150 (match_dup 1))
1151 (zero_extend:SI
1152 (match_dup 2)))
1153 (match_dup 4)))]
1154 "TARGET_MULHW"
1155 "maclhwu. %0, %1, %2"
1156 [(set_attr "type" "imul3")])
1157
1158(define_insn "*maclhwu"
1159 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1160 (plus:SI (mult:SI (zero_extend:SI
1161 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1162 (zero_extend:SI
1163 (match_operand:HI 2 "gpc_reg_operand" "r")))
1164 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1165 "TARGET_MULHW"
1166 "maclhwu %0, %1, %2"
1167 [(set_attr "type" "imul3")])
1168
1169(define_insn "*nmacchwc"
1170 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1171 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1172 (mult:SI (ashiftrt:SI
1173 (match_operand:SI 2 "gpc_reg_operand" "r")
1174 (const_int 16))
1175 (sign_extend:SI
1176 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1177 (const_int 0)))
1178 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1179 (minus:SI (match_dup 4)
1180 (mult:SI (ashiftrt:SI
1181 (match_dup 2)
1182 (const_int 16))
1183 (sign_extend:SI
1184 (match_dup 1)))))]
1185 "TARGET_MULHW"
1186 "nmacchw. %0, %1, %2"
1187 [(set_attr "type" "imul3")])
1188
1189(define_insn "*nmacchw"
1190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1191 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1192 (mult:SI (ashiftrt:SI
1193 (match_operand:SI 2 "gpc_reg_operand" "r")
1194 (const_int 16))
1195 (sign_extend:SI
1196 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1197 "TARGET_MULHW"
1198 "nmacchw %0, %1, %2"
1199 [(set_attr "type" "imul3")])
1200
1201(define_insn "*nmachhwc"
1202 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1203 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1204 (mult:SI (ashiftrt:SI
1205 (match_operand:SI 1 "gpc_reg_operand" "%r")
1206 (const_int 16))
1207 (ashiftrt:SI
1208 (match_operand:SI 2 "gpc_reg_operand" "r")
1209 (const_int 16))))
1210 (const_int 0)))
1211 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1212 (minus:SI (match_dup 4)
1213 (mult:SI (ashiftrt:SI
1214 (match_dup 1)
1215 (const_int 16))
1216 (ashiftrt:SI
1217 (match_dup 2)
1218 (const_int 16)))))]
1219 "TARGET_MULHW"
1220 "nmachhw. %0, %1, %2"
1221 [(set_attr "type" "imul3")])
1222
1223(define_insn "*nmachhw"
1224 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1225 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1226 (mult:SI (ashiftrt:SI
1227 (match_operand:SI 1 "gpc_reg_operand" "%r")
1228 (const_int 16))
1229 (ashiftrt:SI
1230 (match_operand:SI 2 "gpc_reg_operand" "r")
1231 (const_int 16)))))]
1232 "TARGET_MULHW"
1233 "nmachhw %0, %1, %2"
1234 [(set_attr "type" "imul3")])
1235
1236(define_insn "*nmaclhwc"
1237 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1238 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1239 (mult:SI (sign_extend:SI
1240 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1241 (sign_extend:SI
1242 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1243 (const_int 0)))
1244 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1245 (minus:SI (match_dup 4)
1246 (mult:SI (sign_extend:SI
1247 (match_dup 1))
1248 (sign_extend:SI
1249 (match_dup 2)))))]
1250 "TARGET_MULHW"
1251 "nmaclhw. %0, %1, %2"
1252 [(set_attr "type" "imul3")])
1253
1254(define_insn "*nmaclhw"
1255 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1256 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1257 (mult:SI (sign_extend:SI
1258 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1259 (sign_extend:SI
1260 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1261 "TARGET_MULHW"
1262 "nmaclhw %0, %1, %2"
1263 [(set_attr "type" "imul3")])
1264
1265(define_insn "*mulchwc"
1266 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1267 (compare:CC (mult:SI (ashiftrt:SI
1268 (match_operand:SI 2 "gpc_reg_operand" "r")
1269 (const_int 16))
1270 (sign_extend:SI
1271 (match_operand:HI 1 "gpc_reg_operand" "r")))
1272 (const_int 0)))
1273 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1274 (mult:SI (ashiftrt:SI
1275 (match_dup 2)
1276 (const_int 16))
1277 (sign_extend:SI
1278 (match_dup 1))))]
1279 "TARGET_MULHW"
1280 "mulchw. %0, %1, %2"
1281 [(set_attr "type" "imul3")])
1282
1283(define_insn "*mulchw"
1284 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1285 (mult:SI (ashiftrt:SI
1286 (match_operand:SI 2 "gpc_reg_operand" "r")
1287 (const_int 16))
1288 (sign_extend:SI
1289 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1290 "TARGET_MULHW"
1291 "mulchw %0, %1, %2"
1292 [(set_attr "type" "imul3")])
1293
1294(define_insn "*mulchwuc"
1295 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1296 (compare:CC (mult:SI (lshiftrt:SI
1297 (match_operand:SI 2 "gpc_reg_operand" "r")
1298 (const_int 16))
1299 (zero_extend:SI
1300 (match_operand:HI 1 "gpc_reg_operand" "r")))
1301 (const_int 0)))
1302 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1303 (mult:SI (lshiftrt:SI
1304 (match_dup 2)
1305 (const_int 16))
1306 (zero_extend:SI
1307 (match_dup 1))))]
1308 "TARGET_MULHW"
1309 "mulchwu. %0, %1, %2"
1310 [(set_attr "type" "imul3")])
1311
1312(define_insn "*mulchwu"
1313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1314 (mult:SI (lshiftrt:SI
1315 (match_operand:SI 2 "gpc_reg_operand" "r")
1316 (const_int 16))
1317 (zero_extend:SI
1318 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1319 "TARGET_MULHW"
1320 "mulchwu %0, %1, %2"
1321 [(set_attr "type" "imul3")])
1322
1323(define_insn "*mulhhwc"
1324 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1325 (compare:CC (mult:SI (ashiftrt:SI
1326 (match_operand:SI 1 "gpc_reg_operand" "%r")
1327 (const_int 16))
1328 (ashiftrt:SI
1329 (match_operand:SI 2 "gpc_reg_operand" "r")
1330 (const_int 16)))
1331 (const_int 0)))
1332 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1333 (mult:SI (ashiftrt:SI
1334 (match_dup 1)
1335 (const_int 16))
1336 (ashiftrt:SI
1337 (match_dup 2)
1338 (const_int 16))))]
1339 "TARGET_MULHW"
1340 "mulhhw. %0, %1, %2"
1341 [(set_attr "type" "imul3")])
1342
1343(define_insn "*mulhhw"
1344 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1345 (mult:SI (ashiftrt:SI
1346 (match_operand:SI 1 "gpc_reg_operand" "%r")
1347 (const_int 16))
1348 (ashiftrt:SI
1349 (match_operand:SI 2 "gpc_reg_operand" "r")
1350 (const_int 16))))]
1351 "TARGET_MULHW"
1352 "mulhhw %0, %1, %2"
1353 [(set_attr "type" "imul3")])
1354
1355(define_insn "*mulhhwuc"
1356 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1357 (compare:CC (mult:SI (lshiftrt:SI
1358 (match_operand:SI 1 "gpc_reg_operand" "%r")
1359 (const_int 16))
1360 (lshiftrt:SI
1361 (match_operand:SI 2 "gpc_reg_operand" "r")
1362 (const_int 16)))
1363 (const_int 0)))
1364 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1365 (mult:SI (lshiftrt:SI
1366 (match_dup 1)
1367 (const_int 16))
1368 (lshiftrt:SI
1369 (match_dup 2)
1370 (const_int 16))))]
1371 "TARGET_MULHW"
1372 "mulhhwu. %0, %1, %2"
1373 [(set_attr "type" "imul3")])
1374
1375(define_insn "*mulhhwu"
1376 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1377 (mult:SI (lshiftrt:SI
1378 (match_operand:SI 1 "gpc_reg_operand" "%r")
1379 (const_int 16))
1380 (lshiftrt:SI
1381 (match_operand:SI 2 "gpc_reg_operand" "r")
1382 (const_int 16))))]
1383 "TARGET_MULHW"
1384 "mulhhwu %0, %1, %2"
1385 [(set_attr "type" "imul3")])
1386
1387(define_insn "*mullhwc"
1388 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1389 (compare:CC (mult:SI (sign_extend:SI
1390 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1391 (sign_extend:SI
1392 (match_operand:HI 2 "gpc_reg_operand" "r")))
1393 (const_int 0)))
1394 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1395 (mult:SI (sign_extend:SI
1396 (match_dup 1))
1397 (sign_extend:SI
1398 (match_dup 2))))]
1399 "TARGET_MULHW"
1400 "mullhw. %0, %1, %2"
1401 [(set_attr "type" "imul3")])
1402
1403(define_insn "*mullhw"
1404 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1405 (mult:SI (sign_extend:SI
1406 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1407 (sign_extend:SI
1408 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1409 "TARGET_MULHW"
1410 "mullhw %0, %1, %2"
1411 [(set_attr "type" "imul3")])
1412
1413(define_insn "*mullhwuc"
1414 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1415 (compare:CC (mult:SI (zero_extend:SI
1416 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1417 (zero_extend:SI
1418 (match_operand:HI 2 "gpc_reg_operand" "r")))
1419 (const_int 0)))
1420 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1421 (mult:SI (zero_extend:SI
1422 (match_dup 1))
1423 (zero_extend:SI
1424 (match_dup 2))))]
1425 "TARGET_MULHW"
1426 "mullhwu. %0, %1, %2"
1427 [(set_attr "type" "imul3")])
1428
1429(define_insn "*mullhwu"
1430 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1431 (mult:SI (zero_extend:SI
1432 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1433 (zero_extend:SI
1434 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1435 "TARGET_MULHW"
1436 "mullhwu %0, %1, %2"
1437 [(set_attr "type" "imul3")])
1438\f
4adf8008 1439;; IBM 405, 440 and 464 string-search dlmzb instruction support.
716019c0
JM		 1440(define_insn "dlmzb"
1441 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1442 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1443 (match_operand:SI 2 "gpc_reg_operand" "r")]
1444 UNSPEC_DLMZB_CR))
1445 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1446 (unspec:SI [(match_dup 1)
1447 (match_dup 2)]
1448 UNSPEC_DLMZB))]
1449 "TARGET_DLMZB"
1450 "dlmzb. %0, %1, %2")
1451
1452(define_expand "strlensi"
1453 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1454 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1455 (match_operand:QI 2 "const_int_operand" "")
1456 (match_operand 3 "const_int_operand" "")]
1457 UNSPEC_DLMZB_STRLEN))
1458 (clobber (match_scratch:CC 4 "=x"))]
1459 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1460{
1461 rtx result = operands[0];
1462 rtx src = operands[1];
1463 rtx search_char = operands[2];
1464 rtx align = operands[3];
1465 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1466 rtx loop_label, end_label, mem, cr0, cond;
1467 if (search_char != const0_rtx
1468 || GET_CODE (align) != CONST_INT
1469 || INTVAL (align) < 8)
1470 FAIL;
1471 word1 = gen_reg_rtx (SImode);
1472 word2 = gen_reg_rtx (SImode);
1473 scratch_dlmzb = gen_reg_rtx (SImode);
1474 scratch_string = gen_reg_rtx (Pmode);
1475 loop_label = gen_label_rtx ();
1476 end_label = gen_label_rtx ();
1477 addr = force_reg (Pmode, XEXP (src, 0));
1478 emit_move_insn (scratch_string, addr);
1479 emit_label (loop_label);
1480 mem = change_address (src, SImode, scratch_string);
1481 emit_move_insn (word1, mem);
1482 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1483 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1484 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1485 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1486 emit_jump_insn (gen_rtx_SET (VOIDmode,
1487 pc_rtx,
1488 gen_rtx_IF_THEN_ELSE (VOIDmode,
1489 cond,
1490 gen_rtx_LABEL_REF
1491 (VOIDmode,
1492 end_label),
1493 pc_rtx)));
1494 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1495 emit_jump_insn (gen_rtx_SET (VOIDmode,
1496 pc_rtx,
1497 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
ea5bd0d8 1498 emit_barrier ();
716019c0
JM		 1499 emit_label (end_label);
1500 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1501 emit_insn (gen_subsi3 (result, scratch_string, addr));
1502 emit_insn (gen_subsi3 (result, result, const1_rtx));
1503 DONE;
1504})
1505\f
9ebbca7d 1506(define_split
c921bad8 1507 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 1508 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1509 (const_int 0)))
1510 (set (match_operand:SI 0 "gpc_reg_operand" "")
1511 (sign_extend:SI (match_dup 1)))]
1512 "reload_completed"
1513 [(set (match_dup 0)
1514 (sign_extend:SI (match_dup 1)))
1515 (set (match_dup 2)
1516 (compare:CC (match_dup 0)
1517 (const_int 0)))]
1518 "")
1519
1fd4e8c1 1520;; Fixed-point arithmetic insns.
deb9225a 1521
0354e5d8
GK		 1522(define_expand "add<mode>3"
1523 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1524 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
4ae234b0 1525 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
7cd5235b 1526 ""
7cd5235b 1527{
0354e5d8
GK		 1528 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1529 {
1530 if (non_short_cint_operand (operands[2], DImode))
1531 FAIL;
1532 }
1533 else if (GET_CODE (operands[2]) == CONST_INT
1534 && ! add_operand (operands[2], <MODE>mode))
7cd5235b 1535 {
b3a13419
ILT		 1536 rtx tmp = ((!can_create_pseudo_p ()
1537 || rtx_equal_p (operands[0], operands[1]))
0354e5d8 1538 ? operands[0] : gen_reg_rtx (<MODE>mode));
7cd5235b 1539
2bfcf297 1540 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1541 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8
GK		 1542 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1543
279bb624 1544 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
0354e5d8 1545 FAIL;
7cd5235b 1546
9ebbca7d
GK		 1547 /* The ordering here is important for the prolog expander.
1548 When space is allocated from the stack, adding 'low' first may
1549 produce a temporary deallocation (which would be bad). */
0354e5d8
GK		 1550 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1551 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
7cd5235b
MM		 1552 DONE;
1553 }
279bb624 1554})
7cd5235b 1555
0354e5d8
GK		 1556;; Discourage ai/addic because of carry but provide it in an alternative
1557;; allowing register zero as source.
1558(define_insn "*add<mode>3_internal1"
1559 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1560 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1561 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
7393f7f8 1562 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1fd4e8c1 1563 "@
deb9225a
RK		 1564 {cax|add} %0,%1,%2
1565 {cal %0,%2(%1)|addi %0,%1,%2}
1566 {ai|addic} %0,%1,%2
7cd5235b
MM		 1567 {cau|addis} %0,%1,%v2"
1568 [(set_attr "length" "4,4,4,4")])
1fd4e8c1 1569
ee890fe2
SS		 1570(define_insn "addsi3_high"
1571 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1572 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1573 (high:SI (match_operand 2 "" ""))))]
1574 "TARGET_MACHO && !TARGET_64BIT"
1575 "{cau|addis} %0,%1,ha16(%2)"
1576 [(set_attr "length" "4")])
1577
0354e5d8 1578(define_insn "*add<mode>3_internal2"
cb8cc086 1579 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1580 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1581 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1582 (const_int 0)))
0354e5d8
GK		 1583 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1584 ""
deb9225a
RK		 1585 "@
1586 {cax.|add.} %3,%1,%2
cb8cc086
MM		 1587 {ai.|addic.} %3,%1,%2
1588 #
1589 #"
a62bfff2 1590 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1591 (set_attr "length" "4,4,8,8")])
1592
1593(define_split
1594 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1595 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1596 (match_operand:GPR 2 "reg_or_short_operand" ""))
cb8cc086 1597 (const_int 0)))
0354e5d8
GK		 1598 (clobber (match_scratch:GPR 3 ""))]
1599 "reload_completed"
cb8cc086 1600 [(set (match_dup 3)
0354e5d8 1601 (plus:GPR (match_dup 1)
cb8cc086
MM		 1602 (match_dup 2)))
1603 (set (match_dup 0)
1604 (compare:CC (match_dup 3)
1605 (const_int 0)))]
1606 "")
7e69e155 1607
0354e5d8 1608(define_insn "*add<mode>3_internal3"
cb8cc086 1609 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1610 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1611 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1612 (const_int 0)))
0354e5d8
GK		 1613 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1614 (plus:P (match_dup 1)
1615 (match_dup 2)))]
1616 ""
deb9225a
RK		 1617 "@
1618 {cax.|add.} %0,%1,%2
cb8cc086
MM		 1619 {ai.|addic.} %0,%1,%2
1620 #
1621 #"
a62bfff2 1622 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1623 (set_attr "length" "4,4,8,8")])
1624
1625(define_split
1626 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1627 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1628 (match_operand:P 2 "reg_or_short_operand" ""))
cb8cc086 1629 (const_int 0)))
0354e5d8
GK		 1630 (set (match_operand:P 0 "gpc_reg_operand" "")
1631 (plus:P (match_dup 1) (match_dup 2)))]
1632 "reload_completed"
cb8cc086 1633 [(set (match_dup 0)
0354e5d8
GK		 1634 (plus:P (match_dup 1)
1635 (match_dup 2)))
cb8cc086
MM		 1636 (set (match_dup 3)
1637 (compare:CC (match_dup 0)
1638 (const_int 0)))]
1639 "")
7e69e155 1640
f357808b
RK		 1641;; Split an add that we can't do in one insn into two insns, each of which
1642;; does one 16-bit part. This is used by combine. Note that the low-order
1643;; add should be last in case the result gets used in an address.
1644
1645(define_split
0354e5d8
GK		 1646 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1647 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1648 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1fd4e8c1 1649 ""
0354e5d8
GK		 1650 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1651 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1fd4e8c1 1652{
2bfcf297 1653 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1654 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8 1655 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1fd4e8c1 1656
e6ca2c17 1657 operands[4] = GEN_INT (low);
279bb624 1658 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
0354e5d8 1659 operands[3] = GEN_INT (rest);
b3a13419 1660 else if (can_create_pseudo_p ())
0354e5d8
GK		 1661 {
1662 operands[3] = gen_reg_rtx (DImode);
1663 emit_move_insn (operands[3], operands[2]);
1664 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1665 DONE;
1666 }
1667 else
1668 FAIL;
279bb624 1669})
1fd4e8c1 1670
0354e5d8
GK		 1671(define_insn "one_cmpl<mode>2"
1672 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1673 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1 1674 ""
ca7f5001
RK		 1675 "nor %0,%1,%1")
1676
1677(define_insn ""
52d3af72 1678 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 1679 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
ca7f5001 1680 (const_int 0)))
0354e5d8
GK		 1681 (clobber (match_scratch:P 2 "=r,r"))]
1682 ""
52d3af72
DE		 1683 "@
1684 nor. %2,%1,%1
1685 #"
cacf1ca8 1686 [(set_attr "type" "fast_compare,compare")
52d3af72
DE		 1687 (set_attr "length" "4,8")])
1688
1689(define_split
c921bad8 1690 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
0354e5d8 1691 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1692 (const_int 0)))
0354e5d8
GK		 1693 (clobber (match_scratch:P 2 ""))]
1694 "reload_completed"
52d3af72 1695 [(set (match_dup 2)
0354e5d8 1696 (not:P (match_dup 1)))
52d3af72
DE		 1697 (set (match_dup 0)
1698 (compare:CC (match_dup 2)
1699 (const_int 0)))]
1700 "")
ca7f5001
RK		 1701
1702(define_insn ""
52d3af72 1703 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 1704 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 1705 (const_int 0)))
0354e5d8
GK		 1706 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1707 (not:P (match_dup 1)))]
1708 ""
52d3af72
DE		 1709 "@
1710 nor. %0,%1,%1
1711 #"
cacf1ca8 1712 [(set_attr "type" "fast_compare,compare")
52d3af72
DE		 1713 (set_attr "length" "4,8")])
1714
1715(define_split
c921bad8 1716 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
0354e5d8 1717 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1718 (const_int 0)))
0354e5d8
GK		 1719 (set (match_operand:P 0 "gpc_reg_operand" "")
1720 (not:P (match_dup 1)))]
1721 "reload_completed"
52d3af72 1722 [(set (match_dup 0)
0354e5d8 1723 (not:P (match_dup 1)))
52d3af72
DE		 1724 (set (match_dup 2)
1725 (compare:CC (match_dup 0)
1726 (const_int 0)))]
1727 "")
1fd4e8c1
RK		 1728
1729(define_insn ""
3d91674b
RK		 1730 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1731 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1732 (match_operand:SI 2 "gpc_reg_operand" "r")))]
deb9225a 1733 "! TARGET_POWERPC"
ca7f5001 1734 "{sf%I1|subf%I1c} %0,%2,%1")
1fd4e8c1 1735
deb9225a 1736(define_insn ""
0354e5d8
GK		 1737 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1738 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1739 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
deb9225a
RK		 1740 "TARGET_POWERPC"
1741 "@
1742 subf %0,%2,%1
1743 subfic %0,%2,%1")
1744
1fd4e8c1 1745(define_insn ""
cb8cc086
MM		 1746 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1747 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1748 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1749 (const_int 0)))
cb8cc086 1750 (clobber (match_scratch:SI 3 "=r,r"))]
deb9225a 1751 "! TARGET_POWERPC"
cb8cc086
MM		 1752 "@
1753 {sf.|subfc.} %3,%2,%1
1754 #"
1755 [(set_attr "type" "compare")
1756 (set_attr "length" "4,8")])
1fd4e8c1 1757
deb9225a 1758(define_insn ""
cb8cc086 1759 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1760 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1761 (match_operand:P 2 "gpc_reg_operand" "r,r"))
deb9225a 1762 (const_int 0)))
0354e5d8
GK		 1763 (clobber (match_scratch:P 3 "=r,r"))]
1764 "TARGET_POWERPC"
cb8cc086
MM		 1765 "@
1766 subf. %3,%2,%1
1767 #"
a62bfff2 1768 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1769 (set_attr "length" "4,8")])
1770
1771(define_split
1772 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1773 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1774 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1775 (const_int 0)))
0354e5d8
GK		 1776 (clobber (match_scratch:P 3 ""))]
1777 "reload_completed"
cb8cc086 1778 [(set (match_dup 3)
0354e5d8 1779 (minus:P (match_dup 1)
cb8cc086
MM		 1780 (match_dup 2)))
1781 (set (match_dup 0)
1782 (compare:CC (match_dup 3)
1783 (const_int 0)))]
1784 "")
deb9225a 1785
1fd4e8c1 1786(define_insn ""
cb8cc086
MM		 1787 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1788 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1789 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1790 (const_int 0)))
cb8cc086 1791 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 1792 (minus:SI (match_dup 1) (match_dup 2)))]
deb9225a 1793 "! TARGET_POWERPC"
cb8cc086
MM		 1794 "@
1795 {sf.|subfc.} %0,%2,%1
1796 #"
1797 [(set_attr "type" "compare")
1798 (set_attr "length" "4,8")])
815cdc52 1799
29ae5b89 1800(define_insn ""
cb8cc086 1801 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1802 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1803 (match_operand:P 2 "gpc_reg_operand" "r,r"))
815cdc52 1804 (const_int 0)))
0354e5d8
GK		 1805 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1806 (minus:P (match_dup 1)
cb8cc086 1807 (match_dup 2)))]
0354e5d8 1808 "TARGET_POWERPC"
90612787
DE		 1809 "@
1810 subf. %0,%2,%1
1811 #"
a62bfff2 1812 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1813 (set_attr "length" "4,8")])
1814
1815(define_split
1816 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1817 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1818 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1819 (const_int 0)))
0354e5d8
GK		 1820 (set (match_operand:P 0 "gpc_reg_operand" "")
1821 (minus:P (match_dup 1)
cb8cc086 1822 (match_dup 2)))]
0354e5d8 1823 "reload_completed"
cb8cc086 1824 [(set (match_dup 0)
0354e5d8 1825 (minus:P (match_dup 1)
cb8cc086
MM		 1826 (match_dup 2)))
1827 (set (match_dup 3)
1828 (compare:CC (match_dup 0)
1829 (const_int 0)))]
1830 "")
deb9225a 1831
0354e5d8
GK		 1832(define_expand "sub<mode>3"
1833 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1834 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
4ae234b0 1835 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1fd4e8c1 1836 ""
a0044fb1
RK		 1837 "
1838{
1839 if (GET_CODE (operands[2]) == CONST_INT)
1840 {
0354e5d8
GK		 1841 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1842 negate_rtx (<MODE>mode, operands[2])));
a0044fb1
RK		 1843 DONE;
1844 }
1845}")
1fd4e8c1
RK		 1846
1847;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1848;; instruction and some auxiliary computations. Then we just have a single
95ac8e67
RK		 1849;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1850;; combine.
1fd4e8c1
RK		 1851
1852(define_expand "sminsi3"
1853 [(set (match_dup 3)
cd2b37d9 1854 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1855 (match_operand:SI 2 "reg_or_short_operand" ""))
1856 (const_int 0)
1857 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1858 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1859 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1860 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1861 "
a3170dc6
AH		 1862{
1863 if (TARGET_ISEL)
1864 {
1865 operands[2] = force_reg (SImode, operands[2]);
1866 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1867 DONE;
1868 }
1869
1870 operands[3] = gen_reg_rtx (SImode);
1871}")
1fd4e8c1 1872
95ac8e67
RK		 1873(define_split
1874 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1875 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1876 (match_operand:SI 2 "reg_or_short_operand" "")))
1877 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1878 "TARGET_POWER"
95ac8e67
RK		 1879 [(set (match_dup 3)
1880 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1881 (const_int 0)
1882 (minus:SI (match_dup 2) (match_dup 1))))
1883 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1884 "")
1885
1fd4e8c1
RK		 1886(define_expand "smaxsi3"
1887 [(set (match_dup 3)
cd2b37d9 1888 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1889 (match_operand:SI 2 "reg_or_short_operand" ""))
1890 (const_int 0)
1891 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1892 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1893 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1894 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1895 "
a3170dc6
AH		 1896{
1897 if (TARGET_ISEL)
1898 {
1899 operands[2] = force_reg (SImode, operands[2]);
1900 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1901 DONE;
1902 }
1903 operands[3] = gen_reg_rtx (SImode);
1904}")
1fd4e8c1 1905
95ac8e67
RK		 1906(define_split
1907 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1908 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1909 (match_operand:SI 2 "reg_or_short_operand" "")))
1910 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1911 "TARGET_POWER"
95ac8e67
RK		 1912 [(set (match_dup 3)
1913 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1914 (const_int 0)
1915 (minus:SI (match_dup 2) (match_dup 1))))
1916 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1917 "")
1918
1fd4e8c1 1919(define_expand "uminsi3"
cd2b37d9 1920 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1921 (match_dup 5)))
cd2b37d9 1922 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1923 (match_dup 5)))
1fd4e8c1
RK		 1924 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1925 (const_int 0)
1926 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1927 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1928 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1929 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1930 "
bb68ff55 1931{
a3170dc6
AH		 1932 if (TARGET_ISEL)
1933 {
1934 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1935 DONE;
1936 }
bb68ff55
MM		 1937 operands[3] = gen_reg_rtx (SImode);
1938 operands[4] = gen_reg_rtx (SImode);
1939 operands[5] = GEN_INT (-2147483647 - 1);
1940}")
1fd4e8c1
RK		 1941
1942(define_expand "umaxsi3"
cd2b37d9 1943 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1944 (match_dup 5)))
cd2b37d9 1945 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1946 (match_dup 5)))
1fd4e8c1
RK		 1947 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1948 (const_int 0)
1949 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1950 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1951 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1952 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1953 "
bb68ff55 1954{
a3170dc6
AH		 1955 if (TARGET_ISEL)
1956 {
1957 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1958 DONE;
1959 }
bb68ff55
MM		 1960 operands[3] = gen_reg_rtx (SImode);
1961 operands[4] = gen_reg_rtx (SImode);
1962 operands[5] = GEN_INT (-2147483647 - 1);
1963}")
1fd4e8c1
RK		 1964
1965(define_insn ""
cd2b37d9
RK		 1966 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1967 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
5c23c401 1968 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 1969 (const_int 0)
1970 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1971 "TARGET_POWER"
1fd4e8c1
RK		 1972 "doz%I2 %0,%1,%2")
1973
1974(define_insn ""
9ebbca7d 1975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 1976 (compare:CC
9ebbca7d
GK		 1977 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1978 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1979 (const_int 0)
1980 (minus:SI (match_dup 2) (match_dup 1)))
1981 (const_int 0)))
9ebbca7d 1982 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 1983 "TARGET_POWER"
9ebbca7d
GK		 1984 "@
1985 doz%I2. %3,%1,%2
1986 #"
1987 [(set_attr "type" "delayed_compare")
1988 (set_attr "length" "4,8")])
1989
1990(define_split
1991 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1992 (compare:CC
1993 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1994 (match_operand:SI 2 "reg_or_short_operand" ""))
1995 (const_int 0)
1996 (minus:SI (match_dup 2) (match_dup 1)))
1997 (const_int 0)))
1998 (clobber (match_scratch:SI 3 ""))]
1999 "TARGET_POWER && reload_completed"
2000 [(set (match_dup 3)
2001 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2002 (const_int 0)
2003 (minus:SI (match_dup 2) (match_dup 1))))
2004 (set (match_dup 0)
2005 (compare:CC (match_dup 3)
2006 (const_int 0)))]
2007 "")
1fd4e8c1
RK		 2008
2009(define_insn ""
9ebbca7d 2010 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 2011 (compare:CC
9ebbca7d
GK		 2012 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2013 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 2014 (const_int 0)
2015 (minus:SI (match_dup 2) (match_dup 1)))
2016 (const_int 0)))
9ebbca7d 2017 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 2018 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2019 (const_int 0)
2020 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 2021 "TARGET_POWER"
9ebbca7d
GK		 2022 "@
2023 doz%I2. %0,%1,%2
2024 #"
2025 [(set_attr "type" "delayed_compare")
2026 (set_attr "length" "4,8")])
2027
2028(define_split
2029 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2030 (compare:CC
2031 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2032 (match_operand:SI 2 "reg_or_short_operand" ""))
2033 (const_int 0)
2034 (minus:SI (match_dup 2) (match_dup 1)))
2035 (const_int 0)))
2036 (set (match_operand:SI 0 "gpc_reg_operand" "")
2037 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2038 (const_int 0)
2039 (minus:SI (match_dup 2) (match_dup 1))))]
2040 "TARGET_POWER && reload_completed"
2041 [(set (match_dup 0)
2042 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2043 (const_int 0)
2044 (minus:SI (match_dup 2) (match_dup 1))))
2045 (set (match_dup 3)
2046 (compare:CC (match_dup 0)
2047 (const_int 0)))]
2048 "")
1fd4e8c1
RK		 2049
2050;; We don't need abs with condition code because such comparisons should
2051;; never be done.
ea9be077
MM		 2052(define_expand "abssi2"
2053 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2054 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2055 ""
2056 "
2057{
a3170dc6
AH		 2058 if (TARGET_ISEL)
2059 {
2060 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2061 DONE;
2062 }
2063 else if (! TARGET_POWER)
ea9be077
MM		 2064 {
2065 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2066 DONE;
2067 }
2068}")
2069
ea112fc4 2070(define_insn "*abssi2_power"
cd2b37d9
RK		 2071 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2072 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
ca7f5001 2073 "TARGET_POWER"
1fd4e8c1
RK		 2074 "abs %0,%1")
2075
a3170dc6
AH		 2076(define_insn_and_split "abssi2_isel"
2077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2078 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8c48b6f5 2079 (clobber (match_scratch:SI 2 "=&b"))
a3170dc6
AH		 2080 (clobber (match_scratch:CC 3 "=y"))]
2081 "TARGET_ISEL"
2082 "#"
2083 "&& reload_completed"
2084 [(set (match_dup 2) (neg:SI (match_dup 1)))
2085 (set (match_dup 3)
2086 (compare:CC (match_dup 1)
2087 (const_int 0)))
2088 (set (match_dup 0)
2089 (if_then_else:SI (ge (match_dup 3)
2090 (const_int 0))
2091 (match_dup 1)
2092 (match_dup 2)))]
2093 "")
2094
ea112fc4 2095(define_insn_and_split "abssi2_nopower"
ea9be077 2096 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2097 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
ea9be077 2098 (clobber (match_scratch:SI 2 "=&r,&r"))]
a3170dc6 2099 "! TARGET_POWER && ! TARGET_ISEL"
ea112fc4
DE		 2100 "#"
2101 "&& reload_completed"
ea9be077
MM		 2102 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2103 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2104 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
ea9be077
MM		 2105 "")
2106
463b558b 2107(define_insn "*nabs_power"
cd2b37d9
RK		 2108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2109 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
ca7f5001 2110 "TARGET_POWER"
1fd4e8c1
RK		 2111 "nabs %0,%1")
2112
ea112fc4 2113(define_insn_and_split "*nabs_nopower"
ea9be077 2114 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2115 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
ea9be077 2116 (clobber (match_scratch:SI 2 "=&r,&r"))]
0ad91047 2117 "! TARGET_POWER"
ea112fc4
DE		 2118 "#"
2119 "&& reload_completed"
ea9be077
MM		 2120 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2121 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2122 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
ea9be077
MM		 2123 "")
2124
0354e5d8
GK		 2125(define_expand "neg<mode>2"
2126 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2127 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2128 ""
2129 "")
2130
2131(define_insn "*neg<mode>2_internal"
2132 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2133 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1
RK		 2134 ""
2135 "neg %0,%1")
2136
2137(define_insn ""
9ebbca7d 2138 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 2139 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 2140 (const_int 0)))
0354e5d8
GK		 2141 (clobber (match_scratch:P 2 "=r,r"))]
2142 ""
9ebbca7d
GK		 2143 "@
2144 neg. %2,%1
2145 #"
a62bfff2 2146 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2147 (set_attr "length" "4,8")])
2148
2149(define_split
2150 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 2151 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2152 (const_int 0)))
0354e5d8
GK		 2153 (clobber (match_scratch:P 2 ""))]
2154 "reload_completed"
9ebbca7d 2155 [(set (match_dup 2)
0354e5d8 2156 (neg:P (match_dup 1)))
9ebbca7d
GK		 2157 (set (match_dup 0)
2158 (compare:CC (match_dup 2)
2159 (const_int 0)))]
2160 "")
1fd4e8c1
RK		 2161
2162(define_insn ""
9ebbca7d 2163 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 2164 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 2165 (const_int 0)))
0354e5d8
GK		 2166 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2167 (neg:P (match_dup 1)))]
2168 ""
9ebbca7d
GK		 2169 "@
2170 neg. %0,%1
2171 #"
a62bfff2 2172 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2173 (set_attr "length" "4,8")])
2174
2175(define_split
2176 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 2177 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2178 (const_int 0)))
0354e5d8
GK		 2179 (set (match_operand:P 0 "gpc_reg_operand" "")
2180 (neg:P (match_dup 1)))]
66859ace 2181 "reload_completed"
9ebbca7d 2182 [(set (match_dup 0)
0354e5d8 2183 (neg:P (match_dup 1)))
9ebbca7d
GK		 2184 (set (match_dup 2)
2185 (compare:CC (match_dup 0)
2186 (const_int 0)))]
2187 "")
1fd4e8c1 2188
0354e5d8
GK		 2189(define_insn "clz<mode>2"
2190 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2191 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1b1edcfa 2192 ""
44cd321e
PS		 2193 "{cntlz|cntlz<wd>} %0,%1"
2194 [(set_attr "type" "cntlz")])
1b1edcfa 2195
0354e5d8 2196(define_expand "ctz<mode>2"
4977bab6 2197 [(set (match_dup 2)
e42ac3de 2198 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2199 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2200 (match_dup 2)))
1b1edcfa 2201 (clobber (scratch:CC))])
0354e5d8 2202 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2203 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2204 (minus:GPR (match_dup 5) (match_dup 4)))]
1fd4e8c1 2205 ""
4977bab6 2206 {
0354e5d8
GK		 2207 operands[2] = gen_reg_rtx (<MODE>mode);
2208 operands[3] = gen_reg_rtx (<MODE>mode);
2209 operands[4] = gen_reg_rtx (<MODE>mode);
2210 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
4977bab6 2211 })
6ae08853 2212
0354e5d8 2213(define_expand "ffs<mode>2"
1b1edcfa 2214 [(set (match_dup 2)
e42ac3de 2215 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2216 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2217 (match_dup 2)))
1b1edcfa 2218 (clobber (scratch:CC))])
0354e5d8 2219 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2220 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2221 (minus:GPR (match_dup 5) (match_dup 4)))]
4977bab6 2222 ""
1b1edcfa 2223 {
0354e5d8
GK		 2224 operands[2] = gen_reg_rtx (<MODE>mode);
2225 operands[3] = gen_reg_rtx (<MODE>mode);
2226 operands[4] = gen_reg_rtx (<MODE>mode);
2227 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1b1edcfa 2228 })
6ae08853 2229
432218ba
DE		 2230(define_insn "popcntb<mode>2"
2231 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2232 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2233 UNSPEC_POPCNTB))]
2234 "TARGET_POPCNTB"
2235 "popcntb %0,%1")
2236
cacf1ca8
MM		 2237(define_insn "popcntwsi2"
2238 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2239 (popcount:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2240 "TARGET_POPCNTD"
2241 "popcntw %0,%1")
2242
2243(define_insn "popcntddi2"
2244 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2245 (popcount:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
2246 "TARGET_POPCNTD && TARGET_POWERPC64"
2247 "popcntd %0,%1")
2248
565ef4ba 2249(define_expand "popcount<mode>2"
e42ac3de
RS		 2250 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2251 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
cacf1ca8 2252 "TARGET_POPCNTB || TARGET_POPCNTD"
565ef4ba
RS		 2253 {
2254 rs6000_emit_popcount (operands[0], operands[1]);
2255 DONE;
2256 })
2257
2258(define_expand "parity<mode>2"
e42ac3de
RS		 2259 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2260 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
565ef4ba
RS		 2261 "TARGET_POPCNTB"
2262 {
2263 rs6000_emit_parity (operands[0], operands[1]);
2264 DONE;
2265 })
2266
03f79051
DE		 2267(define_insn "bswapsi2"
2268 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2269 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2270 ""
2271 "@
2272 {lbrx|lwbrx} %0,%y1
2273 {stbrx|stwbrx} %1,%y0
2274 #"
2275 [(set_attr "length" "4,4,12")])
2276
2277(define_split
2278 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2279 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2280 "reload_completed"
2281 [(set (match_dup 0)
2282 (rotate:SI (match_dup 1) (const_int 8)))
2283 (set (zero_extract:SI (match_dup 0)
2284 (const_int 8)
2285 (const_int 0))
2286 (match_dup 1))
2287 (set (zero_extract:SI (match_dup 0)
2288 (const_int 8)
2289 (const_int 16))
2290 (rotate:SI (match_dup 1)
2291 (const_int 16)))]
2292 "")
2293
ca7f5001
RK		 2294(define_expand "mulsi3"
2295 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2296 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2297 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2298 ""
2299 "
2300{
2301 if (TARGET_POWER)
68b40e7e 2302 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
ca7f5001 2303 else
68b40e7e 2304 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
ca7f5001
RK		 2305 DONE;
2306}")
2307
68b40e7e 2308(define_insn "mulsi3_mq"
cd2b37d9
RK		 2309 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2310 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1fd4e8c1
RK		 2311 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2312 (clobber (match_scratch:SI 3 "=q,q"))]
ca7f5001
RK		 2313 "TARGET_POWER"
2314 "@
2315 {muls|mullw} %0,%1,%2
2316 {muli|mulli} %0,%1,%2"
6ae08853 2317 [(set (attr "type")
c859cda6
DJ		 2318 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2319 (const_string "imul3")
6ae08853 2320 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2321 (const_string "imul2")]
2322 (const_string "imul")))])
ca7f5001 2323
68b40e7e 2324(define_insn "mulsi3_no_mq"
ca7f5001
RK		 2325 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2326 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2327 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
68b40e7e 2328 "! TARGET_POWER"
1fd4e8c1 2329 "@
d904e9ed
RK		 2330 {muls|mullw} %0,%1,%2
2331 {muli|mulli} %0,%1,%2"
6ae08853 2332 [(set (attr "type")
c859cda6
DJ		 2333 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2334 (const_string "imul3")
6ae08853 2335 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2336 (const_string "imul2")]
2337 (const_string "imul")))])
1fd4e8c1 2338
9259f3b0 2339(define_insn "*mulsi3_mq_internal1"
9ebbca7d
GK		 2340 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2341 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2342 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2343 (const_int 0)))
9ebbca7d
GK		 2344 (clobber (match_scratch:SI 3 "=r,r"))
2345 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2346 "TARGET_POWER"
9ebbca7d
GK		 2347 "@
2348 {muls.|mullw.} %3,%1,%2
2349 #"
9259f3b0 2350 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2351 (set_attr "length" "4,8")])
2352
2353(define_split
2354 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2355 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2356 (match_operand:SI 2 "gpc_reg_operand" ""))
2357 (const_int 0)))
2358 (clobber (match_scratch:SI 3 ""))
2359 (clobber (match_scratch:SI 4 ""))]
2360 "TARGET_POWER && reload_completed"
2361 [(parallel [(set (match_dup 3)
2362 (mult:SI (match_dup 1) (match_dup 2)))
2363 (clobber (match_dup 4))])
2364 (set (match_dup 0)
2365 (compare:CC (match_dup 3)
2366 (const_int 0)))]
2367 "")
ca7f5001 2368
9259f3b0 2369(define_insn "*mulsi3_no_mq_internal1"
9ebbca7d
GK		 2370 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2371 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2372 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2373 (const_int 0)))
9ebbca7d 2374 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 2375 "! TARGET_POWER"
9ebbca7d
GK		 2376 "@
2377 {muls.|mullw.} %3,%1,%2
2378 #"
9259f3b0 2379 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2380 (set_attr "length" "4,8")])
2381
2382(define_split
c921bad8 2383 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 2384 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2385 (match_operand:SI 2 "gpc_reg_operand" ""))
2386 (const_int 0)))
2387 (clobber (match_scratch:SI 3 ""))]
2388 "! TARGET_POWER && reload_completed"
2389 [(set (match_dup 3)
2390 (mult:SI (match_dup 1) (match_dup 2)))
2391 (set (match_dup 0)
2392 (compare:CC (match_dup 3)
2393 (const_int 0)))]
2394 "")
1fd4e8c1 2395
9259f3b0 2396(define_insn "*mulsi3_mq_internal2"
9ebbca7d
GK		 2397 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2398 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2399 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2400 (const_int 0)))
9ebbca7d 2401 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
29ae5b89 2402 (mult:SI (match_dup 1) (match_dup 2)))
9ebbca7d 2403 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2404 "TARGET_POWER"
9ebbca7d
GK		 2405 "@
2406 {muls.|mullw.} %0,%1,%2
2407 #"
9259f3b0 2408 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2409 (set_attr "length" "4,8")])
2410
2411(define_split
2412 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2413 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2414 (match_operand:SI 2 "gpc_reg_operand" ""))
2415 (const_int 0)))
2416 (set (match_operand:SI 0 "gpc_reg_operand" "")
2417 (mult:SI (match_dup 1) (match_dup 2)))
2418 (clobber (match_scratch:SI 4 ""))]
2419 "TARGET_POWER && reload_completed"
2420 [(parallel [(set (match_dup 0)
2421 (mult:SI (match_dup 1) (match_dup 2)))
2422 (clobber (match_dup 4))])
2423 (set (match_dup 3)
2424 (compare:CC (match_dup 0)
2425 (const_int 0)))]
2426 "")
ca7f5001 2427
9259f3b0 2428(define_insn "*mulsi3_no_mq_internal2"
9ebbca7d
GK		 2429 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2430 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2431 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2432 (const_int 0)))
9ebbca7d 2433 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 2434 (mult:SI (match_dup 1) (match_dup 2)))]
25c341fa 2435 "! TARGET_POWER"
9ebbca7d
GK		 2436 "@
2437 {muls.|mullw.} %0,%1,%2
2438 #"
9259f3b0 2439 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2440 (set_attr "length" "4,8")])
2441
2442(define_split
c921bad8 2443 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 2444 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2445 (match_operand:SI 2 "gpc_reg_operand" ""))
2446 (const_int 0)))
2447 (set (match_operand:SI 0 "gpc_reg_operand" "")
2448 (mult:SI (match_dup 1) (match_dup 2)))]
2449 "! TARGET_POWER && reload_completed"
2450 [(set (match_dup 0)
2451 (mult:SI (match_dup 1) (match_dup 2)))
2452 (set (match_dup 3)
2453 (compare:CC (match_dup 0)
2454 (const_int 0)))]
2455 "")
1fd4e8c1
RK		 2456
2457;; Operand 1 is divided by operand 2; quotient goes to operand
2458;; 0 and remainder to operand 3.
2459;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2460
8ffd9c51
RK		 2461(define_expand "divmodsi4"
2462 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2463 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2464 (match_operand:SI 2 "gpc_reg_operand" "")))
bb157ff4 2465 (set (match_operand:SI 3 "register_operand" "")
8ffd9c51
RK		 2466 (mod:SI (match_dup 1) (match_dup 2)))])]
2467 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2468 "
2469{
2470 if (! TARGET_POWER && ! TARGET_POWERPC)
2471 {
39403d82
DE		 2472 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2473 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2474 emit_insn (gen_divss_call ());
39403d82
DE		 2475 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2476 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
8ffd9c51
RK		 2477 DONE;
2478 }
2479}")
deb9225a 2480
bb157ff4 2481(define_insn "*divmodsi4_internal"
cd2b37d9
RK		 2482 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2483 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2484 (match_operand:SI 2 "gpc_reg_operand" "r")))
bb157ff4 2485 (set (match_operand:SI 3 "register_operand" "=q")
1fd4e8c1 2486 (mod:SI (match_dup 1) (match_dup 2)))]
ca7f5001 2487 "TARGET_POWER"
cfb557c4
RK		 2488 "divs %0,%1,%2"
2489 [(set_attr "type" "idiv")])
1fd4e8c1 2490
4ae234b0
GK		 2491(define_expand "udiv<mode>3"
2492 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2493 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2494 (match_operand:GPR 2 "gpc_reg_operand" "")))]
8ffd9c51
RK		 2495 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2496 "
2497{
2498 if (! TARGET_POWER && ! TARGET_POWERPC)
2499 {
39403d82
DE		 2500 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2501 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2502 emit_insn (gen_quous_call ());
39403d82 2503 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2504 DONE;
2505 }
f192bf8b
DE		 2506 else if (TARGET_POWER)
2507 {
2508 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2509 DONE;
2510 }
8ffd9c51 2511}")
deb9225a 2512
f192bf8b
DE		 2513(define_insn "udivsi3_mq"
2514 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2515 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2516 (match_operand:SI 2 "gpc_reg_operand" "r")))
2517 (clobber (match_scratch:SI 3 "=q"))]
2518 "TARGET_POWERPC && TARGET_POWER"
2519 "divwu %0,%1,%2"
2520 [(set_attr "type" "idiv")])
2521
2522(define_insn "*udivsi3_no_mq"
4ae234b0
GK		 2523 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2524 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2525 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2526 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2527 "div<wd>u %0,%1,%2"
44cd321e
PS		 2528 [(set (attr "type")
2529 (cond [(match_operand:SI 0 "" "")
2530 (const_string "idiv")]
2531 (const_string "ldiv")))])
2532
ca7f5001 2533
1fd4e8c1 2534;; For powers of two we can do srai/aze for divide and then adjust for
ca7f5001 2535;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
8ffd9c51
RK		 2536;; used; for PowerPC, force operands into register and do a normal divide;
2537;; for AIX common-mode, use quoss call on register operands.
4ae234b0
GK		 2538(define_expand "div<mode>3"
2539 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2540 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2541 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
1fd4e8c1
RK		 2542 ""
2543 "
2544{
ca7f5001 2545 if (GET_CODE (operands[2]) == CONST_INT
2bfcf297 2546 && INTVAL (operands[2]) > 0
ca7f5001
RK		 2547 && exact_log2 (INTVAL (operands[2])) >= 0)
2548 ;
b6c9286a 2549 else if (TARGET_POWERPC)
f192bf8b 2550 {
99e8e649 2551 operands[2] = force_reg (<MODE>mode, operands[2]);
f192bf8b
DE		 2552 if (TARGET_POWER)
2553 {
2554 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2555 DONE;
2556 }
2557 }
b6c9286a 2558 else if (TARGET_POWER)
1fd4e8c1 2559 FAIL;
405c5495 2560 else
8ffd9c51 2561 {
39403d82
DE		 2562 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2563 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2564 emit_insn (gen_quoss_call ());
39403d82 2565 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2566 DONE;
2567 }
1fd4e8c1
RK		 2568}")
2569
f192bf8b
DE		 2570(define_insn "divsi3_mq"
2571 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2572 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2573 (match_operand:SI 2 "gpc_reg_operand" "r")))
2574 (clobber (match_scratch:SI 3 "=q"))]
2575 "TARGET_POWERPC && TARGET_POWER"
2576 "divw %0,%1,%2"
2577 [(set_attr "type" "idiv")])
2578
4ae234b0
GK		 2579(define_insn "*div<mode>3_no_mq"
2580 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2581 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2582 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2583 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2584 "div<wd> %0,%1,%2"
44cd321e
PS		 2585 [(set (attr "type")
2586 (cond [(match_operand:SI 0 "" "")
2587 (const_string "idiv")]
2588 (const_string "ldiv")))])
f192bf8b 2589
4ae234b0
GK		 2590(define_expand "mod<mode>3"
2591 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2592 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2593 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
39b52ba2 2594 ""
1fd4e8c1
RK		 2595 "
2596{
481c7efa 2597 int i;
39b52ba2
RK		 2598 rtx temp1;
2599 rtx temp2;
2600
2bfcf297 2601 if (GET_CODE (operands[2]) != CONST_INT
a65c591c 2602 || INTVAL (operands[2]) <= 0
2bfcf297 2603 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
39b52ba2
RK		 2604 FAIL;
2605
4ae234b0
GK		 2606 temp1 = gen_reg_rtx (<MODE>mode);
2607 temp2 = gen_reg_rtx (<MODE>mode);
1fd4e8c1 2608
4ae234b0
GK		 2609 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2610 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2611 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
85644414 2612 DONE;
1fd4e8c1
RK		 2613}")
2614
2615(define_insn ""
4ae234b0
GK		 2616 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2617 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2618 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2bfcf297 2619 ""
4ae234b0 2620 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
943c15ed
DE		 2621 [(set_attr "type" "two")
2622 (set_attr "length" "8")])
1fd4e8c1
RK		 2623
2624(define_insn ""
9ebbca7d 2625 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2626 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2627 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2628 (const_int 0)))
4ae234b0 2629 (clobber (match_scratch:P 3 "=r,r"))]
2bfcf297 2630 ""
9ebbca7d 2631 "@
4ae234b0 2632 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
9ebbca7d 2633 #"
b19003d8 2634 [(set_attr "type" "compare")
c921bad8
AP		 2635 (set_attr "length" "8,12")
2636 (set_attr "cell_micro" "not")])
9ebbca7d
GK		 2637
2638(define_split
2639 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2640 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2641 (match_operand:GPR 2 "exact_log2_cint_operand"
2642 ""))
9ebbca7d 2643 (const_int 0)))
4ae234b0 2644 (clobber (match_scratch:GPR 3 ""))]
2bfcf297 2645 "reload_completed"
9ebbca7d 2646 [(set (match_dup 3)
4ae234b0 2647 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2648 (set (match_dup 0)
2649 (compare:CC (match_dup 3)
2650 (const_int 0)))]
2651 "")
1fd4e8c1
RK		 2652
2653(define_insn ""
9ebbca7d 2654 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2655 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2656 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2657 (const_int 0)))
4ae234b0
GK		 2658 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2659 (div:P (match_dup 1) (match_dup 2)))]
2bfcf297 2660 ""
9ebbca7d 2661 "@
4ae234b0 2662 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
9ebbca7d 2663 #"
b19003d8 2664 [(set_attr "type" "compare")
c921bad8
AP		 2665 (set_attr "length" "8,12")
2666 (set_attr "cell_micro" "not")])
9ebbca7d
GK		 2667
2668(define_split
2669 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2670 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2671 (match_operand:GPR 2 "exact_log2_cint_operand"
2672 ""))
9ebbca7d 2673 (const_int 0)))
4ae234b0
GK		 2674 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2675 (div:GPR (match_dup 1) (match_dup 2)))]
2bfcf297 2676 "reload_completed"
9ebbca7d 2677 [(set (match_dup 0)
4ae234b0 2678 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2679 (set (match_dup 3)
2680 (compare:CC (match_dup 0)
2681 (const_int 0)))]
2682 "")
1fd4e8c1
RK		 2683
2684(define_insn ""
cd2b37d9 2685 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 2686 (udiv:SI
996a5f59 2687 (plus:DI (ashift:DI
cd2b37d9 2688 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 2689 (const_int 32))
23a900dc 2690 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
cd2b37d9 2691 (match_operand:SI 3 "gpc_reg_operand" "r")))
740ab4a2 2692 (set (match_operand:SI 2 "register_operand" "=*q")
1fd4e8c1 2693 (umod:SI
996a5f59 2694 (plus:DI (ashift:DI
1fd4e8c1 2695 (zero_extend:DI (match_dup 1)) (const_int 32))
740ab4a2 2696 (zero_extend:DI (match_dup 4)))
1fd4e8c1 2697 (match_dup 3)))]
ca7f5001 2698 "TARGET_POWER"
cfb557c4
RK		 2699 "div %0,%1,%3"
2700 [(set_attr "type" "idiv")])
1fd4e8c1
RK		 2701
2702;; To do unsigned divide we handle the cases of the divisor looking like a
2703;; negative number. If it is a constant that is less than 2**31, we don't
2704;; have to worry about the branches. So make a few subroutines here.
2705;;
2706;; First comes the normal case.
2707(define_expand "udivmodsi4_normal"
2708 [(set (match_dup 4) (const_int 0))
2709 (parallel [(set (match_operand:SI 0 "" "")
996a5f59 2710 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2711 (const_int 32))
2712 (zero_extend:DI (match_operand:SI 1 "" "")))
2713 (match_operand:SI 2 "" "")))
2714 (set (match_operand:SI 3 "" "")
996a5f59 2715 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2716 (const_int 32))
2717 (zero_extend:DI (match_dup 1)))
2718 (match_dup 2)))])]
ca7f5001 2719 "TARGET_POWER"
1fd4e8c1
RK		 2720 "
2721{ operands[4] = gen_reg_rtx (SImode); }")
2722
2723;; This handles the branches.
2724(define_expand "udivmodsi4_tests"
2725 [(set (match_operand:SI 0 "" "") (const_int 0))
2726 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2727 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2728 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2729 (label_ref (match_operand:SI 4 "" "")) (pc)))
2730 (set (match_dup 0) (const_int 1))
2731 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2732 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2733 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2734 (label_ref (match_dup 4)) (pc)))]
ca7f5001 2735 "TARGET_POWER"
1fd4e8c1
RK		 2736 "
2737{ operands[5] = gen_reg_rtx (CCUNSmode);
2738 operands[6] = gen_reg_rtx (CCmode);
2739}")
2740
2741(define_expand "udivmodsi4"
cd2b37d9
RK		 2742 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2743 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 2744 (match_operand:SI 2 "reg_or_cint_operand" "")))
cd2b37d9 2745 (set (match_operand:SI 3 "gpc_reg_operand" "")
1fd4e8c1 2746 (umod:SI (match_dup 1) (match_dup 2)))])]
8ffd9c51 2747 ""
1fd4e8c1
RK		 2748 "
2749{
2750 rtx label = 0;
2751
8ffd9c51 2752 if (! TARGET_POWER)
c4d38ccb
MM		 2753 {
2754 if (! TARGET_POWERPC)
2755 {
39403d82
DE		 2756 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2757 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
c4d38ccb 2758 emit_insn (gen_divus_call ());
39403d82
DE		 2759 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2760 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
c4d38ccb
MM		 2761 DONE;
2762 }
2763 else
2764 FAIL;
2765 }
0081a354 2766
1fd4e8c1
RK		 2767 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2768 {
2769 operands[2] = force_reg (SImode, operands[2]);
2770 label = gen_label_rtx ();
2771 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2772 operands[3], label));
2773 }
2774 else
2775 operands[2] = force_reg (SImode, operands[2]);
2776
2777 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2778 operands[3]));
2779 if (label)
2780 emit_label (label);
2781
2782 DONE;
2783}")
0081a354 2784
fada905b
MM		 2785;; AIX architecture-independent common-mode multiply (DImode),
2786;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2787;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2788;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2789;; assumed unused if generating common-mode, so ignore.
2790(define_insn "mulh_call"
2791 [(set (reg:SI 3)
2792 (truncate:SI
2793 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2794 (sign_extend:DI (reg:SI 4)))
2795 (const_int 32))))
1de43f85 2796 (clobber (reg:SI LR_REGNO))]
fada905b 2797 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2798 "bla __mulh"
2799 [(set_attr "type" "imul")])
fada905b
MM		 2800
2801(define_insn "mull_call"
2802 [(set (reg:DI 3)
2803 (mult:DI (sign_extend:DI (reg:SI 3))
2804 (sign_extend:DI (reg:SI 4))))
1de43f85 2805 (clobber (reg:SI LR_REGNO))
fada905b
MM		 2806 (clobber (reg:SI 0))]
2807 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2808 "bla __mull"
2809 [(set_attr "type" "imul")])
fada905b
MM		 2810
2811(define_insn "divss_call"
2812 [(set (reg:SI 3)
2813 (div:SI (reg:SI 3) (reg:SI 4)))
2814 (set (reg:SI 4)
2815 (mod:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2816 (clobber (reg:SI LR_REGNO))
fada905b
MM		 2817 (clobber (reg:SI 0))]
2818 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2819 "bla __divss"
2820 [(set_attr "type" "idiv")])
fada905b
MM		 2821
2822(define_insn "divus_call"
8ffd9c51
RK		 2823 [(set (reg:SI 3)
2824 (udiv:SI (reg:SI 3) (reg:SI 4)))
2825 (set (reg:SI 4)
2826 (umod:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2827 (clobber (reg:SI LR_REGNO))
fada905b 2828 (clobber (reg:SI 0))
e65a3857 2829 (clobber (match_scratch:CC 0 "=x"))
1de43f85 2830 (clobber (reg:CC CR1_REGNO))]
fada905b 2831 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2832 "bla __divus"
2833 [(set_attr "type" "idiv")])
fada905b
MM		 2834
2835(define_insn "quoss_call"
2836 [(set (reg:SI 3)
2837 (div:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2838 (clobber (reg:SI LR_REGNO))]
8ffd9c51 2839 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2840 "bla __quoss"
2841 [(set_attr "type" "idiv")])
0081a354 2842
fada905b
MM		 2843(define_insn "quous_call"
2844 [(set (reg:SI 3)
2845 (udiv:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2846 (clobber (reg:SI LR_REGNO))
fada905b 2847 (clobber (reg:SI 0))
e65a3857 2848 (clobber (match_scratch:CC 0 "=x"))
1de43f85 2849 (clobber (reg:CC CR1_REGNO))]
fada905b 2850 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2851 "bla __quous"
2852 [(set_attr "type" "idiv")])
8ffd9c51 2853\f
bb21487f 2854;; Logical instructions
dfbdccdb
GK		 2855;; The logical instructions are mostly combined by using match_operator,
2856;; but the plain AND insns are somewhat different because there is no
2857;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2858;; those rotate-and-mask operations. Thus, the AND insns come first.
2859
c921bad8
AP		 2860(define_expand "andsi3"
2861 [(parallel
2862 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2863 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2864 (match_operand:SI 2 "and_operand" "")))
2865 (clobber (match_scratch:CC 3 ""))])]
2866 ""
2867 "")
2868
2869(define_insn "andsi3_mc"
29ae5b89
JL		 2870 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2871 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
5f59ecb7 2872 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
29ae5b89 2873 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
c921bad8 2874 "rs6000_gen_cell_microcode"
1fd4e8c1
RK		 2875 "@
2876 and %0,%1,%2
ca7f5001
RK		 2877 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2878 {andil.|andi.} %0,%1,%b2
520308bc 2879 {andiu.|andis.} %0,%1,%u2"
cacf1ca8 2880 [(set_attr "type" "*,*,fast_compare,fast_compare")])
52d3af72 2881
c921bad8
AP		 2882(define_insn "andsi3_nomc"
2883 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2884 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2885 (match_operand:SI 2 "and_operand" "?r,T")))
2886 (clobber (match_scratch:CC 3 "=X,X"))]
2887 "!rs6000_gen_cell_microcode"
2888 "@
2889 and %0,%1,%2
2890 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
2891
2892(define_insn "andsi3_internal0_nomc"
2893 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2894 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2895 (match_operand:SI 2 "and_operand" "?r,T")))]
2896 "!rs6000_gen_cell_microcode"
2897 "@
2898 and %0,%1,%2
2899 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
2900
2901
52d3af72 2902;; Note to set cr's other than cr0 we do the and immediate and then
0ba1b2ff 2903;; the test again -- this avoids a mfcr which on the higher end
52d3af72 2904;; machines causes an execution serialization
1fd4e8c1 2905
c921bad8 2906(define_insn "*andsi3_internal2_mc"
52d3af72
DE		 2907 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2908 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2909 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
1fd4e8c1 2910 (const_int 0)))
52d3af72
DE		 2911 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2912 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
c921bad8 2913 "TARGET_32BIT && rs6000_gen_cell_microcode"
1fd4e8c1
RK		 2914 "@
2915 and. %3,%1,%2
ca7f5001
RK		 2916 {andil.|andi.} %3,%1,%b2
2917 {andiu.|andis.} %3,%1,%u2
52d3af72
DE		 2918 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2919 #
2920 #
2921 #
2922 #"
cacf1ca8
MM		 2923 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
2924 compare,compare,compare,compare")
52d3af72 2925 (set_attr "length" "4,4,4,4,8,8,8,8")])
1fd4e8c1 2926
c921bad8 2927(define_insn "*andsi3_internal3_mc"
0ba1b2ff
AM		 2928 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2929 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2930 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2931 (const_int 0)))
2932 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2933 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
c921bad8 2934 "TARGET_64BIT && rs6000_gen_cell_microcode"
0ba1b2ff
AM		 2935 "@
2936 #
2937 {andil.|andi.} %3,%1,%b2
2938 {andiu.|andis.} %3,%1,%u2
2939 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2940 #
2941 #
2942 #
2943 #"
cacf1ca8
MM		 2944 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
2945 compare,compare,compare")
0ba1b2ff
AM		 2946 (set_attr "length" "8,4,4,4,8,8,8,8")])
2947
52d3af72 2948(define_split
c921bad8 2949 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4ae234b0
GK		 2950 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2951 (match_operand:GPR 2 "and_operand" ""))
1fd4e8c1 2952 (const_int 0)))
4ae234b0 2953 (clobber (match_scratch:GPR 3 ""))
52d3af72 2954 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2955 "reload_completed"
52d3af72 2956 [(parallel [(set (match_dup 3)
4ae234b0
GK		 2957 (and:<MODE> (match_dup 1)
2958 (match_dup 2)))
52d3af72
DE		 2959 (clobber (match_dup 4))])
2960 (set (match_dup 0)
2961 (compare:CC (match_dup 3)
2962 (const_int 0)))]
2963 "")
2964
0ba1b2ff
AM		 2965;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2966;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2967
2968(define_split
2969 [(set (match_operand:CC 0 "cc_reg_operand" "")
2970 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2971 (match_operand:SI 2 "gpc_reg_operand" ""))
2972 (const_int 0)))
2973 (clobber (match_scratch:SI 3 ""))
2974 (clobber (match_scratch:CC 4 ""))]
2975 "TARGET_POWERPC64 && reload_completed"
2976 [(parallel [(set (match_dup 3)
2977 (and:SI (match_dup 1)
2978 (match_dup 2)))
2979 (clobber (match_dup 4))])
2980 (set (match_dup 0)
2981 (compare:CC (match_dup 3)
2982 (const_int 0)))]
2983 "")
2984
2985(define_insn "*andsi3_internal4"
52d3af72
DE		 2986 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2987 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2988 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
52d3af72
DE		 2989 (const_int 0)))
2990 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2991 (and:SI (match_dup 1)
2992 (match_dup 2)))
2993 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
c921bad8 2994 "TARGET_32BIT && rs6000_gen_cell_microcode"
1fd4e8c1
RK		 2995 "@
2996 and. %0,%1,%2
ca7f5001
RK		 2997 {andil.|andi.} %0,%1,%b2
2998 {andiu.|andis.} %0,%1,%u2
52d3af72
DE		 2999 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3000 #
3001 #
3002 #
3003 #"
cacf1ca8
MM		 3004 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3005 compare,compare,compare,compare")
52d3af72
DE		 3006 (set_attr "length" "4,4,4,4,8,8,8,8")])
3007
c921bad8 3008(define_insn "*andsi3_internal5_mc"
0ba1b2ff
AM		 3009 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3010 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3011 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3012 (const_int 0)))
3013 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3014 (and:SI (match_dup 1)
3015 (match_dup 2)))
3016 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
c921bad8 3017 "TARGET_64BIT && rs6000_gen_cell_microcode"
0ba1b2ff
AM		 3018 "@
3019 #
3020 {andil.|andi.} %0,%1,%b2
3021 {andiu.|andis.} %0,%1,%u2
3022 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3023 #
3024 #
3025 #
3026 #"
cacf1ca8
MM		 3027 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3028 compare,compare,compare")
0ba1b2ff
AM		 3029 (set_attr "length" "8,4,4,4,8,8,8,8")])
3030
52d3af72 3031(define_split
c921bad8 3032 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
52d3af72
DE		 3033 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3034 (match_operand:SI 2 "and_operand" ""))
3035 (const_int 0)))
3036 (set (match_operand:SI 0 "gpc_reg_operand" "")
3037 (and:SI (match_dup 1)
3038 (match_dup 2)))
3039 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 3040 "reload_completed"
52d3af72
DE		 3041 [(parallel [(set (match_dup 0)
3042 (and:SI (match_dup 1)
3043 (match_dup 2)))
3044 (clobber (match_dup 4))])
3045 (set (match_dup 3)
3046 (compare:CC (match_dup 0)
3047 (const_int 0)))]
3048 "")
1fd4e8c1 3049
0ba1b2ff
AM		 3050(define_split
3051 [(set (match_operand:CC 3 "cc_reg_operand" "")
3052 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3053 (match_operand:SI 2 "gpc_reg_operand" ""))
3054 (const_int 0)))
3055 (set (match_operand:SI 0 "gpc_reg_operand" "")
3056 (and:SI (match_dup 1)
3057 (match_dup 2)))
3058 (clobber (match_scratch:CC 4 ""))]
3059 "TARGET_POWERPC64 && reload_completed"
3060 [(parallel [(set (match_dup 0)
3061 (and:SI (match_dup 1)
3062 (match_dup 2)))
3063 (clobber (match_dup 4))])
3064 (set (match_dup 3)
3065 (compare:CC (match_dup 0)
3066 (const_int 0)))]
3067 "")
3068
3069;; Handle the PowerPC64 rlwinm corner case
3070
3071(define_insn_and_split "*andsi3_internal6"
3072 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3073 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3074 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3075 "TARGET_POWERPC64"
3076 "#"
3077 "TARGET_POWERPC64"
3078 [(set (match_dup 0)
3079 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3080 (match_dup 4)))
3081 (set (match_dup 0)
3082 (rotate:SI (match_dup 0) (match_dup 5)))]
3083 "
3084{
3085 int mb = extract_MB (operands[2]);
3086 int me = extract_ME (operands[2]);
3087 operands[3] = GEN_INT (me + 1);
3088 operands[5] = GEN_INT (32 - (me + 1));
3089 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3090}"
3091 [(set_attr "length" "8")])
3092
7cd5235b 3093(define_expand "iorsi3"
cd2b37d9 3094 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 3095 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 3096 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
7cd5235b 3097 ""
f357808b
RK		 3098 "
3099{
7cd5235b 3100 if (GET_CODE (operands[2]) == CONST_INT
677a9668 3101 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 3102 {
3103 HOST_WIDE_INT value = INTVAL (operands[2]);
b3a13419
ILT		 3104 rtx tmp = ((!can_create_pseudo_p ()
3105 || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 3106 ? operands[0] : gen_reg_rtx (SImode));
3107
a260abc9
DE		 3108 emit_insn (gen_iorsi3 (tmp, operands[1],
3109 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3110 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 3111 DONE;
3112 }
f357808b
RK		 3113}")
3114
7cd5235b 3115(define_expand "xorsi3"
cd2b37d9 3116 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 3117 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 3118 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
1fd4e8c1 3119 ""
7cd5235b 3120 "
1fd4e8c1 3121{
7cd5235b 3122 if (GET_CODE (operands[2]) == CONST_INT
677a9668 3123 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 3124 {
3125 HOST_WIDE_INT value = INTVAL (operands[2]);
b3a13419
ILT		 3126 rtx tmp = ((!can_create_pseudo_p ()
3127 || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 3128 ? operands[0] : gen_reg_rtx (SImode));
3129
a260abc9
DE		 3130 emit_insn (gen_xorsi3 (tmp, operands[1],
3131 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3132 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 3133 DONE;
3134 }
1fd4e8c1
RK		 3135}")
3136
dfbdccdb 3137(define_insn "*boolsi3_internal1"
7cd5235b 3138 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 3139 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3140 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3141 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
1fd4e8c1
RK		 3142 ""
3143 "@
dfbdccdb
GK		 3144 %q3 %0,%1,%2
3145 {%q3il|%q3i} %0,%1,%b2
3146 {%q3iu|%q3is} %0,%1,%u2")
1fd4e8c1 3147
dfbdccdb 3148(define_insn "*boolsi3_internal2"
52d3af72 3149 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 3150 (compare:CC (match_operator:SI 4 "boolean_or_operator"
dfbdccdb
GK		 3151 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3152 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3153 (const_int 0)))
52d3af72 3154 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3155 "TARGET_32BIT"
52d3af72 3156 "@
dfbdccdb 3157 %q4. %3,%1,%2
52d3af72 3158 #"
cacf1ca8 3159 [(set_attr "type" "fast_compare,compare")
52d3af72
DE		 3160 (set_attr "length" "4,8")])
3161
3162(define_split
c921bad8 3163 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 3164 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3165 [(match_operand:SI 1 "gpc_reg_operand" "")
3166 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3167 (const_int 0)))
52d3af72 3168 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3169 "TARGET_32BIT && reload_completed"
dfbdccdb 3170 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3171 (set (match_dup 0)
3172 (compare:CC (match_dup 3)
3173 (const_int 0)))]
3174 "")
815cdc52 3175
dfbdccdb 3176(define_insn "*boolsi3_internal3"
52d3af72 3177 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3178 (compare:CC (match_operator:SI 4 "boolean_operator"
3179 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3180 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3181 (const_int 0)))
52d3af72 3182 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3183 (match_dup 4))]
4b8a63d6 3184 "TARGET_32BIT"
52d3af72 3185 "@
dfbdccdb 3186 %q4. %0,%1,%2
52d3af72 3187 #"
cacf1ca8 3188 [(set_attr "type" "fast_compare,compare")
52d3af72
DE		 3189 (set_attr "length" "4,8")])
3190
3191(define_split
c921bad8 3192 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 3193 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3194 [(match_operand:SI 1 "gpc_reg_operand" "")
3195 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3196 (const_int 0)))
75540af0 3197 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3198 (match_dup 4))]
4b8a63d6 3199 "TARGET_32BIT && reload_completed"
dfbdccdb 3200 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3201 (set (match_dup 3)
3202 (compare:CC (match_dup 0)
3203 (const_int 0)))]
3204 "")
1fd4e8c1 3205
6ae08853 3206;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 3207;; each of which does one 16-bit part. This is used by combine.
a260abc9
DE		 3208
3209(define_split
3210 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1d328b19 3211 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3212 [(match_operand:SI 1 "gpc_reg_operand" "")
3213 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
a260abc9 3214 ""
dfbdccdb
GK		 3215 [(set (match_dup 0) (match_dup 4))
3216 (set (match_dup 0) (match_dup 5))]
a260abc9
DE		 3217"
3218{
dfbdccdb
GK		 3219 rtx i;
3220 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
1c563bed 3221 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3222 operands[1], i);
dfbdccdb 3223 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
1c563bed 3224 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3225 operands[0], i);
a260abc9
DE		 3226}")
3227
dfbdccdb 3228(define_insn "*boolcsi3_internal1"
cd2b37d9 3229 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3230 (match_operator:SI 3 "boolean_operator"
3231 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3232 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
1fd4e8c1 3233 ""
dfbdccdb 3234 "%q3 %0,%2,%1")
1fd4e8c1 3235
dfbdccdb 3236(define_insn "*boolcsi3_internal2"
52d3af72 3237 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3238 (compare:CC (match_operator:SI 4 "boolean_operator"
3239 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3240 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3241 (const_int 0)))
52d3af72 3242 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3243 "TARGET_32BIT"
52d3af72 3244 "@
dfbdccdb 3245 %q4. %3,%2,%1
52d3af72
DE		 3246 #"
3247 [(set_attr "type" "compare")
3248 (set_attr "length" "4,8")])
3249
3250(define_split
c921bad8 3251 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 3252 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3253 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3254 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3255 (const_int 0)))
52d3af72 3256 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3257 "TARGET_32BIT && reload_completed"
dfbdccdb 3258 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3259 (set (match_dup 0)
3260 (compare:CC (match_dup 3)
3261 (const_int 0)))]
3262 "")
1fd4e8c1 3263
dfbdccdb 3264(define_insn "*boolcsi3_internal3"
52d3af72 3265 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3266 (compare:CC (match_operator:SI 4 "boolean_operator"
3267 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3268 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3269 (const_int 0)))
52d3af72 3270 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3271 (match_dup 4))]
4b8a63d6 3272 "TARGET_32BIT"
52d3af72 3273 "@
dfbdccdb 3274 %q4. %0,%2,%1
52d3af72
DE		 3275 #"
3276 [(set_attr "type" "compare")
3277 (set_attr "length" "4,8")])
3278
3279(define_split
c921bad8 3280 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 3281 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3282 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3283 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3284 (const_int 0)))
75540af0 3285 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3286 (match_dup 4))]
4b8a63d6 3287 "TARGET_32BIT && reload_completed"
dfbdccdb 3288 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3289 (set (match_dup 3)
3290 (compare:CC (match_dup 0)
3291 (const_int 0)))]
3292 "")
3293
dfbdccdb 3294(define_insn "*boolccsi3_internal1"
cd2b37d9 3295 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3296 (match_operator:SI 3 "boolean_operator"
3297 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3298 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
1fd4e8c1 3299 ""
dfbdccdb 3300 "%q3 %0,%1,%2")
1fd4e8c1 3301
dfbdccdb 3302(define_insn "*boolccsi3_internal2"
52d3af72 3303 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3304 (compare:CC (match_operator:SI 4 "boolean_operator"
3305 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3306 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3307 (const_int 0)))
52d3af72 3308 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3309 "TARGET_32BIT"
52d3af72 3310 "@
dfbdccdb 3311 %q4. %3,%1,%2
52d3af72 3312 #"
cacf1ca8 3313 [(set_attr "type" "fast_compare,compare")
52d3af72
DE		 3314 (set_attr "length" "4,8")])
3315
3316(define_split
c921bad8 3317 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 3318 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3319 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3320 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3321 (const_int 0)))
52d3af72 3322 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3323 "TARGET_32BIT && reload_completed"
dfbdccdb 3324 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3325 (set (match_dup 0)
3326 (compare:CC (match_dup 3)
3327 (const_int 0)))]
3328 "")
1fd4e8c1 3329
dfbdccdb 3330(define_insn "*boolccsi3_internal3"
52d3af72 3331 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3332 (compare:CC (match_operator:SI 4 "boolean_operator"
3333 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3334 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3335 (const_int 0)))
52d3af72 3336 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3337 (match_dup 4))]
4b8a63d6 3338 "TARGET_32BIT"
52d3af72 3339 "@
dfbdccdb 3340 %q4. %0,%1,%2
52d3af72 3341 #"
cacf1ca8 3342 [(set_attr "type" "fast_compare,compare")
52d3af72
DE		 3343 (set_attr "length" "4,8")])
3344
3345(define_split
c921bad8 3346 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 3347 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3348 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3349 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3350 (const_int 0)))
75540af0 3351 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3352 (match_dup 4))]
4b8a63d6 3353 "TARGET_32BIT && reload_completed"
dfbdccdb 3354 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3355 (set (match_dup 3)
3356 (compare:CC (match_dup 0)
3357 (const_int 0)))]
3358 "")
1fd4e8c1
RK		 3359
3360;; maskir insn. We need four forms because things might be in arbitrary
3361;; orders. Don't define forms that only set CR fields because these
3362;; would modify an input register.
3363
7cd5235b 3364(define_insn "*maskir_internal1"
cd2b37d9 3365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3366 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3367 (match_operand:SI 1 "gpc_reg_operand" "0"))
3368 (and:SI (match_dup 2)
cd2b37d9 3369 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
ca7f5001 3370 "TARGET_POWER"
01def764 3371 "maskir %0,%3,%2")
1fd4e8c1 3372
7cd5235b 3373(define_insn "*maskir_internal2"
242e8072 3374 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3375 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3376 (match_operand:SI 1 "gpc_reg_operand" "0"))
cd2b37d9 3377 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764 3378 (match_dup 2))))]
ca7f5001 3379 "TARGET_POWER"
01def764 3380 "maskir %0,%3,%2")
1fd4e8c1 3381
7cd5235b 3382(define_insn "*maskir_internal3"
cd2b37d9 3383 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764 3384 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
cd2b37d9 3385 (match_operand:SI 3 "gpc_reg_operand" "r"))
01def764
RK		 3386 (and:SI (not:SI (match_dup 2))
3387 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3388 "TARGET_POWER"
01def764 3389 "maskir %0,%3,%2")
1fd4e8c1 3390
7cd5235b 3391(define_insn "*maskir_internal4"
cd2b37d9
RK		 3392 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3393 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764
RK		 3394 (match_operand:SI 2 "gpc_reg_operand" "r"))
3395 (and:SI (not:SI (match_dup 2))
3396 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3397 "TARGET_POWER"
01def764 3398 "maskir %0,%3,%2")
1fd4e8c1 3399
7cd5235b 3400(define_insn "*maskir_internal5"
9ebbca7d 3401 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3402 (compare:CC
9ebbca7d
GK		 3403 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3404 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
01def764 3405 (and:SI (match_dup 2)
9ebbca7d 3406 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1fd4e8c1 3407 (const_int 0)))
9ebbca7d 3408 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3409 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3410 (and:SI (match_dup 2) (match_dup 3))))]
ca7f5001 3411 "TARGET_POWER"
9ebbca7d
GK		 3412 "@
3413 maskir. %0,%3,%2
3414 #"
3415 [(set_attr "type" "compare")
3416 (set_attr "length" "4,8")])
3417
3418(define_split
3419 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3420 (compare:CC
3421 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3422 (match_operand:SI 1 "gpc_reg_operand" ""))
3423 (and:SI (match_dup 2)
3424 (match_operand:SI 3 "gpc_reg_operand" "")))
3425 (const_int 0)))
3426 (set (match_operand:SI 0 "gpc_reg_operand" "")
3427 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3428 (and:SI (match_dup 2) (match_dup 3))))]
3429 "TARGET_POWER && reload_completed"
3430 [(set (match_dup 0)
3431 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3432 (and:SI (match_dup 2) (match_dup 3))))
3433 (set (match_dup 4)
3434 (compare:CC (match_dup 0)
3435 (const_int 0)))]
3436 "")
1fd4e8c1 3437
7cd5235b 3438(define_insn "*maskir_internal6"
9ebbca7d 3439 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3440 (compare:CC
9ebbca7d
GK		 3441 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3442 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3443 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
01def764 3444 (match_dup 2)))
1fd4e8c1 3445 (const_int 0)))
9ebbca7d 3446 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3447 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3448 (and:SI (match_dup 3) (match_dup 2))))]
ca7f5001 3449 "TARGET_POWER"
9ebbca7d
GK		 3450 "@
3451 maskir. %0,%3,%2
3452 #"
3453 [(set_attr "type" "compare")
3454 (set_attr "length" "4,8")])
3455
3456(define_split
3457 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3458 (compare:CC
3459 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3460 (match_operand:SI 1 "gpc_reg_operand" ""))
3461 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3462 (match_dup 2)))
3463 (const_int 0)))
3464 (set (match_operand:SI 0 "gpc_reg_operand" "")
3465 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3466 (and:SI (match_dup 3) (match_dup 2))))]
3467 "TARGET_POWER && reload_completed"
3468 [(set (match_dup 0)
3469 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3470 (and:SI (match_dup 3) (match_dup 2))))
3471 (set (match_dup 4)
3472 (compare:CC (match_dup 0)
3473 (const_int 0)))]
3474 "")
1fd4e8c1 3475
7cd5235b 3476(define_insn "*maskir_internal7"
9ebbca7d 3477 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
815cdc52 3478 (compare:CC
9ebbca7d
GK		 3479 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3480 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
815cdc52 3481 (and:SI (not:SI (match_dup 2))
9ebbca7d 3482 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
815cdc52 3483 (const_int 0)))
9ebbca7d 3484 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 3485 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3486 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3487 "TARGET_POWER"
9ebbca7d
GK		 3488 "@
3489 maskir. %0,%3,%2
3490 #"
3491 [(set_attr "type" "compare")
3492 (set_attr "length" "4,8")])
3493
3494(define_split
3495 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3496 (compare:CC
3497 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3498 (match_operand:SI 3 "gpc_reg_operand" ""))
3499 (and:SI (not:SI (match_dup 2))
3500 (match_operand:SI 1 "gpc_reg_operand" "")))
3501 (const_int 0)))
3502 (set (match_operand:SI 0 "gpc_reg_operand" "")
3503 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3504 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3505 "TARGET_POWER && reload_completed"
3506 [(set (match_dup 0)
3507 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3508 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3509 (set (match_dup 4)
3510 (compare:CC (match_dup 0)
3511 (const_int 0)))]
3512 "")
1fd4e8c1 3513
7cd5235b 3514(define_insn "*maskir_internal8"
9ebbca7d 3515 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3516 (compare:CC
9ebbca7d
GK		 3517 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3518 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
01def764 3519 (and:SI (not:SI (match_dup 2))
9ebbca7d 3520 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
1fd4e8c1 3521 (const_int 0)))
9ebbca7d 3522 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3523 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3524 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
ca7f5001 3525 "TARGET_POWER"
9ebbca7d
GK		 3526 "@
3527 maskir. %0,%3,%2
3528 #"
3529 [(set_attr "type" "compare")
3530 (set_attr "length" "4,8")])
fcce224d 3531
9ebbca7d
GK		 3532(define_split
3533 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3534 (compare:CC
3535 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3536 (match_operand:SI 2 "gpc_reg_operand" ""))
3537 (and:SI (not:SI (match_dup 2))
3538 (match_operand:SI 1 "gpc_reg_operand" "")))
3539 (const_int 0)))
3540 (set (match_operand:SI 0 "gpc_reg_operand" "")
3541 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3542 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3543 "TARGET_POWER && reload_completed"
3544 [(set (match_dup 0)
3545 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3546 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3547 (set (match_dup 4)
3548 (compare:CC (match_dup 0)
3549 (const_int 0)))]
3550 "")
fcce224d 3551\f
1fd4e8c1
RK		 3552;; Rotate and shift insns, in all their variants. These support shifts,
3553;; field inserts and extracts, and various combinations thereof.
034c1be0 3554(define_expand "insv"
0ad91047
DE		 3555 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3556 (match_operand:SI 1 "const_int_operand" "")
3557 (match_operand:SI 2 "const_int_operand" ""))
3558 (match_operand 3 "gpc_reg_operand" ""))]
034c1be0
MM		 3559 ""
3560 "
3561{
3562 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3563 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
14502dad
JM		 3564 compiler if the address of the structure is taken later. Likewise, do
3565 not handle invalid E500 subregs. */
034c1be0 3566 if (GET_CODE (operands[0]) == SUBREG
14502dad
JM		 3567 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3568 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3569 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
034c1be0 3570 FAIL;
a78e33fc
DE		 3571
3572 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3573 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3574 else
3575 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3576 DONE;
034c1be0
MM		 3577}")
3578
a78e33fc 3579(define_insn "insvsi"
cd2b37d9 3580 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1
RK		 3581 (match_operand:SI 1 "const_int_operand" "i")
3582 (match_operand:SI 2 "const_int_operand" "i"))
cd2b37d9 3583 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1fd4e8c1
RK		 3584 ""
3585 "*
3586{
3587 int start = INTVAL (operands[2]) & 31;
3588 int size = INTVAL (operands[1]) & 31;
3589
89e9f3a8
MM		 3590 operands[4] = GEN_INT (32 - start - size);
3591 operands[1] = GEN_INT (start + size - 1);
a66078ee 3592 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3593}"
3594 [(set_attr "type" "insert_word")])
1fd4e8c1 3595
a78e33fc 3596(define_insn "*insvsi_internal1"
d56d506a
RK		 3597 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3598 (match_operand:SI 1 "const_int_operand" "i")
3599 (match_operand:SI 2 "const_int_operand" "i"))
6d0a8091 3600 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
d56d506a 3601 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3602 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3603 "*
3604{
3605 int shift = INTVAL (operands[4]) & 31;
3606 int start = INTVAL (operands[2]) & 31;
3607 int size = INTVAL (operands[1]) & 31;
3608
89e9f3a8 3609 operands[4] = GEN_INT (shift - start - size);
6d0a8091 3610 operands[1] = GEN_INT (start + size - 1);
a66078ee 3611 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3612}"
3613 [(set_attr "type" "insert_word")])
d56d506a 3614
a78e33fc 3615(define_insn "*insvsi_internal2"
d56d506a
RK		 3616 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3617 (match_operand:SI 1 "const_int_operand" "i")
3618 (match_operand:SI 2 "const_int_operand" "i"))
3619 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3620 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3621 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3622 "*
3623{
3624 int shift = INTVAL (operands[4]) & 31;
3625 int start = INTVAL (operands[2]) & 31;
3626 int size = INTVAL (operands[1]) & 31;
3627
89e9f3a8
MM		 3628 operands[4] = GEN_INT (32 - shift - start - size);
3629 operands[1] = GEN_INT (start + size - 1);
a66078ee 3630 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3631}"
3632 [(set_attr "type" "insert_word")])
d56d506a 3633
a78e33fc 3634(define_insn "*insvsi_internal3"
d56d506a
RK		 3635 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3636 (match_operand:SI 1 "const_int_operand" "i")
3637 (match_operand:SI 2 "const_int_operand" "i"))
3638 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3639 (match_operand:SI 4 "const_int_operand" "i")))]
95e8f2f3 3640 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3641 "*
3642{
3643 int shift = INTVAL (operands[4]) & 31;
3644 int start = INTVAL (operands[2]) & 31;
3645 int size = INTVAL (operands[1]) & 31;
3646
89e9f3a8
MM		 3647 operands[4] = GEN_INT (32 - shift - start - size);
3648 operands[1] = GEN_INT (start + size - 1);
a66078ee 3649 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3650}"
3651 [(set_attr "type" "insert_word")])
d56d506a 3652
a78e33fc 3653(define_insn "*insvsi_internal4"
d56d506a
RK		 3654 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3655 (match_operand:SI 1 "const_int_operand" "i")
3656 (match_operand:SI 2 "const_int_operand" "i"))
3657 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3658 (match_operand:SI 4 "const_int_operand" "i")
3659 (match_operand:SI 5 "const_int_operand" "i")))]
3660 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3661 "*
3662{
3663 int extract_start = INTVAL (operands[5]) & 31;
3664 int extract_size = INTVAL (operands[4]) & 31;
3665 int insert_start = INTVAL (operands[2]) & 31;
3666 int insert_size = INTVAL (operands[1]) & 31;
3667
3668/* Align extract field with insert field */
3a598fbe 3669 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
89e9f3a8 3670 operands[1] = GEN_INT (insert_start + insert_size - 1);
a66078ee 3671 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
8e8238f1
DE		 3672}"
3673 [(set_attr "type" "insert_word")])
d56d506a 3674
f241bf89
EC		 3675;; combine patterns for rlwimi
3676(define_insn "*insvsi_internal5"
3677 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3678 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3679 (match_operand:SI 1 "mask_operand" "i"))
3680 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3681 (match_operand:SI 2 "const_int_operand" "i"))
3682 (match_operand:SI 5 "mask_operand" "i"))))]
3683 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3684 "*
3685{
3686 int me = extract_ME(operands[5]);
3687 int mb = extract_MB(operands[5]);
3688 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3689 operands[2] = GEN_INT(mb);
3690 operands[1] = GEN_INT(me);
3691 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3692}"
3693 [(set_attr "type" "insert_word")])
3694
3695(define_insn "*insvsi_internal6"
3696 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3697 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3698 (match_operand:SI 2 "const_int_operand" "i"))
3699 (match_operand:SI 5 "mask_operand" "i"))
3700 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3701 (match_operand:SI 1 "mask_operand" "i"))))]
3702 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3703 "*
3704{
3705 int me = extract_ME(operands[5]);
3706 int mb = extract_MB(operands[5]);
3707 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3708 operands[2] = GEN_INT(mb);
3709 operands[1] = GEN_INT(me);
3710 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3711}"
3712 [(set_attr "type" "insert_word")])
3713
a78e33fc 3714(define_insn "insvdi"
685f3906 3715 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
a78e33fc
DE		 3716 (match_operand:SI 1 "const_int_operand" "i")
3717 (match_operand:SI 2 "const_int_operand" "i"))
685f3906
DE		 3718 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3719 "TARGET_POWERPC64"
3720 "*
3721{
3722 int start = INTVAL (operands[2]) & 63;
3723 int size = INTVAL (operands[1]) & 63;
3724
a78e33fc
DE		 3725 operands[1] = GEN_INT (64 - start - size);
3726 return \"rldimi %0,%3,%H1,%H2\";
44cd321e
PS		 3727}"
3728 [(set_attr "type" "insert_dword")])
685f3906 3729
11ac38b2
DE		 3730(define_insn "*insvdi_internal2"
3731 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3732 (match_operand:SI 1 "const_int_operand" "i")
3733 (match_operand:SI 2 "const_int_operand" "i"))
3734 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3735 (match_operand:SI 4 "const_int_operand" "i")))]
3736 "TARGET_POWERPC64
3737 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3738 "*
3739{
3740 int shift = INTVAL (operands[4]) & 63;
3741 int start = (INTVAL (operands[2]) & 63) - 32;
3742 int size = INTVAL (operands[1]) & 63;
3743
3744 operands[4] = GEN_INT (64 - shift - start - size);
3745 operands[2] = GEN_INT (start);
3746 operands[1] = GEN_INT (start + size - 1);
3747 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3748}")
3749
3750(define_insn "*insvdi_internal3"
3751 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3752 (match_operand:SI 1 "const_int_operand" "i")
3753 (match_operand:SI 2 "const_int_operand" "i"))
3754 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3755 (match_operand:SI 4 "const_int_operand" "i")))]
3756 "TARGET_POWERPC64
3757 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3758 "*
3759{
3760 int shift = INTVAL (operands[4]) & 63;
3761 int start = (INTVAL (operands[2]) & 63) - 32;
3762 int size = INTVAL (operands[1]) & 63;
3763
3764 operands[4] = GEN_INT (64 - shift - start - size);
3765 operands[2] = GEN_INT (start);
3766 operands[1] = GEN_INT (start + size - 1);
3767 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3768}")
3769
034c1be0 3770(define_expand "extzv"
0ad91047
DE		 3771 [(set (match_operand 0 "gpc_reg_operand" "")
3772 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3773 (match_operand:SI 2 "const_int_operand" "")
3774 (match_operand:SI 3 "const_int_operand" "")))]
034c1be0
MM		 3775 ""
3776 "
3777{
3778 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3779 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3780 compiler if the address of the structure is taken later. */
3781 if (GET_CODE (operands[0]) == SUBREG
3782 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3783 FAIL;
a78e33fc
DE		 3784
3785 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3786 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3787 else
3788 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3789 DONE;
034c1be0
MM		 3790}")
3791
a78e33fc 3792(define_insn "extzvsi"
cd2b37d9
RK		 3793 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3794 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3795 (match_operand:SI 2 "const_int_operand" "i")
3796 (match_operand:SI 3 "const_int_operand" "i")))]
3797 ""
3798 "*
3799{
3800 int start = INTVAL (operands[3]) & 31;
3801 int size = INTVAL (operands[2]) & 31;
3802
3803 if (start + size >= 32)
3804 operands[3] = const0_rtx;
3805 else
89e9f3a8 3806 operands[3] = GEN_INT (start + size);
ca7f5001 3807 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
1fd4e8c1
RK		 3808}")
3809
a78e33fc 3810(define_insn "*extzvsi_internal1"
9ebbca7d
GK		 3811 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3812 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3813 (match_operand:SI 2 "const_int_operand" "i,i")
3814 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3815 (const_int 0)))
9ebbca7d 3816 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3817 ""
1fd4e8c1
RK		 3818 "*
3819{
3820 int start = INTVAL (operands[3]) & 31;
3821 int size = INTVAL (operands[2]) & 31;
3822
9ebbca7d
GK		 3823 /* Force split for non-cc0 compare. */
3824 if (which_alternative == 1)
3825 return \"#\";
3826
43a88a8c 3827 /* If the bit-field being tested fits in the upper or lower half of a
a7a975e1
RK		 3828 word, it is possible to use andiu. or andil. to test it. This is
3829 useful because the condition register set-use delay is smaller for
3830 andi[ul]. than for rlinm. This doesn't work when the starting bit
3831 position is 0 because the LT and GT bits may be set wrong. */
3832
3833 if ((start > 0 && start + size <= 16) || start >= 16)
df031c43 3834 {
3a598fbe 3835 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
df031c43
RK		 3836 - (1 << (16 - (start & 15) - size))));
3837 if (start < 16)
ca7f5001 3838 return \"{andiu.|andis.} %4,%1,%3\";
df031c43 3839 else
ca7f5001 3840 return \"{andil.|andi.} %4,%1,%3\";
df031c43 3841 }
7e69e155 3842
1fd4e8c1
RK		 3843 if (start + size >= 32)
3844 operands[3] = const0_rtx;
3845 else
89e9f3a8 3846 operands[3] = GEN_INT (start + size);
ca7f5001 3847 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
1fd4e8c1 3848}"
44cd321e 3849 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3850 (set_attr "length" "4,8")])
3851
3852(define_split
c921bad8 3853 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 3854 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3855 (match_operand:SI 2 "const_int_operand" "")
3856 (match_operand:SI 3 "const_int_operand" ""))
3857 (const_int 0)))
3858 (clobber (match_scratch:SI 4 ""))]
ce71f754 3859 "reload_completed"
9ebbca7d
GK		 3860 [(set (match_dup 4)
3861 (zero_extract:SI (match_dup 1) (match_dup 2)
3862 (match_dup 3)))
3863 (set (match_dup 0)
3864 (compare:CC (match_dup 4)
3865 (const_int 0)))]
3866 "")
1fd4e8c1 3867
a78e33fc 3868(define_insn "*extzvsi_internal2"
9ebbca7d
GK		 3869 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3870 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3871 (match_operand:SI 2 "const_int_operand" "i,i")
3872 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3873 (const_int 0)))
9ebbca7d 3874 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3875 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3876 ""
1fd4e8c1
RK		 3877 "*
3878{
3879 int start = INTVAL (operands[3]) & 31;
3880 int size = INTVAL (operands[2]) & 31;
3881
9ebbca7d
GK		 3882 /* Force split for non-cc0 compare. */
3883 if (which_alternative == 1)
3884 return \"#\";
3885
bc401279 3886 /* Since we are using the output value, we can't ignore any need for
43a88a8c 3887 a shift. The bit-field must end at the LSB. */
bc401279 3888 if (start >= 16 && start + size == 32)
df031c43 3889 {
bc401279
AM		 3890 operands[3] = GEN_INT ((1 << size) - 1);
3891 return \"{andil.|andi.} %0,%1,%3\";
df031c43 3892 }
7e69e155 3893
1fd4e8c1
RK		 3894 if (start + size >= 32)
3895 operands[3] = const0_rtx;
3896 else
89e9f3a8 3897 operands[3] = GEN_INT (start + size);
ca7f5001 3898 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
1fd4e8c1 3899}"
44cd321e 3900 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3901 (set_attr "length" "4,8")])
3902
3903(define_split
c921bad8 3904 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 3905 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3906 (match_operand:SI 2 "const_int_operand" "")
3907 (match_operand:SI 3 "const_int_operand" ""))
3908 (const_int 0)))
3909 (set (match_operand:SI 0 "gpc_reg_operand" "")
3910 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3911 "reload_completed"
9ebbca7d
GK		 3912 [(set (match_dup 0)
3913 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3914 (set (match_dup 4)
3915 (compare:CC (match_dup 0)
3916 (const_int 0)))]
3917 "")
1fd4e8c1 3918
a78e33fc 3919(define_insn "extzvdi"
685f3906
DE		 3920 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3921 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3922 (match_operand:SI 2 "const_int_operand" "i")
3923 (match_operand:SI 3 "const_int_operand" "i")))]
685f3906
DE		 3924 "TARGET_POWERPC64"
3925 "*
3926{
3927 int start = INTVAL (operands[3]) & 63;
3928 int size = INTVAL (operands[2]) & 63;
3929
3930 if (start + size >= 64)
3931 operands[3] = const0_rtx;
3932 else
89e9f3a8
MM		 3933 operands[3] = GEN_INT (start + size);
3934 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3935 return \"rldicl %0,%1,%3,%2\";
3936}")
3937
a78e33fc 3938(define_insn "*extzvdi_internal1"
29ae5b89
JL		 3939 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3940 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3941 (match_operand:SI 2 "const_int_operand" "i")
3942 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3943 (const_int 0)))
29ae5b89 3944 (clobber (match_scratch:DI 4 "=r"))]
c921bad8 3945 "TARGET_64BIT && rs6000_gen_cell_microcode"
685f3906
DE		 3946 "*
3947{
3948 int start = INTVAL (operands[3]) & 63;
3949 int size = INTVAL (operands[2]) & 63;
3950
3951 if (start + size >= 64)
3952 operands[3] = const0_rtx;
3953 else
89e9f3a8
MM		 3954 operands[3] = GEN_INT (start + size);
3955 operands[2] = GEN_INT (64 - size);
685f3906 3956 return \"rldicl. %4,%1,%3,%2\";
9a3c428b
DE		 3957}"
3958 [(set_attr "type" "compare")])
685f3906 3959
a78e33fc 3960(define_insn "*extzvdi_internal2"
29ae5b89
JL		 3961 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3962 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3963 (match_operand:SI 2 "const_int_operand" "i")
3964 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3965 (const_int 0)))
29ae5b89 3966 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
685f3906 3967 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
c921bad8 3968 "TARGET_64BIT && rs6000_gen_cell_microcode"
685f3906
DE		 3969 "*
3970{
3971 int start = INTVAL (operands[3]) & 63;
3972 int size = INTVAL (operands[2]) & 63;
3973
3974 if (start + size >= 64)
3975 operands[3] = const0_rtx;
3976 else
89e9f3a8
MM		 3977 operands[3] = GEN_INT (start + size);
3978 operands[2] = GEN_INT (64 - size);
685f3906 3979 return \"rldicl. %0,%1,%3,%2\";
9a3c428b
DE		 3980}"
3981 [(set_attr "type" "compare")])
685f3906 3982
1fd4e8c1 3983(define_insn "rotlsi3"
44cd321e
PS		 3984 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3985 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3986 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
1fd4e8c1 3987 ""
44cd321e
PS		 3988 "@
3989 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3990 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3991 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 3992
a260abc9 3993(define_insn "*rotlsi3_internal2"
44cd321e
PS		 3994 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3995 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3996 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3997 (const_int 0)))
44cd321e 3998 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
ce71f754 3999 ""
9ebbca7d 4000 "@
44cd321e
PS		 4001 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4002 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4003 #
9ebbca7d 4004 #"
44cd321e
PS		 4005 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4006 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4007
4008(define_split
c921bad8 4009 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4010 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4011 (match_operand:SI 2 "reg_or_cint_operand" ""))
4012 (const_int 0)))
4013 (clobber (match_scratch:SI 3 ""))]
ce71f754 4014 "reload_completed"
9ebbca7d
GK		 4015 [(set (match_dup 3)
4016 (rotate:SI (match_dup 1) (match_dup 2)))
4017 (set (match_dup 0)
4018 (compare:CC (match_dup 3)
4019 (const_int 0)))]
4020 "")
1fd4e8c1 4021
a260abc9 4022(define_insn "*rotlsi3_internal3"
44cd321e
PS		 4023 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4024 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4025 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4026 (const_int 0)))
44cd321e 4027 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4028 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 4029 ""
9ebbca7d 4030 "@
44cd321e
PS		 4031 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4032 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4033 #
9ebbca7d 4034 #"
44cd321e
PS		 4035 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4036 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4037
4038(define_split
c921bad8 4039 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4040 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4041 (match_operand:SI 2 "reg_or_cint_operand" ""))
4042 (const_int 0)))
4043 (set (match_operand:SI 0 "gpc_reg_operand" "")
4044 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 4045 "reload_completed"
9ebbca7d
GK		 4046 [(set (match_dup 0)
4047 (rotate:SI (match_dup 1) (match_dup 2)))
4048 (set (match_dup 3)
4049 (compare:CC (match_dup 0)
4050 (const_int 0)))]
4051 "")
1fd4e8c1 4052
a260abc9 4053(define_insn "*rotlsi3_internal4"
44cd321e
PS		 4054 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4055 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4056 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4057 (match_operand:SI 3 "mask_operand" "n,n")))]
1fd4e8c1 4058 ""
44cd321e
PS		 4059 "@
4060 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4061 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4062 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 4063
a260abc9 4064(define_insn "*rotlsi3_internal5"
44cd321e 4065 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 4066 (compare:CC (and:SI
44cd321e
PS		 4067 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4068 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4069 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 4070 (const_int 0)))
44cd321e 4071 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
ce71f754 4072 ""
9ebbca7d 4073 "@
44cd321e
PS		 4074 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4075 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4076 #
9ebbca7d 4077 #"
44cd321e
PS		 4078 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4079 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4080
4081(define_split
c921bad8 4082 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4083 (compare:CC (and:SI
4084 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4085 (match_operand:SI 2 "reg_or_cint_operand" ""))
4086 (match_operand:SI 3 "mask_operand" ""))
4087 (const_int 0)))
4088 (clobber (match_scratch:SI 4 ""))]
ce71f754 4089 "reload_completed"
9ebbca7d
GK		 4090 [(set (match_dup 4)
4091 (and:SI (rotate:SI (match_dup 1)
4092 (match_dup 2))
4093 (match_dup 3)))
4094 (set (match_dup 0)
4095 (compare:CC (match_dup 4)
4096 (const_int 0)))]
4097 "")
1fd4e8c1 4098
a260abc9 4099(define_insn "*rotlsi3_internal6"
44cd321e 4100 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 4101 (compare:CC (and:SI
44cd321e
PS		 4102 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4103 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4104 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 4105 (const_int 0)))
44cd321e 4106 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4107 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4108 ""
9ebbca7d 4109 "@
44cd321e
PS		 4110 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4111 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4112 #
9ebbca7d 4113 #"
44cd321e
PS		 4114 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4115 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4116
4117(define_split
c921bad8 4118 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4119 (compare:CC (and:SI
4120 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4121 (match_operand:SI 2 "reg_or_cint_operand" ""))
4122 (match_operand:SI 3 "mask_operand" ""))
4123 (const_int 0)))
4124 (set (match_operand:SI 0 "gpc_reg_operand" "")
4125 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4126 "reload_completed"
9ebbca7d
GK		 4127 [(set (match_dup 0)
4128 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4129 (set (match_dup 4)
4130 (compare:CC (match_dup 0)
4131 (const_int 0)))]
4132 "")
1fd4e8c1 4133
a260abc9 4134(define_insn "*rotlsi3_internal7"
cd2b37d9 4135 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4136 (zero_extend:SI
4137 (subreg:QI
cd2b37d9 4138 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4139 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4140 ""
c921bad8
AP		 4141 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4142 [(set (attr "cell_micro")
4143 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4144 (const_string "not")
4145 (const_string "always")))])
1fd4e8c1 4146
a260abc9 4147(define_insn "*rotlsi3_internal8"
44cd321e 4148 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4149 (compare:CC (zero_extend:SI
4150 (subreg:QI
44cd321e
PS		 4151 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4152 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4153 (const_int 0)))
44cd321e 4154 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4155 ""
9ebbca7d 4156 "@
44cd321e
PS		 4157 {rlnm.|rlwnm.} %3,%1,%2,0xff
4158 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4159 #
9ebbca7d 4160 #"
44cd321e
PS		 4161 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4162 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4163
4164(define_split
c921bad8 4165 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4166 (compare:CC (zero_extend:SI
4167 (subreg:QI
4168 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4169 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4170 (const_int 0)))
4171 (clobber (match_scratch:SI 3 ""))]
4172 "reload_completed"
4173 [(set (match_dup 3)
4174 (zero_extend:SI (subreg:QI
4175 (rotate:SI (match_dup 1)
4176 (match_dup 2)) 0)))
4177 (set (match_dup 0)
4178 (compare:CC (match_dup 3)
4179 (const_int 0)))]
4180 "")
1fd4e8c1 4181
a260abc9 4182(define_insn "*rotlsi3_internal9"
44cd321e 4183 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4184 (compare:CC (zero_extend:SI
4185 (subreg:QI
44cd321e
PS		 4186 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4187 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4188 (const_int 0)))
44cd321e 4189 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4190 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4191 ""
9ebbca7d 4192 "@
44cd321e
PS		 4193 {rlnm.|rlwnm.} %0,%1,%2,0xff
4194 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4195 #
9ebbca7d 4196 #"
44cd321e
PS		 4197 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4198 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4199
4200(define_split
c921bad8 4201 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4202 (compare:CC (zero_extend:SI
4203 (subreg:QI
4204 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4205 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4206 (const_int 0)))
4207 (set (match_operand:SI 0 "gpc_reg_operand" "")
4208 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4209 "reload_completed"
4210 [(set (match_dup 0)
4211 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4212 (set (match_dup 3)
4213 (compare:CC (match_dup 0)
4214 (const_int 0)))]
4215 "")
1fd4e8c1 4216
a260abc9 4217(define_insn "*rotlsi3_internal10"
44cd321e 4218 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 4219 (zero_extend:SI
4220 (subreg:HI
44cd321e
PS		 4221 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4222 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
1fd4e8c1 4223 ""
44cd321e
PS		 4224 "@
4225 {rlnm|rlwnm} %0,%1,%2,0xffff
4226 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4227 [(set_attr "type" "var_shift_rotate,integer")])
4228
1fd4e8c1 4229
a260abc9 4230(define_insn "*rotlsi3_internal11"
44cd321e 4231 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4232 (compare:CC (zero_extend:SI
4233 (subreg:HI
44cd321e
PS		 4234 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4235 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4236 (const_int 0)))
44cd321e 4237 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4238 ""
9ebbca7d 4239 "@
44cd321e
PS		 4240 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4241 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4242 #
9ebbca7d 4243 #"
44cd321e
PS		 4244 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4245 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4246
4247(define_split
c921bad8 4248 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4249 (compare:CC (zero_extend:SI
4250 (subreg:HI
4251 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4252 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4253 (const_int 0)))
4254 (clobber (match_scratch:SI 3 ""))]
4255 "reload_completed"
4256 [(set (match_dup 3)
4257 (zero_extend:SI (subreg:HI
4258 (rotate:SI (match_dup 1)
4259 (match_dup 2)) 0)))
4260 (set (match_dup 0)
4261 (compare:CC (match_dup 3)
4262 (const_int 0)))]
4263 "")
1fd4e8c1 4264
a260abc9 4265(define_insn "*rotlsi3_internal12"
44cd321e 4266 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4267 (compare:CC (zero_extend:SI
4268 (subreg:HI
44cd321e
PS		 4269 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4270 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4271 (const_int 0)))
44cd321e 4272 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4273 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4274 ""
9ebbca7d 4275 "@
44cd321e
PS		 4276 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4277 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4278 #
9ebbca7d 4279 #"
44cd321e
PS		 4280 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4281 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4282
4283(define_split
c921bad8 4284 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4285 (compare:CC (zero_extend:SI
4286 (subreg:HI
4287 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4288 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4289 (const_int 0)))
4290 (set (match_operand:SI 0 "gpc_reg_operand" "")
4291 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4292 "reload_completed"
4293 [(set (match_dup 0)
4294 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4295 (set (match_dup 3)
4296 (compare:CC (match_dup 0)
4297 (const_int 0)))]
4298 "")
1fd4e8c1
RK		 4299
4300;; Note that we use "sle." instead of "sl." so that we can set
4301;; SHIFT_COUNT_TRUNCATED.
4302
ca7f5001
RK		 4303(define_expand "ashlsi3"
4304 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4305 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4306 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4307 ""
4308 "
4309{
4310 if (TARGET_POWER)
4311 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4312 else
25c341fa 4313 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4314 DONE;
4315}")
4316
4317(define_insn "ashlsi3_power"
cd2b37d9
RK		 4318 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4319 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4320 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4321 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4322 "TARGET_POWER"
1fd4e8c1
RK		 4323 "@
4324 sle %0,%1,%2
9ebbca7d 4325 {sli|slwi} %0,%1,%h2")
ca7f5001 4326
25c341fa 4327(define_insn "ashlsi3_no_power"
44cd321e
PS		 4328 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4329 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4330 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4331 "! TARGET_POWER"
44cd321e
PS		 4332 "@
4333 {sl|slw} %0,%1,%2
4334 {sli|slwi} %0,%1,%h2"
4335 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 4336
4337(define_insn ""
9ebbca7d
GK		 4338 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4339 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4340 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4341 (const_int 0)))
9ebbca7d
GK		 4342 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4343 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4344 "TARGET_POWER"
1fd4e8c1
RK		 4345 "@
4346 sle. %3,%1,%2
9ebbca7d
GK		 4347 {sli.|slwi.} %3,%1,%h2
4348 #
4349 #"
4350 [(set_attr "type" "delayed_compare")
4351 (set_attr "length" "4,4,8,8")])
4352
4353(define_split
4354 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4355 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4356 (match_operand:SI 2 "reg_or_cint_operand" ""))
4357 (const_int 0)))
4358 (clobber (match_scratch:SI 3 ""))
4359 (clobber (match_scratch:SI 4 ""))]
4360 "TARGET_POWER && reload_completed"
4361 [(parallel [(set (match_dup 3)
4362 (ashift:SI (match_dup 1) (match_dup 2)))
4363 (clobber (match_dup 4))])
4364 (set (match_dup 0)
4365 (compare:CC (match_dup 3)
4366 (const_int 0)))]
4367 "")
25c341fa 4368
ca7f5001 4369(define_insn ""
44cd321e
PS		 4370 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4371 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4372 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4373 (const_int 0)))
44cd321e 4374 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4b8a63d6 4375 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4376 "@
44cd321e
PS		 4377 {sl.|slw.} %3,%1,%2
4378 {sli.|slwi.} %3,%1,%h2
4379 #
9ebbca7d 4380 #"
44cd321e
PS		 4381 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4382 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4383
4384(define_split
4385 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4386 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4387 (match_operand:SI 2 "reg_or_cint_operand" ""))
4388 (const_int 0)))
4389 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4390 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4391 [(set (match_dup 3)
4392 (ashift:SI (match_dup 1) (match_dup 2)))
4393 (set (match_dup 0)
4394 (compare:CC (match_dup 3)
4395 (const_int 0)))]
4396 "")
1fd4e8c1
RK		 4397
4398(define_insn ""
9ebbca7d
GK		 4399 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4400 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4401 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4402 (const_int 0)))
9ebbca7d 4403 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4404 (ashift:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4405 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4406 "TARGET_POWER"
1fd4e8c1
RK		 4407 "@
4408 sle. %0,%1,%2
9ebbca7d
GK		 4409 {sli.|slwi.} %0,%1,%h2
4410 #
4411 #"
4412 [(set_attr "type" "delayed_compare")
4413 (set_attr "length" "4,4,8,8")])
4414
4415(define_split
4416 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4417 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4418 (match_operand:SI 2 "reg_or_cint_operand" ""))
4419 (const_int 0)))
4420 (set (match_operand:SI 0 "gpc_reg_operand" "")
4421 (ashift:SI (match_dup 1) (match_dup 2)))
4422 (clobber (match_scratch:SI 4 ""))]
4423 "TARGET_POWER && reload_completed"
4424 [(parallel [(set (match_dup 0)
4425 (ashift:SI (match_dup 1) (match_dup 2)))
4426 (clobber (match_dup 4))])
4427 (set (match_dup 3)
4428 (compare:CC (match_dup 0)
4429 (const_int 0)))]
4430 "")
25c341fa 4431
ca7f5001 4432(define_insn ""
44cd321e
PS		 4433 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4434 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4435 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4436 (const_int 0)))
44cd321e 4437 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 4438 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4439 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4440 "@
44cd321e
PS		 4441 {sl.|slw.} %0,%1,%2
4442 {sli.|slwi.} %0,%1,%h2
4443 #
9ebbca7d 4444 #"
44cd321e
PS		 4445 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4446 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4447
4448(define_split
4449 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4450 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4451 (match_operand:SI 2 "reg_or_cint_operand" ""))
4452 (const_int 0)))
4453 (set (match_operand:SI 0 "gpc_reg_operand" "")
4454 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4455 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4456 [(set (match_dup 0)
4457 (ashift:SI (match_dup 1) (match_dup 2)))
4458 (set (match_dup 3)
4459 (compare:CC (match_dup 0)
4460 (const_int 0)))]
4461 "")
1fd4e8c1 4462
915167f5 4463(define_insn "rlwinm"
cd2b37d9
RK		 4464 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4465 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4466 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4467 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4468 "includes_lshift_p (operands[2], operands[3])"
d56d506a 4469 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
1fd4e8c1
RK		 4470
4471(define_insn ""
9ebbca7d 4472 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4473 (compare:CC
9ebbca7d
GK		 4474 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4475 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4476 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4477 (const_int 0)))
9ebbca7d 4478 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4479 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4480 "@
4481 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4482 #"
4483 [(set_attr "type" "delayed_compare")
4484 (set_attr "length" "4,8")])
4485
4486(define_split
c921bad8 4487 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4488 (compare:CC
4489 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4490 (match_operand:SI 2 "const_int_operand" ""))
4491 (match_operand:SI 3 "mask_operand" ""))
4492 (const_int 0)))
4493 (clobber (match_scratch:SI 4 ""))]
ce71f754 4494 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4495 [(set (match_dup 4)
4496 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4497 (match_dup 3)))
4498 (set (match_dup 0)
4499 (compare:CC (match_dup 4)
4500 (const_int 0)))]
4501 "")
1fd4e8c1
RK		 4502
4503(define_insn ""
9ebbca7d 4504 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4505 (compare:CC
9ebbca7d
GK		 4506 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4507 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4508 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4509 (const_int 0)))
9ebbca7d 4510 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4511 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4512 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4513 "@
4514 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4515 #"
4516 [(set_attr "type" "delayed_compare")
4517 (set_attr "length" "4,8")])
4518
4519(define_split
c921bad8 4520 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4521 (compare:CC
4522 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4523 (match_operand:SI 2 "const_int_operand" ""))
4524 (match_operand:SI 3 "mask_operand" ""))
4525 (const_int 0)))
4526 (set (match_operand:SI 0 "gpc_reg_operand" "")
4527 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4528 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4529 [(set (match_dup 0)
4530 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4531 (set (match_dup 4)
4532 (compare:CC (match_dup 0)
4533 (const_int 0)))]
4534 "")
1fd4e8c1 4535
ca7f5001 4536;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5c23c401 4537;; "sli x,x,0".
ca7f5001
RK		 4538(define_expand "lshrsi3"
4539 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4540 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4541 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4542 ""
4543 "
4544{
4545 if (TARGET_POWER)
4546 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4547 else
25c341fa 4548 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4549 DONE;
4550}")
4551
4552(define_insn "lshrsi3_power"
bdf423cb
MM		 4553 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4554 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4555 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4556 (clobber (match_scratch:SI 3 "=q,X,X"))]
ca7f5001 4557 "TARGET_POWER"
1fd4e8c1
RK		 4558 "@
4559 sre %0,%1,%2
bdf423cb 4560 mr %0,%1
ca7f5001
RK		 4561 {s%A2i|s%A2wi} %0,%1,%h2")
4562
25c341fa 4563(define_insn "lshrsi3_no_power"
44cd321e
PS		 4564 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4565 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4566 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
25c341fa 4567 "! TARGET_POWER"
bdf423cb
MM		 4568 "@
4569 mr %0,%1
44cd321e
PS		 4570 {sr|srw} %0,%1,%2
4571 {sri|srwi} %0,%1,%h2"
4572 [(set_attr "type" "integer,var_shift_rotate,shift")])
1fd4e8c1
RK		 4573
4574(define_insn ""
9ebbca7d
GK		 4575 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4576 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4577 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4578 (const_int 0)))
9ebbca7d
GK		 4579 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4580 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4581 "TARGET_POWER"
1fd4e8c1 4582 "@
29ae5b89
JL		 4583 sre. %3,%1,%2
4584 mr. %1,%1
9ebbca7d
GK		 4585 {s%A2i.|s%A2wi.} %3,%1,%h2
4586 #
4587 #
4588 #"
4589 [(set_attr "type" "delayed_compare")
4590 (set_attr "length" "4,4,4,8,8,8")])
4591
4592(define_split
4593 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4594 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4595 (match_operand:SI 2 "reg_or_cint_operand" ""))
4596 (const_int 0)))
4597 (clobber (match_scratch:SI 3 ""))
4598 (clobber (match_scratch:SI 4 ""))]
4599 "TARGET_POWER && reload_completed"
4600 [(parallel [(set (match_dup 3)
4601 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4602 (clobber (match_dup 4))])
4603 (set (match_dup 0)
4604 (compare:CC (match_dup 3)
4605 (const_int 0)))]
4606 "")
ca7f5001
RK		 4607
4608(define_insn ""
44cd321e
PS		 4609 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4610 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4611 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
ca7f5001 4612 (const_int 0)))
44cd321e 4613 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4b8a63d6 4614 "! TARGET_POWER && TARGET_32BIT"
bdf423cb
MM		 4615 "@
4616 mr. %1,%1
44cd321e
PS		 4617 {sr.|srw.} %3,%1,%2
4618 {sri.|srwi.} %3,%1,%h2
4619 #
9ebbca7d
GK		 4620 #
4621 #"
44cd321e
PS		 4622 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4623 (set_attr "length" "4,4,4,8,8,8")])
1fd4e8c1 4624
9ebbca7d
GK		 4625(define_split
4626 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4627 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4628 (match_operand:SI 2 "reg_or_cint_operand" ""))
4629 (const_int 0)))
4630 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4631 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4632 [(set (match_dup 3)
4633 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4634 (set (match_dup 0)
4635 (compare:CC (match_dup 3)
4636 (const_int 0)))]
4637 "")
4638
4639(define_insn ""
4640 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4641 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4642 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4643 (const_int 0)))
9ebbca7d 4644 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
1fd4e8c1 4645 (lshiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4646 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4647 "TARGET_POWER"
1fd4e8c1 4648 "@
29ae5b89
JL		 4649 sre. %0,%1,%2
4650 mr. %0,%1
9ebbca7d
GK		 4651 {s%A2i.|s%A2wi.} %0,%1,%h2
4652 #
4653 #
4654 #"
4655 [(set_attr "type" "delayed_compare")
4656 (set_attr "length" "4,4,4,8,8,8")])
4657
4658(define_split
4659 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4660 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4661 (match_operand:SI 2 "reg_or_cint_operand" ""))
4662 (const_int 0)))
4663 (set (match_operand:SI 0 "gpc_reg_operand" "")
4664 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4665 (clobber (match_scratch:SI 4 ""))]
4666 "TARGET_POWER && reload_completed"
4667 [(parallel [(set (match_dup 0)
4668 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4669 (clobber (match_dup 4))])
4670 (set (match_dup 3)
4671 (compare:CC (match_dup 0)
4672 (const_int 0)))]
4673 "")
ca7f5001
RK		 4674
4675(define_insn ""
44cd321e
PS		 4676 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4677 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4678 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
815cdc52 4679 (const_int 0)))
44cd321e 4680 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
29ae5b89 4681 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4682 "! TARGET_POWER && TARGET_32BIT"
29ae5b89
JL		 4683 "@
4684 mr. %0,%1
44cd321e
PS		 4685 {sr.|srw.} %0,%1,%2
4686 {sri.|srwi.} %0,%1,%h2
4687 #
9ebbca7d
GK		 4688 #
4689 #"
44cd321e
PS		 4690 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4691 (set_attr "length" "4,4,4,8,8,8")])
9ebbca7d
GK		 4692
4693(define_split
4694 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4695 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4696 (match_operand:SI 2 "reg_or_cint_operand" ""))
4697 (const_int 0)))
4698 (set (match_operand:SI 0 "gpc_reg_operand" "")
4699 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4700 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4701 [(set (match_dup 0)
4702 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4703 (set (match_dup 3)
4704 (compare:CC (match_dup 0)
4705 (const_int 0)))]
4706 "")
1fd4e8c1
RK		 4707
4708(define_insn ""
cd2b37d9
RK		 4709 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4710 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4711 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4712 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4713 "includes_rshift_p (operands[2], operands[3])"
ca7f5001 4714 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
1fd4e8c1
RK		 4715
4716(define_insn ""
9ebbca7d 4717 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4718 (compare:CC
9ebbca7d
GK		 4719 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4720 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4721 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4722 (const_int 0)))
9ebbca7d 4723 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4724 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4725 "@
4726 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4727 #"
4728 [(set_attr "type" "delayed_compare")
4729 (set_attr "length" "4,8")])
4730
4731(define_split
c921bad8 4732 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4733 (compare:CC
4734 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4735 (match_operand:SI 2 "const_int_operand" ""))
4736 (match_operand:SI 3 "mask_operand" ""))
4737 (const_int 0)))
4738 (clobber (match_scratch:SI 4 ""))]
ce71f754 4739 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4740 [(set (match_dup 4)
4741 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4742 (match_dup 3)))
4743 (set (match_dup 0)
4744 (compare:CC (match_dup 4)
4745 (const_int 0)))]
4746 "")
1fd4e8c1
RK		 4747
4748(define_insn ""
9ebbca7d 4749 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4750 (compare:CC
9ebbca7d
GK		 4751 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4752 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4753 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4754 (const_int 0)))
9ebbca7d 4755 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4756 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4757 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4758 "@
4759 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4760 #"
4761 [(set_attr "type" "delayed_compare")
4762 (set_attr "length" "4,8")])
4763
4764(define_split
c921bad8 4765 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4766 (compare:CC
4767 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4768 (match_operand:SI 2 "const_int_operand" ""))
4769 (match_operand:SI 3 "mask_operand" ""))
4770 (const_int 0)))
4771 (set (match_operand:SI 0 "gpc_reg_operand" "")
4772 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4773 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4774 [(set (match_dup 0)
4775 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4776 (set (match_dup 4)
4777 (compare:CC (match_dup 0)
4778 (const_int 0)))]
4779 "")
1fd4e8c1
RK		 4780
4781(define_insn ""
cd2b37d9 4782 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4783 (zero_extend:SI
4784 (subreg:QI
cd2b37d9 4785 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4786 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4787 "includes_rshift_p (operands[2], GEN_INT (255))"
ca7f5001 4788 "{rlinm|rlwinm} %0,%1,%s2,0xff")
1fd4e8c1
RK		 4789
4790(define_insn ""
9ebbca7d 4791 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4792 (compare:CC
4793 (zero_extend:SI
4794 (subreg:QI
9ebbca7d
GK		 4795 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4796 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4797 (const_int 0)))
9ebbca7d 4798 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4799 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4800 "@
4801 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4802 #"
4803 [(set_attr "type" "delayed_compare")
4804 (set_attr "length" "4,8")])
4805
4806(define_split
c921bad8 4807 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4808 (compare:CC
4809 (zero_extend:SI
4810 (subreg:QI
4811 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4812 (match_operand:SI 2 "const_int_operand" "")) 0))
4813 (const_int 0)))
4814 (clobber (match_scratch:SI 3 ""))]
4815 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4816 [(set (match_dup 3)
4817 (zero_extend:SI (subreg:QI
4818 (lshiftrt:SI (match_dup 1)
4819 (match_dup 2)) 0)))
4820 (set (match_dup 0)
4821 (compare:CC (match_dup 3)
4822 (const_int 0)))]
4823 "")
1fd4e8c1
RK		 4824
4825(define_insn ""
9ebbca7d 4826 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4827 (compare:CC
4828 (zero_extend:SI
4829 (subreg:QI
9ebbca7d
GK		 4830 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4831 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4832 (const_int 0)))
9ebbca7d 4833 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4834 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4835 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4836 "@
4837 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4838 #"
4839 [(set_attr "type" "delayed_compare")
4840 (set_attr "length" "4,8")])
4841
4842(define_split
c921bad8 4843 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4844 (compare:CC
4845 (zero_extend:SI
4846 (subreg:QI
4847 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4848 (match_operand:SI 2 "const_int_operand" "")) 0))
4849 (const_int 0)))
4850 (set (match_operand:SI 0 "gpc_reg_operand" "")
4851 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4852 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4853 [(set (match_dup 0)
4854 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4855 (set (match_dup 3)
4856 (compare:CC (match_dup 0)
4857 (const_int 0)))]
4858 "")
1fd4e8c1
RK		 4859
4860(define_insn ""
cd2b37d9 4861 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4862 (zero_extend:SI
4863 (subreg:HI
cd2b37d9 4864 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4865 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4866 "includes_rshift_p (operands[2], GEN_INT (65535))"
ca7f5001 4867 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
1fd4e8c1
RK		 4868
4869(define_insn ""
9ebbca7d 4870 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4871 (compare:CC
4872 (zero_extend:SI
4873 (subreg:HI
9ebbca7d
GK		 4874 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4875 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4876 (const_int 0)))
9ebbca7d 4877 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4878 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4879 "@
4880 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4881 #"
4882 [(set_attr "type" "delayed_compare")
4883 (set_attr "length" "4,8")])
4884
4885(define_split
c921bad8 4886 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4887 (compare:CC
4888 (zero_extend:SI
4889 (subreg:HI
4890 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4891 (match_operand:SI 2 "const_int_operand" "")) 0))
4892 (const_int 0)))
4893 (clobber (match_scratch:SI 3 ""))]
4894 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4895 [(set (match_dup 3)
4896 (zero_extend:SI (subreg:HI
4897 (lshiftrt:SI (match_dup 1)
4898 (match_dup 2)) 0)))
4899 (set (match_dup 0)
4900 (compare:CC (match_dup 3)
4901 (const_int 0)))]
4902 "")
1fd4e8c1
RK		 4903
4904(define_insn ""
9ebbca7d 4905 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4906 (compare:CC
4907 (zero_extend:SI
4908 (subreg:HI
9ebbca7d
GK		 4909 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4910 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4911 (const_int 0)))
9ebbca7d 4912 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4913 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4914 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4915 "@
4916 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4917 #"
4918 [(set_attr "type" "delayed_compare")
4919 (set_attr "length" "4,8")])
4920
4921(define_split
c921bad8 4922 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 4923 (compare:CC
4924 (zero_extend:SI
4925 (subreg:HI
4926 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4927 (match_operand:SI 2 "const_int_operand" "")) 0))
4928 (const_int 0)))
4929 (set (match_operand:SI 0 "gpc_reg_operand" "")
4930 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4931 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4932 [(set (match_dup 0)
4933 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4934 (set (match_dup 3)
4935 (compare:CC (match_dup 0)
4936 (const_int 0)))]
4937 "")
1fd4e8c1
RK		 4938
4939(define_insn ""
cd2b37d9 4940 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4941 (const_int 1)
cd2b37d9
RK		 4942 (match_operand:SI 1 "gpc_reg_operand" "r"))
4943 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4944 (const_int 31)))]
ca7f5001 4945 "TARGET_POWER"
1fd4e8c1
RK		 4946 "rrib %0,%1,%2")
4947
4948(define_insn ""
cd2b37d9 4949 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4950 (const_int 1)
cd2b37d9
RK		 4951 (match_operand:SI 1 "gpc_reg_operand" "r"))
4952 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4953 (const_int 31)))]
ca7f5001 4954 "TARGET_POWER"
1fd4e8c1
RK		 4955 "rrib %0,%1,%2")
4956
4957(define_insn ""
cd2b37d9 4958 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4959 (const_int 1)
cd2b37d9
RK		 4960 (match_operand:SI 1 "gpc_reg_operand" "r"))
4961 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4962 (const_int 1)
4963 (const_int 0)))]
ca7f5001 4964 "TARGET_POWER"
1fd4e8c1
RK		 4965 "rrib %0,%1,%2")
4966
ca7f5001
RK		 4967(define_expand "ashrsi3"
4968 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4969 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4970 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4971 ""
4972 "
4973{
4974 if (TARGET_POWER)
4975 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4976 else
25c341fa 4977 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4978 DONE;
4979}")
4980
4981(define_insn "ashrsi3_power"
cd2b37d9
RK		 4982 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4983 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4984 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4985 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4986 "TARGET_POWER"
1fd4e8c1
RK		 4987 "@
4988 srea %0,%1,%2
44cd321e
PS		 4989 {srai|srawi} %0,%1,%h2"
4990 [(set_attr "type" "shift")])
ca7f5001 4991
25c341fa 4992(define_insn "ashrsi3_no_power"
44cd321e
PS		 4993 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4994 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4995 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4996 "! TARGET_POWER"
44cd321e
PS		 4997 "@
4998 {sra|sraw} %0,%1,%2
4999 {srai|srawi} %0,%1,%h2"
5000 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 5001
5002(define_insn ""
9ebbca7d
GK		 5003 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5004 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5005 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 5006 (const_int 0)))
9ebbca7d
GK		 5007 (clobber (match_scratch:SI 3 "=r,r,r,r"))
5008 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 5009 "TARGET_POWER"
1fd4e8c1
RK		 5010 "@
5011 srea. %3,%1,%2
9ebbca7d
GK		 5012 {srai.|srawi.} %3,%1,%h2
5013 #
5014 #"
5015 [(set_attr "type" "delayed_compare")
5016 (set_attr "length" "4,4,8,8")])
5017
5018(define_split
5019 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5020 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5021 (match_operand:SI 2 "reg_or_cint_operand" ""))
5022 (const_int 0)))
5023 (clobber (match_scratch:SI 3 ""))
5024 (clobber (match_scratch:SI 4 ""))]
5025 "TARGET_POWER && reload_completed"
5026 [(parallel [(set (match_dup 3)
5027 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5028 (clobber (match_dup 4))])
5029 (set (match_dup 0)
5030 (compare:CC (match_dup 3)
5031 (const_int 0)))]
5032 "")
ca7f5001
RK		 5033
5034(define_insn ""
44cd321e
PS		 5035 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5036 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5037 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 5038 (const_int 0)))
44cd321e 5039 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
25c341fa 5040 "! TARGET_POWER"
9ebbca7d 5041 "@
44cd321e
PS		 5042 {sra.|sraw.} %3,%1,%2
5043 {srai.|srawi.} %3,%1,%h2
5044 #
9ebbca7d 5045 #"
44cd321e
PS		 5046 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5047 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 5048
5049(define_split
c921bad8 5050 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 5051 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5052 (match_operand:SI 2 "reg_or_cint_operand" ""))
5053 (const_int 0)))
5054 (clobber (match_scratch:SI 3 ""))]
5055 "! TARGET_POWER && reload_completed"
5056 [(set (match_dup 3)
5057 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5058 (set (match_dup 0)
5059 (compare:CC (match_dup 3)
5060 (const_int 0)))]
5061 "")
1fd4e8c1
RK		 5062
5063(define_insn ""
9ebbca7d
GK		 5064 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5065 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5066 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 5067 (const_int 0)))
9ebbca7d 5068 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 5069 (ashiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 5070 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 5071 "TARGET_POWER"
1fd4e8c1
RK		 5072 "@
5073 srea. %0,%1,%2
9ebbca7d
GK		 5074 {srai.|srawi.} %0,%1,%h2
5075 #
5076 #"
5077 [(set_attr "type" "delayed_compare")
5078 (set_attr "length" "4,4,8,8")])
5079
5080(define_split
5081 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5082 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5083 (match_operand:SI 2 "reg_or_cint_operand" ""))
5084 (const_int 0)))
5085 (set (match_operand:SI 0 "gpc_reg_operand" "")
5086 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5087 (clobber (match_scratch:SI 4 ""))]
5088 "TARGET_POWER && reload_completed"
5089 [(parallel [(set (match_dup 0)
5090 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5091 (clobber (match_dup 4))])
5092 (set (match_dup 3)
5093 (compare:CC (match_dup 0)
5094 (const_int 0)))]
5095 "")
1fd4e8c1 5096
ca7f5001 5097(define_insn ""
44cd321e
PS		 5098 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5099 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5100 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 5101 (const_int 0)))
44cd321e 5102 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 5103 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
25c341fa 5104 "! TARGET_POWER"
9ebbca7d 5105 "@
44cd321e
PS		 5106 {sra.|sraw.} %0,%1,%2
5107 {srai.|srawi.} %0,%1,%h2
5108 #
9ebbca7d 5109 #"
44cd321e
PS		 5110 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5111 (set_attr "length" "4,4,8,8")])
1fd4e8c1 5112\f
9ebbca7d 5113(define_split
c921bad8 5114 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 5115 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5116 (match_operand:SI 2 "reg_or_cint_operand" ""))
5117 (const_int 0)))
5118 (set (match_operand:SI 0 "gpc_reg_operand" "")
5119 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5120 "! TARGET_POWER && reload_completed"
5121 [(set (match_dup 0)
5122 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5123 (set (match_dup 3)
5124 (compare:CC (match_dup 0)
5125 (const_int 0)))]
5126 "")
5127
1fd4e8c1
RK		 5128;; Floating-point insns, excluding normal data motion.
5129;;
ca7f5001
RK		 5130;; PowerPC has a full set of single-precision floating point instructions.
5131;;
5132;; For the POWER architecture, we pretend that we have both SFmode and
5133;; DFmode insns, while, in fact, all fp insns are actually done in double.
5134;; The only conversions we will do will be when storing to memory. In that
5135;; case, we will use the "frsp" instruction before storing.
1fd4e8c1
RK		 5136;;
5137;; Note that when we store into a single-precision memory location, we need to
5138;; use the frsp insn first. If the register being stored isn't dead, we
5139;; need a scratch register for the frsp. But this is difficult when the store
5140;; is done by reload. It is not incorrect to do the frsp on the register in
5141;; this case, we just lose precision that we would have otherwise gotten but
5142;; is not guaranteed. Perhaps this should be tightened up at some point.
5143
99176a91
AH		 5144(define_expand "extendsfdf2"
5145 [(set (match_operand:DF 0 "gpc_reg_operand" "")
97c54d9a 5146 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
696e45ba 5147 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
99176a91
AH		 5148 "")
5149
5150(define_insn_and_split "*extendsfdf2_fpr"
799dbb0f 5151 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
97c54d9a 5152 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
696e45ba 5153 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
11ac38b2
DE		 5154 "@
5155 #
97c54d9a
DE		 5156 fmr %0,%1
5157 lfs%U1%X1 %0,%1"
d7b1468b 5158 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
11ac38b2 5159 [(const_int 0)]
5c30aff8 5160{
11ac38b2
DE		 5161 emit_note (NOTE_INSN_DELETED);
5162 DONE;
5163}
97c54d9a 5164 [(set_attr "type" "fp,fp,fpload")])
1fd4e8c1 5165
7a2f7870
AH		 5166(define_expand "truncdfsf2"
5167 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5168 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
696e45ba 5169 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5170 "")
5171
99176a91 5172(define_insn "*truncdfsf2_fpr"
cd2b37d9 5173 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
799dbb0f 5174 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
696e45ba 5175 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
dcac138d 5176 "frsp %0,%1"
1fd4e8c1
RK		 5177 [(set_attr "type" "fp")])
5178
455350f4
RK		 5179(define_insn "aux_truncdfsf2"
5180 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
615158e2 5181 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
e47911ce 5182 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
455350f4
RK		 5183 "frsp %0,%1"
5184 [(set_attr "type" "fp")])
5185
a3170dc6
AH		 5186(define_expand "negsf2"
5187 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5188 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
696e45ba 5189 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
a3170dc6
AH		 5190 "")
5191
5192(define_insn "*negsf2"
cd2b37d9
RK		 5193 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5194 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
696e45ba 5195 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
1fd4e8c1
RK		 5196 "fneg %0,%1"
5197 [(set_attr "type" "fp")])
5198
a3170dc6
AH		 5199(define_expand "abssf2"
5200 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5201 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
696e45ba 5202 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
a3170dc6
AH		 5203 "")
5204
5205(define_insn "*abssf2"
cd2b37d9
RK		 5206 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5207 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
696e45ba 5208 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
1fd4e8c1
RK		 5209 "fabs %0,%1"
5210 [(set_attr "type" "fp")])
5211
5212(define_insn ""
cd2b37d9
RK		 5213 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5214 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
696e45ba 5215 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
1fd4e8c1
RK		 5216 "fnabs %0,%1"
5217 [(set_attr "type" "fp")])
5218
ca7f5001
RK		 5219(define_expand "addsf3"
5220 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5221 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5222 (match_operand:SF 2 "gpc_reg_operand" "")))]
696e45ba 5223 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
ca7f5001
RK		 5224 "")
5225
5226(define_insn ""
cd2b37d9
RK		 5227 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5228 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5229 (match_operand:SF 2 "gpc_reg_operand" "f")))]
e47911ce 5230 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
b26c8351 5231 "fadds %0,%1,%2"
0bb7b92e
ME		 5232 [(set_attr "type" "fp")
5233 (set_attr "fp_type" "fp_addsub_s")])
ca7f5001
RK		 5234
5235(define_insn ""
5236 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5237 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5238 (match_operand:SF 2 "gpc_reg_operand" "f")))]
e47911ce 5239 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5240 "{fa|fadd} %0,%1,%2"
e47911ce 5241 [(set_attr "type" "fp")])
ca7f5001
RK		 5242
5243(define_expand "subsf3"
5244 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5245 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5246 (match_operand:SF 2 "gpc_reg_operand" "")))]
696e45ba 5247 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
ca7f5001
RK		 5248 "")
5249
5250(define_insn ""
5251 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5252 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5253 (match_operand:SF 2 "gpc_reg_operand" "f")))]
696e45ba 5254 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
b26c8351 5255 "fsubs %0,%1,%2"
0bb7b92e
ME		 5256 [(set_attr "type" "fp")
5257 (set_attr "fp_type" "fp_addsub_s")])
1fd4e8c1 5258
ca7f5001 5259(define_insn ""
cd2b37d9
RK		 5260 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5261 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5262 (match_operand:SF 2 "gpc_reg_operand" "f")))]
e47911ce 5263 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5264 "{fs|fsub} %0,%1,%2"
e47911ce 5265 [(set_attr "type" "fp")])
ca7f5001
RK		 5266
5267(define_expand "mulsf3"
5268 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5269 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5270 (match_operand:SF 2 "gpc_reg_operand" "")))]
696e45ba 5271 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
ca7f5001
RK		 5272 "")
5273
5274(define_insn ""
5275 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5276 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5277 (match_operand:SF 2 "gpc_reg_operand" "f")))]
696e45ba 5278 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
b26c8351 5279 "fmuls %0,%1,%2"
0bb7b92e
ME		 5280 [(set_attr "type" "fp")
5281 (set_attr "fp_type" "fp_mul_s")])
1fd4e8c1 5282
ca7f5001 5283(define_insn ""
cd2b37d9
RK		 5284 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5285 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5286 (match_operand:SF 2 "gpc_reg_operand" "f")))]
e47911ce 5287 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5288 "{fm|fmul} %0,%1,%2"
e47911ce 5289 [(set_attr "type" "dmul")])
1fd4e8c1 5290
ca7f5001
RK		 5291(define_expand "divsf3"
5292 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5293 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5294 (match_operand:SF 2 "gpc_reg_operand" "")))]
696e45ba 5295 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
9c78b944 5296 "")
ca7f5001
RK		 5297
5298(define_insn ""
cd2b37d9
RK		 5299 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5300 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5301 (match_operand:SF 2 "gpc_reg_operand" "f")))]
696e45ba
ME		 5302 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5303 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
b26c8351 5304 "fdivs %0,%1,%2"
ca7f5001
RK		 5305 [(set_attr "type" "sdiv")])
5306
5307(define_insn ""
5308 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5309 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5310 (match_operand:SF 2 "gpc_reg_operand" "f")))]
696e45ba
ME		 5311 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5312 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
b26c8351 5313 "{fd|fdiv} %0,%1,%2"
0780f386 5314 [(set_attr "type" "ddiv")])
1fd4e8c1 5315
9c78b944
DE		 5316(define_expand "recipsf3"
5317 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5318 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5319 (match_operand:SF 2 "gpc_reg_operand" "f")]
5320 UNSPEC_FRES))]
5321 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5322 && flag_finite_math_only && !flag_trapping_math"
5323{
5324 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5325 DONE;
5326})
5327
5328(define_insn "fres"
5329 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5330 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5331 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5332 "fres %0,%1"
5333 [(set_attr "type" "fp")])
5334
cacf1ca8 5335(define_insn "*fmaddsf4_powerpc"
cd2b37d9
RK		 5336 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5337 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5338 (match_operand:SF 2 "gpc_reg_operand" "f"))
5339 (match_operand:SF 3 "gpc_reg_operand" "f")))]
e47911ce 5340 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
696e45ba 5341 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
b26c8351 5342 "fmadds %0,%1,%2,%3"
0bb7b92e
ME		 5343 [(set_attr "type" "fp")
5344 (set_attr "fp_type" "fp_maddsub_s")])
ca7f5001 5345
cacf1ca8 5346(define_insn "*fmaddsf4_power"
ca7f5001
RK		 5347 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5348 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5349 (match_operand:SF 2 "gpc_reg_operand" "f"))
5350 (match_operand:SF 3 "gpc_reg_operand" "f")))]
e47911ce 5351 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5352 "{fma|fmadd} %0,%1,%2,%3"
e47911ce 5353 [(set_attr "type" "dmul")])
1fd4e8c1 5354
cacf1ca8 5355(define_insn "*fmsubsf4_powerpc"
cd2b37d9
RK		 5356 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5357 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5358 (match_operand:SF 2 "gpc_reg_operand" "f"))
5359 (match_operand:SF 3 "gpc_reg_operand" "f")))]
e47911ce 5360 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
696e45ba 5361 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
b26c8351 5362 "fmsubs %0,%1,%2,%3"
0bb7b92e
ME		 5363 [(set_attr "type" "fp")
5364 (set_attr "fp_type" "fp_maddsub_s")])
ca7f5001 5365
cacf1ca8 5366(define_insn "*fmsubsf4_power"
ca7f5001
RK		 5367 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5368 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5369 (match_operand:SF 2 "gpc_reg_operand" "f"))
5370 (match_operand:SF 3 "gpc_reg_operand" "f")))]
e47911ce 5371 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5372 "{fms|fmsub} %0,%1,%2,%3"
e47911ce 5373 [(set_attr "type" "dmul")])
1fd4e8c1 5374
cacf1ca8 5375(define_insn "*fnmaddsf4_powerpc_1"
cd2b37d9
RK		 5376 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5377 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5378 (match_operand:SF 2 "gpc_reg_operand" "f"))
5379 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694 5380 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
1847ea4d 5381 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
16823694 5382 "fnmadds %0,%1,%2,%3"
0bb7b92e
ME		 5383 [(set_attr "type" "fp")
5384 (set_attr "fp_type" "fp_maddsub_s")])
16823694 5385
cacf1ca8 5386(define_insn "*fnmaddsf4_powerpc_2"
16823694
GK		 5387 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5388 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5389 (match_operand:SF 2 "gpc_reg_operand" "f"))
5390 (match_operand:SF 3 "gpc_reg_operand" "f")))]
696e45ba 5391 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
16823694 5392 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5393 "fnmadds %0,%1,%2,%3"
0bb7b92e
ME		 5394 [(set_attr "type" "fp")
5395 (set_attr "fp_type" "fp_maddsub_s")])
ca7f5001 5396
cacf1ca8 5397(define_insn "*fnmaddsf4_power_1"
ca7f5001
RK		 5398 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5399 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5400 (match_operand:SF 2 "gpc_reg_operand" "f"))
5401 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
e47911ce 5402 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5403 "{fnma|fnmadd} %0,%1,%2,%3"
e47911ce 5404 [(set_attr "type" "dmul")])
1fd4e8c1 5405
cacf1ca8 5406(define_insn "*fnmaddsf4_power_2"
16823694
GK		 5407 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5408 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5409 (match_operand:SF 2 "gpc_reg_operand" "f"))
5410 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5411 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
e47911ce 5412 && ! HONOR_SIGNED_ZEROS (SFmode)"
16823694 5413 "{fnma|fnmadd} %0,%1,%2,%3"
e47911ce 5414 [(set_attr "type" "dmul")])
16823694 5415
cacf1ca8 5416(define_insn "*fnmsubsf4_powerpc_1"
cd2b37d9
RK		 5417 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5418 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5419 (match_operand:SF 2 "gpc_reg_operand" "f"))
5420 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694 5421 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
696e45ba 5422 && TARGET_SINGLE_FLOAT && HONOR_SIGNED_ZEROS (SFmode)"
16823694 5423 "fnmsubs %0,%1,%2,%3"
0bb7b92e
ME		 5424 [(set_attr "type" "fp")
5425 (set_attr "fp_type" "fp_maddsub_s")])
16823694 5426
cacf1ca8 5427(define_insn "*fnmsubsf4_powerpc_2"
16823694
GK		 5428 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5429 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5430 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5431 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5432 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
696e45ba 5433 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5434 "fnmsubs %0,%1,%2,%3"
0bb7b92e
ME		 5435 [(set_attr "type" "fp")
5436 (set_attr "fp_type" "fp_maddsub_s")])
ca7f5001 5437
cacf1ca8 5438(define_insn "*fnmsubsf4_power_1"
ca7f5001
RK		 5439 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5440 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5441 (match_operand:SF 2 "gpc_reg_operand" "f"))
5442 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
e47911ce 5443 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5444 "{fnms|fnmsub} %0,%1,%2,%3"
e47911ce 5445 [(set_attr "type" "dmul")])
1fd4e8c1 5446
cacf1ca8 5447(define_insn "*fnmsubsf4_power_2"
16823694
GK		 5448 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5449 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5450 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5451 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5452 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
e47911ce 5453 && ! HONOR_SIGNED_ZEROS (SFmode)"
16823694 5454 "{fnms|fnmsub} %0,%1,%2,%3"
9c6fdb46 5455 [(set_attr "type" "dmul")])
16823694 5456
ca7f5001
RK		 5457(define_expand "sqrtsf2"
5458 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5459 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
e47911ce
DE		 5460 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5461 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
696e45ba 5462 && !TARGET_SIMPLE_FPU"
ca7f5001
RK		 5463 "")
5464
5465(define_insn ""
5466 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5467 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
e47911ce 5468 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
696e45ba 5469 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
ca7f5001
RK		 5470 "fsqrts %0,%1"
5471 [(set_attr "type" "ssqrt")])
5472
5473(define_insn ""
5474 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5475 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
696e45ba
ME		 5476 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5477 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
ca7f5001
RK		 5478 "fsqrt %0,%1"
5479 [(set_attr "type" "dsqrt")])
5480
9c78b944
DE		 5481(define_expand "rsqrtsf2"
5482 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5483 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5484 UNSPEC_RSQRT))]
5485 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5486 && flag_finite_math_only && !flag_trapping_math"
5487{
5488 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5489 DONE;
5490})
5491
5492(define_insn "*rsqrt_internal1"
5493 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5494 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5495 UNSPEC_RSQRT))]
5496 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5497 "frsqrte %0,%1"
5498 [(set_attr "type" "fp")])
5499
0530bc70
AP		 5500(define_expand "copysignsf3"
5501 [(set (match_dup 3)
5502 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5503 (set (match_dup 4)
5504 (neg:SF (abs:SF (match_dup 1))))
5505 (set (match_operand:SF 0 "gpc_reg_operand" "")
5506 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5507 (match_dup 5))
5508 (match_dup 3)
5509 (match_dup 4)))]
696e45ba 5510 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
bb8df8a6 5511 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
0530bc70
AP		 5512 {
5513 operands[3] = gen_reg_rtx (SFmode);
5514 operands[4] = gen_reg_rtx (SFmode);
5515 operands[5] = CONST0_RTX (SFmode);
5516 })
5517
5518(define_expand "copysigndf3"
5519 [(set (match_dup 3)
5520 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5521 (set (match_dup 4)
5522 (neg:DF (abs:DF (match_dup 1))))
5523 (set (match_operand:DF 0 "gpc_reg_operand" "")
5524 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5525 (match_dup 5))
5526 (match_dup 3)
5527 (match_dup 4)))]
696e45ba 5528 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
0530bc70
AP		 5529 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5530 {
5531 operands[3] = gen_reg_rtx (DFmode);
5532 operands[4] = gen_reg_rtx (DFmode);
5533 operands[5] = CONST0_RTX (DFmode);
5534 })
5535
94d7001a
RK		 5536;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5537;; fsel instruction and some auxiliary computations. Then we just have a
5538;; single DEFINE_INSN for fsel and the define_splits to make them if made by
8e871c05 5539;; combine.
7ae4d8d4 5540(define_expand "smaxsf3"
8e871c05 5541 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5542 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5543 (match_operand:SF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5544 (match_dup 1)
5545 (match_dup 2)))]
696e45ba
ME		 5546 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5547 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
50a0b056 5548 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
2f607b94 5549
7ae4d8d4 5550(define_expand "sminsf3"
50a0b056
GK		 5551 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5552 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5553 (match_operand:SF 2 "gpc_reg_operand" ""))
5554 (match_dup 2)
5555 (match_dup 1)))]
696e45ba
ME		 5556 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5557 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
50a0b056 5558 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
2f607b94 5559
8e871c05
RK		 5560(define_split
5561 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5562 (match_operator:SF 3 "min_max_operator"
5563 [(match_operand:SF 1 "gpc_reg_operand" "")
5564 (match_operand:SF 2 "gpc_reg_operand" "")]))]
696e45ba
ME		 5565 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5566 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
50a0b056
GK		 5567 [(const_int 0)]
5568 "
6ae08853 5569{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5570 operands[1], operands[2]);
5571 DONE;
5572}")
2f607b94 5573
cacf1ca8
MM		 5574(define_expand "mov<mode>cc"
5575 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5576 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5577 (match_operand:GPR 2 "gpc_reg_operand" "")
5578 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5579 "TARGET_ISEL<sel>"
a3170dc6
AH		 5580 "
5581{
5582 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5583 DONE;
5584 else
5585 FAIL;
5586}")
5587
5588;; We use the BASE_REGS for the isel input operands because, if rA is
5589;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5590;; because we may switch the operands and rB may end up being rA.
5591;;
5592;; We need 2 patterns: an unsigned and a signed pattern. We could
5593;; leave out the mode in operand 4 and use one pattern, but reload can
5594;; change the mode underneath our feet and then gets confused trying
5595;; to reload the value.
cacf1ca8
MM		 5596(define_insn "isel_signed_<mode>"
5597 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5598 (if_then_else:GPR
a3170dc6
AH		 5599 (match_operator 1 "comparison_operator"
5600 [(match_operand:CC 4 "cc_reg_operand" "y")
5601 (const_int 0)])
cacf1ca8
MM		 5602 (match_operand:GPR 2 "gpc_reg_operand" "b")
5603 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5604 "TARGET_ISEL<sel>"
a3170dc6
AH		 5605 "*
5606{ return output_isel (operands); }"
5607 [(set_attr "length" "4")])
5608
cacf1ca8
MM		 5609(define_insn "isel_unsigned_<mode>"
5610 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5611 (if_then_else:GPR
a3170dc6
AH		 5612 (match_operator 1 "comparison_operator"
5613 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5614 (const_int 0)])
cacf1ca8
MM		 5615 (match_operand:GPR 2 "gpc_reg_operand" "b")
5616 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5617 "TARGET_ISEL<sel>"
a3170dc6
AH		 5618 "*
5619{ return output_isel (operands); }"
5620 [(set_attr "length" "4")])
5621
94d7001a 5622(define_expand "movsfcc"
0ad91047 5623 [(set (match_operand:SF 0 "gpc_reg_operand" "")
94d7001a 5624 (if_then_else:SF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5625 (match_operand:SF 2 "gpc_reg_operand" "")
5626 (match_operand:SF 3 "gpc_reg_operand" "")))]
696e45ba 5627 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
94d7001a
RK		 5628 "
5629{
50a0b056
GK		 5630 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5631 DONE;
94d7001a 5632 else
50a0b056 5633 FAIL;
94d7001a 5634}")
d56d506a 5635
50a0b056 5636(define_insn "*fselsfsf4"
8e871c05
RK		 5637 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5638 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5639 (match_operand:SF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5640 (match_operand:SF 2 "gpc_reg_operand" "f")
5641 (match_operand:SF 3 "gpc_reg_operand" "f")))]
696e45ba 5642 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
8e871c05
RK		 5643 "fsel %0,%1,%2,%3"
5644 [(set_attr "type" "fp")])
2f607b94 5645
50a0b056 5646(define_insn "*fseldfsf4"
94d7001a 5647 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
799dbb0f 5648 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
d365ba42 5649 (match_operand:DF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5650 (match_operand:SF 2 "gpc_reg_operand" "f")
5651 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3a86d13b 5652 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
94d7001a
RK		 5653 "fsel %0,%1,%2,%3"
5654 [(set_attr "type" "fp")])
d56d506a 5655
7a2f7870
AH		 5656(define_expand "negdf2"
5657 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5658 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
696e45ba 5659 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5660 "")
5661
99176a91 5662(define_insn "*negdf2_fpr"
799dbb0f
ME		 5663 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5664 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
696e45ba 5665 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
1fd4e8c1
RK		 5666 "fneg %0,%1"
5667 [(set_attr "type" "fp")])
5668
7a2f7870
AH		 5669(define_expand "absdf2"
5670 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5671 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
696e45ba 5672 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5673 "")
5674
99176a91 5675(define_insn "*absdf2_fpr"
799dbb0f
ME		 5676 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5677 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
696e45ba 5678 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
1fd4e8c1
RK		 5679 "fabs %0,%1"
5680 [(set_attr "type" "fp")])
5681
99176a91 5682(define_insn "*nabsdf2_fpr"
799dbb0f
ME		 5683 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5684 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
696e45ba 5685 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
1fd4e8c1
RK		 5686 "fnabs %0,%1"
5687 [(set_attr "type" "fp")])
5688
7a2f7870
AH		 5689(define_expand "adddf3"
5690 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5691 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5692 (match_operand:DF 2 "gpc_reg_operand" "")))]
696e45ba 5693 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5694 "")
5695
99176a91 5696(define_insn "*adddf3_fpr"
799dbb0f
ME		 5697 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5698 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5699 (match_operand:DF 2 "gpc_reg_operand" "d")))]
696e45ba 5700 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
ca7f5001 5701 "{fa|fadd} %0,%1,%2"
0bb7b92e
ME		 5702 [(set_attr "type" "fp")
5703 (set_attr "fp_type" "fp_addsub_d")])
1fd4e8c1 5704
7a2f7870
AH		 5705(define_expand "subdf3"
5706 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5707 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5708 (match_operand:DF 2 "gpc_reg_operand" "")))]
696e45ba 5709 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5710 "")
5711
99176a91 5712(define_insn "*subdf3_fpr"
799dbb0f
ME		 5713 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5714 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5715 (match_operand:DF 2 "gpc_reg_operand" "d")))]
696e45ba 5716 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
ca7f5001 5717 "{fs|fsub} %0,%1,%2"
0bb7b92e
ME		 5718 [(set_attr "type" "fp")
5719 (set_attr "fp_type" "fp_addsub_d")])
1fd4e8c1 5720
7a2f7870
AH		 5721(define_expand "muldf3"
5722 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5723 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5724 (match_operand:DF 2 "gpc_reg_operand" "")))]
696e45ba 5725 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5726 "")
5727
99176a91 5728(define_insn "*muldf3_fpr"
799dbb0f
ME		 5729 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5730 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5731 (match_operand:DF 2 "gpc_reg_operand" "d")))]
696e45ba 5732 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
ca7f5001 5733 "{fm|fmul} %0,%1,%2"
0bb7b92e
ME		 5734 [(set_attr "type" "dmul")
5735 (set_attr "fp_type" "fp_mul_d")])
5736
7a2f7870
AH		 5737(define_expand "divdf3"
5738 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5739 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5740 (match_operand:DF 2 "gpc_reg_operand" "")))]
e47911ce
DE		 5741 "TARGET_HARD_FLOAT
5742 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
5743 && !TARGET_SIMPLE_FPU"
9c78b944 5744 "")
7a2f7870 5745
99176a91 5746(define_insn "*divdf3_fpr"
799dbb0f
ME		 5747 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5748 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5749 (match_operand:DF 2 "gpc_reg_operand" "d")))]
696e45ba 5750 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU"
ca7f5001 5751 "{fd|fdiv} %0,%1,%2"
cfb557c4 5752 [(set_attr "type" "ddiv")])
1fd4e8c1 5753
9c78b944 5754(define_expand "recipdf3"
799dbb0f
ME		 5755 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5756 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")
5757 (match_operand:DF 2 "gpc_reg_operand" "d")]
9c78b944
DE		 5758 UNSPEC_FRES))]
5759 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
5760 && flag_finite_math_only && !flag_trapping_math"
5761{
5762 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5763 DONE;
5764})
5765
5766(define_insn "fred"
799dbb0f
ME		 5767 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5768 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRES))]
9c78b944
DE		 5769 "TARGET_POPCNTB && flag_finite_math_only"
5770 "fre %0,%1"
5771 [(set_attr "type" "fp")])
5772
1fd4e8c1 5773(define_insn ""
799dbb0f
ME		 5774 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5775 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5776 (match_operand:DF 2 "gpc_reg_operand" "d"))
5777 (match_operand:DF 3 "gpc_reg_operand" "d")))]
696e45ba 5778 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
ca7f5001 5779 "{fma|fmadd} %0,%1,%2,%3"
0bb7b92e
ME		 5780 [(set_attr "type" "dmul")
5781 (set_attr "fp_type" "fp_maddsub_d")])
1fd4e8c1
RK		 5782
5783(define_insn ""
799dbb0f
ME		 5784 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5785 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5786 (match_operand:DF 2 "gpc_reg_operand" "d"))
5787 (match_operand:DF 3 "gpc_reg_operand" "d")))]
696e45ba 5788 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT"
ca7f5001 5789 "{fms|fmsub} %0,%1,%2,%3"
0bb7b92e
ME		 5790 [(set_attr "type" "dmul")
5791 (set_attr "fp_type" "fp_maddsub_d")])
1fd4e8c1
RK		 5792
5793(define_insn ""
799dbb0f
ME		 5794 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5795 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5796 (match_operand:DF 2 "gpc_reg_operand" "d"))
5797 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
696e45ba 5798 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
16823694
GK		 5799 && HONOR_SIGNED_ZEROS (DFmode)"
5800 "{fnma|fnmadd} %0,%1,%2,%3"
0bb7b92e
ME		 5801 [(set_attr "type" "dmul")
5802 (set_attr "fp_type" "fp_maddsub_d")])
16823694
GK		 5803
5804(define_insn ""
799dbb0f
ME		 5805 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5806 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d"))
5807 (match_operand:DF 2 "gpc_reg_operand" "d"))
5808 (match_operand:DF 3 "gpc_reg_operand" "d")))]
696e45ba 5809 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
16823694 5810 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5811 "{fnma|fnmadd} %0,%1,%2,%3"
0bb7b92e
ME		 5812 [(set_attr "type" "dmul")
5813 (set_attr "fp_type" "fp_maddsub_d")])
1fd4e8c1
RK		 5814
5815(define_insn ""
799dbb0f
ME		 5816 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5817 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5818 (match_operand:DF 2 "gpc_reg_operand" "d"))
5819 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
696e45ba 5820 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
16823694
GK		 5821 && HONOR_SIGNED_ZEROS (DFmode)"
5822 "{fnms|fnmsub} %0,%1,%2,%3"
0bb7b92e
ME		 5823 [(set_attr "type" "dmul")
5824 (set_attr "fp_type" "fp_maddsub_d")])
16823694
GK		 5825
5826(define_insn ""
799dbb0f
ME		 5827 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5828 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "d")
5829 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5830 (match_operand:DF 2 "gpc_reg_operand" "d"))))]
696e45ba 5831 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
16823694 5832 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5833 "{fnms|fnmsub} %0,%1,%2,%3"
0bb7b92e
ME		 5834 [(set_attr "type" "dmul")
5835 (set_attr "fp_type" "fp_maddsub_d")])
ca7f5001
RK		 5836
5837(define_insn "sqrtdf2"
799dbb0f
ME		 5838 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5839 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
696e45ba
ME		 5840 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
5841 && TARGET_DOUBLE_FLOAT"
ca7f5001
RK		 5842 "fsqrt %0,%1"
5843 [(set_attr "type" "dsqrt")])
b77dfefc 5844
50a0b056 5845;; The conditional move instructions allow us to perform max and min
6ae08853 5846;; operations even when
b77dfefc 5847
7ae4d8d4 5848(define_expand "smaxdf3"
8e871c05 5849 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5850 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5851 (match_operand:DF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5852 (match_dup 1)
5853 (match_dup 2)))]
696e45ba
ME		 5854 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5855 && !flag_trapping_math"
50a0b056 5856 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
b77dfefc 5857
7ae4d8d4 5858(define_expand "smindf3"
50a0b056
GK		 5859 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5860 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5861 (match_operand:DF 2 "gpc_reg_operand" ""))
5862 (match_dup 2)
5863 (match_dup 1)))]
696e45ba
ME		 5864 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5865 && !flag_trapping_math"
50a0b056 5866 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
b77dfefc 5867
8e871c05
RK		 5868(define_split
5869 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5870 (match_operator:DF 3 "min_max_operator"
5871 [(match_operand:DF 1 "gpc_reg_operand" "")
5872 (match_operand:DF 2 "gpc_reg_operand" "")]))]
696e45ba
ME		 5873 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5874 && !flag_trapping_math"
50a0b056
GK		 5875 [(const_int 0)]
5876 "
6ae08853 5877{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5878 operands[1], operands[2]);
5879 DONE;
5880}")
b77dfefc 5881
94d7001a 5882(define_expand "movdfcc"
0ad91047 5883 [(set (match_operand:DF 0 "gpc_reg_operand" "")
94d7001a 5884 (if_then_else:DF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5885 (match_operand:DF 2 "gpc_reg_operand" "")
5886 (match_operand:DF 3 "gpc_reg_operand" "")))]
696e45ba 5887 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
94d7001a
RK		 5888 "
5889{
50a0b056
GK		 5890 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5891 DONE;
94d7001a 5892 else
50a0b056 5893 FAIL;
94d7001a 5894}")
d56d506a 5895
50a0b056 5896(define_insn "*fseldfdf4"
799dbb0f
ME		 5897 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5898 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
50a0b056 5899 (match_operand:DF 4 "zero_fp_constant" "F"))
799dbb0f
ME		 5900 (match_operand:DF 2 "gpc_reg_operand" "d")
5901 (match_operand:DF 3 "gpc_reg_operand" "d")))]
696e45ba 5902 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8e871c05
RK		 5903 "fsel %0,%1,%2,%3"
5904 [(set_attr "type" "fp")])
d56d506a 5905
50a0b056 5906(define_insn "*fselsfdf4"
799dbb0f 5907 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
94d7001a 5908 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5909 (match_operand:SF 4 "zero_fp_constant" "F"))
799dbb0f
ME		 5910 (match_operand:DF 2 "gpc_reg_operand" "d")
5911 (match_operand:DF 3 "gpc_reg_operand" "d")))]
3a86d13b 5912 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
94d7001a
RK		 5913 "fsel %0,%1,%2,%3"
5914 [(set_attr "type" "fp")])
1fd4e8c1 5915\f
d095928f
AH		 5916;; Conversions to and from floating-point.
5917
5918(define_expand "fixuns_truncsfsi2"
5919 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5920 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
696e45ba 5921 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
d095928f
AH		 5922 "")
5923
5924(define_expand "fix_truncsfsi2"
0bb7b92e
ME		 5925 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5926 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5927 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
5928 "")
d095928f 5929
cacf1ca8
MM		 5930(define_expand "fixuns_truncdfsi2"
5931 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5932 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
5933 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
5934 "")
5935
9ebbca7d
GK		 5936; For each of these conversions, there is a define_expand, a define_insn
5937; with a '#' template, and a define_split (with C code). The idea is
5938; to allow constant folding with the template of the define_insn,
5939; then to have the insns split later (between sched1 and final).
5940
1fd4e8c1 5941(define_expand "floatsidf2"
802a0058
MM		 5942 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5943 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5944 (use (match_dup 2))
5945 (use (match_dup 3))
208c89ce 5946 (clobber (match_dup 4))
a7df97e6 5947 (clobber (match_dup 5))
9ebbca7d 5948 (clobber (match_dup 6))])]
696e45ba
ME		 5949 "TARGET_HARD_FLOAT
5950 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5951 "
5952{
99176a91
AH		 5953 if (TARGET_E500_DOUBLE)
5954 {
5955 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5956 DONE;
5957 }
05d49501
AM		 5958 if (TARGET_POWERPC64)
5959 {
f369bbb1
AP		 5960 rtx x = convert_to_mode (DImode, operands[1], 0);
5961 emit_insn (gen_floatdidf2 (operands[0], x));
05d49501
AM		 5962 DONE;
5963 }
5964
802a0058 5965 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5966 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
9ebbca7d
GK		 5967 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5968 operands[5] = gen_reg_rtx (DFmode);
5969 operands[6] = gen_reg_rtx (SImode);
1fd4e8c1
RK		 5970}")
5971
230215f5 5972(define_insn_and_split "*floatsidf2_internal"
799dbb0f 5973 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
802a0058
MM		 5974 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5975 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
799dbb0f 5976 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
b0d6c7d8 5977 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
799dbb0f 5978 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
6f9c81f5 5979 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
696e45ba 5980 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
802a0058 5981 "#"
b3a13419 5982 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
230215f5 5983 [(pc)]
208c89ce
MM		 5984 "
5985{
9ebbca7d 5986 rtx lowword, highword;
230215f5
GK		 5987 gcc_assert (MEM_P (operands[4]));
5988 highword = adjust_address (operands[4], SImode, 0);
5989 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d
GK		 5990 if (! WORDS_BIG_ENDIAN)
5991 {
5992 rtx tmp;
5993 tmp = highword; highword = lowword; lowword = tmp;
5994 }
5995
6ae08853 5996 emit_insn (gen_xorsi3 (operands[6], operands[1],
9ebbca7d 5997 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
230215f5
GK		 5998 emit_move_insn (lowword, operands[6]);
5999 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 6000 emit_move_insn (operands[5], operands[4]);
6001 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6002 DONE;
230215f5
GK		 6003}"
6004 [(set_attr "length" "24")])
802a0058 6005
a3170dc6
AH		 6006(define_expand "floatunssisf2"
6007 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6008 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
696e45ba 6009 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
a3170dc6
AH		 6010 "")
6011
802a0058
MM		 6012(define_expand "floatunssidf2"
6013 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6014 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6015 (use (match_dup 2))
6016 (use (match_dup 3))
a7df97e6 6017 (clobber (match_dup 4))
9ebbca7d 6018 (clobber (match_dup 5))])]
696e45ba 6019 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 6020 "
6021{
99176a91
AH		 6022 if (TARGET_E500_DOUBLE)
6023 {
6024 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6025 DONE;
6026 }
05d49501
AM		 6027 if (TARGET_POWERPC64)
6028 {
f369bbb1
AP		 6029 rtx x = convert_to_mode (DImode, operands[1], 1);
6030 emit_insn (gen_floatdidf2 (operands[0], x));
05d49501
AM		 6031 DONE;
6032 }
6033
802a0058 6034 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 6035 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
9ebbca7d
GK		 6036 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6037 operands[5] = gen_reg_rtx (DFmode);
1fd4e8c1
RK		 6038}")
6039
230215f5 6040(define_insn_and_split "*floatunssidf2_internal"
799dbb0f 6041 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
802a0058
MM		 6042 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6043 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
799dbb0f 6044 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
b0d6c7d8 6045 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
799dbb0f 6046 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
696e45ba 6047 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
802a0058 6048 "#"
b3a13419 6049 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
230215f5 6050 [(pc)]
9ebbca7d 6051 "
802a0058 6052{
9ebbca7d 6053 rtx lowword, highword;
230215f5
GK		 6054 gcc_assert (MEM_P (operands[4]));
6055 highword = adjust_address (operands[4], SImode, 0);
6056 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d 6057 if (! WORDS_BIG_ENDIAN)
f6968f59 6058 {
9ebbca7d
GK		 6059 rtx tmp;
6060 tmp = highword; highword = lowword; lowword = tmp;
f6968f59 6061 }
802a0058 6062
230215f5
GK		 6063 emit_move_insn (lowword, operands[1]);
6064 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 6065 emit_move_insn (operands[5], operands[4]);
6066 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6067 DONE;
230215f5
GK		 6068}"
6069 [(set_attr "length" "20")])
1fd4e8c1 6070
1fd4e8c1 6071(define_expand "fix_truncdfsi2"
045a8eb3 6072 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
802a0058
MM		 6073 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
6074 (clobber (match_dup 2))
9ebbca7d 6075 (clobber (match_dup 3))])]
99176a91 6076 "(TARGET_POWER2 || TARGET_POWERPC)
696e45ba 6077 && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 6078 "
6079{
99176a91
AH		 6080 if (TARGET_E500_DOUBLE)
6081 {
6082 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
6083 DONE;
6084 }
802a0058 6085 operands[2] = gen_reg_rtx (DImode);
44cd321e
PS		 6086 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6087 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
6088 {
6089 operands[3] = gen_reg_rtx (DImode);
6090 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
6091 operands[2], operands[3]));
6092 DONE;
6093 }
da4c340c
GK		 6094 if (TARGET_PPC_GFXOPT)
6095 {
6096 rtx orig_dest = operands[0];
045a8eb3 6097 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
da4c340c
GK		 6098 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
6099 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
6100 operands[2]));
6101 if (operands[0] != orig_dest)
6102 emit_move_insn (orig_dest, operands[0]);
6103 DONE;
6104 }
9ebbca7d 6105 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
1fd4e8c1
RK		 6106}")
6107
da4c340c 6108(define_insn_and_split "*fix_truncdfsi2_internal"
802a0058 6109 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
799dbb0f
ME		 6110 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6111 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
b0d6c7d8 6112 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
696e45ba
ME		 6113 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6114 && TARGET_DOUBLE_FLOAT"
802a0058 6115 "#"
b3a13419 6116 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
da4c340c 6117 [(pc)]
9ebbca7d 6118 "
802a0058 6119{
9ebbca7d 6120 rtx lowword;
230215f5
GK		 6121 gcc_assert (MEM_P (operands[3]));
6122 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
802a0058 6123
9ebbca7d
GK		 6124 emit_insn (gen_fctiwz (operands[2], operands[1]));
6125 emit_move_insn (operands[3], operands[2]);
230215f5 6126 emit_move_insn (operands[0], lowword);
9ebbca7d 6127 DONE;
da4c340c
GK		 6128}"
6129 [(set_attr "length" "16")])
6130
6131(define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6132 [(set (match_operand:SI 0 "memory_operand" "=Z")
799dbb0f
ME		 6133 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6134 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))]
696e45ba
ME		 6135 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6136 && TARGET_DOUBLE_FLOAT
da4c340c
GK		 6137 && TARGET_PPC_GFXOPT"
6138 "#"
6139 "&& 1"
6140 [(pc)]
6141 "
6142{
6143 emit_insn (gen_fctiwz (operands[2], operands[1]));
6144 emit_insn (gen_stfiwx (operands[0], operands[2]));
6145 DONE;
6146}"
6147 [(set_attr "length" "16")])
802a0058 6148
44cd321e
PS		 6149(define_insn_and_split "fix_truncdfsi2_mfpgpr"
6150 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
799dbb0f
ME		 6151 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6152 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
44cd321e 6153 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
696e45ba
ME		 6154 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6155 && TARGET_DOUBLE_FLOAT"
44cd321e
PS		 6156 "#"
6157 "&& 1"
6158 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6159 (set (match_dup 3) (match_dup 2))
6160 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6161 ""
6162 [(set_attr "length" "12")])
6163
615158e2 6164; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
9ebbca7d
GK		 6165; rather than (set (subreg:SI (reg)) (fix:SI ...))
6166; because the first makes it clear that operand 0 is not live
6167; before the instruction.
6168(define_insn "fctiwz"
799dbb0f
ME		 6169 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6170 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))]
615158e2 6171 UNSPEC_FCTIWZ))]
696e45ba
ME		 6172 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6173 && TARGET_DOUBLE_FLOAT"
a260abc9
DE		 6174 "{fcirz|fctiwz} %0,%1"
6175 [(set_attr "type" "fp")])
6176
9719f3b7 6177(define_insn "btruncdf2"
799dbb0f
ME		 6178 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6179 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIZ))]
696e45ba 6180 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9719f3b7
DE		 6181 "friz %0,%1"
6182 [(set_attr "type" "fp")])
6183
6184(define_insn "btruncsf2"
6185 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6186 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
696e45ba 6187 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
833126ad 6188 "friz %0,%1"
9719f3b7
DE		 6189 [(set_attr "type" "fp")])
6190
6191(define_insn "ceildf2"
799dbb0f
ME		 6192 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6193 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIP))]
696e45ba 6194 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9719f3b7
DE		 6195 "frip %0,%1"
6196 [(set_attr "type" "fp")])
6197
6198(define_insn "ceilsf2"
833126ad 6199 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9719f3b7 6200 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
696e45ba 6201 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
833126ad 6202 "frip %0,%1"
9719f3b7
DE		 6203 [(set_attr "type" "fp")])
6204
6205(define_insn "floordf2"
799dbb0f
ME		 6206 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6207 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIM))]
696e45ba 6208 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9719f3b7
DE		 6209 "frim %0,%1"
6210 [(set_attr "type" "fp")])
6211
6212(define_insn "floorsf2"
6213 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6214 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
696e45ba 6215 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
833126ad 6216 "frim %0,%1"
9719f3b7
DE		 6217 [(set_attr "type" "fp")])
6218
6219(define_insn "rounddf2"
799dbb0f
ME		 6220 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6221 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIN))]
696e45ba 6222 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9719f3b7
DE		 6223 "frin %0,%1"
6224 [(set_attr "type" "fp")])
6225
6226(define_insn "roundsf2"
6227 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6228 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
696e45ba 6229 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
833126ad 6230 "frin %0,%1"
9719f3b7
DE		 6231 [(set_attr "type" "fp")])
6232
da4c340c
GK		 6233; An UNSPEC is used so we don't have to support SImode in FP registers.
6234(define_insn "stfiwx"
6235 [(set (match_operand:SI 0 "memory_operand" "=Z")
799dbb0f 6236 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
da4c340c
GK		 6237 UNSPEC_STFIWX))]
6238 "TARGET_PPC_GFXOPT"
6239 "stfiwx %1,%y0"
6240 [(set_attr "type" "fpstore")])
6241
a3170dc6
AH		 6242(define_expand "floatsisf2"
6243 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6244 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
0bb7b92e 6245 "TARGET_HARD_FLOAT && !TARGET_FPRS"
a3170dc6
AH		 6246 "")
6247
a473029f 6248(define_insn "floatdidf2"
799dbb0f
ME		 6249 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6250 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))]
0bb7b92e 6251 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
a473029f
RK		 6252 "fcfid %0,%1"
6253 [(set_attr "type" "fp")])
6254
6255(define_insn "fix_truncdfdi2"
799dbb0f
ME		 6256 [(set (match_operand:DI 0 "gpc_reg_operand" "=!d#r")
6257 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d")))]
0bb7b92e 6258 "(TARGET_POWERPC64 || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
a473029f
RK		 6259 "fctidz %0,%1"
6260 [(set_attr "type" "fp")])
ea112fc4 6261
678b7733
AM		 6262(define_expand "floatdisf2"
6263 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6264 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
696e45ba 6265 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
678b7733
AM		 6266 "
6267{
994cf173 6268 rtx val = operands[1];
678b7733
AM		 6269 if (!flag_unsafe_math_optimizations)
6270 {
6271 rtx label = gen_label_rtx ();
994cf173
AM		 6272 val = gen_reg_rtx (DImode);
6273 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
678b7733
AM		 6274 emit_label (label);
6275 }
994cf173 6276 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
678b7733
AM		 6277 DONE;
6278}")
6279
6280;; This is not IEEE compliant if rounding mode is "round to nearest".
6281;; If the DI->DF conversion is inexact, then it's possible to suffer
6282;; from double rounding.
6283(define_insn_and_split "floatdisf2_internal1"
ea112fc4 6284 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
799dbb0f
ME		 6285 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))
6286 (clobber (match_scratch:DF 2 "=d"))]
696e45ba 6287 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
ea112fc4
DE		 6288 "#"
6289 "&& reload_completed"
6290 [(set (match_dup 2)
6291 (float:DF (match_dup 1)))
6292 (set (match_dup 0)
6293 (float_truncate:SF (match_dup 2)))]
6294 "")
678b7733
AM		 6295
6296;; Twiddles bits to avoid double rounding.
b6d08ca1 6297;; Bits that might be truncated when converting to DFmode are replaced
678b7733
AM		 6298;; by a bit that won't be lost at that stage, but is below the SFmode
6299;; rounding position.
6300(define_expand "floatdisf2_internal2"
994cf173
AM		 6301 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6302 (const_int 53)))
6303 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6304 (const_int 2047)))
6305 (clobber (scratch:CC))])
6306 (set (match_dup 3) (plus:DI (match_dup 3)
6307 (const_int 1)))
6308 (set (match_dup 0) (plus:DI (match_dup 0)
6309 (const_int 2047)))
6310 (set (match_dup 4) (compare:CCUNS (match_dup 3)
c22e62a6 6311 (const_int 2)))
994cf173
AM		 6312 (set (match_dup 0) (ior:DI (match_dup 0)
6313 (match_dup 1)))
6314 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6315 (const_int -2048)))
6316 (clobber (scratch:CC))])
6317 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6318 (label_ref (match_operand:DI 2 "" ""))
678b7733 6319 (pc)))
994cf173 6320 (set (match_dup 0) (match_dup 1))]
696e45ba 6321 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
678b7733
AM		 6322 "
6323{
678b7733 6324 operands[3] = gen_reg_rtx (DImode);
994cf173 6325 operands[4] = gen_reg_rtx (CCUNSmode);
678b7733 6326}")
1fd4e8c1
RK		 6327\f
6328;; Define the DImode operations that can be done in a small number
a6ec530c
RK		 6329;; of instructions. The & constraints are to prevent the register
6330;; allocator from allocating registers that overlap with the inputs
6331;; (for example, having an input in 7,8 and an output in 6,7). We
38e01259 6332;; also allow for the output being the same as one of the inputs.
a6ec530c 6333
266eb58a 6334(define_insn "*adddi3_noppc64"
a6ec530c
RK		 6335 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6336 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6337 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
e1f83b4d 6338 "! TARGET_POWERPC64"
0f645302
MM		 6339 "*
6340{
6341 if (WORDS_BIG_ENDIAN)
6342 return (GET_CODE (operands[2])) != CONST_INT
6343 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6344 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6345 else
6346 return (GET_CODE (operands[2])) != CONST_INT
6347 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6348 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6349}"
943c15ed
DE		 6350 [(set_attr "type" "two")
6351 (set_attr "length" "8")])
1fd4e8c1 6352
266eb58a 6353(define_insn "*subdi3_noppc64"
e7e5df70
RK		 6354 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6355 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6356 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
266eb58a 6357 "! TARGET_POWERPC64"
5502823b
RK		 6358 "*
6359{
0f645302
MM		 6360 if (WORDS_BIG_ENDIAN)
6361 return (GET_CODE (operands[1]) != CONST_INT)
6362 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6363 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6364 else
6365 return (GET_CODE (operands[1]) != CONST_INT)
6366 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6367 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5502823b 6368}"
943c15ed
DE		 6369 [(set_attr "type" "two")
6370 (set_attr "length" "8")])
ca7f5001 6371
266eb58a 6372(define_insn "*negdi2_noppc64"
a6ec530c
RK		 6373 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6374 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
51b8fc2c 6375 "! TARGET_POWERPC64"
5502823b
RK		 6376 "*
6377{
6378 return (WORDS_BIG_ENDIAN)
6379 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6380 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6381}"
943c15ed
DE		 6382 [(set_attr "type" "two")
6383 (set_attr "length" "8")])
ca7f5001 6384
8ffd9c51
RK		 6385(define_expand "mulsidi3"
6386 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6387 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6388 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
a2f270cc 6389 "! TARGET_POWERPC64"
8ffd9c51
RK		 6390 "
6391{
6392 if (! TARGET_POWER && ! TARGET_POWERPC)
6393 {
39403d82
DE		 6394 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6395 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6396 emit_insn (gen_mull_call ());
cf27b467 6397 if (WORDS_BIG_ENDIAN)
39403d82 6398 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
cf27b467
MM		 6399 else
6400 {
6401 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
39403d82 6402 gen_rtx_REG (SImode, 3));
cf27b467 6403 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
39403d82 6404 gen_rtx_REG (SImode, 4));
cf27b467 6405 }
8ffd9c51
RK		 6406 DONE;
6407 }
6408 else if (TARGET_POWER)
6409 {
6410 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6411 DONE;
6412 }
6413}")
deb9225a 6414
8ffd9c51 6415(define_insn "mulsidi3_mq"
cd2b37d9 6416 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8ffd9c51 6417 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
cd2b37d9 6418 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1fd4e8c1 6419 (clobber (match_scratch:SI 3 "=q"))]
ca7f5001 6420 "TARGET_POWER"
b19003d8 6421 "mul %0,%1,%2\;mfmq %L0"
8ffd9c51
RK		 6422 [(set_attr "type" "imul")
6423 (set_attr "length" "8")])
deb9225a 6424
f192bf8b 6425(define_insn "*mulsidi3_no_mq"
425c176f 6426 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
8ffd9c51
RK		 6427 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6428 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6429 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5502823b
RK		 6430 "*
6431{
6432 return (WORDS_BIG_ENDIAN)
6433 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6434 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6435}"
8ffd9c51
RK		 6436 [(set_attr "type" "imul")
6437 (set_attr "length" "8")])
deb9225a 6438
ebedb4dd
MM		 6439(define_split
6440 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6441 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6442 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6443 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6444 [(set (match_dup 3)
6445 (truncate:SI
6446 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6447 (sign_extend:DI (match_dup 2)))
6448 (const_int 32))))
6449 (set (match_dup 4)
6450 (mult:SI (match_dup 1)
6451 (match_dup 2)))]
6452 "
6453{
6454 int endian = (WORDS_BIG_ENDIAN == 0);
6455 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6456 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6457}")
6458
f192bf8b
DE		 6459(define_expand "umulsidi3"
6460 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6461 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6462 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6463 "TARGET_POWERPC && ! TARGET_POWERPC64"
6464 "
6465{
6466 if (TARGET_POWER)
6467 {
6468 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6469 DONE;
6470 }
6471}")
6472
6473(define_insn "umulsidi3_mq"
6474 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6475 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6476 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6477 (clobber (match_scratch:SI 3 "=q"))]
6478 "TARGET_POWERPC && TARGET_POWER"
6479 "*
6480{
6481 return (WORDS_BIG_ENDIAN)
6482 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6483 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6484}"
6485 [(set_attr "type" "imul")
6486 (set_attr "length" "8")])
6487
6488(define_insn "*umulsidi3_no_mq"
8106dc08
MM		 6489 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6490 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6491 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6492 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
8106dc08
MM		 6493 "*
6494{
6495 return (WORDS_BIG_ENDIAN)
6496 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6497 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6498}"
6499 [(set_attr "type" "imul")
6500 (set_attr "length" "8")])
6501
ebedb4dd
MM		 6502(define_split
6503 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6504 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6505 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6506 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6507 [(set (match_dup 3)
6508 (truncate:SI
6509 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6510 (zero_extend:DI (match_dup 2)))
6511 (const_int 32))))
6512 (set (match_dup 4)
6513 (mult:SI (match_dup 1)
6514 (match_dup 2)))]
6515 "
6516{
6517 int endian = (WORDS_BIG_ENDIAN == 0);
6518 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6519 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6520}")
6521
8ffd9c51
RK		 6522(define_expand "smulsi3_highpart"
6523 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6524 (truncate:SI
6525 (lshiftrt:DI (mult:DI (sign_extend:DI
e42ac3de 6526 (match_operand:SI 1 "gpc_reg_operand" ""))
8ffd9c51 6527 (sign_extend:DI
e42ac3de 6528 (match_operand:SI 2 "gpc_reg_operand" "")))
8ffd9c51
RK		 6529 (const_int 32))))]
6530 ""
6531 "
6532{
6533 if (! TARGET_POWER && ! TARGET_POWERPC)
6534 {
39403d82
DE		 6535 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6536 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6537 emit_insn (gen_mulh_call ());
39403d82 6538 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 6539 DONE;
6540 }
6541 else if (TARGET_POWER)
6542 {
6543 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6544 DONE;
6545 }
6546}")
deb9225a 6547
8ffd9c51
RK		 6548(define_insn "smulsi3_highpart_mq"
6549 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6550 (truncate:SI
fada905b
MM		 6551 (lshiftrt:DI (mult:DI (sign_extend:DI
6552 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6553 (sign_extend:DI
6554 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51
RK		 6555 (const_int 32))))
6556 (clobber (match_scratch:SI 3 "=q"))]
6557 "TARGET_POWER"
6558 "mul %0,%1,%2"
6559 [(set_attr "type" "imul")])
deb9225a 6560
f192bf8b 6561(define_insn "*smulsi3_highpart_no_mq"
8ffd9c51
RK		 6562 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6563 (truncate:SI
fada905b
MM		 6564 (lshiftrt:DI (mult:DI (sign_extend:DI
6565 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6566 (sign_extend:DI
6567 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51 6568 (const_int 32))))]
f192bf8b 6569 "TARGET_POWERPC && ! TARGET_POWER"
8ffd9c51
RK		 6570 "mulhw %0,%1,%2"
6571 [(set_attr "type" "imul")])
deb9225a 6572
f192bf8b
DE		 6573(define_expand "umulsi3_highpart"
6574 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6575 (truncate:SI
6576 (lshiftrt:DI (mult:DI (zero_extend:DI
6577 (match_operand:SI 1 "gpc_reg_operand" ""))
6578 (zero_extend:DI
6579 (match_operand:SI 2 "gpc_reg_operand" "")))
6580 (const_int 32))))]
6581 "TARGET_POWERPC"
6582 "
6583{
6584 if (TARGET_POWER)
6585 {
6586 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6587 DONE;
6588 }
6589}")
6590
6591(define_insn "umulsi3_highpart_mq"
6592 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6593 (truncate:SI
6594 (lshiftrt:DI (mult:DI (zero_extend:DI
6595 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6596 (zero_extend:DI
6597 (match_operand:SI 2 "gpc_reg_operand" "r")))
6598 (const_int 32))))
6599 (clobber (match_scratch:SI 3 "=q"))]
6600 "TARGET_POWERPC && TARGET_POWER"
6601 "mulhwu %0,%1,%2"
6602 [(set_attr "type" "imul")])
6603
6604(define_insn "*umulsi3_highpart_no_mq"
266eb58a
DE		 6605 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6606 (truncate:SI
6607 (lshiftrt:DI (mult:DI (zero_extend:DI
6608 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6609 (zero_extend:DI
6610 (match_operand:SI 2 "gpc_reg_operand" "r")))
6611 (const_int 32))))]
f192bf8b 6612 "TARGET_POWERPC && ! TARGET_POWER"
266eb58a
DE		 6613 "mulhwu %0,%1,%2"
6614 [(set_attr "type" "imul")])
6615
6616;; If operands 0 and 2 are in the same register, we have a problem. But
6617;; operands 0 and 1 (the usual case) can be in the same register. That's
6618;; why we have the strange constraints below.
6619(define_insn "ashldi3_power"
6620 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6621 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6622 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6623 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6624 "TARGET_POWER"
6625 "@
6626 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6627 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6628 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6629 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6630 [(set_attr "length" "8")])
6631
6632(define_insn "lshrdi3_power"
47ad8c61 6633 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
266eb58a
DE		 6634 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6635 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6636 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6637 "TARGET_POWER"
6638 "@
47ad8c61 6639 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
266eb58a
DE		 6640 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6641 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6642 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6643 [(set_attr "length" "8")])
6644
6645;; Shift by a variable amount is too complex to be worth open-coding. We
6646;; just handle shifts by constants.
6647(define_insn "ashrdi3_power"
7093ddee 6648 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
266eb58a
DE		 6649 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6650 (match_operand:SI 2 "const_int_operand" "M,i")))
6651 (clobber (match_scratch:SI 3 "=X,q"))]
6652 "TARGET_POWER"
6653 "@
6654 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6655 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
44cd321e
PS		 6656 [(set_attr "type" "shift")
6657 (set_attr "length" "8")])
4aa74a4f
FS		 6658
6659(define_insn "ashrdi3_no_power"
6660 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6661 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6662 (match_operand:SI 2 "const_int_operand" "M,i")))]
97727e85 6663 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
4aa74a4f
FS		 6664 "@
6665 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6666 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
943c15ed
DE		 6667 [(set_attr "type" "two,three")
6668 (set_attr "length" "8,12")])
683bdff7
FJ		 6669
6670(define_insn "*ashrdisi3_noppc64"
6671 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6ae08853 6672 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
683bdff7
FJ		 6673 (const_int 32)) 4))]
6674 "TARGET_32BIT && !TARGET_POWERPC64"
6675 "*
6676{
6677 if (REGNO (operands[0]) == REGNO (operands[1]))
6678 return \"\";
6679 else
6680 return \"mr %0,%1\";
6681}"
6ae08853 6682 [(set_attr "length" "4")])
683bdff7 6683
266eb58a
DE		 6684\f
6685;; PowerPC64 DImode operations.
6686
ea112fc4 6687(define_insn_and_split "absdi2"
266eb58a 6688 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6689 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
266eb58a
DE		 6690 (clobber (match_scratch:DI 2 "=&r,&r"))]
6691 "TARGET_POWERPC64"
ea112fc4
DE		 6692 "#"
6693 "&& reload_completed"
a260abc9 6694 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6695 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
a238cd8b 6696 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
266eb58a
DE		 6697 "")
6698
ea112fc4 6699(define_insn_and_split "*nabsdi2"
266eb58a 6700 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6701 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
266eb58a
DE		 6702 (clobber (match_scratch:DI 2 "=&r,&r"))]
6703 "TARGET_POWERPC64"
ea112fc4
DE		 6704 "#"
6705 "&& reload_completed"
a260abc9 6706 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6707 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
19ba8161 6708 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
266eb58a
DE		 6709 "")
6710
266eb58a 6711(define_insn "muldi3"
c9692532
DE		 6712 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6713 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6714 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
266eb58a 6715 "TARGET_POWERPC64"
c9692532
DE		 6716 "@
6717 mulld %0,%1,%2
6718 mulli %0,%1,%2"
6719 [(set (attr "type")
6720 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6721 (const_string "imul3")
6722 (match_operand:SI 2 "short_cint_operand" "")
6723 (const_string "imul2")]
6724 (const_string "lmul")))])
266eb58a 6725
9259f3b0
DE		 6726(define_insn "*muldi3_internal1"
6727 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6728 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6729 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6730 (const_int 0)))
6731 (clobber (match_scratch:DI 3 "=r,r"))]
6732 "TARGET_POWERPC64"
6733 "@
6734 mulld. %3,%1,%2
6735 #"
6736 [(set_attr "type" "lmul_compare")
6737 (set_attr "length" "4,8")])
6738
6739(define_split
6740 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6741 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6742 (match_operand:DI 2 "gpc_reg_operand" ""))
6743 (const_int 0)))
6744 (clobber (match_scratch:DI 3 ""))]
6745 "TARGET_POWERPC64 && reload_completed"
6746 [(set (match_dup 3)
6747 (mult:DI (match_dup 1) (match_dup 2)))
6748 (set (match_dup 0)
6749 (compare:CC (match_dup 3)
6750 (const_int 0)))]
6751 "")
6752
6753(define_insn "*muldi3_internal2"
6754 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6755 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6756 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6757 (const_int 0)))
6758 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6759 (mult:DI (match_dup 1) (match_dup 2)))]
6760 "TARGET_POWERPC64"
6761 "@
6762 mulld. %0,%1,%2
6763 #"
6764 [(set_attr "type" "lmul_compare")
6765 (set_attr "length" "4,8")])
6766
6767(define_split
c921bad8 6768 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9259f3b0
DE		 6769 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6770 (match_operand:DI 2 "gpc_reg_operand" ""))
6771 (const_int 0)))
6772 (set (match_operand:DI 0 "gpc_reg_operand" "")
6773 (mult:DI (match_dup 1) (match_dup 2)))]
6774 "TARGET_POWERPC64 && reload_completed"
6775 [(set (match_dup 0)
6776 (mult:DI (match_dup 1) (match_dup 2)))
6777 (set (match_dup 3)
6778 (compare:CC (match_dup 0)
6779 (const_int 0)))]
6780 "")
6781
266eb58a
DE		 6782(define_insn "smuldi3_highpart"
6783 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6784 (truncate:DI
6785 (lshiftrt:TI (mult:TI (sign_extend:TI
6786 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6787 (sign_extend:TI
6788 (match_operand:DI 2 "gpc_reg_operand" "r")))
6789 (const_int 64))))]
6790 "TARGET_POWERPC64"
6791 "mulhd %0,%1,%2"
3cb999d8 6792 [(set_attr "type" "lmul")])
266eb58a
DE		 6793
6794(define_insn "umuldi3_highpart"
6795 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6796 (truncate:DI
6797 (lshiftrt:TI (mult:TI (zero_extend:TI
6798 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6799 (zero_extend:TI
6800 (match_operand:DI 2 "gpc_reg_operand" "r")))
6801 (const_int 64))))]
6802 "TARGET_POWERPC64"
6803 "mulhdu %0,%1,%2"
3cb999d8 6804 [(set_attr "type" "lmul")])
266eb58a 6805
266eb58a 6806(define_insn "rotldi3"
44cd321e
PS		 6807 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6808 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6809 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 6810 "TARGET_POWERPC64"
44cd321e
PS		 6811 "@
6812 rldcl %0,%1,%2,0
6813 rldicl %0,%1,%H2,0"
6814 [(set_attr "type" "var_shift_rotate,integer")])
266eb58a 6815
a260abc9 6816(define_insn "*rotldi3_internal2"
44cd321e
PS		 6817 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6818 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6819 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6820 (const_int 0)))
44cd321e 6821 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6822 "TARGET_64BIT"
9ebbca7d 6823 "@
44cd321e
PS		 6824 rldcl. %3,%1,%2,0
6825 rldicl. %3,%1,%H2,0
6826 #
9ebbca7d 6827 #"
44cd321e
PS		 6828 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6829 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6830
6831(define_split
c921bad8 6832 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 6833 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6834 (match_operand:DI 2 "reg_or_cint_operand" ""))
6835 (const_int 0)))
6836 (clobber (match_scratch:DI 3 ""))]
6837 "TARGET_POWERPC64 && reload_completed"
6838 [(set (match_dup 3)
6839 (rotate:DI (match_dup 1) (match_dup 2)))
6840 (set (match_dup 0)
6841 (compare:CC (match_dup 3)
6842 (const_int 0)))]
6843 "")
266eb58a 6844
a260abc9 6845(define_insn "*rotldi3_internal3"
44cd321e
PS		 6846 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6847 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6848 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6849 (const_int 0)))
44cd321e 6850 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 6851 (rotate:DI (match_dup 1) (match_dup 2)))]
683bdff7 6852 "TARGET_64BIT"
9ebbca7d 6853 "@
44cd321e
PS		 6854 rldcl. %0,%1,%2,0
6855 rldicl. %0,%1,%H2,0
6856 #
9ebbca7d 6857 #"
44cd321e
PS		 6858 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6859 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6860
6861(define_split
c921bad8 6862 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 6863 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6864 (match_operand:DI 2 "reg_or_cint_operand" ""))
6865 (const_int 0)))
6866 (set (match_operand:DI 0 "gpc_reg_operand" "")
6867 (rotate:DI (match_dup 1) (match_dup 2)))]
6868 "TARGET_POWERPC64 && reload_completed"
6869 [(set (match_dup 0)
6870 (rotate:DI (match_dup 1) (match_dup 2)))
6871 (set (match_dup 3)
6872 (compare:CC (match_dup 0)
6873 (const_int 0)))]
6874 "")
266eb58a 6875
a260abc9 6876(define_insn "*rotldi3_internal4"
44cd321e
PS		 6877 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6878 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6879 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6880 (match_operand:DI 3 "mask64_operand" "n,n")))]
a260abc9 6881 "TARGET_POWERPC64"
44cd321e
PS		 6882 "@
6883 rldc%B3 %0,%1,%2,%S3
6884 rldic%B3 %0,%1,%H2,%S3"
6885 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6886
6887(define_insn "*rotldi3_internal5"
44cd321e 6888 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6889 (compare:CC (and:DI
44cd321e
PS		 6890 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6891 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6892 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6893 (const_int 0)))
44cd321e 6894 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
683bdff7 6895 "TARGET_64BIT"
9ebbca7d 6896 "@
44cd321e
PS		 6897 rldc%B3. %4,%1,%2,%S3
6898 rldic%B3. %4,%1,%H2,%S3
6899 #
9ebbca7d 6900 #"
44cd321e
PS		 6901 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6902 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6903
6904(define_split
c921bad8 6905 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 6906 (compare:CC (and:DI
6907 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6908 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6909 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6910 (const_int 0)))
6911 (clobber (match_scratch:DI 4 ""))]
6912 "TARGET_POWERPC64 && reload_completed"
6913 [(set (match_dup 4)
6914 (and:DI (rotate:DI (match_dup 1)
6915 (match_dup 2))
6916 (match_dup 3)))
6917 (set (match_dup 0)
6918 (compare:CC (match_dup 4)
6919 (const_int 0)))]
6920 "")
a260abc9
DE		 6921
6922(define_insn "*rotldi3_internal6"
44cd321e 6923 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6924 (compare:CC (and:DI
44cd321e
PS		 6925 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6926 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6927 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6928 (const_int 0)))
44cd321e 6929 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6930 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6931 "TARGET_64BIT"
9ebbca7d 6932 "@
44cd321e
PS		 6933 rldc%B3. %0,%1,%2,%S3
6934 rldic%B3. %0,%1,%H2,%S3
6935 #
9ebbca7d 6936 #"
44cd321e
PS		 6937 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6938 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6939
6940(define_split
c921bad8 6941 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 6942 (compare:CC (and:DI
6943 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6944 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6945 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6946 (const_int 0)))
6947 (set (match_operand:DI 0 "gpc_reg_operand" "")
6948 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6949 "TARGET_POWERPC64 && reload_completed"
6950 [(set (match_dup 0)
6951 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6952 (set (match_dup 4)
6953 (compare:CC (match_dup 0)
6954 (const_int 0)))]
6955 "")
a260abc9
DE		 6956
6957(define_insn "*rotldi3_internal7"
44cd321e 6958 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6959 (zero_extend:DI
6960 (subreg:QI
44cd321e
PS		 6961 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6962 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6963 "TARGET_POWERPC64"
44cd321e
PS		 6964 "@
6965 rldcl %0,%1,%2,56
6966 rldicl %0,%1,%H2,56"
6967 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6968
6969(define_insn "*rotldi3_internal8"
44cd321e 6970 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6971 (compare:CC (zero_extend:DI
6972 (subreg:QI
44cd321e
PS		 6973 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6974 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6975 (const_int 0)))
44cd321e 6976 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6977 "TARGET_64BIT"
9ebbca7d 6978 "@
44cd321e
PS		 6979 rldcl. %3,%1,%2,56
6980 rldicl. %3,%1,%H2,56
6981 #
9ebbca7d 6982 #"
44cd321e
PS		 6983 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6984 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6985
6986(define_split
c921bad8 6987 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 6988 (compare:CC (zero_extend:DI
6989 (subreg:QI
6990 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6991 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6992 (const_int 0)))
6993 (clobber (match_scratch:DI 3 ""))]
6994 "TARGET_POWERPC64 && reload_completed"
6995 [(set (match_dup 3)
6996 (zero_extend:DI (subreg:QI
6997 (rotate:DI (match_dup 1)
6998 (match_dup 2)) 0)))
6999 (set (match_dup 0)
7000 (compare:CC (match_dup 3)
7001 (const_int 0)))]
7002 "")
a260abc9
DE		 7003
7004(define_insn "*rotldi3_internal9"
44cd321e 7005 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7006 (compare:CC (zero_extend:DI
7007 (subreg:QI
44cd321e
PS		 7008 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7009 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7010 (const_int 0)))
44cd321e 7011 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 7012 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 7013 "TARGET_64BIT"
9ebbca7d 7014 "@
44cd321e
PS		 7015 rldcl. %0,%1,%2,56
7016 rldicl. %0,%1,%H2,56
7017 #
9ebbca7d 7018 #"
44cd321e
PS		 7019 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7020 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7021
7022(define_split
c921bad8 7023 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7024 (compare:CC (zero_extend:DI
7025 (subreg:QI
7026 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7027 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7028 (const_int 0)))
7029 (set (match_operand:DI 0 "gpc_reg_operand" "")
7030 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7031 "TARGET_POWERPC64 && reload_completed"
7032 [(set (match_dup 0)
7033 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7034 (set (match_dup 3)
7035 (compare:CC (match_dup 0)
7036 (const_int 0)))]
7037 "")
a260abc9
DE		 7038
7039(define_insn "*rotldi3_internal10"
44cd321e 7040 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 7041 (zero_extend:DI
7042 (subreg:HI
44cd321e
PS		 7043 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7044 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 7045 "TARGET_POWERPC64"
44cd321e
PS		 7046 "@
7047 rldcl %0,%1,%2,48
7048 rldicl %0,%1,%H2,48"
7049 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 7050
7051(define_insn "*rotldi3_internal11"
44cd321e 7052 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7053 (compare:CC (zero_extend:DI
7054 (subreg:HI
44cd321e
PS		 7055 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7056 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7057 (const_int 0)))
44cd321e 7058 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7059 "TARGET_64BIT"
9ebbca7d 7060 "@
44cd321e
PS		 7061 rldcl. %3,%1,%2,48
7062 rldicl. %3,%1,%H2,48
7063 #
9ebbca7d 7064 #"
44cd321e
PS		 7065 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7066 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7067
7068(define_split
c921bad8 7069 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7070 (compare:CC (zero_extend:DI
7071 (subreg:HI
7072 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7073 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7074 (const_int 0)))
7075 (clobber (match_scratch:DI 3 ""))]
7076 "TARGET_POWERPC64 && reload_completed"
7077 [(set (match_dup 3)
7078 (zero_extend:DI (subreg:HI
7079 (rotate:DI (match_dup 1)
7080 (match_dup 2)) 0)))
7081 (set (match_dup 0)
7082 (compare:CC (match_dup 3)
7083 (const_int 0)))]
7084 "")
a260abc9
DE		 7085
7086(define_insn "*rotldi3_internal12"
44cd321e 7087 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7088 (compare:CC (zero_extend:DI
7089 (subreg:HI
44cd321e
PS		 7090 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7091 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7092 (const_int 0)))
44cd321e 7093 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 7094 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 7095 "TARGET_64BIT"
9ebbca7d 7096 "@
44cd321e
PS		 7097 rldcl. %0,%1,%2,48
7098 rldicl. %0,%1,%H2,48
7099 #
9ebbca7d 7100 #"
44cd321e
PS		 7101 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7102 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7103
7104(define_split
c921bad8 7105 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7106 (compare:CC (zero_extend:DI
7107 (subreg:HI
7108 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7109 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7110 (const_int 0)))
7111 (set (match_operand:DI 0 "gpc_reg_operand" "")
7112 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7113 "TARGET_POWERPC64 && reload_completed"
7114 [(set (match_dup 0)
7115 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7116 (set (match_dup 3)
7117 (compare:CC (match_dup 0)
7118 (const_int 0)))]
7119 "")
a260abc9
DE		 7120
7121(define_insn "*rotldi3_internal13"
44cd321e 7122 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 7123 (zero_extend:DI
7124 (subreg:SI
44cd321e
PS		 7125 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7126 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 7127 "TARGET_POWERPC64"
44cd321e
PS		 7128 "@
7129 rldcl %0,%1,%2,32
7130 rldicl %0,%1,%H2,32"
7131 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 7132
7133(define_insn "*rotldi3_internal14"
44cd321e 7134 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7135 (compare:CC (zero_extend:DI
7136 (subreg:SI
44cd321e
PS		 7137 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7138 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7139 (const_int 0)))
44cd321e 7140 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7141 "TARGET_64BIT"
9ebbca7d 7142 "@
44cd321e
PS		 7143 rldcl. %3,%1,%2,32
7144 rldicl. %3,%1,%H2,32
7145 #
9ebbca7d 7146 #"
44cd321e
PS		 7147 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7148 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7149
7150(define_split
c921bad8 7151 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7152 (compare:CC (zero_extend:DI
7153 (subreg:SI
7154 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7155 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7156 (const_int 0)))
7157 (clobber (match_scratch:DI 3 ""))]
7158 "TARGET_POWERPC64 && reload_completed"
7159 [(set (match_dup 3)
7160 (zero_extend:DI (subreg:SI
7161 (rotate:DI (match_dup 1)
7162 (match_dup 2)) 0)))
7163 (set (match_dup 0)
7164 (compare:CC (match_dup 3)
7165 (const_int 0)))]
7166 "")
a260abc9
DE		 7167
7168(define_insn "*rotldi3_internal15"
44cd321e 7169 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7170 (compare:CC (zero_extend:DI
7171 (subreg:SI
44cd321e
PS		 7172 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7173 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7174 (const_int 0)))
44cd321e 7175 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 7176 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 7177 "TARGET_64BIT"
9ebbca7d 7178 "@
44cd321e
PS		 7179 rldcl. %0,%1,%2,32
7180 rldicl. %0,%1,%H2,32
7181 #
9ebbca7d 7182 #"
44cd321e
PS		 7183 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7184 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7185
7186(define_split
c921bad8 7187 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7188 (compare:CC (zero_extend:DI
7189 (subreg:SI
7190 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7191 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7192 (const_int 0)))
7193 (set (match_operand:DI 0 "gpc_reg_operand" "")
7194 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7195 "TARGET_POWERPC64 && reload_completed"
7196 [(set (match_dup 0)
7197 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7198 (set (match_dup 3)
7199 (compare:CC (match_dup 0)
7200 (const_int 0)))]
7201 "")
a260abc9 7202
266eb58a
DE		 7203(define_expand "ashldi3"
7204 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7205 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7206 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7207 "TARGET_POWERPC64 || TARGET_POWER"
7208 "
7209{
7210 if (TARGET_POWERPC64)
7211 ;
7212 else if (TARGET_POWER)
7213 {
7214 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7215 DONE;
7216 }
7217 else
7218 FAIL;
7219}")
7220
e2c953b6 7221(define_insn "*ashldi3_internal1"
44cd321e
PS		 7222 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7223 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7224 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7225 "TARGET_POWERPC64"
44cd321e
PS		 7226 "@
7227 sld %0,%1,%2
7228 sldi %0,%1,%H2"
7229 [(set_attr "type" "var_shift_rotate,shift")])
6ae08853 7230
e2c953b6 7231(define_insn "*ashldi3_internal2"
44cd321e
PS		 7232 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7233 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7234 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7235 (const_int 0)))
44cd321e 7236 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7237 "TARGET_64BIT"
9ebbca7d 7238 "@
44cd321e
PS		 7239 sld. %3,%1,%2
7240 sldi. %3,%1,%H2
7241 #
9ebbca7d 7242 #"
44cd321e
PS		 7243 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7244 (set_attr "length" "4,4,8,8")])
6ae08853 7245
9ebbca7d
GK		 7246(define_split
7247 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7248 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7249 (match_operand:SI 2 "reg_or_cint_operand" ""))
7250 (const_int 0)))
7251 (clobber (match_scratch:DI 3 ""))]
7252 "TARGET_POWERPC64 && reload_completed"
7253 [(set (match_dup 3)
7254 (ashift:DI (match_dup 1) (match_dup 2)))
7255 (set (match_dup 0)
7256 (compare:CC (match_dup 3)
7257 (const_int 0)))]
7258 "")
7259
e2c953b6 7260(define_insn "*ashldi3_internal3"
44cd321e
PS		 7261 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7262 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7263 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7264 (const_int 0)))
44cd321e 7265 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7266 (ashift:DI (match_dup 1) (match_dup 2)))]
683bdff7 7267 "TARGET_64BIT"
9ebbca7d 7268 "@
44cd321e
PS		 7269 sld. %0,%1,%2
7270 sldi. %0,%1,%H2
7271 #
9ebbca7d 7272 #"
44cd321e
PS		 7273 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7274 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7275
7276(define_split
7277 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7278 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7279 (match_operand:SI 2 "reg_or_cint_operand" ""))
7280 (const_int 0)))
7281 (set (match_operand:DI 0 "gpc_reg_operand" "")
7282 (ashift:DI (match_dup 1) (match_dup 2)))]
7283 "TARGET_POWERPC64 && reload_completed"
7284 [(set (match_dup 0)
7285 (ashift:DI (match_dup 1) (match_dup 2)))
7286 (set (match_dup 3)
7287 (compare:CC (match_dup 0)
7288 (const_int 0)))]
7289 "")
266eb58a 7290
e2c953b6 7291(define_insn "*ashldi3_internal4"
3cb999d8
DE		 7292 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7293 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7294 (match_operand:SI 2 "const_int_operand" "i"))
c5059423
AM		 7295 (match_operand:DI 3 "const_int_operand" "n")))]
7296 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
e2c953b6 7297 "rldic %0,%1,%H2,%W3")
3cb999d8 7298
e2c953b6 7299(define_insn "ashldi3_internal5"
9ebbca7d 7300 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3cb999d8 7301 (compare:CC
9ebbca7d
GK		 7302 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7303 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7304 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7305 (const_int 0)))
9ebbca7d 7306 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7307 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7308 "@
e2c953b6 7309 rldic. %4,%1,%H2,%W3
9ebbca7d 7310 #"
9c6fdb46 7311 [(set_attr "type" "compare")
9ebbca7d
GK		 7312 (set_attr "length" "4,8")])
7313
7314(define_split
c921bad8 7315 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7316 (compare:CC
7317 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7318 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7319 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7320 (const_int 0)))
7321 (clobber (match_scratch:DI 4 ""))]
c5059423
AM		 7322 "TARGET_POWERPC64 && reload_completed
7323 && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 7324 [(set (match_dup 4)
7325 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
e2c953b6 7326 (match_dup 3)))
9ebbca7d
GK		 7327 (set (match_dup 0)
7328 (compare:CC (match_dup 4)
7329 (const_int 0)))]
7330 "")
3cb999d8 7331
e2c953b6 7332(define_insn "*ashldi3_internal6"
9ebbca7d 7333 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3cb999d8 7334 (compare:CC
9ebbca7d
GK		 7335 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7336 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7337 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7338 (const_int 0)))
9ebbca7d 7339 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3cb999d8 7340 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7341 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7342 "@
e2c953b6 7343 rldic. %0,%1,%H2,%W3
9ebbca7d 7344 #"
9c6fdb46 7345 [(set_attr "type" "compare")
9ebbca7d
GK		 7346 (set_attr "length" "4,8")])
7347
7348(define_split
c921bad8 7349 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7350 (compare:CC
7351 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7352 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7353 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7354 (const_int 0)))
7355 (set (match_operand:DI 0 "gpc_reg_operand" "")
7356 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
c5059423
AM		 7357 "TARGET_POWERPC64 && reload_completed
7358 && includes_rldic_lshift_p (operands[2], operands[3])"
7359 [(set (match_dup 0)
7360 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7361 (match_dup 3)))
7362 (set (match_dup 4)
7363 (compare:CC (match_dup 0)
7364 (const_int 0)))]
7365 "")
7366
7367(define_insn "*ashldi3_internal7"
7368 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7369 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7370 (match_operand:SI 2 "const_int_operand" "i"))
1990cd79 7371 (match_operand:DI 3 "mask64_operand" "n")))]
c5059423
AM		 7372 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7373 "rldicr %0,%1,%H2,%S3")
7374
7375(define_insn "ashldi3_internal8"
7376 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7377 (compare:CC
7378 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7379 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7380 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7381 (const_int 0)))
7382 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7383 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7384 "@
7385 rldicr. %4,%1,%H2,%S3
7386 #"
9c6fdb46 7387 [(set_attr "type" "compare")
c5059423
AM		 7388 (set_attr "length" "4,8")])
7389
7390(define_split
c921bad8 7391 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
c5059423
AM		 7392 (compare:CC
7393 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7394 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7395 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7396 (const_int 0)))
7397 (clobber (match_scratch:DI 4 ""))]
7398 "TARGET_POWERPC64 && reload_completed
7399 && includes_rldicr_lshift_p (operands[2], operands[3])"
7400 [(set (match_dup 4)
7401 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7402 (match_dup 3)))
7403 (set (match_dup 0)
7404 (compare:CC (match_dup 4)
7405 (const_int 0)))]
7406 "")
7407
7408(define_insn "*ashldi3_internal9"
7409 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7410 (compare:CC
7411 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7412 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7413 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7414 (const_int 0)))
7415 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7416 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7417 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7418 "@
7419 rldicr. %0,%1,%H2,%S3
7420 #"
9c6fdb46 7421 [(set_attr "type" "compare")
c5059423
AM		 7422 (set_attr "length" "4,8")])
7423
7424(define_split
c921bad8 7425 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
c5059423
AM		 7426 (compare:CC
7427 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7428 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7429 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7430 (const_int 0)))
7431 (set (match_operand:DI 0 "gpc_reg_operand" "")
7432 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7433 "TARGET_POWERPC64 && reload_completed
7434 && includes_rldicr_lshift_p (operands[2], operands[3])"
9ebbca7d 7435 [(set (match_dup 0)
e2c953b6
DE		 7436 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7437 (match_dup 3)))
9ebbca7d
GK		 7438 (set (match_dup 4)
7439 (compare:CC (match_dup 0)
7440 (const_int 0)))]
7441 "")
7442
7443(define_expand "lshrdi3"
266eb58a
DE		 7444 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7445 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7446 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7447 "TARGET_POWERPC64 || TARGET_POWER"
7448 "
7449{
7450 if (TARGET_POWERPC64)
7451 ;
7452 else if (TARGET_POWER)
7453 {
7454 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7455 DONE;
7456 }
7457 else
7458 FAIL;
7459}")
7460
e2c953b6 7461(define_insn "*lshrdi3_internal1"
44cd321e
PS		 7462 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7463 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7464 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7465 "TARGET_POWERPC64"
44cd321e
PS		 7466 "@
7467 srd %0,%1,%2
7468 srdi %0,%1,%H2"
7469 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7470
e2c953b6 7471(define_insn "*lshrdi3_internal2"
44cd321e
PS		 7472 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7473 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7474 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
29ae5b89 7475 (const_int 0)))
44cd321e 7476 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7477 "TARGET_64BIT "
9ebbca7d 7478 "@
44cd321e
PS		 7479 srd. %3,%1,%2
7480 srdi. %3,%1,%H2
7481 #
9ebbca7d 7482 #"
44cd321e
PS		 7483 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7484 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7485
7486(define_split
c921bad8 7487 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7488 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7489 (match_operand:SI 2 "reg_or_cint_operand" ""))
7490 (const_int 0)))
7491 (clobber (match_scratch:DI 3 ""))]
7492 "TARGET_POWERPC64 && reload_completed"
7493 [(set (match_dup 3)
7494 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7495 (set (match_dup 0)
7496 (compare:CC (match_dup 3)
7497 (const_int 0)))]
7498 "")
266eb58a 7499
e2c953b6 7500(define_insn "*lshrdi3_internal3"
44cd321e
PS		 7501 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7502 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7503 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7504 (const_int 0)))
44cd321e 7505 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
29ae5b89 7506 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7507 "TARGET_64BIT"
9ebbca7d 7508 "@
44cd321e
PS		 7509 srd. %0,%1,%2
7510 srdi. %0,%1,%H2
7511 #
9ebbca7d 7512 #"
44cd321e
PS		 7513 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7514 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7515
7516(define_split
c921bad8 7517 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 7518 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7519 (match_operand:SI 2 "reg_or_cint_operand" ""))
7520 (const_int 0)))
7521 (set (match_operand:DI 0 "gpc_reg_operand" "")
7522 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7523 "TARGET_POWERPC64 && reload_completed"
7524 [(set (match_dup 0)
7525 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7526 (set (match_dup 3)
7527 (compare:CC (match_dup 0)
7528 (const_int 0)))]
7529 "")
266eb58a
DE		 7530
7531(define_expand "ashrdi3"
7532 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7533 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7534 (match_operand:SI 2 "reg_or_cint_operand" "")))]
97727e85 7535 "WORDS_BIG_ENDIAN"
266eb58a
DE		 7536 "
7537{
7538 if (TARGET_POWERPC64)
7539 ;
7540 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7541 {
7542 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7543 DONE;
7544 }
97727e85
AH		 7545 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7546 && WORDS_BIG_ENDIAN)
4aa74a4f
FS		 7547 {
7548 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7549 DONE;
7550 }
266eb58a
DE		 7551 else
7552 FAIL;
7553}")
7554
e2c953b6 7555(define_insn "*ashrdi3_internal1"
44cd321e
PS		 7556 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7557 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7558 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7559 "TARGET_POWERPC64"
44cd321e
PS		 7560 "@
7561 srad %0,%1,%2
7562 sradi %0,%1,%H2"
7563 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7564
e2c953b6 7565(define_insn "*ashrdi3_internal2"
44cd321e
PS		 7566 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7567 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7568 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7569 (const_int 0)))
44cd321e 7570 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7571 "TARGET_64BIT"
9ebbca7d 7572 "@
44cd321e
PS		 7573 srad. %3,%1,%2
7574 sradi. %3,%1,%H2
7575 #
9ebbca7d 7576 #"
44cd321e
PS		 7577 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7578 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7579
7580(define_split
7581 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7582 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7583 (match_operand:SI 2 "reg_or_cint_operand" ""))
7584 (const_int 0)))
7585 (clobber (match_scratch:DI 3 ""))]
7586 "TARGET_POWERPC64 && reload_completed"
7587 [(set (match_dup 3)
7588 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7589 (set (match_dup 0)
7590 (compare:CC (match_dup 3)
7591 (const_int 0)))]
7592 "")
266eb58a 7593
e2c953b6 7594(define_insn "*ashrdi3_internal3"
44cd321e
PS		 7595 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7596 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7597 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7598 (const_int 0)))
44cd321e 7599 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7600 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7601 "TARGET_64BIT"
9ebbca7d 7602 "@
44cd321e
PS		 7603 srad. %0,%1,%2
7604 sradi. %0,%1,%H2
7605 #
9ebbca7d 7606 #"
44cd321e
PS		 7607 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7608 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7609
7610(define_split
7611 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7612 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7613 (match_operand:SI 2 "reg_or_cint_operand" ""))
7614 (const_int 0)))
7615 (set (match_operand:DI 0 "gpc_reg_operand" "")
7616 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7617 "TARGET_POWERPC64 && reload_completed"
7618 [(set (match_dup 0)
7619 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7620 (set (match_dup 3)
7621 (compare:CC (match_dup 0)
7622 (const_int 0)))]
7623 "")
815cdc52 7624
c921bad8
AP		 7625(define_expand "anddi3"
7626 [(parallel
7627 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7628 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7629 (match_operand:DI 2 "and64_2_operand" "")))
7630 (clobber (match_scratch:CC 3 ""))])]
7631 "TARGET_POWERPC64"
7632 "")
7633
7634(define_insn "anddi3_mc"
e1e2e653
NS		 7635 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7636 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7637 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7638 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
c921bad8 7639 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
266eb58a
DE		 7640 "@
7641 and %0,%1,%2
29ae5b89 7642 rldic%B2 %0,%1,0,%S2
e1e2e653 7643 rlwinm %0,%1,0,%m2,%M2
29ae5b89 7644 andi. %0,%1,%b2
0ba1b2ff
AM		 7645 andis. %0,%1,%u2
7646 #"
cacf1ca8 7647 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
e1e2e653 7648 (set_attr "length" "4,4,4,4,4,8")])
0ba1b2ff 7649
c921bad8
AP		 7650(define_insn "anddi3_nomc"
7651 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7652 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7653 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7654 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7655 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7656 "@
7657 and %0,%1,%2
7658 rldic%B2 %0,%1,0,%S2
7659 rlwinm %0,%1,0,%m2,%M2
7660 #"
7661 [(set_attr "length" "4,4,4,8")])
7662
0ba1b2ff
AM		 7663(define_split
7664 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7665 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7666 (match_operand:DI 2 "mask64_2_operand" "")))
7667 (clobber (match_scratch:CC 3 ""))]
7668 "TARGET_POWERPC64
7669 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7670 && !mask_operand (operands[2], DImode)
7671 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7672 [(set (match_dup 0)
7673 (and:DI (rotate:DI (match_dup 1)
7674 (match_dup 4))
7675 (match_dup 5)))
7676 (set (match_dup 0)
7677 (and:DI (rotate:DI (match_dup 0)
7678 (match_dup 6))
7679 (match_dup 7)))]
0ba1b2ff
AM		 7680{
7681 build_mask64_2_operands (operands[2], &operands[4]);
e1e2e653 7682})
266eb58a 7683
c921bad8 7684(define_insn "*anddi3_internal2_mc"
1990cd79
AM		 7685 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7686 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7687 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7688 (const_int 0)))
1990cd79
AM		 7689 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7690 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
c921bad8 7691 "TARGET_64BIT && rs6000_gen_cell_microcode"
266eb58a
DE		 7692 "@
7693 and. %3,%1,%2
6c873122 7694 rldic%B2. %3,%1,0,%S2
1990cd79 7695 rlwinm. %3,%1,0,%m2,%M2
6ffc8580
MM		 7696 andi. %3,%1,%b2
7697 andis. %3,%1,%u2
9ebbca7d
GK		 7698 #
7699 #
7700 #
0ba1b2ff
AM		 7701 #
7702 #
1990cd79 7703 #
9ebbca7d 7704 #"
cacf1ca8
MM		 7705 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7706 fast_compare,compare,compare,compare,compare,compare,\
7707 compare,compare")
1990cd79 7708 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d 7709
0ba1b2ff
AM		 7710(define_split
7711 [(set (match_operand:CC 0 "cc_reg_operand" "")
7712 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7713 (match_operand:DI 2 "mask64_2_operand" ""))
7714 (const_int 0)))
7715 (clobber (match_scratch:DI 3 ""))
7716 (clobber (match_scratch:CC 4 ""))]
1990cd79 7717 "TARGET_64BIT && reload_completed
0ba1b2ff 7718 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7719 && !mask_operand (operands[2], DImode)
7720 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7721 [(set (match_dup 3)
7722 (and:DI (rotate:DI (match_dup 1)
7723 (match_dup 5))
7724 (match_dup 6)))
7725 (parallel [(set (match_dup 0)
7726 (compare:CC (and:DI (rotate:DI (match_dup 3)
7727 (match_dup 7))
7728 (match_dup 8))
7729 (const_int 0)))
7730 (clobber (match_dup 3))])]
7731 "
7732{
7733 build_mask64_2_operands (operands[2], &operands[5]);
7734}")
7735
c921bad8 7736(define_insn "*anddi3_internal3_mc"
1990cd79
AM		 7737 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7738 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7739 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7740 (const_int 0)))
1990cd79 7741 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
9ebbca7d 7742 (and:DI (match_dup 1) (match_dup 2)))
1990cd79 7743 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
c921bad8 7744 "TARGET_64BIT && rs6000_gen_cell_microcode"
266eb58a
DE		 7745 "@
7746 and. %0,%1,%2
6c873122 7747 rldic%B2. %0,%1,0,%S2
1990cd79 7748 rlwinm. %0,%1,0,%m2,%M2
6ffc8580
MM		 7749 andi. %0,%1,%b2
7750 andis. %0,%1,%u2
9ebbca7d
GK		 7751 #
7752 #
7753 #
0ba1b2ff
AM		 7754 #
7755 #
1990cd79 7756 #
9ebbca7d 7757 #"
cacf1ca8
MM		 7758 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7759 fast_compare,compare,compare,compare,compare,compare,\
7760 compare,compare")
1990cd79 7761 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d
GK		 7762
7763(define_split
c921bad8 7764 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d 7765 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
1990cd79 7766 (match_operand:DI 2 "and64_2_operand" ""))
9ebbca7d
GK		 7767 (const_int 0)))
7768 (set (match_operand:DI 0 "gpc_reg_operand" "")
7769 (and:DI (match_dup 1) (match_dup 2)))
7770 (clobber (match_scratch:CC 4 ""))]
1990cd79 7771 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 7772 [(parallel [(set (match_dup 0)
7773 (and:DI (match_dup 1) (match_dup 2)))
7774 (clobber (match_dup 4))])
7775 (set (match_dup 3)
7776 (compare:CC (match_dup 0)
7777 (const_int 0)))]
7778 "")
266eb58a 7779
0ba1b2ff
AM		 7780(define_split
7781 [(set (match_operand:CC 3 "cc_reg_operand" "")
7782 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7783 (match_operand:DI 2 "mask64_2_operand" ""))
7784 (const_int 0)))
7785 (set (match_operand:DI 0 "gpc_reg_operand" "")
7786 (and:DI (match_dup 1) (match_dup 2)))
7787 (clobber (match_scratch:CC 4 ""))]
1990cd79 7788 "TARGET_64BIT && reload_completed
0ba1b2ff 7789 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7790 && !mask_operand (operands[2], DImode)
7791 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7792 [(set (match_dup 0)
7793 (and:DI (rotate:DI (match_dup 1)
7794 (match_dup 5))
7795 (match_dup 6)))
7796 (parallel [(set (match_dup 3)
7797 (compare:CC (and:DI (rotate:DI (match_dup 0)
7798 (match_dup 7))
7799 (match_dup 8))
7800 (const_int 0)))
7801 (set (match_dup 0)
7802 (and:DI (rotate:DI (match_dup 0)
7803 (match_dup 7))
7804 (match_dup 8)))])]
7805 "
7806{
7807 build_mask64_2_operands (operands[2], &operands[5]);
7808}")
7809
a260abc9 7810(define_expand "iordi3"
266eb58a 7811 [(set (match_operand:DI 0 "gpc_reg_operand" "")
a260abc9 7812 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7813 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
266eb58a 7814 "TARGET_POWERPC64"
266eb58a
DE		 7815 "
7816{
dfbdccdb 7817 if (non_logical_cint_operand (operands[2], DImode))
266eb58a 7818 {
dfbdccdb 7819 HOST_WIDE_INT value;
b3a13419
ILT		 7820 rtx tmp = ((!can_create_pseudo_p ()
7821 || rtx_equal_p (operands[0], operands[1]))
a260abc9 7822 ? operands[0] : gen_reg_rtx (DImode));
266eb58a 7823
dfbdccdb
GK		 7824 if (GET_CODE (operands[2]) == CONST_INT)
7825 {
7826 value = INTVAL (operands[2]);
7827 emit_insn (gen_iordi3 (tmp, operands[1],
7828 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7829 }
e2c953b6 7830 else
dfbdccdb
GK		 7831 {
7832 value = CONST_DOUBLE_LOW (operands[2]);
7833 emit_insn (gen_iordi3 (tmp, operands[1],
7834 immed_double_const (value
7835 & (~ (HOST_WIDE_INT) 0xffff),
7836 0, DImode)));
7837 }
e2c953b6 7838
9ebbca7d
GK		 7839 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7840 DONE;
7841 }
266eb58a
DE		 7842}")
7843
a260abc9
DE		 7844(define_expand "xordi3"
7845 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7846 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7847 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
a260abc9
DE		 7848 "TARGET_POWERPC64"
7849 "
7850{
dfbdccdb 7851 if (non_logical_cint_operand (operands[2], DImode))
a260abc9 7852 {
dfbdccdb 7853 HOST_WIDE_INT value;
b3a13419
ILT		 7854 rtx tmp = ((!can_create_pseudo_p ()
7855 || rtx_equal_p (operands[0], operands[1]))
a260abc9
DE		 7856 ? operands[0] : gen_reg_rtx (DImode));
7857
dfbdccdb
GK		 7858 if (GET_CODE (operands[2]) == CONST_INT)
7859 {
7860 value = INTVAL (operands[2]);
7861 emit_insn (gen_xordi3 (tmp, operands[1],
7862 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7863 }
e2c953b6 7864 else
dfbdccdb
GK		 7865 {
7866 value = CONST_DOUBLE_LOW (operands[2]);
7867 emit_insn (gen_xordi3 (tmp, operands[1],
7868 immed_double_const (value
7869 & (~ (HOST_WIDE_INT) 0xffff),
7870 0, DImode)));
7871 }
e2c953b6 7872
9ebbca7d
GK		 7873 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7874 DONE;
7875 }
a260abc9
DE		 7876}")
7877
dfbdccdb 7878(define_insn "*booldi3_internal1"
266eb58a 7879 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 7880 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7881 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7882 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
266eb58a 7883 "TARGET_POWERPC64"
1fd4e8c1 7884 "@
dfbdccdb
GK		 7885 %q3 %0,%1,%2
7886 %q3i %0,%1,%b2
7887 %q3is %0,%1,%u2")
1fd4e8c1 7888
dfbdccdb 7889(define_insn "*booldi3_internal2"
9ebbca7d 7890 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 7891 (compare:CC (match_operator:DI 4 "boolean_or_operator"
dfbdccdb
GK		 7892 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7893 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7894 (const_int 0)))
9ebbca7d 7895 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7896 "TARGET_64BIT"
9ebbca7d 7897 "@
dfbdccdb 7898 %q4. %3,%1,%2
9ebbca7d 7899 #"
cacf1ca8 7900 [(set_attr "type" "fast_compare,compare")
9ebbca7d
GK		 7901 (set_attr "length" "4,8")])
7902
7903(define_split
c921bad8 7904 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 7905 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7906 [(match_operand:DI 1 "gpc_reg_operand" "")
7907 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7908 (const_int 0)))
9ebbca7d
GK		 7909 (clobber (match_scratch:DI 3 ""))]
7910 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7911 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7912 (set (match_dup 0)
7913 (compare:CC (match_dup 3)
7914 (const_int 0)))]
7915 "")
1fd4e8c1 7916
dfbdccdb 7917(define_insn "*booldi3_internal3"
9ebbca7d 7918 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
d93e052c 7919 (compare:CC (match_operator:DI 4 "boolean_or_operator"
dfbdccdb
GK		 7920 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7921 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7922 (const_int 0)))
9ebbca7d 7923 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7924 (match_dup 4))]
683bdff7 7925 "TARGET_64BIT"
9ebbca7d 7926 "@
dfbdccdb 7927 %q4. %0,%1,%2
9ebbca7d 7928 #"
cacf1ca8 7929 [(set_attr "type" "fast_compare,compare")
9ebbca7d
GK		 7930 (set_attr "length" "4,8")])
7931
7932(define_split
c921bad8 7933 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 7934 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7935 [(match_operand:DI 1 "gpc_reg_operand" "")
7936 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7937 (const_int 0)))
75540af0 7938 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7939 (match_dup 4))]
9ebbca7d 7940 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7941 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7942 (set (match_dup 3)
7943 (compare:CC (match_dup 0)
7944 (const_int 0)))]
7945 "")
1fd4e8c1 7946
6ae08853 7947;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 7948;; each of which does one 16-bit part. This is used by combine.
266eb58a
DE		 7949
7950(define_split
7951 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1d328b19 7952 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7953 [(match_operand:DI 1 "gpc_reg_operand" "")
7954 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
266eb58a 7955 "TARGET_POWERPC64"
dfbdccdb
GK		 7956 [(set (match_dup 0) (match_dup 4))
7957 (set (match_dup 0) (match_dup 5))]
266eb58a
DE		 7958"
7959{
dfbdccdb 7960 rtx i3,i4;
6ae08853 7961
9ebbca7d
GK		 7962 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7963 {
7964 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
dfbdccdb 7965 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
9ebbca7d 7966 0, DImode);
dfbdccdb 7967 i4 = GEN_INT (value & 0xffff);
9ebbca7d
GK		 7968 }
7969 else
7970 {
dfbdccdb 7971 i3 = GEN_INT (INTVAL (operands[2])
9ebbca7d 7972 & (~ (HOST_WIDE_INT) 0xffff));
dfbdccdb 7973 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
9ebbca7d 7974 }
1c563bed 7975 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7976 operands[1], i3);
1c563bed 7977 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7978 operands[0], i4);
1fd4e8c1
RK		 7979}")
7980
dfbdccdb 7981(define_insn "*boolcdi3_internal1"
9ebbca7d 7982 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7983 (match_operator:DI 3 "boolean_operator"
7984 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7985 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
a473029f 7986 "TARGET_POWERPC64"
1d328b19 7987 "%q3 %0,%2,%1")
a473029f 7988
dfbdccdb 7989(define_insn "*boolcdi3_internal2"
9ebbca7d 7990 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7991 (compare:CC (match_operator:DI 4 "boolean_operator"
7992 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7993 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7994 (const_int 0)))
9ebbca7d 7995 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7996 "TARGET_64BIT"
9ebbca7d 7997 "@
1d328b19 7998 %q4. %3,%2,%1
9ebbca7d 7999 #"
cacf1ca8 8000 [(set_attr "type" "fast_compare,compare")
9ebbca7d
GK		 8001 (set_attr "length" "4,8")])
8002
8003(define_split
c921bad8 8004 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 8005 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 8006 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8007 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 8008 (const_int 0)))
9ebbca7d
GK		 8009 (clobber (match_scratch:DI 3 ""))]
8010 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 8011 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 8012 (set (match_dup 0)
8013 (compare:CC (match_dup 3)
8014 (const_int 0)))]
8015 "")
a473029f 8016
dfbdccdb 8017(define_insn "*boolcdi3_internal3"
9ebbca7d 8018 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 8019 (compare:CC (match_operator:DI 4 "boolean_operator"
8020 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8021 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8022 (const_int 0)))
9ebbca7d 8023 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 8024 (match_dup 4))]
683bdff7 8025 "TARGET_64BIT"
9ebbca7d 8026 "@
1d328b19 8027 %q4. %0,%2,%1
9ebbca7d 8028 #"
cacf1ca8 8029 [(set_attr "type" "fast_compare,compare")
9ebbca7d
GK		 8030 (set_attr "length" "4,8")])
8031
8032(define_split
c921bad8 8033 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 8034 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 8035 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8036 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 8037 (const_int 0)))
75540af0 8038 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 8039 (match_dup 4))]
9ebbca7d 8040 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 8041 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 8042 (set (match_dup 3)
8043 (compare:CC (match_dup 0)
8044 (const_int 0)))]
8045 "")
266eb58a 8046
dfbdccdb 8047(define_insn "*boolccdi3_internal1"
a473029f 8048 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 8049 (match_operator:DI 3 "boolean_operator"
8050 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 8051 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
a473029f 8052 "TARGET_POWERPC64"
dfbdccdb 8053 "%q3 %0,%1,%2")
a473029f 8054
dfbdccdb 8055(define_insn "*boolccdi3_internal2"
9ebbca7d 8056 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 8057 (compare:CC (match_operator:DI 4 "boolean_operator"
8058 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8059 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8060 (const_int 0)))
9ebbca7d 8061 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 8062 "TARGET_64BIT"
9ebbca7d 8063 "@
dfbdccdb 8064 %q4. %3,%1,%2
9ebbca7d 8065 #"
cacf1ca8 8066 [(set_attr "type" "fast_compare,compare")
9ebbca7d
GK		 8067 (set_attr "length" "4,8")])
8068
8069(define_split
c921bad8 8070 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 8071 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 8072 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8073 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 8074 (const_int 0)))
9ebbca7d
GK		 8075 (clobber (match_scratch:DI 3 ""))]
8076 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 8077 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 8078 (set (match_dup 0)
8079 (compare:CC (match_dup 3)
8080 (const_int 0)))]
8081 "")
266eb58a 8082
dfbdccdb 8083(define_insn "*boolccdi3_internal3"
9ebbca7d 8084 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 8085 (compare:CC (match_operator:DI 4 "boolean_operator"
8086 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8087 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8088 (const_int 0)))
9ebbca7d 8089 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 8090 (match_dup 4))]
683bdff7 8091 "TARGET_64BIT"
9ebbca7d 8092 "@
dfbdccdb 8093 %q4. %0,%1,%2
9ebbca7d 8094 #"
cacf1ca8 8095 [(set_attr "type" "fast_compare,compare")
9ebbca7d
GK		 8096 (set_attr "length" "4,8")])
8097
8098(define_split
c921bad8 8099 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
dfbdccdb 8100 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 8101 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8102 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 8103 (const_int 0)))
75540af0 8104 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 8105 (match_dup 4))]
9ebbca7d 8106 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 8107 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 8108 (set (match_dup 3)
8109 (compare:CC (match_dup 0)
8110 (const_int 0)))]
8111 "")
cacf1ca8
MM		 8112
8113(define_expand "smindi3"
8114 [(match_operand:DI 0 "gpc_reg_operand" "")
8115 (match_operand:DI 1 "gpc_reg_operand" "")
8116 (match_operand:DI 2 "gpc_reg_operand" "")]
8117 "TARGET_ISEL64"
8118 "
8119{
8120 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
8121 DONE;
8122}")
8123
8124(define_expand "smaxdi3"
8125 [(match_operand:DI 0 "gpc_reg_operand" "")
8126 (match_operand:DI 1 "gpc_reg_operand" "")
8127 (match_operand:DI 2 "gpc_reg_operand" "")]
8128 "TARGET_ISEL64"
8129 "
8130{
8131 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
8132 DONE;
8133}")
8134
8135(define_expand "umindi3"
8136 [(match_operand:DI 0 "gpc_reg_operand" "")
8137 (match_operand:DI 1 "gpc_reg_operand" "")
8138 (match_operand:DI 2 "gpc_reg_operand" "")]
8139 "TARGET_ISEL64"
8140 "
8141{
8142 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
8143 DONE;
8144}")
8145
8146(define_expand "umaxdi3"
8147 [(match_operand:DI 0 "gpc_reg_operand" "")
8148 (match_operand:DI 1 "gpc_reg_operand" "")
8149 (match_operand:DI 2 "gpc_reg_operand" "")]
8150 "TARGET_ISEL64"
8151 "
8152{
8153 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
8154 DONE;
8155}")
8156
dfbdccdb 8157\f
1fd4e8c1 8158;; Now define ways of moving data around.
4697a36c 8159
766a866c
MM		 8160;; Set up a register with a value from the GOT table
8161
8162(define_expand "movsi_got"
52d3af72 8163 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 8164 (unspec:SI [(match_operand:SI 1 "got_operand" "")
615158e2 8165 (match_dup 2)] UNSPEC_MOVSI_GOT))]
f607bc57 8166 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 8167 "
8168{
38c1f2d7
MM		 8169 if (GET_CODE (operands[1]) == CONST)
8170 {
8171 rtx offset = const0_rtx;
8172 HOST_WIDE_INT value;
8173
8174 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8175 value = INTVAL (offset);
8176 if (value != 0)
8177 {
b3a13419
ILT		 8178 rtx tmp = (!can_create_pseudo_p ()
8179 ? operands[0]
8180 : gen_reg_rtx (Pmode));
38c1f2d7
MM		 8181 emit_insn (gen_movsi_got (tmp, operands[1]));
8182 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8183 DONE;
8184 }
8185 }
8186
c4c40373 8187 operands[2] = rs6000_got_register (operands[1]);
766a866c
MM		 8188}")
8189
84f414bc 8190(define_insn "*movsi_got_internal"
52d3af72 8191 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9ebbca7d 8192 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 8193 (match_operand:SI 2 "gpc_reg_operand" "b")]
8194 UNSPEC_MOVSI_GOT))]
f607bc57 8195 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 8196 "{l|lwz} %0,%a1@got(%2)"
8197 [(set_attr "type" "load")])
8198
b22b9b3e
JL		 8199;; Used by sched, shorten_branches and final when the GOT pseudo reg
8200;; didn't get allocated to a hard register.
6ae08853 8201(define_split
75540af0 8202 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 8203 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 8204 (match_operand:SI 2 "memory_operand" "")]
8205 UNSPEC_MOVSI_GOT))]
f607bc57 8206 "DEFAULT_ABI == ABI_V4
b22b9b3e
JL		 8207 && flag_pic == 1
8208 && (reload_in_progress || reload_completed)"
8209 [(set (match_dup 0) (match_dup 2))
615158e2
JJ		 8210 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8211 UNSPEC_MOVSI_GOT))]
b22b9b3e
JL		 8212 "")
8213
1fd4e8c1
RK		 8214;; For SI, we special-case integers that can't be loaded in one insn. We
8215;; do the load 16-bits at a time. We could do this by loading from memory,
8216;; and this is even supposed to be faster, but it is simpler not to get
8217;; integers in the TOC.
ee890fe2
SS		 8218(define_insn "movsi_low"
8219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
f585a356 8220 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
ee890fe2
SS		 8221 (match_operand 2 "" ""))))]
8222 "TARGET_MACHO && ! TARGET_64BIT"
8223 "{l|lwz} %0,lo16(%2)(%1)"
8224 [(set_attr "type" "load")
8225 (set_attr "length" "4")])
8226
acad7ed3 8227(define_insn "*movsi_internal1"
165a5bad 8228 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
a004eb82 8229 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
2c5cac98 8230 "!TARGET_SINGLE_FPU &&
e0f56f41 8231 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
1fd4e8c1 8232 "@
deb9225a 8233 mr %0,%1
b9442c72 8234 {cal|la} %0,%a1
ca7f5001
RK		 8235 {l%U1%X1|lwz%U1%X1} %0,%1
8236 {st%U0%X0|stw%U0%X0} %1,%0
19d5775a 8237 {lil|li} %0,%1
802a0058 8238 {liu|lis} %0,%v1
beaec479 8239 #
aee86b38 8240 {cal|la} %0,%a1
1fd4e8c1 8241 mf%1 %0
5c23c401 8242 mt%0 %1
e76e75bb 8243 mt%0 %1
a004eb82 8244 mt%0 %1
e34eaae5 8245 {cror 0,0,0|nop}"
02ca7595 8246 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
a004eb82 8247 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
1fd4e8c1 8248
2c5cac98
ME		 8249(define_insn "*movsi_internal1_single"
8250 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
8251 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
8252 "TARGET_SINGLE_FPU &&
e0f56f41 8253 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
2c5cac98
ME		 8254 "@
8255 mr %0,%1
8256 {cal|la} %0,%a1
8257 {l%U1%X1|lwz%U1%X1} %0,%1
8258 {st%U0%X0|stw%U0%X0} %1,%0
8259 {lil|li} %0,%1
8260 {liu|lis} %0,%v1
8261 #
8262 {cal|la} %0,%a1
8263 mf%1 %0
8264 mt%0 %1
8265 mt%0 %1
8266 mt%0 %1
8267 {cror 0,0,0|nop}
8268 stfs%U0%X0 %1, %0
8269 lfs%U1%X1 %0, %1"
8270 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
8271 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
8272
77fa0940
RK		 8273;; Split a load of a large constant into the appropriate two-insn
8274;; sequence.
8275
8276(define_split
8277 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8278 (match_operand:SI 1 "const_int_operand" ""))]
bb21487f 8279 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
77fa0940
RK		 8280 && (INTVAL (operands[1]) & 0xffff) != 0"
8281 [(set (match_dup 0)
8282 (match_dup 2))
8283 (set (match_dup 0)
8284 (ior:SI (match_dup 0)
8285 (match_dup 3)))]
8286 "
af8cb5c5
DE		 8287{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8288
8289 if (tem == operands[0])
8290 DONE;
8291 else
8292 FAIL;
77fa0940
RK		 8293}")
8294
4ae234b0 8295(define_insn "*mov<mode>_internal2"
bb84cb12 8296 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
4ae234b0 8297 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
1fd4e8c1 8298 (const_int 0)))
4ae234b0
GK		 8299 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8300 ""
9ebbca7d 8301 "@
4ae234b0 8302 {cmpi|cmp<wd>i} %2,%0,0
9ebbca7d
GK		 8303 mr. %0,%1
8304 #"
bb84cb12
DE		 8305 [(set_attr "type" "cmp,compare,cmp")
8306 (set_attr "length" "4,4,8")])
8307
9ebbca7d 8308(define_split
c921bad8 8309 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
4ae234b0 8310 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9ebbca7d 8311 (const_int 0)))
4ae234b0
GK		 8312 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8313 "reload_completed"
9ebbca7d
GK		 8314 [(set (match_dup 0) (match_dup 1))
8315 (set (match_dup 2)
8316 (compare:CC (match_dup 0)
8317 (const_int 0)))]
8318 "")
bb84cb12 8319\f
e34eaae5 8320(define_insn "*movhi_internal"
fb81d7ce
RK		 8321 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8322 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8323 "gpc_reg_operand (operands[0], HImode)
8324 || gpc_reg_operand (operands[1], HImode)"
1fd4e8c1 8325 "@
deb9225a 8326 mr %0,%1
1fd4e8c1
RK		 8327 lhz%U1%X1 %0,%1
8328 sth%U0%X0 %1,%0
19d5775a 8329 {lil|li} %0,%w1
1fd4e8c1 8330 mf%1 %0
e76e75bb 8331 mt%0 %1
fb81d7ce 8332 mt%0 %1
e34eaae5 8333 {cror 0,0,0|nop}"
02ca7595 8334 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1 8335
4ae234b0
GK		 8336(define_expand "mov<mode>"
8337 [(set (match_operand:INT 0 "general_operand" "")
8338 (match_operand:INT 1 "any_operand" ""))]
1fd4e8c1 8339 ""
4ae234b0 8340 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
1fd4e8c1 8341
e34eaae5 8342(define_insn "*movqi_internal"
fb81d7ce
RK		 8343 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8344 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8345 "gpc_reg_operand (operands[0], QImode)
8346 || gpc_reg_operand (operands[1], QImode)"
1fd4e8c1 8347 "@
deb9225a 8348 mr %0,%1
1fd4e8c1
RK		 8349 lbz%U1%X1 %0,%1
8350 stb%U0%X0 %1,%0
19d5775a 8351 {lil|li} %0,%1
1fd4e8c1 8352 mf%1 %0
e76e75bb 8353 mt%0 %1
fb81d7ce 8354 mt%0 %1
e34eaae5 8355 {cror 0,0,0|nop}"
02ca7595 8356 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1
RK		 8357\f
8358;; Here is how to move condition codes around. When we store CC data in
8359;; an integer register or memory, we store just the high-order 4 bits.
8360;; This lets us not shift in the most common case of CR0.
8361(define_expand "movcc"
8362 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8363 (match_operand:CC 1 "nonimmediate_operand" ""))]
8364 ""
8365 "")
8366
a65c591c 8367(define_insn "*movcc_internal1"
4eb585a4
DE		 8368 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8369 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
1fd4e8c1
RK		 8370 "register_operand (operands[0], CCmode)
8371 || register_operand (operands[1], CCmode)"
8372 "@
8373 mcrf %0,%1
8374 mtcrf 128,%1
ca7f5001 8375 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
4eb585a4 8376 crxor %0,%0,%0
2c4a9cff
DE		 8377 mfcr %0%Q1
8378 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
deb9225a 8379 mr %0,%1
4eb585a4 8380 {lil|li} %0,%1
b54cf83a 8381 mf%1 %0
b991a865
GK		 8382 mt%0 %1
8383 mt%0 %1
ca7f5001
RK		 8384 {l%U1%X1|lwz%U1%X1} %0,%1
8385 {st%U0%U1|stw%U0%U1} %1,%0"
2c4a9cff 8386 [(set (attr "type")
4eb585a4 8387 (cond [(eq_attr "alternative" "0,3")
2c4a9cff
DE		 8388 (const_string "cr_logical")
8389 (eq_attr "alternative" "1,2")
8390 (const_string "mtcr")
4eb585a4 8391 (eq_attr "alternative" "6,7,9")
2c4a9cff 8392 (const_string "integer")
2c4a9cff 8393 (eq_attr "alternative" "8")
4eb585a4
DE		 8394 (const_string "mfjmpr")
8395 (eq_attr "alternative" "10")
2c4a9cff 8396 (const_string "mtjmpr")
4eb585a4 8397 (eq_attr "alternative" "11")
2c4a9cff 8398 (const_string "load")
4eb585a4 8399 (eq_attr "alternative" "12")
2c4a9cff
DE		 8400 (const_string "store")
8401 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8402 (const_string "mfcrf")
8403 ]
8404 (const_string "mfcr")))
4eb585a4 8405 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
1fd4e8c1 8406\f
e52e05ca
MM		 8407;; For floating-point, we normally deal with the floating-point registers
8408;; unless -msoft-float is used. The sole exception is that parameter passing
8409;; can produce floating-point values in fixed-point registers. Unless the
8410;; value is a simple constant or already in memory, we deal with this by
8411;; allocating memory and copying the value explicitly via that memory location.
1fd4e8c1
RK		 8412(define_expand "movsf"
8413 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8414 (match_operand:SF 1 "any_operand" ""))]
8415 ""
fb4d4348 8416 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
1fd4e8c1 8417
1fd4e8c1 8418(define_split
cd2b37d9 8419 [(set (match_operand:SF 0 "gpc_reg_operand" "")
c4c40373 8420 (match_operand:SF 1 "const_double_operand" ""))]
f99f88e0 8421 "reload_completed
5ae4759c
MM		 8422 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8423 || (GET_CODE (operands[0]) == SUBREG
8424 && GET_CODE (SUBREG_REG (operands[0])) == REG
8425 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373 8426 [(set (match_dup 2) (match_dup 3))]
685f3906
DE		 8427 "
8428{
8429 long l;
8430 REAL_VALUE_TYPE rv;
8431
8432 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8433 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
c4c40373 8434
f99f88e0
DE		 8435 if (! TARGET_POWERPC64)
8436 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8437 else
8438 operands[2] = gen_lowpart (SImode, operands[0]);
a260abc9 8439
2496c7bd 8440 operands[3] = gen_int_mode (l, SImode);
a260abc9
DE		 8441}")
8442
c4c40373 8443(define_insn "*movsf_hardfloat"
fb3249ef 8444 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
ae6669e7 8445 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
d14a6d05 8446 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6 8447 || gpc_reg_operand (operands[1], SFmode))
696e45ba 8448 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
1fd4e8c1 8449 "@
f99f88e0
DE		 8450 mr %0,%1
8451 {l%U1%X1|lwz%U1%X1} %0,%1
8452 {st%U0%X0|stw%U0%X0} %1,%0
1fd4e8c1
RK		 8453 fmr %0,%1
8454 lfs%U1%X1 %0,%1
c4c40373 8455 stfs%U0%X0 %1,%0
b991a865
GK		 8456 mt%0 %1
8457 mt%0 %1
8458 mf%1 %0
e0740893 8459 {cror 0,0,0|nop}
c4c40373
MM		 8460 #
8461 #"
9c6fdb46 8462 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
ae6669e7 8463 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
d14a6d05 8464
c4c40373 8465(define_insn "*movsf_softfloat"
dd0fbae2
MK		 8466 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8467 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
d14a6d05 8468 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 8469 || gpc_reg_operand (operands[1], SFmode))
8470 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
d14a6d05
MM		 8471 "@
8472 mr %0,%1
b991a865
GK		 8473 mt%0 %1
8474 mt%0 %1
8475 mf%1 %0
d14a6d05
MM		 8476 {l%U1%X1|lwz%U1%X1} %0,%1
8477 {st%U0%X0|stw%U0%X0} %1,%0
8478 {lil|li} %0,%1
802a0058 8479 {liu|lis} %0,%v1
aee86b38 8480 {cal|la} %0,%a1
c4c40373 8481 #
dd0fbae2
MK		 8482 #
8483 {cror 0,0,0|nop}"
9c6fdb46 8484 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
dd0fbae2 8485 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
d14a6d05 8486
1fd4e8c1
RK		 8487\f
8488(define_expand "movdf"
8489 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8490 (match_operand:DF 1 "any_operand" ""))]
8491 ""
fb4d4348 8492 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
1fd4e8c1
RK		 8493
8494(define_split
cd2b37d9 8495 [(set (match_operand:DF 0 "gpc_reg_operand" "")
c4c40373 8496 (match_operand:DF 1 "const_int_operand" ""))]
a260abc9 8497 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8498 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8499 || (GET_CODE (operands[0]) == SUBREG
8500 && GET_CODE (SUBREG_REG (operands[0])) == REG
8501 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8502 [(set (match_dup 2) (match_dup 4))
8503 (set (match_dup 3) (match_dup 1))]
8504 "
8505{
5ae4759c 8506 int endian = (WORDS_BIG_ENDIAN == 0);
5f59ecb7
DE		 8507 HOST_WIDE_INT value = INTVAL (operands[1]);
8508
5ae4759c
MM		 8509 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8510 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5f59ecb7
DE		 8511#if HOST_BITS_PER_WIDE_INT == 32
8512 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8513#else
8514 operands[4] = GEN_INT (value >> 32);
a65c591c 8515 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
5f59ecb7 8516#endif
c4c40373
MM		 8517}")
8518
c4c40373
MM		 8519(define_split
8520 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8521 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8522 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8523 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8524 || (GET_CODE (operands[0]) == SUBREG
8525 && GET_CODE (SUBREG_REG (operands[0])) == REG
8526 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8527 [(set (match_dup 2) (match_dup 4))
8528 (set (match_dup 3) (match_dup 5))]
8529 "
8530{
5ae4759c 8531 int endian = (WORDS_BIG_ENDIAN == 0);
47ad8c61
MM		 8532 long l[2];
8533 REAL_VALUE_TYPE rv;
8534
8535 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8536 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8537
5ae4759c
MM		 8538 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8539 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
2496c7bd
LB		 8540 operands[4] = gen_int_mode (l[endian], SImode);
8541 operands[5] = gen_int_mode (l[1 - endian], SImode);
c4c40373
MM		 8542}")
8543
efc08378
DE		 8544(define_split
8545 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8308679f 8546 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8547 "TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8548 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8549 || (GET_CODE (operands[0]) == SUBREG
8550 && GET_CODE (SUBREG_REG (operands[0])) == REG
8551 && REGNO (SUBREG_REG (operands[0])) <= 31))"
a260abc9 8552 [(set (match_dup 2) (match_dup 3))]
5ae4759c 8553 "
a260abc9
DE		 8554{
8555 int endian = (WORDS_BIG_ENDIAN == 0);
8556 long l[2];
8557 REAL_VALUE_TYPE rv;
4977bab6 8558#if HOST_BITS_PER_WIDE_INT >= 64
5b029315 8559 HOST_WIDE_INT val;
4977bab6 8560#endif
a260abc9
DE		 8561
8562 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8563 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8564
8565 operands[2] = gen_lowpart (DImode, operands[0]);
8566 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
5b029315 8567#if HOST_BITS_PER_WIDE_INT >= 64
a2419b96
DE		 8568 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8569 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
5b029315 8570
f5264b52 8571 operands[3] = gen_int_mode (val, DImode);
5b029315 8572#else
a260abc9 8573 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
5b029315 8574#endif
a260abc9 8575}")
efc08378 8576
4eae5fe1 8577;; Don't have reload use general registers to load a constant. First,
1427100a 8578;; it might not work if the output operand is the equivalent of
4eae5fe1
RK		 8579;; a non-offsettable memref, but also it is less efficient than loading
8580;; the constant into an FP register, since it will probably be used there.
8581;; The "??" is a kludge until we can figure out a more reasonable way
8582;; of handling these non-offsettable values.
c4c40373 8583(define_insn "*movdf_hardfloat32"
799dbb0f
ME		 8584 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,d,d,m,!r,!r,!r")
8585 (match_operand:DF 1 "input_operand" "r,m,r,d,m,d,G,H,F"))]
696e45ba 8586 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
52d3af72
DE		 8587 && (gpc_reg_operand (operands[0], DFmode)
8588 || gpc_reg_operand (operands[1], DFmode))"
e7113111
RK		 8589 "*
8590{
8591 switch (which_alternative)
8592 {
a260abc9 8593 default:
37409796 8594 gcc_unreachable ();
e7113111
RK		 8595 case 0:
8596 /* We normally copy the low-numbered register first. However, if
000034eb
DE		 8597 the first register operand 0 is the same as the second register
8598 of operand 1, we must copy in the opposite order. */
e7113111 8599 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
deb9225a 8600 return \"mr %L0,%L1\;mr %0,%1\";
e7113111 8601 else
deb9225a 8602 return \"mr %0,%1\;mr %L0,%L1\";
e7113111 8603 case 1:
d04b6e6e
EB		 8604 if (rs6000_offsettable_memref_p (operands[1])
8605 || (GET_CODE (operands[1]) == MEM
8606 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8607 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
6fb5fa3c
DB		 8608 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8609 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
000034eb
DE		 8610 {
8611 /* If the low-address word is used in the address, we must load
8612 it last. Otherwise, load it first. Note that we cannot have
8613 auto-increment in that case since the address register is
8614 known to be dead. */
8615 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8616 operands[1], 0))
8617 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8618 else
6fb5fa3c 8619 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
000034eb 8620 }
e7113111 8621 else
000034eb
DE		 8622 {
8623 rtx addreg;
8624
000034eb
DE		 8625 addreg = find_addr_reg (XEXP (operands[1], 0));
8626 if (refers_to_regno_p (REGNO (operands[0]),
8627 REGNO (operands[0]) + 1,
8628 operands[1], 0))
8629 {
8630 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8631 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb 8632 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
2284bd2b 8633 return \"{l%X1|lwz%X1} %0,%1\";
000034eb
DE		 8634 }
8635 else
8636 {
2284bd2b 8637 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
000034eb 8638 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8639 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb
DE		 8640 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8641 return \"\";
8642 }
8643 }
e7113111 8644 case 2:
d04b6e6e
EB		 8645 if (rs6000_offsettable_memref_p (operands[0])
8646 || (GET_CODE (operands[0]) == MEM
8647 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8648 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
6fb5fa3c
DB		 8649 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8650 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8651 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
000034eb
DE		 8652 else
8653 {
8654 rtx addreg;
8655
000034eb 8656 addreg = find_addr_reg (XEXP (operands[0], 0));
2284bd2b 8657 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
000034eb 8658 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8659 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
000034eb
DE		 8660 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8661 return \"\";
8662 }
e7113111 8663 case 3:
914a7297 8664 return \"fmr %0,%1\";
e7113111 8665 case 4:
914a7297 8666 return \"lfd%U1%X1 %0,%1\";
e7113111 8667 case 5:
914a7297 8668 return \"stfd%U0%X0 %1,%0\";
e7113111 8669 case 6:
c4c40373 8670 case 7:
c4c40373 8671 case 8:
914a7297 8672 return \"#\";
e7113111
RK		 8673 }
8674}"
943c15ed 8675 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
914a7297 8676 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
51b8fc2c 8677
c4c40373 8678(define_insn "*movdf_softfloat32"
1427100a
DE		 8679 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8680 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
696e45ba 8681 "! TARGET_POWERPC64
82ad047f 8682 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
696e45ba 8683 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
52d3af72
DE		 8684 && (gpc_reg_operand (operands[0], DFmode)
8685 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca
MM		 8686 "*
8687{
8688 switch (which_alternative)
8689 {
a260abc9 8690 default:
37409796 8691 gcc_unreachable ();
dc4f83ca
MM		 8692 case 0:
8693 /* We normally copy the low-numbered register first. However, if
8694 the first register operand 0 is the same as the second register of
8695 operand 1, we must copy in the opposite order. */
8696 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8697 return \"mr %L0,%L1\;mr %0,%1\";
8698 else
8699 return \"mr %0,%1\;mr %L0,%L1\";
8700 case 1:
3cb999d8
DE		 8701 /* If the low-address word is used in the address, we must load
8702 it last. Otherwise, load it first. Note that we cannot have
8703 auto-increment in that case since the address register is
8704 known to be dead. */
dc4f83ca 8705 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3cb999d8 8706 operands[1], 0))
dc4f83ca
MM		 8707 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8708 else
6fb5fa3c 8709 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
dc4f83ca 8710 case 2:
6fb5fa3c 8711 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
dc4f83ca 8712 case 3:
c4c40373
MM		 8713 case 4:
8714 case 5:
dc4f83ca
MM		 8715 return \"#\";
8716 }
8717}"
943c15ed 8718 [(set_attr "type" "two,load,store,*,*,*")
c4c40373 8719 (set_attr "length" "8,8,8,8,12,16")])
dc4f83ca 8720
44cd321e
PS		 8721; ld/std require word-aligned displacements -> 'Y' constraint.
8722; List Y->r and r->Y before r->r for reload.
8723(define_insn "*movdf_hardfloat64_mfpgpr"
799dbb0f
ME		 8724 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r,r,d")
8725 (match_operand:DF 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F,d,r"))]
696e45ba
ME		 8726 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8727 && TARGET_DOUBLE_FLOAT
44cd321e
PS		 8728 && (gpc_reg_operand (operands[0], DFmode)
8729 || gpc_reg_operand (operands[1], DFmode))"
8730 "@
8731 std%U0%X0 %1,%0
8732 ld%U1%X1 %0,%1
8733 mr %0,%1
8734 fmr %0,%1
8735 lfd%U1%X1 %0,%1
8736 stfd%U0%X0 %1,%0
8737 mt%0 %1
8738 mf%1 %0
8739 {cror 0,0,0|nop}
8740 #
8741 #
8742 #
8743 mftgpr %0,%1
8744 mffgpr %0,%1"
8745 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8746 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8747
d2288d5d
HP		 8748; ld/std require word-aligned displacements -> 'Y' constraint.
8749; List Y->r and r->Y before r->r for reload.
c4c40373 8750(define_insn "*movdf_hardfloat64"
799dbb0f
ME		 8751 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,d,d,m,*c*l,!r,*h,!r,!r,!r")
8752 (match_operand:DF 1 "input_operand" "r,Y,r,d,m,d,r,h,0,G,H,F"))]
696e45ba
ME		 8753 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8754 && TARGET_DOUBLE_FLOAT
52d3af72
DE		 8755 && (gpc_reg_operand (operands[0], DFmode)
8756 || gpc_reg_operand (operands[1], DFmode))"
51b8fc2c 8757 "@
96bb8ed3 8758 std%U0%X0 %1,%0
3364872d
FJ		 8759 ld%U1%X1 %0,%1
8760 mr %0,%1
3d5570cb 8761 fmr %0,%1
f63184ac 8762 lfd%U1%X1 %0,%1
914a7297
DE		 8763 stfd%U0%X0 %1,%0
8764 mt%0 %1
8765 mf%1 %0
e0740893 8766 {cror 0,0,0|nop}
914a7297
DE		 8767 #
8768 #
8769 #"
9c6fdb46 8770 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
ae6669e7 8771 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
dc4f83ca 8772
c4c40373 8773(define_insn "*movdf_softfloat64"
d2288d5d
HP		 8774 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8775 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
a3170dc6 8776 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
52d3af72
DE		 8777 && (gpc_reg_operand (operands[0], DFmode)
8778 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca 8779 "@
d2288d5d
HP		 8780 ld%U1%X1 %0,%1
8781 std%U0%X0 %1,%0
dc4f83ca 8782 mr %0,%1
914a7297
DE		 8783 mt%0 %1
8784 mf%1 %0
c4c40373
MM		 8785 #
8786 #
e2d0915c 8787 #
e0740893 8788 {cror 0,0,0|nop}"
9c6fdb46 8789 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
e2d0915c 8790 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
1fd4e8c1 8791\f
06f4e019
DE		 8792(define_expand "movtf"
8793 [(set (match_operand:TF 0 "general_operand" "")
8794 (match_operand:TF 1 "any_operand" ""))]
8521c414 8795 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8796 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8797
a9baceb1
GK		 8798; It's important to list the o->f and f->o moves before f->f because
8799; otherwise reload, given m->f, will try to pick f->f and reload it,
409f61cd 8800; which doesn't make progress. Likewise r->Y must be before r->r.
a9baceb1 8801(define_insn_and_split "*movtf_internal"
799dbb0f
ME		 8802 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
8803 (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
602ea4d3 8804 "!TARGET_IEEEQUAD
39e63627 8805 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
06f4e019
DE		 8806 && (gpc_reg_operand (operands[0], TFmode)
8807 || gpc_reg_operand (operands[1], TFmode))"
a9baceb1 8808 "#"
ecb62ae7 8809 "&& reload_completed"
a9baceb1
GK		 8810 [(pc)]
8811{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
112ccb83 8812 [(set_attr "length" "8,8,8,20,20,16")])
06f4e019 8813
8521c414 8814(define_insn_and_split "*movtf_softfloat"
17caeff2 8815 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8521c414
JM		 8816 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8817 "!TARGET_IEEEQUAD
8818 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8819 && (gpc_reg_operand (operands[0], TFmode)
8820 || gpc_reg_operand (operands[1], TFmode))"
8821 "#"
8822 "&& reload_completed"
8823 [(pc)]
8824{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8825 [(set_attr "length" "20,20,16")])
8826
ecb62ae7 8827(define_expand "extenddftf2"
17caeff2
JM		 8828 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8829 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8830 "!TARGET_IEEEQUAD
8831 && TARGET_HARD_FLOAT
8832 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8833 && TARGET_LONG_DOUBLE_128"
8834{
8835 if (TARGET_E500_DOUBLE)
8836 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8837 else
8838 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8839 DONE;
8840})
8841
8842(define_expand "extenddftf2_fprs"
ecb62ae7
GK		 8843 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8844 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8845 (use (match_dup 2))])]
602ea4d3 8846 "!TARGET_IEEEQUAD
696e45ba
ME		 8847 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8848 && TARGET_LONG_DOUBLE_128"
06f4e019 8849{
ecb62ae7 8850 operands[2] = CONST0_RTX (DFmode);
aa9cf005
DE		 8851 /* Generate GOT reference early for SVR4 PIC. */
8852 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8853 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
ecb62ae7 8854})
06f4e019 8855
ecb62ae7 8856(define_insn_and_split "*extenddftf2_internal"
799dbb0f
ME		 8857 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
8858 (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
8859 (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
602ea4d3 8860 "!TARGET_IEEEQUAD
696e45ba
ME		 8861 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8862 && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8863 "#"
8864 "&& reload_completed"
8865 [(pc)]
06f4e019 8866{
ecb62ae7
GK		 8867 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8868 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8869 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8870 operands[1]);
8871 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8872 operands[2]);
8873 DONE;
6ae08853 8874})
ecb62ae7
GK		 8875
8876(define_expand "extendsftf2"
8877 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8878 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
602ea4d3 8879 "!TARGET_IEEEQUAD
17caeff2
JM		 8880 && TARGET_HARD_FLOAT
8881 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8882 && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8883{
8884 rtx tmp = gen_reg_rtx (DFmode);
8885 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8886 emit_insn (gen_extenddftf2 (operands[0], tmp));
8887 DONE;
8888})
06f4e019 8889
8cb320b8 8890(define_expand "trunctfdf2"
589b3fda
DE		 8891 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8892 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 8893 "!TARGET_IEEEQUAD
17caeff2
JM		 8894 && TARGET_HARD_FLOAT
8895 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8896 && TARGET_LONG_DOUBLE_128"
589b3fda 8897 "")
8cb320b8
DE		 8898
8899(define_insn_and_split "trunctfdf2_internal1"
799dbb0f
ME		 8900 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8901 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
602ea4d3 8902 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8cb320b8
DE		 8903 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8904 "@
8905 #
8906 fmr %0,%1"
8907 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8908 [(const_int 0)]
8909{
8910 emit_note (NOTE_INSN_DELETED);
8911 DONE;
8912}
8913 [(set_attr "type" "fp")])
8914
8915(define_insn "trunctfdf2_internal2"
799dbb0f
ME		 8916 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8917 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
602ea4d3 8918 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
696e45ba
ME		 8919 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8920 && TARGET_LONG_DOUBLE_128"
06f4e019 8921 "fadd %0,%1,%L1"
0bb7b92e
ME		 8922 [(set_attr "type" "fp")
8923 (set_attr "fp_type" "fp_addsub_d")])
06f4e019 8924
17caeff2
JM		 8925(define_expand "trunctfsf2"
8926 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8927 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8928 "!TARGET_IEEEQUAD
8929 && TARGET_HARD_FLOAT
8930 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8931 && TARGET_LONG_DOUBLE_128"
8932{
8933 if (TARGET_E500_DOUBLE)
8934 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8935 else
8936 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8937 DONE;
8938})
8939
8940(define_insn_and_split "trunctfsf2_fprs"
06f4e019 8941 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
799dbb0f
ME		 8942 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8943 (clobber (match_scratch:DF 2 "=d"))]
602ea4d3 8944 "!TARGET_IEEEQUAD
696e45ba
ME		 8945 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8946 && TARGET_LONG_DOUBLE_128"
06f4e019 8947 "#"
ea112fc4 8948 "&& reload_completed"
06f4e019
DE		 8949 [(set (match_dup 2)
8950 (float_truncate:DF (match_dup 1)))
8951 (set (match_dup 0)
8952 (float_truncate:SF (match_dup 2)))]
ea112fc4 8953 "")
06f4e019 8954
0c90aa3c 8955(define_expand "floatsitf2"
d29b7f64
DE		 8956 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8957 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
602ea4d3 8958 "!TARGET_IEEEQUAD
17caeff2
JM		 8959 && TARGET_HARD_FLOAT
8960 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8961 && TARGET_LONG_DOUBLE_128"
0c90aa3c
GK		 8962{
8963 rtx tmp = gen_reg_rtx (DFmode);
8964 expand_float (tmp, operands[1], false);
8965 emit_insn (gen_extenddftf2 (operands[0], tmp));
8966 DONE;
8967})
06f4e019 8968
ecb62ae7
GK		 8969; fadd, but rounding towards zero.
8970; This is probably not the optimal code sequence.
8971(define_insn "fix_trunc_helper"
799dbb0f
ME		 8972 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8973 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
ecb62ae7 8974 UNSPEC_FIX_TRUNC_TF))
799dbb0f 8975 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
696e45ba 8976 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
ecb62ae7
GK		 8977 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8978 [(set_attr "type" "fp")
8979 (set_attr "length" "20")])
8980
0c90aa3c 8981(define_expand "fix_trunctfsi2"
17caeff2
JM		 8982 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8983 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8984 "!TARGET_IEEEQUAD
8985 && (TARGET_POWER2 || TARGET_POWERPC)
8986 && TARGET_HARD_FLOAT
8987 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8988 && TARGET_LONG_DOUBLE_128"
8989{
8990 if (TARGET_E500_DOUBLE)
8991 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8992 else
8993 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8994 DONE;
8995})
8996
8997(define_expand "fix_trunctfsi2_fprs"
ecb62ae7
GK		 8998 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8999 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9000 (clobber (match_dup 2))
9001 (clobber (match_dup 3))
9002 (clobber (match_dup 4))
9003 (clobber (match_dup 5))])]
602ea4d3 9004 "!TARGET_IEEEQUAD
ecb62ae7
GK		 9005 && (TARGET_POWER2 || TARGET_POWERPC)
9006 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9007{
9008 operands[2] = gen_reg_rtx (DFmode);
9009 operands[3] = gen_reg_rtx (DFmode);
9010 operands[4] = gen_reg_rtx (DImode);
9011 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
9012})
9013
9014(define_insn_and_split "*fix_trunctfsi2_internal"
61c07d3c 9015 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
799dbb0f
ME		 9016 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9017 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9018 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9019 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
b0d6c7d8 9020 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
602ea4d3 9021 "!TARGET_IEEEQUAD
39e63627 9022 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 9023 "#"
b3a13419 9024 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
ecb62ae7 9025 [(pc)]
0c90aa3c 9026{
ecb62ae7
GK		 9027 rtx lowword;
9028 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9029
230215f5
GK		 9030 gcc_assert (MEM_P (operands[5]));
9031 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
ecb62ae7
GK		 9032
9033 emit_insn (gen_fctiwz (operands[4], operands[2]));
9034 emit_move_insn (operands[5], operands[4]);
230215f5 9035 emit_move_insn (operands[0], lowword);
0c90aa3c
GK		 9036 DONE;
9037})
06f4e019 9038
17caeff2
JM		 9039(define_expand "negtf2"
9040 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9041 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9042 "!TARGET_IEEEQUAD
9043 && TARGET_HARD_FLOAT
9044 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9045 && TARGET_LONG_DOUBLE_128"
9046 "")
9047
9048(define_insn "negtf2_internal"
799dbb0f
ME		 9049 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9050 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
602ea4d3 9051 "!TARGET_IEEEQUAD
39e63627 9052 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 9053 "*
9054{
9055 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9056 return \"fneg %L0,%L1\;fneg %0,%1\";
9057 else
9058 return \"fneg %0,%1\;fneg %L0,%L1\";
9059}"
9060 [(set_attr "type" "fp")
9061 (set_attr "length" "8")])
9062
1a402dc1 9063(define_expand "abstf2"
17caeff2
JM		 9064 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9065 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 9066 "!TARGET_IEEEQUAD
17caeff2
JM		 9067 && TARGET_HARD_FLOAT
9068 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9069 && TARGET_LONG_DOUBLE_128"
1a402dc1 9070 "
06f4e019 9071{
1a402dc1 9072 rtx label = gen_label_rtx ();
17caeff2
JM		 9073 if (TARGET_E500_DOUBLE)
9074 {
1cdc0d8f 9075 if (flag_finite_math_only && !flag_trapping_math)
17caeff2
JM		 9076 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9077 else
9078 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9079 }
9080 else
9081 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
1a402dc1
AM		 9082 emit_label (label);
9083 DONE;
9084}")
06f4e019 9085
1a402dc1 9086(define_expand "abstf2_internal"
e42ac3de
RS		 9087 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9088 (match_operand:TF 1 "gpc_reg_operand" ""))
1a402dc1
AM		 9089 (set (match_dup 3) (match_dup 5))
9090 (set (match_dup 5) (abs:DF (match_dup 5)))
9091 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9092 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9093 (label_ref (match_operand 2 "" ""))
9094 (pc)))
9095 (set (match_dup 6) (neg:DF (match_dup 6)))]
602ea4d3 9096 "!TARGET_IEEEQUAD
696e45ba
ME		 9097 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9098 && TARGET_LONG_DOUBLE_128"
1a402dc1 9099 "
06f4e019 9100{
1a402dc1
AM		 9101 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9102 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9103 operands[3] = gen_reg_rtx (DFmode);
9104 operands[4] = gen_reg_rtx (CCFPmode);
9105 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9106 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9107}")
06f4e019 9108\f
1fd4e8c1
RK		 9109;; Next come the multi-word integer load and store and the load and store
9110;; multiple insns.
1fd4e8c1 9111
112ccb83
GK		 9112; List r->r after r->"o<>", otherwise reload will try to reload a
9113; non-offsettable address by using r->r which won't make progress.
acad7ed3 9114(define_insn "*movdi_internal32"
799dbb0f
ME		 9115 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r")
9116 (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF"))]
a260abc9 9117 "! TARGET_POWERPC64
4e74d8ec
MM		 9118 && (gpc_reg_operand (operands[0], DImode)
9119 || gpc_reg_operand (operands[1], DImode))"
112ccb83
GK		 9120 "@
9121 #
9122 #
9123 #
9124 fmr %0,%1
9125 lfd%U1%X1 %0,%1
9126 stfd%U0%X0 %1,%0
9127 #"
9128 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
4e74d8ec
MM		 9129
9130(define_split
9131 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9132 (match_operand:DI 1 "const_int_operand" ""))]
a260abc9 9133 "! TARGET_POWERPC64 && reload_completed"
4e74d8ec
MM		 9134 [(set (match_dup 2) (match_dup 4))
9135 (set (match_dup 3) (match_dup 1))]
9136 "
9137{
5f59ecb7 9138 HOST_WIDE_INT value = INTVAL (operands[1]);
bdaa0181
GK		 9139 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9140 DImode);
9141 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9142 DImode);
75d39459 9143#if HOST_BITS_PER_WIDE_INT == 32
5f59ecb7 9144 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
75d39459 9145#else
5f59ecb7 9146 operands[4] = GEN_INT (value >> 32);
a65c591c 9147 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
75d39459 9148#endif
4e74d8ec
MM		 9149}")
9150
3a1f863f 9151(define_split
17caeff2 9152 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
3a1f863f 9153 (match_operand:DI 1 "input_operand" ""))]
6ae08853 9154 "reload_completed && !TARGET_POWERPC64
3a1f863f 9155 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 9156 [(pc)]
9157{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
3a1f863f 9158
44cd321e 9159(define_insn "*movdi_mfpgpr"
799dbb0f
ME		 9160 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
9161 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
44cd321e
PS		 9162 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9163 && (gpc_reg_operand (operands[0], DImode)
9164 || gpc_reg_operand (operands[1], DImode))"
9165 "@
9166 mr %0,%1
9167 ld%U1%X1 %0,%1
9168 std%U0%X0 %1,%0
9169 li %0,%1
9170 lis %0,%v1
9171 #
9172 {cal|la} %0,%a1
9173 fmr %0,%1
9174 lfd%U1%X1 %0,%1
9175 stfd%U0%X0 %1,%0
9176 mf%1 %0
9177 mt%0 %1
9178 {cror 0,0,0|nop}
9179 mftgpr %0,%1
9180 mffgpr %0,%1"
9181 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
9182 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
9183
acad7ed3 9184(define_insn "*movdi_internal64"
799dbb0f
ME		 9185 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h")
9186 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0"))]
44cd321e 9187 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
4e74d8ec
MM		 9188 && (gpc_reg_operand (operands[0], DImode)
9189 || gpc_reg_operand (operands[1], DImode))"
51b8fc2c 9190 "@
3d5570cb
RK		 9191 mr %0,%1
9192 ld%U1%X1 %0,%1
96bb8ed3 9193 std%U0%X0 %1,%0
3d5570cb 9194 li %0,%1
802a0058 9195 lis %0,%v1
e6ca2c17 9196 #
aee86b38 9197 {cal|la} %0,%a1
3d5570cb
RK		 9198 fmr %0,%1
9199 lfd%U1%X1 %0,%1
9200 stfd%U0%X0 %1,%0
9201 mf%1 %0
08075ead 9202 mt%0 %1
e34eaae5 9203 {cror 0,0,0|nop}"
02ca7595 9204 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
e6ca2c17
DE		 9205 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9206
5f59ecb7 9207;; immediate value valid for a single instruction hiding in a const_double
a260abc9
DE		 9208(define_insn ""
9209 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9210 (match_operand:DI 1 "const_double_operand" "F"))]
5f59ecb7
DE		 9211 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9212 && GET_CODE (operands[1]) == CONST_DOUBLE
a260abc9
DE		 9213 && num_insns_constant (operands[1], DImode) == 1"
9214 "*
9215{
9216 return ((unsigned HOST_WIDE_INT)
9217 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9218 ? \"li %0,%1\" : \"lis %0,%v1\";
9219}")
9220
a260abc9
DE		 9221;; Generate all one-bits and clear left or right.
9222;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9223(define_split
9224 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1990cd79 9225 (match_operand:DI 1 "mask64_operand" ""))]
a260abc9
DE		 9226 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9227 [(set (match_dup 0) (const_int -1))
e6ca2c17 9228 (set (match_dup 0)
a260abc9
DE		 9229 (and:DI (rotate:DI (match_dup 0)
9230 (const_int 0))
9231 (match_dup 1)))]
9232 "")
9233
9234;; Split a load of a large constant into the appropriate five-instruction
9235;; sequence. Handle anything in a constant number of insns.
9236;; When non-easy constants can go in the TOC, this should use
9237;; easy_fp_constant predicate.
9238(define_split
9239 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 9240 (match_operand:DI 1 "const_int_operand" ""))]
9241 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9242 [(set (match_dup 0) (match_dup 2))
9243 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
e6ca2c17 9244 "
2bfcf297
DB		 9245{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9246
9247 if (tem == operands[0])
9248 DONE;
e8d791dd 9249 else
2bfcf297 9250 FAIL;
5f59ecb7 9251}")
e6ca2c17 9252
5f59ecb7
DE		 9253(define_split
9254 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 9255 (match_operand:DI 1 "const_double_operand" ""))]
9256 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9257 [(set (match_dup 0) (match_dup 2))
9258 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5f59ecb7 9259 "
2bfcf297
DB		 9260{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9261
9262 if (tem == operands[0])
9263 DONE;
9264 else
9265 FAIL;
e6ca2c17 9266}")
acad7ed3 9267\f
1fd4e8c1
RK		 9268;; TImode is similar, except that we usually want to compute the address into
9269;; a register and use lsi/stsi (the exception is during reload). MQ is also
ca7f5001 9270;; clobbered in stsi for POWER, so we need a SCRATCH for it.
1fd4e8c1
RK		 9271
9272;; We say that MQ is clobbered in the last alternative because the first
9273;; alternative would never get used otherwise since it would need a reload
9274;; while the 2nd alternative would not. We put memory cases first so they
9275;; are preferred. Otherwise, we'd try to reload the output instead of
9276;; giving the SCRATCH mq.
3a1f863f 9277
a260abc9 9278(define_insn "*movti_power"
7f514158
AM		 9279 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9280 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9281 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
6ae08853 9282 "TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca 9283 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
1fd4e8c1
RK		 9284 "*
9285{
9286 switch (which_alternative)
9287 {
dc4f83ca 9288 default:
37409796 9289 gcc_unreachable ();
dc4f83ca 9290
1fd4e8c1 9291 case 0:
3a1f863f
DE		 9292 if (TARGET_STRING)
9293 return \"{stsi|stswi} %1,%P0,16\";
1fd4e8c1 9294 case 1:
1fd4e8c1 9295 case 2:
3a1f863f 9296 return \"#\";
1fd4e8c1
RK		 9297 case 3:
9298 /* If the address is not used in the output, we can use lsi. Otherwise,
9299 fall through to generating four loads. */
e876481c
DE		 9300 if (TARGET_STRING
9301 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
ca7f5001 9302 return \"{lsi|lswi} %0,%P1,16\";
82e41834 9303 /* ... fall through ... */
1fd4e8c1 9304 case 4:
7f514158 9305 case 5:
3a1f863f 9306 return \"#\";
1fd4e8c1
RK		 9307 }
9308}"
7f514158 9309 [(set_attr "type" "store,store,*,load,load,*")])
51b8fc2c 9310
a260abc9 9311(define_insn "*movti_string"
7f514158
AM		 9312 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9313 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
3a1f863f 9314 "! TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca
MM		 9315 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9316 "*
9317{
9318 switch (which_alternative)
9319 {
9320 default:
37409796 9321 gcc_unreachable ();
dc4f83ca 9322 case 0:
3a1f863f
DE		 9323 if (TARGET_STRING)
9324 return \"{stsi|stswi} %1,%P0,16\";
dc4f83ca 9325 case 1:
cd1d3445 9326 case 2:
3a1f863f 9327 return \"#\";
cd1d3445
DE		 9328 case 3:
9329 /* If the address is not used in the output, we can use lsi. Otherwise,
9330 fall through to generating four loads. */
6ae08853 9331 if (TARGET_STRING
3a1f863f 9332 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
cd1d3445
DE		 9333 return \"{lsi|lswi} %0,%P1,16\";
9334 /* ... fall through ... */
9335 case 4:
7f514158 9336 case 5:
3a1f863f 9337 return \"#\";
dc4f83ca
MM		 9338 }
9339}"
c921bad8
AP		 9340 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
9341 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
9342 (const_string "always")
9343 (const_string "conditional")))])
dc4f83ca 9344
a260abc9 9345(define_insn "*movti_ppc64"
112ccb83
GK		 9346 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9347 (match_operand:TI 1 "input_operand" "r,r,m"))]
51b8fc2c
RK		 9348 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9349 || gpc_reg_operand (operands[1], TImode))"
112ccb83 9350 "#"
0be77bf2 9351 [(set_attr "type" "*,store,load")])
3a1f863f 9352
7f514158
AM		 9353(define_split
9354 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9355 (match_operand:TI 1 "const_double_operand" ""))]
9356 "TARGET_POWERPC64"
9357 [(set (match_dup 2) (match_dup 4))
9358 (set (match_dup 3) (match_dup 5))]
9359 "
9360{
9361 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9362 TImode);
9363 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9364 TImode);
9365 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9366 {
9367 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9368 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9369 }
9370 else if (GET_CODE (operands[1]) == CONST_INT)
9371 {
9372 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9373 operands[5] = operands[1];
9374 }
9375 else
9376 FAIL;
9377}")
9378
3a1f863f
DE		 9379(define_split
9380 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9381 (match_operand:TI 1 "input_operand" ""))]
a9baceb1 9382 "reload_completed
3a1f863f 9383 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 9384 [(pc)]
9385{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
1fd4e8c1
RK		 9386\f
9387(define_expand "load_multiple"
2f622005
RK		 9388 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9389 (match_operand:SI 1 "" ""))
9390 (use (match_operand:SI 2 "" ""))])]
09a625f7 9391 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9392 "
9393{
9394 int regno;
9395 int count;
792760b9 9396 rtx op1;
1fd4e8c1
RK		 9397 int i;
9398
9399 /* Support only loading a constant number of fixed-point registers from
9400 memory and only bother with this if more than two; the machine
9401 doesn't support more than eight. */
9402 if (GET_CODE (operands[2]) != CONST_INT
9403 || INTVAL (operands[2]) <= 2
9404 || INTVAL (operands[2]) > 8
9405 || GET_CODE (operands[1]) != MEM
9406 || GET_CODE (operands[0]) != REG
9407 || REGNO (operands[0]) >= 32)
9408 FAIL;
9409
9410 count = INTVAL (operands[2]);
9411 regno = REGNO (operands[0]);
9412
39403d82 9413 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
792760b9
RK		 9414 op1 = replace_equiv_address (operands[1],
9415 force_reg (SImode, XEXP (operands[1], 0)));
1fd4e8c1
RK		 9416
9417 for (i = 0; i < count; i++)
9418 XVECEXP (operands[3], 0, i)
39403d82 9419 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
7ef788f0 9420 adjust_address_nv (op1, SImode, i * 4));
1fd4e8c1
RK		 9421}")
9422
9caa3eb2 9423(define_insn "*ldmsi8"
1fd4e8c1 9424 [(match_parallel 0 "load_multiple_operation"
9caa3eb2
DE		 9425 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9426 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9427 (set (match_operand:SI 3 "gpc_reg_operand" "")
9428 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9429 (set (match_operand:SI 4 "gpc_reg_operand" "")
9430 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9431 (set (match_operand:SI 5 "gpc_reg_operand" "")
9432 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9433 (set (match_operand:SI 6 "gpc_reg_operand" "")
9434 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9435 (set (match_operand:SI 7 "gpc_reg_operand" "")
9436 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9437 (set (match_operand:SI 8 "gpc_reg_operand" "")
9438 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9439 (set (match_operand:SI 9 "gpc_reg_operand" "")
9440 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9441 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
1fd4e8c1 9442 "*
9caa3eb2 9443{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9444 [(set_attr "type" "load_ux")
9caa3eb2 9445 (set_attr "length" "32")])
1fd4e8c1 9446
9caa3eb2
DE		 9447(define_insn "*ldmsi7"
9448 [(match_parallel 0 "load_multiple_operation"
9449 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9450 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9451 (set (match_operand:SI 3 "gpc_reg_operand" "")
9452 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9453 (set (match_operand:SI 4 "gpc_reg_operand" "")
9454 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9455 (set (match_operand:SI 5 "gpc_reg_operand" "")
9456 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9457 (set (match_operand:SI 6 "gpc_reg_operand" "")
9458 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9459 (set (match_operand:SI 7 "gpc_reg_operand" "")
9460 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9461 (set (match_operand:SI 8 "gpc_reg_operand" "")
9462 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9463 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9464 "*
9465{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9466 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9467 (set_attr "length" "32")])
9468
9469(define_insn "*ldmsi6"
9470 [(match_parallel 0 "load_multiple_operation"
9471 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9472 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9473 (set (match_operand:SI 3 "gpc_reg_operand" "")
9474 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9475 (set (match_operand:SI 4 "gpc_reg_operand" "")
9476 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9477 (set (match_operand:SI 5 "gpc_reg_operand" "")
9478 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9479 (set (match_operand:SI 6 "gpc_reg_operand" "")
9480 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9481 (set (match_operand:SI 7 "gpc_reg_operand" "")
9482 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9483 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9484 "*
9485{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9486 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9487 (set_attr "length" "32")])
9488
9489(define_insn "*ldmsi5"
9490 [(match_parallel 0 "load_multiple_operation"
9491 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9492 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9493 (set (match_operand:SI 3 "gpc_reg_operand" "")
9494 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9495 (set (match_operand:SI 4 "gpc_reg_operand" "")
9496 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9497 (set (match_operand:SI 5 "gpc_reg_operand" "")
9498 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9499 (set (match_operand:SI 6 "gpc_reg_operand" "")
9500 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9501 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9502 "*
9503{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9504 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9505 (set_attr "length" "32")])
9506
9507(define_insn "*ldmsi4"
9508 [(match_parallel 0 "load_multiple_operation"
9509 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9510 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9511 (set (match_operand:SI 3 "gpc_reg_operand" "")
9512 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9513 (set (match_operand:SI 4 "gpc_reg_operand" "")
9514 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9515 (set (match_operand:SI 5 "gpc_reg_operand" "")
9516 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9517 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9518 "*
9519{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9520 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9521 (set_attr "length" "32")])
9522
9523(define_insn "*ldmsi3"
9524 [(match_parallel 0 "load_multiple_operation"
9525 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9526 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9527 (set (match_operand:SI 3 "gpc_reg_operand" "")
9528 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9529 (set (match_operand:SI 4 "gpc_reg_operand" "")
9530 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9531 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9532 "*
9533{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9534 [(set_attr "type" "load_ux")
e82ee4cc 9535 (set_attr "length" "32")])
b19003d8 9536
1fd4e8c1 9537(define_expand "store_multiple"
2f622005
RK		 9538 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9539 (match_operand:SI 1 "" ""))
9540 (clobber (scratch:SI))
9541 (use (match_operand:SI 2 "" ""))])]
09a625f7 9542 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9543 "
9544{
9545 int regno;
9546 int count;
9547 rtx to;
792760b9 9548 rtx op0;
1fd4e8c1
RK		 9549 int i;
9550
9551 /* Support only storing a constant number of fixed-point registers to
9552 memory and only bother with this if more than two; the machine
9553 doesn't support more than eight. */
9554 if (GET_CODE (operands[2]) != CONST_INT
9555 || INTVAL (operands[2]) <= 2
9556 || INTVAL (operands[2]) > 8
9557 || GET_CODE (operands[0]) != MEM
9558 || GET_CODE (operands[1]) != REG
9559 || REGNO (operands[1]) >= 32)
9560 FAIL;
9561
9562 count = INTVAL (operands[2]);
9563 regno = REGNO (operands[1]);
9564
39403d82 9565 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
1fd4e8c1 9566 to = force_reg (SImode, XEXP (operands[0], 0));
792760b9 9567 op0 = replace_equiv_address (operands[0], to);
1fd4e8c1
RK		 9568
9569 XVECEXP (operands[3], 0, 0)
7ef788f0 9570 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
39403d82 9571 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
c5c76735 9572 gen_rtx_SCRATCH (SImode));
1fd4e8c1
RK		 9573
9574 for (i = 1; i < count; i++)
9575 XVECEXP (operands[3], 0, i + 1)
39403d82 9576 = gen_rtx_SET (VOIDmode,
7ef788f0 9577 adjust_address_nv (op0, SImode, i * 4),
c5c76735 9578 gen_rtx_REG (SImode, regno + i));
1fd4e8c1
RK		 9579}")
9580
e46e3130 9581(define_insn "*stmsi8"
d14a6d05 9582 [(match_parallel 0 "store_multiple_operation"
e46e3130
DJ		 9583 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9584 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9585 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9586 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9587 (match_operand:SI 4 "gpc_reg_operand" "r"))
9588 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9589 (match_operand:SI 5 "gpc_reg_operand" "r"))
9590 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9591 (match_operand:SI 6 "gpc_reg_operand" "r"))
9592 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9593 (match_operand:SI 7 "gpc_reg_operand" "r"))
9594 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9595 (match_operand:SI 8 "gpc_reg_operand" "r"))
9596 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9597 (match_operand:SI 9 "gpc_reg_operand" "r"))
9598 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9599 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9600 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9601 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9602 [(set_attr "type" "store_ux")
9603 (set_attr "cell_micro" "always")])
e46e3130
DJ		 9604
9605(define_insn "*stmsi7"
9606 [(match_parallel 0 "store_multiple_operation"
9607 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9608 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9609 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9610 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9611 (match_operand:SI 4 "gpc_reg_operand" "r"))
9612 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9613 (match_operand:SI 5 "gpc_reg_operand" "r"))
9614 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9615 (match_operand:SI 6 "gpc_reg_operand" "r"))
9616 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9617 (match_operand:SI 7 "gpc_reg_operand" "r"))
9618 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9619 (match_operand:SI 8 "gpc_reg_operand" "r"))
9620 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9621 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9622 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9623 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9624 [(set_attr "type" "store_ux")
9625 (set_attr "cell_micro" "always")])
e46e3130
DJ		 9626
9627(define_insn "*stmsi6"
9628 [(match_parallel 0 "store_multiple_operation"
9629 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9630 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9631 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9632 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9633 (match_operand:SI 4 "gpc_reg_operand" "r"))
9634 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9635 (match_operand:SI 5 "gpc_reg_operand" "r"))
9636 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9637 (match_operand:SI 6 "gpc_reg_operand" "r"))
9638 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9639 (match_operand:SI 7 "gpc_reg_operand" "r"))
9640 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9641 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9642 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9643 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9644 [(set_attr "type" "store_ux")
9645 (set_attr "cell_micro" "always")])
e46e3130
DJ		 9646
9647(define_insn "*stmsi5"
9648 [(match_parallel 0 "store_multiple_operation"
9649 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9650 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9651 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9652 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9653 (match_operand:SI 4 "gpc_reg_operand" "r"))
9654 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9655 (match_operand:SI 5 "gpc_reg_operand" "r"))
9656 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9657 (match_operand:SI 6 "gpc_reg_operand" "r"))
9658 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9659 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9660 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9661 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9662 [(set_attr "type" "store_ux")
9663 (set_attr "cell_micro" "always")])
e46e3130
DJ		 9664
9665(define_insn "*stmsi4"
9666 [(match_parallel 0 "store_multiple_operation"
9667 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9668 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9669 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9670 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9671 (match_operand:SI 4 "gpc_reg_operand" "r"))
9672 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9673 (match_operand:SI 5 "gpc_reg_operand" "r"))
9674 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9675 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9676 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
b7ff3d82 9677 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9678 [(set_attr "type" "store_ux")
9679 (set_attr "cell_micro" "always")])
7e69e155 9680
e46e3130
DJ		 9681(define_insn "*stmsi3"
9682 [(match_parallel 0 "store_multiple_operation"
9683 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9684 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9685 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9686 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9687 (match_operand:SI 4 "gpc_reg_operand" "r"))
9688 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9689 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9690 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9691 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9692 [(set_attr "type" "store_ux")
9693 (set_attr "cell_micro" "always")])
d2894ab5
DE		 9694
9695(define_insn "*stmsi8_power"
9696 [(match_parallel 0 "store_multiple_operation"
9697 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9698 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9699 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9700 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9701 (match_operand:SI 4 "gpc_reg_operand" "r"))
9702 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9703 (match_operand:SI 5 "gpc_reg_operand" "r"))
9704 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9705 (match_operand:SI 6 "gpc_reg_operand" "r"))
9706 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9707 (match_operand:SI 7 "gpc_reg_operand" "r"))
9708 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9709 (match_operand:SI 8 "gpc_reg_operand" "r"))
9710 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9711 (match_operand:SI 9 "gpc_reg_operand" "r"))
9712 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9713 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9714 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9715 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9716 [(set_attr "type" "store_ux")
9717 (set_attr "cell_micro" "always")])
d2894ab5
DE		 9718
9719(define_insn "*stmsi7_power"
9720 [(match_parallel 0 "store_multiple_operation"
9721 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9722 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9723 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9724 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9725 (match_operand:SI 4 "gpc_reg_operand" "r"))
9726 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9727 (match_operand:SI 5 "gpc_reg_operand" "r"))
9728 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9729 (match_operand:SI 6 "gpc_reg_operand" "r"))
9730 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9731 (match_operand:SI 7 "gpc_reg_operand" "r"))
9732 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9733 (match_operand:SI 8 "gpc_reg_operand" "r"))
9734 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9735 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9736 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9737 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9738 [(set_attr "type" "store_ux")
9739 (set_attr "cell_micro" "always")])
d2894ab5
DE		 9740
9741(define_insn "*stmsi6_power"
9742 [(match_parallel 0 "store_multiple_operation"
9743 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9744 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9745 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9746 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9747 (match_operand:SI 4 "gpc_reg_operand" "r"))
9748 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9749 (match_operand:SI 5 "gpc_reg_operand" "r"))
9750 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9751 (match_operand:SI 6 "gpc_reg_operand" "r"))
9752 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9753 (match_operand:SI 7 "gpc_reg_operand" "r"))
9754 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9755 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9756 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9757 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9758 [(set_attr "type" "store_ux")
9759 (set_attr "cell_micro" "always")])
d2894ab5
DE		 9760
9761(define_insn "*stmsi5_power"
9762 [(match_parallel 0 "store_multiple_operation"
9763 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9764 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9765 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9766 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9767 (match_operand:SI 4 "gpc_reg_operand" "r"))
9768 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9769 (match_operand:SI 5 "gpc_reg_operand" "r"))
9770 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9771 (match_operand:SI 6 "gpc_reg_operand" "r"))
9772 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9773 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9774 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9775 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9776 [(set_attr "type" "store_ux")
9777 (set_attr "cell_micro" "always")])
d2894ab5
DE		 9778
9779(define_insn "*stmsi4_power"
9780 [(match_parallel 0 "store_multiple_operation"
9781 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9782 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9783 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9784 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9785 (match_operand:SI 4 "gpc_reg_operand" "r"))
9786 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9787 (match_operand:SI 5 "gpc_reg_operand" "r"))
9788 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9789 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9790 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9791 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9792 [(set_attr "type" "store_ux")
9793 (set_attr "cell_micro" "always")])
d2894ab5
DE		 9794
9795(define_insn "*stmsi3_power"
9796 [(match_parallel 0 "store_multiple_operation"
9797 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9798 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9799 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9800 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9801 (match_operand:SI 4 "gpc_reg_operand" "r"))
9802 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9803 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9804 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9805 "{stsi|stswi} %2,%1,%O0"
c921bad8
AP		 9806 [(set_attr "type" "store_ux")
9807 (set_attr "cell_micro" "always")])
7e69e155 9808\f
57e84f18 9809(define_expand "setmemsi"
fba73eb1 9810 [(parallel [(set (match_operand:BLK 0 "" "")
98843c92 9811 (match_operand 2 "const_int_operand" ""))
fba73eb1 9812 (use (match_operand:SI 1 "" ""))
57e84f18 9813 (use (match_operand:SI 3 "" ""))])]
fba73eb1
DE		 9814 ""
9815 "
9816{
57e84f18 9817 /* If value to set is not zero, use the library routine. */
a05be2e0 9818 if (operands[2] != const0_rtx)
57e84f18
AS		 9819 FAIL;
9820
fba73eb1
DE		 9821 if (expand_block_clear (operands))
9822 DONE;
9823 else
9824 FAIL;
9825}")
9826
7e69e155
MM		 9827;; String/block move insn.
9828;; Argument 0 is the destination
9829;; Argument 1 is the source
9830;; Argument 2 is the length
9831;; Argument 3 is the alignment
9832
70128ad9 9833(define_expand "movmemsi"
b6c9286a
MM		 9834 [(parallel [(set (match_operand:BLK 0 "" "")
9835 (match_operand:BLK 1 "" ""))
9836 (use (match_operand:SI 2 "" ""))
9837 (use (match_operand:SI 3 "" ""))])]
7e69e155
MM		 9838 ""
9839 "
9840{
9841 if (expand_block_move (operands))
9842 DONE;
9843 else
9844 FAIL;
9845}")
9846
9847;; Move up to 32 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9848;; register allocator doesn't have a clue about allocating 8 word registers.
9849;; rD/rS = r5 is preferred, efficient form.
70128ad9 9850(define_expand "movmemsi_8reg"
b6c9286a
MM		 9851 [(parallel [(set (match_operand 0 "" "")
9852 (match_operand 1 "" ""))
9853 (use (match_operand 2 "" ""))
9854 (use (match_operand 3 "" ""))
7e69e155
MM		 9855 (clobber (reg:SI 5))
9856 (clobber (reg:SI 6))
9857 (clobber (reg:SI 7))
9858 (clobber (reg:SI 8))
9859 (clobber (reg:SI 9))
9860 (clobber (reg:SI 10))
9861 (clobber (reg:SI 11))
9862 (clobber (reg:SI 12))
3c67b673 9863 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9864 "TARGET_STRING"
9865 "")
9866
9867(define_insn ""
52d3af72
DE		 9868 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9869 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9870 (use (match_operand:SI 2 "immediate_operand" "i"))
9871 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9872 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
7e69e155
MM		 9873 (clobber (reg:SI 6))
9874 (clobber (reg:SI 7))
9875 (clobber (reg:SI 8))
9876 (clobber (reg:SI 9))
9877 (clobber (reg:SI 10))
9878 (clobber (reg:SI 11))
9879 (clobber (reg:SI 12))
3c67b673 9880 (clobber (match_scratch:SI 5 "=q"))]
7e69e155 9881 "TARGET_STRING && TARGET_POWER
f9562f27
DE		 9882 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9883 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9884 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9885 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9886 && REGNO (operands[4]) == 5"
9887 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9888 [(set_attr "type" "store_ux")
c921bad8 9889 (set_attr "cell_micro" "always")
b7ff3d82 9890 (set_attr "length" "8")])
7e69e155
MM		 9891
9892(define_insn ""
4ae234b0
GK		 9893 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9894 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9895 (use (match_operand:SI 2 "immediate_operand" "i"))
9896 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9897 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
7e69e155
MM		 9898 (clobber (reg:SI 6))
9899 (clobber (reg:SI 7))
9900 (clobber (reg:SI 8))
9901 (clobber (reg:SI 9))
9902 (clobber (reg:SI 10))
9903 (clobber (reg:SI 11))
9904 (clobber (reg:SI 12))
edd54d25 9905 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9906 "TARGET_STRING && ! TARGET_POWER
f9562f27
DE		 9907 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9908 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9909 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9910 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9911 && REGNO (operands[4]) == 5"
9912 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9913 [(set_attr "type" "store_ux")
c921bad8 9914 (set_attr "cell_micro" "always")
b7ff3d82 9915 (set_attr "length" "8")])
7e69e155
MM		 9916
9917;; Move up to 24 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9918;; register allocator doesn't have a clue about allocating 6 word registers.
9919;; rD/rS = r5 is preferred, efficient form.
70128ad9 9920(define_expand "movmemsi_6reg"
b6c9286a
MM		 9921 [(parallel [(set (match_operand 0 "" "")
9922 (match_operand 1 "" ""))
9923 (use (match_operand 2 "" ""))
9924 (use (match_operand 3 "" ""))
f9562f27
DE		 9925 (clobber (reg:SI 5))
9926 (clobber (reg:SI 6))
7e69e155
MM		 9927 (clobber (reg:SI 7))
9928 (clobber (reg:SI 8))
9929 (clobber (reg:SI 9))
9930 (clobber (reg:SI 10))
3c67b673 9931 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9932 "TARGET_STRING"
9933 "")
9934
9935(define_insn ""
52d3af72
DE		 9936 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9937 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9938 (use (match_operand:SI 2 "immediate_operand" "i"))
9939 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9940 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
f9562f27
DE		 9941 (clobber (reg:SI 6))
9942 (clobber (reg:SI 7))
7e69e155
MM		 9943 (clobber (reg:SI 8))
9944 (clobber (reg:SI 9))
9945 (clobber (reg:SI 10))
3c67b673 9946 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9947 "TARGET_STRING && TARGET_POWER
9948 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
f9562f27
DE		 9949 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9950 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9951 && REGNO (operands[4]) == 5"
3c67b673 9952 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9953 [(set_attr "type" "store_ux")
c921bad8 9954 (set_attr "cell_micro" "always")
b7ff3d82 9955 (set_attr "length" "8")])
7e69e155
MM		 9956
9957(define_insn ""
4ae234b0
GK		 9958 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9959 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9960 (use (match_operand:SI 2 "immediate_operand" "i"))
9961 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9962 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
f9562f27
DE		 9963 (clobber (reg:SI 6))
9964 (clobber (reg:SI 7))
7e69e155
MM		 9965 (clobber (reg:SI 8))
9966 (clobber (reg:SI 9))
9967 (clobber (reg:SI 10))
edd54d25 9968 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9969 "TARGET_STRING && ! TARGET_POWER
7e69e155 9970 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
f9562f27
DE		 9971 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9972 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9973 && REGNO (operands[4]) == 5"
3c67b673 9974 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9975 [(set_attr "type" "store_ux")
c921bad8 9976 (set_attr "cell_micro" "always")
b7ff3d82 9977 (set_attr "length" "8")])
7e69e155 9978
f9562f27
DE		 9979;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9980;; problems with TImode.
9981;; rD/rS = r5 is preferred, efficient form.
70128ad9 9982(define_expand "movmemsi_4reg"
b6c9286a
MM		 9983 [(parallel [(set (match_operand 0 "" "")
9984 (match_operand 1 "" ""))
9985 (use (match_operand 2 "" ""))
9986 (use (match_operand 3 "" ""))
f9562f27
DE		 9987 (clobber (reg:SI 5))
9988 (clobber (reg:SI 6))
9989 (clobber (reg:SI 7))
9990 (clobber (reg:SI 8))
3c67b673 9991 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9992 "TARGET_STRING"
9993 "")
9994
9995(define_insn ""
52d3af72
DE		 9996 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9997 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9998 (use (match_operand:SI 2 "immediate_operand" "i"))
9999 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 10000 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
f9562f27
DE		 10001 (clobber (reg:SI 6))
10002 (clobber (reg:SI 7))
10003 (clobber (reg:SI 8))
3c67b673 10004 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 10005 "TARGET_STRING && TARGET_POWER
10006 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 10007 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10008 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10009 && REGNO (operands[4]) == 5"
3c67b673 10010 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 10011 [(set_attr "type" "store_ux")
c921bad8 10012 (set_attr "cell_micro" "always")
b7ff3d82 10013 (set_attr "length" "8")])
7e69e155
MM		 10014
10015(define_insn ""
4ae234b0
GK		 10016 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10017 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 10018 (use (match_operand:SI 2 "immediate_operand" "i"))
10019 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 10020 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
f9562f27
DE		 10021 (clobber (reg:SI 6))
10022 (clobber (reg:SI 7))
10023 (clobber (reg:SI 8))
edd54d25 10024 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 10025 "TARGET_STRING && ! TARGET_POWER
7e69e155 10026 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 10027 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10028 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10029 && REGNO (operands[4]) == 5"
3c67b673 10030 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 10031 [(set_attr "type" "store_ux")
c921bad8 10032 (set_attr "cell_micro" "always")
b7ff3d82 10033 (set_attr "length" "8")])
7e69e155
MM		 10034
10035;; Move up to 8 bytes at a time.
70128ad9 10036(define_expand "movmemsi_2reg"
b6c9286a
MM		 10037 [(parallel [(set (match_operand 0 "" "")
10038 (match_operand 1 "" ""))
10039 (use (match_operand 2 "" ""))
10040 (use (match_operand 3 "" ""))
3c67b673
RK		 10041 (clobber (match_scratch:DI 4 ""))
10042 (clobber (match_scratch:SI 5 ""))])]
f9562f27 10043 "TARGET_STRING && ! TARGET_POWERPC64"
7e69e155
MM		 10044 "")
10045
10046(define_insn ""
52d3af72
DE		 10047 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10048 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 10049 (use (match_operand:SI 2 "immediate_operand" "i"))
10050 (use (match_operand:SI 3 "immediate_operand" "i"))
10051 (clobber (match_scratch:DI 4 "=&r"))
10052 (clobber (match_scratch:SI 5 "=q"))]
f9562f27 10053 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
3c67b673
RK		 10054 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10055 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 10056 [(set_attr "type" "store_ux")
c921bad8 10057 (set_attr "cell_micro" "always")
b7ff3d82 10058 (set_attr "length" "8")])
7e69e155
MM		 10059
10060(define_insn ""
52d3af72
DE		 10061 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10062 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 10063 (use (match_operand:SI 2 "immediate_operand" "i"))
10064 (use (match_operand:SI 3 "immediate_operand" "i"))
10065 (clobber (match_scratch:DI 4 "=&r"))
edd54d25 10066 (clobber (match_scratch:SI 5 "=X"))]
f9562f27 10067 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
7e69e155 10068 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
3c67b673 10069 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 10070 [(set_attr "type" "store_ux")
c921bad8 10071 (set_attr "cell_micro" "always")
b7ff3d82 10072 (set_attr "length" "8")])
7e69e155
MM		 10073
10074;; Move up to 4 bytes at a time.
70128ad9 10075(define_expand "movmemsi_1reg"
b6c9286a
MM		 10076 [(parallel [(set (match_operand 0 "" "")
10077 (match_operand 1 "" ""))
10078 (use (match_operand 2 "" ""))
10079 (use (match_operand 3 "" ""))
3c67b673
RK		 10080 (clobber (match_scratch:SI 4 ""))
10081 (clobber (match_scratch:SI 5 ""))])]
7e69e155
MM		 10082 "TARGET_STRING"
10083 "")
10084
10085(define_insn ""
52d3af72
DE		 10086 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10087 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 10088 (use (match_operand:SI 2 "immediate_operand" "i"))
10089 (use (match_operand:SI 3 "immediate_operand" "i"))
10090 (clobber (match_scratch:SI 4 "=&r"))
10091 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 10092 "TARGET_STRING && TARGET_POWER
10093 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
3c67b673 10094 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 10095 [(set_attr "type" "store_ux")
c921bad8 10096 (set_attr "cell_micro" "always")
b7ff3d82 10097 (set_attr "length" "8")])
7e69e155
MM		 10098
10099(define_insn ""
4ae234b0
GK		 10100 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10101 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 10102 (use (match_operand:SI 2 "immediate_operand" "i"))
10103 (use (match_operand:SI 3 "immediate_operand" "i"))
10104 (clobber (match_scratch:SI 4 "=&r"))
edd54d25 10105 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 10106 "TARGET_STRING && ! TARGET_POWER
7e69e155 10107 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
09a625f7 10108 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 10109 [(set_attr "type" "store_ux")
c921bad8 10110 (set_attr "cell_micro" "always")
09a625f7 10111 (set_attr "length" "8")])
1fd4e8c1 10112\f
7e69e155 10113;; Define insns that do load or store with update. Some of these we can
1fd4e8c1
RK		 10114;; get by using pre-decrement or pre-increment, but the hardware can also
10115;; do cases where the increment is not the size of the object.
10116;;
10117;; In all these cases, we use operands 0 and 1 for the register being
10118;; incremented because those are the operands that local-alloc will
10119;; tie and these are the pair most likely to be tieable (and the ones
10120;; that will benefit the most).
10121
38c1f2d7 10122(define_insn "*movdi_update1"
51b8fc2c 10123 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
ad8bd902 10124 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
768070a0 10125 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
51b8fc2c
RK		 10126 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10127 (plus:DI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10128 "TARGET_POWERPC64 && TARGET_UPDATE
10129 && (!avoiding_indexed_address_p (DImode)
10130 || !gpc_reg_operand (operands[2], DImode))"
51b8fc2c
RK		 10131 "@
10132 ldux %3,%0,%2
10133 ldu %3,%2(%0)"
b54cf83a 10134 [(set_attr "type" "load_ux,load_u")])
287f13ff 10135
2e6c9641
FJ		 10136(define_insn "movdi_<mode>_update"
10137 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10138 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
51b8fc2c 10139 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
2e6c9641
FJ		 10140 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10141 (plus:P (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10142 "TARGET_POWERPC64 && TARGET_UPDATE
10143 && (!avoiding_indexed_address_p (Pmode)
10144 || !gpc_reg_operand (operands[2], Pmode)
10145 || (REG_P (operands[0])
10146 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
51b8fc2c
RK		 10147 "@
10148 stdux %3,%0,%2
b7ff3d82 10149 stdu %3,%2(%0)"
b54cf83a 10150 [(set_attr "type" "store_ux,store_u")])
51b8fc2c 10151
d4bacef0
BE		 10152;; This pattern is only conditional on TARGET_POWERPC64, as it is
10153;; needed for stack allocation, even if the user passes -mno-update.
10154(define_insn "movdi_<mode>_update_stack"
10155 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10156 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10157 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10158 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10159 (plus:P (match_dup 1) (match_dup 2)))]
10160 "TARGET_POWERPC64"
10161 "@
10162 stdux %3,%0,%2
10163 stdu %3,%2(%0)"
10164 [(set_attr "type" "store_ux,store_u")])
10165
38c1f2d7 10166(define_insn "*movsi_update1"
cd2b37d9
RK		 10167 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10168 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10169 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10170 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10171 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10172 "TARGET_UPDATE
10173 && (!avoiding_indexed_address_p (SImode)
10174 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10175 "@
ca7f5001
RK		 10176 {lux|lwzux} %3,%0,%2
10177 {lu|lwzu} %3,%2(%0)"
b54cf83a
DE		 10178 [(set_attr "type" "load_ux,load_u")])
10179
10180(define_insn "*movsi_update2"
10181 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10182 (sign_extend:DI
10183 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10184 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10185 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10186 (plus:DI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10187 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10188 && !avoiding_indexed_address_p (DImode)"
b54cf83a
DE		 10189 "lwaux %3,%0,%2"
10190 [(set_attr "type" "load_ext_ux")])
1fd4e8c1 10191
4697a36c 10192(define_insn "movsi_update"
cd2b37d9 10193 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10194 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10195 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10196 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10197 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10198 "TARGET_UPDATE
10199 && (!avoiding_indexed_address_p (SImode)
10200 || !gpc_reg_operand (operands[2], SImode)
10201 || (REG_P (operands[0])
10202 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
1fd4e8c1 10203 "@
ca7f5001 10204 {stux|stwux} %3,%0,%2
b7ff3d82 10205 {stu|stwu} %3,%2(%0)"
b54cf83a 10206 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 10207
d4bacef0
BE		 10208;; This is an unconditional pattern; needed for stack allocation, even
10209;; if the user passes -mno-update.
10210(define_insn "movsi_update_stack"
10211 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10212 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10213 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10214 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10215 (plus:SI (match_dup 1) (match_dup 2)))]
10216 ""
10217 "@
10218 {stux|stwux} %3,%0,%2
10219 {stu|stwu} %3,%2(%0)"
10220 [(set_attr "type" "store_ux,store_u")])
10221
b54cf83a 10222(define_insn "*movhi_update1"
cd2b37d9
RK		 10223 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10224 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10225 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10226 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10227 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10228 "TARGET_UPDATE
10229 && (!avoiding_indexed_address_p (SImode)
10230 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10231 "@
5f243543
RK		 10232 lhzux %3,%0,%2
10233 lhzu %3,%2(%0)"
b54cf83a 10234 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 10235
38c1f2d7 10236(define_insn "*movhi_update2"
cd2b37d9 10237 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 10238 (zero_extend:SI
cd2b37d9 10239 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10240 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 10241 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10242 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10243 "TARGET_UPDATE
10244 && (!avoiding_indexed_address_p (SImode)
10245 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10246 "@
5f243543
RK		 10247 lhzux %3,%0,%2
10248 lhzu %3,%2(%0)"
b54cf83a 10249 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 10250
38c1f2d7 10251(define_insn "*movhi_update3"
cd2b37d9 10252 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 10253 (sign_extend:SI
cd2b37d9 10254 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10255 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 10256 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10257 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10258 "TARGET_UPDATE && rs6000_gen_cell_microcode
10259 && (!avoiding_indexed_address_p (SImode)
10260 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10261 "@
5f243543
RK		 10262 lhaux %3,%0,%2
10263 lhau %3,%2(%0)"
b54cf83a 10264 [(set_attr "type" "load_ext_ux,load_ext_u")])
1fd4e8c1 10265
38c1f2d7 10266(define_insn "*movhi_update4"
cd2b37d9 10267 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10268 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10269 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10270 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10271 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10272 "TARGET_UPDATE
10273 && (!avoiding_indexed_address_p (SImode)
10274 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10275 "@
5f243543 10276 sthux %3,%0,%2
b7ff3d82 10277 sthu %3,%2(%0)"
b54cf83a 10278 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 10279
38c1f2d7 10280(define_insn "*movqi_update1"
cd2b37d9
RK		 10281 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10282 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10283 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10284 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10285 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10286 "TARGET_UPDATE
10287 && (!avoiding_indexed_address_p (SImode)
10288 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10289 "@
5f243543
RK		 10290 lbzux %3,%0,%2
10291 lbzu %3,%2(%0)"
b54cf83a 10292 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 10293
38c1f2d7 10294(define_insn "*movqi_update2"
cd2b37d9 10295 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 10296 (zero_extend:SI
cd2b37d9 10297 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10298 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 10299 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10300 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10301 "TARGET_UPDATE
10302 && (!avoiding_indexed_address_p (SImode)
10303 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10304 "@
5f243543
RK		 10305 lbzux %3,%0,%2
10306 lbzu %3,%2(%0)"
b54cf83a 10307 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 10308
38c1f2d7 10309(define_insn "*movqi_update3"
cd2b37d9 10310 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10311 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10312 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10313 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10314 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10315 "TARGET_UPDATE
10316 && (!avoiding_indexed_address_p (SImode)
10317 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10318 "@
5f243543 10319 stbux %3,%0,%2
b7ff3d82 10320 stbu %3,%2(%0)"
b54cf83a 10321 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 10322
38c1f2d7 10323(define_insn "*movsf_update1"
cd2b37d9 10324 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
df8b713c 10325 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10326 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10327 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10328 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10329 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10330 && (!avoiding_indexed_address_p (SImode)
10331 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10332 "@
5f243543
RK		 10333 lfsux %3,%0,%2
10334 lfsu %3,%2(%0)"
b54cf83a 10335 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10336
38c1f2d7 10337(define_insn "*movsf_update2"
cd2b37d9 10338 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10339 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10340 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10341 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10342 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10343 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10344 && (!avoiding_indexed_address_p (SImode)
10345 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10346 "@
85fff2f3 10347 stfsux %3,%0,%2
b7ff3d82 10348 stfsu %3,%2(%0)"
b54cf83a 10349 [(set_attr "type" "fpstore_ux,fpstore_u")])
1fd4e8c1 10350
38c1f2d7
MM		 10351(define_insn "*movsf_update3"
10352 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10353 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10354 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10355 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10356 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10357 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10358 && (!avoiding_indexed_address_p (SImode)
10359 || !gpc_reg_operand (operands[2], SImode))"
38c1f2d7
MM		 10360 "@
10361 {lux|lwzux} %3,%0,%2
10362 {lu|lwzu} %3,%2(%0)"
b54cf83a 10363 [(set_attr "type" "load_ux,load_u")])
38c1f2d7
MM		 10364
10365(define_insn "*movsf_update4"
10366 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10367 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10368 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10369 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10370 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10371 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10372 && (!avoiding_indexed_address_p (SImode)
10373 || !gpc_reg_operand (operands[2], SImode))"
38c1f2d7
MM		 10374 "@
10375 {stux|stwux} %3,%0,%2
10376 {stu|stwu} %3,%2(%0)"
b54cf83a 10377 [(set_attr "type" "store_ux,store_u")])
38c1f2d7
MM		 10378
10379(define_insn "*movdf_update1"
799dbb0f 10380 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
cd2b37d9 10381 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10382 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10383 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10384 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10385 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10386 && (!avoiding_indexed_address_p (SImode)
10387 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10388 "@
5f243543
RK		 10389 lfdux %3,%0,%2
10390 lfdu %3,%2(%0)"
b54cf83a 10391 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10392
38c1f2d7 10393(define_insn "*movdf_update2"
cd2b37d9 10394 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10395 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
799dbb0f 10396 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
cd2b37d9 10397 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10398 (plus:SI (match_dup 1) (match_dup 2)))]
001b9eb6
PH		 10399 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10400 && (!avoiding_indexed_address_p (SImode)
10401 || !gpc_reg_operand (operands[2], SImode))"
1fd4e8c1 10402 "@
5f243543 10403 stfdux %3,%0,%2
b7ff3d82 10404 stfdu %3,%2(%0)"
b54cf83a 10405 [(set_attr "type" "fpstore_ux,fpstore_u")])
4c70a4f3
RK		 10406
10407;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10408
90f81f99 10409(define_insn "*lfq_power2"
bb8df8a6
EC		 10410 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10411 (match_operand:V2DF 1 "memory_operand" ""))]
90f81f99
AP		 10412 "TARGET_POWER2
10413 && TARGET_HARD_FLOAT && TARGET_FPRS"
bb8df8a6 10414 "lfq%U1%X1 %0,%1")
90f81f99
AP		 10415
10416(define_peephole2
10417 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4c70a4f3 10418 (match_operand:DF 1 "memory_operand" ""))
90f81f99 10419 (set (match_operand:DF 2 "gpc_reg_operand" "")
4c70a4f3
RK		 10420 (match_operand:DF 3 "memory_operand" ""))]
10421 "TARGET_POWER2
696e45ba 10422 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4c70a4f3 10423 && registers_ok_for_quad_peep (operands[0], operands[2])
90f81f99
AP		 10424 && mems_ok_for_quad_peep (operands[1], operands[3])"
10425 [(set (match_dup 0)
bb8df8a6
EC		 10426 (match_dup 1))]
10427 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10428 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
4c70a4f3 10429
90f81f99 10430(define_insn "*stfq_power2"
bb8df8a6
EC		 10431 [(set (match_operand:V2DF 0 "memory_operand" "")
10432 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
90f81f99
AP		 10433 "TARGET_POWER2
10434 && TARGET_HARD_FLOAT && TARGET_FPRS"
10435 "stfq%U0%X0 %1,%0")
10436
10437
10438(define_peephole2
4c70a4f3 10439 [(set (match_operand:DF 0 "memory_operand" "")
90f81f99 10440 (match_operand:DF 1 "gpc_reg_operand" ""))
4c70a4f3 10441 (set (match_operand:DF 2 "memory_operand" "")
90f81f99 10442 (match_operand:DF 3 "gpc_reg_operand" ""))]
4c70a4f3 10443 "TARGET_POWER2
696e45ba 10444 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
4c70a4f3 10445 && registers_ok_for_quad_peep (operands[1], operands[3])
90f81f99
AP		 10446 && mems_ok_for_quad_peep (operands[0], operands[2])"
10447 [(set (match_dup 0)
10448 (match_dup 1))]
bb8df8a6
EC		 10449 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10450 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
2f4d9502 10451
036aadfc 10452;; After inserting conditional returns we can sometimes have
2f4d9502
NS		 10453;; unnecessary register moves. Unfortunately we cannot have a
10454;; modeless peephole here, because some single SImode sets have early
10455;; clobber outputs. Although those sets expand to multi-ppc-insn
10456;; sequences, using get_attr_length here will smash the operands
10457;; array. Neither is there an early_cobbler_p predicate.
036aadfc 10458;; Disallow subregs for E500 so we don't munge frob_di_df_2.
2f4d9502
NS		 10459(define_peephole2
10460 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10461 (match_operand:DF 1 "any_operand" ""))
10462 (set (match_operand:DF 2 "gpc_reg_operand" "")
10463 (match_dup 0))]
036aadfc
AM		 10464 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10465 && peep2_reg_dead_p (2, operands[0])"
2f4d9502
NS		 10466 [(set (match_dup 2) (match_dup 1))])
10467
10468(define_peephole2
10469 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10470 (match_operand:SF 1 "any_operand" ""))
10471 (set (match_operand:SF 2 "gpc_reg_operand" "")
10472 (match_dup 0))]
10473 "peep2_reg_dead_p (2, operands[0])"
10474 [(set (match_dup 2) (match_dup 1))])
10475
1fd4e8c1 10476\f
c4501e62
JJ		 10477;; TLS support.
10478
02135bc1
SB		 10479;; Mode attributes for different ABIs.
10480(define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10481(define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10482(define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10483(define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10484
9752c4ad 10485(define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
02135bc1
SB		 10486 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10487 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10488 (match_operand 4 "" "g")))
10489 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10490 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10491 UNSPEC_TLSGD)
10492 (clobber (reg:SI LR_REGNO))]
10493 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10494 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
9752c4ad
AM		 10495 "&& TARGET_TLS_MARKERS"
10496 [(set (match_dup 0)
10497 (unspec:TLSmode [(match_dup 1)
10498 (match_dup 2)]
10499 UNSPEC_TLSGD))
10500 (parallel [(set (match_dup 0)
10501 (call (mem:TLSmode (match_dup 3))
10502 (match_dup 4)))
10503 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10504 (clobber (reg:SI LR_REGNO))])]
10505 ""
02135bc1
SB		 10506 [(set_attr "type" "two")
10507 (set_attr "length" "12")])
10508
9752c4ad 10509(define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
02135bc1
SB		 10510 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10511 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10512 (match_operand 4 "" "g")))
10513 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10514 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10515 UNSPEC_TLSGD)
10516 (clobber (reg:SI LR_REGNO))]
10517 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10518{
10519 if (flag_pic)
10520 {
10521 if (TARGET_SECURE_PLT && flag_pic == 2)
10522 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10523 else
10524 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10525 }
10526 else
10527 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10528}
9752c4ad
AM		 10529 "&& TARGET_TLS_MARKERS"
10530 [(set (match_dup 0)
10531 (unspec:TLSmode [(match_dup 1)
10532 (match_dup 2)]
10533 UNSPEC_TLSGD))
10534 (parallel [(set (match_dup 0)
10535 (call (mem:TLSmode (match_dup 3))
10536 (match_dup 4)))
10537 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10538 (clobber (reg:SI LR_REGNO))])]
10539 ""
02135bc1
SB		 10540 [(set_attr "type" "two")
10541 (set_attr "length" "8")])
c4501e62 10542
9752c4ad
AM		 10543(define_insn "*tls_gd<TLSmode:tls_abi_suffix>"
10544 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10545 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10546 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10547 UNSPEC_TLSGD))]
10548 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10549 "addi %0,%1,%2@got@tlsgd"
10550 [(set_attr "length" "4")])
10551
10552(define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
10553 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10554 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10555 (match_operand 2 "" "g")))
10556 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10557 UNSPEC_TLSGD)
10558 (clobber (reg:SI LR_REGNO))]
10559 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10560 "bl %z1(%3@tlsgd)\;%."
10561 [(set_attr "type" "branch")
10562 (set_attr "length" "8")])
10563
10564(define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
10565 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10566 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10567 (match_operand 2 "" "g")))
10568 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10569 UNSPEC_TLSGD)
10570 (clobber (reg:SI LR_REGNO))]
10571 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10572{
10573 if (flag_pic)
10574 {
10575 if (TARGET_SECURE_PLT && flag_pic == 2)
10576 return "bl %z1+32768(%3@tlsgd)@plt";
10577 return "bl %z1(%3@tlsgd)@plt";
10578 }
10579 return "bl %z1(%3@tlsgd)";
10580}
10581 [(set_attr "type" "branch")
10582 (set_attr "length" "4")])
10583
10584(define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
02135bc1
SB		 10585 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10586 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10587 (match_operand 3 "" "g")))
10588 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10589 UNSPEC_TLSLD)
10590 (clobber (reg:SI LR_REGNO))]
10591 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10592 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
9752c4ad
AM		 10593 "&& TARGET_TLS_MARKERS"
10594 [(set (match_dup 0)
10595 (unspec:TLSmode [(match_dup 1)]
10596 UNSPEC_TLSLD))
10597 (parallel [(set (match_dup 0)
10598 (call (mem:TLSmode (match_dup 2))
10599 (match_dup 3)))
10600 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10601 (clobber (reg:SI LR_REGNO))])]
10602 ""
02135bc1 10603 [(set_attr "length" "12")])
c4501e62 10604
9752c4ad 10605(define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
02135bc1
SB		 10606 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10607 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10608 (match_operand 3 "" "g")))
10609 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10610 UNSPEC_TLSLD)
10611 (clobber (reg:SI LR_REGNO))]
10612 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10613{
10614 if (flag_pic)
10615 {
10616 if (TARGET_SECURE_PLT && flag_pic == 2)
10617 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10618 else
10619 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10620 }
10621 else
10622 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10623}
9752c4ad
AM		 10624 "&& TARGET_TLS_MARKERS"
10625 [(set (match_dup 0)
10626 (unspec:TLSmode [(match_dup 1)]
10627 UNSPEC_TLSLD))
10628 (parallel [(set (match_dup 0)
10629 (call (mem:TLSmode (match_dup 2))
10630 (match_dup 3)))
10631 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10632 (clobber (reg:SI LR_REGNO))])]
10633 ""
02135bc1 10634 [(set_attr "length" "8")])
c4501e62 10635
9752c4ad
AM		 10636(define_insn "*tls_ld<TLSmode:tls_abi_suffix>"
10637 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10638 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10639 UNSPEC_TLSLD))]
10640 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10641 "addi %0,%1,%&@got@tlsld"
10642 [(set_attr "length" "4")])
10643
10644(define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10645 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10646 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10647 (match_operand 2 "" "g")))
10648 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10649 (clobber (reg:SI LR_REGNO))]
10650 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10651 "bl %z1(%&@tlsld)\;%."
10652 [(set_attr "type" "branch")
10653 (set_attr "length" "8")])
10654
10655(define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10656 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10657 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10658 (match_operand 2 "" "g")))
10659 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10660 (clobber (reg:SI LR_REGNO))]
10661 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10662{
10663 if (flag_pic)
10664 {
10665 if (TARGET_SECURE_PLT && flag_pic == 2)
10666 return "bl %z1+32768(%&@tlsld)@plt";
10667 return "bl %z1(%&@tlsld)@plt";
10668 }
10669 return "bl %z1(%&@tlsld)";
10670}
10671 [(set_attr "type" "branch")
10672 (set_attr "length" "4")])
10673
02135bc1
SB		 10674(define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10675 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10676 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10677 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10678 UNSPEC_TLSDTPREL))]
10679 "HAVE_AS_TLS"
10680 "addi %0,%1,%2@dtprel")
c4501e62 10681
02135bc1
SB		 10682(define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10683 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10684 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10685 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10686 UNSPEC_TLSDTPRELHA))]
10687 "HAVE_AS_TLS"
10688 "addis %0,%1,%2@dtprel@ha")
c4501e62 10689
02135bc1
SB		 10690(define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10691 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10692 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10693 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10694 UNSPEC_TLSDTPRELLO))]
10695 "HAVE_AS_TLS"
c4501e62
JJ		 10696 "addi %0,%1,%2@dtprel@l")
10697
02135bc1
SB		 10698(define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10699 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10700 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10701 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10702 UNSPEC_TLSGOTDTPREL))]
10703 "HAVE_AS_TLS"
10704 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
10705
10706(define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10707 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10708 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10709 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10710 UNSPEC_TLSTPREL))]
10711 "HAVE_AS_TLS"
c4501e62
JJ		 10712 "addi %0,%1,%2@tprel")
10713
02135bc1
SB		 10714(define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10715 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10716 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10717 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10718 UNSPEC_TLSTPRELHA))]
10719 "HAVE_AS_TLS"
c4501e62
JJ		 10720 "addis %0,%1,%2@tprel@ha")
10721
02135bc1
SB		 10722(define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10723 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10724 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10725 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10726 UNSPEC_TLSTPRELLO))]
10727 "HAVE_AS_TLS"
c4501e62
JJ		 10728 "addi %0,%1,%2@tprel@l")
10729
c1207243 10730;; "b" output constraint here and on tls_tls input to support linker tls
c4501e62
JJ		 10731;; optimization. The linker may edit the instructions emitted by a
10732;; tls_got_tprel/tls_tls pair to addis,addi.
02135bc1
SB		 10733(define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10734 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10735 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10736 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10737 UNSPEC_TLSGOTTPREL))]
10738 "HAVE_AS_TLS"
10739 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
10740
10741(define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10742 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10743 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10744 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10745 UNSPEC_TLSTLS))]
10746 "HAVE_AS_TLS"
c4501e62
JJ		 10747 "add %0,%1,%2@tls")
10748
c4501e62 10749\f
1fd4e8c1
RK		 10750;; Next come insns related to the calling sequence.
10751;;
10752;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
7e69e155 10753;; We move the back-chain and decrement the stack pointer.
1fd4e8c1
RK		 10754
10755(define_expand "allocate_stack"
e42ac3de 10756 [(set (match_operand 0 "gpc_reg_operand" "")
a260abc9
DE		 10757 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10758 (set (reg 1)
10759 (minus (reg 1) (match_dup 1)))]
1fd4e8c1
RK		 10760 ""
10761 "
4697a36c 10762{ rtx chain = gen_reg_rtx (Pmode);
39403d82 10763 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
4697a36c 10764 rtx neg_op0;
d4bacef0 10765 rtx insn, par, set, mem;
1fd4e8c1
RK		 10766
10767 emit_move_insn (chain, stack_bot);
4697a36c 10768
a157febd 10769 /* Check stack bounds if necessary. */
e3b5732b 10770 if (crtl->limit_stack)
a157febd
GK		 10771 {
10772 rtx available;
6ae08853 10773 available = expand_binop (Pmode, sub_optab,
a157febd
GK		 10774 stack_pointer_rtx, stack_limit_rtx,
10775 NULL_RTX, 1, OPTAB_WIDEN);
10776 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10777 }
10778
e9a25f70
JL		 10779 if (GET_CODE (operands[1]) != CONST_INT
10780 || INTVAL (operands[1]) < -32767
10781 || INTVAL (operands[1]) > 32768)
4697a36c
MM		 10782 {
10783 neg_op0 = gen_reg_rtx (Pmode);
e6ca2c17 10784 if (TARGET_32BIT)
e9a25f70 10785 emit_insn (gen_negsi2 (neg_op0, operands[1]));
e6ca2c17 10786 else
e9a25f70 10787 emit_insn (gen_negdi2 (neg_op0, operands[1]));
4697a36c
MM		 10788 }
10789 else
e9a25f70 10790 neg_op0 = GEN_INT (- INTVAL (operands[1]));
4697a36c 10791
a2a237b5
BE		 10792 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10793 : gen_movdi_di_update_stack))
16044a80
PH		 10794 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10795 chain));
d4bacef0
BE		 10796 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10797 it now and set the alias set/attributes. The above gen_*_update
10798 calls will generate a PARALLEL with the MEM set being the first
10799 operation. */
10800 par = PATTERN (insn);
10801 gcc_assert (GET_CODE (par) == PARALLEL);
10802 set = XVECEXP (par, 0, 0);
10803 gcc_assert (GET_CODE (set) == SET);
10804 mem = SET_DEST (set);
10805 gcc_assert (MEM_P (mem));
10806 MEM_NOTRAP_P (mem) = 1;
10807 set_mem_alias_set (mem, get_frame_alias_set ());
e9a25f70
JL		 10808
10809 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
1fd4e8c1
RK		 10810 DONE;
10811}")
59257ff7
RK		 10812
10813;; These patterns say how to save and restore the stack pointer. We need not
10814;; save the stack pointer at function level since we are careful to
10815;; preserve the backchain. At block level, we have to restore the backchain
10816;; when we restore the stack pointer.
10817;;
10818;; For nonlocal gotos, we must save both the stack pointer and its
10819;; backchain and restore both. Note that in the nonlocal case, the
10820;; save area is a memory location.
10821
10822(define_expand "save_stack_function"
ff381587
MM		 10823 [(match_operand 0 "any_operand" "")
10824 (match_operand 1 "any_operand" "")]
59257ff7 10825 ""
ff381587 10826 "DONE;")
59257ff7
RK		 10827
10828(define_expand "restore_stack_function"
ff381587
MM		 10829 [(match_operand 0 "any_operand" "")
10830 (match_operand 1 "any_operand" "")]
59257ff7 10831 ""
ff381587 10832 "DONE;")
59257ff7 10833
2eef28ec
AM		 10834;; Adjust stack pointer (op0) to a new value (op1).
10835;; First copy old stack backchain to new location, and ensure that the
10836;; scheduler won't reorder the sp assignment before the backchain write.
59257ff7 10837(define_expand "restore_stack_block"
2eef28ec
AM		 10838 [(set (match_dup 2) (match_dup 3))
10839 (set (match_dup 4) (match_dup 2))
10840 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10841 (set (match_operand 0 "register_operand" "")
10842 (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10843 ""
10844 "
dfdfa60f 10845{
583da60a 10846 operands[1] = force_reg (Pmode, operands[1]);
dfdfa60f 10847 operands[2] = gen_reg_rtx (Pmode);
2eef28ec
AM		 10848 operands[3] = gen_frame_mem (Pmode, operands[0]);
10849 operands[4] = gen_frame_mem (Pmode, operands[1]);
10850 operands[5] = gen_frame_mem (BLKmode, operands[0]);
dfdfa60f 10851}")
59257ff7
RK		 10852
10853(define_expand "save_stack_nonlocal"
2eef28ec
AM		 10854 [(set (match_dup 3) (match_dup 4))
10855 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10856 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10857 ""
10858 "
10859{
11b25716 10860 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10861
10862 /* Copy the backchain to the first word, sp to the second. */
2eef28ec
AM		 10863 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10864 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10865 operands[3] = gen_reg_rtx (Pmode);
10866 operands[4] = gen_frame_mem (Pmode, operands[1]);
59257ff7 10867}")
7e69e155 10868
59257ff7 10869(define_expand "restore_stack_nonlocal"
2eef28ec
AM		 10870 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10871 (set (match_dup 3) (match_dup 4))
10872 (set (match_dup 5) (match_dup 2))
10873 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10874 (set (match_operand 0 "register_operand" "") (match_dup 3))]
59257ff7
RK		 10875 ""
10876 "
10877{
11b25716 10878 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10879
10880 /* Restore the backchain from the first word, sp from the second. */
2eef28ec
AM		 10881 operands[2] = gen_reg_rtx (Pmode);
10882 operands[3] = gen_reg_rtx (Pmode);
10883 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10884 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10885 operands[5] = gen_frame_mem (Pmode, operands[3]);
10886 operands[6] = gen_frame_mem (BLKmode, operands[0]);
59257ff7 10887}")
9ebbca7d
GK		 10888\f
10889;; TOC register handling.
b6c9286a 10890
9ebbca7d 10891;; Code to initialize the TOC register...
f0f6a223 10892
9ebbca7d 10893(define_insn "load_toc_aix_si"
e72247f4 10894 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 10895 (unspec:SI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10896 (use (reg:SI 2))])]
2bfcf297 10897 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
f0f6a223
RK		 10898 "*
10899{
9ebbca7d
GK		 10900 char buf[30];
10901 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
a8a05998 10902 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10903 operands[2] = gen_rtx_REG (Pmode, 2);
10904 return \"{l|lwz} %0,%1(%2)\";
f0f6a223
RK		 10905}"
10906 [(set_attr "type" "load")])
9ebbca7d
GK		 10907
10908(define_insn "load_toc_aix_di"
e72247f4 10909 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
615158e2 10910 (unspec:DI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10911 (use (reg:DI 2))])]
2bfcf297 10912 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9ebbca7d
GK		 10913 "*
10914{
10915 char buf[30];
f585a356
DE		 10916#ifdef TARGET_RELOCATABLE
10917 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10918 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10919#else
9ebbca7d 10920 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
f585a356 10921#endif
2bfcf297
DB		 10922 if (TARGET_ELF)
10923 strcat (buf, \"@toc\");
a8a05998 10924 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10925 operands[2] = gen_rtx_REG (Pmode, 2);
10926 return \"ld %0,%1(%2)\";
10927}"
10928 [(set_attr "type" "load")])
10929
10930(define_insn "load_toc_v4_pic_si"
1de43f85 10931 [(set (reg:SI LR_REGNO)
615158e2 10932 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
f607bc57 10933 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9ebbca7d
GK		 10934 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10935 [(set_attr "type" "branch")
10936 (set_attr "length" "4")])
10937
9ebbca7d 10938(define_insn "load_toc_v4_PIC_1"
1de43f85 10939 [(set (reg:SI LR_REGNO)
e65a3857
DE		 10940 (match_operand:SI 0 "immediate_operand" "s"))
10941 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
7f970b70
AM		 10942 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10943 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
e65a3857 10944 "bcl 20,31,%0\\n%0:"
9ebbca7d
GK		 10945 [(set_attr "type" "branch")
10946 (set_attr "length" "4")])
10947
10948(define_insn "load_toc_v4_PIC_1b"
1de43f85 10949 [(set (reg:SI LR_REGNO)
e65a3857 10950 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
c4501e62 10951 UNSPEC_TOCPTR))]
20b71b17 10952 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
e65a3857 10953 "bcl 20,31,$+8\\n\\t.long %0-$"
9ebbca7d
GK		 10954 [(set_attr "type" "branch")
10955 (set_attr "length" "8")])
10956
10957(define_insn "load_toc_v4_PIC_2"
f585a356 10958 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
a2900460 10959 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9ebbca7d
GK		 10960 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10961 (match_operand:SI 3 "immediate_operand" "s")))))]
20b71b17 10962 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9ebbca7d
GK		 10963 "{l|lwz} %0,%2-%3(%1)"
10964 [(set_attr "type" "load")])
10965
7f970b70
AM		 10966(define_insn "load_toc_v4_PIC_3b"
10967 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10968 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10969 (high:SI
10970 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10971 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10972 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10973 "{cau|addis} %0,%1,%2-%3@ha")
10974
10975(define_insn "load_toc_v4_PIC_3c"
10976 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10977 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10978 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10979 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10980 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10981 "{cal|addi} %0,%1,%2-%3@l")
f51eee6a 10982
9ebbca7d
GK		 10983;; If the TOC is shared over a translation unit, as happens with all
10984;; the kinds of PIC that we support, we need to restore the TOC
10985;; pointer only when jumping over units of translation.
f51eee6a 10986;; On Darwin, we need to reload the picbase.
9ebbca7d
GK		 10987
10988(define_expand "builtin_setjmp_receiver"
10989 [(use (label_ref (match_operand 0 "" "")))]
f607bc57 10990 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
f51eee6a
GK		 10991 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10992 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9ebbca7d
GK		 10993 "
10994{
84d7dd4a 10995#if TARGET_MACHO
f51eee6a
GK		 10996 if (DEFAULT_ABI == ABI_DARWIN)
10997 {
08a6a74b 10998 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
f51eee6a
GK		 10999 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11000 rtx tmplabrtx;
11001 char tmplab[20];
11002
08a6a74b 11003 crtl->uses_pic_offset_table = 1;
f51eee6a
GK		 11004 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11005 CODE_LABEL_NUMBER (operands[0]));
485bad26 11006 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
f51eee6a 11007
316fbf19 11008 emit_insn (gen_load_macho_picbase (tmplabrtx));
1de43f85 11009 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
b8a55285 11010 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
f51eee6a
GK		 11011 }
11012 else
84d7dd4a 11013#endif
f51eee6a 11014 rs6000_emit_load_toc_table (FALSE);
9ebbca7d
GK		 11015 DONE;
11016}")
7f970b70
AM		 11017
11018;; Elf specific ways of loading addresses for non-PIC code.
11019;; The output of this could be r0, but we make a very strong
11020;; preference for a base register because it will usually
11021;; be needed there.
11022(define_insn "elf_high"
11023 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11024 (high:SI (match_operand 1 "" "")))]
11025 "TARGET_ELF && ! TARGET_64BIT"
11026 "{liu|lis} %0,%1@ha")
11027
11028(define_insn "elf_low"
11029 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11030 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11031 (match_operand 2 "" "")))]
11032 "TARGET_ELF && ! TARGET_64BIT"
11033 "@
11034 {cal|la} %0,%2@l(%1)
11035 {ai|addic} %0,%1,%K2")
9ebbca7d
GK		 11036\f
11037;; A function pointer under AIX is a pointer to a data area whose first word
11038;; contains the actual address of the function, whose second word contains a
b6c9286a
MM		 11039;; pointer to its TOC, and whose third word contains a value to place in the
11040;; static chain register (r11). Note that if we load the static chain, our
1fd4e8c1 11041;; "trampoline" need not have any executable code.
b6c9286a 11042
cccf3bdc
DE		 11043(define_expand "call_indirect_aix32"
11044 [(set (match_dup 2)
11045 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
11046 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11047 (reg:SI 2))
cccf3bdc
DE		 11048 (set (reg:SI 11)
11049 (mem:SI (plus:SI (match_dup 0)
11050 (const_int 8))))
11051 (parallel [(call (mem:SI (match_dup 2))
11052 (match_operand 1 "" ""))
a893ac80 11053 (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
cccf3bdc 11054 (use (reg:SI 11))
a893ac80 11055 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 11056 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 11057 "TARGET_32BIT"
11058 "
11059{ operands[2] = gen_reg_rtx (SImode); }")
b6c9286a 11060
cccf3bdc
DE		 11061(define_expand "call_indirect_aix64"
11062 [(set (match_dup 2)
11063 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
11064 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11065 (reg:DI 2))
cccf3bdc
DE		 11066 (set (reg:DI 11)
11067 (mem:DI (plus:DI (match_dup 0)
11068 (const_int 16))))
11069 (parallel [(call (mem:SI (match_dup 2))
11070 (match_operand 1 "" ""))
a893ac80 11071 (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
cccf3bdc 11072 (use (reg:DI 11))
a893ac80 11073 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 11074 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 11075 "TARGET_64BIT"
11076 "
11077{ operands[2] = gen_reg_rtx (DImode); }")
b6c9286a 11078
cccf3bdc
DE		 11079(define_expand "call_value_indirect_aix32"
11080 [(set (match_dup 3)
11081 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11082 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11083 (reg:SI 2))
cccf3bdc
DE		 11084 (set (reg:SI 11)
11085 (mem:SI (plus:SI (match_dup 1)
11086 (const_int 8))))
11087 (parallel [(set (match_operand 0 "" "")
11088 (call (mem:SI (match_dup 3))
11089 (match_operand 2 "" "")))
a893ac80 11090 (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
cccf3bdc 11091 (use (reg:SI 11))
a893ac80 11092 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 11093 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 11094 "TARGET_32BIT"
11095 "
11096{ operands[3] = gen_reg_rtx (SImode); }")
b6c9286a 11097
cccf3bdc
DE		 11098(define_expand "call_value_indirect_aix64"
11099 [(set (match_dup 3)
11100 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11101 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11102 (reg:DI 2))
cccf3bdc
DE		 11103 (set (reg:DI 11)
11104 (mem:DI (plus:DI (match_dup 1)
11105 (const_int 16))))
11106 (parallel [(set (match_operand 0 "" "")
11107 (call (mem:SI (match_dup 3))
11108 (match_operand 2 "" "")))
a893ac80 11109 (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
cccf3bdc 11110 (use (reg:DI 11))
a893ac80 11111 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 11112 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 11113 "TARGET_64BIT"
11114 "
11115{ operands[3] = gen_reg_rtx (DImode); }")
1fd4e8c1 11116
b6c9286a 11117;; Now the definitions for the call and call_value insns
1fd4e8c1 11118(define_expand "call"
a260abc9 11119 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
1fd4e8c1 11120 (match_operand 1 "" ""))
4697a36c 11121 (use (match_operand 2 "" ""))
1de43f85 11122 (clobber (reg:SI LR_REGNO))])]
1fd4e8c1
RK		 11123 ""
11124 "
11125{
ee890fe2 11126#if TARGET_MACHO
ab82a49f 11127 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 11128 operands[0] = machopic_indirect_call_target (operands[0]);
11129#endif
11130
37409796
NS		 11131 gcc_assert (GET_CODE (operands[0]) == MEM);
11132 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
1fd4e8c1
RK		 11133
11134 operands[0] = XEXP (operands[0], 0);
7509c759 11135
6a4cee5f 11136 if (GET_CODE (operands[0]) != SYMBOL_REF
473f51b6 11137 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
efdba735 11138 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
1fd4e8c1 11139 {
6a4cee5f
MM		 11140 if (INTVAL (operands[2]) & CALL_LONG)
11141 operands[0] = rs6000_longcall_ref (operands[0]);
11142
37409796
NS		 11143 switch (DEFAULT_ABI)
11144 {
11145 case ABI_V4:
11146 case ABI_DARWIN:
11147 operands[0] = force_reg (Pmode, operands[0]);
11148 break;
1fd4e8c1 11149
37409796 11150 case ABI_AIX:
cccf3bdc
DE		 11151 /* AIX function pointers are really pointers to a three word
11152 area. */
11153 emit_call_insn (TARGET_32BIT
11154 ? gen_call_indirect_aix32 (force_reg (SImode,
11155 operands[0]),
11156 operands[1])
11157 : gen_call_indirect_aix64 (force_reg (DImode,
11158 operands[0]),
11159 operands[1]));
11160 DONE;
37409796
NS		 11161
11162 default:
11163 gcc_unreachable ();
b6c9286a 11164 }
1fd4e8c1
RK		 11165 }
11166}")
11167
11168(define_expand "call_value"
11169 [(parallel [(set (match_operand 0 "" "")
a260abc9 11170 (call (mem:SI (match_operand 1 "address_operand" ""))
1fd4e8c1 11171 (match_operand 2 "" "")))
4697a36c 11172 (use (match_operand 3 "" ""))
1de43f85 11173 (clobber (reg:SI LR_REGNO))])]
1fd4e8c1
RK		 11174 ""
11175 "
11176{
ee890fe2 11177#if TARGET_MACHO
ab82a49f 11178 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 11179 operands[1] = machopic_indirect_call_target (operands[1]);
11180#endif
11181
37409796
NS		 11182 gcc_assert (GET_CODE (operands[1]) == MEM);
11183 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
1fd4e8c1
RK		 11184
11185 operands[1] = XEXP (operands[1], 0);
7509c759 11186
6a4cee5f 11187 if (GET_CODE (operands[1]) != SYMBOL_REF
473f51b6 11188 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
efdba735 11189 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
1fd4e8c1 11190 {
6756293c 11191 if (INTVAL (operands[3]) & CALL_LONG)
6a4cee5f
MM		 11192 operands[1] = rs6000_longcall_ref (operands[1]);
11193
37409796
NS		 11194 switch (DEFAULT_ABI)
11195 {
11196 case ABI_V4:
11197 case ABI_DARWIN:
11198 operands[1] = force_reg (Pmode, operands[1]);
11199 break;
1fd4e8c1 11200
37409796 11201 case ABI_AIX:
cccf3bdc
DE		 11202 /* AIX function pointers are really pointers to a three word
11203 area. */
11204 emit_call_insn (TARGET_32BIT
11205 ? gen_call_value_indirect_aix32 (operands[0],
11206 force_reg (SImode,
11207 operands[1]),
11208 operands[2])
11209 : gen_call_value_indirect_aix64 (operands[0],
11210 force_reg (DImode,
11211 operands[1]),
11212 operands[2]));
11213 DONE;
37409796
NS		 11214
11215 default:
11216 gcc_unreachable ();
b6c9286a 11217 }
1fd4e8c1
RK		 11218 }
11219}")
11220
04780ee7 11221;; Call to function in current module. No TOC pointer reload needed.
a0ab749a 11222;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 11223;; either the function was not prototyped, or it was prototyped as a
11224;; variable argument function. It is > 0 if FP registers were passed
11225;; and < 0 if they were not.
04780ee7 11226
a260abc9 11227(define_insn "*call_local32"
4697a36c
MM		 11228 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11229 (match_operand 1 "" "g,g"))
11230 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11231 (clobber (reg:SI LR_REGNO))]
5a19791c 11232 "(INTVAL (operands[2]) & CALL_LONG) == 0"
4697a36c
MM		 11233 "*
11234{
6a4cee5f
MM		 11235 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11236 output_asm_insn (\"crxor 6,6,6\", operands);
11237
11238 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11239 output_asm_insn (\"creqv 6,6,6\", operands);
4697a36c 11240
a226df46 11241 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
4697a36c 11242}"
b7ff3d82
DE		 11243 [(set_attr "type" "branch")
11244 (set_attr "length" "4,8")])
04780ee7 11245
a260abc9
DE		 11246(define_insn "*call_local64"
11247 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11248 (match_operand 1 "" "g,g"))
11249 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11250 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 11251 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11252 "*
11253{
11254 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11255 output_asm_insn (\"crxor 6,6,6\", operands);
11256
11257 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11258 output_asm_insn (\"creqv 6,6,6\", operands);
11259
11260 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11261}"
11262 [(set_attr "type" "branch")
11263 (set_attr "length" "4,8")])
11264
cccf3bdc 11265(define_insn "*call_value_local32"
d18dba68 11266 [(set (match_operand 0 "" "")
a260abc9
DE		 11267 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11268 (match_operand 2 "" "g,g")))
11269 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11270 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 11271 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11272 "*
11273{
11274 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11275 output_asm_insn (\"crxor 6,6,6\", operands);
11276
11277 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11278 output_asm_insn (\"creqv 6,6,6\", operands);
11279
11280 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11281}"
11282 [(set_attr "type" "branch")
11283 (set_attr "length" "4,8")])
11284
11285
cccf3bdc 11286(define_insn "*call_value_local64"
d18dba68 11287 [(set (match_operand 0 "" "")
a260abc9
DE		 11288 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11289 (match_operand 2 "" "g,g")))
11290 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11291 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 11292 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11293 "*
11294{
11295 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11296 output_asm_insn (\"crxor 6,6,6\", operands);
11297
11298 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11299 output_asm_insn (\"creqv 6,6,6\", operands);
11300
11301 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11302}"
11303 [(set_attr "type" "branch")
11304 (set_attr "length" "4,8")])
11305
04780ee7 11306;; Call to function which may be in another module. Restore the TOC
911f679c 11307;; pointer (r2) after the call unless this is System V.
a0ab749a 11308;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 11309;; either the function was not prototyped, or it was prototyped as a
11310;; variable argument function. It is > 0 if FP registers were passed
11311;; and < 0 if they were not.
04780ee7 11312
a893ac80
AP		 11313(define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
11314 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11315 (match_operand 1 "" "g,g"))
11316 (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
11317 (use (reg:SI 11))
11318 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11319 (clobber (reg:SI LR_REGNO))]
11320 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11321 "#"
11322 "&& reload_completed"
11323 [(set (reg:SI 2)
11324 (mem:SI (plus:SI (match_dup 2) (const_int 4))))
11325 (parallel [(call (mem:SI (match_dup 0))
11326 (match_dup 1))
11327 (use (reg:SI 2))
11328 (use (reg:SI 11))
11329 (set (reg:SI 2)
11330 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11331 (clobber (reg:SI LR_REGNO))])]
11332 ""
11333 [(set_attr "type" "jmpreg")
11334 (set_attr "length" "12")])
11335
cccf3bdc 11336(define_insn "*call_indirect_nonlocal_aix32"
70ae0191
DE		 11337 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11338 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 11339 (use (reg:SI 2))
11340 (use (reg:SI 11))
11341 (set (reg:SI 2)
11342 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 11343 (clobber (reg:SI LR_REGNO))]
a893ac80 11344 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
cccf3bdc
DE		 11345 "b%T0l\;{l|lwz} 2,20(1)"
11346 [(set_attr "type" "jmpreg")
11347 (set_attr "length" "8")])
11348
a260abc9 11349(define_insn "*call_nonlocal_aix32"
cc4d5fec 11350 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11351 (match_operand 1 "" "g"))
11352 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11353 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11354 "TARGET_32BIT
11355 && DEFAULT_ABI == ABI_AIX
5a19791c 11356 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 11357 "bl %z0\;%."
b7ff3d82 11358 [(set_attr "type" "branch")
cccf3bdc 11359 (set_attr "length" "8")])
a893ac80
AP		 11360
11361(define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
11362 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11363 (match_operand 1 "" "g,g"))
11364 (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
11365 (const_int 8))))
11366 (use (reg:DI 11))
11367 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11368 (clobber (reg:SI LR_REGNO))]
11369 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11370 "#"
11371 "&& reload_completed"
11372 [(set (reg:DI 2)
11373 (mem:DI (plus:DI (match_dup 2) (const_int 8))))
11374 (parallel [(call (mem:SI (match_dup 0))
11375 (match_dup 1))
11376 (use (reg:DI 2))
11377 (use (reg:DI 11))
11378 (set (reg:DI 2)
11379 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11380 (clobber (reg:SI LR_REGNO))])]
11381 ""
11382 [(set_attr "type" "jmpreg")
11383 (set_attr "length" "12")])
cccf3bdc
DE		 11384
11385(define_insn "*call_indirect_nonlocal_aix64"
70ae0191
DE		 11386 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11387 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 11388 (use (reg:DI 2))
11389 (use (reg:DI 11))
11390 (set (reg:DI 2)
11391 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 11392 (clobber (reg:SI LR_REGNO))]
a893ac80 11393 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
cccf3bdc
DE		 11394 "b%T0l\;ld 2,40(1)"
11395 [(set_attr "type" "jmpreg")
11396 (set_attr "length" "8")])
59313e4e 11397
a260abc9 11398(define_insn "*call_nonlocal_aix64"
cc4d5fec 11399 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11400 (match_operand 1 "" "g"))
11401 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11402 (clobber (reg:SI LR_REGNO))]
6ae08853 11403 "TARGET_64BIT
9ebbca7d 11404 && DEFAULT_ABI == ABI_AIX
a260abc9 11405 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 11406 "bl %z0\;%."
a260abc9 11407 [(set_attr "type" "branch")
cccf3bdc 11408 (set_attr "length" "8")])
7509c759 11409
a893ac80
AP		 11410(define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
11411 [(set (match_operand 0 "" "")
11412 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11413 (match_operand 2 "" "g,g")))
11414 (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
11415 (const_int 4))))
11416 (use (reg:SI 11))
11417 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11418 (clobber (reg:SI LR_REGNO))]
11419 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11420 "#"
11421 "&& reload_completed"
11422 [(set (reg:SI 2)
11423 (mem:SI (plus:SI (match_dup 3) (const_int 4))))
11424 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11425 (match_dup 2)))
11426 (use (reg:SI 2))
11427 (use (reg:SI 11))
11428 (set (reg:SI 2)
11429 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11430 (clobber (reg:SI LR_REGNO))])]
11431 ""
11432 [(set_attr "type" "jmpreg")
11433 (set_attr "length" "12")])
11434
cccf3bdc 11435(define_insn "*call_value_indirect_nonlocal_aix32"
d18dba68 11436 [(set (match_operand 0 "" "")
70ae0191
DE		 11437 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11438 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 11439 (use (reg:SI 2))
11440 (use (reg:SI 11))
11441 (set (reg:SI 2)
11442 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 11443 (clobber (reg:SI LR_REGNO))]
a893ac80 11444 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
cccf3bdc
DE		 11445 "b%T1l\;{l|lwz} 2,20(1)"
11446 [(set_attr "type" "jmpreg")
11447 (set_attr "length" "8")])
1fd4e8c1 11448
cccf3bdc 11449(define_insn "*call_value_nonlocal_aix32"
d18dba68 11450 [(set (match_operand 0 "" "")
cc4d5fec 11451 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11452 (match_operand 2 "" "g")))
11453 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11454 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 11455 "TARGET_32BIT
11456 && DEFAULT_ABI == ABI_AIX
a260abc9 11457 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc 11458 "bl %z1\;%."
b7ff3d82 11459 [(set_attr "type" "branch")
cccf3bdc 11460 (set_attr "length" "8")])
04780ee7 11461
a893ac80
AP		 11462(define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
11463 [(set (match_operand 0 "" "")
11464 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11465 (match_operand 2 "" "g,g")))
11466 (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
11467 (const_int 8))))
11468 (use (reg:DI 11))
11469 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11470 (clobber (reg:SI LR_REGNO))]
11471 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11472 "#"
11473 "&& reload_completed"
11474 [(set (reg:DI 2)
11475 (mem:DI (plus:DI (match_dup 3) (const_int 8))))
11476 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11477 (match_dup 2)))
11478 (use (reg:DI 2))
11479 (use (reg:DI 11))
11480 (set (reg:DI 2)
11481 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11482 (clobber (reg:SI LR_REGNO))])]
11483 ""
11484 [(set_attr "type" "jmpreg")
11485 (set_attr "length" "12")])
11486
cccf3bdc 11487(define_insn "*call_value_indirect_nonlocal_aix64"
d18dba68 11488 [(set (match_operand 0 "" "")
70ae0191
DE		 11489 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11490 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 11491 (use (reg:DI 2))
11492 (use (reg:DI 11))
11493 (set (reg:DI 2)
11494 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 11495 (clobber (reg:SI LR_REGNO))]
a893ac80 11496 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
cccf3bdc
DE		 11497 "b%T1l\;ld 2,40(1)"
11498 [(set_attr "type" "jmpreg")
11499 (set_attr "length" "8")])
11500
11501(define_insn "*call_value_nonlocal_aix64"
d18dba68 11502 [(set (match_operand 0 "" "")
cc4d5fec 11503 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 11504 (match_operand 2 "" "g")))
11505 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11506 (clobber (reg:SI LR_REGNO))]
6ae08853 11507 "TARGET_64BIT
9ebbca7d 11508 && DEFAULT_ABI == ABI_AIX
5a19791c 11509 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc
DE		 11510 "bl %z1\;%."
11511 [(set_attr "type" "branch")
11512 (set_attr "length" "8")])
11513
11514;; A function pointer under System V is just a normal pointer
11515;; operands[0] is the function pointer
11516;; operands[1] is the stack size to clean up
11517;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11518;; which indicates how to set cr1
11519
9613eaff
SH		 11520(define_insn "*call_indirect_nonlocal_sysv<mode>"
11521 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11522 (match_operand 1 "" "g,g,g,g"))
11523 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
1de43f85 11524 (clobber (reg:SI LR_REGNO))]
50d440bc 11525 "DEFAULT_ABI == ABI_V4
f607bc57 11526 || DEFAULT_ABI == ABI_DARWIN"
911f679c 11527{
cccf3bdc 11528 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11529 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f 11530
cccf3bdc 11531 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11532 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11533
a5c76ee6
ZW		 11534 return "b%T0l";
11535}
6d0a8091
DJ		 11536 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11537 (set_attr "length" "4,4,8,8")])
cccf3bdc 11538
1d3155fc 11539(define_insn_and_split "*call_nonlocal_sysv<mode>"
9613eaff 11540 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11541 (match_operand 1 "" "g,g"))
11542 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11543 (clobber (reg:SI LR_REGNO))]
efdba735
SH		 11544 "(DEFAULT_ABI == ABI_DARWIN
11545 || (DEFAULT_ABI == ABI_V4
11546 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11547{
11548 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11549 output_asm_insn ("crxor 6,6,6", operands);
11550
11551 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11552 output_asm_insn ("creqv 6,6,6", operands);
11553
c989f2f7 11554#if TARGET_MACHO
efdba735
SH		 11555 return output_call(insn, operands, 0, 2);
11556#else
7f970b70
AM		 11557 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11558 {
1d3155fc
AM		 11559 gcc_assert (!TARGET_SECURE_PLT);
11560 return "bl %z0@plt";
7f970b70
AM		 11561 }
11562 else
11563 return "bl %z0";
6ae08853 11564#endif
1d3155fc
AM		 11565}
11566 "DEFAULT_ABI == ABI_V4
11567 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11568 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11569 [(parallel [(call (mem:SI (match_dup 0))
11570 (match_dup 1))
11571 (use (match_dup 2))
11572 (use (match_dup 3))
11573 (clobber (reg:SI LR_REGNO))])]
11574{
11575 operands[3] = pic_offset_table_rtx;
11576}
11577 [(set_attr "type" "branch,branch")
11578 (set_attr "length" "4,8")])
11579
11580(define_insn "*call_nonlocal_sysv_secure<mode>"
11581 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11582 (match_operand 1 "" "g,g"))
11583 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11584 (use (match_operand:SI 3 "register_operand" "r,r"))
11585 (clobber (reg:SI LR_REGNO))]
11586 "(DEFAULT_ABI == ABI_V4
11587 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11588 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11589{
11590 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11591 output_asm_insn ("crxor 6,6,6", operands);
11592
11593 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11594 output_asm_insn ("creqv 6,6,6", operands);
11595
11596 if (flag_pic == 2)
11597 /* The magic 32768 offset here and in the other sysv call insns
11598 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11599 See sysv4.h:toc_section. */
11600 return "bl %z0+32768@plt";
11601 else
11602 return "bl %z0@plt";
a5c76ee6
ZW		 11603}
11604 [(set_attr "type" "branch,branch")
11605 (set_attr "length" "4,8")])
11606
9613eaff 11607(define_insn "*call_value_indirect_nonlocal_sysv<mode>"
d18dba68 11608 [(set (match_operand 0 "" "")
9613eaff 11609 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11610 (match_operand 2 "" "g,g,g,g")))
11611 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
1de43f85 11612 (clobber (reg:SI LR_REGNO))]
50d440bc 11613 "DEFAULT_ABI == ABI_V4
f607bc57 11614 || DEFAULT_ABI == ABI_DARWIN"
b6c9286a 11615{
6a4cee5f 11616 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11617 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f
MM		 11618
11619 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11620 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11621
a5c76ee6
ZW		 11622 return "b%T1l";
11623}
6d0a8091
DJ		 11624 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11625 (set_attr "length" "4,4,8,8")])
a5c76ee6 11626
1d3155fc 11627(define_insn_and_split "*call_value_nonlocal_sysv<mode>"
a5c76ee6 11628 [(set (match_operand 0 "" "")
9613eaff 11629 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11630 (match_operand 2 "" "g,g")))
11631 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11632 (clobber (reg:SI LR_REGNO))]
efdba735
SH		 11633 "(DEFAULT_ABI == ABI_DARWIN
11634 || (DEFAULT_ABI == ABI_V4
11635 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11636{
11637 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11638 output_asm_insn ("crxor 6,6,6", operands);
11639
11640 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11641 output_asm_insn ("creqv 6,6,6", operands);
11642
c989f2f7 11643#if TARGET_MACHO
efdba735
SH		 11644 return output_call(insn, operands, 1, 3);
11645#else
7f970b70
AM		 11646 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11647 {
1d3155fc
AM		 11648 gcc_assert (!TARGET_SECURE_PLT);
11649 return "bl %z1@plt";
7f970b70
AM		 11650 }
11651 else
11652 return "bl %z1";
6ae08853 11653#endif
1d3155fc
AM		 11654}
11655 "DEFAULT_ABI == ABI_V4
11656 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11657 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11658 [(parallel [(set (match_dup 0)
11659 (call (mem:SI (match_dup 1))
11660 (match_dup 2)))
11661 (use (match_dup 3))
11662 (use (match_dup 4))
11663 (clobber (reg:SI LR_REGNO))])]
11664{
11665 operands[4] = pic_offset_table_rtx;
11666}
11667 [(set_attr "type" "branch,branch")
11668 (set_attr "length" "4,8")])
11669
11670(define_insn "*call_value_nonlocal_sysv_secure<mode>"
11671 [(set (match_operand 0 "" "")
11672 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11673 (match_operand 2 "" "g,g")))
11674 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11675 (use (match_operand:SI 4 "register_operand" "r,r"))
11676 (clobber (reg:SI LR_REGNO))]
11677 "(DEFAULT_ABI == ABI_V4
11678 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11679 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11680{
11681 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11682 output_asm_insn ("crxor 6,6,6", operands);
11683
11684 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11685 output_asm_insn ("creqv 6,6,6", operands);
11686
11687 if (flag_pic == 2)
11688 return "bl %z1+32768@plt";
11689 else
11690 return "bl %z1@plt";
a5c76ee6
ZW		 11691}
11692 [(set_attr "type" "branch,branch")
11693 (set_attr "length" "4,8")])
e6f948e3
RK		 11694
11695;; Call subroutine returning any type.
e6f948e3
RK		 11696(define_expand "untyped_call"
11697 [(parallel [(call (match_operand 0 "" "")
11698 (const_int 0))
11699 (match_operand 1 "" "")
11700 (match_operand 2 "" "")])]
11701 ""
11702 "
11703{
11704 int i;
11705
7d70b8b2 11706 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
e6f948e3
RK		 11707
11708 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11709 {
11710 rtx set = XVECEXP (operands[2], 0, i);
11711 emit_move_insn (SET_DEST (set), SET_SRC (set));
11712 }
11713
11714 /* The optimizer does not know that the call sets the function value
11715 registers we stored in the result block. We avoid problems by
11716 claiming that all hard registers are used and clobbered at this
11717 point. */
11718 emit_insn (gen_blockage ());
11719
11720 DONE;
11721}")
11722
5e1bf043
DJ		 11723;; sibling call patterns
11724(define_expand "sibcall"
11725 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11726 (match_operand 1 "" ""))
11727 (use (match_operand 2 "" ""))
1de43f85 11728 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11729 (return)])]
11730 ""
11731 "
11732{
11733#if TARGET_MACHO
ab82a49f 11734 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11735 operands[0] = machopic_indirect_call_target (operands[0]);
11736#endif
11737
37409796
NS		 11738 gcc_assert (GET_CODE (operands[0]) == MEM);
11739 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
5e1bf043
DJ		 11740
11741 operands[0] = XEXP (operands[0], 0);
5e1bf043
DJ		 11742}")
11743
11744;; this and similar patterns must be marked as using LR, otherwise
11745;; dataflow will try to delete the store into it. This is true
11746;; even when the actual reg to jump to is in CTR, when LR was
11747;; saved and restored around the PIC-setting BCL.
11748(define_insn "*sibcall_local32"
11749 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11750 (match_operand 1 "" "g,g"))
11751 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11752 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11753 (return)]
11754 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11755 "*
11756{
11757 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11758 output_asm_insn (\"crxor 6,6,6\", operands);
11759
11760 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11761 output_asm_insn (\"creqv 6,6,6\", operands);
11762
11763 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11764}"
11765 [(set_attr "type" "branch")
11766 (set_attr "length" "4,8")])
11767
11768(define_insn "*sibcall_local64"
11769 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11770 (match_operand 1 "" "g,g"))
11771 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11772 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11773 (return)]
11774 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11775 "*
11776{
11777 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11778 output_asm_insn (\"crxor 6,6,6\", operands);
11779
11780 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11781 output_asm_insn (\"creqv 6,6,6\", operands);
11782
11783 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11784}"
11785 [(set_attr "type" "branch")
11786 (set_attr "length" "4,8")])
11787
11788(define_insn "*sibcall_value_local32"
11789 [(set (match_operand 0 "" "")
11790 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11791 (match_operand 2 "" "g,g")))
11792 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11793 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11794 (return)]
11795 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11796 "*
11797{
11798 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11799 output_asm_insn (\"crxor 6,6,6\", operands);
11800
11801 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11802 output_asm_insn (\"creqv 6,6,6\", operands);
11803
11804 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11805}"
11806 [(set_attr "type" "branch")
11807 (set_attr "length" "4,8")])
11808
11809
11810(define_insn "*sibcall_value_local64"
11811 [(set (match_operand 0 "" "")
11812 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11813 (match_operand 2 "" "g,g")))
11814 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11815 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11816 (return)]
11817 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11818 "*
11819{
11820 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11821 output_asm_insn (\"crxor 6,6,6\", operands);
11822
11823 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11824 output_asm_insn (\"creqv 6,6,6\", operands);
11825
11826 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11827}"
11828 [(set_attr "type" "branch")
11829 (set_attr "length" "4,8")])
11830
11831(define_insn "*sibcall_nonlocal_aix32"
11832 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11833 (match_operand 1 "" "g"))
11834 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11835 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11836 (return)]
11837 "TARGET_32BIT
11838 && DEFAULT_ABI == ABI_AIX
11839 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11840 "b %z0"
11841 [(set_attr "type" "branch")
11842 (set_attr "length" "4")])
11843
11844(define_insn "*sibcall_nonlocal_aix64"
11845 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11846 (match_operand 1 "" "g"))
11847 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11848 (use (reg:SI LR_REGNO))
5e1bf043 11849 (return)]
6ae08853 11850 "TARGET_64BIT
5e1bf043
DJ		 11851 && DEFAULT_ABI == ABI_AIX
11852 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11853 "b %z0"
11854 [(set_attr "type" "branch")
11855 (set_attr "length" "4")])
11856
11857(define_insn "*sibcall_value_nonlocal_aix32"
11858 [(set (match_operand 0 "" "")
11859 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11860 (match_operand 2 "" "g")))
11861 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11862 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11863 (return)]
11864 "TARGET_32BIT
11865 && DEFAULT_ABI == ABI_AIX
11866 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11867 "b %z1"
11868 [(set_attr "type" "branch")
11869 (set_attr "length" "4")])
11870
11871(define_insn "*sibcall_value_nonlocal_aix64"
11872 [(set (match_operand 0 "" "")
11873 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11874 (match_operand 2 "" "g")))
11875 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11876 (use (reg:SI LR_REGNO))
5e1bf043 11877 (return)]
6ae08853 11878 "TARGET_64BIT
5e1bf043
DJ		 11879 && DEFAULT_ABI == ABI_AIX
11880 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11881 "b %z1"
11882 [(set_attr "type" "branch")
11883 (set_attr "length" "4")])
11884
9613eaff
SH		 11885(define_insn "*sibcall_nonlocal_sysv<mode>"
11886 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11887 (match_operand 1 "" ""))
11888 (use (match_operand 2 "immediate_operand" "O,n"))
1de43f85 11889 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11890 (return)]
11891 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11892 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11893 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11894 "*
11895{
11896 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11897 output_asm_insn (\"crxor 6,6,6\", operands);
11898
11899 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11900 output_asm_insn (\"creqv 6,6,6\", operands);
11901
7f970b70
AM		 11902 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11903 {
1d3155fc
AM		 11904 gcc_assert (!TARGET_SECURE_PLT);
11905 return \"b %z0@plt\";
7f970b70
AM		 11906 }
11907 else
11908 return \"b %z0\";
5e1bf043
DJ		 11909}"
11910 [(set_attr "type" "branch,branch")
11911 (set_attr "length" "4,8")])
11912
11913(define_expand "sibcall_value"
11914 [(parallel [(set (match_operand 0 "register_operand" "")
11915 (call (mem:SI (match_operand 1 "address_operand" ""))
11916 (match_operand 2 "" "")))
11917 (use (match_operand 3 "" ""))
1de43f85 11918 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11919 (return)])]
11920 ""
11921 "
11922{
11923#if TARGET_MACHO
ab82a49f 11924 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11925 operands[1] = machopic_indirect_call_target (operands[1]);
11926#endif
11927
37409796
NS		 11928 gcc_assert (GET_CODE (operands[1]) == MEM);
11929 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
5e1bf043
DJ		 11930
11931 operands[1] = XEXP (operands[1], 0);
5e1bf043
DJ		 11932}")
11933
9613eaff 11934(define_insn "*sibcall_value_nonlocal_sysv<mode>"
5e1bf043 11935 [(set (match_operand 0 "" "")
9613eaff 11936 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11937 (match_operand 2 "" "")))
11938 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11939 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11940 (return)]
11941 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11942 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11943 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11944 "*
11945{
11946 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11947 output_asm_insn (\"crxor 6,6,6\", operands);
11948
11949 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11950 output_asm_insn (\"creqv 6,6,6\", operands);
11951
7f970b70
AM		 11952 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11953 {
1d3155fc
AM		 11954 gcc_assert (!TARGET_SECURE_PLT);
11955 return \"b %z1@plt\";
7f970b70
AM		 11956 }
11957 else
11958 return \"b %z1\";
5e1bf043
DJ		 11959}"
11960 [(set_attr "type" "branch,branch")
11961 (set_attr "length" "4,8")])
11962
11963(define_expand "sibcall_epilogue"
11964 [(use (const_int 0))]
11965 "TARGET_SCHED_PROLOG"
11966 "
11967{
11968 rs6000_emit_epilogue (TRUE);
11969 DONE;
11970}")
11971
e6f948e3
RK		 11972;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11973;; all of memory. This blocks insns from being moved across this point.
11974
11975(define_insn "blockage"
615158e2 11976 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
e6f948e3
RK		 11977 ""
11978 "")
1fd4e8c1
RK		 11979\f
11980;; Compare insns are next. Note that the RS/6000 has two types of compares,
7e69e155 11981;; signed & unsigned, and one type of branch.
1fd4e8c1
RK		 11982;;
11983;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
f90b7a5a
PB		 11984;; insns, and branches.
11985
11986(define_expand "cbranch<mode>4"
11987 [(use (match_operator 0 "rs6000_cbranch_operator"
11988 [(match_operand:GPR 1 "gpc_reg_operand" "")
11989 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11990 (use (match_operand 3 ""))]
1fd4e8c1
RK		 11991 ""
11992 "
11993{
f90b7a5a 11994 /* Take care of the possibility that operands[2] might be negative but
1fd4e8c1 11995 this might be a logical operation. That insn doesn't exist. */
f90b7a5a
PB		 11996 if (GET_CODE (operands[2]) == CONST_INT
11997 && INTVAL (operands[2]) < 0)
11998 {
11999 operands[2] = force_reg (<MODE>mode, operands[2]);
12000 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12001 GET_MODE (operands[0]),
12002 operands[1], operands[2]);
12003 }
1fd4e8c1 12004
f90b7a5a 12005 rs6000_emit_cbranch (<MODE>mode, operands);
d6f99ca4
DE		 12006 DONE;
12007}")
12008
f90b7a5a
PB		 12009(define_expand "cbranch<mode>4"
12010 [(use (match_operator 0 "rs6000_cbranch_operator"
12011 [(match_operand:FP 1 "gpc_reg_operand" "")
12012 (match_operand:FP 2 "gpc_reg_operand" "")]))
12013 (use (match_operand 3 ""))]
1fd4e8c1
RK		 12014 ""
12015 "
6ae08853 12016{
f90b7a5a 12017 rs6000_emit_cbranch (<MODE>mode, operands);
39a10a29 12018 DONE;
1fd4e8c1
RK		 12019}")
12020
f90b7a5a
PB		 12021(define_expand "cstore<mode>4"
12022 [(use (match_operator 1 "rs6000_cbranch_operator"
12023 [(match_operand:GPR 2 "gpc_reg_operand" "")
12024 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12025 (clobber (match_operand:SI 0 "register_operand"))]
1fd4e8c1
RK		 12026 ""
12027 "
5638268e 12028{
f90b7a5a
PB		 12029 /* Take care of the possibility that operands[3] might be negative but
12030 this might be a logical operation. That insn doesn't exist. */
12031 if (GET_CODE (operands[3]) == CONST_INT
12032 && INTVAL (operands[3]) < 0)
12033 {
12034 operands[3] = force_reg (<MODE>mode, operands[3]);
12035 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12036 GET_MODE (operands[1]),
12037 operands[2], operands[3]);
12038 }
1fd4e8c1 12039
f90b7a5a
PB		 12040 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12041 For SEQ, likewise, except that comparisons with zero should be done
12042 with an scc insns. However, due to the order that combine see the
12043 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12044 the cases we don't want to handle or are best handled by portable
12045 code. */
12046 if (GET_CODE (operands[1]) == NE)
1fd4e8c1 12047 FAIL;
f90b7a5a
PB		 12048 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12049 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12050 && operands[3] == const0_rtx)
5638268e 12051 FAIL;
f90b7a5a 12052 rs6000_emit_sCOND (<MODE>mode, operands);
5638268e
DE		 12053 DONE;
12054}")
1fd4e8c1 12055
f90b7a5a
PB		 12056(define_expand "cstore<mode>4"
12057 [(use (match_operator 1 "rs6000_cbranch_operator"
12058 [(match_operand:FP 2 "gpc_reg_operand" "")
12059 (match_operand:FP 3 "gpc_reg_operand" "")]))
12060 (clobber (match_operand:SI 0 "register_operand"))]
1fd4e8c1
RK		 12061 ""
12062 "
5638268e 12063{
f90b7a5a 12064 rs6000_emit_sCOND (<MODE>mode, operands);
39a10a29 12065 DONE;
1fd4e8c1
RK		 12066}")
12067
b7053a3f 12068
3aebbe5f
JJ		 12069(define_expand "stack_protect_set"
12070 [(match_operand 0 "memory_operand" "")
12071 (match_operand 1 "memory_operand" "")]
12072 ""
12073{
77008252
JJ		 12074#ifdef TARGET_THREAD_SSP_OFFSET
12075 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12076 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12077 operands[1] = gen_rtx_MEM (Pmode, addr);
12078#endif
3aebbe5f
JJ		 12079 if (TARGET_64BIT)
12080 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12081 else
12082 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12083 DONE;
12084})
12085
12086(define_insn "stack_protect_setsi"
12087 [(set (match_operand:SI 0 "memory_operand" "=m")
12088 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12089 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12090 "TARGET_32BIT"
12091 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
12092 [(set_attr "type" "three")
12093 (set_attr "length" "12")])
12094
12095(define_insn "stack_protect_setdi"
12096 [(set (match_operand:DI 0 "memory_operand" "=m")
12097 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12098 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12099 "TARGET_64BIT"
12100 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
12101 [(set_attr "type" "three")
12102 (set_attr "length" "12")])
12103
12104(define_expand "stack_protect_test"
12105 [(match_operand 0 "memory_operand" "")
12106 (match_operand 1 "memory_operand" "")
12107 (match_operand 2 "" "")]
12108 ""
12109{
f90b7a5a 12110 rtx test, op0, op1;
77008252
JJ		 12111#ifdef TARGET_THREAD_SSP_OFFSET
12112 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12113 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12114 operands[1] = gen_rtx_MEM (Pmode, addr);
12115#endif
f90b7a5a
PB		 12116 op0 = operands[0];
12117 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12118 test = gen_rtx_EQ (VOIDmode, op0, op1);
12119 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
3aebbe5f
JJ		 12120 DONE;
12121})
12122
12123(define_insn "stack_protect_testsi"
12124 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12125 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12126 (match_operand:SI 2 "memory_operand" "m,m")]
12127 UNSPEC_SP_TEST))
41f12ed0
JJ		 12128 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12129 (clobber (match_scratch:SI 3 "=&r,&r"))]
3aebbe5f
JJ		 12130 "TARGET_32BIT"
12131 "@
12132 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12133 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12134 [(set_attr "length" "16,20")])
12135
12136(define_insn "stack_protect_testdi"
12137 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12138 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
12139 (match_operand:DI 2 "memory_operand" "m,m")]
12140 UNSPEC_SP_TEST))
41f12ed0
JJ		 12141 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12142 (clobber (match_scratch:DI 3 "=&r,&r"))]
3aebbe5f
JJ		 12143 "TARGET_64BIT"
12144 "@
12145 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12146 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12147 [(set_attr "length" "16,20")])
12148
1fd4e8c1
RK		 12149\f
12150;; Here are the actual compare insns.
4ae234b0 12151(define_insn "*cmp<mode>_internal1"
1fd4e8c1 12152 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
4ae234b0
GK		 12153 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12154 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
1fd4e8c1 12155 ""
4ae234b0 12156 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
b54cf83a 12157 [(set_attr "type" "cmp")])
266eb58a 12158
f357808b 12159;; If we are comparing a register for equality with a large constant,
28d0e143
PB		 12160;; we can do this with an XOR followed by a compare. But this is profitable
12161;; only if the large constant is only used for the comparison (and in this
12162;; case we already have a register to reuse as scratch).
130869aa
PB		 12163;;
12164;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12165;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
f357808b 12166
28d0e143 12167(define_peephole2
130869aa 12168 [(set (match_operand:SI 0 "register_operand")
410c459d 12169 (match_operand:SI 1 "logical_const_operand" ""))
130869aa 12170 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
28d0e143 12171 [(match_dup 0)
410c459d 12172 (match_operand:SI 2 "logical_const_operand" "")]))
28d0e143 12173 (set (match_operand:CC 4 "cc_reg_operand" "")
130869aa 12174 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
28d0e143
PB		 12175 (match_dup 0)))
12176 (set (pc)
12177 (if_then_else (match_operator 6 "equality_operator"
12178 [(match_dup 4) (const_int 0)])
12179 (match_operand 7 "" "")
12180 (match_operand 8 "" "")))]
130869aa
PB		 12181 "peep2_reg_dead_p (3, operands[0])
12182 && peep2_reg_dead_p (4, operands[4])"
12183 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
28d0e143
PB		 12184 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12185 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12186
12187{
12188 /* Get the constant we are comparing against, and see what it looks like
12189 when sign-extended from 16 to 32 bits. Then see what constant we could
12190 XOR with SEXTC to get the sign-extended value. */
12191 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
130869aa 12192 SImode,
28d0e143
PB		 12193 operands[1], operands[2]);
12194 HOST_WIDE_INT c = INTVAL (cnst);
a65c591c 12195 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
5f59ecb7 12196 HOST_WIDE_INT xorv = c ^ sextc;
f357808b 12197
28d0e143
PB		 12198 operands[9] = GEN_INT (xorv);
12199 operands[10] = GEN_INT (sextc);
12200})
f357808b 12201
acad7ed3 12202(define_insn "*cmpsi_internal2"
1fd4e8c1 12203 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
cd2b37d9 12204 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9ebbca7d 12205 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
1fd4e8c1 12206 ""
e2c953b6 12207 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
b54cf83a 12208 [(set_attr "type" "cmp")])
1fd4e8c1 12209
acad7ed3 12210(define_insn "*cmpdi_internal2"
266eb58a
DE		 12211 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12212 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
9ebbca7d 12213 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
266eb58a 12214 ""
e2c953b6 12215 "cmpld%I2 %0,%1,%b2"
b54cf83a 12216 [(set_attr "type" "cmp")])
266eb58a 12217
1fd4e8c1
RK		 12218;; The following two insns don't exist as single insns, but if we provide
12219;; them, we can swap an add and compare, which will enable us to overlap more
12220;; of the required delay between a compare and branch. We generate code for
12221;; them by splitting.
12222
12223(define_insn ""
12224 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
cd2b37d9 12225 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12226 (match_operand:SI 2 "short_cint_operand" "i")))
cd2b37d9 12227 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12228 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12229 ""
baf97f86
RK		 12230 "#"
12231 [(set_attr "length" "8")])
7e69e155 12232
1fd4e8c1
RK		 12233(define_insn ""
12234 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
cd2b37d9 12235 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 12236 (match_operand:SI 2 "u_short_cint_operand" "i")))
cd2b37d9 12237 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12238 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12239 ""
baf97f86
RK		 12240 "#"
12241 [(set_attr "length" "8")])
7e69e155 12242
1fd4e8c1
RK		 12243(define_split
12244 [(set (match_operand:CC 3 "cc_reg_operand" "")
cd2b37d9 12245 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 12246 (match_operand:SI 2 "short_cint_operand" "")))
cd2b37d9 12247 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 12248 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12249 ""
12250 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12251 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12252
12253(define_split
12254 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
cd2b37d9 12255 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 12256 (match_operand:SI 2 "u_short_cint_operand" "")))
cd2b37d9 12257 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 12258 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12259 ""
12260 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12261 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12262
acad7ed3 12263(define_insn "*cmpsf_internal1"
1fd4e8c1 12264 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 12265 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12266 (match_operand:SF 2 "gpc_reg_operand" "f")))]
696e45ba 12267 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
1fd4e8c1
RK		 12268 "fcmpu %0,%1,%2"
12269 [(set_attr "type" "fpcompare")])
12270
acad7ed3 12271(define_insn "*cmpdf_internal1"
1fd4e8c1 12272 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
799dbb0f
ME		 12273 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
12274 (match_operand:DF 2 "gpc_reg_operand" "d")))]
696e45ba 12275 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
1fd4e8c1
RK		 12276 "fcmpu %0,%1,%2"
12277 [(set_attr "type" "fpcompare")])
d6f99ca4
DE		 12278
12279;; Only need to compare second words if first words equal
12280(define_insn "*cmptf_internal1"
12281 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
799dbb0f
ME		 12282 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12283 (match_operand:TF 2 "gpc_reg_operand" "d")))]
602ea4d3 12284 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
696e45ba 12285 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
ecb62ae7 12286 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
d6f99ca4
DE		 12287 [(set_attr "type" "fpcompare")
12288 (set_attr "length" "12")])
de17c25f
DE		 12289
12290(define_insn_and_split "*cmptf_internal2"
12291 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
799dbb0f
ME		 12292 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12293 (match_operand:TF 2 "gpc_reg_operand" "d")))
12294 (clobber (match_scratch:DF 3 "=d"))
12295 (clobber (match_scratch:DF 4 "=d"))
12296 (clobber (match_scratch:DF 5 "=d"))
12297 (clobber (match_scratch:DF 6 "=d"))
12298 (clobber (match_scratch:DF 7 "=d"))
12299 (clobber (match_scratch:DF 8 "=d"))
12300 (clobber (match_scratch:DF 9 "=d"))
12301 (clobber (match_scratch:DF 10 "=d"))]
602ea4d3 12302 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
696e45ba 12303 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
de17c25f
DE		 12304 "#"
12305 "&& reload_completed"
12306 [(set (match_dup 3) (match_dup 13))
12307 (set (match_dup 4) (match_dup 14))
12308 (set (match_dup 9) (abs:DF (match_dup 5)))
12309 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12310 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12311 (label_ref (match_dup 11))
12312 (pc)))
12313 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12314 (set (pc) (label_ref (match_dup 12)))
12315 (match_dup 11)
12316 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12317 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12318 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12319 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
12320 (match_dup 12)]
12321{
12322 REAL_VALUE_TYPE rv;
12323 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12324 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12325
12326 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12327 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12328 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12329 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12330 operands[11] = gen_label_rtx ();
12331 operands[12] = gen_label_rtx ();
12332 real_inf (&rv);
12333 operands[13] = force_const_mem (DFmode,
12334 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12335 operands[14] = force_const_mem (DFmode,
12336 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12337 DFmode));
12338 if (TARGET_TOC)
12339 {
12340 operands[13] = gen_const_mem (DFmode,
12341 create_TOC_reference (XEXP (operands[13], 0)));
12342 operands[14] = gen_const_mem (DFmode,
12343 create_TOC_reference (XEXP (operands[14], 0)));
12344 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12345 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12346 }
12347})
1fd4e8c1
RK		 12348\f
12349;; Now we have the scc insns. We can do some combinations because of the
12350;; way the machine works.
12351;;
12352;; Note that this is probably faster if we can put an insn between the
c5defebb
RK		 12353;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12354;; cases the insns below which don't use an intermediate CR field will
12355;; be used instead.
1fd4e8c1 12356(define_insn ""
cd2b37d9 12357 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12358 (match_operator:SI 1 "scc_comparison_operator"
12359 [(match_operand 2 "cc_reg_operand" "y")
12360 (const_int 0)]))]
12361 ""
2c4a9cff
DE		 12362 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12363 [(set (attr "type")
12364 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12365 (const_string "mfcrf")
12366 ]
12367 (const_string "mfcr")))
c1618c0c 12368 (set_attr "length" "8")])
1fd4e8c1 12369
423c1189 12370;; Same as above, but get the GT bit.
64022b5d 12371(define_insn "move_from_CR_gt_bit"
423c1189 12372 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
64022b5d 12373 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
c187a21f 12374 "TARGET_HARD_FLOAT && !TARGET_FPRS"
64022b5d 12375 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
423c1189 12376 [(set_attr "type" "mfcr")
c1618c0c 12377 (set_attr "length" "8")])
423c1189 12378
a3170dc6
AH		 12379;; Same as above, but get the OV/ORDERED bit.
12380(define_insn "move_from_CR_ov_bit"
12381 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 12382 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
a3170dc6 12383 "TARGET_ISEL"
b7053a3f 12384 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
b54cf83a 12385 [(set_attr "type" "mfcr")
c1618c0c 12386 (set_attr "length" "8")])
a3170dc6 12387
1fd4e8c1 12388(define_insn ""
9ebbca7d
GK		 12389 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12390 (match_operator:DI 1 "scc_comparison_operator"
12391 [(match_operand 2 "cc_reg_operand" "y")
12392 (const_int 0)]))]
12393 "TARGET_POWERPC64"
2c4a9cff
DE		 12394 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12395 [(set (attr "type")
12396 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12397 (const_string "mfcrf")
12398 ]
12399 (const_string "mfcr")))
c1618c0c 12400 (set_attr "length" "8")])
9ebbca7d
GK		 12401
12402(define_insn ""
12403 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12404 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12405 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1
RK		 12406 (const_int 0)])
12407 (const_int 0)))
9ebbca7d 12408 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 12409 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12410 "TARGET_32BIT"
9ebbca7d 12411 "@
2c4a9cff 12412 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
9ebbca7d 12413 #"
b19003d8 12414 [(set_attr "type" "delayed_compare")
c1618c0c 12415 (set_attr "length" "8,16")])
9ebbca7d
GK		 12416
12417(define_split
12418 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12419 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12420 [(match_operand 2 "cc_reg_operand" "")
12421 (const_int 0)])
12422 (const_int 0)))
12423 (set (match_operand:SI 3 "gpc_reg_operand" "")
12424 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12425 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12426 [(set (match_dup 3)
12427 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12428 (set (match_dup 0)
12429 (compare:CC (match_dup 3)
12430 (const_int 0)))]
12431 "")
1fd4e8c1
RK		 12432
12433(define_insn ""
cd2b37d9 12434 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12435 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12436 [(match_operand 2 "cc_reg_operand" "y")
12437 (const_int 0)])
12438 (match_operand:SI 3 "const_int_operand" "n")))]
12439 ""
12440 "*
12441{
12442 int is_bit = ccr_bit (operands[1], 1);
12443 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12444 int count;
12445
12446 if (is_bit >= put_bit)
12447 count = is_bit - put_bit;
12448 else
12449 count = 32 - (put_bit - is_bit);
12450
89e9f3a8
MM		 12451 operands[4] = GEN_INT (count);
12452 operands[5] = GEN_INT (put_bit);
1fd4e8c1 12453
2c4a9cff 12454 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
b19003d8 12455}"
2c4a9cff
DE		 12456 [(set (attr "type")
12457 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12458 (const_string "mfcrf")
12459 ]
12460 (const_string "mfcr")))
c1618c0c 12461 (set_attr "length" "8")])
1fd4e8c1
RK		 12462
12463(define_insn ""
9ebbca7d 12464 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12465 (compare:CC
12466 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12467 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1 12468 (const_int 0)])
9ebbca7d 12469 (match_operand:SI 3 "const_int_operand" "n,n"))
1fd4e8c1 12470 (const_int 0)))
9ebbca7d 12471 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12472 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12473 (match_dup 3)))]
ce71f754 12474 ""
1fd4e8c1
RK		 12475 "*
12476{
12477 int is_bit = ccr_bit (operands[1], 1);
12478 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12479 int count;
12480
9ebbca7d
GK		 12481 /* Force split for non-cc0 compare. */
12482 if (which_alternative == 1)
12483 return \"#\";
12484
1fd4e8c1
RK		 12485 if (is_bit >= put_bit)
12486 count = is_bit - put_bit;
12487 else
12488 count = 32 - (put_bit - is_bit);
12489
89e9f3a8
MM		 12490 operands[5] = GEN_INT (count);
12491 operands[6] = GEN_INT (put_bit);
1fd4e8c1 12492
2c4a9cff 12493 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
1fd4e8c1 12494}"
b19003d8 12495 [(set_attr "type" "delayed_compare")
c1618c0c 12496 (set_attr "length" "8,16")])
9ebbca7d
GK		 12497
12498(define_split
c921bad8 12499 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 12500 (compare:CC
12501 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12502 [(match_operand 2 "cc_reg_operand" "")
12503 (const_int 0)])
12504 (match_operand:SI 3 "const_int_operand" ""))
12505 (const_int 0)))
12506 (set (match_operand:SI 4 "gpc_reg_operand" "")
12507 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12508 (match_dup 3)))]
ce71f754 12509 "reload_completed"
9ebbca7d
GK		 12510 [(set (match_dup 4)
12511 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12512 (match_dup 3)))
12513 (set (match_dup 0)
12514 (compare:CC (match_dup 4)
12515 (const_int 0)))]
12516 "")
1fd4e8c1 12517
c5defebb
RK		 12518;; There is a 3 cycle delay between consecutive mfcr instructions
12519;; so it is useful to combine 2 scc instructions to use only one mfcr.
12520
12521(define_peephole
cd2b37d9 12522 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
c5defebb
RK		 12523 (match_operator:SI 1 "scc_comparison_operator"
12524 [(match_operand 2 "cc_reg_operand" "y")
12525 (const_int 0)]))
cd2b37d9 12526 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
c5defebb
RK		 12527 (match_operator:SI 4 "scc_comparison_operator"
12528 [(match_operand 5 "cc_reg_operand" "y")
12529 (const_int 0)]))]
309323c2 12530 "REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12531 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12532 [(set_attr "type" "mfcr")
c1618c0c 12533 (set_attr "length" "12")])
c5defebb 12534
9ebbca7d
GK		 12535(define_peephole
12536 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12537 (match_operator:DI 1 "scc_comparison_operator"
12538 [(match_operand 2 "cc_reg_operand" "y")
12539 (const_int 0)]))
12540 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12541 (match_operator:DI 4 "scc_comparison_operator"
12542 [(match_operand 5 "cc_reg_operand" "y")
12543 (const_int 0)]))]
309323c2 12544 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12545 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12546 [(set_attr "type" "mfcr")
c1618c0c 12547 (set_attr "length" "12")])
9ebbca7d 12548
1fd4e8c1
RK		 12549;; There are some scc insns that can be done directly, without a compare.
12550;; These are faster because they don't involve the communications between
12551;; the FXU and branch units. In fact, we will be replacing all of the
12552;; integer scc insns here or in the portable methods in emit_store_flag.
12553;;
12554;; Also support (neg (scc ..)) since that construct is used to replace
12555;; branches, (plus (scc ..) ..) since that construct is common and
12556;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12557;; cases where it is no more expensive than (neg (scc ..)).
12558
12559;; Have reload force a constant into a register for the simple insns that
12560;; otherwise won't accept constants. We do this because it is faster than
12561;; the cmp/mfcr sequence we would otherwise generate.
12562
e9441276
DE		 12563(define_mode_attr scc_eq_op2 [(SI "rKLI")
12564 (DI "rKJI")])
a260abc9 12565
e9441276
DE		 12566(define_insn_and_split "*eq<mode>"
12567 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12568 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
d0515b39 12569 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
27f0fe7f 12570 "!TARGET_POWER"
e9441276 12571 "#"
27f0fe7f 12572 "!TARGET_POWER"
d0515b39
DE		 12573 [(set (match_dup 0)
12574 (clz:GPR (match_dup 3)))
70ae0191 12575 (set (match_dup 0)
d0515b39 12576 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
70ae0191 12577 {
e9441276
DE		 12578 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12579 {
d0515b39
DE		 12580 /* Use output operand as intermediate. */
12581 operands[3] = operands[0];
12582
e9441276 12583 if (logical_operand (operands[2], <MODE>mode))
d0515b39 12584 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12585 gen_rtx_XOR (<MODE>mode,
12586 operands[1], operands[2])));
12587 else
d0515b39 12588 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12589 gen_rtx_PLUS (<MODE>mode, operands[1],
12590 negate_rtx (<MODE>mode,
12591 operands[2]))));
12592 }
12593 else
d0515b39 12594 operands[3] = operands[1];
9ebbca7d 12595
d0515b39 12596 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
e9441276 12597 })
a260abc9 12598
e9441276 12599(define_insn_and_split "*eq<mode>_compare"
d0515b39 12600 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
70ae0191 12601 (compare:CC
1fa5c709
DE		 12602 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12603 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
70ae0191 12604 (const_int 0)))
1fa5c709 12605 (set (match_operand:P 0 "gpc_reg_operand" "=r")
d0515b39 12606 (eq:P (match_dup 1) (match_dup 2)))]
27f0fe7f 12607 "!TARGET_POWER && optimize_size"
e9441276 12608 "#"
27f0fe7f 12609 "!TARGET_POWER && optimize_size"
d0515b39 12610 [(set (match_dup 0)
1fa5c709 12611 (clz:P (match_dup 4)))
d0515b39
DE		 12612 (parallel [(set (match_dup 3)
12613 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
70ae0191
DE		 12614 (const_int 0)))
12615 (set (match_dup 0)
d0515b39 12616 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
70ae0191 12617 {
e9441276
DE		 12618 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12619 {
d0515b39
DE		 12620 /* Use output operand as intermediate. */
12621 operands[4] = operands[0];
12622
e9441276
DE		 12623 if (logical_operand (operands[2], <MODE>mode))
12624 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12625 gen_rtx_XOR (<MODE>mode,
12626 operands[1], operands[2])));
12627 else
12628 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12629 gen_rtx_PLUS (<MODE>mode, operands[1],
12630 negate_rtx (<MODE>mode,
12631 operands[2]))));
12632 }
12633 else
12634 operands[4] = operands[1];
12635
d0515b39 12636 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
70ae0191
DE		 12637 })
12638
05f68097
DE		 12639(define_insn "*eqsi_power"
12640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12641 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12642 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12643 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12644 "TARGET_POWER"
12645 "@
12646 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12647 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12648 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12649 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12650 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12651 [(set_attr "type" "three,two,three,three,three")
12652 (set_attr "length" "12,8,12,12,12")])
12653
b19003d8
RK		 12654;; We have insns of the form shown by the first define_insn below. If
12655;; there is something inside the comparison operation, we must split it.
12656(define_split
12657 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12658 (plus:SI (match_operator 1 "comparison_operator"
12659 [(match_operand:SI 2 "" "")
12660 (match_operand:SI 3
12661 "reg_or_cint_operand" "")])
12662 (match_operand:SI 4 "gpc_reg_operand" "")))
12663 (clobber (match_operand:SI 5 "register_operand" ""))]
12664 "! gpc_reg_operand (operands[2], SImode)"
12665 [(set (match_dup 5) (match_dup 2))
12666 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12667 (match_dup 4)))])
1fd4e8c1 12668
297abd0d 12669(define_insn "*plus_eqsi"
5276df18 12670 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
cd2b37d9 12671 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
56fc483e 12672 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
5276df18 12673 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
59d6560b 12674 "TARGET_32BIT"
1fd4e8c1 12675 "@
5276df18
DE		 12676 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12677 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12678 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12679 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12680 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
943c15ed
DE		 12681 [(set_attr "type" "three,two,three,three,three")
12682 (set_attr "length" "12,8,12,12,12")])
1fd4e8c1 12683
297abd0d 12684(define_insn "*compare_plus_eqsi"
9ebbca7d 12685 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12686 (compare:CC
1fd4e8c1 12687 (plus:SI
9ebbca7d 12688 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12689 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12690 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12691 (const_int 0)))
9ebbca7d 12692 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
297abd0d 12693 "TARGET_32BIT && optimize_size"
1fd4e8c1 12694 "@
ca7f5001 12695 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
19378cf8 12696 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
ca7f5001
RK		 12697 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12698 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12699 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12700 #
12701 #
12702 #
12703 #
12704 #"
b19003d8 12705 [(set_attr "type" "compare")
9ebbca7d
GK		 12706 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12707
12708(define_split
12709 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12710 (compare:CC
12711 (plus:SI
12712 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12713 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12714 (match_operand:SI 3 "gpc_reg_operand" ""))
12715 (const_int 0)))
12716 (clobber (match_scratch:SI 4 ""))]
297abd0d 12717 "TARGET_32BIT && optimize_size && reload_completed"
9ebbca7d
GK		 12718 [(set (match_dup 4)
12719 (plus:SI (eq:SI (match_dup 1)
12720 (match_dup 2))
12721 (match_dup 3)))
12722 (set (match_dup 0)
12723 (compare:CC (match_dup 4)
12724 (const_int 0)))]
12725 "")
1fd4e8c1 12726
297abd0d 12727(define_insn "*plus_eqsi_compare"
0387639b 12728 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12729 (compare:CC
1fd4e8c1 12730 (plus:SI
9ebbca7d 12731 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12732 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12733 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12734 (const_int 0)))
0387639b
DE		 12735 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12736 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12737 "TARGET_32BIT && optimize_size"
1fd4e8c1 12738 "@
0387639b
DE		 12739 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12740 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12741 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12742 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12743 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12744 #
12745 #
12746 #
12747 #
12748 #"
12749 [(set_attr "type" "compare")
12750 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12751
12752(define_split
0387639b 12753 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12754 (compare:CC
12755 (plus:SI
12756 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12757 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12758 (match_operand:SI 3 "gpc_reg_operand" ""))
12759 (const_int 0)))
12760 (set (match_operand:SI 0 "gpc_reg_operand" "")
0387639b 12761 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12762 "TARGET_32BIT && optimize_size && reload_completed"
0387639b 12763 [(set (match_dup 0)
9ebbca7d 12764 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
0387639b 12765 (set (match_dup 4)
9ebbca7d
GK		 12766 (compare:CC (match_dup 0)
12767 (const_int 0)))]
12768 "")
12769
d0515b39
DE		 12770(define_insn "*neg_eq0<mode>"
12771 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12772 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12773 (const_int 0))))]
59d6560b 12774 ""
d0515b39
DE		 12775 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12776 [(set_attr "type" "two")
12777 (set_attr "length" "8")])
12778
12779(define_insn_and_split "*neg_eq<mode>"
12780 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12781 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12782 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
59d6560b 12783 ""
d0515b39 12784 "#"
59d6560b 12785 ""
d0515b39
DE		 12786 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12787 {
12788 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12789 {
12790 /* Use output operand as intermediate. */
12791 operands[3] = operands[0];
12792
12793 if (logical_operand (operands[2], <MODE>mode))
12794 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12795 gen_rtx_XOR (<MODE>mode,
12796 operands[1], operands[2])));
12797 else
12798 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12799 gen_rtx_PLUS (<MODE>mode, operands[1],
12800 negate_rtx (<MODE>mode,
12801 operands[2]))));
12802 }
12803 else
12804 operands[3] = operands[1];
12805 })
1fd4e8c1 12806
ea9be077
MM		 12807;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12808;; since it nabs/sr is just as fast.
ce45ef46 12809(define_insn "*ne0si"
b4e95693 12810 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
ea9be077
MM		 12811 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12812 (const_int 31)))
12813 (clobber (match_scratch:SI 2 "=&r"))]
683bdff7 12814 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
ea9be077 12815 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
943c15ed
DE		 12816 [(set_attr "type" "two")
12817 (set_attr "length" "8")])
ea9be077 12818
ce45ef46 12819(define_insn "*ne0di"
a260abc9
DE		 12820 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12821 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12822 (const_int 63)))
12823 (clobber (match_scratch:DI 2 "=&r"))]
683bdff7 12824 "TARGET_64BIT"
a260abc9 12825 "addic %2,%1,-1\;subfe %0,%2,%1"
943c15ed
DE		 12826 [(set_attr "type" "two")
12827 (set_attr "length" "8")])
a260abc9 12828
1fd4e8c1 12829;; This is what (plus (ne X (const_int 0)) Y) looks like.
297abd0d 12830(define_insn "*plus_ne0si"
cd2b37d9 12831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 12832 (plus:SI (lshiftrt:SI
cd2b37d9 12833 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1fd4e8c1 12834 (const_int 31))
cd2b37d9 12835 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1 12836 (clobber (match_scratch:SI 3 "=&r"))]
683bdff7 12837 "TARGET_32BIT"
ca7f5001 12838 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
943c15ed
DE		 12839 [(set_attr "type" "two")
12840 (set_attr "length" "8")])
1fd4e8c1 12841
297abd0d 12842(define_insn "*plus_ne0di"
a260abc9
DE		 12843 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12844 (plus:DI (lshiftrt:DI
12845 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12846 (const_int 63))
12847 (match_operand:DI 2 "gpc_reg_operand" "r")))
12848 (clobber (match_scratch:DI 3 "=&r"))]
683bdff7 12849 "TARGET_64BIT"
a260abc9 12850 "addic %3,%1,-1\;addze %0,%2"
943c15ed
DE		 12851 [(set_attr "type" "two")
12852 (set_attr "length" "8")])
a260abc9 12853
297abd0d 12854(define_insn "*compare_plus_ne0si"
9ebbca7d 12855 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12856 (compare:CC
12857 (plus:SI (lshiftrt:SI
9ebbca7d 12858 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12859 (const_int 31))
9ebbca7d 12860 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12861 (const_int 0)))
889b90a1
GK		 12862 (clobber (match_scratch:SI 3 "=&r,&r"))
12863 (clobber (match_scratch:SI 4 "=X,&r"))]
683bdff7 12864 "TARGET_32BIT"
9ebbca7d
GK		 12865 "@
12866 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12867 #"
b19003d8 12868 [(set_attr "type" "compare")
9ebbca7d
GK		 12869 (set_attr "length" "8,12")])
12870
12871(define_split
12872 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12873 (compare:CC
12874 (plus:SI (lshiftrt:SI
12875 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12876 (const_int 31))
12877 (match_operand:SI 2 "gpc_reg_operand" ""))
12878 (const_int 0)))
889b90a1
GK		 12879 (clobber (match_scratch:SI 3 ""))
12880 (clobber (match_scratch:SI 4 ""))]
683bdff7 12881 "TARGET_32BIT && reload_completed"
889b90a1 12882 [(parallel [(set (match_dup 3)
ce71f754
AM		 12883 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12884 (const_int 31))
12885 (match_dup 2)))
889b90a1 12886 (clobber (match_dup 4))])
9ebbca7d
GK		 12887 (set (match_dup 0)
12888 (compare:CC (match_dup 3)
12889 (const_int 0)))]
12890 "")
1fd4e8c1 12891
297abd0d 12892(define_insn "*compare_plus_ne0di"
9ebbca7d 12893 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12894 (compare:CC
12895 (plus:DI (lshiftrt:DI
9ebbca7d 12896 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12897 (const_int 63))
9ebbca7d 12898 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12899 (const_int 0)))
9ebbca7d 12900 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12901 "TARGET_64BIT"
9ebbca7d
GK		 12902 "@
12903 addic %3,%1,-1\;addze. %3,%2
12904 #"
a260abc9 12905 [(set_attr "type" "compare")
9ebbca7d
GK		 12906 (set_attr "length" "8,12")])
12907
12908(define_split
c921bad8 12909 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 12910 (compare:CC
12911 (plus:DI (lshiftrt:DI
12912 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12913 (const_int 63))
12914 (match_operand:DI 2 "gpc_reg_operand" ""))
12915 (const_int 0)))
12916 (clobber (match_scratch:DI 3 ""))]
683bdff7 12917 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12918 [(set (match_dup 3)
12919 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12920 (const_int 63))
12921 (match_dup 2)))
12922 (set (match_dup 0)
12923 (compare:CC (match_dup 3)
12924 (const_int 0)))]
12925 "")
a260abc9 12926
297abd0d 12927(define_insn "*plus_ne0si_compare"
9ebbca7d 12928 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12929 (compare:CC
12930 (plus:SI (lshiftrt:SI
9ebbca7d 12931 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12932 (const_int 31))
9ebbca7d 12933 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12934 (const_int 0)))
9ebbca7d 12935 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12936 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12937 (match_dup 2)))
9ebbca7d 12938 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 12939 "TARGET_32BIT"
9ebbca7d
GK		 12940 "@
12941 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12942 #"
b19003d8 12943 [(set_attr "type" "compare")
9ebbca7d
GK		 12944 (set_attr "length" "8,12")])
12945
12946(define_split
12947 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12948 (compare:CC
12949 (plus:SI (lshiftrt:SI
12950 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12951 (const_int 31))
12952 (match_operand:SI 2 "gpc_reg_operand" ""))
12953 (const_int 0)))
12954 (set (match_operand:SI 0 "gpc_reg_operand" "")
12955 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12956 (match_dup 2)))
12957 (clobber (match_scratch:SI 3 ""))]
683bdff7 12958 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12959 [(parallel [(set (match_dup 0)
12960 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12961 (match_dup 2)))
12962 (clobber (match_dup 3))])
12963 (set (match_dup 4)
12964 (compare:CC (match_dup 0)
12965 (const_int 0)))]
12966 "")
1fd4e8c1 12967
297abd0d 12968(define_insn "*plus_ne0di_compare"
9ebbca7d 12969 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12970 (compare:CC
12971 (plus:DI (lshiftrt:DI
9ebbca7d 12972 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12973 (const_int 63))
9ebbca7d 12974 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12975 (const_int 0)))
9ebbca7d 12976 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 12977 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12978 (match_dup 2)))
9ebbca7d 12979 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12980 "TARGET_64BIT"
9ebbca7d
GK		 12981 "@
12982 addic %3,%1,-1\;addze. %0,%2
12983 #"
a260abc9 12984 [(set_attr "type" "compare")
9ebbca7d
GK		 12985 (set_attr "length" "8,12")])
12986
12987(define_split
c921bad8 12988 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 12989 (compare:CC
12990 (plus:DI (lshiftrt:DI
12991 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12992 (const_int 63))
12993 (match_operand:DI 2 "gpc_reg_operand" ""))
12994 (const_int 0)))
12995 (set (match_operand:DI 0 "gpc_reg_operand" "")
12996 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12997 (match_dup 2)))
12998 (clobber (match_scratch:DI 3 ""))]
683bdff7 12999 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13000 [(parallel [(set (match_dup 0)
13001 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13002 (match_dup 2)))
13003 (clobber (match_dup 3))])
13004 (set (match_dup 4)
13005 (compare:CC (match_dup 0)
13006 (const_int 0)))]
13007 "")
a260abc9 13008
1fd4e8c1 13009(define_insn ""
cd2b37d9
RK		 13010 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13011 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 13012 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
13013 (clobber (match_scratch:SI 3 "=r,X"))]
ca7f5001 13014 "TARGET_POWER"
1fd4e8c1 13015 "@
ca7f5001 13016 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
7f340546 13017 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13018 [(set_attr "length" "12")])
1fd4e8c1
RK		 13019
13020(define_insn ""
9ebbca7d 13021 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13022 (compare:CC
9ebbca7d
GK		 13023 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13024 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
1fd4e8c1 13025 (const_int 0)))
9ebbca7d 13026 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 13027 (le:SI (match_dup 1) (match_dup 2)))
9ebbca7d 13028 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
ca7f5001 13029 "TARGET_POWER"
1fd4e8c1 13030 "@
ca7f5001 13031 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
9ebbca7d
GK		 13032 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
13033 #
13034 #"
13035 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
13036 (set_attr "length" "12,12,16,16")])
13037
13038(define_split
13039 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13040 (compare:CC
13041 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13042 (match_operand:SI 2 "reg_or_short_operand" ""))
13043 (const_int 0)))
13044 (set (match_operand:SI 0 "gpc_reg_operand" "")
13045 (le:SI (match_dup 1) (match_dup 2)))
13046 (clobber (match_scratch:SI 3 ""))]
13047 "TARGET_POWER && reload_completed"
13048 [(parallel [(set (match_dup 0)
13049 (le:SI (match_dup 1) (match_dup 2)))
13050 (clobber (match_dup 3))])
13051 (set (match_dup 4)
13052 (compare:CC (match_dup 0)
13053 (const_int 0)))]
13054 "")
1fd4e8c1
RK		 13055
13056(define_insn ""
097657c3 13057 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
cd2b37d9 13058 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 13059 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
097657c3 13060 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
ca7f5001 13061 "TARGET_POWER"
1fd4e8c1 13062 "@
097657c3
AM		 13063 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13064 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
b19003d8 13065 [(set_attr "length" "12")])
1fd4e8c1
RK		 13066
13067(define_insn ""
9ebbca7d 13068 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13069 (compare:CC
9ebbca7d
GK		 13070 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13071 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13072 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13073 (const_int 0)))
9ebbca7d 13074 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
ca7f5001 13075 "TARGET_POWER"
1fd4e8c1 13076 "@
ca7f5001 13077 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 13078 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
13079 #
13080 #"
b19003d8 13081 [(set_attr "type" "compare")
9ebbca7d
GK		 13082 (set_attr "length" "12,12,16,16")])
13083
13084(define_split
13085 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13086 (compare:CC
13087 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13088 (match_operand:SI 2 "reg_or_short_operand" ""))
13089 (match_operand:SI 3 "gpc_reg_operand" ""))
13090 (const_int 0)))
13091 (clobber (match_scratch:SI 4 ""))]
13092 "TARGET_POWER && reload_completed"
13093 [(set (match_dup 4)
13094 (plus:SI (le:SI (match_dup 1) (match_dup 2))
097657c3 13095 (match_dup 3)))
9ebbca7d
GK		 13096 (set (match_dup 0)
13097 (compare:CC (match_dup 4)
13098 (const_int 0)))]
13099 "")
1fd4e8c1
RK		 13100
13101(define_insn ""
097657c3 13102 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13103 (compare:CC
9ebbca7d
GK		 13104 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13105 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13106 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13107 (const_int 0)))
097657c3
AM		 13108 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13109 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13110 "TARGET_POWER"
1fd4e8c1 13111 "@
097657c3
AM		 13112 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13113 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 13114 #
13115 #"
b19003d8 13116 [(set_attr "type" "compare")
9ebbca7d
GK		 13117 (set_attr "length" "12,12,16,16")])
13118
13119(define_split
097657c3 13120 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13121 (compare:CC
13122 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13123 (match_operand:SI 2 "reg_or_short_operand" ""))
13124 (match_operand:SI 3 "gpc_reg_operand" ""))
13125 (const_int 0)))
13126 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13127 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13128 "TARGET_POWER && reload_completed"
097657c3 13129 [(set (match_dup 0)
9ebbca7d 13130 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13131 (set (match_dup 4)
9ebbca7d
GK		 13132 (compare:CC (match_dup 0)
13133 (const_int 0)))]
13134 "")
1fd4e8c1
RK		 13135
13136(define_insn ""
cd2b37d9
RK		 13137 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13138 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 13139 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
ca7f5001 13140 "TARGET_POWER"
1fd4e8c1 13141 "@
ca7f5001
RK		 13142 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
13143 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13144 [(set_attr "length" "12")])
1fd4e8c1 13145
a2dba291
DE		 13146(define_insn "*leu<mode>"
13147 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13148 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13149 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13150 ""
ca7f5001 13151 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 13152 [(set_attr "type" "three")
13153 (set_attr "length" "12")])
1fd4e8c1 13154
a2dba291 13155(define_insn "*leu<mode>_compare"
9ebbca7d 13156 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13157 (compare:CC
a2dba291
DE		 13158 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13159 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13160 (const_int 0)))
a2dba291
DE		 13161 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13162 (leu:P (match_dup 1) (match_dup 2)))]
13163 ""
9ebbca7d
GK		 13164 "@
13165 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13166 #"
b19003d8 13167 [(set_attr "type" "compare")
9ebbca7d
GK		 13168 (set_attr "length" "12,16")])
13169
13170(define_split
13171 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13172 (compare:CC
a2dba291
DE		 13173 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13174 (match_operand:P 2 "reg_or_short_operand" ""))
9ebbca7d 13175 (const_int 0)))
a2dba291
DE		 13176 (set (match_operand:P 0 "gpc_reg_operand" "")
13177 (leu:P (match_dup 1) (match_dup 2)))]
13178 "reload_completed"
9ebbca7d 13179 [(set (match_dup 0)
a2dba291 13180 (leu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 13181 (set (match_dup 3)
13182 (compare:CC (match_dup 0)
13183 (const_int 0)))]
13184 "")
1fd4e8c1 13185
a2dba291
DE		 13186(define_insn "*plus_leu<mode>"
13187 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13188 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13189 (match_operand:P 2 "reg_or_short_operand" "rI"))
13190 (match_operand:P 3 "gpc_reg_operand" "r")))]
13191 ""
80103f96 13192 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
943c15ed
DE		 13193 [(set_attr "type" "two")
13194 (set_attr "length" "8")])
1fd4e8c1
RK		 13195
13196(define_insn ""
9ebbca7d 13197 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13198 (compare:CC
9ebbca7d
GK		 13199 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13200 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13201 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13202 (const_int 0)))
9ebbca7d 13203 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 13204 "TARGET_32BIT"
9ebbca7d
GK		 13205 "@
13206 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
13207 #"
b19003d8 13208 [(set_attr "type" "compare")
9ebbca7d
GK		 13209 (set_attr "length" "8,12")])
13210
13211(define_split
13212 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13213 (compare:CC
13214 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13215 (match_operand:SI 2 "reg_or_short_operand" ""))
13216 (match_operand:SI 3 "gpc_reg_operand" ""))
13217 (const_int 0)))
13218 (clobber (match_scratch:SI 4 ""))]
683bdff7 13219 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13220 [(set (match_dup 4)
13221 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13222 (match_dup 3)))
13223 (set (match_dup 0)
13224 (compare:CC (match_dup 4)
13225 (const_int 0)))]
13226 "")
1fd4e8c1
RK		 13227
13228(define_insn ""
097657c3 13229 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13230 (compare:CC
9ebbca7d
GK		 13231 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13232 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13233 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13234 (const_int 0)))
097657c3
AM		 13235 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13236 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13237 "TARGET_32BIT"
9ebbca7d 13238 "@
097657c3 13239 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
9ebbca7d 13240 #"
b19003d8 13241 [(set_attr "type" "compare")
9ebbca7d
GK		 13242 (set_attr "length" "8,12")])
13243
13244(define_split
097657c3 13245 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13246 (compare:CC
13247 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13248 (match_operand:SI 2 "reg_or_short_operand" ""))
13249 (match_operand:SI 3 "gpc_reg_operand" ""))
13250 (const_int 0)))
13251 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13252 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13253 "TARGET_32BIT && reload_completed"
097657c3 13254 [(set (match_dup 0)
9ebbca7d 13255 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13256 (set (match_dup 4)
9ebbca7d
GK		 13257 (compare:CC (match_dup 0)
13258 (const_int 0)))]
13259 "")
1fd4e8c1 13260
a2dba291
DE		 13261(define_insn "*neg_leu<mode>"
13262 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13263 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13264 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13265 ""
ca7f5001 13266 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
943c15ed
DE		 13267 [(set_attr "type" "three")
13268 (set_attr "length" "12")])
1fd4e8c1 13269
a2dba291
DE		 13270(define_insn "*and_neg_leu<mode>"
13271 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13272 (and:P (neg:P
13273 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13274 (match_operand:P 2 "reg_or_short_operand" "rI")))
13275 (match_operand:P 3 "gpc_reg_operand" "r")))]
13276 ""
097657c3 13277 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 13278 [(set_attr "type" "three")
13279 (set_attr "length" "12")])
1fd4e8c1
RK		 13280
13281(define_insn ""
9ebbca7d 13282 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 13283 (compare:CC
13284 (and:SI (neg:SI
9ebbca7d
GK		 13285 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13286 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13287 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13288 (const_int 0)))
9ebbca7d 13289 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 13290 "TARGET_32BIT"
9ebbca7d
GK		 13291 "@
13292 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13293 #"
13294 [(set_attr "type" "compare")
13295 (set_attr "length" "12,16")])
13296
13297(define_split
13298 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13299 (compare:CC
13300 (and:SI (neg:SI
13301 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13302 (match_operand:SI 2 "reg_or_short_operand" "")))
13303 (match_operand:SI 3 "gpc_reg_operand" ""))
13304 (const_int 0)))
13305 (clobber (match_scratch:SI 4 ""))]
683bdff7 13306 "TARGET_32BIT && reload_completed"
9ebbca7d 13307 [(set (match_dup 4)
097657c3
AM		 13308 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13309 (match_dup 3)))
9ebbca7d
GK		 13310 (set (match_dup 0)
13311 (compare:CC (match_dup 4)
13312 (const_int 0)))]
13313 "")
1fd4e8c1
RK		 13314
13315(define_insn ""
097657c3 13316 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 13317 (compare:CC
13318 (and:SI (neg:SI
9ebbca7d
GK		 13319 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13320 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13321 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13322 (const_int 0)))
097657c3
AM		 13323 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13324 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13325 "TARGET_32BIT"
9ebbca7d 13326 "@
097657c3 13327 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d 13328 #"
b19003d8 13329 [(set_attr "type" "compare")
9ebbca7d
GK		 13330 (set_attr "length" "12,16")])
13331
13332(define_split
097657c3 13333 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13334 (compare:CC
13335 (and:SI (neg:SI
13336 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13337 (match_operand:SI 2 "reg_or_short_operand" "")))
13338 (match_operand:SI 3 "gpc_reg_operand" ""))
13339 (const_int 0)))
13340 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13341 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13342 "TARGET_32BIT && reload_completed"
097657c3
AM		 13343 [(set (match_dup 0)
13344 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13345 (match_dup 3)))
13346 (set (match_dup 4)
9ebbca7d
GK		 13347 (compare:CC (match_dup 0)
13348 (const_int 0)))]
13349 "")
1fd4e8c1
RK		 13350
13351(define_insn ""
cd2b37d9
RK		 13352 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13353 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13354 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
ca7f5001 13355 "TARGET_POWER"
7f340546 13356 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13357 [(set_attr "length" "12")])
1fd4e8c1
RK		 13358
13359(define_insn ""
9ebbca7d 13360 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13361 (compare:CC
9ebbca7d
GK		 13362 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13363 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13364 (const_int 0)))
9ebbca7d 13365 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13366 (lt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13367 "TARGET_POWER"
9ebbca7d
GK		 13368 "@
13369 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13370 #"
29ae5b89 13371 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13372 (set_attr "length" "12,16")])
13373
13374(define_split
13375 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13376 (compare:CC
13377 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13378 (match_operand:SI 2 "reg_or_short_operand" ""))
13379 (const_int 0)))
13380 (set (match_operand:SI 0 "gpc_reg_operand" "")
13381 (lt:SI (match_dup 1) (match_dup 2)))]
13382 "TARGET_POWER && reload_completed"
13383 [(set (match_dup 0)
13384 (lt:SI (match_dup 1) (match_dup 2)))
13385 (set (match_dup 3)
13386 (compare:CC (match_dup 0)
13387 (const_int 0)))]
13388 "")
1fd4e8c1
RK		 13389
13390(define_insn ""
097657c3 13391 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13392 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13393 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13394 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13395 "TARGET_POWER"
097657c3 13396 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13397 [(set_attr "length" "12")])
1fd4e8c1
RK		 13398
13399(define_insn ""
9ebbca7d 13400 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13401 (compare:CC
9ebbca7d
GK		 13402 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13403 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13404 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13405 (const_int 0)))
9ebbca7d 13406 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13407 "TARGET_POWER"
9ebbca7d
GK		 13408 "@
13409 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13410 #"
b19003d8 13411 [(set_attr "type" "compare")
9ebbca7d
GK		 13412 (set_attr "length" "12,16")])
13413
13414(define_split
13415 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13416 (compare:CC
13417 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13418 (match_operand:SI 2 "reg_or_short_operand" ""))
13419 (match_operand:SI 3 "gpc_reg_operand" ""))
13420 (const_int 0)))
13421 (clobber (match_scratch:SI 4 ""))]
13422 "TARGET_POWER && reload_completed"
13423 [(set (match_dup 4)
13424 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
097657c3 13425 (match_dup 3)))
9ebbca7d
GK		 13426 (set (match_dup 0)
13427 (compare:CC (match_dup 4)
13428 (const_int 0)))]
13429 "")
1fd4e8c1
RK		 13430
13431(define_insn ""
097657c3 13432 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13433 (compare:CC
9ebbca7d
GK		 13434 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13435 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13436 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13437 (const_int 0)))
097657c3
AM		 13438 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13439 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13440 "TARGET_POWER"
9ebbca7d 13441 "@
097657c3 13442 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13443 #"
b19003d8 13444 [(set_attr "type" "compare")
9ebbca7d
GK		 13445 (set_attr "length" "12,16")])
13446
13447(define_split
097657c3 13448 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13449 (compare:CC
13450 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13451 (match_operand:SI 2 "reg_or_short_operand" ""))
13452 (match_operand:SI 3 "gpc_reg_operand" ""))
13453 (const_int 0)))
13454 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13455 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13456 "TARGET_POWER && reload_completed"
097657c3 13457 [(set (match_dup 0)
9ebbca7d 13458 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13459 (set (match_dup 4)
9ebbca7d
GK		 13460 (compare:CC (match_dup 0)
13461 (const_int 0)))]
13462 "")
1fd4e8c1
RK		 13463
13464(define_insn ""
cd2b37d9
RK		 13465 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13466 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13467 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13468 "TARGET_POWER"
13469 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13470 [(set_attr "length" "12")])
1fd4e8c1 13471
ce45ef46
DE		 13472(define_insn_and_split "*ltu<mode>"
13473 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13474 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13475 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13476 ""
c0600ecd 13477 "#"
ce45ef46
DE		 13478 ""
13479 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13480 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 13481 "")
1fd4e8c1 13482
1e24ce83 13483(define_insn_and_split "*ltu<mode>_compare"
9ebbca7d 13484 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13485 (compare:CC
a2dba291
DE		 13486 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13487 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13488 (const_int 0)))
a2dba291
DE		 13489 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13490 (ltu:P (match_dup 1) (match_dup 2)))]
13491 ""
1e24ce83
DE		 13492 "#"
13493 ""
13494 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13495 (parallel [(set (match_dup 3)
13496 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13497 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 13498 "")
1fd4e8c1 13499
a2dba291
DE		 13500(define_insn_and_split "*plus_ltu<mode>"
13501 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13502 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13503 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
1e24ce83 13504 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
a2dba291 13505 ""
c0600ecd 13506 "#"
04fa46cf 13507 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 13508 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13509 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 13510 "")
1fd4e8c1 13511
1e24ce83 13512(define_insn_and_split "*plus_ltu<mode>_compare"
097657c3 13513 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13514 (compare:CC
1e24ce83
DE		 13515 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13516 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13517 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13518 (const_int 0)))
1e24ce83
DE		 13519 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13520 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13521 ""
13522 "#"
13523 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13524 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13525 (parallel [(set (match_dup 4)
13526 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13527 (const_int 0)))
13528 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 13529 "")
1fd4e8c1 13530
ce45ef46
DE		 13531(define_insn "*neg_ltu<mode>"
13532 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13533 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13534 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13535 ""
c0600ecd
DE		 13536 "@
13537 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13538 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
943c15ed 13539 [(set_attr "type" "two")
c0600ecd 13540 (set_attr "length" "8")])
1fd4e8c1
RK		 13541
13542(define_insn ""
cd2b37d9
RK		 13543 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13544 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 13545 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13546 (clobber (match_scratch:SI 3 "=r"))]
ca7f5001
RK		 13547 "TARGET_POWER"
13548 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
b19003d8 13549 [(set_attr "length" "12")])
1fd4e8c1 13550
9ebbca7d
GK		 13551(define_insn ""
13552 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13553 (compare:CC
9ebbca7d
GK		 13554 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13555 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13556 (const_int 0)))
9ebbca7d 13557 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13558 (ge:SI (match_dup 1) (match_dup 2)))
9ebbca7d 13559 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 13560 "TARGET_POWER"
9ebbca7d
GK		 13561 "@
13562 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13563 #"
13564 [(set_attr "type" "compare")
13565 (set_attr "length" "12,16")])
13566
13567(define_split
13568 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13569 (compare:CC
13570 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13571 (match_operand:SI 2 "reg_or_short_operand" ""))
13572 (const_int 0)))
13573 (set (match_operand:SI 0 "gpc_reg_operand" "")
13574 (ge:SI (match_dup 1) (match_dup 2)))
13575 (clobber (match_scratch:SI 3 ""))]
13576 "TARGET_POWER && reload_completed"
13577 [(parallel [(set (match_dup 0)
097657c3
AM		 13578 (ge:SI (match_dup 1) (match_dup 2)))
13579 (clobber (match_dup 3))])
9ebbca7d
GK		 13580 (set (match_dup 4)
13581 (compare:CC (match_dup 0)
13582 (const_int 0)))]
13583 "")
13584
1fd4e8c1 13585(define_insn ""
097657c3 13586 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13587 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13588 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13589 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13590 "TARGET_POWER"
097657c3 13591 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
b19003d8 13592 [(set_attr "length" "12")])
1fd4e8c1
RK		 13593
13594(define_insn ""
9ebbca7d 13595 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13596 (compare:CC
9ebbca7d
GK		 13597 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13598 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13599 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13600 (const_int 0)))
9ebbca7d 13601 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13602 "TARGET_POWER"
9ebbca7d
GK		 13603 "@
13604 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13605 #"
b19003d8 13606 [(set_attr "type" "compare")
9ebbca7d
GK		 13607 (set_attr "length" "12,16")])
13608
13609(define_split
13610 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13611 (compare:CC
13612 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13613 (match_operand:SI 2 "reg_or_short_operand" ""))
13614 (match_operand:SI 3 "gpc_reg_operand" ""))
13615 (const_int 0)))
13616 (clobber (match_scratch:SI 4 ""))]
13617 "TARGET_POWER && reload_completed"
13618 [(set (match_dup 4)
13619 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
097657c3 13620 (match_dup 3)))
9ebbca7d
GK		 13621 (set (match_dup 0)
13622 (compare:CC (match_dup 4)
13623 (const_int 0)))]
13624 "")
1fd4e8c1
RK		 13625
13626(define_insn ""
097657c3 13627 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13628 (compare:CC
9ebbca7d
GK		 13629 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13630 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13631 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13632 (const_int 0)))
097657c3
AM		 13633 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13634 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13635 "TARGET_POWER"
9ebbca7d 13636 "@
097657c3 13637 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d 13638 #"
b19003d8 13639 [(set_attr "type" "compare")
9ebbca7d
GK		 13640 (set_attr "length" "12,16")])
13641
13642(define_split
097657c3 13643 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13644 (compare:CC
13645 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13646 (match_operand:SI 2 "reg_or_short_operand" ""))
13647 (match_operand:SI 3 "gpc_reg_operand" ""))
13648 (const_int 0)))
13649 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13650 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13651 "TARGET_POWER && reload_completed"
097657c3 13652 [(set (match_dup 0)
9ebbca7d 13653 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13654 (set (match_dup 4)
9ebbca7d
GK		 13655 (compare:CC (match_dup 0)
13656 (const_int 0)))]
13657 "")
1fd4e8c1
RK		 13658
13659(define_insn ""
cd2b37d9
RK		 13660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13661 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13662 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13663 "TARGET_POWER"
13664 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 13665 [(set_attr "length" "12")])
1fd4e8c1 13666
a2dba291
DE		 13667(define_insn "*geu<mode>"
13668 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13669 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13670 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13671 ""
1fd4e8c1 13672 "@
ca7f5001
RK		 13673 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13674 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 13675 [(set_attr "type" "three")
13676 (set_attr "length" "12")])
1fd4e8c1 13677
a2dba291 13678(define_insn "*geu<mode>_compare"
9ebbca7d 13679 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13680 (compare:CC
a2dba291
DE		 13681 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13682 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13683 (const_int 0)))
a2dba291
DE		 13684 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13685 (geu:P (match_dup 1) (match_dup 2)))]
13686 ""
1fd4e8c1 13687 "@
ca7f5001 13688 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
9ebbca7d
GK		 13689 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13690 #
13691 #"
b19003d8 13692 [(set_attr "type" "compare")
9ebbca7d
GK		 13693 (set_attr "length" "12,12,16,16")])
13694
13695(define_split
c921bad8 13696 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d 13697 (compare:CC
a2dba291
DE		 13698 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13699 (match_operand:P 2 "reg_or_neg_short_operand" ""))
9ebbca7d 13700 (const_int 0)))
a2dba291
DE		 13701 (set (match_operand:P 0 "gpc_reg_operand" "")
13702 (geu:P (match_dup 1) (match_dup 2)))]
13703 "reload_completed"
9ebbca7d 13704 [(set (match_dup 0)
a2dba291 13705 (geu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 13706 (set (match_dup 3)
13707 (compare:CC (match_dup 0)
13708 (const_int 0)))]
13709 "")
f9562f27 13710
a2dba291
DE		 13711(define_insn "*plus_geu<mode>"
13712 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13713 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13714 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13715 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13716 ""
1fd4e8c1 13717 "@
80103f96
FS		 13718 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13719 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
943c15ed
DE		 13720 [(set_attr "type" "two")
13721 (set_attr "length" "8")])
1fd4e8c1
RK		 13722
13723(define_insn ""
9ebbca7d 13724 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13725 (compare:CC
9ebbca7d
GK		 13726 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13727 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13728 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13729 (const_int 0)))
9ebbca7d 13730 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13731 "TARGET_32BIT"
1fd4e8c1 13732 "@
ca7f5001 13733 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
9ebbca7d
GK		 13734 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13735 #
13736 #"
b19003d8 13737 [(set_attr "type" "compare")
9ebbca7d
GK		 13738 (set_attr "length" "8,8,12,12")])
13739
13740(define_split
13741 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13742 (compare:CC
13743 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13744 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13745 (match_operand:SI 3 "gpc_reg_operand" ""))
13746 (const_int 0)))
13747 (clobber (match_scratch:SI 4 ""))]
683bdff7 13748 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13749 [(set (match_dup 4)
13750 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13751 (match_dup 3)))
13752 (set (match_dup 0)
13753 (compare:CC (match_dup 4)
13754 (const_int 0)))]
13755 "")
1fd4e8c1
RK		 13756
13757(define_insn ""
097657c3 13758 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13759 (compare:CC
9ebbca7d
GK		 13760 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13761 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13762 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13763 (const_int 0)))
097657c3
AM		 13764 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13765 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13766 "TARGET_32BIT"
1fd4e8c1 13767 "@
097657c3
AM		 13768 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13769 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
9ebbca7d
GK		 13770 #
13771 #"
b19003d8 13772 [(set_attr "type" "compare")
9ebbca7d
GK		 13773 (set_attr "length" "8,8,12,12")])
13774
13775(define_split
097657c3 13776 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13777 (compare:CC
13778 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13779 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13780 (match_operand:SI 3 "gpc_reg_operand" ""))
13781 (const_int 0)))
13782 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13783 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13784 "TARGET_32BIT && reload_completed"
097657c3 13785 [(set (match_dup 0)
9ebbca7d 13786 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13787 (set (match_dup 4)
9ebbca7d
GK		 13788 (compare:CC (match_dup 0)
13789 (const_int 0)))]
13790 "")
1fd4e8c1 13791
a2dba291
DE		 13792(define_insn "*neg_geu<mode>"
13793 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13794 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13795 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13796 ""
1fd4e8c1 13797 "@
ca7f5001 13798 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
8106dc08 13799 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
943c15ed
DE		 13800 [(set_attr "type" "three")
13801 (set_attr "length" "12")])
1fd4e8c1 13802
a2dba291
DE		 13803(define_insn "*and_neg_geu<mode>"
13804 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13805 (and:P (neg:P
13806 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13807 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13808 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13809 ""
1fd4e8c1 13810 "@
097657c3
AM		 13811 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13812 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 13813 [(set_attr "type" "three")
13814 (set_attr "length" "12")])
1fd4e8c1
RK		 13815
13816(define_insn ""
9ebbca7d 13817 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13818 (compare:CC
13819 (and:SI (neg:SI
9ebbca7d
GK		 13820 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13821 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13822 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13823 (const_int 0)))
9ebbca7d 13824 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13825 "TARGET_32BIT"
1fd4e8c1 13826 "@
ca7f5001 13827 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
9ebbca7d
GK		 13828 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13829 #
13830 #"
b19003d8 13831 [(set_attr "type" "compare")
9ebbca7d
GK		 13832 (set_attr "length" "12,12,16,16")])
13833
13834(define_split
13835 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13836 (compare:CC
13837 (and:SI (neg:SI
13838 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13839 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13840 (match_operand:SI 3 "gpc_reg_operand" ""))
13841 (const_int 0)))
13842 (clobber (match_scratch:SI 4 ""))]
683bdff7 13843 "TARGET_32BIT && reload_completed"
9ebbca7d 13844 [(set (match_dup 4)
097657c3
AM		 13845 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13846 (match_dup 3)))
9ebbca7d
GK		 13847 (set (match_dup 0)
13848 (compare:CC (match_dup 4)
13849 (const_int 0)))]
13850 "")
1fd4e8c1
RK		 13851
13852(define_insn ""
097657c3 13853 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13854 (compare:CC
13855 (and:SI (neg:SI
9ebbca7d
GK		 13856 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13857 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13858 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13859 (const_int 0)))
097657c3
AM		 13860 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13861 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13862 "TARGET_32BIT"
1fd4e8c1 13863 "@
097657c3
AM		 13864 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13865 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d
GK		 13866 #
13867 #"
b19003d8 13868 [(set_attr "type" "compare")
9ebbca7d
GK		 13869 (set_attr "length" "12,12,16,16")])
13870
13871(define_split
097657c3 13872 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13873 (compare:CC
13874 (and:SI (neg:SI
13875 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13876 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13877 (match_operand:SI 3 "gpc_reg_operand" ""))
13878 (const_int 0)))
13879 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13880 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13881 "TARGET_32BIT && reload_completed"
097657c3 13882 [(set (match_dup 0)
9ebbca7d 13883 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
097657c3 13884 (set (match_dup 4)
9ebbca7d
GK		 13885 (compare:CC (match_dup 0)
13886 (const_int 0)))]
13887 "")
1fd4e8c1 13888
1fd4e8c1 13889(define_insn ""
cd2b37d9
RK		 13890 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13891 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13892 (match_operand:SI 2 "reg_or_short_operand" "r")))]
ca7f5001
RK		 13893 "TARGET_POWER"
13894 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13895 [(set_attr "length" "12")])
1fd4e8c1
RK		 13896
13897(define_insn ""
9ebbca7d 13898 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13899 (compare:CC
9ebbca7d
GK		 13900 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13901 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
1fd4e8c1 13902 (const_int 0)))
9ebbca7d 13903 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13904 (gt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13905 "TARGET_POWER"
9ebbca7d
GK		 13906 "@
13907 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13908 #"
29ae5b89 13909 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13910 (set_attr "length" "12,16")])
13911
13912(define_split
13913 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13914 (compare:CC
13915 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13916 (match_operand:SI 2 "reg_or_short_operand" ""))
13917 (const_int 0)))
13918 (set (match_operand:SI 0 "gpc_reg_operand" "")
13919 (gt:SI (match_dup 1) (match_dup 2)))]
13920 "TARGET_POWER && reload_completed"
13921 [(set (match_dup 0)
13922 (gt:SI (match_dup 1) (match_dup 2)))
13923 (set (match_dup 3)
13924 (compare:CC (match_dup 0)
13925 (const_int 0)))]
13926 "")
1fd4e8c1 13927
d0515b39 13928(define_insn "*plus_gt0<mode>"
a2dba291
DE		 13929 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13930 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13931 (const_int 0))
13932 (match_operand:P 2 "gpc_reg_operand" "r")))]
13933 ""
80103f96 13934 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
943c15ed
DE		 13935 [(set_attr "type" "three")
13936 (set_attr "length" "12")])
1fd4e8c1
RK		 13937
13938(define_insn ""
9ebbca7d 13939 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13940 (compare:CC
9ebbca7d 13941 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 13942 (const_int 0))
9ebbca7d 13943 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 13944 (const_int 0)))
9ebbca7d 13945 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 13946 "TARGET_32BIT"
9ebbca7d
GK		 13947 "@
13948 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13949 #"
b19003d8 13950 [(set_attr "type" "compare")
9ebbca7d
GK		 13951 (set_attr "length" "12,16")])
13952
13953(define_split
13954 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13955 (compare:CC
13956 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13957 (const_int 0))
13958 (match_operand:SI 2 "gpc_reg_operand" ""))
13959 (const_int 0)))
13960 (clobber (match_scratch:SI 3 ""))]
683bdff7 13961 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13962 [(set (match_dup 3)
13963 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13964 (match_dup 2)))
13965 (set (match_dup 0)
13966 (compare:CC (match_dup 3)
13967 (const_int 0)))]
13968 "")
1fd4e8c1 13969
f9562f27 13970(define_insn ""
9ebbca7d 13971 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
f9562f27 13972 (compare:CC
9ebbca7d 13973 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13974 (const_int 0))
9ebbca7d 13975 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13976 (const_int 0)))
9ebbca7d 13977 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 13978 "TARGET_64BIT"
9ebbca7d
GK		 13979 "@
13980 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13981 #"
f9562f27 13982 [(set_attr "type" "compare")
9ebbca7d
GK		 13983 (set_attr "length" "12,16")])
13984
13985(define_split
c921bad8 13986 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 13987 (compare:CC
13988 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13989 (const_int 0))
13990 (match_operand:DI 2 "gpc_reg_operand" ""))
13991 (const_int 0)))
13992 (clobber (match_scratch:DI 3 ""))]
683bdff7 13993 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13994 [(set (match_dup 3)
13995 (plus:DI (gt:DI (match_dup 1) (const_int 0))
097657c3 13996 (match_dup 2)))
9ebbca7d
GK		 13997 (set (match_dup 0)
13998 (compare:CC (match_dup 3)
13999 (const_int 0)))]
14000 "")
f9562f27 14001
1fd4e8c1 14002(define_insn ""
097657c3 14003 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9ebbca7d
GK		 14004 (compare:CC
14005 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14006 (const_int 0))
14007 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14008 (const_int 0)))
097657c3
AM		 14009 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14010 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 14011 "TARGET_32BIT"
9ebbca7d 14012 "@
097657c3 14013 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
9ebbca7d
GK		 14014 #"
14015 [(set_attr "type" "compare")
14016 (set_attr "length" "12,16")])
14017
14018(define_split
097657c3 14019 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1fd4e8c1 14020 (compare:CC
9ebbca7d 14021 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 14022 (const_int 0))
9ebbca7d 14023 (match_operand:SI 2 "gpc_reg_operand" ""))
1fd4e8c1 14024 (const_int 0)))
9ebbca7d 14025 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 14026 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 14027 "TARGET_32BIT && reload_completed"
097657c3 14028 [(set (match_dup 0)
9ebbca7d 14029 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 14030 (set (match_dup 3)
9ebbca7d
GK		 14031 (compare:CC (match_dup 0)
14032 (const_int 0)))]
14033 "")
1fd4e8c1 14034
f9562f27 14035(define_insn ""
097657c3 14036 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 14037 (compare:CC
9ebbca7d 14038 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 14039 (const_int 0))
9ebbca7d 14040 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 14041 (const_int 0)))
097657c3
AM		 14042 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14043 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 14044 "TARGET_64BIT"
9ebbca7d 14045 "@
097657c3 14046 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
9ebbca7d 14047 #"
f9562f27 14048 [(set_attr "type" "compare")
9ebbca7d
GK		 14049 (set_attr "length" "12,16")])
14050
14051(define_split
c921bad8 14052 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
9ebbca7d
GK		 14053 (compare:CC
14054 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14055 (const_int 0))
14056 (match_operand:DI 2 "gpc_reg_operand" ""))
14057 (const_int 0)))
14058 (set (match_operand:DI 0 "gpc_reg_operand" "")
097657c3 14059 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 14060 "TARGET_64BIT && reload_completed"
097657c3 14061 [(set (match_dup 0)
9ebbca7d 14062 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 14063 (set (match_dup 3)
9ebbca7d
GK		 14064 (compare:CC (match_dup 0)
14065 (const_int 0)))]
14066 "")
f9562f27 14067
1fd4e8c1 14068(define_insn ""
097657c3 14069 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 14070 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 14071 (match_operand:SI 2 "reg_or_short_operand" "r"))
097657c3 14072 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 14073 "TARGET_POWER"
097657c3 14074 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 14075 [(set_attr "length" "12")])
1fd4e8c1
RK		 14076
14077(define_insn ""
9ebbca7d 14078 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 14079 (compare:CC
9ebbca7d
GK		 14080 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14081 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14082 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 14083 (const_int 0)))
9ebbca7d 14084 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 14085 "TARGET_POWER"
9ebbca7d
GK		 14086 "@
14087 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14088 #"
b19003d8 14089 [(set_attr "type" "compare")
9ebbca7d
GK		 14090 (set_attr "length" "12,16")])
14091
14092(define_split
14093 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14094 (compare:CC
14095 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14096 (match_operand:SI 2 "reg_or_short_operand" ""))
14097 (match_operand:SI 3 "gpc_reg_operand" ""))
14098 (const_int 0)))
14099 (clobber (match_scratch:SI 4 ""))]
14100 "TARGET_POWER && reload_completed"
14101 [(set (match_dup 4)
097657c3 14102 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9ebbca7d
GK		 14103 (set (match_dup 0)
14104 (compare:CC (match_dup 4)
14105 (const_int 0)))]
14106 "")
1fd4e8c1
RK		 14107
14108(define_insn ""
097657c3 14109 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 14110 (compare:CC
9ebbca7d
GK		 14111 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14112 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14113 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 14114 (const_int 0)))
097657c3
AM		 14115 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14116 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 14117 "TARGET_POWER"
9ebbca7d 14118 "@
097657c3 14119 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 14120 #"
b19003d8 14121 [(set_attr "type" "compare")
9ebbca7d
GK		 14122 (set_attr "length" "12,16")])
14123
14124(define_split
097657c3 14125 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 14126 (compare:CC
14127 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14128 (match_operand:SI 2 "reg_or_short_operand" ""))
14129 (match_operand:SI 3 "gpc_reg_operand" ""))
14130 (const_int 0)))
14131 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 14132 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 14133 "TARGET_POWER && reload_completed"
097657c3 14134 [(set (match_dup 0)
9ebbca7d 14135 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 14136 (set (match_dup 4)
9ebbca7d
GK		 14137 (compare:CC (match_dup 0)
14138 (const_int 0)))]
14139 "")
1fd4e8c1 14140
1fd4e8c1 14141(define_insn ""
cd2b37d9
RK		 14142 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14143 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 14144 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
ca7f5001
RK		 14145 "TARGET_POWER"
14146 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 14147 [(set_attr "length" "12")])
1fd4e8c1 14148
ce45ef46
DE		 14149(define_insn_and_split "*gtu<mode>"
14150 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14151 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14152 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14153 ""
c0600ecd 14154 "#"
ce45ef46
DE		 14155 ""
14156 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14157 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 14158 "")
f9562f27 14159
1e24ce83 14160(define_insn_and_split "*gtu<mode>_compare"
9ebbca7d 14161 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 14162 (compare:CC
a2dba291
DE		 14163 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14164 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 14165 (const_int 0)))
a2dba291
DE		 14166 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14167 (gtu:P (match_dup 1) (match_dup 2)))]
14168 ""
1e24ce83
DE		 14169 "#"
14170 ""
14171 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14172 (parallel [(set (match_dup 3)
14173 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14174 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 14175 "")
f9562f27 14176
1e24ce83 14177(define_insn_and_split "*plus_gtu<mode>"
a2dba291
DE		 14178 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14179 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14180 (match_operand:P 2 "reg_or_short_operand" "rI"))
14181 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14182 ""
c0600ecd 14183 "#"
04fa46cf 14184 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 14185 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14186 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 14187 "")
f9562f27 14188
1e24ce83 14189(define_insn_and_split "*plus_gtu<mode>_compare"
097657c3 14190 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 14191 (compare:CC
1e24ce83
DE		 14192 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14193 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14194 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
f9562f27 14195 (const_int 0)))
1e24ce83
DE		 14196 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14197 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14198 ""
14199 "#"
14200 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14201 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14202 (parallel [(set (match_dup 4)
14203 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14204 (const_int 0)))
14205 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 14206 "")
f9562f27 14207
ce45ef46
DE		 14208(define_insn "*neg_gtu<mode>"
14209 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14210 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14211 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14212 ""
ca7f5001 14213 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
943c15ed 14214 [(set_attr "type" "two")
c0600ecd 14215 (set_attr "length" "8")])
f9562f27 14216
1fd4e8c1
RK		 14217\f
14218;; Define both directions of branch and return. If we need a reload
14219;; register, we'd rather use CR0 since it is much easier to copy a
14220;; register CC value to there.
14221
14222(define_insn ""
14223 [(set (pc)
14224 (if_then_else (match_operator 1 "branch_comparison_operator"
14225 [(match_operand 2
b54cf83a 14226 "cc_reg_operand" "y")
1fd4e8c1
RK		 14227 (const_int 0)])
14228 (label_ref (match_operand 0 "" ""))
14229 (pc)))]
14230 ""
b19003d8
RK		 14231 "*
14232{
12a4e8c5 14233 return output_cbranch (operands[1], \"%l0\", 0, insn);
b19003d8
RK		 14234}"
14235 [(set_attr "type" "branch")])
14236
1fd4e8c1
RK		 14237(define_insn ""
14238 [(set (pc)
14239 (if_then_else (match_operator 0 "branch_comparison_operator"
14240 [(match_operand 1
b54cf83a 14241 "cc_reg_operand" "y")
1fd4e8c1
RK		 14242 (const_int 0)])
14243 (return)
14244 (pc)))]
14245 "direct_return ()"
12a4e8c5
GK		 14246 "*
14247{
14248 return output_cbranch (operands[0], NULL, 0, insn);
14249}"
9c6fdb46 14250 [(set_attr "type" "jmpreg")
39a10a29 14251 (set_attr "length" "4")])
1fd4e8c1
RK		 14252
14253(define_insn ""
14254 [(set (pc)
14255 (if_then_else (match_operator 1 "branch_comparison_operator"
14256 [(match_operand 2
b54cf83a 14257 "cc_reg_operand" "y")
1fd4e8c1
RK		 14258 (const_int 0)])
14259 (pc)
14260 (label_ref (match_operand 0 "" ""))))]
14261 ""
b19003d8
RK		 14262 "*
14263{
12a4e8c5 14264 return output_cbranch (operands[1], \"%l0\", 1, insn);
b19003d8
RK		 14265}"
14266 [(set_attr "type" "branch")])
1fd4e8c1
RK		 14267
14268(define_insn ""
14269 [(set (pc)
14270 (if_then_else (match_operator 0 "branch_comparison_operator"
14271 [(match_operand 1
b54cf83a 14272 "cc_reg_operand" "y")
1fd4e8c1
RK		 14273 (const_int 0)])
14274 (pc)
14275 (return)))]
14276 "direct_return ()"
12a4e8c5
GK		 14277 "*
14278{
14279 return output_cbranch (operands[0], NULL, 1, insn);
14280}"
9c6fdb46 14281 [(set_attr "type" "jmpreg")
39a10a29
GK		 14282 (set_attr "length" "4")])
14283
14284;; Logic on condition register values.
14285
14286; This pattern matches things like
14287; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14288; (eq:SI (reg:CCFP 68) (const_int 0)))
14289; (const_int 1)))
14290; which are generated by the branch logic.
b54cf83a 14291; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
39a10a29 14292
423c1189 14293(define_insn "*cceq_ior_compare"
b54cf83a 14294 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 14295 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
b54cf83a 14296 [(match_operator:SI 2
39a10a29
GK		 14297 "branch_positive_comparison_operator"
14298 [(match_operand 3
b54cf83a 14299 "cc_reg_operand" "y,y")
39a10a29 14300 (const_int 0)])
b54cf83a 14301 (match_operator:SI 4
39a10a29
GK		 14302 "branch_positive_comparison_operator"
14303 [(match_operand 5
b54cf83a 14304 "cc_reg_operand" "0,y")
39a10a29
GK		 14305 (const_int 0)])])
14306 (const_int 1)))]
24fab1d3 14307 ""
39a10a29 14308 "cr%q1 %E0,%j2,%j4"
b54cf83a 14309 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 14310
14311; Why is the constant -1 here, but 1 in the previous pattern?
14312; Because ~1 has all but the low bit set.
14313(define_insn ""
b54cf83a 14314 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 14315 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
b54cf83a 14316 [(not:SI (match_operator:SI 2
39a10a29
GK		 14317 "branch_positive_comparison_operator"
14318 [(match_operand 3
b54cf83a 14319 "cc_reg_operand" "y,y")
39a10a29
GK		 14320 (const_int 0)]))
14321 (match_operator:SI 4
14322 "branch_positive_comparison_operator"
14323 [(match_operand 5
b54cf83a 14324 "cc_reg_operand" "0,y")
39a10a29
GK		 14325 (const_int 0)])])
14326 (const_int -1)))]
14327 ""
14328 "cr%q1 %E0,%j2,%j4"
b54cf83a 14329 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29 14330
423c1189 14331(define_insn "*cceq_rev_compare"
b54cf83a 14332 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
6c873122 14333 (compare:CCEQ (match_operator:SI 1
39a10a29 14334 "branch_positive_comparison_operator"
6c873122 14335 [(match_operand 2
b54cf83a 14336 "cc_reg_operand" "0,y")
39a10a29
GK		 14337 (const_int 0)])
14338 (const_int 0)))]
423c1189 14339 ""
251b3667 14340 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
b54cf83a 14341 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 14342
14343;; If we are comparing the result of two comparisons, this can be done
14344;; using creqv or crxor.
14345
14346(define_insn_and_split ""
14347 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14348 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14349 [(match_operand 2 "cc_reg_operand" "y")
14350 (const_int 0)])
14351 (match_operator 3 "branch_comparison_operator"
14352 [(match_operand 4 "cc_reg_operand" "y")
14353 (const_int 0)])))]
14354 ""
14355 "#"
14356 ""
14357 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14358 (match_dup 5)))]
14359 "
14360{
14361 int positive_1, positive_2;
14362
364849ee
DE		 14363 positive_1 = branch_positive_comparison_operator (operands[1],
14364 GET_MODE (operands[1]));
14365 positive_2 = branch_positive_comparison_operator (operands[3],
14366 GET_MODE (operands[3]));
39a10a29
GK		 14367
14368 if (! positive_1)
1c563bed 14369 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
0f4c242b
KH		 14370 GET_CODE (operands[1])),
14371 SImode,
14372 operands[2], const0_rtx);
39a10a29 14373 else if (GET_MODE (operands[1]) != SImode)
0f4c242b
KH		 14374 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14375 operands[2], const0_rtx);
39a10a29
GK		 14376
14377 if (! positive_2)
1c563bed 14378 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
0f4c242b
KH		 14379 GET_CODE (operands[3])),
14380 SImode,
14381 operands[4], const0_rtx);
39a10a29 14382 else if (GET_MODE (operands[3]) != SImode)
0f4c242b
KH		 14383 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14384 operands[4], const0_rtx);
39a10a29
GK		 14385
14386 if (positive_1 == positive_2)
251b3667
DE		 14387 {
14388 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14389 operands[5] = constm1_rtx;
14390 }
14391 else
14392 {
14393 operands[5] = const1_rtx;
14394 }
39a10a29 14395}")
1fd4e8c1
RK		 14396
14397;; Unconditional branch and return.
14398
14399(define_insn "jump"
14400 [(set (pc)
14401 (label_ref (match_operand 0 "" "")))]
14402 ""
b7ff3d82
DE		 14403 "b %l0"
14404 [(set_attr "type" "branch")])
1fd4e8c1
RK		 14405
14406(define_insn "return"
14407 [(return)]
14408 "direct_return ()"
324e52cc
TG		 14409 "{br|blr}"
14410 [(set_attr "type" "jmpreg")])
1fd4e8c1 14411
0ad91047 14412(define_expand "indirect_jump"
4ae234b0 14413 [(set (pc) (match_operand 0 "register_operand" ""))])
0ad91047 14414
4ae234b0
GK		 14415(define_insn "*indirect_jump<mode>"
14416 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14417 ""
b92b324d
DE		 14418 "@
14419 bctr
14420 {br|blr}"
324e52cc 14421 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14422
14423;; Table jump for switch statements:
14424(define_expand "tablejump"
e6ca2c17
DE		 14425 [(use (match_operand 0 "" ""))
14426 (use (label_ref (match_operand 1 "" "")))]
14427 ""
14428 "
14429{
14430 if (TARGET_32BIT)
14431 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14432 else
14433 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14434 DONE;
14435}")
14436
14437(define_expand "tablejumpsi"
1fd4e8c1
RK		 14438 [(set (match_dup 3)
14439 (plus:SI (match_operand:SI 0 "" "")
14440 (match_dup 2)))
14441 (parallel [(set (pc) (match_dup 3))
14442 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14443 "TARGET_32BIT"
1fd4e8c1
RK		 14444 "
14445{ operands[0] = force_reg (SImode, operands[0]);
c5c76735 14446 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
1fd4e8c1
RK		 14447 operands[3] = gen_reg_rtx (SImode);
14448}")
14449
e6ca2c17 14450(define_expand "tablejumpdi"
6ae08853 14451 [(set (match_dup 4)
e42ac3de 14452 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
9ebbca7d
GK		 14453 (set (match_dup 3)
14454 (plus:DI (match_dup 4)
e6ca2c17
DE		 14455 (match_dup 2)))
14456 (parallel [(set (pc) (match_dup 3))
14457 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14458 "TARGET_64BIT"
e6ca2c17 14459 "
9ebbca7d 14460{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
e6ca2c17 14461 operands[3] = gen_reg_rtx (DImode);
9ebbca7d 14462 operands[4] = gen_reg_rtx (DImode);
e6ca2c17
DE		 14463}")
14464
ce45ef46 14465(define_insn "*tablejump<mode>_internal1"
1fd4e8c1 14466 [(set (pc)
4ae234b0 14467 (match_operand:P 0 "register_operand" "c,*l"))
1fd4e8c1 14468 (use (label_ref (match_operand 1 "" "")))]
4ae234b0 14469 ""
c859cda6
DJ		 14470 "@
14471 bctr
14472 {br|blr}"
a6845123 14473 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14474
14475(define_insn "nop"
14476 [(const_int 0)]
14477 ""
ca7f5001 14478 "{cror 0,0,0|nop}")
1fd4e8c1 14479\f
7e69e155 14480;; Define the subtract-one-and-jump insns, starting with the template
c225ba7b
RK		 14481;; so loop.c knows what to generate.
14482
5527bf14
RH		 14483(define_expand "doloop_end"
14484 [(use (match_operand 0 "" "")) ; loop pseudo
14485 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14486 (use (match_operand 2 "" "")) ; max iterations
14487 (use (match_operand 3 "" "")) ; loop level
14488 (use (match_operand 4 "" ""))] ; label
0ad91047
DE		 14489 ""
14490 "
14491{
5527bf14
RH		 14492 /* Only use this on innermost loops. */
14493 if (INTVAL (operands[3]) > 1)
14494 FAIL;
683bdff7 14495 if (TARGET_64BIT)
5527bf14
RH		 14496 {
14497 if (GET_MODE (operands[0]) != DImode)
14498 FAIL;
14499 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14500 }
0ad91047 14501 else
5527bf14
RH		 14502 {
14503 if (GET_MODE (operands[0]) != SImode)
14504 FAIL;
14505 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14506 }
0ad91047
DE		 14507 DONE;
14508}")
14509
4ae234b0 14510(define_expand "ctr<mode>"
3cb999d8 14511 [(parallel [(set (pc)
4ae234b0 14512 (if_then_else (ne (match_operand:P 0 "register_operand" "")
3cb999d8
DE		 14513 (const_int 1))
14514 (label_ref (match_operand 1 "" ""))
14515 (pc)))
b6c9286a 14516 (set (match_dup 0)
4ae234b0 14517 (plus:P (match_dup 0)
b6c9286a 14518 (const_int -1)))
5f81043f 14519 (clobber (match_scratch:CC 2 ""))
4ae234b0
GK		 14520 (clobber (match_scratch:P 3 ""))])]
14521 ""
61c07d3c 14522 "")
c225ba7b 14523
1fd4e8c1
RK		 14524;; We need to be able to do this for any operand, including MEM, or we
14525;; will cause reload to blow up since we don't allow output reloads on
7e69e155 14526;; JUMP_INSNs.
0ad91047 14527;; For the length attribute to be calculated correctly, the
5f81043f
RK		 14528;; label MUST be operand 0.
14529
4ae234b0 14530(define_insn "*ctr<mode>_internal1"
0ad91047 14531 [(set (pc)
4ae234b0 14532 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14533 (const_int 1))
14534 (label_ref (match_operand 0 "" ""))
14535 (pc)))
4ae234b0
GK		 14536 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14537 (plus:P (match_dup 1)
0ad91047 14538 (const_int -1)))
43b68ce5 14539 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14540 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14541 ""
0ad91047
DE		 14542 "*
14543{
14544 if (which_alternative != 0)
14545 return \"#\";
856a6884 14546 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14547 return \"{bdn|bdnz} %l0\";
14548 else
f607bc57 14549 return \"bdz $+8\;b %l0\";
0ad91047
DE		 14550}"
14551 [(set_attr "type" "branch")
5a195cb5 14552 (set_attr "length" "*,12,16,16")])
0ad91047 14553
4ae234b0 14554(define_insn "*ctr<mode>_internal2"
0ad91047 14555 [(set (pc)
4ae234b0 14556 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14557 (const_int 1))
14558 (pc)
14559 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14560 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14561 (plus:P (match_dup 1)
0ad91047 14562 (const_int -1)))
43b68ce5 14563 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14564 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14565 ""
5f81043f
RK		 14566 "*
14567{
14568 if (which_alternative != 0)
14569 return \"#\";
856a6884 14570 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14571 return \"bdz %l0\";
14572 else
f607bc57 14573 return \"{bdn|bdnz} $+8\;b %l0\";
5f81043f
RK		 14574}"
14575 [(set_attr "type" "branch")
5a195cb5 14576 (set_attr "length" "*,12,16,16")])
5f81043f 14577
0ad91047
DE		 14578;; Similar but use EQ
14579
4ae234b0 14580(define_insn "*ctr<mode>_internal5"
5f81043f 14581 [(set (pc)
4ae234b0 14582 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
1fd4e8c1 14583 (const_int 1))
a6845123 14584 (label_ref (match_operand 0 "" ""))
1fd4e8c1 14585 (pc)))
4ae234b0
GK		 14586 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14587 (plus:P (match_dup 1)
0ad91047 14588 (const_int -1)))
43b68ce5 14589 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14590 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14591 ""
0ad91047
DE		 14592 "*
14593{
14594 if (which_alternative != 0)
14595 return \"#\";
856a6884 14596 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14597 return \"bdz %l0\";
14598 else
f607bc57 14599 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 14600}"
14601 [(set_attr "type" "branch")
5a195cb5 14602 (set_attr "length" "*,12,16,16")])
0ad91047 14603
4ae234b0 14604(define_insn "*ctr<mode>_internal6"
0ad91047 14605 [(set (pc)
4ae234b0 14606 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14607 (const_int 1))
14608 (pc)
14609 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14610 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14611 (plus:P (match_dup 1)
0ad91047 14612 (const_int -1)))
43b68ce5 14613 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14614 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14615 ""
5f81043f
RK		 14616 "*
14617{
14618 if (which_alternative != 0)
14619 return \"#\";
856a6884 14620 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14621 return \"{bdn|bdnz} %l0\";
14622 else
f607bc57 14623 return \"bdz $+8\;b %l0\";
5f81043f
RK		 14624}"
14625 [(set_attr "type" "branch")
5a195cb5 14626 (set_attr "length" "*,12,16,16")])
5f81043f 14627
0ad91047
DE		 14628;; Now the splitters if we could not allocate the CTR register
14629
1fd4e8c1
RK		 14630(define_split
14631 [(set (pc)
14632 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14633 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14634 (const_int 1)])
61c07d3c
DE		 14635 (match_operand 5 "" "")
14636 (match_operand 6 "" "")))
4ae234b0
GK		 14637 (set (match_operand:P 0 "gpc_reg_operand" "")
14638 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14639 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14640 (clobber (match_scratch:P 4 ""))]
14641 "reload_completed"
0ad91047 14642 [(parallel [(set (match_dup 3)
4ae234b0 14643 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14644 (const_int -1))
14645 (const_int 0)))
14646 (set (match_dup 0)
4ae234b0 14647 (plus:P (match_dup 1)
0ad91047 14648 (const_int -1)))])
61c07d3c
DE		 14649 (set (pc) (if_then_else (match_dup 7)
14650 (match_dup 5)
14651 (match_dup 6)))]
0ad91047 14652 "
0f4c242b
KH		 14653{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14654 operands[3], const0_rtx); }")
0ad91047
DE		 14655
14656(define_split
14657 [(set (pc)
14658 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14659 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14660 (const_int 1)])
61c07d3c
DE		 14661 (match_operand 5 "" "")
14662 (match_operand 6 "" "")))
4ae234b0
GK		 14663 (set (match_operand:P 0 "nonimmediate_operand" "")
14664 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14665 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14666 (clobber (match_scratch:P 4 ""))]
14667 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
0ad91047 14668 [(parallel [(set (match_dup 3)
4ae234b0 14669 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14670 (const_int -1))
14671 (const_int 0)))
14672 (set (match_dup 4)
4ae234b0 14673 (plus:P (match_dup 1)
0ad91047
DE		 14674 (const_int -1)))])
14675 (set (match_dup 0)
14676 (match_dup 4))
61c07d3c
DE		 14677 (set (pc) (if_then_else (match_dup 7)
14678 (match_dup 5)
14679 (match_dup 6)))]
0ad91047 14680 "
0f4c242b
KH		 14681{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14682 operands[3], const0_rtx); }")
e0cd0770
JC		 14683\f
14684(define_insn "trap"
14685 [(trap_if (const_int 1) (const_int 0))]
14686 ""
44cd321e
PS		 14687 "{t 31,0,0|trap}"
14688 [(set_attr "type" "trap")])
e0cd0770 14689
f90b7a5a
PB		 14690(define_expand "ctrap<mode>4"
14691 [(trap_if (match_operator 0 "ordered_comparison_operator"
14692 [(match_operand:GPR 1 "register_operand")
14693 (match_operand:GPR 2 "reg_or_short_operand")])
14694 (match_operand 3 "zero_constant" ""))]
e0cd0770 14695 ""
f90b7a5a 14696 "")
e0cd0770
JC		 14697
14698(define_insn ""
f90b7a5a 14699 [(trap_if (match_operator 0 "ordered_comparison_operator"
4ae234b0
GK		 14700 [(match_operand:GPR 1 "register_operand" "r")
14701 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
e0cd0770
JC		 14702 (const_int 0))]
14703 ""
44cd321e
PS		 14704 "{t|t<wd>}%V0%I2 %1,%2"
14705 [(set_attr "type" "trap")])
9ebbca7d
GK		 14706\f
14707;; Insns related to generating the function prologue and epilogue.
14708
14709(define_expand "prologue"
14710 [(use (const_int 0))]
14711 "TARGET_SCHED_PROLOG"
14712 "
14713{
14714 rs6000_emit_prologue ();
14715 DONE;
14716}")
14717
2c4a9cff
DE		 14718(define_insn "*movesi_from_cr_one"
14719 [(match_parallel 0 "mfcr_operation"
14720 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14721 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14722 (match_operand 3 "immediate_operand" "n")]
14723 UNSPEC_MOVESI_FROM_CR))])]
14724 "TARGET_MFCRF"
14725 "*
14726{
14727 int mask = 0;
14728 int i;
14729 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14730 {
14731 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14732 operands[4] = GEN_INT (mask);
14733 output_asm_insn (\"mfcr %1,%4\", operands);
14734 }
14735 return \"\";
14736}"
14737 [(set_attr "type" "mfcrf")])
14738
9ebbca7d
GK		 14739(define_insn "movesi_from_cr"
14740 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1de43f85
DE		 14741 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14742 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14743 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14744 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
615158e2 14745 UNSPEC_MOVESI_FROM_CR))]
9ebbca7d 14746 ""
309323c2 14747 "mfcr %0"
b54cf83a 14748 [(set_attr "type" "mfcr")])
9ebbca7d
GK		 14749
14750(define_insn "*stmw"
e033a023
DE		 14751 [(match_parallel 0 "stmw_operation"
14752 [(set (match_operand:SI 1 "memory_operand" "=m")
14753 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14754 "TARGET_MULTIPLE"
9c6fdb46
DE		 14755 "{stm|stmw} %2,%1"
14756 [(set_attr "type" "store_ux")])
6ae08853 14757
f78c3290
NF		 14758(define_insn "*save_gpregs_<mode>"
14759 [(match_parallel 0 "any_parallel_operand"
14760 [(clobber (reg:P 65))
14761 (use (match_operand:P 1 "symbol_ref_operand" "s"))
e1ece9f1
NF		 14762 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14763 (set (match_operand:P 3 "memory_operand" "=m")
14764 (match_operand:P 4 "gpc_reg_operand" "r"))])]
f78c3290
NF		 14765 ""
14766 "bl %z1"
14767 [(set_attr "type" "branch")
14768 (set_attr "length" "4")])
14769
4ae234b0 14770(define_insn "*save_fpregs_<mode>"
85d346f1 14771 [(match_parallel 0 "any_parallel_operand"
e65a3857 14772 [(clobber (reg:P 65))
f78c3290 14773 (use (match_operand:P 1 "symbol_ref_operand" "s"))
e1ece9f1
NF		 14774 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14775 (set (match_operand:DF 3 "memory_operand" "=m")
799dbb0f 14776 (match_operand:DF 4 "gpc_reg_operand" "d"))])]
4ae234b0 14777 ""
e65a3857 14778 "bl %z1"
e033a023
DE		 14779 [(set_attr "type" "branch")
14780 (set_attr "length" "4")])
9ebbca7d
GK		 14781
14782; These are to explain that changes to the stack pointer should
14783; not be moved over stores to stack memory.
14784(define_insn "stack_tie"
14785 [(set (match_operand:BLK 0 "memory_operand" "+m")
615158e2 14786 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9ebbca7d
GK		 14787 ""
14788 ""
14789 [(set_attr "length" "0")])
14790
14791
14792(define_expand "epilogue"
14793 [(use (const_int 0))]
14794 "TARGET_SCHED_PROLOG"
14795 "
14796{
14797 rs6000_emit_epilogue (FALSE);
14798 DONE;
14799}")
14800
14801; On some processors, doing the mtcrf one CC register at a time is
14802; faster (like on the 604e). On others, doing them all at once is
14803; faster; for instance, on the 601 and 750.
14804
14805(define_expand "movsi_to_cr_one"
e42ac3de
RS		 14806 [(set (match_operand:CC 0 "cc_reg_operand" "")
14807 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
615158e2 14808 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
35aba846
DE		 14809 ""
14810 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
9ebbca7d
GK		 14811
14812(define_insn "*movsi_to_cr"
35aba846
DE		 14813 [(match_parallel 0 "mtcrf_operation"
14814 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14815 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14816 (match_operand 3 "immediate_operand" "n")]
615158e2 14817 UNSPEC_MOVESI_TO_CR))])]
9ebbca7d 14818 ""
e35b9579
GK		 14819 "*
14820{
14821 int mask = 0;
14822 int i;
14823 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14824 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14825 operands[4] = GEN_INT (mask);
14826 return \"mtcrf %4,%2\";
309323c2 14827}"
b54cf83a 14828 [(set_attr "type" "mtcr")])
9ebbca7d 14829
b54cf83a 14830(define_insn "*mtcrfsi"
309323c2
DE		 14831 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14832 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
615158e2
JJ		 14833 (match_operand 2 "immediate_operand" "n")]
14834 UNSPEC_MOVESI_TO_CR))]
6ae08853 14835 "GET_CODE (operands[0]) == REG
309323c2
DE		 14836 && CR_REGNO_P (REGNO (operands[0]))
14837 && GET_CODE (operands[2]) == CONST_INT
14838 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14839 "mtcrf %R0,%1"
b54cf83a 14840 [(set_attr "type" "mtcr")])
9ebbca7d
GK		 14841
14842; The load-multiple instructions have similar properties.
14843; Note that "load_multiple" is a name known to the machine-independent
9c6fdb46 14844; code that actually corresponds to the PowerPC load-string.
9ebbca7d
GK		 14845
14846(define_insn "*lmw"
35aba846
DE		 14847 [(match_parallel 0 "lmw_operation"
14848 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14849 (match_operand:SI 2 "memory_operand" "m"))])]
14850 "TARGET_MULTIPLE"
9c6fdb46 14851 "{lm|lmw} %1,%2"
c921bad8
AP		 14852 [(set_attr "type" "load_ux")
14853 (set_attr "cell_micro" "always")])
6ae08853 14854
4ae234b0 14855(define_insn "*return_internal_<mode>"
e35b9579 14856 [(return)
4ae234b0
GK		 14857 (use (match_operand:P 0 "register_operand" "lc"))]
14858 ""
cccf3bdc 14859 "b%T0"
9ebbca7d
GK		 14860 [(set_attr "type" "jmpreg")])
14861
14862; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
85d346f1 14863; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
9ebbca7d 14864
f78c3290
NF		 14865(define_insn "*restore_gpregs_<mode>"
14866 [(match_parallel 0 "any_parallel_operand"
14867 [(clobber (match_operand:P 1 "register_operand" "=l"))
14868 (use (match_operand:P 2 "symbol_ref_operand" "s"))
e1ece9f1
NF		 14869 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14870 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14871 (match_operand:P 5 "memory_operand" "m"))])]
f78c3290
NF		 14872 ""
14873 "bl %z2"
14874 [(set_attr "type" "branch")
14875 (set_attr "length" "4")])
14876
14877(define_insn "*return_and_restore_gpregs_<mode>"
14878 [(match_parallel 0 "any_parallel_operand"
14879 [(return)
14880 (clobber (match_operand:P 1 "register_operand" "=l"))
14881 (use (match_operand:P 2 "symbol_ref_operand" "s"))
e1ece9f1
NF		 14882 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14883 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14884 (match_operand:P 5 "memory_operand" "m"))])]
f78c3290
NF		 14885 ""
14886 "b %z2"
14887 [(set_attr "type" "branch")
14888 (set_attr "length" "4")])
14889
4ae234b0 14890(define_insn "*return_and_restore_fpregs_<mode>"
85d346f1 14891 [(match_parallel 0 "any_parallel_operand"
e35b9579 14892 [(return)
f78c3290
NF		 14893 (clobber (match_operand:P 1 "register_operand" "=l"))
14894 (use (match_operand:P 2 "symbol_ref_operand" "s"))
e1ece9f1 14895 (use (match_operand:P 3 "gpc_reg_operand" "r"))
799dbb0f 14896 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
e1ece9f1 14897 (match_operand:DF 5 "memory_operand" "m"))])]
4ae234b0 14898 ""
f78c3290
NF		 14899 "b %z2"
14900 [(set_attr "type" "branch")
14901 (set_attr "length" "4")])
9ebbca7d 14902
83720594
RH		 14903; This is used in compiling the unwind routines.
14904(define_expand "eh_return"
34dc173c 14905 [(use (match_operand 0 "general_operand" ""))]
9ebbca7d
GK		 14906 ""
14907 "
14908{
83720594 14909 if (TARGET_32BIT)
34dc173c 14910 emit_insn (gen_eh_set_lr_si (operands[0]));
9ebbca7d 14911 else
34dc173c 14912 emit_insn (gen_eh_set_lr_di (operands[0]));
9ebbca7d
GK		 14913 DONE;
14914}")
14915
83720594 14916; We can't expand this before we know where the link register is stored.
4ae234b0
GK		 14917(define_insn "eh_set_lr_<mode>"
14918 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
615158e2 14919 UNSPECV_EH_RR)
4ae234b0
GK		 14920 (clobber (match_scratch:P 1 "=&b"))]
14921 ""
83720594 14922 "#")
9ebbca7d
GK		 14923
14924(define_split
615158e2 14925 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
83720594
RH		 14926 (clobber (match_scratch 1 ""))]
14927 "reload_completed"
14928 [(const_int 0)]
9ebbca7d
GK		 14929 "
14930{
d1d0c603 14931 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
83720594
RH		 14932 DONE;
14933}")
0ac081f6 14934
01a2ccd0 14935(define_insn "prefetch"
3256a76e 14936 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
6041bf2f
DE		 14937 (match_operand:SI 1 "const_int_operand" "n")
14938 (match_operand:SI 2 "const_int_operand" "n"))]
01a2ccd0 14939 "TARGET_POWERPC"
6041bf2f
DE		 14940 "*
14941{
01a2ccd0
DE		 14942 if (GET_CODE (operands[0]) == REG)
14943 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14944 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
6041bf2f
DE		 14945}"
14946 [(set_attr "type" "load")])
915167f5 14947\f
a3170dc6 14948
f565b0a1 14949(include "sync.md")
10ed84db 14950(include "altivec.md")
a3170dc6 14951(include "spe.md")
7393f7f8 14952(include "dfp.md")
96038623 14953(include "paired.md")
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