]> git.ipfire.org Git - thirdparty/gcc.git/blame - gcc/config/rs6000/rs6000.md
projects / thirdparty / gcc.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Fix typo.
[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.md
CommitLineData
996a5f59 1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
d24652ee 2;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
8ef65e3d 3;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
602ea4d3 4;; Free Software Foundation, Inc.
996a5f59 5;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
1fd4e8c1 6
5de601cf 7;; This file is part of GCC.
1fd4e8c1 8
5de601cf
NC		 9;; GCC is free software; you can redistribute it and/or modify it
10;; under the terms of the GNU General Public License as published
2f83c7d6 11;; by the Free Software Foundation; either version 3, or (at your
5de601cf 12;; option) any later version.
1fd4e8c1 13
5de601cf
NC		 14;; GCC is distributed in the hope that it will be useful, but WITHOUT
15;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17;; License for more details.
1fd4e8c1
RK		 18
19;; You should have received a copy of the GNU General Public License
2f83c7d6
NC		 20;; along with GCC; see the file COPYING3. If not see
21;; <http://www.gnu.org/licenses/>.
1fd4e8c1
RK		 22
23;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
9ebbca7d 24
1de43f85
DE		 25;;
26;; REGNOS
27;;
28
29(define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
51
615158e2
JJ		 52;;
53;; UNSPEC usage
54;;
55
56(define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
59 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
60 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
61 (UNSPEC_MOVSI_GOT 8)
62 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
63 (UNSPEC_FCTIWZ 10)
9719f3b7
DE		 64 (UNSPEC_FRIM 11)
65 (UNSPEC_FRIN 12)
66 (UNSPEC_FRIP 13)
67 (UNSPEC_FRIZ 14)
615158e2
JJ		 68 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
69 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
70 (UNSPEC_TLSGD 17)
71 (UNSPEC_TLSLD 18)
72 (UNSPEC_MOVESI_FROM_CR 19)
73 (UNSPEC_MOVESI_TO_CR 20)
74 (UNSPEC_TLSDTPREL 21)
75 (UNSPEC_TLSDTPRELHA 22)
76 (UNSPEC_TLSDTPRELLO 23)
77 (UNSPEC_TLSGOTDTPREL 24)
78 (UNSPEC_TLSTPREL 25)
79 (UNSPEC_TLSTPRELHA 26)
80 (UNSPEC_TLSTPRELLO 27)
81 (UNSPEC_TLSGOTTPREL 28)
82 (UNSPEC_TLSTLS 29)
ecb62ae7 83 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
cef6b86c 84 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
da4c340c 85 (UNSPEC_STFIWX 32)
9f0076e5
DE		 86 (UNSPEC_POPCNTB 33)
87 (UNSPEC_FRES 34)
88 (UNSPEC_SP_SET 35)
89 (UNSPEC_SP_TEST 36)
90 (UNSPEC_SYNC 37)
91 (UNSPEC_LWSYNC 38)
92 (UNSPEC_ISYNC 39)
93 (UNSPEC_SYNC_OP 40)
94 (UNSPEC_ATOMIC 41)
95 (UNSPEC_CMPXCHG 42)
96 (UNSPEC_XCHG 43)
97 (UNSPEC_AND 44)
716019c0
JM		 98 (UNSPEC_DLMZB 45)
99 (UNSPEC_DLMZB_CR 46)
100 (UNSPEC_DLMZB_STRLEN 47)
9c78b944 101 (UNSPEC_RSQRT 48)
615158e2
JJ		 102 ])
103
104;;
105;; UNSPEC_VOLATILE usage
106;;
107
108(define_constants
109 [(UNSPECV_BLOCK 0)
b52110d4
DE		 110 (UNSPECV_LL 1) ; load-locked
111 (UNSPECV_SC 2) ; store-conditional
615158e2
JJ		 112 (UNSPECV_EH_RR 9) ; eh_reg_restore
113 ])
1fd4e8c1
RK		 114\f
115;; Define an insn type attribute. This is used in function unit delay
116;; computations.
44cd321e 117(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr"
1fd4e8c1
RK		 118 (const_string "integer"))
119
b19003d8 120;; Length (in bytes).
6ae08853 121; '(pc)' in the following doesn't include the instruction itself; it is
6cbadf36 122; calculated as if the instruction had zero size.
b19003d8
RK		 123(define_attr "length" ""
124 (if_then_else (eq_attr "type" "branch")
6cbadf36 125 (if_then_else (and (ge (minus (match_dup 0) (pc))
b19003d8 126 (const_int -32768))
6cbadf36
GK		 127 (lt (minus (match_dup 0) (pc))
128 (const_int 32764)))
39a10a29
GK		 129 (const_int 4)
130 (const_int 8))
b19003d8
RK		 131 (const_int 4)))
132
cfb557c4
RK		 133;; Processor type -- this attribute must exactly match the processor_type
134;; enumeration in rs6000.h.
135
edae5fe3 136(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,power4,power5,power6,cell"
cfb557c4
RK		 137 (const (symbol_ref "rs6000_cpu_attr")))
138
d296e02e
AP		 139
140;; If this instruction is microcoded on the CELL processor
141; The default for load and stores is conditional
142; The default for load extended and the recorded instructions is always microcoded
143(define_attr "cell_micro" "not,conditional,always"
144 (if_then_else (ior (ior (eq_attr "type" "load")
145 (eq_attr "type" "store"))
146 (ior (eq_attr "type" "fpload")
147 (eq_attr "type" "fpstore")))
148 (const_string "conditional")
149 (if_then_else (ior (eq_attr "type" "load_ext")
150 (ior (eq_attr "type" "compare")
151 (eq_attr "type" "delayed_compare")))
152 (const_string "always")
153 (const_string "not"))))
154
155
b54cf83a
DE		 156(automata_option "ndfa")
157
158(include "rios1.md")
159(include "rios2.md")
160(include "rs64.md")
161(include "mpc.md")
162(include "40x.md")
02ca7595 163(include "440.md")
b54cf83a
DE		 164(include "603.md")
165(include "6xx.md")
166(include "7xx.md")
167(include "7450.md")
5e8006fa 168(include "8540.md")
fa41c305 169(include "e300c2c3.md")
edae5fe3 170(include "e500mc.md")
b54cf83a 171(include "power4.md")
ec507f2d 172(include "power5.md")
44cd321e 173(include "power6.md")
d296e02e 174(include "cell.md")
48d72335
DE		 175
176(include "predicates.md")
279bb624 177(include "constraints.md")
48d72335 178
ac9e2cff 179(include "darwin.md")
309323c2 180
1fd4e8c1 181\f
3abcb3a7 182;; Mode iterators
915167f5 183
3abcb3a7 184; This mode iterator allows :GPR to be used to indicate the allowable size
915167f5 185; of whole values in GPRs.
3abcb3a7 186(define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
915167f5 187
0354e5d8 188; Any supported integer mode.
3abcb3a7 189(define_mode_iterator INT [QI HI SI DI TI])
915167f5 190
0354e5d8 191; Any supported integer mode that fits in one register.
3abcb3a7 192(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
915167f5 193
b5568f07 194; extend modes for DImode
3abcb3a7 195(define_mode_iterator QHSI [QI HI SI])
b5568f07 196
0354e5d8 197; SImode or DImode, even if DImode doesn't fit in GPRs.
3abcb3a7 198(define_mode_iterator SDI [SI DI])
0354e5d8
GK		 199
200; The size of a pointer. Also, the size of the value that a record-condition
201; (one with a '.') will compare.
3abcb3a7 202(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
2e6c9641 203
4ae234b0 204; Any hardware-supported floating-point mode
cf8e1455
DE		 205(define_mode_iterator FP [(SF "TARGET_HARD_FLOAT")
206 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
602ea4d3 207 (TF "!TARGET_IEEEQUAD
17caeff2
JM		 208 && TARGET_HARD_FLOAT
209 && (TARGET_FPRS || TARGET_E500_DOUBLE)
6ef9a246
JJ		 210 && TARGET_LONG_DOUBLE_128")
211 (DD "TARGET_DFP")
212 (TD "TARGET_DFP")])
4ae234b0 213
915167f5 214; Various instructions that come in SI and DI forms.
0354e5d8 215; A generic w/d attribute, for things like cmpw/cmpd.
b5568f07
DE		 216(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
217
218; DImode bits
219(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
915167f5
GK		 220
221\f
1fd4e8c1
RK		 222;; Start with fixed-point load and store insns. Here we put only the more
223;; complex forms. Basic data transfer is done later.
224
b5568f07 225(define_expand "zero_extend<mode>di2"
51b8fc2c 226 [(set (match_operand:DI 0 "gpc_reg_operand" "")
b5568f07 227 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
51b8fc2c
RK		 228 "TARGET_POWERPC64"
229 "")
230
b5568f07 231(define_insn "*zero_extend<mode>di2_internal1"
51b8fc2c 232 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
b5568f07 233 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
51b8fc2c
RK		 234 "TARGET_POWERPC64"
235 "@
b5568f07
DE		 236 l<wd>z%U1%X1 %0,%1
237 rldicl %0,%1,0,<dbits>"
51b8fc2c
RK		 238 [(set_attr "type" "load,*")])
239
b5568f07 240(define_insn "*zero_extend<mode>di2_internal2"
9ebbca7d 241 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
b5568f07 242 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
815cdc52 243 (const_int 0)))
9ebbca7d 244 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 245 "TARGET_64BIT"
9ebbca7d 246 "@
b5568f07 247 rldicl. %2,%1,0,<dbits>
9ebbca7d
GK		 248 #"
249 [(set_attr "type" "compare")
250 (set_attr "length" "4,8")])
251
252(define_split
253 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
b5568f07 254 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 255 (const_int 0)))
256 (clobber (match_scratch:DI 2 ""))]
257 "TARGET_POWERPC64 && reload_completed"
258 [(set (match_dup 2)
259 (zero_extend:DI (match_dup 1)))
260 (set (match_dup 0)
261 (compare:CC (match_dup 2)
262 (const_int 0)))]
263 "")
51b8fc2c 264
b5568f07 265(define_insn "*zero_extend<mode>di2_internal3"
9ebbca7d 266 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
b5568f07 267 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 268 (const_int 0)))
9ebbca7d 269 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 270 (zero_extend:DI (match_dup 1)))]
683bdff7 271 "TARGET_64BIT"
9ebbca7d 272 "@
b5568f07 273 rldicl. %0,%1,0,<dbits>
9ebbca7d
GK		 274 #"
275 [(set_attr "type" "compare")
276 (set_attr "length" "4,8")])
277
278(define_split
279 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
b5568f07 280 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
9ebbca7d
GK		 281 (const_int 0)))
282 (set (match_operand:DI 0 "gpc_reg_operand" "")
283 (zero_extend:DI (match_dup 1)))]
284 "TARGET_POWERPC64 && reload_completed"
285 [(set (match_dup 0)
286 (zero_extend:DI (match_dup 1)))
287 (set (match_dup 2)
288 (compare:CC (match_dup 0)
289 (const_int 0)))]
290 "")
51b8fc2c 291
2bee0449
RK		 292(define_insn "extendqidi2"
293 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
294 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 295 "TARGET_POWERPC64"
44cd321e
PS		 296 "extsb %0,%1"
297 [(set_attr "type" "exts")])
51b8fc2c
RK		 298
299(define_insn ""
9ebbca7d
GK		 300 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
301 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 302 (const_int 0)))
9ebbca7d 303 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 304 "TARGET_64BIT"
9ebbca7d
GK		 305 "@
306 extsb. %2,%1
307 #"
308 [(set_attr "type" "compare")
309 (set_attr "length" "4,8")])
310
311(define_split
312 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
313 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
314 (const_int 0)))
315 (clobber (match_scratch:DI 2 ""))]
316 "TARGET_POWERPC64 && reload_completed"
317 [(set (match_dup 2)
318 (sign_extend:DI (match_dup 1)))
319 (set (match_dup 0)
320 (compare:CC (match_dup 2)
321 (const_int 0)))]
322 "")
51b8fc2c
RK		 323
324(define_insn ""
9ebbca7d
GK		 325 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
326 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 327 (const_int 0)))
9ebbca7d 328 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 329 (sign_extend:DI (match_dup 1)))]
683bdff7 330 "TARGET_64BIT"
9ebbca7d
GK		 331 "@
332 extsb. %0,%1
333 #"
334 [(set_attr "type" "compare")
335 (set_attr "length" "4,8")])
336
337(define_split
338 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
339 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
340 (const_int 0)))
341 (set (match_operand:DI 0 "gpc_reg_operand" "")
342 (sign_extend:DI (match_dup 1)))]
343 "TARGET_POWERPC64 && reload_completed"
344 [(set (match_dup 0)
345 (sign_extend:DI (match_dup 1)))
346 (set (match_dup 2)
347 (compare:CC (match_dup 0)
348 (const_int 0)))]
349 "")
51b8fc2c 350
51b8fc2c
RK		 351(define_expand "extendhidi2"
352 [(set (match_operand:DI 0 "gpc_reg_operand" "")
353 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
354 "TARGET_POWERPC64"
355 "")
356
357(define_insn ""
358 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
359 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
360 "TARGET_POWERPC64"
361 "@
362 lha%U1%X1 %0,%1
363 extsh %0,%1"
44cd321e 364 [(set_attr "type" "load_ext,exts")])
51b8fc2c
RK		 365
366(define_insn ""
9ebbca7d
GK		 367 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
368 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 369 (const_int 0)))
9ebbca7d 370 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 371 "TARGET_64BIT"
9ebbca7d
GK		 372 "@
373 extsh. %2,%1
374 #"
375 [(set_attr "type" "compare")
376 (set_attr "length" "4,8")])
377
378(define_split
379 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
380 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
381 (const_int 0)))
382 (clobber (match_scratch:DI 2 ""))]
383 "TARGET_POWERPC64 && reload_completed"
384 [(set (match_dup 2)
385 (sign_extend:DI (match_dup 1)))
386 (set (match_dup 0)
387 (compare:CC (match_dup 2)
388 (const_int 0)))]
389 "")
51b8fc2c
RK		 390
391(define_insn ""
9ebbca7d
GK		 392 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
393 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 394 (const_int 0)))
9ebbca7d 395 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 396 (sign_extend:DI (match_dup 1)))]
683bdff7 397 "TARGET_64BIT"
9ebbca7d
GK		 398 "@
399 extsh. %0,%1
400 #"
401 [(set_attr "type" "compare")
402 (set_attr "length" "4,8")])
403
404(define_split
405 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
406 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
407 (const_int 0)))
408 (set (match_operand:DI 0 "gpc_reg_operand" "")
409 (sign_extend:DI (match_dup 1)))]
410 "TARGET_POWERPC64 && reload_completed"
411 [(set (match_dup 0)
412 (sign_extend:DI (match_dup 1)))
413 (set (match_dup 2)
414 (compare:CC (match_dup 0)
415 (const_int 0)))]
416 "")
51b8fc2c 417
51b8fc2c
RK		 418(define_expand "extendsidi2"
419 [(set (match_operand:DI 0 "gpc_reg_operand" "")
420 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
421 "TARGET_POWERPC64"
422 "")
423
424(define_insn ""
425 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
287f13ff 426 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
51b8fc2c
RK		 427 "TARGET_POWERPC64"
428 "@
429 lwa%U1%X1 %0,%1
430 extsw %0,%1"
44cd321e 431 [(set_attr "type" "load_ext,exts")])
51b8fc2c
RK		 432
433(define_insn ""
9ebbca7d
GK		 434 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
435 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 436 (const_int 0)))
9ebbca7d 437 (clobber (match_scratch:DI 2 "=r,r"))]
683bdff7 438 "TARGET_64BIT"
9ebbca7d
GK		 439 "@
440 extsw. %2,%1
441 #"
442 [(set_attr "type" "compare")
443 (set_attr "length" "4,8")])
444
445(define_split
446 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
447 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
448 (const_int 0)))
449 (clobber (match_scratch:DI 2 ""))]
450 "TARGET_POWERPC64 && reload_completed"
451 [(set (match_dup 2)
452 (sign_extend:DI (match_dup 1)))
453 (set (match_dup 0)
454 (compare:CC (match_dup 2)
455 (const_int 0)))]
456 "")
51b8fc2c
RK		 457
458(define_insn ""
9ebbca7d
GK		 459 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
460 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 461 (const_int 0)))
9ebbca7d 462 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
51b8fc2c 463 (sign_extend:DI (match_dup 1)))]
683bdff7 464 "TARGET_64BIT"
9ebbca7d
GK		 465 "@
466 extsw. %0,%1
467 #"
468 [(set_attr "type" "compare")
469 (set_attr "length" "4,8")])
470
471(define_split
472 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
473 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
474 (const_int 0)))
475 (set (match_operand:DI 0 "gpc_reg_operand" "")
476 (sign_extend:DI (match_dup 1)))]
477 "TARGET_POWERPC64 && reload_completed"
478 [(set (match_dup 0)
479 (sign_extend:DI (match_dup 1)))
480 (set (match_dup 2)
481 (compare:CC (match_dup 0)
482 (const_int 0)))]
483 "")
51b8fc2c 484
1fd4e8c1 485(define_expand "zero_extendqisi2"
cd2b37d9
RK		 486 [(set (match_operand:SI 0 "gpc_reg_operand" "")
487 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 488 ""
489 "")
490
491(define_insn ""
cd2b37d9 492 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 493 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
494 ""
495 "@
496 lbz%U1%X1 %0,%1
005a35b9 497 {rlinm|rlwinm} %0,%1,0,0xff"
1fd4e8c1
RK		 498 [(set_attr "type" "load,*")])
499
500(define_insn ""
9ebbca7d
GK		 501 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
502 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 503 (const_int 0)))
9ebbca7d 504 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 505 ""
9ebbca7d
GK		 506 "@
507 {andil.|andi.} %2,%1,0xff
508 #"
509 [(set_attr "type" "compare")
510 (set_attr "length" "4,8")])
511
512(define_split
513 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
514 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
515 (const_int 0)))
516 (clobber (match_scratch:SI 2 ""))]
517 "reload_completed"
518 [(set (match_dup 2)
519 (zero_extend:SI (match_dup 1)))
520 (set (match_dup 0)
521 (compare:CC (match_dup 2)
522 (const_int 0)))]
523 "")
1fd4e8c1
RK		 524
525(define_insn ""
9ebbca7d
GK		 526 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
527 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 528 (const_int 0)))
9ebbca7d 529 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 530 (zero_extend:SI (match_dup 1)))]
531 ""
9ebbca7d
GK		 532 "@
533 {andil.|andi.} %0,%1,0xff
534 #"
535 [(set_attr "type" "compare")
536 (set_attr "length" "4,8")])
537
538(define_split
539 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
540 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
541 (const_int 0)))
542 (set (match_operand:SI 0 "gpc_reg_operand" "")
543 (zero_extend:SI (match_dup 1)))]
544 "reload_completed"
545 [(set (match_dup 0)
546 (zero_extend:SI (match_dup 1)))
547 (set (match_dup 2)
548 (compare:CC (match_dup 0)
549 (const_int 0)))]
550 "")
1fd4e8c1 551
51b8fc2c
RK		 552(define_expand "extendqisi2"
553 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
554 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
555 ""
556 "
557{
558 if (TARGET_POWERPC)
559 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
560 else if (TARGET_POWER)
561 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
562 else
563 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
564 DONE;
565}")
566
567(define_insn "extendqisi2_ppc"
2bee0449
RK		 568 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
569 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
51b8fc2c 570 "TARGET_POWERPC"
44cd321e
PS		 571 "extsb %0,%1"
572 [(set_attr "type" "exts")])
51b8fc2c
RK		 573
574(define_insn ""
9ebbca7d
GK		 575 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
576 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 577 (const_int 0)))
9ebbca7d 578 (clobber (match_scratch:SI 2 "=r,r"))]
51b8fc2c 579 "TARGET_POWERPC"
9ebbca7d
GK		 580 "@
581 extsb. %2,%1
582 #"
583 [(set_attr "type" "compare")
584 (set_attr "length" "4,8")])
585
586(define_split
587 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
588 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
589 (const_int 0)))
590 (clobber (match_scratch:SI 2 ""))]
591 "TARGET_POWERPC && reload_completed"
592 [(set (match_dup 2)
593 (sign_extend:SI (match_dup 1)))
594 (set (match_dup 0)
595 (compare:CC (match_dup 2)
596 (const_int 0)))]
597 "")
51b8fc2c
RK		 598
599(define_insn ""
9ebbca7d
GK		 600 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
601 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 602 (const_int 0)))
9ebbca7d 603 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 604 (sign_extend:SI (match_dup 1)))]
605 "TARGET_POWERPC"
9ebbca7d
GK		 606 "@
607 extsb. %0,%1
608 #"
609 [(set_attr "type" "compare")
610 (set_attr "length" "4,8")])
611
612(define_split
613 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
614 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
615 (const_int 0)))
616 (set (match_operand:SI 0 "gpc_reg_operand" "")
617 (sign_extend:SI (match_dup 1)))]
618 "TARGET_POWERPC && reload_completed"
619 [(set (match_dup 0)
620 (sign_extend:SI (match_dup 1)))
621 (set (match_dup 2)
622 (compare:CC (match_dup 0)
623 (const_int 0)))]
624 "")
51b8fc2c
RK		 625
626(define_expand "extendqisi2_power"
627 [(parallel [(set (match_dup 2)
628 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
629 (const_int 24)))
630 (clobber (scratch:SI))])
631 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
632 (ashiftrt:SI (match_dup 2)
633 (const_int 24)))
634 (clobber (scratch:SI))])]
635 "TARGET_POWER"
636 "
637{ operands[1] = gen_lowpart (SImode, operands[1]);
638 operands[2] = gen_reg_rtx (SImode); }")
639
640(define_expand "extendqisi2_no_power"
641 [(set (match_dup 2)
642 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
643 (const_int 24)))
644 (set (match_operand:SI 0 "gpc_reg_operand" "")
645 (ashiftrt:SI (match_dup 2)
646 (const_int 24)))]
647 "! TARGET_POWER && ! TARGET_POWERPC"
648 "
649{ operands[1] = gen_lowpart (SImode, operands[1]);
650 operands[2] = gen_reg_rtx (SImode); }")
651
1fd4e8c1 652(define_expand "zero_extendqihi2"
cd2b37d9
RK		 653 [(set (match_operand:HI 0 "gpc_reg_operand" "")
654 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 655 ""
656 "")
657
658(define_insn ""
cd2b37d9 659 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 660 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
661 ""
662 "@
663 lbz%U1%X1 %0,%1
005a35b9 664 {rlinm|rlwinm} %0,%1,0,0xff"
51b8fc2c
RK		 665 [(set_attr "type" "load,*")])
666
667(define_insn ""
9ebbca7d
GK		 668 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
669 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 670 (const_int 0)))
9ebbca7d 671 (clobber (match_scratch:HI 2 "=r,r"))]
51b8fc2c 672 ""
9ebbca7d
GK		 673 "@
674 {andil.|andi.} %2,%1,0xff
675 #"
676 [(set_attr "type" "compare")
677 (set_attr "length" "4,8")])
678
679(define_split
680 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
681 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
682 (const_int 0)))
683 (clobber (match_scratch:HI 2 ""))]
684 "reload_completed"
685 [(set (match_dup 2)
686 (zero_extend:HI (match_dup 1)))
687 (set (match_dup 0)
688 (compare:CC (match_dup 2)
689 (const_int 0)))]
690 "")
1fd4e8c1 691
51b8fc2c 692(define_insn ""
9ebbca7d
GK		 693 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
694 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 695 (const_int 0)))
9ebbca7d 696 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 697 (zero_extend:HI (match_dup 1)))]
698 ""
9ebbca7d
GK		 699 "@
700 {andil.|andi.} %0,%1,0xff
701 #"
702 [(set_attr "type" "compare")
703 (set_attr "length" "4,8")])
704
705(define_split
706 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
707 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
708 (const_int 0)))
709 (set (match_operand:HI 0 "gpc_reg_operand" "")
710 (zero_extend:HI (match_dup 1)))]
711 "reload_completed"
712 [(set (match_dup 0)
713 (zero_extend:HI (match_dup 1)))
714 (set (match_dup 2)
715 (compare:CC (match_dup 0)
716 (const_int 0)))]
717 "")
815cdc52
MM		 718
719(define_expand "extendqihi2"
720 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
721 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
722 ""
723 "
724{
725 if (TARGET_POWERPC)
726 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
727 else if (TARGET_POWER)
728 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
729 else
730 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
731 DONE;
732}")
733
734(define_insn "extendqihi2_ppc"
735 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
736 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
737 "TARGET_POWERPC"
44cd321e
PS		 738 "extsb %0,%1"
739 [(set_attr "type" "exts")])
815cdc52
MM		 740
741(define_insn ""
9ebbca7d
GK		 742 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
743 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
815cdc52 744 (const_int 0)))
9ebbca7d 745 (clobber (match_scratch:HI 2 "=r,r"))]
815cdc52 746 "TARGET_POWERPC"
9ebbca7d
GK		 747 "@
748 extsb. %2,%1
749 #"
750 [(set_attr "type" "compare")
751 (set_attr "length" "4,8")])
752
753(define_split
754 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
755 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
756 (const_int 0)))
757 (clobber (match_scratch:HI 2 ""))]
758 "TARGET_POWERPC && reload_completed"
759 [(set (match_dup 2)
760 (sign_extend:HI (match_dup 1)))
761 (set (match_dup 0)
762 (compare:CC (match_dup 2)
763 (const_int 0)))]
764 "")
815cdc52
MM		 765
766(define_insn ""
9ebbca7d
GK		 767 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
768 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
51b8fc2c 769 (const_int 0)))
9ebbca7d 770 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
51b8fc2c
RK		 771 (sign_extend:HI (match_dup 1)))]
772 "TARGET_POWERPC"
9ebbca7d
GK		 773 "@
774 extsb. %0,%1
775 #"
776 [(set_attr "type" "compare")
777 (set_attr "length" "4,8")])
778
779(define_split
780 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
781 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
782 (const_int 0)))
783 (set (match_operand:HI 0 "gpc_reg_operand" "")
784 (sign_extend:HI (match_dup 1)))]
785 "TARGET_POWERPC && reload_completed"
786 [(set (match_dup 0)
787 (sign_extend:HI (match_dup 1)))
788 (set (match_dup 2)
789 (compare:CC (match_dup 0)
790 (const_int 0)))]
791 "")
51b8fc2c
RK		 792
793(define_expand "extendqihi2_power"
794 [(parallel [(set (match_dup 2)
795 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
796 (const_int 24)))
797 (clobber (scratch:SI))])
798 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
799 (ashiftrt:SI (match_dup 2)
800 (const_int 24)))
801 (clobber (scratch:SI))])]
802 "TARGET_POWER"
803 "
804{ operands[0] = gen_lowpart (SImode, operands[0]);
805 operands[1] = gen_lowpart (SImode, operands[1]);
806 operands[2] = gen_reg_rtx (SImode); }")
807
808(define_expand "extendqihi2_no_power"
809 [(set (match_dup 2)
810 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
811 (const_int 24)))
812 (set (match_operand:HI 0 "gpc_reg_operand" "")
813 (ashiftrt:SI (match_dup 2)
814 (const_int 24)))]
815 "! TARGET_POWER && ! TARGET_POWERPC"
816 "
817{ operands[0] = gen_lowpart (SImode, operands[0]);
818 operands[1] = gen_lowpart (SImode, operands[1]);
819 operands[2] = gen_reg_rtx (SImode); }")
820
1fd4e8c1 821(define_expand "zero_extendhisi2"
5f243543 822 [(set (match_operand:SI 0 "gpc_reg_operand" "")
cd2b37d9 823 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 824 ""
825 "")
826
827(define_insn ""
cd2b37d9 828 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 829 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
830 ""
831 "@
832 lhz%U1%X1 %0,%1
005a35b9 833 {rlinm|rlwinm} %0,%1,0,0xffff"
1fd4e8c1
RK		 834 [(set_attr "type" "load,*")])
835
836(define_insn ""
9ebbca7d
GK		 837 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
838 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 839 (const_int 0)))
9ebbca7d 840 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 841 ""
9ebbca7d
GK		 842 "@
843 {andil.|andi.} %2,%1,0xffff
844 #"
845 [(set_attr "type" "compare")
846 (set_attr "length" "4,8")])
847
848(define_split
849 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
850 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
851 (const_int 0)))
852 (clobber (match_scratch:SI 2 ""))]
853 "reload_completed"
854 [(set (match_dup 2)
855 (zero_extend:SI (match_dup 1)))
856 (set (match_dup 0)
857 (compare:CC (match_dup 2)
858 (const_int 0)))]
859 "")
1fd4e8c1
RK		 860
861(define_insn ""
9ebbca7d
GK		 862 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
863 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 864 (const_int 0)))
9ebbca7d 865 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 866 (zero_extend:SI (match_dup 1)))]
867 ""
9ebbca7d
GK		 868 "@
869 {andil.|andi.} %0,%1,0xffff
870 #"
871 [(set_attr "type" "compare")
872 (set_attr "length" "4,8")])
873
874(define_split
875 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
876 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
877 (const_int 0)))
878 (set (match_operand:SI 0 "gpc_reg_operand" "")
879 (zero_extend:SI (match_dup 1)))]
880 "reload_completed"
881 [(set (match_dup 0)
882 (zero_extend:SI (match_dup 1)))
883 (set (match_dup 2)
884 (compare:CC (match_dup 0)
885 (const_int 0)))]
886 "")
1fd4e8c1
RK		 887
888(define_expand "extendhisi2"
cd2b37d9
RK		 889 [(set (match_operand:SI 0 "gpc_reg_operand" "")
890 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1fd4e8c1
RK		 891 ""
892 "")
893
894(define_insn ""
cd2b37d9 895 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 896 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
897 ""
898 "@
899 lha%U1%X1 %0,%1
ca7f5001 900 {exts|extsh} %0,%1"
44cd321e 901 [(set_attr "type" "load_ext,exts")])
1fd4e8c1
RK		 902
903(define_insn ""
9ebbca7d
GK		 904 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
905 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 906 (const_int 0)))
9ebbca7d 907 (clobber (match_scratch:SI 2 "=r,r"))]
1fd4e8c1 908 ""
9ebbca7d
GK		 909 "@
910 {exts.|extsh.} %2,%1
911 #"
912 [(set_attr "type" "compare")
913 (set_attr "length" "4,8")])
914
915(define_split
916 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
917 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
918 (const_int 0)))
919 (clobber (match_scratch:SI 2 ""))]
920 "reload_completed"
921 [(set (match_dup 2)
922 (sign_extend:SI (match_dup 1)))
923 (set (match_dup 0)
924 (compare:CC (match_dup 2)
925 (const_int 0)))]
926 "")
1fd4e8c1
RK		 927
928(define_insn ""
9ebbca7d
GK		 929 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
930 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 931 (const_int 0)))
9ebbca7d 932 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 933 (sign_extend:SI (match_dup 1)))]
934 ""
9ebbca7d
GK		 935 "@
936 {exts.|extsh.} %0,%1
937 #"
938 [(set_attr "type" "compare")
939 (set_attr "length" "4,8")])
1fd4e8c1 940\f
4adf8008 941;; IBM 405, 440 and 464 half-word multiplication operations.
131aeb82
JM		 942
943(define_insn "*macchwc"
944 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
945 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
946 (match_operand:SI 2 "gpc_reg_operand" "r")
947 (const_int 16))
948 (sign_extend:SI
949 (match_operand:HI 1 "gpc_reg_operand" "r")))
950 (match_operand:SI 4 "gpc_reg_operand" "0"))
951 (const_int 0)))
952 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
953 (plus:SI (mult:SI (ashiftrt:SI
954 (match_dup 2)
955 (const_int 16))
956 (sign_extend:SI
957 (match_dup 1)))
958 (match_dup 4)))]
959 "TARGET_MULHW"
960 "macchw. %0, %1, %2"
961 [(set_attr "type" "imul3")])
962
963(define_insn "*macchw"
964 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
965 (plus:SI (mult:SI (ashiftrt:SI
966 (match_operand:SI 2 "gpc_reg_operand" "r")
967 (const_int 16))
968 (sign_extend:SI
969 (match_operand:HI 1 "gpc_reg_operand" "r")))
970 (match_operand:SI 3 "gpc_reg_operand" "0")))]
971 "TARGET_MULHW"
972 "macchw %0, %1, %2"
973 [(set_attr "type" "imul3")])
974
975(define_insn "*macchwuc"
976 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
977 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
978 (match_operand:SI 2 "gpc_reg_operand" "r")
979 (const_int 16))
980 (zero_extend:SI
981 (match_operand:HI 1 "gpc_reg_operand" "r")))
982 (match_operand:SI 4 "gpc_reg_operand" "0"))
983 (const_int 0)))
984 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
985 (plus:SI (mult:SI (lshiftrt:SI
986 (match_dup 2)
987 (const_int 16))
988 (zero_extend:SI
989 (match_dup 1)))
990 (match_dup 4)))]
991 "TARGET_MULHW"
992 "macchwu. %0, %1, %2"
993 [(set_attr "type" "imul3")])
994
995(define_insn "*macchwu"
996 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
997 (plus:SI (mult:SI (lshiftrt:SI
998 (match_operand:SI 2 "gpc_reg_operand" "r")
999 (const_int 16))
1000 (zero_extend:SI
1001 (match_operand:HI 1 "gpc_reg_operand" "r")))
1002 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1003 "TARGET_MULHW"
1004 "macchwu %0, %1, %2"
1005 [(set_attr "type" "imul3")])
1006
1007(define_insn "*machhwc"
1008 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1009 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1010 (match_operand:SI 1 "gpc_reg_operand" "%r")
1011 (const_int 16))
1012 (ashiftrt:SI
1013 (match_operand:SI 2 "gpc_reg_operand" "r")
1014 (const_int 16)))
1015 (match_operand:SI 4 "gpc_reg_operand" "0"))
1016 (const_int 0)))
1017 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1018 (plus:SI (mult:SI (ashiftrt:SI
1019 (match_dup 1)
1020 (const_int 16))
1021 (ashiftrt:SI
1022 (match_dup 2)
1023 (const_int 16)))
1024 (match_dup 4)))]
1025 "TARGET_MULHW"
1026 "machhw. %0, %1, %2"
1027 [(set_attr "type" "imul3")])
1028
1029(define_insn "*machhw"
1030 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1031 (plus:SI (mult:SI (ashiftrt:SI
1032 (match_operand:SI 1 "gpc_reg_operand" "%r")
1033 (const_int 16))
1034 (ashiftrt:SI
1035 (match_operand:SI 2 "gpc_reg_operand" "r")
1036 (const_int 16)))
1037 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1038 "TARGET_MULHW"
1039 "machhw %0, %1, %2"
1040 [(set_attr "type" "imul3")])
1041
1042(define_insn "*machhwuc"
1043 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1044 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1045 (match_operand:SI 1 "gpc_reg_operand" "%r")
1046 (const_int 16))
1047 (lshiftrt:SI
1048 (match_operand:SI 2 "gpc_reg_operand" "r")
1049 (const_int 16)))
1050 (match_operand:SI 4 "gpc_reg_operand" "0"))
1051 (const_int 0)))
1052 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1053 (plus:SI (mult:SI (lshiftrt:SI
1054 (match_dup 1)
1055 (const_int 16))
1056 (lshiftrt:SI
1057 (match_dup 2)
1058 (const_int 16)))
1059 (match_dup 4)))]
1060 "TARGET_MULHW"
1061 "machhwu. %0, %1, %2"
1062 [(set_attr "type" "imul3")])
1063
1064(define_insn "*machhwu"
1065 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1066 (plus:SI (mult:SI (lshiftrt:SI
1067 (match_operand:SI 1 "gpc_reg_operand" "%r")
1068 (const_int 16))
1069 (lshiftrt:SI
1070 (match_operand:SI 2 "gpc_reg_operand" "r")
1071 (const_int 16)))
1072 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1073 "TARGET_MULHW"
1074 "machhwu %0, %1, %2"
1075 [(set_attr "type" "imul3")])
1076
1077(define_insn "*maclhwc"
1078 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1079 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1080 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1081 (sign_extend:SI
1082 (match_operand:HI 2 "gpc_reg_operand" "r")))
1083 (match_operand:SI 4 "gpc_reg_operand" "0"))
1084 (const_int 0)))
1085 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1086 (plus:SI (mult:SI (sign_extend:SI
1087 (match_dup 1))
1088 (sign_extend:SI
1089 (match_dup 2)))
1090 (match_dup 4)))]
1091 "TARGET_MULHW"
1092 "maclhw. %0, %1, %2"
1093 [(set_attr "type" "imul3")])
1094
1095(define_insn "*maclhw"
1096 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1097 (plus:SI (mult:SI (sign_extend:SI
1098 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1099 (sign_extend:SI
1100 (match_operand:HI 2 "gpc_reg_operand" "r")))
1101 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1102 "TARGET_MULHW"
1103 "maclhw %0, %1, %2"
1104 [(set_attr "type" "imul3")])
1105
1106(define_insn "*maclhwuc"
1107 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1108 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1109 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1110 (zero_extend:SI
1111 (match_operand:HI 2 "gpc_reg_operand" "r")))
1112 (match_operand:SI 4 "gpc_reg_operand" "0"))
1113 (const_int 0)))
1114 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1115 (plus:SI (mult:SI (zero_extend:SI
1116 (match_dup 1))
1117 (zero_extend:SI
1118 (match_dup 2)))
1119 (match_dup 4)))]
1120 "TARGET_MULHW"
1121 "maclhwu. %0, %1, %2"
1122 [(set_attr "type" "imul3")])
1123
1124(define_insn "*maclhwu"
1125 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1126 (plus:SI (mult:SI (zero_extend:SI
1127 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1128 (zero_extend:SI
1129 (match_operand:HI 2 "gpc_reg_operand" "r")))
1130 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1131 "TARGET_MULHW"
1132 "maclhwu %0, %1, %2"
1133 [(set_attr "type" "imul3")])
1134
1135(define_insn "*nmacchwc"
1136 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1137 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1138 (mult:SI (ashiftrt:SI
1139 (match_operand:SI 2 "gpc_reg_operand" "r")
1140 (const_int 16))
1141 (sign_extend:SI
1142 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1143 (const_int 0)))
1144 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1145 (minus:SI (match_dup 4)
1146 (mult:SI (ashiftrt:SI
1147 (match_dup 2)
1148 (const_int 16))
1149 (sign_extend:SI
1150 (match_dup 1)))))]
1151 "TARGET_MULHW"
1152 "nmacchw. %0, %1, %2"
1153 [(set_attr "type" "imul3")])
1154
1155(define_insn "*nmacchw"
1156 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1157 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1158 (mult:SI (ashiftrt:SI
1159 (match_operand:SI 2 "gpc_reg_operand" "r")
1160 (const_int 16))
1161 (sign_extend:SI
1162 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1163 "TARGET_MULHW"
1164 "nmacchw %0, %1, %2"
1165 [(set_attr "type" "imul3")])
1166
1167(define_insn "*nmachhwc"
1168 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1169 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1170 (mult:SI (ashiftrt:SI
1171 (match_operand:SI 1 "gpc_reg_operand" "%r")
1172 (const_int 16))
1173 (ashiftrt:SI
1174 (match_operand:SI 2 "gpc_reg_operand" "r")
1175 (const_int 16))))
1176 (const_int 0)))
1177 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1178 (minus:SI (match_dup 4)
1179 (mult:SI (ashiftrt:SI
1180 (match_dup 1)
1181 (const_int 16))
1182 (ashiftrt:SI
1183 (match_dup 2)
1184 (const_int 16)))))]
1185 "TARGET_MULHW"
1186 "nmachhw. %0, %1, %2"
1187 [(set_attr "type" "imul3")])
1188
1189(define_insn "*nmachhw"
1190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1191 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1192 (mult:SI (ashiftrt:SI
1193 (match_operand:SI 1 "gpc_reg_operand" "%r")
1194 (const_int 16))
1195 (ashiftrt:SI
1196 (match_operand:SI 2 "gpc_reg_operand" "r")
1197 (const_int 16)))))]
1198 "TARGET_MULHW"
1199 "nmachhw %0, %1, %2"
1200 [(set_attr "type" "imul3")])
1201
1202(define_insn "*nmaclhwc"
1203 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1204 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1205 (mult:SI (sign_extend:SI
1206 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1207 (sign_extend:SI
1208 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1209 (const_int 0)))
1210 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1211 (minus:SI (match_dup 4)
1212 (mult:SI (sign_extend:SI
1213 (match_dup 1))
1214 (sign_extend:SI
1215 (match_dup 2)))))]
1216 "TARGET_MULHW"
1217 "nmaclhw. %0, %1, %2"
1218 [(set_attr "type" "imul3")])
1219
1220(define_insn "*nmaclhw"
1221 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1222 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1223 (mult:SI (sign_extend:SI
1224 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1225 (sign_extend:SI
1226 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1227 "TARGET_MULHW"
1228 "nmaclhw %0, %1, %2"
1229 [(set_attr "type" "imul3")])
1230
1231(define_insn "*mulchwc"
1232 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1233 (compare:CC (mult:SI (ashiftrt:SI
1234 (match_operand:SI 2 "gpc_reg_operand" "r")
1235 (const_int 16))
1236 (sign_extend:SI
1237 (match_operand:HI 1 "gpc_reg_operand" "r")))
1238 (const_int 0)))
1239 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1240 (mult:SI (ashiftrt:SI
1241 (match_dup 2)
1242 (const_int 16))
1243 (sign_extend:SI
1244 (match_dup 1))))]
1245 "TARGET_MULHW"
1246 "mulchw. %0, %1, %2"
1247 [(set_attr "type" "imul3")])
1248
1249(define_insn "*mulchw"
1250 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1251 (mult:SI (ashiftrt:SI
1252 (match_operand:SI 2 "gpc_reg_operand" "r")
1253 (const_int 16))
1254 (sign_extend:SI
1255 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1256 "TARGET_MULHW"
1257 "mulchw %0, %1, %2"
1258 [(set_attr "type" "imul3")])
1259
1260(define_insn "*mulchwuc"
1261 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1262 (compare:CC (mult:SI (lshiftrt:SI
1263 (match_operand:SI 2 "gpc_reg_operand" "r")
1264 (const_int 16))
1265 (zero_extend:SI
1266 (match_operand:HI 1 "gpc_reg_operand" "r")))
1267 (const_int 0)))
1268 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1269 (mult:SI (lshiftrt:SI
1270 (match_dup 2)
1271 (const_int 16))
1272 (zero_extend:SI
1273 (match_dup 1))))]
1274 "TARGET_MULHW"
1275 "mulchwu. %0, %1, %2"
1276 [(set_attr "type" "imul3")])
1277
1278(define_insn "*mulchwu"
1279 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1280 (mult:SI (lshiftrt:SI
1281 (match_operand:SI 2 "gpc_reg_operand" "r")
1282 (const_int 16))
1283 (zero_extend:SI
1284 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1285 "TARGET_MULHW"
1286 "mulchwu %0, %1, %2"
1287 [(set_attr "type" "imul3")])
1288
1289(define_insn "*mulhhwc"
1290 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1291 (compare:CC (mult:SI (ashiftrt:SI
1292 (match_operand:SI 1 "gpc_reg_operand" "%r")
1293 (const_int 16))
1294 (ashiftrt:SI
1295 (match_operand:SI 2 "gpc_reg_operand" "r")
1296 (const_int 16)))
1297 (const_int 0)))
1298 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1299 (mult:SI (ashiftrt:SI
1300 (match_dup 1)
1301 (const_int 16))
1302 (ashiftrt:SI
1303 (match_dup 2)
1304 (const_int 16))))]
1305 "TARGET_MULHW"
1306 "mulhhw. %0, %1, %2"
1307 [(set_attr "type" "imul3")])
1308
1309(define_insn "*mulhhw"
1310 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1311 (mult:SI (ashiftrt:SI
1312 (match_operand:SI 1 "gpc_reg_operand" "%r")
1313 (const_int 16))
1314 (ashiftrt:SI
1315 (match_operand:SI 2 "gpc_reg_operand" "r")
1316 (const_int 16))))]
1317 "TARGET_MULHW"
1318 "mulhhw %0, %1, %2"
1319 [(set_attr "type" "imul3")])
1320
1321(define_insn "*mulhhwuc"
1322 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1323 (compare:CC (mult:SI (lshiftrt:SI
1324 (match_operand:SI 1 "gpc_reg_operand" "%r")
1325 (const_int 16))
1326 (lshiftrt:SI
1327 (match_operand:SI 2 "gpc_reg_operand" "r")
1328 (const_int 16)))
1329 (const_int 0)))
1330 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1331 (mult:SI (lshiftrt:SI
1332 (match_dup 1)
1333 (const_int 16))
1334 (lshiftrt:SI
1335 (match_dup 2)
1336 (const_int 16))))]
1337 "TARGET_MULHW"
1338 "mulhhwu. %0, %1, %2"
1339 [(set_attr "type" "imul3")])
1340
1341(define_insn "*mulhhwu"
1342 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1343 (mult:SI (lshiftrt:SI
1344 (match_operand:SI 1 "gpc_reg_operand" "%r")
1345 (const_int 16))
1346 (lshiftrt:SI
1347 (match_operand:SI 2 "gpc_reg_operand" "r")
1348 (const_int 16))))]
1349 "TARGET_MULHW"
1350 "mulhhwu %0, %1, %2"
1351 [(set_attr "type" "imul3")])
1352
1353(define_insn "*mullhwc"
1354 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1355 (compare:CC (mult:SI (sign_extend:SI
1356 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1357 (sign_extend:SI
1358 (match_operand:HI 2 "gpc_reg_operand" "r")))
1359 (const_int 0)))
1360 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1361 (mult:SI (sign_extend:SI
1362 (match_dup 1))
1363 (sign_extend:SI
1364 (match_dup 2))))]
1365 "TARGET_MULHW"
1366 "mullhw. %0, %1, %2"
1367 [(set_attr "type" "imul3")])
1368
1369(define_insn "*mullhw"
1370 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1371 (mult:SI (sign_extend:SI
1372 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1373 (sign_extend:SI
1374 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1375 "TARGET_MULHW"
1376 "mullhw %0, %1, %2"
1377 [(set_attr "type" "imul3")])
1378
1379(define_insn "*mullhwuc"
1380 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1381 (compare:CC (mult:SI (zero_extend:SI
1382 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1383 (zero_extend:SI
1384 (match_operand:HI 2 "gpc_reg_operand" "r")))
1385 (const_int 0)))
1386 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1387 (mult:SI (zero_extend:SI
1388 (match_dup 1))
1389 (zero_extend:SI
1390 (match_dup 2))))]
1391 "TARGET_MULHW"
1392 "mullhwu. %0, %1, %2"
1393 [(set_attr "type" "imul3")])
1394
1395(define_insn "*mullhwu"
1396 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1397 (mult:SI (zero_extend:SI
1398 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1399 (zero_extend:SI
1400 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1401 "TARGET_MULHW"
1402 "mullhwu %0, %1, %2"
1403 [(set_attr "type" "imul3")])
1404\f
4adf8008 1405;; IBM 405, 440 and 464 string-search dlmzb instruction support.
716019c0
JM		 1406(define_insn "dlmzb"
1407 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1408 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1409 (match_operand:SI 2 "gpc_reg_operand" "r")]
1410 UNSPEC_DLMZB_CR))
1411 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1412 (unspec:SI [(match_dup 1)
1413 (match_dup 2)]
1414 UNSPEC_DLMZB))]
1415 "TARGET_DLMZB"
1416 "dlmzb. %0, %1, %2")
1417
1418(define_expand "strlensi"
1419 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1420 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1421 (match_operand:QI 2 "const_int_operand" "")
1422 (match_operand 3 "const_int_operand" "")]
1423 UNSPEC_DLMZB_STRLEN))
1424 (clobber (match_scratch:CC 4 "=x"))]
1425 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1426{
1427 rtx result = operands[0];
1428 rtx src = operands[1];
1429 rtx search_char = operands[2];
1430 rtx align = operands[3];
1431 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1432 rtx loop_label, end_label, mem, cr0, cond;
1433 if (search_char != const0_rtx
1434 || GET_CODE (align) != CONST_INT
1435 || INTVAL (align) < 8)
1436 FAIL;
1437 word1 = gen_reg_rtx (SImode);
1438 word2 = gen_reg_rtx (SImode);
1439 scratch_dlmzb = gen_reg_rtx (SImode);
1440 scratch_string = gen_reg_rtx (Pmode);
1441 loop_label = gen_label_rtx ();
1442 end_label = gen_label_rtx ();
1443 addr = force_reg (Pmode, XEXP (src, 0));
1444 emit_move_insn (scratch_string, addr);
1445 emit_label (loop_label);
1446 mem = change_address (src, SImode, scratch_string);
1447 emit_move_insn (word1, mem);
1448 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1449 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1450 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1451 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1452 emit_jump_insn (gen_rtx_SET (VOIDmode,
1453 pc_rtx,
1454 gen_rtx_IF_THEN_ELSE (VOIDmode,
1455 cond,
1456 gen_rtx_LABEL_REF
1457 (VOIDmode,
1458 end_label),
1459 pc_rtx)));
1460 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1461 emit_jump_insn (gen_rtx_SET (VOIDmode,
1462 pc_rtx,
1463 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
ea5bd0d8 1464 emit_barrier ();
716019c0
JM		 1465 emit_label (end_label);
1466 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1467 emit_insn (gen_subsi3 (result, scratch_string, addr));
1468 emit_insn (gen_subsi3 (result, result, const1_rtx));
1469 DONE;
1470})
1471\f
9ebbca7d
GK		 1472(define_split
1473 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1474 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1475 (const_int 0)))
1476 (set (match_operand:SI 0 "gpc_reg_operand" "")
1477 (sign_extend:SI (match_dup 1)))]
1478 "reload_completed"
1479 [(set (match_dup 0)
1480 (sign_extend:SI (match_dup 1)))
1481 (set (match_dup 2)
1482 (compare:CC (match_dup 0)
1483 (const_int 0)))]
1484 "")
1485
1fd4e8c1 1486;; Fixed-point arithmetic insns.
deb9225a 1487
0354e5d8
GK		 1488(define_expand "add<mode>3"
1489 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1490 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
4ae234b0 1491 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
7cd5235b 1492 ""
7cd5235b 1493{
0354e5d8
GK		 1494 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1495 {
1496 if (non_short_cint_operand (operands[2], DImode))
1497 FAIL;
1498 }
1499 else if (GET_CODE (operands[2]) == CONST_INT
1500 && ! add_operand (operands[2], <MODE>mode))
7cd5235b 1501 {
b3a13419
ILT		 1502 rtx tmp = ((!can_create_pseudo_p ()
1503 || rtx_equal_p (operands[0], operands[1]))
0354e5d8 1504 ? operands[0] : gen_reg_rtx (<MODE>mode));
7cd5235b 1505
2bfcf297 1506 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1507 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8
GK		 1508 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1509
279bb624 1510 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
0354e5d8 1511 FAIL;
7cd5235b 1512
9ebbca7d
GK		 1513 /* The ordering here is important for the prolog expander.
1514 When space is allocated from the stack, adding 'low' first may
1515 produce a temporary deallocation (which would be bad). */
0354e5d8
GK		 1516 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1517 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
7cd5235b
MM		 1518 DONE;
1519 }
279bb624 1520})
7cd5235b 1521
0354e5d8
GK		 1522;; Discourage ai/addic because of carry but provide it in an alternative
1523;; allowing register zero as source.
1524(define_insn "*add<mode>3_internal1"
1525 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1526 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1527 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
7393f7f8 1528 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1fd4e8c1 1529 "@
deb9225a
RK		 1530 {cax|add} %0,%1,%2
1531 {cal %0,%2(%1)|addi %0,%1,%2}
1532 {ai|addic} %0,%1,%2
7cd5235b
MM		 1533 {cau|addis} %0,%1,%v2"
1534 [(set_attr "length" "4,4,4,4")])
1fd4e8c1 1535
ee890fe2
SS		 1536(define_insn "addsi3_high"
1537 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1538 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1539 (high:SI (match_operand 2 "" ""))))]
1540 "TARGET_MACHO && !TARGET_64BIT"
1541 "{cau|addis} %0,%1,ha16(%2)"
1542 [(set_attr "length" "4")])
1543
0354e5d8 1544(define_insn "*add<mode>3_internal2"
cb8cc086 1545 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1546 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1547 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1548 (const_int 0)))
0354e5d8
GK		 1549 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1550 ""
deb9225a
RK		 1551 "@
1552 {cax.|add.} %3,%1,%2
cb8cc086
MM		 1553 {ai.|addic.} %3,%1,%2
1554 #
1555 #"
a62bfff2 1556 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1557 (set_attr "length" "4,4,8,8")])
1558
1559(define_split
1560 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1561 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1562 (match_operand:GPR 2 "reg_or_short_operand" ""))
cb8cc086 1563 (const_int 0)))
0354e5d8
GK		 1564 (clobber (match_scratch:GPR 3 ""))]
1565 "reload_completed"
cb8cc086 1566 [(set (match_dup 3)
0354e5d8 1567 (plus:GPR (match_dup 1)
cb8cc086
MM		 1568 (match_dup 2)))
1569 (set (match_dup 0)
1570 (compare:CC (match_dup 3)
1571 (const_int 0)))]
1572 "")
7e69e155 1573
0354e5d8 1574(define_insn "*add<mode>3_internal3"
cb8cc086 1575 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
0354e5d8
GK		 1576 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1577 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1fd4e8c1 1578 (const_int 0)))
0354e5d8
GK		 1579 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1580 (plus:P (match_dup 1)
1581 (match_dup 2)))]
1582 ""
deb9225a
RK		 1583 "@
1584 {cax.|add.} %0,%1,%2
cb8cc086
MM		 1585 {ai.|addic.} %0,%1,%2
1586 #
1587 #"
a62bfff2 1588 [(set_attr "type" "fast_compare,compare,compare,compare")
cb8cc086
MM		 1589 (set_attr "length" "4,4,8,8")])
1590
1591(define_split
1592 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1593 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1594 (match_operand:P 2 "reg_or_short_operand" ""))
cb8cc086 1595 (const_int 0)))
0354e5d8
GK		 1596 (set (match_operand:P 0 "gpc_reg_operand" "")
1597 (plus:P (match_dup 1) (match_dup 2)))]
1598 "reload_completed"
cb8cc086 1599 [(set (match_dup 0)
0354e5d8
GK		 1600 (plus:P (match_dup 1)
1601 (match_dup 2)))
cb8cc086
MM		 1602 (set (match_dup 3)
1603 (compare:CC (match_dup 0)
1604 (const_int 0)))]
1605 "")
7e69e155 1606
f357808b
RK		 1607;; Split an add that we can't do in one insn into two insns, each of which
1608;; does one 16-bit part. This is used by combine. Note that the low-order
1609;; add should be last in case the result gets used in an address.
1610
1611(define_split
0354e5d8
GK		 1612 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1613 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1614 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1fd4e8c1 1615 ""
0354e5d8
GK		 1616 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1617 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1fd4e8c1 1618{
2bfcf297 1619 HOST_WIDE_INT val = INTVAL (operands[2]);
a65c591c 1620 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
0354e5d8 1621 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1fd4e8c1 1622
e6ca2c17 1623 operands[4] = GEN_INT (low);
279bb624 1624 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
0354e5d8 1625 operands[3] = GEN_INT (rest);
b3a13419 1626 else if (can_create_pseudo_p ())
0354e5d8
GK		 1627 {
1628 operands[3] = gen_reg_rtx (DImode);
1629 emit_move_insn (operands[3], operands[2]);
1630 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1631 DONE;
1632 }
1633 else
1634 FAIL;
279bb624 1635})
1fd4e8c1 1636
0354e5d8
GK		 1637(define_insn "one_cmpl<mode>2"
1638 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1639 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1 1640 ""
ca7f5001
RK		 1641 "nor %0,%1,%1")
1642
1643(define_insn ""
52d3af72 1644 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 1645 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
ca7f5001 1646 (const_int 0)))
0354e5d8
GK		 1647 (clobber (match_scratch:P 2 "=r,r"))]
1648 ""
52d3af72
DE		 1649 "@
1650 nor. %2,%1,%1
1651 #"
1652 [(set_attr "type" "compare")
1653 (set_attr "length" "4,8")])
1654
1655(define_split
1656 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 1657 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1658 (const_int 0)))
0354e5d8
GK		 1659 (clobber (match_scratch:P 2 ""))]
1660 "reload_completed"
52d3af72 1661 [(set (match_dup 2)
0354e5d8 1662 (not:P (match_dup 1)))
52d3af72
DE		 1663 (set (match_dup 0)
1664 (compare:CC (match_dup 2)
1665 (const_int 0)))]
1666 "")
ca7f5001
RK		 1667
1668(define_insn ""
52d3af72 1669 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 1670 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 1671 (const_int 0)))
0354e5d8
GK		 1672 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1673 (not:P (match_dup 1)))]
1674 ""
52d3af72
DE		 1675 "@
1676 nor. %0,%1,%1
1677 #"
1678 [(set_attr "type" "compare")
1679 (set_attr "length" "4,8")])
1680
1681(define_split
1682 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 1683 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
52d3af72 1684 (const_int 0)))
0354e5d8
GK		 1685 (set (match_operand:P 0 "gpc_reg_operand" "")
1686 (not:P (match_dup 1)))]
1687 "reload_completed"
52d3af72 1688 [(set (match_dup 0)
0354e5d8 1689 (not:P (match_dup 1)))
52d3af72
DE		 1690 (set (match_dup 2)
1691 (compare:CC (match_dup 0)
1692 (const_int 0)))]
1693 "")
1fd4e8c1
RK		 1694
1695(define_insn ""
3d91674b
RK		 1696 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1697 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1698 (match_operand:SI 2 "gpc_reg_operand" "r")))]
deb9225a 1699 "! TARGET_POWERPC"
ca7f5001 1700 "{sf%I1|subf%I1c} %0,%2,%1")
1fd4e8c1 1701
deb9225a 1702(define_insn ""
0354e5d8
GK		 1703 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1704 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1705 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
deb9225a
RK		 1706 "TARGET_POWERPC"
1707 "@
1708 subf %0,%2,%1
1709 subfic %0,%2,%1")
1710
1fd4e8c1 1711(define_insn ""
cb8cc086
MM		 1712 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1713 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1714 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1715 (const_int 0)))
cb8cc086 1716 (clobber (match_scratch:SI 3 "=r,r"))]
deb9225a 1717 "! TARGET_POWERPC"
cb8cc086
MM		 1718 "@
1719 {sf.|subfc.} %3,%2,%1
1720 #"
1721 [(set_attr "type" "compare")
1722 (set_attr "length" "4,8")])
1fd4e8c1 1723
deb9225a 1724(define_insn ""
cb8cc086 1725 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1726 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1727 (match_operand:P 2 "gpc_reg_operand" "r,r"))
deb9225a 1728 (const_int 0)))
0354e5d8
GK		 1729 (clobber (match_scratch:P 3 "=r,r"))]
1730 "TARGET_POWERPC"
cb8cc086
MM		 1731 "@
1732 subf. %3,%2,%1
1733 #"
a62bfff2 1734 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1735 (set_attr "length" "4,8")])
1736
1737(define_split
1738 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1739 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1740 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1741 (const_int 0)))
0354e5d8
GK		 1742 (clobber (match_scratch:P 3 ""))]
1743 "reload_completed"
cb8cc086 1744 [(set (match_dup 3)
0354e5d8 1745 (minus:P (match_dup 1)
cb8cc086
MM		 1746 (match_dup 2)))
1747 (set (match_dup 0)
1748 (compare:CC (match_dup 3)
1749 (const_int 0)))]
1750 "")
deb9225a 1751
1fd4e8c1 1752(define_insn ""
cb8cc086
MM		 1753 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1754 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1755 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 1756 (const_int 0)))
cb8cc086 1757 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 1758 (minus:SI (match_dup 1) (match_dup 2)))]
deb9225a 1759 "! TARGET_POWERPC"
cb8cc086
MM		 1760 "@
1761 {sf.|subfc.} %0,%2,%1
1762 #"
1763 [(set_attr "type" "compare")
1764 (set_attr "length" "4,8")])
815cdc52 1765
29ae5b89 1766(define_insn ""
cb8cc086 1767 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
0354e5d8
GK		 1768 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1769 (match_operand:P 2 "gpc_reg_operand" "r,r"))
815cdc52 1770 (const_int 0)))
0354e5d8
GK		 1771 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1772 (minus:P (match_dup 1)
cb8cc086 1773 (match_dup 2)))]
0354e5d8 1774 "TARGET_POWERPC"
90612787
DE		 1775 "@
1776 subf. %0,%2,%1
1777 #"
a62bfff2 1778 [(set_attr "type" "fast_compare")
cb8cc086
MM		 1779 (set_attr "length" "4,8")])
1780
1781(define_split
1782 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
0354e5d8
GK		 1783 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1784 (match_operand:P 2 "gpc_reg_operand" ""))
cb8cc086 1785 (const_int 0)))
0354e5d8
GK		 1786 (set (match_operand:P 0 "gpc_reg_operand" "")
1787 (minus:P (match_dup 1)
cb8cc086 1788 (match_dup 2)))]
0354e5d8 1789 "reload_completed"
cb8cc086 1790 [(set (match_dup 0)
0354e5d8 1791 (minus:P (match_dup 1)
cb8cc086
MM		 1792 (match_dup 2)))
1793 (set (match_dup 3)
1794 (compare:CC (match_dup 0)
1795 (const_int 0)))]
1796 "")
deb9225a 1797
0354e5d8
GK		 1798(define_expand "sub<mode>3"
1799 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1800 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
4ae234b0 1801 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1fd4e8c1 1802 ""
a0044fb1
RK		 1803 "
1804{
1805 if (GET_CODE (operands[2]) == CONST_INT)
1806 {
0354e5d8
GK		 1807 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1808 negate_rtx (<MODE>mode, operands[2])));
a0044fb1
RK		 1809 DONE;
1810 }
1811}")
1fd4e8c1
RK		 1812
1813;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1814;; instruction and some auxiliary computations. Then we just have a single
95ac8e67
RK		 1815;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1816;; combine.
1fd4e8c1
RK		 1817
1818(define_expand "sminsi3"
1819 [(set (match_dup 3)
cd2b37d9 1820 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1821 (match_operand:SI 2 "reg_or_short_operand" ""))
1822 (const_int 0)
1823 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1824 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1825 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1826 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1827 "
a3170dc6
AH		 1828{
1829 if (TARGET_ISEL)
1830 {
1831 operands[2] = force_reg (SImode, operands[2]);
1832 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1833 DONE;
1834 }
1835
1836 operands[3] = gen_reg_rtx (SImode);
1837}")
1fd4e8c1 1838
95ac8e67
RK		 1839(define_split
1840 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1841 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1842 (match_operand:SI 2 "reg_or_short_operand" "")))
1843 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1844 "TARGET_POWER"
95ac8e67
RK		 1845 [(set (match_dup 3)
1846 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1847 (const_int 0)
1848 (minus:SI (match_dup 2) (match_dup 1))))
1849 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1850 "")
1851
1fd4e8c1
RK		 1852(define_expand "smaxsi3"
1853 [(set (match_dup 3)
cd2b37d9 1854 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1
RK		 1855 (match_operand:SI 2 "reg_or_short_operand" ""))
1856 (const_int 0)
1857 (minus:SI (match_dup 2) (match_dup 1))))
cd2b37d9 1858 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1859 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1860 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1861 "
a3170dc6
AH		 1862{
1863 if (TARGET_ISEL)
1864 {
1865 operands[2] = force_reg (SImode, operands[2]);
1866 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1867 DONE;
1868 }
1869 operands[3] = gen_reg_rtx (SImode);
1870}")
1fd4e8c1 1871
95ac8e67
RK		 1872(define_split
1873 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1874 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1875 (match_operand:SI 2 "reg_or_short_operand" "")))
1876 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
ca7f5001 1877 "TARGET_POWER"
95ac8e67
RK		 1878 [(set (match_dup 3)
1879 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1880 (const_int 0)
1881 (minus:SI (match_dup 2) (match_dup 1))))
1882 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1883 "")
1884
1fd4e8c1 1885(define_expand "uminsi3"
cd2b37d9 1886 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1887 (match_dup 5)))
cd2b37d9 1888 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1889 (match_dup 5)))
1fd4e8c1
RK		 1890 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1891 (const_int 0)
1892 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1893 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1894 (minus:SI (match_dup 2) (match_dup 3)))]
a3170dc6 1895 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1896 "
bb68ff55 1897{
a3170dc6
AH		 1898 if (TARGET_ISEL)
1899 {
1900 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1901 DONE;
1902 }
bb68ff55
MM		 1903 operands[3] = gen_reg_rtx (SImode);
1904 operands[4] = gen_reg_rtx (SImode);
1905 operands[5] = GEN_INT (-2147483647 - 1);
1906}")
1fd4e8c1
RK		 1907
1908(define_expand "umaxsi3"
cd2b37d9 1909 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
bb68ff55 1910 (match_dup 5)))
cd2b37d9 1911 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
bb68ff55 1912 (match_dup 5)))
1fd4e8c1
RK		 1913 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1914 (const_int 0)
1915 (minus:SI (match_dup 4) (match_dup 3))))
cd2b37d9 1916 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1 1917 (plus:SI (match_dup 3) (match_dup 1)))]
a3170dc6 1918 "TARGET_POWER || TARGET_ISEL"
1fd4e8c1 1919 "
bb68ff55 1920{
a3170dc6
AH		 1921 if (TARGET_ISEL)
1922 {
1923 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1924 DONE;
1925 }
bb68ff55
MM		 1926 operands[3] = gen_reg_rtx (SImode);
1927 operands[4] = gen_reg_rtx (SImode);
1928 operands[5] = GEN_INT (-2147483647 - 1);
1929}")
1fd4e8c1
RK		 1930
1931(define_insn ""
cd2b37d9
RK		 1932 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1933 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
5c23c401 1934 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1fd4e8c1
RK		 1935 (const_int 0)
1936 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1937 "TARGET_POWER"
1fd4e8c1
RK		 1938 "doz%I2 %0,%1,%2")
1939
1940(define_insn ""
9ebbca7d 1941 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 1942 (compare:CC
9ebbca7d
GK		 1943 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1944 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1945 (const_int 0)
1946 (minus:SI (match_dup 2) (match_dup 1)))
1947 (const_int 0)))
9ebbca7d 1948 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 1949 "TARGET_POWER"
9ebbca7d
GK		 1950 "@
1951 doz%I2. %3,%1,%2
1952 #"
1953 [(set_attr "type" "delayed_compare")
1954 (set_attr "length" "4,8")])
1955
1956(define_split
1957 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1958 (compare:CC
1959 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1960 (match_operand:SI 2 "reg_or_short_operand" ""))
1961 (const_int 0)
1962 (minus:SI (match_dup 2) (match_dup 1)))
1963 (const_int 0)))
1964 (clobber (match_scratch:SI 3 ""))]
1965 "TARGET_POWER && reload_completed"
1966 [(set (match_dup 3)
1967 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1968 (const_int 0)
1969 (minus:SI (match_dup 2) (match_dup 1))))
1970 (set (match_dup 0)
1971 (compare:CC (match_dup 3)
1972 (const_int 0)))]
1973 "")
1fd4e8c1
RK		 1974
1975(define_insn ""
9ebbca7d 1976 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 1977 (compare:CC
9ebbca7d
GK		 1978 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1979 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1
RK		 1980 (const_int 0)
1981 (minus:SI (match_dup 2) (match_dup 1)))
1982 (const_int 0)))
9ebbca7d 1983 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 1984 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1985 (const_int 0)
1986 (minus:SI (match_dup 2) (match_dup 1))))]
ca7f5001 1987 "TARGET_POWER"
9ebbca7d
GK		 1988 "@
1989 doz%I2. %0,%1,%2
1990 #"
1991 [(set_attr "type" "delayed_compare")
1992 (set_attr "length" "4,8")])
1993
1994(define_split
1995 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1996 (compare:CC
1997 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1998 (match_operand:SI 2 "reg_or_short_operand" ""))
1999 (const_int 0)
2000 (minus:SI (match_dup 2) (match_dup 1)))
2001 (const_int 0)))
2002 (set (match_operand:SI 0 "gpc_reg_operand" "")
2003 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2004 (const_int 0)
2005 (minus:SI (match_dup 2) (match_dup 1))))]
2006 "TARGET_POWER && reload_completed"
2007 [(set (match_dup 0)
2008 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2009 (const_int 0)
2010 (minus:SI (match_dup 2) (match_dup 1))))
2011 (set (match_dup 3)
2012 (compare:CC (match_dup 0)
2013 (const_int 0)))]
2014 "")
1fd4e8c1
RK		 2015
2016;; We don't need abs with condition code because such comparisons should
2017;; never be done.
ea9be077
MM		 2018(define_expand "abssi2"
2019 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2020 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2021 ""
2022 "
2023{
a3170dc6
AH		 2024 if (TARGET_ISEL)
2025 {
2026 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2027 DONE;
2028 }
2029 else if (! TARGET_POWER)
ea9be077
MM		 2030 {
2031 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2032 DONE;
2033 }
2034}")
2035
ea112fc4 2036(define_insn "*abssi2_power"
cd2b37d9
RK		 2037 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2038 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
ca7f5001 2039 "TARGET_POWER"
1fd4e8c1
RK		 2040 "abs %0,%1")
2041
a3170dc6
AH		 2042(define_insn_and_split "abssi2_isel"
2043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2044 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8c48b6f5 2045 (clobber (match_scratch:SI 2 "=&b"))
a3170dc6
AH		 2046 (clobber (match_scratch:CC 3 "=y"))]
2047 "TARGET_ISEL"
2048 "#"
2049 "&& reload_completed"
2050 [(set (match_dup 2) (neg:SI (match_dup 1)))
2051 (set (match_dup 3)
2052 (compare:CC (match_dup 1)
2053 (const_int 0)))
2054 (set (match_dup 0)
2055 (if_then_else:SI (ge (match_dup 3)
2056 (const_int 0))
2057 (match_dup 1)
2058 (match_dup 2)))]
2059 "")
2060
ea112fc4 2061(define_insn_and_split "abssi2_nopower"
ea9be077 2062 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2063 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
ea9be077 2064 (clobber (match_scratch:SI 2 "=&r,&r"))]
a3170dc6 2065 "! TARGET_POWER && ! TARGET_ISEL"
ea112fc4
DE		 2066 "#"
2067 "&& reload_completed"
ea9be077
MM		 2068 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2069 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2070 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
ea9be077
MM		 2071 "")
2072
463b558b 2073(define_insn "*nabs_power"
cd2b37d9
RK		 2074 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2075 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
ca7f5001 2076 "TARGET_POWER"
1fd4e8c1
RK		 2077 "nabs %0,%1")
2078
ea112fc4 2079(define_insn_and_split "*nabs_nopower"
ea9be077 2080 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 2081 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
ea9be077 2082 (clobber (match_scratch:SI 2 "=&r,&r"))]
0ad91047 2083 "! TARGET_POWER"
ea112fc4
DE		 2084 "#"
2085 "&& reload_completed"
ea9be077
MM		 2086 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2087 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
7093ddee 2088 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
ea9be077
MM		 2089 "")
2090
0354e5d8
GK		 2091(define_expand "neg<mode>2"
2092 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2093 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2094 ""
2095 "")
2096
2097(define_insn "*neg<mode>2_internal"
2098 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2099 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1fd4e8c1
RK		 2100 ""
2101 "neg %0,%1")
2102
2103(define_insn ""
9ebbca7d 2104 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
0354e5d8 2105 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1fd4e8c1 2106 (const_int 0)))
0354e5d8
GK		 2107 (clobber (match_scratch:P 2 "=r,r"))]
2108 ""
9ebbca7d
GK		 2109 "@
2110 neg. %2,%1
2111 #"
a62bfff2 2112 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2113 (set_attr "length" "4,8")])
2114
2115(define_split
2116 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
0354e5d8 2117 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2118 (const_int 0)))
0354e5d8
GK		 2119 (clobber (match_scratch:P 2 ""))]
2120 "reload_completed"
9ebbca7d 2121 [(set (match_dup 2)
0354e5d8 2122 (neg:P (match_dup 1)))
9ebbca7d
GK		 2123 (set (match_dup 0)
2124 (compare:CC (match_dup 2)
2125 (const_int 0)))]
2126 "")
1fd4e8c1
RK		 2127
2128(define_insn ""
9ebbca7d 2129 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
0354e5d8 2130 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
815cdc52 2131 (const_int 0)))
0354e5d8
GK		 2132 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2133 (neg:P (match_dup 1)))]
2134 ""
9ebbca7d
GK		 2135 "@
2136 neg. %0,%1
2137 #"
a62bfff2 2138 [(set_attr "type" "fast_compare")
9ebbca7d
GK		 2139 (set_attr "length" "4,8")])
2140
2141(define_split
2142 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
0354e5d8 2143 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
9ebbca7d 2144 (const_int 0)))
0354e5d8
GK		 2145 (set (match_operand:P 0 "gpc_reg_operand" "")
2146 (neg:P (match_dup 1)))]
66859ace 2147 "reload_completed"
9ebbca7d 2148 [(set (match_dup 0)
0354e5d8 2149 (neg:P (match_dup 1)))
9ebbca7d
GK		 2150 (set (match_dup 2)
2151 (compare:CC (match_dup 0)
2152 (const_int 0)))]
2153 "")
1fd4e8c1 2154
0354e5d8
GK		 2155(define_insn "clz<mode>2"
2156 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2157 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1b1edcfa 2158 ""
44cd321e
PS		 2159 "{cntlz|cntlz<wd>} %0,%1"
2160 [(set_attr "type" "cntlz")])
1b1edcfa 2161
0354e5d8 2162(define_expand "ctz<mode>2"
4977bab6 2163 [(set (match_dup 2)
e42ac3de 2164 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2165 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2166 (match_dup 2)))
1b1edcfa 2167 (clobber (scratch:CC))])
0354e5d8 2168 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2169 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2170 (minus:GPR (match_dup 5) (match_dup 4)))]
1fd4e8c1 2171 ""
4977bab6 2172 {
0354e5d8
GK		 2173 operands[2] = gen_reg_rtx (<MODE>mode);
2174 operands[3] = gen_reg_rtx (<MODE>mode);
2175 operands[4] = gen_reg_rtx (<MODE>mode);
2176 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
4977bab6 2177 })
6ae08853 2178
0354e5d8 2179(define_expand "ffs<mode>2"
1b1edcfa 2180 [(set (match_dup 2)
e42ac3de 2181 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
0354e5d8
GK		 2182 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2183 (match_dup 2)))
1b1edcfa 2184 (clobber (scratch:CC))])
0354e5d8 2185 (set (match_dup 4) (clz:GPR (match_dup 3)))
e42ac3de 2186 (set (match_operand:GPR 0 "gpc_reg_operand" "")
0354e5d8 2187 (minus:GPR (match_dup 5) (match_dup 4)))]
4977bab6 2188 ""
1b1edcfa 2189 {
0354e5d8
GK		 2190 operands[2] = gen_reg_rtx (<MODE>mode);
2191 operands[3] = gen_reg_rtx (<MODE>mode);
2192 operands[4] = gen_reg_rtx (<MODE>mode);
2193 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
1b1edcfa 2194 })
6ae08853 2195
432218ba
DE		 2196(define_insn "popcntb<mode>2"
2197 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2198 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2199 UNSPEC_POPCNTB))]
2200 "TARGET_POPCNTB"
2201 "popcntb %0,%1")
2202
565ef4ba 2203(define_expand "popcount<mode>2"
e42ac3de
RS		 2204 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2205 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
565ef4ba
RS		 2206 "TARGET_POPCNTB"
2207 {
2208 rs6000_emit_popcount (operands[0], operands[1]);
2209 DONE;
2210 })
2211
2212(define_expand "parity<mode>2"
e42ac3de
RS		 2213 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2214 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
565ef4ba
RS		 2215 "TARGET_POPCNTB"
2216 {
2217 rs6000_emit_parity (operands[0], operands[1]);
2218 DONE;
2219 })
2220
03f79051
DE		 2221(define_insn "bswapsi2"
2222 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2223 (bswap:SI (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2224 ""
2225 "@
2226 {lbrx|lwbrx} %0,%y1
2227 {stbrx|stwbrx} %1,%y0
2228 #"
2229 [(set_attr "length" "4,4,12")])
2230
2231(define_split
2232 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2233 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2234 "reload_completed"
2235 [(set (match_dup 0)
2236 (rotate:SI (match_dup 1) (const_int 8)))
2237 (set (zero_extract:SI (match_dup 0)
2238 (const_int 8)
2239 (const_int 0))
2240 (match_dup 1))
2241 (set (zero_extract:SI (match_dup 0)
2242 (const_int 8)
2243 (const_int 16))
2244 (rotate:SI (match_dup 1)
2245 (const_int 16)))]
2246 "")
2247
ca7f5001
RK		 2248(define_expand "mulsi3"
2249 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2250 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2251 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2252 ""
2253 "
2254{
2255 if (TARGET_POWER)
68b40e7e 2256 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
ca7f5001 2257 else
68b40e7e 2258 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
ca7f5001
RK		 2259 DONE;
2260}")
2261
68b40e7e 2262(define_insn "mulsi3_mq"
cd2b37d9
RK		 2263 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2264 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1fd4e8c1
RK		 2265 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2266 (clobber (match_scratch:SI 3 "=q,q"))]
ca7f5001
RK		 2267 "TARGET_POWER"
2268 "@
2269 {muls|mullw} %0,%1,%2
2270 {muli|mulli} %0,%1,%2"
6ae08853 2271 [(set (attr "type")
c859cda6
DJ		 2272 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2273 (const_string "imul3")
6ae08853 2274 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2275 (const_string "imul2")]
2276 (const_string "imul")))])
ca7f5001 2277
68b40e7e 2278(define_insn "mulsi3_no_mq"
ca7f5001
RK		 2279 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2280 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2281 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
68b40e7e 2282 "! TARGET_POWER"
1fd4e8c1 2283 "@
d904e9ed
RK		 2284 {muls|mullw} %0,%1,%2
2285 {muli|mulli} %0,%1,%2"
6ae08853 2286 [(set (attr "type")
c859cda6
DJ		 2287 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2288 (const_string "imul3")
6ae08853 2289 (match_operand:SI 2 "short_cint_operand" "")
c859cda6
DJ		 2290 (const_string "imul2")]
2291 (const_string "imul")))])
1fd4e8c1 2292
9259f3b0 2293(define_insn "*mulsi3_mq_internal1"
9ebbca7d
GK		 2294 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2295 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2296 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2297 (const_int 0)))
9ebbca7d
GK		 2298 (clobber (match_scratch:SI 3 "=r,r"))
2299 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2300 "TARGET_POWER"
9ebbca7d
GK		 2301 "@
2302 {muls.|mullw.} %3,%1,%2
2303 #"
9259f3b0 2304 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2305 (set_attr "length" "4,8")])
2306
2307(define_split
2308 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2309 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2310 (match_operand:SI 2 "gpc_reg_operand" ""))
2311 (const_int 0)))
2312 (clobber (match_scratch:SI 3 ""))
2313 (clobber (match_scratch:SI 4 ""))]
2314 "TARGET_POWER && reload_completed"
2315 [(parallel [(set (match_dup 3)
2316 (mult:SI (match_dup 1) (match_dup 2)))
2317 (clobber (match_dup 4))])
2318 (set (match_dup 0)
2319 (compare:CC (match_dup 3)
2320 (const_int 0)))]
2321 "")
ca7f5001 2322
9259f3b0 2323(define_insn "*mulsi3_no_mq_internal1"
9ebbca7d
GK		 2324 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2325 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2326 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2327 (const_int 0)))
9ebbca7d 2328 (clobber (match_scratch:SI 3 "=r,r"))]
25c341fa 2329 "! TARGET_POWER"
9ebbca7d
GK		 2330 "@
2331 {muls.|mullw.} %3,%1,%2
2332 #"
9259f3b0 2333 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2334 (set_attr "length" "4,8")])
2335
2336(define_split
2337 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2338 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2339 (match_operand:SI 2 "gpc_reg_operand" ""))
2340 (const_int 0)))
2341 (clobber (match_scratch:SI 3 ""))]
2342 "! TARGET_POWER && reload_completed"
2343 [(set (match_dup 3)
2344 (mult:SI (match_dup 1) (match_dup 2)))
2345 (set (match_dup 0)
2346 (compare:CC (match_dup 3)
2347 (const_int 0)))]
2348 "")
1fd4e8c1 2349
9259f3b0 2350(define_insn "*mulsi3_mq_internal2"
9ebbca7d
GK		 2351 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2352 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2353 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 2354 (const_int 0)))
9ebbca7d 2355 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
29ae5b89 2356 (mult:SI (match_dup 1) (match_dup 2)))
9ebbca7d 2357 (clobber (match_scratch:SI 4 "=q,q"))]
ca7f5001 2358 "TARGET_POWER"
9ebbca7d
GK		 2359 "@
2360 {muls.|mullw.} %0,%1,%2
2361 #"
9259f3b0 2362 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2363 (set_attr "length" "4,8")])
2364
2365(define_split
2366 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2367 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2368 (match_operand:SI 2 "gpc_reg_operand" ""))
2369 (const_int 0)))
2370 (set (match_operand:SI 0 "gpc_reg_operand" "")
2371 (mult:SI (match_dup 1) (match_dup 2)))
2372 (clobber (match_scratch:SI 4 ""))]
2373 "TARGET_POWER && reload_completed"
2374 [(parallel [(set (match_dup 0)
2375 (mult:SI (match_dup 1) (match_dup 2)))
2376 (clobber (match_dup 4))])
2377 (set (match_dup 3)
2378 (compare:CC (match_dup 0)
2379 (const_int 0)))]
2380 "")
ca7f5001 2381
9259f3b0 2382(define_insn "*mulsi3_no_mq_internal2"
9ebbca7d
GK		 2383 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2384 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2385 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
ca7f5001 2386 (const_int 0)))
9ebbca7d 2387 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
ca7f5001 2388 (mult:SI (match_dup 1) (match_dup 2)))]
25c341fa 2389 "! TARGET_POWER"
9ebbca7d
GK		 2390 "@
2391 {muls.|mullw.} %0,%1,%2
2392 #"
9259f3b0 2393 [(set_attr "type" "imul_compare")
9ebbca7d
GK		 2394 (set_attr "length" "4,8")])
2395
2396(define_split
2397 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2398 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2399 (match_operand:SI 2 "gpc_reg_operand" ""))
2400 (const_int 0)))
2401 (set (match_operand:SI 0 "gpc_reg_operand" "")
2402 (mult:SI (match_dup 1) (match_dup 2)))]
2403 "! TARGET_POWER && reload_completed"
2404 [(set (match_dup 0)
2405 (mult:SI (match_dup 1) (match_dup 2)))
2406 (set (match_dup 3)
2407 (compare:CC (match_dup 0)
2408 (const_int 0)))]
2409 "")
1fd4e8c1
RK		 2410
2411;; Operand 1 is divided by operand 2; quotient goes to operand
2412;; 0 and remainder to operand 3.
2413;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2414
8ffd9c51
RK		 2415(define_expand "divmodsi4"
2416 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2417 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2418 (match_operand:SI 2 "gpc_reg_operand" "")))
bb157ff4 2419 (set (match_operand:SI 3 "register_operand" "")
8ffd9c51
RK		 2420 (mod:SI (match_dup 1) (match_dup 2)))])]
2421 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2422 "
2423{
2424 if (! TARGET_POWER && ! TARGET_POWERPC)
2425 {
39403d82
DE		 2426 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2427 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2428 emit_insn (gen_divss_call ());
39403d82
DE		 2429 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2430 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
8ffd9c51
RK		 2431 DONE;
2432 }
2433}")
deb9225a 2434
bb157ff4 2435(define_insn "*divmodsi4_internal"
cd2b37d9
RK		 2436 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2437 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2438 (match_operand:SI 2 "gpc_reg_operand" "r")))
bb157ff4 2439 (set (match_operand:SI 3 "register_operand" "=q")
1fd4e8c1 2440 (mod:SI (match_dup 1) (match_dup 2)))]
ca7f5001 2441 "TARGET_POWER"
cfb557c4
RK		 2442 "divs %0,%1,%2"
2443 [(set_attr "type" "idiv")])
1fd4e8c1 2444
4ae234b0
GK		 2445(define_expand "udiv<mode>3"
2446 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2447 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2448 (match_operand:GPR 2 "gpc_reg_operand" "")))]
8ffd9c51
RK		 2449 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2450 "
2451{
2452 if (! TARGET_POWER && ! TARGET_POWERPC)
2453 {
39403d82
DE		 2454 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2455 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2456 emit_insn (gen_quous_call ());
39403d82 2457 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2458 DONE;
2459 }
f192bf8b
DE		 2460 else if (TARGET_POWER)
2461 {
2462 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2463 DONE;
2464 }
8ffd9c51 2465}")
deb9225a 2466
f192bf8b
DE		 2467(define_insn "udivsi3_mq"
2468 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2469 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2470 (match_operand:SI 2 "gpc_reg_operand" "r")))
2471 (clobber (match_scratch:SI 3 "=q"))]
2472 "TARGET_POWERPC && TARGET_POWER"
2473 "divwu %0,%1,%2"
2474 [(set_attr "type" "idiv")])
2475
2476(define_insn "*udivsi3_no_mq"
4ae234b0
GK		 2477 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2478 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2479 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2480 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2481 "div<wd>u %0,%1,%2"
44cd321e
PS		 2482 [(set (attr "type")
2483 (cond [(match_operand:SI 0 "" "")
2484 (const_string "idiv")]
2485 (const_string "ldiv")))])
2486
ca7f5001 2487
1fd4e8c1 2488;; For powers of two we can do srai/aze for divide and then adjust for
ca7f5001 2489;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
8ffd9c51
RK		 2490;; used; for PowerPC, force operands into register and do a normal divide;
2491;; for AIX common-mode, use quoss call on register operands.
4ae234b0
GK		 2492(define_expand "div<mode>3"
2493 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2494 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2495 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
1fd4e8c1
RK		 2496 ""
2497 "
2498{
ca7f5001 2499 if (GET_CODE (operands[2]) == CONST_INT
2bfcf297 2500 && INTVAL (operands[2]) > 0
ca7f5001
RK		 2501 && exact_log2 (INTVAL (operands[2])) >= 0)
2502 ;
b6c9286a 2503 else if (TARGET_POWERPC)
f192bf8b 2504 {
99e8e649 2505 operands[2] = force_reg (<MODE>mode, operands[2]);
f192bf8b
DE		 2506 if (TARGET_POWER)
2507 {
2508 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2509 DONE;
2510 }
2511 }
b6c9286a 2512 else if (TARGET_POWER)
1fd4e8c1 2513 FAIL;
405c5495 2514 else
8ffd9c51 2515 {
39403d82
DE		 2516 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2517 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 2518 emit_insn (gen_quoss_call ());
39403d82 2519 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 2520 DONE;
2521 }
1fd4e8c1
RK		 2522}")
2523
f192bf8b
DE		 2524(define_insn "divsi3_mq"
2525 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2526 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2527 (match_operand:SI 2 "gpc_reg_operand" "r")))
2528 (clobber (match_scratch:SI 3 "=q"))]
2529 "TARGET_POWERPC && TARGET_POWER"
2530 "divw %0,%1,%2"
2531 [(set_attr "type" "idiv")])
2532
4ae234b0
GK		 2533(define_insn "*div<mode>3_no_mq"
2534 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2535 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2536 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
f192bf8b 2537 "TARGET_POWERPC && ! TARGET_POWER"
4ae234b0 2538 "div<wd> %0,%1,%2"
44cd321e
PS		 2539 [(set (attr "type")
2540 (cond [(match_operand:SI 0 "" "")
2541 (const_string "idiv")]
2542 (const_string "ldiv")))])
f192bf8b 2543
4ae234b0
GK		 2544(define_expand "mod<mode>3"
2545 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2546 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2547 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
39b52ba2 2548 ""
1fd4e8c1
RK		 2549 "
2550{
481c7efa 2551 int i;
39b52ba2
RK		 2552 rtx temp1;
2553 rtx temp2;
2554
2bfcf297 2555 if (GET_CODE (operands[2]) != CONST_INT
a65c591c 2556 || INTVAL (operands[2]) <= 0
2bfcf297 2557 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
39b52ba2
RK		 2558 FAIL;
2559
4ae234b0
GK		 2560 temp1 = gen_reg_rtx (<MODE>mode);
2561 temp2 = gen_reg_rtx (<MODE>mode);
1fd4e8c1 2562
4ae234b0
GK		 2563 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2564 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2565 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
85644414 2566 DONE;
1fd4e8c1
RK		 2567}")
2568
2569(define_insn ""
4ae234b0
GK		 2570 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2571 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2572 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2bfcf297 2573 ""
4ae234b0 2574 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
943c15ed
DE		 2575 [(set_attr "type" "two")
2576 (set_attr "length" "8")])
1fd4e8c1
RK		 2577
2578(define_insn ""
9ebbca7d 2579 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2580 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2581 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2582 (const_int 0)))
4ae234b0 2583 (clobber (match_scratch:P 3 "=r,r"))]
2bfcf297 2584 ""
9ebbca7d 2585 "@
4ae234b0 2586 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
9ebbca7d 2587 #"
b19003d8 2588 [(set_attr "type" "compare")
9ebbca7d
GK		 2589 (set_attr "length" "8,12")])
2590
2591(define_split
2592 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2593 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2594 (match_operand:GPR 2 "exact_log2_cint_operand"
2595 ""))
9ebbca7d 2596 (const_int 0)))
4ae234b0 2597 (clobber (match_scratch:GPR 3 ""))]
2bfcf297 2598 "reload_completed"
9ebbca7d 2599 [(set (match_dup 3)
4ae234b0 2600 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2601 (set (match_dup 0)
2602 (compare:CC (match_dup 3)
2603 (const_int 0)))]
2604 "")
1fd4e8c1
RK		 2605
2606(define_insn ""
9ebbca7d 2607 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4ae234b0
GK		 2608 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2609 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
b6b12107 2610 (const_int 0)))
4ae234b0
GK		 2611 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2612 (div:P (match_dup 1) (match_dup 2)))]
2bfcf297 2613 ""
9ebbca7d 2614 "@
4ae234b0 2615 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
9ebbca7d 2616 #"
b19003d8 2617 [(set_attr "type" "compare")
9ebbca7d
GK		 2618 (set_attr "length" "8,12")])
2619
2620(define_split
2621 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2622 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2623 (match_operand:GPR 2 "exact_log2_cint_operand"
2624 ""))
9ebbca7d 2625 (const_int 0)))
4ae234b0
GK		 2626 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2627 (div:GPR (match_dup 1) (match_dup 2)))]
2bfcf297 2628 "reload_completed"
9ebbca7d 2629 [(set (match_dup 0)
4ae234b0 2630 (div:<MODE> (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 2631 (set (match_dup 3)
2632 (compare:CC (match_dup 0)
2633 (const_int 0)))]
2634 "")
1fd4e8c1
RK		 2635
2636(define_insn ""
cd2b37d9 2637 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 2638 (udiv:SI
996a5f59 2639 (plus:DI (ashift:DI
cd2b37d9 2640 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1fd4e8c1 2641 (const_int 32))
23a900dc 2642 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
cd2b37d9 2643 (match_operand:SI 3 "gpc_reg_operand" "r")))
740ab4a2 2644 (set (match_operand:SI 2 "register_operand" "=*q")
1fd4e8c1 2645 (umod:SI
996a5f59 2646 (plus:DI (ashift:DI
1fd4e8c1 2647 (zero_extend:DI (match_dup 1)) (const_int 32))
740ab4a2 2648 (zero_extend:DI (match_dup 4)))
1fd4e8c1 2649 (match_dup 3)))]
ca7f5001 2650 "TARGET_POWER"
cfb557c4
RK		 2651 "div %0,%1,%3"
2652 [(set_attr "type" "idiv")])
1fd4e8c1
RK		 2653
2654;; To do unsigned divide we handle the cases of the divisor looking like a
2655;; negative number. If it is a constant that is less than 2**31, we don't
2656;; have to worry about the branches. So make a few subroutines here.
2657;;
2658;; First comes the normal case.
2659(define_expand "udivmodsi4_normal"
2660 [(set (match_dup 4) (const_int 0))
2661 (parallel [(set (match_operand:SI 0 "" "")
996a5f59 2662 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2663 (const_int 32))
2664 (zero_extend:DI (match_operand:SI 1 "" "")))
2665 (match_operand:SI 2 "" "")))
2666 (set (match_operand:SI 3 "" "")
996a5f59 2667 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1fd4e8c1
RK		 2668 (const_int 32))
2669 (zero_extend:DI (match_dup 1)))
2670 (match_dup 2)))])]
ca7f5001 2671 "TARGET_POWER"
1fd4e8c1
RK		 2672 "
2673{ operands[4] = gen_reg_rtx (SImode); }")
2674
2675;; This handles the branches.
2676(define_expand "udivmodsi4_tests"
2677 [(set (match_operand:SI 0 "" "") (const_int 0))
2678 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2679 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2680 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2681 (label_ref (match_operand:SI 4 "" "")) (pc)))
2682 (set (match_dup 0) (const_int 1))
2683 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2684 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2685 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2686 (label_ref (match_dup 4)) (pc)))]
ca7f5001 2687 "TARGET_POWER"
1fd4e8c1
RK		 2688 "
2689{ operands[5] = gen_reg_rtx (CCUNSmode);
2690 operands[6] = gen_reg_rtx (CCmode);
2691}")
2692
2693(define_expand "udivmodsi4"
cd2b37d9
RK		 2694 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2695 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 2696 (match_operand:SI 2 "reg_or_cint_operand" "")))
cd2b37d9 2697 (set (match_operand:SI 3 "gpc_reg_operand" "")
1fd4e8c1 2698 (umod:SI (match_dup 1) (match_dup 2)))])]
8ffd9c51 2699 ""
1fd4e8c1
RK		 2700 "
2701{
2702 rtx label = 0;
2703
8ffd9c51 2704 if (! TARGET_POWER)
c4d38ccb
MM		 2705 {
2706 if (! TARGET_POWERPC)
2707 {
39403d82
DE		 2708 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2709 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
c4d38ccb 2710 emit_insn (gen_divus_call ());
39403d82
DE		 2711 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2712 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
c4d38ccb
MM		 2713 DONE;
2714 }
2715 else
2716 FAIL;
2717 }
0081a354 2718
1fd4e8c1
RK		 2719 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2720 {
2721 operands[2] = force_reg (SImode, operands[2]);
2722 label = gen_label_rtx ();
2723 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2724 operands[3], label));
2725 }
2726 else
2727 operands[2] = force_reg (SImode, operands[2]);
2728
2729 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2730 operands[3]));
2731 if (label)
2732 emit_label (label);
2733
2734 DONE;
2735}")
0081a354 2736
fada905b
MM		 2737;; AIX architecture-independent common-mode multiply (DImode),
2738;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2739;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2740;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2741;; assumed unused if generating common-mode, so ignore.
2742(define_insn "mulh_call"
2743 [(set (reg:SI 3)
2744 (truncate:SI
2745 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2746 (sign_extend:DI (reg:SI 4)))
2747 (const_int 32))))
1de43f85 2748 (clobber (reg:SI LR_REGNO))]
fada905b 2749 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2750 "bla __mulh"
2751 [(set_attr "type" "imul")])
fada905b
MM		 2752
2753(define_insn "mull_call"
2754 [(set (reg:DI 3)
2755 (mult:DI (sign_extend:DI (reg:SI 3))
2756 (sign_extend:DI (reg:SI 4))))
1de43f85 2757 (clobber (reg:SI LR_REGNO))
fada905b
MM		 2758 (clobber (reg:SI 0))]
2759 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2760 "bla __mull"
2761 [(set_attr "type" "imul")])
fada905b
MM		 2762
2763(define_insn "divss_call"
2764 [(set (reg:SI 3)
2765 (div:SI (reg:SI 3) (reg:SI 4)))
2766 (set (reg:SI 4)
2767 (mod:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2768 (clobber (reg:SI LR_REGNO))
fada905b
MM		 2769 (clobber (reg:SI 0))]
2770 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2771 "bla __divss"
2772 [(set_attr "type" "idiv")])
fada905b
MM		 2773
2774(define_insn "divus_call"
8ffd9c51
RK		 2775 [(set (reg:SI 3)
2776 (udiv:SI (reg:SI 3) (reg:SI 4)))
2777 (set (reg:SI 4)
2778 (umod:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2779 (clobber (reg:SI LR_REGNO))
fada905b 2780 (clobber (reg:SI 0))
e65a3857 2781 (clobber (match_scratch:CC 0 "=x"))
1de43f85 2782 (clobber (reg:CC CR1_REGNO))]
fada905b 2783 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2784 "bla __divus"
2785 [(set_attr "type" "idiv")])
fada905b
MM		 2786
2787(define_insn "quoss_call"
2788 [(set (reg:SI 3)
2789 (div:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2790 (clobber (reg:SI LR_REGNO))]
8ffd9c51 2791 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2792 "bla __quoss"
2793 [(set_attr "type" "idiv")])
0081a354 2794
fada905b
MM		 2795(define_insn "quous_call"
2796 [(set (reg:SI 3)
2797 (udiv:SI (reg:SI 3) (reg:SI 4)))
1de43f85 2798 (clobber (reg:SI LR_REGNO))
fada905b 2799 (clobber (reg:SI 0))
e65a3857 2800 (clobber (match_scratch:CC 0 "=x"))
1de43f85 2801 (clobber (reg:CC CR1_REGNO))]
fada905b 2802 "! TARGET_POWER && ! TARGET_POWERPC"
b7ff3d82
DE		 2803 "bla __quous"
2804 [(set_attr "type" "idiv")])
8ffd9c51 2805\f
bb21487f 2806;; Logical instructions
dfbdccdb
GK		 2807;; The logical instructions are mostly combined by using match_operator,
2808;; but the plain AND insns are somewhat different because there is no
2809;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2810;; those rotate-and-mask operations. Thus, the AND insns come first.
2811
29ae5b89
JL		 2812(define_insn "andsi3"
2813 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2814 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
5f59ecb7 2815 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
29ae5b89 2816 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1fd4e8c1
RK		 2817 ""
2818 "@
2819 and %0,%1,%2
ca7f5001
RK		 2820 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2821 {andil.|andi.} %0,%1,%b2
520308bc
DE		 2822 {andiu.|andis.} %0,%1,%u2"
2823 [(set_attr "type" "*,*,compare,compare")])
52d3af72
DE		 2824
2825;; Note to set cr's other than cr0 we do the and immediate and then
0ba1b2ff 2826;; the test again -- this avoids a mfcr which on the higher end
52d3af72 2827;; machines causes an execution serialization
1fd4e8c1 2828
7cd5235b 2829(define_insn "*andsi3_internal2"
52d3af72
DE		 2830 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2831 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2832 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
1fd4e8c1 2833 (const_int 0)))
52d3af72
DE		 2834 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2835 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2836 "TARGET_32BIT"
1fd4e8c1
RK		 2837 "@
2838 and. %3,%1,%2
ca7f5001
RK		 2839 {andil.|andi.} %3,%1,%b2
2840 {andiu.|andis.} %3,%1,%u2
52d3af72
DE		 2841 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2842 #
2843 #
2844 #
2845 #"
2846 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2847 (set_attr "length" "4,4,4,4,8,8,8,8")])
1fd4e8c1 2848
0ba1b2ff
AM		 2849(define_insn "*andsi3_internal3"
2850 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2851 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2852 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2853 (const_int 0)))
2854 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2855 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2856 "TARGET_64BIT"
0ba1b2ff
AM		 2857 "@
2858 #
2859 {andil.|andi.} %3,%1,%b2
2860 {andiu.|andis.} %3,%1,%u2
2861 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2862 #
2863 #
2864 #
2865 #"
2866 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2867 (set_attr "length" "8,4,4,4,8,8,8,8")])
2868
52d3af72
DE		 2869(define_split
2870 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4ae234b0
GK		 2871 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2872 (match_operand:GPR 2 "and_operand" ""))
1fd4e8c1 2873 (const_int 0)))
4ae234b0 2874 (clobber (match_scratch:GPR 3 ""))
52d3af72 2875 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2876 "reload_completed"
52d3af72 2877 [(parallel [(set (match_dup 3)
4ae234b0
GK		 2878 (and:<MODE> (match_dup 1)
2879 (match_dup 2)))
52d3af72
DE		 2880 (clobber (match_dup 4))])
2881 (set (match_dup 0)
2882 (compare:CC (match_dup 3)
2883 (const_int 0)))]
2884 "")
2885
0ba1b2ff
AM		 2886;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2887;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2888
2889(define_split
2890 [(set (match_operand:CC 0 "cc_reg_operand" "")
2891 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2892 (match_operand:SI 2 "gpc_reg_operand" ""))
2893 (const_int 0)))
2894 (clobber (match_scratch:SI 3 ""))
2895 (clobber (match_scratch:CC 4 ""))]
2896 "TARGET_POWERPC64 && reload_completed"
2897 [(parallel [(set (match_dup 3)
2898 (and:SI (match_dup 1)
2899 (match_dup 2)))
2900 (clobber (match_dup 4))])
2901 (set (match_dup 0)
2902 (compare:CC (match_dup 3)
2903 (const_int 0)))]
2904 "")
2905
2906(define_insn "*andsi3_internal4"
52d3af72
DE		 2907 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2908 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
5f59ecb7 2909 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
52d3af72
DE		 2910 (const_int 0)))
2911 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2912 (and:SI (match_dup 1)
2913 (match_dup 2)))
2914 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
4b8a63d6 2915 "TARGET_32BIT"
1fd4e8c1
RK		 2916 "@
2917 and. %0,%1,%2
ca7f5001
RK		 2918 {andil.|andi.} %0,%1,%b2
2919 {andiu.|andis.} %0,%1,%u2
52d3af72
DE		 2920 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2921 #
2922 #
2923 #
2924 #"
2925 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2926 (set_attr "length" "4,4,4,4,8,8,8,8")])
2927
0ba1b2ff
AM		 2928(define_insn "*andsi3_internal5"
2929 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2930 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2931 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2932 (const_int 0)))
2933 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2934 (and:SI (match_dup 1)
2935 (match_dup 2)))
2936 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
683bdff7 2937 "TARGET_64BIT"
0ba1b2ff
AM		 2938 "@
2939 #
2940 {andil.|andi.} %0,%1,%b2
2941 {andiu.|andis.} %0,%1,%u2
2942 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2943 #
2944 #
2945 #
2946 #"
2947 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2948 (set_attr "length" "8,4,4,4,8,8,8,8")])
2949
52d3af72
DE		 2950(define_split
2951 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2952 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2953 (match_operand:SI 2 "and_operand" ""))
2954 (const_int 0)))
2955 (set (match_operand:SI 0 "gpc_reg_operand" "")
2956 (and:SI (match_dup 1)
2957 (match_dup 2)))
2958 (clobber (match_scratch:CC 4 ""))]
0ba1b2ff 2959 "reload_completed"
52d3af72
DE		 2960 [(parallel [(set (match_dup 0)
2961 (and:SI (match_dup 1)
2962 (match_dup 2)))
2963 (clobber (match_dup 4))])
2964 (set (match_dup 3)
2965 (compare:CC (match_dup 0)
2966 (const_int 0)))]
2967 "")
1fd4e8c1 2968
0ba1b2ff
AM		 2969(define_split
2970 [(set (match_operand:CC 3 "cc_reg_operand" "")
2971 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2972 (match_operand:SI 2 "gpc_reg_operand" ""))
2973 (const_int 0)))
2974 (set (match_operand:SI 0 "gpc_reg_operand" "")
2975 (and:SI (match_dup 1)
2976 (match_dup 2)))
2977 (clobber (match_scratch:CC 4 ""))]
2978 "TARGET_POWERPC64 && reload_completed"
2979 [(parallel [(set (match_dup 0)
2980 (and:SI (match_dup 1)
2981 (match_dup 2)))
2982 (clobber (match_dup 4))])
2983 (set (match_dup 3)
2984 (compare:CC (match_dup 0)
2985 (const_int 0)))]
2986 "")
2987
2988;; Handle the PowerPC64 rlwinm corner case
2989
2990(define_insn_and_split "*andsi3_internal6"
2991 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2992 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2993 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2994 "TARGET_POWERPC64"
2995 "#"
2996 "TARGET_POWERPC64"
2997 [(set (match_dup 0)
2998 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2999 (match_dup 4)))
3000 (set (match_dup 0)
3001 (rotate:SI (match_dup 0) (match_dup 5)))]
3002 "
3003{
3004 int mb = extract_MB (operands[2]);
3005 int me = extract_ME (operands[2]);
3006 operands[3] = GEN_INT (me + 1);
3007 operands[5] = GEN_INT (32 - (me + 1));
3008 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3009}"
3010 [(set_attr "length" "8")])
3011
7cd5235b 3012(define_expand "iorsi3"
cd2b37d9 3013 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 3014 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 3015 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
7cd5235b 3016 ""
f357808b
RK		 3017 "
3018{
7cd5235b 3019 if (GET_CODE (operands[2]) == CONST_INT
677a9668 3020 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 3021 {
3022 HOST_WIDE_INT value = INTVAL (operands[2]);
b3a13419
ILT		 3023 rtx tmp = ((!can_create_pseudo_p ()
3024 || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 3025 ? operands[0] : gen_reg_rtx (SImode));
3026
a260abc9
DE		 3027 emit_insn (gen_iorsi3 (tmp, operands[1],
3028 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3029 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 3030 DONE;
3031 }
f357808b
RK		 3032}")
3033
7cd5235b 3034(define_expand "xorsi3"
cd2b37d9 3035 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7cd5235b 3036 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1d328b19 3037 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
1fd4e8c1 3038 ""
7cd5235b 3039 "
1fd4e8c1 3040{
7cd5235b 3041 if (GET_CODE (operands[2]) == CONST_INT
677a9668 3042 && ! logical_operand (operands[2], SImode))
7cd5235b
MM		 3043 {
3044 HOST_WIDE_INT value = INTVAL (operands[2]);
b3a13419
ILT		 3045 rtx tmp = ((!can_create_pseudo_p ()
3046 || rtx_equal_p (operands[0], operands[1]))
7cd5235b
MM		 3047 ? operands[0] : gen_reg_rtx (SImode));
3048
a260abc9
DE		 3049 emit_insn (gen_xorsi3 (tmp, operands[1],
3050 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3051 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7cd5235b
MM		 3052 DONE;
3053 }
1fd4e8c1
RK		 3054}")
3055
dfbdccdb 3056(define_insn "*boolsi3_internal1"
7cd5235b 3057 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 3058 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3059 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3060 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
1fd4e8c1
RK		 3061 ""
3062 "@
dfbdccdb
GK		 3063 %q3 %0,%1,%2
3064 {%q3il|%q3i} %0,%1,%b2
3065 {%q3iu|%q3is} %0,%1,%u2")
1fd4e8c1 3066
dfbdccdb 3067(define_insn "*boolsi3_internal2"
52d3af72 3068 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 3069 (compare:CC (match_operator:SI 4 "boolean_or_operator"
dfbdccdb
GK		 3070 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3071 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3072 (const_int 0)))
52d3af72 3073 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3074 "TARGET_32BIT"
52d3af72 3075 "@
dfbdccdb 3076 %q4. %3,%1,%2
52d3af72
DE		 3077 #"
3078 [(set_attr "type" "compare")
3079 (set_attr "length" "4,8")])
3080
3081(define_split
3082 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3083 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3084 [(match_operand:SI 1 "gpc_reg_operand" "")
3085 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3086 (const_int 0)))
52d3af72 3087 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3088 "TARGET_32BIT && reload_completed"
dfbdccdb 3089 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3090 (set (match_dup 0)
3091 (compare:CC (match_dup 3)
3092 (const_int 0)))]
3093 "")
815cdc52 3094
dfbdccdb 3095(define_insn "*boolsi3_internal3"
52d3af72 3096 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3097 (compare:CC (match_operator:SI 4 "boolean_operator"
3098 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3099 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3100 (const_int 0)))
52d3af72 3101 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3102 (match_dup 4))]
4b8a63d6 3103 "TARGET_32BIT"
52d3af72 3104 "@
dfbdccdb 3105 %q4. %0,%1,%2
52d3af72
DE		 3106 #"
3107 [(set_attr "type" "compare")
3108 (set_attr "length" "4,8")])
3109
3110(define_split
e72247f4 3111 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3112 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3113 [(match_operand:SI 1 "gpc_reg_operand" "")
3114 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3115 (const_int 0)))
75540af0 3116 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3117 (match_dup 4))]
4b8a63d6 3118 "TARGET_32BIT && reload_completed"
dfbdccdb 3119 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3120 (set (match_dup 3)
3121 (compare:CC (match_dup 0)
3122 (const_int 0)))]
3123 "")
1fd4e8c1 3124
6ae08853 3125;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 3126;; each of which does one 16-bit part. This is used by combine.
a260abc9
DE		 3127
3128(define_split
3129 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1d328b19 3130 (match_operator:SI 3 "boolean_or_operator"
dfbdccdb
GK		 3131 [(match_operand:SI 1 "gpc_reg_operand" "")
3132 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
a260abc9 3133 ""
dfbdccdb
GK		 3134 [(set (match_dup 0) (match_dup 4))
3135 (set (match_dup 0) (match_dup 5))]
a260abc9
DE		 3136"
3137{
dfbdccdb
GK		 3138 rtx i;
3139 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
1c563bed 3140 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3141 operands[1], i);
dfbdccdb 3142 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
1c563bed 3143 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
0f4c242b 3144 operands[0], i);
a260abc9
DE		 3145}")
3146
dfbdccdb 3147(define_insn "*boolcsi3_internal1"
cd2b37d9 3148 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3149 (match_operator:SI 3 "boolean_operator"
3150 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3151 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
1fd4e8c1 3152 ""
dfbdccdb 3153 "%q3 %0,%2,%1")
1fd4e8c1 3154
dfbdccdb 3155(define_insn "*boolcsi3_internal2"
52d3af72 3156 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3157 (compare:CC (match_operator:SI 4 "boolean_operator"
3158 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3159 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3160 (const_int 0)))
52d3af72 3161 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3162 "TARGET_32BIT"
52d3af72 3163 "@
dfbdccdb 3164 %q4. %3,%2,%1
52d3af72
DE		 3165 #"
3166 [(set_attr "type" "compare")
3167 (set_attr "length" "4,8")])
3168
3169(define_split
3170 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3171 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3172 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3173 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3174 (const_int 0)))
52d3af72 3175 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3176 "TARGET_32BIT && reload_completed"
dfbdccdb 3177 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3178 (set (match_dup 0)
3179 (compare:CC (match_dup 3)
3180 (const_int 0)))]
3181 "")
1fd4e8c1 3182
dfbdccdb 3183(define_insn "*boolcsi3_internal3"
52d3af72 3184 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3185 (compare:CC (match_operator:SI 4 "boolean_operator"
3186 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3187 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3188 (const_int 0)))
52d3af72 3189 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3190 (match_dup 4))]
4b8a63d6 3191 "TARGET_32BIT"
52d3af72 3192 "@
dfbdccdb 3193 %q4. %0,%2,%1
52d3af72
DE		 3194 #"
3195 [(set_attr "type" "compare")
3196 (set_attr "length" "4,8")])
3197
3198(define_split
e72247f4 3199 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3200 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3201 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3202 (match_operand:SI 2 "gpc_reg_operand" "")])
dfbdccdb 3203 (const_int 0)))
75540af0 3204 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3205 (match_dup 4))]
4b8a63d6 3206 "TARGET_32BIT && reload_completed"
dfbdccdb 3207 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3208 (set (match_dup 3)
3209 (compare:CC (match_dup 0)
3210 (const_int 0)))]
3211 "")
3212
dfbdccdb 3213(define_insn "*boolccsi3_internal1"
cd2b37d9 3214 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 3215 (match_operator:SI 3 "boolean_operator"
3216 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
40501e5f 3217 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
1fd4e8c1 3218 ""
dfbdccdb 3219 "%q3 %0,%1,%2")
1fd4e8c1 3220
dfbdccdb 3221(define_insn "*boolccsi3_internal2"
52d3af72 3222 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3223 (compare:CC (match_operator:SI 4 "boolean_operator"
3224 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3225 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3226 (const_int 0)))
52d3af72 3227 (clobber (match_scratch:SI 3 "=r,r"))]
4b8a63d6 3228 "TARGET_32BIT"
52d3af72 3229 "@
dfbdccdb 3230 %q4. %3,%1,%2
52d3af72
DE		 3231 #"
3232 [(set_attr "type" "compare")
3233 (set_attr "length" "4,8")])
3234
3235(define_split
3236 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 3237 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3238 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3239 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3240 (const_int 0)))
52d3af72 3241 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 3242 "TARGET_32BIT && reload_completed"
dfbdccdb 3243 [(set (match_dup 3) (match_dup 4))
52d3af72
DE		 3244 (set (match_dup 0)
3245 (compare:CC (match_dup 3)
3246 (const_int 0)))]
3247 "")
1fd4e8c1 3248
dfbdccdb 3249(define_insn "*boolccsi3_internal3"
52d3af72 3250 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 3251 (compare:CC (match_operator:SI 4 "boolean_operator"
3252 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3253 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3254 (const_int 0)))
52d3af72 3255 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 3256 (match_dup 4))]
4b8a63d6 3257 "TARGET_32BIT"
52d3af72 3258 "@
dfbdccdb 3259 %q4. %0,%1,%2
52d3af72
DE		 3260 #"
3261 [(set_attr "type" "compare")
3262 (set_attr "length" "4,8")])
3263
3264(define_split
e72247f4 3265 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 3266 (compare:CC (match_operator:SI 4 "boolean_operator"
75540af0
JH		 3267 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3268 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
dfbdccdb 3269 (const_int 0)))
75540af0 3270 (set (match_operand:SI 0 "gpc_reg_operand" "")
dfbdccdb 3271 (match_dup 4))]
4b8a63d6 3272 "TARGET_32BIT && reload_completed"
dfbdccdb 3273 [(set (match_dup 0) (match_dup 4))
52d3af72
DE		 3274 (set (match_dup 3)
3275 (compare:CC (match_dup 0)
3276 (const_int 0)))]
3277 "")
1fd4e8c1
RK		 3278
3279;; maskir insn. We need four forms because things might be in arbitrary
3280;; orders. Don't define forms that only set CR fields because these
3281;; would modify an input register.
3282
7cd5235b 3283(define_insn "*maskir_internal1"
cd2b37d9 3284 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3285 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3286 (match_operand:SI 1 "gpc_reg_operand" "0"))
3287 (and:SI (match_dup 2)
cd2b37d9 3288 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
ca7f5001 3289 "TARGET_POWER"
01def764 3290 "maskir %0,%3,%2")
1fd4e8c1 3291
7cd5235b 3292(define_insn "*maskir_internal2"
242e8072 3293 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764
RK		 3294 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3295 (match_operand:SI 1 "gpc_reg_operand" "0"))
cd2b37d9 3296 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764 3297 (match_dup 2))))]
ca7f5001 3298 "TARGET_POWER"
01def764 3299 "maskir %0,%3,%2")
1fd4e8c1 3300
7cd5235b 3301(define_insn "*maskir_internal3"
cd2b37d9 3302 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
01def764 3303 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
cd2b37d9 3304 (match_operand:SI 3 "gpc_reg_operand" "r"))
01def764
RK		 3305 (and:SI (not:SI (match_dup 2))
3306 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3307 "TARGET_POWER"
01def764 3308 "maskir %0,%3,%2")
1fd4e8c1 3309
7cd5235b 3310(define_insn "*maskir_internal4"
cd2b37d9
RK		 3311 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3312 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
01def764
RK		 3313 (match_operand:SI 2 "gpc_reg_operand" "r"))
3314 (and:SI (not:SI (match_dup 2))
3315 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
ca7f5001 3316 "TARGET_POWER"
01def764 3317 "maskir %0,%3,%2")
1fd4e8c1 3318
7cd5235b 3319(define_insn "*maskir_internal5"
9ebbca7d 3320 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3321 (compare:CC
9ebbca7d
GK		 3322 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3323 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
01def764 3324 (and:SI (match_dup 2)
9ebbca7d 3325 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
1fd4e8c1 3326 (const_int 0)))
9ebbca7d 3327 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3328 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3329 (and:SI (match_dup 2) (match_dup 3))))]
ca7f5001 3330 "TARGET_POWER"
9ebbca7d
GK		 3331 "@
3332 maskir. %0,%3,%2
3333 #"
3334 [(set_attr "type" "compare")
3335 (set_attr "length" "4,8")])
3336
3337(define_split
3338 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3339 (compare:CC
3340 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3341 (match_operand:SI 1 "gpc_reg_operand" ""))
3342 (and:SI (match_dup 2)
3343 (match_operand:SI 3 "gpc_reg_operand" "")))
3344 (const_int 0)))
3345 (set (match_operand:SI 0 "gpc_reg_operand" "")
3346 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3347 (and:SI (match_dup 2) (match_dup 3))))]
3348 "TARGET_POWER && reload_completed"
3349 [(set (match_dup 0)
3350 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3351 (and:SI (match_dup 2) (match_dup 3))))
3352 (set (match_dup 4)
3353 (compare:CC (match_dup 0)
3354 (const_int 0)))]
3355 "")
1fd4e8c1 3356
7cd5235b 3357(define_insn "*maskir_internal6"
9ebbca7d 3358 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3359 (compare:CC
9ebbca7d
GK		 3360 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3361 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3362 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
01def764 3363 (match_dup 2)))
1fd4e8c1 3364 (const_int 0)))
9ebbca7d 3365 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3366 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3367 (and:SI (match_dup 3) (match_dup 2))))]
ca7f5001 3368 "TARGET_POWER"
9ebbca7d
GK		 3369 "@
3370 maskir. %0,%3,%2
3371 #"
3372 [(set_attr "type" "compare")
3373 (set_attr "length" "4,8")])
3374
3375(define_split
3376 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3377 (compare:CC
3378 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3379 (match_operand:SI 1 "gpc_reg_operand" ""))
3380 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3381 (match_dup 2)))
3382 (const_int 0)))
3383 (set (match_operand:SI 0 "gpc_reg_operand" "")
3384 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3385 (and:SI (match_dup 3) (match_dup 2))))]
3386 "TARGET_POWER && reload_completed"
3387 [(set (match_dup 0)
3388 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3389 (and:SI (match_dup 3) (match_dup 2))))
3390 (set (match_dup 4)
3391 (compare:CC (match_dup 0)
3392 (const_int 0)))]
3393 "")
1fd4e8c1 3394
7cd5235b 3395(define_insn "*maskir_internal7"
9ebbca7d 3396 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
815cdc52 3397 (compare:CC
9ebbca7d
GK		 3398 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3399 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
815cdc52 3400 (and:SI (not:SI (match_dup 2))
9ebbca7d 3401 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
815cdc52 3402 (const_int 0)))
9ebbca7d 3403 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
815cdc52
MM		 3404 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3405 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3406 "TARGET_POWER"
9ebbca7d
GK		 3407 "@
3408 maskir. %0,%3,%2
3409 #"
3410 [(set_attr "type" "compare")
3411 (set_attr "length" "4,8")])
3412
3413(define_split
3414 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3415 (compare:CC
3416 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3417 (match_operand:SI 3 "gpc_reg_operand" ""))
3418 (and:SI (not:SI (match_dup 2))
3419 (match_operand:SI 1 "gpc_reg_operand" "")))
3420 (const_int 0)))
3421 (set (match_operand:SI 0 "gpc_reg_operand" "")
3422 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3423 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3424 "TARGET_POWER && reload_completed"
3425 [(set (match_dup 0)
3426 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3427 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3428 (set (match_dup 4)
3429 (compare:CC (match_dup 0)
3430 (const_int 0)))]
3431 "")
1fd4e8c1 3432
7cd5235b 3433(define_insn "*maskir_internal8"
9ebbca7d 3434 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 3435 (compare:CC
9ebbca7d
GK		 3436 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3437 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
01def764 3438 (and:SI (not:SI (match_dup 2))
9ebbca7d 3439 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
1fd4e8c1 3440 (const_int 0)))
9ebbca7d 3441 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
01def764
RK		 3442 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3443 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
ca7f5001 3444 "TARGET_POWER"
9ebbca7d
GK		 3445 "@
3446 maskir. %0,%3,%2
3447 #"
3448 [(set_attr "type" "compare")
3449 (set_attr "length" "4,8")])
fcce224d 3450
9ebbca7d
GK		 3451(define_split
3452 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3453 (compare:CC
3454 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3455 (match_operand:SI 2 "gpc_reg_operand" ""))
3456 (and:SI (not:SI (match_dup 2))
3457 (match_operand:SI 1 "gpc_reg_operand" "")))
3458 (const_int 0)))
3459 (set (match_operand:SI 0 "gpc_reg_operand" "")
3460 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3461 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3462 "TARGET_POWER && reload_completed"
3463 [(set (match_dup 0)
3464 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3465 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3466 (set (match_dup 4)
3467 (compare:CC (match_dup 0)
3468 (const_int 0)))]
3469 "")
fcce224d 3470\f
1fd4e8c1
RK		 3471;; Rotate and shift insns, in all their variants. These support shifts,
3472;; field inserts and extracts, and various combinations thereof.
034c1be0 3473(define_expand "insv"
0ad91047
DE		 3474 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3475 (match_operand:SI 1 "const_int_operand" "")
3476 (match_operand:SI 2 "const_int_operand" ""))
3477 (match_operand 3 "gpc_reg_operand" ""))]
034c1be0
MM		 3478 ""
3479 "
3480{
3481 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3482 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
14502dad
JM		 3483 compiler if the address of the structure is taken later. Likewise, do
3484 not handle invalid E500 subregs. */
034c1be0 3485 if (GET_CODE (operands[0]) == SUBREG
14502dad
JM		 3486 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3487 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3488 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
034c1be0 3489 FAIL;
a78e33fc
DE		 3490
3491 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3492 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3493 else
3494 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3495 DONE;
034c1be0
MM		 3496}")
3497
a78e33fc 3498(define_insn "insvsi"
cd2b37d9 3499 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1
RK		 3500 (match_operand:SI 1 "const_int_operand" "i")
3501 (match_operand:SI 2 "const_int_operand" "i"))
cd2b37d9 3502 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1fd4e8c1
RK		 3503 ""
3504 "*
3505{
3506 int start = INTVAL (operands[2]) & 31;
3507 int size = INTVAL (operands[1]) & 31;
3508
89e9f3a8
MM		 3509 operands[4] = GEN_INT (32 - start - size);
3510 operands[1] = GEN_INT (start + size - 1);
a66078ee 3511 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3512}"
3513 [(set_attr "type" "insert_word")])
1fd4e8c1 3514
a78e33fc 3515(define_insn "*insvsi_internal1"
d56d506a
RK		 3516 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3517 (match_operand:SI 1 "const_int_operand" "i")
3518 (match_operand:SI 2 "const_int_operand" "i"))
6d0a8091 3519 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
d56d506a 3520 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3521 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3522 "*
3523{
3524 int shift = INTVAL (operands[4]) & 31;
3525 int start = INTVAL (operands[2]) & 31;
3526 int size = INTVAL (operands[1]) & 31;
3527
89e9f3a8 3528 operands[4] = GEN_INT (shift - start - size);
6d0a8091 3529 operands[1] = GEN_INT (start + size - 1);
a66078ee 3530 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3531}"
3532 [(set_attr "type" "insert_word")])
d56d506a 3533
a78e33fc 3534(define_insn "*insvsi_internal2"
d56d506a
RK		 3535 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3536 (match_operand:SI 1 "const_int_operand" "i")
3537 (match_operand:SI 2 "const_int_operand" "i"))
3538 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3539 (match_operand:SI 4 "const_int_operand" "i")))]
f0dc3f49 3540 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3541 "*
3542{
3543 int shift = INTVAL (operands[4]) & 31;
3544 int start = INTVAL (operands[2]) & 31;
3545 int size = INTVAL (operands[1]) & 31;
3546
89e9f3a8
MM		 3547 operands[4] = GEN_INT (32 - shift - start - size);
3548 operands[1] = GEN_INT (start + size - 1);
a66078ee 3549 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3550}"
3551 [(set_attr "type" "insert_word")])
d56d506a 3552
a78e33fc 3553(define_insn "*insvsi_internal3"
d56d506a
RK		 3554 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3555 (match_operand:SI 1 "const_int_operand" "i")
3556 (match_operand:SI 2 "const_int_operand" "i"))
3557 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3558 (match_operand:SI 4 "const_int_operand" "i")))]
95e8f2f3 3559 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
d56d506a
RK		 3560 "*
3561{
3562 int shift = INTVAL (operands[4]) & 31;
3563 int start = INTVAL (operands[2]) & 31;
3564 int size = INTVAL (operands[1]) & 31;
3565
89e9f3a8
MM		 3566 operands[4] = GEN_INT (32 - shift - start - size);
3567 operands[1] = GEN_INT (start + size - 1);
a66078ee 3568 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
8e8238f1
DE		 3569}"
3570 [(set_attr "type" "insert_word")])
d56d506a 3571
a78e33fc 3572(define_insn "*insvsi_internal4"
d56d506a
RK		 3573 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3574 (match_operand:SI 1 "const_int_operand" "i")
3575 (match_operand:SI 2 "const_int_operand" "i"))
3576 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3577 (match_operand:SI 4 "const_int_operand" "i")
3578 (match_operand:SI 5 "const_int_operand" "i")))]
3579 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3580 "*
3581{
3582 int extract_start = INTVAL (operands[5]) & 31;
3583 int extract_size = INTVAL (operands[4]) & 31;
3584 int insert_start = INTVAL (operands[2]) & 31;
3585 int insert_size = INTVAL (operands[1]) & 31;
3586
3587/* Align extract field with insert field */
3a598fbe 3588 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
89e9f3a8 3589 operands[1] = GEN_INT (insert_start + insert_size - 1);
a66078ee 3590 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
8e8238f1
DE		 3591}"
3592 [(set_attr "type" "insert_word")])
d56d506a 3593
f241bf89
EC		 3594;; combine patterns for rlwimi
3595(define_insn "*insvsi_internal5"
3596 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3597 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3598 (match_operand:SI 1 "mask_operand" "i"))
3599 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3600 (match_operand:SI 2 "const_int_operand" "i"))
3601 (match_operand:SI 5 "mask_operand" "i"))))]
3602 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3603 "*
3604{
3605 int me = extract_ME(operands[5]);
3606 int mb = extract_MB(operands[5]);
3607 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3608 operands[2] = GEN_INT(mb);
3609 operands[1] = GEN_INT(me);
3610 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3611}"
3612 [(set_attr "type" "insert_word")])
3613
3614(define_insn "*insvsi_internal6"
3615 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3616 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3617 (match_operand:SI 2 "const_int_operand" "i"))
3618 (match_operand:SI 5 "mask_operand" "i"))
3619 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3620 (match_operand:SI 1 "mask_operand" "i"))))]
3621 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3622 "*
3623{
3624 int me = extract_ME(operands[5]);
3625 int mb = extract_MB(operands[5]);
3626 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3627 operands[2] = GEN_INT(mb);
3628 operands[1] = GEN_INT(me);
3629 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3630}"
3631 [(set_attr "type" "insert_word")])
3632
a78e33fc 3633(define_insn "insvdi"
685f3906 3634 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
a78e33fc
DE		 3635 (match_operand:SI 1 "const_int_operand" "i")
3636 (match_operand:SI 2 "const_int_operand" "i"))
685f3906
DE		 3637 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3638 "TARGET_POWERPC64"
3639 "*
3640{
3641 int start = INTVAL (operands[2]) & 63;
3642 int size = INTVAL (operands[1]) & 63;
3643
a78e33fc
DE		 3644 operands[1] = GEN_INT (64 - start - size);
3645 return \"rldimi %0,%3,%H1,%H2\";
44cd321e
PS		 3646}"
3647 [(set_attr "type" "insert_dword")])
685f3906 3648
11ac38b2
DE		 3649(define_insn "*insvdi_internal2"
3650 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3651 (match_operand:SI 1 "const_int_operand" "i")
3652 (match_operand:SI 2 "const_int_operand" "i"))
3653 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3654 (match_operand:SI 4 "const_int_operand" "i")))]
3655 "TARGET_POWERPC64
3656 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3657 "*
3658{
3659 int shift = INTVAL (operands[4]) & 63;
3660 int start = (INTVAL (operands[2]) & 63) - 32;
3661 int size = INTVAL (operands[1]) & 63;
3662
3663 operands[4] = GEN_INT (64 - shift - start - size);
3664 operands[2] = GEN_INT (start);
3665 operands[1] = GEN_INT (start + size - 1);
3666 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3667}")
3668
3669(define_insn "*insvdi_internal3"
3670 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3671 (match_operand:SI 1 "const_int_operand" "i")
3672 (match_operand:SI 2 "const_int_operand" "i"))
3673 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3674 (match_operand:SI 4 "const_int_operand" "i")))]
3675 "TARGET_POWERPC64
3676 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3677 "*
3678{
3679 int shift = INTVAL (operands[4]) & 63;
3680 int start = (INTVAL (operands[2]) & 63) - 32;
3681 int size = INTVAL (operands[1]) & 63;
3682
3683 operands[4] = GEN_INT (64 - shift - start - size);
3684 operands[2] = GEN_INT (start);
3685 operands[1] = GEN_INT (start + size - 1);
3686 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3687}")
3688
034c1be0 3689(define_expand "extzv"
0ad91047
DE		 3690 [(set (match_operand 0 "gpc_reg_operand" "")
3691 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3692 (match_operand:SI 2 "const_int_operand" "")
3693 (match_operand:SI 3 "const_int_operand" "")))]
034c1be0
MM		 3694 ""
3695 "
3696{
3697 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3698 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3699 compiler if the address of the structure is taken later. */
3700 if (GET_CODE (operands[0]) == SUBREG
3701 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3702 FAIL;
a78e33fc
DE		 3703
3704 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3705 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3706 else
3707 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3708 DONE;
034c1be0
MM		 3709}")
3710
a78e33fc 3711(define_insn "extzvsi"
cd2b37d9
RK		 3712 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3713 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 3714 (match_operand:SI 2 "const_int_operand" "i")
3715 (match_operand:SI 3 "const_int_operand" "i")))]
3716 ""
3717 "*
3718{
3719 int start = INTVAL (operands[3]) & 31;
3720 int size = INTVAL (operands[2]) & 31;
3721
3722 if (start + size >= 32)
3723 operands[3] = const0_rtx;
3724 else
89e9f3a8 3725 operands[3] = GEN_INT (start + size);
ca7f5001 3726 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
1fd4e8c1
RK		 3727}")
3728
a78e33fc 3729(define_insn "*extzvsi_internal1"
9ebbca7d
GK		 3730 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3731 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3732 (match_operand:SI 2 "const_int_operand" "i,i")
3733 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3734 (const_int 0)))
9ebbca7d 3735 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 3736 ""
1fd4e8c1
RK		 3737 "*
3738{
3739 int start = INTVAL (operands[3]) & 31;
3740 int size = INTVAL (operands[2]) & 31;
3741
9ebbca7d
GK		 3742 /* Force split for non-cc0 compare. */
3743 if (which_alternative == 1)
3744 return \"#\";
3745
43a88a8c 3746 /* If the bit-field being tested fits in the upper or lower half of a
a7a975e1
RK		 3747 word, it is possible to use andiu. or andil. to test it. This is
3748 useful because the condition register set-use delay is smaller for
3749 andi[ul]. than for rlinm. This doesn't work when the starting bit
3750 position is 0 because the LT and GT bits may be set wrong. */
3751
3752 if ((start > 0 && start + size <= 16) || start >= 16)
df031c43 3753 {
3a598fbe 3754 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
df031c43
RK		 3755 - (1 << (16 - (start & 15) - size))));
3756 if (start < 16)
ca7f5001 3757 return \"{andiu.|andis.} %4,%1,%3\";
df031c43 3758 else
ca7f5001 3759 return \"{andil.|andi.} %4,%1,%3\";
df031c43 3760 }
7e69e155 3761
1fd4e8c1
RK		 3762 if (start + size >= 32)
3763 operands[3] = const0_rtx;
3764 else
89e9f3a8 3765 operands[3] = GEN_INT (start + size);
ca7f5001 3766 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
1fd4e8c1 3767}"
44cd321e 3768 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3769 (set_attr "length" "4,8")])
3770
3771(define_split
3772 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3773 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3774 (match_operand:SI 2 "const_int_operand" "")
3775 (match_operand:SI 3 "const_int_operand" ""))
3776 (const_int 0)))
3777 (clobber (match_scratch:SI 4 ""))]
ce71f754 3778 "reload_completed"
9ebbca7d
GK		 3779 [(set (match_dup 4)
3780 (zero_extract:SI (match_dup 1) (match_dup 2)
3781 (match_dup 3)))
3782 (set (match_dup 0)
3783 (compare:CC (match_dup 4)
3784 (const_int 0)))]
3785 "")
1fd4e8c1 3786
a78e33fc 3787(define_insn "*extzvsi_internal2"
9ebbca7d
GK		 3788 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3789 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3790 (match_operand:SI 2 "const_int_operand" "i,i")
3791 (match_operand:SI 3 "const_int_operand" "i,i"))
1fd4e8c1 3792 (const_int 0)))
9ebbca7d 3793 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 3794 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3795 ""
1fd4e8c1
RK		 3796 "*
3797{
3798 int start = INTVAL (operands[3]) & 31;
3799 int size = INTVAL (operands[2]) & 31;
3800
9ebbca7d
GK		 3801 /* Force split for non-cc0 compare. */
3802 if (which_alternative == 1)
3803 return \"#\";
3804
bc401279 3805 /* Since we are using the output value, we can't ignore any need for
43a88a8c 3806 a shift. The bit-field must end at the LSB. */
bc401279 3807 if (start >= 16 && start + size == 32)
df031c43 3808 {
bc401279
AM		 3809 operands[3] = GEN_INT ((1 << size) - 1);
3810 return \"{andil.|andi.} %0,%1,%3\";
df031c43 3811 }
7e69e155 3812
1fd4e8c1
RK		 3813 if (start + size >= 32)
3814 operands[3] = const0_rtx;
3815 else
89e9f3a8 3816 operands[3] = GEN_INT (start + size);
ca7f5001 3817 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
1fd4e8c1 3818}"
44cd321e 3819 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 3820 (set_attr "length" "4,8")])
3821
3822(define_split
3823 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3824 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3825 (match_operand:SI 2 "const_int_operand" "")
3826 (match_operand:SI 3 "const_int_operand" ""))
3827 (const_int 0)))
3828 (set (match_operand:SI 0 "gpc_reg_operand" "")
3829 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
ce71f754 3830 "reload_completed"
9ebbca7d
GK		 3831 [(set (match_dup 0)
3832 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3833 (set (match_dup 4)
3834 (compare:CC (match_dup 0)
3835 (const_int 0)))]
3836 "")
1fd4e8c1 3837
a78e33fc 3838(define_insn "extzvdi"
685f3906
DE		 3839 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3840 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3841 (match_operand:SI 2 "const_int_operand" "i")
3842 (match_operand:SI 3 "const_int_operand" "i")))]
685f3906
DE		 3843 "TARGET_POWERPC64"
3844 "*
3845{
3846 int start = INTVAL (operands[3]) & 63;
3847 int size = INTVAL (operands[2]) & 63;
3848
3849 if (start + size >= 64)
3850 operands[3] = const0_rtx;
3851 else
89e9f3a8
MM		 3852 operands[3] = GEN_INT (start + size);
3853 operands[2] = GEN_INT (64 - size);
685f3906
DE		 3854 return \"rldicl %0,%1,%3,%2\";
3855}")
3856
a78e33fc 3857(define_insn "*extzvdi_internal1"
29ae5b89
JL		 3858 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3859 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3860 (match_operand:SI 2 "const_int_operand" "i")
3861 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3862 (const_int 0)))
29ae5b89 3863 (clobber (match_scratch:DI 4 "=r"))]
683bdff7 3864 "TARGET_64BIT"
685f3906
DE		 3865 "*
3866{
3867 int start = INTVAL (operands[3]) & 63;
3868 int size = INTVAL (operands[2]) & 63;
3869
3870 if (start + size >= 64)
3871 operands[3] = const0_rtx;
3872 else
89e9f3a8
MM		 3873 operands[3] = GEN_INT (start + size);
3874 operands[2] = GEN_INT (64 - size);
685f3906 3875 return \"rldicl. %4,%1,%3,%2\";
9a3c428b
DE		 3876}"
3877 [(set_attr "type" "compare")])
685f3906 3878
a78e33fc 3879(define_insn "*extzvdi_internal2"
29ae5b89
JL		 3880 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3881 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
a78e33fc
DE		 3882 (match_operand:SI 2 "const_int_operand" "i")
3883 (match_operand:SI 3 "const_int_operand" "i"))
685f3906 3884 (const_int 0)))
29ae5b89 3885 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
685f3906 3886 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
683bdff7 3887 "TARGET_64BIT"
685f3906
DE		 3888 "*
3889{
3890 int start = INTVAL (operands[3]) & 63;
3891 int size = INTVAL (operands[2]) & 63;
3892
3893 if (start + size >= 64)
3894 operands[3] = const0_rtx;
3895 else
89e9f3a8
MM		 3896 operands[3] = GEN_INT (start + size);
3897 operands[2] = GEN_INT (64 - size);
685f3906 3898 return \"rldicl. %0,%1,%3,%2\";
9a3c428b
DE		 3899}"
3900 [(set_attr "type" "compare")])
685f3906 3901
1fd4e8c1 3902(define_insn "rotlsi3"
44cd321e
PS		 3903 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3904 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3905 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
1fd4e8c1 3906 ""
44cd321e
PS		 3907 "@
3908 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3909 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3910 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 3911
a260abc9 3912(define_insn "*rotlsi3_internal2"
44cd321e
PS		 3913 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3914 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3915 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3916 (const_int 0)))
44cd321e 3917 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
ce71f754 3918 ""
9ebbca7d 3919 "@
44cd321e
PS		 3920 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3921 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3922 #
9ebbca7d 3923 #"
44cd321e
PS		 3924 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3925 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3926
3927(define_split
3928 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3929 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3930 (match_operand:SI 2 "reg_or_cint_operand" ""))
3931 (const_int 0)))
3932 (clobber (match_scratch:SI 3 ""))]
ce71f754 3933 "reload_completed"
9ebbca7d
GK		 3934 [(set (match_dup 3)
3935 (rotate:SI (match_dup 1) (match_dup 2)))
3936 (set (match_dup 0)
3937 (compare:CC (match_dup 3)
3938 (const_int 0)))]
3939 "")
1fd4e8c1 3940
a260abc9 3941(define_insn "*rotlsi3_internal3"
44cd321e
PS		 3942 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3943 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3944 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 3945 (const_int 0)))
44cd321e 3946 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 3947 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3948 ""
9ebbca7d 3949 "@
44cd321e
PS		 3950 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3951 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3952 #
9ebbca7d 3953 #"
44cd321e
PS		 3954 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3955 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3956
3957(define_split
3958 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3959 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3960 (match_operand:SI 2 "reg_or_cint_operand" ""))
3961 (const_int 0)))
3962 (set (match_operand:SI 0 "gpc_reg_operand" "")
3963 (rotate:SI (match_dup 1) (match_dup 2)))]
ce71f754 3964 "reload_completed"
9ebbca7d
GK		 3965 [(set (match_dup 0)
3966 (rotate:SI (match_dup 1) (match_dup 2)))
3967 (set (match_dup 3)
3968 (compare:CC (match_dup 0)
3969 (const_int 0)))]
3970 "")
1fd4e8c1 3971
a260abc9 3972(define_insn "*rotlsi3_internal4"
44cd321e
PS		 3973 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3974 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3975 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
3976 (match_operand:SI 3 "mask_operand" "n,n")))]
1fd4e8c1 3977 ""
44cd321e
PS		 3978 "@
3979 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
3980 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
3981 [(set_attr "type" "var_shift_rotate,integer")])
1fd4e8c1 3982
a260abc9 3983(define_insn "*rotlsi3_internal5"
44cd321e 3984 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 3985 (compare:CC (and:SI
44cd321e
PS		 3986 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3987 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3988 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 3989 (const_int 0)))
44cd321e 3990 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
ce71f754 3991 ""
9ebbca7d 3992 "@
44cd321e
PS		 3993 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
3994 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
3995 #
9ebbca7d 3996 #"
44cd321e
PS		 3997 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3998 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 3999
4000(define_split
4001 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4002 (compare:CC (and:SI
4003 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4004 (match_operand:SI 2 "reg_or_cint_operand" ""))
4005 (match_operand:SI 3 "mask_operand" ""))
4006 (const_int 0)))
4007 (clobber (match_scratch:SI 4 ""))]
ce71f754 4008 "reload_completed"
9ebbca7d
GK		 4009 [(set (match_dup 4)
4010 (and:SI (rotate:SI (match_dup 1)
4011 (match_dup 2))
4012 (match_dup 3)))
4013 (set (match_dup 0)
4014 (compare:CC (match_dup 4)
4015 (const_int 0)))]
4016 "")
1fd4e8c1 4017
a260abc9 4018(define_insn "*rotlsi3_internal6"
44cd321e 4019 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 4020 (compare:CC (and:SI
44cd321e
PS		 4021 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4022 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4023 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
1fd4e8c1 4024 (const_int 0)))
44cd321e 4025 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4026 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4027 ""
9ebbca7d 4028 "@
44cd321e
PS		 4029 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4030 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4031 #
9ebbca7d 4032 #"
44cd321e
PS		 4033 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4034 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4035
4036(define_split
4037 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4038 (compare:CC (and:SI
4039 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4040 (match_operand:SI 2 "reg_or_cint_operand" ""))
4041 (match_operand:SI 3 "mask_operand" ""))
4042 (const_int 0)))
4043 (set (match_operand:SI 0 "gpc_reg_operand" "")
4044 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4045 "reload_completed"
9ebbca7d
GK		 4046 [(set (match_dup 0)
4047 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4048 (set (match_dup 4)
4049 (compare:CC (match_dup 0)
4050 (const_int 0)))]
4051 "")
1fd4e8c1 4052
a260abc9 4053(define_insn "*rotlsi3_internal7"
cd2b37d9 4054 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4055 (zero_extend:SI
4056 (subreg:QI
cd2b37d9 4057 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4058 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4059 ""
ca7f5001 4060 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
1fd4e8c1 4061
a260abc9 4062(define_insn "*rotlsi3_internal8"
44cd321e 4063 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4064 (compare:CC (zero_extend:SI
4065 (subreg:QI
44cd321e
PS		 4066 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4067 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4068 (const_int 0)))
44cd321e 4069 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4070 ""
9ebbca7d 4071 "@
44cd321e
PS		 4072 {rlnm.|rlwnm.} %3,%1,%2,0xff
4073 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4074 #
9ebbca7d 4075 #"
44cd321e
PS		 4076 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4077 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4078
4079(define_split
4080 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4081 (compare:CC (zero_extend:SI
4082 (subreg:QI
4083 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4084 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4085 (const_int 0)))
4086 (clobber (match_scratch:SI 3 ""))]
4087 "reload_completed"
4088 [(set (match_dup 3)
4089 (zero_extend:SI (subreg:QI
4090 (rotate:SI (match_dup 1)
4091 (match_dup 2)) 0)))
4092 (set (match_dup 0)
4093 (compare:CC (match_dup 3)
4094 (const_int 0)))]
4095 "")
1fd4e8c1 4096
a260abc9 4097(define_insn "*rotlsi3_internal9"
44cd321e 4098 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4099 (compare:CC (zero_extend:SI
4100 (subreg:QI
44cd321e
PS		 4101 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4102 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4103 (const_int 0)))
44cd321e 4104 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4105 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4106 ""
9ebbca7d 4107 "@
44cd321e
PS		 4108 {rlnm.|rlwnm.} %0,%1,%2,0xff
4109 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4110 #
9ebbca7d 4111 #"
44cd321e
PS		 4112 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4113 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4114
4115(define_split
4116 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4117 (compare:CC (zero_extend:SI
4118 (subreg:QI
4119 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4120 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4121 (const_int 0)))
4122 (set (match_operand:SI 0 "gpc_reg_operand" "")
4123 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4124 "reload_completed"
4125 [(set (match_dup 0)
4126 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4127 (set (match_dup 3)
4128 (compare:CC (match_dup 0)
4129 (const_int 0)))]
4130 "")
1fd4e8c1 4131
a260abc9 4132(define_insn "*rotlsi3_internal10"
44cd321e 4133 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 4134 (zero_extend:SI
4135 (subreg:HI
44cd321e
PS		 4136 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4137 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
1fd4e8c1 4138 ""
44cd321e
PS		 4139 "@
4140 {rlnm|rlwnm} %0,%1,%2,0xffff
4141 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4142 [(set_attr "type" "var_shift_rotate,integer")])
4143
1fd4e8c1 4144
a260abc9 4145(define_insn "*rotlsi3_internal11"
44cd321e 4146 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4147 (compare:CC (zero_extend:SI
4148 (subreg:HI
44cd321e
PS		 4149 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4150 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4151 (const_int 0)))
44cd321e 4152 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1fd4e8c1 4153 ""
9ebbca7d 4154 "@
44cd321e
PS		 4155 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4156 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4157 #
9ebbca7d 4158 #"
44cd321e
PS		 4159 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4160 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4161
4162(define_split
4163 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4164 (compare:CC (zero_extend:SI
4165 (subreg:HI
4166 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4167 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4168 (const_int 0)))
4169 (clobber (match_scratch:SI 3 ""))]
4170 "reload_completed"
4171 [(set (match_dup 3)
4172 (zero_extend:SI (subreg:HI
4173 (rotate:SI (match_dup 1)
4174 (match_dup 2)) 0)))
4175 (set (match_dup 0)
4176 (compare:CC (match_dup 3)
4177 (const_int 0)))]
4178 "")
1fd4e8c1 4179
a260abc9 4180(define_insn "*rotlsi3_internal12"
44cd321e 4181 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 4182 (compare:CC (zero_extend:SI
4183 (subreg:HI
44cd321e
PS		 4184 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4185 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
1fd4e8c1 4186 (const_int 0)))
44cd321e 4187 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1
RK		 4188 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4189 ""
9ebbca7d 4190 "@
44cd321e
PS		 4191 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4192 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4193 #
9ebbca7d 4194 #"
44cd321e
PS		 4195 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4196 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4197
4198(define_split
4199 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4200 (compare:CC (zero_extend:SI
4201 (subreg:HI
4202 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4203 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4204 (const_int 0)))
4205 (set (match_operand:SI 0 "gpc_reg_operand" "")
4206 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4207 "reload_completed"
4208 [(set (match_dup 0)
4209 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4210 (set (match_dup 3)
4211 (compare:CC (match_dup 0)
4212 (const_int 0)))]
4213 "")
1fd4e8c1
RK		 4214
4215;; Note that we use "sle." instead of "sl." so that we can set
4216;; SHIFT_COUNT_TRUNCATED.
4217
ca7f5001
RK		 4218(define_expand "ashlsi3"
4219 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4220 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4221 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4222 ""
4223 "
4224{
4225 if (TARGET_POWER)
4226 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4227 else
25c341fa 4228 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4229 DONE;
4230}")
4231
4232(define_insn "ashlsi3_power"
cd2b37d9
RK		 4233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4234 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4235 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4236 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4237 "TARGET_POWER"
1fd4e8c1
RK		 4238 "@
4239 sle %0,%1,%2
9ebbca7d 4240 {sli|slwi} %0,%1,%h2")
ca7f5001 4241
25c341fa 4242(define_insn "ashlsi3_no_power"
44cd321e
PS		 4243 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4244 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4245 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4246 "! TARGET_POWER"
44cd321e
PS		 4247 "@
4248 {sl|slw} %0,%1,%2
4249 {sli|slwi} %0,%1,%h2"
4250 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 4251
4252(define_insn ""
9ebbca7d
GK		 4253 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4254 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4255 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4256 (const_int 0)))
9ebbca7d
GK		 4257 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4258 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4259 "TARGET_POWER"
1fd4e8c1
RK		 4260 "@
4261 sle. %3,%1,%2
9ebbca7d
GK		 4262 {sli.|slwi.} %3,%1,%h2
4263 #
4264 #"
4265 [(set_attr "type" "delayed_compare")
4266 (set_attr "length" "4,4,8,8")])
4267
4268(define_split
4269 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4270 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4271 (match_operand:SI 2 "reg_or_cint_operand" ""))
4272 (const_int 0)))
4273 (clobber (match_scratch:SI 3 ""))
4274 (clobber (match_scratch:SI 4 ""))]
4275 "TARGET_POWER && reload_completed"
4276 [(parallel [(set (match_dup 3)
4277 (ashift:SI (match_dup 1) (match_dup 2)))
4278 (clobber (match_dup 4))])
4279 (set (match_dup 0)
4280 (compare:CC (match_dup 3)
4281 (const_int 0)))]
4282 "")
25c341fa 4283
ca7f5001 4284(define_insn ""
44cd321e
PS		 4285 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4286 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4287 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4288 (const_int 0)))
44cd321e 4289 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4b8a63d6 4290 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4291 "@
44cd321e
PS		 4292 {sl.|slw.} %3,%1,%2
4293 {sli.|slwi.} %3,%1,%h2
4294 #
9ebbca7d 4295 #"
44cd321e
PS		 4296 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4297 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4298
4299(define_split
4300 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4301 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4302 (match_operand:SI 2 "reg_or_cint_operand" ""))
4303 (const_int 0)))
4304 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4305 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4306 [(set (match_dup 3)
4307 (ashift:SI (match_dup 1) (match_dup 2)))
4308 (set (match_dup 0)
4309 (compare:CC (match_dup 3)
4310 (const_int 0)))]
4311 "")
1fd4e8c1
RK		 4312
4313(define_insn ""
9ebbca7d
GK		 4314 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4315 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4316 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4317 (const_int 0)))
9ebbca7d 4318 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4319 (ashift:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4320 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4321 "TARGET_POWER"
1fd4e8c1
RK		 4322 "@
4323 sle. %0,%1,%2
9ebbca7d
GK		 4324 {sli.|slwi.} %0,%1,%h2
4325 #
4326 #"
4327 [(set_attr "type" "delayed_compare")
4328 (set_attr "length" "4,4,8,8")])
4329
4330(define_split
4331 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4332 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4333 (match_operand:SI 2 "reg_or_cint_operand" ""))
4334 (const_int 0)))
4335 (set (match_operand:SI 0 "gpc_reg_operand" "")
4336 (ashift:SI (match_dup 1) (match_dup 2)))
4337 (clobber (match_scratch:SI 4 ""))]
4338 "TARGET_POWER && reload_completed"
4339 [(parallel [(set (match_dup 0)
4340 (ashift:SI (match_dup 1) (match_dup 2)))
4341 (clobber (match_dup 4))])
4342 (set (match_dup 3)
4343 (compare:CC (match_dup 0)
4344 (const_int 0)))]
4345 "")
25c341fa 4346
ca7f5001 4347(define_insn ""
44cd321e
PS		 4348 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4349 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4350 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4351 (const_int 0)))
44cd321e 4352 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 4353 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4354 "! TARGET_POWER && TARGET_32BIT"
9ebbca7d 4355 "@
44cd321e
PS		 4356 {sl.|slw.} %0,%1,%2
4357 {sli.|slwi.} %0,%1,%h2
4358 #
9ebbca7d 4359 #"
44cd321e
PS		 4360 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4361 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4362
4363(define_split
4364 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4365 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4366 (match_operand:SI 2 "reg_or_cint_operand" ""))
4367 (const_int 0)))
4368 (set (match_operand:SI 0 "gpc_reg_operand" "")
4369 (ashift:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4370 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4371 [(set (match_dup 0)
4372 (ashift:SI (match_dup 1) (match_dup 2)))
4373 (set (match_dup 3)
4374 (compare:CC (match_dup 0)
4375 (const_int 0)))]
4376 "")
1fd4e8c1 4377
915167f5 4378(define_insn "rlwinm"
cd2b37d9
RK		 4379 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4380 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4381 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4382 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4383 "includes_lshift_p (operands[2], operands[3])"
d56d506a 4384 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
1fd4e8c1
RK		 4385
4386(define_insn ""
9ebbca7d 4387 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4388 (compare:CC
9ebbca7d
GK		 4389 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4390 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4391 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4392 (const_int 0)))
9ebbca7d 4393 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4394 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4395 "@
4396 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4397 #"
4398 [(set_attr "type" "delayed_compare")
4399 (set_attr "length" "4,8")])
4400
4401(define_split
4402 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4403 (compare:CC
4404 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4405 (match_operand:SI 2 "const_int_operand" ""))
4406 (match_operand:SI 3 "mask_operand" ""))
4407 (const_int 0)))
4408 (clobber (match_scratch:SI 4 ""))]
ce71f754 4409 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4410 [(set (match_dup 4)
4411 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4412 (match_dup 3)))
4413 (set (match_dup 0)
4414 (compare:CC (match_dup 4)
4415 (const_int 0)))]
4416 "")
1fd4e8c1
RK		 4417
4418(define_insn ""
9ebbca7d 4419 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4420 (compare:CC
9ebbca7d
GK		 4421 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4422 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4423 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4424 (const_int 0)))
9ebbca7d 4425 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4426 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4427 "includes_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4428 "@
4429 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4430 #"
4431 [(set_attr "type" "delayed_compare")
4432 (set_attr "length" "4,8")])
4433
4434(define_split
4435 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4436 (compare:CC
4437 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4438 (match_operand:SI 2 "const_int_operand" ""))
4439 (match_operand:SI 3 "mask_operand" ""))
4440 (const_int 0)))
4441 (set (match_operand:SI 0 "gpc_reg_operand" "")
4442 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4443 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4444 [(set (match_dup 0)
4445 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4446 (set (match_dup 4)
4447 (compare:CC (match_dup 0)
4448 (const_int 0)))]
4449 "")
1fd4e8c1 4450
ca7f5001 4451;; The AIX assembler mis-handles "sri x,x,0", so write that case as
5c23c401 4452;; "sli x,x,0".
ca7f5001
RK		 4453(define_expand "lshrsi3"
4454 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4455 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4456 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4457 ""
4458 "
4459{
4460 if (TARGET_POWER)
4461 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4462 else
25c341fa 4463 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4464 DONE;
4465}")
4466
4467(define_insn "lshrsi3_power"
bdf423cb
MM		 4468 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4469 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4470 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4471 (clobber (match_scratch:SI 3 "=q,X,X"))]
ca7f5001 4472 "TARGET_POWER"
1fd4e8c1
RK		 4473 "@
4474 sre %0,%1,%2
bdf423cb 4475 mr %0,%1
ca7f5001
RK		 4476 {s%A2i|s%A2wi} %0,%1,%h2")
4477
25c341fa 4478(define_insn "lshrsi3_no_power"
44cd321e
PS		 4479 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4480 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4481 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
25c341fa 4482 "! TARGET_POWER"
bdf423cb
MM		 4483 "@
4484 mr %0,%1
44cd321e
PS		 4485 {sr|srw} %0,%1,%2
4486 {sri|srwi} %0,%1,%h2"
4487 [(set_attr "type" "integer,var_shift_rotate,shift")])
1fd4e8c1
RK		 4488
4489(define_insn ""
9ebbca7d
GK		 4490 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4491 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4492 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4493 (const_int 0)))
9ebbca7d
GK		 4494 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4495 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4496 "TARGET_POWER"
1fd4e8c1 4497 "@
29ae5b89
JL		 4498 sre. %3,%1,%2
4499 mr. %1,%1
9ebbca7d
GK		 4500 {s%A2i.|s%A2wi.} %3,%1,%h2
4501 #
4502 #
4503 #"
4504 [(set_attr "type" "delayed_compare")
4505 (set_attr "length" "4,4,4,8,8,8")])
4506
4507(define_split
4508 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4509 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4510 (match_operand:SI 2 "reg_or_cint_operand" ""))
4511 (const_int 0)))
4512 (clobber (match_scratch:SI 3 ""))
4513 (clobber (match_scratch:SI 4 ""))]
4514 "TARGET_POWER && reload_completed"
4515 [(parallel [(set (match_dup 3)
4516 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4517 (clobber (match_dup 4))])
4518 (set (match_dup 0)
4519 (compare:CC (match_dup 3)
4520 (const_int 0)))]
4521 "")
ca7f5001
RK		 4522
4523(define_insn ""
44cd321e
PS		 4524 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4525 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4526 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
ca7f5001 4527 (const_int 0)))
44cd321e 4528 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4b8a63d6 4529 "! TARGET_POWER && TARGET_32BIT"
bdf423cb
MM		 4530 "@
4531 mr. %1,%1
44cd321e
PS		 4532 {sr.|srw.} %3,%1,%2
4533 {sri.|srwi.} %3,%1,%h2
4534 #
9ebbca7d
GK		 4535 #
4536 #"
44cd321e
PS		 4537 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4538 (set_attr "length" "4,4,4,8,8,8")])
1fd4e8c1 4539
9ebbca7d
GK		 4540(define_split
4541 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4542 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4543 (match_operand:SI 2 "reg_or_cint_operand" ""))
4544 (const_int 0)))
4545 (clobber (match_scratch:SI 3 ""))]
4b8a63d6 4546 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4547 [(set (match_dup 3)
4548 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4549 (set (match_dup 0)
4550 (compare:CC (match_dup 3)
4551 (const_int 0)))]
4552 "")
4553
4554(define_insn ""
4555 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4556 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4557 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
1fd4e8c1 4558 (const_int 0)))
9ebbca7d 4559 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
1fd4e8c1 4560 (lshiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4561 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
ca7f5001 4562 "TARGET_POWER"
1fd4e8c1 4563 "@
29ae5b89
JL		 4564 sre. %0,%1,%2
4565 mr. %0,%1
9ebbca7d
GK		 4566 {s%A2i.|s%A2wi.} %0,%1,%h2
4567 #
4568 #
4569 #"
4570 [(set_attr "type" "delayed_compare")
4571 (set_attr "length" "4,4,4,8,8,8")])
4572
4573(define_split
4574 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4575 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4576 (match_operand:SI 2 "reg_or_cint_operand" ""))
4577 (const_int 0)))
4578 (set (match_operand:SI 0 "gpc_reg_operand" "")
4579 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4580 (clobber (match_scratch:SI 4 ""))]
4581 "TARGET_POWER && reload_completed"
4582 [(parallel [(set (match_dup 0)
4583 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4584 (clobber (match_dup 4))])
4585 (set (match_dup 3)
4586 (compare:CC (match_dup 0)
4587 (const_int 0)))]
4588 "")
ca7f5001
RK		 4589
4590(define_insn ""
44cd321e
PS		 4591 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4592 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4593 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
815cdc52 4594 (const_int 0)))
44cd321e 4595 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
29ae5b89 4596 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4597 "! TARGET_POWER && TARGET_32BIT"
29ae5b89
JL		 4598 "@
4599 mr. %0,%1
44cd321e
PS		 4600 {sr.|srw.} %0,%1,%2
4601 {sri.|srwi.} %0,%1,%h2
4602 #
9ebbca7d
GK		 4603 #
4604 #"
44cd321e
PS		 4605 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4606 (set_attr "length" "4,4,4,8,8,8")])
9ebbca7d
GK		 4607
4608(define_split
4609 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4610 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4611 (match_operand:SI 2 "reg_or_cint_operand" ""))
4612 (const_int 0)))
4613 (set (match_operand:SI 0 "gpc_reg_operand" "")
4614 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4b8a63d6 4615 "! TARGET_POWER && TARGET_32BIT && reload_completed"
9ebbca7d
GK		 4616 [(set (match_dup 0)
4617 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4618 (set (match_dup 3)
4619 (compare:CC (match_dup 0)
4620 (const_int 0)))]
4621 "")
1fd4e8c1
RK		 4622
4623(define_insn ""
cd2b37d9
RK		 4624 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4625 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4626 (match_operand:SI 2 "const_int_operand" "i"))
ce71f754 4627 (match_operand:SI 3 "mask_operand" "n")))]
1fd4e8c1 4628 "includes_rshift_p (operands[2], operands[3])"
ca7f5001 4629 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
1fd4e8c1
RK		 4630
4631(define_insn ""
9ebbca7d 4632 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 4633 (compare:CC
9ebbca7d
GK		 4634 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4635 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4636 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4637 (const_int 0)))
9ebbca7d 4638 (clobber (match_scratch:SI 4 "=r,r"))]
ce71f754 4639 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4640 "@
4641 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4642 #"
4643 [(set_attr "type" "delayed_compare")
4644 (set_attr "length" "4,8")])
4645
4646(define_split
4647 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4648 (compare:CC
4649 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4650 (match_operand:SI 2 "const_int_operand" ""))
4651 (match_operand:SI 3 "mask_operand" ""))
4652 (const_int 0)))
4653 (clobber (match_scratch:SI 4 ""))]
ce71f754 4654 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4655 [(set (match_dup 4)
4656 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4657 (match_dup 3)))
4658 (set (match_dup 0)
4659 (compare:CC (match_dup 4)
4660 (const_int 0)))]
4661 "")
1fd4e8c1
RK		 4662
4663(define_insn ""
9ebbca7d 4664 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 4665 (compare:CC
9ebbca7d
GK		 4666 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4667 (match_operand:SI 2 "const_int_operand" "i,i"))
ce71f754 4668 (match_operand:SI 3 "mask_operand" "n,n"))
1fd4e8c1 4669 (const_int 0)))
9ebbca7d 4670 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4671 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4672 "includes_rshift_p (operands[2], operands[3])"
9ebbca7d
GK		 4673 "@
4674 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4675 #"
4676 [(set_attr "type" "delayed_compare")
4677 (set_attr "length" "4,8")])
4678
4679(define_split
4680 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4681 (compare:CC
4682 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4683 (match_operand:SI 2 "const_int_operand" ""))
4684 (match_operand:SI 3 "mask_operand" ""))
4685 (const_int 0)))
4686 (set (match_operand:SI 0 "gpc_reg_operand" "")
4687 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ce71f754 4688 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
9ebbca7d
GK		 4689 [(set (match_dup 0)
4690 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4691 (set (match_dup 4)
4692 (compare:CC (match_dup 0)
4693 (const_int 0)))]
4694 "")
1fd4e8c1
RK		 4695
4696(define_insn ""
cd2b37d9 4697 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4698 (zero_extend:SI
4699 (subreg:QI
cd2b37d9 4700 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4701 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4702 "includes_rshift_p (operands[2], GEN_INT (255))"
ca7f5001 4703 "{rlinm|rlwinm} %0,%1,%s2,0xff")
1fd4e8c1
RK		 4704
4705(define_insn ""
9ebbca7d 4706 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4707 (compare:CC
4708 (zero_extend:SI
4709 (subreg:QI
9ebbca7d
GK		 4710 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4711 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4712 (const_int 0)))
9ebbca7d 4713 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4714 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4715 "@
4716 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4717 #"
4718 [(set_attr "type" "delayed_compare")
4719 (set_attr "length" "4,8")])
4720
4721(define_split
4722 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4723 (compare:CC
4724 (zero_extend:SI
4725 (subreg:QI
4726 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4727 (match_operand:SI 2 "const_int_operand" "")) 0))
4728 (const_int 0)))
4729 (clobber (match_scratch:SI 3 ""))]
4730 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4731 [(set (match_dup 3)
4732 (zero_extend:SI (subreg:QI
4733 (lshiftrt:SI (match_dup 1)
4734 (match_dup 2)) 0)))
4735 (set (match_dup 0)
4736 (compare:CC (match_dup 3)
4737 (const_int 0)))]
4738 "")
1fd4e8c1
RK		 4739
4740(define_insn ""
9ebbca7d 4741 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4742 (compare:CC
4743 (zero_extend:SI
4744 (subreg:QI
9ebbca7d
GK		 4745 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4746 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4747 (const_int 0)))
9ebbca7d 4748 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4749 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4750 "includes_rshift_p (operands[2], GEN_INT (255))"
9ebbca7d
GK		 4751 "@
4752 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4753 #"
4754 [(set_attr "type" "delayed_compare")
4755 (set_attr "length" "4,8")])
4756
4757(define_split
4758 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4759 (compare:CC
4760 (zero_extend:SI
4761 (subreg:QI
4762 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4763 (match_operand:SI 2 "const_int_operand" "")) 0))
4764 (const_int 0)))
4765 (set (match_operand:SI 0 "gpc_reg_operand" "")
4766 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4767 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4768 [(set (match_dup 0)
4769 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4770 (set (match_dup 3)
4771 (compare:CC (match_dup 0)
4772 (const_int 0)))]
4773 "")
1fd4e8c1
RK		 4774
4775(define_insn ""
cd2b37d9 4776 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 4777 (zero_extend:SI
4778 (subreg:HI
cd2b37d9 4779 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 4780 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
89e9f3a8 4781 "includes_rshift_p (operands[2], GEN_INT (65535))"
ca7f5001 4782 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
1fd4e8c1
RK		 4783
4784(define_insn ""
9ebbca7d 4785 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4786 (compare:CC
4787 (zero_extend:SI
4788 (subreg:HI
9ebbca7d
GK		 4789 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4790 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4791 (const_int 0)))
9ebbca7d 4792 (clobber (match_scratch:SI 3 "=r,r"))]
89e9f3a8 4793 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4794 "@
4795 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4796 #"
4797 [(set_attr "type" "delayed_compare")
4798 (set_attr "length" "4,8")])
4799
4800(define_split
4801 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4802 (compare:CC
4803 (zero_extend:SI
4804 (subreg:HI
4805 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4806 (match_operand:SI 2 "const_int_operand" "")) 0))
4807 (const_int 0)))
4808 (clobber (match_scratch:SI 3 ""))]
4809 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4810 [(set (match_dup 3)
4811 (zero_extend:SI (subreg:HI
4812 (lshiftrt:SI (match_dup 1)
4813 (match_dup 2)) 0)))
4814 (set (match_dup 0)
4815 (compare:CC (match_dup 3)
4816 (const_int 0)))]
4817 "")
1fd4e8c1
RK		 4818
4819(define_insn ""
9ebbca7d 4820 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 4821 (compare:CC
4822 (zero_extend:SI
4823 (subreg:HI
9ebbca7d
GK		 4824 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4825 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
1fd4e8c1 4826 (const_int 0)))
9ebbca7d 4827 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 4828 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
89e9f3a8 4829 "includes_rshift_p (operands[2], GEN_INT (65535))"
9ebbca7d
GK		 4830 "@
4831 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4832 #"
4833 [(set_attr "type" "delayed_compare")
4834 (set_attr "length" "4,8")])
4835
4836(define_split
4837 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4838 (compare:CC
4839 (zero_extend:SI
4840 (subreg:HI
4841 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4842 (match_operand:SI 2 "const_int_operand" "")) 0))
4843 (const_int 0)))
4844 (set (match_operand:SI 0 "gpc_reg_operand" "")
4845 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4846 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4847 [(set (match_dup 0)
4848 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4849 (set (match_dup 3)
4850 (compare:CC (match_dup 0)
4851 (const_int 0)))]
4852 "")
1fd4e8c1
RK		 4853
4854(define_insn ""
cd2b37d9 4855 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4856 (const_int 1)
cd2b37d9
RK		 4857 (match_operand:SI 1 "gpc_reg_operand" "r"))
4858 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4859 (const_int 31)))]
ca7f5001 4860 "TARGET_POWER"
1fd4e8c1
RK		 4861 "rrib %0,%1,%2")
4862
4863(define_insn ""
cd2b37d9 4864 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4865 (const_int 1)
cd2b37d9
RK		 4866 (match_operand:SI 1 "gpc_reg_operand" "r"))
4867 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1 4868 (const_int 31)))]
ca7f5001 4869 "TARGET_POWER"
1fd4e8c1
RK		 4870 "rrib %0,%1,%2")
4871
4872(define_insn ""
cd2b37d9 4873 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1fd4e8c1 4874 (const_int 1)
cd2b37d9
RK		 4875 (match_operand:SI 1 "gpc_reg_operand" "r"))
4876 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1fd4e8c1
RK		 4877 (const_int 1)
4878 (const_int 0)))]
ca7f5001 4879 "TARGET_POWER"
1fd4e8c1
RK		 4880 "rrib %0,%1,%2")
4881
ca7f5001
RK		 4882(define_expand "ashrsi3"
4883 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4884 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4885 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4886 ""
4887 "
4888{
4889 if (TARGET_POWER)
4890 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4891 else
25c341fa 4892 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
ca7f5001
RK		 4893 DONE;
4894}")
4895
4896(define_insn "ashrsi3_power"
cd2b37d9
RK		 4897 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4898 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 4899 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4900 (clobber (match_scratch:SI 3 "=q,X"))]
ca7f5001 4901 "TARGET_POWER"
1fd4e8c1
RK		 4902 "@
4903 srea %0,%1,%2
44cd321e
PS		 4904 {srai|srawi} %0,%1,%h2"
4905 [(set_attr "type" "shift")])
ca7f5001 4906
25c341fa 4907(define_insn "ashrsi3_no_power"
44cd321e
PS		 4908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4909 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4910 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
25c341fa 4911 "! TARGET_POWER"
44cd321e
PS		 4912 "@
4913 {sra|sraw} %0,%1,%2
4914 {srai|srawi} %0,%1,%h2"
4915 [(set_attr "type" "var_shift_rotate,shift")])
1fd4e8c1
RK		 4916
4917(define_insn ""
9ebbca7d
GK		 4918 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4919 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4920 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4921 (const_int 0)))
9ebbca7d
GK		 4922 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4923 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4924 "TARGET_POWER"
1fd4e8c1
RK		 4925 "@
4926 srea. %3,%1,%2
9ebbca7d
GK		 4927 {srai.|srawi.} %3,%1,%h2
4928 #
4929 #"
4930 [(set_attr "type" "delayed_compare")
4931 (set_attr "length" "4,4,8,8")])
4932
4933(define_split
4934 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4935 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4936 (match_operand:SI 2 "reg_or_cint_operand" ""))
4937 (const_int 0)))
4938 (clobber (match_scratch:SI 3 ""))
4939 (clobber (match_scratch:SI 4 ""))]
4940 "TARGET_POWER && reload_completed"
4941 [(parallel [(set (match_dup 3)
4942 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4943 (clobber (match_dup 4))])
4944 (set (match_dup 0)
4945 (compare:CC (match_dup 3)
4946 (const_int 0)))]
4947 "")
ca7f5001
RK		 4948
4949(define_insn ""
44cd321e
PS		 4950 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4951 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4952 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 4953 (const_int 0)))
44cd321e 4954 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
25c341fa 4955 "! TARGET_POWER"
9ebbca7d 4956 "@
44cd321e
PS		 4957 {sra.|sraw.} %3,%1,%2
4958 {srai.|srawi.} %3,%1,%h2
4959 #
9ebbca7d 4960 #"
44cd321e
PS		 4961 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4962 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 4963
4964(define_split
4965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4966 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4967 (match_operand:SI 2 "reg_or_cint_operand" ""))
4968 (const_int 0)))
4969 (clobber (match_scratch:SI 3 ""))]
4970 "! TARGET_POWER && reload_completed"
4971 [(set (match_dup 3)
4972 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4973 (set (match_dup 0)
4974 (compare:CC (match_dup 3)
4975 (const_int 0)))]
4976 "")
1fd4e8c1
RK		 4977
4978(define_insn ""
9ebbca7d
GK		 4979 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4980 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4981 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
1fd4e8c1 4982 (const_int 0)))
9ebbca7d 4983 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 4984 (ashiftrt:SI (match_dup 1) (match_dup 2)))
9ebbca7d 4985 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
ca7f5001 4986 "TARGET_POWER"
1fd4e8c1
RK		 4987 "@
4988 srea. %0,%1,%2
9ebbca7d
GK		 4989 {srai.|srawi.} %0,%1,%h2
4990 #
4991 #"
4992 [(set_attr "type" "delayed_compare")
4993 (set_attr "length" "4,4,8,8")])
4994
4995(define_split
4996 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4997 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4998 (match_operand:SI 2 "reg_or_cint_operand" ""))
4999 (const_int 0)))
5000 (set (match_operand:SI 0 "gpc_reg_operand" "")
5001 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5002 (clobber (match_scratch:SI 4 ""))]
5003 "TARGET_POWER && reload_completed"
5004 [(parallel [(set (match_dup 0)
5005 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5006 (clobber (match_dup 4))])
5007 (set (match_dup 3)
5008 (compare:CC (match_dup 0)
5009 (const_int 0)))]
5010 "")
1fd4e8c1 5011
ca7f5001 5012(define_insn ""
44cd321e
PS		 5013 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5014 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5015 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
ca7f5001 5016 (const_int 0)))
44cd321e 5017 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
ca7f5001 5018 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
25c341fa 5019 "! TARGET_POWER"
9ebbca7d 5020 "@
44cd321e
PS		 5021 {sra.|sraw.} %0,%1,%2
5022 {srai.|srawi.} %0,%1,%h2
5023 #
9ebbca7d 5024 #"
44cd321e
PS		 5025 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5026 (set_attr "length" "4,4,8,8")])
1fd4e8c1 5027\f
9ebbca7d
GK		 5028(define_split
5029 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5030 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5031 (match_operand:SI 2 "reg_or_cint_operand" ""))
5032 (const_int 0)))
5033 (set (match_operand:SI 0 "gpc_reg_operand" "")
5034 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5035 "! TARGET_POWER && reload_completed"
5036 [(set (match_dup 0)
5037 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5038 (set (match_dup 3)
5039 (compare:CC (match_dup 0)
5040 (const_int 0)))]
5041 "")
5042
1fd4e8c1
RK		 5043;; Floating-point insns, excluding normal data motion.
5044;;
ca7f5001
RK		 5045;; PowerPC has a full set of single-precision floating point instructions.
5046;;
5047;; For the POWER architecture, we pretend that we have both SFmode and
5048;; DFmode insns, while, in fact, all fp insns are actually done in double.
5049;; The only conversions we will do will be when storing to memory. In that
5050;; case, we will use the "frsp" instruction before storing.
1fd4e8c1
RK		 5051;;
5052;; Note that when we store into a single-precision memory location, we need to
5053;; use the frsp insn first. If the register being stored isn't dead, we
5054;; need a scratch register for the frsp. But this is difficult when the store
5055;; is done by reload. It is not incorrect to do the frsp on the register in
5056;; this case, we just lose precision that we would have otherwise gotten but
5057;; is not guaranteed. Perhaps this should be tightened up at some point.
5058
99176a91
AH		 5059(define_expand "extendsfdf2"
5060 [(set (match_operand:DF 0 "gpc_reg_operand" "")
97c54d9a 5061 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
cf8e1455 5062 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
99176a91
AH		 5063 "")
5064
5065(define_insn_and_split "*extendsfdf2_fpr"
97c54d9a
DE		 5066 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
5067 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
cf8e1455 5068 "TARGET_HARD_FLOAT && TARGET_FPRS"
11ac38b2
DE		 5069 "@
5070 #
97c54d9a
DE		 5071 fmr %0,%1
5072 lfs%U1%X1 %0,%1"
d7b1468b 5073 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
11ac38b2 5074 [(const_int 0)]
5c30aff8 5075{
11ac38b2
DE		 5076 emit_note (NOTE_INSN_DELETED);
5077 DONE;
5078}
97c54d9a 5079 [(set_attr "type" "fp,fp,fpload")])
1fd4e8c1 5080
7a2f7870
AH		 5081(define_expand "truncdfsf2"
5082 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5083 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
cf8e1455 5084 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5085 "")
5086
99176a91 5087(define_insn "*truncdfsf2_fpr"
cd2b37d9
RK		 5088 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5089 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
cf8e1455 5090 "TARGET_HARD_FLOAT && TARGET_FPRS"
dcac138d 5091 "frsp %0,%1"
1fd4e8c1
RK		 5092 [(set_attr "type" "fp")])
5093
455350f4
RK		 5094(define_insn "aux_truncdfsf2"
5095 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
615158e2 5096 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
cf8e1455 5097 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
455350f4
RK		 5098 "frsp %0,%1"
5099 [(set_attr "type" "fp")])
5100
a3170dc6
AH		 5101(define_expand "negsf2"
5102 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5103 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
cf8e1455 5104 "TARGET_HARD_FLOAT"
a3170dc6
AH		 5105 "")
5106
5107(define_insn "*negsf2"
cd2b37d9
RK		 5108 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5109 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
cf8e1455 5110 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5111 "fneg %0,%1"
5112 [(set_attr "type" "fp")])
5113
a3170dc6
AH		 5114(define_expand "abssf2"
5115 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5116 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
cf8e1455 5117 "TARGET_HARD_FLOAT"
a3170dc6
AH		 5118 "")
5119
5120(define_insn "*abssf2"
cd2b37d9
RK		 5121 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5122 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
cf8e1455 5123 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5124 "fabs %0,%1"
5125 [(set_attr "type" "fp")])
5126
5127(define_insn ""
cd2b37d9
RK		 5128 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5129 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
cf8e1455 5130 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5131 "fnabs %0,%1"
5132 [(set_attr "type" "fp")])
5133
ca7f5001
RK		 5134(define_expand "addsf3"
5135 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5136 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5137 (match_operand:SF 2 "gpc_reg_operand" "")))]
cf8e1455 5138 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5139 "")
5140
5141(define_insn ""
cd2b37d9
RK		 5142 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5143 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5144 (match_operand:SF 2 "gpc_reg_operand" "f")))]
cf8e1455 5145 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5146 "fadds %0,%1,%2"
ca7f5001
RK		 5147 [(set_attr "type" "fp")])
5148
5149(define_insn ""
5150 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5151 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5152 (match_operand:SF 2 "gpc_reg_operand" "f")))]
cf8e1455 5153 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5154 "{fa|fadd} %0,%1,%2"
ca7f5001
RK		 5155 [(set_attr "type" "fp")])
5156
5157(define_expand "subsf3"
5158 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5159 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5160 (match_operand:SF 2 "gpc_reg_operand" "")))]
cf8e1455 5161 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5162 "")
5163
5164(define_insn ""
5165 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5166 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5167 (match_operand:SF 2 "gpc_reg_operand" "f")))]
cf8e1455 5168 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5169 "fsubs %0,%1,%2"
1fd4e8c1
RK		 5170 [(set_attr "type" "fp")])
5171
ca7f5001 5172(define_insn ""
cd2b37d9
RK		 5173 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5174 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5175 (match_operand:SF 2 "gpc_reg_operand" "f")))]
cf8e1455 5176 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5177 "{fs|fsub} %0,%1,%2"
ca7f5001
RK		 5178 [(set_attr "type" "fp")])
5179
5180(define_expand "mulsf3"
5181 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5182 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5183 (match_operand:SF 2 "gpc_reg_operand" "")))]
cf8e1455 5184 "TARGET_HARD_FLOAT"
ca7f5001
RK		 5185 "")
5186
5187(define_insn ""
5188 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5189 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5190 (match_operand:SF 2 "gpc_reg_operand" "f")))]
cf8e1455 5191 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5192 "fmuls %0,%1,%2"
1fd4e8c1
RK		 5193 [(set_attr "type" "fp")])
5194
ca7f5001 5195(define_insn ""
cd2b37d9
RK		 5196 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5197 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5198 (match_operand:SF 2 "gpc_reg_operand" "f")))]
cf8e1455 5199 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5200 "{fm|fmul} %0,%1,%2"
0780f386 5201 [(set_attr "type" "dmul")])
1fd4e8c1 5202
ca7f5001
RK		 5203(define_expand "divsf3"
5204 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5205 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5206 (match_operand:SF 2 "gpc_reg_operand" "")))]
cf8e1455 5207 "TARGET_HARD_FLOAT"
9c78b944 5208 "")
ca7f5001
RK		 5209
5210(define_insn ""
cd2b37d9
RK		 5211 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5212 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5213 (match_operand:SF 2 "gpc_reg_operand" "f")))]
cf8e1455 5214 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5215 "fdivs %0,%1,%2"
ca7f5001
RK		 5216 [(set_attr "type" "sdiv")])
5217
5218(define_insn ""
5219 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5220 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5221 (match_operand:SF 2 "gpc_reg_operand" "f")))]
cf8e1455 5222 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
b26c8351 5223 "{fd|fdiv} %0,%1,%2"
0780f386 5224 [(set_attr "type" "ddiv")])
1fd4e8c1 5225
9c78b944
DE		 5226(define_expand "recipsf3"
5227 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5228 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5229 (match_operand:SF 2 "gpc_reg_operand" "f")]
5230 UNSPEC_FRES))]
5231 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5232 && flag_finite_math_only && !flag_trapping_math"
5233{
5234 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5235 DONE;
5236})
5237
5238(define_insn "fres"
5239 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5240 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5241 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5242 "fres %0,%1"
5243 [(set_attr "type" "fp")])
5244
1fd4e8c1 5245(define_insn ""
cd2b37d9
RK		 5246 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5247 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5248 (match_operand:SF 2 "gpc_reg_operand" "f"))
5249 (match_operand:SF 3 "gpc_reg_operand" "f")))]
cf8e1455 5250 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5251 "fmadds %0,%1,%2,%3"
ca7f5001
RK		 5252 [(set_attr "type" "fp")])
5253
5254(define_insn ""
5255 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5256 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5257 (match_operand:SF 2 "gpc_reg_operand" "f"))
5258 (match_operand:SF 3 "gpc_reg_operand" "f")))]
cf8e1455 5259 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5260 "{fma|fmadd} %0,%1,%2,%3"
cf27b467 5261 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5262
5263(define_insn ""
cd2b37d9
RK		 5264 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5265 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5266 (match_operand:SF 2 "gpc_reg_operand" "f"))
5267 (match_operand:SF 3 "gpc_reg_operand" "f")))]
cf8e1455 5268 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5269 "fmsubs %0,%1,%2,%3"
ca7f5001
RK		 5270 [(set_attr "type" "fp")])
5271
5272(define_insn ""
5273 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5274 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5275 (match_operand:SF 2 "gpc_reg_operand" "f"))
5276 (match_operand:SF 3 "gpc_reg_operand" "f")))]
cf8e1455 5277 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5278 "{fms|fmsub} %0,%1,%2,%3"
cf27b467 5279 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5280
5281(define_insn ""
cd2b37d9
RK		 5282 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5283 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5284 (match_operand:SF 2 "gpc_reg_operand" "f"))
5285 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694 5286 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
cf8e1455 5287 && HONOR_SIGNED_ZEROS (SFmode)"
16823694
GK		 5288 "fnmadds %0,%1,%2,%3"
5289 [(set_attr "type" "fp")])
5290
5291(define_insn ""
5292 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5293 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5294 (match_operand:SF 2 "gpc_reg_operand" "f"))
5295 (match_operand:SF 3 "gpc_reg_operand" "f")))]
cf8e1455 5296 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
16823694 5297 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5298 "fnmadds %0,%1,%2,%3"
ca7f5001
RK		 5299 [(set_attr "type" "fp")])
5300
5301(define_insn ""
5302 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5303 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5304 (match_operand:SF 2 "gpc_reg_operand" "f"))
5305 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
cf8e1455 5306 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5307 "{fnma|fnmadd} %0,%1,%2,%3"
cf27b467 5308 [(set_attr "type" "dmul")])
1fd4e8c1 5309
16823694
GK		 5310(define_insn ""
5311 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5312 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5313 (match_operand:SF 2 "gpc_reg_operand" "f"))
5314 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5315 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
cf8e1455 5316 && ! HONOR_SIGNED_ZEROS (SFmode)"
16823694
GK		 5317 "{fnma|fnmadd} %0,%1,%2,%3"
5318 [(set_attr "type" "dmul")])
5319
1fd4e8c1 5320(define_insn ""
cd2b37d9
RK		 5321 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5322 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5323 (match_operand:SF 2 "gpc_reg_operand" "f"))
5324 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
16823694 5325 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
cf8e1455 5326 && HONOR_SIGNED_ZEROS (SFmode)"
16823694
GK		 5327 "fnmsubs %0,%1,%2,%3"
5328 [(set_attr "type" "fp")])
5329
5330(define_insn ""
5331 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5332 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5333 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5334 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5335 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
cf8e1455 5336 && ! HONOR_SIGNED_ZEROS (SFmode)"
b26c8351 5337 "fnmsubs %0,%1,%2,%3"
ca7f5001
RK		 5338 [(set_attr "type" "fp")])
5339
5340(define_insn ""
5341 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5342 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5343 (match_operand:SF 2 "gpc_reg_operand" "f"))
5344 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
cf8e1455 5345 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
b26c8351 5346 "{fnms|fnmsub} %0,%1,%2,%3"
cf27b467 5347 [(set_attr "type" "dmul")])
1fd4e8c1 5348
16823694
GK		 5349(define_insn ""
5350 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5351 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5352 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5353 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5354 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
cf8e1455 5355 && ! HONOR_SIGNED_ZEROS (SFmode)"
16823694 5356 "{fnms|fnmsub} %0,%1,%2,%3"
9c6fdb46 5357 [(set_attr "type" "dmul")])
16823694 5358
ca7f5001
RK		 5359(define_expand "sqrtsf2"
5360 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5361 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
cf8e1455 5362 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5363 "")
5364
5365(define_insn ""
5366 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5367 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
cf8e1455 5368 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5369 "fsqrts %0,%1"
5370 [(set_attr "type" "ssqrt")])
5371
5372(define_insn ""
5373 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5374 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
cf8e1455 5375 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5376 "fsqrt %0,%1"
5377 [(set_attr "type" "dsqrt")])
5378
9c78b944
DE		 5379(define_expand "rsqrtsf2"
5380 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5381 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5382 UNSPEC_RSQRT))]
5383 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5384 && flag_finite_math_only && !flag_trapping_math"
5385{
5386 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5387 DONE;
5388})
5389
5390(define_insn "*rsqrt_internal1"
5391 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5392 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5393 UNSPEC_RSQRT))]
5394 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5395 "frsqrte %0,%1"
5396 [(set_attr "type" "fp")])
5397
0530bc70
AP		 5398(define_expand "copysignsf3"
5399 [(set (match_dup 3)
5400 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5401 (set (match_dup 4)
5402 (neg:SF (abs:SF (match_dup 1))))
5403 (set (match_operand:SF 0 "gpc_reg_operand" "")
5404 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5405 (match_dup 5))
5406 (match_dup 3)
5407 (match_dup 4)))]
cf8e1455 5408 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
bb8df8a6 5409 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
0530bc70
AP		 5410 {
5411 operands[3] = gen_reg_rtx (SFmode);
5412 operands[4] = gen_reg_rtx (SFmode);
5413 operands[5] = CONST0_RTX (SFmode);
5414 })
5415
5416(define_expand "copysigndf3"
5417 [(set (match_dup 3)
5418 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5419 (set (match_dup 4)
5420 (neg:DF (abs:DF (match_dup 1))))
5421 (set (match_operand:DF 0 "gpc_reg_operand" "")
5422 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5423 (match_dup 5))
5424 (match_dup 3)
5425 (match_dup 4)))]
cf8e1455 5426 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
0530bc70
AP		 5427 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5428 {
5429 operands[3] = gen_reg_rtx (DFmode);
5430 operands[4] = gen_reg_rtx (DFmode);
5431 operands[5] = CONST0_RTX (DFmode);
5432 })
5433
94d7001a
RK		 5434;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5435;; fsel instruction and some auxiliary computations. Then we just have a
5436;; single DEFINE_INSN for fsel and the define_splits to make them if made by
8e871c05 5437;; combine.
7ae4d8d4 5438(define_expand "smaxsf3"
8e871c05 5439 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5440 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5441 (match_operand:SF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5442 (match_dup 1)
5443 (match_dup 2)))]
cf8e1455 5444 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5445 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
2f607b94 5446
7ae4d8d4 5447(define_expand "sminsf3"
50a0b056
GK		 5448 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5449 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5450 (match_operand:SF 2 "gpc_reg_operand" ""))
5451 (match_dup 2)
5452 (match_dup 1)))]
cf8e1455 5453 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5454 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
2f607b94 5455
8e871c05
RK		 5456(define_split
5457 [(set (match_operand:SF 0 "gpc_reg_operand" "")
50a0b056
GK		 5458 (match_operator:SF 3 "min_max_operator"
5459 [(match_operand:SF 1 "gpc_reg_operand" "")
5460 (match_operand:SF 2 "gpc_reg_operand" "")]))]
cf8e1455 5461 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056
GK		 5462 [(const_int 0)]
5463 "
6ae08853 5464{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5465 operands[1], operands[2]);
5466 DONE;
5467}")
2f607b94 5468
a3170dc6
AH		 5469(define_expand "movsicc"
5470 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5471 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5472 (match_operand:SI 2 "gpc_reg_operand" "")
5473 (match_operand:SI 3 "gpc_reg_operand" "")))]
5474 "TARGET_ISEL"
5475 "
5476{
5477 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5478 DONE;
5479 else
5480 FAIL;
5481}")
5482
5483;; We use the BASE_REGS for the isel input operands because, if rA is
5484;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5485;; because we may switch the operands and rB may end up being rA.
5486;;
5487;; We need 2 patterns: an unsigned and a signed pattern. We could
5488;; leave out the mode in operand 4 and use one pattern, but reload can
5489;; change the mode underneath our feet and then gets confused trying
5490;; to reload the value.
5491(define_insn "isel_signed"
5492 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5493 (if_then_else:SI
5494 (match_operator 1 "comparison_operator"
5495 [(match_operand:CC 4 "cc_reg_operand" "y")
5496 (const_int 0)])
5497 (match_operand:SI 2 "gpc_reg_operand" "b")
5498 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5499 "TARGET_ISEL"
5500 "*
5501{ return output_isel (operands); }"
5502 [(set_attr "length" "4")])
5503
5504(define_insn "isel_unsigned"
5505 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5506 (if_then_else:SI
5507 (match_operator 1 "comparison_operator"
5508 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5509 (const_int 0)])
5510 (match_operand:SI 2 "gpc_reg_operand" "b")
5511 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5512 "TARGET_ISEL"
5513 "*
5514{ return output_isel (operands); }"
5515 [(set_attr "length" "4")])
5516
94d7001a 5517(define_expand "movsfcc"
0ad91047 5518 [(set (match_operand:SF 0 "gpc_reg_operand" "")
94d7001a 5519 (if_then_else:SF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5520 (match_operand:SF 2 "gpc_reg_operand" "")
5521 (match_operand:SF 3 "gpc_reg_operand" "")))]
cf8e1455 5522 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5523 "
5524{
50a0b056
GK		 5525 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5526 DONE;
94d7001a 5527 else
50a0b056 5528 FAIL;
94d7001a 5529}")
d56d506a 5530
50a0b056 5531(define_insn "*fselsfsf4"
8e871c05
RK		 5532 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5533 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5534 (match_operand:SF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5535 (match_operand:SF 2 "gpc_reg_operand" "f")
5536 (match_operand:SF 3 "gpc_reg_operand" "f")))]
cf8e1455 5537 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 5538 "fsel %0,%1,%2,%3"
5539 [(set_attr "type" "fp")])
2f607b94 5540
50a0b056 5541(define_insn "*fseldfsf4"
94d7001a
RK		 5542 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5543 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
d365ba42 5544 (match_operand:DF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5545 (match_operand:SF 2 "gpc_reg_operand" "f")
5546 (match_operand:SF 3 "gpc_reg_operand" "f")))]
cf8e1455 5547 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5548 "fsel %0,%1,%2,%3"
5549 [(set_attr "type" "fp")])
d56d506a 5550
7a2f7870
AH		 5551(define_expand "negdf2"
5552 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5553 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
cf8e1455 5554 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5555 "")
5556
99176a91 5557(define_insn "*negdf2_fpr"
cd2b37d9
RK		 5558 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5559 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
cf8e1455 5560 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5561 "fneg %0,%1"
5562 [(set_attr "type" "fp")])
5563
7a2f7870
AH		 5564(define_expand "absdf2"
5565 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5566 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
cf8e1455 5567 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5568 "")
5569
99176a91 5570(define_insn "*absdf2_fpr"
cd2b37d9
RK		 5571 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5572 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
cf8e1455 5573 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5574 "fabs %0,%1"
5575 [(set_attr "type" "fp")])
5576
99176a91 5577(define_insn "*nabsdf2_fpr"
cd2b37d9
RK		 5578 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5579 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
cf8e1455 5580 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 5581 "fnabs %0,%1"
5582 [(set_attr "type" "fp")])
5583
7a2f7870
AH		 5584(define_expand "adddf3"
5585 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5586 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5587 (match_operand:DF 2 "gpc_reg_operand" "")))]
cf8e1455 5588 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5589 "")
5590
99176a91 5591(define_insn "*adddf3_fpr"
cd2b37d9
RK		 5592 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5593 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5594 (match_operand:DF 2 "gpc_reg_operand" "f")))]
cf8e1455 5595 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5596 "{fa|fadd} %0,%1,%2"
1fd4e8c1
RK		 5597 [(set_attr "type" "fp")])
5598
7a2f7870
AH		 5599(define_expand "subdf3"
5600 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5601 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5602 (match_operand:DF 2 "gpc_reg_operand" "")))]
cf8e1455 5603 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5604 "")
5605
99176a91 5606(define_insn "*subdf3_fpr"
cd2b37d9
RK		 5607 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5608 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5609 (match_operand:DF 2 "gpc_reg_operand" "f")))]
cf8e1455 5610 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5611 "{fs|fsub} %0,%1,%2"
1fd4e8c1
RK		 5612 [(set_attr "type" "fp")])
5613
7a2f7870
AH		 5614(define_expand "muldf3"
5615 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5616 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5617 (match_operand:DF 2 "gpc_reg_operand" "")))]
cf8e1455 5618 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
7a2f7870
AH		 5619 "")
5620
99176a91 5621(define_insn "*muldf3_fpr"
cd2b37d9
RK		 5622 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5623 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5624 (match_operand:DF 2 "gpc_reg_operand" "f")))]
cf8e1455 5625 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5626 "{fm|fmul} %0,%1,%2"
cfb557c4 5627 [(set_attr "type" "dmul")])
1fd4e8c1 5628
7a2f7870
AH		 5629(define_expand "divdf3"
5630 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5631 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5632 (match_operand:DF 2 "gpc_reg_operand" "")))]
cf8e1455 5633 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
9c78b944 5634 "")
7a2f7870 5635
99176a91 5636(define_insn "*divdf3_fpr"
cd2b37d9
RK		 5637 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5638 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5639 (match_operand:DF 2 "gpc_reg_operand" "f")))]
cf8e1455 5640 "TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001 5641 "{fd|fdiv} %0,%1,%2"
cfb557c4 5642 [(set_attr "type" "ddiv")])
1fd4e8c1 5643
9c78b944
DE		 5644(define_expand "recipdf3"
5645 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5646 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")
5647 (match_operand:DF 2 "gpc_reg_operand" "f")]
5648 UNSPEC_FRES))]
5649 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
5650 && flag_finite_math_only && !flag_trapping_math"
5651{
5652 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5653 DONE;
5654})
5655
5656(define_insn "fred"
5657 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5658 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5659 "TARGET_POPCNTB && flag_finite_math_only"
5660 "fre %0,%1"
5661 [(set_attr "type" "fp")])
5662
1fd4e8c1 5663(define_insn ""
cd2b37d9
RK		 5664 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5665 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5666 (match_operand:DF 2 "gpc_reg_operand" "f"))
5667 (match_operand:DF 3 "gpc_reg_operand" "f")))]
cf8e1455 5668 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 5669 "{fma|fmadd} %0,%1,%2,%3"
cfb557c4 5670 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5671
5672(define_insn ""
cd2b37d9
RK		 5673 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5674 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5675 (match_operand:DF 2 "gpc_reg_operand" "f"))
5676 (match_operand:DF 3 "gpc_reg_operand" "f")))]
cf8e1455 5677 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
ca7f5001 5678 "{fms|fmsub} %0,%1,%2,%3"
cfb557c4 5679 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5680
5681(define_insn ""
cd2b37d9
RK		 5682 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5683 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5684 (match_operand:DF 2 "gpc_reg_operand" "f"))
5685 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
cf8e1455 5686 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
16823694
GK		 5687 && HONOR_SIGNED_ZEROS (DFmode)"
5688 "{fnma|fnmadd} %0,%1,%2,%3"
5689 [(set_attr "type" "dmul")])
5690
5691(define_insn ""
5692 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5693 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5694 (match_operand:DF 2 "gpc_reg_operand" "f"))
5695 (match_operand:DF 3 "gpc_reg_operand" "f")))]
cf8e1455 5696 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
16823694 5697 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5698 "{fnma|fnmadd} %0,%1,%2,%3"
cfb557c4 5699 [(set_attr "type" "dmul")])
1fd4e8c1
RK		 5700
5701(define_insn ""
cd2b37d9
RK		 5702 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5703 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5704 (match_operand:DF 2 "gpc_reg_operand" "f"))
5705 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
cf8e1455 5706 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
16823694
GK		 5707 && HONOR_SIGNED_ZEROS (DFmode)"
5708 "{fnms|fnmsub} %0,%1,%2,%3"
5709 [(set_attr "type" "dmul")])
5710
5711(define_insn ""
5712 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5713 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5714 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5715 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
cf8e1455 5716 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
16823694 5717 && ! HONOR_SIGNED_ZEROS (DFmode)"
ca7f5001 5718 "{fnms|fnmsub} %0,%1,%2,%3"
cfb557c4 5719 [(set_attr "type" "dmul")])
ca7f5001
RK		 5720
5721(define_insn "sqrtdf2"
5722 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5723 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
cf8e1455 5724 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
ca7f5001
RK		 5725 "fsqrt %0,%1"
5726 [(set_attr "type" "dsqrt")])
b77dfefc 5727
50a0b056 5728;; The conditional move instructions allow us to perform max and min
6ae08853 5729;; operations even when
b77dfefc 5730
7ae4d8d4 5731(define_expand "smaxdf3"
8e871c05 5732 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5733 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5734 (match_operand:DF 2 "gpc_reg_operand" ""))
8e871c05
RK		 5735 (match_dup 1)
5736 (match_dup 2)))]
cf8e1455 5737 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5738 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
b77dfefc 5739
7ae4d8d4 5740(define_expand "smindf3"
50a0b056
GK		 5741 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5742 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5743 (match_operand:DF 2 "gpc_reg_operand" ""))
5744 (match_dup 2)
5745 (match_dup 1)))]
cf8e1455 5746 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056 5747 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
b77dfefc 5748
8e871c05
RK		 5749(define_split
5750 [(set (match_operand:DF 0 "gpc_reg_operand" "")
50a0b056
GK		 5751 (match_operator:DF 3 "min_max_operator"
5752 [(match_operand:DF 1 "gpc_reg_operand" "")
5753 (match_operand:DF 2 "gpc_reg_operand" "")]))]
cf8e1455 5754 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
50a0b056
GK		 5755 [(const_int 0)]
5756 "
6ae08853 5757{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
50a0b056
GK		 5758 operands[1], operands[2]);
5759 DONE;
5760}")
b77dfefc 5761
94d7001a 5762(define_expand "movdfcc"
0ad91047 5763 [(set (match_operand:DF 0 "gpc_reg_operand" "")
94d7001a 5764 (if_then_else:DF (match_operand 1 "comparison_operator" "")
0ad91047
DE		 5765 (match_operand:DF 2 "gpc_reg_operand" "")
5766 (match_operand:DF 3 "gpc_reg_operand" "")))]
cf8e1455 5767 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
94d7001a
RK		 5768 "
5769{
50a0b056
GK		 5770 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5771 DONE;
94d7001a 5772 else
50a0b056 5773 FAIL;
94d7001a 5774}")
d56d506a 5775
50a0b056 5776(define_insn "*fseldfdf4"
8e871c05
RK		 5777 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5778 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
50a0b056 5779 (match_operand:DF 4 "zero_fp_constant" "F"))
8e871c05
RK		 5780 (match_operand:DF 2 "gpc_reg_operand" "f")
5781 (match_operand:DF 3 "gpc_reg_operand" "f")))]
cf8e1455 5782 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
8e871c05
RK		 5783 "fsel %0,%1,%2,%3"
5784 [(set_attr "type" "fp")])
d56d506a 5785
50a0b056 5786(define_insn "*fselsfdf4"
94d7001a
RK		 5787 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5788 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
50a0b056 5789 (match_operand:SF 4 "zero_fp_constant" "F"))
94d7001a
RK		 5790 (match_operand:DF 2 "gpc_reg_operand" "f")
5791 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5792 "TARGET_PPC_GFXOPT"
5793 "fsel %0,%1,%2,%3"
5794 [(set_attr "type" "fp")])
1fd4e8c1 5795\f
d095928f
AH		 5796;; Conversions to and from floating-point.
5797
5798(define_expand "fixuns_truncsfsi2"
5799 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5800 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
cf8e1455 5801 "TARGET_HARD_FLOAT && !TARGET_FPRS"
d095928f
AH		 5802 "")
5803
5804(define_expand "fix_truncsfsi2"
5805 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5806 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
cf8e1455 5807 "TARGET_HARD_FLOAT && !TARGET_FPRS"
d095928f
AH		 5808 "")
5809
9ebbca7d
GK		 5810; For each of these conversions, there is a define_expand, a define_insn
5811; with a '#' template, and a define_split (with C code). The idea is
5812; to allow constant folding with the template of the define_insn,
5813; then to have the insns split later (between sched1 and final).
5814
1fd4e8c1 5815(define_expand "floatsidf2"
802a0058
MM		 5816 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5817 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5818 (use (match_dup 2))
5819 (use (match_dup 3))
208c89ce 5820 (clobber (match_dup 4))
a7df97e6 5821 (clobber (match_dup 5))
9ebbca7d 5822 (clobber (match_dup 6))])]
cf8e1455 5823 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5824 "
5825{
99176a91
AH		 5826 if (TARGET_E500_DOUBLE)
5827 {
5828 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5829 DONE;
5830 }
05d49501
AM		 5831 if (TARGET_POWERPC64)
5832 {
f369bbb1
AP		 5833 rtx x = convert_to_mode (DImode, operands[1], 0);
5834 emit_insn (gen_floatdidf2 (operands[0], x));
05d49501
AM		 5835 DONE;
5836 }
5837
802a0058 5838 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5839 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
9ebbca7d
GK		 5840 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5841 operands[5] = gen_reg_rtx (DFmode);
5842 operands[6] = gen_reg_rtx (SImode);
1fd4e8c1
RK		 5843}")
5844
230215f5 5845(define_insn_and_split "*floatsidf2_internal"
802a0058
MM		 5846 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5847 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5848 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5849 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
b0d6c7d8 5850 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6f9c81f5
DJ		 5851 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5852 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
cf8e1455 5853 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5854 "#"
b3a13419 5855 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
230215f5 5856 [(pc)]
208c89ce
MM		 5857 "
5858{
9ebbca7d 5859 rtx lowword, highword;
230215f5
GK		 5860 gcc_assert (MEM_P (operands[4]));
5861 highword = adjust_address (operands[4], SImode, 0);
5862 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d
GK		 5863 if (! WORDS_BIG_ENDIAN)
5864 {
5865 rtx tmp;
5866 tmp = highword; highword = lowword; lowword = tmp;
5867 }
5868
6ae08853 5869 emit_insn (gen_xorsi3 (operands[6], operands[1],
9ebbca7d 5870 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
230215f5
GK		 5871 emit_move_insn (lowword, operands[6]);
5872 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 5873 emit_move_insn (operands[5], operands[4]);
5874 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5875 DONE;
230215f5
GK		 5876}"
5877 [(set_attr "length" "24")])
802a0058 5878
a3170dc6
AH		 5879(define_expand "floatunssisf2"
5880 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5881 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
cf8e1455 5882 "TARGET_HARD_FLOAT && !TARGET_FPRS"
a3170dc6
AH		 5883 "")
5884
802a0058
MM		 5885(define_expand "floatunssidf2"
5886 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5887 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5888 (use (match_dup 2))
5889 (use (match_dup 3))
a7df97e6 5890 (clobber (match_dup 4))
9ebbca7d 5891 (clobber (match_dup 5))])]
cf8e1455 5892 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5893 "
5894{
99176a91
AH		 5895 if (TARGET_E500_DOUBLE)
5896 {
5897 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5898 DONE;
5899 }
05d49501
AM		 5900 if (TARGET_POWERPC64)
5901 {
f369bbb1
AP		 5902 rtx x = convert_to_mode (DImode, operands[1], 1);
5903 emit_insn (gen_floatdidf2 (operands[0], x));
05d49501
AM		 5904 DONE;
5905 }
5906
802a0058 5907 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5692c7bc 5908 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
9ebbca7d
GK		 5909 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5910 operands[5] = gen_reg_rtx (DFmode);
1fd4e8c1
RK		 5911}")
5912
230215f5 5913(define_insn_and_split "*floatunssidf2_internal"
802a0058
MM		 5914 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5915 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5916 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5917 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
b0d6c7d8 5918 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6f9c81f5 5919 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
cf8e1455 5920 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5921 "#"
b3a13419 5922 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[4]))"
230215f5 5923 [(pc)]
9ebbca7d 5924 "
802a0058 5925{
9ebbca7d 5926 rtx lowword, highword;
230215f5
GK		 5927 gcc_assert (MEM_P (operands[4]));
5928 highword = adjust_address (operands[4], SImode, 0);
5929 lowword = adjust_address (operands[4], SImode, 4);
9ebbca7d 5930 if (! WORDS_BIG_ENDIAN)
f6968f59 5931 {
9ebbca7d
GK		 5932 rtx tmp;
5933 tmp = highword; highword = lowword; lowword = tmp;
f6968f59 5934 }
802a0058 5935
230215f5
GK		 5936 emit_move_insn (lowword, operands[1]);
5937 emit_move_insn (highword, operands[2]);
9ebbca7d
GK		 5938 emit_move_insn (operands[5], operands[4]);
5939 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5940 DONE;
230215f5
GK		 5941}"
5942 [(set_attr "length" "20")])
1fd4e8c1 5943
1fd4e8c1 5944(define_expand "fix_truncdfsi2"
045a8eb3 5945 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
802a0058
MM		 5946 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5947 (clobber (match_dup 2))
9ebbca7d 5948 (clobber (match_dup 3))])]
99176a91 5949 "(TARGET_POWER2 || TARGET_POWERPC)
cf8e1455 5950 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
1fd4e8c1
RK		 5951 "
5952{
99176a91
AH		 5953 if (TARGET_E500_DOUBLE)
5954 {
5955 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5956 DONE;
5957 }
802a0058 5958 operands[2] = gen_reg_rtx (DImode);
44cd321e
PS		 5959 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
5960 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
5961 {
5962 operands[3] = gen_reg_rtx (DImode);
5963 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
5964 operands[2], operands[3]));
5965 DONE;
5966 }
da4c340c
GK		 5967 if (TARGET_PPC_GFXOPT)
5968 {
5969 rtx orig_dest = operands[0];
045a8eb3 5970 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
da4c340c
GK		 5971 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5972 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5973 operands[2]));
5974 if (operands[0] != orig_dest)
5975 emit_move_insn (orig_dest, operands[0]);
5976 DONE;
5977 }
9ebbca7d 5978 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
1fd4e8c1
RK		 5979}")
5980
da4c340c 5981(define_insn_and_split "*fix_truncdfsi2_internal"
802a0058
MM		 5982 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5983 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
e3485bbc 5984 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
b0d6c7d8 5985 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
cf8e1455 5986 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
802a0058 5987 "#"
b3a13419 5988 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[3]))"
da4c340c 5989 [(pc)]
9ebbca7d 5990 "
802a0058 5991{
9ebbca7d 5992 rtx lowword;
230215f5
GK		 5993 gcc_assert (MEM_P (operands[3]));
5994 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
802a0058 5995
9ebbca7d
GK		 5996 emit_insn (gen_fctiwz (operands[2], operands[1]));
5997 emit_move_insn (operands[3], operands[2]);
230215f5 5998 emit_move_insn (operands[0], lowword);
9ebbca7d 5999 DONE;
da4c340c
GK		 6000}"
6001 [(set_attr "length" "16")])
6002
6003(define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6004 [(set (match_operand:SI 0 "memory_operand" "=Z")
6005 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6006 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
cf8e1455 6007 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
da4c340c
GK		 6008 && TARGET_PPC_GFXOPT"
6009 "#"
6010 "&& 1"
6011 [(pc)]
6012 "
6013{
6014 emit_insn (gen_fctiwz (operands[2], operands[1]));
6015 emit_insn (gen_stfiwx (operands[0], operands[2]));
6016 DONE;
6017}"
6018 [(set_attr "length" "16")])
802a0058 6019
44cd321e
PS		 6020(define_insn_and_split "fix_truncdfsi2_mfpgpr"
6021 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6022 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
6023 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
6024 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
cf8e1455 6025 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS"
44cd321e
PS		 6026 "#"
6027 "&& 1"
6028 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6029 (set (match_dup 3) (match_dup 2))
6030 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6031 ""
6032 [(set_attr "length" "12")])
6033
615158e2 6034; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
9ebbca7d
GK		 6035; rather than (set (subreg:SI (reg)) (fix:SI ...))
6036; because the first makes it clear that operand 0 is not live
6037; before the instruction.
6038(define_insn "fctiwz"
da4c340c 6039 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
615158e2
JJ		 6040 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
6041 UNSPEC_FCTIWZ))]
cf8e1455 6042 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
a260abc9
DE		 6043 "{fcirz|fctiwz} %0,%1"
6044 [(set_attr "type" "fp")])
6045
9719f3b7
DE		 6046(define_insn "btruncdf2"
6047 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6048 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
cf8e1455 6049 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
9719f3b7
DE		 6050 "friz %0,%1"
6051 [(set_attr "type" "fp")])
6052
6053(define_insn "btruncsf2"
6054 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6055 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
cf8e1455 6056 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6057 "friz %0,%1"
9719f3b7
DE		 6058 [(set_attr "type" "fp")])
6059
6060(define_insn "ceildf2"
6061 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6062 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
cf8e1455 6063 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
9719f3b7
DE		 6064 "frip %0,%1"
6065 [(set_attr "type" "fp")])
6066
6067(define_insn "ceilsf2"
833126ad 6068 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9719f3b7 6069 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
cf8e1455 6070 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6071 "frip %0,%1"
9719f3b7
DE		 6072 [(set_attr "type" "fp")])
6073
6074(define_insn "floordf2"
6075 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6076 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
cf8e1455 6077 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
9719f3b7
DE		 6078 "frim %0,%1"
6079 [(set_attr "type" "fp")])
6080
6081(define_insn "floorsf2"
6082 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6083 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
cf8e1455 6084 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6085 "frim %0,%1"
9719f3b7
DE		 6086 [(set_attr "type" "fp")])
6087
6088(define_insn "rounddf2"
6089 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6090 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
cf8e1455 6091 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
9719f3b7
DE		 6092 "frin %0,%1"
6093 [(set_attr "type" "fp")])
6094
6095(define_insn "roundsf2"
6096 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6097 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
cf8e1455 6098 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
833126ad 6099 "frin %0,%1"
9719f3b7
DE		 6100 [(set_attr "type" "fp")])
6101
da4c340c
GK		 6102; An UNSPEC is used so we don't have to support SImode in FP registers.
6103(define_insn "stfiwx"
6104 [(set (match_operand:SI 0 "memory_operand" "=Z")
6105 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
6106 UNSPEC_STFIWX))]
6107 "TARGET_PPC_GFXOPT"
6108 "stfiwx %1,%y0"
6109 [(set_attr "type" "fpstore")])
6110
a3170dc6
AH		 6111(define_expand "floatsisf2"
6112 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6113 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
cf8e1455 6114 "TARGET_HARD_FLOAT && !TARGET_FPRS"
a3170dc6
AH		 6115 "")
6116
a473029f
RK		 6117(define_insn "floatdidf2"
6118 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
94e98316 6119 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))]
cf8e1455 6120 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 6121 "fcfid %0,%1"
6122 [(set_attr "type" "fp")])
6123
6124(define_insn "fix_truncdfdi2"
94e98316 6125 [(set (match_operand:DI 0 "gpc_reg_operand" "=!f#r")
a473029f 6126 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
cf8e1455 6127 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
a473029f
RK		 6128 "fctidz %0,%1"
6129 [(set_attr "type" "fp")])
ea112fc4 6130
678b7733
AM		 6131(define_expand "floatdisf2"
6132 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6133 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
cf8e1455 6134 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 6135 "
6136{
994cf173 6137 rtx val = operands[1];
678b7733
AM		 6138 if (!flag_unsafe_math_optimizations)
6139 {
6140 rtx label = gen_label_rtx ();
994cf173
AM		 6141 val = gen_reg_rtx (DImode);
6142 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
678b7733
AM		 6143 emit_label (label);
6144 }
994cf173 6145 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
678b7733
AM		 6146 DONE;
6147}")
6148
6149;; This is not IEEE compliant if rounding mode is "round to nearest".
6150;; If the DI->DF conversion is inexact, then it's possible to suffer
6151;; from double rounding.
6152(define_insn_and_split "floatdisf2_internal1"
ea112fc4 6153 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
94e98316 6154 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!f#r")))
ea112fc4 6155 (clobber (match_scratch:DF 2 "=f"))]
cf8e1455 6156 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
ea112fc4
DE		 6157 "#"
6158 "&& reload_completed"
6159 [(set (match_dup 2)
6160 (float:DF (match_dup 1)))
6161 (set (match_dup 0)
6162 (float_truncate:SF (match_dup 2)))]
6163 "")
678b7733
AM		 6164
6165;; Twiddles bits to avoid double rounding.
b6d08ca1 6166;; Bits that might be truncated when converting to DFmode are replaced
678b7733
AM		 6167;; by a bit that won't be lost at that stage, but is below the SFmode
6168;; rounding position.
6169(define_expand "floatdisf2_internal2"
994cf173
AM		 6170 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6171 (const_int 53)))
6172 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6173 (const_int 2047)))
6174 (clobber (scratch:CC))])
6175 (set (match_dup 3) (plus:DI (match_dup 3)
6176 (const_int 1)))
6177 (set (match_dup 0) (plus:DI (match_dup 0)
6178 (const_int 2047)))
6179 (set (match_dup 4) (compare:CCUNS (match_dup 3)
c22e62a6 6180 (const_int 2)))
994cf173
AM		 6181 (set (match_dup 0) (ior:DI (match_dup 0)
6182 (match_dup 1)))
6183 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6184 (const_int -2048)))
6185 (clobber (scratch:CC))])
6186 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6187 (label_ref (match_operand:DI 2 "" ""))
678b7733 6188 (pc)))
994cf173 6189 (set (match_dup 0) (match_dup 1))]
cf8e1455 6190 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
678b7733
AM		 6191 "
6192{
678b7733 6193 operands[3] = gen_reg_rtx (DImode);
994cf173 6194 operands[4] = gen_reg_rtx (CCUNSmode);
678b7733 6195}")
1fd4e8c1
RK		 6196\f
6197;; Define the DImode operations that can be done in a small number
a6ec530c
RK		 6198;; of instructions. The & constraints are to prevent the register
6199;; allocator from allocating registers that overlap with the inputs
6200;; (for example, having an input in 7,8 and an output in 6,7). We
38e01259 6201;; also allow for the output being the same as one of the inputs.
a6ec530c 6202
266eb58a 6203(define_insn "*adddi3_noppc64"
a6ec530c
RK		 6204 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6205 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6206 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
e1f83b4d 6207 "! TARGET_POWERPC64"
0f645302
MM		 6208 "*
6209{
6210 if (WORDS_BIG_ENDIAN)
6211 return (GET_CODE (operands[2])) != CONST_INT
6212 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6213 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6214 else
6215 return (GET_CODE (operands[2])) != CONST_INT
6216 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6217 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6218}"
943c15ed
DE		 6219 [(set_attr "type" "two")
6220 (set_attr "length" "8")])
1fd4e8c1 6221
266eb58a 6222(define_insn "*subdi3_noppc64"
e7e5df70
RK		 6223 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6224 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6225 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
266eb58a 6226 "! TARGET_POWERPC64"
5502823b
RK		 6227 "*
6228{
0f645302
MM		 6229 if (WORDS_BIG_ENDIAN)
6230 return (GET_CODE (operands[1]) != CONST_INT)
6231 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6232 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6233 else
6234 return (GET_CODE (operands[1]) != CONST_INT)
6235 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6236 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5502823b 6237}"
943c15ed
DE		 6238 [(set_attr "type" "two")
6239 (set_attr "length" "8")])
ca7f5001 6240
266eb58a 6241(define_insn "*negdi2_noppc64"
a6ec530c
RK		 6242 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6243 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
51b8fc2c 6244 "! TARGET_POWERPC64"
5502823b
RK		 6245 "*
6246{
6247 return (WORDS_BIG_ENDIAN)
6248 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6249 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6250}"
943c15ed
DE		 6251 [(set_attr "type" "two")
6252 (set_attr "length" "8")])
ca7f5001 6253
8ffd9c51
RK		 6254(define_expand "mulsidi3"
6255 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6256 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6257 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
a2f270cc 6258 "! TARGET_POWERPC64"
8ffd9c51
RK		 6259 "
6260{
6261 if (! TARGET_POWER && ! TARGET_POWERPC)
6262 {
39403d82
DE		 6263 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6264 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6265 emit_insn (gen_mull_call ());
cf27b467 6266 if (WORDS_BIG_ENDIAN)
39403d82 6267 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
cf27b467
MM		 6268 else
6269 {
6270 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
39403d82 6271 gen_rtx_REG (SImode, 3));
cf27b467 6272 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
39403d82 6273 gen_rtx_REG (SImode, 4));
cf27b467 6274 }
8ffd9c51
RK		 6275 DONE;
6276 }
6277 else if (TARGET_POWER)
6278 {
6279 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6280 DONE;
6281 }
6282}")
deb9225a 6283
8ffd9c51 6284(define_insn "mulsidi3_mq"
cd2b37d9 6285 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8ffd9c51 6286 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
cd2b37d9 6287 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
1fd4e8c1 6288 (clobber (match_scratch:SI 3 "=q"))]
ca7f5001 6289 "TARGET_POWER"
b19003d8 6290 "mul %0,%1,%2\;mfmq %L0"
8ffd9c51
RK		 6291 [(set_attr "type" "imul")
6292 (set_attr "length" "8")])
deb9225a 6293
f192bf8b 6294(define_insn "*mulsidi3_no_mq"
425c176f 6295 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
8ffd9c51
RK		 6296 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6297 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6298 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5502823b
RK		 6299 "*
6300{
6301 return (WORDS_BIG_ENDIAN)
6302 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6303 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6304}"
8ffd9c51
RK		 6305 [(set_attr "type" "imul")
6306 (set_attr "length" "8")])
deb9225a 6307
ebedb4dd
MM		 6308(define_split
6309 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6310 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6311 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6312 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6313 [(set (match_dup 3)
6314 (truncate:SI
6315 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6316 (sign_extend:DI (match_dup 2)))
6317 (const_int 32))))
6318 (set (match_dup 4)
6319 (mult:SI (match_dup 1)
6320 (match_dup 2)))]
6321 "
6322{
6323 int endian = (WORDS_BIG_ENDIAN == 0);
6324 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6325 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6326}")
6327
f192bf8b
DE		 6328(define_expand "umulsidi3"
6329 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6330 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6331 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6332 "TARGET_POWERPC && ! TARGET_POWERPC64"
6333 "
6334{
6335 if (TARGET_POWER)
6336 {
6337 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6338 DONE;
6339 }
6340}")
6341
6342(define_insn "umulsidi3_mq"
6343 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6344 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6345 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6346 (clobber (match_scratch:SI 3 "=q"))]
6347 "TARGET_POWERPC && TARGET_POWER"
6348 "*
6349{
6350 return (WORDS_BIG_ENDIAN)
6351 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6352 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6353}"
6354 [(set_attr "type" "imul")
6355 (set_attr "length" "8")])
6356
6357(define_insn "*umulsidi3_no_mq"
8106dc08
MM		 6358 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6359 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6360 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
f192bf8b 6361 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
8106dc08
MM		 6362 "*
6363{
6364 return (WORDS_BIG_ENDIAN)
6365 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6366 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6367}"
6368 [(set_attr "type" "imul")
6369 (set_attr "length" "8")])
6370
ebedb4dd
MM		 6371(define_split
6372 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6373 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6374 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
cf27b467 6375 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
ebedb4dd
MM		 6376 [(set (match_dup 3)
6377 (truncate:SI
6378 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6379 (zero_extend:DI (match_dup 2)))
6380 (const_int 32))))
6381 (set (match_dup 4)
6382 (mult:SI (match_dup 1)
6383 (match_dup 2)))]
6384 "
6385{
6386 int endian = (WORDS_BIG_ENDIAN == 0);
6387 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6388 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6389}")
6390
8ffd9c51
RK		 6391(define_expand "smulsi3_highpart"
6392 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6393 (truncate:SI
6394 (lshiftrt:DI (mult:DI (sign_extend:DI
e42ac3de 6395 (match_operand:SI 1 "gpc_reg_operand" ""))
8ffd9c51 6396 (sign_extend:DI
e42ac3de 6397 (match_operand:SI 2 "gpc_reg_operand" "")))
8ffd9c51
RK		 6398 (const_int 32))))]
6399 ""
6400 "
6401{
6402 if (! TARGET_POWER && ! TARGET_POWERPC)
6403 {
39403d82
DE		 6404 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6405 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
fada905b 6406 emit_insn (gen_mulh_call ());
39403d82 6407 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
8ffd9c51
RK		 6408 DONE;
6409 }
6410 else if (TARGET_POWER)
6411 {
6412 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6413 DONE;
6414 }
6415}")
deb9225a 6416
8ffd9c51
RK		 6417(define_insn "smulsi3_highpart_mq"
6418 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6419 (truncate:SI
fada905b
MM		 6420 (lshiftrt:DI (mult:DI (sign_extend:DI
6421 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6422 (sign_extend:DI
6423 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51
RK		 6424 (const_int 32))))
6425 (clobber (match_scratch:SI 3 "=q"))]
6426 "TARGET_POWER"
6427 "mul %0,%1,%2"
6428 [(set_attr "type" "imul")])
deb9225a 6429
f192bf8b 6430(define_insn "*smulsi3_highpart_no_mq"
8ffd9c51
RK		 6431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6432 (truncate:SI
fada905b
MM		 6433 (lshiftrt:DI (mult:DI (sign_extend:DI
6434 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6435 (sign_extend:DI
6436 (match_operand:SI 2 "gpc_reg_operand" "r")))
8ffd9c51 6437 (const_int 32))))]
f192bf8b 6438 "TARGET_POWERPC && ! TARGET_POWER"
8ffd9c51
RK		 6439 "mulhw %0,%1,%2"
6440 [(set_attr "type" "imul")])
deb9225a 6441
f192bf8b
DE		 6442(define_expand "umulsi3_highpart"
6443 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6444 (truncate:SI
6445 (lshiftrt:DI (mult:DI (zero_extend:DI
6446 (match_operand:SI 1 "gpc_reg_operand" ""))
6447 (zero_extend:DI
6448 (match_operand:SI 2 "gpc_reg_operand" "")))
6449 (const_int 32))))]
6450 "TARGET_POWERPC"
6451 "
6452{
6453 if (TARGET_POWER)
6454 {
6455 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6456 DONE;
6457 }
6458}")
6459
6460(define_insn "umulsi3_highpart_mq"
6461 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6462 (truncate:SI
6463 (lshiftrt:DI (mult:DI (zero_extend:DI
6464 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6465 (zero_extend:DI
6466 (match_operand:SI 2 "gpc_reg_operand" "r")))
6467 (const_int 32))))
6468 (clobber (match_scratch:SI 3 "=q"))]
6469 "TARGET_POWERPC && TARGET_POWER"
6470 "mulhwu %0,%1,%2"
6471 [(set_attr "type" "imul")])
6472
6473(define_insn "*umulsi3_highpart_no_mq"
266eb58a
DE		 6474 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6475 (truncate:SI
6476 (lshiftrt:DI (mult:DI (zero_extend:DI
6477 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6478 (zero_extend:DI
6479 (match_operand:SI 2 "gpc_reg_operand" "r")))
6480 (const_int 32))))]
f192bf8b 6481 "TARGET_POWERPC && ! TARGET_POWER"
266eb58a
DE		 6482 "mulhwu %0,%1,%2"
6483 [(set_attr "type" "imul")])
6484
6485;; If operands 0 and 2 are in the same register, we have a problem. But
6486;; operands 0 and 1 (the usual case) can be in the same register. That's
6487;; why we have the strange constraints below.
6488(define_insn "ashldi3_power"
6489 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6490 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6491 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6492 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6493 "TARGET_POWER"
6494 "@
6495 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6496 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6497 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6498 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6499 [(set_attr "length" "8")])
6500
6501(define_insn "lshrdi3_power"
47ad8c61 6502 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
266eb58a
DE		 6503 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6504 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6505 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6506 "TARGET_POWER"
6507 "@
47ad8c61 6508 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
266eb58a
DE		 6509 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6510 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6511 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6512 [(set_attr "length" "8")])
6513
6514;; Shift by a variable amount is too complex to be worth open-coding. We
6515;; just handle shifts by constants.
6516(define_insn "ashrdi3_power"
7093ddee 6517 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
266eb58a
DE		 6518 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6519 (match_operand:SI 2 "const_int_operand" "M,i")))
6520 (clobber (match_scratch:SI 3 "=X,q"))]
6521 "TARGET_POWER"
6522 "@
6523 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6524 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
44cd321e
PS		 6525 [(set_attr "type" "shift")
6526 (set_attr "length" "8")])
4aa74a4f
FS		 6527
6528(define_insn "ashrdi3_no_power"
6529 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6530 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6531 (match_operand:SI 2 "const_int_operand" "M,i")))]
97727e85 6532 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
4aa74a4f
FS		 6533 "@
6534 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6535 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
943c15ed
DE		 6536 [(set_attr "type" "two,three")
6537 (set_attr "length" "8,12")])
683bdff7
FJ		 6538
6539(define_insn "*ashrdisi3_noppc64"
6540 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6ae08853 6541 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
683bdff7
FJ		 6542 (const_int 32)) 4))]
6543 "TARGET_32BIT && !TARGET_POWERPC64"
6544 "*
6545{
6546 if (REGNO (operands[0]) == REGNO (operands[1]))
6547 return \"\";
6548 else
6549 return \"mr %0,%1\";
6550}"
6ae08853 6551 [(set_attr "length" "4")])
683bdff7 6552
266eb58a
DE		 6553\f
6554;; PowerPC64 DImode operations.
6555
ea112fc4 6556(define_insn_and_split "absdi2"
266eb58a 6557 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6558 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
266eb58a
DE		 6559 (clobber (match_scratch:DI 2 "=&r,&r"))]
6560 "TARGET_POWERPC64"
ea112fc4
DE		 6561 "#"
6562 "&& reload_completed"
a260abc9 6563 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6564 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
a238cd8b 6565 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
266eb58a
DE		 6566 "")
6567
ea112fc4 6568(define_insn_and_split "*nabsdi2"
266eb58a 6569 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
ea112fc4 6570 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
266eb58a
DE		 6571 (clobber (match_scratch:DI 2 "=&r,&r"))]
6572 "TARGET_POWERPC64"
ea112fc4
DE		 6573 "#"
6574 "&& reload_completed"
a260abc9 6575 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
266eb58a 6576 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
19ba8161 6577 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
266eb58a
DE		 6578 "")
6579
266eb58a 6580(define_insn "muldi3"
c9692532
DE		 6581 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6582 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6583 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
266eb58a 6584 "TARGET_POWERPC64"
c9692532
DE		 6585 "@
6586 mulld %0,%1,%2
6587 mulli %0,%1,%2"
6588 [(set (attr "type")
6589 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6590 (const_string "imul3")
6591 (match_operand:SI 2 "short_cint_operand" "")
6592 (const_string "imul2")]
6593 (const_string "lmul")))])
266eb58a 6594
9259f3b0
DE		 6595(define_insn "*muldi3_internal1"
6596 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6597 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6598 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6599 (const_int 0)))
6600 (clobber (match_scratch:DI 3 "=r,r"))]
6601 "TARGET_POWERPC64"
6602 "@
6603 mulld. %3,%1,%2
6604 #"
6605 [(set_attr "type" "lmul_compare")
6606 (set_attr "length" "4,8")])
6607
6608(define_split
6609 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6610 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6611 (match_operand:DI 2 "gpc_reg_operand" ""))
6612 (const_int 0)))
6613 (clobber (match_scratch:DI 3 ""))]
6614 "TARGET_POWERPC64 && reload_completed"
6615 [(set (match_dup 3)
6616 (mult:DI (match_dup 1) (match_dup 2)))
6617 (set (match_dup 0)
6618 (compare:CC (match_dup 3)
6619 (const_int 0)))]
6620 "")
6621
6622(define_insn "*muldi3_internal2"
6623 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6624 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6625 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6626 (const_int 0)))
6627 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6628 (mult:DI (match_dup 1) (match_dup 2)))]
6629 "TARGET_POWERPC64"
6630 "@
6631 mulld. %0,%1,%2
6632 #"
6633 [(set_attr "type" "lmul_compare")
6634 (set_attr "length" "4,8")])
6635
6636(define_split
6637 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6638 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6639 (match_operand:DI 2 "gpc_reg_operand" ""))
6640 (const_int 0)))
6641 (set (match_operand:DI 0 "gpc_reg_operand" "")
6642 (mult:DI (match_dup 1) (match_dup 2)))]
6643 "TARGET_POWERPC64 && reload_completed"
6644 [(set (match_dup 0)
6645 (mult:DI (match_dup 1) (match_dup 2)))
6646 (set (match_dup 3)
6647 (compare:CC (match_dup 0)
6648 (const_int 0)))]
6649 "")
6650
266eb58a
DE		 6651(define_insn "smuldi3_highpart"
6652 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6653 (truncate:DI
6654 (lshiftrt:TI (mult:TI (sign_extend:TI
6655 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6656 (sign_extend:TI
6657 (match_operand:DI 2 "gpc_reg_operand" "r")))
6658 (const_int 64))))]
6659 "TARGET_POWERPC64"
6660 "mulhd %0,%1,%2"
3cb999d8 6661 [(set_attr "type" "lmul")])
266eb58a
DE		 6662
6663(define_insn "umuldi3_highpart"
6664 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6665 (truncate:DI
6666 (lshiftrt:TI (mult:TI (zero_extend:TI
6667 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6668 (zero_extend:TI
6669 (match_operand:DI 2 "gpc_reg_operand" "r")))
6670 (const_int 64))))]
6671 "TARGET_POWERPC64"
6672 "mulhdu %0,%1,%2"
3cb999d8 6673 [(set_attr "type" "lmul")])
266eb58a 6674
266eb58a 6675(define_insn "rotldi3"
44cd321e
PS		 6676 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6677 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6678 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 6679 "TARGET_POWERPC64"
44cd321e
PS		 6680 "@
6681 rldcl %0,%1,%2,0
6682 rldicl %0,%1,%H2,0"
6683 [(set_attr "type" "var_shift_rotate,integer")])
266eb58a 6684
a260abc9 6685(define_insn "*rotldi3_internal2"
44cd321e
PS		 6686 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6687 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6688 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6689 (const_int 0)))
44cd321e 6690 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6691 "TARGET_64BIT"
9ebbca7d 6692 "@
44cd321e
PS		 6693 rldcl. %3,%1,%2,0
6694 rldicl. %3,%1,%H2,0
6695 #
9ebbca7d 6696 #"
44cd321e
PS		 6697 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6698 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6699
6700(define_split
6701 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6702 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6703 (match_operand:DI 2 "reg_or_cint_operand" ""))
6704 (const_int 0)))
6705 (clobber (match_scratch:DI 3 ""))]
6706 "TARGET_POWERPC64 && reload_completed"
6707 [(set (match_dup 3)
6708 (rotate:DI (match_dup 1) (match_dup 2)))
6709 (set (match_dup 0)
6710 (compare:CC (match_dup 3)
6711 (const_int 0)))]
6712 "")
266eb58a 6713
a260abc9 6714(define_insn "*rotldi3_internal3"
44cd321e
PS		 6715 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6716 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6717 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 6718 (const_int 0)))
44cd321e 6719 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 6720 (rotate:DI (match_dup 1) (match_dup 2)))]
683bdff7 6721 "TARGET_64BIT"
9ebbca7d 6722 "@
44cd321e
PS		 6723 rldcl. %0,%1,%2,0
6724 rldicl. %0,%1,%H2,0
6725 #
9ebbca7d 6726 #"
44cd321e
PS		 6727 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6728 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6729
6730(define_split
6731 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6732 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6733 (match_operand:DI 2 "reg_or_cint_operand" ""))
6734 (const_int 0)))
6735 (set (match_operand:DI 0 "gpc_reg_operand" "")
6736 (rotate:DI (match_dup 1) (match_dup 2)))]
6737 "TARGET_POWERPC64 && reload_completed"
6738 [(set (match_dup 0)
6739 (rotate:DI (match_dup 1) (match_dup 2)))
6740 (set (match_dup 3)
6741 (compare:CC (match_dup 0)
6742 (const_int 0)))]
6743 "")
266eb58a 6744
a260abc9 6745(define_insn "*rotldi3_internal4"
44cd321e
PS		 6746 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6747 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6748 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6749 (match_operand:DI 3 "mask64_operand" "n,n")))]
a260abc9 6750 "TARGET_POWERPC64"
44cd321e
PS		 6751 "@
6752 rldc%B3 %0,%1,%2,%S3
6753 rldic%B3 %0,%1,%H2,%S3"
6754 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6755
6756(define_insn "*rotldi3_internal5"
44cd321e 6757 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6758 (compare:CC (and:DI
44cd321e
PS		 6759 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6760 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6761 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6762 (const_int 0)))
44cd321e 6763 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
683bdff7 6764 "TARGET_64BIT"
9ebbca7d 6765 "@
44cd321e
PS		 6766 rldc%B3. %4,%1,%2,%S3
6767 rldic%B3. %4,%1,%H2,%S3
6768 #
9ebbca7d 6769 #"
44cd321e
PS		 6770 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6771 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6772
6773(define_split
6774 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6775 (compare:CC (and:DI
6776 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6777 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6778 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6779 (const_int 0)))
6780 (clobber (match_scratch:DI 4 ""))]
6781 "TARGET_POWERPC64 && reload_completed"
6782 [(set (match_dup 4)
6783 (and:DI (rotate:DI (match_dup 1)
6784 (match_dup 2))
6785 (match_dup 3)))
6786 (set (match_dup 0)
6787 (compare:CC (match_dup 4)
6788 (const_int 0)))]
6789 "")
a260abc9
DE		 6790
6791(define_insn "*rotldi3_internal6"
44cd321e 6792 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
a260abc9 6793 (compare:CC (and:DI
44cd321e
PS		 6794 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6795 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6796 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
a260abc9 6797 (const_int 0)))
44cd321e 6798 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6799 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 6800 "TARGET_64BIT"
9ebbca7d 6801 "@
44cd321e
PS		 6802 rldc%B3. %0,%1,%2,%S3
6803 rldic%B3. %0,%1,%H2,%S3
6804 #
9ebbca7d 6805 #"
44cd321e
PS		 6806 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6807 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6808
6809(define_split
6810 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6811 (compare:CC (and:DI
6812 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6813 (match_operand:DI 2 "reg_or_cint_operand" ""))
1990cd79 6814 (match_operand:DI 3 "mask64_operand" ""))
9ebbca7d
GK		 6815 (const_int 0)))
6816 (set (match_operand:DI 0 "gpc_reg_operand" "")
6817 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6818 "TARGET_POWERPC64 && reload_completed"
6819 [(set (match_dup 0)
6820 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6821 (set (match_dup 4)
6822 (compare:CC (match_dup 0)
6823 (const_int 0)))]
6824 "")
a260abc9
DE		 6825
6826(define_insn "*rotldi3_internal7"
44cd321e 6827 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6828 (zero_extend:DI
6829 (subreg:QI
44cd321e
PS		 6830 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6831 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6832 "TARGET_POWERPC64"
44cd321e
PS		 6833 "@
6834 rldcl %0,%1,%2,56
6835 rldicl %0,%1,%H2,56"
6836 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6837
6838(define_insn "*rotldi3_internal8"
44cd321e 6839 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6840 (compare:CC (zero_extend:DI
6841 (subreg:QI
44cd321e
PS		 6842 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6843 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6844 (const_int 0)))
44cd321e 6845 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6846 "TARGET_64BIT"
9ebbca7d 6847 "@
44cd321e
PS		 6848 rldcl. %3,%1,%2,56
6849 rldicl. %3,%1,%H2,56
6850 #
9ebbca7d 6851 #"
44cd321e
PS		 6852 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6853 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6854
6855(define_split
6856 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6857 (compare:CC (zero_extend:DI
6858 (subreg:QI
6859 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6860 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6861 (const_int 0)))
6862 (clobber (match_scratch:DI 3 ""))]
6863 "TARGET_POWERPC64 && reload_completed"
6864 [(set (match_dup 3)
6865 (zero_extend:DI (subreg:QI
6866 (rotate:DI (match_dup 1)
6867 (match_dup 2)) 0)))
6868 (set (match_dup 0)
6869 (compare:CC (match_dup 3)
6870 (const_int 0)))]
6871 "")
a260abc9
DE		 6872
6873(define_insn "*rotldi3_internal9"
44cd321e 6874 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6875 (compare:CC (zero_extend:DI
6876 (subreg:QI
44cd321e
PS		 6877 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6878 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6879 (const_int 0)))
44cd321e 6880 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6881 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6882 "TARGET_64BIT"
9ebbca7d 6883 "@
44cd321e
PS		 6884 rldcl. %0,%1,%2,56
6885 rldicl. %0,%1,%H2,56
6886 #
9ebbca7d 6887 #"
44cd321e
PS		 6888 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6889 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6890
6891(define_split
6892 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6893 (compare:CC (zero_extend:DI
6894 (subreg:QI
6895 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6896 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6897 (const_int 0)))
6898 (set (match_operand:DI 0 "gpc_reg_operand" "")
6899 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6900 "TARGET_POWERPC64 && reload_completed"
6901 [(set (match_dup 0)
6902 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6903 (set (match_dup 3)
6904 (compare:CC (match_dup 0)
6905 (const_int 0)))]
6906 "")
a260abc9
DE		 6907
6908(define_insn "*rotldi3_internal10"
44cd321e 6909 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6910 (zero_extend:DI
6911 (subreg:HI
44cd321e
PS		 6912 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6913 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6914 "TARGET_POWERPC64"
44cd321e
PS		 6915 "@
6916 rldcl %0,%1,%2,48
6917 rldicl %0,%1,%H2,48"
6918 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 6919
6920(define_insn "*rotldi3_internal11"
44cd321e 6921 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6922 (compare:CC (zero_extend:DI
6923 (subreg:HI
44cd321e
PS		 6924 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6925 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6926 (const_int 0)))
44cd321e 6927 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 6928 "TARGET_64BIT"
9ebbca7d 6929 "@
44cd321e
PS		 6930 rldcl. %3,%1,%2,48
6931 rldicl. %3,%1,%H2,48
6932 #
9ebbca7d 6933 #"
44cd321e
PS		 6934 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6935 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6936
6937(define_split
6938 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6939 (compare:CC (zero_extend:DI
6940 (subreg:HI
6941 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6942 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6943 (const_int 0)))
6944 (clobber (match_scratch:DI 3 ""))]
6945 "TARGET_POWERPC64 && reload_completed"
6946 [(set (match_dup 3)
6947 (zero_extend:DI (subreg:HI
6948 (rotate:DI (match_dup 1)
6949 (match_dup 2)) 0)))
6950 (set (match_dup 0)
6951 (compare:CC (match_dup 3)
6952 (const_int 0)))]
6953 "")
a260abc9
DE		 6954
6955(define_insn "*rotldi3_internal12"
44cd321e 6956 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 6957 (compare:CC (zero_extend:DI
6958 (subreg:HI
44cd321e
PS		 6959 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6960 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 6961 (const_int 0)))
44cd321e 6962 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 6963 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 6964 "TARGET_64BIT"
9ebbca7d 6965 "@
44cd321e
PS		 6966 rldcl. %0,%1,%2,48
6967 rldicl. %0,%1,%H2,48
6968 #
9ebbca7d 6969 #"
44cd321e
PS		 6970 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6971 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 6972
6973(define_split
6974 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6975 (compare:CC (zero_extend:DI
6976 (subreg:HI
6977 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6978 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6979 (const_int 0)))
6980 (set (match_operand:DI 0 "gpc_reg_operand" "")
6981 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6982 "TARGET_POWERPC64 && reload_completed"
6983 [(set (match_dup 0)
6984 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6985 (set (match_dup 3)
6986 (compare:CC (match_dup 0)
6987 (const_int 0)))]
6988 "")
a260abc9
DE		 6989
6990(define_insn "*rotldi3_internal13"
44cd321e 6991 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 6992 (zero_extend:DI
6993 (subreg:SI
44cd321e
PS		 6994 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6995 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
a260abc9 6996 "TARGET_POWERPC64"
44cd321e
PS		 6997 "@
6998 rldcl %0,%1,%2,32
6999 rldicl %0,%1,%H2,32"
7000 [(set_attr "type" "var_shift_rotate,integer")])
a260abc9
DE		 7001
7002(define_insn "*rotldi3_internal14"
44cd321e 7003 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7004 (compare:CC (zero_extend:DI
7005 (subreg:SI
44cd321e
PS		 7006 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7007 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7008 (const_int 0)))
44cd321e 7009 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7010 "TARGET_64BIT"
9ebbca7d 7011 "@
44cd321e
PS		 7012 rldcl. %3,%1,%2,32
7013 rldicl. %3,%1,%H2,32
7014 #
9ebbca7d 7015 #"
44cd321e
PS		 7016 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7017 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7018
7019(define_split
7020 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7021 (compare:CC (zero_extend:DI
7022 (subreg:SI
7023 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7024 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7025 (const_int 0)))
7026 (clobber (match_scratch:DI 3 ""))]
7027 "TARGET_POWERPC64 && reload_completed"
7028 [(set (match_dup 3)
7029 (zero_extend:DI (subreg:SI
7030 (rotate:DI (match_dup 1)
7031 (match_dup 2)) 0)))
7032 (set (match_dup 0)
7033 (compare:CC (match_dup 3)
7034 (const_int 0)))]
7035 "")
a260abc9
DE		 7036
7037(define_insn "*rotldi3_internal15"
44cd321e 7038 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
a260abc9
DE		 7039 (compare:CC (zero_extend:DI
7040 (subreg:SI
44cd321e
PS		 7041 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7042 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
a260abc9 7043 (const_int 0)))
44cd321e 7044 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
a260abc9 7045 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
683bdff7 7046 "TARGET_64BIT"
9ebbca7d 7047 "@
44cd321e
PS		 7048 rldcl. %0,%1,%2,32
7049 rldicl. %0,%1,%H2,32
7050 #
9ebbca7d 7051 #"
44cd321e
PS		 7052 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7053 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7054
7055(define_split
7056 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7057 (compare:CC (zero_extend:DI
7058 (subreg:SI
7059 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7060 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7061 (const_int 0)))
7062 (set (match_operand:DI 0 "gpc_reg_operand" "")
7063 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7064 "TARGET_POWERPC64 && reload_completed"
7065 [(set (match_dup 0)
7066 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7067 (set (match_dup 3)
7068 (compare:CC (match_dup 0)
7069 (const_int 0)))]
7070 "")
a260abc9 7071
266eb58a
DE		 7072(define_expand "ashldi3"
7073 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7074 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7075 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7076 "TARGET_POWERPC64 || TARGET_POWER"
7077 "
7078{
7079 if (TARGET_POWERPC64)
7080 ;
7081 else if (TARGET_POWER)
7082 {
7083 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7084 DONE;
7085 }
7086 else
7087 FAIL;
7088}")
7089
e2c953b6 7090(define_insn "*ashldi3_internal1"
44cd321e
PS		 7091 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7092 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7093 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7094 "TARGET_POWERPC64"
44cd321e
PS		 7095 "@
7096 sld %0,%1,%2
7097 sldi %0,%1,%H2"
7098 [(set_attr "type" "var_shift_rotate,shift")])
6ae08853 7099
e2c953b6 7100(define_insn "*ashldi3_internal2"
44cd321e
PS		 7101 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7102 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7103 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7104 (const_int 0)))
44cd321e 7105 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7106 "TARGET_64BIT"
9ebbca7d 7107 "@
44cd321e
PS		 7108 sld. %3,%1,%2
7109 sldi. %3,%1,%H2
7110 #
9ebbca7d 7111 #"
44cd321e
PS		 7112 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7113 (set_attr "length" "4,4,8,8")])
6ae08853 7114
9ebbca7d
GK		 7115(define_split
7116 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7117 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7118 (match_operand:SI 2 "reg_or_cint_operand" ""))
7119 (const_int 0)))
7120 (clobber (match_scratch:DI 3 ""))]
7121 "TARGET_POWERPC64 && reload_completed"
7122 [(set (match_dup 3)
7123 (ashift:DI (match_dup 1) (match_dup 2)))
7124 (set (match_dup 0)
7125 (compare:CC (match_dup 3)
7126 (const_int 0)))]
7127 "")
7128
e2c953b6 7129(define_insn "*ashldi3_internal3"
44cd321e
PS		 7130 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7131 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7132 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7133 (const_int 0)))
44cd321e 7134 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7135 (ashift:DI (match_dup 1) (match_dup 2)))]
683bdff7 7136 "TARGET_64BIT"
9ebbca7d 7137 "@
44cd321e
PS		 7138 sld. %0,%1,%2
7139 sldi. %0,%1,%H2
7140 #
9ebbca7d 7141 #"
44cd321e
PS		 7142 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7143 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7144
7145(define_split
7146 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7147 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7148 (match_operand:SI 2 "reg_or_cint_operand" ""))
7149 (const_int 0)))
7150 (set (match_operand:DI 0 "gpc_reg_operand" "")
7151 (ashift:DI (match_dup 1) (match_dup 2)))]
7152 "TARGET_POWERPC64 && reload_completed"
7153 [(set (match_dup 0)
7154 (ashift:DI (match_dup 1) (match_dup 2)))
7155 (set (match_dup 3)
7156 (compare:CC (match_dup 0)
7157 (const_int 0)))]
7158 "")
266eb58a 7159
e2c953b6 7160(define_insn "*ashldi3_internal4"
3cb999d8
DE		 7161 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7162 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7163 (match_operand:SI 2 "const_int_operand" "i"))
c5059423
AM		 7164 (match_operand:DI 3 "const_int_operand" "n")))]
7165 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
e2c953b6 7166 "rldic %0,%1,%H2,%W3")
3cb999d8 7167
e2c953b6 7168(define_insn "ashldi3_internal5"
9ebbca7d 7169 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3cb999d8 7170 (compare:CC
9ebbca7d
GK		 7171 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7172 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7173 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7174 (const_int 0)))
9ebbca7d 7175 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7176 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7177 "@
e2c953b6 7178 rldic. %4,%1,%H2,%W3
9ebbca7d 7179 #"
9c6fdb46 7180 [(set_attr "type" "compare")
9ebbca7d
GK		 7181 (set_attr "length" "4,8")])
7182
7183(define_split
7184 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7185 (compare:CC
7186 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7187 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7188 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7189 (const_int 0)))
7190 (clobber (match_scratch:DI 4 ""))]
c5059423
AM		 7191 "TARGET_POWERPC64 && reload_completed
7192 && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d
GK		 7193 [(set (match_dup 4)
7194 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
e2c953b6 7195 (match_dup 3)))
9ebbca7d
GK		 7196 (set (match_dup 0)
7197 (compare:CC (match_dup 4)
7198 (const_int 0)))]
7199 "")
3cb999d8 7200
e2c953b6 7201(define_insn "*ashldi3_internal6"
9ebbca7d 7202 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3cb999d8 7203 (compare:CC
9ebbca7d
GK		 7204 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7205 (match_operand:SI 2 "const_int_operand" "i,i"))
c5059423 7206 (match_operand:DI 3 "const_int_operand" "n,n"))
3cb999d8 7207 (const_int 0)))
9ebbca7d 7208 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3cb999d8 7209 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7210 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
9ebbca7d 7211 "@
e2c953b6 7212 rldic. %0,%1,%H2,%W3
9ebbca7d 7213 #"
9c6fdb46 7214 [(set_attr "type" "compare")
9ebbca7d
GK		 7215 (set_attr "length" "4,8")])
7216
7217(define_split
7218 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7219 (compare:CC
7220 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7221 (match_operand:SI 2 "const_int_operand" ""))
c5059423 7222 (match_operand:DI 3 "const_int_operand" ""))
9ebbca7d
GK		 7223 (const_int 0)))
7224 (set (match_operand:DI 0 "gpc_reg_operand" "")
7225 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
c5059423
AM		 7226 "TARGET_POWERPC64 && reload_completed
7227 && includes_rldic_lshift_p (operands[2], operands[3])"
7228 [(set (match_dup 0)
7229 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7230 (match_dup 3)))
7231 (set (match_dup 4)
7232 (compare:CC (match_dup 0)
7233 (const_int 0)))]
7234 "")
7235
7236(define_insn "*ashldi3_internal7"
7237 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7238 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7239 (match_operand:SI 2 "const_int_operand" "i"))
1990cd79 7240 (match_operand:DI 3 "mask64_operand" "n")))]
c5059423
AM		 7241 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7242 "rldicr %0,%1,%H2,%S3")
7243
7244(define_insn "ashldi3_internal8"
7245 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7246 (compare:CC
7247 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7248 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7249 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7250 (const_int 0)))
7251 (clobber (match_scratch:DI 4 "=r,r"))]
683bdff7 7252 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7253 "@
7254 rldicr. %4,%1,%H2,%S3
7255 #"
9c6fdb46 7256 [(set_attr "type" "compare")
c5059423
AM		 7257 (set_attr "length" "4,8")])
7258
7259(define_split
7260 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7261 (compare:CC
7262 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7263 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7264 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7265 (const_int 0)))
7266 (clobber (match_scratch:DI 4 ""))]
7267 "TARGET_POWERPC64 && reload_completed
7268 && includes_rldicr_lshift_p (operands[2], operands[3])"
7269 [(set (match_dup 4)
7270 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7271 (match_dup 3)))
7272 (set (match_dup 0)
7273 (compare:CC (match_dup 4)
7274 (const_int 0)))]
7275 "")
7276
7277(define_insn "*ashldi3_internal9"
7278 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7279 (compare:CC
7280 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7281 (match_operand:SI 2 "const_int_operand" "i,i"))
1990cd79 7282 (match_operand:DI 3 "mask64_operand" "n,n"))
c5059423
AM		 7283 (const_int 0)))
7284 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7285 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 7286 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
c5059423
AM		 7287 "@
7288 rldicr. %0,%1,%H2,%S3
7289 #"
9c6fdb46 7290 [(set_attr "type" "compare")
c5059423
AM		 7291 (set_attr "length" "4,8")])
7292
7293(define_split
7294 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7295 (compare:CC
7296 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7297 (match_operand:SI 2 "const_int_operand" ""))
1990cd79 7298 (match_operand:DI 3 "mask64_operand" ""))
c5059423
AM		 7299 (const_int 0)))
7300 (set (match_operand:DI 0 "gpc_reg_operand" "")
7301 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7302 "TARGET_POWERPC64 && reload_completed
7303 && includes_rldicr_lshift_p (operands[2], operands[3])"
9ebbca7d 7304 [(set (match_dup 0)
e2c953b6
DE		 7305 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7306 (match_dup 3)))
9ebbca7d
GK		 7307 (set (match_dup 4)
7308 (compare:CC (match_dup 0)
7309 (const_int 0)))]
7310 "")
7311
7312(define_expand "lshrdi3"
266eb58a
DE		 7313 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7314 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7315 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7316 "TARGET_POWERPC64 || TARGET_POWER"
7317 "
7318{
7319 if (TARGET_POWERPC64)
7320 ;
7321 else if (TARGET_POWER)
7322 {
7323 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7324 DONE;
7325 }
7326 else
7327 FAIL;
7328}")
7329
e2c953b6 7330(define_insn "*lshrdi3_internal1"
44cd321e
PS		 7331 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7332 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7333 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7334 "TARGET_POWERPC64"
44cd321e
PS		 7335 "@
7336 srd %0,%1,%2
7337 srdi %0,%1,%H2"
7338 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7339
e2c953b6 7340(define_insn "*lshrdi3_internal2"
44cd321e
PS		 7341 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7342 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7343 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
29ae5b89 7344 (const_int 0)))
44cd321e 7345 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7346 "TARGET_64BIT "
9ebbca7d 7347 "@
44cd321e
PS		 7348 srd. %3,%1,%2
7349 srdi. %3,%1,%H2
7350 #
9ebbca7d 7351 #"
44cd321e
PS		 7352 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7353 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7354
7355(define_split
7356 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7357 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7358 (match_operand:SI 2 "reg_or_cint_operand" ""))
7359 (const_int 0)))
7360 (clobber (match_scratch:DI 3 ""))]
7361 "TARGET_POWERPC64 && reload_completed"
7362 [(set (match_dup 3)
7363 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7364 (set (match_dup 0)
7365 (compare:CC (match_dup 3)
7366 (const_int 0)))]
7367 "")
266eb58a 7368
e2c953b6 7369(define_insn "*lshrdi3_internal3"
44cd321e
PS		 7370 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7371 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7372 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7373 (const_int 0)))
44cd321e 7374 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
29ae5b89 7375 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7376 "TARGET_64BIT"
9ebbca7d 7377 "@
44cd321e
PS		 7378 srd. %0,%1,%2
7379 srdi. %0,%1,%H2
7380 #
9ebbca7d 7381 #"
44cd321e
PS		 7382 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7383 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7384
7385(define_split
7386 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7387 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7388 (match_operand:SI 2 "reg_or_cint_operand" ""))
7389 (const_int 0)))
7390 (set (match_operand:DI 0 "gpc_reg_operand" "")
7391 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7392 "TARGET_POWERPC64 && reload_completed"
7393 [(set (match_dup 0)
7394 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7395 (set (match_dup 3)
7396 (compare:CC (match_dup 0)
7397 (const_int 0)))]
7398 "")
266eb58a
DE		 7399
7400(define_expand "ashrdi3"
7401 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7402 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7403 (match_operand:SI 2 "reg_or_cint_operand" "")))]
97727e85 7404 "WORDS_BIG_ENDIAN"
266eb58a
DE		 7405 "
7406{
7407 if (TARGET_POWERPC64)
7408 ;
7409 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7410 {
7411 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7412 DONE;
7413 }
97727e85
AH		 7414 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7415 && WORDS_BIG_ENDIAN)
4aa74a4f
FS		 7416 {
7417 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7418 DONE;
7419 }
266eb58a
DE		 7420 else
7421 FAIL;
7422}")
7423
e2c953b6 7424(define_insn "*ashrdi3_internal1"
44cd321e
PS		 7425 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7426 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7427 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
266eb58a 7428 "TARGET_POWERPC64"
44cd321e
PS		 7429 "@
7430 srad %0,%1,%2
7431 sradi %0,%1,%H2"
7432 [(set_attr "type" "var_shift_rotate,shift")])
266eb58a 7433
e2c953b6 7434(define_insn "*ashrdi3_internal2"
44cd321e
PS		 7435 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7436 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7437 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7438 (const_int 0)))
44cd321e 7439 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
683bdff7 7440 "TARGET_64BIT"
9ebbca7d 7441 "@
44cd321e
PS		 7442 srad. %3,%1,%2
7443 sradi. %3,%1,%H2
7444 #
9ebbca7d 7445 #"
44cd321e
PS		 7446 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7447 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7448
7449(define_split
7450 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7451 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7452 (match_operand:SI 2 "reg_or_cint_operand" ""))
7453 (const_int 0)))
7454 (clobber (match_scratch:DI 3 ""))]
7455 "TARGET_POWERPC64 && reload_completed"
7456 [(set (match_dup 3)
7457 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7458 (set (match_dup 0)
7459 (compare:CC (match_dup 3)
7460 (const_int 0)))]
7461 "")
266eb58a 7462
e2c953b6 7463(define_insn "*ashrdi3_internal3"
44cd321e
PS		 7464 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7465 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7466 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
266eb58a 7467 (const_int 0)))
44cd321e 7468 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
266eb58a 7469 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
683bdff7 7470 "TARGET_64BIT"
9ebbca7d 7471 "@
44cd321e
PS		 7472 srad. %0,%1,%2
7473 sradi. %0,%1,%H2
7474 #
9ebbca7d 7475 #"
44cd321e
PS		 7476 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7477 (set_attr "length" "4,4,8,8")])
9ebbca7d
GK		 7478
7479(define_split
7480 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7481 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7482 (match_operand:SI 2 "reg_or_cint_operand" ""))
7483 (const_int 0)))
7484 (set (match_operand:DI 0 "gpc_reg_operand" "")
7485 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7486 "TARGET_POWERPC64 && reload_completed"
7487 [(set (match_dup 0)
7488 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7489 (set (match_dup 3)
7490 (compare:CC (match_dup 0)
7491 (const_int 0)))]
7492 "")
815cdc52 7493
29ae5b89 7494(define_insn "anddi3"
e1e2e653
NS		 7495 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7496 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7497 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7498 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
6ffc8580 7499 "TARGET_POWERPC64"
266eb58a
DE		 7500 "@
7501 and %0,%1,%2
29ae5b89 7502 rldic%B2 %0,%1,0,%S2
e1e2e653 7503 rlwinm %0,%1,0,%m2,%M2
29ae5b89 7504 andi. %0,%1,%b2
0ba1b2ff
AM		 7505 andis. %0,%1,%u2
7506 #"
e1e2e653
NS		 7507 [(set_attr "type" "*,*,*,compare,compare,*")
7508 (set_attr "length" "4,4,4,4,4,8")])
0ba1b2ff
AM		 7509
7510(define_split
7511 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7512 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7513 (match_operand:DI 2 "mask64_2_operand" "")))
7514 (clobber (match_scratch:CC 3 ""))]
7515 "TARGET_POWERPC64
7516 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7517 && !mask_operand (operands[2], DImode)
7518 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7519 [(set (match_dup 0)
7520 (and:DI (rotate:DI (match_dup 1)
7521 (match_dup 4))
7522 (match_dup 5)))
7523 (set (match_dup 0)
7524 (and:DI (rotate:DI (match_dup 0)
7525 (match_dup 6))
7526 (match_dup 7)))]
0ba1b2ff
AM		 7527{
7528 build_mask64_2_operands (operands[2], &operands[4]);
e1e2e653 7529})
266eb58a 7530
a260abc9 7531(define_insn "*anddi3_internal2"
1990cd79
AM		 7532 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7533 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7534 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7535 (const_int 0)))
1990cd79
AM		 7536 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7537 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7538 "TARGET_64BIT"
266eb58a
DE		 7539 "@
7540 and. %3,%1,%2
6c873122 7541 rldic%B2. %3,%1,0,%S2
1990cd79 7542 rlwinm. %3,%1,0,%m2,%M2
6ffc8580
MM		 7543 andi. %3,%1,%b2
7544 andis. %3,%1,%u2
9ebbca7d
GK		 7545 #
7546 #
7547 #
0ba1b2ff
AM		 7548 #
7549 #
1990cd79 7550 #
9ebbca7d 7551 #"
44cd321e 7552 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
1990cd79 7553 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d 7554
0ba1b2ff
AM		 7555(define_split
7556 [(set (match_operand:CC 0 "cc_reg_operand" "")
7557 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7558 (match_operand:DI 2 "mask64_2_operand" ""))
7559 (const_int 0)))
7560 (clobber (match_scratch:DI 3 ""))
7561 (clobber (match_scratch:CC 4 ""))]
1990cd79 7562 "TARGET_64BIT && reload_completed
0ba1b2ff 7563 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7564 && !mask_operand (operands[2], DImode)
7565 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7566 [(set (match_dup 3)
7567 (and:DI (rotate:DI (match_dup 1)
7568 (match_dup 5))
7569 (match_dup 6)))
7570 (parallel [(set (match_dup 0)
7571 (compare:CC (and:DI (rotate:DI (match_dup 3)
7572 (match_dup 7))
7573 (match_dup 8))
7574 (const_int 0)))
7575 (clobber (match_dup 3))])]
7576 "
7577{
7578 build_mask64_2_operands (operands[2], &operands[5]);
7579}")
7580
a260abc9 7581(define_insn "*anddi3_internal3"
1990cd79
AM		 7582 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7583 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7584 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
266eb58a 7585 (const_int 0)))
1990cd79 7586 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
9ebbca7d 7587 (and:DI (match_dup 1) (match_dup 2)))
1990cd79 7588 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
683bdff7 7589 "TARGET_64BIT"
266eb58a
DE		 7590 "@
7591 and. %0,%1,%2
6c873122 7592 rldic%B2. %0,%1,0,%S2
1990cd79 7593 rlwinm. %0,%1,0,%m2,%M2
6ffc8580
MM		 7594 andi. %0,%1,%b2
7595 andis. %0,%1,%u2
9ebbca7d
GK		 7596 #
7597 #
7598 #
0ba1b2ff
AM		 7599 #
7600 #
1990cd79 7601 #
9ebbca7d 7602 #"
44cd321e 7603 [(set_attr "type" "compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
1990cd79 7604 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
9ebbca7d
GK		 7605
7606(define_split
7607 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7608 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
1990cd79 7609 (match_operand:DI 2 "and64_2_operand" ""))
9ebbca7d
GK		 7610 (const_int 0)))
7611 (set (match_operand:DI 0 "gpc_reg_operand" "")
7612 (and:DI (match_dup 1) (match_dup 2)))
7613 (clobber (match_scratch:CC 4 ""))]
1990cd79 7614 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 7615 [(parallel [(set (match_dup 0)
7616 (and:DI (match_dup 1) (match_dup 2)))
7617 (clobber (match_dup 4))])
7618 (set (match_dup 3)
7619 (compare:CC (match_dup 0)
7620 (const_int 0)))]
7621 "")
266eb58a 7622
0ba1b2ff
AM		 7623(define_split
7624 [(set (match_operand:CC 3 "cc_reg_operand" "")
7625 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7626 (match_operand:DI 2 "mask64_2_operand" ""))
7627 (const_int 0)))
7628 (set (match_operand:DI 0 "gpc_reg_operand" "")
7629 (and:DI (match_dup 1) (match_dup 2)))
7630 (clobber (match_scratch:CC 4 ""))]
1990cd79 7631 "TARGET_64BIT && reload_completed
0ba1b2ff 7632 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
1990cd79
AM		 7633 && !mask_operand (operands[2], DImode)
7634 && !mask64_operand (operands[2], DImode)"
0ba1b2ff
AM		 7635 [(set (match_dup 0)
7636 (and:DI (rotate:DI (match_dup 1)
7637 (match_dup 5))
7638 (match_dup 6)))
7639 (parallel [(set (match_dup 3)
7640 (compare:CC (and:DI (rotate:DI (match_dup 0)
7641 (match_dup 7))
7642 (match_dup 8))
7643 (const_int 0)))
7644 (set (match_dup 0)
7645 (and:DI (rotate:DI (match_dup 0)
7646 (match_dup 7))
7647 (match_dup 8)))])]
7648 "
7649{
7650 build_mask64_2_operands (operands[2], &operands[5]);
7651}")
7652
a260abc9 7653(define_expand "iordi3"
266eb58a 7654 [(set (match_operand:DI 0 "gpc_reg_operand" "")
a260abc9 7655 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7656 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
266eb58a 7657 "TARGET_POWERPC64"
266eb58a
DE		 7658 "
7659{
dfbdccdb 7660 if (non_logical_cint_operand (operands[2], DImode))
266eb58a 7661 {
dfbdccdb 7662 HOST_WIDE_INT value;
b3a13419
ILT		 7663 rtx tmp = ((!can_create_pseudo_p ()
7664 || rtx_equal_p (operands[0], operands[1]))
a260abc9 7665 ? operands[0] : gen_reg_rtx (DImode));
266eb58a 7666
dfbdccdb
GK		 7667 if (GET_CODE (operands[2]) == CONST_INT)
7668 {
7669 value = INTVAL (operands[2]);
7670 emit_insn (gen_iordi3 (tmp, operands[1],
7671 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7672 }
e2c953b6 7673 else
dfbdccdb
GK		 7674 {
7675 value = CONST_DOUBLE_LOW (operands[2]);
7676 emit_insn (gen_iordi3 (tmp, operands[1],
7677 immed_double_const (value
7678 & (~ (HOST_WIDE_INT) 0xffff),
7679 0, DImode)));
7680 }
e2c953b6 7681
9ebbca7d
GK		 7682 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7683 DONE;
7684 }
266eb58a
DE		 7685}")
7686
a260abc9
DE		 7687(define_expand "xordi3"
7688 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7689 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
1d328b19 7690 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
a260abc9
DE		 7691 "TARGET_POWERPC64"
7692 "
7693{
dfbdccdb 7694 if (non_logical_cint_operand (operands[2], DImode))
a260abc9 7695 {
dfbdccdb 7696 HOST_WIDE_INT value;
b3a13419
ILT		 7697 rtx tmp = ((!can_create_pseudo_p ()
7698 || rtx_equal_p (operands[0], operands[1]))
a260abc9
DE		 7699 ? operands[0] : gen_reg_rtx (DImode));
7700
dfbdccdb
GK		 7701 if (GET_CODE (operands[2]) == CONST_INT)
7702 {
7703 value = INTVAL (operands[2]);
7704 emit_insn (gen_xordi3 (tmp, operands[1],
7705 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7706 }
e2c953b6 7707 else
dfbdccdb
GK		 7708 {
7709 value = CONST_DOUBLE_LOW (operands[2]);
7710 emit_insn (gen_xordi3 (tmp, operands[1],
7711 immed_double_const (value
7712 & (~ (HOST_WIDE_INT) 0xffff),
7713 0, DImode)));
7714 }
e2c953b6 7715
9ebbca7d
GK		 7716 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7717 DONE;
7718 }
a260abc9
DE		 7719}")
7720
dfbdccdb 7721(define_insn "*booldi3_internal1"
266eb58a 7722 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
1d328b19 7723 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7724 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7725 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
266eb58a 7726 "TARGET_POWERPC64"
1fd4e8c1 7727 "@
dfbdccdb
GK		 7728 %q3 %0,%1,%2
7729 %q3i %0,%1,%b2
7730 %q3is %0,%1,%u2")
1fd4e8c1 7731
dfbdccdb 7732(define_insn "*booldi3_internal2"
9ebbca7d 7733 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1d328b19 7734 (compare:CC (match_operator:DI 4 "boolean_or_operator"
dfbdccdb
GK		 7735 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7736 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7737 (const_int 0)))
9ebbca7d 7738 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7739 "TARGET_64BIT"
9ebbca7d 7740 "@
dfbdccdb 7741 %q4. %3,%1,%2
9ebbca7d
GK		 7742 #"
7743 [(set_attr "type" "compare")
7744 (set_attr "length" "4,8")])
7745
7746(define_split
7747 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7748 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7749 [(match_operand:DI 1 "gpc_reg_operand" "")
7750 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7751 (const_int 0)))
9ebbca7d
GK		 7752 (clobber (match_scratch:DI 3 ""))]
7753 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7754 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7755 (set (match_dup 0)
7756 (compare:CC (match_dup 3)
7757 (const_int 0)))]
7758 "")
1fd4e8c1 7759
dfbdccdb 7760(define_insn "*booldi3_internal3"
9ebbca7d 7761 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7762 (compare:CC (match_operator:DI 4 "boolean_operator"
7763 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7764 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7765 (const_int 0)))
9ebbca7d 7766 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7767 (match_dup 4))]
683bdff7 7768 "TARGET_64BIT"
9ebbca7d 7769 "@
dfbdccdb 7770 %q4. %0,%1,%2
9ebbca7d
GK		 7771 #"
7772 [(set_attr "type" "compare")
7773 (set_attr "length" "4,8")])
7774
7775(define_split
e72247f4 7776 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7777 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7778 [(match_operand:DI 1 "gpc_reg_operand" "")
7779 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7780 (const_int 0)))
75540af0 7781 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7782 (match_dup 4))]
9ebbca7d 7783 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7784 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7785 (set (match_dup 3)
7786 (compare:CC (match_dup 0)
7787 (const_int 0)))]
7788 "")
1fd4e8c1 7789
6ae08853 7790;; Split a logical operation that we can't do in one insn into two insns,
dfbdccdb 7791;; each of which does one 16-bit part. This is used by combine.
266eb58a
DE		 7792
7793(define_split
7794 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1d328b19 7795 (match_operator:DI 3 "boolean_or_operator"
dfbdccdb
GK		 7796 [(match_operand:DI 1 "gpc_reg_operand" "")
7797 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
266eb58a 7798 "TARGET_POWERPC64"
dfbdccdb
GK		 7799 [(set (match_dup 0) (match_dup 4))
7800 (set (match_dup 0) (match_dup 5))]
266eb58a
DE		 7801"
7802{
dfbdccdb 7803 rtx i3,i4;
6ae08853 7804
9ebbca7d
GK		 7805 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7806 {
7807 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
dfbdccdb 7808 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
9ebbca7d 7809 0, DImode);
dfbdccdb 7810 i4 = GEN_INT (value & 0xffff);
9ebbca7d
GK		 7811 }
7812 else
7813 {
dfbdccdb 7814 i3 = GEN_INT (INTVAL (operands[2])
9ebbca7d 7815 & (~ (HOST_WIDE_INT) 0xffff));
dfbdccdb 7816 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
9ebbca7d 7817 }
1c563bed 7818 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7819 operands[1], i3);
1c563bed 7820 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
0f4c242b 7821 operands[0], i4);
1fd4e8c1
RK		 7822}")
7823
dfbdccdb 7824(define_insn "*boolcdi3_internal1"
9ebbca7d 7825 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7826 (match_operator:DI 3 "boolean_operator"
7827 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7828 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
a473029f 7829 "TARGET_POWERPC64"
1d328b19 7830 "%q3 %0,%2,%1")
a473029f 7831
dfbdccdb 7832(define_insn "*boolcdi3_internal2"
9ebbca7d 7833 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7834 (compare:CC (match_operator:DI 4 "boolean_operator"
7835 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7836 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7837 (const_int 0)))
9ebbca7d 7838 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7839 "TARGET_64BIT"
9ebbca7d 7840 "@
1d328b19 7841 %q4. %3,%2,%1
9ebbca7d
GK		 7842 #"
7843 [(set_attr "type" "compare")
7844 (set_attr "length" "4,8")])
7845
7846(define_split
7847 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7848 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7849 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7850 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7851 (const_int 0)))
9ebbca7d
GK		 7852 (clobber (match_scratch:DI 3 ""))]
7853 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7854 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7855 (set (match_dup 0)
7856 (compare:CC (match_dup 3)
7857 (const_int 0)))]
7858 "")
a473029f 7859
dfbdccdb 7860(define_insn "*boolcdi3_internal3"
9ebbca7d 7861 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7862 (compare:CC (match_operator:DI 4 "boolean_operator"
7863 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7864 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7865 (const_int 0)))
9ebbca7d 7866 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7867 (match_dup 4))]
683bdff7 7868 "TARGET_64BIT"
9ebbca7d 7869 "@
1d328b19 7870 %q4. %0,%2,%1
9ebbca7d
GK		 7871 #"
7872 [(set_attr "type" "compare")
7873 (set_attr "length" "4,8")])
7874
7875(define_split
e72247f4 7876 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7877 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7878 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7879 (match_operand:DI 2 "gpc_reg_operand" "")])
dfbdccdb 7880 (const_int 0)))
75540af0 7881 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7882 (match_dup 4))]
9ebbca7d 7883 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7884 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7885 (set (match_dup 3)
7886 (compare:CC (match_dup 0)
7887 (const_int 0)))]
7888 "")
266eb58a 7889
dfbdccdb 7890(define_insn "*boolccdi3_internal1"
a473029f 7891 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
dfbdccdb
GK		 7892 (match_operator:DI 3 "boolean_operator"
7893 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
40501e5f 7894 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
a473029f 7895 "TARGET_POWERPC64"
dfbdccdb 7896 "%q3 %0,%1,%2")
a473029f 7897
dfbdccdb 7898(define_insn "*boolccdi3_internal2"
9ebbca7d 7899 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7900 (compare:CC (match_operator:DI 4 "boolean_operator"
7901 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7902 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7903 (const_int 0)))
9ebbca7d 7904 (clobber (match_scratch:DI 3 "=r,r"))]
683bdff7 7905 "TARGET_64BIT"
9ebbca7d 7906 "@
dfbdccdb 7907 %q4. %3,%1,%2
9ebbca7d
GK		 7908 #"
7909 [(set_attr "type" "compare")
7910 (set_attr "length" "4,8")])
7911
7912(define_split
7913 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
dfbdccdb 7914 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7915 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7916 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7917 (const_int 0)))
9ebbca7d
GK		 7918 (clobber (match_scratch:DI 3 ""))]
7919 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7920 [(set (match_dup 3) (match_dup 4))
9ebbca7d
GK		 7921 (set (match_dup 0)
7922 (compare:CC (match_dup 3)
7923 (const_int 0)))]
7924 "")
266eb58a 7925
dfbdccdb 7926(define_insn "*boolccdi3_internal3"
9ebbca7d 7927 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
dfbdccdb
GK		 7928 (compare:CC (match_operator:DI 4 "boolean_operator"
7929 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7930 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7931 (const_int 0)))
9ebbca7d 7932 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
dfbdccdb 7933 (match_dup 4))]
683bdff7 7934 "TARGET_64BIT"
9ebbca7d 7935 "@
dfbdccdb 7936 %q4. %0,%1,%2
9ebbca7d
GK		 7937 #"
7938 [(set_attr "type" "compare")
7939 (set_attr "length" "4,8")])
7940
7941(define_split
e72247f4 7942 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
dfbdccdb 7943 (compare:CC (match_operator:DI 4 "boolean_operator"
75540af0
JH		 7944 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7945 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
dfbdccdb 7946 (const_int 0)))
75540af0 7947 (set (match_operand:DI 0 "gpc_reg_operand" "")
dfbdccdb 7948 (match_dup 4))]
9ebbca7d 7949 "TARGET_POWERPC64 && reload_completed"
dfbdccdb 7950 [(set (match_dup 0) (match_dup 4))
9ebbca7d
GK		 7951 (set (match_dup 3)
7952 (compare:CC (match_dup 0)
7953 (const_int 0)))]
7954 "")
dfbdccdb 7955\f
1fd4e8c1 7956;; Now define ways of moving data around.
4697a36c 7957
766a866c
MM		 7958;; Set up a register with a value from the GOT table
7959
7960(define_expand "movsi_got"
52d3af72 7961 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 7962 (unspec:SI [(match_operand:SI 1 "got_operand" "")
615158e2 7963 (match_dup 2)] UNSPEC_MOVSI_GOT))]
f607bc57 7964 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 7965 "
7966{
38c1f2d7
MM		 7967 if (GET_CODE (operands[1]) == CONST)
7968 {
7969 rtx offset = const0_rtx;
7970 HOST_WIDE_INT value;
7971
7972 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7973 value = INTVAL (offset);
7974 if (value != 0)
7975 {
b3a13419
ILT		 7976 rtx tmp = (!can_create_pseudo_p ()
7977 ? operands[0]
7978 : gen_reg_rtx (Pmode));
38c1f2d7
MM		 7979 emit_insn (gen_movsi_got (tmp, operands[1]));
7980 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7981 DONE;
7982 }
7983 }
7984
c4c40373 7985 operands[2] = rs6000_got_register (operands[1]);
766a866c
MM		 7986}")
7987
84f414bc 7988(define_insn "*movsi_got_internal"
52d3af72 7989 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9ebbca7d 7990 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 7991 (match_operand:SI 2 "gpc_reg_operand" "b")]
7992 UNSPEC_MOVSI_GOT))]
f607bc57 7993 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
766a866c
MM		 7994 "{l|lwz} %0,%a1@got(%2)"
7995 [(set_attr "type" "load")])
7996
b22b9b3e
JL		 7997;; Used by sched, shorten_branches and final when the GOT pseudo reg
7998;; didn't get allocated to a hard register.
6ae08853 7999(define_split
75540af0 8000 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9ebbca7d 8001 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
615158e2
JJ		 8002 (match_operand:SI 2 "memory_operand" "")]
8003 UNSPEC_MOVSI_GOT))]
f607bc57 8004 "DEFAULT_ABI == ABI_V4
b22b9b3e
JL		 8005 && flag_pic == 1
8006 && (reload_in_progress || reload_completed)"
8007 [(set (match_dup 0) (match_dup 2))
615158e2
JJ		 8008 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8009 UNSPEC_MOVSI_GOT))]
b22b9b3e
JL		 8010 "")
8011
1fd4e8c1
RK		 8012;; For SI, we special-case integers that can't be loaded in one insn. We
8013;; do the load 16-bits at a time. We could do this by loading from memory,
8014;; and this is even supposed to be faster, but it is simpler not to get
8015;; integers in the TOC.
ee890fe2
SS		 8016(define_insn "movsi_low"
8017 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
f585a356 8018 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
ee890fe2
SS		 8019 (match_operand 2 "" ""))))]
8020 "TARGET_MACHO && ! TARGET_64BIT"
8021 "{l|lwz} %0,lo16(%2)(%1)"
8022 [(set_attr "type" "load")
8023 (set_attr "length" "4")])
8024
acad7ed3 8025(define_insn "*movsi_internal1"
165a5bad 8026 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
a004eb82 8027 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
19d5775a
RK		 8028 "gpc_reg_operand (operands[0], SImode)
8029 || gpc_reg_operand (operands[1], SImode)"
1fd4e8c1 8030 "@
deb9225a 8031 mr %0,%1
b9442c72 8032 {cal|la} %0,%a1
ca7f5001
RK		 8033 {l%U1%X1|lwz%U1%X1} %0,%1
8034 {st%U0%X0|stw%U0%X0} %1,%0
19d5775a 8035 {lil|li} %0,%1
802a0058 8036 {liu|lis} %0,%v1
beaec479 8037 #
aee86b38 8038 {cal|la} %0,%a1
1fd4e8c1 8039 mf%1 %0
5c23c401 8040 mt%0 %1
e76e75bb 8041 mt%0 %1
a004eb82 8042 mt%0 %1
e34eaae5 8043 {cror 0,0,0|nop}"
02ca7595 8044 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
a004eb82 8045 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
1fd4e8c1 8046
77fa0940
RK		 8047;; Split a load of a large constant into the appropriate two-insn
8048;; sequence.
8049
8050(define_split
8051 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8052 (match_operand:SI 1 "const_int_operand" ""))]
bb21487f 8053 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
77fa0940
RK		 8054 && (INTVAL (operands[1]) & 0xffff) != 0"
8055 [(set (match_dup 0)
8056 (match_dup 2))
8057 (set (match_dup 0)
8058 (ior:SI (match_dup 0)
8059 (match_dup 3)))]
8060 "
af8cb5c5
DE		 8061{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8062
8063 if (tem == operands[0])
8064 DONE;
8065 else
8066 FAIL;
77fa0940
RK		 8067}")
8068
4ae234b0 8069(define_insn "*mov<mode>_internal2"
bb84cb12 8070 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
4ae234b0 8071 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
1fd4e8c1 8072 (const_int 0)))
4ae234b0
GK		 8073 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8074 ""
9ebbca7d 8075 "@
4ae234b0 8076 {cmpi|cmp<wd>i} %2,%0,0
9ebbca7d
GK		 8077 mr. %0,%1
8078 #"
bb84cb12
DE		 8079 [(set_attr "type" "cmp,compare,cmp")
8080 (set_attr "length" "4,4,8")])
8081
9ebbca7d
GK		 8082(define_split
8083 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
4ae234b0 8084 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
9ebbca7d 8085 (const_int 0)))
4ae234b0
GK		 8086 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8087 "reload_completed"
9ebbca7d
GK		 8088 [(set (match_dup 0) (match_dup 1))
8089 (set (match_dup 2)
8090 (compare:CC (match_dup 0)
8091 (const_int 0)))]
8092 "")
bb84cb12 8093\f
e34eaae5 8094(define_insn "*movhi_internal"
fb81d7ce
RK		 8095 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8096 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8097 "gpc_reg_operand (operands[0], HImode)
8098 || gpc_reg_operand (operands[1], HImode)"
1fd4e8c1 8099 "@
deb9225a 8100 mr %0,%1
1fd4e8c1
RK		 8101 lhz%U1%X1 %0,%1
8102 sth%U0%X0 %1,%0
19d5775a 8103 {lil|li} %0,%w1
1fd4e8c1 8104 mf%1 %0
e76e75bb 8105 mt%0 %1
fb81d7ce 8106 mt%0 %1
e34eaae5 8107 {cror 0,0,0|nop}"
02ca7595 8108 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1 8109
4ae234b0
GK		 8110(define_expand "mov<mode>"
8111 [(set (match_operand:INT 0 "general_operand" "")
8112 (match_operand:INT 1 "any_operand" ""))]
1fd4e8c1 8113 ""
4ae234b0 8114 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
1fd4e8c1 8115
e34eaae5 8116(define_insn "*movqi_internal"
fb81d7ce
RK		 8117 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8118 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
19d5775a
RK		 8119 "gpc_reg_operand (operands[0], QImode)
8120 || gpc_reg_operand (operands[1], QImode)"
1fd4e8c1 8121 "@
deb9225a 8122 mr %0,%1
1fd4e8c1
RK		 8123 lbz%U1%X1 %0,%1
8124 stb%U0%X0 %1,%0
19d5775a 8125 {lil|li} %0,%1
1fd4e8c1 8126 mf%1 %0
e76e75bb 8127 mt%0 %1
fb81d7ce 8128 mt%0 %1
e34eaae5 8129 {cror 0,0,0|nop}"
02ca7595 8130 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
1fd4e8c1
RK		 8131\f
8132;; Here is how to move condition codes around. When we store CC data in
8133;; an integer register or memory, we store just the high-order 4 bits.
8134;; This lets us not shift in the most common case of CR0.
8135(define_expand "movcc"
8136 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8137 (match_operand:CC 1 "nonimmediate_operand" ""))]
8138 ""
8139 "")
8140
a65c591c 8141(define_insn "*movcc_internal1"
4eb585a4
DE		 8142 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8143 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
1fd4e8c1
RK		 8144 "register_operand (operands[0], CCmode)
8145 || register_operand (operands[1], CCmode)"
8146 "@
8147 mcrf %0,%1
8148 mtcrf 128,%1
ca7f5001 8149 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
4eb585a4 8150 crxor %0,%0,%0
2c4a9cff
DE		 8151 mfcr %0%Q1
8152 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
deb9225a 8153 mr %0,%1
4eb585a4 8154 {lil|li} %0,%1
b54cf83a 8155 mf%1 %0
b991a865
GK		 8156 mt%0 %1
8157 mt%0 %1
ca7f5001
RK		 8158 {l%U1%X1|lwz%U1%X1} %0,%1
8159 {st%U0%U1|stw%U0%U1} %1,%0"
2c4a9cff 8160 [(set (attr "type")
4eb585a4 8161 (cond [(eq_attr "alternative" "0,3")
2c4a9cff
DE		 8162 (const_string "cr_logical")
8163 (eq_attr "alternative" "1,2")
8164 (const_string "mtcr")
4eb585a4 8165 (eq_attr "alternative" "6,7,9")
2c4a9cff 8166 (const_string "integer")
2c4a9cff 8167 (eq_attr "alternative" "8")
4eb585a4
DE		 8168 (const_string "mfjmpr")
8169 (eq_attr "alternative" "10")
2c4a9cff 8170 (const_string "mtjmpr")
4eb585a4 8171 (eq_attr "alternative" "11")
2c4a9cff 8172 (const_string "load")
4eb585a4 8173 (eq_attr "alternative" "12")
2c4a9cff
DE		 8174 (const_string "store")
8175 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8176 (const_string "mfcrf")
8177 ]
8178 (const_string "mfcr")))
4eb585a4 8179 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
1fd4e8c1 8180\f
e52e05ca
MM		 8181;; For floating-point, we normally deal with the floating-point registers
8182;; unless -msoft-float is used. The sole exception is that parameter passing
8183;; can produce floating-point values in fixed-point registers. Unless the
8184;; value is a simple constant or already in memory, we deal with this by
8185;; allocating memory and copying the value explicitly via that memory location.
1fd4e8c1
RK		 8186(define_expand "movsf"
8187 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8188 (match_operand:SF 1 "any_operand" ""))]
8189 ""
fb4d4348 8190 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
1fd4e8c1 8191
1fd4e8c1 8192(define_split
cd2b37d9 8193 [(set (match_operand:SF 0 "gpc_reg_operand" "")
c4c40373 8194 (match_operand:SF 1 "const_double_operand" ""))]
f99f88e0 8195 "reload_completed
5ae4759c
MM		 8196 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8197 || (GET_CODE (operands[0]) == SUBREG
8198 && GET_CODE (SUBREG_REG (operands[0])) == REG
8199 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373 8200 [(set (match_dup 2) (match_dup 3))]
685f3906
DE		 8201 "
8202{
8203 long l;
8204 REAL_VALUE_TYPE rv;
8205
8206 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8207 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
c4c40373 8208
f99f88e0
DE		 8209 if (! TARGET_POWERPC64)
8210 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8211 else
8212 operands[2] = gen_lowpart (SImode, operands[0]);
a260abc9 8213
2496c7bd 8214 operands[3] = gen_int_mode (l, SImode);
a260abc9
DE		 8215}")
8216
c4c40373 8217(define_insn "*movsf_hardfloat"
fb3249ef 8218 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
ae6669e7 8219 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
d14a6d05 8220 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6 8221 || gpc_reg_operand (operands[1], SFmode))
cf8e1455 8222 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
1fd4e8c1 8223 "@
f99f88e0
DE		 8224 mr %0,%1
8225 {l%U1%X1|lwz%U1%X1} %0,%1
8226 {st%U0%X0|stw%U0%X0} %1,%0
1fd4e8c1
RK		 8227 fmr %0,%1
8228 lfs%U1%X1 %0,%1
c4c40373 8229 stfs%U0%X0 %1,%0
b991a865
GK		 8230 mt%0 %1
8231 mt%0 %1
8232 mf%1 %0
e0740893 8233 {cror 0,0,0|nop}
c4c40373
MM		 8234 #
8235 #"
9c6fdb46 8236 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
ae6669e7 8237 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
d14a6d05 8238
c4c40373 8239(define_insn "*movsf_softfloat"
dd0fbae2
MK		 8240 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8241 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
d14a6d05 8242 "(gpc_reg_operand (operands[0], SFmode)
a3170dc6
AH		 8243 || gpc_reg_operand (operands[1], SFmode))
8244 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
d14a6d05
MM		 8245 "@
8246 mr %0,%1
b991a865
GK		 8247 mt%0 %1
8248 mt%0 %1
8249 mf%1 %0
d14a6d05
MM		 8250 {l%U1%X1|lwz%U1%X1} %0,%1
8251 {st%U0%X0|stw%U0%X0} %1,%0
8252 {lil|li} %0,%1
802a0058 8253 {liu|lis} %0,%v1
aee86b38 8254 {cal|la} %0,%a1
c4c40373 8255 #
dd0fbae2
MK		 8256 #
8257 {cror 0,0,0|nop}"
9c6fdb46 8258 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
dd0fbae2 8259 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
d14a6d05 8260
1fd4e8c1
RK		 8261\f
8262(define_expand "movdf"
8263 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8264 (match_operand:DF 1 "any_operand" ""))]
8265 ""
fb4d4348 8266 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
1fd4e8c1
RK		 8267
8268(define_split
cd2b37d9 8269 [(set (match_operand:DF 0 "gpc_reg_operand" "")
c4c40373 8270 (match_operand:DF 1 "const_int_operand" ""))]
a260abc9 8271 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8272 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8273 || (GET_CODE (operands[0]) == SUBREG
8274 && GET_CODE (SUBREG_REG (operands[0])) == REG
8275 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8276 [(set (match_dup 2) (match_dup 4))
8277 (set (match_dup 3) (match_dup 1))]
8278 "
8279{
5ae4759c 8280 int endian = (WORDS_BIG_ENDIAN == 0);
5f59ecb7
DE		 8281 HOST_WIDE_INT value = INTVAL (operands[1]);
8282
5ae4759c
MM		 8283 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8284 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
5f59ecb7
DE		 8285#if HOST_BITS_PER_WIDE_INT == 32
8286 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8287#else
8288 operands[4] = GEN_INT (value >> 32);
a65c591c 8289 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
5f59ecb7 8290#endif
c4c40373
MM		 8291}")
8292
c4c40373
MM		 8293(define_split
8294 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8295 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8296 "! TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8297 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8298 || (GET_CODE (operands[0]) == SUBREG
8299 && GET_CODE (SUBREG_REG (operands[0])) == REG
8300 && REGNO (SUBREG_REG (operands[0])) <= 31))"
c4c40373
MM		 8301 [(set (match_dup 2) (match_dup 4))
8302 (set (match_dup 3) (match_dup 5))]
8303 "
8304{
5ae4759c 8305 int endian = (WORDS_BIG_ENDIAN == 0);
47ad8c61
MM		 8306 long l[2];
8307 REAL_VALUE_TYPE rv;
8308
8309 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8310 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8311
5ae4759c
MM		 8312 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8313 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
2496c7bd
LB		 8314 operands[4] = gen_int_mode (l[endian], SImode);
8315 operands[5] = gen_int_mode (l[1 - endian], SImode);
c4c40373
MM		 8316}")
8317
efc08378
DE		 8318(define_split
8319 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8308679f 8320 (match_operand:DF 1 "const_double_operand" ""))]
a260abc9 8321 "TARGET_POWERPC64 && reload_completed
5ae4759c
MM		 8322 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8323 || (GET_CODE (operands[0]) == SUBREG
8324 && GET_CODE (SUBREG_REG (operands[0])) == REG
8325 && REGNO (SUBREG_REG (operands[0])) <= 31))"
a260abc9 8326 [(set (match_dup 2) (match_dup 3))]
5ae4759c 8327 "
a260abc9
DE		 8328{
8329 int endian = (WORDS_BIG_ENDIAN == 0);
8330 long l[2];
8331 REAL_VALUE_TYPE rv;
4977bab6 8332#if HOST_BITS_PER_WIDE_INT >= 64
5b029315 8333 HOST_WIDE_INT val;
4977bab6 8334#endif
a260abc9
DE		 8335
8336 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8337 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8338
8339 operands[2] = gen_lowpart (DImode, operands[0]);
8340 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
5b029315 8341#if HOST_BITS_PER_WIDE_INT >= 64
a2419b96
DE		 8342 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8343 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
5b029315 8344
f5264b52 8345 operands[3] = gen_int_mode (val, DImode);
5b029315 8346#else
a260abc9 8347 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
5b029315 8348#endif
a260abc9 8349}")
efc08378 8350
4eae5fe1 8351;; Don't have reload use general registers to load a constant. First,
1427100a 8352;; it might not work if the output operand is the equivalent of
4eae5fe1
RK		 8353;; a non-offsettable memref, but also it is less efficient than loading
8354;; the constant into an FP register, since it will probably be used there.
8355;; The "??" is a kludge until we can figure out a more reasonable way
8356;; of handling these non-offsettable values.
c4c40373 8357(define_insn "*movdf_hardfloat32"
914a7297
DE		 8358 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8359 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
cf8e1455 8360 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8361 && (gpc_reg_operand (operands[0], DFmode)
8362 || gpc_reg_operand (operands[1], DFmode))"
e7113111
RK		 8363 "*
8364{
8365 switch (which_alternative)
8366 {
a260abc9 8367 default:
37409796 8368 gcc_unreachable ();
e7113111
RK		 8369 case 0:
8370 /* We normally copy the low-numbered register first. However, if
000034eb
DE		 8371 the first register operand 0 is the same as the second register
8372 of operand 1, we must copy in the opposite order. */
e7113111 8373 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
deb9225a 8374 return \"mr %L0,%L1\;mr %0,%1\";
e7113111 8375 else
deb9225a 8376 return \"mr %0,%1\;mr %L0,%L1\";
e7113111 8377 case 1:
d04b6e6e
EB		 8378 if (rs6000_offsettable_memref_p (operands[1])
8379 || (GET_CODE (operands[1]) == MEM
8380 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8381 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
6fb5fa3c
DB		 8382 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC
8383 || GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY)))
000034eb
DE		 8384 {
8385 /* If the low-address word is used in the address, we must load
8386 it last. Otherwise, load it first. Note that we cannot have
8387 auto-increment in that case since the address register is
8388 known to be dead. */
8389 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8390 operands[1], 0))
8391 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8392 else
6fb5fa3c 8393 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
000034eb 8394 }
e7113111 8395 else
000034eb
DE		 8396 {
8397 rtx addreg;
8398
000034eb
DE		 8399 addreg = find_addr_reg (XEXP (operands[1], 0));
8400 if (refers_to_regno_p (REGNO (operands[0]),
8401 REGNO (operands[0]) + 1,
8402 operands[1], 0))
8403 {
8404 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8405 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb 8406 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
2284bd2b 8407 return \"{l%X1|lwz%X1} %0,%1\";
000034eb
DE		 8408 }
8409 else
8410 {
2284bd2b 8411 output_asm_insn (\"{l%X1|lwz%X1} %0,%1\", operands);
000034eb 8412 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8413 output_asm_insn (\"{l%X1|lwz%X1} %L0,%1\", operands);
000034eb
DE		 8414 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8415 return \"\";
8416 }
8417 }
e7113111 8418 case 2:
d04b6e6e
EB		 8419 if (rs6000_offsettable_memref_p (operands[0])
8420 || (GET_CODE (operands[0]) == MEM
8421 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8422 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
6fb5fa3c
DB		 8423 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
8424 || GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY)))
8425 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
000034eb
DE		 8426 else
8427 {
8428 rtx addreg;
8429
000034eb 8430 addreg = find_addr_reg (XEXP (operands[0], 0));
2284bd2b 8431 output_asm_insn (\"{st%X0|stw%X0} %1,%0\", operands);
000034eb 8432 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
2284bd2b 8433 output_asm_insn (\"{st%X0|stw%X0} %L1,%0\", operands);
000034eb
DE		 8434 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8435 return \"\";
8436 }
e7113111 8437 case 3:
914a7297 8438 return \"fmr %0,%1\";
e7113111 8439 case 4:
914a7297 8440 return \"lfd%U1%X1 %0,%1\";
e7113111 8441 case 5:
914a7297 8442 return \"stfd%U0%X0 %1,%0\";
e7113111 8443 case 6:
c4c40373 8444 case 7:
c4c40373 8445 case 8:
914a7297 8446 return \"#\";
e7113111
RK		 8447 }
8448}"
943c15ed 8449 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
914a7297 8450 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
51b8fc2c 8451
c4c40373 8452(define_insn "*movdf_softfloat32"
1427100a
DE		 8453 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8454 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
cf8e1455 8455 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
52d3af72
DE		 8456 && (gpc_reg_operand (operands[0], DFmode)
8457 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca
MM		 8458 "*
8459{
8460 switch (which_alternative)
8461 {
a260abc9 8462 default:
37409796 8463 gcc_unreachable ();
dc4f83ca
MM		 8464 case 0:
8465 /* We normally copy the low-numbered register first. However, if
8466 the first register operand 0 is the same as the second register of
8467 operand 1, we must copy in the opposite order. */
8468 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8469 return \"mr %L0,%L1\;mr %0,%1\";
8470 else
8471 return \"mr %0,%1\;mr %L0,%L1\";
8472 case 1:
3cb999d8
DE		 8473 /* If the low-address word is used in the address, we must load
8474 it last. Otherwise, load it first. Note that we cannot have
8475 auto-increment in that case since the address register is
8476 known to be dead. */
dc4f83ca 8477 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
3cb999d8 8478 operands[1], 0))
dc4f83ca
MM		 8479 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8480 else
6fb5fa3c 8481 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
dc4f83ca 8482 case 2:
6fb5fa3c 8483 return \"{st%U0%X0|stw%U0%X0} %1,%0\;{st|stw} %L1,%L0\";
dc4f83ca 8484 case 3:
c4c40373
MM		 8485 case 4:
8486 case 5:
dc4f83ca
MM		 8487 return \"#\";
8488 }
8489}"
943c15ed 8490 [(set_attr "type" "two,load,store,*,*,*")
c4c40373 8491 (set_attr "length" "8,8,8,8,12,16")])
dc4f83ca 8492
44cd321e
PS		 8493; ld/std require word-aligned displacements -> 'Y' constraint.
8494; List Y->r and r->Y before r->r for reload.
8495(define_insn "*movdf_hardfloat64_mfpgpr"
8496 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r,r,f")
8497 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F,f,r"))]
cf8e1455 8498 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
44cd321e
PS		 8499 && (gpc_reg_operand (operands[0], DFmode)
8500 || gpc_reg_operand (operands[1], DFmode))"
8501 "@
8502 std%U0%X0 %1,%0
8503 ld%U1%X1 %0,%1
8504 mr %0,%1
8505 fmr %0,%1
8506 lfd%U1%X1 %0,%1
8507 stfd%U0%X0 %1,%0
8508 mt%0 %1
8509 mf%1 %0
8510 {cror 0,0,0|nop}
8511 #
8512 #
8513 #
8514 mftgpr %0,%1
8515 mffgpr %0,%1"
8516 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8517 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8518
d2288d5d
HP		 8519; ld/std require word-aligned displacements -> 'Y' constraint.
8520; List Y->r and r->Y before r->r for reload.
c4c40373 8521(define_insn "*movdf_hardfloat64"
fb3249ef 8522 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
ae6669e7 8523 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
cf8e1455 8524 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
52d3af72
DE		 8525 && (gpc_reg_operand (operands[0], DFmode)
8526 || gpc_reg_operand (operands[1], DFmode))"
51b8fc2c 8527 "@
96bb8ed3 8528 std%U0%X0 %1,%0
3364872d
FJ		 8529 ld%U1%X1 %0,%1
8530 mr %0,%1
3d5570cb 8531 fmr %0,%1
f63184ac 8532 lfd%U1%X1 %0,%1
914a7297
DE		 8533 stfd%U0%X0 %1,%0
8534 mt%0 %1
8535 mf%1 %0
e0740893 8536 {cror 0,0,0|nop}
914a7297
DE		 8537 #
8538 #
8539 #"
9c6fdb46 8540 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
ae6669e7 8541 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
dc4f83ca 8542
c4c40373 8543(define_insn "*movdf_softfloat64"
d2288d5d
HP		 8544 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8545 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
a3170dc6 8546 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
52d3af72
DE		 8547 && (gpc_reg_operand (operands[0], DFmode)
8548 || gpc_reg_operand (operands[1], DFmode))"
dc4f83ca 8549 "@
d2288d5d
HP		 8550 ld%U1%X1 %0,%1
8551 std%U0%X0 %1,%0
dc4f83ca 8552 mr %0,%1
914a7297
DE		 8553 mt%0 %1
8554 mf%1 %0
c4c40373
MM		 8555 #
8556 #
e2d0915c 8557 #
e0740893 8558 {cror 0,0,0|nop}"
9c6fdb46 8559 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
e2d0915c 8560 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
1fd4e8c1 8561\f
06f4e019
DE		 8562(define_expand "movtf"
8563 [(set (match_operand:TF 0 "general_operand" "")
8564 (match_operand:TF 1 "any_operand" ""))]
8521c414 8565 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8566 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8567
a9baceb1
GK		 8568; It's important to list the o->f and f->o moves before f->f because
8569; otherwise reload, given m->f, will try to pick f->f and reload it,
409f61cd 8570; which doesn't make progress. Likewise r->Y must be before r->r.
a9baceb1 8571(define_insn_and_split "*movtf_internal"
409f61cd
AM		 8572 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8573 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
602ea4d3 8574 "!TARGET_IEEEQUAD
39e63627 8575 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
06f4e019
DE		 8576 && (gpc_reg_operand (operands[0], TFmode)
8577 || gpc_reg_operand (operands[1], TFmode))"
a9baceb1 8578 "#"
ecb62ae7 8579 "&& reload_completed"
a9baceb1
GK		 8580 [(pc)]
8581{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
112ccb83 8582 [(set_attr "length" "8,8,8,20,20,16")])
06f4e019 8583
8521c414 8584(define_insn_and_split "*movtf_softfloat"
17caeff2 8585 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
8521c414
JM		 8586 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
8587 "!TARGET_IEEEQUAD
8588 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8589 && (gpc_reg_operand (operands[0], TFmode)
8590 || gpc_reg_operand (operands[1], TFmode))"
8591 "#"
8592 "&& reload_completed"
8593 [(pc)]
8594{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8595 [(set_attr "length" "20,20,16")])
8596
ecb62ae7 8597(define_expand "extenddftf2"
17caeff2
JM		 8598 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8599 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8600 "!TARGET_IEEEQUAD
8601 && TARGET_HARD_FLOAT
8602 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8603 && TARGET_LONG_DOUBLE_128"
8604{
8605 if (TARGET_E500_DOUBLE)
8606 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8607 else
8608 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8609 DONE;
8610})
8611
8612(define_expand "extenddftf2_fprs"
ecb62ae7
GK		 8613 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8614 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8615 (use (match_dup 2))])]
602ea4d3 8616 "!TARGET_IEEEQUAD
cf8e1455 8617 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8618{
ecb62ae7 8619 operands[2] = CONST0_RTX (DFmode);
aa9cf005
DE		 8620 /* Generate GOT reference early for SVR4 PIC. */
8621 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8622 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
ecb62ae7 8623})
06f4e019 8624
ecb62ae7
GK		 8625(define_insn_and_split "*extenddftf2_internal"
8626 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8627 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
97c54d9a 8628 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
602ea4d3 8629 "!TARGET_IEEEQUAD
cf8e1455 8630 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8631 "#"
8632 "&& reload_completed"
8633 [(pc)]
06f4e019 8634{
ecb62ae7
GK		 8635 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8636 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8637 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8638 operands[1]);
8639 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8640 operands[2]);
8641 DONE;
6ae08853 8642})
ecb62ae7
GK		 8643
8644(define_expand "extendsftf2"
8645 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8646 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
602ea4d3 8647 "!TARGET_IEEEQUAD
17caeff2
JM		 8648 && TARGET_HARD_FLOAT
8649 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8650 && TARGET_LONG_DOUBLE_128"
ecb62ae7
GK		 8651{
8652 rtx tmp = gen_reg_rtx (DFmode);
8653 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8654 emit_insn (gen_extenddftf2 (operands[0], tmp));
8655 DONE;
8656})
06f4e019 8657
8cb320b8 8658(define_expand "trunctfdf2"
589b3fda
DE		 8659 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8660 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 8661 "!TARGET_IEEEQUAD
17caeff2
JM		 8662 && TARGET_HARD_FLOAT
8663 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8664 && TARGET_LONG_DOUBLE_128"
589b3fda 8665 "")
8cb320b8
DE		 8666
8667(define_insn_and_split "trunctfdf2_internal1"
8668 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8669 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
602ea4d3 8670 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8cb320b8
DE		 8671 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8672 "@
8673 #
8674 fmr %0,%1"
8675 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8676 [(const_int 0)]
8677{
8678 emit_note (NOTE_INSN_DELETED);
8679 DONE;
8680}
8681 [(set_attr "type" "fp")])
8682
8683(define_insn "trunctfdf2_internal2"
8684 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8685 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
602ea4d3 8686 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
cf8e1455 8687 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8688 "fadd %0,%1,%L1"
8cb320b8 8689 [(set_attr "type" "fp")])
06f4e019 8690
17caeff2
JM		 8691(define_expand "trunctfsf2"
8692 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8693 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8694 "!TARGET_IEEEQUAD
8695 && TARGET_HARD_FLOAT
8696 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8697 && TARGET_LONG_DOUBLE_128"
8698{
8699 if (TARGET_E500_DOUBLE)
8700 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8701 else
8702 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8703 DONE;
8704})
8705
8706(define_insn_and_split "trunctfsf2_fprs"
06f4e019 8707 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
ea112fc4
DE		 8708 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8709 (clobber (match_scratch:DF 2 "=f"))]
602ea4d3 8710 "!TARGET_IEEEQUAD
cf8e1455 8711 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019 8712 "#"
ea112fc4 8713 "&& reload_completed"
06f4e019
DE		 8714 [(set (match_dup 2)
8715 (float_truncate:DF (match_dup 1)))
8716 (set (match_dup 0)
8717 (float_truncate:SF (match_dup 2)))]
ea112fc4 8718 "")
06f4e019 8719
0c90aa3c 8720(define_expand "floatsitf2"
d29b7f64
DE		 8721 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8722 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
602ea4d3 8723 "!TARGET_IEEEQUAD
17caeff2
JM		 8724 && TARGET_HARD_FLOAT
8725 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8726 && TARGET_LONG_DOUBLE_128"
0c90aa3c
GK		 8727{
8728 rtx tmp = gen_reg_rtx (DFmode);
8729 expand_float (tmp, operands[1], false);
8730 emit_insn (gen_extenddftf2 (operands[0], tmp));
8731 DONE;
8732})
06f4e019 8733
ecb62ae7
GK		 8734; fadd, but rounding towards zero.
8735; This is probably not the optimal code sequence.
8736(define_insn "fix_trunc_helper"
8737 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8738 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8739 UNSPEC_FIX_TRUNC_TF))
8740 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
cf8e1455 8741 "TARGET_HARD_FLOAT && TARGET_FPRS"
ecb62ae7
GK		 8742 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8743 [(set_attr "type" "fp")
8744 (set_attr "length" "20")])
8745
0c90aa3c 8746(define_expand "fix_trunctfsi2"
17caeff2
JM		 8747 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8748 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8749 "!TARGET_IEEEQUAD
8750 && (TARGET_POWER2 || TARGET_POWERPC)
8751 && TARGET_HARD_FLOAT
8752 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8753 && TARGET_LONG_DOUBLE_128"
8754{
8755 if (TARGET_E500_DOUBLE)
8756 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8757 else
8758 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8759 DONE;
8760})
8761
8762(define_expand "fix_trunctfsi2_fprs"
ecb62ae7
GK		 8763 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8764 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8765 (clobber (match_dup 2))
8766 (clobber (match_dup 3))
8767 (clobber (match_dup 4))
8768 (clobber (match_dup 5))])]
602ea4d3 8769 "!TARGET_IEEEQUAD
ecb62ae7
GK		 8770 && (TARGET_POWER2 || TARGET_POWERPC)
8771 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8772{
8773 operands[2] = gen_reg_rtx (DFmode);
8774 operands[3] = gen_reg_rtx (DFmode);
8775 operands[4] = gen_reg_rtx (DImode);
8776 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8777})
8778
8779(define_insn_and_split "*fix_trunctfsi2_internal"
61c07d3c 8780 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
ecb62ae7
GK		 8781 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8782 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8783 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8784 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
b0d6c7d8 8785 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
602ea4d3 8786 "!TARGET_IEEEQUAD
39e63627 8787 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 8788 "#"
b3a13419 8789 "&& (can_create_pseudo_p () || offsettable_nonstrict_memref_p (operands[5]))"
ecb62ae7 8790 [(pc)]
0c90aa3c 8791{
ecb62ae7
GK		 8792 rtx lowword;
8793 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8794
230215f5
GK		 8795 gcc_assert (MEM_P (operands[5]));
8796 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
ecb62ae7
GK		 8797
8798 emit_insn (gen_fctiwz (operands[4], operands[2]));
8799 emit_move_insn (operands[5], operands[4]);
230215f5 8800 emit_move_insn (operands[0], lowword);
0c90aa3c
GK		 8801 DONE;
8802})
06f4e019 8803
17caeff2
JM		 8804(define_expand "negtf2"
8805 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8806 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
8807 "!TARGET_IEEEQUAD
8808 && TARGET_HARD_FLOAT
8809 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8810 && TARGET_LONG_DOUBLE_128"
8811 "")
8812
8813(define_insn "negtf2_internal"
06f4e019
DE		 8814 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8815 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
602ea4d3 8816 "!TARGET_IEEEQUAD
39e63627 8817 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
06f4e019
DE		 8818 "*
8819{
8820 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8821 return \"fneg %L0,%L1\;fneg %0,%1\";
8822 else
8823 return \"fneg %0,%1\;fneg %L0,%L1\";
8824}"
8825 [(set_attr "type" "fp")
8826 (set_attr "length" "8")])
8827
1a402dc1 8828(define_expand "abstf2"
17caeff2
JM		 8829 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8830 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
602ea4d3 8831 "!TARGET_IEEEQUAD
17caeff2
JM		 8832 && TARGET_HARD_FLOAT
8833 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8834 && TARGET_LONG_DOUBLE_128"
1a402dc1 8835 "
06f4e019 8836{
1a402dc1 8837 rtx label = gen_label_rtx ();
17caeff2
JM		 8838 if (TARGET_E500_DOUBLE)
8839 {
8840 if (flag_unsafe_math_optimizations)
8841 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
8842 else
8843 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
8844 }
8845 else
8846 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
1a402dc1
AM		 8847 emit_label (label);
8848 DONE;
8849}")
06f4e019 8850
1a402dc1 8851(define_expand "abstf2_internal"
e42ac3de
RS		 8852 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8853 (match_operand:TF 1 "gpc_reg_operand" ""))
1a402dc1
AM		 8854 (set (match_dup 3) (match_dup 5))
8855 (set (match_dup 5) (abs:DF (match_dup 5)))
8856 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8857 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8858 (label_ref (match_operand 2 "" ""))
8859 (pc)))
8860 (set (match_dup 6) (neg:DF (match_dup 6)))]
602ea4d3 8861 "!TARGET_IEEEQUAD
cf8e1455 8862 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
1a402dc1 8863 "
06f4e019 8864{
1a402dc1
AM		 8865 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8866 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8867 operands[3] = gen_reg_rtx (DFmode);
8868 operands[4] = gen_reg_rtx (CCFPmode);
8869 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8870 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8871}")
06f4e019 8872\f
1fd4e8c1
RK		 8873;; Next come the multi-word integer load and store and the load and store
8874;; multiple insns.
1fd4e8c1 8875
112ccb83
GK		 8876; List r->r after r->"o<>", otherwise reload will try to reload a
8877; non-offsettable address by using r->r which won't make progress.
acad7ed3 8878(define_insn "*movdi_internal32"
17caeff2 8879 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
112ccb83 8880 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
a260abc9 8881 "! TARGET_POWERPC64
4e74d8ec
MM		 8882 && (gpc_reg_operand (operands[0], DImode)
8883 || gpc_reg_operand (operands[1], DImode))"
112ccb83
GK		 8884 "@
8885 #
8886 #
8887 #
8888 fmr %0,%1
8889 lfd%U1%X1 %0,%1
8890 stfd%U0%X0 %1,%0
8891 #"
8892 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
4e74d8ec
MM		 8893
8894(define_split
8895 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8896 (match_operand:DI 1 "const_int_operand" ""))]
a260abc9 8897 "! TARGET_POWERPC64 && reload_completed"
4e74d8ec
MM		 8898 [(set (match_dup 2) (match_dup 4))
8899 (set (match_dup 3) (match_dup 1))]
8900 "
8901{
5f59ecb7 8902 HOST_WIDE_INT value = INTVAL (operands[1]);
bdaa0181
GK		 8903 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8904 DImode);
8905 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8906 DImode);
75d39459 8907#if HOST_BITS_PER_WIDE_INT == 32
5f59ecb7 8908 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
75d39459 8909#else
5f59ecb7 8910 operands[4] = GEN_INT (value >> 32);
a65c591c 8911 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
75d39459 8912#endif
4e74d8ec
MM		 8913}")
8914
3a1f863f 8915(define_split
17caeff2 8916 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "")
3a1f863f 8917 (match_operand:DI 1 "input_operand" ""))]
6ae08853 8918 "reload_completed && !TARGET_POWERPC64
3a1f863f 8919 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 8920 [(pc)]
8921{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
3a1f863f 8922
44cd321e
PS		 8923(define_insn "*movdi_mfpgpr"
8924 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h,r,*f")
8925 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0,*f,r"))]
8926 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8927 && (gpc_reg_operand (operands[0], DImode)
8928 || gpc_reg_operand (operands[1], DImode))"
8929 "@
8930 mr %0,%1
8931 ld%U1%X1 %0,%1
8932 std%U0%X0 %1,%0
8933 li %0,%1
8934 lis %0,%v1
8935 #
8936 {cal|la} %0,%a1
8937 fmr %0,%1
8938 lfd%U1%X1 %0,%1
8939 stfd%U0%X0 %1,%0
8940 mf%1 %0
8941 mt%0 %1
8942 {cror 0,0,0|nop}
8943 mftgpr %0,%1
8944 mffgpr %0,%1"
8945 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
8946 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
8947
acad7ed3 8948(define_insn "*movdi_internal64"
343f6bbf 8949 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
9615f239 8950 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
44cd321e 8951 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
4e74d8ec
MM		 8952 && (gpc_reg_operand (operands[0], DImode)
8953 || gpc_reg_operand (operands[1], DImode))"
51b8fc2c 8954 "@
3d5570cb
RK		 8955 mr %0,%1
8956 ld%U1%X1 %0,%1
96bb8ed3 8957 std%U0%X0 %1,%0
3d5570cb 8958 li %0,%1
802a0058 8959 lis %0,%v1
e6ca2c17 8960 #
aee86b38 8961 {cal|la} %0,%a1
3d5570cb
RK		 8962 fmr %0,%1
8963 lfd%U1%X1 %0,%1
8964 stfd%U0%X0 %1,%0
8965 mf%1 %0
08075ead 8966 mt%0 %1
e34eaae5 8967 {cror 0,0,0|nop}"
02ca7595 8968 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
e6ca2c17
DE		 8969 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8970
5f59ecb7 8971;; immediate value valid for a single instruction hiding in a const_double
a260abc9
DE		 8972(define_insn ""
8973 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8974 (match_operand:DI 1 "const_double_operand" "F"))]
5f59ecb7
DE		 8975 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8976 && GET_CODE (operands[1]) == CONST_DOUBLE
a260abc9
DE		 8977 && num_insns_constant (operands[1], DImode) == 1"
8978 "*
8979{
8980 return ((unsigned HOST_WIDE_INT)
8981 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8982 ? \"li %0,%1\" : \"lis %0,%v1\";
8983}")
8984
a260abc9
DE		 8985;; Generate all one-bits and clear left or right.
8986;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8987(define_split
8988 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1990cd79 8989 (match_operand:DI 1 "mask64_operand" ""))]
a260abc9
DE		 8990 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8991 [(set (match_dup 0) (const_int -1))
e6ca2c17 8992 (set (match_dup 0)
a260abc9
DE		 8993 (and:DI (rotate:DI (match_dup 0)
8994 (const_int 0))
8995 (match_dup 1)))]
8996 "")
8997
8998;; Split a load of a large constant into the appropriate five-instruction
8999;; sequence. Handle anything in a constant number of insns.
9000;; When non-easy constants can go in the TOC, this should use
9001;; easy_fp_constant predicate.
9002(define_split
9003 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 9004 (match_operand:DI 1 "const_int_operand" ""))]
9005 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9006 [(set (match_dup 0) (match_dup 2))
9007 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
e6ca2c17 9008 "
2bfcf297
DB		 9009{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9010
9011 if (tem == operands[0])
9012 DONE;
e8d791dd 9013 else
2bfcf297 9014 FAIL;
5f59ecb7 9015}")
e6ca2c17 9016
5f59ecb7
DE		 9017(define_split
9018 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2bfcf297
DB		 9019 (match_operand:DI 1 "const_double_operand" ""))]
9020 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9021 [(set (match_dup 0) (match_dup 2))
9022 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
5f59ecb7 9023 "
2bfcf297
DB		 9024{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9025
9026 if (tem == operands[0])
9027 DONE;
9028 else
9029 FAIL;
e6ca2c17 9030}")
acad7ed3 9031\f
1fd4e8c1
RK		 9032;; TImode is similar, except that we usually want to compute the address into
9033;; a register and use lsi/stsi (the exception is during reload). MQ is also
ca7f5001 9034;; clobbered in stsi for POWER, so we need a SCRATCH for it.
1fd4e8c1
RK		 9035
9036;; We say that MQ is clobbered in the last alternative because the first
9037;; alternative would never get used otherwise since it would need a reload
9038;; while the 2nd alternative would not. We put memory cases first so they
9039;; are preferred. Otherwise, we'd try to reload the output instead of
9040;; giving the SCRATCH mq.
3a1f863f 9041
a260abc9 9042(define_insn "*movti_power"
7f514158
AM		 9043 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9044 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9045 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
6ae08853 9046 "TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca 9047 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
1fd4e8c1
RK		 9048 "*
9049{
9050 switch (which_alternative)
9051 {
dc4f83ca 9052 default:
37409796 9053 gcc_unreachable ();
dc4f83ca 9054
1fd4e8c1 9055 case 0:
3a1f863f
DE		 9056 if (TARGET_STRING)
9057 return \"{stsi|stswi} %1,%P0,16\";
1fd4e8c1 9058 case 1:
1fd4e8c1 9059 case 2:
3a1f863f 9060 return \"#\";
1fd4e8c1
RK		 9061 case 3:
9062 /* If the address is not used in the output, we can use lsi. Otherwise,
9063 fall through to generating four loads. */
e876481c
DE		 9064 if (TARGET_STRING
9065 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
ca7f5001 9066 return \"{lsi|lswi} %0,%P1,16\";
82e41834 9067 /* ... fall through ... */
1fd4e8c1 9068 case 4:
7f514158 9069 case 5:
3a1f863f 9070 return \"#\";
1fd4e8c1
RK		 9071 }
9072}"
7f514158 9073 [(set_attr "type" "store,store,*,load,load,*")])
51b8fc2c 9074
a260abc9 9075(define_insn "*movti_string"
7f514158
AM		 9076 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9077 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
3a1f863f 9078 "! TARGET_POWER && ! TARGET_POWERPC64
dc4f83ca
MM		 9079 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9080 "*
9081{
9082 switch (which_alternative)
9083 {
9084 default:
37409796 9085 gcc_unreachable ();
dc4f83ca 9086 case 0:
3a1f863f
DE		 9087 if (TARGET_STRING)
9088 return \"{stsi|stswi} %1,%P0,16\";
dc4f83ca 9089 case 1:
cd1d3445 9090 case 2:
3a1f863f 9091 return \"#\";
cd1d3445
DE		 9092 case 3:
9093 /* If the address is not used in the output, we can use lsi. Otherwise,
9094 fall through to generating four loads. */
6ae08853 9095 if (TARGET_STRING
3a1f863f 9096 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
cd1d3445
DE		 9097 return \"{lsi|lswi} %0,%P1,16\";
9098 /* ... fall through ... */
9099 case 4:
7f514158 9100 case 5:
3a1f863f 9101 return \"#\";
dc4f83ca
MM		 9102 }
9103}"
9c6fdb46 9104 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
dc4f83ca 9105
a260abc9 9106(define_insn "*movti_ppc64"
112ccb83
GK		 9107 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9108 (match_operand:TI 1 "input_operand" "r,r,m"))]
51b8fc2c
RK		 9109 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9110 || gpc_reg_operand (operands[1], TImode))"
112ccb83 9111 "#"
3a1f863f
DE		 9112 [(set_attr "type" "*,load,store")])
9113
7f514158
AM		 9114(define_split
9115 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9116 (match_operand:TI 1 "const_double_operand" ""))]
9117 "TARGET_POWERPC64"
9118 [(set (match_dup 2) (match_dup 4))
9119 (set (match_dup 3) (match_dup 5))]
9120 "
9121{
9122 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9123 TImode);
9124 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9125 TImode);
9126 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9127 {
9128 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9129 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9130 }
9131 else if (GET_CODE (operands[1]) == CONST_INT)
9132 {
9133 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9134 operands[5] = operands[1];
9135 }
9136 else
9137 FAIL;
9138}")
9139
3a1f863f
DE		 9140(define_split
9141 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9142 (match_operand:TI 1 "input_operand" ""))]
a9baceb1 9143 "reload_completed
3a1f863f 9144 && gpr_or_gpr_p (operands[0], operands[1])"
a9baceb1
GK		 9145 [(pc)]
9146{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
1fd4e8c1
RK		 9147\f
9148(define_expand "load_multiple"
2f622005
RK		 9149 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9150 (match_operand:SI 1 "" ""))
9151 (use (match_operand:SI 2 "" ""))])]
09a625f7 9152 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9153 "
9154{
9155 int regno;
9156 int count;
792760b9 9157 rtx op1;
1fd4e8c1
RK		 9158 int i;
9159
9160 /* Support only loading a constant number of fixed-point registers from
9161 memory and only bother with this if more than two; the machine
9162 doesn't support more than eight. */
9163 if (GET_CODE (operands[2]) != CONST_INT
9164 || INTVAL (operands[2]) <= 2
9165 || INTVAL (operands[2]) > 8
9166 || GET_CODE (operands[1]) != MEM
9167 || GET_CODE (operands[0]) != REG
9168 || REGNO (operands[0]) >= 32)
9169 FAIL;
9170
9171 count = INTVAL (operands[2]);
9172 regno = REGNO (operands[0]);
9173
39403d82 9174 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
792760b9
RK		 9175 op1 = replace_equiv_address (operands[1],
9176 force_reg (SImode, XEXP (operands[1], 0)));
1fd4e8c1
RK		 9177
9178 for (i = 0; i < count; i++)
9179 XVECEXP (operands[3], 0, i)
39403d82 9180 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
7ef788f0 9181 adjust_address_nv (op1, SImode, i * 4));
1fd4e8c1
RK		 9182}")
9183
9caa3eb2 9184(define_insn "*ldmsi8"
1fd4e8c1 9185 [(match_parallel 0 "load_multiple_operation"
9caa3eb2
DE		 9186 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9187 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9188 (set (match_operand:SI 3 "gpc_reg_operand" "")
9189 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9190 (set (match_operand:SI 4 "gpc_reg_operand" "")
9191 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9192 (set (match_operand:SI 5 "gpc_reg_operand" "")
9193 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9194 (set (match_operand:SI 6 "gpc_reg_operand" "")
9195 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9196 (set (match_operand:SI 7 "gpc_reg_operand" "")
9197 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9198 (set (match_operand:SI 8 "gpc_reg_operand" "")
9199 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9200 (set (match_operand:SI 9 "gpc_reg_operand" "")
9201 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9202 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
1fd4e8c1 9203 "*
9caa3eb2 9204{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9205 [(set_attr "type" "load_ux")
9caa3eb2 9206 (set_attr "length" "32")])
1fd4e8c1 9207
9caa3eb2
DE		 9208(define_insn "*ldmsi7"
9209 [(match_parallel 0 "load_multiple_operation"
9210 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9211 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9212 (set (match_operand:SI 3 "gpc_reg_operand" "")
9213 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9214 (set (match_operand:SI 4 "gpc_reg_operand" "")
9215 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9216 (set (match_operand:SI 5 "gpc_reg_operand" "")
9217 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9218 (set (match_operand:SI 6 "gpc_reg_operand" "")
9219 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9220 (set (match_operand:SI 7 "gpc_reg_operand" "")
9221 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9222 (set (match_operand:SI 8 "gpc_reg_operand" "")
9223 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9224 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9225 "*
9226{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9227 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9228 (set_attr "length" "32")])
9229
9230(define_insn "*ldmsi6"
9231 [(match_parallel 0 "load_multiple_operation"
9232 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9233 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9234 (set (match_operand:SI 3 "gpc_reg_operand" "")
9235 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9236 (set (match_operand:SI 4 "gpc_reg_operand" "")
9237 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9238 (set (match_operand:SI 5 "gpc_reg_operand" "")
9239 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9240 (set (match_operand:SI 6 "gpc_reg_operand" "")
9241 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9242 (set (match_operand:SI 7 "gpc_reg_operand" "")
9243 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9244 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9245 "*
9246{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9247 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9248 (set_attr "length" "32")])
9249
9250(define_insn "*ldmsi5"
9251 [(match_parallel 0 "load_multiple_operation"
9252 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9253 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9254 (set (match_operand:SI 3 "gpc_reg_operand" "")
9255 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9256 (set (match_operand:SI 4 "gpc_reg_operand" "")
9257 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9258 (set (match_operand:SI 5 "gpc_reg_operand" "")
9259 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9260 (set (match_operand:SI 6 "gpc_reg_operand" "")
9261 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9262 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9263 "*
9264{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9265 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9266 (set_attr "length" "32")])
9267
9268(define_insn "*ldmsi4"
9269 [(match_parallel 0 "load_multiple_operation"
9270 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9271 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9272 (set (match_operand:SI 3 "gpc_reg_operand" "")
9273 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9274 (set (match_operand:SI 4 "gpc_reg_operand" "")
9275 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9276 (set (match_operand:SI 5 "gpc_reg_operand" "")
9277 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9278 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9279 "*
9280{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9281 [(set_attr "type" "load_ux")
9caa3eb2
DE		 9282 (set_attr "length" "32")])
9283
9284(define_insn "*ldmsi3"
9285 [(match_parallel 0 "load_multiple_operation"
9286 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9287 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9288 (set (match_operand:SI 3 "gpc_reg_operand" "")
9289 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9290 (set (match_operand:SI 4 "gpc_reg_operand" "")
9291 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9292 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9293 "*
9294{ return rs6000_output_load_multiple (operands); }"
9c6fdb46 9295 [(set_attr "type" "load_ux")
e82ee4cc 9296 (set_attr "length" "32")])
b19003d8 9297
1fd4e8c1 9298(define_expand "store_multiple"
2f622005
RK		 9299 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9300 (match_operand:SI 1 "" ""))
9301 (clobber (scratch:SI))
9302 (use (match_operand:SI 2 "" ""))])]
09a625f7 9303 "TARGET_STRING && !TARGET_POWERPC64"
1fd4e8c1
RK		 9304 "
9305{
9306 int regno;
9307 int count;
9308 rtx to;
792760b9 9309 rtx op0;
1fd4e8c1
RK		 9310 int i;
9311
9312 /* Support only storing a constant number of fixed-point registers to
9313 memory and only bother with this if more than two; the machine
9314 doesn't support more than eight. */
9315 if (GET_CODE (operands[2]) != CONST_INT
9316 || INTVAL (operands[2]) <= 2
9317 || INTVAL (operands[2]) > 8
9318 || GET_CODE (operands[0]) != MEM
9319 || GET_CODE (operands[1]) != REG
9320 || REGNO (operands[1]) >= 32)
9321 FAIL;
9322
9323 count = INTVAL (operands[2]);
9324 regno = REGNO (operands[1]);
9325
39403d82 9326 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
1fd4e8c1 9327 to = force_reg (SImode, XEXP (operands[0], 0));
792760b9 9328 op0 = replace_equiv_address (operands[0], to);
1fd4e8c1
RK		 9329
9330 XVECEXP (operands[3], 0, 0)
7ef788f0 9331 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
39403d82 9332 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
c5c76735 9333 gen_rtx_SCRATCH (SImode));
1fd4e8c1
RK		 9334
9335 for (i = 1; i < count; i++)
9336 XVECEXP (operands[3], 0, i + 1)
39403d82 9337 = gen_rtx_SET (VOIDmode,
7ef788f0 9338 adjust_address_nv (op0, SImode, i * 4),
c5c76735 9339 gen_rtx_REG (SImode, regno + i));
1fd4e8c1
RK		 9340}")
9341
e46e3130 9342(define_insn "*stmsi8"
d14a6d05 9343 [(match_parallel 0 "store_multiple_operation"
e46e3130
DJ		 9344 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9345 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9346 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9347 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9348 (match_operand:SI 4 "gpc_reg_operand" "r"))
9349 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9350 (match_operand:SI 5 "gpc_reg_operand" "r"))
9351 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9352 (match_operand:SI 6 "gpc_reg_operand" "r"))
9353 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9354 (match_operand:SI 7 "gpc_reg_operand" "r"))
9355 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9356 (match_operand:SI 8 "gpc_reg_operand" "r"))
9357 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9358 (match_operand:SI 9 "gpc_reg_operand" "r"))
9359 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9360 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9361 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9362 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9363 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9364
9365(define_insn "*stmsi7"
9366 [(match_parallel 0 "store_multiple_operation"
9367 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9368 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9369 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9370 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9371 (match_operand:SI 4 "gpc_reg_operand" "r"))
9372 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9373 (match_operand:SI 5 "gpc_reg_operand" "r"))
9374 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9375 (match_operand:SI 6 "gpc_reg_operand" "r"))
9376 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9377 (match_operand:SI 7 "gpc_reg_operand" "r"))
9378 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9379 (match_operand:SI 8 "gpc_reg_operand" "r"))
9380 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9381 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9382 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9383 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9384 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9385
9386(define_insn "*stmsi6"
9387 [(match_parallel 0 "store_multiple_operation"
9388 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9389 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9390 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9391 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9392 (match_operand:SI 4 "gpc_reg_operand" "r"))
9393 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9394 (match_operand:SI 5 "gpc_reg_operand" "r"))
9395 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9396 (match_operand:SI 6 "gpc_reg_operand" "r"))
9397 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9398 (match_operand:SI 7 "gpc_reg_operand" "r"))
9399 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9400 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9401 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9402 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9403 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9404
9405(define_insn "*stmsi5"
9406 [(match_parallel 0 "store_multiple_operation"
9407 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9408 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9409 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9410 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9411 (match_operand:SI 4 "gpc_reg_operand" "r"))
9412 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9413 (match_operand:SI 5 "gpc_reg_operand" "r"))
9414 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9415 (match_operand:SI 6 "gpc_reg_operand" "r"))
9416 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9417 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9418 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9419 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9420 [(set_attr "type" "store_ux")])
e46e3130
DJ		 9421
9422(define_insn "*stmsi4"
9423 [(match_parallel 0 "store_multiple_operation"
9424 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9425 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9426 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9427 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9428 (match_operand:SI 4 "gpc_reg_operand" "r"))
9429 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9430 (match_operand:SI 5 "gpc_reg_operand" "r"))
9431 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9432 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9433 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
b7ff3d82 9434 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9435 [(set_attr "type" "store_ux")])
7e69e155 9436
e46e3130
DJ		 9437(define_insn "*stmsi3"
9438 [(match_parallel 0 "store_multiple_operation"
9439 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9440 (match_operand:SI 2 "gpc_reg_operand" "r"))
edd54d25 9441 (clobber (match_scratch:SI 3 "=X"))
e46e3130
DJ		 9442 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9443 (match_operand:SI 4 "gpc_reg_operand" "r"))
9444 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9445 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9446 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9447 "{stsi|stswi} %2,%1,%O0"
9c6fdb46 9448 [(set_attr "type" "store_ux")])
d2894ab5
DE		 9449
9450(define_insn "*stmsi8_power"
9451 [(match_parallel 0 "store_multiple_operation"
9452 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9453 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9454 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9455 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9456 (match_operand:SI 4 "gpc_reg_operand" "r"))
9457 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9458 (match_operand:SI 5 "gpc_reg_operand" "r"))
9459 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9460 (match_operand:SI 6 "gpc_reg_operand" "r"))
9461 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9462 (match_operand:SI 7 "gpc_reg_operand" "r"))
9463 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9464 (match_operand:SI 8 "gpc_reg_operand" "r"))
9465 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9466 (match_operand:SI 9 "gpc_reg_operand" "r"))
9467 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9468 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9469 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9470 "{stsi|stswi} %2,%1,%O0"
9471 [(set_attr "type" "store_ux")])
9472
9473(define_insn "*stmsi7_power"
9474 [(match_parallel 0 "store_multiple_operation"
9475 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9476 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9477 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9478 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9479 (match_operand:SI 4 "gpc_reg_operand" "r"))
9480 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9481 (match_operand:SI 5 "gpc_reg_operand" "r"))
9482 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9483 (match_operand:SI 6 "gpc_reg_operand" "r"))
9484 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9485 (match_operand:SI 7 "gpc_reg_operand" "r"))
9486 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9487 (match_operand:SI 8 "gpc_reg_operand" "r"))
9488 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9489 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9490 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9491 "{stsi|stswi} %2,%1,%O0"
9492 [(set_attr "type" "store_ux")])
9493
9494(define_insn "*stmsi6_power"
9495 [(match_parallel 0 "store_multiple_operation"
9496 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9497 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9498 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9499 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9500 (match_operand:SI 4 "gpc_reg_operand" "r"))
9501 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9502 (match_operand:SI 5 "gpc_reg_operand" "r"))
9503 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9504 (match_operand:SI 6 "gpc_reg_operand" "r"))
9505 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9506 (match_operand:SI 7 "gpc_reg_operand" "r"))
9507 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9508 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9509 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9510 "{stsi|stswi} %2,%1,%O0"
9511 [(set_attr "type" "store_ux")])
9512
9513(define_insn "*stmsi5_power"
9514 [(match_parallel 0 "store_multiple_operation"
9515 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9516 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9517 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9518 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9519 (match_operand:SI 4 "gpc_reg_operand" "r"))
9520 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9521 (match_operand:SI 5 "gpc_reg_operand" "r"))
9522 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9523 (match_operand:SI 6 "gpc_reg_operand" "r"))
9524 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9525 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9526 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9527 "{stsi|stswi} %2,%1,%O0"
9528 [(set_attr "type" "store_ux")])
9529
9530(define_insn "*stmsi4_power"
9531 [(match_parallel 0 "store_multiple_operation"
9532 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9533 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9534 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9535 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9536 (match_operand:SI 4 "gpc_reg_operand" "r"))
9537 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9538 (match_operand:SI 5 "gpc_reg_operand" "r"))
9539 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9540 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9541 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9542 "{stsi|stswi} %2,%1,%O0"
9543 [(set_attr "type" "store_ux")])
9544
9545(define_insn "*stmsi3_power"
9546 [(match_parallel 0 "store_multiple_operation"
9547 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9548 (match_operand:SI 2 "gpc_reg_operand" "r"))
1958f718 9549 (clobber (match_scratch:SI 3 "=q"))
d2894ab5
DE		 9550 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9551 (match_operand:SI 4 "gpc_reg_operand" "r"))
9552 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9553 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9554 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9555 "{stsi|stswi} %2,%1,%O0"
9556 [(set_attr "type" "store_ux")])
7e69e155 9557\f
57e84f18 9558(define_expand "setmemsi"
fba73eb1 9559 [(parallel [(set (match_operand:BLK 0 "" "")
98843c92 9560 (match_operand 2 "const_int_operand" ""))
fba73eb1 9561 (use (match_operand:SI 1 "" ""))
57e84f18 9562 (use (match_operand:SI 3 "" ""))])]
fba73eb1
DE		 9563 ""
9564 "
9565{
57e84f18 9566 /* If value to set is not zero, use the library routine. */
a05be2e0 9567 if (operands[2] != const0_rtx)
57e84f18
AS		 9568 FAIL;
9569
fba73eb1
DE		 9570 if (expand_block_clear (operands))
9571 DONE;
9572 else
9573 FAIL;
9574}")
9575
7e69e155
MM		 9576;; String/block move insn.
9577;; Argument 0 is the destination
9578;; Argument 1 is the source
9579;; Argument 2 is the length
9580;; Argument 3 is the alignment
9581
70128ad9 9582(define_expand "movmemsi"
b6c9286a
MM		 9583 [(parallel [(set (match_operand:BLK 0 "" "")
9584 (match_operand:BLK 1 "" ""))
9585 (use (match_operand:SI 2 "" ""))
9586 (use (match_operand:SI 3 "" ""))])]
7e69e155
MM		 9587 ""
9588 "
9589{
9590 if (expand_block_move (operands))
9591 DONE;
9592 else
9593 FAIL;
9594}")
9595
9596;; Move up to 32 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9597;; register allocator doesn't have a clue about allocating 8 word registers.
9598;; rD/rS = r5 is preferred, efficient form.
70128ad9 9599(define_expand "movmemsi_8reg"
b6c9286a
MM		 9600 [(parallel [(set (match_operand 0 "" "")
9601 (match_operand 1 "" ""))
9602 (use (match_operand 2 "" ""))
9603 (use (match_operand 3 "" ""))
7e69e155
MM		 9604 (clobber (reg:SI 5))
9605 (clobber (reg:SI 6))
9606 (clobber (reg:SI 7))
9607 (clobber (reg:SI 8))
9608 (clobber (reg:SI 9))
9609 (clobber (reg:SI 10))
9610 (clobber (reg:SI 11))
9611 (clobber (reg:SI 12))
3c67b673 9612 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9613 "TARGET_STRING"
9614 "")
9615
9616(define_insn ""
52d3af72
DE		 9617 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9618 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9619 (use (match_operand:SI 2 "immediate_operand" "i"))
9620 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9621 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
7e69e155
MM		 9622 (clobber (reg:SI 6))
9623 (clobber (reg:SI 7))
9624 (clobber (reg:SI 8))
9625 (clobber (reg:SI 9))
9626 (clobber (reg:SI 10))
9627 (clobber (reg:SI 11))
9628 (clobber (reg:SI 12))
3c67b673 9629 (clobber (match_scratch:SI 5 "=q"))]
7e69e155 9630 "TARGET_STRING && TARGET_POWER
f9562f27
DE		 9631 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9632 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9633 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9634 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9635 && REGNO (operands[4]) == 5"
9636 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9637 [(set_attr "type" "store_ux")
b7ff3d82 9638 (set_attr "length" "8")])
7e69e155
MM		 9639
9640(define_insn ""
4ae234b0
GK		 9641 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9642 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9643 (use (match_operand:SI 2 "immediate_operand" "i"))
9644 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9645 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
7e69e155
MM		 9646 (clobber (reg:SI 6))
9647 (clobber (reg:SI 7))
9648 (clobber (reg:SI 8))
9649 (clobber (reg:SI 9))
9650 (clobber (reg:SI 10))
9651 (clobber (reg:SI 11))
9652 (clobber (reg:SI 12))
edd54d25 9653 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9654 "TARGET_STRING && ! TARGET_POWER
f9562f27
DE		 9655 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9656 || INTVAL (operands[2]) == 0)
7e69e155
MM		 9657 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9658 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
3c67b673
RK		 9659 && REGNO (operands[4]) == 5"
9660 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9661 [(set_attr "type" "store_ux")
b7ff3d82 9662 (set_attr "length" "8")])
7e69e155
MM		 9663
9664;; Move up to 24 bytes at a time. The fixed registers are needed because the
f9562f27
DE		 9665;; register allocator doesn't have a clue about allocating 6 word registers.
9666;; rD/rS = r5 is preferred, efficient form.
70128ad9 9667(define_expand "movmemsi_6reg"
b6c9286a
MM		 9668 [(parallel [(set (match_operand 0 "" "")
9669 (match_operand 1 "" ""))
9670 (use (match_operand 2 "" ""))
9671 (use (match_operand 3 "" ""))
f9562f27
DE		 9672 (clobber (reg:SI 5))
9673 (clobber (reg:SI 6))
7e69e155
MM		 9674 (clobber (reg:SI 7))
9675 (clobber (reg:SI 8))
9676 (clobber (reg:SI 9))
9677 (clobber (reg:SI 10))
3c67b673 9678 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9679 "TARGET_STRING"
9680 "")
9681
9682(define_insn ""
52d3af72
DE		 9683 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9684 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9685 (use (match_operand:SI 2 "immediate_operand" "i"))
9686 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9687 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
f9562f27
DE		 9688 (clobber (reg:SI 6))
9689 (clobber (reg:SI 7))
7e69e155
MM		 9690 (clobber (reg:SI 8))
9691 (clobber (reg:SI 9))
9692 (clobber (reg:SI 10))
3c67b673 9693 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9694 "TARGET_STRING && TARGET_POWER
9695 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
f9562f27
DE		 9696 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9697 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9698 && REGNO (operands[4]) == 5"
3c67b673 9699 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9700 [(set_attr "type" "store_ux")
b7ff3d82 9701 (set_attr "length" "8")])
7e69e155
MM		 9702
9703(define_insn ""
4ae234b0
GK		 9704 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9705 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9706 (use (match_operand:SI 2 "immediate_operand" "i"))
9707 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9708 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
f9562f27
DE		 9709 (clobber (reg:SI 6))
9710 (clobber (reg:SI 7))
7e69e155
MM		 9711 (clobber (reg:SI 8))
9712 (clobber (reg:SI 9))
9713 (clobber (reg:SI 10))
edd54d25 9714 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9715 "TARGET_STRING && ! TARGET_POWER
7e69e155 9716 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
f9562f27
DE		 9717 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9718 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9719 && REGNO (operands[4]) == 5"
3c67b673 9720 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9721 [(set_attr "type" "store_ux")
b7ff3d82 9722 (set_attr "length" "8")])
7e69e155 9723
f9562f27
DE		 9724;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9725;; problems with TImode.
9726;; rD/rS = r5 is preferred, efficient form.
70128ad9 9727(define_expand "movmemsi_4reg"
b6c9286a
MM		 9728 [(parallel [(set (match_operand 0 "" "")
9729 (match_operand 1 "" ""))
9730 (use (match_operand 2 "" ""))
9731 (use (match_operand 3 "" ""))
f9562f27
DE		 9732 (clobber (reg:SI 5))
9733 (clobber (reg:SI 6))
9734 (clobber (reg:SI 7))
9735 (clobber (reg:SI 8))
3c67b673 9736 (clobber (match_scratch:SI 4 ""))])]
7e69e155
MM		 9737 "TARGET_STRING"
9738 "")
9739
9740(define_insn ""
52d3af72
DE		 9741 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9742 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9743 (use (match_operand:SI 2 "immediate_operand" "i"))
9744 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9745 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
f9562f27
DE		 9746 (clobber (reg:SI 6))
9747 (clobber (reg:SI 7))
9748 (clobber (reg:SI 8))
3c67b673 9749 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9750 "TARGET_STRING && TARGET_POWER
9751 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9752 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9753 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9754 && REGNO (operands[4]) == 5"
3c67b673 9755 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9756 [(set_attr "type" "store_ux")
b7ff3d82 9757 (set_attr "length" "8")])
7e69e155
MM		 9758
9759(define_insn ""
4ae234b0
GK		 9760 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9761 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9762 (use (match_operand:SI 2 "immediate_operand" "i"))
9763 (use (match_operand:SI 3 "immediate_operand" "i"))
423addc5 9764 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
f9562f27
DE		 9765 (clobber (reg:SI 6))
9766 (clobber (reg:SI 7))
9767 (clobber (reg:SI 8))
edd54d25 9768 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9769 "TARGET_STRING && ! TARGET_POWER
7e69e155 9770 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
f9562f27
DE		 9771 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9772 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9773 && REGNO (operands[4]) == 5"
3c67b673 9774 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9775 [(set_attr "type" "store_ux")
b7ff3d82 9776 (set_attr "length" "8")])
7e69e155
MM		 9777
9778;; Move up to 8 bytes at a time.
70128ad9 9779(define_expand "movmemsi_2reg"
b6c9286a
MM		 9780 [(parallel [(set (match_operand 0 "" "")
9781 (match_operand 1 "" ""))
9782 (use (match_operand 2 "" ""))
9783 (use (match_operand 3 "" ""))
3c67b673
RK		 9784 (clobber (match_scratch:DI 4 ""))
9785 (clobber (match_scratch:SI 5 ""))])]
f9562f27 9786 "TARGET_STRING && ! TARGET_POWERPC64"
7e69e155
MM		 9787 "")
9788
9789(define_insn ""
52d3af72
DE		 9790 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9791 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9792 (use (match_operand:SI 2 "immediate_operand" "i"))
9793 (use (match_operand:SI 3 "immediate_operand" "i"))
9794 (clobber (match_scratch:DI 4 "=&r"))
9795 (clobber (match_scratch:SI 5 "=q"))]
f9562f27 9796 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
3c67b673
RK		 9797 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9798 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9799 [(set_attr "type" "store_ux")
b7ff3d82 9800 (set_attr "length" "8")])
7e69e155
MM		 9801
9802(define_insn ""
52d3af72
DE		 9803 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9804 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9805 (use (match_operand:SI 2 "immediate_operand" "i"))
9806 (use (match_operand:SI 3 "immediate_operand" "i"))
9807 (clobber (match_scratch:DI 4 "=&r"))
edd54d25 9808 (clobber (match_scratch:SI 5 "=X"))]
f9562f27 9809 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
7e69e155 9810 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
3c67b673 9811 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9812 [(set_attr "type" "store_ux")
b7ff3d82 9813 (set_attr "length" "8")])
7e69e155
MM		 9814
9815;; Move up to 4 bytes at a time.
70128ad9 9816(define_expand "movmemsi_1reg"
b6c9286a
MM		 9817 [(parallel [(set (match_operand 0 "" "")
9818 (match_operand 1 "" ""))
9819 (use (match_operand 2 "" ""))
9820 (use (match_operand 3 "" ""))
3c67b673
RK		 9821 (clobber (match_scratch:SI 4 ""))
9822 (clobber (match_scratch:SI 5 ""))])]
7e69e155
MM		 9823 "TARGET_STRING"
9824 "")
9825
9826(define_insn ""
52d3af72
DE		 9827 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9828 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9829 (use (match_operand:SI 2 "immediate_operand" "i"))
9830 (use (match_operand:SI 3 "immediate_operand" "i"))
9831 (clobber (match_scratch:SI 4 "=&r"))
9832 (clobber (match_scratch:SI 5 "=q"))]
7e69e155
MM		 9833 "TARGET_STRING && TARGET_POWER
9834 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
3c67b673 9835 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9836 [(set_attr "type" "store_ux")
b7ff3d82 9837 (set_attr "length" "8")])
7e69e155
MM		 9838
9839(define_insn ""
4ae234b0
GK		 9840 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9841 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
3c67b673
RK		 9842 (use (match_operand:SI 2 "immediate_operand" "i"))
9843 (use (match_operand:SI 3 "immediate_operand" "i"))
9844 (clobber (match_scratch:SI 4 "=&r"))
edd54d25 9845 (clobber (match_scratch:SI 5 "=X"))]
0ad91047 9846 "TARGET_STRING && ! TARGET_POWER
7e69e155 9847 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
09a625f7 9848 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9c6fdb46 9849 [(set_attr "type" "store_ux")
09a625f7 9850 (set_attr "length" "8")])
1fd4e8c1 9851\f
7e69e155 9852;; Define insns that do load or store with update. Some of these we can
1fd4e8c1
RK		 9853;; get by using pre-decrement or pre-increment, but the hardware can also
9854;; do cases where the increment is not the size of the object.
9855;;
9856;; In all these cases, we use operands 0 and 1 for the register being
9857;; incremented because those are the operands that local-alloc will
9858;; tie and these are the pair most likely to be tieable (and the ones
9859;; that will benefit the most).
9860
38c1f2d7 9861(define_insn "*movdi_update1"
51b8fc2c 9862 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
ad8bd902 9863 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
768070a0 9864 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
51b8fc2c
RK		 9865 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9866 (plus:DI (match_dup 1) (match_dup 2)))]
38c1f2d7 9867 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9868 "@
9869 ldux %3,%0,%2
9870 ldu %3,%2(%0)"
b54cf83a 9871 [(set_attr "type" "load_ux,load_u")])
287f13ff 9872
2e6c9641
FJ		 9873(define_insn "movdi_<mode>_update"
9874 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9875 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
51b8fc2c 9876 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
2e6c9641
FJ		 9877 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9878 (plus:P (match_dup 1) (match_dup 2)))]
38c1f2d7 9879 "TARGET_POWERPC64 && TARGET_UPDATE"
51b8fc2c
RK		 9880 "@
9881 stdux %3,%0,%2
b7ff3d82 9882 stdu %3,%2(%0)"
b54cf83a 9883 [(set_attr "type" "store_ux,store_u")])
51b8fc2c 9884
38c1f2d7 9885(define_insn "*movsi_update1"
cd2b37d9
RK		 9886 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9887 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9888 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9889 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9890 (plus:SI (match_dup 1) (match_dup 2)))]
f7b3ab8a 9891 "TARGET_UPDATE"
1fd4e8c1 9892 "@
ca7f5001
RK		 9893 {lux|lwzux} %3,%0,%2
9894 {lu|lwzu} %3,%2(%0)"
b54cf83a
DE		 9895 [(set_attr "type" "load_ux,load_u")])
9896
9897(define_insn "*movsi_update2"
9898 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9899 (sign_extend:DI
9900 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9901 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9902 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9903 (plus:DI (match_dup 1) (match_dup 2)))]
9904 "TARGET_POWERPC64"
9905 "lwaux %3,%0,%2"
9906 [(set_attr "type" "load_ext_ux")])
1fd4e8c1 9907
4697a36c 9908(define_insn "movsi_update"
cd2b37d9 9909 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9910 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9911 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9912 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9913 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9914 "TARGET_UPDATE"
1fd4e8c1 9915 "@
ca7f5001 9916 {stux|stwux} %3,%0,%2
b7ff3d82 9917 {stu|stwu} %3,%2(%0)"
b54cf83a 9918 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9919
b54cf83a 9920(define_insn "*movhi_update1"
cd2b37d9
RK		 9921 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9922 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9923 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9924 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9925 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9926 "TARGET_UPDATE"
1fd4e8c1 9927 "@
5f243543
RK		 9928 lhzux %3,%0,%2
9929 lhzu %3,%2(%0)"
b54cf83a 9930 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9931
38c1f2d7 9932(define_insn "*movhi_update2"
cd2b37d9 9933 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9934 (zero_extend:SI
cd2b37d9 9935 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9936 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9937 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9938 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9939 "TARGET_UPDATE"
1fd4e8c1 9940 "@
5f243543
RK		 9941 lhzux %3,%0,%2
9942 lhzu %3,%2(%0)"
b54cf83a 9943 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9944
38c1f2d7 9945(define_insn "*movhi_update3"
cd2b37d9 9946 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9947 (sign_extend:SI
cd2b37d9 9948 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9949 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9950 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9951 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9952 "TARGET_UPDATE"
1fd4e8c1 9953 "@
5f243543
RK		 9954 lhaux %3,%0,%2
9955 lhau %3,%2(%0)"
b54cf83a 9956 [(set_attr "type" "load_ext_ux,load_ext_u")])
1fd4e8c1 9957
38c1f2d7 9958(define_insn "*movhi_update4"
cd2b37d9 9959 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9960 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9961 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9962 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9963 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9964 "TARGET_UPDATE"
1fd4e8c1 9965 "@
5f243543 9966 sthux %3,%0,%2
b7ff3d82 9967 sthu %3,%2(%0)"
b54cf83a 9968 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 9969
38c1f2d7 9970(define_insn "*movqi_update1"
cd2b37d9
RK		 9971 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9972 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9973 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 9974 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9975 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9976 "TARGET_UPDATE"
1fd4e8c1 9977 "@
5f243543
RK		 9978 lbzux %3,%0,%2
9979 lbzu %3,%2(%0)"
b54cf83a 9980 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9981
38c1f2d7 9982(define_insn "*movqi_update2"
cd2b37d9 9983 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 9984 (zero_extend:SI
cd2b37d9 9985 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9986 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
cd2b37d9 9987 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 9988 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 9989 "TARGET_UPDATE"
1fd4e8c1 9990 "@
5f243543
RK		 9991 lbzux %3,%0,%2
9992 lbzu %3,%2(%0)"
b54cf83a 9993 [(set_attr "type" "load_ux,load_u")])
1fd4e8c1 9994
38c1f2d7 9995(define_insn "*movqi_update3"
cd2b37d9 9996 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 9997 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 9998 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9999 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10000 (plus:SI (match_dup 1) (match_dup 2)))]
38c1f2d7 10001 "TARGET_UPDATE"
1fd4e8c1 10002 "@
5f243543 10003 stbux %3,%0,%2
b7ff3d82 10004 stbu %3,%2(%0)"
b54cf83a 10005 [(set_attr "type" "store_ux,store_u")])
1fd4e8c1 10006
38c1f2d7 10007(define_insn "*movsf_update1"
cd2b37d9 10008 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
df8b713c 10009 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10010 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10011 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10012 (plus:SI (match_dup 1) (match_dup 2)))]
cf8e1455 10013 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10014 "@
5f243543
RK		 10015 lfsux %3,%0,%2
10016 lfsu %3,%2(%0)"
b54cf83a 10017 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10018
38c1f2d7 10019(define_insn "*movsf_update2"
cd2b37d9 10020 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10021 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10022 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10023 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10024 (plus:SI (match_dup 1) (match_dup 2)))]
cf8e1455 10025 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10026 "@
85fff2f3 10027 stfsux %3,%0,%2
b7ff3d82 10028 stfsu %3,%2(%0)"
b54cf83a 10029 [(set_attr "type" "fpstore_ux,fpstore_u")])
1fd4e8c1 10030
38c1f2d7
MM		 10031(define_insn "*movsf_update3"
10032 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10033 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10034 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10035 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10036 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10037 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 10038 "@
10039 {lux|lwzux} %3,%0,%2
10040 {lu|lwzu} %3,%2(%0)"
b54cf83a 10041 [(set_attr "type" "load_ux,load_u")])
38c1f2d7
MM		 10042
10043(define_insn "*movsf_update4"
10044 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10045 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10046 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10047 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10048 (plus:SI (match_dup 1) (match_dup 2)))]
a3170dc6 10049 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
38c1f2d7
MM		 10050 "@
10051 {stux|stwux} %3,%0,%2
10052 {stu|stwu} %3,%2(%0)"
b54cf83a 10053 [(set_attr "type" "store_ux,store_u")])
38c1f2d7
MM		 10054
10055(define_insn "*movdf_update1"
cd2b37d9
RK		 10056 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10057 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10058 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
cd2b37d9 10059 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10060 (plus:SI (match_dup 1) (match_dup 2)))]
cf8e1455 10061 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10062 "@
5f243543
RK		 10063 lfdux %3,%0,%2
10064 lfdu %3,%2(%0)"
b54cf83a 10065 [(set_attr "type" "fpload_ux,fpload_u")])
1fd4e8c1 10066
38c1f2d7 10067(define_insn "*movdf_update2"
cd2b37d9 10068 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
1fd4e8c1 10069 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
cd2b37d9
RK		 10070 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10071 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
1fd4e8c1 10072 (plus:SI (match_dup 1) (match_dup 2)))]
cf8e1455 10073 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
1fd4e8c1 10074 "@
5f243543 10075 stfdux %3,%0,%2
b7ff3d82 10076 stfdu %3,%2(%0)"
b54cf83a 10077 [(set_attr "type" "fpstore_ux,fpstore_u")])
4c70a4f3
RK		 10078
10079;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10080
90f81f99 10081(define_insn "*lfq_power2"
bb8df8a6
EC		 10082 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10083 (match_operand:V2DF 1 "memory_operand" ""))]
90f81f99
AP		 10084 "TARGET_POWER2
10085 && TARGET_HARD_FLOAT && TARGET_FPRS"
bb8df8a6 10086 "lfq%U1%X1 %0,%1")
90f81f99
AP		 10087
10088(define_peephole2
10089 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4c70a4f3 10090 (match_operand:DF 1 "memory_operand" ""))
90f81f99 10091 (set (match_operand:DF 2 "gpc_reg_operand" "")
4c70a4f3
RK		 10092 (match_operand:DF 3 "memory_operand" ""))]
10093 "TARGET_POWER2
cf8e1455 10094 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3 10095 && registers_ok_for_quad_peep (operands[0], operands[2])
90f81f99
AP		 10096 && mems_ok_for_quad_peep (operands[1], operands[3])"
10097 [(set (match_dup 0)
bb8df8a6
EC		 10098 (match_dup 1))]
10099 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10100 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
4c70a4f3 10101
90f81f99 10102(define_insn "*stfq_power2"
bb8df8a6
EC		 10103 [(set (match_operand:V2DF 0 "memory_operand" "")
10104 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
90f81f99
AP		 10105 "TARGET_POWER2
10106 && TARGET_HARD_FLOAT && TARGET_FPRS"
10107 "stfq%U0%X0 %1,%0")
10108
10109
10110(define_peephole2
4c70a4f3 10111 [(set (match_operand:DF 0 "memory_operand" "")
90f81f99 10112 (match_operand:DF 1 "gpc_reg_operand" ""))
4c70a4f3 10113 (set (match_operand:DF 2 "memory_operand" "")
90f81f99 10114 (match_operand:DF 3 "gpc_reg_operand" ""))]
4c70a4f3 10115 "TARGET_POWER2
cf8e1455 10116 && TARGET_HARD_FLOAT && TARGET_FPRS
4c70a4f3 10117 && registers_ok_for_quad_peep (operands[1], operands[3])
90f81f99
AP		 10118 && mems_ok_for_quad_peep (operands[0], operands[2])"
10119 [(set (match_dup 0)
10120 (match_dup 1))]
bb8df8a6
EC		 10121 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10122 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
2f4d9502 10123
036aadfc 10124;; After inserting conditional returns we can sometimes have
2f4d9502
NS		 10125;; unnecessary register moves. Unfortunately we cannot have a
10126;; modeless peephole here, because some single SImode sets have early
10127;; clobber outputs. Although those sets expand to multi-ppc-insn
10128;; sequences, using get_attr_length here will smash the operands
10129;; array. Neither is there an early_cobbler_p predicate.
036aadfc 10130;; Disallow subregs for E500 so we don't munge frob_di_df_2.
2f4d9502
NS		 10131(define_peephole2
10132 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10133 (match_operand:DF 1 "any_operand" ""))
10134 (set (match_operand:DF 2 "gpc_reg_operand" "")
10135 (match_dup 0))]
036aadfc
AM		 10136 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10137 && peep2_reg_dead_p (2, operands[0])"
2f4d9502
NS		 10138 [(set (match_dup 2) (match_dup 1))])
10139
10140(define_peephole2
10141 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10142 (match_operand:SF 1 "any_operand" ""))
10143 (set (match_operand:SF 2 "gpc_reg_operand" "")
10144 (match_dup 0))]
10145 "peep2_reg_dead_p (2, operands[0])"
10146 [(set (match_dup 2) (match_dup 1))])
10147
1fd4e8c1 10148\f
c4501e62
JJ		 10149;; TLS support.
10150
02135bc1
SB		 10151;; Mode attributes for different ABIs.
10152(define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10153(define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10154(define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10155(define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10156
10157(define_insn "tls_gd_aix<TLSmode:tls_abi_suffix>"
10158 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10159 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10160 (match_operand 4 "" "g")))
10161 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10162 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10163 UNSPEC_TLSGD)
10164 (clobber (reg:SI LR_REGNO))]
10165 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10166 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
10167 [(set_attr "type" "two")
10168 (set_attr "length" "12")])
10169
10170(define_insn "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10171 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10172 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10173 (match_operand 4 "" "g")))
10174 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10175 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10176 UNSPEC_TLSGD)
10177 (clobber (reg:SI LR_REGNO))]
10178 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10179{
10180 if (flag_pic)
10181 {
10182 if (TARGET_SECURE_PLT && flag_pic == 2)
10183 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10184 else
10185 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10186 }
10187 else
10188 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10189}
10190 [(set_attr "type" "two")
10191 (set_attr "length" "8")])
c4501e62 10192
02135bc1
SB		 10193(define_insn "tls_ld_aix<TLSmode:tls_abi_suffix>"
10194 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10195 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10196 (match_operand 3 "" "g")))
10197 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10198 UNSPEC_TLSLD)
10199 (clobber (reg:SI LR_REGNO))]
10200 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10201 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
10202 [(set_attr "length" "12")])
c4501e62 10203
02135bc1
SB		 10204(define_insn "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10205 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10206 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10207 (match_operand 3 "" "g")))
10208 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10209 UNSPEC_TLSLD)
10210 (clobber (reg:SI LR_REGNO))]
10211 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10212{
10213 if (flag_pic)
10214 {
10215 if (TARGET_SECURE_PLT && flag_pic == 2)
10216 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10217 else
10218 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10219 }
10220 else
10221 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10222}
10223 [(set_attr "length" "8")])
c4501e62 10224
02135bc1
SB		 10225(define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10226 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10227 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10228 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10229 UNSPEC_TLSDTPREL))]
10230 "HAVE_AS_TLS"
10231 "addi %0,%1,%2@dtprel")
c4501e62 10232
02135bc1
SB		 10233(define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10234 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10235 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10236 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10237 UNSPEC_TLSDTPRELHA))]
10238 "HAVE_AS_TLS"
10239 "addis %0,%1,%2@dtprel@ha")
c4501e62 10240
02135bc1
SB		 10241(define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10242 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10243 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10244 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10245 UNSPEC_TLSDTPRELLO))]
10246 "HAVE_AS_TLS"
c4501e62
JJ		 10247 "addi %0,%1,%2@dtprel@l")
10248
02135bc1
SB		 10249(define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10250 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10251 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10252 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10253 UNSPEC_TLSGOTDTPREL))]
10254 "HAVE_AS_TLS"
10255 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
10256
10257(define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10258 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10259 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10260 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10261 UNSPEC_TLSTPREL))]
10262 "HAVE_AS_TLS"
c4501e62
JJ		 10263 "addi %0,%1,%2@tprel")
10264
02135bc1
SB		 10265(define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10266 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10267 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10268 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10269 UNSPEC_TLSTPRELHA))]
10270 "HAVE_AS_TLS"
c4501e62
JJ		 10271 "addis %0,%1,%2@tprel@ha")
10272
02135bc1
SB		 10273(define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10274 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10275 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10276 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10277 UNSPEC_TLSTPRELLO))]
10278 "HAVE_AS_TLS"
c4501e62
JJ		 10279 "addi %0,%1,%2@tprel@l")
10280
c1207243 10281;; "b" output constraint here and on tls_tls input to support linker tls
c4501e62
JJ		 10282;; optimization. The linker may edit the instructions emitted by a
10283;; tls_got_tprel/tls_tls pair to addis,addi.
02135bc1
SB		 10284(define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10285 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10286 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10287 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10288 UNSPEC_TLSGOTTPREL))]
10289 "HAVE_AS_TLS"
10290 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
10291
10292(define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10293 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10294 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10295 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10296 UNSPEC_TLSTLS))]
10297 "HAVE_AS_TLS"
c4501e62
JJ		 10298 "add %0,%1,%2@tls")
10299
c4501e62 10300\f
1fd4e8c1
RK		 10301;; Next come insns related to the calling sequence.
10302;;
10303;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
7e69e155 10304;; We move the back-chain and decrement the stack pointer.
1fd4e8c1
RK		 10305
10306(define_expand "allocate_stack"
e42ac3de 10307 [(set (match_operand 0 "gpc_reg_operand" "")
a260abc9
DE		 10308 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10309 (set (reg 1)
10310 (minus (reg 1) (match_dup 1)))]
1fd4e8c1
RK		 10311 ""
10312 "
4697a36c 10313{ rtx chain = gen_reg_rtx (Pmode);
39403d82 10314 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
4697a36c 10315 rtx neg_op0;
1fd4e8c1
RK		 10316
10317 emit_move_insn (chain, stack_bot);
4697a36c 10318
a157febd 10319 /* Check stack bounds if necessary. */
e3b5732b 10320 if (crtl->limit_stack)
a157febd
GK		 10321 {
10322 rtx available;
6ae08853 10323 available = expand_binop (Pmode, sub_optab,
a157febd
GK		 10324 stack_pointer_rtx, stack_limit_rtx,
10325 NULL_RTX, 1, OPTAB_WIDEN);
10326 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10327 }
10328
e9a25f70
JL		 10329 if (GET_CODE (operands[1]) != CONST_INT
10330 || INTVAL (operands[1]) < -32767
10331 || INTVAL (operands[1]) > 32768)
4697a36c
MM		 10332 {
10333 neg_op0 = gen_reg_rtx (Pmode);
e6ca2c17 10334 if (TARGET_32BIT)
e9a25f70 10335 emit_insn (gen_negsi2 (neg_op0, operands[1]));
e6ca2c17 10336 else
e9a25f70 10337 emit_insn (gen_negdi2 (neg_op0, operands[1]));
4697a36c
MM		 10338 }
10339 else
e9a25f70 10340 neg_op0 = GEN_INT (- INTVAL (operands[1]));
4697a36c 10341
38c1f2d7 10342 if (TARGET_UPDATE)
16044a80
PH		 10343 {
10344 rtx insn, par, set, mem;
10345
10346 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update
10347 : gen_movdi_di_update))
10348 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10349 chain));
10350 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10351 it now and set the alias set/attributes. The above gen_*_update
10352 calls will generate a PARALLEL with the MEM set being the first
10353 operation. */
10354 par = PATTERN (insn);
10355 gcc_assert (GET_CODE (par) == PARALLEL);
10356 set = XVECEXP (par, 0, 0);
10357 gcc_assert (GET_CODE (set) == SET);
10358 mem = SET_DEST (set);
10359 gcc_assert (MEM_P (mem));
10360 MEM_NOTRAP_P (mem) = 1;
10361 set_mem_alias_set (mem, get_frame_alias_set ());
10362 }
4697a36c 10363
38c1f2d7
MM		 10364 else
10365 {
10366 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10367 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
16044a80 10368 emit_move_insn (gen_frame_mem (Pmode, stack_pointer_rtx), chain);
38c1f2d7 10369 }
e9a25f70
JL		 10370
10371 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
1fd4e8c1
RK		 10372 DONE;
10373}")
59257ff7
RK		 10374
10375;; These patterns say how to save and restore the stack pointer. We need not
10376;; save the stack pointer at function level since we are careful to
10377;; preserve the backchain. At block level, we have to restore the backchain
10378;; when we restore the stack pointer.
10379;;
10380;; For nonlocal gotos, we must save both the stack pointer and its
10381;; backchain and restore both. Note that in the nonlocal case, the
10382;; save area is a memory location.
10383
10384(define_expand "save_stack_function"
ff381587
MM		 10385 [(match_operand 0 "any_operand" "")
10386 (match_operand 1 "any_operand" "")]
59257ff7 10387 ""
ff381587 10388 "DONE;")
59257ff7
RK		 10389
10390(define_expand "restore_stack_function"
ff381587
MM		 10391 [(match_operand 0 "any_operand" "")
10392 (match_operand 1 "any_operand" "")]
59257ff7 10393 ""
ff381587 10394 "DONE;")
59257ff7 10395
2eef28ec
AM		 10396;; Adjust stack pointer (op0) to a new value (op1).
10397;; First copy old stack backchain to new location, and ensure that the
10398;; scheduler won't reorder the sp assignment before the backchain write.
59257ff7 10399(define_expand "restore_stack_block"
2eef28ec
AM		 10400 [(set (match_dup 2) (match_dup 3))
10401 (set (match_dup 4) (match_dup 2))
10402 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10403 (set (match_operand 0 "register_operand" "")
10404 (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10405 ""
10406 "
dfdfa60f 10407{
583da60a 10408 operands[1] = force_reg (Pmode, operands[1]);
dfdfa60f 10409 operands[2] = gen_reg_rtx (Pmode);
2eef28ec
AM		 10410 operands[3] = gen_frame_mem (Pmode, operands[0]);
10411 operands[4] = gen_frame_mem (Pmode, operands[1]);
10412 operands[5] = gen_frame_mem (BLKmode, operands[0]);
dfdfa60f 10413}")
59257ff7
RK		 10414
10415(define_expand "save_stack_nonlocal"
2eef28ec
AM		 10416 [(set (match_dup 3) (match_dup 4))
10417 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10418 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
59257ff7
RK		 10419 ""
10420 "
10421{
11b25716 10422 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10423
10424 /* Copy the backchain to the first word, sp to the second. */
2eef28ec
AM		 10425 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10426 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10427 operands[3] = gen_reg_rtx (Pmode);
10428 operands[4] = gen_frame_mem (Pmode, operands[1]);
59257ff7 10429}")
7e69e155 10430
59257ff7 10431(define_expand "restore_stack_nonlocal"
2eef28ec
AM		 10432 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10433 (set (match_dup 3) (match_dup 4))
10434 (set (match_dup 5) (match_dup 2))
10435 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10436 (set (match_operand 0 "register_operand" "") (match_dup 3))]
59257ff7
RK		 10437 ""
10438 "
10439{
11b25716 10440 int units_per_word = (TARGET_32BIT) ? 4 : 8;
59257ff7
RK		 10441
10442 /* Restore the backchain from the first word, sp from the second. */
2eef28ec
AM		 10443 operands[2] = gen_reg_rtx (Pmode);
10444 operands[3] = gen_reg_rtx (Pmode);
10445 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10446 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10447 operands[5] = gen_frame_mem (Pmode, operands[3]);
10448 operands[6] = gen_frame_mem (BLKmode, operands[0]);
59257ff7 10449}")
9ebbca7d
GK		 10450\f
10451;; TOC register handling.
b6c9286a 10452
9ebbca7d 10453;; Code to initialize the TOC register...
f0f6a223 10454
9ebbca7d 10455(define_insn "load_toc_aix_si"
e72247f4 10456 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 10457 (unspec:SI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10458 (use (reg:SI 2))])]
2bfcf297 10459 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
f0f6a223
RK		 10460 "*
10461{
9ebbca7d
GK		 10462 char buf[30];
10463 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
a8a05998 10464 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10465 operands[2] = gen_rtx_REG (Pmode, 2);
10466 return \"{l|lwz} %0,%1(%2)\";
f0f6a223
RK		 10467}"
10468 [(set_attr "type" "load")])
9ebbca7d
GK		 10469
10470(define_insn "load_toc_aix_di"
e72247f4 10471 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
615158e2 10472 (unspec:DI [(const_int 0)] UNSPEC_TOC))
46aaf10d 10473 (use (reg:DI 2))])]
2bfcf297 10474 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9ebbca7d
GK		 10475 "*
10476{
10477 char buf[30];
f585a356
DE		 10478#ifdef TARGET_RELOCATABLE
10479 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10480 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10481#else
9ebbca7d 10482 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
f585a356 10483#endif
2bfcf297
DB		 10484 if (TARGET_ELF)
10485 strcat (buf, \"@toc\");
a8a05998 10486 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9ebbca7d
GK		 10487 operands[2] = gen_rtx_REG (Pmode, 2);
10488 return \"ld %0,%1(%2)\";
10489}"
10490 [(set_attr "type" "load")])
10491
10492(define_insn "load_toc_v4_pic_si"
1de43f85 10493 [(set (reg:SI LR_REGNO)
615158e2 10494 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
f607bc57 10495 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
9ebbca7d
GK		 10496 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10497 [(set_attr "type" "branch")
10498 (set_attr "length" "4")])
10499
9ebbca7d 10500(define_insn "load_toc_v4_PIC_1"
1de43f85 10501 [(set (reg:SI LR_REGNO)
e65a3857
DE		 10502 (match_operand:SI 0 "immediate_operand" "s"))
10503 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
7f970b70
AM		 10504 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10505 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
e65a3857 10506 "bcl 20,31,%0\\n%0:"
9ebbca7d
GK		 10507 [(set_attr "type" "branch")
10508 (set_attr "length" "4")])
10509
10510(define_insn "load_toc_v4_PIC_1b"
1de43f85 10511 [(set (reg:SI LR_REGNO)
e65a3857 10512 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
c4501e62 10513 UNSPEC_TOCPTR))]
20b71b17 10514 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
e65a3857 10515 "bcl 20,31,$+8\\n\\t.long %0-$"
9ebbca7d
GK		 10516 [(set_attr "type" "branch")
10517 (set_attr "length" "8")])
10518
10519(define_insn "load_toc_v4_PIC_2"
f585a356 10520 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
a2900460 10521 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
9ebbca7d
GK		 10522 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10523 (match_operand:SI 3 "immediate_operand" "s")))))]
20b71b17 10524 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
9ebbca7d
GK		 10525 "{l|lwz} %0,%2-%3(%1)"
10526 [(set_attr "type" "load")])
10527
7f970b70
AM		 10528(define_insn "load_toc_v4_PIC_3b"
10529 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10530 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10531 (high:SI
10532 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10533 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10534 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10535 "{cau|addis} %0,%1,%2-%3@ha")
10536
10537(define_insn "load_toc_v4_PIC_3c"
10538 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10539 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10540 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10541 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10542 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10543 "{cal|addi} %0,%1,%2-%3@l")
f51eee6a 10544
9ebbca7d
GK		 10545;; If the TOC is shared over a translation unit, as happens with all
10546;; the kinds of PIC that we support, we need to restore the TOC
10547;; pointer only when jumping over units of translation.
f51eee6a 10548;; On Darwin, we need to reload the picbase.
9ebbca7d
GK		 10549
10550(define_expand "builtin_setjmp_receiver"
10551 [(use (label_ref (match_operand 0 "" "")))]
f607bc57 10552 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
f51eee6a
GK		 10553 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10554 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
9ebbca7d
GK		 10555 "
10556{
84d7dd4a 10557#if TARGET_MACHO
f51eee6a
GK		 10558 if (DEFAULT_ABI == ABI_DARWIN)
10559 {
d24652ee 10560 const char *picbase = machopic_function_base_name ();
485bad26 10561 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
f51eee6a
GK		 10562 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10563 rtx tmplabrtx;
10564 char tmplab[20];
10565
10566 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10567 CODE_LABEL_NUMBER (operands[0]));
485bad26 10568 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
f51eee6a 10569
316fbf19 10570 emit_insn (gen_load_macho_picbase (tmplabrtx));
1de43f85 10571 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
b8a55285 10572 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
f51eee6a
GK		 10573 }
10574 else
84d7dd4a 10575#endif
f51eee6a 10576 rs6000_emit_load_toc_table (FALSE);
9ebbca7d
GK		 10577 DONE;
10578}")
7f970b70
AM		 10579
10580;; Elf specific ways of loading addresses for non-PIC code.
10581;; The output of this could be r0, but we make a very strong
10582;; preference for a base register because it will usually
10583;; be needed there.
10584(define_insn "elf_high"
10585 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10586 (high:SI (match_operand 1 "" "")))]
10587 "TARGET_ELF && ! TARGET_64BIT"
10588 "{liu|lis} %0,%1@ha")
10589
10590(define_insn "elf_low"
10591 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10592 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10593 (match_operand 2 "" "")))]
10594 "TARGET_ELF && ! TARGET_64BIT"
10595 "@
10596 {cal|la} %0,%2@l(%1)
10597 {ai|addic} %0,%1,%K2")
9ebbca7d
GK		 10598\f
10599;; A function pointer under AIX is a pointer to a data area whose first word
10600;; contains the actual address of the function, whose second word contains a
b6c9286a
MM		 10601;; pointer to its TOC, and whose third word contains a value to place in the
10602;; static chain register (r11). Note that if we load the static chain, our
1fd4e8c1 10603;; "trampoline" need not have any executable code.
b6c9286a 10604
cccf3bdc
DE		 10605(define_expand "call_indirect_aix32"
10606 [(set (match_dup 2)
10607 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10608 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10609 (reg:SI 2))
10610 (set (reg:SI 2)
10611 (mem:SI (plus:SI (match_dup 0)
10612 (const_int 4))))
10613 (set (reg:SI 11)
10614 (mem:SI (plus:SI (match_dup 0)
10615 (const_int 8))))
10616 (parallel [(call (mem:SI (match_dup 2))
10617 (match_operand 1 "" ""))
10618 (use (reg:SI 2))
10619 (use (reg:SI 11))
10620 (set (reg:SI 2)
10621 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 10622 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10623 "TARGET_32BIT"
10624 "
10625{ operands[2] = gen_reg_rtx (SImode); }")
b6c9286a 10626
cccf3bdc
DE		 10627(define_expand "call_indirect_aix64"
10628 [(set (match_dup 2)
10629 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10630 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10631 (reg:DI 2))
10632 (set (reg:DI 2)
10633 (mem:DI (plus:DI (match_dup 0)
10634 (const_int 8))))
10635 (set (reg:DI 11)
10636 (mem:DI (plus:DI (match_dup 0)
10637 (const_int 16))))
10638 (parallel [(call (mem:SI (match_dup 2))
10639 (match_operand 1 "" ""))
10640 (use (reg:DI 2))
10641 (use (reg:DI 11))
10642 (set (reg:DI 2)
10643 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 10644 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10645 "TARGET_64BIT"
10646 "
10647{ operands[2] = gen_reg_rtx (DImode); }")
b6c9286a 10648
cccf3bdc
DE		 10649(define_expand "call_value_indirect_aix32"
10650 [(set (match_dup 3)
10651 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10652 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10653 (reg:SI 2))
10654 (set (reg:SI 2)
10655 (mem:SI (plus:SI (match_dup 1)
10656 (const_int 4))))
10657 (set (reg:SI 11)
10658 (mem:SI (plus:SI (match_dup 1)
10659 (const_int 8))))
10660 (parallel [(set (match_operand 0 "" "")
10661 (call (mem:SI (match_dup 3))
10662 (match_operand 2 "" "")))
10663 (use (reg:SI 2))
10664 (use (reg:SI 11))
10665 (set (reg:SI 2)
10666 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 10667 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10668 "TARGET_32BIT"
10669 "
10670{ operands[3] = gen_reg_rtx (SImode); }")
b6c9286a 10671
cccf3bdc
DE		 10672(define_expand "call_value_indirect_aix64"
10673 [(set (match_dup 3)
10674 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10675 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10676 (reg:DI 2))
10677 (set (reg:DI 2)
10678 (mem:DI (plus:DI (match_dup 1)
10679 (const_int 8))))
10680 (set (reg:DI 11)
10681 (mem:DI (plus:DI (match_dup 1)
10682 (const_int 16))))
10683 (parallel [(set (match_operand 0 "" "")
10684 (call (mem:SI (match_dup 3))
10685 (match_operand 2 "" "")))
10686 (use (reg:DI 2))
10687 (use (reg:DI 11))
10688 (set (reg:DI 2)
10689 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 10690 (clobber (reg:SI LR_REGNO))])]
cccf3bdc
DE		 10691 "TARGET_64BIT"
10692 "
10693{ operands[3] = gen_reg_rtx (DImode); }")
1fd4e8c1 10694
b6c9286a 10695;; Now the definitions for the call and call_value insns
1fd4e8c1 10696(define_expand "call"
a260abc9 10697 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
1fd4e8c1 10698 (match_operand 1 "" ""))
4697a36c 10699 (use (match_operand 2 "" ""))
1de43f85 10700 (clobber (reg:SI LR_REGNO))])]
1fd4e8c1
RK		 10701 ""
10702 "
10703{
ee890fe2 10704#if TARGET_MACHO
ab82a49f 10705 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10706 operands[0] = machopic_indirect_call_target (operands[0]);
10707#endif
10708
37409796
NS		 10709 gcc_assert (GET_CODE (operands[0]) == MEM);
10710 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
1fd4e8c1
RK		 10711
10712 operands[0] = XEXP (operands[0], 0);
7509c759 10713
6a4cee5f 10714 if (GET_CODE (operands[0]) != SYMBOL_REF
473f51b6 10715 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
efdba735 10716 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
1fd4e8c1 10717 {
6a4cee5f
MM		 10718 if (INTVAL (operands[2]) & CALL_LONG)
10719 operands[0] = rs6000_longcall_ref (operands[0]);
10720
37409796
NS		 10721 switch (DEFAULT_ABI)
10722 {
10723 case ABI_V4:
10724 case ABI_DARWIN:
10725 operands[0] = force_reg (Pmode, operands[0]);
10726 break;
1fd4e8c1 10727
37409796 10728 case ABI_AIX:
cccf3bdc
DE		 10729 /* AIX function pointers are really pointers to a three word
10730 area. */
10731 emit_call_insn (TARGET_32BIT
10732 ? gen_call_indirect_aix32 (force_reg (SImode,
10733 operands[0]),
10734 operands[1])
10735 : gen_call_indirect_aix64 (force_reg (DImode,
10736 operands[0]),
10737 operands[1]));
10738 DONE;
37409796
NS		 10739
10740 default:
10741 gcc_unreachable ();
b6c9286a 10742 }
1fd4e8c1
RK		 10743 }
10744}")
10745
10746(define_expand "call_value"
10747 [(parallel [(set (match_operand 0 "" "")
a260abc9 10748 (call (mem:SI (match_operand 1 "address_operand" ""))
1fd4e8c1 10749 (match_operand 2 "" "")))
4697a36c 10750 (use (match_operand 3 "" ""))
1de43f85 10751 (clobber (reg:SI LR_REGNO))])]
1fd4e8c1
RK		 10752 ""
10753 "
10754{
ee890fe2 10755#if TARGET_MACHO
ab82a49f 10756 if (MACHOPIC_INDIRECT)
ee890fe2
SS		 10757 operands[1] = machopic_indirect_call_target (operands[1]);
10758#endif
10759
37409796
NS		 10760 gcc_assert (GET_CODE (operands[1]) == MEM);
10761 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
1fd4e8c1
RK		 10762
10763 operands[1] = XEXP (operands[1], 0);
7509c759 10764
6a4cee5f 10765 if (GET_CODE (operands[1]) != SYMBOL_REF
473f51b6 10766 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
efdba735 10767 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
1fd4e8c1 10768 {
6756293c 10769 if (INTVAL (operands[3]) & CALL_LONG)
6a4cee5f
MM		 10770 operands[1] = rs6000_longcall_ref (operands[1]);
10771
37409796
NS		 10772 switch (DEFAULT_ABI)
10773 {
10774 case ABI_V4:
10775 case ABI_DARWIN:
10776 operands[1] = force_reg (Pmode, operands[1]);
10777 break;
1fd4e8c1 10778
37409796 10779 case ABI_AIX:
cccf3bdc
DE		 10780 /* AIX function pointers are really pointers to a three word
10781 area. */
10782 emit_call_insn (TARGET_32BIT
10783 ? gen_call_value_indirect_aix32 (operands[0],
10784 force_reg (SImode,
10785 operands[1]),
10786 operands[2])
10787 : gen_call_value_indirect_aix64 (operands[0],
10788 force_reg (DImode,
10789 operands[1]),
10790 operands[2]));
10791 DONE;
37409796
NS		 10792
10793 default:
10794 gcc_unreachable ();
b6c9286a 10795 }
1fd4e8c1
RK		 10796 }
10797}")
10798
04780ee7 10799;; Call to function in current module. No TOC pointer reload needed.
a0ab749a 10800;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10801;; either the function was not prototyped, or it was prototyped as a
10802;; variable argument function. It is > 0 if FP registers were passed
10803;; and < 0 if they were not.
04780ee7 10804
a260abc9 10805(define_insn "*call_local32"
4697a36c
MM		 10806 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10807 (match_operand 1 "" "g,g"))
10808 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 10809 (clobber (reg:SI LR_REGNO))]
5a19791c 10810 "(INTVAL (operands[2]) & CALL_LONG) == 0"
4697a36c
MM		 10811 "*
10812{
6a4cee5f
MM		 10813 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10814 output_asm_insn (\"crxor 6,6,6\", operands);
10815
10816 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10817 output_asm_insn (\"creqv 6,6,6\", operands);
4697a36c 10818
a226df46 10819 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
4697a36c 10820}"
b7ff3d82
DE		 10821 [(set_attr "type" "branch")
10822 (set_attr "length" "4,8")])
04780ee7 10823
a260abc9
DE		 10824(define_insn "*call_local64"
10825 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10826 (match_operand 1 "" "g,g"))
10827 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 10828 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 10829 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10830 "*
10831{
10832 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10833 output_asm_insn (\"crxor 6,6,6\", operands);
10834
10835 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10836 output_asm_insn (\"creqv 6,6,6\", operands);
10837
10838 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10839}"
10840 [(set_attr "type" "branch")
10841 (set_attr "length" "4,8")])
10842
cccf3bdc 10843(define_insn "*call_value_local32"
d18dba68 10844 [(set (match_operand 0 "" "")
a260abc9
DE		 10845 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10846 (match_operand 2 "" "g,g")))
10847 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 10848 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 10849 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10850 "*
10851{
10852 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10853 output_asm_insn (\"crxor 6,6,6\", operands);
10854
10855 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10856 output_asm_insn (\"creqv 6,6,6\", operands);
10857
10858 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10859}"
10860 [(set_attr "type" "branch")
10861 (set_attr "length" "4,8")])
10862
10863
cccf3bdc 10864(define_insn "*call_value_local64"
d18dba68 10865 [(set (match_operand 0 "" "")
a260abc9
DE		 10866 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10867 (match_operand 2 "" "g,g")))
10868 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 10869 (clobber (reg:SI LR_REGNO))]
a260abc9
DE		 10870 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10871 "*
10872{
10873 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10874 output_asm_insn (\"crxor 6,6,6\", operands);
10875
10876 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10877 output_asm_insn (\"creqv 6,6,6\", operands);
10878
10879 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10880}"
10881 [(set_attr "type" "branch")
10882 (set_attr "length" "4,8")])
10883
04780ee7 10884;; Call to function which may be in another module. Restore the TOC
911f679c 10885;; pointer (r2) after the call unless this is System V.
a0ab749a 10886;; Operand2 is nonzero if we are using the V.4 calling sequence and
4697a36c
MM		 10887;; either the function was not prototyped, or it was prototyped as a
10888;; variable argument function. It is > 0 if FP registers were passed
10889;; and < 0 if they were not.
04780ee7 10890
cccf3bdc 10891(define_insn "*call_indirect_nonlocal_aix32"
70ae0191
DE		 10892 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10893 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 10894 (use (reg:SI 2))
10895 (use (reg:SI 11))
10896 (set (reg:SI 2)
10897 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 10898 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 10899 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10900 "b%T0l\;{l|lwz} 2,20(1)"
10901 [(set_attr "type" "jmpreg")
10902 (set_attr "length" "8")])
10903
a260abc9 10904(define_insn "*call_nonlocal_aix32"
cc4d5fec 10905 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10906 (match_operand 1 "" "g"))
10907 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 10908 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 10909 "TARGET_32BIT
10910 && DEFAULT_ABI == ABI_AIX
5a19791c 10911 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 10912 "bl %z0\;%."
b7ff3d82 10913 [(set_attr "type" "branch")
cccf3bdc
DE		 10914 (set_attr "length" "8")])
10915
10916(define_insn "*call_indirect_nonlocal_aix64"
70ae0191
DE		 10917 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10918 (match_operand 1 "" "g,g"))
cccf3bdc
DE		 10919 (use (reg:DI 2))
10920 (use (reg:DI 11))
10921 (set (reg:DI 2)
10922 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 10923 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 10924 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10925 "b%T0l\;ld 2,40(1)"
10926 [(set_attr "type" "jmpreg")
10927 (set_attr "length" "8")])
59313e4e 10928
a260abc9 10929(define_insn "*call_nonlocal_aix64"
cc4d5fec 10930 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10931 (match_operand 1 "" "g"))
10932 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 10933 (clobber (reg:SI LR_REGNO))]
6ae08853 10934 "TARGET_64BIT
9ebbca7d 10935 && DEFAULT_ABI == ABI_AIX
a260abc9 10936 && (INTVAL (operands[2]) & CALL_LONG) == 0"
cccf3bdc 10937 "bl %z0\;%."
a260abc9 10938 [(set_attr "type" "branch")
cccf3bdc 10939 (set_attr "length" "8")])
7509c759 10940
cccf3bdc 10941(define_insn "*call_value_indirect_nonlocal_aix32"
d18dba68 10942 [(set (match_operand 0 "" "")
70ae0191
DE		 10943 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10944 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 10945 (use (reg:SI 2))
10946 (use (reg:SI 11))
10947 (set (reg:SI 2)
10948 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
1de43f85 10949 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 10950 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10951 "b%T1l\;{l|lwz} 2,20(1)"
10952 [(set_attr "type" "jmpreg")
10953 (set_attr "length" "8")])
1fd4e8c1 10954
cccf3bdc 10955(define_insn "*call_value_nonlocal_aix32"
d18dba68 10956 [(set (match_operand 0 "" "")
cc4d5fec 10957 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10958 (match_operand 2 "" "g")))
10959 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 10960 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 10961 "TARGET_32BIT
10962 && DEFAULT_ABI == ABI_AIX
a260abc9 10963 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc 10964 "bl %z1\;%."
b7ff3d82 10965 [(set_attr "type" "branch")
cccf3bdc 10966 (set_attr "length" "8")])
04780ee7 10967
cccf3bdc 10968(define_insn "*call_value_indirect_nonlocal_aix64"
d18dba68 10969 [(set (match_operand 0 "" "")
70ae0191
DE		 10970 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10971 (match_operand 2 "" "g,g")))
cccf3bdc
DE		 10972 (use (reg:DI 2))
10973 (use (reg:DI 11))
10974 (set (reg:DI 2)
10975 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
1de43f85 10976 (clobber (reg:SI LR_REGNO))]
cccf3bdc
DE		 10977 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10978 "b%T1l\;ld 2,40(1)"
10979 [(set_attr "type" "jmpreg")
10980 (set_attr "length" "8")])
10981
10982(define_insn "*call_value_nonlocal_aix64"
d18dba68 10983 [(set (match_operand 0 "" "")
cc4d5fec 10984 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
cccf3bdc
DE		 10985 (match_operand 2 "" "g")))
10986 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 10987 (clobber (reg:SI LR_REGNO))]
6ae08853 10988 "TARGET_64BIT
9ebbca7d 10989 && DEFAULT_ABI == ABI_AIX
5a19791c 10990 && (INTVAL (operands[3]) & CALL_LONG) == 0"
cccf3bdc
DE		 10991 "bl %z1\;%."
10992 [(set_attr "type" "branch")
10993 (set_attr "length" "8")])
10994
10995;; A function pointer under System V is just a normal pointer
10996;; operands[0] is the function pointer
10997;; operands[1] is the stack size to clean up
10998;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10999;; which indicates how to set cr1
11000
9613eaff
SH		 11001(define_insn "*call_indirect_nonlocal_sysv<mode>"
11002 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11003 (match_operand 1 "" "g,g,g,g"))
11004 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
1de43f85 11005 (clobber (reg:SI LR_REGNO))]
50d440bc 11006 "DEFAULT_ABI == ABI_V4
f607bc57 11007 || DEFAULT_ABI == ABI_DARWIN"
911f679c 11008{
cccf3bdc 11009 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11010 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f 11011
cccf3bdc 11012 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11013 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11014
a5c76ee6
ZW		 11015 return "b%T0l";
11016}
6d0a8091
DJ		 11017 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11018 (set_attr "length" "4,4,8,8")])
cccf3bdc 11019
1d3155fc 11020(define_insn_and_split "*call_nonlocal_sysv<mode>"
9613eaff 11021 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11022 (match_operand 1 "" "g,g"))
11023 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11024 (clobber (reg:SI LR_REGNO))]
efdba735
SH		 11025 "(DEFAULT_ABI == ABI_DARWIN
11026 || (DEFAULT_ABI == ABI_V4
11027 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11028{
11029 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11030 output_asm_insn ("crxor 6,6,6", operands);
11031
11032 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11033 output_asm_insn ("creqv 6,6,6", operands);
11034
c989f2f7 11035#if TARGET_MACHO
efdba735
SH		 11036 return output_call(insn, operands, 0, 2);
11037#else
7f970b70
AM		 11038 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11039 {
1d3155fc
AM		 11040 gcc_assert (!TARGET_SECURE_PLT);
11041 return "bl %z0@plt";
7f970b70
AM		 11042 }
11043 else
11044 return "bl %z0";
6ae08853 11045#endif
1d3155fc
AM		 11046}
11047 "DEFAULT_ABI == ABI_V4
11048 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11049 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11050 [(parallel [(call (mem:SI (match_dup 0))
11051 (match_dup 1))
11052 (use (match_dup 2))
11053 (use (match_dup 3))
11054 (clobber (reg:SI LR_REGNO))])]
11055{
11056 operands[3] = pic_offset_table_rtx;
11057}
11058 [(set_attr "type" "branch,branch")
11059 (set_attr "length" "4,8")])
11060
11061(define_insn "*call_nonlocal_sysv_secure<mode>"
11062 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11063 (match_operand 1 "" "g,g"))
11064 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11065 (use (match_operand:SI 3 "register_operand" "r,r"))
11066 (clobber (reg:SI LR_REGNO))]
11067 "(DEFAULT_ABI == ABI_V4
11068 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11069 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11070{
11071 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11072 output_asm_insn ("crxor 6,6,6", operands);
11073
11074 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11075 output_asm_insn ("creqv 6,6,6", operands);
11076
11077 if (flag_pic == 2)
11078 /* The magic 32768 offset here and in the other sysv call insns
11079 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11080 See sysv4.h:toc_section. */
11081 return "bl %z0+32768@plt";
11082 else
11083 return "bl %z0@plt";
a5c76ee6
ZW		 11084}
11085 [(set_attr "type" "branch,branch")
11086 (set_attr "length" "4,8")])
11087
9613eaff 11088(define_insn "*call_value_indirect_nonlocal_sysv<mode>"
d18dba68 11089 [(set (match_operand 0 "" "")
9613eaff 11090 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
6d0a8091
DJ		 11091 (match_operand 2 "" "g,g,g,g")))
11092 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
1de43f85 11093 (clobber (reg:SI LR_REGNO))]
50d440bc 11094 "DEFAULT_ABI == ABI_V4
f607bc57 11095 || DEFAULT_ABI == ABI_DARWIN"
b6c9286a 11096{
6a4cee5f 11097 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
a5c76ee6 11098 output_asm_insn ("crxor 6,6,6", operands);
6a4cee5f
MM		 11099
11100 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
a5c76ee6 11101 output_asm_insn ("creqv 6,6,6", operands);
7509c759 11102
a5c76ee6
ZW		 11103 return "b%T1l";
11104}
6d0a8091
DJ		 11105 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11106 (set_attr "length" "4,4,8,8")])
a5c76ee6 11107
1d3155fc 11108(define_insn_and_split "*call_value_nonlocal_sysv<mode>"
a5c76ee6 11109 [(set (match_operand 0 "" "")
9613eaff 11110 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
a5c76ee6
ZW		 11111 (match_operand 2 "" "g,g")))
11112 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11113 (clobber (reg:SI LR_REGNO))]
efdba735
SH		 11114 "(DEFAULT_ABI == ABI_DARWIN
11115 || (DEFAULT_ABI == ABI_V4
11116 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
a5c76ee6
ZW		 11117{
11118 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11119 output_asm_insn ("crxor 6,6,6", operands);
11120
11121 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11122 output_asm_insn ("creqv 6,6,6", operands);
11123
c989f2f7 11124#if TARGET_MACHO
efdba735
SH		 11125 return output_call(insn, operands, 1, 3);
11126#else
7f970b70
AM		 11127 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11128 {
1d3155fc
AM		 11129 gcc_assert (!TARGET_SECURE_PLT);
11130 return "bl %z1@plt";
7f970b70
AM		 11131 }
11132 else
11133 return "bl %z1";
6ae08853 11134#endif
1d3155fc
AM		 11135}
11136 "DEFAULT_ABI == ABI_V4
11137 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11138 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11139 [(parallel [(set (match_dup 0)
11140 (call (mem:SI (match_dup 1))
11141 (match_dup 2)))
11142 (use (match_dup 3))
11143 (use (match_dup 4))
11144 (clobber (reg:SI LR_REGNO))])]
11145{
11146 operands[4] = pic_offset_table_rtx;
11147}
11148 [(set_attr "type" "branch,branch")
11149 (set_attr "length" "4,8")])
11150
11151(define_insn "*call_value_nonlocal_sysv_secure<mode>"
11152 [(set (match_operand 0 "" "")
11153 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11154 (match_operand 2 "" "g,g")))
11155 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11156 (use (match_operand:SI 4 "register_operand" "r,r"))
11157 (clobber (reg:SI LR_REGNO))]
11158 "(DEFAULT_ABI == ABI_V4
11159 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11160 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11161{
11162 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11163 output_asm_insn ("crxor 6,6,6", operands);
11164
11165 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11166 output_asm_insn ("creqv 6,6,6", operands);
11167
11168 if (flag_pic == 2)
11169 return "bl %z1+32768@plt";
11170 else
11171 return "bl %z1@plt";
a5c76ee6
ZW		 11172}
11173 [(set_attr "type" "branch,branch")
11174 (set_attr "length" "4,8")])
e6f948e3
RK		 11175
11176;; Call subroutine returning any type.
e6f948e3
RK		 11177(define_expand "untyped_call"
11178 [(parallel [(call (match_operand 0 "" "")
11179 (const_int 0))
11180 (match_operand 1 "" "")
11181 (match_operand 2 "" "")])]
11182 ""
11183 "
11184{
11185 int i;
11186
7d70b8b2 11187 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
e6f948e3
RK		 11188
11189 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11190 {
11191 rtx set = XVECEXP (operands[2], 0, i);
11192 emit_move_insn (SET_DEST (set), SET_SRC (set));
11193 }
11194
11195 /* The optimizer does not know that the call sets the function value
11196 registers we stored in the result block. We avoid problems by
11197 claiming that all hard registers are used and clobbered at this
11198 point. */
11199 emit_insn (gen_blockage ());
11200
11201 DONE;
11202}")
11203
5e1bf043
DJ		 11204;; sibling call patterns
11205(define_expand "sibcall"
11206 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11207 (match_operand 1 "" ""))
11208 (use (match_operand 2 "" ""))
1de43f85 11209 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11210 (return)])]
11211 ""
11212 "
11213{
11214#if TARGET_MACHO
ab82a49f 11215 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11216 operands[0] = machopic_indirect_call_target (operands[0]);
11217#endif
11218
37409796
NS		 11219 gcc_assert (GET_CODE (operands[0]) == MEM);
11220 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
5e1bf043
DJ		 11221
11222 operands[0] = XEXP (operands[0], 0);
5e1bf043
DJ		 11223}")
11224
11225;; this and similar patterns must be marked as using LR, otherwise
11226;; dataflow will try to delete the store into it. This is true
11227;; even when the actual reg to jump to is in CTR, when LR was
11228;; saved and restored around the PIC-setting BCL.
11229(define_insn "*sibcall_local32"
11230 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11231 (match_operand 1 "" "g,g"))
11232 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11233 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11234 (return)]
11235 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11236 "*
11237{
11238 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11239 output_asm_insn (\"crxor 6,6,6\", operands);
11240
11241 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11242 output_asm_insn (\"creqv 6,6,6\", operands);
11243
11244 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11245}"
11246 [(set_attr "type" "branch")
11247 (set_attr "length" "4,8")])
11248
11249(define_insn "*sibcall_local64"
11250 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11251 (match_operand 1 "" "g,g"))
11252 (use (match_operand:SI 2 "immediate_operand" "O,n"))
1de43f85 11253 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11254 (return)]
11255 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11256 "*
11257{
11258 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11259 output_asm_insn (\"crxor 6,6,6\", operands);
11260
11261 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11262 output_asm_insn (\"creqv 6,6,6\", operands);
11263
11264 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11265}"
11266 [(set_attr "type" "branch")
11267 (set_attr "length" "4,8")])
11268
11269(define_insn "*sibcall_value_local32"
11270 [(set (match_operand 0 "" "")
11271 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11272 (match_operand 2 "" "g,g")))
11273 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11274 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11275 (return)]
11276 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11277 "*
11278{
11279 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11280 output_asm_insn (\"crxor 6,6,6\", operands);
11281
11282 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11283 output_asm_insn (\"creqv 6,6,6\", operands);
11284
11285 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11286}"
11287 [(set_attr "type" "branch")
11288 (set_attr "length" "4,8")])
11289
11290
11291(define_insn "*sibcall_value_local64"
11292 [(set (match_operand 0 "" "")
11293 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11294 (match_operand 2 "" "g,g")))
11295 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11296 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11297 (return)]
11298 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11299 "*
11300{
11301 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11302 output_asm_insn (\"crxor 6,6,6\", operands);
11303
11304 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11305 output_asm_insn (\"creqv 6,6,6\", operands);
11306
11307 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11308}"
11309 [(set_attr "type" "branch")
11310 (set_attr "length" "4,8")])
11311
11312(define_insn "*sibcall_nonlocal_aix32"
11313 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11314 (match_operand 1 "" "g"))
11315 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11316 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11317 (return)]
11318 "TARGET_32BIT
11319 && DEFAULT_ABI == ABI_AIX
11320 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11321 "b %z0"
11322 [(set_attr "type" "branch")
11323 (set_attr "length" "4")])
11324
11325(define_insn "*sibcall_nonlocal_aix64"
11326 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11327 (match_operand 1 "" "g"))
11328 (use (match_operand:SI 2 "immediate_operand" "O"))
1de43f85 11329 (use (reg:SI LR_REGNO))
5e1bf043 11330 (return)]
6ae08853 11331 "TARGET_64BIT
5e1bf043
DJ		 11332 && DEFAULT_ABI == ABI_AIX
11333 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11334 "b %z0"
11335 [(set_attr "type" "branch")
11336 (set_attr "length" "4")])
11337
11338(define_insn "*sibcall_value_nonlocal_aix32"
11339 [(set (match_operand 0 "" "")
11340 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11341 (match_operand 2 "" "g")))
11342 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11343 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11344 (return)]
11345 "TARGET_32BIT
11346 && DEFAULT_ABI == ABI_AIX
11347 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11348 "b %z1"
11349 [(set_attr "type" "branch")
11350 (set_attr "length" "4")])
11351
11352(define_insn "*sibcall_value_nonlocal_aix64"
11353 [(set (match_operand 0 "" "")
11354 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11355 (match_operand 2 "" "g")))
11356 (use (match_operand:SI 3 "immediate_operand" "O"))
1de43f85 11357 (use (reg:SI LR_REGNO))
5e1bf043 11358 (return)]
6ae08853 11359 "TARGET_64BIT
5e1bf043
DJ		 11360 && DEFAULT_ABI == ABI_AIX
11361 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11362 "b %z1"
11363 [(set_attr "type" "branch")
11364 (set_attr "length" "4")])
11365
9613eaff
SH		 11366(define_insn "*sibcall_nonlocal_sysv<mode>"
11367 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11368 (match_operand 1 "" ""))
11369 (use (match_operand 2 "immediate_operand" "O,n"))
1de43f85 11370 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11371 (return)]
11372 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11373 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11374 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11375 "*
11376{
11377 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11378 output_asm_insn (\"crxor 6,6,6\", operands);
11379
11380 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11381 output_asm_insn (\"creqv 6,6,6\", operands);
11382
7f970b70
AM		 11383 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11384 {
1d3155fc
AM		 11385 gcc_assert (!TARGET_SECURE_PLT);
11386 return \"b %z0@plt\";
7f970b70
AM		 11387 }
11388 else
11389 return \"b %z0\";
5e1bf043
DJ		 11390}"
11391 [(set_attr "type" "branch,branch")
11392 (set_attr "length" "4,8")])
11393
11394(define_expand "sibcall_value"
11395 [(parallel [(set (match_operand 0 "register_operand" "")
11396 (call (mem:SI (match_operand 1 "address_operand" ""))
11397 (match_operand 2 "" "")))
11398 (use (match_operand 3 "" ""))
1de43f85 11399 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11400 (return)])]
11401 ""
11402 "
11403{
11404#if TARGET_MACHO
ab82a49f 11405 if (MACHOPIC_INDIRECT)
5e1bf043
DJ		 11406 operands[1] = machopic_indirect_call_target (operands[1]);
11407#endif
11408
37409796
NS		 11409 gcc_assert (GET_CODE (operands[1]) == MEM);
11410 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
5e1bf043
DJ		 11411
11412 operands[1] = XEXP (operands[1], 0);
5e1bf043
DJ		 11413}")
11414
9613eaff 11415(define_insn "*sibcall_value_nonlocal_sysv<mode>"
5e1bf043 11416 [(set (match_operand 0 "" "")
9613eaff 11417 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
5e1bf043
DJ		 11418 (match_operand 2 "" "")))
11419 (use (match_operand:SI 3 "immediate_operand" "O,n"))
1de43f85 11420 (use (reg:SI LR_REGNO))
5e1bf043
DJ		 11421 (return)]
11422 "(DEFAULT_ABI == ABI_DARWIN
50d440bc 11423 || DEFAULT_ABI == ABI_V4)
5e1bf043
DJ		 11424 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11425 "*
11426{
11427 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11428 output_asm_insn (\"crxor 6,6,6\", operands);
11429
11430 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11431 output_asm_insn (\"creqv 6,6,6\", operands);
11432
7f970b70
AM		 11433 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11434 {
1d3155fc
AM		 11435 gcc_assert (!TARGET_SECURE_PLT);
11436 return \"b %z1@plt\";
7f970b70
AM		 11437 }
11438 else
11439 return \"b %z1\";
5e1bf043
DJ		 11440}"
11441 [(set_attr "type" "branch,branch")
11442 (set_attr "length" "4,8")])
11443
11444(define_expand "sibcall_epilogue"
11445 [(use (const_int 0))]
11446 "TARGET_SCHED_PROLOG"
11447 "
11448{
11449 rs6000_emit_epilogue (TRUE);
11450 DONE;
11451}")
11452
e6f948e3
RK		 11453;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11454;; all of memory. This blocks insns from being moved across this point.
11455
11456(define_insn "blockage"
615158e2 11457 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
e6f948e3
RK		 11458 ""
11459 "")
1fd4e8c1
RK		 11460\f
11461;; Compare insns are next. Note that the RS/6000 has two types of compares,
7e69e155 11462;; signed & unsigned, and one type of branch.
1fd4e8c1
RK		 11463;;
11464;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11465;; insns, and branches. We store the operands of compares until we see
11466;; how it is used.
4ae234b0 11467(define_expand "cmp<mode>"
1fd4e8c1 11468 [(set (cc0)
4ae234b0
GK		 11469 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11470 (match_operand:GPR 1 "reg_or_short_operand" "")))]
1fd4e8c1
RK		 11471 ""
11472 "
11473{
11474 /* Take care of the possibility that operands[1] might be negative but
11475 this might be a logical operation. That insn doesn't exist. */
11476 if (GET_CODE (operands[1]) == CONST_INT
11477 && INTVAL (operands[1]) < 0)
4ae234b0 11478 operands[1] = force_reg (<MODE>mode, operands[1]);
1fd4e8c1
RK		 11479
11480 rs6000_compare_op0 = operands[0];
11481 rs6000_compare_op1 = operands[1];
11482 rs6000_compare_fp_p = 0;
11483 DONE;
11484}")
11485
4ae234b0
GK		 11486(define_expand "cmp<mode>"
11487 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11488 (match_operand:FP 1 "gpc_reg_operand" "")))]
11489 ""
d6f99ca4
DE		 11490 "
11491{
11492 rs6000_compare_op0 = operands[0];
11493 rs6000_compare_op1 = operands[1];
11494 rs6000_compare_fp_p = 1;
11495 DONE;
11496}")
11497
1fd4e8c1 11498(define_expand "beq"
39a10a29 11499 [(use (match_operand 0 "" ""))]
1fd4e8c1 11500 ""
39a10a29 11501 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 11502
11503(define_expand "bne"
39a10a29 11504 [(use (match_operand 0 "" ""))]
1fd4e8c1 11505 ""
39a10a29 11506 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
1fd4e8c1 11507
39a10a29
GK		 11508(define_expand "bge"
11509 [(use (match_operand 0 "" ""))]
1fd4e8c1 11510 ""
39a10a29 11511 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
1fd4e8c1
RK		 11512
11513(define_expand "bgt"
39a10a29 11514 [(use (match_operand 0 "" ""))]
1fd4e8c1 11515 ""
39a10a29 11516 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
1fd4e8c1
RK		 11517
11518(define_expand "ble"
39a10a29 11519 [(use (match_operand 0 "" ""))]
1fd4e8c1 11520 ""
39a10a29 11521 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
1fd4e8c1 11522
39a10a29
GK		 11523(define_expand "blt"
11524 [(use (match_operand 0 "" ""))]
1fd4e8c1 11525 ""
39a10a29 11526 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
1fd4e8c1 11527
39a10a29
GK		 11528(define_expand "bgeu"
11529 [(use (match_operand 0 "" ""))]
1fd4e8c1 11530 ""
39a10a29 11531 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
1fd4e8c1 11532
39a10a29
GK		 11533(define_expand "bgtu"
11534 [(use (match_operand 0 "" ""))]
1fd4e8c1 11535 ""
39a10a29 11536 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
1fd4e8c1 11537
39a10a29
GK		 11538(define_expand "bleu"
11539 [(use (match_operand 0 "" ""))]
1fd4e8c1 11540 ""
39a10a29 11541 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
1fd4e8c1 11542
39a10a29
GK		 11543(define_expand "bltu"
11544 [(use (match_operand 0 "" ""))]
1fd4e8c1 11545 ""
39a10a29 11546 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
1fd4e8c1 11547
1c882ea4 11548(define_expand "bunordered"
39a10a29 11549 [(use (match_operand 0 "" ""))]
8ef65e3d 11550 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11551 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
1c882ea4
GK		 11552
11553(define_expand "bordered"
39a10a29 11554 [(use (match_operand 0 "" ""))]
8ef65e3d 11555 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11556 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
1c882ea4
GK		 11557
11558(define_expand "buneq"
39a10a29 11559 [(use (match_operand 0 "" ""))]
b26941b4 11560 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11561 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
1c882ea4
GK		 11562
11563(define_expand "bunge"
39a10a29 11564 [(use (match_operand 0 "" ""))]
b26941b4 11565 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11566 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
1c882ea4
GK		 11567
11568(define_expand "bungt"
39a10a29 11569 [(use (match_operand 0 "" ""))]
b26941b4 11570 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11571 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
1c882ea4
GK		 11572
11573(define_expand "bunle"
39a10a29 11574 [(use (match_operand 0 "" ""))]
b26941b4 11575 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11576 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
1c882ea4
GK		 11577
11578(define_expand "bunlt"
39a10a29 11579 [(use (match_operand 0 "" ""))]
b26941b4 11580 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
39a10a29 11581 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
1c882ea4
GK		 11582
11583(define_expand "bltgt"
39a10a29 11584 [(use (match_operand 0 "" ""))]
1c882ea4 11585 ""
39a10a29 11586 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
1c882ea4 11587
1fd4e8c1
RK		 11588;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11589;; For SEQ, likewise, except that comparisons with zero should be done
11590;; with an scc insns. However, due to the order that combine see the
11591;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11592;; the cases we don't want to handle.
11593(define_expand "seq"
39a10a29 11594 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11595 ""
39a10a29 11596 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
1fd4e8c1
RK		 11597
11598(define_expand "sne"
39a10a29 11599 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11600 ""
11601 "
6ae08853 11602{
39a10a29 11603 if (! rs6000_compare_fp_p)
1fd4e8c1
RK		 11604 FAIL;
11605
6ae08853 11606 rs6000_emit_sCOND (NE, operands[0]);
39a10a29 11607 DONE;
1fd4e8c1
RK		 11608}")
11609
b7053a3f
GK		 11610;; A >= 0 is best done the portable way for A an integer.
11611(define_expand "sge"
39a10a29 11612 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11613 ""
11614 "
5638268e 11615{
e56d7409 11616 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11617 FAIL;
11618
b7053a3f 11619 rs6000_emit_sCOND (GE, operands[0]);
39a10a29 11620 DONE;
1fd4e8c1
RK		 11621}")
11622
b7053a3f
GK		 11623;; A > 0 is best done using the portable sequence, so fail in that case.
11624(define_expand "sgt"
39a10a29 11625 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11626 ""
11627 "
5638268e 11628{
e56d7409 11629 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11630 FAIL;
11631
6ae08853 11632 rs6000_emit_sCOND (GT, operands[0]);
39a10a29 11633 DONE;
1fd4e8c1
RK		 11634}")
11635
b7053a3f
GK		 11636;; A <= 0 is best done the portable way for A an integer.
11637(define_expand "sle"
39a10a29 11638 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11639 ""
5638268e
DE		 11640 "
11641{
e56d7409 11642 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
5638268e
DE		 11643 FAIL;
11644
6ae08853 11645 rs6000_emit_sCOND (LE, operands[0]);
5638268e
DE		 11646 DONE;
11647}")
1fd4e8c1 11648
b7053a3f
GK		 11649;; A < 0 is best done in the portable way for A an integer.
11650(define_expand "slt"
39a10a29 11651 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1
RK		 11652 ""
11653 "
5638268e 11654{
e56d7409 11655 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
1fd4e8c1
RK		 11656 FAIL;
11657
6ae08853 11658 rs6000_emit_sCOND (LT, operands[0]);
39a10a29 11659 DONE;
1fd4e8c1
RK		 11660}")
11661
b7053a3f
GK		 11662(define_expand "sgeu"
11663 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11664 ""
11665 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11666
1fd4e8c1 11667(define_expand "sgtu"
39a10a29 11668 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11669 ""
39a10a29 11670 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
1fd4e8c1 11671
b7053a3f
GK		 11672(define_expand "sleu"
11673 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11674 ""
11675 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11676
1fd4e8c1 11677(define_expand "sltu"
39a10a29 11678 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
1fd4e8c1 11679 ""
39a10a29 11680 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
1fd4e8c1 11681
b7053a3f 11682(define_expand "sunordered"
39a10a29 11683 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
8ef65e3d 11684 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f 11685 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
1fd4e8c1 11686
b7053a3f 11687(define_expand "sordered"
39a10a29 11688 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
8ef65e3d 11689 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11690 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11691
11692(define_expand "suneq"
11693 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11694 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11695 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11696
11697(define_expand "sunge"
11698 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11699 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11700 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11701
11702(define_expand "sungt"
11703 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11704 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11705 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11706
11707(define_expand "sunle"
11708 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11709 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11710 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11711
11712(define_expand "sunlt"
11713 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
b26941b4 11714 "! (TARGET_HARD_FLOAT && !TARGET_FPRS)"
b7053a3f
GK		 11715 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11716
11717(define_expand "sltgt"
11718 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11719 ""
11720 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11721
3aebbe5f
JJ		 11722(define_expand "stack_protect_set"
11723 [(match_operand 0 "memory_operand" "")
11724 (match_operand 1 "memory_operand" "")]
11725 ""
11726{
77008252
JJ		 11727#ifdef TARGET_THREAD_SSP_OFFSET
11728 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11729 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11730 operands[1] = gen_rtx_MEM (Pmode, addr);
11731#endif
3aebbe5f
JJ		 11732 if (TARGET_64BIT)
11733 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11734 else
11735 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11736 DONE;
11737})
11738
11739(define_insn "stack_protect_setsi"
11740 [(set (match_operand:SI 0 "memory_operand" "=m")
11741 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11742 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11743 "TARGET_32BIT"
11744 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11745 [(set_attr "type" "three")
11746 (set_attr "length" "12")])
11747
11748(define_insn "stack_protect_setdi"
11749 [(set (match_operand:DI 0 "memory_operand" "=m")
11750 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11751 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11752 "TARGET_64BIT"
11753 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11754 [(set_attr "type" "three")
11755 (set_attr "length" "12")])
11756
11757(define_expand "stack_protect_test"
11758 [(match_operand 0 "memory_operand" "")
11759 (match_operand 1 "memory_operand" "")
11760 (match_operand 2 "" "")]
11761 ""
11762{
77008252
JJ		 11763#ifdef TARGET_THREAD_SSP_OFFSET
11764 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11765 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11766 operands[1] = gen_rtx_MEM (Pmode, addr);
11767#endif
3aebbe5f
JJ		 11768 rs6000_compare_op0 = operands[0];
11769 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11770 UNSPEC_SP_TEST);
11771 rs6000_compare_fp_p = 0;
11772 emit_jump_insn (gen_beq (operands[2]));
11773 DONE;
11774})
11775
11776(define_insn "stack_protect_testsi"
11777 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11778 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11779 (match_operand:SI 2 "memory_operand" "m,m")]
11780 UNSPEC_SP_TEST))
41f12ed0
JJ		 11781 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11782 (clobber (match_scratch:SI 3 "=&r,&r"))]
3aebbe5f
JJ		 11783 "TARGET_32BIT"
11784 "@
11785 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11786 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11787 [(set_attr "length" "16,20")])
11788
11789(define_insn "stack_protect_testdi"
11790 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11791 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11792 (match_operand:DI 2 "memory_operand" "m,m")]
11793 UNSPEC_SP_TEST))
41f12ed0
JJ		 11794 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11795 (clobber (match_scratch:DI 3 "=&r,&r"))]
3aebbe5f
JJ		 11796 "TARGET_64BIT"
11797 "@
11798 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11799 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11800 [(set_attr "length" "16,20")])
11801
1fd4e8c1
RK		 11802\f
11803;; Here are the actual compare insns.
4ae234b0 11804(define_insn "*cmp<mode>_internal1"
1fd4e8c1 11805 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
4ae234b0
GK		 11806 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11807 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
1fd4e8c1 11808 ""
4ae234b0 11809 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
b54cf83a 11810 [(set_attr "type" "cmp")])
266eb58a 11811
f357808b 11812;; If we are comparing a register for equality with a large constant,
28d0e143
PB		 11813;; we can do this with an XOR followed by a compare. But this is profitable
11814;; only if the large constant is only used for the comparison (and in this
11815;; case we already have a register to reuse as scratch).
130869aa
PB		 11816;;
11817;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11818;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
f357808b 11819
28d0e143 11820(define_peephole2
130869aa 11821 [(set (match_operand:SI 0 "register_operand")
410c459d 11822 (match_operand:SI 1 "logical_const_operand" ""))
130869aa 11823 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
28d0e143 11824 [(match_dup 0)
410c459d 11825 (match_operand:SI 2 "logical_const_operand" "")]))
28d0e143 11826 (set (match_operand:CC 4 "cc_reg_operand" "")
130869aa 11827 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
28d0e143
PB		 11828 (match_dup 0)))
11829 (set (pc)
11830 (if_then_else (match_operator 6 "equality_operator"
11831 [(match_dup 4) (const_int 0)])
11832 (match_operand 7 "" "")
11833 (match_operand 8 "" "")))]
130869aa
PB		 11834 "peep2_reg_dead_p (3, operands[0])
11835 && peep2_reg_dead_p (4, operands[4])"
11836 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
28d0e143
PB		 11837 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11838 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11839
11840{
11841 /* Get the constant we are comparing against, and see what it looks like
11842 when sign-extended from 16 to 32 bits. Then see what constant we could
11843 XOR with SEXTC to get the sign-extended value. */
11844 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
130869aa 11845 SImode,
28d0e143
PB		 11846 operands[1], operands[2]);
11847 HOST_WIDE_INT c = INTVAL (cnst);
a65c591c 11848 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
5f59ecb7 11849 HOST_WIDE_INT xorv = c ^ sextc;
f357808b 11850
28d0e143
PB		 11851 operands[9] = GEN_INT (xorv);
11852 operands[10] = GEN_INT (sextc);
11853})
f357808b 11854
acad7ed3 11855(define_insn "*cmpsi_internal2"
1fd4e8c1 11856 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
cd2b37d9 11857 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9ebbca7d 11858 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
1fd4e8c1 11859 ""
e2c953b6 11860 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
b54cf83a 11861 [(set_attr "type" "cmp")])
1fd4e8c1 11862
acad7ed3 11863(define_insn "*cmpdi_internal2"
266eb58a
DE		 11864 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11865 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
9ebbca7d 11866 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
266eb58a 11867 ""
e2c953b6 11868 "cmpld%I2 %0,%1,%b2"
b54cf83a 11869 [(set_attr "type" "cmp")])
266eb58a 11870
1fd4e8c1
RK		 11871;; The following two insns don't exist as single insns, but if we provide
11872;; them, we can swap an add and compare, which will enable us to overlap more
11873;; of the required delay between a compare and branch. We generate code for
11874;; them by splitting.
11875
11876(define_insn ""
11877 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
cd2b37d9 11878 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11879 (match_operand:SI 2 "short_cint_operand" "i")))
cd2b37d9 11880 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11881 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11882 ""
baf97f86
RK		 11883 "#"
11884 [(set_attr "length" "8")])
7e69e155 11885
1fd4e8c1
RK		 11886(define_insn ""
11887 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
cd2b37d9 11888 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 11889 (match_operand:SI 2 "u_short_cint_operand" "i")))
cd2b37d9 11890 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 11891 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11892 ""
baf97f86
RK		 11893 "#"
11894 [(set_attr "length" "8")])
7e69e155 11895
1fd4e8c1
RK		 11896(define_split
11897 [(set (match_operand:CC 3 "cc_reg_operand" "")
cd2b37d9 11898 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11899 (match_operand:SI 2 "short_cint_operand" "")))
cd2b37d9 11900 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11901 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11902 ""
11903 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11904 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11905
11906(define_split
11907 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
cd2b37d9 11908 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 11909 (match_operand:SI 2 "u_short_cint_operand" "")))
cd2b37d9 11910 (set (match_operand:SI 0 "gpc_reg_operand" "")
1fd4e8c1
RK		 11911 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11912 ""
11913 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11914 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11915
acad7ed3 11916(define_insn "*cmpsf_internal1"
1fd4e8c1 11917 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11918 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11919 (match_operand:SF 2 "gpc_reg_operand" "f")))]
cf8e1455 11920 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11921 "fcmpu %0,%1,%2"
11922 [(set_attr "type" "fpcompare")])
11923
acad7ed3 11924(define_insn "*cmpdf_internal1"
1fd4e8c1 11925 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
cd2b37d9
RK		 11926 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11927 (match_operand:DF 2 "gpc_reg_operand" "f")))]
cf8e1455 11928 "TARGET_HARD_FLOAT && TARGET_FPRS"
1fd4e8c1
RK		 11929 "fcmpu %0,%1,%2"
11930 [(set_attr "type" "fpcompare")])
d6f99ca4
DE		 11931
11932;; Only need to compare second words if first words equal
11933(define_insn "*cmptf_internal1"
11934 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11935 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11936 (match_operand:TF 2 "gpc_reg_operand" "f")))]
602ea4d3 11937 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
cf8e1455 11938 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
ecb62ae7 11939 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
d6f99ca4
DE		 11940 [(set_attr "type" "fpcompare")
11941 (set_attr "length" "12")])
de17c25f
DE		 11942
11943(define_insn_and_split "*cmptf_internal2"
11944 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11945 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11946 (match_operand:TF 2 "gpc_reg_operand" "f")))
11947 (clobber (match_scratch:DF 3 "=f"))
11948 (clobber (match_scratch:DF 4 "=f"))
11949 (clobber (match_scratch:DF 5 "=f"))
11950 (clobber (match_scratch:DF 6 "=f"))
11951 (clobber (match_scratch:DF 7 "=f"))
11952 (clobber (match_scratch:DF 8 "=f"))
11953 (clobber (match_scratch:DF 9 "=f"))
11954 (clobber (match_scratch:DF 10 "=f"))]
602ea4d3 11955 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
cf8e1455 11956 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
de17c25f
DE		 11957 "#"
11958 "&& reload_completed"
11959 [(set (match_dup 3) (match_dup 13))
11960 (set (match_dup 4) (match_dup 14))
11961 (set (match_dup 9) (abs:DF (match_dup 5)))
11962 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11963 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11964 (label_ref (match_dup 11))
11965 (pc)))
11966 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11967 (set (pc) (label_ref (match_dup 12)))
11968 (match_dup 11)
11969 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11970 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11971 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11972 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11973 (match_dup 12)]
11974{
11975 REAL_VALUE_TYPE rv;
11976 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11977 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11978
11979 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11980 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11981 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11982 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11983 operands[11] = gen_label_rtx ();
11984 operands[12] = gen_label_rtx ();
11985 real_inf (&rv);
11986 operands[13] = force_const_mem (DFmode,
11987 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11988 operands[14] = force_const_mem (DFmode,
11989 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11990 DFmode));
11991 if (TARGET_TOC)
11992 {
11993 operands[13] = gen_const_mem (DFmode,
11994 create_TOC_reference (XEXP (operands[13], 0)));
11995 operands[14] = gen_const_mem (DFmode,
11996 create_TOC_reference (XEXP (operands[14], 0)));
11997 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11998 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11999 }
12000})
1fd4e8c1
RK		 12001\f
12002;; Now we have the scc insns. We can do some combinations because of the
12003;; way the machine works.
12004;;
12005;; Note that this is probably faster if we can put an insn between the
c5defebb
RK		 12006;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12007;; cases the insns below which don't use an intermediate CR field will
12008;; be used instead.
1fd4e8c1 12009(define_insn ""
cd2b37d9 12010 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12011 (match_operator:SI 1 "scc_comparison_operator"
12012 [(match_operand 2 "cc_reg_operand" "y")
12013 (const_int 0)]))]
12014 ""
2c4a9cff
DE		 12015 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12016 [(set (attr "type")
12017 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12018 (const_string "mfcrf")
12019 ]
12020 (const_string "mfcr")))
c1618c0c 12021 (set_attr "length" "8")])
1fd4e8c1 12022
423c1189 12023;; Same as above, but get the GT bit.
64022b5d 12024(define_insn "move_from_CR_gt_bit"
423c1189 12025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
64022b5d 12026 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
423c1189 12027 "TARGET_E500"
64022b5d 12028 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
423c1189 12029 [(set_attr "type" "mfcr")
c1618c0c 12030 (set_attr "length" "8")])
423c1189 12031
a3170dc6
AH		 12032;; Same as above, but get the OV/ORDERED bit.
12033(define_insn "move_from_CR_ov_bit"
12034 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
615158e2 12035 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
a3170dc6 12036 "TARGET_ISEL"
b7053a3f 12037 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
b54cf83a 12038 [(set_attr "type" "mfcr")
c1618c0c 12039 (set_attr "length" "8")])
a3170dc6 12040
1fd4e8c1 12041(define_insn ""
9ebbca7d
GK		 12042 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12043 (match_operator:DI 1 "scc_comparison_operator"
12044 [(match_operand 2 "cc_reg_operand" "y")
12045 (const_int 0)]))]
12046 "TARGET_POWERPC64"
2c4a9cff
DE		 12047 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12048 [(set (attr "type")
12049 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12050 (const_string "mfcrf")
12051 ]
12052 (const_string "mfcr")))
c1618c0c 12053 (set_attr "length" "8")])
9ebbca7d
GK		 12054
12055(define_insn ""
12056 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12057 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12058 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1
RK		 12059 (const_int 0)])
12060 (const_int 0)))
9ebbca7d 12061 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
1fd4e8c1 12062 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12063 "TARGET_32BIT"
9ebbca7d 12064 "@
2c4a9cff 12065 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
9ebbca7d 12066 #"
b19003d8 12067 [(set_attr "type" "delayed_compare")
c1618c0c 12068 (set_attr "length" "8,16")])
9ebbca7d
GK		 12069
12070(define_split
12071 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12072 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12073 [(match_operand 2 "cc_reg_operand" "")
12074 (const_int 0)])
12075 (const_int 0)))
12076 (set (match_operand:SI 3 "gpc_reg_operand" "")
12077 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
4b8a63d6 12078 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12079 [(set (match_dup 3)
12080 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12081 (set (match_dup 0)
12082 (compare:CC (match_dup 3)
12083 (const_int 0)))]
12084 "")
1fd4e8c1
RK		 12085
12086(define_insn ""
cd2b37d9 12087 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1
RK		 12088 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12089 [(match_operand 2 "cc_reg_operand" "y")
12090 (const_int 0)])
12091 (match_operand:SI 3 "const_int_operand" "n")))]
12092 ""
12093 "*
12094{
12095 int is_bit = ccr_bit (operands[1], 1);
12096 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12097 int count;
12098
12099 if (is_bit >= put_bit)
12100 count = is_bit - put_bit;
12101 else
12102 count = 32 - (put_bit - is_bit);
12103
89e9f3a8
MM		 12104 operands[4] = GEN_INT (count);
12105 operands[5] = GEN_INT (put_bit);
1fd4e8c1 12106
2c4a9cff 12107 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
b19003d8 12108}"
2c4a9cff
DE		 12109 [(set (attr "type")
12110 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12111 (const_string "mfcrf")
12112 ]
12113 (const_string "mfcr")))
c1618c0c 12114 (set_attr "length" "8")])
1fd4e8c1
RK		 12115
12116(define_insn ""
9ebbca7d 12117 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12118 (compare:CC
12119 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
9ebbca7d 12120 [(match_operand 2 "cc_reg_operand" "y,y")
1fd4e8c1 12121 (const_int 0)])
9ebbca7d 12122 (match_operand:SI 3 "const_int_operand" "n,n"))
1fd4e8c1 12123 (const_int 0)))
9ebbca7d 12124 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12125 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12126 (match_dup 3)))]
ce71f754 12127 ""
1fd4e8c1
RK		 12128 "*
12129{
12130 int is_bit = ccr_bit (operands[1], 1);
12131 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12132 int count;
12133
9ebbca7d
GK		 12134 /* Force split for non-cc0 compare. */
12135 if (which_alternative == 1)
12136 return \"#\";
12137
1fd4e8c1
RK		 12138 if (is_bit >= put_bit)
12139 count = is_bit - put_bit;
12140 else
12141 count = 32 - (put_bit - is_bit);
12142
89e9f3a8
MM		 12143 operands[5] = GEN_INT (count);
12144 operands[6] = GEN_INT (put_bit);
1fd4e8c1 12145
2c4a9cff 12146 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
1fd4e8c1 12147}"
b19003d8 12148 [(set_attr "type" "delayed_compare")
c1618c0c 12149 (set_attr "length" "8,16")])
9ebbca7d
GK		 12150
12151(define_split
12152 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12153 (compare:CC
12154 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12155 [(match_operand 2 "cc_reg_operand" "")
12156 (const_int 0)])
12157 (match_operand:SI 3 "const_int_operand" ""))
12158 (const_int 0)))
12159 (set (match_operand:SI 4 "gpc_reg_operand" "")
12160 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12161 (match_dup 3)))]
ce71f754 12162 "reload_completed"
9ebbca7d
GK		 12163 [(set (match_dup 4)
12164 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12165 (match_dup 3)))
12166 (set (match_dup 0)
12167 (compare:CC (match_dup 4)
12168 (const_int 0)))]
12169 "")
1fd4e8c1 12170
c5defebb
RK		 12171;; There is a 3 cycle delay between consecutive mfcr instructions
12172;; so it is useful to combine 2 scc instructions to use only one mfcr.
12173
12174(define_peephole
cd2b37d9 12175 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
c5defebb
RK		 12176 (match_operator:SI 1 "scc_comparison_operator"
12177 [(match_operand 2 "cc_reg_operand" "y")
12178 (const_int 0)]))
cd2b37d9 12179 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
c5defebb
RK		 12180 (match_operator:SI 4 "scc_comparison_operator"
12181 [(match_operand 5 "cc_reg_operand" "y")
12182 (const_int 0)]))]
309323c2 12183 "REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12184 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12185 [(set_attr "type" "mfcr")
c1618c0c 12186 (set_attr "length" "12")])
c5defebb 12187
9ebbca7d
GK		 12188(define_peephole
12189 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12190 (match_operator:DI 1 "scc_comparison_operator"
12191 [(match_operand 2 "cc_reg_operand" "y")
12192 (const_int 0)]))
12193 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12194 (match_operator:DI 4 "scc_comparison_operator"
12195 [(match_operand 5 "cc_reg_operand" "y")
12196 (const_int 0)]))]
309323c2 12197 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
b7053a3f 12198 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
b54cf83a 12199 [(set_attr "type" "mfcr")
c1618c0c 12200 (set_attr "length" "12")])
9ebbca7d 12201
1fd4e8c1
RK		 12202;; There are some scc insns that can be done directly, without a compare.
12203;; These are faster because they don't involve the communications between
12204;; the FXU and branch units. In fact, we will be replacing all of the
12205;; integer scc insns here or in the portable methods in emit_store_flag.
12206;;
12207;; Also support (neg (scc ..)) since that construct is used to replace
12208;; branches, (plus (scc ..) ..) since that construct is common and
12209;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12210;; cases where it is no more expensive than (neg (scc ..)).
12211
12212;; Have reload force a constant into a register for the simple insns that
12213;; otherwise won't accept constants. We do this because it is faster than
12214;; the cmp/mfcr sequence we would otherwise generate.
12215
e9441276
DE		 12216(define_mode_attr scc_eq_op2 [(SI "rKLI")
12217 (DI "rKJI")])
a260abc9 12218
e9441276
DE		 12219(define_insn_and_split "*eq<mode>"
12220 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12221 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
d0515b39 12222 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
27f0fe7f 12223 "!TARGET_POWER"
e9441276 12224 "#"
27f0fe7f 12225 "!TARGET_POWER"
d0515b39
DE		 12226 [(set (match_dup 0)
12227 (clz:GPR (match_dup 3)))
70ae0191 12228 (set (match_dup 0)
d0515b39 12229 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
70ae0191 12230 {
e9441276
DE		 12231 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12232 {
d0515b39
DE		 12233 /* Use output operand as intermediate. */
12234 operands[3] = operands[0];
12235
e9441276 12236 if (logical_operand (operands[2], <MODE>mode))
d0515b39 12237 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12238 gen_rtx_XOR (<MODE>mode,
12239 operands[1], operands[2])));
12240 else
d0515b39 12241 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
e9441276
DE		 12242 gen_rtx_PLUS (<MODE>mode, operands[1],
12243 negate_rtx (<MODE>mode,
12244 operands[2]))));
12245 }
12246 else
d0515b39 12247 operands[3] = operands[1];
9ebbca7d 12248
d0515b39 12249 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
e9441276 12250 })
a260abc9 12251
e9441276 12252(define_insn_and_split "*eq<mode>_compare"
d0515b39 12253 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
70ae0191 12254 (compare:CC
1fa5c709
DE		 12255 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12256 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
70ae0191 12257 (const_int 0)))
1fa5c709 12258 (set (match_operand:P 0 "gpc_reg_operand" "=r")
d0515b39 12259 (eq:P (match_dup 1) (match_dup 2)))]
27f0fe7f 12260 "!TARGET_POWER && optimize_size"
e9441276 12261 "#"
27f0fe7f 12262 "!TARGET_POWER && optimize_size"
d0515b39 12263 [(set (match_dup 0)
1fa5c709 12264 (clz:P (match_dup 4)))
d0515b39
DE		 12265 (parallel [(set (match_dup 3)
12266 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
70ae0191
DE		 12267 (const_int 0)))
12268 (set (match_dup 0)
d0515b39 12269 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
70ae0191 12270 {
e9441276
DE		 12271 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12272 {
d0515b39
DE		 12273 /* Use output operand as intermediate. */
12274 operands[4] = operands[0];
12275
e9441276
DE		 12276 if (logical_operand (operands[2], <MODE>mode))
12277 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12278 gen_rtx_XOR (<MODE>mode,
12279 operands[1], operands[2])));
12280 else
12281 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12282 gen_rtx_PLUS (<MODE>mode, operands[1],
12283 negate_rtx (<MODE>mode,
12284 operands[2]))));
12285 }
12286 else
12287 operands[4] = operands[1];
12288
d0515b39 12289 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
70ae0191
DE		 12290 })
12291
05f68097
DE		 12292(define_insn "*eqsi_power"
12293 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12294 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12295 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
12296 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
12297 "TARGET_POWER"
12298 "@
12299 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12300 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
12301 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12302 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
12303 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
12304 [(set_attr "type" "three,two,three,three,three")
12305 (set_attr "length" "12,8,12,12,12")])
12306
b19003d8
RK		 12307;; We have insns of the form shown by the first define_insn below. If
12308;; there is something inside the comparison operation, we must split it.
12309(define_split
12310 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12311 (plus:SI (match_operator 1 "comparison_operator"
12312 [(match_operand:SI 2 "" "")
12313 (match_operand:SI 3
12314 "reg_or_cint_operand" "")])
12315 (match_operand:SI 4 "gpc_reg_operand" "")))
12316 (clobber (match_operand:SI 5 "register_operand" ""))]
12317 "! gpc_reg_operand (operands[2], SImode)"
12318 [(set (match_dup 5) (match_dup 2))
12319 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12320 (match_dup 4)))])
1fd4e8c1 12321
297abd0d 12322(define_insn "*plus_eqsi"
5276df18 12323 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
cd2b37d9 12324 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
56fc483e 12325 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
5276df18 12326 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
59d6560b 12327 "TARGET_32BIT"
1fd4e8c1 12328 "@
5276df18
DE		 12329 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12330 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12331 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12332 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12333 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
943c15ed
DE		 12334 [(set_attr "type" "three,two,three,three,three")
12335 (set_attr "length" "12,8,12,12,12")])
1fd4e8c1 12336
297abd0d 12337(define_insn "*compare_plus_eqsi"
9ebbca7d 12338 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12339 (compare:CC
1fd4e8c1 12340 (plus:SI
9ebbca7d 12341 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12342 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12343 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12344 (const_int 0)))
9ebbca7d 12345 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
297abd0d 12346 "TARGET_32BIT && optimize_size"
1fd4e8c1 12347 "@
ca7f5001 12348 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
19378cf8 12349 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
ca7f5001
RK		 12350 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12351 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12352 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12353 #
12354 #
12355 #
12356 #
12357 #"
b19003d8 12358 [(set_attr "type" "compare")
9ebbca7d
GK		 12359 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12360
12361(define_split
12362 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12363 (compare:CC
12364 (plus:SI
12365 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12366 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12367 (match_operand:SI 3 "gpc_reg_operand" ""))
12368 (const_int 0)))
12369 (clobber (match_scratch:SI 4 ""))]
297abd0d 12370 "TARGET_32BIT && optimize_size && reload_completed"
9ebbca7d
GK		 12371 [(set (match_dup 4)
12372 (plus:SI (eq:SI (match_dup 1)
12373 (match_dup 2))
12374 (match_dup 3)))
12375 (set (match_dup 0)
12376 (compare:CC (match_dup 4)
12377 (const_int 0)))]
12378 "")
1fd4e8c1 12379
297abd0d 12380(define_insn "*plus_eqsi_compare"
0387639b 12381 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
7e69e155 12382 (compare:CC
1fd4e8c1 12383 (plus:SI
9ebbca7d 12384 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
56fc483e 12385 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
9ebbca7d 12386 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
1fd4e8c1 12387 (const_int 0)))
0387639b
DE		 12388 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12389 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12390 "TARGET_32BIT && optimize_size"
1fd4e8c1 12391 "@
0387639b
DE		 12392 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12393 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12394 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12395 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12396 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12397 #
12398 #
12399 #
12400 #
12401 #"
12402 [(set_attr "type" "compare")
12403 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12404
12405(define_split
0387639b 12406 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12407 (compare:CC
12408 (plus:SI
12409 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
56fc483e 12410 (match_operand:SI 2 "scc_eq_operand" ""))
9ebbca7d
GK		 12411 (match_operand:SI 3 "gpc_reg_operand" ""))
12412 (const_int 0)))
12413 (set (match_operand:SI 0 "gpc_reg_operand" "")
0387639b 12414 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
297abd0d 12415 "TARGET_32BIT && optimize_size && reload_completed"
0387639b 12416 [(set (match_dup 0)
9ebbca7d 12417 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
0387639b 12418 (set (match_dup 4)
9ebbca7d
GK		 12419 (compare:CC (match_dup 0)
12420 (const_int 0)))]
12421 "")
12422
d0515b39
DE		 12423(define_insn "*neg_eq0<mode>"
12424 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12425 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12426 (const_int 0))))]
59d6560b 12427 ""
d0515b39
DE		 12428 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12429 [(set_attr "type" "two")
12430 (set_attr "length" "8")])
12431
12432(define_insn_and_split "*neg_eq<mode>"
12433 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12434 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12435 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
59d6560b 12436 ""
d0515b39 12437 "#"
59d6560b 12438 ""
d0515b39
DE		 12439 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12440 {
12441 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12442 {
12443 /* Use output operand as intermediate. */
12444 operands[3] = operands[0];
12445
12446 if (logical_operand (operands[2], <MODE>mode))
12447 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12448 gen_rtx_XOR (<MODE>mode,
12449 operands[1], operands[2])));
12450 else
12451 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12452 gen_rtx_PLUS (<MODE>mode, operands[1],
12453 negate_rtx (<MODE>mode,
12454 operands[2]))));
12455 }
12456 else
12457 operands[3] = operands[1];
12458 })
1fd4e8c1 12459
ea9be077
MM		 12460;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12461;; since it nabs/sr is just as fast.
ce45ef46 12462(define_insn "*ne0si"
b4e95693 12463 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
ea9be077
MM		 12464 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12465 (const_int 31)))
12466 (clobber (match_scratch:SI 2 "=&r"))]
683bdff7 12467 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
ea9be077 12468 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
943c15ed
DE		 12469 [(set_attr "type" "two")
12470 (set_attr "length" "8")])
ea9be077 12471
ce45ef46 12472(define_insn "*ne0di"
a260abc9
DE		 12473 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12474 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12475 (const_int 63)))
12476 (clobber (match_scratch:DI 2 "=&r"))]
683bdff7 12477 "TARGET_64BIT"
a260abc9 12478 "addic %2,%1,-1\;subfe %0,%2,%1"
943c15ed
DE		 12479 [(set_attr "type" "two")
12480 (set_attr "length" "8")])
a260abc9 12481
1fd4e8c1 12482;; This is what (plus (ne X (const_int 0)) Y) looks like.
297abd0d 12483(define_insn "*plus_ne0si"
cd2b37d9 12484 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1fd4e8c1 12485 (plus:SI (lshiftrt:SI
cd2b37d9 12486 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
1fd4e8c1 12487 (const_int 31))
cd2b37d9 12488 (match_operand:SI 2 "gpc_reg_operand" "r")))
1fd4e8c1 12489 (clobber (match_scratch:SI 3 "=&r"))]
683bdff7 12490 "TARGET_32BIT"
ca7f5001 12491 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
943c15ed
DE		 12492 [(set_attr "type" "two")
12493 (set_attr "length" "8")])
1fd4e8c1 12494
297abd0d 12495(define_insn "*plus_ne0di"
a260abc9
DE		 12496 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12497 (plus:DI (lshiftrt:DI
12498 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12499 (const_int 63))
12500 (match_operand:DI 2 "gpc_reg_operand" "r")))
12501 (clobber (match_scratch:DI 3 "=&r"))]
683bdff7 12502 "TARGET_64BIT"
a260abc9 12503 "addic %3,%1,-1\;addze %0,%2"
943c15ed
DE		 12504 [(set_attr "type" "two")
12505 (set_attr "length" "8")])
a260abc9 12506
297abd0d 12507(define_insn "*compare_plus_ne0si"
9ebbca7d 12508 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12509 (compare:CC
12510 (plus:SI (lshiftrt:SI
9ebbca7d 12511 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12512 (const_int 31))
9ebbca7d 12513 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12514 (const_int 0)))
889b90a1
GK		 12515 (clobber (match_scratch:SI 3 "=&r,&r"))
12516 (clobber (match_scratch:SI 4 "=X,&r"))]
683bdff7 12517 "TARGET_32BIT"
9ebbca7d
GK		 12518 "@
12519 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12520 #"
b19003d8 12521 [(set_attr "type" "compare")
9ebbca7d
GK		 12522 (set_attr "length" "8,12")])
12523
12524(define_split
12525 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12526 (compare:CC
12527 (plus:SI (lshiftrt:SI
12528 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12529 (const_int 31))
12530 (match_operand:SI 2 "gpc_reg_operand" ""))
12531 (const_int 0)))
889b90a1
GK		 12532 (clobber (match_scratch:SI 3 ""))
12533 (clobber (match_scratch:SI 4 ""))]
683bdff7 12534 "TARGET_32BIT && reload_completed"
889b90a1 12535 [(parallel [(set (match_dup 3)
ce71f754
AM		 12536 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12537 (const_int 31))
12538 (match_dup 2)))
889b90a1 12539 (clobber (match_dup 4))])
9ebbca7d
GK		 12540 (set (match_dup 0)
12541 (compare:CC (match_dup 3)
12542 (const_int 0)))]
12543 "")
1fd4e8c1 12544
297abd0d 12545(define_insn "*compare_plus_ne0di"
9ebbca7d 12546 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12547 (compare:CC
12548 (plus:DI (lshiftrt:DI
9ebbca7d 12549 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12550 (const_int 63))
9ebbca7d 12551 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12552 (const_int 0)))
9ebbca7d 12553 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12554 "TARGET_64BIT"
9ebbca7d
GK		 12555 "@
12556 addic %3,%1,-1\;addze. %3,%2
12557 #"
a260abc9 12558 [(set_attr "type" "compare")
9ebbca7d
GK		 12559 (set_attr "length" "8,12")])
12560
12561(define_split
12562 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12563 (compare:CC
12564 (plus:DI (lshiftrt:DI
12565 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12566 (const_int 63))
12567 (match_operand:DI 2 "gpc_reg_operand" ""))
12568 (const_int 0)))
12569 (clobber (match_scratch:DI 3 ""))]
683bdff7 12570 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12571 [(set (match_dup 3)
12572 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12573 (const_int 63))
12574 (match_dup 2)))
12575 (set (match_dup 0)
12576 (compare:CC (match_dup 3)
12577 (const_int 0)))]
12578 "")
a260abc9 12579
297abd0d 12580(define_insn "*plus_ne0si_compare"
9ebbca7d 12581 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12582 (compare:CC
12583 (plus:SI (lshiftrt:SI
9ebbca7d 12584 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
1fd4e8c1 12585 (const_int 31))
9ebbca7d 12586 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 12587 (const_int 0)))
9ebbca7d 12588 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1
RK		 12589 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12590 (match_dup 2)))
9ebbca7d 12591 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 12592 "TARGET_32BIT"
9ebbca7d
GK		 12593 "@
12594 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12595 #"
b19003d8 12596 [(set_attr "type" "compare")
9ebbca7d
GK		 12597 (set_attr "length" "8,12")])
12598
12599(define_split
12600 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12601 (compare:CC
12602 (plus:SI (lshiftrt:SI
12603 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12604 (const_int 31))
12605 (match_operand:SI 2 "gpc_reg_operand" ""))
12606 (const_int 0)))
12607 (set (match_operand:SI 0 "gpc_reg_operand" "")
12608 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12609 (match_dup 2)))
12610 (clobber (match_scratch:SI 3 ""))]
683bdff7 12611 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12612 [(parallel [(set (match_dup 0)
12613 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12614 (match_dup 2)))
12615 (clobber (match_dup 3))])
12616 (set (match_dup 4)
12617 (compare:CC (match_dup 0)
12618 (const_int 0)))]
12619 "")
1fd4e8c1 12620
297abd0d 12621(define_insn "*plus_ne0di_compare"
9ebbca7d 12622 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
a260abc9
DE		 12623 (compare:CC
12624 (plus:DI (lshiftrt:DI
9ebbca7d 12625 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
a260abc9 12626 (const_int 63))
9ebbca7d 12627 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
a260abc9 12628 (const_int 0)))
9ebbca7d 12629 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
a260abc9
DE		 12630 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12631 (match_dup 2)))
9ebbca7d 12632 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 12633 "TARGET_64BIT"
9ebbca7d
GK		 12634 "@
12635 addic %3,%1,-1\;addze. %0,%2
12636 #"
a260abc9 12637 [(set_attr "type" "compare")
9ebbca7d
GK		 12638 (set_attr "length" "8,12")])
12639
12640(define_split
12641 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12642 (compare:CC
12643 (plus:DI (lshiftrt:DI
12644 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12645 (const_int 63))
12646 (match_operand:DI 2 "gpc_reg_operand" ""))
12647 (const_int 0)))
12648 (set (match_operand:DI 0 "gpc_reg_operand" "")
12649 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12650 (match_dup 2)))
12651 (clobber (match_scratch:DI 3 ""))]
683bdff7 12652 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 12653 [(parallel [(set (match_dup 0)
12654 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12655 (match_dup 2)))
12656 (clobber (match_dup 3))])
12657 (set (match_dup 4)
12658 (compare:CC (match_dup 0)
12659 (const_int 0)))]
12660 "")
a260abc9 12661
1fd4e8c1 12662(define_insn ""
cd2b37d9
RK		 12663 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12664 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1
RK		 12665 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12666 (clobber (match_scratch:SI 3 "=r,X"))]
ca7f5001 12667 "TARGET_POWER"
1fd4e8c1 12668 "@
ca7f5001 12669 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
7f340546 12670 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 12671 [(set_attr "length" "12")])
1fd4e8c1
RK		 12672
12673(define_insn ""
9ebbca7d 12674 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12675 (compare:CC
9ebbca7d
GK		 12676 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12677 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
1fd4e8c1 12678 (const_int 0)))
9ebbca7d 12679 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1fd4e8c1 12680 (le:SI (match_dup 1) (match_dup 2)))
9ebbca7d 12681 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
ca7f5001 12682 "TARGET_POWER"
1fd4e8c1 12683 "@
ca7f5001 12684 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
9ebbca7d
GK		 12685 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12686 #
12687 #"
12688 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12689 (set_attr "length" "12,12,16,16")])
12690
12691(define_split
12692 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12693 (compare:CC
12694 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12695 (match_operand:SI 2 "reg_or_short_operand" ""))
12696 (const_int 0)))
12697 (set (match_operand:SI 0 "gpc_reg_operand" "")
12698 (le:SI (match_dup 1) (match_dup 2)))
12699 (clobber (match_scratch:SI 3 ""))]
12700 "TARGET_POWER && reload_completed"
12701 [(parallel [(set (match_dup 0)
12702 (le:SI (match_dup 1) (match_dup 2)))
12703 (clobber (match_dup 3))])
12704 (set (match_dup 4)
12705 (compare:CC (match_dup 0)
12706 (const_int 0)))]
12707 "")
1fd4e8c1
RK		 12708
12709(define_insn ""
097657c3 12710 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
cd2b37d9 12711 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12712 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
097657c3 12713 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
ca7f5001 12714 "TARGET_POWER"
1fd4e8c1 12715 "@
097657c3
AM		 12716 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12717 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
b19003d8 12718 [(set_attr "length" "12")])
1fd4e8c1
RK		 12719
12720(define_insn ""
9ebbca7d 12721 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12722 (compare:CC
9ebbca7d
GK		 12723 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12724 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12725 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12726 (const_int 0)))
9ebbca7d 12727 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
ca7f5001 12728 "TARGET_POWER"
1fd4e8c1 12729 "@
ca7f5001 12730 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
9ebbca7d
GK		 12731 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12732 #
12733 #"
b19003d8 12734 [(set_attr "type" "compare")
9ebbca7d
GK		 12735 (set_attr "length" "12,12,16,16")])
12736
12737(define_split
12738 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12739 (compare:CC
12740 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12741 (match_operand:SI 2 "reg_or_short_operand" ""))
12742 (match_operand:SI 3 "gpc_reg_operand" ""))
12743 (const_int 0)))
12744 (clobber (match_scratch:SI 4 ""))]
12745 "TARGET_POWER && reload_completed"
12746 [(set (match_dup 4)
12747 (plus:SI (le:SI (match_dup 1) (match_dup 2))
097657c3 12748 (match_dup 3)))
9ebbca7d
GK		 12749 (set (match_dup 0)
12750 (compare:CC (match_dup 4)
12751 (const_int 0)))]
12752 "")
1fd4e8c1
RK		 12753
12754(define_insn ""
097657c3 12755 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 12756 (compare:CC
9ebbca7d
GK		 12757 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12758 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12759 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 12760 (const_int 0)))
097657c3
AM		 12761 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12762 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 12763 "TARGET_POWER"
1fd4e8c1 12764 "@
097657c3
AM		 12765 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12766 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
9ebbca7d
GK		 12767 #
12768 #"
b19003d8 12769 [(set_attr "type" "compare")
9ebbca7d
GK		 12770 (set_attr "length" "12,12,16,16")])
12771
12772(define_split
097657c3 12773 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12774 (compare:CC
12775 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12776 (match_operand:SI 2 "reg_or_short_operand" ""))
12777 (match_operand:SI 3 "gpc_reg_operand" ""))
12778 (const_int 0)))
12779 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12780 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 12781 "TARGET_POWER && reload_completed"
097657c3 12782 [(set (match_dup 0)
9ebbca7d 12783 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12784 (set (match_dup 4)
9ebbca7d
GK		 12785 (compare:CC (match_dup 0)
12786 (const_int 0)))]
12787 "")
1fd4e8c1
RK		 12788
12789(define_insn ""
cd2b37d9
RK		 12790 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12791 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 12792 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
ca7f5001 12793 "TARGET_POWER"
1fd4e8c1 12794 "@
ca7f5001
RK		 12795 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12796 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 12797 [(set_attr "length" "12")])
1fd4e8c1 12798
a2dba291
DE		 12799(define_insn "*leu<mode>"
12800 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12801 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12802 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12803 ""
ca7f5001 12804 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 12805 [(set_attr "type" "three")
12806 (set_attr "length" "12")])
1fd4e8c1 12807
a2dba291 12808(define_insn "*leu<mode>_compare"
9ebbca7d 12809 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 12810 (compare:CC
a2dba291
DE		 12811 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12812 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 12813 (const_int 0)))
a2dba291
DE		 12814 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12815 (leu:P (match_dup 1) (match_dup 2)))]
12816 ""
9ebbca7d
GK		 12817 "@
12818 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12819 #"
b19003d8 12820 [(set_attr "type" "compare")
9ebbca7d
GK		 12821 (set_attr "length" "12,16")])
12822
12823(define_split
12824 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12825 (compare:CC
a2dba291
DE		 12826 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12827 (match_operand:P 2 "reg_or_short_operand" ""))
9ebbca7d 12828 (const_int 0)))
a2dba291
DE		 12829 (set (match_operand:P 0 "gpc_reg_operand" "")
12830 (leu:P (match_dup 1) (match_dup 2)))]
12831 "reload_completed"
9ebbca7d 12832 [(set (match_dup 0)
a2dba291 12833 (leu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 12834 (set (match_dup 3)
12835 (compare:CC (match_dup 0)
12836 (const_int 0)))]
12837 "")
1fd4e8c1 12838
a2dba291
DE		 12839(define_insn "*plus_leu<mode>"
12840 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12841 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12842 (match_operand:P 2 "reg_or_short_operand" "rI"))
12843 (match_operand:P 3 "gpc_reg_operand" "r")))]
12844 ""
80103f96 12845 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
943c15ed
DE		 12846 [(set_attr "type" "two")
12847 (set_attr "length" "8")])
1fd4e8c1
RK		 12848
12849(define_insn ""
9ebbca7d 12850 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 12851 (compare:CC
9ebbca7d
GK		 12852 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12853 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12854 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12855 (const_int 0)))
9ebbca7d 12856 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12857 "TARGET_32BIT"
9ebbca7d
GK		 12858 "@
12859 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12860 #"
b19003d8 12861 [(set_attr "type" "compare")
9ebbca7d
GK		 12862 (set_attr "length" "8,12")])
12863
12864(define_split
12865 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12866 (compare:CC
12867 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12868 (match_operand:SI 2 "reg_or_short_operand" ""))
12869 (match_operand:SI 3 "gpc_reg_operand" ""))
12870 (const_int 0)))
12871 (clobber (match_scratch:SI 4 ""))]
683bdff7 12872 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 12873 [(set (match_dup 4)
12874 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12875 (match_dup 3)))
12876 (set (match_dup 0)
12877 (compare:CC (match_dup 4)
12878 (const_int 0)))]
12879 "")
1fd4e8c1
RK		 12880
12881(define_insn ""
097657c3 12882 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 12883 (compare:CC
9ebbca7d
GK		 12884 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12885 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12886 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12887 (const_int 0)))
097657c3
AM		 12888 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12889 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12890 "TARGET_32BIT"
9ebbca7d 12891 "@
097657c3 12892 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
9ebbca7d 12893 #"
b19003d8 12894 [(set_attr "type" "compare")
9ebbca7d
GK		 12895 (set_attr "length" "8,12")])
12896
12897(define_split
097657c3 12898 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12899 (compare:CC
12900 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12901 (match_operand:SI 2 "reg_or_short_operand" ""))
12902 (match_operand:SI 3 "gpc_reg_operand" ""))
12903 (const_int 0)))
12904 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12905 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 12906 "TARGET_32BIT && reload_completed"
097657c3 12907 [(set (match_dup 0)
9ebbca7d 12908 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 12909 (set (match_dup 4)
9ebbca7d
GK		 12910 (compare:CC (match_dup 0)
12911 (const_int 0)))]
12912 "")
1fd4e8c1 12913
a2dba291
DE		 12914(define_insn "*neg_leu<mode>"
12915 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12916 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12917 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12918 ""
ca7f5001 12919 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
943c15ed
DE		 12920 [(set_attr "type" "three")
12921 (set_attr "length" "12")])
1fd4e8c1 12922
a2dba291
DE		 12923(define_insn "*and_neg_leu<mode>"
12924 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12925 (and:P (neg:P
12926 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12927 (match_operand:P 2 "reg_or_short_operand" "rI")))
12928 (match_operand:P 3 "gpc_reg_operand" "r")))]
12929 ""
097657c3 12930 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 12931 [(set_attr "type" "three")
12932 (set_attr "length" "12")])
1fd4e8c1
RK		 12933
12934(define_insn ""
9ebbca7d 12935 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12936 (compare:CC
12937 (and:SI (neg:SI
9ebbca7d
GK		 12938 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12939 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12940 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12941 (const_int 0)))
9ebbca7d 12942 (clobber (match_scratch:SI 4 "=&r,&r"))]
683bdff7 12943 "TARGET_32BIT"
9ebbca7d
GK		 12944 "@
12945 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12946 #"
12947 [(set_attr "type" "compare")
12948 (set_attr "length" "12,16")])
12949
12950(define_split
12951 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12952 (compare:CC
12953 (and:SI (neg:SI
12954 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12955 (match_operand:SI 2 "reg_or_short_operand" "")))
12956 (match_operand:SI 3 "gpc_reg_operand" ""))
12957 (const_int 0)))
12958 (clobber (match_scratch:SI 4 ""))]
683bdff7 12959 "TARGET_32BIT && reload_completed"
9ebbca7d 12960 [(set (match_dup 4)
097657c3
AM		 12961 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12962 (match_dup 3)))
9ebbca7d
GK		 12963 (set (match_dup 0)
12964 (compare:CC (match_dup 4)
12965 (const_int 0)))]
12966 "")
1fd4e8c1
RK		 12967
12968(define_insn ""
097657c3 12969 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1
RK		 12970 (compare:CC
12971 (and:SI (neg:SI
9ebbca7d
GK		 12972 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12973 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12974 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 12975 (const_int 0)))
097657c3
AM		 12976 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12977 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 12978 "TARGET_32BIT"
9ebbca7d 12979 "@
097657c3 12980 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d 12981 #"
b19003d8 12982 [(set_attr "type" "compare")
9ebbca7d
GK		 12983 (set_attr "length" "12,16")])
12984
12985(define_split
097657c3 12986 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 12987 (compare:CC
12988 (and:SI (neg:SI
12989 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12990 (match_operand:SI 2 "reg_or_short_operand" "")))
12991 (match_operand:SI 3 "gpc_reg_operand" ""))
12992 (const_int 0)))
12993 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 12994 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 12995 "TARGET_32BIT && reload_completed"
097657c3
AM		 12996 [(set (match_dup 0)
12997 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12998 (match_dup 3)))
12999 (set (match_dup 4)
9ebbca7d
GK		 13000 (compare:CC (match_dup 0)
13001 (const_int 0)))]
13002 "")
1fd4e8c1
RK		 13003
13004(define_insn ""
cd2b37d9
RK		 13005 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13006 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13007 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
ca7f5001 13008 "TARGET_POWER"
7f340546 13009 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13010 [(set_attr "length" "12")])
1fd4e8c1
RK		 13011
13012(define_insn ""
9ebbca7d 13013 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13014 (compare:CC
9ebbca7d
GK		 13015 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13016 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13017 (const_int 0)))
9ebbca7d 13018 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13019 (lt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13020 "TARGET_POWER"
9ebbca7d
GK		 13021 "@
13022 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13023 #"
29ae5b89 13024 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13025 (set_attr "length" "12,16")])
13026
13027(define_split
13028 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13029 (compare:CC
13030 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13031 (match_operand:SI 2 "reg_or_short_operand" ""))
13032 (const_int 0)))
13033 (set (match_operand:SI 0 "gpc_reg_operand" "")
13034 (lt:SI (match_dup 1) (match_dup 2)))]
13035 "TARGET_POWER && reload_completed"
13036 [(set (match_dup 0)
13037 (lt:SI (match_dup 1) (match_dup 2)))
13038 (set (match_dup 3)
13039 (compare:CC (match_dup 0)
13040 (const_int 0)))]
13041 "")
1fd4e8c1
RK		 13042
13043(define_insn ""
097657c3 13044 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13045 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13046 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13047 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13048 "TARGET_POWER"
097657c3 13049 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13050 [(set_attr "length" "12")])
1fd4e8c1
RK		 13051
13052(define_insn ""
9ebbca7d 13053 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13054 (compare:CC
9ebbca7d
GK		 13055 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13056 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13057 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13058 (const_int 0)))
9ebbca7d 13059 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13060 "TARGET_POWER"
9ebbca7d
GK		 13061 "@
13062 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13063 #"
b19003d8 13064 [(set_attr "type" "compare")
9ebbca7d
GK		 13065 (set_attr "length" "12,16")])
13066
13067(define_split
13068 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13069 (compare:CC
13070 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13071 (match_operand:SI 2 "reg_or_short_operand" ""))
13072 (match_operand:SI 3 "gpc_reg_operand" ""))
13073 (const_int 0)))
13074 (clobber (match_scratch:SI 4 ""))]
13075 "TARGET_POWER && reload_completed"
13076 [(set (match_dup 4)
13077 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
097657c3 13078 (match_dup 3)))
9ebbca7d
GK		 13079 (set (match_dup 0)
13080 (compare:CC (match_dup 4)
13081 (const_int 0)))]
13082 "")
1fd4e8c1
RK		 13083
13084(define_insn ""
097657c3 13085 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13086 (compare:CC
9ebbca7d
GK		 13087 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13088 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13089 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13090 (const_int 0)))
097657c3
AM		 13091 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13092 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13093 "TARGET_POWER"
9ebbca7d 13094 "@
097657c3 13095 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13096 #"
b19003d8 13097 [(set_attr "type" "compare")
9ebbca7d
GK		 13098 (set_attr "length" "12,16")])
13099
13100(define_split
097657c3 13101 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13102 (compare:CC
13103 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13104 (match_operand:SI 2 "reg_or_short_operand" ""))
13105 (match_operand:SI 3 "gpc_reg_operand" ""))
13106 (const_int 0)))
13107 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13108 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13109 "TARGET_POWER && reload_completed"
097657c3 13110 [(set (match_dup 0)
9ebbca7d 13111 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13112 (set (match_dup 4)
9ebbca7d
GK		 13113 (compare:CC (match_dup 0)
13114 (const_int 0)))]
13115 "")
1fd4e8c1
RK		 13116
13117(define_insn ""
cd2b37d9
RK		 13118 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13119 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13120 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13121 "TARGET_POWER"
13122 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13123 [(set_attr "length" "12")])
1fd4e8c1 13124
ce45ef46
DE		 13125(define_insn_and_split "*ltu<mode>"
13126 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13127 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13128 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13129 ""
c0600ecd 13130 "#"
ce45ef46
DE		 13131 ""
13132 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13133 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 13134 "")
1fd4e8c1 13135
1e24ce83 13136(define_insn_and_split "*ltu<mode>_compare"
9ebbca7d 13137 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13138 (compare:CC
a2dba291
DE		 13139 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13140 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13141 (const_int 0)))
a2dba291
DE		 13142 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13143 (ltu:P (match_dup 1) (match_dup 2)))]
13144 ""
1e24ce83
DE		 13145 "#"
13146 ""
13147 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13148 (parallel [(set (match_dup 3)
13149 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13150 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 13151 "")
1fd4e8c1 13152
a2dba291
DE		 13153(define_insn_and_split "*plus_ltu<mode>"
13154 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
13155 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13156 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
1e24ce83 13157 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
a2dba291 13158 ""
c0600ecd 13159 "#"
04fa46cf 13160 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 13161 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13162 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 13163 "")
1fd4e8c1 13164
1e24ce83 13165(define_insn_and_split "*plus_ltu<mode>_compare"
097657c3 13166 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13167 (compare:CC
1e24ce83
DE		 13168 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13169 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13170 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13171 (const_int 0)))
1e24ce83
DE		 13172 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13173 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13174 ""
13175 "#"
13176 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13177 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13178 (parallel [(set (match_dup 4)
13179 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13180 (const_int 0)))
13181 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 13182 "")
1fd4e8c1 13183
ce45ef46
DE		 13184(define_insn "*neg_ltu<mode>"
13185 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13186 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13187 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13188 ""
c0600ecd
DE		 13189 "@
13190 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13191 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
943c15ed 13192 [(set_attr "type" "two")
c0600ecd 13193 (set_attr "length" "8")])
1fd4e8c1
RK		 13194
13195(define_insn ""
cd2b37d9
RK		 13196 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13197 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1
RK		 13198 (match_operand:SI 2 "reg_or_short_operand" "rI")))
13199 (clobber (match_scratch:SI 3 "=r"))]
ca7f5001
RK		 13200 "TARGET_POWER"
13201 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
b19003d8 13202 [(set_attr "length" "12")])
1fd4e8c1 13203
9ebbca7d
GK		 13204(define_insn ""
13205 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13206 (compare:CC
9ebbca7d
GK		 13207 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13208 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13209 (const_int 0)))
9ebbca7d 13210 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13211 (ge:SI (match_dup 1) (match_dup 2)))
9ebbca7d 13212 (clobber (match_scratch:SI 3 "=r,r"))]
ca7f5001 13213 "TARGET_POWER"
9ebbca7d
GK		 13214 "@
13215 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13216 #"
13217 [(set_attr "type" "compare")
13218 (set_attr "length" "12,16")])
13219
13220(define_split
13221 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13222 (compare:CC
13223 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13224 (match_operand:SI 2 "reg_or_short_operand" ""))
13225 (const_int 0)))
13226 (set (match_operand:SI 0 "gpc_reg_operand" "")
13227 (ge:SI (match_dup 1) (match_dup 2)))
13228 (clobber (match_scratch:SI 3 ""))]
13229 "TARGET_POWER && reload_completed"
13230 [(parallel [(set (match_dup 0)
097657c3
AM		 13231 (ge:SI (match_dup 1) (match_dup 2)))
13232 (clobber (match_dup 3))])
9ebbca7d
GK		 13233 (set (match_dup 4)
13234 (compare:CC (match_dup 0)
13235 (const_int 0)))]
13236 "")
13237
1fd4e8c1 13238(define_insn ""
097657c3 13239 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13240 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13241 (match_operand:SI 2 "reg_or_short_operand" "rI"))
097657c3 13242 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13243 "TARGET_POWER"
097657c3 13244 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
b19003d8 13245 [(set_attr "length" "12")])
1fd4e8c1
RK		 13246
13247(define_insn ""
9ebbca7d 13248 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13249 (compare:CC
9ebbca7d
GK		 13250 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13251 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13252 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13253 (const_int 0)))
9ebbca7d 13254 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13255 "TARGET_POWER"
9ebbca7d
GK		 13256 "@
13257 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13258 #"
b19003d8 13259 [(set_attr "type" "compare")
9ebbca7d
GK		 13260 (set_attr "length" "12,16")])
13261
13262(define_split
13263 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13264 (compare:CC
13265 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13266 (match_operand:SI 2 "reg_or_short_operand" ""))
13267 (match_operand:SI 3 "gpc_reg_operand" ""))
13268 (const_int 0)))
13269 (clobber (match_scratch:SI 4 ""))]
13270 "TARGET_POWER && reload_completed"
13271 [(set (match_dup 4)
13272 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
097657c3 13273 (match_dup 3)))
9ebbca7d
GK		 13274 (set (match_dup 0)
13275 (compare:CC (match_dup 4)
13276 (const_int 0)))]
13277 "")
1fd4e8c1
RK		 13278
13279(define_insn ""
097657c3 13280 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13281 (compare:CC
9ebbca7d
GK		 13282 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13283 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13284 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13285 (const_int 0)))
097657c3
AM		 13286 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13287 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13288 "TARGET_POWER"
9ebbca7d 13289 "@
097657c3 13290 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
9ebbca7d 13291 #"
b19003d8 13292 [(set_attr "type" "compare")
9ebbca7d
GK		 13293 (set_attr "length" "12,16")])
13294
13295(define_split
097657c3 13296 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13297 (compare:CC
13298 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13299 (match_operand:SI 2 "reg_or_short_operand" ""))
13300 (match_operand:SI 3 "gpc_reg_operand" ""))
13301 (const_int 0)))
13302 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13303 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13304 "TARGET_POWER && reload_completed"
097657c3 13305 [(set (match_dup 0)
9ebbca7d 13306 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13307 (set (match_dup 4)
9ebbca7d
GK		 13308 (compare:CC (match_dup 0)
13309 (const_int 0)))]
13310 "")
1fd4e8c1
RK		 13311
13312(define_insn ""
cd2b37d9
RK		 13313 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13314 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13315 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
ca7f5001
RK		 13316 "TARGET_POWER"
13317 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
b19003d8 13318 [(set_attr "length" "12")])
1fd4e8c1 13319
a2dba291
DE		 13320(define_insn "*geu<mode>"
13321 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13322 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13323 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13324 ""
1fd4e8c1 13325 "@
ca7f5001
RK		 13326 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13327 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
943c15ed
DE		 13328 [(set_attr "type" "three")
13329 (set_attr "length" "12")])
1fd4e8c1 13330
a2dba291 13331(define_insn "*geu<mode>_compare"
9ebbca7d 13332 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13333 (compare:CC
a2dba291
DE		 13334 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13335 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
1fd4e8c1 13336 (const_int 0)))
a2dba291
DE		 13337 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13338 (geu:P (match_dup 1) (match_dup 2)))]
13339 ""
1fd4e8c1 13340 "@
ca7f5001 13341 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
9ebbca7d
GK		 13342 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13343 #
13344 #"
b19003d8 13345 [(set_attr "type" "compare")
9ebbca7d
GK		 13346 (set_attr "length" "12,12,16,16")])
13347
13348(define_split
13349 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13350 (compare:CC
a2dba291
DE		 13351 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13352 (match_operand:P 2 "reg_or_neg_short_operand" ""))
9ebbca7d 13353 (const_int 0)))
a2dba291
DE		 13354 (set (match_operand:P 0 "gpc_reg_operand" "")
13355 (geu:P (match_dup 1) (match_dup 2)))]
13356 "reload_completed"
9ebbca7d 13357 [(set (match_dup 0)
a2dba291 13358 (geu:P (match_dup 1) (match_dup 2)))
9ebbca7d
GK		 13359 (set (match_dup 3)
13360 (compare:CC (match_dup 0)
13361 (const_int 0)))]
13362 "")
f9562f27 13363
a2dba291
DE		 13364(define_insn "*plus_geu<mode>"
13365 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13366 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13367 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13368 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13369 ""
1fd4e8c1 13370 "@
80103f96
FS		 13371 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13372 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
943c15ed
DE		 13373 [(set_attr "type" "two")
13374 (set_attr "length" "8")])
1fd4e8c1
RK		 13375
13376(define_insn ""
9ebbca7d 13377 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13378 (compare:CC
9ebbca7d
GK		 13379 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13380 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13381 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13382 (const_int 0)))
9ebbca7d 13383 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13384 "TARGET_32BIT"
1fd4e8c1 13385 "@
ca7f5001 13386 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
9ebbca7d
GK		 13387 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13388 #
13389 #"
b19003d8 13390 [(set_attr "type" "compare")
9ebbca7d
GK		 13391 (set_attr "length" "8,8,12,12")])
13392
13393(define_split
13394 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13395 (compare:CC
13396 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13397 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13398 (match_operand:SI 3 "gpc_reg_operand" ""))
13399 (const_int 0)))
13400 (clobber (match_scratch:SI 4 ""))]
683bdff7 13401 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13402 [(set (match_dup 4)
13403 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13404 (match_dup 3)))
13405 (set (match_dup 0)
13406 (compare:CC (match_dup 4)
13407 (const_int 0)))]
13408 "")
1fd4e8c1
RK		 13409
13410(define_insn ""
097657c3 13411 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1 13412 (compare:CC
9ebbca7d
GK		 13413 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13414 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13415 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13416 (const_int 0)))
097657c3
AM		 13417 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13418 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13419 "TARGET_32BIT"
1fd4e8c1 13420 "@
097657c3
AM		 13421 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13422 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
9ebbca7d
GK		 13423 #
13424 #"
b19003d8 13425 [(set_attr "type" "compare")
9ebbca7d
GK		 13426 (set_attr "length" "8,8,12,12")])
13427
13428(define_split
097657c3 13429 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13430 (compare:CC
13431 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13432 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13433 (match_operand:SI 3 "gpc_reg_operand" ""))
13434 (const_int 0)))
13435 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13436 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
683bdff7 13437 "TARGET_32BIT && reload_completed"
097657c3 13438 [(set (match_dup 0)
9ebbca7d 13439 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13440 (set (match_dup 4)
9ebbca7d
GK		 13441 (compare:CC (match_dup 0)
13442 (const_int 0)))]
13443 "")
1fd4e8c1 13444
a2dba291
DE		 13445(define_insn "*neg_geu<mode>"
13446 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13447 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13448 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13449 ""
1fd4e8c1 13450 "@
ca7f5001 13451 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
8106dc08 13452 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
943c15ed
DE		 13453 [(set_attr "type" "three")
13454 (set_attr "length" "12")])
1fd4e8c1 13455
a2dba291
DE		 13456(define_insn "*and_neg_geu<mode>"
13457 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13458 (and:P (neg:P
13459 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13460 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13461 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13462 ""
1fd4e8c1 13463 "@
097657c3
AM		 13464 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13465 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
943c15ed
DE		 13466 [(set_attr "type" "three")
13467 (set_attr "length" "12")])
1fd4e8c1
RK		 13468
13469(define_insn ""
9ebbca7d 13470 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13471 (compare:CC
13472 (and:SI (neg:SI
9ebbca7d
GK		 13473 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13474 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13475 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13476 (const_int 0)))
9ebbca7d 13477 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
683bdff7 13478 "TARGET_32BIT"
1fd4e8c1 13479 "@
ca7f5001 13480 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
9ebbca7d
GK		 13481 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13482 #
13483 #"
b19003d8 13484 [(set_attr "type" "compare")
9ebbca7d
GK		 13485 (set_attr "length" "12,12,16,16")])
13486
13487(define_split
13488 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13489 (compare:CC
13490 (and:SI (neg:SI
13491 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13492 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13493 (match_operand:SI 3 "gpc_reg_operand" ""))
13494 (const_int 0)))
13495 (clobber (match_scratch:SI 4 ""))]
683bdff7 13496 "TARGET_32BIT && reload_completed"
9ebbca7d 13497 [(set (match_dup 4)
097657c3
AM		 13498 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13499 (match_dup 3)))
9ebbca7d
GK		 13500 (set (match_dup 0)
13501 (compare:CC (match_dup 4)
13502 (const_int 0)))]
13503 "")
1fd4e8c1
RK		 13504
13505(define_insn ""
097657c3 13506 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
1fd4e8c1
RK		 13507 (compare:CC
13508 (and:SI (neg:SI
9ebbca7d
GK		 13509 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13510 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13511 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
1fd4e8c1 13512 (const_int 0)))
097657c3
AM		 13513 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13514 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13515 "TARGET_32BIT"
1fd4e8c1 13516 "@
097657c3
AM		 13517 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13518 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
9ebbca7d
GK		 13519 #
13520 #"
b19003d8 13521 [(set_attr "type" "compare")
9ebbca7d
GK		 13522 (set_attr "length" "12,12,16,16")])
13523
13524(define_split
097657c3 13525 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13526 (compare:CC
13527 (and:SI (neg:SI
13528 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13529 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13530 (match_operand:SI 3 "gpc_reg_operand" ""))
13531 (const_int 0)))
13532 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13533 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
683bdff7 13534 "TARGET_32BIT && reload_completed"
097657c3 13535 [(set (match_dup 0)
9ebbca7d 13536 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
097657c3 13537 (set (match_dup 4)
9ebbca7d
GK		 13538 (compare:CC (match_dup 0)
13539 (const_int 0)))]
13540 "")
1fd4e8c1 13541
1fd4e8c1 13542(define_insn ""
cd2b37d9
RK		 13543 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13544 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13545 (match_operand:SI 2 "reg_or_short_operand" "r")))]
ca7f5001
RK		 13546 "TARGET_POWER"
13547 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
b19003d8 13548 [(set_attr "length" "12")])
1fd4e8c1
RK		 13549
13550(define_insn ""
9ebbca7d 13551 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13552 (compare:CC
9ebbca7d
GK		 13553 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13554 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
1fd4e8c1 13555 (const_int 0)))
9ebbca7d 13556 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1fd4e8c1 13557 (gt:SI (match_dup 1) (match_dup 2)))]
ca7f5001 13558 "TARGET_POWER"
9ebbca7d
GK		 13559 "@
13560 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13561 #"
29ae5b89 13562 [(set_attr "type" "delayed_compare")
9ebbca7d
GK		 13563 (set_attr "length" "12,16")])
13564
13565(define_split
13566 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13567 (compare:CC
13568 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13569 (match_operand:SI 2 "reg_or_short_operand" ""))
13570 (const_int 0)))
13571 (set (match_operand:SI 0 "gpc_reg_operand" "")
13572 (gt:SI (match_dup 1) (match_dup 2)))]
13573 "TARGET_POWER && reload_completed"
13574 [(set (match_dup 0)
13575 (gt:SI (match_dup 1) (match_dup 2)))
13576 (set (match_dup 3)
13577 (compare:CC (match_dup 0)
13578 (const_int 0)))]
13579 "")
1fd4e8c1 13580
d0515b39 13581(define_insn "*plus_gt0<mode>"
a2dba291
DE		 13582 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13583 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13584 (const_int 0))
13585 (match_operand:P 2 "gpc_reg_operand" "r")))]
13586 ""
80103f96 13587 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
943c15ed
DE		 13588 [(set_attr "type" "three")
13589 (set_attr "length" "12")])
1fd4e8c1
RK		 13590
13591(define_insn ""
9ebbca7d 13592 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13593 (compare:CC
9ebbca7d 13594 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1fd4e8c1 13595 (const_int 0))
9ebbca7d 13596 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1fd4e8c1 13597 (const_int 0)))
9ebbca7d 13598 (clobber (match_scratch:SI 3 "=&r,&r"))]
683bdff7 13599 "TARGET_32BIT"
9ebbca7d
GK		 13600 "@
13601 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13602 #"
b19003d8 13603 [(set_attr "type" "compare")
9ebbca7d
GK		 13604 (set_attr "length" "12,16")])
13605
13606(define_split
13607 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13608 (compare:CC
13609 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13610 (const_int 0))
13611 (match_operand:SI 2 "gpc_reg_operand" ""))
13612 (const_int 0)))
13613 (clobber (match_scratch:SI 3 ""))]
683bdff7 13614 "TARGET_32BIT && reload_completed"
9ebbca7d
GK		 13615 [(set (match_dup 3)
13616 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13617 (match_dup 2)))
13618 (set (match_dup 0)
13619 (compare:CC (match_dup 3)
13620 (const_int 0)))]
13621 "")
1fd4e8c1 13622
f9562f27 13623(define_insn ""
9ebbca7d 13624 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
f9562f27 13625 (compare:CC
9ebbca7d 13626 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13627 (const_int 0))
9ebbca7d 13628 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13629 (const_int 0)))
9ebbca7d 13630 (clobber (match_scratch:DI 3 "=&r,&r"))]
683bdff7 13631 "TARGET_64BIT"
9ebbca7d
GK		 13632 "@
13633 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13634 #"
f9562f27 13635 [(set_attr "type" "compare")
9ebbca7d
GK		 13636 (set_attr "length" "12,16")])
13637
13638(define_split
13639 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13640 (compare:CC
13641 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13642 (const_int 0))
13643 (match_operand:DI 2 "gpc_reg_operand" ""))
13644 (const_int 0)))
13645 (clobber (match_scratch:DI 3 ""))]
683bdff7 13646 "TARGET_64BIT && reload_completed"
9ebbca7d
GK		 13647 [(set (match_dup 3)
13648 (plus:DI (gt:DI (match_dup 1) (const_int 0))
097657c3 13649 (match_dup 2)))
9ebbca7d
GK		 13650 (set (match_dup 0)
13651 (compare:CC (match_dup 3)
13652 (const_int 0)))]
13653 "")
f9562f27 13654
1fd4e8c1 13655(define_insn ""
097657c3 13656 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
9ebbca7d
GK		 13657 (compare:CC
13658 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13659 (const_int 0))
13660 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13661 (const_int 0)))
097657c3
AM		 13662 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13663 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13664 "TARGET_32BIT"
9ebbca7d 13665 "@
097657c3 13666 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
9ebbca7d
GK		 13667 #"
13668 [(set_attr "type" "compare")
13669 (set_attr "length" "12,16")])
13670
13671(define_split
097657c3 13672 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1fd4e8c1 13673 (compare:CC
9ebbca7d 13674 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1fd4e8c1 13675 (const_int 0))
9ebbca7d 13676 (match_operand:SI 2 "gpc_reg_operand" ""))
1fd4e8c1 13677 (const_int 0)))
9ebbca7d 13678 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13679 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13680 "TARGET_32BIT && reload_completed"
097657c3 13681 [(set (match_dup 0)
9ebbca7d 13682 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13683 (set (match_dup 3)
9ebbca7d
GK		 13684 (compare:CC (match_dup 0)
13685 (const_int 0)))]
13686 "")
1fd4e8c1 13687
f9562f27 13688(define_insn ""
097657c3 13689 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
f9562f27 13690 (compare:CC
9ebbca7d 13691 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
f9562f27 13692 (const_int 0))
9ebbca7d 13693 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
f9562f27 13694 (const_int 0)))
097657c3
AM		 13695 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13696 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13697 "TARGET_64BIT"
9ebbca7d 13698 "@
097657c3 13699 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
9ebbca7d 13700 #"
f9562f27 13701 [(set_attr "type" "compare")
9ebbca7d
GK		 13702 (set_attr "length" "12,16")])
13703
13704(define_split
097657c3 13705 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13706 (compare:CC
13707 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13708 (const_int 0))
13709 (match_operand:DI 2 "gpc_reg_operand" ""))
13710 (const_int 0)))
13711 (set (match_operand:DI 0 "gpc_reg_operand" "")
097657c3 13712 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
683bdff7 13713 "TARGET_64BIT && reload_completed"
097657c3 13714 [(set (match_dup 0)
9ebbca7d 13715 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
097657c3 13716 (set (match_dup 3)
9ebbca7d
GK		 13717 (compare:CC (match_dup 0)
13718 (const_int 0)))]
13719 "")
f9562f27 13720
1fd4e8c1 13721(define_insn ""
097657c3 13722 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
cd2b37d9 13723 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13724 (match_operand:SI 2 "reg_or_short_operand" "r"))
097657c3 13725 (match_operand:SI 3 "gpc_reg_operand" "r")))]
ca7f5001 13726 "TARGET_POWER"
097657c3 13727 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
b19003d8 13728 [(set_attr "length" "12")])
1fd4e8c1
RK		 13729
13730(define_insn ""
9ebbca7d 13731 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1fd4e8c1 13732 (compare:CC
9ebbca7d
GK		 13733 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13734 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13735 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13736 (const_int 0)))
9ebbca7d 13737 (clobber (match_scratch:SI 4 "=&r,&r"))]
ca7f5001 13738 "TARGET_POWER"
9ebbca7d
GK		 13739 "@
13740 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13741 #"
b19003d8 13742 [(set_attr "type" "compare")
9ebbca7d
GK		 13743 (set_attr "length" "12,16")])
13744
13745(define_split
13746 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13747 (compare:CC
13748 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13749 (match_operand:SI 2 "reg_or_short_operand" ""))
13750 (match_operand:SI 3 "gpc_reg_operand" ""))
13751 (const_int 0)))
13752 (clobber (match_scratch:SI 4 ""))]
13753 "TARGET_POWER && reload_completed"
13754 [(set (match_dup 4)
097657c3 13755 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
9ebbca7d
GK		 13756 (set (match_dup 0)
13757 (compare:CC (match_dup 4)
13758 (const_int 0)))]
13759 "")
1fd4e8c1
RK		 13760
13761(define_insn ""
097657c3 13762 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
1fd4e8c1 13763 (compare:CC
9ebbca7d
GK		 13764 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13765 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13766 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
1fd4e8c1 13767 (const_int 0)))
097657c3
AM		 13768 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13769 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
ca7f5001 13770 "TARGET_POWER"
9ebbca7d 13771 "@
097657c3 13772 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
9ebbca7d 13773 #"
b19003d8 13774 [(set_attr "type" "compare")
9ebbca7d
GK		 13775 (set_attr "length" "12,16")])
13776
13777(define_split
097657c3 13778 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
9ebbca7d
GK		 13779 (compare:CC
13780 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13781 (match_operand:SI 2 "reg_or_short_operand" ""))
13782 (match_operand:SI 3 "gpc_reg_operand" ""))
13783 (const_int 0)))
13784 (set (match_operand:SI 0 "gpc_reg_operand" "")
097657c3 13785 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
9ebbca7d 13786 "TARGET_POWER && reload_completed"
097657c3 13787 [(set (match_dup 0)
9ebbca7d 13788 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
097657c3 13789 (set (match_dup 4)
9ebbca7d
GK		 13790 (compare:CC (match_dup 0)
13791 (const_int 0)))]
13792 "")
1fd4e8c1 13793
1fd4e8c1 13794(define_insn ""
cd2b37d9
RK		 13795 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13796 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1fd4e8c1 13797 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
ca7f5001
RK		 13798 "TARGET_POWER"
13799 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
b19003d8 13800 [(set_attr "length" "12")])
1fd4e8c1 13801
ce45ef46
DE		 13802(define_insn_and_split "*gtu<mode>"
13803 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13804 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13805 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13806 ""
c0600ecd 13807 "#"
ce45ef46
DE		 13808 ""
13809 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13810 (set (match_dup 0) (neg:P (match_dup 0)))]
c0600ecd 13811 "")
f9562f27 13812
1e24ce83 13813(define_insn_and_split "*gtu<mode>_compare"
9ebbca7d 13814 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1fd4e8c1 13815 (compare:CC
a2dba291
DE		 13816 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13817 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
1fd4e8c1 13818 (const_int 0)))
a2dba291
DE		 13819 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13820 (gtu:P (match_dup 1) (match_dup 2)))]
13821 ""
1e24ce83
DE		 13822 "#"
13823 ""
13824 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13825 (parallel [(set (match_dup 3)
13826 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13827 (set (match_dup 0) (neg:P (match_dup 0)))])]
9ebbca7d 13828 "")
f9562f27 13829
1e24ce83 13830(define_insn_and_split "*plus_gtu<mode>"
a2dba291
DE		 13831 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13832 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13833 (match_operand:P 2 "reg_or_short_operand" "rI"))
13834 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13835 ""
c0600ecd 13836 "#"
04fa46cf 13837 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
a2dba291
DE		 13838 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13839 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
c0600ecd 13840 "")
f9562f27 13841
1e24ce83 13842(define_insn_and_split "*plus_gtu<mode>_compare"
097657c3 13843 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
f9562f27 13844 (compare:CC
1e24ce83
DE		 13845 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13846 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13847 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
f9562f27 13848 (const_int 0)))
1e24ce83
DE		 13849 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13850 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13851 ""
13852 "#"
13853 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13854 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13855 (parallel [(set (match_dup 4)
13856 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13857 (const_int 0)))
13858 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
9ebbca7d 13859 "")
f9562f27 13860
ce45ef46
DE		 13861(define_insn "*neg_gtu<mode>"
13862 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13863 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13864 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13865 ""
ca7f5001 13866 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
943c15ed 13867 [(set_attr "type" "two")
c0600ecd 13868 (set_attr "length" "8")])
f9562f27 13869
1fd4e8c1
RK		 13870\f
13871;; Define both directions of branch and return. If we need a reload
13872;; register, we'd rather use CR0 since it is much easier to copy a
13873;; register CC value to there.
13874
13875(define_insn ""
13876 [(set (pc)
13877 (if_then_else (match_operator 1 "branch_comparison_operator"
13878 [(match_operand 2
b54cf83a 13879 "cc_reg_operand" "y")
1fd4e8c1
RK		 13880 (const_int 0)])
13881 (label_ref (match_operand 0 "" ""))
13882 (pc)))]
13883 ""
b19003d8
RK		 13884 "*
13885{
12a4e8c5 13886 return output_cbranch (operands[1], \"%l0\", 0, insn);
b19003d8
RK		 13887}"
13888 [(set_attr "type" "branch")])
13889
1fd4e8c1
RK		 13890(define_insn ""
13891 [(set (pc)
13892 (if_then_else (match_operator 0 "branch_comparison_operator"
13893 [(match_operand 1
b54cf83a 13894 "cc_reg_operand" "y")
1fd4e8c1
RK		 13895 (const_int 0)])
13896 (return)
13897 (pc)))]
13898 "direct_return ()"
12a4e8c5
GK		 13899 "*
13900{
13901 return output_cbranch (operands[0], NULL, 0, insn);
13902}"
9c6fdb46 13903 [(set_attr "type" "jmpreg")
39a10a29 13904 (set_attr "length" "4")])
1fd4e8c1
RK		 13905
13906(define_insn ""
13907 [(set (pc)
13908 (if_then_else (match_operator 1 "branch_comparison_operator"
13909 [(match_operand 2
b54cf83a 13910 "cc_reg_operand" "y")
1fd4e8c1
RK		 13911 (const_int 0)])
13912 (pc)
13913 (label_ref (match_operand 0 "" ""))))]
13914 ""
b19003d8
RK		 13915 "*
13916{
12a4e8c5 13917 return output_cbranch (operands[1], \"%l0\", 1, insn);
b19003d8
RK		 13918}"
13919 [(set_attr "type" "branch")])
1fd4e8c1
RK		 13920
13921(define_insn ""
13922 [(set (pc)
13923 (if_then_else (match_operator 0 "branch_comparison_operator"
13924 [(match_operand 1
b54cf83a 13925 "cc_reg_operand" "y")
1fd4e8c1
RK		 13926 (const_int 0)])
13927 (pc)
13928 (return)))]
13929 "direct_return ()"
12a4e8c5
GK		 13930 "*
13931{
13932 return output_cbranch (operands[0], NULL, 1, insn);
13933}"
9c6fdb46 13934 [(set_attr "type" "jmpreg")
39a10a29
GK		 13935 (set_attr "length" "4")])
13936
13937;; Logic on condition register values.
13938
13939; This pattern matches things like
13940; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13941; (eq:SI (reg:CCFP 68) (const_int 0)))
13942; (const_int 1)))
13943; which are generated by the branch logic.
b54cf83a 13944; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
39a10a29 13945
423c1189 13946(define_insn "*cceq_ior_compare"
b54cf83a 13947 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13948 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
b54cf83a 13949 [(match_operator:SI 2
39a10a29
GK		 13950 "branch_positive_comparison_operator"
13951 [(match_operand 3
b54cf83a 13952 "cc_reg_operand" "y,y")
39a10a29 13953 (const_int 0)])
b54cf83a 13954 (match_operator:SI 4
39a10a29
GK		 13955 "branch_positive_comparison_operator"
13956 [(match_operand 5
b54cf83a 13957 "cc_reg_operand" "0,y")
39a10a29
GK		 13958 (const_int 0)])])
13959 (const_int 1)))]
24fab1d3 13960 ""
39a10a29 13961 "cr%q1 %E0,%j2,%j4"
b54cf83a 13962 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 13963
13964; Why is the constant -1 here, but 1 in the previous pattern?
13965; Because ~1 has all but the low bit set.
13966(define_insn ""
b54cf83a 13967 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
39a10a29 13968 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
b54cf83a 13969 [(not:SI (match_operator:SI 2
39a10a29
GK		 13970 "branch_positive_comparison_operator"
13971 [(match_operand 3
b54cf83a 13972 "cc_reg_operand" "y,y")
39a10a29
GK		 13973 (const_int 0)]))
13974 (match_operator:SI 4
13975 "branch_positive_comparison_operator"
13976 [(match_operand 5
b54cf83a 13977 "cc_reg_operand" "0,y")
39a10a29
GK		 13978 (const_int 0)])])
13979 (const_int -1)))]
13980 ""
13981 "cr%q1 %E0,%j2,%j4"
b54cf83a 13982 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29 13983
423c1189 13984(define_insn "*cceq_rev_compare"
b54cf83a 13985 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
6c873122 13986 (compare:CCEQ (match_operator:SI 1
39a10a29 13987 "branch_positive_comparison_operator"
6c873122 13988 [(match_operand 2
b54cf83a 13989 "cc_reg_operand" "0,y")
39a10a29
GK		 13990 (const_int 0)])
13991 (const_int 0)))]
423c1189 13992 ""
251b3667 13993 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
b54cf83a 13994 [(set_attr "type" "cr_logical,delayed_cr")])
39a10a29
GK		 13995
13996;; If we are comparing the result of two comparisons, this can be done
13997;; using creqv or crxor.
13998
13999(define_insn_and_split ""
14000 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14001 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14002 [(match_operand 2 "cc_reg_operand" "y")
14003 (const_int 0)])
14004 (match_operator 3 "branch_comparison_operator"
14005 [(match_operand 4 "cc_reg_operand" "y")
14006 (const_int 0)])))]
14007 ""
14008 "#"
14009 ""
14010 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14011 (match_dup 5)))]
14012 "
14013{
14014 int positive_1, positive_2;
14015
364849ee
DE		 14016 positive_1 = branch_positive_comparison_operator (operands[1],
14017 GET_MODE (operands[1]));
14018 positive_2 = branch_positive_comparison_operator (operands[3],
14019 GET_MODE (operands[3]));
39a10a29
GK		 14020
14021 if (! positive_1)
1c563bed 14022 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
0f4c242b
KH		 14023 GET_CODE (operands[1])),
14024 SImode,
14025 operands[2], const0_rtx);
39a10a29 14026 else if (GET_MODE (operands[1]) != SImode)
0f4c242b
KH		 14027 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14028 operands[2], const0_rtx);
39a10a29
GK		 14029
14030 if (! positive_2)
1c563bed 14031 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
0f4c242b
KH		 14032 GET_CODE (operands[3])),
14033 SImode,
14034 operands[4], const0_rtx);
39a10a29 14035 else if (GET_MODE (operands[3]) != SImode)
0f4c242b
KH		 14036 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14037 operands[4], const0_rtx);
39a10a29
GK		 14038
14039 if (positive_1 == positive_2)
251b3667
DE		 14040 {
14041 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14042 operands[5] = constm1_rtx;
14043 }
14044 else
14045 {
14046 operands[5] = const1_rtx;
14047 }
39a10a29 14048}")
1fd4e8c1
RK		 14049
14050;; Unconditional branch and return.
14051
14052(define_insn "jump"
14053 [(set (pc)
14054 (label_ref (match_operand 0 "" "")))]
14055 ""
b7ff3d82
DE		 14056 "b %l0"
14057 [(set_attr "type" "branch")])
1fd4e8c1
RK		 14058
14059(define_insn "return"
14060 [(return)]
14061 "direct_return ()"
324e52cc
TG		 14062 "{br|blr}"
14063 [(set_attr "type" "jmpreg")])
1fd4e8c1 14064
0ad91047 14065(define_expand "indirect_jump"
4ae234b0 14066 [(set (pc) (match_operand 0 "register_operand" ""))])
0ad91047 14067
4ae234b0
GK		 14068(define_insn "*indirect_jump<mode>"
14069 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14070 ""
b92b324d
DE		 14071 "@
14072 bctr
14073 {br|blr}"
324e52cc 14074 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14075
14076;; Table jump for switch statements:
14077(define_expand "tablejump"
e6ca2c17
DE		 14078 [(use (match_operand 0 "" ""))
14079 (use (label_ref (match_operand 1 "" "")))]
14080 ""
14081 "
14082{
14083 if (TARGET_32BIT)
14084 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14085 else
14086 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14087 DONE;
14088}")
14089
14090(define_expand "tablejumpsi"
1fd4e8c1
RK		 14091 [(set (match_dup 3)
14092 (plus:SI (match_operand:SI 0 "" "")
14093 (match_dup 2)))
14094 (parallel [(set (pc) (match_dup 3))
14095 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14096 "TARGET_32BIT"
1fd4e8c1
RK		 14097 "
14098{ operands[0] = force_reg (SImode, operands[0]);
c5c76735 14099 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
1fd4e8c1
RK		 14100 operands[3] = gen_reg_rtx (SImode);
14101}")
14102
e6ca2c17 14103(define_expand "tablejumpdi"
6ae08853 14104 [(set (match_dup 4)
e42ac3de 14105 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
9ebbca7d
GK		 14106 (set (match_dup 3)
14107 (plus:DI (match_dup 4)
e6ca2c17
DE		 14108 (match_dup 2)))
14109 (parallel [(set (pc) (match_dup 3))
14110 (use (label_ref (match_operand 1 "" "")))])]
0ad91047 14111 "TARGET_64BIT"
e6ca2c17 14112 "
9ebbca7d 14113{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
e6ca2c17 14114 operands[3] = gen_reg_rtx (DImode);
9ebbca7d 14115 operands[4] = gen_reg_rtx (DImode);
e6ca2c17
DE		 14116}")
14117
ce45ef46 14118(define_insn "*tablejump<mode>_internal1"
1fd4e8c1 14119 [(set (pc)
4ae234b0 14120 (match_operand:P 0 "register_operand" "c,*l"))
1fd4e8c1 14121 (use (label_ref (match_operand 1 "" "")))]
4ae234b0 14122 ""
c859cda6
DJ		 14123 "@
14124 bctr
14125 {br|blr}"
a6845123 14126 [(set_attr "type" "jmpreg")])
1fd4e8c1
RK		 14127
14128(define_insn "nop"
14129 [(const_int 0)]
14130 ""
ca7f5001 14131 "{cror 0,0,0|nop}")
1fd4e8c1 14132\f
7e69e155 14133;; Define the subtract-one-and-jump insns, starting with the template
c225ba7b
RK		 14134;; so loop.c knows what to generate.
14135
5527bf14
RH		 14136(define_expand "doloop_end"
14137 [(use (match_operand 0 "" "")) ; loop pseudo
14138 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14139 (use (match_operand 2 "" "")) ; max iterations
14140 (use (match_operand 3 "" "")) ; loop level
14141 (use (match_operand 4 "" ""))] ; label
0ad91047
DE		 14142 ""
14143 "
14144{
5527bf14
RH		 14145 /* Only use this on innermost loops. */
14146 if (INTVAL (operands[3]) > 1)
14147 FAIL;
683bdff7 14148 if (TARGET_64BIT)
5527bf14
RH		 14149 {
14150 if (GET_MODE (operands[0]) != DImode)
14151 FAIL;
14152 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14153 }
0ad91047 14154 else
5527bf14
RH		 14155 {
14156 if (GET_MODE (operands[0]) != SImode)
14157 FAIL;
14158 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14159 }
0ad91047
DE		 14160 DONE;
14161}")
14162
4ae234b0 14163(define_expand "ctr<mode>"
3cb999d8 14164 [(parallel [(set (pc)
4ae234b0 14165 (if_then_else (ne (match_operand:P 0 "register_operand" "")
3cb999d8
DE		 14166 (const_int 1))
14167 (label_ref (match_operand 1 "" ""))
14168 (pc)))
b6c9286a 14169 (set (match_dup 0)
4ae234b0 14170 (plus:P (match_dup 0)
b6c9286a 14171 (const_int -1)))
5f81043f 14172 (clobber (match_scratch:CC 2 ""))
4ae234b0
GK		 14173 (clobber (match_scratch:P 3 ""))])]
14174 ""
61c07d3c 14175 "")
c225ba7b 14176
1fd4e8c1
RK		 14177;; We need to be able to do this for any operand, including MEM, or we
14178;; will cause reload to blow up since we don't allow output reloads on
7e69e155 14179;; JUMP_INSNs.
0ad91047 14180;; For the length attribute to be calculated correctly, the
5f81043f
RK		 14181;; label MUST be operand 0.
14182
4ae234b0 14183(define_insn "*ctr<mode>_internal1"
0ad91047 14184 [(set (pc)
4ae234b0 14185 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14186 (const_int 1))
14187 (label_ref (match_operand 0 "" ""))
14188 (pc)))
4ae234b0
GK		 14189 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14190 (plus:P (match_dup 1)
0ad91047 14191 (const_int -1)))
43b68ce5 14192 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14193 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14194 ""
0ad91047
DE		 14195 "*
14196{
14197 if (which_alternative != 0)
14198 return \"#\";
856a6884 14199 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14200 return \"{bdn|bdnz} %l0\";
14201 else
f607bc57 14202 return \"bdz $+8\;b %l0\";
0ad91047
DE		 14203}"
14204 [(set_attr "type" "branch")
5a195cb5 14205 (set_attr "length" "*,12,16,16")])
0ad91047 14206
4ae234b0 14207(define_insn "*ctr<mode>_internal2"
0ad91047 14208 [(set (pc)
4ae234b0 14209 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14210 (const_int 1))
14211 (pc)
14212 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14213 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14214 (plus:P (match_dup 1)
0ad91047 14215 (const_int -1)))
43b68ce5 14216 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14217 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14218 ""
5f81043f
RK		 14219 "*
14220{
14221 if (which_alternative != 0)
14222 return \"#\";
856a6884 14223 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14224 return \"bdz %l0\";
14225 else
f607bc57 14226 return \"{bdn|bdnz} $+8\;b %l0\";
5f81043f
RK		 14227}"
14228 [(set_attr "type" "branch")
5a195cb5 14229 (set_attr "length" "*,12,16,16")])
5f81043f 14230
0ad91047
DE		 14231;; Similar but use EQ
14232
4ae234b0 14233(define_insn "*ctr<mode>_internal5"
5f81043f 14234 [(set (pc)
4ae234b0 14235 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
1fd4e8c1 14236 (const_int 1))
a6845123 14237 (label_ref (match_operand 0 "" ""))
1fd4e8c1 14238 (pc)))
4ae234b0
GK		 14239 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14240 (plus:P (match_dup 1)
0ad91047 14241 (const_int -1)))
43b68ce5 14242 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14243 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14244 ""
0ad91047
DE		 14245 "*
14246{
14247 if (which_alternative != 0)
14248 return \"#\";
856a6884 14249 else if (get_attr_length (insn) == 4)
0ad91047
DE		 14250 return \"bdz %l0\";
14251 else
f607bc57 14252 return \"{bdn|bdnz} $+8\;b %l0\";
0ad91047
DE		 14253}"
14254 [(set_attr "type" "branch")
5a195cb5 14255 (set_attr "length" "*,12,16,16")])
0ad91047 14256
4ae234b0 14257(define_insn "*ctr<mode>_internal6"
0ad91047 14258 [(set (pc)
4ae234b0 14259 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
0ad91047
DE		 14260 (const_int 1))
14261 (pc)
14262 (label_ref (match_operand 0 "" ""))))
4ae234b0
GK		 14263 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
14264 (plus:P (match_dup 1)
0ad91047 14265 (const_int -1)))
43b68ce5 14266 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
4ae234b0
GK		 14267 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
14268 ""
5f81043f
RK		 14269 "*
14270{
14271 if (which_alternative != 0)
14272 return \"#\";
856a6884 14273 else if (get_attr_length (insn) == 4)
5f81043f
RK		 14274 return \"{bdn|bdnz} %l0\";
14275 else
f607bc57 14276 return \"bdz $+8\;b %l0\";
5f81043f
RK		 14277}"
14278 [(set_attr "type" "branch")
5a195cb5 14279 (set_attr "length" "*,12,16,16")])
5f81043f 14280
0ad91047
DE		 14281;; Now the splitters if we could not allocate the CTR register
14282
1fd4e8c1
RK		 14283(define_split
14284 [(set (pc)
14285 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14286 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14287 (const_int 1)])
61c07d3c
DE		 14288 (match_operand 5 "" "")
14289 (match_operand 6 "" "")))
4ae234b0
GK		 14290 (set (match_operand:P 0 "gpc_reg_operand" "")
14291 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14292 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14293 (clobber (match_scratch:P 4 ""))]
14294 "reload_completed"
0ad91047 14295 [(parallel [(set (match_dup 3)
4ae234b0 14296 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14297 (const_int -1))
14298 (const_int 0)))
14299 (set (match_dup 0)
4ae234b0 14300 (plus:P (match_dup 1)
0ad91047 14301 (const_int -1)))])
61c07d3c
DE		 14302 (set (pc) (if_then_else (match_dup 7)
14303 (match_dup 5)
14304 (match_dup 6)))]
0ad91047 14305 "
0f4c242b
KH		 14306{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14307 operands[3], const0_rtx); }")
0ad91047
DE		 14308
14309(define_split
14310 [(set (pc)
14311 (if_then_else (match_operator 2 "comparison_operator"
4ae234b0 14312 [(match_operand:P 1 "gpc_reg_operand" "")
0ad91047 14313 (const_int 1)])
61c07d3c
DE		 14314 (match_operand 5 "" "")
14315 (match_operand 6 "" "")))
4ae234b0
GK		 14316 (set (match_operand:P 0 "nonimmediate_operand" "")
14317 (plus:P (match_dup 1) (const_int -1)))
0ad91047 14318 (clobber (match_scratch:CC 3 ""))
4ae234b0
GK		 14319 (clobber (match_scratch:P 4 ""))]
14320 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
0ad91047 14321 [(parallel [(set (match_dup 3)
4ae234b0 14322 (compare:CC (plus:P (match_dup 1)
0ad91047
DE		 14323 (const_int -1))
14324 (const_int 0)))
14325 (set (match_dup 4)
4ae234b0 14326 (plus:P (match_dup 1)
0ad91047
DE		 14327 (const_int -1)))])
14328 (set (match_dup 0)
14329 (match_dup 4))
61c07d3c
DE		 14330 (set (pc) (if_then_else (match_dup 7)
14331 (match_dup 5)
14332 (match_dup 6)))]
0ad91047 14333 "
0f4c242b
KH		 14334{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
14335 operands[3], const0_rtx); }")
e0cd0770
JC		 14336\f
14337(define_insn "trap"
14338 [(trap_if (const_int 1) (const_int 0))]
14339 ""
44cd321e
PS		 14340 "{t 31,0,0|trap}"
14341 [(set_attr "type" "trap")])
e0cd0770
JC		 14342
14343(define_expand "conditional_trap"
14344 [(trap_if (match_operator 0 "trap_comparison_operator"
14345 [(match_dup 2) (match_dup 3)])
14346 (match_operand 1 "const_int_operand" ""))]
14347 ""
14348 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14349 operands[2] = rs6000_compare_op0;
14350 operands[3] = rs6000_compare_op1;")
14351
14352(define_insn ""
14353 [(trap_if (match_operator 0 "trap_comparison_operator"
4ae234b0
GK		 14354 [(match_operand:GPR 1 "register_operand" "r")
14355 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
e0cd0770
JC		 14356 (const_int 0))]
14357 ""
44cd321e
PS		 14358 "{t|t<wd>}%V0%I2 %1,%2"
14359 [(set_attr "type" "trap")])
9ebbca7d
GK		 14360\f
14361;; Insns related to generating the function prologue and epilogue.
14362
14363(define_expand "prologue"
14364 [(use (const_int 0))]
14365 "TARGET_SCHED_PROLOG"
14366 "
14367{
14368 rs6000_emit_prologue ();
14369 DONE;
14370}")
14371
2c4a9cff
DE		 14372(define_insn "*movesi_from_cr_one"
14373 [(match_parallel 0 "mfcr_operation"
14374 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14375 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14376 (match_operand 3 "immediate_operand" "n")]
14377 UNSPEC_MOVESI_FROM_CR))])]
14378 "TARGET_MFCRF"
14379 "*
14380{
14381 int mask = 0;
14382 int i;
14383 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14384 {
14385 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14386 operands[4] = GEN_INT (mask);
14387 output_asm_insn (\"mfcr %1,%4\", operands);
14388 }
14389 return \"\";
14390}"
14391 [(set_attr "type" "mfcrf")])
14392
9ebbca7d
GK		 14393(define_insn "movesi_from_cr"
14394 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1de43f85
DE		 14395 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
14396 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
14397 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14398 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
615158e2 14399 UNSPEC_MOVESI_FROM_CR))]
9ebbca7d 14400 ""
309323c2 14401 "mfcr %0"
b54cf83a 14402 [(set_attr "type" "mfcr")])
9ebbca7d
GK		 14403
14404(define_insn "*stmw"
e033a023
DE		 14405 [(match_parallel 0 "stmw_operation"
14406 [(set (match_operand:SI 1 "memory_operand" "=m")
14407 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14408 "TARGET_MULTIPLE"
9c6fdb46
DE		 14409 "{stm|stmw} %2,%1"
14410 [(set_attr "type" "store_ux")])
6ae08853 14411
f78c3290
NF		 14412(define_insn "*save_gpregs_<mode>"
14413 [(match_parallel 0 "any_parallel_operand"
14414 [(clobber (reg:P 65))
14415 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14416 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14417 (set (match_operand:P 3 "memory_operand" "=m")
14418 (match_operand:P 4 "gpc_reg_operand" "r"))])]
14419 ""
14420 "bl %z1"
14421 [(set_attr "type" "branch")
14422 (set_attr "length" "4")])
14423
4ae234b0 14424(define_insn "*save_fpregs_<mode>"
85d346f1 14425 [(match_parallel 0 "any_parallel_operand"
e65a3857 14426 [(clobber (reg:P 65))
f78c3290
NF		 14427 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14428 (use (match_operand:P 2 "gpc_reg_operand" "r"))
14429 (set (match_operand:DF 3 "memory_operand" "=m")
14430 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
4ae234b0 14431 ""
e65a3857 14432 "bl %z1"
e033a023
DE		 14433 [(set_attr "type" "branch")
14434 (set_attr "length" "4")])
9ebbca7d
GK		 14435
14436; These are to explain that changes to the stack pointer should
14437; not be moved over stores to stack memory.
14438(define_insn "stack_tie"
14439 [(set (match_operand:BLK 0 "memory_operand" "+m")
615158e2 14440 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
9ebbca7d
GK		 14441 ""
14442 ""
14443 [(set_attr "length" "0")])
14444
14445
14446(define_expand "epilogue"
14447 [(use (const_int 0))]
14448 "TARGET_SCHED_PROLOG"
14449 "
14450{
14451 rs6000_emit_epilogue (FALSE);
14452 DONE;
14453}")
14454
14455; On some processors, doing the mtcrf one CC register at a time is
14456; faster (like on the 604e). On others, doing them all at once is
14457; faster; for instance, on the 601 and 750.
14458
14459(define_expand "movsi_to_cr_one"
e42ac3de
RS		 14460 [(set (match_operand:CC 0 "cc_reg_operand" "")
14461 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
615158e2 14462 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
35aba846
DE		 14463 ""
14464 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
9ebbca7d
GK		 14465
14466(define_insn "*movsi_to_cr"
35aba846
DE		 14467 [(match_parallel 0 "mtcrf_operation"
14468 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14469 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14470 (match_operand 3 "immediate_operand" "n")]
615158e2 14471 UNSPEC_MOVESI_TO_CR))])]
9ebbca7d 14472 ""
e35b9579
GK		 14473 "*
14474{
14475 int mask = 0;
14476 int i;
14477 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14478 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14479 operands[4] = GEN_INT (mask);
14480 return \"mtcrf %4,%2\";
309323c2 14481}"
b54cf83a 14482 [(set_attr "type" "mtcr")])
9ebbca7d 14483
b54cf83a 14484(define_insn "*mtcrfsi"
309323c2
DE		 14485 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14486 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
615158e2
JJ		 14487 (match_operand 2 "immediate_operand" "n")]
14488 UNSPEC_MOVESI_TO_CR))]
6ae08853 14489 "GET_CODE (operands[0]) == REG
309323c2
DE		 14490 && CR_REGNO_P (REGNO (operands[0]))
14491 && GET_CODE (operands[2]) == CONST_INT
14492 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14493 "mtcrf %R0,%1"
b54cf83a 14494 [(set_attr "type" "mtcr")])
9ebbca7d
GK		 14495
14496; The load-multiple instructions have similar properties.
14497; Note that "load_multiple" is a name known to the machine-independent
9c6fdb46 14498; code that actually corresponds to the PowerPC load-string.
9ebbca7d
GK		 14499
14500(define_insn "*lmw"
35aba846
DE		 14501 [(match_parallel 0 "lmw_operation"
14502 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14503 (match_operand:SI 2 "memory_operand" "m"))])]
14504 "TARGET_MULTIPLE"
9c6fdb46
DE		 14505 "{lm|lmw} %1,%2"
14506 [(set_attr "type" "load_ux")])
6ae08853 14507
4ae234b0 14508(define_insn "*return_internal_<mode>"
e35b9579 14509 [(return)
4ae234b0
GK		 14510 (use (match_operand:P 0 "register_operand" "lc"))]
14511 ""
cccf3bdc 14512 "b%T0"
9ebbca7d
GK		 14513 [(set_attr "type" "jmpreg")])
14514
14515; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
85d346f1 14516; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
9ebbca7d 14517
f78c3290
NF		 14518(define_insn "*restore_gpregs_<mode>"
14519 [(match_parallel 0 "any_parallel_operand"
14520 [(clobber (match_operand:P 1 "register_operand" "=l"))
14521 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14522 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14523 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14524 (match_operand:P 5 "memory_operand" "m"))])]
14525 ""
14526 "bl %z2"
14527 [(set_attr "type" "branch")
14528 (set_attr "length" "4")])
14529
14530(define_insn "*return_and_restore_gpregs_<mode>"
14531 [(match_parallel 0 "any_parallel_operand"
14532 [(return)
14533 (clobber (match_operand:P 1 "register_operand" "=l"))
14534 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14535 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14536 (set (match_operand:P 4 "gpc_reg_operand" "=r")
14537 (match_operand:P 5 "memory_operand" "m"))])]
14538 ""
14539 "b %z2"
14540 [(set_attr "type" "branch")
14541 (set_attr "length" "4")])
14542
4ae234b0 14543(define_insn "*return_and_restore_fpregs_<mode>"
85d346f1 14544 [(match_parallel 0 "any_parallel_operand"
e35b9579 14545 [(return)
f78c3290
NF		 14546 (clobber (match_operand:P 1 "register_operand" "=l"))
14547 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14548 (use (match_operand:P 3 "gpc_reg_operand" "r"))
14549 (set (match_operand:DF 4 "gpc_reg_operand" "=f")
14550 (match_operand:DF 5 "memory_operand" "m"))])]
4ae234b0 14551 ""
f78c3290
NF		 14552 "b %z2"
14553 [(set_attr "type" "branch")
14554 (set_attr "length" "4")])
9ebbca7d 14555
83720594
RH		 14556; This is used in compiling the unwind routines.
14557(define_expand "eh_return"
34dc173c 14558 [(use (match_operand 0 "general_operand" ""))]
9ebbca7d
GK		 14559 ""
14560 "
14561{
83720594 14562 if (TARGET_32BIT)
34dc173c 14563 emit_insn (gen_eh_set_lr_si (operands[0]));
9ebbca7d 14564 else
34dc173c 14565 emit_insn (gen_eh_set_lr_di (operands[0]));
9ebbca7d
GK		 14566 DONE;
14567}")
14568
83720594 14569; We can't expand this before we know where the link register is stored.
4ae234b0
GK		 14570(define_insn "eh_set_lr_<mode>"
14571 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
615158e2 14572 UNSPECV_EH_RR)
4ae234b0
GK		 14573 (clobber (match_scratch:P 1 "=&b"))]
14574 ""
83720594 14575 "#")
9ebbca7d
GK		 14576
14577(define_split
615158e2 14578 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
83720594
RH		 14579 (clobber (match_scratch 1 ""))]
14580 "reload_completed"
14581 [(const_int 0)]
9ebbca7d
GK		 14582 "
14583{
d1d0c603 14584 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
83720594
RH		 14585 DONE;
14586}")
0ac081f6 14587
01a2ccd0 14588(define_insn "prefetch"
3256a76e 14589 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
6041bf2f
DE		 14590 (match_operand:SI 1 "const_int_operand" "n")
14591 (match_operand:SI 2 "const_int_operand" "n"))]
01a2ccd0 14592 "TARGET_POWERPC"
6041bf2f
DE		 14593 "*
14594{
01a2ccd0
DE		 14595 if (GET_CODE (operands[0]) == REG)
14596 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14597 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
6041bf2f
DE		 14598}"
14599 [(set_attr "type" "load")])
915167f5 14600\f
a3170dc6 14601
f565b0a1 14602(include "sync.md")
10ed84db 14603(include "altivec.md")
a3170dc6 14604(include "spe.md")
7393f7f8 14605(include "dfp.md")
96038623 14606(include "paired.md")
Mirror of https://gcc.gnu.org/git/gcc.git