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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
34792e82 | 2 | ;; Copyright (C) 1990, 91-98, 1999 Free Software Foundation, Inc. |
996a5f59 | 3 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 RK |
4 | |
5 | ;; This file is part of GNU CC. | |
6 | ||
7 | ;; GNU CC is free software; you can redistribute it and/or modify | |
8 | ;; it under the terms of the GNU General Public License as published by | |
9 | ;; the Free Software Foundation; either version 2, or (at your option) | |
10 | ;; any later version. | |
11 | ||
12 | ;; GNU CC is distributed in the hope that it will be useful, | |
13 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ;; GNU General Public License for more details. | |
16 | ||
17 | ;; You should have received a copy of the GNU General Public License | |
18 | ;; along with GNU CC; see the file COPYING. If not, write to | |
3f63df56 RK |
19 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | ;; Boston, MA 02111-1307, USA. | |
1fd4e8c1 RK |
21 | |
22 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
23 | \f | |
24 | ;; Define an insn type attribute. This is used in function unit delay | |
25 | ;; computations. | |
b7ff3d82 | 26 | (define_attr "type" "integer,load,store,fpload,fpstore,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg" |
1fd4e8c1 RK |
27 | (const_string "integer")) |
28 | ||
b19003d8 RK |
29 | ;; Length (in bytes). |
30 | (define_attr "length" "" | |
31 | (if_then_else (eq_attr "type" "branch") | |
32 | (if_then_else (and (ge (minus (pc) (match_dup 0)) | |
33 | (const_int -32768)) | |
34 | (lt (minus (pc) (match_dup 0)) | |
35 | (const_int 32767))) | |
36 | (const_int 8) | |
37 | (const_int 12)) | |
38 | (const_int 4))) | |
39 | ||
cfb557c4 RK |
40 | ;; Processor type -- this attribute must exactly match the processor_type |
41 | ;; enumeration in rs6000.h. | |
42 | ||
bef84347 | 43 | (define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750" |
cfb557c4 RK |
44 | (const (symbol_ref "rs6000_cpu_attr"))) |
45 | ||
46 | ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY | |
47 | ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) | |
48 | ||
b7ff3d82 | 49 | ; Load/Store Unit -- pure PowerPC only |
51b8fc2c | 50 | ; (POWER and 601 use Integer Unit) |
cfb557c4 RK |
51 | (define_function_unit "lsu" 1 0 |
52 | (and (eq_attr "type" "load") | |
bef84347 | 53 | (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b6c9286a | 54 | 2 1) |
cfb557c4 RK |
55 | |
56 | (define_function_unit "lsu" 1 0 | |
b7ff3d82 | 57 | (and (eq_attr "type" "store,fpstore") |
bef84347 | 58 | (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b7ff3d82 | 59 | 1 1) |
b6c9286a MM |
60 | |
61 | (define_function_unit "lsu" 1 0 | |
62 | (and (eq_attr "type" "fpload") | |
bef84347 | 63 | (eq_attr "cpu" "mpccore,ppc603,ppc750")) |
b6c9286a | 64 | 2 1) |
cfb557c4 | 65 | |
b7ff3d82 DE |
66 | (define_function_unit "lsu" 1 0 |
67 | (and (eq_attr "type" "fpload") | |
cac8ce95 | 68 | (eq_attr "cpu" "ppc604,ppc604e,ppc620")) |
b7ff3d82 DE |
69 | 3 1) |
70 | ||
cfb557c4 RK |
71 | (define_function_unit "iu" 1 0 |
72 | (and (eq_attr "type" "load") | |
b7ff3d82 | 73 | (eq_attr "cpu" "rios1,ppc403,ppc601")) |
b6c9286a | 74 | 2 1) |
cfb557c4 RK |
75 | |
76 | (define_function_unit "iu" 1 0 | |
b7ff3d82 DE |
77 | (and (eq_attr "type" "store,fpstore") |
78 | (eq_attr "cpu" "rios1,ppc403,ppc601")) | |
79 | 1 1) | |
80 | ||
81 | (define_function_unit "fpu" 1 0 | |
82 | (and (eq_attr "type" "fpstore") | |
3624a679 | 83 | (eq_attr "cpu" "rios1,ppc601")) |
b7ff3d82 | 84 | 0 1) |
cfb557c4 | 85 | |
49a0b204 | 86 | (define_function_unit "iu" 1 0 |
b7ff3d82 | 87 | (and (eq_attr "type" "fpload") |
b6c9286a | 88 | (eq_attr "cpu" "rios1")) |
b7ff3d82 DE |
89 | 2 1) |
90 | ||
91 | (define_function_unit "iu" 1 0 | |
92 | (and (eq_attr "type" "fpload") | |
93 | (eq_attr "cpu" "ppc601")) | |
94 | 3 1) | |
95 | ||
96 | (define_function_unit "iu2" 2 0 | |
97 | (and (eq_attr "type" "load,fpload") | |
98 | (eq_attr "cpu" "rios2")) | |
99 | 2 1) | |
100 | ||
101 | (define_function_unit "iu2" 2 0 | |
102 | (and (eq_attr "type" "store,fpstore") | |
103 | (eq_attr "cpu" "rios2")) | |
104 | 1 1) | |
105 | ||
106 | ; Integer Unit (RIOS1, PPC601, PPC603) | |
107 | (define_function_unit "iu" 1 0 | |
108 | (and (eq_attr "type" "integer") | |
109 | (eq_attr "cpu" "rios1,mpccore,ppc403,ppc601,ppc603")) | |
110 | 1 1) | |
49a0b204 | 111 | |
da0ae67f MM |
112 | (define_function_unit "iu" 1 0 |
113 | (and (eq_attr "type" "imul") | |
114 | (eq_attr "cpu" "ppc403")) | |
115 | 4 4) | |
116 | ||
cfb557c4 RK |
117 | (define_function_unit "iu" 1 0 |
118 | (and (eq_attr "type" "imul") | |
b7ff3d82 | 119 | (eq_attr "cpu" "rios1,ppc601,ppc603")) |
51b8fc2c | 120 | 5 5) |
cfb557c4 RK |
121 | |
122 | (define_function_unit "iu" 1 0 | |
123 | (and (eq_attr "type" "idiv") | |
ca7f5001 | 124 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 125 | 19 19) |
cfb557c4 RK |
126 | |
127 | (define_function_unit "iu" 1 0 | |
128 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
129 | (eq_attr "cpu" "ppc403")) |
130 | 33 33) | |
51b8fc2c | 131 | |
da0ae67f MM |
132 | (define_function_unit "iu" 1 0 |
133 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
134 | (eq_attr "cpu" "ppc601")) |
135 | 36 36) | |
da0ae67f | 136 | |
51b8fc2c RK |
137 | (define_function_unit "iu" 1 0 |
138 | (and (eq_attr "type" "idiv") | |
b7ff3d82 | 139 | (eq_attr "cpu" "ppc603")) |
51b8fc2c RK |
140 | 37 36) |
141 | ||
142 | ; RIOS2 has two integer units: a primary one which can perform all | |
143 | ; operations and a secondary one which is fed in lock step with the first | |
b6c9286a MM |
144 | ; and can perform "simple" integer operations. |
145 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
146 | ; for the complex insns. | |
51b8fc2c RK |
147 | (define_function_unit "iu2" 2 0 |
148 | (and (eq_attr "type" "integer") | |
149 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 150 | 1 1) |
b6c9286a MM |
151 | |
152 | (define_function_unit "iu2" 2 0 | |
153 | (and (eq_attr "type" "imul") | |
154 | (eq_attr "cpu" "rios2")) | |
155 | 2 2) | |
156 | ||
157 | (define_function_unit "iu2" 2 0 | |
158 | (and (eq_attr "type" "idiv") | |
159 | (eq_attr "cpu" "rios2")) | |
160 | 13 13) | |
51b8fc2c RK |
161 | |
162 | (define_function_unit "imuldiv" 1 0 | |
163 | (and (eq_attr "type" "imul") | |
164 | (eq_attr "cpu" "rios2")) | |
b6c9286a MM |
165 | 2 2) |
166 | ||
51b8fc2c RK |
167 | (define_function_unit "imuldiv" 1 0 |
168 | (and (eq_attr "type" "idiv") | |
169 | (eq_attr "cpu" "rios2")) | |
b6c9286a | 170 | 13 13) |
51b8fc2c | 171 | |
cf27b467 MM |
172 | ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions |
173 | ; Divide latency varies greatly from 2-11, use 6 as average | |
174 | (define_function_unit "imuldiv" 1 0 | |
175 | (and (eq_attr "type" "imul") | |
176 | (eq_attr "cpu" "mpccore")) | |
177 | 2 1) | |
178 | ||
179 | (define_function_unit "imuldiv" 1 0 | |
180 | (and (eq_attr "type" "idiv") | |
181 | (eq_attr "cpu" "mpccore")) | |
182 | 6 6) | |
183 | ||
cac8ce95 | 184 | ; PPC604{,e} has two units that perform integer operations |
b6c9286a MM |
185 | ; and one unit for divide/multiply operations (and move |
186 | ; from/to spr). | |
187 | (define_function_unit "iu2" 2 0 | |
51b8fc2c | 188 | (and (eq_attr "type" "integer") |
cac8ce95 | 189 | (eq_attr "cpu" "ppc604,ppc604e,ppc620")) |
b7ff3d82 | 190 | 1 1) |
51b8fc2c RK |
191 | |
192 | (define_function_unit "imuldiv" 1 0 | |
193 | (and (eq_attr "type" "imul") | |
194 | (eq_attr "cpu" "ppc604,ppc620")) | |
b7ff3d82 | 195 | 4 2) |
51b8fc2c | 196 | |
cac8ce95 DE |
197 | (define_function_unit "imuldiv" 1 0 |
198 | (and (eq_attr "type" "imul") | |
199 | (eq_attr "cpu" "ppc604e")) | |
200 | 2 1) | |
201 | ||
51b8fc2c RK |
202 | (define_function_unit "imuldiv" 1 0 |
203 | (and (eq_attr "type" "idiv") | |
cac8ce95 | 204 | (eq_attr "cpu" "ppc604,ppc604e,ppc620")) |
b7ff3d82 | 205 | 20 19) |
cfb557c4 | 206 | |
bef84347 VM |
207 | ; PPC750 has two integer units: a primary one which can perform all |
208 | ; operations and a secondary one which is fed in lock step with the first | |
209 | ; and can perform "simple" integer operations. | |
210 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
211 | ; for the complex insns. | |
212 | (define_function_unit "iu2" 2 0 | |
213 | (and (eq_attr "type" "integer") | |
214 | (eq_attr "cpu" "ppc750")) | |
215 | 1 1) | |
216 | ||
217 | (define_function_unit "iu2" 2 0 | |
218 | (and (eq_attr "type" "imul") | |
219 | (eq_attr "cpu" "ppc750")) | |
220 | 4 2) | |
221 | ||
222 | (define_function_unit "imuldiv" 1 0 | |
223 | (and (eq_attr "type" "imul") | |
224 | (eq_attr "cpu" "ppc750")) | |
225 | 4 2) | |
226 | ||
227 | (define_function_unit "imuldiv" 1 0 | |
228 | (and (eq_attr "type" "idiv") | |
229 | (eq_attr "cpu" "ppc750")) | |
230 | 19 19) | |
231 | ||
b6c9286a | 232 | ; compare is done on integer unit, but feeds insns which |
acc5239d | 233 | ; execute on the branch unit. |
b6c9286a MM |
234 | (define_function_unit "iu" 1 0 |
235 | (and (eq_attr "type" "compare") | |
b7ff3d82 DE |
236 | (eq_attr "cpu" "rios1")) |
237 | 4 1) | |
238 | ||
239 | (define_function_unit "iu" 1 0 | |
240 | (and (eq_attr "type" "delayed_compare") | |
241 | (eq_attr "cpu" "rios1")) | |
242 | 5 1) | |
243 | ||
244 | (define_function_unit "iu" 1 0 | |
245 | (and (eq_attr "type" "compare,delayed_compare") | |
bef84347 | 246 | (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b7ff3d82 | 247 | 3 1) |
b6c9286a MM |
248 | |
249 | (define_function_unit "iu2" 2 0 | |
b7ff3d82 | 250 | (and (eq_attr "type" "compare,delayed_compare") |
b6c9286a | 251 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 252 | 3 1) |
b6c9286a | 253 | |
b6c9286a | 254 | (define_function_unit "iu2" 2 0 |
b7ff3d82 | 255 | (and (eq_attr "type" "compare,delayed_compare") |
bef84347 | 256 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc750")) |
b6c9286a | 257 | 1 1) |
cfb557c4 | 258 | |
b6c9286a MM |
259 | ; fp compare uses fp unit |
260 | (define_function_unit "fpu" 1 0 | |
cfb557c4 | 261 | (and (eq_attr "type" "fpcompare") |
b6c9286a | 262 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 263 | 9 1) |
cfb557c4 | 264 | |
b6c9286a MM |
265 | ; rios1 and rios2 have different fpcompare delays |
266 | (define_function_unit "fpu2" 2 0 | |
cfb557c4 | 267 | (and (eq_attr "type" "fpcompare") |
b6c9286a MM |
268 | (eq_attr "cpu" "rios2")) |
269 | 5 1) | |
270 | ||
271 | ; on ppc601 and ppc603, fpcompare takes also 2 cycles from | |
272 | ; the integer unit | |
273 | ; here we do not define delays, just occupy the unit. The dependencies | |
b7ff3d82 | 274 | ; will be assigned by the fpcompare definition in the fpu. |
b6c9286a MM |
275 | (define_function_unit "iu" 1 0 |
276 | (and (eq_attr "type" "fpcompare") | |
b7ff3d82 | 277 | (eq_attr "cpu" "ppc601,ppc603")) |
b6c9286a MM |
278 | 0 2) |
279 | ||
280 | ; fp compare uses fp unit | |
281 | (define_function_unit "fpu" 1 0 | |
282 | (and (eq_attr "type" "fpcompare") | |
bef84347 | 283 | (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b6c9286a | 284 | 5 1) |
cfb557c4 | 285 | |
cf27b467 MM |
286 | (define_function_unit "fpu" 1 0 |
287 | (and (eq_attr "type" "fpcompare") | |
288 | (eq_attr "cpu" "mpccore")) | |
289 | 1 1) | |
290 | ||
cfb557c4 | 291 | (define_function_unit "bpu" 1 0 |
324e52cc | 292 | (and (eq_attr "type" "mtjmpr") |
2661cdd9 | 293 | (eq_attr "cpu" "rios1,rios2")) |
b7ff3d82 | 294 | 5 1) |
cfb557c4 RK |
295 | |
296 | (define_function_unit "bpu" 1 0 | |
324e52cc | 297 | (and (eq_attr "type" "mtjmpr") |
bef84347 | 298 | (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b7ff3d82 | 299 | 4 1) |
cfb557c4 | 300 | |
b6c9286a MM |
301 | ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines. |
302 | (define_function_unit "bpu" 1 0 | |
303 | (eq_attr "type" "jmpreg") | |
b7ff3d82 | 304 | 1 1) |
b6c9286a MM |
305 | |
306 | (define_function_unit "bpu" 1 0 | |
307 | (eq_attr "type" "branch") | |
b7ff3d82 | 308 | 1 1) |
b6c9286a | 309 | |
cf27b467 | 310 | ; Floating Point Unit |
cfb557c4 | 311 | (define_function_unit "fpu" 1 0 |
51b8fc2c | 312 | (and (eq_attr "type" "fp,dmul") |
2661cdd9 | 313 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 314 | 2 1) |
cfb557c4 | 315 | |
cf27b467 MM |
316 | (define_function_unit "fpu" 1 0 |
317 | (and (eq_attr "type" "fp") | |
318 | (eq_attr "cpu" "mpccore")) | |
319 | 4 4) | |
320 | ||
cfb557c4 RK |
321 | (define_function_unit "fpu" 1 0 |
322 | (and (eq_attr "type" "fp") | |
51b8fc2c | 323 | (eq_attr "cpu" "ppc601")) |
b7ff3d82 | 324 | 4 1) |
cfb557c4 | 325 | |
51b8fc2c RK |
326 | (define_function_unit "fpu" 1 0 |
327 | (and (eq_attr "type" "fp") | |
bef84347 | 328 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b6c9286a | 329 | 3 1) |
51b8fc2c | 330 | |
cf27b467 MM |
331 | (define_function_unit "fpu" 1 0 |
332 | (and (eq_attr "type" "dmul") | |
333 | (eq_attr "cpu" "mpccore")) | |
334 | 5 5) | |
335 | ||
cfb557c4 RK |
336 | (define_function_unit "fpu" 1 0 |
337 | (and (eq_attr "type" "dmul") | |
51b8fc2c | 338 | (eq_attr "cpu" "ppc601")) |
b6c9286a | 339 | 5 2) |
cfb557c4 | 340 | |
b6c9286a | 341 | ; is this true? |
cfb557c4 RK |
342 | (define_function_unit "fpu" 1 0 |
343 | (and (eq_attr "type" "dmul") | |
bef84347 | 344 | (eq_attr "cpu" "ppc603,ppc750")) |
51b8fc2c | 345 | 4 2) |
cfb557c4 RK |
346 | |
347 | (define_function_unit "fpu" 1 0 | |
51b8fc2c | 348 | (and (eq_attr "type" "dmul") |
cac8ce95 | 349 | (eq_attr "cpu" "ppc604,ppc604e,ppc620")) |
b6c9286a | 350 | 3 1) |
51b8fc2c RK |
351 | |
352 | (define_function_unit "fpu" 1 0 | |
353 | (and (eq_attr "type" "sdiv,ddiv") | |
2661cdd9 | 354 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 355 | 19 19) |
cfb557c4 RK |
356 | |
357 | (define_function_unit "fpu" 1 0 | |
358 | (and (eq_attr "type" "sdiv") | |
51b8fc2c RK |
359 | (eq_attr "cpu" "ppc601")) |
360 | 17 17) | |
361 | ||
cf27b467 MM |
362 | (define_function_unit "fpu" 1 0 |
363 | (and (eq_attr "type" "sdiv") | |
364 | (eq_attr "cpu" "mpccore")) | |
365 | 10 10) | |
366 | ||
51b8fc2c RK |
367 | (define_function_unit "fpu" 1 0 |
368 | (and (eq_attr "type" "sdiv") | |
cac8ce95 | 369 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620")) |
51b8fc2c | 370 | 18 18) |
cfb557c4 | 371 | |
cf27b467 MM |
372 | (define_function_unit "fpu" 1 0 |
373 | (and (eq_attr "type" "ddiv") | |
374 | (eq_attr "cpu" "mpccore")) | |
375 | 17 17) | |
376 | ||
cfb557c4 RK |
377 | (define_function_unit "fpu" 1 0 |
378 | (and (eq_attr "type" "ddiv") | |
bef84347 | 379 | (eq_attr "cpu" "ppc601,ppc604,ppc604e,ppc620,ppc750")) |
51b8fc2c | 380 | 31 31) |
cfb557c4 RK |
381 | |
382 | (define_function_unit "fpu" 1 0 | |
383 | (and (eq_attr "type" "ddiv") | |
b7ff3d82 | 384 | (eq_attr "cpu" "ppc603")) |
51b8fc2c | 385 | 33 33) |
cfb557c4 RK |
386 | |
387 | (define_function_unit "fpu" 1 0 | |
388 | (and (eq_attr "type" "ssqrt") | |
a473029f | 389 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 390 | 31 31) |
cfb557c4 RK |
391 | |
392 | (define_function_unit "fpu" 1 0 | |
393 | (and (eq_attr "type" "dsqrt") | |
a473029f | 394 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 395 | 31 31) |
b73d04f2 | 396 | |
51b8fc2c | 397 | ; RIOS2 has two symmetric FPUs. |
cfb557c4 RK |
398 | (define_function_unit "fpu2" 2 0 |
399 | (and (eq_attr "type" "fp") | |
4652f1d4 | 400 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 401 | 2 1) |
cfb557c4 RK |
402 | |
403 | (define_function_unit "fpu2" 2 0 | |
404 | (and (eq_attr "type" "dmul") | |
405 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 406 | 2 1) |
cfb557c4 RK |
407 | |
408 | (define_function_unit "fpu2" 2 0 | |
51b8fc2c | 409 | (and (eq_attr "type" "sdiv,ddiv") |
cfb557c4 | 410 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 411 | 17 17) |
ca7f5001 RK |
412 | |
413 | (define_function_unit "fpu2" 2 0 | |
51b8fc2c | 414 | (and (eq_attr "type" "ssqrt,dsqrt") |
ca7f5001 | 415 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 416 | 26 26) |
b6c9286a | 417 | |
1fd4e8c1 RK |
418 | \f |
419 | ;; Start with fixed-point load and store insns. Here we put only the more | |
420 | ;; complex forms. Basic data transfer is done later. | |
421 | ||
51b8fc2c RK |
422 | (define_expand "zero_extendqidi2" |
423 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
424 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
425 | "TARGET_POWERPC64" | |
426 | "") | |
427 | ||
428 | (define_insn "" | |
429 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
430 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
431 | "TARGET_POWERPC64" | |
432 | "@ | |
433 | lbz%U1%X1 %0,%1 | |
4371f8af | 434 | rldicl %0,%1,0,56" |
51b8fc2c RK |
435 | [(set_attr "type" "load,*")]) |
436 | ||
437 | (define_insn "" | |
29ae5b89 JL |
438 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
439 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
815cdc52 MM |
440 | (const_int 0))) |
441 | (clobber (match_scratch:DI 2 "=r"))] | |
29ae5b89 JL |
442 | "TARGET_POWERPC64" |
443 | "rldicl. %2,%1,0,56" | |
444 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
445 | |
446 | (define_insn "" | |
29ae5b89 JL |
447 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
448 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 449 | (const_int 0))) |
29ae5b89 | 450 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c | 451 | (zero_extend:DI (match_dup 1)))] |
58e09803 | 452 | "TARGET_POWERPC64" |
29ae5b89 JL |
453 | "rldicl. %0,%1,0,56" |
454 | [(set_attr "type" "compare")]) | |
51b8fc2c | 455 | |
2bee0449 RK |
456 | (define_insn "extendqidi2" |
457 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
458 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 459 | "TARGET_POWERPC64" |
2bee0449 | 460 | "extsb %0,%1") |
51b8fc2c RK |
461 | |
462 | (define_insn "" | |
29ae5b89 JL |
463 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
464 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 465 | (const_int 0))) |
29ae5b89 | 466 | (clobber (match_scratch:DI 2 "=r"))] |
51b8fc2c | 467 | "TARGET_POWERPC64" |
29ae5b89 JL |
468 | "extsb. %2,%1" |
469 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
470 | |
471 | (define_insn "" | |
29ae5b89 JL |
472 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
473 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 474 | (const_int 0))) |
29ae5b89 | 475 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
476 | (sign_extend:DI (match_dup 1)))] |
477 | "TARGET_POWERPC64" | |
29ae5b89 JL |
478 | "extsb. %0,%1" |
479 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
480 | |
481 | (define_expand "zero_extendhidi2" | |
482 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
483 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
484 | "TARGET_POWERPC64" | |
485 | "") | |
486 | ||
487 | (define_insn "" | |
488 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
489 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
490 | "TARGET_POWERPC64" | |
491 | "@ | |
492 | lhz%U1%X1 %0,%1 | |
4371f8af | 493 | rldicl %0,%1,0,48" |
51b8fc2c RK |
494 | [(set_attr "type" "load,*")]) |
495 | ||
496 | (define_insn "" | |
29ae5b89 JL |
497 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
498 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 499 | (const_int 0))) |
29ae5b89 | 500 | (clobber (match_scratch:DI 2 "=r"))] |
51b8fc2c | 501 | "TARGET_POWERPC64" |
29ae5b89 JL |
502 | "rldicl. %2,%1,0,48" |
503 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
504 | |
505 | (define_insn "" | |
29ae5b89 JL |
506 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
507 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 508 | (const_int 0))) |
29ae5b89 | 509 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
510 | (zero_extend:DI (match_dup 1)))] |
511 | "TARGET_POWERPC64" | |
29ae5b89 JL |
512 | "rldicl. %0,%1,0,48" |
513 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
514 | |
515 | (define_expand "extendhidi2" | |
516 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
517 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
518 | "TARGET_POWERPC64" | |
519 | "") | |
520 | ||
521 | (define_insn "" | |
522 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
523 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
524 | "TARGET_POWERPC64" | |
525 | "@ | |
526 | lha%U1%X1 %0,%1 | |
527 | extsh %0,%1" | |
528 | [(set_attr "type" "load,*")]) | |
529 | ||
530 | (define_insn "" | |
29ae5b89 JL |
531 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
532 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 533 | (const_int 0))) |
29ae5b89 | 534 | (clobber (match_scratch:DI 2 "=r"))] |
51b8fc2c | 535 | "TARGET_POWERPC64" |
29ae5b89 JL |
536 | "extsh. %2,%1" |
537 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
538 | |
539 | (define_insn "" | |
29ae5b89 JL |
540 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
541 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 542 | (const_int 0))) |
29ae5b89 | 543 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
544 | (sign_extend:DI (match_dup 1)))] |
545 | "TARGET_POWERPC64" | |
29ae5b89 JL |
546 | "extsh. %0,%1" |
547 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
548 | |
549 | (define_expand "zero_extendsidi2" | |
550 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
551 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
552 | "TARGET_POWERPC64" | |
553 | "") | |
554 | ||
555 | (define_insn "" | |
556 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
557 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
558 | "TARGET_POWERPC64" | |
559 | "@ | |
560 | lwz%U1%X1 %0,%1 | |
561 | rldicl %0,%1,0,32" | |
562 | [(set_attr "type" "load,*")]) | |
563 | ||
564 | (define_insn "" | |
29ae5b89 JL |
565 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
566 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 567 | (const_int 0))) |
29ae5b89 | 568 | (clobber (match_scratch:DI 2 "=r"))] |
51b8fc2c | 569 | "TARGET_POWERPC64" |
29ae5b89 JL |
570 | "rldicl. %2,%1,0,32" |
571 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
572 | |
573 | (define_insn "" | |
29ae5b89 JL |
574 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
575 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 576 | (const_int 0))) |
29ae5b89 | 577 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
578 | (zero_extend:DI (match_dup 1)))] |
579 | "TARGET_POWERPC64" | |
29ae5b89 JL |
580 | "rldicl. %0,%1,0,32" |
581 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
582 | |
583 | (define_expand "extendsidi2" | |
584 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
585 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
586 | "TARGET_POWERPC64" | |
587 | "") | |
588 | ||
589 | (define_insn "" | |
590 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 591 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
592 | "TARGET_POWERPC64" |
593 | "@ | |
594 | lwa%U1%X1 %0,%1 | |
595 | extsw %0,%1" | |
596 | [(set_attr "type" "load,*")]) | |
597 | ||
598 | (define_insn "" | |
29ae5b89 JL |
599 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
600 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 601 | (const_int 0))) |
29ae5b89 | 602 | (clobber (match_scratch:DI 2 "=r"))] |
51b8fc2c | 603 | "TARGET_POWERPC64" |
29ae5b89 JL |
604 | "extsw. %2,%1" |
605 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
606 | |
607 | (define_insn "" | |
29ae5b89 JL |
608 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
609 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 610 | (const_int 0))) |
29ae5b89 | 611 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
612 | (sign_extend:DI (match_dup 1)))] |
613 | "TARGET_POWERPC64" | |
29ae5b89 JL |
614 | "extsw. %0,%1" |
615 | [(set_attr "type" "compare")]) | |
51b8fc2c | 616 | |
1fd4e8c1 | 617 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
618 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
619 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
620 | "" |
621 | "") | |
622 | ||
623 | (define_insn "" | |
cd2b37d9 | 624 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
625 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
626 | "" | |
627 | "@ | |
628 | lbz%U1%X1 %0,%1 | |
005a35b9 | 629 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
630 | [(set_attr "type" "load,*")]) |
631 | ||
632 | (define_insn "" | |
29ae5b89 JL |
633 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
634 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 635 | (const_int 0))) |
29ae5b89 | 636 | (clobber (match_scratch:SI 2 "=r"))] |
1fd4e8c1 | 637 | "" |
29ae5b89 JL |
638 | "{andil.|andi.} %2,%1,0xff" |
639 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
640 | |
641 | (define_insn "" | |
29ae5b89 JL |
642 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
643 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 644 | (const_int 0))) |
29ae5b89 | 645 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
646 | (zero_extend:SI (match_dup 1)))] |
647 | "" | |
29ae5b89 JL |
648 | "{andil.|andi.} %0,%1,0xff" |
649 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 650 | |
51b8fc2c RK |
651 | (define_expand "extendqisi2" |
652 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
653 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
654 | "" | |
655 | " | |
656 | { | |
657 | if (TARGET_POWERPC) | |
658 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
659 | else if (TARGET_POWER) | |
660 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
661 | else | |
662 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
663 | DONE; | |
664 | }") | |
665 | ||
666 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
667 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
668 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 669 | "TARGET_POWERPC" |
2bee0449 | 670 | "extsb %0,%1") |
51b8fc2c RK |
671 | |
672 | (define_insn "" | |
29ae5b89 JL |
673 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
674 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 675 | (const_int 0))) |
29ae5b89 | 676 | (clobber (match_scratch:SI 2 "=r"))] |
51b8fc2c | 677 | "TARGET_POWERPC" |
29ae5b89 JL |
678 | "extsb. %2,%1" |
679 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
680 | |
681 | (define_insn "" | |
29ae5b89 JL |
682 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
683 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 684 | (const_int 0))) |
29ae5b89 | 685 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
686 | (sign_extend:SI (match_dup 1)))] |
687 | "TARGET_POWERPC" | |
29ae5b89 JL |
688 | "extsb. %0,%1" |
689 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
690 | |
691 | (define_expand "extendqisi2_power" | |
692 | [(parallel [(set (match_dup 2) | |
693 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
694 | (const_int 24))) | |
695 | (clobber (scratch:SI))]) | |
696 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
697 | (ashiftrt:SI (match_dup 2) | |
698 | (const_int 24))) | |
699 | (clobber (scratch:SI))])] | |
700 | "TARGET_POWER" | |
701 | " | |
702 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
703 | operands[2] = gen_reg_rtx (SImode); }") | |
704 | ||
705 | (define_expand "extendqisi2_no_power" | |
706 | [(set (match_dup 2) | |
707 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
708 | (const_int 24))) | |
709 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
710 | (ashiftrt:SI (match_dup 2) | |
711 | (const_int 24)))] | |
712 | "! TARGET_POWER && ! TARGET_POWERPC" | |
713 | " | |
714 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
715 | operands[2] = gen_reg_rtx (SImode); }") | |
716 | ||
1fd4e8c1 | 717 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
718 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
719 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
720 | "" |
721 | "") | |
722 | ||
723 | (define_insn "" | |
cd2b37d9 | 724 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
725 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
726 | "" | |
727 | "@ | |
728 | lbz%U1%X1 %0,%1 | |
005a35b9 | 729 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
730 | [(set_attr "type" "load,*")]) |
731 | ||
732 | (define_insn "" | |
29ae5b89 JL |
733 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
734 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 735 | (const_int 0))) |
29ae5b89 | 736 | (clobber (match_scratch:HI 2 "=r"))] |
51b8fc2c | 737 | "" |
29ae5b89 JL |
738 | "{andil.|andi.} %2,%1,0xff" |
739 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 740 | |
51b8fc2c | 741 | (define_insn "" |
29ae5b89 JL |
742 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
743 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 744 | (const_int 0))) |
29ae5b89 | 745 | (set (match_operand:HI 0 "gpc_reg_operand" "=r") |
815cdc52 MM |
746 | (zero_extend:HI (match_dup 1)))] |
747 | "" | |
29ae5b89 JL |
748 | "{andil.|andi.} %0,%1,0xff" |
749 | [(set_attr "type" "compare")]) | |
815cdc52 MM |
750 | |
751 | (define_expand "extendqihi2" | |
752 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
753 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
754 | "" | |
755 | " | |
756 | { | |
757 | if (TARGET_POWERPC) | |
758 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
759 | else if (TARGET_POWER) | |
760 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
761 | else | |
762 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
763 | DONE; | |
764 | }") | |
765 | ||
766 | (define_insn "extendqihi2_ppc" | |
767 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
768 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
769 | "TARGET_POWERPC" | |
770 | "extsb %0,%1") | |
771 | ||
772 | (define_insn "" | |
29ae5b89 JL |
773 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
774 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
815cdc52 | 775 | (const_int 0))) |
29ae5b89 | 776 | (clobber (match_scratch:HI 2 "=r"))] |
815cdc52 | 777 | "TARGET_POWERPC" |
29ae5b89 JL |
778 | "extsb. %2,%1" |
779 | [(set_attr "type" "compare")]) | |
815cdc52 MM |
780 | |
781 | (define_insn "" | |
29ae5b89 JL |
782 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
783 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")) | |
51b8fc2c | 784 | (const_int 0))) |
29ae5b89 | 785 | (set (match_operand:HI 0 "gpc_reg_operand" "=r") |
51b8fc2c RK |
786 | (sign_extend:HI (match_dup 1)))] |
787 | "TARGET_POWERPC" | |
29ae5b89 JL |
788 | "extsb. %0,%1" |
789 | [(set_attr "type" "compare")]) | |
51b8fc2c RK |
790 | |
791 | (define_expand "extendqihi2_power" | |
792 | [(parallel [(set (match_dup 2) | |
793 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
794 | (const_int 24))) | |
795 | (clobber (scratch:SI))]) | |
796 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
797 | (ashiftrt:SI (match_dup 2) | |
798 | (const_int 24))) | |
799 | (clobber (scratch:SI))])] | |
800 | "TARGET_POWER" | |
801 | " | |
802 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
803 | operands[1] = gen_lowpart (SImode, operands[1]); | |
804 | operands[2] = gen_reg_rtx (SImode); }") | |
805 | ||
806 | (define_expand "extendqihi2_no_power" | |
807 | [(set (match_dup 2) | |
808 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
809 | (const_int 24))) | |
810 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
811 | (ashiftrt:SI (match_dup 2) | |
812 | (const_int 24)))] | |
813 | "! TARGET_POWER && ! TARGET_POWERPC" | |
814 | " | |
815 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
816 | operands[1] = gen_lowpart (SImode, operands[1]); | |
817 | operands[2] = gen_reg_rtx (SImode); }") | |
818 | ||
1fd4e8c1 | 819 | (define_expand "zero_extendhisi2" |
5f243543 | 820 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 821 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
822 | "" |
823 | "") | |
824 | ||
825 | (define_insn "" | |
cd2b37d9 | 826 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
827 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
828 | "" | |
829 | "@ | |
830 | lhz%U1%X1 %0,%1 | |
005a35b9 | 831 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
832 | [(set_attr "type" "load,*")]) |
833 | ||
834 | (define_insn "" | |
29ae5b89 JL |
835 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
836 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 837 | (const_int 0))) |
29ae5b89 | 838 | (clobber (match_scratch:SI 2 "=r"))] |
1fd4e8c1 | 839 | "" |
29ae5b89 JL |
840 | "{andil.|andi.} %2,%1,0xffff" |
841 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
842 | |
843 | (define_insn "" | |
29ae5b89 JL |
844 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
845 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 846 | (const_int 0))) |
29ae5b89 | 847 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
848 | (zero_extend:SI (match_dup 1)))] |
849 | "" | |
29ae5b89 JL |
850 | "{andil.|andi.} %0,%1,0xffff" |
851 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
852 | |
853 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
854 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
855 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
856 | "" |
857 | "") | |
858 | ||
859 | (define_insn "" | |
cd2b37d9 | 860 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
861 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
862 | "" | |
863 | "@ | |
864 | lha%U1%X1 %0,%1 | |
ca7f5001 | 865 | {exts|extsh} %0,%1" |
1fd4e8c1 RK |
866 | [(set_attr "type" "load,*")]) |
867 | ||
868 | (define_insn "" | |
29ae5b89 JL |
869 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
870 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 871 | (const_int 0))) |
29ae5b89 | 872 | (clobber (match_scratch:SI 2 "=r"))] |
1fd4e8c1 | 873 | "" |
29ae5b89 JL |
874 | "{exts.|extsh.} %2,%1" |
875 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
876 | |
877 | (define_insn "" | |
29ae5b89 JL |
878 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
879 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 880 | (const_int 0))) |
29ae5b89 | 881 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
882 | (sign_extend:SI (match_dup 1)))] |
883 | "" | |
29ae5b89 JL |
884 | "{exts.|extsh.} %0,%1" |
885 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
886 | \f |
887 | ;; Fixed-point arithmetic insns. | |
deb9225a RK |
888 | |
889 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
890 | ;; allowing register zero as source. | |
7cd5235b MM |
891 | (define_expand "addsi3" |
892 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
893 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
894 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
895 | "" | |
896 | " | |
897 | { | |
898 | if (GET_CODE (operands[2]) == CONST_INT && !add_operand (operands[2], SImode)) | |
899 | { | |
900 | rtx tmp = ((reload_in_progress || reload_completed | |
901 | || rtx_equal_p (operands[0], operands[1])) | |
902 | ? operands[0] : gen_reg_rtx (SImode)); | |
903 | ||
904 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; | |
905 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
906 | ||
907 | if (low & 0x8000) | |
908 | high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16; | |
909 | ||
910 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (high))); | |
911 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); | |
912 | DONE; | |
913 | } | |
914 | }") | |
915 | ||
916 | (define_insn "*addsi3_internal1" | |
917 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
918 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
919 | (match_operand:SI 2 "add_operand" "r,I,I,J")))] | |
1fd4e8c1 RK |
920 | "" |
921 | "@ | |
deb9225a RK |
922 | {cax|add} %0,%1,%2 |
923 | {cal %0,%2(%1)|addi %0,%1,%2} | |
924 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
925 | {cau|addis} %0,%1,%v2" |
926 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 927 | |
7cd5235b | 928 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
929 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
930 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
931 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 932 | (const_int 0))) |
cb8cc086 | 933 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
1fd4e8c1 | 934 | "" |
deb9225a RK |
935 | "@ |
936 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
937 | {ai.|addic.} %3,%1,%2 |
938 | # | |
939 | #" | |
940 | [(set_attr "type" "compare") | |
941 | (set_attr "length" "4,4,8,8")]) | |
942 | ||
943 | (define_split | |
944 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
945 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
946 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
947 | (const_int 0))) | |
948 | (clobber (match_scratch:SI 3 ""))] | |
949 | "reload_completed" | |
950 | [(set (match_dup 3) | |
951 | (plus:SI (match_dup 1) | |
952 | (match_dup 2))) | |
953 | (set (match_dup 0) | |
954 | (compare:CC (match_dup 3) | |
955 | (const_int 0)))] | |
956 | "") | |
7e69e155 | 957 | |
7cd5235b | 958 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
959 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
960 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
961 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 962 | (const_int 0))) |
cb8cc086 MM |
963 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
964 | (plus:SI (match_dup 1) | |
965 | (match_dup 2)))] | |
1fd4e8c1 | 966 | "" |
deb9225a RK |
967 | "@ |
968 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
969 | {ai.|addic.} %0,%1,%2 |
970 | # | |
971 | #" | |
972 | [(set_attr "type" "compare") | |
973 | (set_attr "length" "4,4,8,8")]) | |
974 | ||
975 | (define_split | |
976 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
977 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
978 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
979 | (const_int 0))) | |
980 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
981 | (plus:SI (match_dup 1) (match_dup 2)))] | |
982 | "reload_completed" | |
983 | [(set (match_dup 0) | |
984 | (plus:SI (match_dup 1) | |
985 | (match_dup 2))) | |
986 | (set (match_dup 3) | |
987 | (compare:CC (match_dup 0) | |
988 | (const_int 0)))] | |
989 | "") | |
7e69e155 | 990 | |
f357808b RK |
991 | ;; Split an add that we can't do in one insn into two insns, each of which |
992 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
993 | ;; add should be last in case the result gets used in an address. | |
994 | ||
995 | (define_split | |
cd2b37d9 RK |
996 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
997 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 998 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 999 | "" |
f357808b RK |
1000 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1001 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1002 | " | |
1fd4e8c1 | 1003 | { |
e6ca2c17 DE |
1004 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; |
1005 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
1fd4e8c1 | 1006 | |
f357808b | 1007 | if (low & 0x8000) |
e6ca2c17 | 1008 | high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16; |
1fd4e8c1 | 1009 | |
e6ca2c17 DE |
1010 | operands[3] = GEN_INT (high); |
1011 | operands[4] = GEN_INT (low); | |
1fd4e8c1 RK |
1012 | }") |
1013 | ||
8de2a197 | 1014 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1015 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1016 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1017 | "" |
ca7f5001 RK |
1018 | "nor %0,%1,%1") |
1019 | ||
1020 | (define_insn "" | |
52d3af72 DE |
1021 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1022 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1023 | (const_int 0))) |
52d3af72 | 1024 | (clobber (match_scratch:SI 2 "=r,r"))] |
ca7f5001 | 1025 | "" |
52d3af72 DE |
1026 | "@ |
1027 | nor. %2,%1,%1 | |
1028 | #" | |
1029 | [(set_attr "type" "compare") | |
1030 | (set_attr "length" "4,8")]) | |
1031 | ||
1032 | (define_split | |
1033 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1034 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1035 | (const_int 0))) | |
1036 | (clobber (match_scratch:SI 2 ""))] | |
1037 | "reload_completed" | |
1038 | [(set (match_dup 2) | |
1039 | (not:SI (match_dup 1))) | |
1040 | (set (match_dup 0) | |
1041 | (compare:CC (match_dup 2) | |
1042 | (const_int 0)))] | |
1043 | "") | |
ca7f5001 RK |
1044 | |
1045 | (define_insn "" | |
52d3af72 DE |
1046 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1047 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1048 | (const_int 0))) |
52d3af72 | 1049 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1050 | (not:SI (match_dup 1)))] |
29ae5b89 | 1051 | "" |
52d3af72 DE |
1052 | "@ |
1053 | nor. %0,%1,%1 | |
1054 | #" | |
1055 | [(set_attr "type" "compare") | |
1056 | (set_attr "length" "4,8")]) | |
1057 | ||
1058 | (define_split | |
1059 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1060 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1061 | (const_int 0))) | |
1062 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1063 | (not:SI (match_dup 1)))] | |
1064 | "reload_completed" | |
1065 | [(set (match_dup 0) | |
1066 | (not:SI (match_dup 1))) | |
1067 | (set (match_dup 2) | |
1068 | (compare:CC (match_dup 0) | |
1069 | (const_int 0)))] | |
1070 | "") | |
1fd4e8c1 RK |
1071 | |
1072 | (define_insn "" | |
3d91674b RK |
1073 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1074 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1075 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1076 | "! TARGET_POWERPC" |
ca7f5001 | 1077 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1078 | |
deb9225a RK |
1079 | (define_insn "" |
1080 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1081 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1082 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1083 | "TARGET_POWERPC" | |
1084 | "@ | |
1085 | subf %0,%2,%1 | |
1086 | subfic %0,%2,%1") | |
1087 | ||
1fd4e8c1 | 1088 | (define_insn "" |
cb8cc086 MM |
1089 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1090 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1091 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1092 | (const_int 0))) |
cb8cc086 | 1093 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1094 | "! TARGET_POWERPC" |
cb8cc086 MM |
1095 | "@ |
1096 | {sf.|subfc.} %3,%2,%1 | |
1097 | #" | |
1098 | [(set_attr "type" "compare") | |
1099 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1100 | |
deb9225a | 1101 | (define_insn "" |
cb8cc086 MM |
1102 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1103 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1104 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1105 | (const_int 0))) |
cb8cc086 | 1106 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1107 | "TARGET_POWERPC" |
cb8cc086 MM |
1108 | "@ |
1109 | subf. %3,%2,%1 | |
1110 | #" | |
1111 | [(set_attr "type" "compare") | |
1112 | (set_attr "length" "4,8")]) | |
1113 | ||
1114 | (define_split | |
1115 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1116 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1117 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1118 | (const_int 0))) | |
1119 | (clobber (match_scratch:SI 3 ""))] | |
1120 | "reload_completed" | |
1121 | [(set (match_dup 3) | |
1122 | (minus:SI (match_dup 1) | |
1123 | (match_dup 2))) | |
1124 | (set (match_dup 0) | |
1125 | (compare:CC (match_dup 3) | |
1126 | (const_int 0)))] | |
1127 | "") | |
deb9225a | 1128 | |
1fd4e8c1 | 1129 | (define_insn "" |
cb8cc086 MM |
1130 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1131 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1132 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1133 | (const_int 0))) |
cb8cc086 | 1134 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1135 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1136 | "! TARGET_POWERPC" |
cb8cc086 MM |
1137 | "@ |
1138 | {sf.|subfc.} %0,%2,%1 | |
1139 | #" | |
1140 | [(set_attr "type" "compare") | |
1141 | (set_attr "length" "4,8")]) | |
815cdc52 | 1142 | |
29ae5b89 | 1143 | (define_insn "" |
cb8cc086 MM |
1144 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1145 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1146 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1147 | (const_int 0))) |
cb8cc086 MM |
1148 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1149 | (minus:SI (match_dup 1) | |
1150 | (match_dup 2)))] | |
29ae5b89 | 1151 | "TARGET_POWERPC" |
90612787 DE |
1152 | "@ |
1153 | subf. %0,%2,%1 | |
1154 | #" | |
cb8cc086 MM |
1155 | [(set_attr "type" "compare") |
1156 | (set_attr "length" "4,8")]) | |
1157 | ||
1158 | (define_split | |
1159 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1160 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1161 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1162 | (const_int 0))) | |
1163 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1164 | (minus:SI (match_dup 1) | |
1165 | (match_dup 2)))] | |
1166 | "reload_completed" | |
1167 | [(set (match_dup 0) | |
1168 | (minus:SI (match_dup 1) | |
1169 | (match_dup 2))) | |
1170 | (set (match_dup 3) | |
1171 | (compare:CC (match_dup 0) | |
1172 | (const_int 0)))] | |
1173 | "") | |
deb9225a | 1174 | |
1fd4e8c1 | 1175 | (define_expand "subsi3" |
cd2b37d9 | 1176 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1177 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
1178 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
1179 | "" | |
a0044fb1 RK |
1180 | " |
1181 | { | |
1182 | if (GET_CODE (operands[2]) == CONST_INT) | |
1183 | { | |
1184 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1185 | negate_rtx (SImode, operands[2]))); | |
1186 | DONE; | |
1187 | } | |
1188 | }") | |
1fd4e8c1 RK |
1189 | |
1190 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1191 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1192 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1193 | ;; combine. | |
1fd4e8c1 RK |
1194 | |
1195 | (define_expand "sminsi3" | |
1196 | [(set (match_dup 3) | |
cd2b37d9 | 1197 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1198 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1199 | (const_int 0) | |
1200 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1201 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1202 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1203 | "TARGET_POWER" |
1fd4e8c1 RK |
1204 | " |
1205 | { operands[3] = gen_reg_rtx (SImode); }") | |
1206 | ||
95ac8e67 RK |
1207 | (define_split |
1208 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1209 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1210 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1211 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1212 | "TARGET_POWER" |
95ac8e67 RK |
1213 | [(set (match_dup 3) |
1214 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1215 | (const_int 0) | |
1216 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1217 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1218 | "") | |
1219 | ||
1fd4e8c1 RK |
1220 | (define_expand "smaxsi3" |
1221 | [(set (match_dup 3) | |
cd2b37d9 | 1222 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1223 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1224 | (const_int 0) | |
1225 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1226 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1227 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1228 | "TARGET_POWER" |
1fd4e8c1 RK |
1229 | " |
1230 | { operands[3] = gen_reg_rtx (SImode); }") | |
1231 | ||
95ac8e67 RK |
1232 | (define_split |
1233 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1234 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1235 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1236 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1237 | "TARGET_POWER" |
95ac8e67 RK |
1238 | [(set (match_dup 3) |
1239 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1240 | (const_int 0) | |
1241 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1242 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1243 | "") | |
1244 | ||
1fd4e8c1 | 1245 | (define_expand "uminsi3" |
cd2b37d9 | 1246 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1247 | (match_dup 5))) |
cd2b37d9 | 1248 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1249 | (match_dup 5))) |
1fd4e8c1 RK |
1250 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1251 | (const_int 0) | |
1252 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1253 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1254 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1255 | "TARGET_POWER" |
1fd4e8c1 | 1256 | " |
bb68ff55 MM |
1257 | { |
1258 | operands[3] = gen_reg_rtx (SImode); | |
1259 | operands[4] = gen_reg_rtx (SImode); | |
1260 | operands[5] = GEN_INT (-2147483647 - 1); | |
1261 | }") | |
1fd4e8c1 RK |
1262 | |
1263 | (define_expand "umaxsi3" | |
cd2b37d9 | 1264 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1265 | (match_dup 5))) |
cd2b37d9 | 1266 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1267 | (match_dup 5))) |
1fd4e8c1 RK |
1268 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1269 | (const_int 0) | |
1270 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1271 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1272 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1273 | "TARGET_POWER" |
1fd4e8c1 | 1274 | " |
bb68ff55 MM |
1275 | { |
1276 | operands[3] = gen_reg_rtx (SImode); | |
1277 | operands[4] = gen_reg_rtx (SImode); | |
1278 | operands[5] = GEN_INT (-2147483647 - 1); | |
1279 | }") | |
1fd4e8c1 RK |
1280 | |
1281 | (define_insn "" | |
cd2b37d9 RK |
1282 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1283 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1284 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1285 | (const_int 0) |
1286 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1287 | "TARGET_POWER" |
1fd4e8c1 RK |
1288 | "doz%I2 %0,%1,%2") |
1289 | ||
1290 | (define_insn "" | |
29ae5b89 | 1291 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 1292 | (compare:CC |
29ae5b89 JL |
1293 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") |
1294 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 RK |
1295 | (const_int 0) |
1296 | (minus:SI (match_dup 2) (match_dup 1))) | |
1297 | (const_int 0))) | |
29ae5b89 | 1298 | (clobber (match_scratch:SI 3 "=r"))] |
ca7f5001 | 1299 | "TARGET_POWER" |
29ae5b89 JL |
1300 | "doz%I2. %3,%1,%2" |
1301 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
1302 | |
1303 | (define_insn "" | |
29ae5b89 | 1304 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 | 1305 | (compare:CC |
29ae5b89 JL |
1306 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") |
1307 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 RK |
1308 | (const_int 0) |
1309 | (minus:SI (match_dup 2) (match_dup 1))) | |
1310 | (const_int 0))) | |
29ae5b89 | 1311 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
1312 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1313 | (const_int 0) | |
1314 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1315 | "TARGET_POWER" |
29ae5b89 | 1316 | "doz%I2. %0,%1,%2" |
1fd4e8c1 RK |
1317 | [(set_attr "type" "delayed_compare")]) |
1318 | ||
1319 | ;; We don't need abs with condition code because such comparisons should | |
1320 | ;; never be done. | |
ea9be077 MM |
1321 | (define_expand "abssi2" |
1322 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1323 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1324 | "" | |
1325 | " | |
1326 | { | |
1327 | if (!TARGET_POWER) | |
1328 | { | |
1329 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1330 | DONE; | |
1331 | } | |
1332 | }") | |
1333 | ||
1334 | (define_insn "abssi2_power" | |
cd2b37d9 RK |
1335 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1336 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1337 | "TARGET_POWER" |
1fd4e8c1 RK |
1338 | "abs %0,%1") |
1339 | ||
ea9be077 MM |
1340 | (define_insn "abssi2_nopower" |
1341 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1342 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
1343 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
1344 | "!TARGET_POWER" | |
3595d104 MM |
1345 | "* |
1346 | { | |
1347 | return (TARGET_POWERPC) | |
1348 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\" | |
1349 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\"; | |
1350 | }" | |
ea9be077 MM |
1351 | [(set_attr "length" "12")]) |
1352 | ||
1353 | (define_split | |
1354 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1355 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
1356 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
1357 | "!TARGET_POWER && reload_completed" | |
1358 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) | |
1359 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1360 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1361 | "") |
1362 | ||
463b558b | 1363 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1364 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1365 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1366 | "TARGET_POWER" |
1fd4e8c1 RK |
1367 | "nabs %0,%1") |
1368 | ||
463b558b | 1369 | (define_insn "*nabs_no_power" |
ea9be077 MM |
1370 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
1371 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
1372 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
1373 | "!TARGET_POWER" | |
3595d104 MM |
1374 | "* |
1375 | { | |
1376 | return (TARGET_POWERPC) | |
1377 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\" | |
1378 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\"; | |
1379 | }" | |
ea9be077 MM |
1380 | [(set_attr "length" "12")]) |
1381 | ||
1382 | (define_split | |
1383 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1384 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
1385 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
1386 | "!TARGET_POWER && reload_completed" | |
1387 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) | |
1388 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1389 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1390 | "") |
1391 | ||
1fd4e8c1 | 1392 | (define_insn "negsi2" |
cd2b37d9 RK |
1393 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1394 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1395 | "" |
1396 | "neg %0,%1") | |
1397 | ||
1398 | (define_insn "" | |
29ae5b89 JL |
1399 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1400 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 1401 | (const_int 0))) |
29ae5b89 | 1402 | (clobber (match_scratch:SI 2 "=r"))] |
1fd4e8c1 | 1403 | "" |
29ae5b89 JL |
1404 | "neg. %2,%1" |
1405 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
1406 | |
1407 | (define_insn "" | |
29ae5b89 JL |
1408 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
1409 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
815cdc52 MM |
1410 | (const_int 0))) |
1411 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1412 | (neg:SI (match_dup 1)))] | |
29ae5b89 JL |
1413 | "" |
1414 | "neg. %0,%1" | |
1415 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
1416 | |
1417 | (define_insn "ffssi2" | |
242e8072 RK |
1418 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
1419 | (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1420 | "" |
7f340546 | 1421 | "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" |
b19003d8 | 1422 | [(set_attr "length" "16")]) |
1fd4e8c1 | 1423 | |
ca7f5001 RK |
1424 | (define_expand "mulsi3" |
1425 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1426 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
1427 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
1428 | "" | |
1429 | " | |
1430 | { | |
1431 | if (TARGET_POWER) | |
68b40e7e | 1432 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 1433 | else |
68b40e7e | 1434 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
1435 | DONE; |
1436 | }") | |
1437 | ||
68b40e7e | 1438 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
1439 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1440 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
1441 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
1442 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
1443 | "TARGET_POWER" |
1444 | "@ | |
1445 | {muls|mullw} %0,%1,%2 | |
1446 | {muli|mulli} %0,%1,%2" | |
1447 | [(set_attr "type" "imul")]) | |
1448 | ||
68b40e7e | 1449 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
1450 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1451 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1452 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 1453 | "! TARGET_POWER" |
1fd4e8c1 | 1454 | "@ |
d904e9ed RK |
1455 | {muls|mullw} %0,%1,%2 |
1456 | {muli|mulli} %0,%1,%2" | |
cfb557c4 | 1457 | [(set_attr "type" "imul")]) |
1fd4e8c1 RK |
1458 | |
1459 | (define_insn "" | |
29ae5b89 JL |
1460 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1461 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1462 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 1463 | (const_int 0))) |
29ae5b89 JL |
1464 | (clobber (match_scratch:SI 3 "=r")) |
1465 | (clobber (match_scratch:SI 4 "=q"))] | |
ca7f5001 | 1466 | "TARGET_POWER" |
29ae5b89 JL |
1467 | "{muls.|mullw.} %3,%1,%2" |
1468 | [(set_attr "type" "delayed_compare")]) | |
ca7f5001 RK |
1469 | |
1470 | (define_insn "" | |
29ae5b89 JL |
1471 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1472 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1473 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
ca7f5001 | 1474 | (const_int 0))) |
29ae5b89 | 1475 | (clobber (match_scratch:SI 3 "=r"))] |
25c341fa | 1476 | "! TARGET_POWER" |
29ae5b89 JL |
1477 | "{muls.|mullw.} %3,%1,%2" |
1478 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
1479 | |
1480 | (define_insn "" | |
29ae5b89 JL |
1481 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1482 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1483 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 1484 | (const_int 0))) |
29ae5b89 JL |
1485 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1486 | (mult:SI (match_dup 1) (match_dup 2))) | |
1487 | (clobber (match_scratch:SI 4 "=q"))] | |
ca7f5001 | 1488 | "TARGET_POWER" |
29ae5b89 JL |
1489 | "{muls.|mullw.} %0,%1,%2" |
1490 | [(set_attr "type" "delayed_compare")]) | |
ca7f5001 RK |
1491 | |
1492 | (define_insn "" | |
29ae5b89 JL |
1493 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1494 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
1495 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
ca7f5001 | 1496 | (const_int 0))) |
29ae5b89 | 1497 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ca7f5001 | 1498 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 1499 | "! TARGET_POWER" |
29ae5b89 JL |
1500 | "{muls.|mullw.} %0,%1,%2" |
1501 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
1502 | |
1503 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
1504 | ;; 0 and remainder to operand 3. | |
1505 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
1506 | ||
8ffd9c51 RK |
1507 | (define_expand "divmodsi4" |
1508 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1509 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1510 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
1511 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
1512 | (mod:SI (match_dup 1) (match_dup 2)))])] | |
1513 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1514 | " | |
1515 | { | |
1516 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1517 | { | |
39403d82 DE |
1518 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1519 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1520 | emit_insn (gen_divss_call ()); |
39403d82 DE |
1521 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1522 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
1523 | DONE; |
1524 | } | |
1525 | }") | |
deb9225a | 1526 | |
fada905b | 1527 | (define_insn "" |
cd2b37d9 RK |
1528 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1529 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1530 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1531 | (set (match_operand:SI 3 "gpc_reg_operand" "=q") | |
1fd4e8c1 | 1532 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 1533 | "TARGET_POWER" |
cfb557c4 RK |
1534 | "divs %0,%1,%2" |
1535 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 1536 | |
8ffd9c51 RK |
1537 | (define_expand "udivsi3" |
1538 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1539 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1540 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
1541 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1542 | " | |
1543 | { | |
1544 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1545 | { | |
39403d82 DE |
1546 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1547 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1548 | emit_insn (gen_quous_call ()); |
39403d82 | 1549 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1550 | DONE; |
1551 | } | |
f192bf8b DE |
1552 | else if (TARGET_POWER) |
1553 | { | |
1554 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
1555 | DONE; | |
1556 | } | |
8ffd9c51 | 1557 | }") |
deb9225a | 1558 | |
f192bf8b DE |
1559 | (define_insn "udivsi3_mq" |
1560 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1561 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1562 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1563 | (clobber (match_scratch:SI 3 "=q"))] | |
1564 | "TARGET_POWERPC && TARGET_POWER" | |
1565 | "divwu %0,%1,%2" | |
1566 | [(set_attr "type" "idiv")]) | |
1567 | ||
1568 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
1569 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1570 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1571 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 1572 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 1573 | "divwu %0,%1,%2" |
ca7f5001 RK |
1574 | [(set_attr "type" "idiv")]) |
1575 | ||
1fd4e8c1 | 1576 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 1577 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
1578 | ;; used; for PowerPC, force operands into register and do a normal divide; |
1579 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 1580 | (define_expand "divsi3" |
cd2b37d9 RK |
1581 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1582 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
1583 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
1584 | "" | |
1585 | " | |
1586 | { | |
ca7f5001 RK |
1587 | if (GET_CODE (operands[2]) == CONST_INT |
1588 | && exact_log2 (INTVAL (operands[2])) >= 0) | |
1589 | ; | |
b6c9286a | 1590 | else if (TARGET_POWERPC) |
f192bf8b DE |
1591 | { |
1592 | operands[2] = force_reg (SImode, operands[2]); | |
1593 | if (TARGET_POWER) | |
1594 | { | |
1595 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
1596 | DONE; | |
1597 | } | |
1598 | } | |
b6c9286a | 1599 | else if (TARGET_POWER) |
1fd4e8c1 | 1600 | FAIL; |
405c5495 | 1601 | else |
8ffd9c51 | 1602 | { |
39403d82 DE |
1603 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1604 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1605 | emit_insn (gen_quoss_call ()); |
39403d82 | 1606 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1607 | DONE; |
1608 | } | |
1fd4e8c1 RK |
1609 | }") |
1610 | ||
f192bf8b DE |
1611 | (define_insn "divsi3_mq" |
1612 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1613 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1614 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1615 | (clobber (match_scratch:SI 3 "=q"))] | |
1616 | "TARGET_POWERPC && TARGET_POWER" | |
1617 | "divw %0,%1,%2" | |
1618 | [(set_attr "type" "idiv")]) | |
1619 | ||
1620 | (define_insn "*divsi3_no_mq" | |
1621 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1622 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1623 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1624 | "TARGET_POWERPC && ! TARGET_POWER" | |
1625 | "divw %0,%1,%2" | |
1626 | [(set_attr "type" "idiv")]) | |
1627 | ||
1fd4e8c1 | 1628 | (define_expand "modsi3" |
85644414 RK |
1629 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
1630 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 1631 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 1632 | "" |
1fd4e8c1 RK |
1633 | " |
1634 | { | |
39b52ba2 RK |
1635 | int i = exact_log2 (INTVAL (operands[2])); |
1636 | rtx temp1; | |
1637 | rtx temp2; | |
1638 | ||
405c5495 | 1639 | if (GET_CODE (operands[2]) != CONST_INT || i < 0) |
39b52ba2 RK |
1640 | FAIL; |
1641 | ||
1642 | temp1 = gen_reg_rtx (SImode); | |
1643 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 1644 | |
85644414 | 1645 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 1646 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
1647 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
1648 | DONE; | |
1fd4e8c1 RK |
1649 | }") |
1650 | ||
1651 | (define_insn "" | |
cd2b37d9 RK |
1652 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1653 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
1654 | (match_operand:SI 2 "const_int_operand" "N")))] |
1655 | "exact_log2 (INTVAL (operands[2])) >= 0" | |
ca7f5001 | 1656 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 1657 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
1658 | |
1659 | (define_insn "" | |
29ae5b89 JL |
1660 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1661 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1662 | (match_operand:SI 2 "const_int_operand" "N")) | |
b6b12107 | 1663 | (const_int 0))) |
29ae5b89 | 1664 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 1665 | "exact_log2 (INTVAL (operands[2])) >= 0" |
29ae5b89 | 1666 | "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3" |
b19003d8 | 1667 | [(set_attr "type" "compare") |
29ae5b89 | 1668 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
1669 | |
1670 | (define_insn "" | |
29ae5b89 JL |
1671 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1672 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1673 | (match_operand:SI 2 "const_int_operand" "N")) | |
b6b12107 | 1674 | (const_int 0))) |
29ae5b89 JL |
1675 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1676 | (div:SI (match_dup 1) (match_dup 2)))] | |
1fd4e8c1 | 1677 | "exact_log2 (INTVAL (operands[2])) >= 0" |
29ae5b89 | 1678 | "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0" |
b19003d8 | 1679 | [(set_attr "type" "compare") |
29ae5b89 | 1680 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
1681 | |
1682 | (define_insn "" | |
cd2b37d9 | 1683 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 1684 | (udiv:SI |
996a5f59 | 1685 | (plus:DI (ashift:DI |
cd2b37d9 | 1686 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 1687 | (const_int 32)) |
23a900dc | 1688 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 1689 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 1690 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 1691 | (umod:SI |
996a5f59 | 1692 | (plus:DI (ashift:DI |
1fd4e8c1 | 1693 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 1694 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 1695 | (match_dup 3)))] |
ca7f5001 | 1696 | "TARGET_POWER" |
cfb557c4 RK |
1697 | "div %0,%1,%3" |
1698 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
1699 | |
1700 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
1701 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
1702 | ;; have to worry about the branches. So make a few subroutines here. | |
1703 | ;; | |
1704 | ;; First comes the normal case. | |
1705 | (define_expand "udivmodsi4_normal" | |
1706 | [(set (match_dup 4) (const_int 0)) | |
1707 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 1708 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
1709 | (const_int 32)) |
1710 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
1711 | (match_operand:SI 2 "" ""))) | |
1712 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 1713 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
1714 | (const_int 32)) |
1715 | (zero_extend:DI (match_dup 1))) | |
1716 | (match_dup 2)))])] | |
ca7f5001 | 1717 | "TARGET_POWER" |
1fd4e8c1 RK |
1718 | " |
1719 | { operands[4] = gen_reg_rtx (SImode); }") | |
1720 | ||
1721 | ;; This handles the branches. | |
1722 | (define_expand "udivmodsi4_tests" | |
1723 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
1724 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
1725 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
1726 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
1727 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
1728 | (set (match_dup 0) (const_int 1)) | |
1729 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
1730 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
1731 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
1732 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 1733 | "TARGET_POWER" |
1fd4e8c1 RK |
1734 | " |
1735 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
1736 | operands[6] = gen_reg_rtx (CCmode); | |
1737 | }") | |
1738 | ||
1739 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
1740 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1741 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 1742 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 1743 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 1744 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 1745 | "" |
1fd4e8c1 RK |
1746 | " |
1747 | { | |
1748 | rtx label = 0; | |
1749 | ||
8ffd9c51 | 1750 | if (! TARGET_POWER) |
c4d38ccb MM |
1751 | { |
1752 | if (! TARGET_POWERPC) | |
1753 | { | |
39403d82 DE |
1754 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1755 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 1756 | emit_insn (gen_divus_call ()); |
39403d82 DE |
1757 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1758 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
1759 | DONE; |
1760 | } | |
1761 | else | |
1762 | FAIL; | |
1763 | } | |
0081a354 | 1764 | |
1fd4e8c1 RK |
1765 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
1766 | { | |
1767 | operands[2] = force_reg (SImode, operands[2]); | |
1768 | label = gen_label_rtx (); | |
1769 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
1770 | operands[3], label)); | |
1771 | } | |
1772 | else | |
1773 | operands[2] = force_reg (SImode, operands[2]); | |
1774 | ||
1775 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
1776 | operands[3])); | |
1777 | if (label) | |
1778 | emit_label (label); | |
1779 | ||
1780 | DONE; | |
1781 | }") | |
0081a354 | 1782 | |
fada905b MM |
1783 | ;; AIX architecture-independent common-mode multiply (DImode), |
1784 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
1785 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
1786 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
1787 | ;; assumed unused if generating common-mode, so ignore. | |
1788 | (define_insn "mulh_call" | |
1789 | [(set (reg:SI 3) | |
1790 | (truncate:SI | |
1791 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
1792 | (sign_extend:DI (reg:SI 4))) | |
1793 | (const_int 32)))) | |
cf27b467 | 1794 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 1795 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
1796 | "bla __mulh" |
1797 | [(set_attr "type" "imul")]) | |
fada905b MM |
1798 | |
1799 | (define_insn "mull_call" | |
1800 | [(set (reg:DI 3) | |
1801 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
1802 | (sign_extend:DI (reg:SI 4)))) | |
1803 | (clobber (match_scratch:SI 0 "=l")) | |
1804 | (clobber (reg:SI 0))] | |
1805 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
1806 | "bla __mull" |
1807 | [(set_attr "type" "imul")]) | |
fada905b MM |
1808 | |
1809 | (define_insn "divss_call" | |
1810 | [(set (reg:SI 3) | |
1811 | (div:SI (reg:SI 3) (reg:SI 4))) | |
1812 | (set (reg:SI 4) | |
1813 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
1814 | (clobber (match_scratch:SI 0 "=l")) | |
1815 | (clobber (reg:SI 0))] | |
1816 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
1817 | "bla __divss" |
1818 | [(set_attr "type" "idiv")]) | |
fada905b MM |
1819 | |
1820 | (define_insn "divus_call" | |
8ffd9c51 RK |
1821 | [(set (reg:SI 3) |
1822 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
1823 | (set (reg:SI 4) | |
1824 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
1825 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
1826 | (clobber (reg:SI 0)) |
1827 | (clobber (match_scratch:CC 1 "=x")) | |
1828 | (clobber (reg:CC 69))] | |
1829 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
1830 | "bla __divus" |
1831 | [(set_attr "type" "idiv")]) | |
fada905b MM |
1832 | |
1833 | (define_insn "quoss_call" | |
1834 | [(set (reg:SI 3) | |
1835 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 1836 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 1837 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
1838 | "bla __quoss" |
1839 | [(set_attr "type" "idiv")]) | |
0081a354 | 1840 | |
fada905b MM |
1841 | (define_insn "quous_call" |
1842 | [(set (reg:SI 3) | |
1843 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
1844 | (clobber (match_scratch:SI 0 "=l")) | |
1845 | (clobber (reg:SI 0)) | |
1846 | (clobber (match_scratch:CC 1 "=x")) | |
1847 | (clobber (reg:CC 69))] | |
1848 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
1849 | "bla __quous" |
1850 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 1851 | \f |
bb21487f | 1852 | ;; Logical instructions |
29ae5b89 JL |
1853 | (define_insn "andsi3" |
1854 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
1855 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1856 | (match_operand:SI 2 "and_operand" "?r,L,K,J"))) | |
1857 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] | |
1fd4e8c1 RK |
1858 | "" |
1859 | "@ | |
1860 | and %0,%1,%2 | |
ca7f5001 RK |
1861 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
1862 | {andil.|andi.} %0,%1,%b2 | |
29ae5b89 | 1863 | {andiu.|andis.} %0,%1,%u2" |
52d3af72 DE |
1864 | [(set_attr "length" "4")]) |
1865 | ||
1866 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
1867 | ;; the test again -- this avoids a mcrf which on the higher end | |
1868 | ;; machines causes an execution serialization | |
1fd4e8c1 | 1869 | |
7cd5235b | 1870 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
1871 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
1872 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
1873 | (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L")) | |
1fd4e8c1 | 1874 | (const_int 0))) |
52d3af72 DE |
1875 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
1876 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
1fd4e8c1 RK |
1877 | "" |
1878 | "@ | |
1879 | and. %3,%1,%2 | |
ca7f5001 RK |
1880 | {andil.|andi.} %3,%1,%b2 |
1881 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
1882 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
1883 | # | |
1884 | # | |
1885 | # | |
1886 | #" | |
1887 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
1888 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 1889 | |
52d3af72 DE |
1890 | (define_split |
1891 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1892 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1893 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 1894 | (const_int 0))) |
52d3af72 DE |
1895 | (clobber (match_scratch:SI 3 "")) |
1896 | (clobber (match_scratch:CC 4 ""))] | |
1897 | "reload_completed" | |
1898 | [(parallel [(set (match_dup 3) | |
1899 | (and:SI (match_dup 1) | |
1900 | (match_dup 2))) | |
1901 | (clobber (match_dup 4))]) | |
1902 | (set (match_dup 0) | |
1903 | (compare:CC (match_dup 3) | |
1904 | (const_int 0)))] | |
1905 | "") | |
1906 | ||
1907 | (define_insn "*andsi3_internal3" | |
1908 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
1909 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
1910 | (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L")) | |
1911 | (const_int 0))) | |
1912 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
1913 | (and:SI (match_dup 1) | |
1914 | (match_dup 2))) | |
1915 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
1fd4e8c1 RK |
1916 | "" |
1917 | "@ | |
1918 | and. %0,%1,%2 | |
ca7f5001 RK |
1919 | {andil.|andi.} %0,%1,%b2 |
1920 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
1921 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
1922 | # | |
1923 | # | |
1924 | # | |
1925 | #" | |
1926 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
1927 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1928 | ||
1929 | (define_split | |
1930 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1931 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1932 | (match_operand:SI 2 "and_operand" "")) | |
1933 | (const_int 0))) | |
1934 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1935 | (and:SI (match_dup 1) | |
1936 | (match_dup 2))) | |
1937 | (clobber (match_scratch:CC 4 ""))] | |
1938 | "reload_completed" | |
1939 | [(parallel [(set (match_dup 0) | |
1940 | (and:SI (match_dup 1) | |
1941 | (match_dup 2))) | |
1942 | (clobber (match_dup 4))]) | |
1943 | (set (match_dup 3) | |
1944 | (compare:CC (match_dup 0) | |
1945 | (const_int 0)))] | |
1946 | "") | |
1fd4e8c1 | 1947 | |
7cd5235b | 1948 | (define_expand "iorsi3" |
cd2b37d9 | 1949 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b MM |
1950 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1951 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
1952 | "" | |
f357808b RK |
1953 | " |
1954 | { | |
7cd5235b MM |
1955 | if (GET_CODE (operands[2]) == CONST_INT |
1956 | && !logical_operand (operands[2], SImode)) | |
1957 | { | |
1958 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
1959 | rtx tmp = ((reload_in_progress || reload_completed | |
1960 | || rtx_equal_p (operands[0], operands[1])) | |
1961 | ? operands[0] : gen_reg_rtx (SImode)); | |
1962 | ||
a260abc9 DE |
1963 | emit_insn (gen_iorsi3 (tmp, operands[1], |
1964 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
1965 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
1966 | DONE; |
1967 | } | |
f357808b RK |
1968 | }") |
1969 | ||
7cd5235b MM |
1970 | (define_insn "*iorsi3_internal1" |
1971 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") | |
1972 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") | |
1973 | (match_operand:SI 2 "logical_operand" "r,K,J")))] | |
1fd4e8c1 RK |
1974 | "" |
1975 | "@ | |
1976 | or %0,%1,%2 | |
ca7f5001 | 1977 | {oril|ori} %0,%1,%b2 |
7cd5235b MM |
1978 | {oriu|oris} %0,%1,%u2" |
1979 | [(set_attr "length" "4,4,4")]) | |
1fd4e8c1 | 1980 | |
7cd5235b | 1981 | (define_insn "*iorsi3_internal2" |
52d3af72 DE |
1982 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1983 | (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1984 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1985 | (const_int 0))) |
52d3af72 | 1986 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 1987 | "" |
52d3af72 DE |
1988 | "@ |
1989 | or. %3,%1,%2 | |
1990 | #" | |
1991 | [(set_attr "type" "compare") | |
1992 | (set_attr "length" "4,8")]) | |
1993 | ||
1994 | (define_split | |
1995 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1996 | (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1997 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1998 | (const_int 0))) | |
1999 | (clobber (match_scratch:SI 3 ""))] | |
2000 | "reload_completed" | |
2001 | [(set (match_dup 3) | |
2002 | (ior:SI (match_dup 1) | |
2003 | (match_dup 2))) | |
2004 | (set (match_dup 0) | |
2005 | (compare:CC (match_dup 3) | |
2006 | (const_int 0)))] | |
2007 | "") | |
1fd4e8c1 | 2008 | |
7cd5235b | 2009 | (define_insn "*iorsi3_internal3" |
52d3af72 DE |
2010 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2011 | (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2012 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2013 | (const_int 0))) |
52d3af72 DE |
2014 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2015 | (ior:SI (match_dup 1) | |
2016 | (match_dup 2)))] | |
1fd4e8c1 | 2017 | "" |
52d3af72 DE |
2018 | "@ |
2019 | or. %0,%1,%2 | |
2020 | #" | |
2021 | [(set_attr "type" "compare") | |
2022 | (set_attr "length" "4,8")]) | |
2023 | ||
2024 | (define_split | |
2025 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2026 | (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2027 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2028 | (const_int 0))) | |
2029 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2030 | (ior:SI (match_dup 1) (match_dup 2)))] | |
2031 | "reload_completed" | |
2032 | [(set (match_dup 0) | |
2033 | (ior:SI (match_dup 1) | |
2034 | (match_dup 2))) | |
2035 | (set (match_dup 3) | |
2036 | (compare:CC (match_dup 0) | |
2037 | (const_int 0)))] | |
2038 | "") | |
1fd4e8c1 | 2039 | |
a260abc9 DE |
2040 | ;; Split an IOR that we can't do in one insn into two insns, each of which |
2041 | ;; does one 16-bit part. This is used by combine. | |
2042 | ||
2043 | (define_split | |
2044 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2045 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2046 | (match_operand:SI 2 "non_logical_cint_operand" "")))] | |
2047 | "" | |
2048 | [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3))) | |
2049 | (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))] | |
2050 | " | |
2051 | { | |
2052 | operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
2053 | operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
2054 | }") | |
2055 | ||
7cd5235b | 2056 | (define_expand "xorsi3" |
cd2b37d9 | 2057 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b MM |
2058 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
2059 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
1fd4e8c1 | 2060 | "" |
7cd5235b | 2061 | " |
1fd4e8c1 | 2062 | { |
7cd5235b MM |
2063 | if (GET_CODE (operands[2]) == CONST_INT |
2064 | && !logical_operand (operands[2], SImode)) | |
2065 | { | |
2066 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
2067 | rtx tmp = ((reload_in_progress || reload_completed | |
2068 | || rtx_equal_p (operands[0], operands[1])) | |
2069 | ? operands[0] : gen_reg_rtx (SImode)); | |
2070 | ||
a260abc9 DE |
2071 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2072 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2073 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2074 | DONE; |
2075 | } | |
1fd4e8c1 RK |
2076 | }") |
2077 | ||
7cd5235b MM |
2078 | (define_insn "*xorsi3_internal1" |
2079 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") | |
2080 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") | |
2081 | (match_operand:SI 2 "logical_operand" "r,K,J")))] | |
1fd4e8c1 RK |
2082 | "" |
2083 | "@ | |
2084 | xor %0,%1,%2 | |
ca7f5001 | 2085 | {xoril|xori} %0,%1,%b2 |
7cd5235b MM |
2086 | {xoriu|xoris} %0,%1,%u2" |
2087 | [(set_attr "length" "4,4,4")]) | |
1fd4e8c1 | 2088 | |
7cd5235b | 2089 | (define_insn "*xorsi3_internal2" |
52d3af72 DE |
2090 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2091 | (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2092 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2093 | (const_int 0))) |
52d3af72 | 2094 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 2095 | "" |
52d3af72 DE |
2096 | "@ |
2097 | xor. %3,%1,%2 | |
2098 | #" | |
2099 | [(set_attr "type" "compare") | |
2100 | (set_attr "length" "4,8")]) | |
2101 | ||
2102 | (define_split | |
2103 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2104 | (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2105 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2106 | (const_int 0))) | |
2107 | (clobber (match_scratch:SI 3 ""))] | |
2108 | "reload_completed" | |
2109 | [(set (match_dup 3) | |
2110 | (xor:SI (match_dup 1) | |
2111 | (match_dup 2))) | |
2112 | (set (match_dup 0) | |
2113 | (compare:CC (match_dup 3) | |
2114 | (const_int 0)))] | |
2115 | "") | |
815cdc52 | 2116 | |
29ae5b89 | 2117 | (define_insn "*xorsi3_internal3" |
52d3af72 DE |
2118 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2119 | (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2120 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2121 | (const_int 0))) |
52d3af72 DE |
2122 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2123 | (xor:SI (match_dup 1) | |
2124 | (match_dup 2)))] | |
29ae5b89 | 2125 | "" |
52d3af72 DE |
2126 | "@ |
2127 | xor. %0,%1,%2 | |
2128 | #" | |
2129 | [(set_attr "type" "compare") | |
2130 | (set_attr "length" "4,8")]) | |
2131 | ||
2132 | (define_split | |
2133 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2134 | (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2135 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2136 | (const_int 0))) | |
2137 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2138 | (xor:SI (match_dup 1) (match_dup 2)))] | |
2139 | "reload_completed" | |
2140 | [(set (match_dup 0) | |
2141 | (xor:SI (match_dup 1) | |
2142 | (match_dup 2))) | |
2143 | (set (match_dup 3) | |
2144 | (compare:CC (match_dup 0) | |
2145 | (const_int 0)))] | |
2146 | "") | |
1fd4e8c1 | 2147 | |
a260abc9 DE |
2148 | ;; Split an XOR that we can't do in one insn into two insns, each of which |
2149 | ;; does one 16-bit part. This is used by combine. | |
2150 | ||
2151 | (define_split | |
2152 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2153 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2154 | (match_operand:SI 2 "non_logical_cint_operand" "")))] | |
2155 | "" | |
2156 | [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3))) | |
2157 | (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))] | |
2158 | " | |
2159 | { | |
2160 | operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
2161 | operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
2162 | }") | |
2163 | ||
2164 | (define_insn "*eqvsi3_internal1" | |
cd2b37d9 RK |
2165 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2166 | (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") | |
2167 | (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
1fd4e8c1 RK |
2168 | "" |
2169 | "eqv %0,%1,%2") | |
2170 | ||
a260abc9 | 2171 | (define_insn "*eqvsi3_internal2" |
52d3af72 DE |
2172 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2173 | (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2174 | (match_operand:SI 2 "gpc_reg_operand" "r,r"))) | |
1fd4e8c1 | 2175 | (const_int 0))) |
52d3af72 | 2176 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 2177 | "" |
52d3af72 DE |
2178 | "@ |
2179 | eqv. %3,%1,%2 | |
2180 | #" | |
2181 | [(set_attr "type" "compare") | |
2182 | (set_attr "length" "4,8")]) | |
2183 | ||
2184 | (define_split | |
2185 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2186 | (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2187 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2188 | (const_int 0))) | |
2189 | (clobber (match_scratch:SI 3 ""))] | |
2190 | "reload_completed" | |
2191 | [(set (match_dup 3) | |
2192 | (not:SI (xor:SI (match_dup 1) | |
2193 | (match_dup 2)))) | |
2194 | (set (match_dup 0) | |
2195 | (compare:CC (match_dup 3) | |
2196 | (const_int 0)))] | |
2197 | "") | |
1fd4e8c1 | 2198 | |
a260abc9 | 2199 | (define_insn "*eqvsi3_internal3" |
52d3af72 DE |
2200 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2201 | (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2202 | (match_operand:SI 2 "gpc_reg_operand" "r,r"))) | |
1fd4e8c1 | 2203 | (const_int 0))) |
52d3af72 | 2204 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
2205 | (not:SI (xor:SI (match_dup 1) (match_dup 2))))] |
2206 | "" | |
52d3af72 DE |
2207 | "@ |
2208 | eqv. %0,%1,%2 | |
2209 | #" | |
2210 | [(set_attr "type" "compare") | |
2211 | (set_attr "length" "4,8")]) | |
2212 | ||
2213 | (define_split | |
2214 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2215 | (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2216 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
2217 | (const_int 0))) | |
2218 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2219 | (not:SI (xor:SI (match_dup 1) | |
2220 | (match_dup 2))))] | |
2221 | "reload_completed" | |
2222 | [(set (match_dup 0) | |
2223 | (not:SI (xor:SI (match_dup 1) | |
2224 | (match_dup 2)))) | |
2225 | (set (match_dup 3) | |
2226 | (compare:CC (match_dup 0) | |
2227 | (const_int 0)))] | |
2228 | "") | |
1fd4e8c1 | 2229 | |
a260abc9 | 2230 | (define_insn "*andcsi3_internal1" |
cd2b37d9 RK |
2231 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2232 | (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2233 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
2234 | "" |
2235 | "andc %0,%2,%1") | |
2236 | ||
a260abc9 | 2237 | (define_insn "*andcsi3_internal2" |
52d3af72 DE |
2238 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2239 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2240 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2241 | (const_int 0))) |
52d3af72 | 2242 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 2243 | "" |
52d3af72 DE |
2244 | "@ |
2245 | andc. %3,%2,%1 | |
2246 | #" | |
2247 | [(set_attr "type" "compare") | |
2248 | (set_attr "length" "4,8")]) | |
2249 | ||
2250 | (define_split | |
2251 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2252 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2253 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2254 | (const_int 0))) | |
2255 | (clobber (match_scratch:SI 3 ""))] | |
2256 | "reload_completed" | |
2257 | [(set (match_dup 3) | |
2258 | (and:SI (not:SI (match_dup 1)) | |
2259 | (match_dup 2))) | |
2260 | (set (match_dup 0) | |
2261 | (compare:CC (match_dup 3) | |
2262 | (const_int 0)))] | |
2263 | "") | |
1fd4e8c1 | 2264 | |
a260abc9 | 2265 | (define_insn "*andcsi3_internal3" |
52d3af72 DE |
2266 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2267 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2268 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2269 | (const_int 0))) |
52d3af72 DE |
2270 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2271 | (and:SI (not:SI (match_dup 1)) | |
2272 | (match_dup 2)))] | |
1fd4e8c1 | 2273 | "" |
52d3af72 DE |
2274 | "@ |
2275 | andc. %0,%2,%1 | |
2276 | #" | |
2277 | [(set_attr "type" "compare") | |
2278 | (set_attr "length" "4,8")]) | |
2279 | ||
2280 | (define_split | |
2281 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2282 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2283 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2284 | (const_int 0))) | |
2285 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2286 | (and:SI (not:SI (match_dup 1)) | |
2287 | (match_dup 2)))] | |
2288 | "reload_completed" | |
2289 | [(set (match_dup 0) | |
2290 | (and:SI (not:SI (match_dup 1)) | |
2291 | (match_dup 2))) | |
2292 | (set (match_dup 3) | |
2293 | (compare:CC (match_dup 0) | |
2294 | (const_int 0)))] | |
2295 | "") | |
1fd4e8c1 | 2296 | |
a260abc9 | 2297 | (define_insn "*iorcsi3_internal1" |
cd2b37d9 RK |
2298 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2299 | (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2300 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
2301 | "" |
2302 | "orc %0,%2,%1") | |
2303 | ||
a260abc9 | 2304 | (define_insn "*iorcsi3_internal2" |
52d3af72 DE |
2305 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2306 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2307 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2308 | (const_int 0))) |
52d3af72 | 2309 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 2310 | "" |
52d3af72 DE |
2311 | "@ |
2312 | orc. %3,%2,%1 | |
2313 | #" | |
2314 | [(set_attr "type" "compare") | |
2315 | (set_attr "length" "4,8")]) | |
2316 | ||
2317 | (define_split | |
2318 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2319 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2320 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2321 | (const_int 0))) | |
2322 | (clobber (match_scratch:SI 3 ""))] | |
2323 | "reload_completed" | |
2324 | [(set (match_dup 3) | |
2325 | (ior:SI (not:SI (match_dup 1)) | |
2326 | (match_dup 2))) | |
2327 | (set (match_dup 0) | |
2328 | (compare:CC (match_dup 3) | |
2329 | (const_int 0)))] | |
2330 | "") | |
1fd4e8c1 | 2331 | |
a260abc9 | 2332 | (define_insn "*iorcsi3_internal3" |
52d3af72 DE |
2333 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2334 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2335 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2336 | (const_int 0))) |
52d3af72 | 2337 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
2338 | (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] |
2339 | "" | |
52d3af72 DE |
2340 | "@ |
2341 | orc. %0,%2,%1 | |
2342 | #" | |
1fd4e8c1 RK |
2343 | [(set_attr "type" "compare")]) |
2344 | ||
52d3af72 DE |
2345 | (define_split |
2346 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2347 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2348 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2349 | (const_int 0))) | |
2350 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2351 | (ior:SI (not:SI (match_dup 1)) | |
2352 | (match_dup 2)))] | |
2353 | "reload_completed" | |
2354 | [(set (match_dup 0) | |
2355 | (ior:SI (not:SI (match_dup 1)) | |
2356 | (match_dup 2))) | |
2357 | (set (match_dup 3) | |
2358 | (compare:CC (match_dup 0) | |
2359 | (const_int 0)))] | |
2360 | "") | |
2361 | ||
a260abc9 | 2362 | (define_insn "*nandsi3_internal1" |
cd2b37d9 | 2363 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
29ae5b89 | 2364 | (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 2365 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] |
1fd4e8c1 RK |
2366 | "" |
2367 | "nand %0,%1,%2") | |
2368 | ||
a260abc9 | 2369 | (define_insn "*nandsi3_internal2" |
52d3af72 DE |
2370 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2371 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2372 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) | |
1fd4e8c1 | 2373 | (const_int 0))) |
52d3af72 | 2374 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 2375 | "" |
52d3af72 DE |
2376 | "@ |
2377 | nand. %3,%1,%2 | |
2378 | #" | |
2379 | [(set_attr "type" "compare") | |
2380 | (set_attr "length" "4,8")]) | |
2381 | ||
2382 | (define_split | |
2383 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2384 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2385 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2386 | (const_int 0))) | |
2387 | (clobber (match_scratch:SI 3 ""))] | |
2388 | "reload_completed" | |
2389 | [(set (match_dup 3) | |
2390 | (ior:SI (not:SI (match_dup 1)) | |
2391 | (not:SI (match_dup 2)))) | |
2392 | (set (match_dup 0) | |
2393 | (compare:CC (match_dup 3) | |
2394 | (const_int 0)))] | |
2395 | "") | |
1fd4e8c1 | 2396 | |
a260abc9 | 2397 | (define_insn "*nandsi3_internal3" |
52d3af72 DE |
2398 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2399 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2400 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) | |
1fd4e8c1 | 2401 | (const_int 0))) |
52d3af72 DE |
2402 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2403 | (ior:SI (not:SI (match_dup 1)) | |
2404 | (not:SI (match_dup 2))))] | |
1fd4e8c1 | 2405 | "" |
52d3af72 DE |
2406 | "@ |
2407 | nand. %0,%1,%2 | |
2408 | #" | |
2409 | [(set_attr "type" "compare") | |
2410 | (set_attr "length" "4,8")]) | |
2411 | ||
2412 | (define_split | |
2413 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2414 | (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2415 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2416 | (const_int 0))) | |
2417 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2418 | (ior:SI (not:SI (match_dup 1)) | |
2419 | (not:SI (match_dup 2))))] | |
2420 | "reload_completed" | |
2421 | [(set (match_dup 0) | |
2422 | (ior:SI (not:SI (match_dup 1)) | |
2423 | (not:SI (match_dup 2)))) | |
2424 | (set (match_dup 3) | |
2425 | (compare:CC (match_dup 0) | |
2426 | (const_int 0)))] | |
2427 | "") | |
1fd4e8c1 | 2428 | |
a260abc9 | 2429 | (define_insn "*norsi3_internal1" |
cd2b37d9 | 2430 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
29ae5b89 | 2431 | (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 2432 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] |
1fd4e8c1 RK |
2433 | "" |
2434 | "nor %0,%1,%2") | |
2435 | ||
a260abc9 | 2436 | (define_insn "*norsi3_internal2" |
52d3af72 DE |
2437 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2438 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2439 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) | |
1fd4e8c1 | 2440 | (const_int 0))) |
52d3af72 | 2441 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 2442 | "" |
52d3af72 DE |
2443 | "@ |
2444 | nor. %3,%1,%2 | |
2445 | #" | |
2446 | [(set_attr "type" "compare") | |
2447 | (set_attr "length" "4,8")]) | |
2448 | ||
2449 | (define_split | |
2450 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2451 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2452 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2453 | (const_int 0))) | |
2454 | (clobber (match_scratch:SI 3 ""))] | |
2455 | "reload_completed" | |
2456 | [(set (match_dup 3) | |
2457 | (and:SI (not:SI (match_dup 1)) | |
2458 | (not:SI (match_dup 2)))) | |
2459 | (set (match_dup 0) | |
2460 | (compare:CC (match_dup 3) | |
2461 | (const_int 0)))] | |
2462 | "") | |
1fd4e8c1 | 2463 | |
a260abc9 | 2464 | (define_insn "*norsi3_internal3" |
52d3af72 DE |
2465 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2466 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2467 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))) | |
1fd4e8c1 | 2468 | (const_int 0))) |
52d3af72 DE |
2469 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2470 | (and:SI (not:SI (match_dup 1)) | |
2471 | (not:SI (match_dup 2))))] | |
1fd4e8c1 | 2472 | "" |
52d3af72 DE |
2473 | "@ |
2474 | nor. %0,%1,%2 | |
2475 | #" | |
2476 | [(set_attr "type" "compare") | |
2477 | (set_attr "length" "4,8")]) | |
2478 | ||
2479 | (define_split | |
2480 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2481 | (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
2482 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2483 | (const_int 0))) | |
2484 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2485 | (and:SI (not:SI (match_dup 1)) | |
2486 | (not:SI (match_dup 2))))] | |
2487 | "reload_completed" | |
2488 | [(set (match_dup 0) | |
2489 | (and:SI (not:SI (match_dup 1)) | |
2490 | (not:SI (match_dup 2)))) | |
2491 | (set (match_dup 3) | |
2492 | (compare:CC (match_dup 0) | |
2493 | (const_int 0)))] | |
2494 | "") | |
1fd4e8c1 RK |
2495 | |
2496 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2497 | ;; orders. Don't define forms that only set CR fields because these | |
2498 | ;; would modify an input register. | |
2499 | ||
7cd5235b | 2500 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2501 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2502 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2503 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2504 | (and:SI (match_dup 2) | |
cd2b37d9 | 2505 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2506 | "TARGET_POWER" |
01def764 | 2507 | "maskir %0,%3,%2") |
1fd4e8c1 | 2508 | |
7cd5235b | 2509 | (define_insn "*maskir_internal2" |
242e8072 | 2510 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2511 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2512 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2513 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2514 | (match_dup 2))))] |
ca7f5001 | 2515 | "TARGET_POWER" |
01def764 | 2516 | "maskir %0,%3,%2") |
1fd4e8c1 | 2517 | |
7cd5235b | 2518 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2519 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2520 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2521 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2522 | (and:SI (not:SI (match_dup 2)) |
2523 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2524 | "TARGET_POWER" |
01def764 | 2525 | "maskir %0,%3,%2") |
1fd4e8c1 | 2526 | |
7cd5235b | 2527 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2528 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2529 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2530 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2531 | (and:SI (not:SI (match_dup 2)) | |
2532 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2533 | "TARGET_POWER" |
01def764 | 2534 | "maskir %0,%3,%2") |
1fd4e8c1 | 2535 | |
7cd5235b | 2536 | (define_insn "*maskir_internal5" |
29ae5b89 | 2537 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 2538 | (compare:CC |
29ae5b89 JL |
2539 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2540 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
01def764 | 2541 | (and:SI (match_dup 2) |
29ae5b89 | 2542 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 2543 | (const_int 0))) |
29ae5b89 | 2544 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2545 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2546 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2547 | "TARGET_POWER" |
29ae5b89 JL |
2548 | "maskir. %0,%3,%2" |
2549 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2550 | |
7cd5235b | 2551 | (define_insn "*maskir_internal6" |
29ae5b89 | 2552 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 2553 | (compare:CC |
29ae5b89 JL |
2554 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2555 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2556 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 | 2557 | (match_dup 2))) |
1fd4e8c1 | 2558 | (const_int 0))) |
29ae5b89 | 2559 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2560 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2561 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 2562 | "TARGET_POWER" |
29ae5b89 JL |
2563 | "maskir. %0,%3,%2" |
2564 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2565 | |
7cd5235b | 2566 | (define_insn "*maskir_internal7" |
29ae5b89 | 2567 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
815cdc52 | 2568 | (compare:CC |
29ae5b89 JL |
2569 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
2570 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
815cdc52 | 2571 | (and:SI (not:SI (match_dup 2)) |
29ae5b89 | 2572 | (match_operand:SI 1 "gpc_reg_operand" "0"))) |
815cdc52 | 2573 | (const_int 0))) |
29ae5b89 | 2574 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
815cdc52 MM |
2575 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
2576 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2577 | "TARGET_POWER" | |
29ae5b89 JL |
2578 | "maskir. %0,%3,%2" |
2579 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 2580 | |
7cd5235b | 2581 | (define_insn "*maskir_internal8" |
29ae5b89 | 2582 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 2583 | (compare:CC |
29ae5b89 JL |
2584 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
2585 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
01def764 | 2586 | (and:SI (not:SI (match_dup 2)) |
29ae5b89 | 2587 | (match_operand:SI 1 "gpc_reg_operand" "0"))) |
1fd4e8c1 | 2588 | (const_int 0))) |
29ae5b89 | 2589 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2590 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
2591 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 2592 | "TARGET_POWER" |
29ae5b89 JL |
2593 | "maskir. %0,%3,%2" |
2594 | [(set_attr "type" "compare")]) | |
1fd4e8c1 RK |
2595 | \f |
2596 | ;; Rotate and shift insns, in all their variants. These support shifts, | |
2597 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 MM |
2598 | (define_expand "insv" |
2599 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") | |
2600 | (match_operand:SI 1 "const_int_operand" "i") | |
2601 | (match_operand:SI 2 "const_int_operand" "i")) | |
2602 | (match_operand:SI 3 "gpc_reg_operand" "r"))] | |
2603 | "" | |
2604 | " | |
2605 | { | |
2606 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2607 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2608 | compiler if the address of the structure is taken later. */ | |
2609 | if (GET_CODE (operands[0]) == SUBREG | |
2610 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2611 | FAIL; | |
2612 | }") | |
2613 | ||
2614 | (define_insn "" | |
cd2b37d9 | 2615 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
2616 | (match_operand:SI 1 "const_int_operand" "i") |
2617 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 2618 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
2619 | "" |
2620 | "* | |
2621 | { | |
2622 | int start = INTVAL (operands[2]) & 31; | |
2623 | int size = INTVAL (operands[1]) & 31; | |
2624 | ||
89e9f3a8 MM |
2625 | operands[4] = GEN_INT (32 - start - size); |
2626 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2627 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
1fd4e8c1 RK |
2628 | }") |
2629 | ||
d56d506a RK |
2630 | (define_insn "" |
2631 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") | |
2632 | (match_operand:SI 1 "const_int_operand" "i") | |
2633 | (match_operand:SI 2 "const_int_operand" "i")) | |
2634 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2635 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2636 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2637 | "* |
2638 | { | |
2639 | int shift = INTVAL (operands[4]) & 31; | |
2640 | int start = INTVAL (operands[2]) & 31; | |
2641 | int size = INTVAL (operands[1]) & 31; | |
2642 | ||
89e9f3a8 MM |
2643 | operands[4] = GEN_INT (shift - start - size); |
2644 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2645 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
2646 | }") |
2647 | ||
2648 | (define_insn "" | |
2649 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") | |
2650 | (match_operand:SI 1 "const_int_operand" "i") | |
2651 | (match_operand:SI 2 "const_int_operand" "i")) | |
2652 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2653 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2654 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2655 | "* |
2656 | { | |
2657 | int shift = INTVAL (operands[4]) & 31; | |
2658 | int start = INTVAL (operands[2]) & 31; | |
2659 | int size = INTVAL (operands[1]) & 31; | |
2660 | ||
89e9f3a8 MM |
2661 | operands[4] = GEN_INT (32 - shift - start - size); |
2662 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2663 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
2664 | }") |
2665 | ||
2666 | (define_insn "" | |
2667 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") | |
2668 | (match_operand:SI 1 "const_int_operand" "i") | |
2669 | (match_operand:SI 2 "const_int_operand" "i")) | |
2670 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2671 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 2672 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2673 | "* |
2674 | { | |
2675 | int shift = INTVAL (operands[4]) & 31; | |
2676 | int start = INTVAL (operands[2]) & 31; | |
2677 | int size = INTVAL (operands[1]) & 31; | |
2678 | ||
89e9f3a8 MM |
2679 | operands[4] = GEN_INT (32 - shift - start - size); |
2680 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2681 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
2682 | }") |
2683 | ||
2684 | (define_insn "" | |
2685 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") | |
2686 | (match_operand:SI 1 "const_int_operand" "i") | |
2687 | (match_operand:SI 2 "const_int_operand" "i")) | |
2688 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2689 | (match_operand:SI 4 "const_int_operand" "i") | |
2690 | (match_operand:SI 5 "const_int_operand" "i")))] | |
2691 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
2692 | "* | |
2693 | { | |
2694 | int extract_start = INTVAL (operands[5]) & 31; | |
2695 | int extract_size = INTVAL (operands[4]) & 31; | |
2696 | int insert_start = INTVAL (operands[2]) & 31; | |
2697 | int insert_size = INTVAL (operands[1]) & 31; | |
2698 | ||
2699 | /* Align extract field with insert field */ | |
3a598fbe | 2700 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 2701 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 2702 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
d56d506a RK |
2703 | }") |
2704 | ||
685f3906 DE |
2705 | (define_insn "" |
2706 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
2707 | (match_operand:DI 1 "const_int_operand" "i") | |
2708 | (match_operand:DI 2 "const_int_operand" "i")) | |
2709 | (match_operand:DI 3 "gpc_reg_operand" "r"))] | |
2710 | "TARGET_POWERPC64" | |
2711 | "* | |
2712 | { | |
2713 | int start = INTVAL (operands[2]) & 63; | |
2714 | int size = INTVAL (operands[1]) & 63; | |
2715 | ||
89e9f3a8 | 2716 | operands[2] = GEN_INT (64 - start - size); |
a66078ee | 2717 | return \"rldimi %0,%3,%H2,%H1\"; |
685f3906 DE |
2718 | }") |
2719 | ||
034c1be0 MM |
2720 | (define_expand "extzv" |
2721 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2722 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2723 | (match_operand:SI 2 "const_int_operand" "i") | |
2724 | (match_operand:SI 3 "const_int_operand" "i")))] | |
2725 | "" | |
2726 | " | |
2727 | { | |
2728 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2729 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2730 | compiler if the address of the structure is taken later. */ | |
2731 | if (GET_CODE (operands[0]) == SUBREG | |
2732 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2733 | FAIL; | |
2734 | }") | |
2735 | ||
2736 | (define_insn "" | |
cd2b37d9 RK |
2737 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2738 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2739 | (match_operand:SI 2 "const_int_operand" "i") |
2740 | (match_operand:SI 3 "const_int_operand" "i")))] | |
2741 | "" | |
2742 | "* | |
2743 | { | |
2744 | int start = INTVAL (operands[3]) & 31; | |
2745 | int size = INTVAL (operands[2]) & 31; | |
2746 | ||
2747 | if (start + size >= 32) | |
2748 | operands[3] = const0_rtx; | |
2749 | else | |
89e9f3a8 | 2750 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 2751 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
2752 | }") |
2753 | ||
2754 | (define_insn "" | |
29ae5b89 JL |
2755 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
2756 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2757 | (match_operand:SI 2 "const_int_operand" "i") | |
2758 | (match_operand:SI 3 "const_int_operand" "i")) | |
1fd4e8c1 | 2759 | (const_int 0))) |
29ae5b89 | 2760 | (clobber (match_scratch:SI 4 "=r"))] |
1fd4e8c1 RK |
2761 | "" |
2762 | "* | |
2763 | { | |
2764 | int start = INTVAL (operands[3]) & 31; | |
2765 | int size = INTVAL (operands[2]) & 31; | |
2766 | ||
a7a975e1 RK |
2767 | /* If the bitfield being tested fits in the upper or lower half of a |
2768 | word, it is possible to use andiu. or andil. to test it. This is | |
2769 | useful because the condition register set-use delay is smaller for | |
2770 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
2771 | position is 0 because the LT and GT bits may be set wrong. */ | |
2772 | ||
2773 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 2774 | { |
3a598fbe | 2775 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
2776 | - (1 << (16 - (start & 15) - size)))); |
2777 | if (start < 16) | |
ca7f5001 | 2778 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 2779 | else |
ca7f5001 | 2780 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 2781 | } |
7e69e155 | 2782 | |
1fd4e8c1 RK |
2783 | if (start + size >= 32) |
2784 | operands[3] = const0_rtx; | |
2785 | else | |
89e9f3a8 | 2786 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 2787 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 2788 | }" |
29ae5b89 | 2789 | [(set_attr "type" "compare")]) |
1fd4e8c1 RK |
2790 | |
2791 | (define_insn "" | |
29ae5b89 JL |
2792 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
2793 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2794 | (match_operand:SI 2 "const_int_operand" "i") | |
2795 | (match_operand:SI 3 "const_int_operand" "i")) | |
1fd4e8c1 | 2796 | (const_int 0))) |
29ae5b89 | 2797 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2798 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
2799 | "" | |
2800 | "* | |
2801 | { | |
2802 | int start = INTVAL (operands[3]) & 31; | |
2803 | int size = INTVAL (operands[2]) & 31; | |
2804 | ||
a7a975e1 | 2805 | if (start >= 16 && start + size == 32) |
df031c43 | 2806 | { |
89e9f3a8 | 2807 | operands[3] = GEN_INT ((1 << (32 - start)) - 1); |
ca7f5001 | 2808 | return \"{andil.|andi.} %0,%1,%3\"; |
df031c43 | 2809 | } |
7e69e155 | 2810 | |
1fd4e8c1 RK |
2811 | if (start + size >= 32) |
2812 | operands[3] = const0_rtx; | |
2813 | else | |
89e9f3a8 | 2814 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 2815 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
2816 | }" |
2817 | [(set_attr "type" "delayed_compare")]) | |
2818 | ||
685f3906 DE |
2819 | (define_insn "" |
2820 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
2821 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2822 | (match_operand:DI 2 "const_int_operand" "i") | |
2823 | (match_operand:DI 3 "const_int_operand" "i")))] | |
2824 | "TARGET_POWERPC64" | |
2825 | "* | |
2826 | { | |
2827 | int start = INTVAL (operands[3]) & 63; | |
2828 | int size = INTVAL (operands[2]) & 63; | |
2829 | ||
2830 | if (start + size >= 64) | |
2831 | operands[3] = const0_rtx; | |
2832 | else | |
89e9f3a8 MM |
2833 | operands[3] = GEN_INT (start + size); |
2834 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
2835 | return \"rldicl %0,%1,%3,%2\"; |
2836 | }") | |
2837 | ||
2838 | (define_insn "" | |
29ae5b89 JL |
2839 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
2840 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2841 | (match_operand:DI 2 "const_int_operand" "i") | |
2842 | (match_operand:DI 3 "const_int_operand" "i")) | |
685f3906 | 2843 | (const_int 0))) |
29ae5b89 | 2844 | (clobber (match_scratch:DI 4 "=r"))] |
685f3906 DE |
2845 | "TARGET_POWERPC64" |
2846 | "* | |
2847 | { | |
2848 | int start = INTVAL (operands[3]) & 63; | |
2849 | int size = INTVAL (operands[2]) & 63; | |
2850 | ||
2851 | if (start + size >= 64) | |
2852 | operands[3] = const0_rtx; | |
2853 | else | |
89e9f3a8 MM |
2854 | operands[3] = GEN_INT (start + size); |
2855 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
2856 | return \"rldicl. %4,%1,%3,%2\"; |
2857 | }") | |
2858 | ||
2859 | (define_insn "" | |
29ae5b89 JL |
2860 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
2861 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2862 | (match_operand:DI 2 "const_int_operand" "i") | |
2863 | (match_operand:DI 3 "const_int_operand" "i")) | |
685f3906 | 2864 | (const_int 0))) |
29ae5b89 | 2865 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 DE |
2866 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
2867 | "TARGET_POWERPC64" | |
2868 | "* | |
2869 | { | |
2870 | int start = INTVAL (operands[3]) & 63; | |
2871 | int size = INTVAL (operands[2]) & 63; | |
2872 | ||
2873 | if (start + size >= 64) | |
2874 | operands[3] = const0_rtx; | |
2875 | else | |
89e9f3a8 MM |
2876 | operands[3] = GEN_INT (start + size); |
2877 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
2878 | return \"rldicl. %0,%1,%3,%2\"; |
2879 | }") | |
2880 | ||
1fd4e8c1 | 2881 | (define_insn "rotlsi3" |
cd2b37d9 RK |
2882 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2883 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2884 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
2885 | "" | |
ca7f5001 | 2886 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 2887 | |
a260abc9 | 2888 | (define_insn "*rotlsi3_internal2" |
29ae5b89 JL |
2889 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
2890 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2891 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
1fd4e8c1 | 2892 | (const_int 0))) |
29ae5b89 | 2893 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 2894 | "" |
29ae5b89 JL |
2895 | "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff" |
2896 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 2897 | |
a260abc9 | 2898 | (define_insn "*rotlsi3_internal3" |
29ae5b89 JL |
2899 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
2900 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2901 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
1fd4e8c1 | 2902 | (const_int 0))) |
29ae5b89 | 2903 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2904 | (rotate:SI (match_dup 1) (match_dup 2)))] |
2905 | "" | |
29ae5b89 JL |
2906 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff" |
2907 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 2908 | |
a260abc9 | 2909 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
2910 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2911 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2912 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
2913 | (match_operand:SI 3 "mask_operand" "L")))] | |
2914 | "" | |
ca7f5001 | 2915 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 2916 | |
a260abc9 | 2917 | (define_insn "*rotlsi3_internal5" |
29ae5b89 | 2918 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 2919 | (compare:CC (and:SI |
29ae5b89 JL |
2920 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2921 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
2922 | (match_operand:SI 3 "mask_operand" "L")) | |
1fd4e8c1 | 2923 | (const_int 0))) |
29ae5b89 | 2924 | (clobber (match_scratch:SI 4 "=r"))] |
1fd4e8c1 | 2925 | "" |
29ae5b89 JL |
2926 | "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3" |
2927 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 2928 | |
a260abc9 | 2929 | (define_insn "*rotlsi3_internal6" |
29ae5b89 | 2930 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 2931 | (compare:CC (and:SI |
29ae5b89 JL |
2932 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2933 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
2934 | (match_operand:SI 3 "mask_operand" "L")) | |
1fd4e8c1 | 2935 | (const_int 0))) |
29ae5b89 | 2936 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2937 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
2938 | "" | |
29ae5b89 JL |
2939 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3" |
2940 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 2941 | |
a260abc9 | 2942 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 2943 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2944 | (zero_extend:SI |
2945 | (subreg:QI | |
cd2b37d9 | 2946 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2947 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
2948 | "" | |
ca7f5001 | 2949 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 2950 | |
a260abc9 | 2951 | (define_insn "*rotlsi3_internal8" |
29ae5b89 | 2952 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
2953 | (compare:CC (zero_extend:SI |
2954 | (subreg:QI | |
29ae5b89 JL |
2955 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2956 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) | |
1fd4e8c1 | 2957 | (const_int 0))) |
29ae5b89 | 2958 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 2959 | "" |
29ae5b89 JL |
2960 | "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff" |
2961 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 2962 | |
a260abc9 | 2963 | (define_insn "*rotlsi3_internal9" |
29ae5b89 | 2964 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
2965 | (compare:CC (zero_extend:SI |
2966 | (subreg:QI | |
29ae5b89 JL |
2967 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2968 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) | |
1fd4e8c1 | 2969 | (const_int 0))) |
29ae5b89 | 2970 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2971 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
2972 | "" | |
29ae5b89 JL |
2973 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff" |
2974 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 2975 | |
a260abc9 | 2976 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 2977 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
2978 | (zero_extend:SI |
2979 | (subreg:HI | |
cd2b37d9 | 2980 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
2981 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
2982 | "" | |
ca7f5001 | 2983 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 2984 | |
a260abc9 | 2985 | (define_insn "*rotlsi3_internal11" |
29ae5b89 | 2986 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
2987 | (compare:CC (zero_extend:SI |
2988 | (subreg:HI | |
29ae5b89 JL |
2989 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
2990 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) | |
1fd4e8c1 | 2991 | (const_int 0))) |
29ae5b89 | 2992 | (clobber (match_scratch:SI 3 "=r"))] |
1fd4e8c1 | 2993 | "" |
29ae5b89 JL |
2994 | "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff" |
2995 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 2996 | |
a260abc9 | 2997 | (define_insn "*rotlsi3_internal12" |
29ae5b89 | 2998 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
2999 | (compare:CC (zero_extend:SI |
3000 | (subreg:HI | |
29ae5b89 JL |
3001 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3002 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) | |
1fd4e8c1 | 3003 | (const_int 0))) |
29ae5b89 | 3004 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3005 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3006 | "" | |
29ae5b89 JL |
3007 | "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff" |
3008 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3009 | |
3010 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3011 | ;; SHIFT_COUNT_TRUNCATED. | |
3012 | ||
ca7f5001 RK |
3013 | (define_expand "ashlsi3" |
3014 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3015 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3016 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3017 | "" | |
3018 | " | |
3019 | { | |
3020 | if (TARGET_POWER) | |
3021 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3022 | else | |
25c341fa | 3023 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3024 | DONE; |
3025 | }") | |
3026 | ||
3027 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3028 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3029 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3030 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3031 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3032 | "TARGET_POWER" |
1fd4e8c1 RK |
3033 | "@ |
3034 | sle %0,%1,%2 | |
ca7f5001 RK |
3035 | {sli|slwi} %0,%1,%h2" |
3036 | [(set_attr "length" "8")]) | |
3037 | ||
25c341fa | 3038 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3039 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3040 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3041 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3042 | "! TARGET_POWER" |
d904e9ed | 3043 | "{sl|slw}%I2 %0,%1,%h2" |
b19003d8 | 3044 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
3045 | |
3046 | (define_insn "" | |
29ae5b89 JL |
3047 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
3048 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3049 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) | |
1fd4e8c1 | 3050 | (const_int 0))) |
29ae5b89 JL |
3051 | (clobber (match_scratch:SI 3 "=r,r")) |
3052 | (clobber (match_scratch:SI 4 "=q,X"))] | |
ca7f5001 | 3053 | "TARGET_POWER" |
1fd4e8c1 RK |
3054 | "@ |
3055 | sle. %3,%1,%2 | |
29ae5b89 JL |
3056 | {sli.|slwi.} %3,%1,%h2" |
3057 | [(set_attr "type" "delayed_compare")]) | |
25c341fa | 3058 | |
ca7f5001 | 3059 | (define_insn "" |
29ae5b89 JL |
3060 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
3061 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3062 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
ca7f5001 | 3063 | (const_int 0))) |
29ae5b89 | 3064 | (clobber (match_scratch:SI 3 "=r"))] |
8ffd9c51 | 3065 | "! TARGET_POWER" |
29ae5b89 JL |
3066 | "{sl|slw}%I2. %3,%1,%h2" |
3067 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3068 | |
3069 | (define_insn "" | |
29ae5b89 JL |
3070 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
3071 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3072 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) | |
1fd4e8c1 | 3073 | (const_int 0))) |
29ae5b89 | 3074 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3075 | (ashift:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 3076 | (clobber (match_scratch:SI 4 "=q,X"))] |
ca7f5001 | 3077 | "TARGET_POWER" |
1fd4e8c1 RK |
3078 | "@ |
3079 | sle. %0,%1,%2 | |
29ae5b89 | 3080 | {sli.|slwi.} %0,%1,%h2" |
ca7f5001 | 3081 | [(set_attr "type" "delayed_compare")]) |
25c341fa | 3082 | |
ca7f5001 | 3083 | (define_insn "" |
29ae5b89 JL |
3084 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
3085 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3086 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
ca7f5001 | 3087 | (const_int 0))) |
29ae5b89 | 3088 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ca7f5001 | 3089 | (ashift:SI (match_dup 1) (match_dup 2)))] |
8ffd9c51 | 3090 | "! TARGET_POWER" |
d904e9ed | 3091 | "{sl|slw}%I2. %0,%1,%h2" |
1fd4e8c1 RK |
3092 | [(set_attr "type" "delayed_compare")]) |
3093 | ||
3094 | (define_insn "" | |
cd2b37d9 RK |
3095 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3096 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3097 | (match_operand:SI 2 "const_int_operand" "i")) |
3098 | (match_operand:SI 3 "mask_operand" "L")))] | |
3099 | "includes_lshift_p (operands[2], operands[3])" | |
d56d506a | 3100 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3101 | |
3102 | (define_insn "" | |
29ae5b89 | 3103 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 3104 | (compare:CC |
29ae5b89 JL |
3105 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3106 | (match_operand:SI 2 "const_int_operand" "i")) | |
3107 | (match_operand:SI 3 "mask_operand" "L")) | |
1fd4e8c1 | 3108 | (const_int 0))) |
29ae5b89 | 3109 | (clobber (match_scratch:SI 4 "=r"))] |
1fd4e8c1 | 3110 | "includes_lshift_p (operands[2], operands[3])" |
29ae5b89 | 3111 | "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3" |
1fd4e8c1 RK |
3112 | [(set_attr "type" "delayed_compare")]) |
3113 | ||
3114 | (define_insn "" | |
29ae5b89 | 3115 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 3116 | (compare:CC |
29ae5b89 JL |
3117 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3118 | (match_operand:SI 2 "const_int_operand" "i")) | |
3119 | (match_operand:SI 3 "mask_operand" "L")) | |
1fd4e8c1 | 3120 | (const_int 0))) |
29ae5b89 | 3121 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3122 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
3123 | "includes_lshift_p (operands[2], operands[3])" | |
29ae5b89 | 3124 | "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3" |
1fd4e8c1 RK |
3125 | [(set_attr "type" "delayed_compare")]) |
3126 | ||
ca7f5001 | 3127 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3128 | ;; "sli x,x,0". |
ca7f5001 RK |
3129 | (define_expand "lshrsi3" |
3130 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3131 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3132 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3133 | "" | |
3134 | " | |
3135 | { | |
3136 | if (TARGET_POWER) | |
3137 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
3138 | else | |
25c341fa | 3139 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3140 | DONE; |
3141 | }") | |
3142 | ||
3143 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
3144 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
3145 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3146 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
3147 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 3148 | "TARGET_POWER" |
1fd4e8c1 RK |
3149 | "@ |
3150 | sre %0,%1,%2 | |
bdf423cb | 3151 | mr %0,%1 |
ca7f5001 RK |
3152 | {s%A2i|s%A2wi} %0,%1,%h2") |
3153 | ||
25c341fa | 3154 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
3155 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3156 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3157 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 3158 | "! TARGET_POWER" |
bdf423cb MM |
3159 | "@ |
3160 | mr %0,%1 | |
3161 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
3162 | |
3163 | (define_insn "" | |
29ae5b89 JL |
3164 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x") |
3165 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3166 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")) | |
1fd4e8c1 | 3167 | (const_int 0))) |
29ae5b89 JL |
3168 | (clobber (match_scratch:SI 3 "=r,X,r")) |
3169 | (clobber (match_scratch:SI 4 "=q,X,X"))] | |
ca7f5001 | 3170 | "TARGET_POWER" |
1fd4e8c1 | 3171 | "@ |
29ae5b89 JL |
3172 | sre. %3,%1,%2 |
3173 | mr. %1,%1 | |
3174 | {s%A2i.|s%A2wi.} %3,%1,%h2" | |
3175 | [(set_attr "type" "delayed_compare")]) | |
ca7f5001 RK |
3176 | |
3177 | (define_insn "" | |
29ae5b89 JL |
3178 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
3179 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3180 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")) | |
ca7f5001 | 3181 | (const_int 0))) |
29ae5b89 | 3182 | (clobber (match_scratch:SI 3 "=X,r"))] |
25c341fa | 3183 | "! TARGET_POWER" |
bdf423cb MM |
3184 | "@ |
3185 | mr. %1,%1 | |
29ae5b89 JL |
3186 | {sr|srw}%I2. %3,%1,%h2" |
3187 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3188 | |
3189 | (define_insn "" | |
29ae5b89 JL |
3190 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x") |
3191 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3192 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")) | |
1fd4e8c1 | 3193 | (const_int 0))) |
29ae5b89 | 3194 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1fd4e8c1 | 3195 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 3196 | (clobber (match_scratch:SI 4 "=q,X,X"))] |
ca7f5001 | 3197 | "TARGET_POWER" |
1fd4e8c1 | 3198 | "@ |
29ae5b89 JL |
3199 | sre. %0,%1,%2 |
3200 | mr. %0,%1 | |
3201 | {s%A2i.|s%A2wi.} %0,%1,%h2" | |
3202 | [(set_attr "type" "delayed_compare")]) | |
ca7f5001 RK |
3203 | |
3204 | (define_insn "" | |
29ae5b89 JL |
3205 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
3206 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3207 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")) | |
815cdc52 | 3208 | (const_int 0))) |
29ae5b89 JL |
3209 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3210 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
3211 | "! TARGET_POWER" | |
3212 | "@ | |
3213 | mr. %0,%1 | |
3214 | {sr|srw}%I2. %0,%1,%h2" | |
3215 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3216 | |
3217 | (define_insn "" | |
cd2b37d9 RK |
3218 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3219 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3220 | (match_operand:SI 2 "const_int_operand" "i")) |
3221 | (match_operand:SI 3 "mask_operand" "L")))] | |
3222 | "includes_rshift_p (operands[2], operands[3])" | |
ca7f5001 | 3223 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
3224 | |
3225 | (define_insn "" | |
29ae5b89 | 3226 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 3227 | (compare:CC |
29ae5b89 JL |
3228 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3229 | (match_operand:SI 2 "const_int_operand" "i")) | |
3230 | (match_operand:SI 3 "mask_operand" "L")) | |
1fd4e8c1 | 3231 | (const_int 0))) |
29ae5b89 | 3232 | (clobber (match_scratch:SI 4 "=r"))] |
1fd4e8c1 | 3233 | "includes_rshift_p (operands[2], operands[3])" |
29ae5b89 JL |
3234 | "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3" |
3235 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3236 | |
3237 | (define_insn "" | |
29ae5b89 | 3238 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 3239 | (compare:CC |
29ae5b89 JL |
3240 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3241 | (match_operand:SI 2 "const_int_operand" "i")) | |
3242 | (match_operand:SI 3 "mask_operand" "L")) | |
1fd4e8c1 | 3243 | (const_int 0))) |
29ae5b89 | 3244 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3245 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
3246 | "includes_rshift_p (operands[2], operands[3])" | |
29ae5b89 JL |
3247 | "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3" |
3248 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3249 | |
3250 | (define_insn "" | |
cd2b37d9 | 3251 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3252 | (zero_extend:SI |
3253 | (subreg:QI | |
cd2b37d9 | 3254 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 3255 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 3256 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 3257 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
3258 | |
3259 | (define_insn "" | |
29ae5b89 | 3260 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
3261 | (compare:CC |
3262 | (zero_extend:SI | |
3263 | (subreg:QI | |
29ae5b89 JL |
3264 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3265 | (match_operand:SI 2 "const_int_operand" "i")) 0)) | |
1fd4e8c1 | 3266 | (const_int 0))) |
29ae5b89 | 3267 | (clobber (match_scratch:SI 3 "=r"))] |
89e9f3a8 | 3268 | "includes_rshift_p (operands[2], GEN_INT (255))" |
29ae5b89 JL |
3269 | "{rlinm.|rlwinm.} %3,%1,%s2,0xff" |
3270 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3271 | |
3272 | (define_insn "" | |
29ae5b89 | 3273 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
3274 | (compare:CC |
3275 | (zero_extend:SI | |
3276 | (subreg:QI | |
29ae5b89 JL |
3277 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3278 | (match_operand:SI 2 "const_int_operand" "i")) 0)) | |
1fd4e8c1 | 3279 | (const_int 0))) |
29ae5b89 | 3280 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 3281 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 3282 | "includes_rshift_p (operands[2], GEN_INT (255))" |
29ae5b89 JL |
3283 | "{rlinm.|rlwinm.} %0,%1,%s2,0xff" |
3284 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3285 | |
3286 | (define_insn "" | |
cd2b37d9 | 3287 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3288 | (zero_extend:SI |
3289 | (subreg:HI | |
cd2b37d9 | 3290 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 3291 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 3292 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 3293 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
3294 | |
3295 | (define_insn "" | |
29ae5b89 | 3296 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
3297 | (compare:CC |
3298 | (zero_extend:SI | |
3299 | (subreg:HI | |
29ae5b89 JL |
3300 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3301 | (match_operand:SI 2 "const_int_operand" "i")) 0)) | |
1fd4e8c1 | 3302 | (const_int 0))) |
29ae5b89 | 3303 | (clobber (match_scratch:SI 3 "=r"))] |
89e9f3a8 | 3304 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
29ae5b89 JL |
3305 | "{rlinm.|rlwinm.} %3,%1,%s2,0xffff" |
3306 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3307 | |
3308 | (define_insn "" | |
29ae5b89 | 3309 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
3310 | (compare:CC |
3311 | (zero_extend:SI | |
3312 | (subreg:HI | |
29ae5b89 JL |
3313 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
3314 | (match_operand:SI 2 "const_int_operand" "i")) 0)) | |
1fd4e8c1 | 3315 | (const_int 0))) |
29ae5b89 | 3316 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 3317 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 3318 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 3319 | "{rlinm.|rlwinm.} %0,%1,%s2,0xffff" |
1fd4e8c1 RK |
3320 | [(set_attr "type" "delayed_compare")]) |
3321 | ||
3322 | (define_insn "" | |
cd2b37d9 | 3323 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 3324 | (const_int 1) |
cd2b37d9 RK |
3325 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
3326 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3327 | (const_int 31)))] |
ca7f5001 | 3328 | "TARGET_POWER" |
1fd4e8c1 RK |
3329 | "rrib %0,%1,%2") |
3330 | ||
3331 | (define_insn "" | |
cd2b37d9 | 3332 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 3333 | (const_int 1) |
cd2b37d9 RK |
3334 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
3335 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3336 | (const_int 31)))] |
ca7f5001 | 3337 | "TARGET_POWER" |
1fd4e8c1 RK |
3338 | "rrib %0,%1,%2") |
3339 | ||
3340 | (define_insn "" | |
cd2b37d9 | 3341 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 3342 | (const_int 1) |
cd2b37d9 RK |
3343 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
3344 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3345 | (const_int 1) |
3346 | (const_int 0)))] | |
ca7f5001 | 3347 | "TARGET_POWER" |
1fd4e8c1 RK |
3348 | "rrib %0,%1,%2") |
3349 | ||
ca7f5001 RK |
3350 | (define_expand "ashrsi3" |
3351 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
3352 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3353 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
3354 | "" | |
3355 | " | |
3356 | { | |
3357 | if (TARGET_POWER) | |
3358 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
3359 | else | |
25c341fa | 3360 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3361 | DONE; |
3362 | }") | |
3363 | ||
3364 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
3365 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3366 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3367 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3368 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3369 | "TARGET_POWER" |
1fd4e8c1 RK |
3370 | "@ |
3371 | srea %0,%1,%2 | |
ca7f5001 RK |
3372 | {srai|srawi} %0,%1,%h2") |
3373 | ||
25c341fa | 3374 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
3375 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3376 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3377 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3378 | "! TARGET_POWER" |
d904e9ed | 3379 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3380 | |
3381 | (define_insn "" | |
29ae5b89 JL |
3382 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
3383 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3384 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) | |
1fd4e8c1 | 3385 | (const_int 0))) |
29ae5b89 JL |
3386 | (clobber (match_scratch:SI 3 "=r,r")) |
3387 | (clobber (match_scratch:SI 4 "=q,X"))] | |
ca7f5001 | 3388 | "TARGET_POWER" |
1fd4e8c1 RK |
3389 | "@ |
3390 | srea. %3,%1,%2 | |
29ae5b89 JL |
3391 | {srai.|srawi.} %3,%1,%h2" |
3392 | [(set_attr "type" "delayed_compare")]) | |
ca7f5001 RK |
3393 | |
3394 | (define_insn "" | |
29ae5b89 JL |
3395 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
3396 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3397 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
ca7f5001 | 3398 | (const_int 0))) |
29ae5b89 | 3399 | (clobber (match_scratch:SI 3 "=r"))] |
25c341fa | 3400 | "! TARGET_POWER" |
29ae5b89 JL |
3401 | "{sra|sraw}%I2. %3,%1,%h2" |
3402 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3403 | |
3404 | (define_insn "" | |
29ae5b89 JL |
3405 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
3406 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3407 | (match_operand:SI 2 "reg_or_cint_operand" "r,i")) | |
1fd4e8c1 | 3408 | (const_int 0))) |
29ae5b89 | 3409 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3410 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 3411 | (clobber (match_scratch:SI 4 "=q,X"))] |
ca7f5001 | 3412 | "TARGET_POWER" |
1fd4e8c1 RK |
3413 | "@ |
3414 | srea. %0,%1,%2 | |
29ae5b89 JL |
3415 | {srai.|srawi.} %0,%1,%h2" |
3416 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 | 3417 | |
ca7f5001 | 3418 | (define_insn "" |
29ae5b89 JL |
3419 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
3420 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3421 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
ca7f5001 | 3422 | (const_int 0))) |
29ae5b89 | 3423 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ca7f5001 | 3424 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 3425 | "! TARGET_POWER" |
29ae5b89 JL |
3426 | "{sra|sraw}%I2. %0,%1,%h2" |
3427 | [(set_attr "type" "delayed_compare")]) | |
1fd4e8c1 RK |
3428 | \f |
3429 | ;; Floating-point insns, excluding normal data motion. | |
3430 | ;; | |
ca7f5001 RK |
3431 | ;; PowerPC has a full set of single-precision floating point instructions. |
3432 | ;; | |
3433 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
3434 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
3435 | ;; The only conversions we will do will be when storing to memory. In that | |
3436 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
3437 | ;; |
3438 | ;; Note that when we store into a single-precision memory location, we need to | |
3439 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
3440 | ;; need a scratch register for the frsp. But this is difficult when the store | |
3441 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
3442 | ;; this case, we just lose precision that we would have otherwise gotten but | |
3443 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
3444 | ||
e8112008 | 3445 | (define_insn "extendsfdf2" |
cd2b37d9 | 3446 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
e8112008 | 3447 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] |
d14a6d05 | 3448 | "TARGET_HARD_FLOAT" |
e8112008 | 3449 | "* |
5c30aff8 | 3450 | { |
e8112008 RK |
3451 | if (REGNO (operands[0]) == REGNO (operands[1])) |
3452 | return \"\"; | |
3453 | else | |
3454 | return \"fmr %0,%1\"; | |
3455 | }" | |
3456 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
3457 | |
3458 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
3459 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3460 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3461 | "TARGET_HARD_FLOAT" |
dcac138d | 3462 | "frsp %0,%1" |
1fd4e8c1 RK |
3463 | [(set_attr "type" "fp")]) |
3464 | ||
455350f4 RK |
3465 | (define_insn "aux_truncdfsf2" |
3466 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3467 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))] | |
3468 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" | |
3469 | "frsp %0,%1" | |
3470 | [(set_attr "type" "fp")]) | |
3471 | ||
1fd4e8c1 | 3472 | (define_insn "negsf2" |
cd2b37d9 RK |
3473 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3474 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3475 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3476 | "fneg %0,%1" |
3477 | [(set_attr "type" "fp")]) | |
3478 | ||
3479 | (define_insn "abssf2" | |
cd2b37d9 RK |
3480 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3481 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3482 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3483 | "fabs %0,%1" |
3484 | [(set_attr "type" "fp")]) | |
3485 | ||
3486 | (define_insn "" | |
cd2b37d9 RK |
3487 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3488 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 3489 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3490 | "fnabs %0,%1" |
3491 | [(set_attr "type" "fp")]) | |
3492 | ||
ca7f5001 RK |
3493 | (define_expand "addsf3" |
3494 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3495 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
3496 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 3497 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
3498 | "") |
3499 | ||
3500 | (define_insn "" | |
cd2b37d9 RK |
3501 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3502 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3503 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3504 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3505 | "fadds %0,%1,%2" |
ca7f5001 RK |
3506 | [(set_attr "type" "fp")]) |
3507 | ||
3508 | (define_insn "" | |
3509 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3510 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3511 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3512 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3513 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
3514 | [(set_attr "type" "fp")]) |
3515 | ||
3516 | (define_expand "subsf3" | |
3517 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3518 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
3519 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 3520 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
3521 | "") |
3522 | ||
3523 | (define_insn "" | |
3524 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3525 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
3526 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3527 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3528 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
3529 | [(set_attr "type" "fp")]) |
3530 | ||
ca7f5001 | 3531 | (define_insn "" |
cd2b37d9 RK |
3532 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3533 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
3534 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3535 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3536 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
3537 | [(set_attr "type" "fp")]) |
3538 | ||
3539 | (define_expand "mulsf3" | |
3540 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3541 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
3542 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 3543 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
3544 | "") |
3545 | ||
3546 | (define_insn "" | |
3547 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3548 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3549 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3550 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3551 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
3552 | [(set_attr "type" "fp")]) |
3553 | ||
ca7f5001 | 3554 | (define_insn "" |
cd2b37d9 RK |
3555 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3556 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3557 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3558 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3559 | "{fm|fmul} %0,%1,%2" |
0780f386 | 3560 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 3561 | |
ca7f5001 RK |
3562 | (define_expand "divsf3" |
3563 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3564 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
3565 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 3566 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
3567 | "") |
3568 | ||
3569 | (define_insn "" | |
cd2b37d9 RK |
3570 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3571 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
3572 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3573 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3574 | "fdivs %0,%1,%2" |
ca7f5001 RK |
3575 | [(set_attr "type" "sdiv")]) |
3576 | ||
3577 | (define_insn "" | |
3578 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3579 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
3580 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3581 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 3582 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 3583 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
3584 | |
3585 | (define_insn "" | |
cd2b37d9 RK |
3586 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3587 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3588 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3589 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 3590 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3591 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
3592 | [(set_attr "type" "fp")]) |
3593 | ||
3594 | (define_insn "" | |
3595 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3596 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3597 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3598 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 3599 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3600 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 3601 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3602 | |
3603 | (define_insn "" | |
cd2b37d9 RK |
3604 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3605 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3606 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3607 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 3608 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3609 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
3610 | [(set_attr "type" "fp")]) |
3611 | ||
3612 | (define_insn "" | |
3613 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3614 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3615 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3616 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 3617 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3618 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 3619 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3620 | |
3621 | (define_insn "" | |
cd2b37d9 RK |
3622 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3623 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3624 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3625 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 3626 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3627 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
3628 | [(set_attr "type" "fp")]) |
3629 | ||
3630 | (define_insn "" | |
3631 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3632 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3633 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3634 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 3635 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3636 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 3637 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3638 | |
3639 | (define_insn "" | |
cd2b37d9 RK |
3640 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3641 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3642 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3643 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 3644 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3645 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
3646 | [(set_attr "type" "fp")]) |
3647 | ||
3648 | (define_insn "" | |
3649 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3650 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
3651 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
3652 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 3653 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 3654 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 3655 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 3656 | |
ca7f5001 RK |
3657 | (define_expand "sqrtsf2" |
3658 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3659 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 3660 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
3661 | "") |
3662 | ||
3663 | (define_insn "" | |
3664 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3665 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3666 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT" |
ca7f5001 RK |
3667 | "fsqrts %0,%1" |
3668 | [(set_attr "type" "ssqrt")]) | |
3669 | ||
3670 | (define_insn "" | |
3671 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3672 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3673 | "TARGET_POWER2 && TARGET_HARD_FLOAT" |
ca7f5001 RK |
3674 | "fsqrt %0,%1" |
3675 | [(set_attr "type" "dsqrt")]) | |
3676 | ||
94d7001a RK |
3677 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
3678 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
3679 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
3680 | ;; combine. |
3681 | (define_expand "maxsf3" | |
3682 | [(set (match_dup 3) | |
3683 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
3684 | (match_operand:SF 2 "gpc_reg_operand" ""))) | |
3685 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
3686 | (if_then_else:SF (ge (match_dup 3) | |
3687 | (const_int 0)) | |
3688 | (match_dup 1) | |
3689 | (match_dup 2)))] | |
d14a6d05 | 3690 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3691 | " |
3692 | { operands[3] = gen_reg_rtx (SFmode); }") | |
2f607b94 | 3693 | |
8e871c05 RK |
3694 | (define_split |
3695 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3696 | (smax:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
f63184ac | 3697 | (match_operand:SF 2 "gpc_reg_operand" ""))) |
8e871c05 | 3698 | (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 3699 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3700 | [(set (match_dup 3) |
3701 | (minus:SF (match_dup 1) (match_dup 2))) | |
a81bd72f | 3702 | (set (match_dup 0) |
8e871c05 RK |
3703 | (if_then_else:SF (ge (match_dup 3) |
3704 | (const_int 0)) | |
3705 | (match_dup 1) | |
3706 | (match_dup 2)))] | |
3707 | "") | |
2f607b94 | 3708 | |
8e871c05 RK |
3709 | (define_expand "minsf3" |
3710 | [(set (match_dup 3) | |
3711 | (minus:SF (match_operand:SF 2 "gpc_reg_operand" "") | |
3712 | (match_operand:SF 1 "gpc_reg_operand" ""))) | |
3713 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
3714 | (if_then_else:SF (ge (match_dup 3) | |
3715 | (const_int 0)) | |
3716 | (match_dup 1) | |
3717 | (match_dup 2)))] | |
d14a6d05 | 3718 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3719 | " |
3720 | { operands[3] = gen_reg_rtx (SFmode); }") | |
2f607b94 | 3721 | |
8e871c05 RK |
3722 | (define_split |
3723 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
3724 | (smin:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
f63184ac | 3725 | (match_operand:SF 2 "gpc_reg_operand" ""))) |
8e871c05 | 3726 | (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 3727 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3728 | [(set (match_dup 3) |
3729 | (minus:SF (match_dup 2) (match_dup 1))) | |
a81bd72f | 3730 | (set (match_dup 0) |
8e871c05 RK |
3731 | (if_then_else:SF (ge (match_dup 3) |
3732 | (const_int 0)) | |
3733 | (match_dup 1) | |
3734 | (match_dup 2)))] | |
3735 | "") | |
2f607b94 | 3736 | |
94d7001a RK |
3737 | (define_expand "movsfcc" |
3738 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3739 | (if_then_else:SF (match_operand 1 "comparison_operator" "") | |
3740 | (match_operand:SF 2 "gpc_reg_operand" "f") | |
3741 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3742 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
3743 | " |
3744 | { | |
3745 | rtx temp, op0, op1; | |
3746 | enum rtx_code code = GET_CODE (operands[1]); | |
3747 | if (! rs6000_compare_fp_p) | |
3748 | FAIL; | |
3749 | switch (code) | |
3750 | { | |
3751 | case GE: case EQ: case NE: | |
3752 | op0 = rs6000_compare_op0; | |
3753 | op1 = rs6000_compare_op1; | |
3754 | break; | |
3755 | case GT: | |
3756 | op0 = rs6000_compare_op1; | |
3757 | op1 = rs6000_compare_op0; | |
3758 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
3759 | break; | |
3760 | case LE: | |
3761 | op0 = rs6000_compare_op1; | |
3762 | op1 = rs6000_compare_op0; | |
3763 | break; | |
3764 | case LT: | |
3765 | op0 = rs6000_compare_op0; | |
3766 | op1 = rs6000_compare_op1; | |
3767 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
3768 | break; | |
3769 | default: | |
3770 | FAIL; | |
3771 | } | |
3772 | if (GET_MODE (rs6000_compare_op0) == DFmode) | |
3773 | { | |
3774 | temp = gen_reg_rtx (DFmode); | |
3775 | emit_insn (gen_subdf3 (temp, op0, op1)); | |
3776 | emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3])); | |
3777 | if (code == EQ) | |
3778 | { | |
3779 | emit_insn (gen_negdf2 (temp, temp)); | |
3780 | emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3])); | |
3781 | } | |
a6c2a102 | 3782 | else if (code == NE) |
94d7001a RK |
3783 | { |
3784 | emit_insn (gen_negdf2 (temp, temp)); | |
3785 | emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0])); | |
3786 | } | |
3787 | } | |
3788 | else | |
3789 | { | |
3790 | temp = gen_reg_rtx (SFmode); | |
3791 | emit_insn (gen_subsf3 (temp, op0, op1)); | |
3792 | emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3])); | |
3793 | if (code == EQ) | |
3794 | { | |
3795 | emit_insn (gen_negsf2 (temp, temp)); | |
3796 | emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3])); | |
3797 | } | |
a6c2a102 | 3798 | else if (code == NE) |
94d7001a RK |
3799 | { |
3800 | emit_insn (gen_negsf2 (temp, temp)); | |
3801 | emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0])); | |
3802 | } | |
3803 | } | |
3804 | DONE; | |
3805 | }") | |
d56d506a | 3806 | |
94d7001a | 3807 | (define_insn "fselsfsf4" |
8e871c05 RK |
3808 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
3809 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
3810 | (const_int 0)) | |
3811 | (match_operand:SF 2 "gpc_reg_operand" "f") | |
3812 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3813 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3814 | "fsel %0,%1,%2,%3" |
3815 | [(set_attr "type" "fp")]) | |
2f607b94 | 3816 | |
94d7001a RK |
3817 | (define_insn "fseldfsf4" |
3818 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
3819 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
3820 | (const_int 0)) | |
3821 | (match_operand:SF 2 "gpc_reg_operand" "f") | |
3822 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3823 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
3824 | "fsel %0,%1,%2,%3" |
3825 | [(set_attr "type" "fp")]) | |
d56d506a | 3826 | |
1fd4e8c1 | 3827 | (define_insn "negdf2" |
cd2b37d9 RK |
3828 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3829 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3830 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3831 | "fneg %0,%1" |
3832 | [(set_attr "type" "fp")]) | |
3833 | ||
3834 | (define_insn "absdf2" | |
cd2b37d9 RK |
3835 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3836 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3837 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3838 | "fabs %0,%1" |
3839 | [(set_attr "type" "fp")]) | |
3840 | ||
3841 | (define_insn "" | |
cd2b37d9 RK |
3842 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3843 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 3844 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
3845 | "fnabs %0,%1" |
3846 | [(set_attr "type" "fp")]) | |
3847 | ||
3848 | (define_insn "adddf3" | |
cd2b37d9 RK |
3849 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3850 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3851 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3852 | "TARGET_HARD_FLOAT" |
ca7f5001 | 3853 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
3854 | [(set_attr "type" "fp")]) |
3855 | ||
3856 | (define_insn "subdf3" | |
cd2b37d9 RK |
3857 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3858 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
3859 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3860 | "TARGET_HARD_FLOAT" |
ca7f5001 | 3861 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
3862 | [(set_attr "type" "fp")]) |
3863 | ||
3864 | (define_insn "muldf3" | |
cd2b37d9 RK |
3865 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3866 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3867 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3868 | "TARGET_HARD_FLOAT" |
ca7f5001 | 3869 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 3870 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3871 | |
3872 | (define_insn "divdf3" | |
cd2b37d9 RK |
3873 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3874 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
3875 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3876 | "TARGET_HARD_FLOAT" |
ca7f5001 | 3877 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 3878 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
3879 | |
3880 | (define_insn "" | |
cd2b37d9 RK |
3881 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3882 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3883 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
3884 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 3885 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 3886 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 3887 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3888 | |
3889 | (define_insn "" | |
cd2b37d9 RK |
3890 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3891 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3892 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
3893 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 3894 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 3895 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 3896 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3897 | |
3898 | (define_insn "" | |
cd2b37d9 RK |
3899 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3900 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3901 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
3902 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 3903 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 3904 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 3905 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
3906 | |
3907 | (define_insn "" | |
cd2b37d9 RK |
3908 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
3909 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
3910 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
3911 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 3912 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 3913 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 3914 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
3915 | |
3916 | (define_insn "sqrtdf2" | |
3917 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
3918 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3919 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
3920 | "fsqrt %0,%1" |
3921 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 3922 | |
94d7001a RK |
3923 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
3924 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
3925 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 | 3926 | ;; combine. |
b77dfefc | 3927 | |
8e871c05 RK |
3928 | (define_expand "maxdf3" |
3929 | [(set (match_dup 3) | |
3930 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
3931 | (match_operand:DF 2 "gpc_reg_operand" ""))) | |
3932 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
3933 | (if_then_else:DF (ge (match_dup 3) | |
3934 | (const_int 0)) | |
3935 | (match_dup 1) | |
3936 | (match_dup 2)))] | |
d14a6d05 | 3937 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3938 | " |
3939 | { operands[3] = gen_reg_rtx (DFmode); }") | |
b77dfefc | 3940 | |
8e871c05 RK |
3941 | (define_split |
3942 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
3943 | (smax:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
f63184ac | 3944 | (match_operand:DF 2 "gpc_reg_operand" ""))) |
8e871c05 | 3945 | (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 3946 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3947 | [(set (match_dup 3) |
3948 | (minus:DF (match_dup 1) (match_dup 2))) | |
a81bd72f | 3949 | (set (match_dup 0) |
8e871c05 RK |
3950 | (if_then_else:DF (ge (match_dup 3) |
3951 | (const_int 0)) | |
3952 | (match_dup 1) | |
3953 | (match_dup 2)))] | |
3954 | "") | |
b77dfefc | 3955 | |
8e871c05 RK |
3956 | (define_expand "mindf3" |
3957 | [(set (match_dup 3) | |
3958 | (minus:DF (match_operand:DF 2 "gpc_reg_operand" "") | |
3959 | (match_operand:DF 1 "gpc_reg_operand" ""))) | |
3960 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
3961 | (if_then_else:DF (ge (match_dup 3) | |
3962 | (const_int 0)) | |
3963 | (match_dup 1) | |
3964 | (match_dup 2)))] | |
d14a6d05 | 3965 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3966 | " |
3967 | { operands[3] = gen_reg_rtx (DFmode); }") | |
b77dfefc | 3968 | |
8e871c05 RK |
3969 | (define_split |
3970 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
3971 | (smin:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
f63184ac | 3972 | (match_operand:DF 2 "gpc_reg_operand" ""))) |
8e871c05 | 3973 | (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 3974 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
3975 | [(set (match_dup 3) |
3976 | (minus:DF (match_dup 2) (match_dup 1))) | |
a81bd72f | 3977 | (set (match_dup 0) |
8e871c05 RK |
3978 | (if_then_else:DF (ge (match_dup 3) |
3979 | (const_int 0)) | |
3980 | (match_dup 1) | |
3981 | (match_dup 2)))] | |
3982 | "") | |
b77dfefc | 3983 | |
94d7001a RK |
3984 | (define_expand "movdfcc" |
3985 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
3986 | (if_then_else:DF (match_operand 1 "comparison_operator" "") | |
3987 | (match_operand:DF 2 "gpc_reg_operand" "f") | |
3988 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 3989 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
3990 | " |
3991 | { | |
3992 | rtx temp, op0, op1; | |
3993 | enum rtx_code code = GET_CODE (operands[1]); | |
3994 | if (! rs6000_compare_fp_p) | |
3995 | FAIL; | |
3996 | switch (code) | |
3997 | { | |
3998 | case GE: case EQ: case NE: | |
3999 | op0 = rs6000_compare_op0; | |
4000 | op1 = rs6000_compare_op1; | |
4001 | break; | |
4002 | case GT: | |
4003 | op0 = rs6000_compare_op1; | |
4004 | op1 = rs6000_compare_op0; | |
4005 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
4006 | break; | |
4007 | case LE: | |
4008 | op0 = rs6000_compare_op1; | |
4009 | op1 = rs6000_compare_op0; | |
4010 | break; | |
4011 | case LT: | |
4012 | op0 = rs6000_compare_op0; | |
4013 | op1 = rs6000_compare_op1; | |
4014 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
4015 | break; | |
4016 | default: | |
4017 | FAIL; | |
4018 | } | |
4019 | if (GET_MODE (rs6000_compare_op0) == DFmode) | |
4020 | { | |
4021 | temp = gen_reg_rtx (DFmode); | |
4022 | emit_insn (gen_subdf3 (temp, op0, op1)); | |
4023 | emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3])); | |
4024 | if (code == EQ) | |
4025 | { | |
4026 | emit_insn (gen_negdf2 (temp, temp)); | |
4027 | emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3])); | |
4028 | } | |
a6c2a102 | 4029 | else if (code == NE) |
94d7001a RK |
4030 | { |
4031 | emit_insn (gen_negdf2 (temp, temp)); | |
4032 | emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0])); | |
4033 | } | |
4034 | } | |
4035 | else | |
4036 | { | |
4037 | temp = gen_reg_rtx (SFmode); | |
4038 | emit_insn (gen_subsf3 (temp, op0, op1)); | |
4039 | emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3])); | |
4040 | if (code == EQ) | |
4041 | { | |
4042 | emit_insn (gen_negsf2 (temp, temp)); | |
4043 | emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3])); | |
4044 | } | |
a6c2a102 | 4045 | else if (code == NE) |
94d7001a RK |
4046 | { |
4047 | emit_insn (gen_negsf2 (temp, temp)); | |
4048 | emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0])); | |
4049 | } | |
4050 | } | |
4051 | DONE; | |
4052 | }") | |
d56d506a | 4053 | |
94d7001a | 4054 | (define_insn "fseldfdf4" |
8e871c05 RK |
4055 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4056 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
4057 | (const_int 0)) | |
4058 | (match_operand:DF 2 "gpc_reg_operand" "f") | |
4059 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4060 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4061 | "fsel %0,%1,%2,%3" |
4062 | [(set_attr "type" "fp")]) | |
d56d506a | 4063 | |
94d7001a RK |
4064 | (define_insn "fselsfdf4" |
4065 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4066 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
4067 | (const_int 0)) | |
4068 | (match_operand:DF 2 "gpc_reg_operand" "f") | |
4069 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
4070 | "TARGET_PPC_GFXOPT" | |
4071 | "fsel %0,%1,%2,%3" | |
4072 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4073 | \f |
4074 | ;; Conversions to and from floating-point. | |
802a0058 | 4075 | |
1fd4e8c1 | 4076 | (define_expand "floatsidf2" |
802a0058 MM |
4077 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
4078 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
4079 | (use (match_dup 2)) | |
4080 | (use (match_dup 3)) | |
208c89ce | 4081 | (clobber (match_dup 4)) |
a7df97e6 | 4082 | (clobber (match_dup 5)) |
802a0058 | 4083 | (clobber (reg:DF 76))])] |
a260abc9 | 4084 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4085 | " |
4086 | { | |
802a0058 MM |
4087 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
4088 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); | |
208c89ce | 4089 | operands[4] = gen_reg_rtx (SImode); |
a7df97e6 | 4090 | operands[5] = gen_reg_rtx (Pmode); |
1fd4e8c1 RK |
4091 | }") |
4092 | ||
802a0058 MM |
4093 | (define_insn "*floatsidf2_internal" |
4094 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
4095 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
4096 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
4097 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
208c89ce | 4098 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
a260abc9 | 4099 | (clobber (match_operand 5 "gpc_reg_operand" "=b")) |
802a0058 | 4100 | (clobber (reg:DF 76))] |
a260abc9 | 4101 | "TARGET_HARD_FLOAT" |
802a0058 | 4102 | "#" |
a7df97e6 | 4103 | [(set_attr "length" "24")]) |
802a0058 MM |
4104 | |
4105 | (define_split | |
dbe3df29 | 4106 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
4107 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
4108 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
4109 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
208c89ce | 4110 | (clobber (match_operand:SI 4 "gpc_reg_operand" "")) |
a260abc9 | 4111 | (clobber (match_operand 5 "gpc_reg_operand" "")) |
802a0058 | 4112 | (clobber (reg:DF 76))] |
a260abc9 | 4113 | "TARGET_HARD_FLOAT" |
802a0058 | 4114 | [(set (match_dup 4) |
208c89ce | 4115 | (xor:SI (match_dup 1) |
a7df97e6 MM |
4116 | (match_dup 6))) |
4117 | (set (match_dup 5) | |
4118 | (unspec [(const_int 0)] 11)) | |
4119 | (set (match_dup 7) | |
4120 | (unspec [(match_dup 4) | |
4121 | (match_dup 5)] 12)) ;; low word | |
4122 | (set (match_dup 7) | |
4123 | (unspec [(match_dup 2) | |
4124 | (match_dup 5) | |
4125 | (match_dup 7)] 13)) ;; high word | |
802a0058 | 4126 | (set (match_dup 0) |
a7df97e6 MM |
4127 | (unspec [(match_dup 7) |
4128 | (match_dup 5)] 14)) | |
802a0058 MM |
4129 | (set (match_dup 0) |
4130 | (minus:DF (match_dup 0) | |
4131 | (match_dup 3)))] | |
208c89ce MM |
4132 | " |
4133 | { | |
a7df97e6 | 4134 | operands[6] = GEN_INT (0x80000000); |
39403d82 | 4135 | operands[7] = gen_rtx_REG (DFmode, FPMEM_REGNUM); |
208c89ce | 4136 | }") |
802a0058 MM |
4137 | |
4138 | (define_expand "floatunssidf2" | |
4139 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4140 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
4141 | (use (match_dup 2)) | |
4142 | (use (match_dup 3)) | |
a7df97e6 | 4143 | (clobber (match_dup 4)) |
802a0058 | 4144 | (clobber (reg:DF 76))])] |
a260abc9 | 4145 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4146 | " |
4147 | { | |
802a0058 MM |
4148 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
4149 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode)); | |
a7df97e6 | 4150 | operands[4] = gen_reg_rtx (Pmode); |
1fd4e8c1 RK |
4151 | }") |
4152 | ||
802a0058 MM |
4153 | (define_insn "*floatunssidf2_internal" |
4154 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
4155 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
4156 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
4157 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
a260abc9 | 4158 | (clobber (match_operand 4 "gpc_reg_operand" "=b")) |
802a0058 | 4159 | (clobber (reg:DF 76))] |
a260abc9 | 4160 | "TARGET_HARD_FLOAT" |
802a0058 | 4161 | "#" |
a7df97e6 | 4162 | [(set_attr "length" "20")]) |
802a0058 MM |
4163 | |
4164 | (define_split | |
4165 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4166 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
4167 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
4168 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
955fc2e7 | 4169 | (clobber (match_operand 4 "gpc_reg_operand" "")) |
802a0058 | 4170 | (clobber (reg:DF 76))] |
a260abc9 | 4171 | "TARGET_HARD_FLOAT" |
802a0058 | 4172 | [(set (match_dup 4) |
a7df97e6 MM |
4173 | (unspec [(const_int 0)] 11)) |
4174 | (set (match_dup 5) | |
4175 | (unspec [(match_dup 1) | |
4176 | (match_dup 4)] 12)) ;; low word | |
4177 | (set (match_dup 5) | |
4178 | (unspec [(match_dup 2) | |
4179 | (match_dup 4) | |
4180 | (match_dup 5)] 13)) ;; high word | |
802a0058 | 4181 | (set (match_dup 0) |
a7df97e6 | 4182 | (unspec [(match_dup 5) |
955fc2e7 | 4183 | (match_dup 4)] 14)) |
802a0058 MM |
4184 | (set (match_dup 0) |
4185 | (minus:DF (match_dup 0) | |
4186 | (match_dup 3)))] | |
39403d82 | 4187 | "operands[5] = gen_rtx_REG (DFmode, FPMEM_REGNUM);") |
802a0058 | 4188 | |
a7df97e6 MM |
4189 | ;; Load up scratch register with base address + offset if needed |
4190 | (define_insn "*floatsidf2_loadaddr" | |
a260abc9 | 4191 | [(set (match_operand 0 "gpc_reg_operand" "=b") |
a7df97e6 MM |
4192 | (unspec [(const_int 0)] 11))] |
4193 | "TARGET_HARD_FLOAT" | |
4194 | "* | |
4195 | { | |
4196 | if (rs6000_fpmem_offset > 32760) | |
4197 | { | |
4198 | rtx xop[3]; | |
4199 | ||
4200 | xop[0] = operands[0]; | |
4201 | xop[1] = (frame_pointer_needed) ? frame_pointer_rtx : stack_pointer_rtx; | |
170e0690 | 4202 | xop[2] = GEN_INT ((rs6000_fpmem_offset >> 16) + ((rs6000_fpmem_offset & 0x8000) >> 15)); |
538bb158 | 4203 | output_asm_insn (\"{cau|addis} %0,%1,%2\", xop); |
a7df97e6 | 4204 | } |
a7df97e6 MM |
4205 | |
4206 | return \"\"; | |
4207 | }" | |
4208 | [(set_attr "length" "4")]) | |
802a0058 MM |
4209 | |
4210 | (define_insn "*floatsidf2_store1" | |
4211 | [(set (reg:DF 76) | |
4212 | (unspec [(match_operand:SI 0 "gpc_reg_operand" "r") | |
a260abc9 DE |
4213 | (match_operand 1 "gpc_reg_operand" "b")] 12))] |
4214 | "TARGET_HARD_FLOAT" | |
802a0058 | 4215 | "* |
dbe3df29 | 4216 | { |
a7df97e6 MM |
4217 | rtx indx; |
4218 | ||
4219 | if (rs6000_fpmem_offset > 32760) | |
4220 | indx = operands[1]; | |
4221 | else if (frame_pointer_needed) | |
4222 | indx = frame_pointer_rtx; | |
4223 | else | |
4224 | indx = stack_pointer_rtx; | |
4225 | ||
39403d82 DE |
4226 | operands[2] = gen_rtx_MEM (SImode, |
4227 | gen_rtx_PLUS (Pmode, | |
a7df97e6 | 4228 | indx, |
170e0690 | 4229 | GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000) |
802a0058 | 4230 | + ((WORDS_BIG_ENDIAN != 0) * 4)))); |
c283c989 | 4231 | |
a7df97e6 | 4232 | return \"{st|stw} %0,%2\"; |
802a0058 MM |
4233 | }" |
4234 | [(set_attr "type" "store")]) | |
4235 | ||
4236 | (define_insn "*floatsidf2_store2" | |
4237 | [(set (reg:DF 76) | |
4238 | (unspec [(match_operand:SI 0 "gpc_reg_operand" "r") | |
a260abc9 | 4239 | (match_operand 1 "gpc_reg_operand" "b") |
a7df97e6 | 4240 | (reg:DF 76)] 13))] |
a260abc9 | 4241 | "TARGET_HARD_FLOAT" |
802a0058 MM |
4242 | "* |
4243 | { | |
a7df97e6 MM |
4244 | rtx indx; |
4245 | ||
4246 | if (rs6000_fpmem_offset > 32760) | |
4247 | indx = operands[1]; | |
4248 | else if (frame_pointer_needed) | |
4249 | indx = frame_pointer_rtx; | |
4250 | else | |
4251 | indx = stack_pointer_rtx; | |
4252 | ||
39403d82 DE |
4253 | operands[2] = gen_rtx_MEM (SImode, |
4254 | gen_rtx_PLUS (Pmode, | |
a7df97e6 | 4255 | indx, |
170e0690 | 4256 | GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000) |
802a0058 MM |
4257 | + ((WORDS_BIG_ENDIAN == 0) * 4)))); |
4258 | ||
a7df97e6 | 4259 | return \"{st|stw} %0,%2\"; |
802a0058 MM |
4260 | }" |
4261 | [(set_attr "type" "store")]) | |
4262 | ||
4263 | (define_insn "*floatsidf2_load" | |
4264 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4265 | (unspec [(reg:DF 76) | |
a260abc9 DE |
4266 | (match_operand 1 "gpc_reg_operand" "b")] 14))] |
4267 | "TARGET_HARD_FLOAT" | |
802a0058 MM |
4268 | "* |
4269 | { | |
a7df97e6 | 4270 | rtx indx; |
f6968f59 | 4271 | HOST_WIDE_INT offset = rs6000_fpmem_offset; |
a7df97e6 MM |
4272 | |
4273 | if (rs6000_fpmem_offset > 32760) | |
f6968f59 MM |
4274 | { |
4275 | indx = operands[1]; | |
170e0690 | 4276 | offset = (((offset & 0xffff) ^ 0x8000) - 0x8000); |
f6968f59 | 4277 | } |
a7df97e6 MM |
4278 | else if (frame_pointer_needed) |
4279 | indx = frame_pointer_rtx; | |
4280 | else | |
4281 | indx = stack_pointer_rtx; | |
4282 | ||
39403d82 DE |
4283 | operands[2] = gen_rtx_MEM (SImode, |
4284 | gen_rtx_PLUS (Pmode, indx, GEN_INT (offset))); | |
802a0058 | 4285 | |
a7df97e6 | 4286 | return \"lfd %0,%2\"; |
802a0058 MM |
4287 | }" |
4288 | [(set_attr "type" "fpload")]) | |
1fd4e8c1 | 4289 | |
1fd4e8c1 | 4290 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
4291 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
4292 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
4293 | (clobber (match_dup 2)) | |
a7df97e6 MM |
4294 | (clobber (match_dup 3)) |
4295 | (clobber (match_dup 4))])] | |
d14a6d05 | 4296 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4297 | " |
4298 | { | |
802a0058 | 4299 | if (!TARGET_POWER2 && !TARGET_POWERPC) |
8ffd9c51 RK |
4300 | { |
4301 | emit_insn (gen_trunc_call (operands[0], operands[1], | |
39403d82 | 4302 | gen_rtx_SYMBOL_REF (Pmode, RS6000_ITRUNC))); |
8ffd9c51 RK |
4303 | DONE; |
4304 | } | |
802a0058 MM |
4305 | |
4306 | operands[2] = gen_reg_rtx (DImode); | |
a7df97e6 | 4307 | operands[3] = gen_reg_rtx (Pmode); |
39403d82 | 4308 | operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM); |
1fd4e8c1 RK |
4309 | }") |
4310 | ||
802a0058 MM |
4311 | (define_insn "*fix_truncdfsi2_internal" |
4312 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4313 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
4314 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) | |
a260abc9 | 4315 | (clobber (match_operand 3 "gpc_reg_operand" "=b")) |
802a0058 MM |
4316 | (clobber (reg:DI 76))] |
4317 | "TARGET_HARD_FLOAT" | |
4318 | "#" | |
4319 | [(set_attr "length" "12")]) | |
4320 | ||
4321 | (define_split | |
4322 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4323 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
4324 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) | |
a260abc9 | 4325 | (clobber (match_operand 3 "gpc_reg_operand" "")) |
802a0058 MM |
4326 | (clobber (reg:DI 76))] |
4327 | "TARGET_HARD_FLOAT" | |
4328 | [(set (match_dup 2) | |
4329 | (sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))) | |
4330 | (set (match_dup 3) | |
a7df97e6 MM |
4331 | (unspec [(const_int 0)] 11)) |
4332 | (set (match_dup 4) | |
802a0058 | 4333 | (unspec [(match_dup 2) |
a7df97e6 | 4334 | (match_dup 3)] 15)) |
802a0058 | 4335 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
a7df97e6 MM |
4336 | (unspec [(match_dup 4) |
4337 | (match_dup 3)] 16))] | |
39403d82 | 4338 | "operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM);") |
802a0058 | 4339 | |
802a0058 MM |
4340 | (define_insn "*fix_truncdfsi2_store" |
4341 | [(set (reg:DI 76) | |
4342 | (unspec [(match_operand:DI 0 "gpc_reg_operand" "f") | |
a260abc9 | 4343 | (match_operand 1 "gpc_reg_operand" "b")] 15))] |
802a0058 MM |
4344 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
4345 | "* | |
4346 | { | |
a7df97e6 MM |
4347 | rtx indx; |
4348 | ||
4349 | if (rs6000_fpmem_offset > 32760) | |
4350 | indx = operands[1]; | |
4351 | else if (frame_pointer_needed) | |
4352 | indx = frame_pointer_rtx; | |
4353 | else | |
4354 | indx = stack_pointer_rtx; | |
4355 | ||
39403d82 DE |
4356 | operands[2] = gen_rtx_MEM (DFmode, |
4357 | gen_rtx_PLUS (Pmode, | |
a7df97e6 | 4358 | indx, |
eaf1bcf1 MM |
4359 | GEN_INT ((((rs6000_fpmem_offset & 0xffff) |
4360 | ^ 0x8000) - 0x8000)))); | |
802a0058 | 4361 | |
1427100a | 4362 | return \"stfd %0,%2\"; |
802a0058 MM |
4363 | }" |
4364 | [(set_attr "type" "fpstore")]) | |
4365 | ||
4366 | (define_insn "*fix_truncdfsi2_load" | |
4367 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4368 | (unspec [(reg:DI 76) | |
a260abc9 | 4369 | (match_operand 1 "gpc_reg_operand" "b")] 16))] |
802a0058 MM |
4370 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
4371 | "* | |
4372 | { | |
a7df97e6 MM |
4373 | rtx indx; |
4374 | ||
4375 | if (rs6000_fpmem_offset > 32760) | |
4376 | indx = operands[1]; | |
4377 | else if (frame_pointer_needed) | |
4378 | indx = frame_pointer_rtx; | |
4379 | else | |
4380 | indx = stack_pointer_rtx; | |
4381 | ||
39403d82 DE |
4382 | operands[2] = gen_rtx_MEM (DFmode, |
4383 | gen_rtx_PLUS (Pmode, | |
a7df97e6 | 4384 | indx, |
170e0690 | 4385 | GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000) |
a7df97e6 | 4386 | + ((WORDS_BIG_ENDIAN) ? 4 : 0)))); |
802a0058 | 4387 | |
a7df97e6 | 4388 | return \"{l|lwz} %0,%2\"; |
802a0058 MM |
4389 | }" |
4390 | [(set_attr "type" "load")]) | |
4391 | ||
1fd4e8c1 | 4392 | (define_expand "fixuns_truncdfsi2" |
cd2b37d9 | 4393 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
b542afe9 | 4394 | (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] |
d14a6d05 | 4395 | "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4396 | " |
4397 | { | |
4398 | emit_insn (gen_trunc_call (operands[0], operands[1], | |
39403d82 | 4399 | gen_rtx_SYMBOL_REF (Pmode, RS6000_UITRUNC))); |
1fd4e8c1 RK |
4400 | DONE; |
4401 | }") | |
4402 | ||
1fd4e8c1 RK |
4403 | (define_expand "trunc_call" |
4404 | [(parallel [(set (match_operand:SI 0 "" "") | |
b542afe9 | 4405 | (fix:SI (match_operand:DF 1 "" ""))) |
1fd4e8c1 | 4406 | (use (match_operand:SI 2 "" ""))])] |
d14a6d05 | 4407 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4408 | " |
4409 | { | |
4410 | rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]); | |
4411 | rtx first = XVECEXP (insns, 0, 0); | |
4412 | rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1); | |
4413 | ||
39403d82 | 4414 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, |
1fd4e8c1 | 4415 | REG_NOTES (first)); |
39403d82 | 4416 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last)); |
1fd4e8c1 RK |
4417 | |
4418 | emit_insn (insns); | |
4419 | DONE; | |
4420 | }") | |
4421 | ||
4422 | (define_expand "trunc_call_rtl" | |
cd2b37d9 | 4423 | [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" "")) |
1fd4e8c1 RK |
4424 | (use (reg:DF 33)) |
4425 | (parallel [(set (reg:SI 3) | |
4426 | (call (mem:SI (match_operand 2 "" "")) (const_int 0))) | |
4697a36c | 4427 | (use (const_int 0)) |
1fd4e8c1 | 4428 | (clobber (scratch:SI))]) |
cd2b37d9 | 4429 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 4430 | (reg:SI 3))] |
d14a6d05 | 4431 | "TARGET_HARD_FLOAT" |
1fd4e8c1 | 4432 | " |
7e69e155 | 4433 | { |
1fd4e8c1 RK |
4434 | rs6000_trunc_used = 1; |
4435 | }") | |
a473029f | 4436 | |
a260abc9 DE |
4437 | (define_insn "*fctiwz" |
4438 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
4439 | (sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
4440 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" | |
4441 | "{fcirz|fctiwz} %0,%1" | |
4442 | [(set_attr "type" "fp")]) | |
4443 | ||
a473029f RK |
4444 | (define_insn "floatdidf2" |
4445 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4446 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4447 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
4448 | "fcfid %0,%1" |
4449 | [(set_attr "type" "fp")]) | |
4450 | ||
4451 | (define_insn "fix_truncdfdi2" | |
4452 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
4453 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4454 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
4455 | "fctidz %0,%1" |
4456 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4457 | \f |
4458 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
4459 | ;; of instructions. The & constraints are to prevent the register |
4460 | ;; allocator from allocating registers that overlap with the inputs | |
4461 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 4462 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 4463 | |
266eb58a | 4464 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
4465 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
4466 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
4467 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 4468 | "! TARGET_POWERPC64" |
0f645302 MM |
4469 | "* |
4470 | { | |
4471 | if (WORDS_BIG_ENDIAN) | |
4472 | return (GET_CODE (operands[2])) != CONST_INT | |
4473 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
4474 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
4475 | else | |
4476 | return (GET_CODE (operands[2])) != CONST_INT | |
4477 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
4478 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
4479 | }" | |
b19003d8 | 4480 | [(set_attr "length" "8")]) |
1fd4e8c1 | 4481 | |
266eb58a | 4482 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
4483 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
4484 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
4485 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 4486 | "! TARGET_POWERPC64" |
5502823b RK |
4487 | "* |
4488 | { | |
0f645302 MM |
4489 | if (WORDS_BIG_ENDIAN) |
4490 | return (GET_CODE (operands[1]) != CONST_INT) | |
4491 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
4492 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
4493 | else | |
4494 | return (GET_CODE (operands[1]) != CONST_INT) | |
4495 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
4496 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 4497 | }" |
ca7f5001 RK |
4498 | [(set_attr "length" "8")]) |
4499 | ||
266eb58a | 4500 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
4501 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
4502 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 4503 | "! TARGET_POWERPC64" |
5502823b RK |
4504 | "* |
4505 | { | |
4506 | return (WORDS_BIG_ENDIAN) | |
4507 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
4508 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
4509 | }" | |
ca7f5001 RK |
4510 | [(set_attr "length" "8")]) |
4511 | ||
8ffd9c51 RK |
4512 | (define_expand "mulsidi3" |
4513 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4514 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
4515 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 4516 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
4517 | " |
4518 | { | |
4519 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
4520 | { | |
39403d82 DE |
4521 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
4522 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 4523 | emit_insn (gen_mull_call ()); |
cf27b467 | 4524 | if (WORDS_BIG_ENDIAN) |
39403d82 | 4525 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
4526 | else |
4527 | { | |
4528 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 4529 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 4530 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 4531 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 4532 | } |
8ffd9c51 RK |
4533 | DONE; |
4534 | } | |
4535 | else if (TARGET_POWER) | |
4536 | { | |
4537 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
4538 | DONE; | |
4539 | } | |
4540 | }") | |
deb9225a | 4541 | |
8ffd9c51 | 4542 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 4543 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 4544 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 4545 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 4546 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 4547 | "TARGET_POWER" |
b19003d8 | 4548 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
4549 | [(set_attr "type" "imul") |
4550 | (set_attr "length" "8")]) | |
deb9225a | 4551 | |
f192bf8b | 4552 | (define_insn "*mulsidi3_no_mq" |
425c176f | 4553 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
4554 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
4555 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 4556 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
4557 | "* |
4558 | { | |
4559 | return (WORDS_BIG_ENDIAN) | |
4560 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
4561 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
4562 | }" | |
8ffd9c51 RK |
4563 | [(set_attr "type" "imul") |
4564 | (set_attr "length" "8")]) | |
deb9225a | 4565 | |
ebedb4dd MM |
4566 | (define_split |
4567 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4568 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
4569 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 4570 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
4571 | [(set (match_dup 3) |
4572 | (truncate:SI | |
4573 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
4574 | (sign_extend:DI (match_dup 2))) | |
4575 | (const_int 32)))) | |
4576 | (set (match_dup 4) | |
4577 | (mult:SI (match_dup 1) | |
4578 | (match_dup 2)))] | |
4579 | " | |
4580 | { | |
4581 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4582 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
4583 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
4584 | }") | |
4585 | ||
f192bf8b DE |
4586 | (define_expand "umulsidi3" |
4587 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4588 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
4589 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
4590 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
4591 | " | |
4592 | { | |
4593 | if (TARGET_POWER) | |
4594 | { | |
4595 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
4596 | DONE; | |
4597 | } | |
4598 | }") | |
4599 | ||
4600 | (define_insn "umulsidi3_mq" | |
4601 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
4602 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4603 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
4604 | (clobber (match_scratch:SI 3 "=q"))] | |
4605 | "TARGET_POWERPC && TARGET_POWER" | |
4606 | "* | |
4607 | { | |
4608 | return (WORDS_BIG_ENDIAN) | |
4609 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
4610 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
4611 | }" | |
4612 | [(set_attr "type" "imul") | |
4613 | (set_attr "length" "8")]) | |
4614 | ||
4615 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
4616 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
4617 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4618 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 4619 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
4620 | "* |
4621 | { | |
4622 | return (WORDS_BIG_ENDIAN) | |
4623 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
4624 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
4625 | }" | |
4626 | [(set_attr "type" "imul") | |
4627 | (set_attr "length" "8")]) | |
4628 | ||
ebedb4dd MM |
4629 | (define_split |
4630 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4631 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
4632 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 4633 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
4634 | [(set (match_dup 3) |
4635 | (truncate:SI | |
4636 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
4637 | (zero_extend:DI (match_dup 2))) | |
4638 | (const_int 32)))) | |
4639 | (set (match_dup 4) | |
4640 | (mult:SI (match_dup 1) | |
4641 | (match_dup 2)))] | |
4642 | " | |
4643 | { | |
4644 | int endian = (WORDS_BIG_ENDIAN == 0); | |
4645 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
4646 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
4647 | }") | |
4648 | ||
8ffd9c51 RK |
4649 | (define_expand "smulsi3_highpart" |
4650 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4651 | (truncate:SI | |
4652 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
4653 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4654 | (sign_extend:DI | |
4655 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
4656 | (const_int 32))))] | |
4657 | "" | |
4658 | " | |
4659 | { | |
4660 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
4661 | { | |
39403d82 DE |
4662 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
4663 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 4664 | emit_insn (gen_mulh_call ()); |
39403d82 | 4665 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
4666 | DONE; |
4667 | } | |
4668 | else if (TARGET_POWER) | |
4669 | { | |
4670 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
4671 | DONE; | |
4672 | } | |
4673 | }") | |
deb9225a | 4674 | |
8ffd9c51 RK |
4675 | (define_insn "smulsi3_highpart_mq" |
4676 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4677 | (truncate:SI | |
fada905b MM |
4678 | (lshiftrt:DI (mult:DI (sign_extend:DI |
4679 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4680 | (sign_extend:DI | |
4681 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
4682 | (const_int 32)))) |
4683 | (clobber (match_scratch:SI 3 "=q"))] | |
4684 | "TARGET_POWER" | |
4685 | "mul %0,%1,%2" | |
4686 | [(set_attr "type" "imul")]) | |
deb9225a | 4687 | |
f192bf8b | 4688 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
4689 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4690 | (truncate:SI | |
fada905b MM |
4691 | (lshiftrt:DI (mult:DI (sign_extend:DI |
4692 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4693 | (sign_extend:DI | |
4694 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 4695 | (const_int 32))))] |
f192bf8b | 4696 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
4697 | "mulhw %0,%1,%2" |
4698 | [(set_attr "type" "imul")]) | |
deb9225a | 4699 | |
f192bf8b DE |
4700 | (define_expand "umulsi3_highpart" |
4701 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4702 | (truncate:SI | |
4703 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
4704 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
4705 | (zero_extend:DI | |
4706 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
4707 | (const_int 32))))] | |
4708 | "TARGET_POWERPC" | |
4709 | " | |
4710 | { | |
4711 | if (TARGET_POWER) | |
4712 | { | |
4713 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
4714 | DONE; | |
4715 | } | |
4716 | }") | |
4717 | ||
4718 | (define_insn "umulsi3_highpart_mq" | |
4719 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4720 | (truncate:SI | |
4721 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
4722 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4723 | (zero_extend:DI | |
4724 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
4725 | (const_int 32)))) | |
4726 | (clobber (match_scratch:SI 3 "=q"))] | |
4727 | "TARGET_POWERPC && TARGET_POWER" | |
4728 | "mulhwu %0,%1,%2" | |
4729 | [(set_attr "type" "imul")]) | |
4730 | ||
4731 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
4732 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4733 | (truncate:SI | |
4734 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
4735 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
4736 | (zero_extend:DI | |
4737 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
4738 | (const_int 32))))] | |
f192bf8b | 4739 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
4740 | "mulhwu %0,%1,%2" |
4741 | [(set_attr "type" "imul")]) | |
4742 | ||
4743 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
4744 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
4745 | ;; why we have the strange constraints below. | |
4746 | (define_insn "ashldi3_power" | |
4747 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
4748 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
4749 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
4750 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
4751 | "TARGET_POWER" | |
4752 | "@ | |
4753 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
4754 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
4755 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
4756 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
4757 | [(set_attr "length" "8")]) | |
4758 | ||
4759 | (define_insn "lshrdi3_power" | |
47ad8c61 | 4760 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
4761 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
4762 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
4763 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
4764 | "TARGET_POWER" | |
4765 | "@ | |
47ad8c61 | 4766 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
4767 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
4768 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
4769 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
4770 | [(set_attr "length" "8")]) | |
4771 | ||
4772 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
4773 | ;; just handle shifts by constants. | |
4774 | (define_insn "ashrdi3_power" | |
7093ddee | 4775 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
4776 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
4777 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
4778 | (clobber (match_scratch:SI 3 "=X,q"))] | |
4779 | "TARGET_POWER" | |
4780 | "@ | |
4781 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
4782 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
4783 | [(set_attr "length" "8")]) | |
4784 | \f | |
4785 | ;; PowerPC64 DImode operations. | |
4786 | ||
4787 | (define_expand "adddi3" | |
4788 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4789 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
a260abc9 | 4790 | (match_operand:DI 2 "reg_or_cint_operand" "")))] |
266eb58a DE |
4791 | "" |
4792 | " | |
4793 | { | |
a260abc9 DE |
4794 | if (! TARGET_POWERPC64) |
4795 | { | |
4796 | if (non_short_cint_operand (operands[2], DImode)) | |
4797 | FAIL; | |
4798 | } | |
4799 | else | |
4800 | if (GET_CODE (operands[2]) == CONST_INT | |
4801 | && !add_operand (operands[2], DImode)) | |
4802 | { | |
4803 | rtx tmp = ((reload_in_progress || reload_completed | |
4804 | || rtx_equal_p (operands[0], operands[1])) | |
4805 | ? operands[0] : gen_reg_rtx (DImode)); | |
4806 | ||
4807 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; | |
4808 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
4809 | ||
4810 | if (low & 0x8000) | |
4811 | high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16; | |
4812 | ||
4813 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (high))); | |
4814 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); | |
4815 | DONE; | |
4816 | } | |
266eb58a DE |
4817 | }") |
4818 | ||
4819 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
4820 | ;; allowing register zero as source. | |
4821 | ||
a260abc9 | 4822 | (define_insn "*adddi3_internal1" |
266eb58a DE |
4823 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
4824 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
4825 | (match_operand:DI 2 "add_operand" "r,I,I,J")))] | |
4826 | "TARGET_POWERPC64" | |
4827 | "@ | |
4828 | add %0,%1,%2 | |
4829 | addi %0,%1,%2 | |
4830 | addic %0,%1,%2 | |
802a0058 | 4831 | addis %0,%1,%v2") |
266eb58a | 4832 | |
a260abc9 | 4833 | (define_insn "*adddi3_internal2" |
29ae5b89 JL |
4834 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
4835 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
4836 | (match_operand:DI 2 "reg_or_short_operand" "r,I")) | |
266eb58a | 4837 | (const_int 0))) |
29ae5b89 | 4838 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a DE |
4839 | "TARGET_POWERPC64" |
4840 | "@ | |
4841 | add. %3,%1,%2 | |
29ae5b89 JL |
4842 | addic. %3,%1,%2" |
4843 | [(set_attr "type" "compare")]) | |
266eb58a | 4844 | |
a260abc9 | 4845 | (define_insn "*adddi3_internal3" |
29ae5b89 JL |
4846 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
4847 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
4848 | (match_operand:DI 2 "reg_or_short_operand" "r,I")) | |
266eb58a | 4849 | (const_int 0))) |
29ae5b89 | 4850 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
4851 | (plus:DI (match_dup 1) (match_dup 2)))] |
4852 | "TARGET_POWERPC64" | |
4853 | "@ | |
4854 | add. %0,%1,%2 | |
29ae5b89 JL |
4855 | addic. %0,%1,%2" |
4856 | [(set_attr "type" "compare")]) | |
266eb58a DE |
4857 | |
4858 | ;; Split an add that we can't do in one insn into two insns, each of which | |
4859 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
4860 | ;; add should be last in case the result gets used in an address. | |
4861 | ||
4862 | (define_split | |
4863 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4864 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
4865 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
4866 | "TARGET_POWERPC64" | |
4867 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
4868 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
4869 | " | |
4870 | { | |
e6ca2c17 DE |
4871 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; |
4872 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
266eb58a DE |
4873 | |
4874 | if (low & 0x8000) | |
e6ca2c17 | 4875 | high+=0x10000, low |= ((HOST_WIDE_INT) -1) << 16; |
266eb58a | 4876 | |
e6ca2c17 DE |
4877 | operands[3] = GEN_INT (high); |
4878 | operands[4] = GEN_INT (low); | |
266eb58a DE |
4879 | }") |
4880 | ||
4881 | (define_insn "one_cmpldi2" | |
4882 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4883 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
4884 | "TARGET_POWERPC64" | |
4885 | "nor %0,%1,%1") | |
4886 | ||
4887 | (define_insn "" | |
29ae5b89 JL |
4888 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
4889 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
266eb58a | 4890 | (const_int 0))) |
29ae5b89 | 4891 | (clobber (match_scratch:DI 2 "=r"))] |
266eb58a DE |
4892 | "TARGET_POWERPC64" |
4893 | "nor. %2,%1,%1" | |
29ae5b89 | 4894 | [(set_attr "type" "compare")]) |
266eb58a DE |
4895 | |
4896 | (define_insn "" | |
29ae5b89 JL |
4897 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
4898 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
266eb58a | 4899 | (const_int 0))) |
29ae5b89 | 4900 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
4901 | (not:DI (match_dup 1)))] |
4902 | "TARGET_POWERPC64" | |
d944f453 | 4903 | "nor. %0,%1,%1" |
266eb58a DE |
4904 | [(set_attr "type" "compare")]) |
4905 | ||
4906 | (define_insn "" | |
4907 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
4908 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
4909 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
4910 | "TARGET_POWERPC64" | |
4911 | "@ | |
4912 | subf %0,%2,%1 | |
4913 | subfic %0,%2,%1") | |
4914 | ||
4915 | (define_insn "" | |
29ae5b89 JL |
4916 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
4917 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4918 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 4919 | (const_int 0))) |
29ae5b89 | 4920 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a DE |
4921 | "TARGET_POWERPC64" |
4922 | "subf. %3,%2,%1" | |
29ae5b89 | 4923 | [(set_attr "type" "compare")]) |
266eb58a DE |
4924 | |
4925 | (define_insn "" | |
29ae5b89 JL |
4926 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
4927 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
4928 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 4929 | (const_int 0))) |
29ae5b89 | 4930 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
4931 | (minus:DI (match_dup 1) (match_dup 2)))] |
4932 | "TARGET_POWERPC64" | |
4933 | "subf. %0,%2,%1" | |
4934 | [(set_attr "type" "compare")]) | |
4935 | ||
4936 | (define_expand "subdi3" | |
4937 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4938 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
4939 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
4940 | "" | |
4941 | " | |
4942 | { | |
4943 | if (GET_CODE (operands[2]) == CONST_INT) | |
4944 | { | |
4945 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
4946 | negate_rtx (DImode, operands[2]))); | |
4947 | DONE; | |
4948 | } | |
4949 | }") | |
4950 | ||
4951 | (define_insn "absdi2" | |
4952 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
4953 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
4954 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
4955 | "TARGET_POWERPC64" | |
a260abc9 | 4956 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0" |
266eb58a DE |
4957 | [(set_attr "length" "12")]) |
4958 | ||
4959 | (define_split | |
4960 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
4961 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
4962 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
4963 | "TARGET_POWERPC64 && reload_completed" | |
a260abc9 | 4964 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 4965 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 4966 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
4967 | "") |
4968 | ||
4969 | (define_insn "" | |
4970 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
4971 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
4972 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
4973 | "TARGET_POWERPC64" | |
a260abc9 | 4974 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2" |
266eb58a DE |
4975 | [(set_attr "length" "12")]) |
4976 | ||
4977 | (define_split | |
4978 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
4979 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
4980 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
4981 | "TARGET_POWERPC64 && reload_completed" | |
a260abc9 | 4982 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a DE |
4983 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
4984 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] | |
4985 | "") | |
4986 | ||
4987 | (define_expand "negdi2" | |
4988 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4989 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
4990 | "" | |
4991 | "") | |
4992 | ||
4993 | (define_insn "" | |
4994 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
4995 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
4996 | "TARGET_POWERPC64" | |
4997 | "neg %0,%1") | |
4998 | ||
4999 | (define_insn "" | |
29ae5b89 JL |
5000 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5001 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
266eb58a | 5002 | (const_int 0))) |
29ae5b89 JL |
5003 | (clobber (match_scratch:DI 2 "=r"))] |
5004 | "TARGET_POWERPC64" | |
5005 | "neg. %2,%1" | |
5006 | [(set_attr "type" "compare")]) | |
815cdc52 | 5007 | |
29ae5b89 JL |
5008 | (define_insn "" |
5009 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") | |
5010 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
815cdc52 | 5011 | (const_int 0))) |
29ae5b89 | 5012 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
815cdc52 | 5013 | (neg:DI (match_dup 1)))] |
29ae5b89 JL |
5014 | "TARGET_POWERPC64" |
5015 | "neg. %0,%1" | |
5016 | [(set_attr "type" "compare")]) | |
266eb58a DE |
5017 | |
5018 | (define_insn "ffsdi2" | |
5019 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5020 | (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5021 | "TARGET_POWERPC64" | |
5022 | "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64" | |
5023 | [(set_attr "length" "16")]) | |
5024 | ||
5025 | (define_insn "muldi3" | |
5026 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5027 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5028 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
5029 | "TARGET_POWERPC64" | |
5030 | "mulld %0,%1,%2" | |
5031 | [(set_attr "type" "imul")]) | |
5032 | ||
5033 | (define_insn "smuldi3_highpart" | |
5034 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5035 | (truncate:DI | |
5036 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
5037 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5038 | (sign_extend:TI | |
5039 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
5040 | (const_int 64))))] | |
5041 | "TARGET_POWERPC64" | |
5042 | "mulhd %0,%1,%2" | |
5043 | [(set_attr "type" "imul")]) | |
5044 | ||
5045 | (define_insn "umuldi3_highpart" | |
5046 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5047 | (truncate:DI | |
5048 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
5049 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5050 | (zero_extend:TI | |
5051 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
5052 | (const_int 64))))] | |
5053 | "TARGET_POWERPC64" | |
5054 | "mulhdu %0,%1,%2" | |
5055 | [(set_attr "type" "imul")]) | |
5056 | ||
5057 | (define_expand "divdi3" | |
5058 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5059 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5060 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
5061 | "TARGET_POWERPC64" | |
5062 | " | |
5063 | { | |
5064 | if (GET_CODE (operands[2]) == CONST_INT | |
5065 | && exact_log2 (INTVAL (operands[2])) >= 0) | |
5066 | ; | |
5067 | else | |
5068 | operands[2] = force_reg (DImode, operands[2]); | |
5069 | }") | |
5070 | ||
5071 | (define_expand "moddi3" | |
5072 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
5073 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
5074 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
5075 | "TARGET_POWERPC64" | |
5076 | " | |
5077 | { | |
5078 | int i = exact_log2 (INTVAL (operands[2])); | |
5079 | rtx temp1; | |
5080 | rtx temp2; | |
5081 | ||
5082 | if (GET_CODE (operands[2]) != CONST_INT || i < 0) | |
5083 | FAIL; | |
5084 | ||
5085 | temp1 = gen_reg_rtx (DImode); | |
5086 | temp2 = gen_reg_rtx (DImode); | |
5087 | ||
5088 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
5089 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
5090 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
5091 | DONE; | |
5092 | }") | |
5093 | ||
5094 | (define_insn "" | |
5095 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5096 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5097 | (match_operand:DI 2 "const_int_operand" "N")))] | |
5098 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" | |
5099 | "sradi %0,%1,%p2\;addze %0,%0" | |
5100 | [(set_attr "length" "8")]) | |
5101 | ||
5102 | (define_insn "" | |
29ae5b89 JL |
5103 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5104 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5105 | (match_operand:DI 2 "const_int_operand" "N")) | |
266eb58a | 5106 | (const_int 0))) |
29ae5b89 | 5107 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5108 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" |
29ae5b89 | 5109 | "sradi %3,%1,%p2\;addze. %3,%3" |
266eb58a | 5110 | [(set_attr "type" "compare") |
29ae5b89 | 5111 | (set_attr "length" "8")]) |
266eb58a DE |
5112 | |
5113 | (define_insn "" | |
29ae5b89 JL |
5114 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5115 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5116 | (match_operand:DI 2 "const_int_operand" "N")) | |
266eb58a | 5117 | (const_int 0))) |
29ae5b89 | 5118 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5119 | (div:DI (match_dup 1) (match_dup 2)))] |
5120 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" | |
29ae5b89 | 5121 | "sradi %0,%1,%p2\;addze. %0,%0" |
266eb58a | 5122 | [(set_attr "type" "compare") |
29ae5b89 | 5123 | (set_attr "length" "8")]) |
266eb58a DE |
5124 | |
5125 | (define_insn "" | |
5126 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5127 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a260abc9 | 5128 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
5129 | "TARGET_POWERPC64" |
5130 | "divd %0,%1,%2" | |
5131 | [(set_attr "type" "idiv")]) | |
5132 | ||
5133 | (define_insn "udivdi3" | |
5134 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5135 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5136 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
5137 | "TARGET_POWERPC64" | |
5138 | "divdu %0,%1,%2" | |
5139 | [(set_attr "type" "idiv")]) | |
5140 | ||
5141 | (define_insn "rotldi3" | |
5142 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5143 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5144 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
5145 | "TARGET_POWERPC64" | |
a66078ee | 5146 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 5147 | |
a260abc9 | 5148 | (define_insn "*rotldi3_internal2" |
29ae5b89 JL |
5149 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5150 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5151 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5152 | (const_int 0))) |
29ae5b89 | 5153 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5154 | "TARGET_POWERPC64" |
29ae5b89 JL |
5155 | "rld%I2cl. %3,%1,%H2,0" |
5156 | [(set_attr "type" "delayed_compare")]) | |
266eb58a | 5157 | |
a260abc9 | 5158 | (define_insn "*rotldi3_internal3" |
29ae5b89 JL |
5159 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5160 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5161 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5162 | (const_int 0))) |
29ae5b89 | 5163 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5164 | (rotate:DI (match_dup 1) (match_dup 2)))] |
5165 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5166 | "rld%I2cl. %0,%1,%H2,0" |
5167 | [(set_attr "type" "delayed_compare")]) | |
266eb58a | 5168 | |
a260abc9 DE |
5169 | (define_insn "*rotldi3_internal4" |
5170 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5171 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5172 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
5173 | (match_operand:DI 3 "mask64_operand" "S")))] | |
5174 | "TARGET_POWERPC64" | |
5175 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
5176 | ||
5177 | (define_insn "*rotldi3_internal5" | |
29ae5b89 | 5178 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
a260abc9 | 5179 | (compare:CC (and:DI |
29ae5b89 JL |
5180 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5181 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
5182 | (match_operand:DI 3 "mask64_operand" "S")) | |
a260abc9 | 5183 | (const_int 0))) |
29ae5b89 | 5184 | (clobber (match_scratch:DI 4 "=r"))] |
a260abc9 | 5185 | "TARGET_POWERPC64" |
29ae5b89 JL |
5186 | "rld%I2c%B3. %4,%1,%H2,%S3" |
5187 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
5188 | |
5189 | (define_insn "*rotldi3_internal6" | |
29ae5b89 | 5190 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
a260abc9 | 5191 | (compare:CC (and:DI |
29ae5b89 JL |
5192 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5193 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
5194 | (match_operand:DI 3 "mask64_operand" "S")) | |
a260abc9 | 5195 | (const_int 0))) |
29ae5b89 | 5196 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
5197 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
5198 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5199 | "rld%I2c%B3. %0,%1,%H2,%S3" |
5200 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
5201 | |
5202 | (define_insn "*rotldi3_internal7" | |
5203 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5204 | (zero_extend:DI | |
5205 | (subreg:QI | |
5206 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5207 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
5208 | "TARGET_POWERPC64" | |
5209 | "rld%I2cl %0,%1,%H2,56") | |
5210 | ||
5211 | (define_insn "*rotldi3_internal8" | |
29ae5b89 | 5212 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
a260abc9 DE |
5213 | (compare:CC (zero_extend:DI |
5214 | (subreg:QI | |
29ae5b89 JL |
5215 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5216 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 5217 | (const_int 0))) |
29ae5b89 | 5218 | (clobber (match_scratch:DI 3 "=r"))] |
a260abc9 | 5219 | "TARGET_POWERPC64" |
29ae5b89 JL |
5220 | "rld%I2cl. %3,%1,%H2,56" |
5221 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
5222 | |
5223 | (define_insn "*rotldi3_internal9" | |
29ae5b89 | 5224 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
a260abc9 DE |
5225 | (compare:CC (zero_extend:DI |
5226 | (subreg:QI | |
29ae5b89 JL |
5227 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5228 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 5229 | (const_int 0))) |
29ae5b89 | 5230 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
5231 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
5232 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5233 | "rld%I2cl. %0,%1,%H2,56" |
5234 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
5235 | |
5236 | (define_insn "*rotldi3_internal10" | |
5237 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5238 | (zero_extend:DI | |
5239 | (subreg:HI | |
5240 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5241 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
5242 | "TARGET_POWERPC64" | |
5243 | "rld%I2cl %0,%1,%H2,48") | |
5244 | ||
5245 | (define_insn "*rotldi3_internal11" | |
29ae5b89 | 5246 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
a260abc9 DE |
5247 | (compare:CC (zero_extend:DI |
5248 | (subreg:HI | |
29ae5b89 JL |
5249 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5250 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 5251 | (const_int 0))) |
29ae5b89 | 5252 | (clobber (match_scratch:DI 3 "=r"))] |
a260abc9 | 5253 | "TARGET_POWERPC64" |
29ae5b89 JL |
5254 | "rld%I2cl. %3,%1,%H2,48" |
5255 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
5256 | |
5257 | (define_insn "*rotldi3_internal12" | |
29ae5b89 | 5258 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
a260abc9 DE |
5259 | (compare:CC (zero_extend:DI |
5260 | (subreg:HI | |
29ae5b89 JL |
5261 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5262 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 5263 | (const_int 0))) |
29ae5b89 | 5264 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
5265 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
5266 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5267 | "rld%I2cl. %0,%1,%H2,48" |
5268 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
5269 | |
5270 | (define_insn "*rotldi3_internal13" | |
5271 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5272 | (zero_extend:DI | |
5273 | (subreg:SI | |
5274 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5275 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
5276 | "TARGET_POWERPC64" | |
5277 | "rld%I2cl %0,%1,%H2,32") | |
5278 | ||
5279 | (define_insn "*rotldi3_internal14" | |
29ae5b89 | 5280 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
a260abc9 DE |
5281 | (compare:CC (zero_extend:DI |
5282 | (subreg:SI | |
29ae5b89 JL |
5283 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5284 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 5285 | (const_int 0))) |
29ae5b89 | 5286 | (clobber (match_scratch:DI 3 "=r"))] |
a260abc9 | 5287 | "TARGET_POWERPC64" |
29ae5b89 JL |
5288 | "rld%I2cl. %3,%1,%H2,32" |
5289 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 DE |
5290 | |
5291 | (define_insn "*rotldi3_internal15" | |
29ae5b89 | 5292 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
a260abc9 DE |
5293 | (compare:CC (zero_extend:DI |
5294 | (subreg:SI | |
29ae5b89 JL |
5295 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
5296 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)) | |
a260abc9 | 5297 | (const_int 0))) |
29ae5b89 | 5298 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
5299 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
5300 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5301 | "rld%I2cl. %0,%1,%H2,32" |
5302 | [(set_attr "type" "delayed_compare")]) | |
a260abc9 | 5303 | |
266eb58a DE |
5304 | (define_expand "ashldi3" |
5305 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5306 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5307 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
5308 | "TARGET_POWERPC64 || TARGET_POWER" | |
5309 | " | |
5310 | { | |
5311 | if (TARGET_POWERPC64) | |
5312 | ; | |
5313 | else if (TARGET_POWER) | |
5314 | { | |
5315 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
5316 | DONE; | |
5317 | } | |
5318 | else | |
5319 | FAIL; | |
5320 | }") | |
5321 | ||
5322 | (define_insn "" | |
5323 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5324 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5325 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
5326 | "TARGET_POWERPC64" | |
a66078ee | 5327 | "sld%I2 %0,%1,%H2" |
266eb58a DE |
5328 | [(set_attr "length" "8")]) |
5329 | ||
5330 | (define_insn "" | |
29ae5b89 JL |
5331 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5332 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5333 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5334 | (const_int 0))) |
29ae5b89 | 5335 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5336 | "TARGET_POWERPC64" |
29ae5b89 JL |
5337 | "sld%I2. %3,%1,%H2" |
5338 | [(set_attr "type" "delayed_compare")]) | |
5339 | ||
266eb58a | 5340 | (define_insn "" |
29ae5b89 JL |
5341 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5342 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5343 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5344 | (const_int 0))) |
29ae5b89 | 5345 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5346 | (ashift:DI (match_dup 1) (match_dup 2)))] |
5347 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5348 | "sld%I2. %0,%1,%H2" |
5349 | [(set_attr "type" "delayed_compare")]) | |
266eb58a DE |
5350 | |
5351 | (define_expand "lshrdi3" | |
5352 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5353 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5354 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
5355 | "TARGET_POWERPC64 || TARGET_POWER" | |
5356 | " | |
5357 | { | |
5358 | if (TARGET_POWERPC64) | |
5359 | ; | |
5360 | else if (TARGET_POWER) | |
5361 | { | |
5362 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
5363 | DONE; | |
5364 | } | |
5365 | else | |
5366 | FAIL; | |
5367 | }") | |
5368 | ||
5369 | (define_insn "" | |
5370 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5371 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5372 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
5373 | "TARGET_POWERPC64" | |
a66078ee | 5374 | "srd%I2 %0,%1,%H2") |
266eb58a DE |
5375 | |
5376 | (define_insn "" | |
29ae5b89 JL |
5377 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5378 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5379 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
5380 | (const_int 0))) | |
5381 | (clobber (match_scratch:DI 3 "=r"))] | |
5382 | "TARGET_POWERPC64" | |
5383 | "srd%I2. %3,%1,%H2" | |
5384 | [(set_attr "type" "delayed_compare")]) | |
266eb58a | 5385 | |
29ae5b89 JL |
5386 | (define_insn "" |
5387 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") | |
5388 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5389 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5390 | (const_int 0))) |
29ae5b89 JL |
5391 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
5392 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
5393 | "TARGET_POWERPC64" | |
5394 | "srd%I2. %0,%1,%H2" | |
5395 | [(set_attr "type" "delayed_compare")]) | |
266eb58a DE |
5396 | |
5397 | (define_expand "ashrdi3" | |
5398 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5399 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5400 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
5401 | "TARGET_POWERPC64 || TARGET_POWER" | |
5402 | " | |
5403 | { | |
5404 | if (TARGET_POWERPC64) | |
5405 | ; | |
5406 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
5407 | { | |
5408 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
5409 | DONE; | |
5410 | } | |
5411 | else | |
5412 | FAIL; | |
5413 | }") | |
5414 | ||
5415 | (define_insn "" | |
5416 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5417 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5418 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
5419 | "TARGET_POWERPC64" | |
375490e0 | 5420 | "srad%I2 %0,%1,%H2") |
266eb58a DE |
5421 | |
5422 | (define_insn "" | |
29ae5b89 JL |
5423 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5424 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5425 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5426 | (const_int 0))) |
29ae5b89 | 5427 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5428 | "TARGET_POWERPC64" |
29ae5b89 JL |
5429 | "srad%I2. %3,%1,%H2" |
5430 | [(set_attr "type" "delayed_compare")]) | |
266eb58a DE |
5431 | |
5432 | (define_insn "" | |
29ae5b89 JL |
5433 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5434 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
5435 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) | |
266eb58a | 5436 | (const_int 0))) |
29ae5b89 | 5437 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5438 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
5439 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5440 | "srad%I2. %0,%1,%H2" |
5441 | [(set_attr "type" "delayed_compare")]) | |
815cdc52 | 5442 | |
29ae5b89 JL |
5443 | (define_insn "anddi3" |
5444 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") | |
5445 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5446 | (match_operand:DI 2 "and64_operand" "?r,S,K,J"))) | |
5447 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] | |
6ffc8580 | 5448 | "TARGET_POWERPC64" |
266eb58a DE |
5449 | "@ |
5450 | and %0,%1,%2 | |
29ae5b89 JL |
5451 | rldic%B2 %0,%1,0,%S2 |
5452 | andi. %0,%1,%b2 | |
5453 | andis. %0,%1,%u2") | |
266eb58a | 5454 | |
a260abc9 | 5455 | (define_insn "*anddi3_internal2" |
29ae5b89 JL |
5456 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") |
5457 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5458 | (match_operand:DI 2 "and64_operand" "r,K,J,S")) | |
266eb58a | 5459 | (const_int 0))) |
29ae5b89 | 5460 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
6ffc8580 | 5461 | "TARGET_POWERPC64" |
266eb58a DE |
5462 | "@ |
5463 | and. %3,%1,%2 | |
6ffc8580 MM |
5464 | andi. %3,%1,%b2 |
5465 | andis. %3,%1,%u2 | |
29ae5b89 JL |
5466 | rldic%B2. %3,%1,0,%S2" |
5467 | [(set_attr "type" "compare,compare,compare,delayed_compare")]) | |
266eb58a | 5468 | |
a260abc9 | 5469 | (define_insn "*anddi3_internal3" |
29ae5b89 JL |
5470 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") |
5471 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5472 | (match_operand:DI 2 "and64_operand" "r,K,J,S")) | |
266eb58a | 5473 | (const_int 0))) |
29ae5b89 JL |
5474 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
5475 | (and:DI (match_dup 1) (match_dup 2)))] | |
6ffc8580 | 5476 | "TARGET_POWERPC64" |
266eb58a DE |
5477 | "@ |
5478 | and. %0,%1,%2 | |
6ffc8580 MM |
5479 | andi. %0,%1,%b2 |
5480 | andis. %0,%1,%u2 | |
29ae5b89 JL |
5481 | rldic%B2. %3,%1,0,%S2" |
5482 | [(set_attr "type" "compare,compare,compare,delayed_compare")]) | |
266eb58a | 5483 | |
a260abc9 | 5484 | (define_expand "iordi3" |
266eb58a | 5485 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 DE |
5486 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
5487 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
266eb58a | 5488 | "TARGET_POWERPC64" |
266eb58a DE |
5489 | " |
5490 | { | |
a260abc9 DE |
5491 | if (GET_CODE (operands[2]) == CONST_INT |
5492 | && !logical_operand (operands[2], DImode)) | |
266eb58a | 5493 | { |
a260abc9 DE |
5494 | HOST_WIDE_INT value = INTVAL (operands[2]); |
5495 | rtx tmp = ((reload_in_progress || reload_completed | |
5496 | || rtx_equal_p (operands[0], operands[1])) | |
5497 | ? operands[0] : gen_reg_rtx (DImode)); | |
266eb58a | 5498 | |
a260abc9 DE |
5499 | emit_insn (gen_iordi3 (tmp, operands[1], |
5500 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
5501 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
5502 | DONE; | |
266eb58a | 5503 | } |
266eb58a DE |
5504 | }") |
5505 | ||
a260abc9 | 5506 | (define_insn "*iordi3_internal1" |
266eb58a DE |
5507 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
5508 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r") | |
5509 | (match_operand:DI 2 "logical_operand" "r,K,J")))] | |
5510 | "TARGET_POWERPC64" | |
5511 | "@ | |
5512 | or %0,%1,%2 | |
5513 | ori %0,%1,%b2 | |
5514 | oris %0,%1,%u2") | |
5515 | ||
a260abc9 | 5516 | (define_insn "*iordi3_internal2" |
29ae5b89 JL |
5517 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5518 | (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5519 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5520 | (const_int 0))) |
29ae5b89 | 5521 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5522 | "TARGET_POWERPC64" |
29ae5b89 JL |
5523 | "or. %3,%1,%2" |
5524 | [(set_attr "type" "compare")]) | |
266eb58a | 5525 | |
a260abc9 | 5526 | (define_insn "*iordi3_internal3" |
29ae5b89 JL |
5527 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5528 | (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5529 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5530 | (const_int 0))) |
29ae5b89 | 5531 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5532 | (ior:DI (match_dup 1) (match_dup 2)))] |
5533 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5534 | "or. %0,%1,%2" |
5535 | [(set_attr "type" "compare")]) | |
266eb58a DE |
5536 | |
5537 | ;; Split an IOR that we can't do in one insn into two insns, each of which | |
5538 | ;; does one 16-bit part. This is used by combine. | |
5539 | ||
5540 | (define_split | |
5541 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5542 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5543 | (match_operand:DI 2 "non_logical_cint_operand" "")))] | |
5544 | "TARGET_POWERPC64" | |
5545 | [(set (match_dup 0) (ior:DI (match_dup 1) (match_dup 3))) | |
5546 | (set (match_dup 0) (ior:DI (match_dup 0) (match_dup 4)))] | |
5547 | " | |
5548 | { | |
3a598fbe | 5549 | operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); |
89e9f3a8 | 5550 | operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
266eb58a | 5551 | }") |
1fd4e8c1 | 5552 | |
a260abc9 DE |
5553 | (define_expand "xordi3" |
5554 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5555 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5556 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
5557 | "TARGET_POWERPC64" | |
5558 | " | |
5559 | { | |
5560 | if (GET_CODE (operands[2]) == CONST_INT | |
5561 | && !logical_operand (operands[2], DImode)) | |
5562 | { | |
5563 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
5564 | rtx tmp = ((reload_in_progress || reload_completed | |
5565 | || rtx_equal_p (operands[0], operands[1])) | |
5566 | ? operands[0] : gen_reg_rtx (DImode)); | |
5567 | ||
5568 | emit_insn (gen_xordi3 (tmp, operands[1], | |
5569 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
5570 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
5571 | DONE; | |
5572 | } | |
5573 | }") | |
5574 | ||
5575 | (define_insn "*xordi3_internal1" | |
266eb58a DE |
5576 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
5577 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r") | |
5578 | (match_operand:DI 2 "logical_operand" "r,K,J")))] | |
5579 | "TARGET_POWERPC64" | |
1fd4e8c1 | 5580 | "@ |
266eb58a DE |
5581 | xor %0,%1,%2 |
5582 | xori %0,%1,%b2 | |
5583 | xoris %0,%1,%u2") | |
1fd4e8c1 | 5584 | |
a260abc9 | 5585 | (define_insn "*xordi3_internal2" |
29ae5b89 JL |
5586 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5587 | (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5588 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5589 | (const_int 0))) |
29ae5b89 | 5590 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5591 | "TARGET_POWERPC64" |
29ae5b89 JL |
5592 | "xor. %3,%1,%2" |
5593 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 5594 | |
a260abc9 | 5595 | (define_insn "*xordi3_internal3" |
29ae5b89 JL |
5596 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5597 | (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5598 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5599 | (const_int 0))) |
29ae5b89 | 5600 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5601 | (xor:DI (match_dup 1) (match_dup 2)))] |
5602 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5603 | "xor. %0,%1,%2" |
5604 | [(set_attr "type" "compare")]) | |
1fd4e8c1 | 5605 | |
266eb58a DE |
5606 | ;; Split an XOR that we can't do in one insn into two insns, each of which |
5607 | ;; does one 16-bit part. This is used by combine. | |
5608 | ||
5609 | (define_split | |
5610 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
a260abc9 DE |
5611 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") |
5612 | (match_operand:DI 2 "non_logical_cint_operand" "")))] | |
266eb58a DE |
5613 | "TARGET_POWERPC64" |
5614 | [(set (match_dup 0) (xor:DI (match_dup 1) (match_dup 3))) | |
5615 | (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 4)))] | |
5616 | " | |
5617 | { | |
a260abc9 | 5618 | operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); |
89e9f3a8 | 5619 | operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff); |
1fd4e8c1 RK |
5620 | }") |
5621 | ||
a260abc9 | 5622 | (define_insn "*eqvdi3_internal1" |
266eb58a DE |
5623 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
5624 | (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5625 | (match_operand:DI 2 "gpc_reg_operand" "r"))))] | |
5626 | "TARGET_POWERPC64" | |
5627 | "eqv %0,%1,%2") | |
a473029f | 5628 | |
a260abc9 | 5629 | (define_insn "*eqvdi3_internal2" |
29ae5b89 JL |
5630 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5631 | (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5632 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
815cdc52 | 5633 | (const_int 0))) |
29ae5b89 JL |
5634 | (clobber (match_scratch:DI 3 "=r"))] |
5635 | "TARGET_POWERPC64" | |
5636 | "eqv. %3,%1,%2" | |
5637 | [(set_attr "type" "compare")]) | |
a473029f | 5638 | |
a260abc9 | 5639 | (define_insn "*eqvdi3_internal3" |
29ae5b89 JL |
5640 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5641 | (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5642 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
266eb58a | 5643 | (const_int 0))) |
29ae5b89 | 5644 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a | 5645 | (not:DI (xor:DI (match_dup 1) (match_dup 2))))] |
29ae5b89 JL |
5646 | "TARGET_POWERPC64" |
5647 | "eqv. %0,%1,%2" | |
5648 | [(set_attr "type" "compare")]) | |
266eb58a | 5649 | |
a260abc9 | 5650 | (define_insn "*andcdi3_internal1" |
a473029f | 5651 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5652 | (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) |
5653 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
a473029f | 5654 | "TARGET_POWERPC64" |
266eb58a | 5655 | "andc %0,%2,%1") |
a473029f | 5656 | |
a260abc9 | 5657 | (define_insn "*andcdi3_internal2" |
29ae5b89 JL |
5658 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5659 | (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
5660 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5661 | (const_int 0))) |
29ae5b89 | 5662 | (clobber (match_scratch:DI 3 "=r"))] |
a473029f | 5663 | "TARGET_POWERPC64" |
29ae5b89 JL |
5664 | "andc. %3,%2,%1" |
5665 | [(set_attr "type" "compare")]) | |
a473029f | 5666 | |
a260abc9 | 5667 | (define_insn "*andcdi3_internal3" |
29ae5b89 JL |
5668 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5669 | (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
5670 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5671 | (const_int 0))) |
29ae5b89 | 5672 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a | 5673 | (and:DI (not:DI (match_dup 1)) (match_dup 2)))] |
a473029f | 5674 | "TARGET_POWERPC64" |
29ae5b89 JL |
5675 | "andc. %0,%2,%1" |
5676 | [(set_attr "type" "compare")]) | |
a473029f | 5677 | |
a260abc9 | 5678 | (define_insn "*iorcdi3_internal1" |
a473029f | 5679 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5680 | (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) |
5681 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
a473029f | 5682 | "TARGET_POWERPC64" |
266eb58a | 5683 | "orc %0,%2,%1") |
a473029f | 5684 | |
a260abc9 | 5685 | (define_insn "*iorcdi3_inernal2" |
29ae5b89 JL |
5686 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5687 | (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
5688 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5689 | (const_int 0))) |
29ae5b89 | 5690 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5691 | "TARGET_POWERPC64" |
29ae5b89 JL |
5692 | "orc. %3,%2,%1" |
5693 | [(set_attr "type" "compare")]) | |
266eb58a | 5694 | |
a260abc9 | 5695 | (define_insn "*iorcdi3_internal3" |
29ae5b89 JL |
5696 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5697 | (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
5698 | (match_operand:DI 2 "gpc_reg_operand" "r")) | |
266eb58a | 5699 | (const_int 0))) |
29ae5b89 | 5700 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5701 | (ior:DI (not:DI (match_dup 1)) (match_dup 2)))] |
5702 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5703 | "orc. %0,%2,%1" |
5704 | [(set_attr "type" "compare")]) | |
266eb58a | 5705 | |
a260abc9 | 5706 | (define_insn "*nanddi3_internal1" |
a473029f | 5707 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
29ae5b89 | 5708 | (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) |
266eb58a | 5709 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))] |
a473029f | 5710 | "TARGET_POWERPC64" |
266eb58a | 5711 | "nand %0,%1,%2") |
a473029f | 5712 | |
a260abc9 | 5713 | (define_insn "*nanddi3_internal2" |
29ae5b89 JL |
5714 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
5715 | (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5716 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
266eb58a | 5717 | (const_int 0))) |
29ae5b89 | 5718 | (clobber (match_scratch:DI 3 "=r"))] |
266eb58a | 5719 | "TARGET_POWERPC64" |
29ae5b89 JL |
5720 | "nand. %3,%1,%2" |
5721 | [(set_attr "type" "compare")]) | |
266eb58a | 5722 | |
a260abc9 | 5723 | (define_insn "*nanddi3_internal3" |
29ae5b89 JL |
5724 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5725 | (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5726 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
266eb58a | 5727 | (const_int 0))) |
29ae5b89 | 5728 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a DE |
5729 | (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))] |
5730 | "TARGET_POWERPC64" | |
29ae5b89 JL |
5731 | "nand. %0,%1,%2" |
5732 | [(set_attr "type" "compare")]) | |
266eb58a | 5733 | |
a260abc9 | 5734 | (define_insn "*nordi3_internal1" |
a473029f | 5735 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
29ae5b89 | 5736 | (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) |
266eb58a | 5737 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))] |
a473029f | 5738 | "TARGET_POWERPC64" |
266eb58a | 5739 | "nor %0,%1,%2") |
a473029f | 5740 | |
29ae5b89 JL |
5741 | (define_insn "*nordi3_internal2" |
5742 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
5743 | (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5744 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
815cdc52 | 5745 | (const_int 0))) |
29ae5b89 JL |
5746 | (clobber (match_scratch:DI 3 "=r"))] |
5747 | "TARGET_POWERPC64" | |
5748 | "nor. %3,%1,%2" | |
5749 | [(set_attr "type" "compare")]) | |
a473029f | 5750 | |
a260abc9 | 5751 | (define_insn "*nordi3_internal3" |
29ae5b89 JL |
5752 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
5753 | (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
5754 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
a473029f | 5755 | (const_int 0))) |
29ae5b89 | 5756 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
266eb58a | 5757 | (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))] |
a473029f | 5758 | "TARGET_POWERPC64" |
29ae5b89 JL |
5759 | "nor. %0,%1,%2" |
5760 | [(set_attr "type" "compare")]) | |
a473029f | 5761 | \f |
1fd4e8c1 | 5762 | ;; Now define ways of moving data around. |
4697a36c MM |
5763 | |
5764 | ;; Elf specific ways of loading addresses for non-PIC code. | |
5765 | ;; The output of this could be r0, but we limit it to base | |
5766 | ;; registers, since almost all uses of this will need it | |
5767 | ;; in a base register shortly. | |
5768 | (define_insn "elf_high" | |
52d3af72 | 5769 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
4697a36c MM |
5770 | (high:SI (match_operand 1 "" "")))] |
5771 | "TARGET_ELF && !TARGET_64BIT" | |
a6c2a102 | 5772 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
5773 | |
5774 | (define_insn "elf_low" | |
52d3af72 DE |
5775 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5776 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
4697a36c MM |
5777 | (match_operand 2 "" "")))] |
5778 | "TARGET_ELF && !TARGET_64BIT" | |
a6c2a102 | 5779 | "{cal|la} %0,%2@l(%1)") |
4697a36c | 5780 | |
766a866c MM |
5781 | ;; Set up a register with a value from the GOT table |
5782 | ||
5783 | (define_expand "movsi_got" | |
52d3af72 | 5784 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
766a866c MM |
5785 | (unspec [(match_operand:SI 1 "got_operand" "") |
5786 | (match_dup 2)] 8))] | |
58307bcd | 5787 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
5788 | " |
5789 | { | |
38c1f2d7 MM |
5790 | if (GET_CODE (operands[1]) == CONST) |
5791 | { | |
5792 | rtx offset = const0_rtx; | |
5793 | HOST_WIDE_INT value; | |
5794 | ||
5795 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
5796 | value = INTVAL (offset); | |
5797 | if (value != 0) | |
5798 | { | |
5799 | rtx tmp = ((reload_in_progress || reload_completed) | |
5800 | ? operands[0] | |
5801 | : gen_reg_rtx (Pmode)); | |
5802 | emit_insn (gen_movsi_got (tmp, operands[1])); | |
5803 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
5804 | DONE; | |
5805 | } | |
5806 | } | |
5807 | ||
c4c40373 | 5808 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
5809 | }") |
5810 | ||
84f414bc | 5811 | (define_insn "*movsi_got_internal" |
52d3af72 | 5812 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
38c1f2d7 | 5813 | (unspec [(match_operand:SI 1 "got_no_const_operand" "") |
52d3af72 | 5814 | (match_operand:SI 2 "gpc_reg_operand" "b")] 8))] |
c81bebd7 | 5815 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
5816 | "{l|lwz} %0,%a1@got(%2)" |
5817 | [(set_attr "type" "load")]) | |
5818 | ||
b22b9b3e JL |
5819 | ;; Sometimes, though, the GOT `register' will be on the stack. Deal with |
5820 | ;; this case specially. | |
5821 | ;; Force final to split this insn (if it hasn't been split already) to | |
5822 | ;; avoid having to create a suitable output template. | |
5823 | (define_insn "*movsi_got_internal_mem" | |
52d3af72 | 5824 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
b22b9b3e JL |
5825 | (unspec [(match_operand:SI 1 "got_no_const_operand" "") |
5826 | (match_operand:SI 2 "memory_operand" "m")] 8))] | |
5827 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
5828 | && flag_pic == 1 | |
5829 | && (reload_in_progress || reload_completed)" | |
5830 | "#" | |
5831 | [(set_attr "type" "load") | |
5832 | (set_attr "length" "8")]) | |
5833 | ||
5834 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg | |
5835 | ;; didn't get allocated to a hard register. | |
5836 | (define_split | |
52d3af72 | 5837 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
b22b9b3e JL |
5838 | (unspec [(match_operand:SI 1 "got_no_const_operand" "") |
5839 | (match_operand:SI 2 "memory_operand" "m")] 8))] | |
5840 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) | |
5841 | && flag_pic == 1 | |
5842 | && (reload_in_progress || reload_completed)" | |
5843 | [(set (match_dup 0) (match_dup 2)) | |
5844 | (set (match_dup 0) (unspec [(match_dup 1)(match_dup 0)] 8))] | |
5845 | "") | |
5846 | ||
1fd4e8c1 RK |
5847 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
5848 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
5849 | ;; and this is even supposed to be faster, but it is simpler not to get | |
5850 | ;; integers in the TOC. | |
5851 | (define_expand "movsi" | |
5852 | [(set (match_operand:SI 0 "general_operand" "") | |
5853 | (match_operand:SI 1 "any_operand" ""))] | |
5854 | "" | |
5855 | " | |
5856 | { | |
5857 | if (GET_CODE (operands[0]) != REG) | |
5858 | operands[1] = force_reg (SImode, operands[1]); | |
5859 | ||
ef0e171b RK |
5860 | /* Convert a move of a CONST_DOUBLE into a CONST_INT */ |
5861 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
5862 | operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
5863 | ||
34792e82 | 5864 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 5865 | if (GET_CODE (operands[1]) == CONSTANT_P_RTX) |
34792e82 JL |
5866 | { |
5867 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
5868 | DONE; | |
5869 | } | |
5870 | ||
88228c4b MM |
5871 | /* Use default pattern for address of ELF small data */ |
5872 | if (TARGET_ELF | |
c81bebd7 | 5873 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
88228c4b | 5874 | && (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST) |
e98bb982 | 5875 | && small_data_operand (operands[1], SImode)) |
88228c4b | 5876 | { |
39403d82 | 5877 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
88228c4b MM |
5878 | DONE; |
5879 | } | |
5880 | ||
c81bebd7 | 5881 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
84f414bc | 5882 | && flag_pic == 1 && got_operand (operands[1], SImode)) |
766a866c MM |
5883 | { |
5884 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
5885 | DONE; | |
5886 | } | |
5887 | ||
4697a36c | 5888 | if (TARGET_ELF && TARGET_NO_TOC && !TARGET_64BIT |
461422d5 | 5889 | && !flag_pic |
4697a36c MM |
5890 | && CONSTANT_P (operands[1]) |
5891 | && GET_CODE (operands[1]) != HIGH | |
34792e82 | 5892 | && GET_CODE (operands[1]) != CONST_INT) |
4697a36c MM |
5893 | { |
5894 | rtx target = (reload_completed || reload_in_progress) | |
5895 | ? operands[0] : gen_reg_rtx (SImode); | |
5896 | ||
b6c9286a MM |
5897 | /* If this is a function address on -mcall-aixdesc or -mcall-nt, |
5898 | convert it to the address of the descriptor. */ | |
5899 | if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) | |
5900 | && GET_CODE (operands[1]) == SYMBOL_REF | |
5901 | && XSTR (operands[1], 0)[0] == '.') | |
5902 | { | |
5903 | char *name = XSTR (operands[1], 0); | |
5904 | rtx new_ref; | |
5905 | while (*name == '.') | |
5906 | name++; | |
39403d82 | 5907 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); |
b6c9286a MM |
5908 | CONSTANT_POOL_ADDRESS_P (new_ref) = CONSTANT_POOL_ADDRESS_P (operands[1]); |
5909 | SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]); | |
5910 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); | |
5911 | operands[1] = new_ref; | |
5912 | } | |
5913 | ||
4697a36c MM |
5914 | emit_insn (gen_elf_high (target, operands[1])); |
5915 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
5916 | DONE; | |
5917 | } | |
5918 | ||
b6c9286a MM |
5919 | if (GET_CODE (operands[1]) == CONST |
5920 | && DEFAULT_ABI == ABI_NT | |
5921 | && !side_effects_p (operands[0])) | |
5922 | { | |
5923 | rtx const_term = const0_rtx; | |
5924 | rtx sym = eliminate_constant_term (XEXP (operands[1], 0), &const_term); | |
5925 | if (sym && GET_CODE (const_term) == CONST_INT | |
5926 | && (GET_CODE (sym) == SYMBOL_REF || GET_CODE (sym) == LABEL_REF)) | |
5927 | { | |
354b734b MM |
5928 | unsigned HOST_WIDE_INT value = INTVAL (const_term); |
5929 | int new_reg_p = (flag_expensive_optimizations | |
5930 | && !reload_completed | |
5931 | && !reload_in_progress); | |
5932 | rtx tmp1 = (new_reg_p && value != 0) ? gen_reg_rtx (SImode) : operands[0]; | |
5933 | ||
5934 | emit_insn (gen_movsi (tmp1, sym)); | |
b6c9286a | 5935 | if (INTVAL (const_term) != 0) |
38c1f2d7 | 5936 | emit_insn (gen_addsi3 (operands[0], tmp1, GEN_INT (value))); |
b6c9286a MM |
5937 | DONE; |
5938 | } | |
5939 | else | |
a6c2a102 | 5940 | rs6000_fatal_bad_address (operands[1]); |
b6c9286a MM |
5941 | } |
5942 | ||
5943 | if ((!TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT) | |
5944 | && CONSTANT_P (operands[1]) | |
4697a36c MM |
5945 | && GET_CODE (operands[1]) != CONST_INT |
5946 | && GET_CODE (operands[1]) != HIGH | |
78b8d850 | 5947 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])) |
b45863ec | 5948 | { |
d302f4f2 MM |
5949 | /* Emit a USE operation so that the constant isn't deleted if |
5950 | expensive optimizations are turned on because nobody | |
e0350319 MM |
5951 | references it. This should only be done for operands that |
5952 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
5953 | This should not be done for operands that contain LABEL_REFs. | |
5954 | For now, we just handle the obvious case. */ | |
5955 | if (GET_CODE (operands[1]) != LABEL_REF) | |
39403d82 | 5956 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); |
d302f4f2 | 5957 | |
30a4619d RK |
5958 | /* If we are to limit the number of things we put in the TOC and |
5959 | this is a symbol plus a constant we can add in one insn, | |
abc95ed3 | 5960 | just put the symbol in the TOC and add the constant. Don't do |
30a4619d RK |
5961 | this if reload is in progress. */ |
5962 | if (GET_CODE (operands[1]) == CONST | |
5963 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
5964 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
5965 | && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode) | |
5966 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF | |
5967 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
5968 | && ! side_effects_p (operands[0])) | |
5969 | { | |
5970 | rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0)); | |
5971 | rtx other = XEXP (XEXP (operands[1], 0), 1); | |
5972 | ||
5973 | emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other)); | |
5974 | DONE; | |
5975 | } | |
5976 | ||
b45863ec RK |
5977 | operands[1] = force_const_mem (SImode, operands[1]); |
5978 | if (! memory_address_p (SImode, XEXP (operands[1], 0)) | |
5979 | && ! reload_in_progress) | |
5980 | operands[1] = change_address (operands[1], SImode, | |
5981 | XEXP (operands[1], 0)); | |
5982 | } | |
1fd4e8c1 RK |
5983 | }") |
5984 | ||
5985 | (define_insn "" | |
a260abc9 DE |
5986 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h") |
5987 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,J,n,R,*h,r,r,0"))] | |
19d5775a RK |
5988 | "gpc_reg_operand (operands[0], SImode) |
5989 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 5990 | "@ |
deb9225a | 5991 | mr %0,%1 |
b9442c72 | 5992 | {cal|la} %0,%a1 |
ca7f5001 RK |
5993 | {l%U1%X1|lwz%U1%X1} %0,%1 |
5994 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 5995 | {lil|li} %0,%1 |
802a0058 | 5996 | {liu|lis} %0,%v1 |
beaec479 | 5997 | # |
57fa6739 | 5998 | {cal|la} %0,%1(%*) |
1fd4e8c1 | 5999 | mf%1 %0 |
5c23c401 | 6000 | mt%0 %1 |
e76e75bb RK |
6001 | mt%0 %1 |
6002 | cror 0,0,0" | |
a260abc9 DE |
6003 | [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*") |
6004 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")]) | |
1fd4e8c1 | 6005 | |
77fa0940 RK |
6006 | ;; Split a load of a large constant into the appropriate two-insn |
6007 | ;; sequence. | |
6008 | ||
6009 | (define_split | |
6010 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
6011 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 6012 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
6013 | && (INTVAL (operands[1]) & 0xffff) != 0" |
6014 | [(set (match_dup 0) | |
6015 | (match_dup 2)) | |
6016 | (set (match_dup 0) | |
6017 | (ior:SI (match_dup 0) | |
6018 | (match_dup 3)))] | |
6019 | " | |
6020 | { | |
3a598fbe | 6021 | operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000); |
89e9f3a8 | 6022 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); |
77fa0940 RK |
6023 | }") |
6024 | ||
1fd4e8c1 | 6025 | (define_insn "" |
29ae5b89 JL |
6026 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
6027 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 6028 | (const_int 0))) |
29ae5b89 | 6029 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] |
1fd4e8c1 | 6030 | "" |
29ae5b89 | 6031 | "mr. %0,%1" |
1fd4e8c1 RK |
6032 | [(set_attr "type" "compare")]) |
6033 | \f | |
6034 | (define_expand "movhi" | |
6035 | [(set (match_operand:HI 0 "general_operand" "") | |
6036 | (match_operand:HI 1 "any_operand" ""))] | |
6037 | "" | |
6038 | " | |
6039 | { | |
6040 | if (GET_CODE (operands[0]) != REG) | |
6041 | operands[1] = force_reg (HImode, operands[1]); | |
6042 | ||
3345af62 | 6043 | if (CONSTANT_P (operands[1]) |
34792e82 | 6044 | && GET_CODE (operands[1]) != CONST_INT) |
b45863ec RK |
6045 | { |
6046 | operands[1] = force_const_mem (HImode, operands[1]); | |
6047 | if (! memory_address_p (HImode, XEXP (operands[1], 0)) | |
6048 | && ! reload_in_progress) | |
6049 | operands[1] = change_address (operands[1], HImode, | |
6050 | XEXP (operands[1], 0)); | |
6051 | } | |
1fd4e8c1 RK |
6052 | }") |
6053 | ||
6054 | (define_insn "" | |
fb81d7ce RK |
6055 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
6056 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
6057 | "gpc_reg_operand (operands[0], HImode) |
6058 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 6059 | "@ |
deb9225a | 6060 | mr %0,%1 |
1fd4e8c1 RK |
6061 | lhz%U1%X1 %0,%1 |
6062 | sth%U0%X0 %1,%0 | |
19d5775a | 6063 | {lil|li} %0,%w1 |
1fd4e8c1 | 6064 | mf%1 %0 |
e76e75bb | 6065 | mt%0 %1 |
fb81d7ce | 6066 | mt%0 %1 |
e76e75bb | 6067 | cror 0,0,0" |
b7ff3d82 | 6068 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
6069 | |
6070 | (define_expand "movqi" | |
6071 | [(set (match_operand:QI 0 "general_operand" "") | |
6072 | (match_operand:QI 1 "any_operand" ""))] | |
6073 | "" | |
6074 | " | |
6075 | { | |
6076 | if (GET_CODE (operands[0]) != REG) | |
6077 | operands[1] = force_reg (QImode, operands[1]); | |
6078 | ||
3345af62 | 6079 | if (CONSTANT_P (operands[1]) |
34792e82 | 6080 | && GET_CODE (operands[1]) != CONST_INT) |
b45863ec RK |
6081 | { |
6082 | operands[1] = force_const_mem (QImode, operands[1]); | |
6083 | if (! memory_address_p (QImode, XEXP (operands[1], 0)) | |
6084 | && ! reload_in_progress) | |
6085 | operands[1] = change_address (operands[1], QImode, | |
6086 | XEXP (operands[1], 0)); | |
6087 | } | |
1fd4e8c1 RK |
6088 | }") |
6089 | ||
6090 | (define_insn "" | |
fb81d7ce RK |
6091 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
6092 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
6093 | "gpc_reg_operand (operands[0], QImode) |
6094 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 6095 | "@ |
deb9225a | 6096 | mr %0,%1 |
1fd4e8c1 RK |
6097 | lbz%U1%X1 %0,%1 |
6098 | stb%U0%X0 %1,%0 | |
19d5775a | 6099 | {lil|li} %0,%1 |
1fd4e8c1 | 6100 | mf%1 %0 |
e76e75bb | 6101 | mt%0 %1 |
fb81d7ce | 6102 | mt%0 %1 |
e76e75bb | 6103 | cror 0,0,0" |
b7ff3d82 | 6104 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
6105 | \f |
6106 | ;; Here is how to move condition codes around. When we store CC data in | |
6107 | ;; an integer register or memory, we store just the high-order 4 bits. | |
6108 | ;; This lets us not shift in the most common case of CR0. | |
6109 | (define_expand "movcc" | |
6110 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
6111 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
6112 | "" | |
6113 | "") | |
6114 | ||
6115 | (define_insn "" | |
6116 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") | |
6117 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] | |
6118 | "register_operand (operands[0], CCmode) | |
6119 | || register_operand (operands[1], CCmode)" | |
6120 | "@ | |
6121 | mcrf %0,%1 | |
6122 | mtcrf 128,%1 | |
ca7f5001 | 6123 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
1fd4e8c1 | 6124 | mfcr %0 |
ca7f5001 | 6125 | mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 |
deb9225a | 6126 | mr %0,%1 |
ca7f5001 RK |
6127 | {l%U1%X1|lwz%U1%X1} %0,%1 |
6128 | {st%U0%U1|stw%U0%U1} %1,%0" | |
b7ff3d82 | 6129 | [(set_attr "type" "*,*,*,compare,*,*,load,store") |
b19003d8 | 6130 | (set_attr "length" "*,*,12,*,8,*,*,*")]) |
1fd4e8c1 | 6131 | \f |
e52e05ca MM |
6132 | ;; For floating-point, we normally deal with the floating-point registers |
6133 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
6134 | ;; can produce floating-point values in fixed-point registers. Unless the | |
6135 | ;; value is a simple constant or already in memory, we deal with this by | |
6136 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
6137 | (define_expand "movsf" |
6138 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
6139 | (match_operand:SF 1 "any_operand" ""))] | |
6140 | "" | |
6141 | " | |
6142 | { | |
6143 | /* If we are called from reload, we might be getting a SUBREG of a hard | |
6144 | reg. So expand it. */ | |
6145 | if (GET_CODE (operands[0]) == SUBREG | |
6146 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
6147 | && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER) | |
6148 | operands[0] = alter_subreg (operands[0]); | |
6149 | if (GET_CODE (operands[1]) == SUBREG | |
6150 | && GET_CODE (SUBREG_REG (operands[1])) == REG | |
6151 | && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER) | |
6152 | operands[1] = alter_subreg (operands[1]); | |
6153 | ||
f99f88e0 | 6154 | if (GET_CODE (operands[0]) == MEM) |
1fd4e8c1 | 6155 | { |
f99f88e0 DE |
6156 | /* If operands[1] is a register, it may have double-precision data |
6157 | in it, so truncate it to single precision. We need not do | |
6158 | this for POWERPC. */ | |
6159 | if (! TARGET_POWERPC && TARGET_HARD_FLOAT | |
6160 | && GET_CODE (operands[1]) == REG | |
6161 | && (FP_REGNO_P (REGNO (operands[1])) | |
6162 | || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)) | |
f2974b07 | 6163 | { |
f99f88e0 DE |
6164 | rtx newreg |
6165 | = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode); | |
6166 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); | |
6167 | operands[1] = newreg; | |
f2974b07 RK |
6168 | } |
6169 | ||
f99f88e0 | 6170 | operands[1] = force_reg (SFmode, operands[1]); |
1fd4e8c1 RK |
6171 | } |
6172 | ||
c4c40373 | 6173 | if (CONSTANT_P (operands[1]) && TARGET_HARD_FLOAT) |
1fd4e8c1 RK |
6174 | { |
6175 | operands[1] = force_const_mem (SFmode, operands[1]); | |
6176 | if (! memory_address_p (SFmode, XEXP (operands[1], 0)) | |
6177 | && ! reload_in_progress) | |
6178 | operands[1] = change_address (operands[1], SFmode, | |
6179 | XEXP (operands[1], 0)); | |
6180 | } | |
6181 | }") | |
6182 | ||
1fd4e8c1 | 6183 | (define_split |
cd2b37d9 | 6184 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 6185 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 6186 | "reload_completed |
5ae4759c MM |
6187 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
6188 | || (GET_CODE (operands[0]) == SUBREG | |
6189 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
6190 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 6191 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
6192 | " |
6193 | { | |
6194 | long l; | |
6195 | REAL_VALUE_TYPE rv; | |
6196 | ||
6197 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
6198 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 6199 | |
f99f88e0 DE |
6200 | if (! TARGET_POWERPC64) |
6201 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
6202 | else | |
6203 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 6204 | |
a260abc9 DE |
6205 | operands[3] = GEN_INT(l); |
6206 | }") | |
6207 | ||
c4c40373 | 6208 | (define_insn "*movsf_hardfloat" |
f99f88e0 DE |
6209 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r") |
6210 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))] | |
d14a6d05 MM |
6211 | "(gpc_reg_operand (operands[0], SFmode) |
6212 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT" | |
1fd4e8c1 | 6213 | "@ |
f99f88e0 DE |
6214 | mr %0,%1 |
6215 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
6216 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
6217 | fmr %0,%1 |
6218 | lfs%U1%X1 %0,%1 | |
c4c40373 MM |
6219 | stfs%U0%X0 %1,%0 |
6220 | # | |
6221 | #" | |
f99f88e0 DE |
6222 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*") |
6223 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 6224 | |
c4c40373 MM |
6225 | (define_insn "*movsf_softfloat" |
6226 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r") | |
6227 | (match_operand:SF 1 "input_operand" "r,m,r,I,J,R,G,Fn"))] | |
d14a6d05 MM |
6228 | "(gpc_reg_operand (operands[0], SFmode) |
6229 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT" | |
6230 | "@ | |
6231 | mr %0,%1 | |
6232 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
6233 | {st%U0%X0|stw%U0%X0} %1,%0 | |
6234 | {lil|li} %0,%1 | |
802a0058 | 6235 | {liu|lis} %0,%v1 |
c4c40373 MM |
6236 | {cal|la} %0,%1(%*) |
6237 | # | |
6238 | #" | |
6239 | [(set_attr "type" "*,load,store,*,*,*,*,*") | |
6240 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 6241 | |
1fd4e8c1 RK |
6242 | \f |
6243 | (define_expand "movdf" | |
6244 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
6245 | (match_operand:DF 1 "any_operand" ""))] | |
6246 | "" | |
6247 | " | |
6248 | { | |
e7113111 RK |
6249 | if (GET_CODE (operands[0]) != REG) |
6250 | operands[1] = force_reg (DFmode, operands[1]); | |
1fd4e8c1 | 6251 | |
e7113111 | 6252 | if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode)) |
1fd4e8c1 RK |
6253 | { |
6254 | operands[1] = force_const_mem (DFmode, operands[1]); | |
6255 | if (! memory_address_p (DFmode, XEXP (operands[1], 0)) | |
6256 | && ! reload_in_progress) | |
6257 | operands[1] = change_address (operands[1], DFmode, | |
6258 | XEXP (operands[1], 0)); | |
6259 | } | |
e7113111 | 6260 | }") |
1fd4e8c1 RK |
6261 | |
6262 | (define_split | |
cd2b37d9 | 6263 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 6264 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 6265 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
6266 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
6267 | || (GET_CODE (operands[0]) == SUBREG | |
6268 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
6269 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
6270 | [(set (match_dup 2) (match_dup 4)) |
6271 | (set (match_dup 3) (match_dup 1))] | |
6272 | " | |
6273 | { | |
5ae4759c MM |
6274 | int endian = (WORDS_BIG_ENDIAN == 0); |
6275 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); | |
6276 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
c4c40373 MM |
6277 | operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx; |
6278 | }") | |
6279 | ||
c4c40373 MM |
6280 | (define_split |
6281 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
6282 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 6283 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
6284 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
6285 | || (GET_CODE (operands[0]) == SUBREG | |
6286 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
6287 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
6288 | [(set (match_dup 2) (match_dup 4)) |
6289 | (set (match_dup 3) (match_dup 5))] | |
6290 | " | |
6291 | { | |
5ae4759c | 6292 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
6293 | long l[2]; |
6294 | REAL_VALUE_TYPE rv; | |
6295 | ||
6296 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
6297 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
6298 | ||
5ae4759c MM |
6299 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
6300 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
47ad8c61 MM |
6301 | operands[4] = GEN_INT (l[endian]); |
6302 | operands[5] = GEN_INT (l[1 - endian]); | |
c4c40373 MM |
6303 | }") |
6304 | ||
efc08378 DE |
6305 | (define_split |
6306 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 6307 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 6308 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
6309 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
6310 | || (GET_CODE (operands[0]) == SUBREG | |
6311 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
6312 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 6313 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 6314 | " |
a260abc9 DE |
6315 | { |
6316 | int endian = (WORDS_BIG_ENDIAN == 0); | |
6317 | long l[2]; | |
6318 | REAL_VALUE_TYPE rv; | |
6319 | ||
6320 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
6321 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
6322 | ||
6323 | operands[2] = gen_lowpart (DImode, operands[0]); | |
6324 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
6325 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); | |
6326 | }") | |
efc08378 | 6327 | |
4eae5fe1 | 6328 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 6329 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
6330 | ;; a non-offsettable memref, but also it is less efficient than loading |
6331 | ;; the constant into an FP register, since it will probably be used there. | |
6332 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
6333 | ;; of handling these non-offsettable values. | |
c4c40373 MM |
6334 | (define_insn "*movdf_hardfloat32" |
6335 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m") | |
6336 | (match_operand:DF 1 "input_operand" "r,o,r,G,H,F,f,m,f"))] | |
dc4f83ca | 6337 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
6338 | && (gpc_reg_operand (operands[0], DFmode) |
6339 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
6340 | "* |
6341 | { | |
6342 | switch (which_alternative) | |
6343 | { | |
a260abc9 | 6344 | default: |
a6c2a102 | 6345 | abort (); |
e7113111 RK |
6346 | case 0: |
6347 | /* We normally copy the low-numbered register first. However, if | |
6348 | the first register operand 0 is the same as the second register of | |
6349 | operand 1, we must copy in the opposite order. */ | |
6350 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 6351 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 6352 | else |
deb9225a | 6353 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 RK |
6354 | case 1: |
6355 | /* If the low-address word is used in the address, we must load it | |
6356 | last. Otherwise, load it first. Note that we cannot have | |
6357 | auto-increment in that case since the address register is known to be | |
6358 | dead. */ | |
6359 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
6360 | operands [1], 0)) | |
ca7f5001 | 6361 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
e7113111 | 6362 | else |
ca7f5001 | 6363 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
e7113111 | 6364 | case 2: |
ca7f5001 | 6365 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
e7113111 | 6366 | case 3: |
e7113111 | 6367 | case 4: |
e7113111 | 6368 | case 5: |
c4c40373 | 6369 | return \"#\"; |
e7113111 | 6370 | case 6: |
c4c40373 MM |
6371 | return \"fmr %0,%1\"; |
6372 | case 7: | |
6373 | return \"lfd%U1%X1 %0,%1\"; | |
6374 | case 8: | |
e7113111 RK |
6375 | return \"stfd%U0%X0 %1,%0\"; |
6376 | } | |
6377 | }" | |
c4c40373 MM |
6378 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
6379 | (set_attr "length" "8,8,8,8,12,16,*,*,*")]) | |
51b8fc2c | 6380 | |
c4c40373 | 6381 | (define_insn "*movdf_softfloat32" |
1427100a DE |
6382 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
6383 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 6384 | "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
6385 | && (gpc_reg_operand (operands[0], DFmode) |
6386 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
6387 | "* |
6388 | { | |
6389 | switch (which_alternative) | |
6390 | { | |
a260abc9 | 6391 | default: |
a6c2a102 | 6392 | abort (); |
dc4f83ca MM |
6393 | case 0: |
6394 | /* We normally copy the low-numbered register first. However, if | |
6395 | the first register operand 0 is the same as the second register of | |
6396 | operand 1, we must copy in the opposite order. */ | |
6397 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
6398 | return \"mr %L0,%L1\;mr %0,%1\"; | |
6399 | else | |
6400 | return \"mr %0,%1\;mr %L0,%L1\"; | |
6401 | case 1: | |
6402 | /* If the low-address word is used in the address, we must load it | |
6403 | last. Otherwise, load it first. Note that we cannot have | |
6404 | auto-increment in that case since the address register is known to be | |
6405 | dead. */ | |
6406 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
6407 | operands [1], 0)) | |
6408 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
6409 | else | |
6410 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
6411 | case 2: | |
6412 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
6413 | case 3: | |
c4c40373 MM |
6414 | case 4: |
6415 | case 5: | |
dc4f83ca MM |
6416 | return \"#\"; |
6417 | } | |
6418 | }" | |
c4c40373 MM |
6419 | [(set_attr "type" "*,load,store,*,*,*") |
6420 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 6421 | |
c4c40373 | 6422 | (define_insn "*movdf_hardfloat64" |
1427100a DE |
6423 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
6424 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 6425 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
6426 | && (gpc_reg_operand (operands[0], DFmode) |
6427 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 6428 | "@ |
3d5570cb RK |
6429 | mr %0,%1 |
6430 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 6431 | std%U0%X0 %1,%0 |
3d5570cb | 6432 | # |
c4c40373 MM |
6433 | # |
6434 | # | |
3d5570cb | 6435 | fmr %0,%1 |
f63184ac | 6436 | lfd%U1%X1 %0,%1 |
3d5570cb | 6437 | stfd%U0%X0 %1,%0" |
c4c40373 MM |
6438 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
6439 | (set_attr "length" "4,4,4,8,12,16,4,4,4")]) | |
dc4f83ca | 6440 | |
c4c40373 | 6441 | (define_insn "*movdf_softfloat64" |
1427100a DE |
6442 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
6443 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 6444 | "TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
6445 | && (gpc_reg_operand (operands[0], DFmode) |
6446 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
6447 | "@ |
6448 | mr %0,%1 | |
6449 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 6450 | std%U0%X0 %1,%0 |
c4c40373 MM |
6451 | # |
6452 | # | |
dc4f83ca | 6453 | #" |
c4c40373 MM |
6454 | [(set_attr "type" "*,load,store,*,*,*") |
6455 | (set_attr "length" "*,*,*,8,12,16")]) | |
1fd4e8c1 RK |
6456 | \f |
6457 | ;; Next come the multi-word integer load and store and the load and store | |
6458 | ;; multiple insns. | |
6459 | (define_expand "movdi" | |
6460 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 6461 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 RK |
6462 | "" |
6463 | " | |
6464 | { | |
e6ca2c17 | 6465 | if (GET_CODE (operands[0]) != REG) |
6b6ccd10 RK |
6466 | operands[1] = force_reg (DImode, operands[1]); |
6467 | ||
a260abc9 DE |
6468 | /* Convert a move of a CONST_DOUBLE into a CONST_INT |
6469 | only if sign-extended lower-half for 32-bit host. */ | |
6470 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
e8d791dd | 6471 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
6472 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 |
6473 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0) | |
6474 | || (CONST_DOUBLE_HIGH (operands[1]) == 0xffffffff | |
6475 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0)) | |
e8d791dd | 6476 | #endif |
a260abc9 DE |
6477 | ) |
6478 | operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
6b6ccd10 | 6479 | |
34792e82 | 6480 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 6481 | if (GET_CODE (operands[1]) == CONSTANT_P_RTX) |
34792e82 JL |
6482 | { |
6483 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
6484 | DONE; | |
6485 | } | |
6486 | ||
a260abc9 DE |
6487 | if (TARGET_64BIT |
6488 | && CONSTANT_P (operands[1]) | |
6489 | #if HOST_BITS_PER_WIDE_INT == 32 | |
6490 | && GET_CODE (operands[1]) != CONST_INT | |
6491 | #endif | |
6492 | && ! easy_fp_constant (operands[1], DImode) | |
6493 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1])) | |
6494 | { | |
6495 | /* Emit a USE operation so that the constant isn't deleted if | |
6496 | expensive optimizations are turned on because nobody | |
6497 | references it. This should only be done for operands that | |
6498 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
6499 | This should not be done for operands that contain LABEL_REFs. | |
6500 | For now, we just handle the obvious case. */ | |
6501 | if (GET_CODE (operands[1]) != LABEL_REF) | |
39403d82 | 6502 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); |
062284d8 | 6503 | |
a260abc9 DE |
6504 | /* If we are to limit the number of things we put in the TOC and |
6505 | this is a symbol plus a constant we can add in one insn, | |
6506 | just put the symbol in the TOC and add the constant. Don't do | |
6507 | this if reload is in progress. */ | |
6508 | if (GET_CODE (operands[1]) == CONST | |
6509 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
6510 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
6511 | && add_operand (XEXP (XEXP (operands[1], 0), 1), DImode) | |
6512 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF | |
6513 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
6514 | && ! side_effects_p (operands[0])) | |
6515 | { | |
6516 | rtx sym = force_const_mem (DImode, XEXP (XEXP (operands[1], 0), 0)); | |
6517 | rtx other = XEXP (XEXP (operands[1], 0), 1); | |
a473029f | 6518 | |
a260abc9 DE |
6519 | emit_insn (gen_adddi3 (operands[0], force_reg (DImode, sym), other)); |
6520 | DONE; | |
6521 | } | |
a473029f | 6522 | |
a260abc9 DE |
6523 | operands[1] = force_const_mem (DImode, operands[1]); |
6524 | if (! memory_address_p (DImode, XEXP (operands[1], 0)) | |
6525 | && ! reload_in_progress) | |
6526 | operands[1] = change_address (operands[1], DImode, | |
6527 | XEXP (operands[1], 0)); | |
a473029f | 6528 | } |
1fd4e8c1 RK |
6529 | }") |
6530 | ||
c4c40373 | 6531 | (define_insn "*movdi_32" |
4e74d8ec MM |
6532 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") |
6533 | (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] | |
a260abc9 | 6534 | "! TARGET_POWERPC64 |
4e74d8ec MM |
6535 | && (gpc_reg_operand (operands[0], DImode) |
6536 | || gpc_reg_operand (operands[1], DImode))" | |
1fd4e8c1 RK |
6537 | "* |
6538 | { | |
6539 | switch (which_alternative) | |
6540 | { | |
a260abc9 | 6541 | default: |
a6c2a102 | 6542 | abort (); |
1fd4e8c1 RK |
6543 | case 0: |
6544 | /* We normally copy the low-numbered register first. However, if | |
6545 | the first register operand 0 is the same as the second register of | |
6546 | operand 1, we must copy in the opposite order. */ | |
6547 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 6548 | return \"mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 6549 | else |
deb9225a | 6550 | return \"mr %0,%1\;mr %L0,%L1\"; |
1fd4e8c1 RK |
6551 | case 1: |
6552 | /* If the low-address word is used in the address, we must load it | |
6553 | last. Otherwise, load it first. Note that we cannot have | |
6554 | auto-increment in that case since the address register is known to be | |
6555 | dead. */ | |
6556 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
6557 | operands [1], 0)) | |
ca7f5001 | 6558 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
1fd4e8c1 | 6559 | else |
ca7f5001 | 6560 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 | 6561 | case 2: |
ca7f5001 | 6562 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8ffd9c51 RK |
6563 | case 3: |
6564 | return \"fmr %0,%1\"; | |
6565 | case 4: | |
6566 | return \"lfd%U1%X1 %0,%1\"; | |
6567 | case 5: | |
6568 | return \"stfd%U0%X0 %1,%0\"; | |
4e74d8ec MM |
6569 | case 6: |
6570 | case 7: | |
6571 | case 8: | |
6572 | case 9: | |
6573 | case 10: | |
6574 | return \"#\"; | |
1fd4e8c1 RK |
6575 | } |
6576 | }" | |
4e74d8ec MM |
6577 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*") |
6578 | (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")]) | |
6579 | ||
6580 | (define_split | |
6581 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6582 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 6583 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
6584 | [(set (match_dup 2) (match_dup 4)) |
6585 | (set (match_dup 3) (match_dup 1))] | |
6586 | " | |
6587 | { | |
39403d82 DE |
6588 | operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0); |
6589 | operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0); | |
75d39459 | 6590 | #if HOST_BITS_PER_WIDE_INT == 32 |
4e74d8ec | 6591 | operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 DE |
6592 | #else |
6593 | operands[4] = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32; | |
6594 | operands[1] = INTVAL (operands[1]) & 0xffffffff; | |
6595 | #endif | |
4e74d8ec MM |
6596 | }") |
6597 | ||
4e74d8ec MM |
6598 | (define_split |
6599 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6600 | (match_operand:DI 1 "const_double_operand" ""))] | |
75d39459 | 6601 | "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
6602 | [(set (match_dup 2) (match_dup 4)) |
6603 | (set (match_dup 3) (match_dup 5))] | |
6604 | " | |
6605 | { | |
39403d82 DE |
6606 | operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0); |
6607 | operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0); | |
f6968f59 MM |
6608 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
6609 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
4e74d8ec MM |
6610 | }") |
6611 | ||
c4c40373 | 6612 | (define_insn "*movdi_64" |
e6ca2c17 | 6613 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h") |
4e74d8ec | 6614 | (match_operand:DI 1 "input_operand" "r,m,r,I,J,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 6615 | "TARGET_POWERPC64 |
4e74d8ec MM |
6616 | && (gpc_reg_operand (operands[0], DImode) |
6617 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 6618 | "@ |
3d5570cb RK |
6619 | mr %0,%1 |
6620 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 6621 | std%U0%X0 %1,%0 |
3d5570cb | 6622 | li %0,%1 |
802a0058 | 6623 | lis %0,%v1 |
e6ca2c17 | 6624 | # |
57fa6739 | 6625 | {cal|la} %0,%1(%*) |
3d5570cb RK |
6626 | fmr %0,%1 |
6627 | lfd%U1%X1 %0,%1 | |
6628 | stfd%U0%X0 %1,%0 | |
6629 | mf%1 %0 | |
08075ead DE |
6630 | mt%0 %1 |
6631 | cror 0,0,0" | |
b7ff3d82 | 6632 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*") |
e6ca2c17 DE |
6633 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
6634 | ||
a260abc9 DE |
6635 | (define_insn "" |
6636 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6637 | (match_operand:DI 1 "const_double_operand" "F"))] | |
6638 | "TARGET_POWERPC64 && GET_CODE (operands[1]) == CONST_DOUBLE | |
6639 | && num_insns_constant (operands[1], DImode) == 1" | |
6640 | "* | |
6641 | { | |
6642 | return ((unsigned HOST_WIDE_INT) | |
6643 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
6644 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
6645 | }") | |
6646 | ||
6647 | (define_split | |
6648 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6649 | (match_operand:DI 1 "const_int_operand" ""))] | |
6650 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
6651 | && num_insns_constant (operands[1], DImode) > 1" | |
6652 | [(set (match_dup 0) | |
6653 | (match_dup 2)) | |
6654 | (set (match_dup 0) | |
6655 | (ior:DI (match_dup 0) | |
6656 | (match_dup 3)))] | |
6657 | " | |
6658 | { | |
6659 | operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000); | |
6660 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); | |
6661 | }") | |
e6ca2c17 DE |
6662 | |
6663 | (define_split | |
6664 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6665 | (match_operand:DI 1 "const_double_operand" ""))] | |
a260abc9 DE |
6666 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
6667 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
6668 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
6669 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0) | |
6670 | || (CONST_DOUBLE_HIGH (operands[1]) == 0xffffffff | |
6671 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))" | |
e6ca2c17 DE |
6672 | [(set (match_dup 0) |
6673 | (match_dup 2)) | |
6674 | (set (match_dup 0) | |
6675 | (ior:DI (match_dup 0) | |
a260abc9 DE |
6676 | (match_dup 3)))] |
6677 | " | |
6678 | { | |
6679 | operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff0000); | |
6680 | operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff); | |
6681 | }") | |
6682 | ||
6683 | (define_split | |
6684 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6685 | (match_operand:DI 1 "const_double_operand" ""))] | |
6686 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
6687 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
6688 | && CONST_DOUBLE_HIGH (operands[1]) == 0 | |
6689 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0" | |
6690 | [(set (match_dup 0) | |
6691 | (match_dup 2)) | |
6692 | (set (match_dup 0) | |
6693 | (zero_extend:DI (subreg:SI (match_dup 0) 0)))] | |
6694 | " | |
6695 | { operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); }") | |
6696 | ||
6697 | (define_split | |
6698 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6699 | (match_operand:DI 1 "const_double_operand" ""))] | |
6700 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
6701 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
6702 | && CONST_DOUBLE_LOW (operands[1]) == 0" | |
6703 | [(set (match_dup 0) | |
6704 | (match_dup 2)) | |
e6ca2c17 DE |
6705 | (set (match_dup 0) |
6706 | (ashift:DI (match_dup 0) | |
a260abc9 DE |
6707 | (const_int 32)))] |
6708 | " | |
6709 | { operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); }") | |
6710 | ||
6711 | ;; Generate all one-bits and clear left or right. | |
6712 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
6713 | (define_split | |
6714 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6715 | (match_operand:DI 1 "mask64_operand" ""))] | |
6716 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
6717 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 6718 | (set (match_dup 0) |
a260abc9 DE |
6719 | (and:DI (rotate:DI (match_dup 0) |
6720 | (const_int 0)) | |
6721 | (match_dup 1)))] | |
6722 | "") | |
6723 | ||
6724 | ;; Split a load of a large constant into the appropriate five-instruction | |
6725 | ;; sequence. Handle anything in a constant number of insns. | |
6726 | ;; When non-easy constants can go in the TOC, this should use | |
6727 | ;; easy_fp_constant predicate. | |
6728 | (define_split | |
6729 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6730 | (match_operand:DI 1 "const_double_operand" ""))] | |
6731 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
6732 | [(set (match_dup 0) | |
6733 | (match_dup 2)) | |
6734 | (set (match_dup 0) | |
6735 | (ashift:DI (match_dup 0) | |
6736 | (const_int 32))) | |
e6ca2c17 DE |
6737 | (set (match_dup 0) |
6738 | (ior:DI (match_dup 0) | |
a260abc9 | 6739 | (match_dup 3)))] |
e6ca2c17 DE |
6740 | " |
6741 | { | |
6742 | HOST_WIDE_INT low; | |
6743 | HOST_WIDE_INT high; | |
6744 | ||
6745 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
6746 | { | |
f6968f59 MM |
6747 | low = CONST_DOUBLE_LOW (operands[1]); |
6748 | high = CONST_DOUBLE_HIGH (operands[1]); | |
e6ca2c17 | 6749 | } |
e8d791dd DE |
6750 | else |
6751 | #if HOST_BITS_PER_WIDE_INT == 32 | |
e6ca2c17 DE |
6752 | { |
6753 | low = INTVAL (operands[1]); | |
6754 | high = (low < 0) ? ~0 : 0; | |
6755 | } | |
e8d791dd | 6756 | #else |
e6ca2c17 DE |
6757 | { |
6758 | low = INTVAL (operands[1]) & 0xffffffff; | |
f4558646 | 6759 | high = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32; |
e6ca2c17 | 6760 | } |
e8d791dd | 6761 | #endif |
e6ca2c17 | 6762 | |
a260abc9 DE |
6763 | operands[2] = GEN_INT (high); |
6764 | operands[3] = GEN_INT (low); | |
e6ca2c17 | 6765 | }") |
08075ead DE |
6766 | |
6767 | (define_insn "" | |
29ae5b89 JL |
6768 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
6769 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
08075ead | 6770 | (const_int 0))) |
29ae5b89 | 6771 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))] |
08075ead | 6772 | "TARGET_POWERPC64" |
29ae5b89 | 6773 | "mr. %0,%1" |
815cdc52 | 6774 | [(set_attr "type" "compare")]) |
1fd4e8c1 RK |
6775 | \f |
6776 | ;; TImode is similar, except that we usually want to compute the address into | |
6777 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 6778 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
6779 | (define_expand "movti" |
6780 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
6781 | (match_operand:TI 1 "general_operand" "")) | |
6782 | (clobber (scratch:SI))])] | |
7e69e155 | 6783 | "TARGET_STRING || TARGET_POWERPC64" |
1fd4e8c1 RK |
6784 | " |
6785 | { | |
6786 | if (GET_CODE (operands[0]) == MEM) | |
6787 | operands[1] = force_reg (TImode, operands[1]); | |
6788 | ||
6789 | if (GET_CODE (operands[0]) == MEM | |
6790 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
6791 | && ! reload_in_progress) | |
6792 | operands[0] = change_address (operands[0], TImode, | |
6793 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
6794 | ||
6795 | if (GET_CODE (operands[1]) == MEM | |
6796 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
6797 | && ! reload_in_progress) | |
6798 | operands[1] = change_address (operands[1], TImode, | |
6799 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
6800 | }") | |
6801 | ||
6802 | ;; We say that MQ is clobbered in the last alternative because the first | |
6803 | ;; alternative would never get used otherwise since it would need a reload | |
6804 | ;; while the 2nd alternative would not. We put memory cases first so they | |
6805 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
6806 | ;; giving the SCRATCH mq. | |
a260abc9 | 6807 | (define_insn "*movti_power" |
e1469d0d | 6808 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
6809 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
6810 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
7e69e155 | 6811 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 6812 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
6813 | "* |
6814 | { | |
6815 | switch (which_alternative) | |
6816 | { | |
dc4f83ca MM |
6817 | default: |
6818 | abort (); | |
6819 | ||
1fd4e8c1 | 6820 | case 0: |
ca7f5001 | 6821 | return \"{stsi|stswi} %1,%P0,16\"; |
1fd4e8c1 RK |
6822 | |
6823 | case 1: | |
ca7f5001 | 6824 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
1fd4e8c1 RK |
6825 | |
6826 | case 2: | |
6827 | /* Normally copy registers with lowest numbered register copied first. | |
6828 | But copy in the other order if the first register of the output | |
6829 | is the second, third, or fourth register in the input. */ | |
6830 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
6831 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
deb9225a | 6832 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 6833 | else |
deb9225a | 6834 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; |
1fd4e8c1 RK |
6835 | case 3: |
6836 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
6837 | fall through to generating four loads. */ | |
6838 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 6839 | return \"{lsi|lswi} %0,%P1,16\"; |
1fd4e8c1 RK |
6840 | /* ... fall through ... */ |
6841 | case 4: | |
6842 | /* If the address register is the same as the register for the lowest- | |
6843 | addressed word, load it last. Similarly for the next two words. | |
6844 | Otherwise load lowest address to highest. */ | |
6845 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
6846 | operands[1], 0)) | |
ca7f5001 | 6847 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; |
1fd4e8c1 RK |
6848 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, |
6849 | REGNO (operands[0]) + 2, operands[1], 0)) | |
ca7f5001 | 6850 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 RK |
6851 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, |
6852 | REGNO (operands[0]) + 3, operands[1], 0)) | |
ca7f5001 | 6853 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; |
1fd4e8c1 | 6854 | else |
ca7f5001 | 6855 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; |
1fd4e8c1 RK |
6856 | } |
6857 | }" | |
b7ff3d82 | 6858 | [(set_attr "type" "store,store,*,load,load") |
b19003d8 | 6859 | (set_attr "length" "*,16,16,*,16")]) |
51b8fc2c | 6860 | |
a260abc9 | 6861 | (define_insn "*movti_string" |
dc4f83ca MM |
6862 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r") |
6863 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,m")) | |
6864 | (clobber (match_scratch:SI 2 "=X,X,X"))] | |
7e69e155 | 6865 | "TARGET_STRING && !TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
6866 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
6867 | "* | |
6868 | { | |
6869 | switch (which_alternative) | |
6870 | { | |
6871 | default: | |
6872 | abort (); | |
6873 | ||
6874 | case 0: | |
6875 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; | |
6876 | ||
6877 | case 1: | |
6878 | /* Normally copy registers with lowest numbered register copied first. | |
6879 | But copy in the other order if the first register of the output | |
6880 | is the second, third, or fourth register in the input. */ | |
6881 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
6882 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
6883 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; | |
6884 | else | |
6885 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; | |
6886 | case 2: | |
6887 | /* If the address register is the same as the register for the lowest- | |
6888 | addressed word, load it last. Similarly for the next two words. | |
6889 | Otherwise load lowest address to highest. */ | |
6890 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
6891 | operands[1], 0)) | |
6892 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; | |
6893 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, | |
6894 | REGNO (operands[0]) + 2, operands[1], 0)) | |
6895 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; | |
6896 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, | |
6897 | REGNO (operands[0]) + 3, operands[1], 0)) | |
6898 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; | |
6899 | else | |
6900 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; | |
6901 | } | |
6902 | }" | |
b7ff3d82 | 6903 | [(set_attr "type" "store,*,load") |
dc4f83ca MM |
6904 | (set_attr "length" "16,16,16")]) |
6905 | ||
a260abc9 | 6906 | (define_insn "*movti_ppc64" |
51b8fc2c RK |
6907 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") |
6908 | (match_operand:TI 1 "input_operand" "r,m,r"))] | |
6909 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) | |
6910 | || gpc_reg_operand (operands[1], TImode))" | |
6911 | "* | |
6912 | { | |
6913 | switch (which_alternative) | |
6914 | { | |
a260abc9 | 6915 | default: |
a6c2a102 | 6916 | abort (); |
51b8fc2c RK |
6917 | case 0: |
6918 | /* We normally copy the low-numbered register first. However, if | |
6919 | the first register operand 0 is the same as the second register of | |
6920 | operand 1, we must copy in the opposite order. */ | |
6921 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
6922 | return \"mr %L0,%L1\;mr %0,%1\"; | |
6923 | else | |
6924 | return \"mr %0,%1\;mr %L0,%L1\"; | |
6925 | case 1: | |
6926 | /* If the low-address word is used in the address, we must load it | |
6927 | last. Otherwise, load it first. Note that we cannot have | |
6928 | auto-increment in that case since the address register is known to be | |
6929 | dead. */ | |
6930 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
6931 | operands [1], 0)) | |
6932 | return \"ld %L0,%L1\;ld %0,%1\"; | |
6933 | else | |
6934 | return \"ld%U1 %0,%1\;ld %L0,%L1\"; | |
6935 | case 2: | |
6936 | return \"std%U0 %1,%0\;std %L1,%L0\"; | |
6937 | } | |
6938 | }" | |
b7ff3d82 | 6939 | [(set_attr "type" "*,load,store") |
51b8fc2c | 6940 | (set_attr "length" "8,8,8")]) |
1fd4e8c1 RK |
6941 | \f |
6942 | (define_expand "load_multiple" | |
2f622005 RK |
6943 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
6944 | (match_operand:SI 1 "" "")) | |
6945 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 6946 | "TARGET_STRING" |
1fd4e8c1 RK |
6947 | " |
6948 | { | |
6949 | int regno; | |
6950 | int count; | |
6951 | rtx from; | |
6952 | int i; | |
6953 | ||
6954 | /* Support only loading a constant number of fixed-point registers from | |
6955 | memory and only bother with this if more than two; the machine | |
6956 | doesn't support more than eight. */ | |
6957 | if (GET_CODE (operands[2]) != CONST_INT | |
6958 | || INTVAL (operands[2]) <= 2 | |
6959 | || INTVAL (operands[2]) > 8 | |
6960 | || GET_CODE (operands[1]) != MEM | |
6961 | || GET_CODE (operands[0]) != REG | |
6962 | || REGNO (operands[0]) >= 32) | |
6963 | FAIL; | |
6964 | ||
6965 | count = INTVAL (operands[2]); | |
6966 | regno = REGNO (operands[0]); | |
6967 | ||
39403d82 | 6968 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
1fd4e8c1 RK |
6969 | from = force_reg (SImode, XEXP (operands[1], 0)); |
6970 | ||
6971 | for (i = 0; i < count; i++) | |
6972 | XVECEXP (operands[3], 0, i) | |
39403d82 | 6973 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
538bb158 JW |
6974 | change_address (operands[1], SImode, |
6975 | plus_constant (from, i * 4))); | |
1fd4e8c1 RK |
6976 | }") |
6977 | ||
6978 | (define_insn "" | |
6979 | [(match_parallel 0 "load_multiple_operation" | |
cd2b37d9 | 6980 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") |
52d3af72 | 6981 | (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])] |
7e69e155 | 6982 | "TARGET_STRING" |
1fd4e8c1 RK |
6983 | "* |
6984 | { | |
6985 | /* We have to handle the case where the pseudo used to contain the address | |
e82ee4cc RK |
6986 | is assigned to one of the output registers. */ |
6987 | int i, j; | |
6988 | int words = XVECLEN (operands[0], 0); | |
6989 | rtx xop[10]; | |
6990 | ||
6991 | if (XVECLEN (operands[0], 0) == 1) | |
6992 | return \"{l|lwz} %1,0(%2)\"; | |
1fd4e8c1 | 6993 | |
e82ee4cc | 6994 | for (i = 0; i < words; i++) |
1fd4e8c1 RK |
6995 | if (refers_to_regno_p (REGNO (operands[1]) + i, |
6996 | REGNO (operands[1]) + i + 1, operands[2], 0)) | |
6997 | { | |
e82ee4cc RK |
6998 | if (i == words-1) |
6999 | { | |
7000 | xop[0] = operands[1]; | |
7001 | xop[1] = operands[2]; | |
7002 | xop[2] = GEN_INT (4 * (words-1)); | |
d89ddcfd | 7003 | output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop); |
e82ee4cc RK |
7004 | return \"\"; |
7005 | } | |
7006 | else if (i == 0) | |
7007 | { | |
7008 | xop[0] = operands[1]; | |
39403d82 | 7009 | xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
e82ee4cc RK |
7010 | xop[2] = GEN_INT (4 * (words-1)); |
7011 | output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop); | |
7012 | return \"\"; | |
7013 | } | |
7014 | else | |
7015 | { | |
7016 | for (j = 0; j < words; j++) | |
7017 | if (j != i) | |
7018 | { | |
39403d82 | 7019 | xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j); |
e82ee4cc RK |
7020 | xop[1] = operands[2]; |
7021 | xop[2] = GEN_INT (j * 4); | |
7022 | output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop); | |
7023 | } | |
7024 | xop[0] = operands[2]; | |
7025 | xop[1] = GEN_INT (i * 4); | |
7026 | output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop); | |
7027 | return \"\"; | |
7028 | } | |
1fd4e8c1 RK |
7029 | } |
7030 | ||
e82ee4cc | 7031 | return \"{lsi|lswi} %1,%2,%N0\"; |
1fd4e8c1 | 7032 | }" |
b19003d8 | 7033 | [(set_attr "type" "load") |
e82ee4cc | 7034 | (set_attr "length" "32")]) |
b19003d8 | 7035 | |
b7ff3d82 | 7036 | \f |
1fd4e8c1 | 7037 | (define_expand "store_multiple" |
2f622005 RK |
7038 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
7039 | (match_operand:SI 1 "" "")) | |
7040 | (clobber (scratch:SI)) | |
7041 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 7042 | "TARGET_STRING" |
1fd4e8c1 RK |
7043 | " |
7044 | { | |
7045 | int regno; | |
7046 | int count; | |
7047 | rtx to; | |
7048 | int i; | |
7049 | ||
7050 | /* Support only storing a constant number of fixed-point registers to | |
7051 | memory and only bother with this if more than two; the machine | |
7052 | doesn't support more than eight. */ | |
7053 | if (GET_CODE (operands[2]) != CONST_INT | |
7054 | || INTVAL (operands[2]) <= 2 | |
7055 | || INTVAL (operands[2]) > 8 | |
7056 | || GET_CODE (operands[0]) != MEM | |
7057 | || GET_CODE (operands[1]) != REG | |
7058 | || REGNO (operands[1]) >= 32) | |
7059 | FAIL; | |
7060 | ||
7061 | count = INTVAL (operands[2]); | |
7062 | regno = REGNO (operands[1]); | |
7063 | ||
39403d82 | 7064 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 RK |
7065 | to = force_reg (SImode, XEXP (operands[0], 0)); |
7066 | ||
7067 | XVECEXP (operands[3], 0, 0) | |
39403d82 | 7068 | = gen_rtx_SET (VOIDmode, change_address (operands[0], SImode, to), |
538bb158 | 7069 | operands[1]); |
39403d82 DE |
7070 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
7071 | gen_rtx_SCRATCH (SImode)); | |
1fd4e8c1 RK |
7072 | |
7073 | for (i = 1; i < count; i++) | |
7074 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 7075 | = gen_rtx_SET (VOIDmode, |
538bb158 JW |
7076 | change_address (operands[0], SImode, |
7077 | plus_constant (to, i * 4)), | |
39403d82 | 7078 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
7079 | }") |
7080 | ||
7081 | (define_insn "" | |
7082 | [(match_parallel 0 "store_multiple_operation" | |
7083 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 7084 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 7085 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 7086 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
7087 | "{stsi|stswi} %2,%P1,%O0" |
7088 | [(set_attr "type" "store")]) | |
d14a6d05 MM |
7089 | |
7090 | (define_insn "" | |
7091 | [(match_parallel 0 "store_multiple_operation" | |
52d3af72 | 7092 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
d14a6d05 MM |
7093 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
7094 | (clobber (match_scratch:SI 3 "X"))])] | |
7e69e155 | 7095 | "TARGET_STRING && !TARGET_POWER" |
b7ff3d82 DE |
7096 | "{stsi|stswi} %2,%1,%O0" |
7097 | [(set_attr "type" "store")]) | |
7e69e155 MM |
7098 | |
7099 | \f | |
7100 | ;; String/block move insn. | |
7101 | ;; Argument 0 is the destination | |
7102 | ;; Argument 1 is the source | |
7103 | ;; Argument 2 is the length | |
7104 | ;; Argument 3 is the alignment | |
7105 | ||
7106 | (define_expand "movstrsi" | |
b6c9286a MM |
7107 | [(parallel [(set (match_operand:BLK 0 "" "") |
7108 | (match_operand:BLK 1 "" "")) | |
7109 | (use (match_operand:SI 2 "" "")) | |
7110 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
7111 | "" |
7112 | " | |
7113 | { | |
7114 | if (expand_block_move (operands)) | |
7115 | DONE; | |
7116 | else | |
7117 | FAIL; | |
7118 | }") | |
7119 | ||
7120 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
7121 | ;; register allocator doesn't have a clue about allocating 8 word registers | |
7122 | (define_expand "movstrsi_8reg" | |
b6c9286a MM |
7123 | [(parallel [(set (match_operand 0 "" "") |
7124 | (match_operand 1 "" "")) | |
7125 | (use (match_operand 2 "" "")) | |
7126 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
7127 | (clobber (reg:SI 5)) |
7128 | (clobber (reg:SI 6)) | |
7129 | (clobber (reg:SI 7)) | |
7130 | (clobber (reg:SI 8)) | |
7131 | (clobber (reg:SI 9)) | |
7132 | (clobber (reg:SI 10)) | |
7133 | (clobber (reg:SI 11)) | |
7134 | (clobber (reg:SI 12)) | |
3c67b673 | 7135 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
7136 | "TARGET_STRING" |
7137 | "") | |
7138 | ||
7139 | (define_insn "" | |
52d3af72 DE |
7140 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7141 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7142 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7143 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 7144 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
7145 | (clobber (reg:SI 6)) |
7146 | (clobber (reg:SI 7)) | |
7147 | (clobber (reg:SI 8)) | |
7148 | (clobber (reg:SI 9)) | |
7149 | (clobber (reg:SI 10)) | |
7150 | (clobber (reg:SI 11)) | |
7151 | (clobber (reg:SI 12)) | |
3c67b673 | 7152 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
7153 | "TARGET_STRING && TARGET_POWER |
7154 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0) | |
7155 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
7156 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
7157 | && REGNO (operands[4]) == 5" |
7158 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
7159 | [(set_attr "type" "load") |
7160 | (set_attr "length" "8")]) | |
7e69e155 MM |
7161 | |
7162 | (define_insn "" | |
52d3af72 DE |
7163 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7164 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7165 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7166 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 7167 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
7168 | (clobber (reg:SI 6)) |
7169 | (clobber (reg:SI 7)) | |
7170 | (clobber (reg:SI 8)) | |
7171 | (clobber (reg:SI 9)) | |
7172 | (clobber (reg:SI 10)) | |
7173 | (clobber (reg:SI 11)) | |
7174 | (clobber (reg:SI 12)) | |
3c67b673 | 7175 | (clobber (match_scratch:SI 5 "X"))] |
7e69e155 MM |
7176 | "TARGET_STRING && !TARGET_POWER |
7177 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0) | |
7178 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
7179 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
7180 | && REGNO (operands[4]) == 5" |
7181 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
7182 | [(set_attr "type" "load") |
7183 | (set_attr "length" "8")]) | |
7e69e155 MM |
7184 | |
7185 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the | |
7186 | ;; register allocator doesn't have a clue about allocating 6 word registers | |
7187 | (define_expand "movstrsi_6reg" | |
b6c9286a MM |
7188 | [(parallel [(set (match_operand 0 "" "") |
7189 | (match_operand 1 "" "")) | |
7190 | (use (match_operand 2 "" "")) | |
7191 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
7192 | (clobber (reg:SI 7)) |
7193 | (clobber (reg:SI 8)) | |
7194 | (clobber (reg:SI 9)) | |
7195 | (clobber (reg:SI 10)) | |
7196 | (clobber (reg:SI 11)) | |
7197 | (clobber (reg:SI 12)) | |
3c67b673 | 7198 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
7199 | "TARGET_STRING" |
7200 | "") | |
7201 | ||
7202 | (define_insn "" | |
52d3af72 DE |
7203 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7204 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7205 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7206 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 7207 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
7208 | (clobber (reg:SI 8)) |
7209 | (clobber (reg:SI 9)) | |
7210 | (clobber (reg:SI 10)) | |
7211 | (clobber (reg:SI 11)) | |
7212 | (clobber (reg:SI 12)) | |
3c67b673 | 7213 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
7214 | "TARGET_STRING && TARGET_POWER |
7215 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
7216 | && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12) | |
7217 | && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
7218 | && REGNO (operands[4]) == 7" |
7219 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
7220 | [(set_attr "type" "load") |
7221 | (set_attr "length" "8")]) | |
7e69e155 MM |
7222 | |
7223 | (define_insn "" | |
52d3af72 DE |
7224 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7225 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7226 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7227 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 7228 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
7229 | (clobber (reg:SI 8)) |
7230 | (clobber (reg:SI 9)) | |
7231 | (clobber (reg:SI 10)) | |
7232 | (clobber (reg:SI 11)) | |
7233 | (clobber (reg:SI 12)) | |
3c67b673 | 7234 | (clobber (match_scratch:SI 5 "X"))] |
7e69e155 MM |
7235 | "TARGET_STRING && !TARGET_POWER |
7236 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 | |
7237 | && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12) | |
7238 | && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
7239 | && REGNO (operands[4]) == 7" |
7240 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
7241 | [(set_attr "type" "load") |
7242 | (set_attr "length" "8")]) | |
7e69e155 MM |
7243 | |
7244 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill problems | |
7245 | ;; with TImode | |
7246 | (define_expand "movstrsi_4reg" | |
b6c9286a MM |
7247 | [(parallel [(set (match_operand 0 "" "") |
7248 | (match_operand 1 "" "")) | |
7249 | (use (match_operand 2 "" "")) | |
7250 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
7251 | (clobber (reg:SI 9)) |
7252 | (clobber (reg:SI 10)) | |
7253 | (clobber (reg:SI 11)) | |
7254 | (clobber (reg:SI 12)) | |
3c67b673 | 7255 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
7256 | "TARGET_STRING" |
7257 | "") | |
7258 | ||
7259 | (define_insn "" | |
52d3af72 DE |
7260 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7261 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7262 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7263 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 7264 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
7265 | (clobber (reg:SI 10)) |
7266 | (clobber (reg:SI 11)) | |
7267 | (clobber (reg:SI 12)) | |
3c67b673 | 7268 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
7269 | "TARGET_STRING && TARGET_POWER |
7270 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
7271 | && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12) | |
7272 | && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
7273 | && REGNO (operands[4]) == 9" |
7274 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
7275 | [(set_attr "type" "load") |
7276 | (set_attr "length" "8")]) | |
7e69e155 MM |
7277 | |
7278 | (define_insn "" | |
52d3af72 DE |
7279 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7280 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7281 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7282 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 7283 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
7284 | (clobber (reg:SI 10)) |
7285 | (clobber (reg:SI 11)) | |
7286 | (clobber (reg:SI 12)) | |
3c67b673 | 7287 | (clobber (match_scratch:SI 5 "X"))] |
7e69e155 MM |
7288 | "TARGET_STRING && !TARGET_POWER |
7289 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
7290 | && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12) | |
7291 | && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
7292 | && REGNO (operands[4]) == 9" |
7293 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
7294 | [(set_attr "type" "load") |
7295 | (set_attr "length" "8")]) | |
7e69e155 MM |
7296 | |
7297 | ;; Move up to 8 bytes at a time. | |
7298 | (define_expand "movstrsi_2reg" | |
b6c9286a MM |
7299 | [(parallel [(set (match_operand 0 "" "") |
7300 | (match_operand 1 "" "")) | |
7301 | (use (match_operand 2 "" "")) | |
7302 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
7303 | (clobber (match_scratch:DI 4 "")) |
7304 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
7305 | "TARGET_STRING && !TARGET_64BIT" |
7306 | "") | |
7307 | ||
7308 | (define_insn "" | |
52d3af72 DE |
7309 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7310 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7311 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7312 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
7313 | (clobber (match_scratch:DI 4 "=&r")) | |
7314 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 | 7315 | "TARGET_STRING && TARGET_POWER && !TARGET_64BIT |
3c67b673 RK |
7316 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
7317 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
7318 | [(set_attr "type" "load") |
7319 | (set_attr "length" "8")]) | |
7e69e155 MM |
7320 | |
7321 | (define_insn "" | |
52d3af72 DE |
7322 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7323 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7324 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7325 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
7326 | (clobber (match_scratch:DI 4 "=&r")) | |
7327 | (clobber (match_scratch:SI 5 "X"))] | |
7e69e155 MM |
7328 | "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT |
7329 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" | |
3c67b673 | 7330 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
7331 | [(set_attr "type" "load") |
7332 | (set_attr "length" "8")]) | |
7e69e155 MM |
7333 | |
7334 | ;; Move up to 4 bytes at a time. | |
7335 | (define_expand "movstrsi_1reg" | |
b6c9286a MM |
7336 | [(parallel [(set (match_operand 0 "" "") |
7337 | (match_operand 1 "" "")) | |
7338 | (use (match_operand 2 "" "")) | |
7339 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
7340 | (clobber (match_scratch:SI 4 "")) |
7341 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
7342 | "TARGET_STRING" |
7343 | "") | |
7344 | ||
7345 | (define_insn "" | |
52d3af72 DE |
7346 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7347 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7348 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7349 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
7350 | (clobber (match_scratch:SI 4 "=&r")) | |
7351 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
7352 | "TARGET_STRING && TARGET_POWER |
7353 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 7354 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
7355 | [(set_attr "type" "load") |
7356 | (set_attr "length" "8")]) | |
7e69e155 MM |
7357 | |
7358 | (define_insn "" | |
52d3af72 DE |
7359 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
7360 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
7361 | (use (match_operand:SI 2 "immediate_operand" "i")) |
7362 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
7363 | (clobber (match_scratch:SI 4 "=&r")) | |
7364 | (clobber (match_scratch:SI 5 "X"))] | |
7e69e155 MM |
7365 | "TARGET_STRING && !TARGET_POWER |
7366 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 7367 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
7368 | [(set_attr "type" "load") |
7369 | (set_attr "length" "8")]) | |
7e69e155 | 7370 | |
1fd4e8c1 | 7371 | \f |
7e69e155 | 7372 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
7373 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
7374 | ;; do cases where the increment is not the size of the object. | |
7375 | ;; | |
7376 | ;; In all these cases, we use operands 0 and 1 for the register being | |
7377 | ;; incremented because those are the operands that local-alloc will | |
7378 | ;; tie and these are the pair most likely to be tieable (and the ones | |
7379 | ;; that will benefit the most). | |
7380 | ||
38c1f2d7 | 7381 | (define_insn "*movdi_update1" |
51b8fc2c | 7382 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 7383 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
51b8fc2c RK |
7384 | (match_operand:DI 2 "reg_or_short_operand" "r,I")))) |
7385 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
7386 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 7387 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
7388 | "@ |
7389 | ldux %3,%0,%2 | |
7390 | ldu %3,%2(%0)" | |
7391 | [(set_attr "type" "load")]) | |
7392 | ||
38c1f2d7 | 7393 | (define_insn "*movdi_update2" |
287f13ff RK |
7394 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") |
7395 | (sign_extend:DI | |
7396 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
7397 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
7398 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
7399 | (plus:DI (match_dup 1) (match_dup 2)))] | |
7400 | "TARGET_POWERPC64" | |
7401 | "lwaux %3,%0,%2" | |
7402 | [(set_attr "type" "load")]) | |
7403 | ||
4697a36c | 7404 | (define_insn "movdi_update" |
51b8fc2c RK |
7405 | [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
7406 | (match_operand:DI 2 "reg_or_short_operand" "r,I"))) | |
7407 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) | |
7408 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
7409 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 7410 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
7411 | "@ |
7412 | stdux %3,%0,%2 | |
b7ff3d82 DE |
7413 | stdu %3,%2(%0)" |
7414 | [(set_attr "type" "store")]) | |
51b8fc2c | 7415 | |
38c1f2d7 | 7416 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
7417 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
7418 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 7419 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 7420 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
7421 | (plus:SI (match_dup 1) (match_dup 2)))] |
7422 | "" | |
7423 | "@ | |
ca7f5001 RK |
7424 | {lux|lwzux} %3,%0,%2 |
7425 | {lu|lwzu} %3,%2(%0)" | |
cfb557c4 | 7426 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7427 | |
4697a36c | 7428 | (define_insn "movsi_update" |
cd2b37d9 | 7429 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7430 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
7431 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
7432 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 7433 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7434 | "TARGET_UPDATE" |
1fd4e8c1 | 7435 | "@ |
ca7f5001 | 7436 | {stux|stwux} %3,%0,%2 |
b7ff3d82 DE |
7437 | {stu|stwu} %3,%2(%0)" |
7438 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 7439 | |
38c1f2d7 | 7440 | (define_insn "*movhi_update" |
cd2b37d9 RK |
7441 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
7442 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 7443 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 7444 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7445 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7446 | "TARGET_UPDATE" |
1fd4e8c1 | 7447 | "@ |
5f243543 RK |
7448 | lhzux %3,%0,%2 |
7449 | lhzu %3,%2(%0)" | |
cfb557c4 | 7450 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7451 | |
38c1f2d7 | 7452 | (define_insn "*movhi_update2" |
cd2b37d9 | 7453 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 7454 | (zero_extend:SI |
cd2b37d9 | 7455 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7456 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 7457 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7458 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7459 | "TARGET_UPDATE" |
1fd4e8c1 | 7460 | "@ |
5f243543 RK |
7461 | lhzux %3,%0,%2 |
7462 | lhzu %3,%2(%0)" | |
cfb557c4 | 7463 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7464 | |
38c1f2d7 | 7465 | (define_insn "*movhi_update3" |
cd2b37d9 | 7466 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 7467 | (sign_extend:SI |
cd2b37d9 | 7468 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7469 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 7470 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7471 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7472 | "TARGET_UPDATE" |
1fd4e8c1 | 7473 | "@ |
5f243543 RK |
7474 | lhaux %3,%0,%2 |
7475 | lhau %3,%2(%0)" | |
cfb557c4 | 7476 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7477 | |
38c1f2d7 | 7478 | (define_insn "*movhi_update4" |
cd2b37d9 | 7479 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7480 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
7481 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
7482 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 7483 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7484 | "TARGET_UPDATE" |
1fd4e8c1 | 7485 | "@ |
5f243543 | 7486 | sthux %3,%0,%2 |
b7ff3d82 DE |
7487 | sthu %3,%2(%0)" |
7488 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 7489 | |
38c1f2d7 | 7490 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
7491 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
7492 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 7493 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 7494 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7495 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7496 | "TARGET_UPDATE" |
1fd4e8c1 | 7497 | "@ |
5f243543 RK |
7498 | lbzux %3,%0,%2 |
7499 | lbzu %3,%2(%0)" | |
cfb557c4 | 7500 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7501 | |
38c1f2d7 | 7502 | (define_insn "*movqi_update2" |
cd2b37d9 | 7503 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 7504 | (zero_extend:SI |
cd2b37d9 | 7505 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7506 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 7507 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7508 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7509 | "TARGET_UPDATE" |
1fd4e8c1 | 7510 | "@ |
5f243543 RK |
7511 | lbzux %3,%0,%2 |
7512 | lbzu %3,%2(%0)" | |
cfb557c4 | 7513 | [(set_attr "type" "load")]) |
1fd4e8c1 | 7514 | |
38c1f2d7 | 7515 | (define_insn "*movqi_update3" |
cd2b37d9 | 7516 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7517 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
7518 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
7519 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 7520 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7521 | "TARGET_UPDATE" |
1fd4e8c1 | 7522 | "@ |
5f243543 | 7523 | stbux %3,%0,%2 |
b7ff3d82 DE |
7524 | stbu %3,%2(%0)" |
7525 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 7526 | |
38c1f2d7 | 7527 | (define_insn "*movsf_update1" |
cd2b37d9 | 7528 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 7529 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7530 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 7531 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7532 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7533 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 7534 | "@ |
5f243543 RK |
7535 | lfsux %3,%0,%2 |
7536 | lfsu %3,%2(%0)" | |
cfb557c4 | 7537 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 7538 | |
38c1f2d7 | 7539 | (define_insn "*movsf_update2" |
cd2b37d9 | 7540 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7541 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
7542 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
7543 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 7544 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7545 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 7546 | "@ |
85fff2f3 | 7547 | stfsux %3,%0,%2 |
b7ff3d82 DE |
7548 | stfsu %3,%2(%0)" |
7549 | [(set_attr "type" "fpstore")]) | |
1fd4e8c1 | 7550 | |
38c1f2d7 MM |
7551 | (define_insn "*movsf_update3" |
7552 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
7553 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
7554 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
7555 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
7556 | (plus:SI (match_dup 1) (match_dup 2)))] | |
7557 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
7558 | "@ | |
7559 | {lux|lwzux} %3,%0,%2 | |
7560 | {lu|lwzu} %3,%2(%0)" | |
7561 | [(set_attr "type" "load")]) | |
7562 | ||
7563 | (define_insn "*movsf_update4" | |
7564 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
7565 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
7566 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
7567 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
7568 | (plus:SI (match_dup 1) (match_dup 2)))] | |
7569 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
7570 | "@ | |
7571 | {stux|stwux} %3,%0,%2 | |
7572 | {stu|stwu} %3,%2(%0)" | |
7573 | [(set_attr "type" "store")]) | |
7574 | ||
7575 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
7576 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
7577 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 7578 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 7579 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 7580 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7581 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 7582 | "@ |
5f243543 RK |
7583 | lfdux %3,%0,%2 |
7584 | lfdu %3,%2(%0)" | |
cfb557c4 | 7585 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 7586 | |
38c1f2d7 | 7587 | (define_insn "*movdf_update2" |
cd2b37d9 | 7588 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 7589 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
7590 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
7591 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 7592 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 7593 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 7594 | "@ |
5f243543 | 7595 | stfdux %3,%0,%2 |
b7ff3d82 DE |
7596 | stfdu %3,%2(%0)" |
7597 | [(set_attr "type" "fpstore")]) | |
4c70a4f3 RK |
7598 | |
7599 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
7600 | ||
7601 | (define_peephole | |
7602 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
7603 | (match_operand:DF 1 "memory_operand" "")) | |
7604 | (set (match_operand:DF 2 "gpc_reg_operand" "=f") | |
7605 | (match_operand:DF 3 "memory_operand" ""))] | |
7606 | "TARGET_POWER2 | |
d14a6d05 | 7607 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
7608 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
7609 | && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) | |
7610 | && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" | |
7611 | "lfq%U1%X1 %0,%1") | |
7612 | ||
7613 | (define_peephole | |
7614 | [(set (match_operand:DF 0 "memory_operand" "") | |
7615 | (match_operand:DF 1 "gpc_reg_operand" "f")) | |
7616 | (set (match_operand:DF 2 "memory_operand" "") | |
7617 | (match_operand:DF 3 "gpc_reg_operand" "f"))] | |
7618 | "TARGET_POWER2 | |
d14a6d05 | 7619 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
7620 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
7621 | && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) | |
7622 | && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" | |
7623 | "stfq%U0%X0 %1,%0") | |
1fd4e8c1 RK |
7624 | \f |
7625 | ;; Next come insns related to the calling sequence. | |
7626 | ;; | |
7627 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 7628 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
7629 | |
7630 | (define_expand "allocate_stack" | |
52d3af72 | 7631 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
7632 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
7633 | (set (reg 1) | |
7634 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
7635 | "" |
7636 | " | |
4697a36c | 7637 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 7638 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 7639 | rtx neg_op0; |
1fd4e8c1 RK |
7640 | |
7641 | emit_move_insn (chain, stack_bot); | |
4697a36c | 7642 | |
e9a25f70 JL |
7643 | /* Under Windows NT, we need to add stack probes for large/variable |
7644 | allocations, so do it via a call to the external function alloca | |
7645 | instead of doing it inline. */ | |
979721f8 | 7646 | if (DEFAULT_ABI == ABI_NT |
e9a25f70 | 7647 | && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) > 4096)) |
979721f8 | 7648 | { |
a260abc9 | 7649 | rtx tmp = gen_reg_rtx (Pmode); |
39403d82 | 7650 | emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, \"__allocate_stack\"), |
a260abc9 | 7651 | tmp, 0, Pmode, 1, operands[1], Pmode); |
cea05fab | 7652 | emit_insn (gen_set_sp (tmp)); |
e9a25f70 | 7653 | emit_move_insn (operands[0], tmp); |
979721f8 MM |
7654 | DONE; |
7655 | } | |
7656 | ||
e9a25f70 JL |
7657 | if (GET_CODE (operands[1]) != CONST_INT |
7658 | || INTVAL (operands[1]) < -32767 | |
7659 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
7660 | { |
7661 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 7662 | if (TARGET_32BIT) |
e9a25f70 | 7663 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 7664 | else |
e9a25f70 | 7665 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
7666 | } |
7667 | else | |
e9a25f70 | 7668 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 7669 | |
38c1f2d7 MM |
7670 | if (TARGET_UPDATE) |
7671 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) | |
7672 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); | |
4697a36c | 7673 | |
38c1f2d7 MM |
7674 | else |
7675 | { | |
7676 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
7677 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 7678 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 7679 | } |
e9a25f70 JL |
7680 | |
7681 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
7682 | DONE; |
7683 | }") | |
59257ff7 | 7684 | |
cea05fab MM |
7685 | ;; Marker to indicate that the stack pointer was changed under NT in |
7686 | ;; ways not known to the compiler | |
7687 | ||
7688 | (define_insn "set_sp" | |
7689 | [(set (reg:SI 1) | |
7690 | (unspec [(match_operand:SI 0 "register_operand" "r")] 7))] | |
7691 | "" | |
7692 | "" | |
7693 | [(set_attr "length" "0")]) | |
7694 | ||
59257ff7 RK |
7695 | ;; These patterns say how to save and restore the stack pointer. We need not |
7696 | ;; save the stack pointer at function level since we are careful to | |
7697 | ;; preserve the backchain. At block level, we have to restore the backchain | |
7698 | ;; when we restore the stack pointer. | |
7699 | ;; | |
7700 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
7701 | ;; backchain and restore both. Note that in the nonlocal case, the | |
7702 | ;; save area is a memory location. | |
7703 | ||
7704 | (define_expand "save_stack_function" | |
ff381587 MM |
7705 | [(match_operand 0 "any_operand" "") |
7706 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 7707 | "" |
ff381587 | 7708 | "DONE;") |
59257ff7 RK |
7709 | |
7710 | (define_expand "restore_stack_function" | |
ff381587 MM |
7711 | [(match_operand 0 "any_operand" "") |
7712 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 7713 | "" |
ff381587 | 7714 | "DONE;") |
59257ff7 RK |
7715 | |
7716 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
7717 | [(use (match_operand 0 "register_operand" "")) |
7718 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 7719 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 7720 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
7721 | "" |
7722 | " | |
dfdfa60f DE |
7723 | { |
7724 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 7725 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 7726 | }") |
59257ff7 RK |
7727 | |
7728 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
7729 | [(match_operand 0 "memory_operand" "") |
7730 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
7731 | "" |
7732 | " | |
7733 | { | |
a260abc9 | 7734 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
7735 | |
7736 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 7737 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
a260abc9 DE |
7738 | emit_move_insn (operand_subword (operands[0], 0, 0, (TARGET_32BIT ? DImode : TImode)), |
7739 | temp); | |
7740 | emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)), | |
7741 | operands[1]); | |
59257ff7 RK |
7742 | DONE; |
7743 | }") | |
7e69e155 | 7744 | |
59257ff7 | 7745 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
7746 | [(match_operand 0 "register_operand" "") |
7747 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
7748 | "" |
7749 | " | |
7750 | { | |
a260abc9 | 7751 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
7752 | |
7753 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 DE |
7754 | emit_move_insn (temp, |
7755 | operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode))); | |
7756 | emit_move_insn (operands[0], | |
7757 | operand_subword (operands[1], 1, 0, (TARGET_32BIT ? DImode : TImode))); | |
39403d82 | 7758 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
7759 | DONE; |
7760 | }") | |
b6c9286a | 7761 | |
956d6950 | 7762 | ;; If we have -mminimal-toc, we need to reload r30 after a nonlocal goto. |
f0f6a223 RK |
7763 | |
7764 | (define_insn "nonlocal_goto_receiver" | |
7765 | [(unspec_volatile [(const_int 0)] 1)] | |
e9a25f70 | 7766 | "TARGET_TOC && TARGET_MINIMAL_TOC" |
f0f6a223 RK |
7767 | "* |
7768 | { | |
38c1f2d7 | 7769 | rs6000_output_load_toc_table (asm_out_file, 30); |
f0f6a223 RK |
7770 | return \"\"; |
7771 | }" | |
7772 | [(set_attr "type" "load")]) | |
b7ff3d82 | 7773 | \f |
b6c9286a MM |
7774 | ;; A function pointer under AIX is a pointer to a data area whose first word |
7775 | ;; contains the actual address of the function, whose second word contains a | |
7776 | ;; pointer to its TOC, and whose third word contains a value to place in the | |
7777 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 RK |
7778 | ;; "trampoline" need not have any executable code. |
7779 | ;; | |
b6c9286a MM |
7780 | ;; operands[0] is a register pointing to the 3 word descriptor (aka, the function address) |
7781 | ;; operands[1] is the stack size to clean up | |
7782 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for AIX) | |
7783 | ;; operands[3] is location to store the TOC | |
7784 | ;; operands[4] is the TOC register | |
7785 | ;; operands[5] is the static chain register | |
7786 | ;; | |
7787 | ;; We do not break this into separate insns, so that the scheduler will not try | |
7788 | ;; to move the load of the new TOC before any loads from the TOC. | |
7789 | ||
a260abc9 | 7790 | (define_insn "call_indirect_aix32" |
52d3af72 | 7791 | [(call (mem:SI (match_operand:SI 0 "gpc_reg_operand" "b")) |
b6c9286a | 7792 | (match_operand 1 "const_int_operand" "n")) |
6a4cee5f | 7793 | (use (match_operand 2 "const_int_operand" "n")) |
97f6e72f | 7794 | (use (match_operand 3 "offsettable_mem_operand" "o")) |
52d3af72 DE |
7795 | (use (match_operand 4 "gpc_reg_operand" "r")) |
7796 | (clobber (match_operand 5 "gpc_reg_operand" "=r")) | |
b6c9286a MM |
7797 | (clobber (match_scratch:SI 6 "=&r")) |
7798 | (clobber (match_scratch:SI 7 "=l"))] | |
6a4cee5f MM |
7799 | "DEFAULT_ABI == ABI_AIX |
7800 | && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)" | |
97f6e72f | 7801 | "{st|stw} %4,%3\;{l|lwz} %6,0(%0)\;{l|lwz} %4,4(%0)\;mt%7 %6\;{l|lwz} %5,8(%0)\;{brl|blrl}\;{l|lwz} %4,%3" |
b7ff3d82 DE |
7802 | [(set_attr "type" "load") |
7803 | (set_attr "length" "28")]) | |
b6c9286a | 7804 | |
a260abc9 | 7805 | (define_insn "call_indirect_aix64" |
52d3af72 | 7806 | [(call (mem:SI (match_operand:DI 0 "gpc_reg_operand" "b")) |
a260abc9 DE |
7807 | (match_operand 1 "const_int_operand" "n")) |
7808 | (use (match_operand 2 "const_int_operand" "n")) | |
97f6e72f | 7809 | (use (match_operand 3 "offsettable_mem_operand" "o")) |
52d3af72 DE |
7810 | (use (match_operand 4 "gpc_reg_operand" "r")) |
7811 | (clobber (match_operand 5 "gpc_reg_operand" "=r")) | |
a260abc9 DE |
7812 | (clobber (match_scratch:SI 6 "=&r")) |
7813 | (clobber (match_scratch:SI 7 "=l"))] | |
7814 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX | |
7815 | && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)" | |
97f6e72f | 7816 | "std %4,%3\;ld %6,0(%0)\;ld %4,8(%0)\;mt%7 %6\;ld %5,16(%0)\;blrl\;ld %4,%3" |
a260abc9 DE |
7817 | [(set_attr "type" "load") |
7818 | (set_attr "length" "28")]) | |
7819 | ||
7820 | (define_insn "call_value_indirect_aix32" | |
b6c9286a | 7821 | [(set (match_operand 0 "register_operand" "fg") |
52d3af72 | 7822 | (call (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
b6c9286a | 7823 | (match_operand 2 "const_int_operand" "n"))) |
6a4cee5f | 7824 | (use (match_operand 3 "const_int_operand" "n")) |
97f6e72f | 7825 | (use (match_operand 4 "offsettable_mem_operand" "o")) |
52d3af72 DE |
7826 | (use (match_operand 5 "gpc_reg_operand" "r")) |
7827 | (clobber (match_operand 6 "gpc_reg_operand" "=r")) | |
b6c9286a MM |
7828 | (clobber (match_scratch:SI 7 "=&r")) |
7829 | (clobber (match_scratch:SI 8 "=l"))] | |
6a4cee5f MM |
7830 | "DEFAULT_ABI == ABI_AIX |
7831 | && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)" | |
97f6e72f | 7832 | "{st|stw} %5,%4\;{l|lwz} %7,0(%1)\;{l|lwz} %5,4(%1)\;mt%8 %7\;{l|lwz} %6,8(%1)\;{brl|blrl}\;{l|lwz} %5,%4" |
a260abc9 DE |
7833 | [(set_attr "type" "load") |
7834 | (set_attr "length" "28")]) | |
7835 | ||
7836 | (define_insn "call_value_indirect_aix64" | |
7837 | [(set (match_operand 0 "register_operand" "fg") | |
52d3af72 | 7838 | (call (mem:SI (match_operand:DI 1 "gpc_reg_operand" "b")) |
a260abc9 DE |
7839 | (match_operand 2 "const_int_operand" "n"))) |
7840 | (use (match_operand 3 "const_int_operand" "n")) | |
97f6e72f | 7841 | (use (match_operand 4 "offsettable_mem_operand" "o")) |
52d3af72 DE |
7842 | (use (match_operand 5 "gpc_reg_operand" "r")) |
7843 | (clobber (match_operand 6 "gpc_reg_operand" "=r")) | |
a260abc9 DE |
7844 | (clobber (match_scratch:SI 7 "=&r")) |
7845 | (clobber (match_scratch:SI 8 "=l"))] | |
7846 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX | |
7847 | && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)" | |
97f6e72f | 7848 | "std %5,%4\;ld %7,0(%1)\;ld %5,8(%1)\;mt%8 %7\;ld %6,16(%1)\;blrl\;ld %5,%4" |
b7ff3d82 DE |
7849 | [(set_attr "type" "load") |
7850 | (set_attr "length" "28")]) | |
b6c9286a MM |
7851 | |
7852 | ;; A function pointer undef NT is a pointer to a data area whose first word | |
7853 | ;; contains the actual address of the function, whose second word contains a | |
7854 | ;; pointer to its TOC. The static chain is not stored under NT, which means | |
7855 | ;; that we need a trampoline. | |
7856 | ;; | |
7857 | ;; operands[0] is an SImode pseudo in which we place the address of the function. | |
7858 | ;; operands[1] is the stack size to clean up | |
7859 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for NT) | |
7860 | ;; operands[3] is location to store the TOC | |
7861 | ;; operands[4] is the TOC register | |
7862 | ;; | |
7863 | ;; We do not break this into separate insns, so that the scheduler will not try | |
7864 | ;; to move the load of the new TOC before any loads from the TOC. | |
7865 | ||
7866 | (define_insn "call_indirect_nt" | |
52d3af72 | 7867 | [(call (mem:SI (match_operand:SI 0 "gpc_reg_operand" "b")) |
b6c9286a | 7868 | (match_operand 1 "const_int_operand" "n")) |
6a4cee5f | 7869 | (use (match_operand 2 "const_int_operand" "n")) |
97f6e72f | 7870 | (use (match_operand 3 "offsettable_mem_operand" "o")) |
52d3af72 | 7871 | (use (match_operand 4 "gpc_reg_operand" "r")) |
b6c9286a MM |
7872 | (clobber (match_scratch:SI 5 "=&r")) |
7873 | (clobber (match_scratch:SI 6 "=l"))] | |
6a4cee5f MM |
7874 | "DEFAULT_ABI == ABI_NT |
7875 | && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)" | |
e1f83b4d | 7876 | "{st|stw} %4,%a3\;{l|lwz} %5,0(%0)\;{l|lwz} %4,4(%0)\;mt%6 %5\;{brl|blrl}\;{l|lwz} %4,%a3" |
b7ff3d82 DE |
7877 | [(set_attr "type" "load") |
7878 | (set_attr "length" "24")]) | |
b6c9286a MM |
7879 | |
7880 | (define_insn "call_value_indirect_nt" | |
7881 | [(set (match_operand 0 "register_operand" "fg") | |
52d3af72 | 7882 | (call (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
b6c9286a | 7883 | (match_operand 2 "const_int_operand" "n"))) |
6a4cee5f | 7884 | (use (match_operand 3 "const_int_operand" "n")) |
97f6e72f | 7885 | (use (match_operand 4 "offsettable_mem_operand" "o")) |
52d3af72 | 7886 | (use (match_operand 5 "gpc_reg_operand" "r")) |
b6c9286a MM |
7887 | (clobber (match_scratch:SI 6 "=&r")) |
7888 | (clobber (match_scratch:SI 7 "=l"))] | |
6a4cee5f MM |
7889 | "DEFAULT_ABI == ABI_NT |
7890 | && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)" | |
e1f83b4d | 7891 | "{st|stw} %5,%a4\;{l|lwz} %6,0(%1)\;{l|lwz} %5,4(%1)\;mt%7 %6\;{brl|blrl}\;{l|lwz} %5,%a4" |
b7ff3d82 DE |
7892 | [(set_attr "type" "load") |
7893 | (set_attr "length" "24")]) | |
b6c9286a MM |
7894 | |
7895 | ;; A function pointer under System V is just a normal pointer | |
7896 | ;; operands[0] is the function pointer | |
7897 | ;; operands[1] is the stack size to clean up | |
7898 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument which indicates how to set cr1 | |
7899 | ||
7900 | (define_insn "call_indirect_sysv" | |
7901 | [(call (mem:SI (match_operand:SI 0 "register_operand" "l,l")) | |
7902 | (match_operand 1 "const_int_operand" "n,n")) | |
7903 | (use (match_operand 2 "const_int_operand" "O,n")) | |
7904 | (clobber (match_scratch:SI 3 "=l,l"))] | |
c81bebd7 | 7905 | "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC" |
b6c9286a MM |
7906 | "* |
7907 | { | |
6a4cee5f MM |
7908 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
7909 | output_asm_insn (\"crxor 6,6,6\", operands); | |
1fd4e8c1 | 7910 | |
6a4cee5f MM |
7911 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
7912 | output_asm_insn (\"creqv 6,6,6\", operands); | |
b6c9286a MM |
7913 | |
7914 | return \"{brl|blrl}\"; | |
7915 | }" | |
b7ff3d82 DE |
7916 | [(set_attr "type" "jmpreg") |
7917 | (set_attr "length" "4,8")]) | |
b6c9286a MM |
7918 | |
7919 | (define_insn "call_value_indirect_sysv" | |
7920 | [(set (match_operand 0 "register_operand" "=fg,fg") | |
7921 | (call (mem:SI (match_operand:SI 1 "register_operand" "l,l")) | |
7922 | (match_operand 2 "const_int_operand" "n,n"))) | |
7923 | (use (match_operand 3 "const_int_operand" "O,n")) | |
7924 | (clobber (match_scratch:SI 4 "=l,l"))] | |
c81bebd7 | 7925 | "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC" |
b6c9286a MM |
7926 | "* |
7927 | { | |
6a4cee5f MM |
7928 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
7929 | output_asm_insn (\"crxor 6,6,6\", operands); | |
b6c9286a | 7930 | |
6a4cee5f MM |
7931 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) |
7932 | output_asm_insn (\"creqv 6,6,6\", operands); | |
b6c9286a MM |
7933 | |
7934 | return \"{brl|blrl}\"; | |
7935 | }" | |
b7ff3d82 DE |
7936 | [(set_attr "type" "jmpreg") |
7937 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 7938 | |
b6c9286a | 7939 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 7940 | (define_expand "call" |
a260abc9 | 7941 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 7942 | (match_operand 1 "" "")) |
4697a36c | 7943 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
7944 | (clobber (scratch:SI))])] |
7945 | "" | |
7946 | " | |
7947 | { | |
7948 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) | |
7949 | abort (); | |
7950 | ||
7951 | operands[0] = XEXP (operands[0], 0); | |
7509c759 MM |
7952 | |
7953 | /* Convert NT DLL imports into an indirect call. */ | |
7954 | if (GET_CODE (operands[0]) == SYMBOL_REF | |
6a4cee5f | 7955 | && (INTVAL (operands[2]) & CALL_NT_DLLIMPORT) != 0) |
7509c759 MM |
7956 | { |
7957 | operands[0] = rs6000_dll_import_ref (operands[0]); | |
7958 | operands[2] = GEN_INT ((int)CALL_NORMAL); | |
7959 | } | |
7960 | ||
6a4cee5f MM |
7961 | if (GET_CODE (operands[0]) != SYMBOL_REF |
7962 | || (INTVAL (operands[2]) & CALL_LONG) != 0) | |
1fd4e8c1 | 7963 | { |
6a4cee5f MM |
7964 | if (INTVAL (operands[2]) & CALL_LONG) |
7965 | operands[0] = rs6000_longcall_ref (operands[0]); | |
7966 | ||
c81bebd7 | 7967 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS) |
b6c9286a MM |
7968 | emit_call_insn (gen_call_indirect_sysv (force_reg (Pmode, operands[0]), |
7969 | operands[1], operands[2])); | |
7970 | else | |
7971 | { | |
39403d82 | 7972 | rtx toc_reg = gen_rtx_REG (Pmode, 2); |
b6c9286a | 7973 | rtx toc_addr = RS6000_SAVE_TOC; |
1fd4e8c1 | 7974 | |
b6c9286a MM |
7975 | if (DEFAULT_ABI == ABI_AIX) |
7976 | { | |
7977 | /* AIX function pointers are really pointers to a three word area */ | |
39403d82 | 7978 | rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); |
a260abc9 DE |
7979 | emit_call_insn (TARGET_32BIT |
7980 | ? gen_call_indirect_aix32 (force_reg (Pmode, operands[0]), | |
7981 | operands[1], operands[2], | |
7982 | toc_addr, toc_reg, static_chain) | |
7983 | : gen_call_indirect_aix64 (force_reg (Pmode, operands[0]), | |
7984 | operands[1], operands[2], | |
7985 | toc_addr, toc_reg, static_chain)); | |
b6c9286a MM |
7986 | } |
7987 | else if (DEFAULT_ABI == ABI_NT) | |
7988 | { | |
7989 | /* NT function pointers are really pointers to a two word area */ | |
7990 | emit_call_insn (gen_call_indirect_nt (force_reg (Pmode, operands[0]), | |
7991 | operands[1], operands[2], | |
7992 | toc_addr, toc_reg)); | |
7993 | } | |
7994 | else | |
7995 | abort (); | |
7996 | } | |
7997 | DONE; | |
1fd4e8c1 RK |
7998 | } |
7999 | }") | |
8000 | ||
8001 | (define_expand "call_value" | |
8002 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 8003 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 8004 | (match_operand 2 "" ""))) |
4697a36c | 8005 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
8006 | (clobber (scratch:SI))])] |
8007 | "" | |
8008 | " | |
8009 | { | |
8010 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) | |
8011 | abort (); | |
8012 | ||
8013 | operands[1] = XEXP (operands[1], 0); | |
7509c759 MM |
8014 | |
8015 | /* Convert NT DLL imports into an indirect call. */ | |
8016 | if (GET_CODE (operands[1]) == SYMBOL_REF | |
6a4cee5f | 8017 | && (INTVAL (operands[3]) & CALL_NT_DLLIMPORT) != 0) |
7509c759 MM |
8018 | { |
8019 | operands[1] = rs6000_dll_import_ref (operands[1]); | |
8020 | operands[3] = GEN_INT ((int)CALL_NORMAL); | |
8021 | } | |
8022 | ||
6a4cee5f MM |
8023 | if (GET_CODE (operands[1]) != SYMBOL_REF |
8024 | || (INTVAL (operands[3]) & CALL_LONG) != 0) | |
1fd4e8c1 | 8025 | { |
6756293c | 8026 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
8027 | operands[1] = rs6000_longcall_ref (operands[1]); |
8028 | ||
c81bebd7 | 8029 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS) |
b6c9286a MM |
8030 | emit_call_insn (gen_call_value_indirect_sysv (operands[0], operands[1], |
8031 | operands[2], operands[3])); | |
8032 | else | |
8033 | { | |
39403d82 | 8034 | rtx toc_reg = gen_rtx_REG (Pmode, 2); |
b6c9286a | 8035 | rtx toc_addr = RS6000_SAVE_TOC; |
1fd4e8c1 | 8036 | |
b6c9286a MM |
8037 | if (DEFAULT_ABI == ABI_AIX) |
8038 | { | |
8039 | /* AIX function pointers are really pointers to a three word area */ | |
39403d82 | 8040 | rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); |
a260abc9 DE |
8041 | emit_call_insn (TARGET_32BIT |
8042 | ? gen_call_value_indirect_aix32 (operands[0], | |
8043 | force_reg (Pmode, operands[1]), | |
8044 | operands[2], operands[3], | |
8045 | toc_addr, toc_reg, static_chain) | |
8046 | : gen_call_value_indirect_aix64 (operands[0], | |
8047 | force_reg (Pmode, operands[1]), | |
8048 | operands[2], operands[3], | |
8049 | toc_addr, toc_reg, static_chain)); | |
b6c9286a MM |
8050 | } |
8051 | else if (DEFAULT_ABI == ABI_NT) | |
8052 | { | |
8053 | /* NT function pointers are really pointers to a two word area */ | |
8054 | emit_call_insn (gen_call_value_indirect_nt (operands[0], | |
8055 | force_reg (Pmode, operands[1]), | |
8056 | operands[2], operands[3], | |
8057 | toc_addr, toc_reg)); | |
8058 | } | |
8059 | else | |
8060 | abort (); | |
8061 | } | |
8062 | DONE; | |
1fd4e8c1 RK |
8063 | } |
8064 | }") | |
8065 | ||
04780ee7 | 8066 | ;; Call to function in current module. No TOC pointer reload needed. |
4697a36c MM |
8067 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
8068 | ;; either the function was not prototyped, or it was prototyped as a | |
8069 | ;; variable argument function. It is > 0 if FP registers were passed | |
8070 | ;; and < 0 if they were not. | |
04780ee7 | 8071 | |
a260abc9 | 8072 | (define_insn "*call_local32" |
4697a36c MM |
8073 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
8074 | (match_operand 1 "" "g,g")) | |
8075 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
8076 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 8077 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
8078 | "* |
8079 | { | |
6a4cee5f MM |
8080 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
8081 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8082 | ||
8083 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
8084 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 8085 | |
a226df46 | 8086 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 8087 | }" |
b7ff3d82 DE |
8088 | [(set_attr "type" "branch") |
8089 | (set_attr "length" "4,8")]) | |
04780ee7 | 8090 | |
a260abc9 DE |
8091 | (define_insn "*call_local64" |
8092 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
8093 | (match_operand 1 "" "g,g")) | |
8094 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
8095 | (clobber (match_scratch:SI 3 "=l,l"))] | |
8096 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
8097 | "* | |
8098 | { | |
8099 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
8100 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8101 | ||
8102 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
8103 | output_asm_insn (\"creqv 6,6,6\", operands); | |
8104 | ||
8105 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
8106 | }" | |
8107 | [(set_attr "type" "branch") | |
8108 | (set_attr "length" "4,8")]) | |
8109 | ||
8110 | (define_insn "*ret_call_local32" | |
8111 | [(set (match_operand 0 "" "=fg,fg") | |
8112 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
8113 | (match_operand 2 "" "g,g"))) | |
8114 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
8115 | (clobber (match_scratch:SI 4 "=l,l"))] | |
8116 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
8117 | "* | |
8118 | { | |
8119 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
8120 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8121 | ||
8122 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
8123 | output_asm_insn (\"creqv 6,6,6\", operands); | |
8124 | ||
8125 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
8126 | }" | |
8127 | [(set_attr "type" "branch") | |
8128 | (set_attr "length" "4,8")]) | |
8129 | ||
8130 | ||
8131 | (define_insn "*ret_call_local64" | |
8132 | [(set (match_operand 0 "" "=fg,fg") | |
8133 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
8134 | (match_operand 2 "" "g,g"))) | |
8135 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
8136 | (clobber (match_scratch:SI 4 "=l,l"))] | |
8137 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
8138 | "* | |
8139 | { | |
8140 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
8141 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8142 | ||
8143 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
8144 | output_asm_insn (\"creqv 6,6,6\", operands); | |
8145 | ||
8146 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
8147 | }" | |
8148 | [(set_attr "type" "branch") | |
8149 | (set_attr "length" "4,8")]) | |
8150 | ||
04780ee7 | 8151 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 8152 | ;; pointer (r2) after the call unless this is System V. |
4697a36c MM |
8153 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
8154 | ;; either the function was not prototyped, or it was prototyped as a | |
8155 | ;; variable argument function. It is > 0 if FP registers were passed | |
8156 | ;; and < 0 if they were not. | |
04780ee7 | 8157 | |
a260abc9 | 8158 | (define_insn "*call_nonlocal_aix32" |
b6c9286a MM |
8159 | [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s")) |
8160 | (match_operand 1 "" "fg,fg")) | |
8161 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
8162 | (clobber (match_scratch:SI 3 "=l,l"))] | |
6a4cee5f | 8163 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) |
5a19791c | 8164 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
911f679c MM |
8165 | "* |
8166 | { | |
b6c9286a | 8167 | /* Indirect calls should go through call_indirect */ |
0f07e76c | 8168 | if (GET_CODE (operands[0]) == REG) |
b6c9286a | 8169 | abort (); |
911f679c | 8170 | |
6a4cee5f MM |
8171 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
8172 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8173 | ||
8174 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
8175 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 8176 | |
b6c9286a MM |
8177 | return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\"; |
8178 | }" | |
b7ff3d82 DE |
8179 | [(set_attr "type" "branch") |
8180 | (set_attr "length" "8,12")]) | |
59313e4e | 8181 | |
a260abc9 DE |
8182 | (define_insn "*call_nonlocal_aix64" |
8183 | [(call (mem:SI (match_operand:DI 0 "call_operand" "s,s")) | |
8184 | (match_operand 1 "" "fg,fg")) | |
8185 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
8186 | (clobber (match_scratch:SI 3 "=l,l"))] | |
8187 | "TARGET_64BIT && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) | |
8188 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
8189 | "* | |
8190 | { | |
8191 | /* Indirect calls should go through call_indirect */ | |
8192 | if (GET_CODE (operands[0]) == REG) | |
8193 | abort (); | |
8194 | ||
8195 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
8196 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8197 | ||
8198 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
8199 | output_asm_insn (\"creqv 6,6,6\", operands); | |
8200 | ||
8201 | return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\"; | |
8202 | }" | |
8203 | [(set_attr "type" "branch") | |
8204 | (set_attr "length" "8,12")]) | |
8205 | ||
8206 | (define_insn "*call_nonlocal_sysv" | |
b6c9286a MM |
8207 | [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s")) |
8208 | (match_operand 1 "" "fg,fg")) | |
8209 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
8210 | (clobber (match_scratch:SI 3 "=l,l"))] | |
c81bebd7 | 8211 | "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5a19791c | 8212 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
b6c9286a MM |
8213 | "* |
8214 | { | |
b6c9286a | 8215 | /* Indirect calls should go through call_indirect */ |
0f07e76c | 8216 | if (GET_CODE (operands[0]) == REG) |
b6c9286a | 8217 | abort (); |
59313e4e | 8218 | |
6a4cee5f MM |
8219 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
8220 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8221 | ||
8222 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
8223 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 8224 | |
a226df46 | 8225 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\"; |
911f679c | 8226 | }" |
b7ff3d82 DE |
8227 | [(set_attr "type" "branch") |
8228 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 8229 | |
a260abc9 | 8230 | (define_insn "*ret_call_nonlocal_aix32" |
4697a36c | 8231 | [(set (match_operand 0 "" "=fg,fg") |
a260abc9 DE |
8232 | (call (mem:SI (match_operand:SI 1 "call_operand" "s,s")) |
8233 | (match_operand 2 "" "fg,fg"))) | |
4697a36c MM |
8234 | (use (match_operand:SI 3 "immediate_operand" "O,n")) |
8235 | (clobber (match_scratch:SI 4 "=l,l"))] | |
a260abc9 DE |
8236 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) |
8237 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
4697a36c MM |
8238 | "* |
8239 | { | |
a260abc9 DE |
8240 | /* This should be handled by call_value_indirect */ |
8241 | if (GET_CODE (operands[1]) == REG) | |
8242 | abort (); | |
8243 | ||
6a4cee5f MM |
8244 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
8245 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8246 | ||
8247 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
8248 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 8249 | |
a260abc9 | 8250 | return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\"; |
4697a36c | 8251 | }" |
b7ff3d82 | 8252 | [(set_attr "type" "branch") |
a260abc9 | 8253 | (set_attr "length" "8,12")]) |
04780ee7 | 8254 | |
a260abc9 | 8255 | (define_insn "*ret_call_nonlocal_aix64" |
b6c9286a | 8256 | [(set (match_operand 0 "" "=fg,fg") |
a260abc9 | 8257 | (call (mem:SI (match_operand:DI 1 "call_operand" "s,s")) |
b6c9286a MM |
8258 | (match_operand 2 "" "fg,fg"))) |
8259 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
8260 | (clobber (match_scratch:SI 4 "=l,l"))] | |
a260abc9 | 8261 | "TARGET_64BIT && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT) |
5a19791c | 8262 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
911f679c MM |
8263 | "* |
8264 | { | |
b6c9286a | 8265 | /* This should be handled by call_value_indirect */ |
59313e4e | 8266 | if (GET_CODE (operands[1]) == REG) |
b6c9286a MM |
8267 | abort (); |
8268 | ||
6a4cee5f MM |
8269 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
8270 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8271 | ||
8272 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
8273 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 8274 | |
b6c9286a MM |
8275 | return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\"; |
8276 | }" | |
b7ff3d82 DE |
8277 | [(set_attr "type" "branch") |
8278 | (set_attr "length" "8,12")]) | |
b6c9286a | 8279 | |
a260abc9 | 8280 | (define_insn "*ret_call_nonlocal_sysv" |
b6c9286a MM |
8281 | [(set (match_operand 0 "" "=fg,fg") |
8282 | (call (mem:SI (match_operand:SI 1 "call_operand" "s,s")) | |
8283 | (match_operand 2 "" "fg,fg"))) | |
8284 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
8285 | (clobber (match_scratch:SI 4 "=l,l"))] | |
c81bebd7 | 8286 | "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5a19791c | 8287 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
b6c9286a MM |
8288 | "* |
8289 | { | |
b6c9286a | 8290 | /* This should be handled by call_value_indirect */ |
59313e4e | 8291 | if (GET_CODE (operands[1]) == REG) |
b6c9286a | 8292 | abort (); |
59313e4e | 8293 | |
6a4cee5f MM |
8294 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
8295 | output_asm_insn (\"crxor 6,6,6\", operands); | |
8296 | ||
8297 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
8298 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 8299 | |
a226df46 | 8300 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\"; |
911f679c | 8301 | }" |
b7ff3d82 DE |
8302 | [(set_attr "type" "branch") |
8303 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
8304 | |
8305 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
8306 | (define_expand "untyped_call" |
8307 | [(parallel [(call (match_operand 0 "" "") | |
8308 | (const_int 0)) | |
8309 | (match_operand 1 "" "") | |
8310 | (match_operand 2 "" "")])] | |
8311 | "" | |
8312 | " | |
8313 | { | |
8314 | int i; | |
8315 | ||
4697a36c | 8316 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
8317 | |
8318 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
8319 | { | |
8320 | rtx set = XVECEXP (operands[2], 0, i); | |
8321 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
8322 | } | |
8323 | ||
8324 | /* The optimizer does not know that the call sets the function value | |
8325 | registers we stored in the result block. We avoid problems by | |
8326 | claiming that all hard registers are used and clobbered at this | |
8327 | point. */ | |
8328 | emit_insn (gen_blockage ()); | |
8329 | ||
8330 | DONE; | |
8331 | }") | |
8332 | ||
8333 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
8334 | ;; all of memory. This blocks insns from being moved across this point. | |
8335 | ||
8336 | (define_insn "blockage" | |
8337 | [(unspec_volatile [(const_int 0)] 0)] | |
8338 | "" | |
8339 | "") | |
4697a36c | 8340 | |
766a866c MM |
8341 | ;; V.4 specific code to initialize the PIC register |
8342 | ||
8343 | (define_insn "init_v4_pic" | |
8344 | [(set (match_operand:SI 0 "register_operand" "=l") | |
8345 | (unspec [(const_int 0)] 7))] | |
c81bebd7 | 8346 | "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS" |
eaf1bcf1 | 8347 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
63d7d7a1 MM |
8348 | [(set_attr "type" "branch") |
8349 | (set_attr "length" "4")]) | |
766a866c | 8350 | |
1fd4e8c1 RK |
8351 | \f |
8352 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 8353 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
8354 | ;; |
8355 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
8356 | ;; insns, and branches. We store the operands of compares until we see | |
8357 | ;; how it is used. | |
8358 | (define_expand "cmpsi" | |
8359 | [(set (cc0) | |
cd2b37d9 | 8360 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8361 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
8362 | "" | |
8363 | " | |
8364 | { | |
8365 | /* Take care of the possibility that operands[1] might be negative but | |
8366 | this might be a logical operation. That insn doesn't exist. */ | |
8367 | if (GET_CODE (operands[1]) == CONST_INT | |
8368 | && INTVAL (operands[1]) < 0) | |
8369 | operands[1] = force_reg (SImode, operands[1]); | |
8370 | ||
8371 | rs6000_compare_op0 = operands[0]; | |
8372 | rs6000_compare_op1 = operands[1]; | |
8373 | rs6000_compare_fp_p = 0; | |
8374 | DONE; | |
8375 | }") | |
8376 | ||
266eb58a DE |
8377 | (define_expand "cmpdi" |
8378 | [(set (cc0) | |
8379 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
8380 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
8381 | "TARGET_POWERPC64" | |
8382 | " | |
8383 | { | |
8384 | /* Take care of the possibility that operands[1] might be negative but | |
8385 | this might be a logical operation. That insn doesn't exist. */ | |
8386 | if (GET_CODE (operands[1]) == CONST_INT | |
8387 | && INTVAL (operands[1]) < 0) | |
8388 | operands[1] = force_reg (DImode, operands[1]); | |
8389 | ||
8390 | rs6000_compare_op0 = operands[0]; | |
8391 | rs6000_compare_op1 = operands[1]; | |
8392 | rs6000_compare_fp_p = 0; | |
8393 | DONE; | |
8394 | }") | |
8395 | ||
1fd4e8c1 | 8396 | (define_expand "cmpsf" |
cd2b37d9 RK |
8397 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
8398 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 8399 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
8400 | " |
8401 | { | |
8402 | rs6000_compare_op0 = operands[0]; | |
8403 | rs6000_compare_op1 = operands[1]; | |
8404 | rs6000_compare_fp_p = 1; | |
8405 | DONE; | |
8406 | }") | |
8407 | ||
8408 | (define_expand "cmpdf" | |
cd2b37d9 RK |
8409 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
8410 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 8411 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
8412 | " |
8413 | { | |
8414 | rs6000_compare_op0 = operands[0]; | |
8415 | rs6000_compare_op1 = operands[1]; | |
8416 | rs6000_compare_fp_p = 1; | |
8417 | DONE; | |
8418 | }") | |
8419 | ||
8420 | (define_expand "beq" | |
8421 | [(set (match_dup 2) (match_dup 1)) | |
8422 | (set (pc) | |
8423 | (if_then_else (eq (match_dup 2) | |
8424 | (const_int 0)) | |
8425 | (label_ref (match_operand 0 "" "")) | |
8426 | (pc)))] | |
8427 | "" | |
8428 | " | |
8429 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8430 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8431 | rs6000_compare_op0, rs6000_compare_op1); |
8432 | operands[2] = gen_reg_rtx (mode); | |
8433 | }") | |
8434 | ||
8435 | (define_expand "bne" | |
8436 | [(set (match_dup 2) (match_dup 1)) | |
8437 | (set (pc) | |
8438 | (if_then_else (ne (match_dup 2) | |
8439 | (const_int 0)) | |
8440 | (label_ref (match_operand 0 "" "")) | |
8441 | (pc)))] | |
8442 | "" | |
8443 | " | |
8444 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8445 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8446 | rs6000_compare_op0, rs6000_compare_op1); |
8447 | operands[2] = gen_reg_rtx (mode); | |
8448 | }") | |
8449 | ||
8450 | (define_expand "blt" | |
8451 | [(set (match_dup 2) (match_dup 1)) | |
8452 | (set (pc) | |
8453 | (if_then_else (lt (match_dup 2) | |
8454 | (const_int 0)) | |
8455 | (label_ref (match_operand 0 "" "")) | |
8456 | (pc)))] | |
8457 | "" | |
8458 | " | |
8459 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8460 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8461 | rs6000_compare_op0, rs6000_compare_op1); |
8462 | operands[2] = gen_reg_rtx (mode); | |
8463 | }") | |
8464 | ||
8465 | (define_expand "bgt" | |
8466 | [(set (match_dup 2) (match_dup 1)) | |
8467 | (set (pc) | |
8468 | (if_then_else (gt (match_dup 2) | |
8469 | (const_int 0)) | |
8470 | (label_ref (match_operand 0 "" "")) | |
8471 | (pc)))] | |
8472 | "" | |
8473 | " | |
8474 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8475 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8476 | rs6000_compare_op0, rs6000_compare_op1); |
8477 | operands[2] = gen_reg_rtx (mode); | |
8478 | }") | |
8479 | ||
8480 | (define_expand "ble" | |
8481 | [(set (match_dup 2) (match_dup 1)) | |
8482 | (set (pc) | |
8483 | (if_then_else (le (match_dup 2) | |
8484 | (const_int 0)) | |
8485 | (label_ref (match_operand 0 "" "")) | |
8486 | (pc)))] | |
8487 | "" | |
8488 | " | |
8489 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8490 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8491 | rs6000_compare_op0, rs6000_compare_op1); |
8492 | operands[2] = gen_reg_rtx (mode); | |
8493 | }") | |
8494 | ||
8495 | (define_expand "bge" | |
8496 | [(set (match_dup 2) (match_dup 1)) | |
8497 | (set (pc) | |
8498 | (if_then_else (ge (match_dup 2) | |
8499 | (const_int 0)) | |
8500 | (label_ref (match_operand 0 "" "")) | |
8501 | (pc)))] | |
8502 | "" | |
8503 | " | |
8504 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8505 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8506 | rs6000_compare_op0, rs6000_compare_op1); |
8507 | operands[2] = gen_reg_rtx (mode); | |
8508 | }") | |
8509 | ||
8510 | (define_expand "bgtu" | |
8511 | [(set (match_dup 2) (match_dup 1)) | |
8512 | (set (pc) | |
8513 | (if_then_else (gtu (match_dup 2) | |
8514 | (const_int 0)) | |
8515 | (label_ref (match_operand 0 "" "")) | |
8516 | (pc)))] | |
8517 | "" | |
8518 | " | |
39403d82 | 8519 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8520 | rs6000_compare_op0, rs6000_compare_op1); |
8521 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8522 | }") | |
8523 | ||
8524 | (define_expand "bltu" | |
8525 | [(set (match_dup 2) (match_dup 1)) | |
8526 | (set (pc) | |
8527 | (if_then_else (ltu (match_dup 2) | |
8528 | (const_int 0)) | |
8529 | (label_ref (match_operand 0 "" "")) | |
8530 | (pc)))] | |
8531 | "" | |
8532 | " | |
39403d82 | 8533 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8534 | rs6000_compare_op0, rs6000_compare_op1); |
8535 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8536 | }") | |
8537 | ||
8538 | (define_expand "bgeu" | |
8539 | [(set (match_dup 2) (match_dup 1)) | |
8540 | (set (pc) | |
8541 | (if_then_else (geu (match_dup 2) | |
8542 | (const_int 0)) | |
8543 | (label_ref (match_operand 0 "" "")) | |
8544 | (pc)))] | |
8545 | "" | |
8546 | " | |
39403d82 | 8547 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8548 | rs6000_compare_op0, rs6000_compare_op1); |
8549 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8550 | }") | |
8551 | ||
8552 | (define_expand "bleu" | |
8553 | [(set (match_dup 2) (match_dup 1)) | |
8554 | (set (pc) | |
8555 | (if_then_else (leu (match_dup 2) | |
8556 | (const_int 0)) | |
8557 | (label_ref (match_operand 0 "" "")) | |
8558 | (pc)))] | |
8559 | "" | |
8560 | " | |
39403d82 | 8561 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8562 | rs6000_compare_op0, rs6000_compare_op1); |
8563 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8564 | }") | |
8565 | ||
8566 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. | |
8567 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
8568 | ;; with an scc insns. However, due to the order that combine see the | |
8569 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
8570 | ;; the cases we don't want to handle. | |
8571 | (define_expand "seq" | |
8572 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8573 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8574 | (eq:SI (match_dup 2) (const_int 0)))] |
8575 | "" | |
8576 | " | |
8577 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8578 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8579 | rs6000_compare_op0, rs6000_compare_op1); |
8580 | operands[2] = gen_reg_rtx (mode); | |
8581 | }") | |
8582 | ||
8583 | (define_expand "sne" | |
8584 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8585 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8586 | (ne:SI (match_dup 2) (const_int 0)))] |
8587 | "" | |
8588 | " | |
8589 | { if (! rs6000_compare_fp_p) | |
8590 | FAIL; | |
8591 | ||
39403d82 | 8592 | operands[1] = gen_rtx_COMPARE (CCFPmode, |
1fd4e8c1 RK |
8593 | rs6000_compare_op0, rs6000_compare_op1); |
8594 | operands[2] = gen_reg_rtx (CCFPmode); | |
8595 | }") | |
8596 | ||
8597 | ;; A > 0 is best done using the portable sequence, so fail in that case. | |
8598 | (define_expand "sgt" | |
8599 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8600 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8601 | (gt:SI (match_dup 2) (const_int 0)))] |
8602 | "" | |
8603 | " | |
8604 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
8605 | ||
8606 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
8607 | FAIL; | |
8608 | ||
39403d82 | 8609 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8610 | rs6000_compare_op0, rs6000_compare_op1); |
8611 | operands[2] = gen_reg_rtx (mode); | |
8612 | }") | |
8613 | ||
8614 | ;; A < 0 is best done in the portable way for A an integer. | |
8615 | (define_expand "slt" | |
8616 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8617 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8618 | (lt:SI (match_dup 2) (const_int 0)))] |
8619 | "" | |
8620 | " | |
8621 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
8622 | ||
8623 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
8624 | FAIL; | |
8625 | ||
39403d82 | 8626 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8627 | rs6000_compare_op0, rs6000_compare_op1); |
8628 | operands[2] = gen_reg_rtx (mode); | |
8629 | }") | |
8630 | ||
8631 | (define_expand "sge" | |
8632 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8633 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8634 | (ge:SI (match_dup 2) (const_int 0)))] |
8635 | "" | |
8636 | " | |
8637 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 8638 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8639 | rs6000_compare_op0, rs6000_compare_op1); |
8640 | operands[2] = gen_reg_rtx (mode); | |
8641 | }") | |
8642 | ||
8643 | ;; A <= 0 is best done the portable way for A an integer. | |
8644 | (define_expand "sle" | |
8645 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8646 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8647 | (le:SI (match_dup 2) (const_int 0)))] |
8648 | "" | |
8649 | " | |
8650 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
8651 | ||
8652 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
8653 | FAIL; | |
8654 | ||
39403d82 | 8655 | operands[1] = gen_rtx_COMPARE (mode, |
1fd4e8c1 RK |
8656 | rs6000_compare_op0, rs6000_compare_op1); |
8657 | operands[2] = gen_reg_rtx (mode); | |
8658 | }") | |
8659 | ||
8660 | (define_expand "sgtu" | |
8661 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8662 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8663 | (gtu:SI (match_dup 2) (const_int 0)))] |
8664 | "" | |
8665 | " | |
39403d82 | 8666 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8667 | rs6000_compare_op0, rs6000_compare_op1); |
8668 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8669 | }") | |
8670 | ||
8671 | (define_expand "sltu" | |
8672 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8673 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8674 | (ltu:SI (match_dup 2) (const_int 0)))] |
8675 | "" | |
8676 | " | |
39403d82 | 8677 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8678 | rs6000_compare_op0, rs6000_compare_op1); |
8679 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8680 | }") | |
8681 | ||
8682 | (define_expand "sgeu" | |
8683 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8684 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8685 | (geu:SI (match_dup 2) (const_int 0)))] |
8686 | "" | |
8687 | " | |
39403d82 | 8688 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8689 | rs6000_compare_op0, rs6000_compare_op1); |
8690 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8691 | }") | |
8692 | ||
8693 | (define_expand "sleu" | |
8694 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 8695 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8696 | (leu:SI (match_dup 2) (const_int 0)))] |
8697 | "" | |
8698 | " | |
39403d82 | 8699 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
1fd4e8c1 RK |
8700 | rs6000_compare_op0, rs6000_compare_op1); |
8701 | operands[2] = gen_reg_rtx (CCUNSmode); | |
8702 | }") | |
8703 | \f | |
8704 | ;; Here are the actual compare insns. | |
8705 | (define_insn "" | |
8706 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
cd2b37d9 | 8707 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
8708 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
8709 | "" | |
7f340546 | 8710 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
1fd4e8c1 RK |
8711 | [(set_attr "type" "compare")]) |
8712 | ||
266eb58a DE |
8713 | (define_insn "" |
8714 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
8715 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
8716 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
8717 | "TARGET_POWERPC64" | |
8718 | "cmpd%I2 %0,%1,%2" | |
8719 | [(set_attr "type" "compare")]) | |
8720 | ||
f357808b RK |
8721 | ;; If we are comparing a register for equality with a large constant, |
8722 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
8723 | ;; register for the result of the XOR. | |
8724 | ||
8725 | (define_split | |
8726 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 8727 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 8728 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 8729 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
8730 | "find_single_use (operands[0], insn, 0) |
8731 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
8732 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
8733 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
8734 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
8735 | " | |
8736 | { | |
8737 | /* Get the constant we are comparing against, C, and see what it looks like | |
8738 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
8739 | with C to get the sign-extended value. */ | |
8740 | ||
8741 | int c = INTVAL (operands[2]); | |
8742 | int sextc = (c << 16) >> 16; | |
8743 | int xorv = c ^ sextc; | |
8744 | ||
89e9f3a8 MM |
8745 | operands[4] = GEN_INT (xorv); |
8746 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
8747 | }") |
8748 | ||
1fd4e8c1 RK |
8749 | (define_insn "" |
8750 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") | |
cd2b37d9 | 8751 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
8752 | (match_operand:SI 2 "reg_or_u_short_operand" "rI")))] |
8753 | "" | |
7f340546 | 8754 | "{cmpl%I2|cmplw%I2} %0,%1,%W2" |
1fd4e8c1 RK |
8755 | [(set_attr "type" "compare")]) |
8756 | ||
266eb58a DE |
8757 | (define_insn "" |
8758 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") | |
8759 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
8760 | (match_operand:DI 2 "reg_or_u_short_operand" "rI")))] | |
8761 | "" | |
8762 | "cmpld%I2 %0,%1,%W2" | |
8763 | [(set_attr "type" "compare")]) | |
8764 | ||
1fd4e8c1 RK |
8765 | ;; The following two insns don't exist as single insns, but if we provide |
8766 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
8767 | ;; of the required delay between a compare and branch. We generate code for | |
8768 | ;; them by splitting. | |
8769 | ||
8770 | (define_insn "" | |
8771 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 8772 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 8773 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 8774 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
8775 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
8776 | "" | |
baf97f86 RK |
8777 | "#" |
8778 | [(set_attr "length" "8")]) | |
7e69e155 | 8779 | |
1fd4e8c1 RK |
8780 | (define_insn "" |
8781 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 8782 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 8783 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 8784 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
8785 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
8786 | "" | |
baf97f86 RK |
8787 | "#" |
8788 | [(set_attr "length" "8")]) | |
7e69e155 | 8789 | |
1fd4e8c1 RK |
8790 | (define_split |
8791 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 8792 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 8793 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 8794 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8795 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
8796 | "" | |
8797 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
8798 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
8799 | ||
8800 | (define_split | |
8801 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 8802 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 8803 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 8804 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
8805 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
8806 | "" | |
8807 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
8808 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
8809 | ||
8810 | (define_insn "" | |
8811 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
cd2b37d9 RK |
8812 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
8813 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 8814 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
8815 | "fcmpu %0,%1,%2" |
8816 | [(set_attr "type" "fpcompare")]) | |
8817 | ||
8818 | (define_insn "" | |
8819 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
cd2b37d9 RK |
8820 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
8821 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 8822 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
8823 | "fcmpu %0,%1,%2" |
8824 | [(set_attr "type" "fpcompare")]) | |
8825 | \f | |
8826 | ;; Now we have the scc insns. We can do some combinations because of the | |
8827 | ;; way the machine works. | |
8828 | ;; | |
8829 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
8830 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
8831 | ;; cases the insns below which don't use an intermediate CR field will | |
8832 | ;; be used instead. | |
1fd4e8c1 | 8833 | (define_insn "" |
cd2b37d9 | 8834 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
8835 | (match_operator:SI 1 "scc_comparison_operator" |
8836 | [(match_operand 2 "cc_reg_operand" "y") | |
8837 | (const_int 0)]))] | |
8838 | "" | |
ca7f5001 | 8839 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" |
b19003d8 | 8840 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
8841 | |
8842 | (define_insn "" | |
8843 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
8844 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
8845 | [(match_operand 2 "cc_reg_operand" "y") | |
8846 | (const_int 0)]) | |
8847 | (const_int 0))) | |
cd2b37d9 | 8848 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
8849 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
8850 | "" | |
ca7f5001 | 8851 | "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1" |
b19003d8 RK |
8852 | [(set_attr "type" "delayed_compare") |
8853 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
8854 | |
8855 | (define_insn "" | |
cd2b37d9 | 8856 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
8857 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
8858 | [(match_operand 2 "cc_reg_operand" "y") | |
8859 | (const_int 0)]) | |
8860 | (match_operand:SI 3 "const_int_operand" "n")))] | |
8861 | "" | |
8862 | "* | |
8863 | { | |
8864 | int is_bit = ccr_bit (operands[1], 1); | |
8865 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
8866 | int count; | |
8867 | ||
8868 | if (is_bit >= put_bit) | |
8869 | count = is_bit - put_bit; | |
8870 | else | |
8871 | count = 32 - (put_bit - is_bit); | |
8872 | ||
89e9f3a8 MM |
8873 | operands[4] = GEN_INT (count); |
8874 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 8875 | |
ca7f5001 | 8876 | return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 RK |
8877 | }" |
8878 | [(set_attr "length" "12")]) | |
1fd4e8c1 RK |
8879 | |
8880 | (define_insn "" | |
8881 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") | |
8882 | (compare:CC | |
8883 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
8884 | [(match_operand 2 "cc_reg_operand" "y") | |
8885 | (const_int 0)]) | |
8886 | (match_operand:SI 3 "const_int_operand" "n")) | |
8887 | (const_int 0))) | |
cd2b37d9 | 8888 | (set (match_operand:SI 4 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
8889 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
8890 | (match_dup 3)))] | |
8891 | "" | |
8892 | "* | |
8893 | { | |
8894 | int is_bit = ccr_bit (operands[1], 1); | |
8895 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
8896 | int count; | |
8897 | ||
8898 | if (is_bit >= put_bit) | |
8899 | count = is_bit - put_bit; | |
8900 | else | |
8901 | count = 32 - (put_bit - is_bit); | |
8902 | ||
89e9f3a8 MM |
8903 | operands[5] = GEN_INT (count); |
8904 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 8905 | |
ca7f5001 | 8906 | return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 8907 | }" |
b19003d8 RK |
8908 | [(set_attr "type" "delayed_compare") |
8909 | (set_attr "length" "12")]) | |
1fd4e8c1 | 8910 | |
c5defebb RK |
8911 | ;; If we are comparing the result of two comparisons, this can be done |
8912 | ;; using creqv or crxor. | |
8913 | ||
8914 | (define_insn "" | |
8915 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
8916 | (compare:CCEQ (match_operator 1 "scc_comparison_operator" | |
8917 | [(match_operand 2 "cc_reg_operand" "y") | |
8918 | (const_int 0)]) | |
8919 | (match_operator 3 "scc_comparison_operator" | |
8920 | [(match_operand 4 "cc_reg_operand" "y") | |
8921 | (const_int 0)])))] | |
8922 | "REGNO (operands[2]) != REGNO (operands[4])" | |
8923 | "* | |
8924 | { | |
8925 | enum rtx_code code1, code2; | |
8926 | ||
8927 | code1 = GET_CODE (operands[1]); | |
8928 | code2 = GET_CODE (operands[3]); | |
8929 | ||
8930 | if ((code1 == EQ || code1 == LT || code1 == GT | |
8931 | || code1 == LTU || code1 == GTU | |
8932 | || (code1 != NE && GET_MODE (operands[2]) == CCFPmode)) | |
8933 | != | |
8934 | (code2 == EQ || code2 == LT || code2 == GT | |
8935 | || code2 == LTU || code2 == GTU | |
8936 | || (code2 != NE && GET_MODE (operands[4]) == CCFPmode))) | |
8937 | return \"%C1%C3crxor %E0,%j1,%j3\"; | |
8938 | else | |
8939 | return \"%C1%C3creqv %E0,%j1,%j3\"; | |
b19003d8 RK |
8940 | }" |
8941 | [(set_attr "length" "12")]) | |
c5defebb RK |
8942 | |
8943 | ;; There is a 3 cycle delay between consecutive mfcr instructions | |
8944 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
8945 | ||
8946 | (define_peephole | |
cd2b37d9 | 8947 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
8948 | (match_operator:SI 1 "scc_comparison_operator" |
8949 | [(match_operand 2 "cc_reg_operand" "y") | |
8950 | (const_int 0)])) | |
cd2b37d9 | 8951 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
8952 | (match_operator:SI 4 "scc_comparison_operator" |
8953 | [(match_operand 5 "cc_reg_operand" "y") | |
8954 | (const_int 0)]))] | |
8955 | "REGNO (operands[2]) != REGNO (operands[5])" | |
ca7f5001 | 8956 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b19003d8 | 8957 | [(set_attr "length" "20")]) |
c5defebb | 8958 | |
1fd4e8c1 RK |
8959 | ;; There are some scc insns that can be done directly, without a compare. |
8960 | ;; These are faster because they don't involve the communications between | |
8961 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
8962 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
8963 | ;; | |
8964 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
8965 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
8966 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
8967 | ;; cases where it is no more expensive than (neg (scc ..)). | |
8968 | ||
8969 | ;; Have reload force a constant into a register for the simple insns that | |
8970 | ;; otherwise won't accept constants. We do this because it is faster than | |
8971 | ;; the cmp/mfcr sequence we would otherwise generate. | |
8972 | ||
8973 | (define_insn "" | |
cd2b37d9 RK |
8974 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
8975 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
1fd4e8c1 RK |
8976 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))) |
8977 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] | |
8978 | "" | |
8979 | "@ | |
ca7f5001 | 8980 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 8981 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
8982 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
8983 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
8984 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 8985 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 8986 | |
a260abc9 DE |
8987 | (define_insn "" |
8988 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
8989 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
8990 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
8991 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
8992 | "TARGET_POWERPC64" | |
8993 | "@ | |
8994 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
8995 | subfic %3,%1,0\;adde %0,%3,%1 | |
8996 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
8997 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
8998 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
8999 | [(set_attr "length" "12,8,12,12,12")]) | |
9000 | ||
1fd4e8c1 | 9001 | (define_insn "" |
29ae5b89 | 9002 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") |
7e69e155 | 9003 | (compare:CC |
29ae5b89 JL |
9004 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
9005 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) | |
1fd4e8c1 | 9006 | (const_int 0))) |
29ae5b89 | 9007 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
1fd4e8c1 | 9008 | (eq:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 9009 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
1fd4e8c1 RK |
9010 | "" |
9011 | "@ | |
ca7f5001 RK |
9012 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
9013 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
9014 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9015 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
29ae5b89 | 9016 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0" |
b19003d8 | 9017 | [(set_attr "type" "compare") |
29ae5b89 | 9018 | (set_attr "length" "12,8,12,12,12")]) |
b19003d8 | 9019 | |
a260abc9 | 9020 | (define_insn "" |
29ae5b89 | 9021 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") |
a260abc9 | 9022 | (compare:CC |
29ae5b89 JL |
9023 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") |
9024 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")) | |
a260abc9 | 9025 | (const_int 0))) |
29ae5b89 | 9026 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") |
a260abc9 | 9027 | (eq:DI (match_dup 1) (match_dup 2))) |
29ae5b89 | 9028 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] |
a260abc9 DE |
9029 | "TARGET_POWERPC64" |
9030 | "@ | |
9031 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9032 | subfic %3,%1,0\;adde. %0,%3,%1 | |
9033 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9034 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
29ae5b89 | 9035 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0" |
a260abc9 | 9036 | [(set_attr "type" "compare") |
29ae5b89 | 9037 | (set_attr "length" "12,8,12,12,12")]) |
a260abc9 | 9038 | |
b19003d8 RK |
9039 | ;; We have insns of the form shown by the first define_insn below. If |
9040 | ;; there is something inside the comparison operation, we must split it. | |
9041 | (define_split | |
9042 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
9043 | (plus:SI (match_operator 1 "comparison_operator" | |
9044 | [(match_operand:SI 2 "" "") | |
9045 | (match_operand:SI 3 | |
9046 | "reg_or_cint_operand" "")]) | |
9047 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
9048 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
9049 | "! gpc_reg_operand (operands[2], SImode)" | |
9050 | [(set (match_dup 5) (match_dup 2)) | |
9051 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
9052 | (match_dup 4)))]) | |
1fd4e8c1 RK |
9053 | |
9054 | (define_insn "" | |
cd2b37d9 RK |
9055 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
9056 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
1fd4e8c1 | 9057 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) |
cd2b37d9 | 9058 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) |
1fd4e8c1 RK |
9059 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
9060 | "" | |
9061 | "@ | |
ca7f5001 RK |
9062 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
9063 | {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3 | |
9064 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
9065 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
d9d934ef | 9066 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" |
b19003d8 | 9067 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
9068 | |
9069 | (define_insn "" | |
29ae5b89 | 9070 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x") |
7e69e155 | 9071 | (compare:CC |
1fd4e8c1 | 9072 | (plus:SI |
29ae5b89 JL |
9073 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
9074 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) | |
9075 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) | |
1fd4e8c1 | 9076 | (const_int 0))) |
29ae5b89 | 9077 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
1fd4e8c1 RK |
9078 | "" |
9079 | "@ | |
ca7f5001 | 9080 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 9081 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
9082 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9083 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
29ae5b89 | 9084 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" |
b19003d8 | 9085 | [(set_attr "type" "compare") |
29ae5b89 | 9086 | (set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
9087 | |
9088 | (define_insn "" | |
29ae5b89 | 9089 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x") |
7e69e155 | 9090 | (compare:CC |
1fd4e8c1 | 9091 | (plus:SI |
29ae5b89 JL |
9092 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
9093 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) | |
9094 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) | |
1fd4e8c1 | 9095 | (const_int 0))) |
29ae5b89 | 9096 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
1fd4e8c1 | 9097 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9098 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
1fd4e8c1 RK |
9099 | "" |
9100 | "@ | |
ca7f5001 | 9101 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
19378cf8 | 9102 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3 |
ca7f5001 RK |
9103 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
9104 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
29ae5b89 | 9105 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" |
b19003d8 | 9106 | [(set_attr "type" "compare") |
29ae5b89 | 9107 | (set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
9108 | |
9109 | (define_insn "" | |
cd2b37d9 | 9110 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 9111 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
1fd4e8c1 RK |
9112 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))] |
9113 | "" | |
9114 | "@ | |
ca7f5001 RK |
9115 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
9116 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
9117 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
9118 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
9119 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 9120 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 9121 | |
ea9be077 MM |
9122 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
9123 | ;; since it nabs/sr is just as fast. | |
463b558b | 9124 | (define_insn "*ne0" |
b4e95693 | 9125 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
9126 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
9127 | (const_int 31))) | |
9128 | (clobber (match_scratch:SI 2 "=&r"))] | |
9129 | "!TARGET_POWER" | |
9130 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" | |
9131 | [(set_attr "length" "8")]) | |
9132 | ||
a260abc9 DE |
9133 | (define_insn "" |
9134 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
9135 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
9136 | (const_int 63))) | |
9137 | (clobber (match_scratch:DI 2 "=&r"))] | |
9138 | "TARGET_POWERPC64" | |
9139 | "addic %2,%1,-1\;subfe %0,%2,%1" | |
9140 | [(set_attr "length" "8")]) | |
9141 | ||
1fd4e8c1 RK |
9142 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
9143 | (define_insn "" | |
cd2b37d9 | 9144 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9145 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 9146 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 9147 | (const_int 31)) |
cd2b37d9 | 9148 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
9149 | (clobber (match_scratch:SI 3 "=&r"))] |
9150 | "" | |
ca7f5001 | 9151 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 9152 | [(set_attr "length" "8")]) |
1fd4e8c1 | 9153 | |
a260abc9 DE |
9154 | (define_insn "" |
9155 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
9156 | (plus:DI (lshiftrt:DI | |
9157 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
9158 | (const_int 63)) | |
9159 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
9160 | (clobber (match_scratch:DI 3 "=&r"))] | |
9161 | "TARGET_POWERPC64" | |
9162 | "addic %3,%1,-1\;addze %0,%2" | |
9163 | [(set_attr "length" "8")]) | |
9164 | ||
1fd4e8c1 | 9165 | (define_insn "" |
29ae5b89 | 9166 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9167 | (compare:CC |
9168 | (plus:SI (lshiftrt:SI | |
29ae5b89 | 9169 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 9170 | (const_int 31)) |
29ae5b89 | 9171 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9172 | (const_int 0))) |
29ae5b89 | 9173 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 9174 | "" |
29ae5b89 | 9175 | "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2" |
b19003d8 | 9176 | [(set_attr "type" "compare") |
29ae5b89 | 9177 | (set_attr "length" "8")]) |
1fd4e8c1 | 9178 | |
a260abc9 | 9179 | (define_insn "" |
29ae5b89 | 9180 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
a260abc9 DE |
9181 | (compare:CC |
9182 | (plus:DI (lshiftrt:DI | |
29ae5b89 | 9183 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) |
a260abc9 | 9184 | (const_int 63)) |
29ae5b89 | 9185 | (match_operand:DI 2 "gpc_reg_operand" "r")) |
a260abc9 | 9186 | (const_int 0))) |
29ae5b89 | 9187 | (clobber (match_scratch:DI 3 "=&r"))] |
a260abc9 | 9188 | "TARGET_POWERPC64" |
29ae5b89 | 9189 | "addic %3,%1,-1\;addze. %3,%2" |
a260abc9 | 9190 | [(set_attr "type" "compare") |
29ae5b89 | 9191 | (set_attr "length" "8")]) |
a260abc9 | 9192 | |
1fd4e8c1 | 9193 | (define_insn "" |
29ae5b89 | 9194 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9195 | (compare:CC |
9196 | (plus:SI (lshiftrt:SI | |
29ae5b89 | 9197 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 9198 | (const_int 31)) |
29ae5b89 | 9199 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9200 | (const_int 0))) |
29ae5b89 | 9201 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9202 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
9203 | (match_dup 2))) | |
29ae5b89 | 9204 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 9205 | "" |
29ae5b89 | 9206 | "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2" |
b19003d8 | 9207 | [(set_attr "type" "compare") |
29ae5b89 | 9208 | (set_attr "length" "8")]) |
1fd4e8c1 | 9209 | |
a260abc9 | 9210 | (define_insn "" |
29ae5b89 | 9211 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
a260abc9 DE |
9212 | (compare:CC |
9213 | (plus:DI (lshiftrt:DI | |
29ae5b89 | 9214 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) |
a260abc9 | 9215 | (const_int 63)) |
29ae5b89 | 9216 | (match_operand:DI 2 "gpc_reg_operand" "r")) |
a260abc9 | 9217 | (const_int 0))) |
29ae5b89 | 9218 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9219 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
9220 | (match_dup 2))) | |
29ae5b89 | 9221 | (clobber (match_scratch:DI 3 "=&r"))] |
a260abc9 | 9222 | "TARGET_POWERPC64" |
29ae5b89 | 9223 | "addic %3,%1,-1\;addze. %0,%2" |
a260abc9 | 9224 | [(set_attr "type" "compare") |
29ae5b89 | 9225 | (set_attr "length" "8")]) |
a260abc9 | 9226 | |
1fd4e8c1 | 9227 | (define_insn "" |
cd2b37d9 RK |
9228 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9229 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
9230 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
9231 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 9232 | "TARGET_POWER" |
1fd4e8c1 | 9233 | "@ |
ca7f5001 | 9234 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 9235 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 9236 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9237 | |
9238 | (define_insn "" | |
29ae5b89 | 9239 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9240 | (compare:CC |
29ae5b89 JL |
9241 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9242 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) | |
1fd4e8c1 | 9243 | (const_int 0))) |
29ae5b89 | 9244 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9245 | (le:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 9246 | (clobber (match_scratch:SI 3 "=r,X"))] |
ca7f5001 | 9247 | "TARGET_POWER" |
1fd4e8c1 | 9248 | "@ |
ca7f5001 | 9249 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
29ae5b89 JL |
9250 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31" |
9251 | [(set_attr "type" "compare,delayed_compare") | |
9252 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
9253 | |
9254 | (define_insn "" | |
cd2b37d9 RK |
9255 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9256 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 9257 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
cd2b37d9 | 9258 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 9259 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 9260 | "TARGET_POWER" |
1fd4e8c1 | 9261 | "@ |
ca7f5001 RK |
9262 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
9263 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" | |
b19003d8 | 9264 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9265 | |
9266 | (define_insn "" | |
29ae5b89 | 9267 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9268 | (compare:CC |
29ae5b89 JL |
9269 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9270 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) | |
9271 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9272 | (const_int 0))) |
29ae5b89 | 9273 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 9274 | "TARGET_POWER" |
1fd4e8c1 | 9275 | "@ |
ca7f5001 | 9276 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
29ae5b89 | 9277 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3" |
b19003d8 | 9278 | [(set_attr "type" "compare") |
29ae5b89 | 9279 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9280 | |
9281 | (define_insn "" | |
29ae5b89 | 9282 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9283 | (compare:CC |
29ae5b89 JL |
9284 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9285 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) | |
9286 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9287 | (const_int 0))) |
29ae5b89 | 9288 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9289 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9290 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 9291 | "TARGET_POWER" |
1fd4e8c1 | 9292 | "@ |
ca7f5001 | 9293 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
29ae5b89 | 9294 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3" |
b19003d8 | 9295 | [(set_attr "type" "compare") |
29ae5b89 | 9296 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9297 | |
9298 | (define_insn "" | |
cd2b37d9 RK |
9299 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9300 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 9301 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 9302 | "TARGET_POWER" |
1fd4e8c1 | 9303 | "@ |
ca7f5001 RK |
9304 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
9305 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 9306 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9307 | |
9308 | (define_insn "" | |
cd2b37d9 RK |
9309 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9310 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
9311 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
9312 | "" | |
ca7f5001 | 9313 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 9314 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9315 | |
9316 | (define_insn "" | |
29ae5b89 | 9317 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 | 9318 | (compare:CC |
29ae5b89 JL |
9319 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9320 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 | 9321 | (const_int 0))) |
29ae5b89 | 9322 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9323 | (leu:SI (match_dup 1) (match_dup 2)))] |
9324 | "" | |
29ae5b89 | 9325 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" |
b19003d8 | 9326 | [(set_attr "type" "compare") |
29ae5b89 | 9327 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9328 | |
9329 | (define_insn "" | |
cd2b37d9 RK |
9330 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9331 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9332 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 9333 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
9334 | (clobber (match_scratch:SI 4 "=&r"))] |
9335 | "" | |
ca7f5001 | 9336 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 9337 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
9338 | |
9339 | (define_insn "" | |
29ae5b89 | 9340 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 9341 | (compare:CC |
29ae5b89 JL |
9342 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9343 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9344 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9345 | (const_int 0))) |
29ae5b89 | 9346 | (clobber (match_scratch:SI 4 "=&r"))] |
1fd4e8c1 | 9347 | "" |
29ae5b89 | 9348 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3" |
b19003d8 | 9349 | [(set_attr "type" "compare") |
29ae5b89 | 9350 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9351 | |
9352 | (define_insn "" | |
29ae5b89 | 9353 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") |
1fd4e8c1 | 9354 | (compare:CC |
29ae5b89 JL |
9355 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9356 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9357 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9358 | (const_int 0))) |
29ae5b89 | 9359 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9360 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9361 | (clobber (match_scratch:SI 4 "=&r"))] |
1fd4e8c1 | 9362 | "" |
29ae5b89 | 9363 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3" |
b19003d8 | 9364 | [(set_attr "type" "compare") |
29ae5b89 | 9365 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9366 | |
9367 | (define_insn "" | |
cd2b37d9 RK |
9368 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9369 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
9370 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
9371 | "" | |
ca7f5001 | 9372 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 9373 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9374 | |
9375 | (define_insn "" | |
cd2b37d9 | 9376 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9377 | (and:SI (neg:SI |
cd2b37d9 | 9378 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 9379 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
cd2b37d9 | 9380 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
9381 | (clobber (match_scratch:SI 4 "=&r"))] |
9382 | "" | |
ca7f5001 | 9383 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" |
b19003d8 | 9384 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9385 | |
9386 | (define_insn "" | |
29ae5b89 | 9387 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9388 | (compare:CC |
9389 | (and:SI (neg:SI | |
29ae5b89 JL |
9390 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9391 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) | |
9392 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9393 | (const_int 0))) |
29ae5b89 | 9394 | (clobber (match_scratch:SI 4 "=&r"))] |
1fd4e8c1 | 9395 | "" |
29ae5b89 | 9396 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" |
b19003d8 | 9397 | [(set_attr "type" "compare") |
29ae5b89 | 9398 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9399 | |
9400 | (define_insn "" | |
29ae5b89 | 9401 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9402 | (compare:CC |
9403 | (and:SI (neg:SI | |
29ae5b89 JL |
9404 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9405 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) | |
9406 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9407 | (const_int 0))) |
29ae5b89 | 9408 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9409 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
29ae5b89 | 9410 | (clobber (match_scratch:SI 4 "=&r"))] |
1fd4e8c1 | 9411 | "" |
29ae5b89 | 9412 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" |
b19003d8 | 9413 | [(set_attr "type" "compare") |
29ae5b89 | 9414 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9415 | |
9416 | (define_insn "" | |
cd2b37d9 RK |
9417 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9418 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9419 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 9420 | "TARGET_POWER" |
7f340546 | 9421 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 9422 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9423 | |
9424 | (define_insn "" | |
29ae5b89 | 9425 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 | 9426 | (compare:CC |
29ae5b89 JL |
9427 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9428 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 | 9429 | (const_int 0))) |
29ae5b89 | 9430 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9431 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 9432 | "TARGET_POWER" |
29ae5b89 JL |
9433 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" |
9434 | [(set_attr "type" "delayed_compare") | |
9435 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
9436 | |
9437 | (define_insn "" | |
cd2b37d9 RK |
9438 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9439 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9440 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 9441 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 9442 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
9443 | "TARGET_POWER" |
9444 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 9445 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9446 | |
9447 | (define_insn "" | |
29ae5b89 | 9448 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 9449 | (compare:CC |
29ae5b89 JL |
9450 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9451 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9452 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9453 | (const_int 0))) |
29ae5b89 | 9454 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9455 | "TARGET_POWER" |
29ae5b89 | 9456 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" |
b19003d8 | 9457 | [(set_attr "type" "compare") |
29ae5b89 | 9458 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9459 | |
9460 | (define_insn "" | |
29ae5b89 | 9461 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") |
1fd4e8c1 | 9462 | (compare:CC |
29ae5b89 JL |
9463 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9464 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9465 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9466 | (const_int 0))) |
29ae5b89 | 9467 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9468 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9469 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9470 | "TARGET_POWER" |
29ae5b89 | 9471 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" |
b19003d8 | 9472 | [(set_attr "type" "compare") |
29ae5b89 | 9473 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9474 | |
9475 | (define_insn "" | |
cd2b37d9 RK |
9476 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9477 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9478 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
9479 | "TARGET_POWER" |
9480 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 9481 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9482 | |
9483 | (define_insn "" | |
cd2b37d9 RK |
9484 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9485 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
9486 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
9487 | "" | |
9488 | "@ | |
ca7f5001 RK |
9489 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
9490 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 9491 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9492 | |
9493 | (define_insn "" | |
29ae5b89 | 9494 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9495 | (compare:CC |
29ae5b89 JL |
9496 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9497 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
1fd4e8c1 | 9498 | (const_int 0))) |
29ae5b89 | 9499 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
9500 | (ltu:SI (match_dup 1) (match_dup 2)))] |
9501 | "" | |
9502 | "@ | |
ca7f5001 | 9503 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
29ae5b89 | 9504 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" |
b19003d8 | 9505 | [(set_attr "type" "compare") |
29ae5b89 | 9506 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9507 | |
9508 | (define_insn "" | |
19378cf8 MM |
9509 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9510 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
9511 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
9512 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI"))) | |
9513 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
1fd4e8c1 RK |
9514 | "" |
9515 | "@ | |
ca7f5001 | 9516 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 |
04be6346 | 9517 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
b19003d8 | 9518 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9519 | |
9520 | (define_insn "" | |
29ae5b89 | 9521 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9522 | (compare:CC |
29ae5b89 JL |
9523 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9524 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
9525 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9526 | (const_int 0))) |
29ae5b89 | 9527 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9528 | "" |
9529 | "@ | |
ca7f5001 | 9530 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
29ae5b89 | 9531 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3" |
b19003d8 | 9532 | [(set_attr "type" "compare") |
29ae5b89 | 9533 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9534 | |
9535 | (define_insn "" | |
29ae5b89 | 9536 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9537 | (compare:CC |
29ae5b89 JL |
9538 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9539 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
9540 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9541 | (const_int 0))) |
29ae5b89 | 9542 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9543 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9544 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9545 | "" |
9546 | "@ | |
ca7f5001 | 9547 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
29ae5b89 | 9548 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" |
b19003d8 | 9549 | [(set_attr "type" "compare") |
29ae5b89 | 9550 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9551 | |
9552 | (define_insn "" | |
cd2b37d9 RK |
9553 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9554 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
9555 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
9556 | "" | |
9557 | "@ | |
ca7f5001 RK |
9558 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
9559 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 9560 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
9561 | |
9562 | (define_insn "" | |
cd2b37d9 RK |
9563 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9564 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
9565 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
9566 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
9567 | "TARGET_POWER" |
9568 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 9569 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9570 | |
9571 | (define_insn "" | |
29ae5b89 | 9572 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 9573 | (compare:CC |
29ae5b89 JL |
9574 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9575 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 | 9576 | (const_int 0))) |
29ae5b89 | 9577 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9578 | (ge:SI (match_dup 1) (match_dup 2))) |
29ae5b89 | 9579 | (clobber (match_scratch:SI 3 "=r"))] |
ca7f5001 | 9580 | "TARGET_POWER" |
29ae5b89 | 9581 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3" |
b19003d8 | 9582 | [(set_attr "type" "compare") |
29ae5b89 | 9583 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9584 | |
9585 | (define_insn "" | |
cd2b37d9 RK |
9586 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9587 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9588 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 9589 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 9590 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
9591 | "TARGET_POWER" |
9592 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" | |
b19003d8 | 9593 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9594 | |
9595 | (define_insn "" | |
29ae5b89 | 9596 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 9597 | (compare:CC |
29ae5b89 JL |
9598 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9599 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9600 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9601 | (const_int 0))) |
29ae5b89 | 9602 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9603 | "TARGET_POWER" |
29ae5b89 | 9604 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3" |
b19003d8 | 9605 | [(set_attr "type" "compare") |
29ae5b89 | 9606 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9607 | |
9608 | (define_insn "" | |
29ae5b89 | 9609 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") |
1fd4e8c1 | 9610 | (compare:CC |
29ae5b89 JL |
9611 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9612 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
9613 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9614 | (const_int 0))) |
29ae5b89 | 9615 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9616 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9617 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9618 | "TARGET_POWER" |
29ae5b89 | 9619 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3" |
b19003d8 | 9620 | [(set_attr "type" "compare") |
29ae5b89 | 9621 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9622 | |
9623 | (define_insn "" | |
cd2b37d9 RK |
9624 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9625 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9626 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
9627 | "TARGET_POWER" |
9628 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 9629 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9630 | |
9631 | ;; This is (and (neg (ge X (const_int 0))) Y). | |
9632 | (define_insn "" | |
cd2b37d9 | 9633 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9634 | (and:SI (neg:SI |
9635 | (lshiftrt:SI | |
cd2b37d9 | 9636 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9637 | (const_int 31))) |
cd2b37d9 | 9638 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
9639 | (clobber (match_scratch:SI 3 "=&r"))] |
9640 | "" | |
ca7f5001 | 9641 | "{srai|srawi} %3,%1,31\;andc %0,%2,%3" |
b19003d8 | 9642 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
9643 | |
9644 | (define_insn "" | |
29ae5b89 | 9645 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9646 | (compare:CC |
9647 | (and:SI (neg:SI | |
9648 | (lshiftrt:SI | |
29ae5b89 | 9649 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9650 | (const_int 31))) |
29ae5b89 | 9651 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9652 | (const_int 0))) |
29ae5b89 | 9653 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 9654 | "" |
29ae5b89 | 9655 | "{srai|srawi} %3,%1,31\;andc. %3,%2,%3" |
b19003d8 | 9656 | [(set_attr "type" "compare") |
29ae5b89 | 9657 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9658 | |
9659 | (define_insn "" | |
29ae5b89 | 9660 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 RK |
9661 | (compare:CC |
9662 | (and:SI (neg:SI | |
9663 | (lshiftrt:SI | |
29ae5b89 | 9664 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9665 | (const_int 31))) |
29ae5b89 | 9666 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9667 | (const_int 0))) |
29ae5b89 | 9668 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9669 | (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) |
9670 | (const_int 31))) | |
9671 | (match_dup 2))) | |
29ae5b89 | 9672 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 9673 | "" |
29ae5b89 | 9674 | "{srai|srawi} %3,%1,31\;andc. %0,%2,%3" |
b19003d8 | 9675 | [(set_attr "type" "compare") |
29ae5b89 | 9676 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9677 | |
9678 | (define_insn "" | |
cd2b37d9 RK |
9679 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9680 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
9681 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
9682 | "" | |
9683 | "@ | |
ca7f5001 RK |
9684 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
9685 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 9686 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9687 | |
9688 | (define_insn "" | |
29ae5b89 | 9689 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9690 | (compare:CC |
29ae5b89 JL |
9691 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9692 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
1fd4e8c1 | 9693 | (const_int 0))) |
29ae5b89 | 9694 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
9695 | (geu:SI (match_dup 1) (match_dup 2)))] |
9696 | "" | |
9697 | "@ | |
ca7f5001 | 9698 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
29ae5b89 | 9699 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0" |
b19003d8 | 9700 | [(set_attr "type" "compare") |
29ae5b89 | 9701 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9702 | |
9703 | (define_insn "" | |
cd2b37d9 RK |
9704 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9705 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 9706 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
cd2b37d9 | 9707 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 RK |
9708 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
9709 | "" | |
9710 | "@ | |
ca7f5001 RK |
9711 | {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3 |
9712 | {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 9713 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
9714 | |
9715 | (define_insn "" | |
29ae5b89 | 9716 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9717 | (compare:CC |
29ae5b89 JL |
9718 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9719 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
9720 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9721 | (const_int 0))) |
29ae5b89 | 9722 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9723 | "" |
9724 | "@ | |
ca7f5001 | 9725 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
29ae5b89 | 9726 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3" |
b19003d8 | 9727 | [(set_attr "type" "compare") |
29ae5b89 | 9728 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9729 | |
9730 | (define_insn "" | |
29ae5b89 | 9731 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9732 | (compare:CC |
29ae5b89 JL |
9733 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9734 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
9735 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9736 | (const_int 0))) |
29ae5b89 | 9737 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9738 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9739 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9740 | "" |
9741 | "@ | |
ca7f5001 | 9742 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 |
19378cf8 | 9743 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3" |
b19003d8 | 9744 | [(set_attr "type" "compare") |
29ae5b89 | 9745 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
9746 | |
9747 | (define_insn "" | |
cd2b37d9 RK |
9748 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9749 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
9750 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
9751 | "" | |
9752 | "@ | |
ca7f5001 | 9753 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 9754 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 9755 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9756 | |
9757 | (define_insn "" | |
cd2b37d9 | 9758 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9759 | (and:SI (neg:SI |
cd2b37d9 | 9760 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 9761 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
cd2b37d9 | 9762 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 RK |
9763 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
9764 | "" | |
9765 | "@ | |
ca7f5001 RK |
9766 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 |
9767 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" | |
b19003d8 | 9768 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9769 | |
9770 | (define_insn "" | |
29ae5b89 | 9771 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 RK |
9772 | (compare:CC |
9773 | (and:SI (neg:SI | |
29ae5b89 JL |
9774 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9775 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) | |
9776 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9777 | (const_int 0))) |
29ae5b89 | 9778 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9779 | "" |
9780 | "@ | |
ca7f5001 | 9781 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
29ae5b89 | 9782 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4" |
b19003d8 | 9783 | [(set_attr "type" "compare") |
29ae5b89 | 9784 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9785 | |
9786 | (define_insn "" | |
29ae5b89 | 9787 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 RK |
9788 | (compare:CC |
9789 | (and:SI (neg:SI | |
29ae5b89 JL |
9790 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9791 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) | |
9792 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9793 | (const_int 0))) |
29ae5b89 | 9794 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9795 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
29ae5b89 | 9796 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 RK |
9797 | "" |
9798 | "@ | |
ca7f5001 | 9799 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
29ae5b89 | 9800 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4" |
b19003d8 | 9801 | [(set_attr "type" "compare") |
29ae5b89 | 9802 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9803 | |
9804 | (define_insn "" | |
cd2b37d9 RK |
9805 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9806 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
9807 | (const_int 0)))] |
9808 | "" | |
ca7f5001 | 9809 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 9810 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9811 | |
9812 | (define_insn "" | |
29ae5b89 | 9813 | [(set (match_operand:CC 2 "cc_reg_operand" "=x") |
1fd4e8c1 | 9814 | (compare:CC |
29ae5b89 | 9815 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
9816 | (const_int 0)) |
9817 | (const_int 0))) | |
29ae5b89 | 9818 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9819 | (gt:SI (match_dup 1) (const_int 0)))] |
9820 | "" | |
29ae5b89 JL |
9821 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31" |
9822 | [(set_attr "type" "delayed_compare") | |
9823 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
9824 | |
9825 | (define_insn "" | |
cd2b37d9 RK |
9826 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9827 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9828 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
9829 | "TARGET_POWER" |
9830 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 9831 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9832 | |
9833 | (define_insn "" | |
29ae5b89 | 9834 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 | 9835 | (compare:CC |
29ae5b89 JL |
9836 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9837 | (match_operand:SI 2 "reg_or_short_operand" "r")) | |
1fd4e8c1 | 9838 | (const_int 0))) |
29ae5b89 | 9839 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9840 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 9841 | "TARGET_POWER" |
29ae5b89 JL |
9842 | "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31" |
9843 | [(set_attr "type" "delayed_compare") | |
9844 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
9845 | |
9846 | (define_insn "" | |
cd2b37d9 RK |
9847 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9848 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9849 | (const_int 0)) |
cd2b37d9 | 9850 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
9851 | (clobber (match_scratch:SI 3 "=&r"))] |
9852 | "" | |
ca7f5001 | 9853 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2" |
b19003d8 | 9854 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9855 | |
9856 | (define_insn "" | |
29ae5b89 | 9857 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 9858 | (compare:CC |
29ae5b89 | 9859 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 9860 | (const_int 0)) |
29ae5b89 | 9861 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9862 | (const_int 0))) |
29ae5b89 | 9863 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 9864 | "" |
19378cf8 | 9865 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2" |
b19003d8 | 9866 | [(set_attr "type" "compare") |
29ae5b89 | 9867 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9868 | |
9869 | (define_insn "" | |
29ae5b89 | 9870 | [(set (match_operand:CC 4 "cc_reg_operand" "=x") |
1fd4e8c1 | 9871 | (compare:CC |
29ae5b89 | 9872 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 9873 | (const_int 0)) |
29ae5b89 | 9874 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 9875 | (const_int 0))) |
29ae5b89 | 9876 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9877 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
29ae5b89 | 9878 | (clobber (match_scratch:SI 3 "=&r"))] |
1fd4e8c1 | 9879 | "" |
19378cf8 | 9880 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2" |
b19003d8 | 9881 | [(set_attr "type" "compare") |
29ae5b89 | 9882 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9883 | |
9884 | (define_insn "" | |
cd2b37d9 RK |
9885 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9886 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9887 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
cd2b37d9 | 9888 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 9889 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
9890 | "TARGET_POWER" |
9891 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 9892 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9893 | |
9894 | (define_insn "" | |
29ae5b89 | 9895 | [(set (match_operand:CC 0 "cc_reg_operand" "=x") |
1fd4e8c1 | 9896 | (compare:CC |
29ae5b89 JL |
9897 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9898 | (match_operand:SI 2 "reg_or_short_operand" "r")) | |
9899 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9900 | (const_int 0))) |
29ae5b89 | 9901 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9902 | "TARGET_POWER" |
29ae5b89 | 9903 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3" |
b19003d8 | 9904 | [(set_attr "type" "compare") |
29ae5b89 | 9905 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9906 | |
9907 | (define_insn "" | |
29ae5b89 | 9908 | [(set (match_operand:CC 5 "cc_reg_operand" "=x") |
1fd4e8c1 | 9909 | (compare:CC |
29ae5b89 JL |
9910 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9911 | (match_operand:SI 2 "reg_or_short_operand" "r")) | |
9912 | (match_operand:SI 3 "gpc_reg_operand" "r")) | |
1fd4e8c1 | 9913 | (const_int 0))) |
29ae5b89 | 9914 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 9915 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9916 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 | 9917 | "TARGET_POWER" |
29ae5b89 | 9918 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3" |
b19003d8 | 9919 | [(set_attr "type" "compare") |
29ae5b89 | 9920 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9921 | |
9922 | (define_insn "" | |
cd2b37d9 RK |
9923 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9924 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
9925 | (const_int 0))))] |
9926 | "" | |
ca7f5001 | 9927 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 9928 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9929 | |
9930 | (define_insn "" | |
cd2b37d9 RK |
9931 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9932 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 9933 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
9934 | "TARGET_POWER" |
9935 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 9936 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9937 | |
9938 | (define_insn "" | |
cd2b37d9 RK |
9939 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9940 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
9941 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
9942 | "" | |
ca7f5001 | 9943 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 9944 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
9945 | |
9946 | (define_insn "" | |
29ae5b89 | 9947 | [(set (match_operand:CC 3 "cc_reg_operand" "=x") |
1fd4e8c1 | 9948 | (compare:CC |
29ae5b89 JL |
9949 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
9950 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
1fd4e8c1 | 9951 | (const_int 0))) |
29ae5b89 | 9952 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
9953 | (gtu:SI (match_dup 1) (match_dup 2)))] |
9954 | "" | |
29ae5b89 | 9955 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0" |
b19003d8 | 9956 | [(set_attr "type" "compare") |
29ae5b89 | 9957 | (set_attr "length" "12")]) |
1fd4e8c1 RK |
9958 | |
9959 | (define_insn "" | |
19378cf8 MM |
9960 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
9961 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
9962 | (match_operand:SI 2 "reg_or_short_operand" "I,rI")) | |
9963 | (match_operand:SI 3 "reg_or_short_operand" "r,rI"))) | |
9964 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
1fd4e8c1 | 9965 | "" |
00751805 | 9966 | "@ |
ca7f5001 | 9967 | {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3 |
ca7f5001 | 9968 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
19378cf8 | 9969 | [(set_attr "length" "8,12")]) |
1fd4e8c1 RK |
9970 | |
9971 | (define_insn "" | |
29ae5b89 | 9972 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9973 | (compare:CC |
29ae5b89 JL |
9974 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9975 | (match_operand:SI 2 "reg_or_short_operand" "I,r")) | |
9976 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9977 | (const_int 0))) |
29ae5b89 | 9978 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 | 9979 | "" |
00751805 | 9980 | "@ |
19378cf8 MM |
9981 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
9982 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3" | |
b19003d8 | 9983 | [(set_attr "type" "compare") |
29ae5b89 | 9984 | (set_attr "length" "8,12")]) |
1fd4e8c1 RK |
9985 | |
9986 | (define_insn "" | |
29ae5b89 | 9987 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") |
1fd4e8c1 | 9988 | (compare:CC |
29ae5b89 JL |
9989 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
9990 | (match_operand:SI 2 "reg_or_short_operand" "I,r")) | |
9991 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 9992 | (const_int 0))) |
29ae5b89 | 9993 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9994 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
29ae5b89 | 9995 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
1fd4e8c1 | 9996 | "" |
00751805 | 9997 | "@ |
ca7f5001 | 9998 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 |
29ae5b89 | 9999 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3" |
b19003d8 | 10000 | [(set_attr "type" "compare") |
29ae5b89 | 10001 | (set_attr "length" "8,12")]) |
1fd4e8c1 RK |
10002 | |
10003 | (define_insn "" | |
cd2b37d9 RK |
10004 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
10005 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
10006 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
10007 | "" | |
ca7f5001 | 10008 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 10009 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
10010 | \f |
10011 | ;; Define both directions of branch and return. If we need a reload | |
10012 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
10013 | ;; register CC value to there. | |
10014 | ||
10015 | (define_insn "" | |
10016 | [(set (pc) | |
10017 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
10018 | [(match_operand 2 | |
10019 | "cc_reg_operand" "x,?y") | |
10020 | (const_int 0)]) | |
10021 | (label_ref (match_operand 0 "" "")) | |
10022 | (pc)))] | |
10023 | "" | |
b19003d8 RK |
10024 | "* |
10025 | { | |
10026 | if (get_attr_length (insn) == 8) | |
10027 | return \"%C1bc %t1,%j1,%l0\"; | |
10028 | else | |
c81bebd7 MM |
10029 | return \"%C1bc %T1,%j1,%$+8\;b %l0\"; |
10030 | ||
b19003d8 RK |
10031 | }" |
10032 | [(set_attr "type" "branch")]) | |
10033 | ||
1fd4e8c1 RK |
10034 | (define_insn "" |
10035 | [(set (pc) | |
10036 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
10037 | [(match_operand 1 | |
10038 | "cc_reg_operand" "x,?y") | |
10039 | (const_int 0)]) | |
10040 | (return) | |
10041 | (pc)))] | |
10042 | "direct_return ()" | |
ca7f5001 | 10043 | "{%C0bcr|%C0bclr} %t0,%j0" |
b7ff3d82 DE |
10044 | [(set_attr "type" "branch") |
10045 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
10046 | |
10047 | (define_insn "" | |
10048 | [(set (pc) | |
10049 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
10050 | [(match_operand 2 | |
10051 | "cc_reg_operand" "x,?y") | |
10052 | (const_int 0)]) | |
10053 | (pc) | |
10054 | (label_ref (match_operand 0 "" ""))))] | |
10055 | "" | |
b19003d8 RK |
10056 | "* |
10057 | { | |
10058 | if (get_attr_length (insn) == 8) | |
10059 | return \"%C1bc %T1,%j1,%l0\"; | |
10060 | else | |
c81bebd7 | 10061 | return \"%C1bc %t1,%j1,%$+8\;b %l0\"; |
b19003d8 RK |
10062 | }" |
10063 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
10064 | |
10065 | (define_insn "" | |
10066 | [(set (pc) | |
10067 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
10068 | [(match_operand 1 | |
10069 | "cc_reg_operand" "x,?y") | |
10070 | (const_int 0)]) | |
10071 | (pc) | |
10072 | (return)))] | |
10073 | "direct_return ()" | |
ca7f5001 | 10074 | "{%C0bcr|%C0bclr} %T0,%j0" |
b7ff3d82 DE |
10075 | [(set_attr "type" "branch") |
10076 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
10077 | |
10078 | ;; Unconditional branch and return. | |
10079 | ||
10080 | (define_insn "jump" | |
10081 | [(set (pc) | |
10082 | (label_ref (match_operand 0 "" "")))] | |
10083 | "" | |
b7ff3d82 DE |
10084 | "b %l0" |
10085 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
10086 | |
10087 | (define_insn "return" | |
10088 | [(return)] | |
10089 | "direct_return ()" | |
324e52cc TG |
10090 | "{br|blr}" |
10091 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 RK |
10092 | |
10093 | (define_insn "indirect_jump" | |
10094 | [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))] | |
10095 | "" | |
10096 | "@ | |
10097 | bctr | |
324e52cc TG |
10098 | {br|blr}" |
10099 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 10100 | |
266eb58a DE |
10101 | (define_insn "" |
10102 | [(set (pc) (match_operand:DI 0 "register_operand" "c,l"))] | |
10103 | "TARGET_POWERPC64" | |
10104 | "@ | |
10105 | bctr | |
10106 | {br|blr}" | |
10107 | [(set_attr "type" "jmpreg")]) | |
10108 | ||
1fd4e8c1 RK |
10109 | ;; Table jump for switch statements: |
10110 | (define_expand "tablejump" | |
e6ca2c17 DE |
10111 | [(use (match_operand 0 "" "")) |
10112 | (use (label_ref (match_operand 1 "" "")))] | |
10113 | "" | |
10114 | " | |
10115 | { | |
10116 | if (TARGET_32BIT) | |
10117 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
10118 | else | |
10119 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
10120 | DONE; | |
10121 | }") | |
10122 | ||
10123 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
10124 | [(set (match_dup 3) |
10125 | (plus:SI (match_operand:SI 0 "" "") | |
10126 | (match_dup 2))) | |
10127 | (parallel [(set (pc) (match_dup 3)) | |
10128 | (use (label_ref (match_operand 1 "" "")))])] | |
10129 | "" | |
10130 | " | |
10131 | { operands[0] = force_reg (SImode, operands[0]); | |
39403d82 | 10132 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (VOIDmode, operands[1])); |
1fd4e8c1 RK |
10133 | operands[3] = gen_reg_rtx (SImode); |
10134 | }") | |
10135 | ||
e6ca2c17 DE |
10136 | (define_expand "tablejumpdi" |
10137 | [(set (match_dup 3) | |
10138 | (plus:DI (match_operand:DI 0 "" "") | |
10139 | (match_dup 2))) | |
10140 | (parallel [(set (pc) (match_dup 3)) | |
10141 | (use (label_ref (match_operand 1 "" "")))])] | |
10142 | "" | |
10143 | " | |
10144 | { operands[0] = force_reg (DImode, operands[0]); | |
39403d82 | 10145 | operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (VOIDmode, operands[1])); |
e6ca2c17 DE |
10146 | operands[3] = gen_reg_rtx (DImode); |
10147 | }") | |
10148 | ||
1fd4e8c1 RK |
10149 | (define_insn "" |
10150 | [(set (pc) | |
740ab4a2 | 10151 | (match_operand:SI 0 "register_operand" "c,l")) |
1fd4e8c1 RK |
10152 | (use (label_ref (match_operand 1 "" "")))] |
10153 | "" | |
10154 | "@ | |
10155 | bctr | |
a6845123 RK |
10156 | {br|blr}" |
10157 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 10158 | |
266eb58a DE |
10159 | (define_insn "" |
10160 | [(set (pc) | |
10161 | (match_operand:DI 0 "register_operand" "c,l")) | |
10162 | (use (label_ref (match_operand 1 "" "")))] | |
10163 | "TARGET_POWERPC64" | |
10164 | "@ | |
10165 | bctr | |
10166 | {br|blr}" | |
10167 | [(set_attr "type" "jmpreg")]) | |
10168 | ||
1fd4e8c1 RK |
10169 | (define_insn "nop" |
10170 | [(const_int 0)] | |
10171 | "" | |
ca7f5001 | 10172 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 10173 | \f |
7e69e155 | 10174 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
10175 | ;; so loop.c knows what to generate. |
10176 | ||
b6c9286a MM |
10177 | (define_expand "decrement_and_branch_on_count" |
10178 | [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
c225ba7b RK |
10179 | (const_int 1)) |
10180 | (label_ref (match_operand 1 "" "")) | |
10181 | (pc))) | |
b6c9286a MM |
10182 | (set (match_dup 0) |
10183 | (plus:SI (match_dup 0) | |
10184 | (const_int -1))) | |
5f81043f RK |
10185 | (clobber (match_scratch:CC 2 "")) |
10186 | (clobber (match_scratch:SI 3 ""))])] | |
c225ba7b RK |
10187 | "" |
10188 | "") | |
10189 | ||
1fd4e8c1 RK |
10190 | ;; We need to be able to do this for any operand, including MEM, or we |
10191 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 10192 | ;; JUMP_INSNs. |
5f81043f RK |
10193 | ;; In order that the length attribute is calculated correctly, the |
10194 | ;; label MUST be operand 0. | |
10195 | ||
1fd4e8c1 RK |
10196 | (define_insn "" |
10197 | [(set (pc) | |
5f81043f | 10198 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 10199 | (const_int 1)) |
a6845123 | 10200 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 10201 | (pc))) |
5f81043f RK |
10202 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
10203 | (plus:SI (match_dup 1) | |
10204 | (const_int -1))) | |
1fd4e8c1 RK |
10205 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
10206 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
10207 | "" | |
b19003d8 RK |
10208 | "* |
10209 | { | |
af87a13e | 10210 | if (which_alternative != 0) |
b19003d8 RK |
10211 | return \"#\"; |
10212 | else if (get_attr_length (insn) == 8) | |
a6845123 | 10213 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 10214 | else |
c81bebd7 | 10215 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 10216 | }" |
baf97f86 RK |
10217 | [(set_attr "type" "branch") |
10218 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 10219 | |
5f81043f RK |
10220 | (define_insn "" |
10221 | [(set (pc) | |
10222 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") | |
10223 | (const_int 1)) | |
10224 | (pc) | |
10225 | (label_ref (match_operand 0 "" "")))) | |
10226 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
10227 | (plus:SI (match_dup 1) | |
10228 | (const_int -1))) | |
10229 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
10230 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
10231 | "" | |
10232 | "* | |
10233 | { | |
10234 | if (which_alternative != 0) | |
10235 | return \"#\"; | |
10236 | else if (get_attr_length (insn) == 8) | |
10237 | return \"bdz %l0\"; | |
10238 | else | |
c81bebd7 | 10239 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
10240 | }" |
10241 | [(set_attr "type" "branch") | |
10242 | (set_attr "length" "*,12,16")]) | |
10243 | ||
c225ba7b | 10244 | ;; Similar, but we can use GE since we have a REG_NONNEG. |
1fd4e8c1 RK |
10245 | (define_insn "" |
10246 | [(set (pc) | |
5f81043f | 10247 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 10248 | (const_int 0)) |
a6845123 | 10249 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 10250 | (pc))) |
5f81043f RK |
10251 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
10252 | (plus:SI (match_dup 1) | |
10253 | (const_int -1))) | |
1fd4e8c1 RK |
10254 | (clobber (match_scratch:CC 3 "=X,&x,&X")) |
10255 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
10256 | "find_reg_note (insn, REG_NONNEG, 0)" | |
b19003d8 RK |
10257 | "* |
10258 | { | |
af87a13e | 10259 | if (which_alternative != 0) |
b19003d8 RK |
10260 | return \"#\"; |
10261 | else if (get_attr_length (insn) == 8) | |
a6845123 | 10262 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 10263 | else |
c81bebd7 | 10264 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 10265 | }" |
baf97f86 RK |
10266 | [(set_attr "type" "branch") |
10267 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 10268 | |
1fd4e8c1 RK |
10269 | (define_insn "" |
10270 | [(set (pc) | |
5f81043f RK |
10271 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
10272 | (const_int 0)) | |
10273 | (pc) | |
10274 | (label_ref (match_operand 0 "" "")))) | |
10275 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
10276 | (plus:SI (match_dup 1) | |
10277 | (const_int -1))) | |
10278 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
10279 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
10280 | "find_reg_note (insn, REG_NONNEG, 0)" | |
10281 | "* | |
10282 | { | |
10283 | if (which_alternative != 0) | |
10284 | return \"#\"; | |
10285 | else if (get_attr_length (insn) == 8) | |
10286 | return \"bdz %l0\"; | |
10287 | else | |
c81bebd7 | 10288 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
10289 | }" |
10290 | [(set_attr "type" "branch") | |
10291 | (set_attr "length" "*,12,16")]) | |
10292 | ||
10293 | (define_insn "" | |
10294 | [(set (pc) | |
10295 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
1fd4e8c1 | 10296 | (const_int 1)) |
a6845123 | 10297 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 10298 | (pc))) |
5f81043f RK |
10299 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
10300 | (plus:SI (match_dup 1) | |
10301 | (const_int -1))) | |
1fd4e8c1 RK |
10302 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
10303 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
10304 | "" | |
b19003d8 RK |
10305 | "* |
10306 | { | |
af87a13e | 10307 | if (which_alternative != 0) |
b19003d8 RK |
10308 | return \"#\"; |
10309 | else if (get_attr_length (insn) == 8) | |
a6845123 | 10310 | return \"bdz %l0\"; |
b19003d8 | 10311 | else |
c81bebd7 | 10312 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
b19003d8 | 10313 | }" |
baf97f86 RK |
10314 | [(set_attr "type" "branch") |
10315 | (set_attr "length" "*,12,16")]) | |
1fd4e8c1 | 10316 | |
5f81043f RK |
10317 | (define_insn "" |
10318 | [(set (pc) | |
10319 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
10320 | (const_int 1)) | |
10321 | (pc) | |
10322 | (label_ref (match_operand 0 "" "")))) | |
10323 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
10324 | (plus:SI (match_dup 1) | |
10325 | (const_int -1))) | |
10326 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
10327 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
10328 | "" | |
10329 | "* | |
10330 | { | |
10331 | if (which_alternative != 0) | |
10332 | return \"#\"; | |
10333 | else if (get_attr_length (insn) == 8) | |
10334 | return \"{bdn|bdnz} %l0\"; | |
10335 | else | |
c81bebd7 | 10336 | return \"bdz %$+8\;b %l0\"; |
5f81043f RK |
10337 | }" |
10338 | [(set_attr "type" "branch") | |
10339 | (set_attr "length" "*,12,16")]) | |
10340 | ||
1fd4e8c1 RK |
10341 | (define_split |
10342 | [(set (pc) | |
10343 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 10344 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10345 | (const_int 1)]) |
10346 | (match_operand 5 "" "") | |
10347 | (match_operand 6 "" ""))) | |
cd2b37d9 | 10348 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
10349 | (plus:SI (match_dup 1) |
10350 | (const_int -1))) | |
1fd4e8c1 RK |
10351 | (clobber (match_scratch:CC 3 "")) |
10352 | (clobber (match_scratch:SI 4 ""))] | |
10353 | "reload_completed" | |
10354 | [(parallel [(set (match_dup 3) | |
5f81043f RK |
10355 | (compare:CC (plus:SI (match_dup 1) |
10356 | (const_int -1)) | |
1fd4e8c1 | 10357 | (const_int 0))) |
5f81043f RK |
10358 | (set (match_dup 0) |
10359 | (plus:SI (match_dup 1) | |
10360 | (const_int -1)))]) | |
10361 | (set (pc) (if_then_else (match_dup 7) | |
10362 | (match_dup 5) | |
10363 | (match_dup 6)))] | |
1fd4e8c1 RK |
10364 | " |
10365 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
10366 | const0_rtx); }") | |
10367 | ||
10368 | (define_split | |
10369 | [(set (pc) | |
10370 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 10371 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10372 | (const_int 1)]) |
10373 | (match_operand 5 "" "") | |
10374 | (match_operand 6 "" ""))) | |
10375 | (set (match_operand:SI 0 "general_operand" "") | |
10376 | (plus:SI (match_dup 1) (const_int -1))) | |
10377 | (clobber (match_scratch:CC 3 "")) | |
10378 | (clobber (match_scratch:SI 4 ""))] | |
cd2b37d9 | 10379 | "reload_completed && ! gpc_reg_operand (operands[0], SImode)" |
1fd4e8c1 | 10380 | [(parallel [(set (match_dup 3) |
5f81043f RK |
10381 | (compare:CC (plus:SI (match_dup 1) |
10382 | (const_int -1)) | |
1fd4e8c1 | 10383 | (const_int 0))) |
5f81043f RK |
10384 | (set (match_dup 4) |
10385 | (plus:SI (match_dup 1) | |
10386 | (const_int -1)))]) | |
10387 | (set (match_dup 0) | |
10388 | (match_dup 4)) | |
10389 | (set (pc) (if_then_else (match_dup 7) | |
10390 | (match_dup 5) | |
10391 | (match_dup 6)))] | |
1fd4e8c1 RK |
10392 | " |
10393 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
10394 | const0_rtx); }") | |
e0cd0770 JC |
10395 | \f |
10396 | (define_insn "trap" | |
10397 | [(trap_if (const_int 1) (const_int 0))] | |
10398 | "" | |
10399 | "{t 31,0,0|trap}") | |
10400 | ||
10401 | (define_expand "conditional_trap" | |
10402 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
10403 | [(match_dup 2) (match_dup 3)]) | |
10404 | (match_operand 1 "const_int_operand" ""))] | |
10405 | "" | |
10406 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
10407 | operands[2] = rs6000_compare_op0; | |
10408 | operands[3] = rs6000_compare_op1;") | |
10409 | ||
10410 | (define_insn "" | |
10411 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
10412 | [(match_operand:SI 1 "register_operand" "r") | |
10413 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
10414 | (const_int 0))] | |
10415 | "" | |
10416 | "t%V0%I2 %1,%2") |